node-red-STM32/OZE_Sensor/Debug/OZE_Sensor.list

OZE_Sensor.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000298  08000000  08000000  00001000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00014258  080002a0  080002a0  000012a0  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000160  080144f8  080144f8  000154f8  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM          00000008  08014658  08014658  00015658  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  4 .init_array   00000004  08014660  08014660  00015660  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .fini_array   00000004  08014664  08014664  00015664  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  6 .data         000000a4  24000000  08014668  00016000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .bss          00012ad4  240000c0  0801470c  000160c0  2**5
                  ALLOC
  8 ._user_heap_stack 00000604  24012b94  0801470c  00016b94  2**0
                  ALLOC
  9 .ARM.attributes 0000002e  00000000  00000000  000160a4  2**0
                  CONTENTS, READONLY
 10 .debug_info   0002d948  00000000  00000000  000160d2  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 11 .debug_abbrev 000058d1  00000000  00000000  00043a1a  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 12 .debug_aranges 00002170  00000000  00000000  000492f0  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 13 .debug_macro  0003dbc2  00000000  00000000  0004b460  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_line   0002bc9b  00000000  00000000  00089022  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_str    00182d62  00000000  00000000  000b4cbd  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .comment      00000043  00000000  00000000  00237a1f  2**0
                  CONTENTS, READONLY
 17 .debug_rnglists 000019c8  00000000  00000000  00237a62  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_frame  000094bc  00000000  00000000  0023942c  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .debug_line_str 00000066  00000000  00000000  002428e8  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

080002a0 <__do_global_dtors_aux>:
 80002a0:	b510      	push	{r4, lr}
 80002a2:	4c05      	ldr	r4, [pc, #20]	@ (80002b8 <__do_global_dtors_aux+0x18>)
 80002a4:	7823      	ldrb	r3, [r4, #0]
 80002a6:	b933      	cbnz	r3, 80002b6 <__do_global_dtors_aux+0x16>
 80002a8:	4b04      	ldr	r3, [pc, #16]	@ (80002bc <__do_global_dtors_aux+0x1c>)
 80002aa:	b113      	cbz	r3, 80002b2 <__do_global_dtors_aux+0x12>
 80002ac:	4804      	ldr	r0, [pc, #16]	@ (80002c0 <__do_global_dtors_aux+0x20>)
 80002ae:	f3af 8000 	nop.w
 80002b2:	2301      	movs	r3, #1
 80002b4:	7023      	strb	r3, [r4, #0]
 80002b6:	bd10      	pop	{r4, pc}
 80002b8:	240000c0 	.word	0x240000c0
 80002bc:	00000000 	.word	0x00000000
 80002c0:	080144e0 	.word	0x080144e0

080002c4 <frame_dummy>:
 80002c4:	b508      	push	{r3, lr}
 80002c6:	4b03      	ldr	r3, [pc, #12]	@ (80002d4 <frame_dummy+0x10>)
 80002c8:	b11b      	cbz	r3, 80002d2 <frame_dummy+0xe>
 80002ca:	4903      	ldr	r1, [pc, #12]	@ (80002d8 <frame_dummy+0x14>)
 80002cc:	4803      	ldr	r0, [pc, #12]	@ (80002dc <frame_dummy+0x18>)
 80002ce:	f3af 8000 	nop.w
 80002d2:	bd08      	pop	{r3, pc}
 80002d4:	00000000 	.word	0x00000000
 80002d8:	240000c4 	.word	0x240000c4
 80002dc:	080144e0 	.word	0x080144e0

080002e0 <memchr>:
 80002e0:	f001 01ff 	and.w	r1, r1, #255	@ 0xff
 80002e4:	2a10      	cmp	r2, #16
 80002e6:	db2b      	blt.n	8000340 <memchr+0x60>
 80002e8:	f010 0f07 	tst.w	r0, #7
 80002ec:	d008      	beq.n	8000300 <memchr+0x20>
 80002ee:	f810 3b01 	ldrb.w	r3, [r0], #1
 80002f2:	3a01      	subs	r2, #1
 80002f4:	428b      	cmp	r3, r1
 80002f6:	d02d      	beq.n	8000354 <memchr+0x74>
 80002f8:	f010 0f07 	tst.w	r0, #7
 80002fc:	b342      	cbz	r2, 8000350 <memchr+0x70>
 80002fe:	d1f6      	bne.n	80002ee <memchr+0xe>
 8000300:	b4f0      	push	{r4, r5, r6, r7}
 8000302:	ea41 2101 	orr.w	r1, r1, r1, lsl #8
 8000306:	ea41 4101 	orr.w	r1, r1, r1, lsl #16
 800030a:	f022 0407 	bic.w	r4, r2, #7
 800030e:	f07f 0700 	mvns.w	r7, #0
 8000312:	2300      	movs	r3, #0
 8000314:	e8f0 5602 	ldrd	r5, r6, [r0], #8
 8000318:	3c08      	subs	r4, #8
 800031a:	ea85 0501 	eor.w	r5, r5, r1
 800031e:	ea86 0601 	eor.w	r6, r6, r1
 8000322:	fa85 f547 	uadd8	r5, r5, r7
 8000326:	faa3 f587 	sel	r5, r3, r7
 800032a:	fa86 f647 	uadd8	r6, r6, r7
 800032e:	faa5 f687 	sel	r6, r5, r7
 8000332:	b98e      	cbnz	r6, 8000358 <memchr+0x78>
 8000334:	d1ee      	bne.n	8000314 <memchr+0x34>
 8000336:	bcf0      	pop	{r4, r5, r6, r7}
 8000338:	f001 01ff 	and.w	r1, r1, #255	@ 0xff
 800033c:	f002 0207 	and.w	r2, r2, #7
 8000340:	b132      	cbz	r2, 8000350 <memchr+0x70>
 8000342:	f810 3b01 	ldrb.w	r3, [r0], #1
 8000346:	3a01      	subs	r2, #1
 8000348:	ea83 0301 	eor.w	r3, r3, r1
 800034c:	b113      	cbz	r3, 8000354 <memchr+0x74>
 800034e:	d1f8      	bne.n	8000342 <memchr+0x62>
 8000350:	2000      	movs	r0, #0
 8000352:	4770      	bx	lr
 8000354:	3801      	subs	r0, #1
 8000356:	4770      	bx	lr
 8000358:	2d00      	cmp	r5, #0
 800035a:	bf06      	itte	eq
 800035c:	4635      	moveq	r5, r6
 800035e:	3803      	subeq	r0, #3
 8000360:	3807      	subne	r0, #7
 8000362:	f015 0f01 	tst.w	r5, #1
 8000366:	d107      	bne.n	8000378 <memchr+0x98>
 8000368:	3001      	adds	r0, #1
 800036a:	f415 7f80 	tst.w	r5, #256	@ 0x100
 800036e:	bf02      	ittt	eq
 8000370:	3001      	addeq	r0, #1
 8000372:	f415 3fc0 	tsteq.w	r5, #98304	@ 0x18000
 8000376:	3001      	addeq	r0, #1
 8000378:	bcf0      	pop	{r4, r5, r6, r7}
 800037a:	3801      	subs	r0, #1
 800037c:	4770      	bx	lr
 800037e:	bf00      	nop

08000380 <__aeabi_uldivmod>:
 8000380:	b953      	cbnz	r3, 8000398 <__aeabi_uldivmod+0x18>
 8000382:	b94a      	cbnz	r2, 8000398 <__aeabi_uldivmod+0x18>
 8000384:	2900      	cmp	r1, #0
 8000386:	bf08      	it	eq
 8000388:	2800      	cmpeq	r0, #0
 800038a:	bf1c      	itt	ne
 800038c:	f04f 31ff 	movne.w	r1, #4294967295	@ 0xffffffff
 8000390:	f04f 30ff 	movne.w	r0, #4294967295	@ 0xffffffff
 8000394:	f000 b96a 	b.w	800066c <__aeabi_idiv0>
 8000398:	f1ad 0c08 	sub.w	ip, sp, #8
 800039c:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 80003a0:	f000 f806 	bl	80003b0 <__udivmoddi4>
 80003a4:	f8dd e004 	ldr.w	lr, [sp, #4]
 80003a8:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 80003ac:	b004      	add	sp, #16
 80003ae:	4770      	bx	lr

080003b0 <__udivmoddi4>:
 80003b0:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 80003b4:	9d08      	ldr	r5, [sp, #32]
 80003b6:	460c      	mov	r4, r1
 80003b8:	2b00      	cmp	r3, #0
 80003ba:	d14e      	bne.n	800045a <__udivmoddi4+0xaa>
 80003bc:	4694      	mov	ip, r2
 80003be:	458c      	cmp	ip, r1
 80003c0:	4686      	mov	lr, r0
 80003c2:	fab2 f282 	clz	r2, r2
 80003c6:	d962      	bls.n	800048e <__udivmoddi4+0xde>
 80003c8:	b14a      	cbz	r2, 80003de <__udivmoddi4+0x2e>
 80003ca:	f1c2 0320 	rsb	r3, r2, #32
 80003ce:	4091      	lsls	r1, r2
 80003d0:	fa20 f303 	lsr.w	r3, r0, r3
 80003d4:	fa0c fc02 	lsl.w	ip, ip, r2
 80003d8:	4319      	orrs	r1, r3
 80003da:	fa00 fe02 	lsl.w	lr, r0, r2
 80003de:	ea4f 471c 	mov.w	r7, ip, lsr #16
 80003e2:	fa1f f68c 	uxth.w	r6, ip
 80003e6:	fbb1 f4f7 	udiv	r4, r1, r7
 80003ea:	ea4f 431e 	mov.w	r3, lr, lsr #16
 80003ee:	fb07 1114 	mls	r1, r7, r4, r1
 80003f2:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
 80003f6:	fb04 f106 	mul.w	r1, r4, r6
 80003fa:	4299      	cmp	r1, r3
 80003fc:	d90a      	bls.n	8000414 <__udivmoddi4+0x64>
 80003fe:	eb1c 0303 	adds.w	r3, ip, r3
 8000402:	f104 30ff 	add.w	r0, r4, #4294967295	@ 0xffffffff
 8000406:	f080 8112 	bcs.w	800062e <__udivmoddi4+0x27e>
 800040a:	4299      	cmp	r1, r3
 800040c:	f240 810f 	bls.w	800062e <__udivmoddi4+0x27e>
 8000410:	3c02      	subs	r4, #2
 8000412:	4463      	add	r3, ip
 8000414:	1a59      	subs	r1, r3, r1
 8000416:	fa1f f38e 	uxth.w	r3, lr
 800041a:	fbb1 f0f7 	udiv	r0, r1, r7
 800041e:	fb07 1110 	mls	r1, r7, r0, r1
 8000422:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
 8000426:	fb00 f606 	mul.w	r6, r0, r6
 800042a:	429e      	cmp	r6, r3
 800042c:	d90a      	bls.n	8000444 <__udivmoddi4+0x94>
 800042e:	eb1c 0303 	adds.w	r3, ip, r3
 8000432:	f100 31ff 	add.w	r1, r0, #4294967295	@ 0xffffffff
 8000436:	f080 80fc 	bcs.w	8000632 <__udivmoddi4+0x282>
 800043a:	429e      	cmp	r6, r3
 800043c:	f240 80f9 	bls.w	8000632 <__udivmoddi4+0x282>
 8000440:	4463      	add	r3, ip
 8000442:	3802      	subs	r0, #2
 8000444:	1b9b      	subs	r3, r3, r6
 8000446:	ea40 4004 	orr.w	r0, r0, r4, lsl #16
 800044a:	2100      	movs	r1, #0
 800044c:	b11d      	cbz	r5, 8000456 <__udivmoddi4+0xa6>
 800044e:	40d3      	lsrs	r3, r2
 8000450:	2200      	movs	r2, #0
 8000452:	e9c5 3200 	strd	r3, r2, [r5]
 8000456:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 800045a:	428b      	cmp	r3, r1
 800045c:	d905      	bls.n	800046a <__udivmoddi4+0xba>
 800045e:	b10d      	cbz	r5, 8000464 <__udivmoddi4+0xb4>
 8000460:	e9c5 0100 	strd	r0, r1, [r5]
 8000464:	2100      	movs	r1, #0
 8000466:	4608      	mov	r0, r1
 8000468:	e7f5      	b.n	8000456 <__udivmoddi4+0xa6>
 800046a:	fab3 f183 	clz	r1, r3
 800046e:	2900      	cmp	r1, #0
 8000470:	d146      	bne.n	8000500 <__udivmoddi4+0x150>
 8000472:	42a3      	cmp	r3, r4
 8000474:	d302      	bcc.n	800047c <__udivmoddi4+0xcc>
 8000476:	4290      	cmp	r0, r2
 8000478:	f0c0 80f0 	bcc.w	800065c <__udivmoddi4+0x2ac>
 800047c:	1a86      	subs	r6, r0, r2
 800047e:	eb64 0303 	sbc.w	r3, r4, r3
 8000482:	2001      	movs	r0, #1
 8000484:	2d00      	cmp	r5, #0
 8000486:	d0e6      	beq.n	8000456 <__udivmoddi4+0xa6>
 8000488:	e9c5 6300 	strd	r6, r3, [r5]
 800048c:	e7e3      	b.n	8000456 <__udivmoddi4+0xa6>
 800048e:	2a00      	cmp	r2, #0
 8000490:	f040 8090 	bne.w	80005b4 <__udivmoddi4+0x204>
 8000494:	eba1 040c 	sub.w	r4, r1, ip
 8000498:	ea4f 481c 	mov.w	r8, ip, lsr #16
 800049c:	fa1f f78c 	uxth.w	r7, ip
 80004a0:	2101      	movs	r1, #1
 80004a2:	fbb4 f6f8 	udiv	r6, r4, r8
 80004a6:	ea4f 431e 	mov.w	r3, lr, lsr #16
 80004aa:	fb08 4416 	mls	r4, r8, r6, r4
 80004ae:	ea43 4304 	orr.w	r3, r3, r4, lsl #16
 80004b2:	fb07 f006 	mul.w	r0, r7, r6
 80004b6:	4298      	cmp	r0, r3
 80004b8:	d908      	bls.n	80004cc <__udivmoddi4+0x11c>
 80004ba:	eb1c 0303 	adds.w	r3, ip, r3
 80004be:	f106 34ff 	add.w	r4, r6, #4294967295	@ 0xffffffff
 80004c2:	d202      	bcs.n	80004ca <__udivmoddi4+0x11a>
 80004c4:	4298      	cmp	r0, r3
 80004c6:	f200 80cd 	bhi.w	8000664 <__udivmoddi4+0x2b4>
 80004ca:	4626      	mov	r6, r4
 80004cc:	1a1c      	subs	r4, r3, r0
 80004ce:	fa1f f38e 	uxth.w	r3, lr
 80004d2:	fbb4 f0f8 	udiv	r0, r4, r8
 80004d6:	fb08 4410 	mls	r4, r8, r0, r4
 80004da:	ea43 4304 	orr.w	r3, r3, r4, lsl #16
 80004de:	fb00 f707 	mul.w	r7, r0, r7
 80004e2:	429f      	cmp	r7, r3
 80004e4:	d908      	bls.n	80004f8 <__udivmoddi4+0x148>
 80004e6:	eb1c 0303 	adds.w	r3, ip, r3
 80004ea:	f100 34ff 	add.w	r4, r0, #4294967295	@ 0xffffffff
 80004ee:	d202      	bcs.n	80004f6 <__udivmoddi4+0x146>
 80004f0:	429f      	cmp	r7, r3
 80004f2:	f200 80b0 	bhi.w	8000656 <__udivmoddi4+0x2a6>
 80004f6:	4620      	mov	r0, r4
 80004f8:	1bdb      	subs	r3, r3, r7
 80004fa:	ea40 4006 	orr.w	r0, r0, r6, lsl #16
 80004fe:	e7a5      	b.n	800044c <__udivmoddi4+0x9c>
 8000500:	f1c1 0620 	rsb	r6, r1, #32
 8000504:	408b      	lsls	r3, r1
 8000506:	fa22 f706 	lsr.w	r7, r2, r6
 800050a:	431f      	orrs	r7, r3
 800050c:	fa20 fc06 	lsr.w	ip, r0, r6
 8000510:	fa04 f301 	lsl.w	r3, r4, r1
 8000514:	ea43 030c 	orr.w	r3, r3, ip
 8000518:	40f4      	lsrs	r4, r6
 800051a:	fa00 f801 	lsl.w	r8, r0, r1
 800051e:	0c38      	lsrs	r0, r7, #16
 8000520:	ea4f 4913 	mov.w	r9, r3, lsr #16
 8000524:	fbb4 fef0 	udiv	lr, r4, r0
 8000528:	fa1f fc87 	uxth.w	ip, r7
 800052c:	fb00 441e 	mls	r4, r0, lr, r4
 8000530:	ea49 4404 	orr.w	r4, r9, r4, lsl #16
 8000534:	fb0e f90c 	mul.w	r9, lr, ip
 8000538:	45a1      	cmp	r9, r4
 800053a:	fa02 f201 	lsl.w	r2, r2, r1
 800053e:	d90a      	bls.n	8000556 <__udivmoddi4+0x1a6>
 8000540:	193c      	adds	r4, r7, r4
 8000542:	f10e 3aff 	add.w	sl, lr, #4294967295	@ 0xffffffff
 8000546:	f080 8084 	bcs.w	8000652 <__udivmoddi4+0x2a2>
 800054a:	45a1      	cmp	r9, r4
 800054c:	f240 8081 	bls.w	8000652 <__udivmoddi4+0x2a2>
 8000550:	f1ae 0e02 	sub.w	lr, lr, #2
 8000554:	443c      	add	r4, r7
 8000556:	eba4 0409 	sub.w	r4, r4, r9
 800055a:	fa1f f983 	uxth.w	r9, r3
 800055e:	fbb4 f3f0 	udiv	r3, r4, r0
 8000562:	fb00 4413 	mls	r4, r0, r3, r4
 8000566:	ea49 4404 	orr.w	r4, r9, r4, lsl #16
 800056a:	fb03 fc0c 	mul.w	ip, r3, ip
 800056e:	45a4      	cmp	ip, r4
 8000570:	d907      	bls.n	8000582 <__udivmoddi4+0x1d2>
 8000572:	193c      	adds	r4, r7, r4
 8000574:	f103 30ff 	add.w	r0, r3, #4294967295	@ 0xffffffff
 8000578:	d267      	bcs.n	800064a <__udivmoddi4+0x29a>
 800057a:	45a4      	cmp	ip, r4
 800057c:	d965      	bls.n	800064a <__udivmoddi4+0x29a>
 800057e:	3b02      	subs	r3, #2
 8000580:	443c      	add	r4, r7
 8000582:	ea43 400e 	orr.w	r0, r3, lr, lsl #16
 8000586:	fba0 9302 	umull	r9, r3, r0, r2
 800058a:	eba4 040c 	sub.w	r4, r4, ip
 800058e:	429c      	cmp	r4, r3
 8000590:	46ce      	mov	lr, r9
 8000592:	469c      	mov	ip, r3
 8000594:	d351      	bcc.n	800063a <__udivmoddi4+0x28a>
 8000596:	d04e      	beq.n	8000636 <__udivmoddi4+0x286>
 8000598:	b155      	cbz	r5, 80005b0 <__udivmoddi4+0x200>
 800059a:	ebb8 030e 	subs.w	r3, r8, lr
 800059e:	eb64 040c 	sbc.w	r4, r4, ip
 80005a2:	fa04 f606 	lsl.w	r6, r4, r6
 80005a6:	40cb      	lsrs	r3, r1
 80005a8:	431e      	orrs	r6, r3
 80005aa:	40cc      	lsrs	r4, r1
 80005ac:	e9c5 6400 	strd	r6, r4, [r5]
 80005b0:	2100      	movs	r1, #0
 80005b2:	e750      	b.n	8000456 <__udivmoddi4+0xa6>
 80005b4:	f1c2 0320 	rsb	r3, r2, #32
 80005b8:	fa20 f103 	lsr.w	r1, r0, r3
 80005bc:	fa0c fc02 	lsl.w	ip, ip, r2
 80005c0:	fa24 f303 	lsr.w	r3, r4, r3
 80005c4:	4094      	lsls	r4, r2
 80005c6:	430c      	orrs	r4, r1
 80005c8:	ea4f 481c 	mov.w	r8, ip, lsr #16
 80005cc:	fa00 fe02 	lsl.w	lr, r0, r2
 80005d0:	fa1f f78c 	uxth.w	r7, ip
 80005d4:	fbb3 f0f8 	udiv	r0, r3, r8
 80005d8:	fb08 3110 	mls	r1, r8, r0, r3
 80005dc:	0c23      	lsrs	r3, r4, #16
 80005de:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
 80005e2:	fb00 f107 	mul.w	r1, r0, r7
 80005e6:	4299      	cmp	r1, r3
 80005e8:	d908      	bls.n	80005fc <__udivmoddi4+0x24c>
 80005ea:	eb1c 0303 	adds.w	r3, ip, r3
 80005ee:	f100 36ff 	add.w	r6, r0, #4294967295	@ 0xffffffff
 80005f2:	d22c      	bcs.n	800064e <__udivmoddi4+0x29e>
 80005f4:	4299      	cmp	r1, r3
 80005f6:	d92a      	bls.n	800064e <__udivmoddi4+0x29e>
 80005f8:	3802      	subs	r0, #2
 80005fa:	4463      	add	r3, ip
 80005fc:	1a5b      	subs	r3, r3, r1
 80005fe:	b2a4      	uxth	r4, r4
 8000600:	fbb3 f1f8 	udiv	r1, r3, r8
 8000604:	fb08 3311 	mls	r3, r8, r1, r3
 8000608:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
 800060c:	fb01 f307 	mul.w	r3, r1, r7
 8000610:	42a3      	cmp	r3, r4
 8000612:	d908      	bls.n	8000626 <__udivmoddi4+0x276>
 8000614:	eb1c 0404 	adds.w	r4, ip, r4
 8000618:	f101 36ff 	add.w	r6, r1, #4294967295	@ 0xffffffff
 800061c:	d213      	bcs.n	8000646 <__udivmoddi4+0x296>
 800061e:	42a3      	cmp	r3, r4
 8000620:	d911      	bls.n	8000646 <__udivmoddi4+0x296>
 8000622:	3902      	subs	r1, #2
 8000624:	4464      	add	r4, ip
 8000626:	1ae4      	subs	r4, r4, r3
 8000628:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
 800062c:	e739      	b.n	80004a2 <__udivmoddi4+0xf2>
 800062e:	4604      	mov	r4, r0
 8000630:	e6f0      	b.n	8000414 <__udivmoddi4+0x64>
 8000632:	4608      	mov	r0, r1
 8000634:	e706      	b.n	8000444 <__udivmoddi4+0x94>
 8000636:	45c8      	cmp	r8, r9
 8000638:	d2ae      	bcs.n	8000598 <__udivmoddi4+0x1e8>
 800063a:	ebb9 0e02 	subs.w	lr, r9, r2
 800063e:	eb63 0c07 	sbc.w	ip, r3, r7
 8000642:	3801      	subs	r0, #1
 8000644:	e7a8      	b.n	8000598 <__udivmoddi4+0x1e8>
 8000646:	4631      	mov	r1, r6
 8000648:	e7ed      	b.n	8000626 <__udivmoddi4+0x276>
 800064a:	4603      	mov	r3, r0
 800064c:	e799      	b.n	8000582 <__udivmoddi4+0x1d2>
 800064e:	4630      	mov	r0, r6
 8000650:	e7d4      	b.n	80005fc <__udivmoddi4+0x24c>
 8000652:	46d6      	mov	lr, sl
 8000654:	e77f      	b.n	8000556 <__udivmoddi4+0x1a6>
 8000656:	4463      	add	r3, ip
 8000658:	3802      	subs	r0, #2
 800065a:	e74d      	b.n	80004f8 <__udivmoddi4+0x148>
 800065c:	4606      	mov	r6, r0
 800065e:	4623      	mov	r3, r4
 8000660:	4608      	mov	r0, r1
 8000662:	e70f      	b.n	8000484 <__udivmoddi4+0xd4>
 8000664:	3e02      	subs	r6, #2
 8000666:	4463      	add	r3, ip
 8000668:	e730      	b.n	80004cc <__udivmoddi4+0x11c>
 800066a:	bf00      	nop

0800066c <__aeabi_idiv0>:
 800066c:	4770      	bx	lr
 800066e:	bf00      	nop

08000670 <vApplicationStackOverflowHook>:
/* Hook prototypes */
void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName);

/* USER CODE BEGIN 4 */
void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
{
 8000670:	b480      	push	{r7}
 8000672:	b083      	sub	sp, #12
 8000674:	af00      	add	r7, sp, #0
 8000676:	6078      	str	r0, [r7, #4]
 8000678:	6039      	str	r1, [r7, #0]
   /* Run time stack overflow checking is performed if
   configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
   called if a stack overflow is detected. */
}
 800067a:	bf00      	nop
 800067c:	370c      	adds	r7, #12
 800067e:	46bd      	mov	sp, r7
 8000680:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000684:	4770      	bx	lr
	...

08000688 <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 8000688:	b580      	push	{r7, lr}
 800068a:	b084      	sub	sp, #16
 800068c:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN 1 */

  /* USER CODE END 1 */

  /* MPU Configuration--------------------------------------------------------*/
  MPU_Config();
 800068e:	f000 fe9b 	bl	80013c8 <MPU_Config>
  \details Turns on I-Cache
  */
__STATIC_FORCEINLINE void SCB_EnableICache (void)
{
  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
 8000692:	4b47      	ldr	r3, [pc, #284]	@ (80007b0 <main+0x128>)
 8000694:	695b      	ldr	r3, [r3, #20]
 8000696:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800069a:	2b00      	cmp	r3, #0
 800069c:	d11b      	bne.n	80006d6 <main+0x4e>
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
 800069e:	f3bf 8f4f 	dsb	sy
}
 80006a2:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 80006a4:	f3bf 8f6f 	isb	sy
}
 80006a8:	bf00      	nop

    __DSB();
    __ISB();
    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
 80006aa:	4b41      	ldr	r3, [pc, #260]	@ (80007b0 <main+0x128>)
 80006ac:	2200      	movs	r2, #0
 80006ae:	f8c3 2250 	str.w	r2, [r3, #592]	@ 0x250
  __ASM volatile ("dsb 0xF":::"memory");
 80006b2:	f3bf 8f4f 	dsb	sy
}
 80006b6:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 80006b8:	f3bf 8f6f 	isb	sy
}
 80006bc:	bf00      	nop
    __DSB();
    __ISB();
    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
 80006be:	4b3c      	ldr	r3, [pc, #240]	@ (80007b0 <main+0x128>)
 80006c0:	695b      	ldr	r3, [r3, #20]
 80006c2:	4a3b      	ldr	r2, [pc, #236]	@ (80007b0 <main+0x128>)
 80006c4:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 80006c8:	6153      	str	r3, [r2, #20]
  __ASM volatile ("dsb 0xF":::"memory");
 80006ca:	f3bf 8f4f 	dsb	sy
}
 80006ce:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 80006d0:	f3bf 8f6f 	isb	sy
}
 80006d4:	e000      	b.n	80006d8 <main+0x50>
    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
 80006d6:	bf00      	nop
  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
    uint32_t ccsidr;
    uint32_t sets;
    uint32_t ways;

    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
 80006d8:	4b35      	ldr	r3, [pc, #212]	@ (80007b0 <main+0x128>)
 80006da:	695b      	ldr	r3, [r3, #20]
 80006dc:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 80006e0:	2b00      	cmp	r3, #0
 80006e2:	d138      	bne.n	8000756 <main+0xce>

    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
 80006e4:	4b32      	ldr	r3, [pc, #200]	@ (80007b0 <main+0x128>)
 80006e6:	2200      	movs	r2, #0
 80006e8:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
  __ASM volatile ("dsb 0xF":::"memory");
 80006ec:	f3bf 8f4f 	dsb	sy
}
 80006f0:	bf00      	nop
    __DSB();

    ccsidr = SCB->CCSIDR;
 80006f2:	4b2f      	ldr	r3, [pc, #188]	@ (80007b0 <main+0x128>)
 80006f4:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 80006f8:	60fb      	str	r3, [r7, #12]

                                            /* invalidate D-Cache */
    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
 80006fa:	68fb      	ldr	r3, [r7, #12]
 80006fc:	0b5b      	lsrs	r3, r3, #13
 80006fe:	f3c3 030e 	ubfx	r3, r3, #0, #15
 8000702:	60bb      	str	r3, [r7, #8]
    do {
      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
 8000704:	68fb      	ldr	r3, [r7, #12]
 8000706:	08db      	lsrs	r3, r3, #3
 8000708:	f3c3 0309 	ubfx	r3, r3, #0, #10
 800070c:	607b      	str	r3, [r7, #4]
      do {
        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
 800070e:	68bb      	ldr	r3, [r7, #8]
 8000710:	015a      	lsls	r2, r3, #5
 8000712:	f643 73e0 	movw	r3, #16352	@ 0x3fe0
 8000716:	4013      	ands	r3, r2
                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
 8000718:	687a      	ldr	r2, [r7, #4]
 800071a:	0792      	lsls	r2, r2, #30
        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
 800071c:	4924      	ldr	r1, [pc, #144]	@ (80007b0 <main+0x128>)
 800071e:	4313      	orrs	r3, r2
 8000720:	f8c1 3260 	str.w	r3, [r1, #608]	@ 0x260
        #if defined ( __CC_ARM )
          __schedule_barrier();
        #endif
      } while (ways-- != 0U);
 8000724:	687b      	ldr	r3, [r7, #4]
 8000726:	1e5a      	subs	r2, r3, #1
 8000728:	607a      	str	r2, [r7, #4]
 800072a:	2b00      	cmp	r3, #0
 800072c:	d1ef      	bne.n	800070e <main+0x86>
    } while(sets-- != 0U);
 800072e:	68bb      	ldr	r3, [r7, #8]
 8000730:	1e5a      	subs	r2, r3, #1
 8000732:	60ba      	str	r2, [r7, #8]
 8000734:	2b00      	cmp	r3, #0
 8000736:	d1e5      	bne.n	8000704 <main+0x7c>
  __ASM volatile ("dsb 0xF":::"memory");
 8000738:	f3bf 8f4f 	dsb	sy
}
 800073c:	bf00      	nop
    __DSB();

    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
 800073e:	4b1c      	ldr	r3, [pc, #112]	@ (80007b0 <main+0x128>)
 8000740:	695b      	ldr	r3, [r3, #20]
 8000742:	4a1b      	ldr	r2, [pc, #108]	@ (80007b0 <main+0x128>)
 8000744:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 8000748:	6153      	str	r3, [r2, #20]
  __ASM volatile ("dsb 0xF":::"memory");
 800074a:	f3bf 8f4f 	dsb	sy
}
 800074e:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 8000750:	f3bf 8f6f 	isb	sy
}
 8000754:	e000      	b.n	8000758 <main+0xd0>
    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
 8000756:	bf00      	nop
  SCB_EnableDCache();

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 8000758:	f002 fe64 	bl	8003424 <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 800075c:	f000 f830 	bl	80007c0 <SystemClock_Config>

/* Configure the peripherals common clocks */
  PeriphCommonClock_Config();
 8000760:	f000 f8aa 	bl	80008b8 <PeriphCommonClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 8000764:	f000 fc50 	bl	8001008 <MX_GPIO_Init>
  MX_DMA_Init();
 8000768:	f000 fc1e 	bl	8000fa8 <MX_DMA_Init>
  MX_RNG_Init();
 800076c:	f000 fb1a 	bl	8000da4 <MX_RNG_Init>
  MX_USART1_UART_Init();
 8000770:	f000 fbca 	bl	8000f08 <MX_USART1_UART_Init>
  MX_ADC1_Init();
 8000774:	f000 f8d0 	bl	8000918 <MX_ADC1_Init>
  MX_UART8_Init();
 8000778:	f000 fb7a 	bl	8000e70 <MX_UART8_Init>
  MX_CRC_Init();
 800077c:	f000 fae8 	bl	8000d50 <MX_CRC_Init>
  MX_ADC2_Init();
 8000780:	f000 f9a2 	bl	8000ac8 <MX_ADC2_Init>
  MX_ADC3_Init();
 8000784:	f000 fa34 	bl	8000bf0 <MX_ADC3_Init>
  MX_TIM2_Init();
 8000788:	f000 fb22 	bl	8000dd0 <MX_TIM2_Init>
  /* USER CODE BEGIN 2 */

  /* USER CODE END 2 */

  /* Init scheduler */
  osKernelInitialize();
 800078c:	f00e ff56 	bl	800f63c <osKernelInitialize>
  /* add queues, ... */
  /* USER CODE END RTOS_QUEUES */

  /* Create the thread(s) */
  /* creation of defaultTask */
  defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
 8000790:	4a08      	ldr	r2, [pc, #32]	@ (80007b4 <main+0x12c>)
 8000792:	2100      	movs	r1, #0
 8000794:	4808      	ldr	r0, [pc, #32]	@ (80007b8 <main+0x130>)
 8000796:	f00e ff9b 	bl	800f6d0 <osThreadNew>
 800079a:	4603      	mov	r3, r0
 800079c:	4a07      	ldr	r2, [pc, #28]	@ (80007bc <main+0x134>)
 800079e:	6013      	str	r3, [r2, #0]

  /* USER CODE BEGIN RTOS_THREADS */
  /* add threads, ... */
//  Uart8TasksInit();
  UartTasksInit();
 80007a0:	f002 f8c8 	bl	8002934 <UartTasksInit>
#ifdef USER_MOCKS
  MockMeasurmetsTaskInit();
#else
  MeasTasksInit();
 80007a4:	f000 fe7a 	bl	800149c <MeasTasksInit>
  /* USER CODE BEGIN RTOS_EVENTS */
  /* add events, ... */
  /* USER CODE END RTOS_EVENTS */

  /* Start scheduler */
  osKernelStart();
 80007a8:	f00e ff6c 	bl	800f684 <osKernelStart>

  /* We should never get here as control is now taken by the scheduler */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
 80007ac:	bf00      	nop
 80007ae:	e7fd      	b.n	80007ac <main+0x124>
 80007b0:	e000ed00 	.word	0xe000ed00
 80007b4:	080145c0 	.word	0x080145c0
 80007b8:	08001329 	.word	0x08001329
 80007bc:	24000580 	.word	0x24000580

080007c0 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 80007c0:	b580      	push	{r7, lr}
 80007c2:	b09c      	sub	sp, #112	@ 0x70
 80007c4:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 80007c6:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 80007ca:	224c      	movs	r2, #76	@ 0x4c
 80007cc:	2100      	movs	r1, #0
 80007ce:	4618      	mov	r0, r3
 80007d0:	f013 f809 	bl	80137e6 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 80007d4:	1d3b      	adds	r3, r7, #4
 80007d6:	2220      	movs	r2, #32
 80007d8:	2100      	movs	r1, #0
 80007da:	4618      	mov	r0, r3
 80007dc:	f013 f803 	bl	80137e6 <memset>

  /** Supply configuration update enable
  */
  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
 80007e0:	2002      	movs	r0, #2
 80007e2:	f007 fe25 	bl	8008430 <HAL_PWREx_ConfigSupply>

  /** Configure the main internal regulator output voltage
  */
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 80007e6:	2300      	movs	r3, #0
 80007e8:	603b      	str	r3, [r7, #0]
 80007ea:	4b31      	ldr	r3, [pc, #196]	@ (80008b0 <SystemClock_Config+0xf0>)
 80007ec:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80007ee:	4a30      	ldr	r2, [pc, #192]	@ (80008b0 <SystemClock_Config+0xf0>)
 80007f0:	f023 0301 	bic.w	r3, r3, #1
 80007f4:	62d3      	str	r3, [r2, #44]	@ 0x2c
 80007f6:	4b2e      	ldr	r3, [pc, #184]	@ (80008b0 <SystemClock_Config+0xf0>)
 80007f8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80007fa:	f003 0301 	and.w	r3, r3, #1
 80007fe:	603b      	str	r3, [r7, #0]
 8000800:	4b2c      	ldr	r3, [pc, #176]	@ (80008b4 <SystemClock_Config+0xf4>)
 8000802:	699b      	ldr	r3, [r3, #24]
 8000804:	4a2b      	ldr	r2, [pc, #172]	@ (80008b4 <SystemClock_Config+0xf4>)
 8000806:	f443 4340 	orr.w	r3, r3, #49152	@ 0xc000
 800080a:	6193      	str	r3, [r2, #24]
 800080c:	4b29      	ldr	r3, [pc, #164]	@ (80008b4 <SystemClock_Config+0xf4>)
 800080e:	699b      	ldr	r3, [r3, #24]
 8000810:	f403 4340 	and.w	r3, r3, #49152	@ 0xc000
 8000814:	603b      	str	r3, [r7, #0]
 8000816:	683b      	ldr	r3, [r7, #0]

  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
 8000818:	bf00      	nop
 800081a:	4b26      	ldr	r3, [pc, #152]	@ (80008b4 <SystemClock_Config+0xf4>)
 800081c:	699b      	ldr	r3, [r3, #24]
 800081e:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 8000822:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 8000826:	d1f8      	bne.n	800081a <SystemClock_Config+0x5a>

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
 8000828:	2321      	movs	r3, #33	@ 0x21
 800082a:	627b      	str	r3, [r7, #36]	@ 0x24
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 800082c:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
 8000830:	62bb      	str	r3, [r7, #40]	@ 0x28
  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
 8000832:	2301      	movs	r3, #1
 8000834:	63fb      	str	r3, [r7, #60]	@ 0x3c
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8000836:	2302      	movs	r3, #2
 8000838:	64bb      	str	r3, [r7, #72]	@ 0x48
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 800083a:	2302      	movs	r3, #2
 800083c:	64fb      	str	r3, [r7, #76]	@ 0x4c
  RCC_OscInitStruct.PLL.PLLM = 5;
 800083e:	2305      	movs	r3, #5
 8000840:	653b      	str	r3, [r7, #80]	@ 0x50
  RCC_OscInitStruct.PLL.PLLN = 160;
 8000842:	23a0      	movs	r3, #160	@ 0xa0
 8000844:	657b      	str	r3, [r7, #84]	@ 0x54
  RCC_OscInitStruct.PLL.PLLP = 2;
 8000846:	2302      	movs	r3, #2
 8000848:	65bb      	str	r3, [r7, #88]	@ 0x58
  RCC_OscInitStruct.PLL.PLLQ = 2;
 800084a:	2302      	movs	r3, #2
 800084c:	65fb      	str	r3, [r7, #92]	@ 0x5c
  RCC_OscInitStruct.PLL.PLLR = 2;
 800084e:	2302      	movs	r3, #2
 8000850:	663b      	str	r3, [r7, #96]	@ 0x60
  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
 8000852:	2308      	movs	r3, #8
 8000854:	667b      	str	r3, [r7, #100]	@ 0x64
  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
 8000856:	2300      	movs	r3, #0
 8000858:	66bb      	str	r3, [r7, #104]	@ 0x68
  RCC_OscInitStruct.PLL.PLLFRACN = 0;
 800085a:	2300      	movs	r3, #0
 800085c:	66fb      	str	r3, [r7, #108]	@ 0x6c
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 800085e:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 8000862:	4618      	mov	r0, r3
 8000864:	f007 fe1e 	bl	80084a4 <HAL_RCC_OscConfig>
 8000868:	4603      	mov	r3, r0
 800086a:	2b00      	cmp	r3, #0
 800086c:	d001      	beq.n	8000872 <SystemClock_Config+0xb2>
  {
    Error_Handler();
 800086e:	f000 fe0f 	bl	8001490 <Error_Handler>
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8000872:	233f      	movs	r3, #63	@ 0x3f
 8000874:	607b      	str	r3, [r7, #4]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 8000876:	2303      	movs	r3, #3
 8000878:	60bb      	str	r3, [r7, #8]
  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
 800087a:	2300      	movs	r3, #0
 800087c:	60fb      	str	r3, [r7, #12]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
 800087e:	2308      	movs	r3, #8
 8000880:	613b      	str	r3, [r7, #16]
  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
 8000882:	2340      	movs	r3, #64	@ 0x40
 8000884:	617b      	str	r3, [r7, #20]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
 8000886:	2340      	movs	r3, #64	@ 0x40
 8000888:	61bb      	str	r3, [r7, #24]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
 800088a:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 800088e:	61fb      	str	r3, [r7, #28]
  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
 8000890:	2340      	movs	r3, #64	@ 0x40
 8000892:	623b      	str	r3, [r7, #32]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8000894:	1d3b      	adds	r3, r7, #4
 8000896:	2102      	movs	r1, #2
 8000898:	4618      	mov	r0, r3
 800089a:	f008 fa5d 	bl	8008d58 <HAL_RCC_ClockConfig>
 800089e:	4603      	mov	r3, r0
 80008a0:	2b00      	cmp	r3, #0
 80008a2:	d001      	beq.n	80008a8 <SystemClock_Config+0xe8>
  {
    Error_Handler();
 80008a4:	f000 fdf4 	bl	8001490 <Error_Handler>
  }
}
 80008a8:	bf00      	nop
 80008aa:	3770      	adds	r7, #112	@ 0x70
 80008ac:	46bd      	mov	sp, r7
 80008ae:	bd80      	pop	{r7, pc}
 80008b0:	58000400 	.word	0x58000400
 80008b4:	58024800 	.word	0x58024800

080008b8 <PeriphCommonClock_Config>:
/**
  * @brief Peripherals Common Clock Configuration
  * @retval None
  */
void PeriphCommonClock_Config(void)
{
 80008b8:	b580      	push	{r7, lr}
 80008ba:	b0b0      	sub	sp, #192	@ 0xc0
 80008bc:	af00      	add	r7, sp, #0
  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 80008be:	463b      	mov	r3, r7
 80008c0:	22c0      	movs	r2, #192	@ 0xc0
 80008c2:	2100      	movs	r1, #0
 80008c4:	4618      	mov	r0, r3
 80008c6:	f012 ff8e 	bl	80137e6 <memset>

  /** Initializes the peripherals clock
  */
  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
 80008ca:	f44f 2200 	mov.w	r2, #524288	@ 0x80000
 80008ce:	f04f 0300 	mov.w	r3, #0
 80008d2:	e9c7 2300 	strd	r2, r3, [r7]
  PeriphClkInitStruct.PLL2.PLL2M = 5;
 80008d6:	2305      	movs	r3, #5
 80008d8:	60bb      	str	r3, [r7, #8]
  PeriphClkInitStruct.PLL2.PLL2N = 52;
 80008da:	2334      	movs	r3, #52	@ 0x34
 80008dc:	60fb      	str	r3, [r7, #12]
  PeriphClkInitStruct.PLL2.PLL2P = 26;
 80008de:	231a      	movs	r3, #26
 80008e0:	613b      	str	r3, [r7, #16]
  PeriphClkInitStruct.PLL2.PLL2Q = 2;
 80008e2:	2302      	movs	r3, #2
 80008e4:	617b      	str	r3, [r7, #20]
  PeriphClkInitStruct.PLL2.PLL2R = 2;
 80008e6:	2302      	movs	r3, #2
 80008e8:	61bb      	str	r3, [r7, #24]
  PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2;
 80008ea:	2380      	movs	r3, #128	@ 0x80
 80008ec:	61fb      	str	r3, [r7, #28]
  PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
 80008ee:	2300      	movs	r3, #0
 80008f0:	623b      	str	r3, [r7, #32]
  PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
 80008f2:	2300      	movs	r3, #0
 80008f4:	627b      	str	r3, [r7, #36]	@ 0x24
  PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
 80008f6:	2300      	movs	r3, #0
 80008f8:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 80008fc:	463b      	mov	r3, r7
 80008fe:	4618      	mov	r0, r3
 8000900:	f008 fdf8 	bl	80094f4 <HAL_RCCEx_PeriphCLKConfig>
 8000904:	4603      	mov	r3, r0
 8000906:	2b00      	cmp	r3, #0
 8000908:	d001      	beq.n	800090e <PeriphCommonClock_Config+0x56>
  {
    Error_Handler();
 800090a:	f000 fdc1 	bl	8001490 <Error_Handler>
  }
}
 800090e:	bf00      	nop
 8000910:	37c0      	adds	r7, #192	@ 0xc0
 8000912:	46bd      	mov	sp, r7
 8000914:	bd80      	pop	{r7, pc}
	...

08000918 <MX_ADC1_Init>:
  * @brief ADC1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_ADC1_Init(void)
{
 8000918:	b580      	push	{r7, lr}
 800091a:	b08a      	sub	sp, #40	@ 0x28
 800091c:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN ADC1_Init 0 */

  /* USER CODE END ADC1_Init 0 */

  ADC_MultiModeTypeDef multimode = {0};
 800091e:	f107 031c 	add.w	r3, r7, #28
 8000922:	2200      	movs	r2, #0
 8000924:	601a      	str	r2, [r3, #0]
 8000926:	605a      	str	r2, [r3, #4]
 8000928:	609a      	str	r2, [r3, #8]
  ADC_ChannelConfTypeDef sConfig = {0};
 800092a:	463b      	mov	r3, r7
 800092c:	2200      	movs	r2, #0
 800092e:	601a      	str	r2, [r3, #0]
 8000930:	605a      	str	r2, [r3, #4]
 8000932:	609a      	str	r2, [r3, #8]
 8000934:	60da      	str	r2, [r3, #12]
 8000936:	611a      	str	r2, [r3, #16]
 8000938:	615a      	str	r2, [r3, #20]
 800093a:	619a      	str	r2, [r3, #24]

  /* USER CODE END ADC1_Init 1 */

  /** Common config
  */
  hadc1.Instance = ADC1;
 800093c:	4b5a      	ldr	r3, [pc, #360]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 800093e:	4a5b      	ldr	r2, [pc, #364]	@ (8000aac <MX_ADC1_Init+0x194>)
 8000940:	601a      	str	r2, [r3, #0]
  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
 8000942:	4b59      	ldr	r3, [pc, #356]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000944:	2200      	movs	r2, #0
 8000946:	605a      	str	r2, [r3, #4]
  hadc1.Init.Resolution = ADC_RESOLUTION_16B;
 8000948:	4b57      	ldr	r3, [pc, #348]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 800094a:	2200      	movs	r2, #0
 800094c:	609a      	str	r2, [r3, #8]
  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
 800094e:	4b56      	ldr	r3, [pc, #344]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000950:	2201      	movs	r2, #1
 8000952:	60da      	str	r2, [r3, #12]
  hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
 8000954:	4b54      	ldr	r3, [pc, #336]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000956:	2208      	movs	r2, #8
 8000958:	611a      	str	r2, [r3, #16]
  hadc1.Init.LowPowerAutoWait = DISABLE;
 800095a:	4b53      	ldr	r3, [pc, #332]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 800095c:	2200      	movs	r2, #0
 800095e:	751a      	strb	r2, [r3, #20]
  hadc1.Init.ContinuousConvMode = ENABLE;
 8000960:	4b51      	ldr	r3, [pc, #324]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000962:	2201      	movs	r2, #1
 8000964:	755a      	strb	r2, [r3, #21]
  hadc1.Init.NbrOfConversion = 6;
 8000966:	4b50      	ldr	r3, [pc, #320]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000968:	2206      	movs	r2, #6
 800096a:	619a      	str	r2, [r3, #24]
  hadc1.Init.DiscontinuousConvMode = DISABLE;
 800096c:	4b4e      	ldr	r3, [pc, #312]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 800096e:	2200      	movs	r2, #0
 8000970:	771a      	strb	r2, [r3, #28]
  hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO;
 8000972:	4b4d      	ldr	r3, [pc, #308]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000974:	f44f 62ac 	mov.w	r2, #1376	@ 0x560
 8000978:	625a      	str	r2, [r3, #36]	@ 0x24
  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
 800097a:	4b4b      	ldr	r3, [pc, #300]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 800097c:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 8000980:	629a      	str	r2, [r3, #40]	@ 0x28
  hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT;
 8000982:	4b49      	ldr	r3, [pc, #292]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000984:	2201      	movs	r2, #1
 8000986:	62da      	str	r2, [r3, #44]	@ 0x2c
  hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
 8000988:	4b47      	ldr	r3, [pc, #284]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 800098a:	2200      	movs	r2, #0
 800098c:	631a      	str	r2, [r3, #48]	@ 0x30
  hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
 800098e:	4b46      	ldr	r3, [pc, #280]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000990:	2200      	movs	r2, #0
 8000992:	635a      	str	r2, [r3, #52]	@ 0x34
  hadc1.Init.OversamplingMode = DISABLE;
 8000994:	4b44      	ldr	r3, [pc, #272]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000996:	2200      	movs	r2, #0
 8000998:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 800099c:	4842      	ldr	r0, [pc, #264]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 800099e:	f002 ffcd 	bl	800393c <HAL_ADC_Init>
 80009a2:	4603      	mov	r3, r0
 80009a4:	2b00      	cmp	r3, #0
 80009a6:	d001      	beq.n	80009ac <MX_ADC1_Init+0x94>
  {
    Error_Handler();
 80009a8:	f000 fd72 	bl	8001490 <Error_Handler>
  }

  /** Configure the ADC multi-mode
  */
  multimode.Mode = ADC_MODE_INDEPENDENT;
 80009ac:	2300      	movs	r3, #0
 80009ae:	61fb      	str	r3, [r7, #28]
  if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
 80009b0:	f107 031c 	add.w	r3, r7, #28
 80009b4:	4619      	mov	r1, r3
 80009b6:	483c      	ldr	r0, [pc, #240]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 80009b8:	f004 f8de 	bl	8004b78 <HAL_ADCEx_MultiModeConfigChannel>
 80009bc:	4603      	mov	r3, r0
 80009be:	2b00      	cmp	r3, #0
 80009c0:	d001      	beq.n	80009c6 <MX_ADC1_Init+0xae>
  {
    Error_Handler();
 80009c2:	f000 fd65 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_8;
 80009c6:	4b3a      	ldr	r3, [pc, #232]	@ (8000ab0 <MX_ADC1_Init+0x198>)
 80009c8:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 80009ca:	2306      	movs	r3, #6
 80009cc:	607b      	str	r3, [r7, #4]
  sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5;
 80009ce:	2306      	movs	r3, #6
 80009d0:	60bb      	str	r3, [r7, #8]
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
 80009d2:	f240 73ff 	movw	r3, #2047	@ 0x7ff
 80009d6:	60fb      	str	r3, [r7, #12]
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
 80009d8:	2304      	movs	r3, #4
 80009da:	613b      	str	r3, [r7, #16]
  sConfig.Offset = 0;
 80009dc:	2300      	movs	r3, #0
 80009de:	617b      	str	r3, [r7, #20]
  sConfig.OffsetSignedSaturation = DISABLE;
 80009e0:	2300      	movs	r3, #0
 80009e2:	767b      	strb	r3, [r7, #25]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 80009e4:	463b      	mov	r3, r7
 80009e6:	4619      	mov	r1, r3
 80009e8:	482f      	ldr	r0, [pc, #188]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 80009ea:	f003 fa21 	bl	8003e30 <HAL_ADC_ConfigChannel>
 80009ee:	4603      	mov	r3, r0
 80009f0:	2b00      	cmp	r3, #0
 80009f2:	d001      	beq.n	80009f8 <MX_ADC1_Init+0xe0>
  {
    Error_Handler();
 80009f4:	f000 fd4c 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_7;
 80009f8:	4b2e      	ldr	r3, [pc, #184]	@ (8000ab4 <MX_ADC1_Init+0x19c>)
 80009fa:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_2;
 80009fc:	230c      	movs	r3, #12
 80009fe:	607b      	str	r3, [r7, #4]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8000a00:	463b      	mov	r3, r7
 8000a02:	4619      	mov	r1, r3
 8000a04:	4828      	ldr	r0, [pc, #160]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000a06:	f003 fa13 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000a0a:	4603      	mov	r3, r0
 8000a0c:	2b00      	cmp	r3, #0
 8000a0e:	d001      	beq.n	8000a14 <MX_ADC1_Init+0xfc>
  {
    Error_Handler();
 8000a10:	f000 fd3e 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_9;
 8000a14:	4b28      	ldr	r3, [pc, #160]	@ (8000ab8 <MX_ADC1_Init+0x1a0>)
 8000a16:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_3;
 8000a18:	2312      	movs	r3, #18
 8000a1a:	607b      	str	r3, [r7, #4]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8000a1c:	463b      	mov	r3, r7
 8000a1e:	4619      	mov	r1, r3
 8000a20:	4821      	ldr	r0, [pc, #132]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000a22:	f003 fa05 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000a26:	4603      	mov	r3, r0
 8000a28:	2b00      	cmp	r3, #0
 8000a2a:	d001      	beq.n	8000a30 <MX_ADC1_Init+0x118>
  {
    Error_Handler();
 8000a2c:	f000 fd30 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_16;
 8000a30:	4b22      	ldr	r3, [pc, #136]	@ (8000abc <MX_ADC1_Init+0x1a4>)
 8000a32:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_4;
 8000a34:	2318      	movs	r3, #24
 8000a36:	607b      	str	r3, [r7, #4]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8000a38:	463b      	mov	r3, r7
 8000a3a:	4619      	mov	r1, r3
 8000a3c:	481a      	ldr	r0, [pc, #104]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000a3e:	f003 f9f7 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000a42:	4603      	mov	r3, r0
 8000a44:	2b00      	cmp	r3, #0
 8000a46:	d001      	beq.n	8000a4c <MX_ADC1_Init+0x134>
  {
    Error_Handler();
 8000a48:	f000 fd22 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_17;
 8000a4c:	4b1c      	ldr	r3, [pc, #112]	@ (8000ac0 <MX_ADC1_Init+0x1a8>)
 8000a4e:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_5;
 8000a50:	f44f 7380 	mov.w	r3, #256	@ 0x100
 8000a54:	607b      	str	r3, [r7, #4]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8000a56:	463b      	mov	r3, r7
 8000a58:	4619      	mov	r1, r3
 8000a5a:	4813      	ldr	r0, [pc, #76]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000a5c:	f003 f9e8 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000a60:	4603      	mov	r3, r0
 8000a62:	2b00      	cmp	r3, #0
 8000a64:	d001      	beq.n	8000a6a <MX_ADC1_Init+0x152>
  {
    Error_Handler();
 8000a66:	f000 fd13 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_14;
 8000a6a:	4b16      	ldr	r3, [pc, #88]	@ (8000ac4 <MX_ADC1_Init+0x1ac>)
 8000a6c:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_6;
 8000a6e:	f44f 7383 	mov.w	r3, #262	@ 0x106
 8000a72:	607b      	str	r3, [r7, #4]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8000a74:	463b      	mov	r3, r7
 8000a76:	4619      	mov	r1, r3
 8000a78:	480b      	ldr	r0, [pc, #44]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000a7a:	f003 f9d9 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000a7e:	4603      	mov	r3, r0
 8000a80:	2b00      	cmp	r3, #0
 8000a82:	d001      	beq.n	8000a88 <MX_ADC1_Init+0x170>
  {
    Error_Handler();
 8000a84:	f000 fd04 	bl	8001490 <Error_Handler>
  }
  /* USER CODE BEGIN ADC1_Init 2 */
  if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK)
 8000a88:	f240 72ff 	movw	r2, #2047	@ 0x7ff
 8000a8c:	f04f 1101 	mov.w	r1, #65537	@ 0x10001
 8000a90:	4805      	ldr	r0, [pc, #20]	@ (8000aa8 <MX_ADC1_Init+0x190>)
 8000a92:	f004 f80d 	bl	8004ab0 <HAL_ADCEx_Calibration_Start>
 8000a96:	4603      	mov	r3, r0
 8000a98:	2b00      	cmp	r3, #0
 8000a9a:	d001      	beq.n	8000aa0 <MX_ADC1_Init+0x188>
  {
	  Error_Handler();
 8000a9c:	f000 fcf8 	bl	8001490 <Error_Handler>
  }
  /* USER CODE END ADC1_Init 2 */

}
 8000aa0:	bf00      	nop
 8000aa2:	3728      	adds	r7, #40	@ 0x28
 8000aa4:	46bd      	mov	sp, r7
 8000aa6:	bd80      	pop	{r7, pc}
 8000aa8:	24000140 	.word	0x24000140
 8000aac:	40022000 	.word	0x40022000
 8000ab0:	21800100 	.word	0x21800100
 8000ab4:	1d500080 	.word	0x1d500080
 8000ab8:	25b00200 	.word	0x25b00200
 8000abc:	43210000 	.word	0x43210000
 8000ac0:	47520000 	.word	0x47520000
 8000ac4:	3ac04000 	.word	0x3ac04000

08000ac8 <MX_ADC2_Init>:
  * @brief ADC2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_ADC2_Init(void)
{
 8000ac8:	b580      	push	{r7, lr}
 8000aca:	b088      	sub	sp, #32
 8000acc:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN ADC2_Init 0 */

  /* USER CODE END ADC2_Init 0 */

  ADC_ChannelConfTypeDef sConfig = {0};
 8000ace:	1d3b      	adds	r3, r7, #4
 8000ad0:	2200      	movs	r2, #0
 8000ad2:	601a      	str	r2, [r3, #0]
 8000ad4:	605a      	str	r2, [r3, #4]
 8000ad6:	609a      	str	r2, [r3, #8]
 8000ad8:	60da      	str	r2, [r3, #12]
 8000ada:	611a      	str	r2, [r3, #16]
 8000adc:	615a      	str	r2, [r3, #20]
 8000ade:	619a      	str	r2, [r3, #24]

  /* USER CODE END ADC2_Init 1 */

  /** Common config
  */
  hadc2.Instance = ADC2;
 8000ae0:	4b3e      	ldr	r3, [pc, #248]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000ae2:	4a3f      	ldr	r2, [pc, #252]	@ (8000be0 <MX_ADC2_Init+0x118>)
 8000ae4:	601a      	str	r2, [r3, #0]
  hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
 8000ae6:	4b3d      	ldr	r3, [pc, #244]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000ae8:	2200      	movs	r2, #0
 8000aea:	605a      	str	r2, [r3, #4]
  hadc2.Init.Resolution = ADC_RESOLUTION_16B;
 8000aec:	4b3b      	ldr	r3, [pc, #236]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000aee:	2200      	movs	r2, #0
 8000af0:	609a      	str	r2, [r3, #8]
  hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
 8000af2:	4b3a      	ldr	r3, [pc, #232]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000af4:	2201      	movs	r2, #1
 8000af6:	60da      	str	r2, [r3, #12]
  hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
 8000af8:	4b38      	ldr	r3, [pc, #224]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000afa:	2208      	movs	r2, #8
 8000afc:	611a      	str	r2, [r3, #16]
  hadc2.Init.LowPowerAutoWait = DISABLE;
 8000afe:	4b37      	ldr	r3, [pc, #220]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b00:	2200      	movs	r2, #0
 8000b02:	751a      	strb	r2, [r3, #20]
  hadc2.Init.ContinuousConvMode = ENABLE;
 8000b04:	4b35      	ldr	r3, [pc, #212]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b06:	2201      	movs	r2, #1
 8000b08:	755a      	strb	r2, [r3, #21]
  hadc2.Init.NbrOfConversion = 3;
 8000b0a:	4b34      	ldr	r3, [pc, #208]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b0c:	2203      	movs	r2, #3
 8000b0e:	619a      	str	r2, [r3, #24]
  hadc2.Init.DiscontinuousConvMode = DISABLE;
 8000b10:	4b32      	ldr	r3, [pc, #200]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b12:	2200      	movs	r2, #0
 8000b14:	771a      	strb	r2, [r3, #28]
  hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO;
 8000b16:	4b31      	ldr	r3, [pc, #196]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b18:	f44f 62ac 	mov.w	r2, #1376	@ 0x560
 8000b1c:	625a      	str	r2, [r3, #36]	@ 0x24
  hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
 8000b1e:	4b2f      	ldr	r3, [pc, #188]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b20:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 8000b24:	629a      	str	r2, [r3, #40]	@ 0x28
  hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT;
 8000b26:	4b2d      	ldr	r3, [pc, #180]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b28:	2201      	movs	r2, #1
 8000b2a:	62da      	str	r2, [r3, #44]	@ 0x2c
  hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
 8000b2c:	4b2b      	ldr	r3, [pc, #172]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b2e:	2200      	movs	r2, #0
 8000b30:	631a      	str	r2, [r3, #48]	@ 0x30
  hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
 8000b32:	4b2a      	ldr	r3, [pc, #168]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b34:	2200      	movs	r2, #0
 8000b36:	635a      	str	r2, [r3, #52]	@ 0x34
  hadc2.Init.OversamplingMode = DISABLE;
 8000b38:	4b28      	ldr	r3, [pc, #160]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b3a:	2200      	movs	r2, #0
 8000b3c:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38
  if (HAL_ADC_Init(&hadc2) != HAL_OK)
 8000b40:	4826      	ldr	r0, [pc, #152]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b42:	f002 fefb 	bl	800393c <HAL_ADC_Init>
 8000b46:	4603      	mov	r3, r0
 8000b48:	2b00      	cmp	r3, #0
 8000b4a:	d001      	beq.n	8000b50 <MX_ADC2_Init+0x88>
  {
    Error_Handler();
 8000b4c:	f000 fca0 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_3;
 8000b50:	4b24      	ldr	r3, [pc, #144]	@ (8000be4 <MX_ADC2_Init+0x11c>)
 8000b52:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8000b54:	2306      	movs	r3, #6
 8000b56:	60bb      	str	r3, [r7, #8]
  sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5;
 8000b58:	2306      	movs	r3, #6
 8000b5a:	60fb      	str	r3, [r7, #12]
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
 8000b5c:	f240 73ff 	movw	r3, #2047	@ 0x7ff
 8000b60:	613b      	str	r3, [r7, #16]
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
 8000b62:	2304      	movs	r3, #4
 8000b64:	617b      	str	r3, [r7, #20]
  sConfig.Offset = 0;
 8000b66:	2300      	movs	r3, #0
 8000b68:	61bb      	str	r3, [r7, #24]
  sConfig.OffsetSignedSaturation = DISABLE;
 8000b6a:	2300      	movs	r3, #0
 8000b6c:	777b      	strb	r3, [r7, #29]
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
 8000b6e:	1d3b      	adds	r3, r7, #4
 8000b70:	4619      	mov	r1, r3
 8000b72:	481a      	ldr	r0, [pc, #104]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b74:	f003 f95c 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000b78:	4603      	mov	r3, r0
 8000b7a:	2b00      	cmp	r3, #0
 8000b7c:	d001      	beq.n	8000b82 <MX_ADC2_Init+0xba>
  {
    Error_Handler();
 8000b7e:	f000 fc87 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_4;
 8000b82:	4b19      	ldr	r3, [pc, #100]	@ (8000be8 <MX_ADC2_Init+0x120>)
 8000b84:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_2;
 8000b86:	230c      	movs	r3, #12
 8000b88:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
 8000b8a:	1d3b      	adds	r3, r7, #4
 8000b8c:	4619      	mov	r1, r3
 8000b8e:	4813      	ldr	r0, [pc, #76]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000b90:	f003 f94e 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000b94:	4603      	mov	r3, r0
 8000b96:	2b00      	cmp	r3, #0
 8000b98:	d001      	beq.n	8000b9e <MX_ADC2_Init+0xd6>
  {
    Error_Handler();
 8000b9a:	f000 fc79 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_5;
 8000b9e:	4b13      	ldr	r3, [pc, #76]	@ (8000bec <MX_ADC2_Init+0x124>)
 8000ba0:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_3;
 8000ba2:	2312      	movs	r3, #18
 8000ba4:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
 8000ba6:	1d3b      	adds	r3, r7, #4
 8000ba8:	4619      	mov	r1, r3
 8000baa:	480c      	ldr	r0, [pc, #48]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000bac:	f003 f940 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000bb0:	4603      	mov	r3, r0
 8000bb2:	2b00      	cmp	r3, #0
 8000bb4:	d001      	beq.n	8000bba <MX_ADC2_Init+0xf2>
  {
    Error_Handler();
 8000bb6:	f000 fc6b 	bl	8001490 <Error_Handler>
  }
  /* USER CODE BEGIN ADC2_Init 2 */
  if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK)
 8000bba:	f240 72ff 	movw	r2, #2047	@ 0x7ff
 8000bbe:	f04f 1101 	mov.w	r1, #65537	@ 0x10001
 8000bc2:	4806      	ldr	r0, [pc, #24]	@ (8000bdc <MX_ADC2_Init+0x114>)
 8000bc4:	f003 ff74 	bl	8004ab0 <HAL_ADCEx_Calibration_Start>
 8000bc8:	4603      	mov	r3, r0
 8000bca:	2b00      	cmp	r3, #0
 8000bcc:	d001      	beq.n	8000bd2 <MX_ADC2_Init+0x10a>
  {
	  Error_Handler();
 8000bce:	f000 fc5f 	bl	8001490 <Error_Handler>
  }
  /* USER CODE END ADC2_Init 2 */

}
 8000bd2:	bf00      	nop
 8000bd4:	3720      	adds	r7, #32
 8000bd6:	46bd      	mov	sp, r7
 8000bd8:	bd80      	pop	{r7, pc}
 8000bda:	bf00      	nop
 8000bdc:	240001a4 	.word	0x240001a4
 8000be0:	40022100 	.word	0x40022100
 8000be4:	0c900008 	.word	0x0c900008
 8000be8:	10c00010 	.word	0x10c00010
 8000bec:	14f00020 	.word	0x14f00020

08000bf0 <MX_ADC3_Init>:
  * @brief ADC3 Initialization Function
  * @param None
  * @retval None
  */
static void MX_ADC3_Init(void)
{
 8000bf0:	b580      	push	{r7, lr}
 8000bf2:	b088      	sub	sp, #32
 8000bf4:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN ADC3_Init 0 */

  /* USER CODE END ADC3_Init 0 */

  ADC_ChannelConfTypeDef sConfig = {0};
 8000bf6:	1d3b      	adds	r3, r7, #4
 8000bf8:	2200      	movs	r2, #0
 8000bfa:	601a      	str	r2, [r3, #0]
 8000bfc:	605a      	str	r2, [r3, #4]
 8000bfe:	609a      	str	r2, [r3, #8]
 8000c00:	60da      	str	r2, [r3, #12]
 8000c02:	611a      	str	r2, [r3, #16]
 8000c04:	615a      	str	r2, [r3, #20]
 8000c06:	619a      	str	r2, [r3, #24]

  /* USER CODE END ADC3_Init 1 */

  /** Common config
  */
  hadc3.Instance = ADC3;
 8000c08:	4b4b      	ldr	r3, [pc, #300]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c0a:	4a4c      	ldr	r2, [pc, #304]	@ (8000d3c <MX_ADC3_Init+0x14c>)
 8000c0c:	601a      	str	r2, [r3, #0]
  hadc3.Init.Resolution = ADC_RESOLUTION_16B;
 8000c0e:	4b4a      	ldr	r3, [pc, #296]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c10:	2200      	movs	r2, #0
 8000c12:	609a      	str	r2, [r3, #8]
  hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE;
 8000c14:	4b48      	ldr	r3, [pc, #288]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c16:	2201      	movs	r2, #1
 8000c18:	60da      	str	r2, [r3, #12]
  hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV;
 8000c1a:	4b47      	ldr	r3, [pc, #284]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c1c:	2208      	movs	r2, #8
 8000c1e:	611a      	str	r2, [r3, #16]
  hadc3.Init.LowPowerAutoWait = DISABLE;
 8000c20:	4b45      	ldr	r3, [pc, #276]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c22:	2200      	movs	r2, #0
 8000c24:	751a      	strb	r2, [r3, #20]
  hadc3.Init.ContinuousConvMode = ENABLE;
 8000c26:	4b44      	ldr	r3, [pc, #272]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c28:	2201      	movs	r2, #1
 8000c2a:	755a      	strb	r2, [r3, #21]
  hadc3.Init.NbrOfConversion = 5;
 8000c2c:	4b42      	ldr	r3, [pc, #264]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c2e:	2205      	movs	r2, #5
 8000c30:	619a      	str	r2, [r3, #24]
  hadc3.Init.DiscontinuousConvMode = DISABLE;
 8000c32:	4b41      	ldr	r3, [pc, #260]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c34:	2200      	movs	r2, #0
 8000c36:	771a      	strb	r2, [r3, #28]
  hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO;
 8000c38:	4b3f      	ldr	r3, [pc, #252]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c3a:	f44f 62ac 	mov.w	r2, #1376	@ 0x560
 8000c3e:	625a      	str	r2, [r3, #36]	@ 0x24
  hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
 8000c40:	4b3d      	ldr	r3, [pc, #244]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c42:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 8000c46:	629a      	str	r2, [r3, #40]	@ 0x28
  hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT;
 8000c48:	4b3b      	ldr	r3, [pc, #236]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c4a:	2201      	movs	r2, #1
 8000c4c:	62da      	str	r2, [r3, #44]	@ 0x2c
  hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED;
 8000c4e:	4b3a      	ldr	r3, [pc, #232]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c50:	2200      	movs	r2, #0
 8000c52:	631a      	str	r2, [r3, #48]	@ 0x30
  hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
 8000c54:	4b38      	ldr	r3, [pc, #224]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c56:	2200      	movs	r2, #0
 8000c58:	635a      	str	r2, [r3, #52]	@ 0x34
  hadc3.Init.OversamplingMode = DISABLE;
 8000c5a:	4b37      	ldr	r3, [pc, #220]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c5c:	2200      	movs	r2, #0
 8000c5e:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38
  if (HAL_ADC_Init(&hadc3) != HAL_OK)
 8000c62:	4835      	ldr	r0, [pc, #212]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c64:	f002 fe6a 	bl	800393c <HAL_ADC_Init>
 8000c68:	4603      	mov	r3, r0
 8000c6a:	2b00      	cmp	r3, #0
 8000c6c:	d001      	beq.n	8000c72 <MX_ADC3_Init+0x82>
  {
    Error_Handler();
 8000c6e:	f000 fc0f 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_0;
 8000c72:	2301      	movs	r3, #1
 8000c74:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8000c76:	2306      	movs	r3, #6
 8000c78:	60bb      	str	r3, [r7, #8]
  sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5;
 8000c7a:	2306      	movs	r3, #6
 8000c7c:	60fb      	str	r3, [r7, #12]
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
 8000c7e:	f240 73ff 	movw	r3, #2047	@ 0x7ff
 8000c82:	613b      	str	r3, [r7, #16]
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
 8000c84:	2304      	movs	r3, #4
 8000c86:	617b      	str	r3, [r7, #20]
  sConfig.Offset = 0;
 8000c88:	2300      	movs	r3, #0
 8000c8a:	61bb      	str	r3, [r7, #24]
  sConfig.OffsetSignedSaturation = DISABLE;
 8000c8c:	2300      	movs	r3, #0
 8000c8e:	777b      	strb	r3, [r7, #29]
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8000c90:	1d3b      	adds	r3, r7, #4
 8000c92:	4619      	mov	r1, r3
 8000c94:	4828      	ldr	r0, [pc, #160]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000c96:	f003 f8cb 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000c9a:	4603      	mov	r3, r0
 8000c9c:	2b00      	cmp	r3, #0
 8000c9e:	d001      	beq.n	8000ca4 <MX_ADC3_Init+0xb4>
  {
    Error_Handler();
 8000ca0:	f000 fbf6 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_1;
 8000ca4:	4b26      	ldr	r3, [pc, #152]	@ (8000d40 <MX_ADC3_Init+0x150>)
 8000ca6:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_2;
 8000ca8:	230c      	movs	r3, #12
 8000caa:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8000cac:	1d3b      	adds	r3, r7, #4
 8000cae:	4619      	mov	r1, r3
 8000cb0:	4821      	ldr	r0, [pc, #132]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000cb2:	f003 f8bd 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000cb6:	4603      	mov	r3, r0
 8000cb8:	2b00      	cmp	r3, #0
 8000cba:	d001      	beq.n	8000cc0 <MX_ADC3_Init+0xd0>
  {
    Error_Handler();
 8000cbc:	f000 fbe8 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_10;
 8000cc0:	4b20      	ldr	r3, [pc, #128]	@ (8000d44 <MX_ADC3_Init+0x154>)
 8000cc2:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_3;
 8000cc4:	2312      	movs	r3, #18
 8000cc6:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8000cc8:	1d3b      	adds	r3, r7, #4
 8000cca:	4619      	mov	r1, r3
 8000ccc:	481a      	ldr	r0, [pc, #104]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000cce:	f003 f8af 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000cd2:	4603      	mov	r3, r0
 8000cd4:	2b00      	cmp	r3, #0
 8000cd6:	d001      	beq.n	8000cdc <MX_ADC3_Init+0xec>
  {
    Error_Handler();
 8000cd8:	f000 fbda 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_11;
 8000cdc:	4b1a      	ldr	r3, [pc, #104]	@ (8000d48 <MX_ADC3_Init+0x158>)
 8000cde:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_4;
 8000ce0:	2318      	movs	r3, #24
 8000ce2:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8000ce4:	1d3b      	adds	r3, r7, #4
 8000ce6:	4619      	mov	r1, r3
 8000ce8:	4813      	ldr	r0, [pc, #76]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000cea:	f003 f8a1 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000cee:	4603      	mov	r3, r0
 8000cf0:	2b00      	cmp	r3, #0
 8000cf2:	d001      	beq.n	8000cf8 <MX_ADC3_Init+0x108>
  {
    Error_Handler();
 8000cf4:	f000 fbcc 	bl	8001490 <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_VREFINT;
 8000cf8:	4b14      	ldr	r3, [pc, #80]	@ (8000d4c <MX_ADC3_Init+0x15c>)
 8000cfa:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_5;
 8000cfc:	f44f 7380 	mov.w	r3, #256	@ 0x100
 8000d00:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8000d02:	1d3b      	adds	r3, r7, #4
 8000d04:	4619      	mov	r1, r3
 8000d06:	480c      	ldr	r0, [pc, #48]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000d08:	f003 f892 	bl	8003e30 <HAL_ADC_ConfigChannel>
 8000d0c:	4603      	mov	r3, r0
 8000d0e:	2b00      	cmp	r3, #0
 8000d10:	d001      	beq.n	8000d16 <MX_ADC3_Init+0x126>
  {
    Error_Handler();
 8000d12:	f000 fbbd 	bl	8001490 <Error_Handler>
  }
  /* USER CODE BEGIN ADC3_Init 2 */
  if (HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK)
 8000d16:	f240 72ff 	movw	r2, #2047	@ 0x7ff
 8000d1a:	f04f 1101 	mov.w	r1, #65537	@ 0x10001
 8000d1e:	4806      	ldr	r0, [pc, #24]	@ (8000d38 <MX_ADC3_Init+0x148>)
 8000d20:	f003 fec6 	bl	8004ab0 <HAL_ADCEx_Calibration_Start>
 8000d24:	4603      	mov	r3, r0
 8000d26:	2b00      	cmp	r3, #0
 8000d28:	d001      	beq.n	8000d2e <MX_ADC3_Init+0x13e>
  {
	  Error_Handler();
 8000d2a:	f000 fbb1 	bl	8001490 <Error_Handler>
  }
  /* USER CODE END ADC3_Init 2 */

}
 8000d2e:	bf00      	nop
 8000d30:	3720      	adds	r7, #32
 8000d32:	46bd      	mov	sp, r7
 8000d34:	bd80      	pop	{r7, pc}
 8000d36:	bf00      	nop
 8000d38:	24000208 	.word	0x24000208
 8000d3c:	58026000 	.word	0x58026000
 8000d40:	04300002 	.word	0x04300002
 8000d44:	2a000400 	.word	0x2a000400
 8000d48:	2e300800 	.word	0x2e300800
 8000d4c:	cfb80000 	.word	0xcfb80000

08000d50 <MX_CRC_Init>:
  * @brief CRC Initialization Function
  * @param None
  * @retval None
  */
static void MX_CRC_Init(void)
{
 8000d50:	b580      	push	{r7, lr}
 8000d52:	af00      	add	r7, sp, #0
  /* USER CODE END CRC_Init 0 */

  /* USER CODE BEGIN CRC_Init 1 */

  /* USER CODE END CRC_Init 1 */
  hcrc.Instance = CRC;
 8000d54:	4b11      	ldr	r3, [pc, #68]	@ (8000d9c <MX_CRC_Init+0x4c>)
 8000d56:	4a12      	ldr	r2, [pc, #72]	@ (8000da0 <MX_CRC_Init+0x50>)
 8000d58:	601a      	str	r2, [r3, #0]
  hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE;
 8000d5a:	4b10      	ldr	r3, [pc, #64]	@ (8000d9c <MX_CRC_Init+0x4c>)
 8000d5c:	2201      	movs	r2, #1
 8000d5e:	711a      	strb	r2, [r3, #4]
  hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE;
 8000d60:	4b0e      	ldr	r3, [pc, #56]	@ (8000d9c <MX_CRC_Init+0x4c>)
 8000d62:	2200      	movs	r2, #0
 8000d64:	715a      	strb	r2, [r3, #5]
  hcrc.Init.GeneratingPolynomial = 4129;
 8000d66:	4b0d      	ldr	r3, [pc, #52]	@ (8000d9c <MX_CRC_Init+0x4c>)
 8000d68:	f241 0221 	movw	r2, #4129	@ 0x1021
 8000d6c:	609a      	str	r2, [r3, #8]
  hcrc.Init.CRCLength = CRC_POLYLENGTH_16B;
 8000d6e:	4b0b      	ldr	r3, [pc, #44]	@ (8000d9c <MX_CRC_Init+0x4c>)
 8000d70:	2208      	movs	r2, #8
 8000d72:	60da      	str	r2, [r3, #12]
  hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE;
 8000d74:	4b09      	ldr	r3, [pc, #36]	@ (8000d9c <MX_CRC_Init+0x4c>)
 8000d76:	2200      	movs	r2, #0
 8000d78:	615a      	str	r2, [r3, #20]
  hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE;
 8000d7a:	4b08      	ldr	r3, [pc, #32]	@ (8000d9c <MX_CRC_Init+0x4c>)
 8000d7c:	2200      	movs	r2, #0
 8000d7e:	619a      	str	r2, [r3, #24]
  hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
 8000d80:	4b06      	ldr	r3, [pc, #24]	@ (8000d9c <MX_CRC_Init+0x4c>)
 8000d82:	2201      	movs	r2, #1
 8000d84:	621a      	str	r2, [r3, #32]
  if (HAL_CRC_Init(&hcrc) != HAL_OK)
 8000d86:	4805      	ldr	r0, [pc, #20]	@ (8000d9c <MX_CRC_Init+0x4c>)
 8000d88:	f004 f92c 	bl	8004fe4 <HAL_CRC_Init>
 8000d8c:	4603      	mov	r3, r0
 8000d8e:	2b00      	cmp	r3, #0
 8000d90:	d001      	beq.n	8000d96 <MX_CRC_Init+0x46>
  {
    Error_Handler();
 8000d92:	f000 fb7d 	bl	8001490 <Error_Handler>
  }
  /* USER CODE BEGIN CRC_Init 2 */

  /* USER CODE END CRC_Init 2 */

}
 8000d96:	bf00      	nop
 8000d98:	bd80      	pop	{r7, pc}
 8000d9a:	bf00      	nop
 8000d9c:	240003d4 	.word	0x240003d4
 8000da0:	58024c00 	.word	0x58024c00

08000da4 <MX_RNG_Init>:
  * @brief RNG Initialization Function
  * @param None
  * @retval None
  */
static void MX_RNG_Init(void)
{
 8000da4:	b580      	push	{r7, lr}
 8000da6:	af00      	add	r7, sp, #0
  /* USER CODE END RNG_Init 0 */

  /* USER CODE BEGIN RNG_Init 1 */

  /* USER CODE END RNG_Init 1 */
  hrng.Instance = RNG;
 8000da8:	4b07      	ldr	r3, [pc, #28]	@ (8000dc8 <MX_RNG_Init+0x24>)
 8000daa:	4a08      	ldr	r2, [pc, #32]	@ (8000dcc <MX_RNG_Init+0x28>)
 8000dac:	601a      	str	r2, [r3, #0]
  hrng.Init.ClockErrorDetection = RNG_CED_ENABLE;
 8000dae:	4b06      	ldr	r3, [pc, #24]	@ (8000dc8 <MX_RNG_Init+0x24>)
 8000db0:	2200      	movs	r2, #0
 8000db2:	605a      	str	r2, [r3, #4]
  if (HAL_RNG_Init(&hrng) != HAL_OK)
 8000db4:	4804      	ldr	r0, [pc, #16]	@ (8000dc8 <MX_RNG_Init+0x24>)
 8000db6:	f00b f87f 	bl	800beb8 <HAL_RNG_Init>
 8000dba:	4603      	mov	r3, r0
 8000dbc:	2b00      	cmp	r3, #0
 8000dbe:	d001      	beq.n	8000dc4 <MX_RNG_Init+0x20>
  {
    Error_Handler();
 8000dc0:	f000 fb66 	bl	8001490 <Error_Handler>
  }
  /* USER CODE BEGIN RNG_Init 2 */

  /* USER CODE END RNG_Init 2 */

}
 8000dc4:	bf00      	nop
 8000dc6:	bd80      	pop	{r7, pc}
 8000dc8:	240003f8 	.word	0x240003f8
 8000dcc:	48021800 	.word	0x48021800

08000dd0 <MX_TIM2_Init>:
  * @brief TIM2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_TIM2_Init(void)
{
 8000dd0:	b580      	push	{r7, lr}
 8000dd2:	b088      	sub	sp, #32
 8000dd4:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN TIM2_Init 0 */

  /* USER CODE END TIM2_Init 0 */

  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
 8000dd6:	f107 0310 	add.w	r3, r7, #16
 8000dda:	2200      	movs	r2, #0
 8000ddc:	601a      	str	r2, [r3, #0]
 8000dde:	605a      	str	r2, [r3, #4]
 8000de0:	609a      	str	r2, [r3, #8]
 8000de2:	60da      	str	r2, [r3, #12]
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8000de4:	1d3b      	adds	r3, r7, #4
 8000de6:	2200      	movs	r2, #0
 8000de8:	601a      	str	r2, [r3, #0]
 8000dea:	605a      	str	r2, [r3, #4]
 8000dec:	609a      	str	r2, [r3, #8]

  /* USER CODE BEGIN TIM2_Init 1 */

  /* USER CODE END TIM2_Init 1 */
  htim2.Instance = TIM2;
 8000dee:	4b1e      	ldr	r3, [pc, #120]	@ (8000e68 <MX_TIM2_Init+0x98>)
 8000df0:	f04f 4280 	mov.w	r2, #1073741824	@ 0x40000000
 8000df4:	601a      	str	r2, [r3, #0]
  htim2.Init.Prescaler = 0;
 8000df6:	4b1c      	ldr	r3, [pc, #112]	@ (8000e68 <MX_TIM2_Init+0x98>)
 8000df8:	2200      	movs	r2, #0
 8000dfa:	605a      	str	r2, [r3, #4]
  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
 8000dfc:	4b1a      	ldr	r3, [pc, #104]	@ (8000e68 <MX_TIM2_Init+0x98>)
 8000dfe:	2200      	movs	r2, #0
 8000e00:	609a      	str	r2, [r3, #8]
  htim2.Init.Period = 9999999;
 8000e02:	4b19      	ldr	r3, [pc, #100]	@ (8000e68 <MX_TIM2_Init+0x98>)
 8000e04:	4a19      	ldr	r2, [pc, #100]	@ (8000e6c <MX_TIM2_Init+0x9c>)
 8000e06:	60da      	str	r2, [r3, #12]
  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4;
 8000e08:	4b17      	ldr	r3, [pc, #92]	@ (8000e68 <MX_TIM2_Init+0x98>)
 8000e0a:	f44f 7200 	mov.w	r2, #512	@ 0x200
 8000e0e:	611a      	str	r2, [r3, #16]
  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
 8000e10:	4b15      	ldr	r3, [pc, #84]	@ (8000e68 <MX_TIM2_Init+0x98>)
 8000e12:	2280      	movs	r2, #128	@ 0x80
 8000e14:	619a      	str	r2, [r3, #24]
  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
 8000e16:	4814      	ldr	r0, [pc, #80]	@ (8000e68 <MX_TIM2_Init+0x98>)
 8000e18:	f00b f8b0 	bl	800bf7c <HAL_TIM_Base_Init>
 8000e1c:	4603      	mov	r3, r0
 8000e1e:	2b00      	cmp	r3, #0
 8000e20:	d001      	beq.n	8000e26 <MX_TIM2_Init+0x56>
  {
    Error_Handler();
 8000e22:	f000 fb35 	bl	8001490 <Error_Handler>
  }
  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
 8000e26:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
 8000e2a:	613b      	str	r3, [r7, #16]
  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
 8000e2c:	f107 0310 	add.w	r3, r7, #16
 8000e30:	4619      	mov	r1, r3
 8000e32:	480d      	ldr	r0, [pc, #52]	@ (8000e68 <MX_TIM2_Init+0x98>)
 8000e34:	f00b faea 	bl	800c40c <HAL_TIM_ConfigClockSource>
 8000e38:	4603      	mov	r3, r0
 8000e3a:	2b00      	cmp	r3, #0
 8000e3c:	d001      	beq.n	8000e42 <MX_TIM2_Init+0x72>
  {
    Error_Handler();
 8000e3e:	f000 fb27 	bl	8001490 <Error_Handler>
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
 8000e42:	2320      	movs	r3, #32
 8000e44:	607b      	str	r3, [r7, #4]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE;
 8000e46:	2380      	movs	r3, #128	@ 0x80
 8000e48:	60fb      	str	r3, [r7, #12]
  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
 8000e4a:	1d3b      	adds	r3, r7, #4
 8000e4c:	4619      	mov	r1, r3
 8000e4e:	4806      	ldr	r0, [pc, #24]	@ (8000e68 <MX_TIM2_Init+0x98>)
 8000e50:	f00b fd40 	bl	800c8d4 <HAL_TIMEx_MasterConfigSynchronization>
 8000e54:	4603      	mov	r3, r0
 8000e56:	2b00      	cmp	r3, #0
 8000e58:	d001      	beq.n	8000e5e <MX_TIM2_Init+0x8e>
  {
    Error_Handler();
 8000e5a:	f000 fb19 	bl	8001490 <Error_Handler>
  }
  /* USER CODE BEGIN TIM2_Init 2 */

  /* USER CODE END TIM2_Init 2 */

}
 8000e5e:	bf00      	nop
 8000e60:	3720      	adds	r7, #32
 8000e62:	46bd      	mov	sp, r7
 8000e64:	bd80      	pop	{r7, pc}
 8000e66:	bf00      	nop
 8000e68:	2400040c 	.word	0x2400040c
 8000e6c:	0098967f 	.word	0x0098967f

08000e70 <MX_UART8_Init>:
  * @brief UART8 Initialization Function
  * @param None
  * @retval None
  */
static void MX_UART8_Init(void)
{
 8000e70:	b580      	push	{r7, lr}
 8000e72:	af00      	add	r7, sp, #0
  /* USER CODE END UART8_Init 0 */

  /* USER CODE BEGIN UART8_Init 1 */

  /* USER CODE END UART8_Init 1 */
  huart8.Instance = UART8;
 8000e74:	4b22      	ldr	r3, [pc, #136]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000e76:	4a23      	ldr	r2, [pc, #140]	@ (8000f04 <MX_UART8_Init+0x94>)
 8000e78:	601a      	str	r2, [r3, #0]
  huart8.Init.BaudRate = 115200;
 8000e7a:	4b21      	ldr	r3, [pc, #132]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000e7c:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
 8000e80:	605a      	str	r2, [r3, #4]
  huart8.Init.WordLength = UART_WORDLENGTH_8B;
 8000e82:	4b1f      	ldr	r3, [pc, #124]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000e84:	2200      	movs	r2, #0
 8000e86:	609a      	str	r2, [r3, #8]
  huart8.Init.StopBits = UART_STOPBITS_1;
 8000e88:	4b1d      	ldr	r3, [pc, #116]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000e8a:	2200      	movs	r2, #0
 8000e8c:	60da      	str	r2, [r3, #12]
  huart8.Init.Parity = UART_PARITY_NONE;
 8000e8e:	4b1c      	ldr	r3, [pc, #112]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000e90:	2200      	movs	r2, #0
 8000e92:	611a      	str	r2, [r3, #16]
  huart8.Init.Mode = UART_MODE_TX_RX;
 8000e94:	4b1a      	ldr	r3, [pc, #104]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000e96:	220c      	movs	r2, #12
 8000e98:	615a      	str	r2, [r3, #20]
  huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8000e9a:	4b19      	ldr	r3, [pc, #100]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000e9c:	2200      	movs	r2, #0
 8000e9e:	619a      	str	r2, [r3, #24]
  huart8.Init.OverSampling = UART_OVERSAMPLING_16;
 8000ea0:	4b17      	ldr	r3, [pc, #92]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000ea2:	2200      	movs	r2, #0
 8000ea4:	61da      	str	r2, [r3, #28]
  huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 8000ea6:	4b16      	ldr	r3, [pc, #88]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000ea8:	2200      	movs	r2, #0
 8000eaa:	621a      	str	r2, [r3, #32]
  huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1;
 8000eac:	4b14      	ldr	r3, [pc, #80]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000eae:	2200      	movs	r2, #0
 8000eb0:	625a      	str	r2, [r3, #36]	@ 0x24
  huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 8000eb2:	4b13      	ldr	r3, [pc, #76]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000eb4:	2200      	movs	r2, #0
 8000eb6:	629a      	str	r2, [r3, #40]	@ 0x28
  if (HAL_UART_Init(&huart8) != HAL_OK)
 8000eb8:	4811      	ldr	r0, [pc, #68]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000eba:	f00b fdb7 	bl	800ca2c <HAL_UART_Init>
 8000ebe:	4603      	mov	r3, r0
 8000ec0:	2b00      	cmp	r3, #0
 8000ec2:	d001      	beq.n	8000ec8 <MX_UART8_Init+0x58>
  {
    Error_Handler();
 8000ec4:	f000 fae4 	bl	8001490 <Error_Handler>
  }
  if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
 8000ec8:	2100      	movs	r1, #0
 8000eca:	480d      	ldr	r0, [pc, #52]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000ecc:	f00e fa57 	bl	800f37e <HAL_UARTEx_SetTxFifoThreshold>
 8000ed0:	4603      	mov	r3, r0
 8000ed2:	2b00      	cmp	r3, #0
 8000ed4:	d001      	beq.n	8000eda <MX_UART8_Init+0x6a>
  {
    Error_Handler();
 8000ed6:	f000 fadb 	bl	8001490 <Error_Handler>
  }
  if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
 8000eda:	2100      	movs	r1, #0
 8000edc:	4808      	ldr	r0, [pc, #32]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000ede:	f00e fa8c 	bl	800f3fa <HAL_UARTEx_SetRxFifoThreshold>
 8000ee2:	4603      	mov	r3, r0
 8000ee4:	2b00      	cmp	r3, #0
 8000ee6:	d001      	beq.n	8000eec <MX_UART8_Init+0x7c>
  {
    Error_Handler();
 8000ee8:	f000 fad2 	bl	8001490 <Error_Handler>
  }
  if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK)
 8000eec:	4804      	ldr	r0, [pc, #16]	@ (8000f00 <MX_UART8_Init+0x90>)
 8000eee:	f00e fa0d 	bl	800f30c <HAL_UARTEx_DisableFifoMode>
 8000ef2:	4603      	mov	r3, r0
 8000ef4:	2b00      	cmp	r3, #0
 8000ef6:	d001      	beq.n	8000efc <MX_UART8_Init+0x8c>
  {
    Error_Handler();
 8000ef8:	f000 faca 	bl	8001490 <Error_Handler>
  }
  /* USER CODE BEGIN UART8_Init 2 */

  /* USER CODE END UART8_Init 2 */

}
 8000efc:	bf00      	nop
 8000efe:	bd80      	pop	{r7, pc}
 8000f00:	24000458 	.word	0x24000458
 8000f04:	40007c00 	.word	0x40007c00

08000f08 <MX_USART1_UART_Init>:
  * @brief USART1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART1_UART_Init(void)
{
 8000f08:	b580      	push	{r7, lr}
 8000f0a:	af00      	add	r7, sp, #0
  /* USER CODE END USART1_Init 0 */

  /* USER CODE BEGIN USART1_Init 1 */

  /* USER CODE END USART1_Init 1 */
  huart1.Instance = USART1;
 8000f0c:	4b24      	ldr	r3, [pc, #144]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f0e:	4a25      	ldr	r2, [pc, #148]	@ (8000fa4 <MX_USART1_UART_Init+0x9c>)
 8000f10:	601a      	str	r2, [r3, #0]
  huart1.Init.BaudRate = 115200;
 8000f12:	4b23      	ldr	r3, [pc, #140]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f14:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
 8000f18:	605a      	str	r2, [r3, #4]
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 8000f1a:	4b21      	ldr	r3, [pc, #132]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f1c:	2200      	movs	r2, #0
 8000f1e:	609a      	str	r2, [r3, #8]
  huart1.Init.StopBits = UART_STOPBITS_1;
 8000f20:	4b1f      	ldr	r3, [pc, #124]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f22:	2200      	movs	r2, #0
 8000f24:	60da      	str	r2, [r3, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 8000f26:	4b1e      	ldr	r3, [pc, #120]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f28:	2200      	movs	r2, #0
 8000f2a:	611a      	str	r2, [r3, #16]
  huart1.Init.Mode = UART_MODE_TX_RX;
 8000f2c:	4b1c      	ldr	r3, [pc, #112]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f2e:	220c      	movs	r2, #12
 8000f30:	615a      	str	r2, [r3, #20]
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8000f32:	4b1b      	ldr	r3, [pc, #108]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f34:	2200      	movs	r2, #0
 8000f36:	619a      	str	r2, [r3, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 8000f38:	4b19      	ldr	r3, [pc, #100]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f3a:	2200      	movs	r2, #0
 8000f3c:	61da      	str	r2, [r3, #28]
  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 8000f3e:	4b18      	ldr	r3, [pc, #96]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f40:	2200      	movs	r2, #0
 8000f42:	621a      	str	r2, [r3, #32]
  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
 8000f44:	4b16      	ldr	r3, [pc, #88]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f46:	2200      	movs	r2, #0
 8000f48:	625a      	str	r2, [r3, #36]	@ 0x24
  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXINVERT_INIT;
 8000f4a:	4b15      	ldr	r3, [pc, #84]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f4c:	2202      	movs	r2, #2
 8000f4e:	629a      	str	r2, [r3, #40]	@ 0x28
  huart1.AdvancedInit.RxPinLevelInvert = UART_ADVFEATURE_RXINV_ENABLE;
 8000f50:	4b13      	ldr	r3, [pc, #76]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f52:	f44f 3280 	mov.w	r2, #65536	@ 0x10000
 8000f56:	631a      	str	r2, [r3, #48]	@ 0x30
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8000f58:	4811      	ldr	r0, [pc, #68]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f5a:	f00b fd67 	bl	800ca2c <HAL_UART_Init>
 8000f5e:	4603      	mov	r3, r0
 8000f60:	2b00      	cmp	r3, #0
 8000f62:	d001      	beq.n	8000f68 <MX_USART1_UART_Init+0x60>
  {
    Error_Handler();
 8000f64:	f000 fa94 	bl	8001490 <Error_Handler>
  }
  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
 8000f68:	2100      	movs	r1, #0
 8000f6a:	480d      	ldr	r0, [pc, #52]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f6c:	f00e fa07 	bl	800f37e <HAL_UARTEx_SetTxFifoThreshold>
 8000f70:	4603      	mov	r3, r0
 8000f72:	2b00      	cmp	r3, #0
 8000f74:	d001      	beq.n	8000f7a <MX_USART1_UART_Init+0x72>
  {
    Error_Handler();
 8000f76:	f000 fa8b 	bl	8001490 <Error_Handler>
  }
  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
 8000f7a:	2100      	movs	r1, #0
 8000f7c:	4808      	ldr	r0, [pc, #32]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f7e:	f00e fa3c 	bl	800f3fa <HAL_UARTEx_SetRxFifoThreshold>
 8000f82:	4603      	mov	r3, r0
 8000f84:	2b00      	cmp	r3, #0
 8000f86:	d001      	beq.n	8000f8c <MX_USART1_UART_Init+0x84>
  {
    Error_Handler();
 8000f88:	f000 fa82 	bl	8001490 <Error_Handler>
  }
  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
 8000f8c:	4804      	ldr	r0, [pc, #16]	@ (8000fa0 <MX_USART1_UART_Init+0x98>)
 8000f8e:	f00e f9bd 	bl	800f30c <HAL_UARTEx_DisableFifoMode>
 8000f92:	4603      	mov	r3, r0
 8000f94:	2b00      	cmp	r3, #0
 8000f96:	d001      	beq.n	8000f9c <MX_USART1_UART_Init+0x94>
  {
    Error_Handler();
 8000f98:	f000 fa7a 	bl	8001490 <Error_Handler>
  }
  /* USER CODE BEGIN USART1_Init 2 */

  /* USER CODE END USART1_Init 2 */

}
 8000f9c:	bf00      	nop
 8000f9e:	bd80      	pop	{r7, pc}
 8000fa0:	240004ec 	.word	0x240004ec
 8000fa4:	40011000 	.word	0x40011000

08000fa8 <MX_DMA_Init>:

/**
  * Enable DMA controller clock
  */
static void MX_DMA_Init(void)
{
 8000fa8:	b580      	push	{r7, lr}
 8000faa:	b082      	sub	sp, #8
 8000fac:	af00      	add	r7, sp, #0

  /* DMA controller clock enable */
  __HAL_RCC_DMA1_CLK_ENABLE();
 8000fae:	4b15      	ldr	r3, [pc, #84]	@ (8001004 <MX_DMA_Init+0x5c>)
 8000fb0:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 8000fb4:	4a13      	ldr	r2, [pc, #76]	@ (8001004 <MX_DMA_Init+0x5c>)
 8000fb6:	f043 0301 	orr.w	r3, r3, #1
 8000fba:	f8c2 30d8 	str.w	r3, [r2, #216]	@ 0xd8
 8000fbe:	4b11      	ldr	r3, [pc, #68]	@ (8001004 <MX_DMA_Init+0x5c>)
 8000fc0:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 8000fc4:	f003 0301 	and.w	r3, r3, #1
 8000fc8:	607b      	str	r3, [r7, #4]
 8000fca:	687b      	ldr	r3, [r7, #4]

  /* DMA interrupt init */
  /* DMA1_Stream0_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
 8000fcc:	2200      	movs	r2, #0
 8000fce:	2105      	movs	r1, #5
 8000fd0:	200b      	movs	r0, #11
 8000fd2:	f003 ff67 	bl	8004ea4 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
 8000fd6:	200b      	movs	r0, #11
 8000fd8:	f003 ff7e 	bl	8004ed8 <HAL_NVIC_EnableIRQ>
  /* DMA1_Stream1_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0);
 8000fdc:	2200      	movs	r2, #0
 8000fde:	2105      	movs	r1, #5
 8000fe0:	200c      	movs	r0, #12
 8000fe2:	f003 ff5f 	bl	8004ea4 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
 8000fe6:	200c      	movs	r0, #12
 8000fe8:	f003 ff76 	bl	8004ed8 <HAL_NVIC_EnableIRQ>
  /* DMA1_Stream2_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0);
 8000fec:	2200      	movs	r2, #0
 8000fee:	2105      	movs	r1, #5
 8000ff0:	200d      	movs	r0, #13
 8000ff2:	f003 ff57 	bl	8004ea4 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
 8000ff6:	200d      	movs	r0, #13
 8000ff8:	f003 ff6e 	bl	8004ed8 <HAL_NVIC_EnableIRQ>

}
 8000ffc:	bf00      	nop
 8000ffe:	3708      	adds	r7, #8
 8001000:	46bd      	mov	sp, r7
 8001002:	bd80      	pop	{r7, pc}
 8001004:	58024400 	.word	0x58024400

08001008 <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 8001008:	b580      	push	{r7, lr}
 800100a:	b08c      	sub	sp, #48	@ 0x30
 800100c:	af00      	add	r7, sp, #0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 800100e:	f107 031c 	add.w	r3, r7, #28
 8001012:	2200      	movs	r2, #0
 8001014:	601a      	str	r2, [r3, #0]
 8001016:	605a      	str	r2, [r3, #4]
 8001018:	609a      	str	r2, [r3, #8]
 800101a:	60da      	str	r2, [r3, #12]
 800101c:	611a      	str	r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOH_CLK_ENABLE();
 800101e:	4b49      	ldr	r3, [pc, #292]	@ (8001144 <MX_GPIO_Init+0x13c>)
 8001020:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001024:	4a47      	ldr	r2, [pc, #284]	@ (8001144 <MX_GPIO_Init+0x13c>)
 8001026:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 800102a:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 800102e:	4b45      	ldr	r3, [pc, #276]	@ (8001144 <MX_GPIO_Init+0x13c>)
 8001030:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001034:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8001038:	61bb      	str	r3, [r7, #24]
 800103a:	69bb      	ldr	r3, [r7, #24]
  __HAL_RCC_GPIOC_CLK_ENABLE();
 800103c:	4b41      	ldr	r3, [pc, #260]	@ (8001144 <MX_GPIO_Init+0x13c>)
 800103e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001042:	4a40      	ldr	r2, [pc, #256]	@ (8001144 <MX_GPIO_Init+0x13c>)
 8001044:	f043 0304 	orr.w	r3, r3, #4
 8001048:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 800104c:	4b3d      	ldr	r3, [pc, #244]	@ (8001144 <MX_GPIO_Init+0x13c>)
 800104e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001052:	f003 0304 	and.w	r3, r3, #4
 8001056:	617b      	str	r3, [r7, #20]
 8001058:	697b      	ldr	r3, [r7, #20]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 800105a:	4b3a      	ldr	r3, [pc, #232]	@ (8001144 <MX_GPIO_Init+0x13c>)
 800105c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001060:	4a38      	ldr	r2, [pc, #224]	@ (8001144 <MX_GPIO_Init+0x13c>)
 8001062:	f043 0301 	orr.w	r3, r3, #1
 8001066:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 800106a:	4b36      	ldr	r3, [pc, #216]	@ (8001144 <MX_GPIO_Init+0x13c>)
 800106c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001070:	f003 0301 	and.w	r3, r3, #1
 8001074:	613b      	str	r3, [r7, #16]
 8001076:	693b      	ldr	r3, [r7, #16]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8001078:	4b32      	ldr	r3, [pc, #200]	@ (8001144 <MX_GPIO_Init+0x13c>)
 800107a:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800107e:	4a31      	ldr	r2, [pc, #196]	@ (8001144 <MX_GPIO_Init+0x13c>)
 8001080:	f043 0302 	orr.w	r3, r3, #2
 8001084:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8001088:	4b2e      	ldr	r3, [pc, #184]	@ (8001144 <MX_GPIO_Init+0x13c>)
 800108a:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800108e:	f003 0302 	and.w	r3, r3, #2
 8001092:	60fb      	str	r3, [r7, #12]
 8001094:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_GPIOE_CLK_ENABLE();
 8001096:	4b2b      	ldr	r3, [pc, #172]	@ (8001144 <MX_GPIO_Init+0x13c>)
 8001098:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800109c:	4a29      	ldr	r2, [pc, #164]	@ (8001144 <MX_GPIO_Init+0x13c>)
 800109e:	f043 0310 	orr.w	r3, r3, #16
 80010a2:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80010a6:	4b27      	ldr	r3, [pc, #156]	@ (8001144 <MX_GPIO_Init+0x13c>)
 80010a8:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80010ac:	f003 0310 	and.w	r3, r3, #16
 80010b0:	60bb      	str	r3, [r7, #8]
 80010b2:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_GPIOD_CLK_ENABLE();
 80010b4:	4b23      	ldr	r3, [pc, #140]	@ (8001144 <MX_GPIO_Init+0x13c>)
 80010b6:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80010ba:	4a22      	ldr	r2, [pc, #136]	@ (8001144 <MX_GPIO_Init+0x13c>)
 80010bc:	f043 0308 	orr.w	r3, r3, #8
 80010c0:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80010c4:	4b1f      	ldr	r3, [pc, #124]	@ (8001144 <MX_GPIO_Init+0x13c>)
 80010c6:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80010ca:	f003 0308 	and.w	r3, r3, #8
 80010ce:	607b      	str	r3, [r7, #4]
 80010d0:	687b      	ldr	r3, [r7, #4]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
 80010d2:	2200      	movs	r2, #0
 80010d4:	f24e 7180 	movw	r1, #59264	@ 0xe780
 80010d8:	481b      	ldr	r0, [pc, #108]	@ (8001148 <MX_GPIO_Init+0x140>)
 80010da:	f007 f975 	bl	80083c8 <HAL_GPIO_WritePin>
                          |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15, GPIO_PIN_RESET);

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET);
 80010de:	2200      	movs	r2, #0
 80010e0:	21f0      	movs	r1, #240	@ 0xf0
 80010e2:	481a      	ldr	r0, [pc, #104]	@ (800114c <MX_GPIO_Init+0x144>)
 80010e4:	f007 f970 	bl	80083c8 <HAL_GPIO_WritePin>

  /*Configure GPIO pins : PE7 PE8 PE9 PE10
                           PE13 PE14 PE15 */
  GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
 80010e8:	f24e 7380 	movw	r3, #59264	@ 0xe780
 80010ec:	61fb      	str	r3, [r7, #28]
                          |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80010ee:	2301      	movs	r3, #1
 80010f0:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80010f2:	2300      	movs	r3, #0
 80010f4:	627b      	str	r3, [r7, #36]	@ 0x24
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80010f6:	2300      	movs	r3, #0
 80010f8:	62bb      	str	r3, [r7, #40]	@ 0x28
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 80010fa:	f107 031c 	add.w	r3, r7, #28
 80010fe:	4619      	mov	r1, r3
 8001100:	4811      	ldr	r0, [pc, #68]	@ (8001148 <MX_GPIO_Init+0x140>)
 8001102:	f006 ffb1 	bl	8008068 <HAL_GPIO_Init>

  /*Configure GPIO pin : PD3 */
  GPIO_InitStruct.Pin = GPIO_PIN_3;
 8001106:	2308      	movs	r3, #8
 8001108:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 800110a:	2300      	movs	r3, #0
 800110c:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 800110e:	2300      	movs	r3, #0
 8001110:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8001112:	f107 031c 	add.w	r3, r7, #28
 8001116:	4619      	mov	r1, r3
 8001118:	480c      	ldr	r0, [pc, #48]	@ (800114c <MX_GPIO_Init+0x144>)
 800111a:	f006 ffa5 	bl	8008068 <HAL_GPIO_Init>

  /*Configure GPIO pins : PD4 PD5 PD6 PD7 */
  GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
 800111e:	23f0      	movs	r3, #240	@ 0xf0
 8001120:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8001122:	2301      	movs	r3, #1
 8001124:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001126:	2300      	movs	r3, #0
 8001128:	627b      	str	r3, [r7, #36]	@ 0x24
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 800112a:	2300      	movs	r3, #0
 800112c:	62bb      	str	r3, [r7, #40]	@ 0x28
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 800112e:	f107 031c 	add.w	r3, r7, #28
 8001132:	4619      	mov	r1, r3
 8001134:	4805      	ldr	r0, [pc, #20]	@ (800114c <MX_GPIO_Init+0x144>)
 8001136:	f006 ff97 	bl	8008068 <HAL_GPIO_Init>

/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
 800113a:	bf00      	nop
 800113c:	3730      	adds	r7, #48	@ 0x30
 800113e:	46bd      	mov	sp, r7
 8001140:	bd80      	pop	{r7, pc}
 8001142:	bf00      	nop
 8001144:	58024400 	.word	0x58024400
 8001148:	58021000 	.word	0x58021000
 800114c:	58020c00 	.word	0x58020c00

08001150 <HAL_ADC_ConvCpltCallback>:

/* USER CODE BEGIN 4 */
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
{
 8001150:	b580      	push	{r7, lr}
 8001152:	b08e      	sub	sp, #56	@ 0x38
 8001154:	af00      	add	r7, sp, #0
 8001156:	6078      	str	r0, [r7, #4]
	if(hadc->Instance == ADC1)
 8001158:	687b      	ldr	r3, [r7, #4]
 800115a:	681b      	ldr	r3, [r3, #0]
 800115c:	4a65      	ldr	r2, [pc, #404]	@ (80012f4 <HAL_ADC_ConvCpltCallback+0x1a4>)
 800115e:	4293      	cmp	r3, r2
 8001160:	d13f      	bne.n	80011e2 <HAL_ADC_ConvCpltCallback+0x92>
	{
		DbgLEDToggle(DBG_LED4);
 8001162:	2080      	movs	r0, #128	@ 0x80
 8001164:	f000 fd62 	bl	8001c2c <DbgLEDToggle>
		SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc1Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE);
 8001168:	4b63      	ldr	r3, [pc, #396]	@ (80012f8 <HAL_ADC_ConvCpltCallback+0x1a8>)
 800116a:	f023 031f 	bic.w	r3, r3, #31
 800116e:	637b      	str	r3, [r7, #52]	@ 0x34
 8001170:	2320      	movs	r3, #32
 8001172:	633b      	str	r3, [r7, #48]	@ 0x30
  \param[in]   dsize   size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
{
  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
    if ( dsize > 0 ) { 
 8001174:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8001176:	2b00      	cmp	r3, #0
 8001178:	dd1d      	ble.n	80011b6 <HAL_ADC_ConvCpltCallback+0x66>
       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
 800117a:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800117c:	f003 021f 	and.w	r2, r3, #31
 8001180:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8001182:	4413      	add	r3, r2
 8001184:	62fb      	str	r3, [r7, #44]	@ 0x2c
      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
 8001186:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8001188:	62bb      	str	r3, [r7, #40]	@ 0x28
  __ASM volatile ("dsb 0xF":::"memory");
 800118a:	f3bf 8f4f 	dsb	sy
}
 800118e:	bf00      	nop
    
      __DSB();

      do {
        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
 8001190:	4a5a      	ldr	r2, [pc, #360]	@ (80012fc <HAL_ADC_ConvCpltCallback+0x1ac>)
 8001192:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8001194:	f8c2 325c 	str.w	r3, [r2, #604]	@ 0x25c
        op_addr += __SCB_DCACHE_LINE_SIZE;
 8001198:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800119a:	3320      	adds	r3, #32
 800119c:	62bb      	str	r3, [r7, #40]	@ 0x28
        op_size -= __SCB_DCACHE_LINE_SIZE;
 800119e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80011a0:	3b20      	subs	r3, #32
 80011a2:	62fb      	str	r3, [r7, #44]	@ 0x2c
      } while ( op_size > 0 );
 80011a4:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80011a6:	2b00      	cmp	r3, #0
 80011a8:	dcf2      	bgt.n	8001190 <HAL_ADC_ConvCpltCallback+0x40>
  __ASM volatile ("dsb 0xF":::"memory");
 80011aa:	f3bf 8f4f 	dsb	sy
}
 80011ae:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 80011b0:	f3bf 8f6f 	isb	sy
}
 80011b4:	bf00      	nop

      __DSB();
      __ISB();
    }
  #endif
}
 80011b6:	bf00      	nop
		if(adc1MeasDataQueue != NULL)
 80011b8:	4b51      	ldr	r3, [pc, #324]	@ (8001300 <HAL_ADC_ConvCpltCallback+0x1b0>)
 80011ba:	681b      	ldr	r3, [r3, #0]
 80011bc:	2b00      	cmp	r3, #0
 80011be:	d006      	beq.n	80011ce <HAL_ADC_ConvCpltCallback+0x7e>
		{
			osMessageQueuePut(adc1MeasDataQueue, &adc1Data, 0, 0);
 80011c0:	4b4f      	ldr	r3, [pc, #316]	@ (8001300 <HAL_ADC_ConvCpltCallback+0x1b0>)
 80011c2:	6818      	ldr	r0, [r3, #0]
 80011c4:	2300      	movs	r3, #0
 80011c6:	2200      	movs	r2, #0
 80011c8:	494b      	ldr	r1, [pc, #300]	@ (80012f8 <HAL_ADC_ConvCpltCallback+0x1a8>)
 80011ca:	f00e fcb1 	bl	800fb30 <osMessageQueuePut>
		}
		if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK)
 80011ce:	2206      	movs	r2, #6
 80011d0:	4949      	ldr	r1, [pc, #292]	@ (80012f8 <HAL_ADC_ConvCpltCallback+0x1a8>)
 80011d2:	484c      	ldr	r0, [pc, #304]	@ (8001304 <HAL_ADC_ConvCpltCallback+0x1b4>)
 80011d4:	f002 fd54 	bl	8003c80 <HAL_ADC_Start_DMA>
 80011d8:	4603      	mov	r3, r0
 80011da:	2b00      	cmp	r3, #0
 80011dc:	d001      	beq.n	80011e2 <HAL_ADC_ConvCpltCallback+0x92>
		{
		  Error_Handler();
 80011de:	f000 f957 	bl	8001490 <Error_Handler>
		}
	}
	if(hadc->Instance == ADC2)
 80011e2:	687b      	ldr	r3, [r7, #4]
 80011e4:	681b      	ldr	r3, [r3, #0]
 80011e6:	4a48      	ldr	r2, [pc, #288]	@ (8001308 <HAL_ADC_ConvCpltCallback+0x1b8>)
 80011e8:	4293      	cmp	r3, r2
 80011ea:	d13c      	bne.n	8001266 <HAL_ADC_ConvCpltCallback+0x116>
	{
		SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc2Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE);
 80011ec:	4b47      	ldr	r3, [pc, #284]	@ (800130c <HAL_ADC_ConvCpltCallback+0x1bc>)
 80011ee:	f023 031f 	bic.w	r3, r3, #31
 80011f2:	627b      	str	r3, [r7, #36]	@ 0x24
 80011f4:	2320      	movs	r3, #32
 80011f6:	623b      	str	r3, [r7, #32]
    if ( dsize > 0 ) { 
 80011f8:	6a3b      	ldr	r3, [r7, #32]
 80011fa:	2b00      	cmp	r3, #0
 80011fc:	dd1d      	ble.n	800123a <HAL_ADC_ConvCpltCallback+0xea>
       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
 80011fe:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8001200:	f003 021f 	and.w	r2, r3, #31
 8001204:	6a3b      	ldr	r3, [r7, #32]
 8001206:	4413      	add	r3, r2
 8001208:	61fb      	str	r3, [r7, #28]
      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
 800120a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800120c:	61bb      	str	r3, [r7, #24]
  __ASM volatile ("dsb 0xF":::"memory");
 800120e:	f3bf 8f4f 	dsb	sy
}
 8001212:	bf00      	nop
        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
 8001214:	4a39      	ldr	r2, [pc, #228]	@ (80012fc <HAL_ADC_ConvCpltCallback+0x1ac>)
 8001216:	69bb      	ldr	r3, [r7, #24]
 8001218:	f8c2 325c 	str.w	r3, [r2, #604]	@ 0x25c
        op_addr += __SCB_DCACHE_LINE_SIZE;
 800121c:	69bb      	ldr	r3, [r7, #24]
 800121e:	3320      	adds	r3, #32
 8001220:	61bb      	str	r3, [r7, #24]
        op_size -= __SCB_DCACHE_LINE_SIZE;
 8001222:	69fb      	ldr	r3, [r7, #28]
 8001224:	3b20      	subs	r3, #32
 8001226:	61fb      	str	r3, [r7, #28]
      } while ( op_size > 0 );
 8001228:	69fb      	ldr	r3, [r7, #28]
 800122a:	2b00      	cmp	r3, #0
 800122c:	dcf2      	bgt.n	8001214 <HAL_ADC_ConvCpltCallback+0xc4>
  __ASM volatile ("dsb 0xF":::"memory");
 800122e:	f3bf 8f4f 	dsb	sy
}
 8001232:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 8001234:	f3bf 8f6f 	isb	sy
}
 8001238:	bf00      	nop
}
 800123a:	bf00      	nop
		if(adc2MeasDataQueue != NULL)
 800123c:	4b34      	ldr	r3, [pc, #208]	@ (8001310 <HAL_ADC_ConvCpltCallback+0x1c0>)
 800123e:	681b      	ldr	r3, [r3, #0]
 8001240:	2b00      	cmp	r3, #0
 8001242:	d006      	beq.n	8001252 <HAL_ADC_ConvCpltCallback+0x102>
		{
			osMessageQueuePut(adc2MeasDataQueue, &adc2Data, 0, 0);
 8001244:	4b32      	ldr	r3, [pc, #200]	@ (8001310 <HAL_ADC_ConvCpltCallback+0x1c0>)
 8001246:	6818      	ldr	r0, [r3, #0]
 8001248:	2300      	movs	r3, #0
 800124a:	2200      	movs	r2, #0
 800124c:	492f      	ldr	r1, [pc, #188]	@ (800130c <HAL_ADC_ConvCpltCallback+0x1bc>)
 800124e:	f00e fc6f 	bl	800fb30 <osMessageQueuePut>
		}
		if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK)
 8001252:	2203      	movs	r2, #3
 8001254:	492d      	ldr	r1, [pc, #180]	@ (800130c <HAL_ADC_ConvCpltCallback+0x1bc>)
 8001256:	482f      	ldr	r0, [pc, #188]	@ (8001314 <HAL_ADC_ConvCpltCallback+0x1c4>)
 8001258:	f002 fd12 	bl	8003c80 <HAL_ADC_Start_DMA>
 800125c:	4603      	mov	r3, r0
 800125e:	2b00      	cmp	r3, #0
 8001260:	d001      	beq.n	8001266 <HAL_ADC_ConvCpltCallback+0x116>
		{
		  Error_Handler();
 8001262:	f000 f915 	bl	8001490 <Error_Handler>
		}
	}
	if(hadc->Instance == ADC3)
 8001266:	687b      	ldr	r3, [r7, #4]
 8001268:	681b      	ldr	r3, [r3, #0]
 800126a:	4a2b      	ldr	r2, [pc, #172]	@ (8001318 <HAL_ADC_ConvCpltCallback+0x1c8>)
 800126c:	4293      	cmp	r3, r2
 800126e:	d13c      	bne.n	80012ea <HAL_ADC_ConvCpltCallback+0x19a>
	{
		SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc3Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE);
 8001270:	4b2a      	ldr	r3, [pc, #168]	@ (800131c <HAL_ADC_ConvCpltCallback+0x1cc>)
 8001272:	f023 031f 	bic.w	r3, r3, #31
 8001276:	617b      	str	r3, [r7, #20]
 8001278:	2320      	movs	r3, #32
 800127a:	613b      	str	r3, [r7, #16]
    if ( dsize > 0 ) { 
 800127c:	693b      	ldr	r3, [r7, #16]
 800127e:	2b00      	cmp	r3, #0
 8001280:	dd1d      	ble.n	80012be <HAL_ADC_ConvCpltCallback+0x16e>
       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
 8001282:	697b      	ldr	r3, [r7, #20]
 8001284:	f003 021f 	and.w	r2, r3, #31
 8001288:	693b      	ldr	r3, [r7, #16]
 800128a:	4413      	add	r3, r2
 800128c:	60fb      	str	r3, [r7, #12]
      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
 800128e:	697b      	ldr	r3, [r7, #20]
 8001290:	60bb      	str	r3, [r7, #8]
  __ASM volatile ("dsb 0xF":::"memory");
 8001292:	f3bf 8f4f 	dsb	sy
}
 8001296:	bf00      	nop
        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
 8001298:	4a18      	ldr	r2, [pc, #96]	@ (80012fc <HAL_ADC_ConvCpltCallback+0x1ac>)
 800129a:	68bb      	ldr	r3, [r7, #8]
 800129c:	f8c2 325c 	str.w	r3, [r2, #604]	@ 0x25c
        op_addr += __SCB_DCACHE_LINE_SIZE;
 80012a0:	68bb      	ldr	r3, [r7, #8]
 80012a2:	3320      	adds	r3, #32
 80012a4:	60bb      	str	r3, [r7, #8]
        op_size -= __SCB_DCACHE_LINE_SIZE;
 80012a6:	68fb      	ldr	r3, [r7, #12]
 80012a8:	3b20      	subs	r3, #32
 80012aa:	60fb      	str	r3, [r7, #12]
      } while ( op_size > 0 );
 80012ac:	68fb      	ldr	r3, [r7, #12]
 80012ae:	2b00      	cmp	r3, #0
 80012b0:	dcf2      	bgt.n	8001298 <HAL_ADC_ConvCpltCallback+0x148>
  __ASM volatile ("dsb 0xF":::"memory");
 80012b2:	f3bf 8f4f 	dsb	sy
}
 80012b6:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 80012b8:	f3bf 8f6f 	isb	sy
}
 80012bc:	bf00      	nop
}
 80012be:	bf00      	nop
		if(adc3MeasDataQueue != NULL)
 80012c0:	4b17      	ldr	r3, [pc, #92]	@ (8001320 <HAL_ADC_ConvCpltCallback+0x1d0>)
 80012c2:	681b      	ldr	r3, [r3, #0]
 80012c4:	2b00      	cmp	r3, #0
 80012c6:	d006      	beq.n	80012d6 <HAL_ADC_ConvCpltCallback+0x186>
		{
			osMessageQueuePut(adc3MeasDataQueue, &adc3Data, 0, 0);
 80012c8:	4b15      	ldr	r3, [pc, #84]	@ (8001320 <HAL_ADC_ConvCpltCallback+0x1d0>)
 80012ca:	6818      	ldr	r0, [r3, #0]
 80012cc:	2300      	movs	r3, #0
 80012ce:	2200      	movs	r2, #0
 80012d0:	4912      	ldr	r1, [pc, #72]	@ (800131c <HAL_ADC_ConvCpltCallback+0x1cc>)
 80012d2:	f00e fc2d 	bl	800fb30 <osMessageQueuePut>
		}
		if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK)
 80012d6:	2205      	movs	r2, #5
 80012d8:	4910      	ldr	r1, [pc, #64]	@ (800131c <HAL_ADC_ConvCpltCallback+0x1cc>)
 80012da:	4812      	ldr	r0, [pc, #72]	@ (8001324 <HAL_ADC_ConvCpltCallback+0x1d4>)
 80012dc:	f002 fcd0 	bl	8003c80 <HAL_ADC_Start_DMA>
 80012e0:	4603      	mov	r3, r0
 80012e2:	2b00      	cmp	r3, #0
 80012e4:	d001      	beq.n	80012ea <HAL_ADC_ConvCpltCallback+0x19a>
		{
		  Error_Handler();
 80012e6:	f000 f8d3 	bl	8001490 <Error_Handler>
		}
	}
}
 80012ea:	bf00      	nop
 80012ec:	3738      	adds	r7, #56	@ 0x38
 80012ee:	46bd      	mov	sp, r7
 80012f0:	bd80      	pop	{r7, pc}
 80012f2:	bf00      	nop
 80012f4:	40022000 	.word	0x40022000
 80012f8:	240000e0 	.word	0x240000e0
 80012fc:	e000ed00 	.word	0xe000ed00
 8001300:	24000590 	.word	0x24000590
 8001304:	24000140 	.word	0x24000140
 8001308:	40022100 	.word	0x40022100
 800130c:	24000100 	.word	0x24000100
 8001310:	24000594 	.word	0x24000594
 8001314:	240001a4 	.word	0x240001a4
 8001318:	58026000 	.word	0x58026000
 800131c:	24000120 	.word	0x24000120
 8001320:	24000598 	.word	0x24000598
 8001324:	24000208 	.word	0x24000208

08001328 <StartDefaultTask>:
  * @param  argument: Not used
  * @retval None
  */
/* USER CODE END Header_StartDefaultTask */
void StartDefaultTask(void *argument)
{
 8001328:	b580      	push	{r7, lr}
 800132a:	b082      	sub	sp, #8
 800132c:	af00      	add	r7, sp, #0
 800132e:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN 5 */
  SelectCurrentSensorGain(CurrentSensorL1, csGain3);
 8001330:	2102      	movs	r1, #2
 8001332:	2000      	movs	r0, #0
 8001334:	f000 fc98 	bl	8001c68 <SelectCurrentSensorGain>
  SelectCurrentSensorGain(CurrentSensorL2, csGain3);
 8001338:	2102      	movs	r1, #2
 800133a:	2001      	movs	r0, #1
 800133c:	f000 fc94 	bl	8001c68 <SelectCurrentSensorGain>
  SelectCurrentSensorGain(CurrentSensorL3, csGain3);
 8001340:	2102      	movs	r1, #2
 8001342:	2002      	movs	r0, #2
 8001344:	f000 fc90 	bl	8001c68 <SelectCurrentSensorGain>
  EnableCurrentSensors();
 8001348:	f000 fc82 	bl	8001c50 <EnableCurrentSensors>
  osDelay(pdMS_TO_TICKS(1000));
 800134c:	f44f 707a 	mov.w	r0, #1000	@ 0x3e8
 8001350:	f00e fa51 	bl	800f7f6 <osDelay>
  if(HAL_TIM_Base_Start(&htim2) != HAL_OK)
 8001354:	4815      	ldr	r0, [pc, #84]	@ (80013ac <StartDefaultTask+0x84>)
 8001356:	f00a fe69 	bl	800c02c <HAL_TIM_Base_Start>
 800135a:	4603      	mov	r3, r0
 800135c:	2b00      	cmp	r3, #0
 800135e:	d001      	beq.n	8001364 <StartDefaultTask+0x3c>
  {
	  Error_Handler();
 8001360:	f000 f896 	bl	8001490 <Error_Handler>
  }
//  if(HAL_ADC_Start_IT(&hadc1) != HAL_OK)
//  {
//	  Error_Handler();
//  }
  if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK)
 8001364:	2206      	movs	r2, #6
 8001366:	4912      	ldr	r1, [pc, #72]	@ (80013b0 <StartDefaultTask+0x88>)
 8001368:	4812      	ldr	r0, [pc, #72]	@ (80013b4 <StartDefaultTask+0x8c>)
 800136a:	f002 fc89 	bl	8003c80 <HAL_ADC_Start_DMA>
 800136e:	4603      	mov	r3, r0
 8001370:	2b00      	cmp	r3, #0
 8001372:	d001      	beq.n	8001378 <StartDefaultTask+0x50>
  {
	  Error_Handler();
 8001374:	f000 f88c 	bl	8001490 <Error_Handler>
  }
  if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK)
 8001378:	2203      	movs	r2, #3
 800137a:	490f      	ldr	r1, [pc, #60]	@ (80013b8 <StartDefaultTask+0x90>)
 800137c:	480f      	ldr	r0, [pc, #60]	@ (80013bc <StartDefaultTask+0x94>)
 800137e:	f002 fc7f 	bl	8003c80 <HAL_ADC_Start_DMA>
 8001382:	4603      	mov	r3, r0
 8001384:	2b00      	cmp	r3, #0
 8001386:	d001      	beq.n	800138c <StartDefaultTask+0x64>
  {
	  Error_Handler();
 8001388:	f000 f882 	bl	8001490 <Error_Handler>
  }
  if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK)
 800138c:	2205      	movs	r2, #5
 800138e:	490c      	ldr	r1, [pc, #48]	@ (80013c0 <StartDefaultTask+0x98>)
 8001390:	480c      	ldr	r0, [pc, #48]	@ (80013c4 <StartDefaultTask+0x9c>)
 8001392:	f002 fc75 	bl	8003c80 <HAL_ADC_Start_DMA>
 8001396:	4603      	mov	r3, r0
 8001398:	2b00      	cmp	r3, #0
 800139a:	d001      	beq.n	80013a0 <StartDefaultTask+0x78>
  {
	  Error_Handler();
 800139c:	f000 f878 	bl	8001490 <Error_Handler>
  }
  /* Infinite loop */
  for(;;)
  {
	 osDelay(pdMS_TO_TICKS(1000));
 80013a0:	f44f 707a 	mov.w	r0, #1000	@ 0x3e8
 80013a4:	f00e fa27 	bl	800f7f6 <osDelay>
 80013a8:	e7fa      	b.n	80013a0 <StartDefaultTask+0x78>
 80013aa:	bf00      	nop
 80013ac:	2400040c 	.word	0x2400040c
 80013b0:	240000e0 	.word	0x240000e0
 80013b4:	24000140 	.word	0x24000140
 80013b8:	24000100 	.word	0x24000100
 80013bc:	240001a4 	.word	0x240001a4
 80013c0:	24000120 	.word	0x24000120
 80013c4:	24000208 	.word	0x24000208

080013c8 <MPU_Config>:
}

 /* MPU Configuration */

void MPU_Config(void)
{
 80013c8:	b580      	push	{r7, lr}
 80013ca:	b084      	sub	sp, #16
 80013cc:	af00      	add	r7, sp, #0
  MPU_Region_InitTypeDef MPU_InitStruct = {0};
 80013ce:	463b      	mov	r3, r7
 80013d0:	2200      	movs	r2, #0
 80013d2:	601a      	str	r2, [r3, #0]
 80013d4:	605a      	str	r2, [r3, #4]
 80013d6:	609a      	str	r2, [r3, #8]
 80013d8:	60da      	str	r2, [r3, #12]

  /* Disables the MPU */
  HAL_MPU_Disable();
 80013da:	f003 fd8b 	bl	8004ef4 <HAL_MPU_Disable>

  /** Initializes and configures the Region and the memory to be protected
  */
  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
 80013de:	2301      	movs	r3, #1
 80013e0:	703b      	strb	r3, [r7, #0]
  MPU_InitStruct.Number = MPU_REGION_NUMBER0;
 80013e2:	2300      	movs	r3, #0
 80013e4:	707b      	strb	r3, [r7, #1]
  MPU_InitStruct.BaseAddress = 0x0;
 80013e6:	2300      	movs	r3, #0
 80013e8:	607b      	str	r3, [r7, #4]
  MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
 80013ea:	231f      	movs	r3, #31
 80013ec:	723b      	strb	r3, [r7, #8]
  MPU_InitStruct.SubRegionDisable = 0x87;
 80013ee:	2387      	movs	r3, #135	@ 0x87
 80013f0:	727b      	strb	r3, [r7, #9]
  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
 80013f2:	2300      	movs	r3, #0
 80013f4:	72bb      	strb	r3, [r7, #10]
  MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
 80013f6:	2300      	movs	r3, #0
 80013f8:	72fb      	strb	r3, [r7, #11]
  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
 80013fa:	2301      	movs	r3, #1
 80013fc:	733b      	strb	r3, [r7, #12]
  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
 80013fe:	2301      	movs	r3, #1
 8001400:	737b      	strb	r3, [r7, #13]
  MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
 8001402:	2300      	movs	r3, #0
 8001404:	73bb      	strb	r3, [r7, #14]
  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
 8001406:	2300      	movs	r3, #0
 8001408:	73fb      	strb	r3, [r7, #15]

  HAL_MPU_ConfigRegion(&MPU_InitStruct);
 800140a:	463b      	mov	r3, r7
 800140c:	4618      	mov	r0, r3
 800140e:	f003 fda9 	bl	8004f64 <HAL_MPU_ConfigRegion>

  /** Initializes and configures the Region and the memory to be protected
  */
  MPU_InitStruct.Number = MPU_REGION_NUMBER1;
 8001412:	2301      	movs	r3, #1
 8001414:	707b      	strb	r3, [r7, #1]
  MPU_InitStruct.BaseAddress = 0x24020000;
 8001416:	4b13      	ldr	r3, [pc, #76]	@ (8001464 <MPU_Config+0x9c>)
 8001418:	607b      	str	r3, [r7, #4]
  MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
 800141a:	2310      	movs	r3, #16
 800141c:	723b      	strb	r3, [r7, #8]
  MPU_InitStruct.SubRegionDisable = 0x0;
 800141e:	2300      	movs	r3, #0
 8001420:	727b      	strb	r3, [r7, #9]
  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
 8001422:	2301      	movs	r3, #1
 8001424:	72bb      	strb	r3, [r7, #10]
  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
 8001426:	2303      	movs	r3, #3
 8001428:	72fb      	strb	r3, [r7, #11]
  MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
 800142a:	2300      	movs	r3, #0
 800142c:	737b      	strb	r3, [r7, #13]

  HAL_MPU_ConfigRegion(&MPU_InitStruct);
 800142e:	463b      	mov	r3, r7
 8001430:	4618      	mov	r0, r3
 8001432:	f003 fd97 	bl	8004f64 <HAL_MPU_ConfigRegion>

  /** Initializes and configures the Region and the memory to be protected
  */
  MPU_InitStruct.Number = MPU_REGION_NUMBER2;
 8001436:	2302      	movs	r3, #2
 8001438:	707b      	strb	r3, [r7, #1]
  MPU_InitStruct.BaseAddress = 0x24040000;
 800143a:	4b0b      	ldr	r3, [pc, #44]	@ (8001468 <MPU_Config+0xa0>)
 800143c:	607b      	str	r3, [r7, #4]
  MPU_InitStruct.Size = MPU_REGION_SIZE_512B;
 800143e:	2308      	movs	r3, #8
 8001440:	723b      	strb	r3, [r7, #8]
  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
 8001442:	2300      	movs	r3, #0
 8001444:	72bb      	strb	r3, [r7, #10]
  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
 8001446:	2301      	movs	r3, #1
 8001448:	737b      	strb	r3, [r7, #13]
  MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
 800144a:	2301      	movs	r3, #1
 800144c:	73fb      	strb	r3, [r7, #15]

  HAL_MPU_ConfigRegion(&MPU_InitStruct);
 800144e:	463b      	mov	r3, r7
 8001450:	4618      	mov	r0, r3
 8001452:	f003 fd87 	bl	8004f64 <HAL_MPU_ConfigRegion>
  /* Enables the MPU */
  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
 8001456:	2004      	movs	r0, #4
 8001458:	f003 fd64 	bl	8004f24 <HAL_MPU_Enable>

}
 800145c:	bf00      	nop
 800145e:	3710      	adds	r7, #16
 8001460:	46bd      	mov	sp, r7
 8001462:	bd80      	pop	{r7, pc}
 8001464:	24020000 	.word	0x24020000
 8001468:	24040000 	.word	0x24040000

0800146c <HAL_TIM_PeriodElapsedCallback>:
  * a global variable "uwTick" used as application time base.
  * @param  htim : TIM handle
  * @retval None
  */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
 800146c:	b580      	push	{r7, lr}
 800146e:	b082      	sub	sp, #8
 8001470:	af00      	add	r7, sp, #0
 8001472:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN Callback 0 */

  /* USER CODE END Callback 0 */
  if (htim->Instance == TIM6) {
 8001474:	687b      	ldr	r3, [r7, #4]
 8001476:	681b      	ldr	r3, [r3, #0]
 8001478:	4a04      	ldr	r2, [pc, #16]	@ (800148c <HAL_TIM_PeriodElapsedCallback+0x20>)
 800147a:	4293      	cmp	r3, r2
 800147c:	d101      	bne.n	8001482 <HAL_TIM_PeriodElapsedCallback+0x16>
    HAL_IncTick();
 800147e:	f002 f80d 	bl	800349c <HAL_IncTick>
//	  HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_4);
//	  HAL_ADC_Start_IT(&hadc1);
  }

  /* USER CODE END Callback 1 */
}
 8001482:	bf00      	nop
 8001484:	3708      	adds	r7, #8
 8001486:	46bd      	mov	sp, r7
 8001488:	bd80      	pop	{r7, pc}
 800148a:	bf00      	nop
 800148c:	40001000 	.word	0x40001000

08001490 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8001490:	b480      	push	{r7}
 8001492:	af00      	add	r7, sp, #0
  __ASM volatile ("cpsid i" : : : "memory");
 8001494:	b672      	cpsid	i
}
 8001496:	bf00      	nop
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
 8001498:	bf00      	nop
 800149a:	e7fd      	b.n	8001498 <Error_Handler+0x8>

0800149c <MeasTasksInit>:
RESMeasurements resMeasurements = { 0 };
SesnorsInfo sensorsInfo         = { 0 };

uint16_t ILxRef[CURRENTS_COUNT] = { 0 };

void MeasTasksInit (void) {
 800149c:	b580      	push	{r7, lr}
 800149e:	b09c      	sub	sp, #112	@ 0x70
 80014a0:	af00      	add	r7, sp, #0
    vRefmVMutex          = osMutexNew (NULL);
 80014a2:	2000      	movs	r0, #0
 80014a4:	f00e f9c2 	bl	800f82c <osMutexNew>
 80014a8:	4603      	mov	r3, r0
 80014aa:	4a38      	ldr	r2, [pc, #224]	@ (800158c <MeasTasksInit+0xf0>)
 80014ac:	6013      	str	r3, [r2, #0]
    resMeasurementsMutex = osMutexNew (NULL);
 80014ae:	2000      	movs	r0, #0
 80014b0:	f00e f9bc 	bl	800f82c <osMutexNew>
 80014b4:	4603      	mov	r3, r0
 80014b6:	4a36      	ldr	r2, [pc, #216]	@ (8001590 <MeasTasksInit+0xf4>)
 80014b8:	6013      	str	r3, [r2, #0]
    sensorsInfoMutex     = osMutexNew (NULL);
 80014ba:	2000      	movs	r0, #0
 80014bc:	f00e f9b6 	bl	800f82c <osMutexNew>
 80014c0:	4603      	mov	r3, r0
 80014c2:	4a34      	ldr	r2, [pc, #208]	@ (8001594 <MeasTasksInit+0xf8>)
 80014c4:	6013      	str	r3, [r2, #0]
    ILxRefMutex			 = osMutexNew (NULL);
 80014c6:	2000      	movs	r0, #0
 80014c8:	f00e f9b0 	bl	800f82c <osMutexNew>
 80014cc:	4603      	mov	r3, r0
 80014ce:	4a32      	ldr	r2, [pc, #200]	@ (8001598 <MeasTasksInit+0xfc>)
 80014d0:	6013      	str	r3, [r2, #0]
    adc1MeasDataQueue    = osMessageQueueNew (8, sizeof (ADC1_Data), NULL);
 80014d2:	2200      	movs	r2, #0
 80014d4:	2120      	movs	r1, #32
 80014d6:	2008      	movs	r0, #8
 80014d8:	f00e fab6 	bl	800fa48 <osMessageQueueNew>
 80014dc:	4603      	mov	r3, r0
 80014de:	4a2f      	ldr	r2, [pc, #188]	@ (800159c <MeasTasksInit+0x100>)
 80014e0:	6013      	str	r3, [r2, #0]
    adc2MeasDataQueue    = osMessageQueueNew (8, sizeof (ADC2_Data), NULL);
 80014e2:	2200      	movs	r2, #0
 80014e4:	2120      	movs	r1, #32
 80014e6:	2008      	movs	r0, #8
 80014e8:	f00e faae 	bl	800fa48 <osMessageQueueNew>
 80014ec:	4603      	mov	r3, r0
 80014ee:	4a2c      	ldr	r2, [pc, #176]	@ (80015a0 <MeasTasksInit+0x104>)
 80014f0:	6013      	str	r3, [r2, #0]
    adc3MeasDataQueue    = osMessageQueueNew (8, sizeof (ADC3_Data), NULL);
 80014f2:	2200      	movs	r2, #0
 80014f4:	2120      	movs	r1, #32
 80014f6:	2008      	movs	r0, #8
 80014f8:	f00e faa6 	bl	800fa48 <osMessageQueueNew>
 80014fc:	4603      	mov	r3, r0
 80014fe:	4a29      	ldr	r2, [pc, #164]	@ (80015a4 <MeasTasksInit+0x108>)
 8001500:	6013      	str	r3, [r2, #0]

    osThreadAttr_t osThreadAttradc1MeasTask = { 0 };
 8001502:	f107 034c 	add.w	r3, r7, #76	@ 0x4c
 8001506:	2224      	movs	r2, #36	@ 0x24
 8001508:	2100      	movs	r1, #0
 800150a:	4618      	mov	r0, r3
 800150c:	f012 f96b 	bl	80137e6 <memset>
    osThreadAttr_t osThreadAttradc2MeasTask = { 0 };
 8001510:	f107 0328 	add.w	r3, r7, #40	@ 0x28
 8001514:	2224      	movs	r2, #36	@ 0x24
 8001516:	2100      	movs	r1, #0
 8001518:	4618      	mov	r0, r3
 800151a:	f012 f964 	bl	80137e6 <memset>
    osThreadAttr_t osThreadAttradc3MeasTask = { 0 };
 800151e:	1d3b      	adds	r3, r7, #4
 8001520:	2224      	movs	r2, #36	@ 0x24
 8001522:	2100      	movs	r1, #0
 8001524:	4618      	mov	r0, r3
 8001526:	f012 f95e 	bl	80137e6 <memset>

    osThreadAttradc1MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2;
 800152a:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 800152e:	663b      	str	r3, [r7, #96]	@ 0x60
    osThreadAttradc1MeasTask.priority   = (osPriority_t)osPriorityRealtime;
 8001530:	2330      	movs	r3, #48	@ 0x30
 8001532:	667b      	str	r3, [r7, #100]	@ 0x64

    osThreadAttradc2MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2;
 8001534:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 8001538:	63fb      	str	r3, [r7, #60]	@ 0x3c
    osThreadAttradc2MeasTask.priority   = (osPriority_t)osPriorityRealtime;
 800153a:	2330      	movs	r3, #48	@ 0x30
 800153c:	643b      	str	r3, [r7, #64]	@ 0x40

    osThreadAttradc3MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2;
 800153e:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 8001542:	61bb      	str	r3, [r7, #24]
    osThreadAttradc3MeasTask.priority   = (osPriority_t)osPriorityNormal;
 8001544:	2318      	movs	r3, #24
 8001546:	61fb      	str	r3, [r7, #28]

    adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask);
 8001548:	f107 034c 	add.w	r3, r7, #76	@ 0x4c
 800154c:	461a      	mov	r2, r3
 800154e:	2100      	movs	r1, #0
 8001550:	4815      	ldr	r0, [pc, #84]	@ (80015a8 <MeasTasksInit+0x10c>)
 8001552:	f00e f8bd 	bl	800f6d0 <osThreadNew>
 8001556:	4603      	mov	r3, r0
 8001558:	4a14      	ldr	r2, [pc, #80]	@ (80015ac <MeasTasksInit+0x110>)
 800155a:	6013      	str	r3, [r2, #0]
    adc2MeasTaskHandle = osThreadNew (ADC2MeasTask, NULL, &osThreadAttradc2MeasTask);
 800155c:	f107 0328 	add.w	r3, r7, #40	@ 0x28
 8001560:	461a      	mov	r2, r3
 8001562:	2100      	movs	r1, #0
 8001564:	4812      	ldr	r0, [pc, #72]	@ (80015b0 <MeasTasksInit+0x114>)
 8001566:	f00e f8b3 	bl	800f6d0 <osThreadNew>
 800156a:	4603      	mov	r3, r0
 800156c:	4a11      	ldr	r2, [pc, #68]	@ (80015b4 <MeasTasksInit+0x118>)
 800156e:	6013      	str	r3, [r2, #0]
    adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask);
 8001570:	1d3b      	adds	r3, r7, #4
 8001572:	461a      	mov	r2, r3
 8001574:	2100      	movs	r1, #0
 8001576:	4810      	ldr	r0, [pc, #64]	@ (80015b8 <MeasTasksInit+0x11c>)
 8001578:	f00e f8aa 	bl	800f6d0 <osThreadNew>
 800157c:	4603      	mov	r3, r0
 800157e:	4a0f      	ldr	r2, [pc, #60]	@ (80015bc <MeasTasksInit+0x120>)
 8001580:	6013      	str	r3, [r2, #0]
}
 8001582:	bf00      	nop
 8001584:	3770      	adds	r7, #112	@ 0x70
 8001586:	46bd      	mov	sp, r7
 8001588:	bd80      	pop	{r7, pc}
 800158a:	bf00      	nop
 800158c:	2400059c 	.word	0x2400059c
 8001590:	240005a0 	.word	0x240005a0
 8001594:	240005a4 	.word	0x240005a4
 8001598:	240005a8 	.word	0x240005a8
 800159c:	24000590 	.word	0x24000590
 80015a0:	24000594 	.word	0x24000594
 80015a4:	24000598 	.word	0x24000598
 80015a8:	080015c1 	.word	0x080015c1
 80015ac:	24000584 	.word	0x24000584
 80015b0:	080018c9 	.word	0x080018c9
 80015b4:	24000588 	.word	0x24000588
 80015b8:	08001bb9 	.word	0x08001bb9
 80015bc:	2400058c 	.word	0x2400058c

080015c0 <ADC1MeasTask>:

void ADC1MeasTask (void* arg) {
 80015c0:	b580      	push	{r7, lr}
 80015c2:	b09a      	sub	sp, #104	@ 0x68
 80015c4:	af00      	add	r7, sp, #0
 80015c6:	6078      	str	r0, [r7, #4]
    float circBuffer[VOLTAGES_COUNT][CIRC_BUFF_LEN];
    float rms[VOLTAGES_COUNT];
    ADC1_Data adcData    = { 0 };
 80015c8:	f107 030c 	add.w	r3, r7, #12
 80015cc:	2220      	movs	r2, #32
 80015ce:	2100      	movs	r1, #0
 80015d0:	4618      	mov	r0, r3
 80015d2:	f012 f908 	bl	80137e6 <memset>
    uint32_t circBuffPos = 0;
 80015d6:	2300      	movs	r3, #0
 80015d8:	667b      	str	r3, [r7, #100]	@ 0x64
    float gainCorrection = 1.0;
 80015da:	f04f 537e 	mov.w	r3, #1065353216	@ 0x3f800000
 80015de:	663b      	str	r3, [r7, #96]	@ 0x60
    while (pdTRUE) {
        osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever);
 80015e0:	4baf      	ldr	r3, [pc, #700]	@ (80018a0 <ADC1MeasTask+0x2e0>)
 80015e2:	6818      	ldr	r0, [r3, #0]
 80015e4:	f107 010c 	add.w	r1, r7, #12
 80015e8:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 80015ec:	2200      	movs	r2, #0
 80015ee:	f00e faff 	bl	800fbf0 <osMessageQueueGet>
#ifdef GAIN_AUTO_CORRECTION
        if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) {
 80015f2:	4bac      	ldr	r3, [pc, #688]	@ (80018a4 <ADC1MeasTask+0x2e4>)
 80015f4:	681b      	ldr	r3, [r3, #0]
 80015f6:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80015fa:	4618      	mov	r0, r3
 80015fc:	f00e f99c 	bl	800f938 <osMutexAcquire>
 8001600:	4603      	mov	r3, r0
 8001602:	2b00      	cmp	r3, #0
 8001604:	d10c      	bne.n	8001620 <ADC1MeasTask+0x60>
            gainCorrection = (float)vRefmV;
 8001606:	4ba8      	ldr	r3, [pc, #672]	@ (80018a8 <ADC1MeasTask+0x2e8>)
 8001608:	681b      	ldr	r3, [r3, #0]
 800160a:	ee07 3a90 	vmov	s15, r3
 800160e:	eef8 7a67 	vcvt.f32.u32	s15, s15
 8001612:	edc7 7a18 	vstr	s15, [r7, #96]	@ 0x60
            osMutexRelease (vRefmVMutex);
 8001616:	4ba3      	ldr	r3, [pc, #652]	@ (80018a4 <ADC1MeasTask+0x2e4>)
 8001618:	681b      	ldr	r3, [r3, #0]
 800161a:	4618      	mov	r0, r3
 800161c:	f00e f9d7 	bl	800f9ce <osMutexRelease>
        }
        gainCorrection = gainCorrection / EXT_VREF_mV;
 8001620:	ed97 7a18 	vldr	s14, [r7, #96]	@ 0x60
 8001624:	eddf 6aa1 	vldr	s13, [pc, #644]	@ 80018ac <ADC1MeasTask+0x2ec>
 8001628:	eec7 7a26 	vdiv.f32	s15, s14, s13
 800162c:	edc7 7a18 	vstr	s15, [r7, #96]	@ 0x60
#endif
        for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) {
 8001630:	2300      	movs	r3, #0
 8001632:	f887 305f 	strb.w	r3, [r7, #95]	@ 0x5f
 8001636:	e0e7      	b.n	8001808 <ADC1MeasTask+0x248>
            float val                  = adcData.adcDataBuffer[i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
 8001638:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 800163c:	005b      	lsls	r3, r3, #1
 800163e:	3368      	adds	r3, #104	@ 0x68
 8001640:	443b      	add	r3, r7
 8001642:	f833 3c5c 	ldrh.w	r3, [r3, #-92]
 8001646:	ee07 3a90 	vmov	s15, r3
 800164a:	eeb8 7be7 	vcvt.f64.s32	d7, s15
 800164e:	eeb0 6b08 	vmov.f64	d6, #8	@ 0x40400000  3.0
 8001652:	ee27 6b06 	vmul.f64	d6, d7, d6
 8001656:	ed9f 5b8e 	vldr	d5, [pc, #568]	@ 8001890 <ADC1MeasTask+0x2d0>
 800165a:	ee86 7b05 	vdiv.f64	d7, d6, d5
 800165e:	ed9f 6b8e 	vldr	d6, [pc, #568]	@ 8001898 <ADC1MeasTask+0x2d8>
 8001662:	ee27 6b06 	vmul.f64	d6, d7, d6
 8001666:	edd7 7a18 	vldr	s15, [r7, #96]	@ 0x60
 800166a:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 800166e:	ee26 6b07 	vmul.f64	d6, d6, d7
 8001672:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 8001676:	4a8e      	ldr	r2, [pc, #568]	@ (80018b0 <ADC1MeasTask+0x2f0>)
 8001678:	00db      	lsls	r3, r3, #3
 800167a:	4413      	add	r3, r2
 800167c:	edd3 7a00 	vldr	s15, [r3]
 8001680:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 8001684:	ee26 6b07 	vmul.f64	d6, d6, d7
 8001688:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 800168c:	4a88      	ldr	r2, [pc, #544]	@ (80018b0 <ADC1MeasTask+0x2f0>)
 800168e:	00db      	lsls	r3, r3, #3
 8001690:	4413      	add	r3, r2
 8001692:	3304      	adds	r3, #4
 8001694:	edd3 7a00 	vldr	s15, [r3]
 8001698:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 800169c:	ee36 7b07 	vadd.f64	d7, d6, d7
 80016a0:	eef7 7bc7 	vcvt.f32.f64	s15, d7
 80016a4:	edc7 7a16 	vstr	s15, [r7, #88]	@ 0x58
            circBuffer[i][circBuffPos] = val;
 80016a8:	f897 205f 	ldrb.w	r2, [r7, #95]	@ 0x5f
 80016ac:	4613      	mov	r3, r2
 80016ae:	009b      	lsls	r3, r3, #2
 80016b0:	4413      	add	r3, r2
 80016b2:	005b      	lsls	r3, r3, #1
 80016b4:	6e7a      	ldr	r2, [r7, #100]	@ 0x64
 80016b6:	4413      	add	r3, r2
 80016b8:	009b      	lsls	r3, r3, #2
 80016ba:	3368      	adds	r3, #104	@ 0x68
 80016bc:	443b      	add	r3, r7
 80016be:	3b38      	subs	r3, #56	@ 0x38
 80016c0:	6dba      	ldr	r2, [r7, #88]	@ 0x58
 80016c2:	601a      	str	r2, [r3, #0]
            rms[i]                     = 0.0;
 80016c4:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 80016c8:	009b      	lsls	r3, r3, #2
 80016ca:	3368      	adds	r3, #104	@ 0x68
 80016cc:	443b      	add	r3, r7
 80016ce:	3b3c      	subs	r3, #60	@ 0x3c
 80016d0:	f04f 0200 	mov.w	r2, #0
 80016d4:	601a      	str	r2, [r3, #0]
            for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) {
 80016d6:	2300      	movs	r3, #0
 80016d8:	f887 305e 	strb.w	r3, [r7, #94]	@ 0x5e
 80016dc:	e025      	b.n	800172a <ADC1MeasTask+0x16a>
                rms[i] += circBuffer[i][c];
 80016de:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 80016e2:	009b      	lsls	r3, r3, #2
 80016e4:	3368      	adds	r3, #104	@ 0x68
 80016e6:	443b      	add	r3, r7
 80016e8:	3b3c      	subs	r3, #60	@ 0x3c
 80016ea:	ed93 7a00 	vldr	s14, [r3]
 80016ee:	f897 205f 	ldrb.w	r2, [r7, #95]	@ 0x5f
 80016f2:	f897 105e 	ldrb.w	r1, [r7, #94]	@ 0x5e
 80016f6:	4613      	mov	r3, r2
 80016f8:	009b      	lsls	r3, r3, #2
 80016fa:	4413      	add	r3, r2
 80016fc:	005b      	lsls	r3, r3, #1
 80016fe:	440b      	add	r3, r1
 8001700:	009b      	lsls	r3, r3, #2
 8001702:	3368      	adds	r3, #104	@ 0x68
 8001704:	443b      	add	r3, r7
 8001706:	3b38      	subs	r3, #56	@ 0x38
 8001708:	edd3 7a00 	vldr	s15, [r3]
 800170c:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 8001710:	ee77 7a27 	vadd.f32	s15, s14, s15
 8001714:	009b      	lsls	r3, r3, #2
 8001716:	3368      	adds	r3, #104	@ 0x68
 8001718:	443b      	add	r3, r7
 800171a:	3b3c      	subs	r3, #60	@ 0x3c
 800171c:	edc3 7a00 	vstr	s15, [r3]
            for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) {
 8001720:	f897 305e 	ldrb.w	r3, [r7, #94]	@ 0x5e
 8001724:	3301      	adds	r3, #1
 8001726:	f887 305e 	strb.w	r3, [r7, #94]	@ 0x5e
 800172a:	f897 305e 	ldrb.w	r3, [r7, #94]	@ 0x5e
 800172e:	2b09      	cmp	r3, #9
 8001730:	d9d5      	bls.n	80016de <ADC1MeasTask+0x11e>
            }
            rms[i] = rms[i] / CIRC_BUFF_LEN;
 8001732:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 8001736:	009b      	lsls	r3, r3, #2
 8001738:	3368      	adds	r3, #104	@ 0x68
 800173a:	443b      	add	r3, r7
 800173c:	3b3c      	subs	r3, #60	@ 0x3c
 800173e:	ed93 7a00 	vldr	s14, [r3]
 8001742:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 8001746:	eef2 6a04 	vmov.f32	s13, #36	@ 0x41200000  10.0
 800174a:	eec7 7a26 	vdiv.f32	s15, s14, s13
 800174e:	009b      	lsls	r3, r3, #2
 8001750:	3368      	adds	r3, #104	@ 0x68
 8001752:	443b      	add	r3, r7
 8001754:	3b3c      	subs	r3, #60	@ 0x3c
 8001756:	edc3 7a00 	vstr	s15, [r3]
            if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
 800175a:	4b56      	ldr	r3, [pc, #344]	@ (80018b4 <ADC1MeasTask+0x2f4>)
 800175c:	681b      	ldr	r3, [r3, #0]
 800175e:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8001762:	4618      	mov	r0, r3
 8001764:	f00e f8e8 	bl	800f938 <osMutexAcquire>
 8001768:	4603      	mov	r3, r0
 800176a:	2b00      	cmp	r3, #0
 800176c:	d147      	bne.n	80017fe <ADC1MeasTask+0x23e>
                if (fabs(resMeasurements.voltagePeak[i]) < fabs(val)) {
 800176e:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 8001772:	4a51      	ldr	r2, [pc, #324]	@ (80018b8 <ADC1MeasTask+0x2f8>)
 8001774:	3302      	adds	r3, #2
 8001776:	009b      	lsls	r3, r3, #2
 8001778:	4413      	add	r3, r2
 800177a:	3304      	adds	r3, #4
 800177c:	edd3 7a00 	vldr	s15, [r3]
 8001780:	eeb0 7ae7 	vabs.f32	s14, s15
 8001784:	edd7 7a16 	vldr	s15, [r7, #88]	@ 0x58
 8001788:	eef0 7ae7 	vabs.f32	s15, s15
 800178c:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8001790:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001794:	d508      	bpl.n	80017a8 <ADC1MeasTask+0x1e8>
                    resMeasurements.voltagePeak[i] = val;
 8001796:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 800179a:	4a47      	ldr	r2, [pc, #284]	@ (80018b8 <ADC1MeasTask+0x2f8>)
 800179c:	3302      	adds	r3, #2
 800179e:	009b      	lsls	r3, r3, #2
 80017a0:	4413      	add	r3, r2
 80017a2:	3304      	adds	r3, #4
 80017a4:	6dba      	ldr	r2, [r7, #88]	@ 0x58
 80017a6:	601a      	str	r2, [r3, #0]
                }
                resMeasurements.voltageRMS[i] = rms[i];
 80017a8:	f897 205f 	ldrb.w	r2, [r7, #95]	@ 0x5f
 80017ac:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 80017b0:	0092      	lsls	r2, r2, #2
 80017b2:	3268      	adds	r2, #104	@ 0x68
 80017b4:	443a      	add	r2, r7
 80017b6:	3a3c      	subs	r2, #60	@ 0x3c
 80017b8:	6812      	ldr	r2, [r2, #0]
 80017ba:	493f      	ldr	r1, [pc, #252]	@ (80018b8 <ADC1MeasTask+0x2f8>)
 80017bc:	009b      	lsls	r3, r3, #2
 80017be:	440b      	add	r3, r1
 80017c0:	601a      	str	r2, [r3, #0]
                resMeasurements.power[i]      = resMeasurements.voltageRMS[i] * resMeasurements.currentRMS[i];
 80017c2:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 80017c6:	4a3c      	ldr	r2, [pc, #240]	@ (80018b8 <ADC1MeasTask+0x2f8>)
 80017c8:	009b      	lsls	r3, r3, #2
 80017ca:	4413      	add	r3, r2
 80017cc:	ed93 7a00 	vldr	s14, [r3]
 80017d0:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 80017d4:	4a38      	ldr	r2, [pc, #224]	@ (80018b8 <ADC1MeasTask+0x2f8>)
 80017d6:	3306      	adds	r3, #6
 80017d8:	009b      	lsls	r3, r3, #2
 80017da:	4413      	add	r3, r2
 80017dc:	edd3 7a00 	vldr	s15, [r3]
 80017e0:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 80017e4:	ee67 7a27 	vmul.f32	s15, s14, s15
 80017e8:	4a33      	ldr	r2, [pc, #204]	@ (80018b8 <ADC1MeasTask+0x2f8>)
 80017ea:	330c      	adds	r3, #12
 80017ec:	009b      	lsls	r3, r3, #2
 80017ee:	4413      	add	r3, r2
 80017f0:	edc3 7a00 	vstr	s15, [r3]
                osMutexRelease (resMeasurementsMutex);
 80017f4:	4b2f      	ldr	r3, [pc, #188]	@ (80018b4 <ADC1MeasTask+0x2f4>)
 80017f6:	681b      	ldr	r3, [r3, #0]
 80017f8:	4618      	mov	r0, r3
 80017fa:	f00e f8e8 	bl	800f9ce <osMutexRelease>
        for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) {
 80017fe:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 8001802:	3301      	adds	r3, #1
 8001804:	f887 305f 	strb.w	r3, [r7, #95]	@ 0x5f
 8001808:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 800180c:	2b00      	cmp	r3, #0
 800180e:	f43f af13 	beq.w	8001638 <ADC1MeasTask+0x78>
            }
        }
        ++circBuffPos;
 8001812:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 8001814:	3301      	adds	r3, #1
 8001816:	667b      	str	r3, [r7, #100]	@ 0x64
        circBuffPos = circBuffPos % CIRC_BUFF_LEN;
 8001818:	6e7a      	ldr	r2, [r7, #100]	@ 0x64
 800181a:	4b28      	ldr	r3, [pc, #160]	@ (80018bc <ADC1MeasTask+0x2fc>)
 800181c:	fba3 1302 	umull	r1, r3, r3, r2
 8001820:	08d9      	lsrs	r1, r3, #3
 8001822:	460b      	mov	r3, r1
 8001824:	009b      	lsls	r3, r3, #2
 8001826:	440b      	add	r3, r1
 8001828:	005b      	lsls	r3, r3, #1
 800182a:	1ad3      	subs	r3, r2, r3
 800182c:	667b      	str	r3, [r7, #100]	@ 0x64

        if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) {
 800182e:	4b24      	ldr	r3, [pc, #144]	@ (80018c0 <ADC1MeasTask+0x300>)
 8001830:	681b      	ldr	r3, [r3, #0]
 8001832:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8001836:	4618      	mov	r0, r3
 8001838:	f00e f87e 	bl	800f938 <osMutexAcquire>
 800183c:	4603      	mov	r3, r0
 800183e:	2b00      	cmp	r3, #0
 8001840:	f47f aece 	bne.w	80015e0 <ADC1MeasTask+0x20>
            uint8_t refIdx = 0;
 8001844:	2300      	movs	r3, #0
 8001846:	f887 305d 	strb.w	r3, [r7, #93]	@ 0x5d
            for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) {
 800184a:	2303      	movs	r3, #3
 800184c:	f887 305c 	strb.w	r3, [r7, #92]	@ 0x5c
 8001850:	e014      	b.n	800187c <ADC1MeasTask+0x2bc>
                ILxRef[refIdx++] = adcData.adcDataBuffer[i];
 8001852:	f897 205c 	ldrb.w	r2, [r7, #92]	@ 0x5c
 8001856:	f897 305d 	ldrb.w	r3, [r7, #93]	@ 0x5d
 800185a:	1c59      	adds	r1, r3, #1
 800185c:	f887 105d 	strb.w	r1, [r7, #93]	@ 0x5d
 8001860:	4619      	mov	r1, r3
 8001862:	0053      	lsls	r3, r2, #1
 8001864:	3368      	adds	r3, #104	@ 0x68
 8001866:	443b      	add	r3, r7
 8001868:	f833 2c5c 	ldrh.w	r2, [r3, #-92]
 800186c:	4b15      	ldr	r3, [pc, #84]	@ (80018c4 <ADC1MeasTask+0x304>)
 800186e:	f823 2011 	strh.w	r2, [r3, r1, lsl #1]
            for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) {
 8001872:	f897 305c 	ldrb.w	r3, [r7, #92]	@ 0x5c
 8001876:	3301      	adds	r3, #1
 8001878:	f887 305c 	strb.w	r3, [r7, #92]	@ 0x5c
 800187c:	f897 305c 	ldrb.w	r3, [r7, #92]	@ 0x5c
 8001880:	2b05      	cmp	r3, #5
 8001882:	d9e6      	bls.n	8001852 <ADC1MeasTask+0x292>
            }
            osMutexRelease (ILxRefMutex);
 8001884:	4b0e      	ldr	r3, [pc, #56]	@ (80018c0 <ADC1MeasTask+0x300>)
 8001886:	681b      	ldr	r3, [r3, #0]
 8001888:	4618      	mov	r0, r3
 800188a:	f00e f8a0 	bl	800f9ce <osMutexRelease>
        osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever);
 800188e:	e6a7      	b.n	80015e0 <ADC1MeasTask+0x20>
 8001890:	00000000 	.word	0x00000000
 8001894:	40efffe0 	.word	0x40efffe0
 8001898:	f5c28f5c 	.word	0xf5c28f5c
 800189c:	401e5c28 	.word	0x401e5c28
 80018a0:	24000590 	.word	0x24000590
 80018a4:	2400059c 	.word	0x2400059c
 80018a8:	24000030 	.word	0x24000030
 80018ac:	453b8000 	.word	0x453b8000
 80018b0:	24000000 	.word	0x24000000
 80018b4:	240005a0 	.word	0x240005a0
 80018b8:	240005ac 	.word	0x240005ac
 80018bc:	cccccccd 	.word	0xcccccccd
 80018c0:	240005a8 	.word	0x240005a8
 80018c4:	24000610 	.word	0x24000610

080018c8 <ADC2MeasTask>:
        }
    }
}

void ADC2MeasTask (void* arg) {
 80018c8:	b580      	push	{r7, lr}
 80018ca:	b09c      	sub	sp, #112	@ 0x70
 80018cc:	af00      	add	r7, sp, #0
 80018ce:	6078      	str	r0, [r7, #4]
    float circBuffer[CURRENTS_COUNT][CIRC_BUFF_LEN];
    float rms[CURRENTS_COUNT];
    ADC2_Data adcData    = { 0 };
 80018d0:	f107 0310 	add.w	r3, r7, #16
 80018d4:	2220      	movs	r2, #32
 80018d6:	2100      	movs	r1, #0
 80018d8:	4618      	mov	r0, r3
 80018da:	f011 ff84 	bl	80137e6 <memset>
    uint32_t circBuffPos = 0;
 80018de:	2300      	movs	r3, #0
 80018e0:	66fb      	str	r3, [r7, #108]	@ 0x6c
    float gainCorrection = 1.0;
 80018e2:	f04f 537e 	mov.w	r3, #1065353216	@ 0x3f800000
 80018e6:	66bb      	str	r3, [r7, #104]	@ 0x68
    while (pdTRUE) {
        osMessageQueueGet (adc2MeasDataQueue, &adcData, 0, osWaitForever);
 80018e8:	4ba9      	ldr	r3, [pc, #676]	@ (8001b90 <ADC2MeasTask+0x2c8>)
 80018ea:	6818      	ldr	r0, [r3, #0]
 80018ec:	f107 0110 	add.w	r1, r7, #16
 80018f0:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 80018f4:	2200      	movs	r2, #0
 80018f6:	f00e f97b 	bl	800fbf0 <osMessageQueueGet>
        if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) {
 80018fa:	4ba6      	ldr	r3, [pc, #664]	@ (8001b94 <ADC2MeasTask+0x2cc>)
 80018fc:	681b      	ldr	r3, [r3, #0]
 80018fe:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8001902:	4618      	mov	r0, r3
 8001904:	f00e f818 	bl	800f938 <osMutexAcquire>
 8001908:	4603      	mov	r3, r0
 800190a:	2b00      	cmp	r3, #0
 800190c:	d10c      	bne.n	8001928 <ADC2MeasTask+0x60>
            gainCorrection = (float)vRefmV;
 800190e:	4ba2      	ldr	r3, [pc, #648]	@ (8001b98 <ADC2MeasTask+0x2d0>)
 8001910:	681b      	ldr	r3, [r3, #0]
 8001912:	ee07 3a90 	vmov	s15, r3
 8001916:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800191a:	edc7 7a1a 	vstr	s15, [r7, #104]	@ 0x68
            osMutexRelease (vRefmVMutex);
 800191e:	4b9d      	ldr	r3, [pc, #628]	@ (8001b94 <ADC2MeasTask+0x2cc>)
 8001920:	681b      	ldr	r3, [r3, #0]
 8001922:	4618      	mov	r0, r3
 8001924:	f00e f853 	bl	800f9ce <osMutexRelease>
        }
        gainCorrection            = gainCorrection / EXT_VREF_mV;
 8001928:	ed97 7a1a 	vldr	s14, [r7, #104]	@ 0x68
 800192c:	eddf 6a9b 	vldr	s13, [pc, #620]	@ 8001b9c <ADC2MeasTask+0x2d4>
 8001930:	eec7 7a26 	vdiv.f32	s15, s14, s13
 8001934:	edc7 7a1a 	vstr	s15, [r7, #104]	@ 0x68
        float ref[CURRENTS_COUNT] = { 0 };
 8001938:	f04f 0300 	mov.w	r3, #0
 800193c:	60fb      	str	r3, [r7, #12]
        if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) {
 800193e:	4b98      	ldr	r3, [pc, #608]	@ (8001ba0 <ADC2MeasTask+0x2d8>)
 8001940:	681b      	ldr	r3, [r3, #0]
 8001942:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8001946:	4618      	mov	r0, r3
 8001948:	f00d fff6 	bl	800f938 <osMutexAcquire>
 800194c:	4603      	mov	r3, r0
 800194e:	2b00      	cmp	r3, #0
 8001950:	d122      	bne.n	8001998 <ADC2MeasTask+0xd0>
            for (uint8_t i = 0; i < CURRENTS_COUNT; i++) {
 8001952:	2300      	movs	r3, #0
 8001954:	f887 3067 	strb.w	r3, [r7, #103]	@ 0x67
 8001958:	e015      	b.n	8001986 <ADC2MeasTask+0xbe>
                ref[i] = (float)ILxRef[i];
 800195a:	f897 3067 	ldrb.w	r3, [r7, #103]	@ 0x67
 800195e:	4a91      	ldr	r2, [pc, #580]	@ (8001ba4 <ADC2MeasTask+0x2dc>)
 8001960:	f832 2013 	ldrh.w	r2, [r2, r3, lsl #1]
 8001964:	f897 3067 	ldrb.w	r3, [r7, #103]	@ 0x67
 8001968:	ee07 2a90 	vmov	s15, r2
 800196c:	eef8 7a67 	vcvt.f32.u32	s15, s15
 8001970:	009b      	lsls	r3, r3, #2
 8001972:	3370      	adds	r3, #112	@ 0x70
 8001974:	443b      	add	r3, r7
 8001976:	3b64      	subs	r3, #100	@ 0x64
 8001978:	edc3 7a00 	vstr	s15, [r3]
            for (uint8_t i = 0; i < CURRENTS_COUNT; i++) {
 800197c:	f897 3067 	ldrb.w	r3, [r7, #103]	@ 0x67
 8001980:	3301      	adds	r3, #1
 8001982:	f887 3067 	strb.w	r3, [r7, #103]	@ 0x67
 8001986:	f897 3067 	ldrb.w	r3, [r7, #103]	@ 0x67
 800198a:	2b00      	cmp	r3, #0
 800198c:	d0e5      	beq.n	800195a <ADC2MeasTask+0x92>
            }
            osMutexRelease (ILxRefMutex);
 800198e:	4b84      	ldr	r3, [pc, #528]	@ (8001ba0 <ADC2MeasTask+0x2d8>)
 8001990:	681b      	ldr	r3, [r3, #0]
 8001992:	4618      	mov	r0, r3
 8001994:	f00e f81b 	bl	800f9ce <osMutexRelease>
        }
        for (uint8_t i = 0; i < CURRENTS_COUNT; i++) {
 8001998:	2300      	movs	r3, #0
 800199a:	f887 3066 	strb.w	r3, [r7, #102]	@ 0x66
 800199e:	e0db      	b.n	8001b58 <ADC2MeasTask+0x290>
            float adcVal               = (float)adcData.adcDataBuffer[i];
 80019a0:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 80019a4:	005b      	lsls	r3, r3, #1
 80019a6:	3370      	adds	r3, #112	@ 0x70
 80019a8:	443b      	add	r3, r7
 80019aa:	f833 3c60 	ldrh.w	r3, [r3, #-96]
 80019ae:	ee07 3a90 	vmov	s15, r3
 80019b2:	eef8 7a67 	vcvt.f32.u32	s15, s15
 80019b6:	edc7 7a18 	vstr	s15, [r7, #96]	@ 0x60
            float val                  = (adcVal - ref[i]) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset;
 80019ba:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 80019be:	009b      	lsls	r3, r3, #2
 80019c0:	3370      	adds	r3, #112	@ 0x70
 80019c2:	443b      	add	r3, r7
 80019c4:	3b64      	subs	r3, #100	@ 0x64
 80019c6:	edd3 7a00 	vldr	s15, [r3]
 80019ca:	ed97 7a18 	vldr	s14, [r7, #96]	@ 0x60
 80019ce:	ee77 7a67 	vsub.f32	s15, s14, s15
 80019d2:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 80019d6:	eeb0 6b08 	vmov.f64	d6, #8	@ 0x40400000  3.0
 80019da:	ee27 6b06 	vmul.f64	d6, d7, d6
 80019de:	ed9f 5b68 	vldr	d5, [pc, #416]	@ 8001b80 <ADC2MeasTask+0x2b8>
 80019e2:	ee86 7b05 	vdiv.f64	d7, d6, d5
 80019e6:	ed9f 6b68 	vldr	d6, [pc, #416]	@ 8001b88 <ADC2MeasTask+0x2c0>
 80019ea:	ee27 6b06 	vmul.f64	d6, d7, d6
 80019ee:	edd7 7a1a 	vldr	s15, [r7, #104]	@ 0x68
 80019f2:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 80019f6:	ee26 6b07 	vmul.f64	d6, d6, d7
 80019fa:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 80019fe:	4a6a      	ldr	r2, [pc, #424]	@ (8001ba8 <ADC2MeasTask+0x2e0>)
 8001a00:	00db      	lsls	r3, r3, #3
 8001a02:	4413      	add	r3, r2
 8001a04:	edd3 7a00 	vldr	s15, [r3]
 8001a08:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 8001a0c:	ee26 6b07 	vmul.f64	d6, d6, d7
 8001a10:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8001a14:	4a64      	ldr	r2, [pc, #400]	@ (8001ba8 <ADC2MeasTask+0x2e0>)
 8001a16:	00db      	lsls	r3, r3, #3
 8001a18:	4413      	add	r3, r2
 8001a1a:	3304      	adds	r3, #4
 8001a1c:	edd3 7a00 	vldr	s15, [r3]
 8001a20:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 8001a24:	ee36 7b07 	vadd.f64	d7, d6, d7
 8001a28:	eef7 7bc7 	vcvt.f32.f64	s15, d7
 8001a2c:	edc7 7a17 	vstr	s15, [r7, #92]	@ 0x5c
            circBuffer[i][circBuffPos] = val;
 8001a30:	f897 2066 	ldrb.w	r2, [r7, #102]	@ 0x66
 8001a34:	4613      	mov	r3, r2
 8001a36:	009b      	lsls	r3, r3, #2
 8001a38:	4413      	add	r3, r2
 8001a3a:	005b      	lsls	r3, r3, #1
 8001a3c:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
 8001a3e:	4413      	add	r3, r2
 8001a40:	009b      	lsls	r3, r3, #2
 8001a42:	3370      	adds	r3, #112	@ 0x70
 8001a44:	443b      	add	r3, r7
 8001a46:	3b3c      	subs	r3, #60	@ 0x3c
 8001a48:	6dfa      	ldr	r2, [r7, #92]	@ 0x5c
 8001a4a:	601a      	str	r2, [r3, #0]
            rms[i]                     = 0.0;
 8001a4c:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8001a50:	009b      	lsls	r3, r3, #2
 8001a52:	3370      	adds	r3, #112	@ 0x70
 8001a54:	443b      	add	r3, r7
 8001a56:	3b40      	subs	r3, #64	@ 0x40
 8001a58:	f04f 0200 	mov.w	r2, #0
 8001a5c:	601a      	str	r2, [r3, #0]
            for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) {
 8001a5e:	2300      	movs	r3, #0
 8001a60:	f887 3065 	strb.w	r3, [r7, #101]	@ 0x65
 8001a64:	e025      	b.n	8001ab2 <ADC2MeasTask+0x1ea>
                rms[i] += circBuffer[i][c];
 8001a66:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8001a6a:	009b      	lsls	r3, r3, #2
 8001a6c:	3370      	adds	r3, #112	@ 0x70
 8001a6e:	443b      	add	r3, r7
 8001a70:	3b40      	subs	r3, #64	@ 0x40
 8001a72:	ed93 7a00 	vldr	s14, [r3]
 8001a76:	f897 2066 	ldrb.w	r2, [r7, #102]	@ 0x66
 8001a7a:	f897 1065 	ldrb.w	r1, [r7, #101]	@ 0x65
 8001a7e:	4613      	mov	r3, r2
 8001a80:	009b      	lsls	r3, r3, #2
 8001a82:	4413      	add	r3, r2
 8001a84:	005b      	lsls	r3, r3, #1
 8001a86:	440b      	add	r3, r1
 8001a88:	009b      	lsls	r3, r3, #2
 8001a8a:	3370      	adds	r3, #112	@ 0x70
 8001a8c:	443b      	add	r3, r7
 8001a8e:	3b3c      	subs	r3, #60	@ 0x3c
 8001a90:	edd3 7a00 	vldr	s15, [r3]
 8001a94:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8001a98:	ee77 7a27 	vadd.f32	s15, s14, s15
 8001a9c:	009b      	lsls	r3, r3, #2
 8001a9e:	3370      	adds	r3, #112	@ 0x70
 8001aa0:	443b      	add	r3, r7
 8001aa2:	3b40      	subs	r3, #64	@ 0x40
 8001aa4:	edc3 7a00 	vstr	s15, [r3]
            for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) {
 8001aa8:	f897 3065 	ldrb.w	r3, [r7, #101]	@ 0x65
 8001aac:	3301      	adds	r3, #1
 8001aae:	f887 3065 	strb.w	r3, [r7, #101]	@ 0x65
 8001ab2:	f897 3065 	ldrb.w	r3, [r7, #101]	@ 0x65
 8001ab6:	2b09      	cmp	r3, #9
 8001ab8:	d9d5      	bls.n	8001a66 <ADC2MeasTask+0x19e>
            }
            rms[i] = rms[i] / CIRC_BUFF_LEN;
 8001aba:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8001abe:	009b      	lsls	r3, r3, #2
 8001ac0:	3370      	adds	r3, #112	@ 0x70
 8001ac2:	443b      	add	r3, r7
 8001ac4:	3b40      	subs	r3, #64	@ 0x40
 8001ac6:	ed93 7a00 	vldr	s14, [r3]
 8001aca:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8001ace:	eef2 6a04 	vmov.f32	s13, #36	@ 0x41200000  10.0
 8001ad2:	eec7 7a26 	vdiv.f32	s15, s14, s13
 8001ad6:	009b      	lsls	r3, r3, #2
 8001ad8:	3370      	adds	r3, #112	@ 0x70
 8001ada:	443b      	add	r3, r7
 8001adc:	3b40      	subs	r3, #64	@ 0x40
 8001ade:	edc3 7a00 	vstr	s15, [r3]
            if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
 8001ae2:	4b32      	ldr	r3, [pc, #200]	@ (8001bac <ADC2MeasTask+0x2e4>)
 8001ae4:	681b      	ldr	r3, [r3, #0]
 8001ae6:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8001aea:	4618      	mov	r0, r3
 8001aec:	f00d ff24 	bl	800f938 <osMutexAcquire>
 8001af0:	4603      	mov	r3, r0
 8001af2:	2b00      	cmp	r3, #0
 8001af4:	d12b      	bne.n	8001b4e <ADC2MeasTask+0x286>
                if (resMeasurements.currentPeak[i] < val) {
 8001af6:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8001afa:	4a2d      	ldr	r2, [pc, #180]	@ (8001bb0 <ADC2MeasTask+0x2e8>)
 8001afc:	3308      	adds	r3, #8
 8001afe:	009b      	lsls	r3, r3, #2
 8001b00:	4413      	add	r3, r2
 8001b02:	3304      	adds	r3, #4
 8001b04:	edd3 7a00 	vldr	s15, [r3]
 8001b08:	ed97 7a17 	vldr	s14, [r7, #92]	@ 0x5c
 8001b0c:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8001b10:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001b14:	dd08      	ble.n	8001b28 <ADC2MeasTask+0x260>
                    resMeasurements.currentPeak[i] = val;
 8001b16:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8001b1a:	4a25      	ldr	r2, [pc, #148]	@ (8001bb0 <ADC2MeasTask+0x2e8>)
 8001b1c:	3308      	adds	r3, #8
 8001b1e:	009b      	lsls	r3, r3, #2
 8001b20:	4413      	add	r3, r2
 8001b22:	3304      	adds	r3, #4
 8001b24:	6dfa      	ldr	r2, [r7, #92]	@ 0x5c
 8001b26:	601a      	str	r2, [r3, #0]
                }
                resMeasurements.currentRMS[i] = rms[i];
 8001b28:	f897 2066 	ldrb.w	r2, [r7, #102]	@ 0x66
 8001b2c:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8001b30:	0092      	lsls	r2, r2, #2
 8001b32:	3270      	adds	r2, #112	@ 0x70
 8001b34:	443a      	add	r2, r7
 8001b36:	3a40      	subs	r2, #64	@ 0x40
 8001b38:	6812      	ldr	r2, [r2, #0]
 8001b3a:	491d      	ldr	r1, [pc, #116]	@ (8001bb0 <ADC2MeasTask+0x2e8>)
 8001b3c:	3306      	adds	r3, #6
 8001b3e:	009b      	lsls	r3, r3, #2
 8001b40:	440b      	add	r3, r1
 8001b42:	601a      	str	r2, [r3, #0]
                osMutexRelease (resMeasurementsMutex);
 8001b44:	4b19      	ldr	r3, [pc, #100]	@ (8001bac <ADC2MeasTask+0x2e4>)
 8001b46:	681b      	ldr	r3, [r3, #0]
 8001b48:	4618      	mov	r0, r3
 8001b4a:	f00d ff40 	bl	800f9ce <osMutexRelease>
        for (uint8_t i = 0; i < CURRENTS_COUNT; i++) {
 8001b4e:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8001b52:	3301      	adds	r3, #1
 8001b54:	f887 3066 	strb.w	r3, [r7, #102]	@ 0x66
 8001b58:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8001b5c:	2b00      	cmp	r3, #0
 8001b5e:	f43f af1f 	beq.w	80019a0 <ADC2MeasTask+0xd8>
            }
        }
        ++circBuffPos;
 8001b62:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8001b64:	3301      	adds	r3, #1
 8001b66:	66fb      	str	r3, [r7, #108]	@ 0x6c
        circBuffPos = circBuffPos % CIRC_BUFF_LEN;
 8001b68:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
 8001b6a:	4b12      	ldr	r3, [pc, #72]	@ (8001bb4 <ADC2MeasTask+0x2ec>)
 8001b6c:	fba3 1302 	umull	r1, r3, r3, r2
 8001b70:	08d9      	lsrs	r1, r3, #3
 8001b72:	460b      	mov	r3, r1
 8001b74:	009b      	lsls	r3, r3, #2
 8001b76:	440b      	add	r3, r1
 8001b78:	005b      	lsls	r3, r3, #1
 8001b7a:	1ad3      	subs	r3, r2, r3
 8001b7c:	66fb      	str	r3, [r7, #108]	@ 0x6c
    while (pdTRUE) {
 8001b7e:	e6b3      	b.n	80018e8 <ADC2MeasTask+0x20>
 8001b80:	00000000 	.word	0x00000000
 8001b84:	40efffe0 	.word	0x40efffe0
 8001b88:	83e425af 	.word	0x83e425af
 8001b8c:	401e4d9e 	.word	0x401e4d9e
 8001b90:	24000594 	.word	0x24000594
 8001b94:	2400059c 	.word	0x2400059c
 8001b98:	24000030 	.word	0x24000030
 8001b9c:	453b8000 	.word	0x453b8000
 8001ba0:	240005a8 	.word	0x240005a8
 8001ba4:	24000610 	.word	0x24000610
 8001ba8:	24000018 	.word	0x24000018
 8001bac:	240005a0 	.word	0x240005a0
 8001bb0:	240005ac 	.word	0x240005ac
 8001bb4:	cccccccd 	.word	0xcccccccd

08001bb8 <ADC3MeasTask>:
    }
}

void ADC3MeasTask (void* arg) {
 8001bb8:	b580      	push	{r7, lr}
 8001bba:	b08c      	sub	sp, #48	@ 0x30
 8001bbc:	af00      	add	r7, sp, #0
 8001bbe:	6078      	str	r0, [r7, #4]
    ADC3_Data adcData = { 0 };
 8001bc0:	f107 030c 	add.w	r3, r7, #12
 8001bc4:	2220      	movs	r2, #32
 8001bc6:	2100      	movs	r1, #0
 8001bc8:	4618      	mov	r0, r3
 8001bca:	f011 fe0c 	bl	80137e6 <memset>
    while (pdTRUE) {
        osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever);
 8001bce:	4b13      	ldr	r3, [pc, #76]	@ (8001c1c <ADC3MeasTask+0x64>)
 8001bd0:	6818      	ldr	r0, [r3, #0]
 8001bd2:	f107 010c 	add.w	r1, r7, #12
 8001bd6:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8001bda:	2200      	movs	r2, #0
 8001bdc:	f00e f808 	bl	800fbf0 <osMessageQueueGet>
        uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B);
 8001be0:	4b0f      	ldr	r3, [pc, #60]	@ (8001c20 <ADC3MeasTask+0x68>)
 8001be2:	881b      	ldrh	r3, [r3, #0]
 8001be4:	461a      	mov	r2, r3
 8001be6:	f640 43e4 	movw	r3, #3300	@ 0xce4
 8001bea:	fb02 f303 	mul.w	r3, r2, r3
 8001bee:	8aba      	ldrh	r2, [r7, #20]
 8001bf0:	fbb3 f3f2 	udiv	r3, r3, r2
 8001bf4:	62fb      	str	r3, [r7, #44]	@ 0x2c
        if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) {
 8001bf6:	4b0b      	ldr	r3, [pc, #44]	@ (8001c24 <ADC3MeasTask+0x6c>)
 8001bf8:	681b      	ldr	r3, [r3, #0]
 8001bfa:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8001bfe:	4618      	mov	r0, r3
 8001c00:	f00d fe9a 	bl	800f938 <osMutexAcquire>
 8001c04:	4603      	mov	r3, r0
 8001c06:	2b00      	cmp	r3, #0
 8001c08:	d1e1      	bne.n	8001bce <ADC3MeasTask+0x16>
            vRefmV = vRef;
 8001c0a:	4a07      	ldr	r2, [pc, #28]	@ (8001c28 <ADC3MeasTask+0x70>)
 8001c0c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001c0e:	6013      	str	r3, [r2, #0]
            osMutexRelease (vRefmVMutex);
 8001c10:	4b04      	ldr	r3, [pc, #16]	@ (8001c24 <ADC3MeasTask+0x6c>)
 8001c12:	681b      	ldr	r3, [r3, #0]
 8001c14:	4618      	mov	r0, r3
 8001c16:	f00d feda 	bl	800f9ce <osMutexRelease>
    while (pdTRUE) {
 8001c1a:	e7d8      	b.n	8001bce <ADC3MeasTask+0x16>
 8001c1c:	24000598 	.word	0x24000598
 8001c20:	1ff1e860 	.word	0x1ff1e860
 8001c24:	2400059c 	.word	0x2400059c
 8001c28:	24000030 	.word	0x24000030

08001c2c <DbgLEDToggle>:
{
	HAL_GPIO_WritePin(GPIOD, ledNumber, GPIO_PIN_RESET);
}

void DbgLEDToggle(uint8_t ledNumber)
{
 8001c2c:	b580      	push	{r7, lr}
 8001c2e:	b082      	sub	sp, #8
 8001c30:	af00      	add	r7, sp, #0
 8001c32:	4603      	mov	r3, r0
 8001c34:	71fb      	strb	r3, [r7, #7]
	HAL_GPIO_TogglePin(GPIOD, ledNumber);
 8001c36:	79fb      	ldrb	r3, [r7, #7]
 8001c38:	b29b      	uxth	r3, r3
 8001c3a:	4619      	mov	r1, r3
 8001c3c:	4803      	ldr	r0, [pc, #12]	@ (8001c4c <DbgLEDToggle+0x20>)
 8001c3e:	f006 fbdc 	bl	80083fa <HAL_GPIO_TogglePin>
}
 8001c42:	bf00      	nop
 8001c44:	3708      	adds	r7, #8
 8001c46:	46bd      	mov	sp, r7
 8001c48:	bd80      	pop	{r7, pc}
 8001c4a:	bf00      	nop
 8001c4c:	58020c00 	.word	0x58020c00

08001c50 <EnableCurrentSensors>:

void EnableCurrentSensors(void)
{
 8001c50:	b580      	push	{r7, lr}
 8001c52:	af00      	add	r7, sp, #0
	HAL_GPIO_WritePin(GPIOE, MCU_CS_PWR_EN, GPIO_PIN_SET);
 8001c54:	2201      	movs	r2, #1
 8001c56:	f44f 4100 	mov.w	r1, #32768	@ 0x8000
 8001c5a:	4802      	ldr	r0, [pc, #8]	@ (8001c64 <EnableCurrentSensors+0x14>)
 8001c5c:	f006 fbb4 	bl	80083c8 <HAL_GPIO_WritePin>
}
 8001c60:	bf00      	nop
 8001c62:	bd80      	pop	{r7, pc}
 8001c64:	58021000 	.word	0x58021000

08001c68 <SelectCurrentSensorGain>:
{
	HAL_GPIO_WritePin(GPIOE, MCU_CS_PWR_EN, GPIO_PIN_RESET);
}

void SelectCurrentSensorGain(CurrentSensor sensor, CurrentSensorGain gain)
{
 8001c68:	b580      	push	{r7, lr}
 8001c6a:	b084      	sub	sp, #16
 8001c6c:	af00      	add	r7, sp, #0
 8001c6e:	4603      	mov	r3, r0
 8001c70:	460a      	mov	r2, r1
 8001c72:	71fb      	strb	r3, [r7, #7]
 8001c74:	4613      	mov	r3, r2
 8001c76:	71bb      	strb	r3, [r7, #6]
	uint8_t gpioOffset = 0;
 8001c78:	2300      	movs	r3, #0
 8001c7a:	73fb      	strb	r3, [r7, #15]
	switch(sensor)
 8001c7c:	79fb      	ldrb	r3, [r7, #7]
 8001c7e:	2b02      	cmp	r3, #2
 8001c80:	d00c      	beq.n	8001c9c <SelectCurrentSensorGain+0x34>
 8001c82:	2b02      	cmp	r3, #2
 8001c84:	dc0d      	bgt.n	8001ca2 <SelectCurrentSensorGain+0x3a>
 8001c86:	2b00      	cmp	r3, #0
 8001c88:	d002      	beq.n	8001c90 <SelectCurrentSensorGain+0x28>
 8001c8a:	2b01      	cmp	r3, #1
 8001c8c:	d003      	beq.n	8001c96 <SelectCurrentSensorGain+0x2e>
		break;
	case CurrentSensorL3:
		gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET;
		break;
	default:
		break;
 8001c8e:	e008      	b.n	8001ca2 <SelectCurrentSensorGain+0x3a>
		gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET;
 8001c90:	2307      	movs	r3, #7
 8001c92:	73fb      	strb	r3, [r7, #15]
		break;
 8001c94:	e006      	b.n	8001ca4 <SelectCurrentSensorGain+0x3c>
		gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET;
 8001c96:	2309      	movs	r3, #9
 8001c98:	73fb      	strb	r3, [r7, #15]
		break;
 8001c9a:	e003      	b.n	8001ca4 <SelectCurrentSensorGain+0x3c>
		gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET;
 8001c9c:	230d      	movs	r3, #13
 8001c9e:	73fb      	strb	r3, [r7, #15]
		break;
 8001ca0:	e000      	b.n	8001ca4 <SelectCurrentSensorGain+0x3c>
		break;
 8001ca2:	bf00      	nop
	}
	if(gpioOffset > 0)
 8001ca4:	7bfb      	ldrb	r3, [r7, #15]
 8001ca6:	2b00      	cmp	r3, #0
 8001ca8:	d023      	beq.n	8001cf2 <SelectCurrentSensorGain+0x8a>
	{
		uint16_t gain0Gpio = 1 << gpioOffset;
 8001caa:	7bfb      	ldrb	r3, [r7, #15]
 8001cac:	2201      	movs	r2, #1
 8001cae:	fa02 f303 	lsl.w	r3, r2, r3
 8001cb2:	81bb      	strh	r3, [r7, #12]
		uint16_t gain1Gpio = 1 << (gpioOffset + 1);
 8001cb4:	7bfb      	ldrb	r3, [r7, #15]
 8001cb6:	3301      	adds	r3, #1
 8001cb8:	2201      	movs	r2, #1
 8001cba:	fa02 f303 	lsl.w	r3, r2, r3
 8001cbe:	817b      	strh	r3, [r7, #10]
		uint16_t gpioState = ((uint16_t)gain) & 0x0001;
 8001cc0:	79bb      	ldrb	r3, [r7, #6]
 8001cc2:	b29b      	uxth	r3, r3
 8001cc4:	f003 0301 	and.w	r3, r3, #1
 8001cc8:	813b      	strh	r3, [r7, #8]
		HAL_GPIO_WritePin(GPIOE, gain0Gpio, gpioState);
 8001cca:	893b      	ldrh	r3, [r7, #8]
 8001ccc:	b2da      	uxtb	r2, r3
 8001cce:	89bb      	ldrh	r3, [r7, #12]
 8001cd0:	4619      	mov	r1, r3
 8001cd2:	480a      	ldr	r0, [pc, #40]	@ (8001cfc <SelectCurrentSensorGain+0x94>)
 8001cd4:	f006 fb78 	bl	80083c8 <HAL_GPIO_WritePin>
		gpioState = (((uint16_t)gain) >> 1) & 0x0001;
 8001cd8:	79bb      	ldrb	r3, [r7, #6]
 8001cda:	085b      	lsrs	r3, r3, #1
 8001cdc:	b2db      	uxtb	r3, r3
 8001cde:	f003 0301 	and.w	r3, r3, #1
 8001ce2:	813b      	strh	r3, [r7, #8]
		HAL_GPIO_WritePin(GPIOE, gain1Gpio, gpioState);
 8001ce4:	893b      	ldrh	r3, [r7, #8]
 8001ce6:	b2da      	uxtb	r2, r3
 8001ce8:	897b      	ldrh	r3, [r7, #10]
 8001cea:	4619      	mov	r1, r3
 8001cec:	4803      	ldr	r0, [pc, #12]	@ (8001cfc <SelectCurrentSensorGain+0x94>)
 8001cee:	f006 fb6b 	bl	80083c8 <HAL_GPIO_WritePin>
	}
}
 8001cf2:	bf00      	nop
 8001cf4:	3710      	adds	r7, #16
 8001cf6:	46bd      	mov	sp, r7
 8001cf8:	bd80      	pop	{r7, pc}
 8001cfa:	bf00      	nop
 8001cfc:	58021000 	.word	0x58021000

08001d00 <WriteDataToBuffer>:
        buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF);
    }
    *buffPos = newBuffPos;
}

void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) {
 8001d00:	b480      	push	{r7}
 8001d02:	b089      	sub	sp, #36	@ 0x24
 8001d04:	af00      	add	r7, sp, #0
 8001d06:	60f8      	str	r0, [r7, #12]
 8001d08:	60b9      	str	r1, [r7, #8]
 8001d0a:	607a      	str	r2, [r7, #4]
 8001d0c:	70fb      	strb	r3, [r7, #3]
    uint32_t* uDataPtr = data;
 8001d0e:	687b      	ldr	r3, [r7, #4]
 8001d10:	61bb      	str	r3, [r7, #24]
    uint32_t uData     = *uDataPtr;
 8001d12:	69bb      	ldr	r3, [r7, #24]
 8001d14:	681b      	ldr	r3, [r3, #0]
 8001d16:	617b      	str	r3, [r7, #20]
    uint8_t i          = 0;
 8001d18:	2300      	movs	r3, #0
 8001d1a:	77fb      	strb	r3, [r7, #31]
    uint8_t newBuffPos = *buffPos;
 8001d1c:	68bb      	ldr	r3, [r7, #8]
 8001d1e:	881b      	ldrh	r3, [r3, #0]
 8001d20:	77bb      	strb	r3, [r7, #30]
    for (i = 0; i < dataSize; i++) {
 8001d22:	2300      	movs	r3, #0
 8001d24:	77fb      	strb	r3, [r7, #31]
 8001d26:	e00e      	b.n	8001d46 <WriteDataToBuffer+0x46>
        buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF);
 8001d28:	7ffb      	ldrb	r3, [r7, #31]
 8001d2a:	00db      	lsls	r3, r3, #3
 8001d2c:	697a      	ldr	r2, [r7, #20]
 8001d2e:	40da      	lsrs	r2, r3
 8001d30:	7fbb      	ldrb	r3, [r7, #30]
 8001d32:	1c59      	adds	r1, r3, #1
 8001d34:	77b9      	strb	r1, [r7, #30]
 8001d36:	4619      	mov	r1, r3
 8001d38:	68fb      	ldr	r3, [r7, #12]
 8001d3a:	440b      	add	r3, r1
 8001d3c:	b2d2      	uxtb	r2, r2
 8001d3e:	701a      	strb	r2, [r3, #0]
    for (i = 0; i < dataSize; i++) {
 8001d40:	7ffb      	ldrb	r3, [r7, #31]
 8001d42:	3301      	adds	r3, #1
 8001d44:	77fb      	strb	r3, [r7, #31]
 8001d46:	7ffa      	ldrb	r2, [r7, #31]
 8001d48:	78fb      	ldrb	r3, [r7, #3]
 8001d4a:	429a      	cmp	r2, r3
 8001d4c:	d3ec      	bcc.n	8001d28 <WriteDataToBuffer+0x28>
    }
    *buffPos = newBuffPos;
 8001d4e:	7fbb      	ldrb	r3, [r7, #30]
 8001d50:	b29a      	uxth	r2, r3
 8001d52:	68bb      	ldr	r3, [r7, #8]
 8001d54:	801a      	strh	r2, [r3, #0]
}
 8001d56:	bf00      	nop
 8001d58:	3724      	adds	r7, #36	@ 0x24
 8001d5a:	46bd      	mov	sp, r7
 8001d5c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001d60:	4770      	bx	lr
	...

08001d64 <PrepareRespFrame>:
    txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc);

    return txBufferPos;
}

uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) {
 8001d64:	b580      	push	{r7, lr}
 8001d66:	b084      	sub	sp, #16
 8001d68:	af00      	add	r7, sp, #0
 8001d6a:	6078      	str	r0, [r7, #4]
 8001d6c:	4608      	mov	r0, r1
 8001d6e:	4611      	mov	r1, r2
 8001d70:	461a      	mov	r2, r3
 8001d72:	4603      	mov	r3, r0
 8001d74:	807b      	strh	r3, [r7, #2]
 8001d76:	460b      	mov	r3, r1
 8001d78:	707b      	strb	r3, [r7, #1]
 8001d7a:	4613      	mov	r3, r2
 8001d7c:	703b      	strb	r3, [r7, #0]
    uint16_t crc         = 0;
 8001d7e:	2300      	movs	r3, #0
 8001d80:	81bb      	strh	r3, [r7, #12]
    uint16_t txBufferPos = 0;
 8001d82:	2300      	movs	r3, #0
 8001d84:	81fb      	strh	r3, [r7, #14]
    uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response
 8001d86:	787b      	ldrb	r3, [r7, #1]
 8001d88:	b21a      	sxth	r2, r3
 8001d8a:	4b43      	ldr	r3, [pc, #268]	@ (8001e98 <PrepareRespFrame+0x134>)
 8001d8c:	4313      	orrs	r3, r2
 8001d8e:	b21b      	sxth	r3, r3
 8001d90:	817b      	strh	r3, [r7, #10]

    memset (txBuffer, 0x00, dataLength);
 8001d92:	8bbb      	ldrh	r3, [r7, #28]
 8001d94:	461a      	mov	r2, r3
 8001d96:	2100      	movs	r1, #0
 8001d98:	6878      	ldr	r0, [r7, #4]
 8001d9a:	f011 fd24 	bl	80137e6 <memset>
    txBuffer[txBufferPos++] = FRAME_INDICATOR;
 8001d9e:	89fb      	ldrh	r3, [r7, #14]
 8001da0:	1c5a      	adds	r2, r3, #1
 8001da2:	81fa      	strh	r2, [r7, #14]
 8001da4:	461a      	mov	r2, r3
 8001da6:	687b      	ldr	r3, [r7, #4]
 8001da8:	4413      	add	r3, r2
 8001daa:	22aa      	movs	r2, #170	@ 0xaa
 8001dac:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId);
 8001dae:	89fb      	ldrh	r3, [r7, #14]
 8001db0:	1c5a      	adds	r2, r3, #1
 8001db2:	81fa      	strh	r2, [r7, #14]
 8001db4:	461a      	mov	r2, r3
 8001db6:	687b      	ldr	r3, [r7, #4]
 8001db8:	4413      	add	r3, r2
 8001dba:	887a      	ldrh	r2, [r7, #2]
 8001dbc:	b2d2      	uxtb	r2, r2
 8001dbe:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId);
 8001dc0:	887b      	ldrh	r3, [r7, #2]
 8001dc2:	0a1b      	lsrs	r3, r3, #8
 8001dc4:	b29a      	uxth	r2, r3
 8001dc6:	89fb      	ldrh	r3, [r7, #14]
 8001dc8:	1c59      	adds	r1, r3, #1
 8001dca:	81f9      	strh	r1, [r7, #14]
 8001dcc:	4619      	mov	r1, r3
 8001dce:	687b      	ldr	r3, [r7, #4]
 8001dd0:	440b      	add	r3, r1
 8001dd2:	b2d2      	uxtb	r2, r2
 8001dd4:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd);
 8001dd6:	89fb      	ldrh	r3, [r7, #14]
 8001dd8:	1c5a      	adds	r2, r3, #1
 8001dda:	81fa      	strh	r2, [r7, #14]
 8001ddc:	461a      	mov	r2, r3
 8001dde:	687b      	ldr	r3, [r7, #4]
 8001de0:	4413      	add	r3, r2
 8001de2:	897a      	ldrh	r2, [r7, #10]
 8001de4:	b2d2      	uxtb	r2, r2
 8001de6:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd);
 8001de8:	897b      	ldrh	r3, [r7, #10]
 8001dea:	0a1b      	lsrs	r3, r3, #8
 8001dec:	b29a      	uxth	r2, r3
 8001dee:	89fb      	ldrh	r3, [r7, #14]
 8001df0:	1c59      	adds	r1, r3, #1
 8001df2:	81f9      	strh	r1, [r7, #14]
 8001df4:	4619      	mov	r1, r3
 8001df6:	687b      	ldr	r3, [r7, #4]
 8001df8:	440b      	add	r3, r1
 8001dfa:	b2d2      	uxtb	r2, r2
 8001dfc:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength);
 8001dfe:	89fb      	ldrh	r3, [r7, #14]
 8001e00:	1c5a      	adds	r2, r3, #1
 8001e02:	81fa      	strh	r2, [r7, #14]
 8001e04:	461a      	mov	r2, r3
 8001e06:	687b      	ldr	r3, [r7, #4]
 8001e08:	4413      	add	r3, r2
 8001e0a:	8bba      	ldrh	r2, [r7, #28]
 8001e0c:	b2d2      	uxtb	r2, r2
 8001e0e:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength);
 8001e10:	8bbb      	ldrh	r3, [r7, #28]
 8001e12:	0a1b      	lsrs	r3, r3, #8
 8001e14:	b29a      	uxth	r2, r3
 8001e16:	89fb      	ldrh	r3, [r7, #14]
 8001e18:	1c59      	adds	r1, r3, #1
 8001e1a:	81f9      	strh	r1, [r7, #14]
 8001e1c:	4619      	mov	r1, r3
 8001e1e:	687b      	ldr	r3, [r7, #4]
 8001e20:	440b      	add	r3, r1
 8001e22:	b2d2      	uxtb	r2, r2
 8001e24:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = (uint8_t)respStatus;
 8001e26:	89fb      	ldrh	r3, [r7, #14]
 8001e28:	1c5a      	adds	r2, r3, #1
 8001e2a:	81fa      	strh	r2, [r7, #14]
 8001e2c:	461a      	mov	r2, r3
 8001e2e:	687b      	ldr	r3, [r7, #4]
 8001e30:	4413      	add	r3, r2
 8001e32:	783a      	ldrb	r2, [r7, #0]
 8001e34:	701a      	strb	r2, [r3, #0]
    if (dataLength > 0) {
 8001e36:	8bbb      	ldrh	r3, [r7, #28]
 8001e38:	2b00      	cmp	r3, #0
 8001e3a:	d00b      	beq.n	8001e54 <PrepareRespFrame+0xf0>
        memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength);
 8001e3c:	89fb      	ldrh	r3, [r7, #14]
 8001e3e:	687a      	ldr	r2, [r7, #4]
 8001e40:	4413      	add	r3, r2
 8001e42:	8bba      	ldrh	r2, [r7, #28]
 8001e44:	69b9      	ldr	r1, [r7, #24]
 8001e46:	4618      	mov	r0, r3
 8001e48:	f011 fd9f 	bl	801398a <memcpy>
        txBufferPos += dataLength;
 8001e4c:	89fa      	ldrh	r2, [r7, #14]
 8001e4e:	8bbb      	ldrh	r3, [r7, #28]
 8001e50:	4413      	add	r3, r2
 8001e52:	81fb      	strh	r3, [r7, #14]
    }
    crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos);
 8001e54:	89fb      	ldrh	r3, [r7, #14]
 8001e56:	461a      	mov	r2, r3
 8001e58:	6879      	ldr	r1, [r7, #4]
 8001e5a:	4810      	ldr	r0, [pc, #64]	@ (8001e9c <PrepareRespFrame+0x138>)
 8001e5c:	f003 f926 	bl	80050ac <HAL_CRC_Calculate>
 8001e60:	4603      	mov	r3, r0
 8001e62:	81bb      	strh	r3, [r7, #12]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc);
 8001e64:	89fb      	ldrh	r3, [r7, #14]
 8001e66:	1c5a      	adds	r2, r3, #1
 8001e68:	81fa      	strh	r2, [r7, #14]
 8001e6a:	461a      	mov	r2, r3
 8001e6c:	687b      	ldr	r3, [r7, #4]
 8001e6e:	4413      	add	r3, r2
 8001e70:	89ba      	ldrh	r2, [r7, #12]
 8001e72:	b2d2      	uxtb	r2, r2
 8001e74:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc);
 8001e76:	89bb      	ldrh	r3, [r7, #12]
 8001e78:	0a1b      	lsrs	r3, r3, #8
 8001e7a:	b29a      	uxth	r2, r3
 8001e7c:	89fb      	ldrh	r3, [r7, #14]
 8001e7e:	1c59      	adds	r1, r3, #1
 8001e80:	81f9      	strh	r1, [r7, #14]
 8001e82:	4619      	mov	r1, r3
 8001e84:	687b      	ldr	r3, [r7, #4]
 8001e86:	440b      	add	r3, r1
 8001e88:	b2d2      	uxtb	r2, r2
 8001e8a:	701a      	strb	r2, [r3, #0]

    return txBufferPos;
 8001e8c:	89fb      	ldrh	r3, [r7, #14]
}
 8001e8e:	4618      	mov	r0, r3
 8001e90:	3710      	adds	r7, #16
 8001e92:	46bd      	mov	sp, r7
 8001e94:	bd80      	pop	{r7, pc}
 8001e96:	bf00      	nop
 8001e98:	ffff8000 	.word	0xffff8000
 8001e9c:	240003d4 	.word	0x240003d4

08001ea0 <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8001ea0:	b580      	push	{r7, lr}
 8001ea2:	b082      	sub	sp, #8
 8001ea4:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 8001ea6:	4b10      	ldr	r3, [pc, #64]	@ (8001ee8 <HAL_MspInit+0x48>)
 8001ea8:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 8001eac:	4a0e      	ldr	r2, [pc, #56]	@ (8001ee8 <HAL_MspInit+0x48>)
 8001eae:	f043 0302 	orr.w	r3, r3, #2
 8001eb2:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
 8001eb6:	4b0c      	ldr	r3, [pc, #48]	@ (8001ee8 <HAL_MspInit+0x48>)
 8001eb8:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 8001ebc:	f003 0302 	and.w	r3, r3, #2
 8001ec0:	607b      	str	r3, [r7, #4]
 8001ec2:	687b      	ldr	r3, [r7, #4]

  /* System interrupt init*/
  /* PendSV_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
 8001ec4:	2200      	movs	r2, #0
 8001ec6:	210f      	movs	r1, #15
 8001ec8:	f06f 0001 	mvn.w	r0, #1
 8001ecc:	f002 ffea 	bl	8004ea4 <HAL_NVIC_SetPriority>

  /* Peripheral interrupt init */
  /* RCC_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(RCC_IRQn, 5, 0);
 8001ed0:	2200      	movs	r2, #0
 8001ed2:	2105      	movs	r1, #5
 8001ed4:	2005      	movs	r0, #5
 8001ed6:	f002 ffe5 	bl	8004ea4 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(RCC_IRQn);
 8001eda:	2005      	movs	r0, #5
 8001edc:	f002 fffc 	bl	8004ed8 <HAL_NVIC_EnableIRQ>

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8001ee0:	bf00      	nop
 8001ee2:	3708      	adds	r7, #8
 8001ee4:	46bd      	mov	sp, r7
 8001ee6:	bd80      	pop	{r7, pc}
 8001ee8:	58024400 	.word	0x58024400

08001eec <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
 8001eec:	b580      	push	{r7, lr}
 8001eee:	b092      	sub	sp, #72	@ 0x48
 8001ef0:	af00      	add	r7, sp, #0
 8001ef2:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001ef4:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8001ef8:	2200      	movs	r2, #0
 8001efa:	601a      	str	r2, [r3, #0]
 8001efc:	605a      	str	r2, [r3, #4]
 8001efe:	609a      	str	r2, [r3, #8]
 8001f00:	60da      	str	r2, [r3, #12]
 8001f02:	611a      	str	r2, [r3, #16]
  if(hadc->Instance==ADC1)
 8001f04:	687b      	ldr	r3, [r7, #4]
 8001f06:	681b      	ldr	r3, [r3, #0]
 8001f08:	4a9d      	ldr	r2, [pc, #628]	@ (8002180 <HAL_ADC_MspInit+0x294>)
 8001f0a:	4293      	cmp	r3, r2
 8001f0c:	f040 8099 	bne.w	8002042 <HAL_ADC_MspInit+0x156>
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */
    /* Peripheral clock enable */
    HAL_RCC_ADC12_CLK_ENABLED++;
 8001f10:	4b9c      	ldr	r3, [pc, #624]	@ (8002184 <HAL_ADC_MspInit+0x298>)
 8001f12:	681b      	ldr	r3, [r3, #0]
 8001f14:	3301      	adds	r3, #1
 8001f16:	4a9b      	ldr	r2, [pc, #620]	@ (8002184 <HAL_ADC_MspInit+0x298>)
 8001f18:	6013      	str	r3, [r2, #0]
    if(HAL_RCC_ADC12_CLK_ENABLED==1){
 8001f1a:	4b9a      	ldr	r3, [pc, #616]	@ (8002184 <HAL_ADC_MspInit+0x298>)
 8001f1c:	681b      	ldr	r3, [r3, #0]
 8001f1e:	2b01      	cmp	r3, #1
 8001f20:	d10e      	bne.n	8001f40 <HAL_ADC_MspInit+0x54>
      __HAL_RCC_ADC12_CLK_ENABLE();
 8001f22:	4b99      	ldr	r3, [pc, #612]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8001f24:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 8001f28:	4a97      	ldr	r2, [pc, #604]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8001f2a:	f043 0320 	orr.w	r3, r3, #32
 8001f2e:	f8c2 30d8 	str.w	r3, [r2, #216]	@ 0xd8
 8001f32:	4b95      	ldr	r3, [pc, #596]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8001f34:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 8001f38:	f003 0320 	and.w	r3, r3, #32
 8001f3c:	633b      	str	r3, [r7, #48]	@ 0x30
 8001f3e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
    }

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8001f40:	4b91      	ldr	r3, [pc, #580]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8001f42:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001f46:	4a90      	ldr	r2, [pc, #576]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8001f48:	f043 0301 	orr.w	r3, r3, #1
 8001f4c:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8001f50:	4b8d      	ldr	r3, [pc, #564]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8001f52:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001f56:	f003 0301 	and.w	r3, r3, #1
 8001f5a:	62fb      	str	r3, [r7, #44]	@ 0x2c
 8001f5c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
    __HAL_RCC_GPIOC_CLK_ENABLE();
 8001f5e:	4b8a      	ldr	r3, [pc, #552]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8001f60:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001f64:	4a88      	ldr	r2, [pc, #544]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8001f66:	f043 0304 	orr.w	r3, r3, #4
 8001f6a:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8001f6e:	4b86      	ldr	r3, [pc, #536]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8001f70:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001f74:	f003 0304 	and.w	r3, r3, #4
 8001f78:	62bb      	str	r3, [r7, #40]	@ 0x28
 8001f7a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8001f7c:	4b82      	ldr	r3, [pc, #520]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8001f7e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001f82:	4a81      	ldr	r2, [pc, #516]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8001f84:	f043 0302 	orr.w	r3, r3, #2
 8001f88:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8001f8c:	4b7e      	ldr	r3, [pc, #504]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8001f8e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001f92:	f003 0302 	and.w	r3, r3, #2
 8001f96:	627b      	str	r3, [r7, #36]	@ 0x24
 8001f98:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
    PA2     ------> ADC1_INP14
    PA7     ------> ADC1_INP7
    PC5     ------> ADC1_INP8
    PB0     ------> ADC1_INP9
    */
    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
 8001f9a:	2387      	movs	r3, #135	@ 0x87
 8001f9c:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001f9e:	2303      	movs	r3, #3
 8001fa0:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001fa2:	2300      	movs	r3, #0
 8001fa4:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001fa6:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8001faa:	4619      	mov	r1, r3
 8001fac:	4877      	ldr	r0, [pc, #476]	@ (800218c <HAL_ADC_MspInit+0x2a0>)
 8001fae:	f006 f85b 	bl	8008068 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = GPIO_PIN_5;
 8001fb2:	2320      	movs	r3, #32
 8001fb4:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001fb6:	2303      	movs	r3, #3
 8001fb8:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001fba:	2300      	movs	r3, #0
 8001fbc:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8001fbe:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8001fc2:	4619      	mov	r1, r3
 8001fc4:	4872      	ldr	r0, [pc, #456]	@ (8002190 <HAL_ADC_MspInit+0x2a4>)
 8001fc6:	f006 f84f 	bl	8008068 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = GPIO_PIN_0;
 8001fca:	2301      	movs	r3, #1
 8001fcc:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001fce:	2303      	movs	r3, #3
 8001fd0:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001fd2:	2300      	movs	r3, #0
 8001fd4:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001fd6:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8001fda:	4619      	mov	r1, r3
 8001fdc:	486d      	ldr	r0, [pc, #436]	@ (8002194 <HAL_ADC_MspInit+0x2a8>)
 8001fde:	f006 f843 	bl	8008068 <HAL_GPIO_Init>

    /* ADC1 DMA Init */
    /* ADC1 Init */
    hdma_adc1.Instance = DMA1_Stream0;
 8001fe2:	4b6d      	ldr	r3, [pc, #436]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 8001fe4:	4a6d      	ldr	r2, [pc, #436]	@ (800219c <HAL_ADC_MspInit+0x2b0>)
 8001fe6:	601a      	str	r2, [r3, #0]
    hdma_adc1.Init.Request = DMA_REQUEST_ADC1;
 8001fe8:	4b6b      	ldr	r3, [pc, #428]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 8001fea:	2209      	movs	r2, #9
 8001fec:	605a      	str	r2, [r3, #4]
    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8001fee:	4b6a      	ldr	r3, [pc, #424]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 8001ff0:	2200      	movs	r2, #0
 8001ff2:	609a      	str	r2, [r3, #8]
    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
 8001ff4:	4b68      	ldr	r3, [pc, #416]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 8001ff6:	2200      	movs	r2, #0
 8001ff8:	60da      	str	r2, [r3, #12]
    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
 8001ffa:	4b67      	ldr	r3, [pc, #412]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 8001ffc:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 8002000:	611a      	str	r2, [r3, #16]
    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
 8002002:	4b65      	ldr	r3, [pc, #404]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 8002004:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 8002008:	615a      	str	r2, [r3, #20]
    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
 800200a:	4b63      	ldr	r3, [pc, #396]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 800200c:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
 8002010:	619a      	str	r2, [r3, #24]
    hdma_adc1.Init.Mode = DMA_NORMAL;
 8002012:	4b61      	ldr	r3, [pc, #388]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 8002014:	2200      	movs	r2, #0
 8002016:	61da      	str	r2, [r3, #28]
    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
 8002018:	4b5f      	ldr	r3, [pc, #380]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 800201a:	2200      	movs	r2, #0
 800201c:	621a      	str	r2, [r3, #32]
    hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
 800201e:	4b5e      	ldr	r3, [pc, #376]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 8002020:	2200      	movs	r2, #0
 8002022:	625a      	str	r2, [r3, #36]	@ 0x24
    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
 8002024:	485c      	ldr	r0, [pc, #368]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 8002026:	f003 f9e3 	bl	80053f0 <HAL_DMA_Init>
 800202a:	4603      	mov	r3, r0
 800202c:	2b00      	cmp	r3, #0
 800202e:	d001      	beq.n	8002034 <HAL_ADC_MspInit+0x148>
    {
      Error_Handler();
 8002030:	f7ff fa2e 	bl	8001490 <Error_Handler>
    }

    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
 8002034:	687b      	ldr	r3, [r7, #4]
 8002036:	4a58      	ldr	r2, [pc, #352]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 8002038:	64da      	str	r2, [r3, #76]	@ 0x4c
 800203a:	4a57      	ldr	r2, [pc, #348]	@ (8002198 <HAL_ADC_MspInit+0x2ac>)
 800203c:	687b      	ldr	r3, [r7, #4]
 800203e:	6393      	str	r3, [r2, #56]	@ 0x38
  /* USER CODE BEGIN ADC3_MspInit 1 */

  /* USER CODE END ADC3_MspInit 1 */
  }

}
 8002040:	e11e      	b.n	8002280 <HAL_ADC_MspInit+0x394>
  else if(hadc->Instance==ADC2)
 8002042:	687b      	ldr	r3, [r7, #4]
 8002044:	681b      	ldr	r3, [r3, #0]
 8002046:	4a56      	ldr	r2, [pc, #344]	@ (80021a0 <HAL_ADC_MspInit+0x2b4>)
 8002048:	4293      	cmp	r3, r2
 800204a:	f040 80af 	bne.w	80021ac <HAL_ADC_MspInit+0x2c0>
    HAL_RCC_ADC12_CLK_ENABLED++;
 800204e:	4b4d      	ldr	r3, [pc, #308]	@ (8002184 <HAL_ADC_MspInit+0x298>)
 8002050:	681b      	ldr	r3, [r3, #0]
 8002052:	3301      	adds	r3, #1
 8002054:	4a4b      	ldr	r2, [pc, #300]	@ (8002184 <HAL_ADC_MspInit+0x298>)
 8002056:	6013      	str	r3, [r2, #0]
    if(HAL_RCC_ADC12_CLK_ENABLED==1){
 8002058:	4b4a      	ldr	r3, [pc, #296]	@ (8002184 <HAL_ADC_MspInit+0x298>)
 800205a:	681b      	ldr	r3, [r3, #0]
 800205c:	2b01      	cmp	r3, #1
 800205e:	d10e      	bne.n	800207e <HAL_ADC_MspInit+0x192>
      __HAL_RCC_ADC12_CLK_ENABLE();
 8002060:	4b49      	ldr	r3, [pc, #292]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8002062:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 8002066:	4a48      	ldr	r2, [pc, #288]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8002068:	f043 0320 	orr.w	r3, r3, #32
 800206c:	f8c2 30d8 	str.w	r3, [r2, #216]	@ 0xd8
 8002070:	4b45      	ldr	r3, [pc, #276]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8002072:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 8002076:	f003 0320 	and.w	r3, r3, #32
 800207a:	623b      	str	r3, [r7, #32]
 800207c:	6a3b      	ldr	r3, [r7, #32]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 800207e:	4b42      	ldr	r3, [pc, #264]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8002080:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8002084:	4a40      	ldr	r2, [pc, #256]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8002086:	f043 0301 	orr.w	r3, r3, #1
 800208a:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 800208e:	4b3e      	ldr	r3, [pc, #248]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 8002090:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8002094:	f003 0301 	and.w	r3, r3, #1
 8002098:	61fb      	str	r3, [r7, #28]
 800209a:	69fb      	ldr	r3, [r7, #28]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 800209c:	4b3a      	ldr	r3, [pc, #232]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 800209e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80020a2:	4a39      	ldr	r2, [pc, #228]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 80020a4:	f043 0304 	orr.w	r3, r3, #4
 80020a8:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80020ac:	4b36      	ldr	r3, [pc, #216]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 80020ae:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80020b2:	f003 0304 	and.w	r3, r3, #4
 80020b6:	61bb      	str	r3, [r7, #24]
 80020b8:	69bb      	ldr	r3, [r7, #24]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 80020ba:	4b33      	ldr	r3, [pc, #204]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 80020bc:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80020c0:	4a31      	ldr	r2, [pc, #196]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 80020c2:	f043 0302 	orr.w	r3, r3, #2
 80020c6:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80020ca:	4b2f      	ldr	r3, [pc, #188]	@ (8002188 <HAL_ADC_MspInit+0x29c>)
 80020cc:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80020d0:	f003 0302 	and.w	r3, r3, #2
 80020d4:	617b      	str	r3, [r7, #20]
 80020d6:	697b      	ldr	r3, [r7, #20]
    GPIO_InitStruct.Pin = GPIO_PIN_6;
 80020d8:	2340      	movs	r3, #64	@ 0x40
 80020da:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 80020dc:	2303      	movs	r3, #3
 80020de:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80020e0:	2300      	movs	r3, #0
 80020e2:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80020e4:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 80020e8:	4619      	mov	r1, r3
 80020ea:	4828      	ldr	r0, [pc, #160]	@ (800218c <HAL_ADC_MspInit+0x2a0>)
 80020ec:	f005 ffbc 	bl	8008068 <HAL_GPIO_Init>
    GPIO_InitStruct.Pin = GPIO_PIN_4;
 80020f0:	2310      	movs	r3, #16
 80020f2:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 80020f4:	2303      	movs	r3, #3
 80020f6:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80020f8:	2300      	movs	r3, #0
 80020fa:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 80020fc:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8002100:	4619      	mov	r1, r3
 8002102:	4823      	ldr	r0, [pc, #140]	@ (8002190 <HAL_ADC_MspInit+0x2a4>)
 8002104:	f005 ffb0 	bl	8008068 <HAL_GPIO_Init>
    GPIO_InitStruct.Pin = GPIO_PIN_1;
 8002108:	2302      	movs	r3, #2
 800210a:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 800210c:	2303      	movs	r3, #3
 800210e:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8002110:	2300      	movs	r3, #0
 8002112:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8002114:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8002118:	4619      	mov	r1, r3
 800211a:	481e      	ldr	r0, [pc, #120]	@ (8002194 <HAL_ADC_MspInit+0x2a8>)
 800211c:	f005 ffa4 	bl	8008068 <HAL_GPIO_Init>
    hdma_adc2.Instance = DMA1_Stream1;
 8002120:	4b20      	ldr	r3, [pc, #128]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 8002122:	4a21      	ldr	r2, [pc, #132]	@ (80021a8 <HAL_ADC_MspInit+0x2bc>)
 8002124:	601a      	str	r2, [r3, #0]
    hdma_adc2.Init.Request = DMA_REQUEST_ADC2;
 8002126:	4b1f      	ldr	r3, [pc, #124]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 8002128:	220a      	movs	r2, #10
 800212a:	605a      	str	r2, [r3, #4]
    hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY;
 800212c:	4b1d      	ldr	r3, [pc, #116]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 800212e:	2200      	movs	r2, #0
 8002130:	609a      	str	r2, [r3, #8]
    hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE;
 8002132:	4b1c      	ldr	r3, [pc, #112]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 8002134:	2200      	movs	r2, #0
 8002136:	60da      	str	r2, [r3, #12]
    hdma_adc2.Init.MemInc = DMA_MINC_ENABLE;
 8002138:	4b1a      	ldr	r3, [pc, #104]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 800213a:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 800213e:	611a      	str	r2, [r3, #16]
    hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
 8002140:	4b18      	ldr	r3, [pc, #96]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 8002142:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 8002146:	615a      	str	r2, [r3, #20]
    hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
 8002148:	4b16      	ldr	r3, [pc, #88]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 800214a:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
 800214e:	619a      	str	r2, [r3, #24]
    hdma_adc2.Init.Mode = DMA_NORMAL;
 8002150:	4b14      	ldr	r3, [pc, #80]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 8002152:	2200      	movs	r2, #0
 8002154:	61da      	str	r2, [r3, #28]
    hdma_adc2.Init.Priority = DMA_PRIORITY_LOW;
 8002156:	4b13      	ldr	r3, [pc, #76]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 8002158:	2200      	movs	r2, #0
 800215a:	621a      	str	r2, [r3, #32]
    hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
 800215c:	4b11      	ldr	r3, [pc, #68]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 800215e:	2200      	movs	r2, #0
 8002160:	625a      	str	r2, [r3, #36]	@ 0x24
    if (HAL_DMA_Init(&hdma_adc2) != HAL_OK)
 8002162:	4810      	ldr	r0, [pc, #64]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 8002164:	f003 f944 	bl	80053f0 <HAL_DMA_Init>
 8002168:	4603      	mov	r3, r0
 800216a:	2b00      	cmp	r3, #0
 800216c:	d001      	beq.n	8002172 <HAL_ADC_MspInit+0x286>
      Error_Handler();
 800216e:	f7ff f98f 	bl	8001490 <Error_Handler>
    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2);
 8002172:	687b      	ldr	r3, [r7, #4]
 8002174:	4a0b      	ldr	r2, [pc, #44]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 8002176:	64da      	str	r2, [r3, #76]	@ 0x4c
 8002178:	4a0a      	ldr	r2, [pc, #40]	@ (80021a4 <HAL_ADC_MspInit+0x2b8>)
 800217a:	687b      	ldr	r3, [r7, #4]
 800217c:	6393      	str	r3, [r2, #56]	@ 0x38
}
 800217e:	e07f      	b.n	8002280 <HAL_ADC_MspInit+0x394>
 8002180:	40022000 	.word	0x40022000
 8002184:	24000614 	.word	0x24000614
 8002188:	58024400 	.word	0x58024400
 800218c:	58020000 	.word	0x58020000
 8002190:	58020800 	.word	0x58020800
 8002194:	58020400 	.word	0x58020400
 8002198:	2400026c 	.word	0x2400026c
 800219c:	40020010 	.word	0x40020010
 80021a0:	40022100 	.word	0x40022100
 80021a4:	240002e4 	.word	0x240002e4
 80021a8:	40020028 	.word	0x40020028
  else if(hadc->Instance==ADC3)
 80021ac:	687b      	ldr	r3, [r7, #4]
 80021ae:	681b      	ldr	r3, [r3, #0]
 80021b0:	4a35      	ldr	r2, [pc, #212]	@ (8002288 <HAL_ADC_MspInit+0x39c>)
 80021b2:	4293      	cmp	r3, r2
 80021b4:	d164      	bne.n	8002280 <HAL_ADC_MspInit+0x394>
    __HAL_RCC_ADC3_CLK_ENABLE();
 80021b6:	4b35      	ldr	r3, [pc, #212]	@ (800228c <HAL_ADC_MspInit+0x3a0>)
 80021b8:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80021bc:	4a33      	ldr	r2, [pc, #204]	@ (800228c <HAL_ADC_MspInit+0x3a0>)
 80021be:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 80021c2:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80021c6:	4b31      	ldr	r3, [pc, #196]	@ (800228c <HAL_ADC_MspInit+0x3a0>)
 80021c8:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80021cc:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 80021d0:	613b      	str	r3, [r7, #16]
 80021d2:	693b      	ldr	r3, [r7, #16]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 80021d4:	4b2d      	ldr	r3, [pc, #180]	@ (800228c <HAL_ADC_MspInit+0x3a0>)
 80021d6:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80021da:	4a2c      	ldr	r2, [pc, #176]	@ (800228c <HAL_ADC_MspInit+0x3a0>)
 80021dc:	f043 0304 	orr.w	r3, r3, #4
 80021e0:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80021e4:	4b29      	ldr	r3, [pc, #164]	@ (800228c <HAL_ADC_MspInit+0x3a0>)
 80021e6:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80021ea:	f003 0304 	and.w	r3, r3, #4
 80021ee:	60fb      	str	r3, [r7, #12]
 80021f0:	68fb      	ldr	r3, [r7, #12]
    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
 80021f2:	2303      	movs	r3, #3
 80021f4:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 80021f6:	2303      	movs	r3, #3
 80021f8:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80021fa:	2300      	movs	r3, #0
 80021fc:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 80021fe:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8002202:	4619      	mov	r1, r3
 8002204:	4822      	ldr	r0, [pc, #136]	@ (8002290 <HAL_ADC_MspInit+0x3a4>)
 8002206:	f005 ff2f 	bl	8008068 <HAL_GPIO_Init>
    HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN);
 800220a:	f04f 6180 	mov.w	r1, #67108864	@ 0x4000000
 800220e:	f04f 6080 	mov.w	r0, #67108864	@ 0x4000000
 8002212:	f001 f96f 	bl	80034f4 <HAL_SYSCFG_AnalogSwitchConfig>
    HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN);
 8002216:	f04f 6100 	mov.w	r1, #134217728	@ 0x8000000
 800221a:	f04f 6000 	mov.w	r0, #134217728	@ 0x8000000
 800221e:	f001 f969 	bl	80034f4 <HAL_SYSCFG_AnalogSwitchConfig>
    hdma_adc3.Instance = DMA1_Stream2;
 8002222:	4b1c      	ldr	r3, [pc, #112]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 8002224:	4a1c      	ldr	r2, [pc, #112]	@ (8002298 <HAL_ADC_MspInit+0x3ac>)
 8002226:	601a      	str	r2, [r3, #0]
    hdma_adc3.Init.Request = DMA_REQUEST_ADC3;
 8002228:	4b1a      	ldr	r3, [pc, #104]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 800222a:	2273      	movs	r2, #115	@ 0x73
 800222c:	605a      	str	r2, [r3, #4]
    hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY;
 800222e:	4b19      	ldr	r3, [pc, #100]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 8002230:	2200      	movs	r2, #0
 8002232:	609a      	str	r2, [r3, #8]
    hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE;
 8002234:	4b17      	ldr	r3, [pc, #92]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 8002236:	2200      	movs	r2, #0
 8002238:	60da      	str	r2, [r3, #12]
    hdma_adc3.Init.MemInc = DMA_MINC_ENABLE;
 800223a:	4b16      	ldr	r3, [pc, #88]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 800223c:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 8002240:	611a      	str	r2, [r3, #16]
    hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
 8002242:	4b14      	ldr	r3, [pc, #80]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 8002244:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 8002248:	615a      	str	r2, [r3, #20]
    hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
 800224a:	4b12      	ldr	r3, [pc, #72]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 800224c:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
 8002250:	619a      	str	r2, [r3, #24]
    hdma_adc3.Init.Mode = DMA_NORMAL;
 8002252:	4b10      	ldr	r3, [pc, #64]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 8002254:	2200      	movs	r2, #0
 8002256:	61da      	str	r2, [r3, #28]
    hdma_adc3.Init.Priority = DMA_PRIORITY_LOW;
 8002258:	4b0e      	ldr	r3, [pc, #56]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 800225a:	2200      	movs	r2, #0
 800225c:	621a      	str	r2, [r3, #32]
    hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
 800225e:	4b0d      	ldr	r3, [pc, #52]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 8002260:	2200      	movs	r2, #0
 8002262:	625a      	str	r2, [r3, #36]	@ 0x24
    if (HAL_DMA_Init(&hdma_adc3) != HAL_OK)
 8002264:	480b      	ldr	r0, [pc, #44]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 8002266:	f003 f8c3 	bl	80053f0 <HAL_DMA_Init>
 800226a:	4603      	mov	r3, r0
 800226c:	2b00      	cmp	r3, #0
 800226e:	d001      	beq.n	8002274 <HAL_ADC_MspInit+0x388>
      Error_Handler();
 8002270:	f7ff f90e 	bl	8001490 <Error_Handler>
    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3);
 8002274:	687b      	ldr	r3, [r7, #4]
 8002276:	4a07      	ldr	r2, [pc, #28]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 8002278:	64da      	str	r2, [r3, #76]	@ 0x4c
 800227a:	4a06      	ldr	r2, [pc, #24]	@ (8002294 <HAL_ADC_MspInit+0x3a8>)
 800227c:	687b      	ldr	r3, [r7, #4]
 800227e:	6393      	str	r3, [r2, #56]	@ 0x38
}
 8002280:	bf00      	nop
 8002282:	3748      	adds	r7, #72	@ 0x48
 8002284:	46bd      	mov	sp, r7
 8002286:	bd80      	pop	{r7, pc}
 8002288:	58026000 	.word	0x58026000
 800228c:	58024400 	.word	0x58024400
 8002290:	58020800 	.word	0x58020800
 8002294:	2400035c 	.word	0x2400035c
 8002298:	40020040 	.word	0x40020040

0800229c <HAL_CRC_MspInit>:
* This function configures the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
{
 800229c:	b480      	push	{r7}
 800229e:	b085      	sub	sp, #20
 80022a0:	af00      	add	r7, sp, #0
 80022a2:	6078      	str	r0, [r7, #4]
  if(hcrc->Instance==CRC)
 80022a4:	687b      	ldr	r3, [r7, #4]
 80022a6:	681b      	ldr	r3, [r3, #0]
 80022a8:	4a0b      	ldr	r2, [pc, #44]	@ (80022d8 <HAL_CRC_MspInit+0x3c>)
 80022aa:	4293      	cmp	r3, r2
 80022ac:	d10e      	bne.n	80022cc <HAL_CRC_MspInit+0x30>
  {
  /* USER CODE BEGIN CRC_MspInit 0 */

  /* USER CODE END CRC_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_CRC_CLK_ENABLE();
 80022ae:	4b0b      	ldr	r3, [pc, #44]	@ (80022dc <HAL_CRC_MspInit+0x40>)
 80022b0:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80022b4:	4a09      	ldr	r2, [pc, #36]	@ (80022dc <HAL_CRC_MspInit+0x40>)
 80022b6:	f443 2300 	orr.w	r3, r3, #524288	@ 0x80000
 80022ba:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80022be:	4b07      	ldr	r3, [pc, #28]	@ (80022dc <HAL_CRC_MspInit+0x40>)
 80022c0:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80022c4:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
 80022c8:	60fb      	str	r3, [r7, #12]
 80022ca:	68fb      	ldr	r3, [r7, #12]
  /* USER CODE BEGIN CRC_MspInit 1 */

  /* USER CODE END CRC_MspInit 1 */
  }

}
 80022cc:	bf00      	nop
 80022ce:	3714      	adds	r7, #20
 80022d0:	46bd      	mov	sp, r7
 80022d2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80022d6:	4770      	bx	lr
 80022d8:	58024c00 	.word	0x58024c00
 80022dc:	58024400 	.word	0x58024400

080022e0 <HAL_RNG_MspInit>:
* This function configures the hardware resources used in this example
* @param hrng: RNG handle pointer
* @retval None
*/
void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng)
{
 80022e0:	b580      	push	{r7, lr}
 80022e2:	b0b4      	sub	sp, #208	@ 0xd0
 80022e4:	af00      	add	r7, sp, #0
 80022e6:	6078      	str	r0, [r7, #4]
  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 80022e8:	f107 0310 	add.w	r3, r7, #16
 80022ec:	22c0      	movs	r2, #192	@ 0xc0
 80022ee:	2100      	movs	r1, #0
 80022f0:	4618      	mov	r0, r3
 80022f2:	f011 fa78 	bl	80137e6 <memset>
  if(hrng->Instance==RNG)
 80022f6:	687b      	ldr	r3, [r7, #4]
 80022f8:	681b      	ldr	r3, [r3, #0]
 80022fa:	4a14      	ldr	r2, [pc, #80]	@ (800234c <HAL_RNG_MspInit+0x6c>)
 80022fc:	4293      	cmp	r3, r2
 80022fe:	d121      	bne.n	8002344 <HAL_RNG_MspInit+0x64>

  /* USER CODE END RNG_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
 8002300:	f44f 3200 	mov.w	r2, #131072	@ 0x20000
 8002304:	f04f 0300 	mov.w	r3, #0
 8002308:	e9c7 2304 	strd	r2, r3, [r7, #16]
    PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
 800230c:	2300      	movs	r3, #0
 800230e:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 8002312:	f107 0310 	add.w	r3, r7, #16
 8002316:	4618      	mov	r0, r3
 8002318:	f007 f8ec 	bl	80094f4 <HAL_RCCEx_PeriphCLKConfig>
 800231c:	4603      	mov	r3, r0
 800231e:	2b00      	cmp	r3, #0
 8002320:	d001      	beq.n	8002326 <HAL_RNG_MspInit+0x46>
    {
      Error_Handler();
 8002322:	f7ff f8b5 	bl	8001490 <Error_Handler>
    }

    /* Peripheral clock enable */
    __HAL_RCC_RNG_CLK_ENABLE();
 8002326:	4b0a      	ldr	r3, [pc, #40]	@ (8002350 <HAL_RNG_MspInit+0x70>)
 8002328:	f8d3 30dc 	ldr.w	r3, [r3, #220]	@ 0xdc
 800232c:	4a08      	ldr	r2, [pc, #32]	@ (8002350 <HAL_RNG_MspInit+0x70>)
 800232e:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 8002332:	f8c2 30dc 	str.w	r3, [r2, #220]	@ 0xdc
 8002336:	4b06      	ldr	r3, [pc, #24]	@ (8002350 <HAL_RNG_MspInit+0x70>)
 8002338:	f8d3 30dc 	ldr.w	r3, [r3, #220]	@ 0xdc
 800233c:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8002340:	60fb      	str	r3, [r7, #12]
 8002342:	68fb      	ldr	r3, [r7, #12]
  /* USER CODE BEGIN RNG_MspInit 1 */

  /* USER CODE END RNG_MspInit 1 */
  }

}
 8002344:	bf00      	nop
 8002346:	37d0      	adds	r7, #208	@ 0xd0
 8002348:	46bd      	mov	sp, r7
 800234a:	bd80      	pop	{r7, pc}
 800234c:	48021800 	.word	0x48021800
 8002350:	58024400 	.word	0x58024400

08002354 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
 8002354:	b580      	push	{r7, lr}
 8002356:	b084      	sub	sp, #16
 8002358:	af00      	add	r7, sp, #0
 800235a:	6078      	str	r0, [r7, #4]
  if(htim_base->Instance==TIM2)
 800235c:	687b      	ldr	r3, [r7, #4]
 800235e:	681b      	ldr	r3, [r3, #0]
 8002360:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8002364:	d116      	bne.n	8002394 <HAL_TIM_Base_MspInit+0x40>
  {
  /* USER CODE BEGIN TIM2_MspInit 0 */

  /* USER CODE END TIM2_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_TIM2_CLK_ENABLE();
 8002366:	4b0d      	ldr	r3, [pc, #52]	@ (800239c <HAL_TIM_Base_MspInit+0x48>)
 8002368:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 800236c:	4a0b      	ldr	r2, [pc, #44]	@ (800239c <HAL_TIM_Base_MspInit+0x48>)
 800236e:	f043 0301 	orr.w	r3, r3, #1
 8002372:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
 8002376:	4b09      	ldr	r3, [pc, #36]	@ (800239c <HAL_TIM_Base_MspInit+0x48>)
 8002378:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 800237c:	f003 0301 	and.w	r3, r3, #1
 8002380:	60fb      	str	r3, [r7, #12]
 8002382:	68fb      	ldr	r3, [r7, #12]
    /* TIM2 interrupt Init */
    HAL_NVIC_SetPriority(TIM2_IRQn, 5, 0);
 8002384:	2200      	movs	r2, #0
 8002386:	2105      	movs	r1, #5
 8002388:	201c      	movs	r0, #28
 800238a:	f002 fd8b 	bl	8004ea4 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(TIM2_IRQn);
 800238e:	201c      	movs	r0, #28
 8002390:	f002 fda2 	bl	8004ed8 <HAL_NVIC_EnableIRQ>
  /* USER CODE BEGIN TIM2_MspInit 1 */

  /* USER CODE END TIM2_MspInit 1 */
  }

}
 8002394:	bf00      	nop
 8002396:	3710      	adds	r7, #16
 8002398:	46bd      	mov	sp, r7
 800239a:	bd80      	pop	{r7, pc}
 800239c:	58024400 	.word	0x58024400

080023a0 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 80023a0:	b580      	push	{r7, lr}
 80023a2:	b0bc      	sub	sp, #240	@ 0xf0
 80023a4:	af00      	add	r7, sp, #0
 80023a6:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80023a8:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
 80023ac:	2200      	movs	r2, #0
 80023ae:	601a      	str	r2, [r3, #0]
 80023b0:	605a      	str	r2, [r3, #4]
 80023b2:	609a      	str	r2, [r3, #8]
 80023b4:	60da      	str	r2, [r3, #12]
 80023b6:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 80023b8:	f107 0318 	add.w	r3, r7, #24
 80023bc:	22c0      	movs	r2, #192	@ 0xc0
 80023be:	2100      	movs	r1, #0
 80023c0:	4618      	mov	r0, r3
 80023c2:	f011 fa10 	bl	80137e6 <memset>
  if(huart->Instance==UART8)
 80023c6:	687b      	ldr	r3, [r7, #4]
 80023c8:	681b      	ldr	r3, [r3, #0]
 80023ca:	4a55      	ldr	r2, [pc, #340]	@ (8002520 <HAL_UART_MspInit+0x180>)
 80023cc:	4293      	cmp	r3, r2
 80023ce:	d14e      	bne.n	800246e <HAL_UART_MspInit+0xce>

  /* USER CODE END UART8_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8;
 80023d0:	f04f 0202 	mov.w	r2, #2
 80023d4:	f04f 0300 	mov.w	r3, #0
 80023d8:	e9c7 2306 	strd	r2, r3, [r7, #24]
    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
 80023dc:	2300      	movs	r3, #0
 80023de:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 80023e2:	f107 0318 	add.w	r3, r7, #24
 80023e6:	4618      	mov	r0, r3
 80023e8:	f007 f884 	bl	80094f4 <HAL_RCCEx_PeriphCLKConfig>
 80023ec:	4603      	mov	r3, r0
 80023ee:	2b00      	cmp	r3, #0
 80023f0:	d001      	beq.n	80023f6 <HAL_UART_MspInit+0x56>
    {
      Error_Handler();
 80023f2:	f7ff f84d 	bl	8001490 <Error_Handler>
    }

    /* Peripheral clock enable */
    __HAL_RCC_UART8_CLK_ENABLE();
 80023f6:	4b4b      	ldr	r3, [pc, #300]	@ (8002524 <HAL_UART_MspInit+0x184>)
 80023f8:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 80023fc:	4a49      	ldr	r2, [pc, #292]	@ (8002524 <HAL_UART_MspInit+0x184>)
 80023fe:	f043 4300 	orr.w	r3, r3, #2147483648	@ 0x80000000
 8002402:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
 8002406:	4b47      	ldr	r3, [pc, #284]	@ (8002524 <HAL_UART_MspInit+0x184>)
 8002408:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 800240c:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
 8002410:	617b      	str	r3, [r7, #20]
 8002412:	697b      	ldr	r3, [r7, #20]

    __HAL_RCC_GPIOE_CLK_ENABLE();
 8002414:	4b43      	ldr	r3, [pc, #268]	@ (8002524 <HAL_UART_MspInit+0x184>)
 8002416:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800241a:	4a42      	ldr	r2, [pc, #264]	@ (8002524 <HAL_UART_MspInit+0x184>)
 800241c:	f043 0310 	orr.w	r3, r3, #16
 8002420:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8002424:	4b3f      	ldr	r3, [pc, #252]	@ (8002524 <HAL_UART_MspInit+0x184>)
 8002426:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800242a:	f003 0310 	and.w	r3, r3, #16
 800242e:	613b      	str	r3, [r7, #16]
 8002430:	693b      	ldr	r3, [r7, #16]
    /**UART8 GPIO Configuration
    PE0     ------> UART8_RX
    PE1     ------> UART8_TX
    */
    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
 8002432:	2303      	movs	r3, #3
 8002434:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8002438:	2302      	movs	r3, #2
 800243a:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 800243e:	2300      	movs	r3, #0
 8002440:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8002444:	2300      	movs	r3, #0
 8002446:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
    GPIO_InitStruct.Alternate = GPIO_AF8_UART8;
 800244a:	2308      	movs	r3, #8
 800244c:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 8002450:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
 8002454:	4619      	mov	r1, r3
 8002456:	4834      	ldr	r0, [pc, #208]	@ (8002528 <HAL_UART_MspInit+0x188>)
 8002458:	f005 fe06 	bl	8008068 <HAL_GPIO_Init>

    /* UART8 interrupt Init */
    HAL_NVIC_SetPriority(UART8_IRQn, 5, 0);
 800245c:	2200      	movs	r2, #0
 800245e:	2105      	movs	r1, #5
 8002460:	2053      	movs	r0, #83	@ 0x53
 8002462:	f002 fd1f 	bl	8004ea4 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(UART8_IRQn);
 8002466:	2053      	movs	r0, #83	@ 0x53
 8002468:	f002 fd36 	bl	8004ed8 <HAL_NVIC_EnableIRQ>
  /* USER CODE BEGIN USART1_MspInit 1 */

  /* USER CODE END USART1_MspInit 1 */
  }

}
 800246c:	e053      	b.n	8002516 <HAL_UART_MspInit+0x176>
  else if(huart->Instance==USART1)
 800246e:	687b      	ldr	r3, [r7, #4]
 8002470:	681b      	ldr	r3, [r3, #0]
 8002472:	4a2e      	ldr	r2, [pc, #184]	@ (800252c <HAL_UART_MspInit+0x18c>)
 8002474:	4293      	cmp	r3, r2
 8002476:	d14e      	bne.n	8002516 <HAL_UART_MspInit+0x176>
    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
 8002478:	f04f 0201 	mov.w	r2, #1
 800247c:	f04f 0300 	mov.w	r3, #0
 8002480:	e9c7 2306 	strd	r2, r3, [r7, #24]
    PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
 8002484:	2300      	movs	r3, #0
 8002486:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 800248a:	f107 0318 	add.w	r3, r7, #24
 800248e:	4618      	mov	r0, r3
 8002490:	f007 f830 	bl	80094f4 <HAL_RCCEx_PeriphCLKConfig>
 8002494:	4603      	mov	r3, r0
 8002496:	2b00      	cmp	r3, #0
 8002498:	d001      	beq.n	800249e <HAL_UART_MspInit+0xfe>
      Error_Handler();
 800249a:	f7fe fff9 	bl	8001490 <Error_Handler>
    __HAL_RCC_USART1_CLK_ENABLE();
 800249e:	4b21      	ldr	r3, [pc, #132]	@ (8002524 <HAL_UART_MspInit+0x184>)
 80024a0:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
 80024a4:	4a1f      	ldr	r2, [pc, #124]	@ (8002524 <HAL_UART_MspInit+0x184>)
 80024a6:	f043 0310 	orr.w	r3, r3, #16
 80024aa:	f8c2 30f0 	str.w	r3, [r2, #240]	@ 0xf0
 80024ae:	4b1d      	ldr	r3, [pc, #116]	@ (8002524 <HAL_UART_MspInit+0x184>)
 80024b0:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
 80024b4:	f003 0310 	and.w	r3, r3, #16
 80024b8:	60fb      	str	r3, [r7, #12]
 80024ba:	68fb      	ldr	r3, [r7, #12]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 80024bc:	4b19      	ldr	r3, [pc, #100]	@ (8002524 <HAL_UART_MspInit+0x184>)
 80024be:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80024c2:	4a18      	ldr	r2, [pc, #96]	@ (8002524 <HAL_UART_MspInit+0x184>)
 80024c4:	f043 0302 	orr.w	r3, r3, #2
 80024c8:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80024cc:	4b15      	ldr	r3, [pc, #84]	@ (8002524 <HAL_UART_MspInit+0x184>)
 80024ce:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80024d2:	f003 0302 	and.w	r3, r3, #2
 80024d6:	60bb      	str	r3, [r7, #8]
 80024d8:	68bb      	ldr	r3, [r7, #8]
    GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
 80024da:	f44f 4340 	mov.w	r3, #49152	@ 0xc000
 80024de:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 80024e2:	2302      	movs	r3, #2
 80024e4:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80024e8:	2300      	movs	r3, #0
 80024ea:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80024ee:	2300      	movs	r3, #0
 80024f0:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
    GPIO_InitStruct.Alternate = GPIO_AF4_USART1;
 80024f4:	2304      	movs	r3, #4
 80024f6:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 80024fa:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
 80024fe:	4619      	mov	r1, r3
 8002500:	480b      	ldr	r0, [pc, #44]	@ (8002530 <HAL_UART_MspInit+0x190>)
 8002502:	f005 fdb1 	bl	8008068 <HAL_GPIO_Init>
    HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
 8002506:	2200      	movs	r2, #0
 8002508:	2105      	movs	r1, #5
 800250a:	2025      	movs	r0, #37	@ 0x25
 800250c:	f002 fcca 	bl	8004ea4 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(USART1_IRQn);
 8002510:	2025      	movs	r0, #37	@ 0x25
 8002512:	f002 fce1 	bl	8004ed8 <HAL_NVIC_EnableIRQ>
}
 8002516:	bf00      	nop
 8002518:	37f0      	adds	r7, #240	@ 0xf0
 800251a:	46bd      	mov	sp, r7
 800251c:	bd80      	pop	{r7, pc}
 800251e:	bf00      	nop
 8002520:	40007c00 	.word	0x40007c00
 8002524:	58024400 	.word	0x58024400
 8002528:	58021000 	.word	0x58021000
 800252c:	40011000 	.word	0x40011000
 8002530:	58020400 	.word	0x58020400

08002534 <HAL_InitTick>:
  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
  * @param  TickPriority: Tick interrupt priority.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8002534:	b580      	push	{r7, lr}
 8002536:	b090      	sub	sp, #64	@ 0x40
 8002538:	af00      	add	r7, sp, #0
 800253a:	6078      	str	r0, [r7, #4]
  uint32_t              uwTimclock, uwAPB1Prescaler;

  uint32_t              uwPrescalerValue;
  uint32_t              pFLatency;
/*Configure the TIM6 IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 800253c:	687b      	ldr	r3, [r7, #4]
 800253e:	2b0f      	cmp	r3, #15
 8002540:	d827      	bhi.n	8002592 <HAL_InitTick+0x5e>
  {
  HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
 8002542:	2200      	movs	r2, #0
 8002544:	6879      	ldr	r1, [r7, #4]
 8002546:	2036      	movs	r0, #54	@ 0x36
 8002548:	f002 fcac 	bl	8004ea4 <HAL_NVIC_SetPriority>

  /* Enable the TIM6 global Interrupt */
  HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
 800254c:	2036      	movs	r0, #54	@ 0x36
 800254e:	f002 fcc3 	bl	8004ed8 <HAL_NVIC_EnableIRQ>
    uwTickPrio = TickPriority;
 8002552:	4a29      	ldr	r2, [pc, #164]	@ (80025f8 <HAL_InitTick+0xc4>)
 8002554:	687b      	ldr	r3, [r7, #4]
 8002556:	6013      	str	r3, [r2, #0]
  {
    return HAL_ERROR;
  }

  /* Enable TIM6 clock */
  __HAL_RCC_TIM6_CLK_ENABLE();
 8002558:	4b28      	ldr	r3, [pc, #160]	@ (80025fc <HAL_InitTick+0xc8>)
 800255a:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 800255e:	4a27      	ldr	r2, [pc, #156]	@ (80025fc <HAL_InitTick+0xc8>)
 8002560:	f043 0310 	orr.w	r3, r3, #16
 8002564:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
 8002568:	4b24      	ldr	r3, [pc, #144]	@ (80025fc <HAL_InitTick+0xc8>)
 800256a:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 800256e:	f003 0310 	and.w	r3, r3, #16
 8002572:	60fb      	str	r3, [r7, #12]
 8002574:	68fb      	ldr	r3, [r7, #12]

  /* Get clock configuration */
  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
 8002576:	f107 0210 	add.w	r2, r7, #16
 800257a:	f107 0314 	add.w	r3, r7, #20
 800257e:	4611      	mov	r1, r2
 8002580:	4618      	mov	r0, r3
 8002582:	f006 ff75 	bl	8009470 <HAL_RCC_GetClockConfig>

  /* Get APB1 prescaler */
  uwAPB1Prescaler = clkconfig.APB1CLKDivider;
 8002586:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8002588:	63bb      	str	r3, [r7, #56]	@ 0x38
  /* Compute TIM6 clock */
  if (uwAPB1Prescaler == RCC_HCLK_DIV1)
 800258a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800258c:	2b00      	cmp	r3, #0
 800258e:	d106      	bne.n	800259e <HAL_InitTick+0x6a>
 8002590:	e001      	b.n	8002596 <HAL_InitTick+0x62>
    return HAL_ERROR;
 8002592:	2301      	movs	r3, #1
 8002594:	e02b      	b.n	80025ee <HAL_InitTick+0xba>
  {
    uwTimclock = HAL_RCC_GetPCLK1Freq();
 8002596:	f006 ff3f 	bl	8009418 <HAL_RCC_GetPCLK1Freq>
 800259a:	63f8      	str	r0, [r7, #60]	@ 0x3c
 800259c:	e004      	b.n	80025a8 <HAL_InitTick+0x74>
  }
  else
  {
    uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
 800259e:	f006 ff3b 	bl	8009418 <HAL_RCC_GetPCLK1Freq>
 80025a2:	4603      	mov	r3, r0
 80025a4:	005b      	lsls	r3, r3, #1
 80025a6:	63fb      	str	r3, [r7, #60]	@ 0x3c
  }

  /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
 80025a8:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 80025aa:	4a15      	ldr	r2, [pc, #84]	@ (8002600 <HAL_InitTick+0xcc>)
 80025ac:	fba2 2303 	umull	r2, r3, r2, r3
 80025b0:	0c9b      	lsrs	r3, r3, #18
 80025b2:	3b01      	subs	r3, #1
 80025b4:	637b      	str	r3, [r7, #52]	@ 0x34

  /* Initialize TIM6 */
  htim6.Instance = TIM6;
 80025b6:	4b13      	ldr	r3, [pc, #76]	@ (8002604 <HAL_InitTick+0xd0>)
 80025b8:	4a13      	ldr	r2, [pc, #76]	@ (8002608 <HAL_InitTick+0xd4>)
 80025ba:	601a      	str	r2, [r3, #0]
  + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
  + ClockDivision = 0
  + Counter direction = Up
  */
  htim6.Init.Period = (1000000U / 1000U) - 1U;
 80025bc:	4b11      	ldr	r3, [pc, #68]	@ (8002604 <HAL_InitTick+0xd0>)
 80025be:	f240 32e7 	movw	r2, #999	@ 0x3e7
 80025c2:	60da      	str	r2, [r3, #12]
  htim6.Init.Prescaler = uwPrescalerValue;
 80025c4:	4a0f      	ldr	r2, [pc, #60]	@ (8002604 <HAL_InitTick+0xd0>)
 80025c6:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80025c8:	6053      	str	r3, [r2, #4]
  htim6.Init.ClockDivision = 0;
 80025ca:	4b0e      	ldr	r3, [pc, #56]	@ (8002604 <HAL_InitTick+0xd0>)
 80025cc:	2200      	movs	r2, #0
 80025ce:	611a      	str	r2, [r3, #16]
  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
 80025d0:	4b0c      	ldr	r3, [pc, #48]	@ (8002604 <HAL_InitTick+0xd0>)
 80025d2:	2200      	movs	r2, #0
 80025d4:	609a      	str	r2, [r3, #8]

  if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
 80025d6:	480b      	ldr	r0, [pc, #44]	@ (8002604 <HAL_InitTick+0xd0>)
 80025d8:	f009 fcd0 	bl	800bf7c <HAL_TIM_Base_Init>
 80025dc:	4603      	mov	r3, r0
 80025de:	2b00      	cmp	r3, #0
 80025e0:	d104      	bne.n	80025ec <HAL_InitTick+0xb8>
  {
    /* Start the TIM time Base generation in interrupt mode */
    return HAL_TIM_Base_Start_IT(&htim6);
 80025e2:	4808      	ldr	r0, [pc, #32]	@ (8002604 <HAL_InitTick+0xd0>)
 80025e4:	f009 fd92 	bl	800c10c <HAL_TIM_Base_Start_IT>
 80025e8:	4603      	mov	r3, r0
 80025ea:	e000      	b.n	80025ee <HAL_InitTick+0xba>
  }

  /* Return function status */
  return HAL_ERROR;
 80025ec:	2301      	movs	r3, #1
}
 80025ee:	4618      	mov	r0, r3
 80025f0:	3740      	adds	r7, #64	@ 0x40
 80025f2:	46bd      	mov	sp, r7
 80025f4:	bd80      	pop	{r7, pc}
 80025f6:	bf00      	nop
 80025f8:	2400003c 	.word	0x2400003c
 80025fc:	58024400 	.word	0x58024400
 8002600:	431bde83 	.word	0x431bde83
 8002604:	24000618 	.word	0x24000618
 8002608:	40001000 	.word	0x40001000

0800260c <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 800260c:	b480      	push	{r7}
 800260e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
   while (1)
 8002610:	bf00      	nop
 8002612:	e7fd      	b.n	8002610 <NMI_Handler+0x4>

08002614 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8002614:	b480      	push	{r7}
 8002616:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 8002618:	bf00      	nop
 800261a:	e7fd      	b.n	8002618 <HardFault_Handler+0x4>

0800261c <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 800261c:	b480      	push	{r7}
 800261e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 8002620:	bf00      	nop
 8002622:	e7fd      	b.n	8002620 <MemManage_Handler+0x4>

08002624 <BusFault_Handler>:

/**
  * @brief This function handles Pre-fetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8002624:	b480      	push	{r7}
 8002626:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 8002628:	bf00      	nop
 800262a:	e7fd      	b.n	8002628 <BusFault_Handler+0x4>

0800262c <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 800262c:	b480      	push	{r7}
 800262e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 8002630:	bf00      	nop
 8002632:	e7fd      	b.n	8002630 <UsageFault_Handler+0x4>

08002634 <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 8002634:	b480      	push	{r7}
 8002636:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 8002638:	bf00      	nop
 800263a:	46bd      	mov	sp, r7
 800263c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002640:	4770      	bx	lr

08002642 <RCC_IRQHandler>:

/**
  * @brief This function handles RCC global interrupt.
  */
void RCC_IRQHandler(void)
{
 8002642:	b480      	push	{r7}
 8002644:	af00      	add	r7, sp, #0

  /* USER CODE END RCC_IRQn 0 */
  /* USER CODE BEGIN RCC_IRQn 1 */

  /* USER CODE END RCC_IRQn 1 */
}
 8002646:	bf00      	nop
 8002648:	46bd      	mov	sp, r7
 800264a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800264e:	4770      	bx	lr

08002650 <DMA1_Stream0_IRQHandler>:

/**
  * @brief This function handles DMA1 stream0 global interrupt.
  */
void DMA1_Stream0_IRQHandler(void)
{
 8002650:	b580      	push	{r7, lr}
 8002652:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */

  /* USER CODE END DMA1_Stream0_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc1);
 8002654:	4802      	ldr	r0, [pc, #8]	@ (8002660 <DMA1_Stream0_IRQHandler+0x10>)
 8002656:	f004 f9f5 	bl	8006a44 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */

  /* USER CODE END DMA1_Stream0_IRQn 1 */
}
 800265a:	bf00      	nop
 800265c:	bd80      	pop	{r7, pc}
 800265e:	bf00      	nop
 8002660:	2400026c 	.word	0x2400026c

08002664 <DMA1_Stream1_IRQHandler>:

/**
  * @brief This function handles DMA1 stream1 global interrupt.
  */
void DMA1_Stream1_IRQHandler(void)
{
 8002664:	b580      	push	{r7, lr}
 8002666:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */

  /* USER CODE END DMA1_Stream1_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc2);
 8002668:	4802      	ldr	r0, [pc, #8]	@ (8002674 <DMA1_Stream1_IRQHandler+0x10>)
 800266a:	f004 f9eb 	bl	8006a44 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */

  /* USER CODE END DMA1_Stream1_IRQn 1 */
}
 800266e:	bf00      	nop
 8002670:	bd80      	pop	{r7, pc}
 8002672:	bf00      	nop
 8002674:	240002e4 	.word	0x240002e4

08002678 <DMA1_Stream2_IRQHandler>:

/**
  * @brief This function handles DMA1 stream2 global interrupt.
  */
void DMA1_Stream2_IRQHandler(void)
{
 8002678:	b580      	push	{r7, lr}
 800267a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */

  /* USER CODE END DMA1_Stream2_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc3);
 800267c:	4802      	ldr	r0, [pc, #8]	@ (8002688 <DMA1_Stream2_IRQHandler+0x10>)
 800267e:	f004 f9e1 	bl	8006a44 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */

  /* USER CODE END DMA1_Stream2_IRQn 1 */
}
 8002682:	bf00      	nop
 8002684:	bd80      	pop	{r7, pc}
 8002686:	bf00      	nop
 8002688:	2400035c 	.word	0x2400035c

0800268c <TIM2_IRQHandler>:

/**
  * @brief This function handles TIM2 global interrupt.
  */
void TIM2_IRQHandler(void)
{
 800268c:	b580      	push	{r7, lr}
 800268e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM2_IRQn 0 */

  /* USER CODE END TIM2_IRQn 0 */
  HAL_TIM_IRQHandler(&htim2);
 8002690:	4802      	ldr	r0, [pc, #8]	@ (800269c <TIM2_IRQHandler+0x10>)
 8002692:	f009 fdb3 	bl	800c1fc <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM2_IRQn 1 */

  /* USER CODE END TIM2_IRQn 1 */
}
 8002696:	bf00      	nop
 8002698:	bd80      	pop	{r7, pc}
 800269a:	bf00      	nop
 800269c:	2400040c 	.word	0x2400040c

080026a0 <USART1_IRQHandler>:

/**
  * @brief This function handles USART1 global interrupt.
  */
void USART1_IRQHandler(void)
{
 80026a0:	b580      	push	{r7, lr}
 80026a2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN USART1_IRQn 0 */

  /* USER CODE END USART1_IRQn 0 */
  HAL_UART_IRQHandler(&huart1);
 80026a4:	4802      	ldr	r0, [pc, #8]	@ (80026b0 <USART1_IRQHandler+0x10>)
 80026a6:	f00a faa5 	bl	800cbf4 <HAL_UART_IRQHandler>
  /* USER CODE BEGIN USART1_IRQn 1 */

  /* USER CODE END USART1_IRQn 1 */
}
 80026aa:	bf00      	nop
 80026ac:	bd80      	pop	{r7, pc}
 80026ae:	bf00      	nop
 80026b0:	240004ec 	.word	0x240004ec

080026b4 <TIM6_DAC_IRQHandler>:

/**
  * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts.
  */
void TIM6_DAC_IRQHandler(void)
{
 80026b4:	b580      	push	{r7, lr}
 80026b6:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */

  /* USER CODE END TIM6_DAC_IRQn 0 */
  HAL_TIM_IRQHandler(&htim6);
 80026b8:	4802      	ldr	r0, [pc, #8]	@ (80026c4 <TIM6_DAC_IRQHandler+0x10>)
 80026ba:	f009 fd9f 	bl	800c1fc <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */

  /* USER CODE END TIM6_DAC_IRQn 1 */
}
 80026be:	bf00      	nop
 80026c0:	bd80      	pop	{r7, pc}
 80026c2:	bf00      	nop
 80026c4:	24000618 	.word	0x24000618

080026c8 <UART8_IRQHandler>:

/**
  * @brief This function handles UART8 global interrupt.
  */
void UART8_IRQHandler(void)
{
 80026c8:	b580      	push	{r7, lr}
 80026ca:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UART8_IRQn 0 */

  /* USER CODE END UART8_IRQn 0 */
  HAL_UART_IRQHandler(&huart8);
 80026cc:	4802      	ldr	r0, [pc, #8]	@ (80026d8 <UART8_IRQHandler+0x10>)
 80026ce:	f00a fa91 	bl	800cbf4 <HAL_UART_IRQHandler>
  /* USER CODE BEGIN UART8_IRQn 1 */

  /* USER CODE END UART8_IRQn 1 */
}
 80026d2:	bf00      	nop
 80026d4:	bd80      	pop	{r7, pc}
 80026d6:	bf00      	nop
 80026d8:	24000458 	.word	0x24000458

080026dc <_read>:
  _kill(status, -1);
  while (1) {}    /* Make sure we hang here */
}

__attribute__((weak)) int _read(int file, char *ptr, int len)
{
 80026dc:	b580      	push	{r7, lr}
 80026de:	b086      	sub	sp, #24
 80026e0:	af00      	add	r7, sp, #0
 80026e2:	60f8      	str	r0, [r7, #12]
 80026e4:	60b9      	str	r1, [r7, #8]
 80026e6:	607a      	str	r2, [r7, #4]
  (void)file;
  int DataIdx;

  for (DataIdx = 0; DataIdx < len; DataIdx++)
 80026e8:	2300      	movs	r3, #0
 80026ea:	617b      	str	r3, [r7, #20]
 80026ec:	e00a      	b.n	8002704 <_read+0x28>
  {
    *ptr++ = __io_getchar();
 80026ee:	f3af 8000 	nop.w
 80026f2:	4601      	mov	r1, r0
 80026f4:	68bb      	ldr	r3, [r7, #8]
 80026f6:	1c5a      	adds	r2, r3, #1
 80026f8:	60ba      	str	r2, [r7, #8]
 80026fa:	b2ca      	uxtb	r2, r1
 80026fc:	701a      	strb	r2, [r3, #0]
  for (DataIdx = 0; DataIdx < len; DataIdx++)
 80026fe:	697b      	ldr	r3, [r7, #20]
 8002700:	3301      	adds	r3, #1
 8002702:	617b      	str	r3, [r7, #20]
 8002704:	697a      	ldr	r2, [r7, #20]
 8002706:	687b      	ldr	r3, [r7, #4]
 8002708:	429a      	cmp	r2, r3
 800270a:	dbf0      	blt.n	80026ee <_read+0x12>
  }

  return len;
 800270c:	687b      	ldr	r3, [r7, #4]
}
 800270e:	4618      	mov	r0, r3
 8002710:	3718      	adds	r7, #24
 8002712:	46bd      	mov	sp, r7
 8002714:	bd80      	pop	{r7, pc}

08002716 <_write>:

__attribute__((weak)) int _write(int file, char *ptr, int len)
{
 8002716:	b580      	push	{r7, lr}
 8002718:	b086      	sub	sp, #24
 800271a:	af00      	add	r7, sp, #0
 800271c:	60f8      	str	r0, [r7, #12]
 800271e:	60b9      	str	r1, [r7, #8]
 8002720:	607a      	str	r2, [r7, #4]
  (void)file;
  int DataIdx;

  for (DataIdx = 0; DataIdx < len; DataIdx++)
 8002722:	2300      	movs	r3, #0
 8002724:	617b      	str	r3, [r7, #20]
 8002726:	e009      	b.n	800273c <_write+0x26>
  {
    __io_putchar(*ptr++);
 8002728:	68bb      	ldr	r3, [r7, #8]
 800272a:	1c5a      	adds	r2, r3, #1
 800272c:	60ba      	str	r2, [r7, #8]
 800272e:	781b      	ldrb	r3, [r3, #0]
 8002730:	4618      	mov	r0, r3
 8002732:	f3af 8000 	nop.w
  for (DataIdx = 0; DataIdx < len; DataIdx++)
 8002736:	697b      	ldr	r3, [r7, #20]
 8002738:	3301      	adds	r3, #1
 800273a:	617b      	str	r3, [r7, #20]
 800273c:	697a      	ldr	r2, [r7, #20]
 800273e:	687b      	ldr	r3, [r7, #4]
 8002740:	429a      	cmp	r2, r3
 8002742:	dbf1      	blt.n	8002728 <_write+0x12>
  }
  return len;
 8002744:	687b      	ldr	r3, [r7, #4]
}
 8002746:	4618      	mov	r0, r3
 8002748:	3718      	adds	r7, #24
 800274a:	46bd      	mov	sp, r7
 800274c:	bd80      	pop	{r7, pc}

0800274e <_close>:

int _close(int file)
{
 800274e:	b480      	push	{r7}
 8002750:	b083      	sub	sp, #12
 8002752:	af00      	add	r7, sp, #0
 8002754:	6078      	str	r0, [r7, #4]
  (void)file;
  return -1;
 8002756:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
}
 800275a:	4618      	mov	r0, r3
 800275c:	370c      	adds	r7, #12
 800275e:	46bd      	mov	sp, r7
 8002760:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002764:	4770      	bx	lr

08002766 <_fstat>:


int _fstat(int file, struct stat *st)
{
 8002766:	b480      	push	{r7}
 8002768:	b083      	sub	sp, #12
 800276a:	af00      	add	r7, sp, #0
 800276c:	6078      	str	r0, [r7, #4]
 800276e:	6039      	str	r1, [r7, #0]
  (void)file;
  st->st_mode = S_IFCHR;
 8002770:	683b      	ldr	r3, [r7, #0]
 8002772:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
 8002776:	605a      	str	r2, [r3, #4]
  return 0;
 8002778:	2300      	movs	r3, #0
}
 800277a:	4618      	mov	r0, r3
 800277c:	370c      	adds	r7, #12
 800277e:	46bd      	mov	sp, r7
 8002780:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002784:	4770      	bx	lr

08002786 <_isatty>:

int _isatty(int file)
{
 8002786:	b480      	push	{r7}
 8002788:	b083      	sub	sp, #12
 800278a:	af00      	add	r7, sp, #0
 800278c:	6078      	str	r0, [r7, #4]
  (void)file;
  return 1;
 800278e:	2301      	movs	r3, #1
}
 8002790:	4618      	mov	r0, r3
 8002792:	370c      	adds	r7, #12
 8002794:	46bd      	mov	sp, r7
 8002796:	f85d 7b04 	ldr.w	r7, [sp], #4
 800279a:	4770      	bx	lr

0800279c <_lseek>:

int _lseek(int file, int ptr, int dir)
{
 800279c:	b480      	push	{r7}
 800279e:	b085      	sub	sp, #20
 80027a0:	af00      	add	r7, sp, #0
 80027a2:	60f8      	str	r0, [r7, #12]
 80027a4:	60b9      	str	r1, [r7, #8]
 80027a6:	607a      	str	r2, [r7, #4]
  (void)file;
  (void)ptr;
  (void)dir;
  return 0;
 80027a8:	2300      	movs	r3, #0
}
 80027aa:	4618      	mov	r0, r3
 80027ac:	3714      	adds	r7, #20
 80027ae:	46bd      	mov	sp, r7
 80027b0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80027b4:	4770      	bx	lr
	...

080027b8 <_sbrk>:
 *
 * @param incr Memory size
 * @return Pointer to allocated memory
 */
void *_sbrk(ptrdiff_t incr)
{
 80027b8:	b580      	push	{r7, lr}
 80027ba:	b086      	sub	sp, #24
 80027bc:	af00      	add	r7, sp, #0
 80027be:	6078      	str	r0, [r7, #4]
  extern uint8_t _end; /* Symbol defined in the linker script */
  extern uint8_t _estack; /* Symbol defined in the linker script */
  extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
  const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
 80027c0:	4a14      	ldr	r2, [pc, #80]	@ (8002814 <_sbrk+0x5c>)
 80027c2:	4b15      	ldr	r3, [pc, #84]	@ (8002818 <_sbrk+0x60>)
 80027c4:	1ad3      	subs	r3, r2, r3
 80027c6:	617b      	str	r3, [r7, #20]
  const uint8_t *max_heap = (uint8_t *)stack_limit;
 80027c8:	697b      	ldr	r3, [r7, #20]
 80027ca:	613b      	str	r3, [r7, #16]
  uint8_t *prev_heap_end;

  /* Initialize heap end at first call */
  if (NULL == __sbrk_heap_end)
 80027cc:	4b13      	ldr	r3, [pc, #76]	@ (800281c <_sbrk+0x64>)
 80027ce:	681b      	ldr	r3, [r3, #0]
 80027d0:	2b00      	cmp	r3, #0
 80027d2:	d102      	bne.n	80027da <_sbrk+0x22>
  {
    __sbrk_heap_end = &_end;
 80027d4:	4b11      	ldr	r3, [pc, #68]	@ (800281c <_sbrk+0x64>)
 80027d6:	4a12      	ldr	r2, [pc, #72]	@ (8002820 <_sbrk+0x68>)
 80027d8:	601a      	str	r2, [r3, #0]
  }

  /* Protect heap from growing into the reserved MSP stack */
  if (__sbrk_heap_end + incr > max_heap)
 80027da:	4b10      	ldr	r3, [pc, #64]	@ (800281c <_sbrk+0x64>)
 80027dc:	681a      	ldr	r2, [r3, #0]
 80027de:	687b      	ldr	r3, [r7, #4]
 80027e0:	4413      	add	r3, r2
 80027e2:	693a      	ldr	r2, [r7, #16]
 80027e4:	429a      	cmp	r2, r3
 80027e6:	d207      	bcs.n	80027f8 <_sbrk+0x40>
  {
    errno = ENOMEM;
 80027e8:	f011 f8a2 	bl	8013930 <__errno>
 80027ec:	4603      	mov	r3, r0
 80027ee:	220c      	movs	r2, #12
 80027f0:	601a      	str	r2, [r3, #0]
    return (void *)-1;
 80027f2:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 80027f6:	e009      	b.n	800280c <_sbrk+0x54>
  }

  prev_heap_end = __sbrk_heap_end;
 80027f8:	4b08      	ldr	r3, [pc, #32]	@ (800281c <_sbrk+0x64>)
 80027fa:	681b      	ldr	r3, [r3, #0]
 80027fc:	60fb      	str	r3, [r7, #12]
  __sbrk_heap_end += incr;
 80027fe:	4b07      	ldr	r3, [pc, #28]	@ (800281c <_sbrk+0x64>)
 8002800:	681a      	ldr	r2, [r3, #0]
 8002802:	687b      	ldr	r3, [r7, #4]
 8002804:	4413      	add	r3, r2
 8002806:	4a05      	ldr	r2, [pc, #20]	@ (800281c <_sbrk+0x64>)
 8002808:	6013      	str	r3, [r2, #0]

  return (void *)prev_heap_end;
 800280a:	68fb      	ldr	r3, [r7, #12]
}
 800280c:	4618      	mov	r0, r3
 800280e:	3718      	adds	r7, #24
 8002810:	46bd      	mov	sp, r7
 8002812:	bd80      	pop	{r7, pc}
 8002814:	24060000 	.word	0x24060000
 8002818:	00000400 	.word	0x00000400
 800281c:	24000664 	.word	0x24000664
 8002820:	24012b98 	.word	0x24012b98

08002824 <SystemInit>:
  *         configuration.
  * @param  None
  * @retval None
  */
void SystemInit (void)
{
 8002824:	b480      	push	{r7}
 8002826:	af00      	add	r7, sp, #0
 __IO uint32_t tmpreg;
#endif /* DATA_IN_D2_SRAM */

  /* FPU settings ------------------------------------------------------------*/
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
 8002828:	4b37      	ldr	r3, [pc, #220]	@ (8002908 <SystemInit+0xe4>)
 800282a:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800282e:	4a36      	ldr	r2, [pc, #216]	@ (8002908 <SystemInit+0xe4>)
 8002830:	f443 0370 	orr.w	r3, r3, #15728640	@ 0xf00000
 8002834:	f8c2 3088 	str.w	r3, [r2, #136]	@ 0x88
  #endif
  /* Reset the RCC clock configuration to the default reset state ------------*/

   /* Increasing the CPU frequency */
  if(FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
 8002838:	4b34      	ldr	r3, [pc, #208]	@ (800290c <SystemInit+0xe8>)
 800283a:	681b      	ldr	r3, [r3, #0]
 800283c:	f003 030f 	and.w	r3, r3, #15
 8002840:	2b06      	cmp	r3, #6
 8002842:	d807      	bhi.n	8002854 <SystemInit+0x30>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
 8002844:	4b31      	ldr	r3, [pc, #196]	@ (800290c <SystemInit+0xe8>)
 8002846:	681b      	ldr	r3, [r3, #0]
 8002848:	f023 030f 	bic.w	r3, r3, #15
 800284c:	4a2f      	ldr	r2, [pc, #188]	@ (800290c <SystemInit+0xe8>)
 800284e:	f043 0307 	orr.w	r3, r3, #7
 8002852:	6013      	str	r3, [r2, #0]
  }

  /* Set HSION bit */
  RCC->CR |= RCC_CR_HSION;
 8002854:	4b2e      	ldr	r3, [pc, #184]	@ (8002910 <SystemInit+0xec>)
 8002856:	681b      	ldr	r3, [r3, #0]
 8002858:	4a2d      	ldr	r2, [pc, #180]	@ (8002910 <SystemInit+0xec>)
 800285a:	f043 0301 	orr.w	r3, r3, #1
 800285e:	6013      	str	r3, [r2, #0]

  /* Reset CFGR register */
  RCC->CFGR = 0x00000000;
 8002860:	4b2b      	ldr	r3, [pc, #172]	@ (8002910 <SystemInit+0xec>)
 8002862:	2200      	movs	r2, #0
 8002864:	611a      	str	r2, [r3, #16]

  /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
  RCC->CR &= 0xEAF6ED7FU;
 8002866:	4b2a      	ldr	r3, [pc, #168]	@ (8002910 <SystemInit+0xec>)
 8002868:	681a      	ldr	r2, [r3, #0]
 800286a:	4929      	ldr	r1, [pc, #164]	@ (8002910 <SystemInit+0xec>)
 800286c:	4b29      	ldr	r3, [pc, #164]	@ (8002914 <SystemInit+0xf0>)
 800286e:	4013      	ands	r3, r2
 8002870:	600b      	str	r3, [r1, #0]

   /* Decreasing the number of wait states because of lower CPU frequency */
  if(FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
 8002872:	4b26      	ldr	r3, [pc, #152]	@ (800290c <SystemInit+0xe8>)
 8002874:	681b      	ldr	r3, [r3, #0]
 8002876:	f003 0308 	and.w	r3, r3, #8
 800287a:	2b00      	cmp	r3, #0
 800287c:	d007      	beq.n	800288e <SystemInit+0x6a>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
 800287e:	4b23      	ldr	r3, [pc, #140]	@ (800290c <SystemInit+0xe8>)
 8002880:	681b      	ldr	r3, [r3, #0]
 8002882:	f023 030f 	bic.w	r3, r3, #15
 8002886:	4a21      	ldr	r2, [pc, #132]	@ (800290c <SystemInit+0xe8>)
 8002888:	f043 0307 	orr.w	r3, r3, #7
 800288c:	6013      	str	r3, [r2, #0]
  }

#if defined(D3_SRAM_BASE)
  /* Reset D1CFGR register */
  RCC->D1CFGR = 0x00000000;
 800288e:	4b20      	ldr	r3, [pc, #128]	@ (8002910 <SystemInit+0xec>)
 8002890:	2200      	movs	r2, #0
 8002892:	619a      	str	r2, [r3, #24]

  /* Reset D2CFGR register */
  RCC->D2CFGR = 0x00000000;
 8002894:	4b1e      	ldr	r3, [pc, #120]	@ (8002910 <SystemInit+0xec>)
 8002896:	2200      	movs	r2, #0
 8002898:	61da      	str	r2, [r3, #28]

  /* Reset D3CFGR register */
  RCC->D3CFGR = 0x00000000;
 800289a:	4b1d      	ldr	r3, [pc, #116]	@ (8002910 <SystemInit+0xec>)
 800289c:	2200      	movs	r2, #0
 800289e:	621a      	str	r2, [r3, #32]

  /* Reset SRDCFGR register */
  RCC->SRDCFGR = 0x00000000;
#endif
  /* Reset PLLCKSELR register */
  RCC->PLLCKSELR = 0x02020200;
 80028a0:	4b1b      	ldr	r3, [pc, #108]	@ (8002910 <SystemInit+0xec>)
 80028a2:	4a1d      	ldr	r2, [pc, #116]	@ (8002918 <SystemInit+0xf4>)
 80028a4:	629a      	str	r2, [r3, #40]	@ 0x28

  /* Reset PLLCFGR register */
  RCC->PLLCFGR = 0x01FF0000;
 80028a6:	4b1a      	ldr	r3, [pc, #104]	@ (8002910 <SystemInit+0xec>)
 80028a8:	4a1c      	ldr	r2, [pc, #112]	@ (800291c <SystemInit+0xf8>)
 80028aa:	62da      	str	r2, [r3, #44]	@ 0x2c
  /* Reset PLL1DIVR register */
  RCC->PLL1DIVR = 0x01010280;
 80028ac:	4b18      	ldr	r3, [pc, #96]	@ (8002910 <SystemInit+0xec>)
 80028ae:	4a1c      	ldr	r2, [pc, #112]	@ (8002920 <SystemInit+0xfc>)
 80028b0:	631a      	str	r2, [r3, #48]	@ 0x30
  /* Reset PLL1FRACR register */
  RCC->PLL1FRACR = 0x00000000;
 80028b2:	4b17      	ldr	r3, [pc, #92]	@ (8002910 <SystemInit+0xec>)
 80028b4:	2200      	movs	r2, #0
 80028b6:	635a      	str	r2, [r3, #52]	@ 0x34

  /* Reset PLL2DIVR register */
  RCC->PLL2DIVR = 0x01010280;
 80028b8:	4b15      	ldr	r3, [pc, #84]	@ (8002910 <SystemInit+0xec>)
 80028ba:	4a19      	ldr	r2, [pc, #100]	@ (8002920 <SystemInit+0xfc>)
 80028bc:	639a      	str	r2, [r3, #56]	@ 0x38

  /* Reset PLL2FRACR register */

  RCC->PLL2FRACR = 0x00000000;
 80028be:	4b14      	ldr	r3, [pc, #80]	@ (8002910 <SystemInit+0xec>)
 80028c0:	2200      	movs	r2, #0
 80028c2:	63da      	str	r2, [r3, #60]	@ 0x3c
  /* Reset PLL3DIVR register */
  RCC->PLL3DIVR = 0x01010280;
 80028c4:	4b12      	ldr	r3, [pc, #72]	@ (8002910 <SystemInit+0xec>)
 80028c6:	4a16      	ldr	r2, [pc, #88]	@ (8002920 <SystemInit+0xfc>)
 80028c8:	641a      	str	r2, [r3, #64]	@ 0x40

  /* Reset PLL3FRACR register */
  RCC->PLL3FRACR = 0x00000000;
 80028ca:	4b11      	ldr	r3, [pc, #68]	@ (8002910 <SystemInit+0xec>)
 80028cc:	2200      	movs	r2, #0
 80028ce:	645a      	str	r2, [r3, #68]	@ 0x44

  /* Reset HSEBYP bit */
  RCC->CR &= 0xFFFBFFFFU;
 80028d0:	4b0f      	ldr	r3, [pc, #60]	@ (8002910 <SystemInit+0xec>)
 80028d2:	681b      	ldr	r3, [r3, #0]
 80028d4:	4a0e      	ldr	r2, [pc, #56]	@ (8002910 <SystemInit+0xec>)
 80028d6:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
 80028da:	6013      	str	r3, [r2, #0]

  /* Disable all interrupts */
  RCC->CIER = 0x00000000;
 80028dc:	4b0c      	ldr	r3, [pc, #48]	@ (8002910 <SystemInit+0xec>)
 80028de:	2200      	movs	r2, #0
 80028e0:	661a      	str	r2, [r3, #96]	@ 0x60

#if (STM32H7_DEV_ID == 0x450UL)
  /* dual core CM7 or single core line */
  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
 80028e2:	4b10      	ldr	r3, [pc, #64]	@ (8002924 <SystemInit+0x100>)
 80028e4:	681a      	ldr	r2, [r3, #0]
 80028e6:	4b10      	ldr	r3, [pc, #64]	@ (8002928 <SystemInit+0x104>)
 80028e8:	4013      	ands	r3, r2
 80028ea:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 80028ee:	d202      	bcs.n	80028f6 <SystemInit+0xd2>
  {
    /* if stm32h7 revY*/
    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
    *((__IO uint32_t*)0x51008108) = 0x000000001U;
 80028f0:	4b0e      	ldr	r3, [pc, #56]	@ (800292c <SystemInit+0x108>)
 80028f2:	2201      	movs	r2, #1
 80028f4:	601a      	str	r2, [r3, #0]
  /*
   * Disable the FMC bank1 (enabled after reset).
   * This, prevents CPU speculation access on this bank which blocks the use of FMC during
   * 24us. During this time the others FMC master (such as LTDC) cannot use it!
   */
  FMC_Bank1_R->BTCR[0] = 0x000030D2;
 80028f6:	4b0e      	ldr	r3, [pc, #56]	@ (8002930 <SystemInit+0x10c>)
 80028f8:	f243 02d2 	movw	r2, #12498	@ 0x30d2
 80028fc:	601a      	str	r2, [r3, #0]
#if defined(USER_VECT_TAB_ADDRESS)
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */

#endif /*DUAL_CORE && CORE_CM4*/
}
 80028fe:	bf00      	nop
 8002900:	46bd      	mov	sp, r7
 8002902:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002906:	4770      	bx	lr
 8002908:	e000ed00 	.word	0xe000ed00
 800290c:	52002000 	.word	0x52002000
 8002910:	58024400 	.word	0x58024400
 8002914:	eaf6ed7f 	.word	0xeaf6ed7f
 8002918:	02020200 	.word	0x02020200
 800291c:	01ff0000 	.word	0x01ff0000
 8002920:	01010280 	.word	0x01010280
 8002924:	5c001000 	.word	0x5c001000
 8002928:	ffff0000 	.word	0xffff0000
 800292c:	51008108 	.word	0x51008108
 8002930:	52004000 	.word	0x52004000

08002934 <UartTasksInit>:
//osMutexId_t resMeasurementsMutex;
//osMutexId_t sensorsInfoMutex;

extern RNG_HandleTypeDef hrng;

void UartTasksInit(void) {
 8002934:	b580      	push	{r7, lr}
 8002936:	af00      	add	r7, sp, #0
  uart1TaskData.uartRxBuffer = uart1RxBuffer;
 8002938:	4b13      	ldr	r3, [pc, #76]	@ (8002988 <UartTasksInit+0x54>)
 800293a:	4a14      	ldr	r2, [pc, #80]	@ (800298c <UartTasksInit+0x58>)
 800293c:	601a      	str	r2, [r3, #0]
  uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE;
 800293e:	4b12      	ldr	r3, [pc, #72]	@ (8002988 <UartTasksInit+0x54>)
 8002940:	f44f 7280 	mov.w	r2, #256	@ 0x100
 8002944:	809a      	strh	r2, [r3, #4]
  uart1TaskData.uartTxBuffer = uart1TxBuffer;
 8002946:	4b10      	ldr	r3, [pc, #64]	@ (8002988 <UartTasksInit+0x54>)
 8002948:	4a11      	ldr	r2, [pc, #68]	@ (8002990 <UartTasksInit+0x5c>)
 800294a:	609a      	str	r2, [r3, #8]
  uart1TaskData.uartRxBufferLen = UART1_TX_BUFF_SIZE;
 800294c:	4b0e      	ldr	r3, [pc, #56]	@ (8002988 <UartTasksInit+0x54>)
 800294e:	f44f 7280 	mov.w	r2, #256	@ 0x100
 8002952:	809a      	strh	r2, [r3, #4]
  uart1TaskData.frameData = uart1TaskFrameData;
 8002954:	4b0c      	ldr	r3, [pc, #48]	@ (8002988 <UartTasksInit+0x54>)
 8002956:	4a0f      	ldr	r2, [pc, #60]	@ (8002994 <UartTasksInit+0x60>)
 8002958:	611a      	str	r2, [r3, #16]
  uart1TaskData.frameDataLen = UART1_RX_BUFF_SIZE;
 800295a:	4b0b      	ldr	r3, [pc, #44]	@ (8002988 <UartTasksInit+0x54>)
 800295c:	f44f 7280 	mov.w	r2, #256	@ 0x100
 8002960:	829a      	strh	r2, [r3, #20]
  uart1TaskData.huart = &huart1;
 8002962:	4b09      	ldr	r3, [pc, #36]	@ (8002988 <UartTasksInit+0x54>)
 8002964:	4a0c      	ldr	r2, [pc, #48]	@ (8002998 <UartTasksInit+0x64>)
 8002966:	631a      	str	r2, [r3, #48]	@ 0x30
  uart1TaskData.uartNumber = 1;
 8002968:	4b07      	ldr	r3, [pc, #28]	@ (8002988 <UartTasksInit+0x54>)
 800296a:	2201      	movs	r2, #1
 800296c:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
  uart1TaskData.processDataCb = Uart1ReceivedDataProcessCallback;
 8002970:	4b05      	ldr	r3, [pc, #20]	@ (8002988 <UartTasksInit+0x54>)
 8002972:	4a0a      	ldr	r2, [pc, #40]	@ (800299c <UartTasksInit+0x68>)
 8002974:	629a      	str	r2, [r3, #40]	@ 0x28
  uart1TaskData.processRxDataMsgBuffer = NULL;
 8002976:	4b04      	ldr	r3, [pc, #16]	@ (8002988 <UartTasksInit+0x54>)
 8002978:	2200      	movs	r2, #0
 800297a:	625a      	str	r2, [r3, #36]	@ 0x24
//  uart8TaskData.huart = &huart8;
//  uart8TaskData.uartNumber = 8;
//  uart8TaskData.processDataCb = Uart8ReceivedDataProcessCallback;
//  uart8TaskData.processRxDataMsgBuffer = NULL;

  UartTaskCreate(&uart1TaskData);
 800297c:	4802      	ldr	r0, [pc, #8]	@ (8002988 <UartTasksInit+0x54>)
 800297e:	f000 f80f 	bl	80029a0 <UartTaskCreate>
//  UartTaskCreate(&uart8TaskData);
}
 8002982:	bf00      	nop
 8002984:	bd80      	pop	{r7, pc}
 8002986:	bf00      	nop
 8002988:	24000968 	.word	0x24000968
 800298c:	24000668 	.word	0x24000668
 8002990:	24000768 	.word	0x24000768
 8002994:	24000868 	.word	0x24000868
 8002998:	240004ec 	.word	0x240004ec
 800299c:	080030a5 	.word	0x080030a5

080029a0 <UartTaskCreate>:

void UartTaskCreate (UartTaskData* uartTaskData) {
 80029a0:	b580      	push	{r7, lr}
 80029a2:	b08c      	sub	sp, #48	@ 0x30
 80029a4:	af00      	add	r7, sp, #0
 80029a6:	6078      	str	r0, [r7, #4]
    osThreadAttr_t osThreadAttrRxUart = { 0 };
 80029a8:	f107 030c 	add.w	r3, r7, #12
 80029ac:	2224      	movs	r2, #36	@ 0x24
 80029ae:	2100      	movs	r1, #0
 80029b0:	4618      	mov	r0, r3
 80029b2:	f010 ff18 	bl	80137e6 <memset>
//    osThreadAttr_t osThreadAttrTxUart = { 0 };

    osThreadAttrRxUart.stack_size = configMINIMAL_STACK_SIZE * 2;
 80029b6:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 80029ba:	623b      	str	r3, [r7, #32]
    osThreadAttrRxUart.priority   = (osPriority_t)osPriorityHigh;
 80029bc:	2328      	movs	r3, #40	@ 0x28
 80029be:	627b      	str	r3, [r7, #36]	@ 0x24
    uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart);
 80029c0:	f107 030c 	add.w	r3, r7, #12
 80029c4:	461a      	mov	r2, r3
 80029c6:	6879      	ldr	r1, [r7, #4]
 80029c8:	4804      	ldr	r0, [pc, #16]	@ (80029dc <UartTaskCreate+0x3c>)
 80029ca:	f00c fe81 	bl	800f6d0 <osThreadNew>
 80029ce:	4602      	mov	r2, r0
 80029d0:	687b      	ldr	r3, [r7, #4]
 80029d2:	619a      	str	r2, [r3, #24]
//    uartTaskData->sendCmdToSlaveQueue = osMessageQueueNew (16, sizeof (InterProcessData), &uartTxMsgQueueAttr);

//    osThreadAttrTxUart.stack_size        = configMINIMAL_STACK_SIZE * 4;
//    osThreadAttrTxUart.priority          = (osPriority_t)osPriorityNormal;
//    uartTaskData->uartTransmitTaskHandle = osThreadNew (UartTxTask, uartTaskData, &osThreadAttrTxUart);
}
 80029d4:	bf00      	nop
 80029d6:	3730      	adds	r7, #48	@ 0x30
 80029d8:	46bd      	mov	sp, r7
 80029da:	bd80      	pop	{r7, pc}
 80029dc:	08002af5 	.word	0x08002af5

080029e0 <HAL_UART_RxCpltCallback>:
//    osThreadAttrTxUart.stack_size        = configMINIMAL_STACK_SIZE * 4;
//    osThreadAttrTxUart.priority          = (osPriority_t)osPriorityNormal;
//    uart8TaskData.uartTransmitTaskHandle = osThreadNew (UartTxTask, &uart8TaskData, &osThreadAttrTxUart);
}

void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) {
 80029e0:	b480      	push	{r7}
 80029e2:	b083      	sub	sp, #12
 80029e4:	af00      	add	r7, sp, #0
 80029e6:	6078      	str	r0, [r7, #4]
    //	osSemaphoreRelease(uart8RxSemaphore);
}
 80029e8:	bf00      	nop
 80029ea:	370c      	adds	r7, #12
 80029ec:	46bd      	mov	sp, r7
 80029ee:	f85d 7b04 	ldr.w	r7, [sp], #4
 80029f2:	4770      	bx	lr

080029f4 <HAL_UARTEx_RxEventCallback>:

void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef* huart, uint16_t Size) {
 80029f4:	b580      	push	{r7, lr}
 80029f6:	b082      	sub	sp, #8
 80029f8:	af00      	add	r7, sp, #0
 80029fa:	6078      	str	r0, [r7, #4]
 80029fc:	460b      	mov	r3, r1
 80029fe:	807b      	strh	r3, [r7, #2]
  if (huart->Instance == USART1) {
 8002a00:	687b      	ldr	r3, [r7, #4]
 8002a02:	681b      	ldr	r3, [r3, #0]
 8002a04:	4a0c      	ldr	r2, [pc, #48]	@ (8002a38 <HAL_UARTEx_RxEventCallback+0x44>)
 8002a06:	4293      	cmp	r3, r2
 8002a08:	d106      	bne.n	8002a18 <HAL_UARTEx_RxEventCallback+0x24>
    HandleUartRxCallback(&uart1TaskData, huart, Size);
 8002a0a:	887b      	ldrh	r3, [r7, #2]
 8002a0c:	461a      	mov	r2, r3
 8002a0e:	6879      	ldr	r1, [r7, #4]
 8002a10:	480a      	ldr	r0, [pc, #40]	@ (8002a3c <HAL_UARTEx_RxEventCallback+0x48>)
 8002a12:	f000 f823 	bl	8002a5c <HandleUartRxCallback>
  } else if (huart->Instance == UART8) {
    HandleUartRxCallback(&uart8TaskData, huart, Size);
  }
}
 8002a16:	e00a      	b.n	8002a2e <HAL_UARTEx_RxEventCallback+0x3a>
  } else if (huart->Instance == UART8) {
 8002a18:	687b      	ldr	r3, [r7, #4]
 8002a1a:	681b      	ldr	r3, [r3, #0]
 8002a1c:	4a08      	ldr	r2, [pc, #32]	@ (8002a40 <HAL_UARTEx_RxEventCallback+0x4c>)
 8002a1e:	4293      	cmp	r3, r2
 8002a20:	d105      	bne.n	8002a2e <HAL_UARTEx_RxEventCallback+0x3a>
    HandleUartRxCallback(&uart8TaskData, huart, Size);
 8002a22:	887b      	ldrh	r3, [r7, #2]
 8002a24:	461a      	mov	r2, r3
 8002a26:	6879      	ldr	r1, [r7, #4]
 8002a28:	4806      	ldr	r0, [pc, #24]	@ (8002a44 <HAL_UARTEx_RxEventCallback+0x50>)
 8002a2a:	f000 f817 	bl	8002a5c <HandleUartRxCallback>
}
 8002a2e:	bf00      	nop
 8002a30:	3708      	adds	r7, #8
 8002a32:	46bd      	mov	sp, r7
 8002a34:	bd80      	pop	{r7, pc}
 8002a36:	bf00      	nop
 8002a38:	40011000 	.word	0x40011000
 8002a3c:	24000968 	.word	0x24000968
 8002a40:	40007c00 	.word	0x40007c00
 8002a44:	240009a0 	.word	0x240009a0

08002a48 <HAL_UART_TxCpltCallback>:

void HAL_UART_TxCpltCallback (UART_HandleTypeDef* huart) {
 8002a48:	b480      	push	{r7}
 8002a4a:	b083      	sub	sp, #12
 8002a4c:	af00      	add	r7, sp, #0
 8002a4e:	6078      	str	r0, [r7, #4]
    if (huart->Instance == UART8) {
    }
}
 8002a50:	bf00      	nop
 8002a52:	370c      	adds	r7, #12
 8002a54:	46bd      	mov	sp, r7
 8002a56:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002a5a:	4770      	bx	lr

08002a5c <HandleUartRxCallback>:

void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) {
 8002a5c:	b580      	push	{r7, lr}
 8002a5e:	b088      	sub	sp, #32
 8002a60:	af02      	add	r7, sp, #8
 8002a62:	60f8      	str	r0, [r7, #12]
 8002a64:	60b9      	str	r1, [r7, #8]
 8002a66:	4613      	mov	r3, r2
 8002a68:	80fb      	strh	r3, [r7, #6]
    BaseType_t pxHigherPriorityTaskWoken = pdFALSE;
 8002a6a:	2300      	movs	r3, #0
 8002a6c:	617b      	str	r3, [r7, #20]
    osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
 8002a6e:	68fb      	ldr	r3, [r7, #12]
 8002a70:	6a1b      	ldr	r3, [r3, #32]
 8002a72:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8002a76:	4618      	mov	r0, r3
 8002a78:	f00c ff5e 	bl	800f938 <osMutexAcquire>
    memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size);
 8002a7c:	68fb      	ldr	r3, [r7, #12]
 8002a7e:	691b      	ldr	r3, [r3, #16]
 8002a80:	68fa      	ldr	r2, [r7, #12]
 8002a82:	8ad2      	ldrh	r2, [r2, #22]
 8002a84:	1898      	adds	r0, r3, r2
 8002a86:	68fb      	ldr	r3, [r7, #12]
 8002a88:	681b      	ldr	r3, [r3, #0]
 8002a8a:	88fa      	ldrh	r2, [r7, #6]
 8002a8c:	4619      	mov	r1, r3
 8002a8e:	f010 ff7c 	bl	801398a <memcpy>
    uartTaskData->frameBytesCount += Size;
 8002a92:	68fb      	ldr	r3, [r7, #12]
 8002a94:	8ada      	ldrh	r2, [r3, #22]
 8002a96:	88fb      	ldrh	r3, [r7, #6]
 8002a98:	4413      	add	r3, r2
 8002a9a:	b29a      	uxth	r2, r3
 8002a9c:	68fb      	ldr	r3, [r7, #12]
 8002a9e:	82da      	strh	r2, [r3, #22]
    osMutexRelease (uartTaskData->rxDataBufferMutex);
 8002aa0:	68fb      	ldr	r3, [r7, #12]
 8002aa2:	6a1b      	ldr	r3, [r3, #32]
 8002aa4:	4618      	mov	r0, r3
 8002aa6:	f00c ff92 	bl	800f9ce <osMutexRelease>
    xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken);
 8002aaa:	68fb      	ldr	r3, [r7, #12]
 8002aac:	6998      	ldr	r0, [r3, #24]
 8002aae:	88f9      	ldrh	r1, [r7, #6]
 8002ab0:	f107 0314 	add.w	r3, r7, #20
 8002ab4:	9300      	str	r3, [sp, #0]
 8002ab6:	2300      	movs	r3, #0
 8002ab8:	2203      	movs	r2, #3
 8002aba:	f00f fc83 	bl	80123c4 <xTaskGenericNotifyFromISR>
    //	HAL_UARTEx_ReceiveToIdle_DMA(huart, uart8RxBuffer, UART8_RX_BUFF_SIZE);
    //	__HAL_DMA_DISABLE_IT(&hdma_uart8_rx, DMA_IT_HT);
    HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
 8002abe:	68fb      	ldr	r3, [r7, #12]
 8002ac0:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 8002ac2:	68fb      	ldr	r3, [r7, #12]
 8002ac4:	6819      	ldr	r1, [r3, #0]
 8002ac6:	68fb      	ldr	r3, [r7, #12]
 8002ac8:	889b      	ldrh	r3, [r3, #4]
 8002aca:	461a      	mov	r2, r3
 8002acc:	f00c fcd3 	bl	800f476 <HAL_UARTEx_ReceiveToIdle_IT>
    portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken);
 8002ad0:	697b      	ldr	r3, [r7, #20]
 8002ad2:	2b00      	cmp	r3, #0
 8002ad4:	d007      	beq.n	8002ae6 <HandleUartRxCallback+0x8a>
 8002ad6:	4b06      	ldr	r3, [pc, #24]	@ (8002af0 <HandleUartRxCallback+0x94>)
 8002ad8:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8002adc:	601a      	str	r2, [r3, #0]
 8002ade:	f3bf 8f4f 	dsb	sy
 8002ae2:	f3bf 8f6f 	isb	sy
}
 8002ae6:	bf00      	nop
 8002ae8:	3718      	adds	r7, #24
 8002aea:	46bd      	mov	sp, r7
 8002aec:	bd80      	pop	{r7, pc}
 8002aee:	bf00      	nop
 8002af0:	e000ed04 	.word	0xe000ed04

08002af4 <UartRxTask>:

void UartRxTask (void* argument) {
 8002af4:	b580      	push	{r7, lr}
 8002af6:	b0d2      	sub	sp, #328	@ 0x148
 8002af8:	af02      	add	r7, sp, #8
 8002afa:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002afe:	f5a3 739e 	sub.w	r3, r3, #316	@ 0x13c
 8002b02:	6018      	str	r0, [r3, #0]
    UartTaskData* uartTaskData             = (UartTaskData*)argument;
 8002b04:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002b08:	f5a3 739e 	sub.w	r3, r3, #316	@ 0x13c
 8002b0c:	681b      	ldr	r3, [r3, #0]
 8002b0e:	f8c7 312c 	str.w	r3, [r7, #300]	@ 0x12c
    SerialProtocolFrameData spFrameData    = { 0 };
 8002b12:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002b16:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002b1a:	4618      	mov	r0, r3
 8002b1c:	f44f 7386 	mov.w	r3, #268	@ 0x10c
 8002b20:	461a      	mov	r2, r3
 8002b22:	2100      	movs	r1, #0
 8002b24:	f010 fe5f 	bl	80137e6 <memset>
    uint32_t bytesRec                      = 0;
 8002b28:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002b2c:	f5a3 739a 	sub.w	r3, r3, #308	@ 0x134
 8002b30:	2200      	movs	r2, #0
 8002b32:	601a      	str	r2, [r3, #0]
    uint32_t crc                           = 0;
 8002b34:	2300      	movs	r3, #0
 8002b36:	f8c7 3128 	str.w	r3, [r7, #296]	@ 0x128
    uint16_t frameCommandRaw               = 0x0000;
 8002b3a:	2300      	movs	r3, #0
 8002b3c:	f8a7 3126 	strh.w	r3, [r7, #294]	@ 0x126
    uint16_t frameBytesCount               = 0;
 8002b40:	2300      	movs	r3, #0
 8002b42:	f8a7 3124 	strh.w	r3, [r7, #292]	@ 0x124
    uint16_t frameCrc                      = 0;
 8002b46:	2300      	movs	r3, #0
 8002b48:	f8a7 3122 	strh.w	r3, [r7, #290]	@ 0x122
    uint16_t frameTotalLength              = 0;
 8002b4c:	2300      	movs	r3, #0
 8002b4e:	f8a7 313e 	strh.w	r3, [r7, #318]	@ 0x13e
    uint16_t dataToSend                    = 0;
 8002b52:	2300      	movs	r3, #0
 8002b54:	f8a7 313c 	strh.w	r3, [r7, #316]	@ 0x13c
    portBASE_TYPE crcPass                  = pdFAIL;
 8002b58:	2300      	movs	r3, #0
 8002b5a:	f8c7 3138 	str.w	r3, [r7, #312]	@ 0x138
    portBASE_TYPE proceed                  = pdFALSE;
 8002b5e:	2300      	movs	r3, #0
 8002b60:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
    portBASE_TYPE frameTimeout             = pdFAIL;
 8002b64:	2300      	movs	r3, #0
 8002b66:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
    enum SerialReceiverStates receverState = srWaitForHeader;
 8002b6a:	2300      	movs	r3, #0
 8002b6c:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133

    uartTaskData->rxDataBufferMutex = osMutexNew (NULL);
 8002b70:	2000      	movs	r0, #0
 8002b72:	f00c fe5b 	bl	800f82c <osMutexNew>
 8002b76:	4602      	mov	r2, r0
 8002b78:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002b7c:	621a      	str	r2, [r3, #32]
    HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
 8002b7e:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002b82:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 8002b84:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002b88:	6819      	ldr	r1, [r3, #0]
 8002b8a:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002b8e:	889b      	ldrh	r3, [r3, #4]
 8002b90:	461a      	mov	r2, r3
 8002b92:	f00c fc70 	bl	800f476 <HAL_UARTEx_ReceiveToIdle_IT>
    //	HAL_UARTEx_ReceiveToIdle_DMA(&huart8, uart8RxBuffer, 32);
    while (pdTRUE) {
        //		HAL_UART_Receive_IT(&huart8, uart8RxBuffer, 1);
        //		if(osSemaphoreAcquire(uart8RxSemaphore, pdMS_TO_TICKS(1000)) !=
        // osOK) 		if(xTaskNotifyWait(0, 0, &bytesRec, portMAX_DELAY) == pdTrue)
        frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
 8002b96:	f107 020c 	add.w	r2, r7, #12
 8002b9a:	f44f 63fa 	mov.w	r3, #2000	@ 0x7d0
 8002b9e:	2100      	movs	r1, #0
 8002ba0:	2000      	movs	r0, #0
 8002ba2:	f00f faed 	bl	8012180 <xTaskNotifyWait>
 8002ba6:	4603      	mov	r3, r0
 8002ba8:	2b00      	cmp	r3, #0
 8002baa:	bf0c      	ite	eq
 8002bac:	2301      	moveq	r3, #1
 8002bae:	2300      	movne	r3, #0
 8002bb0:	b2db      	uxtb	r3, r3
 8002bb2:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c

        osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
 8002bb6:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002bba:	6a1b      	ldr	r3, [r3, #32]
 8002bbc:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8002bc0:	4618      	mov	r0, r3
 8002bc2:	f00c feb9 	bl	800f938 <osMutexAcquire>
        frameBytesCount = uartTaskData->frameBytesCount;
 8002bc6:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002bca:	8adb      	ldrh	r3, [r3, #22]
 8002bcc:	f8a7 3124 	strh.w	r3, [r7, #292]	@ 0x124
        osMutexRelease (uartTaskData->rxDataBufferMutex);
 8002bd0:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002bd4:	6a1b      	ldr	r3, [r3, #32]
 8002bd6:	4618      	mov	r0, r3
 8002bd8:	f00c fef9 	bl	800f9ce <osMutexRelease>
        if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) {
 8002bdc:	f8d7 311c 	ldr.w	r3, [r7, #284]	@ 0x11c
 8002be0:	2b01      	cmp	r3, #1
 8002be2:	d10a      	bne.n	8002bfa <UartRxTask+0x106>
 8002be4:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 8002be8:	2b00      	cmp	r3, #0
 8002bea:	d006      	beq.n	8002bfa <UartRxTask+0x106>
            receverState = srFail;
 8002bec:	2304      	movs	r3, #4
 8002bee:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
            proceed      = pdTRUE;
 8002bf2:	2301      	movs	r3, #1
 8002bf4:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
 8002bf8:	e029      	b.n	8002c4e <UartRxTask+0x15a>
        } else {
            if (frameTimeout == pdFALSE) {
 8002bfa:	f8d7 311c 	ldr.w	r3, [r7, #284]	@ 0x11c
 8002bfe:	2b00      	cmp	r3, #0
 8002c00:	d111      	bne.n	8002c26 <UartRxTask+0x132>
                proceed = pdTRUE;
 8002c02:	2301      	movs	r3, #1
 8002c04:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
#if UART_TASK_LOGS
                printf ("Uart%d: RX bytes received: %ld\n", uartTaskData->uartNumber, bytesRec);
 8002c08:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002c0c:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8002c10:	4619      	mov	r1, r3
 8002c12:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002c16:	f5a3 739a 	sub.w	r3, r3, #308	@ 0x134
 8002c1a:	681b      	ldr	r3, [r3, #0]
 8002c1c:	461a      	mov	r2, r3
 8002c1e:	48c1      	ldr	r0, [pc, #772]	@ (8002f24 <UartRxTask+0x430>)
 8002c20:	f010 fd8c 	bl	801373c <iprintf>
 8002c24:	e22f      	b.n	8003086 <UartRxTask+0x592>
#endif
            } else {
                if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) {
 8002c26:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002c2a:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8002c2c:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 8002c30:	2b20      	cmp	r3, #32
 8002c32:	f040 8228 	bne.w	8003086 <UartRxTask+0x592>
                    HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
 8002c36:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002c3a:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 8002c3c:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002c40:	6819      	ldr	r1, [r3, #0]
 8002c42:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002c46:	889b      	ldrh	r3, [r3, #4]
 8002c48:	461a      	mov	r2, r3
 8002c4a:	f00c fc14 	bl	800f476 <HAL_UARTEx_ReceiveToIdle_IT>
                }
            }
        }

        while (proceed) {
 8002c4e:	e21a      	b.n	8003086 <UartRxTask+0x592>
            switch (receverState) {
 8002c50:	f897 3133 	ldrb.w	r3, [r7, #307]	@ 0x133
 8002c54:	2b04      	cmp	r3, #4
 8002c56:	f200 81f1 	bhi.w	800303c <UartRxTask+0x548>
 8002c5a:	a201      	add	r2, pc, #4	@ (adr r2, 8002c60 <UartRxTask+0x16c>)
 8002c5c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8002c60:	08002c75 	.word	0x08002c75
 8002c64:	08002dd7 	.word	0x08002dd7
 8002c68:	08002dbb 	.word	0x08002dbb
 8002c6c:	08002e77 	.word	0x08002e77
 8002c70:	08002f31 	.word	0x08002f31
            case srWaitForHeader:
                osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
 8002c74:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002c78:	6a1b      	ldr	r3, [r3, #32]
 8002c7a:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8002c7e:	4618      	mov	r0, r3
 8002c80:	f00c fe5a 	bl	800f938 <osMutexAcquire>
                if (uartTaskData->frameData[0] == FRAME_INDICATOR) {
 8002c84:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002c88:	691b      	ldr	r3, [r3, #16]
 8002c8a:	781b      	ldrb	r3, [r3, #0]
 8002c8c:	2baa      	cmp	r3, #170	@ 0xaa
 8002c8e:	f040 8082 	bne.w	8002d96 <UartRxTask+0x2a2>
                    if (frameBytesCount > FRAME_ID_LENGTH) {
 8002c92:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 8002c96:	2b02      	cmp	r3, #2
 8002c98:	d914      	bls.n	8002cc4 <UartRxTask+0x1d0>
                        spFrameData.frameHeader.frameId =
                        CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_ID_LENGTH - FRAME_COMMAND_LENGTH]));
 8002c9a:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002c9e:	691b      	ldr	r3, [r3, #16]
 8002ca0:	3302      	adds	r3, #2
 8002ca2:	781b      	ldrb	r3, [r3, #0]
 8002ca4:	021b      	lsls	r3, r3, #8
 8002ca6:	b21a      	sxth	r2, r3
 8002ca8:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002cac:	691b      	ldr	r3, [r3, #16]
 8002cae:	3301      	adds	r3, #1
 8002cb0:	781b      	ldrb	r3, [r3, #0]
 8002cb2:	b21b      	sxth	r3, r3
 8002cb4:	4313      	orrs	r3, r2
 8002cb6:	b21b      	sxth	r3, r3
 8002cb8:	b29a      	uxth	r2, r3
                        spFrameData.frameHeader.frameId =
 8002cba:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002cbe:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002cc2:	801a      	strh	r2, [r3, #0]
                    }
                    if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) {
 8002cc4:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 8002cc8:	2b04      	cmp	r3, #4
 8002cca:	d923      	bls.n	8002d14 <UartRxTask+0x220>
                        frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH]));
 8002ccc:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002cd0:	691b      	ldr	r3, [r3, #16]
 8002cd2:	3304      	adds	r3, #4
 8002cd4:	781b      	ldrb	r3, [r3, #0]
 8002cd6:	021b      	lsls	r3, r3, #8
 8002cd8:	b21a      	sxth	r2, r3
 8002cda:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002cde:	691b      	ldr	r3, [r3, #16]
 8002ce0:	3303      	adds	r3, #3
 8002ce2:	781b      	ldrb	r3, [r3, #0]
 8002ce4:	b21b      	sxth	r3, r3
 8002ce6:	4313      	orrs	r3, r2
 8002ce8:	b21b      	sxth	r3, r3
 8002cea:	f8a7 3126 	strh.w	r3, [r7, #294]	@ 0x126
                        spFrameData.frameHeader.frameCommand    = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF);
 8002cee:	f8b7 3126 	ldrh.w	r3, [r7, #294]	@ 0x126
 8002cf2:	b2da      	uxtb	r2, r3
 8002cf4:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002cf8:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002cfc:	709a      	strb	r2, [r3, #2]
                        spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE;
 8002cfe:	f9b7 3126 	ldrsh.w	r3, [r7, #294]	@ 0x126
 8002d02:	13db      	asrs	r3, r3, #15
 8002d04:	b21b      	sxth	r3, r3
 8002d06:	f003 0201 	and.w	r2, r3, #1
 8002d0a:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002d0e:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002d12:	609a      	str	r2, [r3, #8]
                    }
                    if ((frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH) && ((spFrameData.frameHeader.frameCommand & 0x8000) != 0)) {
 8002d14:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 8002d18:	2b05      	cmp	r3, #5
 8002d1a:	d913      	bls.n	8002d44 <UartRxTask+0x250>
 8002d1c:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002d20:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002d24:	789b      	ldrb	r3, [r3, #2]
 8002d26:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 8002d2a:	2b00      	cmp	r3, #0
 8002d2c:	d00a      	beq.n	8002d44 <UartRxTask+0x250>
                        spFrameData.frameHeader.respStatus = (SerialProtocolRespStatus)(uartTaskData->frameData[FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH]);
 8002d2e:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002d32:	691b      	ldr	r3, [r3, #16]
 8002d34:	3305      	adds	r3, #5
 8002d36:	781b      	ldrb	r3, [r3, #0]
 8002d38:	b25a      	sxtb	r2, r3
 8002d3a:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002d3e:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002d42:	70da      	strb	r2, [r3, #3]
                    }
                    if (frameBytesCount >= FRAME_HEADER_LENGTH) {
 8002d44:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 8002d48:	2b07      	cmp	r3, #7
 8002d4a:	d920      	bls.n	8002d8e <UartRxTask+0x29a>
                        spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH]));
 8002d4c:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002d50:	691b      	ldr	r3, [r3, #16]
 8002d52:	3306      	adds	r3, #6
 8002d54:	781b      	ldrb	r3, [r3, #0]
 8002d56:	021b      	lsls	r3, r3, #8
 8002d58:	b21a      	sxth	r2, r3
 8002d5a:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002d5e:	691b      	ldr	r3, [r3, #16]
 8002d60:	3305      	adds	r3, #5
 8002d62:	781b      	ldrb	r3, [r3, #0]
 8002d64:	b21b      	sxth	r3, r3
 8002d66:	4313      	orrs	r3, r2
 8002d68:	b21b      	sxth	r3, r3
 8002d6a:	b29a      	uxth	r2, r3
 8002d6c:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002d70:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002d74:	809a      	strh	r2, [r3, #4]
                        frameTotalLength                        = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH;
 8002d76:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002d7a:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002d7e:	889b      	ldrh	r3, [r3, #4]
 8002d80:	330a      	adds	r3, #10
 8002d82:	f8a7 313e 	strh.w	r3, [r7, #318]	@ 0x13e
                        receverState                            = srRecieveData;
 8002d86:	2302      	movs	r3, #2
 8002d88:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
 8002d8c:	e00e      	b.n	8002dac <UartRxTask+0x2b8>
                    } else {
                        proceed = pdFALSE;
 8002d8e:	2300      	movs	r3, #0
 8002d90:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
 8002d94:	e00a      	b.n	8002dac <UartRxTask+0x2b8>
                    }
                } else {
                    if (frameBytesCount > 0) {
 8002d96:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 8002d9a:	2b00      	cmp	r3, #0
 8002d9c:	d003      	beq.n	8002da6 <UartRxTask+0x2b2>
                        receverState = srFail;
 8002d9e:	2304      	movs	r3, #4
 8002da0:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
 8002da4:	e002      	b.n	8002dac <UartRxTask+0x2b8>
                    } else {
                        proceed = pdFALSE;
 8002da6:	2300      	movs	r3, #0
 8002da8:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
                    }
                }
                osMutexRelease (uartTaskData->rxDataBufferMutex);
 8002dac:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002db0:	6a1b      	ldr	r3, [r3, #32]
 8002db2:	4618      	mov	r0, r3
 8002db4:	f00c fe0b 	bl	800f9ce <osMutexRelease>
                break;
 8002db8:	e165      	b.n	8003086 <UartRxTask+0x592>
            case srRecieveData:
                if (frameBytesCount >= frameTotalLength) {
 8002dba:	f8b7 2124 	ldrh.w	r2, [r7, #292]	@ 0x124
 8002dbe:	f8b7 313e 	ldrh.w	r3, [r7, #318]	@ 0x13e
 8002dc2:	429a      	cmp	r2, r3
 8002dc4:	d303      	bcc.n	8002dce <UartRxTask+0x2da>
                    receverState = srCheckCrc;
 8002dc6:	2301      	movs	r3, #1
 8002dc8:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                } else {
                    proceed = pdFALSE;
                }
                break;
 8002dcc:	e15b      	b.n	8003086 <UartRxTask+0x592>
                    proceed = pdFALSE;
 8002dce:	2300      	movs	r3, #0
 8002dd0:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
                break;
 8002dd4:	e157      	b.n	8003086 <UartRxTask+0x592>
            case srCheckCrc:
                osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
 8002dd6:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002dda:	6a1b      	ldr	r3, [r3, #32]
 8002ddc:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8002de0:	4618      	mov	r0, r3
 8002de2:	f00c fda9 	bl	800f938 <osMutexAcquire>
                frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH]));
 8002de6:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002dea:	691a      	ldr	r2, [r3, #16]
 8002dec:	f8b7 313e 	ldrh.w	r3, [r7, #318]	@ 0x13e
 8002df0:	3b01      	subs	r3, #1
 8002df2:	4413      	add	r3, r2
 8002df4:	781b      	ldrb	r3, [r3, #0]
 8002df6:	021b      	lsls	r3, r3, #8
 8002df8:	b21a      	sxth	r2, r3
 8002dfa:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002dfe:	6919      	ldr	r1, [r3, #16]
 8002e00:	f8b7 313e 	ldrh.w	r3, [r7, #318]	@ 0x13e
 8002e04:	3b02      	subs	r3, #2
 8002e06:	440b      	add	r3, r1
 8002e08:	781b      	ldrb	r3, [r3, #0]
 8002e0a:	b21b      	sxth	r3, r3
 8002e0c:	4313      	orrs	r3, r2
 8002e0e:	b21b      	sxth	r3, r3
 8002e10:	f8a7 3122 	strh.w	r3, [r7, #290]	@ 0x122
                crc      = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH);
 8002e14:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002e18:	6919      	ldr	r1, [r3, #16]
 8002e1a:	f8b7 313e 	ldrh.w	r3, [r7, #318]	@ 0x13e
 8002e1e:	3b02      	subs	r3, #2
 8002e20:	461a      	mov	r2, r3
 8002e22:	4841      	ldr	r0, [pc, #260]	@ (8002f28 <UartRxTask+0x434>)
 8002e24:	f002 f942 	bl	80050ac <HAL_CRC_Calculate>
 8002e28:	f8c7 0128 	str.w	r0, [r7, #296]	@ 0x128
                osMutexRelease (uartTaskData->rxDataBufferMutex);
 8002e2c:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002e30:	6a1b      	ldr	r3, [r3, #32]
 8002e32:	4618      	mov	r0, r3
 8002e34:	f00c fdcb 	bl	800f9ce <osMutexRelease>
                crcPass = frameCrc == crc;
 8002e38:	f8b7 3122 	ldrh.w	r3, [r7, #290]	@ 0x122
 8002e3c:	f8d7 2128 	ldr.w	r2, [r7, #296]	@ 0x128
 8002e40:	429a      	cmp	r2, r3
 8002e42:	bf0c      	ite	eq
 8002e44:	2301      	moveq	r3, #1
 8002e46:	2300      	movne	r3, #0
 8002e48:	b2db      	uxtb	r3, r3
 8002e4a:	f8c7 3138 	str.w	r3, [r7, #312]	@ 0x138
                if (crcPass) {
 8002e4e:	f8d7 3138 	ldr.w	r3, [r7, #312]	@ 0x138
 8002e52:	2b00      	cmp	r3, #0
 8002e54:	d00b      	beq.n	8002e6e <UartRxTask+0x37a>
#if UART_TASK_LOGS
                    printf ("Uart%d: Frame CRC PASS\n", uartTaskData->uartNumber);
 8002e56:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002e5a:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8002e5e:	4619      	mov	r1, r3
 8002e60:	4832      	ldr	r0, [pc, #200]	@ (8002f2c <UartRxTask+0x438>)
 8002e62:	f010 fc6b 	bl	801373c <iprintf>
#endif
                    receverState = srExecuteCmd;
 8002e66:	2303      	movs	r3, #3
 8002e68:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                } else {
                    receverState = srFail;
                }
                break;
 8002e6c:	e10b      	b.n	8003086 <UartRxTask+0x592>
                    receverState = srFail;
 8002e6e:	2304      	movs	r3, #4
 8002e70:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                break;
 8002e74:	e107      	b.n	8003086 <UartRxTask+0x592>
            case srExecuteCmd:
                if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) {
 8002e76:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002e7a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002e7c:	2b00      	cmp	r3, #0
 8002e7e:	d104      	bne.n	8002e8a <UartRxTask+0x396>
 8002e80:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002e84:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8002e86:	2b00      	cmp	r3, #0
 8002e88:	d01e      	beq.n	8002ec8 <UartRxTask+0x3d4>
                    osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
 8002e8a:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002e8e:	6a1b      	ldr	r3, [r3, #32]
 8002e90:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8002e94:	4618      	mov	r0, r3
 8002e96:	f00c fd4f 	bl	800f938 <osMutexAcquire>
                    memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength);
 8002e9a:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002e9e:	691b      	ldr	r3, [r3, #16]
 8002ea0:	f103 0108 	add.w	r1, r3, #8
 8002ea4:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002ea8:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002eac:	889b      	ldrh	r3, [r3, #4]
 8002eae:	461a      	mov	r2, r3
 8002eb0:	f107 0310 	add.w	r3, r7, #16
 8002eb4:	330c      	adds	r3, #12
 8002eb6:	4618      	mov	r0, r3
 8002eb8:	f010 fd67 	bl	801398a <memcpy>
                    osMutexRelease (uartTaskData->rxDataBufferMutex);
 8002ebc:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002ec0:	6a1b      	ldr	r3, [r3, #32]
 8002ec2:	4618      	mov	r0, r3
 8002ec4:	f00c fd83 	bl	800f9ce <osMutexRelease>
                }

                if (uartTaskData->processRxDataMsgBuffer != NULL) {
 8002ec8:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002ecc:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8002ece:	2b00      	cmp	r3, #0
 8002ed0:	d015      	beq.n	8002efe <UartRxTask+0x40a>
                    if(xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE)
 8002ed2:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002ed6:	6a58      	ldr	r0, [r3, #36]	@ 0x24
 8002ed8:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002edc:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002ee0:	889b      	ldrh	r3, [r3, #4]
 8002ee2:	f103 020c 	add.w	r2, r3, #12
 8002ee6:	f107 0110 	add.w	r1, r7, #16
 8002eea:	23c8      	movs	r3, #200	@ 0xc8
 8002eec:	f00d ff92 	bl	8010e14 <xStreamBufferSend>
 8002ef0:	4603      	mov	r3, r0
 8002ef2:	2b00      	cmp	r3, #0
 8002ef4:	d103      	bne.n	8002efe <UartRxTask+0x40a>
                    {
                    	receverState = srFail;
 8002ef6:	2304      	movs	r3, #4
 8002ef8:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                    	break;
 8002efc:	e0c3      	b.n	8003086 <UartRxTask+0x592>
                    }
                }
                if (uartTaskData->processDataCb != NULL) {
 8002efe:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002f02:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002f04:	2b00      	cmp	r3, #0
 8002f06:	d008      	beq.n	8002f1a <UartRxTask+0x426>
                    uartTaskData->processDataCb (uartTaskData, &spFrameData);
 8002f08:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002f0c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8002f0e:	f107 0210 	add.w	r2, r7, #16
 8002f12:	4611      	mov	r1, r2
 8002f14:	f8d7 012c 	ldr.w	r0, [r7, #300]	@ 0x12c
 8002f18:	4798      	blx	r3
                }
                receverState = srFinish;
 8002f1a:	2305      	movs	r3, #5
 8002f1c:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                break;
 8002f20:	e0b1      	b.n	8003086 <UartRxTask+0x592>
 8002f22:	bf00      	nop
 8002f24:	08014518 	.word	0x08014518
 8002f28:	240003d4 	.word	0x240003d4
 8002f2c:	08014538 	.word	0x08014538
            case srFail:
                dataToSend = 0;
 8002f30:	2300      	movs	r3, #0
 8002f32:	f8a7 313c 	strh.w	r3, [r7, #316]	@ 0x13c
                if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) {
 8002f36:	f8d7 311c 	ldr.w	r3, [r7, #284]	@ 0x11c
 8002f3a:	2b01      	cmp	r3, #1
 8002f3c:	d124      	bne.n	8002f88 <UartRxTask+0x494>
 8002f3e:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 8002f42:	2b02      	cmp	r3, #2
 8002f44:	d920      	bls.n	8002f88 <UartRxTask+0x494>
                    dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0);
 8002f46:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002f4a:	6898      	ldr	r0, [r3, #8]
 8002f4c:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002f50:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002f54:	8819      	ldrh	r1, [r3, #0]
 8002f56:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002f5a:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002f5e:	789a      	ldrb	r2, [r3, #2]
 8002f60:	2300      	movs	r3, #0
 8002f62:	9301      	str	r3, [sp, #4]
 8002f64:	2300      	movs	r3, #0
 8002f66:	9300      	str	r3, [sp, #0]
 8002f68:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8002f6c:	f7fe fefa 	bl	8001d64 <PrepareRespFrame>
 8002f70:	4603      	mov	r3, r0
 8002f72:	f8a7 313c 	strh.w	r3, [r7, #316]	@ 0x13c
#if UART_TASK_LOGS
                    printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber);
 8002f76:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002f7a:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8002f7e:	4619      	mov	r1, r3
 8002f80:	4844      	ldr	r0, [pc, #272]	@ (8003094 <UartRxTask+0x5a0>)
 8002f82:	f010 fbdb 	bl	801373c <iprintf>
 8002f86:	e03c      	b.n	8003002 <UartRxTask+0x50e>
#endif
                } else if (!crcPass) {
 8002f88:	f8d7 3138 	ldr.w	r3, [r7, #312]	@ 0x138
 8002f8c:	2b00      	cmp	r3, #0
 8002f8e:	d120      	bne.n	8002fd2 <UartRxTask+0x4de>
                    dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0);
 8002f90:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002f94:	6898      	ldr	r0, [r3, #8]
 8002f96:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002f9a:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002f9e:	8819      	ldrh	r1, [r3, #0]
 8002fa0:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002fa4:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002fa8:	789a      	ldrb	r2, [r3, #2]
 8002faa:	2300      	movs	r3, #0
 8002fac:	9301      	str	r3, [sp, #4]
 8002fae:	2300      	movs	r3, #0
 8002fb0:	9300      	str	r3, [sp, #0]
 8002fb2:	f06f 0301 	mvn.w	r3, #1
 8002fb6:	f7fe fed5 	bl	8001d64 <PrepareRespFrame>
 8002fba:	4603      	mov	r3, r0
 8002fbc:	f8a7 313c 	strh.w	r3, [r7, #316]	@ 0x13c
#if UART_TASK_LOGS
                    printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber);
 8002fc0:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002fc4:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8002fc8:	4619      	mov	r1, r3
 8002fca:	4833      	ldr	r0, [pc, #204]	@ (8003098 <UartRxTask+0x5a4>)
 8002fcc:	f010 fbb6 	bl	801373c <iprintf>
 8002fd0:	e017      	b.n	8003002 <UartRxTask+0x50e>
#endif
                }
                else
                {
                	dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0);
 8002fd2:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8002fd6:	6898      	ldr	r0, [r3, #8]
 8002fd8:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002fdc:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002fe0:	8819      	ldrh	r1, [r3, #0]
 8002fe2:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8002fe6:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8002fea:	789a      	ldrb	r2, [r3, #2]
 8002fec:	2300      	movs	r3, #0
 8002fee:	9301      	str	r3, [sp, #4]
 8002ff0:	2300      	movs	r3, #0
 8002ff2:	9300      	str	r3, [sp, #0]
 8002ff4:	f06f 0303 	mvn.w	r3, #3
 8002ff8:	f7fe feb4 	bl	8001d64 <PrepareRespFrame>
 8002ffc:	4603      	mov	r3, r0
 8002ffe:	f8a7 313c 	strh.w	r3, [r7, #316]	@ 0x13c
                }
                if (dataToSend > 0) {
 8003002:	f8b7 313c 	ldrh.w	r3, [r7, #316]	@ 0x13c
 8003006:	2b00      	cmp	r3, #0
 8003008:	d00a      	beq.n	8003020 <UartRxTask+0x52c>
                    HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend);
 800300a:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800300e:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 8003010:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8003014:	689b      	ldr	r3, [r3, #8]
 8003016:	f8b7 213c 	ldrh.w	r2, [r7, #316]	@ 0x13c
 800301a:	4619      	mov	r1, r3
 800301c:	f009 fd56 	bl	800cacc <HAL_UART_Transmit_IT>
                }
#if UART_TASK_LOGS
                printf ("Uart%d: TX bytes sent: %d\n", dataToSend, uartTaskData->uartNumber);
 8003020:	f8b7 113c 	ldrh.w	r1, [r7, #316]	@ 0x13c
 8003024:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8003028:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 800302c:	461a      	mov	r2, r3
 800302e:	481b      	ldr	r0, [pc, #108]	@ (800309c <UartRxTask+0x5a8>)
 8003030:	f010 fb84 	bl	801373c <iprintf>
#endif
                receverState = srFinish;
 8003034:	2305      	movs	r3, #5
 8003036:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                break;
 800303a:	e024      	b.n	8003086 <UartRxTask+0x592>
            case srFinish:
            default:
                osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
 800303c:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8003040:	6a1b      	ldr	r3, [r3, #32]
 8003042:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8003046:	4618      	mov	r0, r3
 8003048:	f00c fc76 	bl	800f938 <osMutexAcquire>
                uartTaskData->frameBytesCount = 0;
 800304c:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8003050:	2200      	movs	r2, #0
 8003052:	82da      	strh	r2, [r3, #22]
                osMutexRelease (uartTaskData->rxDataBufferMutex);
 8003054:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8003058:	6a1b      	ldr	r3, [r3, #32]
 800305a:	4618      	mov	r0, r3
 800305c:	f00c fcb7 	bl	800f9ce <osMutexRelease>
                spFrameData.frameHeader.frameCommand = spUnknown;
 8003060:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8003064:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8003068:	2209      	movs	r2, #9
 800306a:	709a      	strb	r2, [r3, #2]
                frameTotalLength                     = 0;
 800306c:	2300      	movs	r3, #0
 800306e:	f8a7 313e 	strh.w	r3, [r7, #318]	@ 0x13e
                outputDataBufferPos                  = 0;
 8003072:	4b0b      	ldr	r3, [pc, #44]	@ (80030a0 <UartRxTask+0x5ac>)
 8003074:	2200      	movs	r2, #0
 8003076:	801a      	strh	r2, [r3, #0]
                receverState                         = srWaitForHeader;
 8003078:	2300      	movs	r3, #0
 800307a:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                proceed                              = pdFALSE;
 800307e:	2300      	movs	r3, #0
 8003080:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
                break;
 8003084:	bf00      	nop
        while (proceed) {
 8003086:	f8d7 3134 	ldr.w	r3, [r7, #308]	@ 0x134
 800308a:	2b00      	cmp	r3, #0
 800308c:	f47f ade0 	bne.w	8002c50 <UartRxTask+0x15c>
        frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
 8003090:	e581      	b.n	8002b96 <UartRxTask+0xa2>
 8003092:	bf00      	nop
 8003094:	08014550 	.word	0x08014550
 8003098:	08014574 	.word	0x08014574
 800309c:	0801458c 	.word	0x0801458c
 80030a0:	24000a58 	.word	0x24000a58

080030a4 <Uart1ReceivedDataProcessCallback>:
void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData)
{
	Uart1ReceivedDataProcessCallback(arg, spFrameData);
}

void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) {
 80030a4:	b590      	push	{r4, r7, lr}
 80030a6:	b08f      	sub	sp, #60	@ 0x3c
 80030a8:	af02      	add	r7, sp, #8
 80030aa:	6078      	str	r0, [r7, #4]
 80030ac:	6039      	str	r1, [r7, #0]
    UartTaskData* uartTaskData = (UartTaskData*)arg;
 80030ae:	687b      	ldr	r3, [r7, #4]
 80030b0:	613b      	str	r3, [r7, #16]
    uint16_t dataToSend        = 0;
 80030b2:	2300      	movs	r3, #0
 80030b4:	81fb      	strh	r3, [r7, #14]
    outputDataBufferPos = 0;
 80030b6:	4b99      	ldr	r3, [pc, #612]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 80030b8:	2200      	movs	r2, #0
 80030ba:	801a      	strh	r2, [r3, #0]
    SerialProtocolRespStatus respStatus = spUnknownCommand;
 80030bc:	23fd      	movs	r3, #253	@ 0xfd
 80030be:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
    switch (spFrameData->frameHeader.frameCommand) {
 80030c2:	683b      	ldr	r3, [r7, #0]
 80030c4:	789b      	ldrb	r3, [r3, #2]
 80030c6:	2b08      	cmp	r3, #8
 80030c8:	f200 814e 	bhi.w	8003368 <Uart1ReceivedDataProcessCallback+0x2c4>
 80030cc:	a201      	add	r2, pc, #4	@ (adr r2, 80030d4 <Uart1ReceivedDataProcessCallback+0x30>)
 80030ce:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80030d2:	bf00      	nop
 80030d4:	080030f9 	.word	0x080030f9
 80030d8:	080031d9 	.word	0x080031d9
 80030dc:	080032a1 	.word	0x080032a1
 80030e0:	080032a1 	.word	0x080032a1
 80030e4:	080032a1 	.word	0x080032a1
 80030e8:	080032b1 	.word	0x080032b1
 80030ec:	080032b1 	.word	0x080032b1
 80030f0:	080032a9 	.word	0x080032a9
 80030f4:	080032b9 	.word	0x080032b9
    case spGetElectricalMeasurments:
    	osMutexAcquire (resMeasurementsMutex, osWaitForever);
 80030f8:	4b89      	ldr	r3, [pc, #548]	@ (8003320 <Uart1ReceivedDataProcessCallback+0x27c>)
 80030fa:	681b      	ldr	r3, [r3, #0]
 80030fc:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8003100:	4618      	mov	r0, r3
 8003102:	f00c fc19 	bl	800f938 <osMutexAcquire>
		for(int i = 0; i < 3; i++)
 8003106:	2300      	movs	r3, #0
 8003108:	62bb      	str	r3, [r7, #40]	@ 0x28
 800310a:	e00b      	b.n	8003124 <Uart1ReceivedDataProcessCallback+0x80>
		{
			WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof(float));
 800310c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800310e:	009b      	lsls	r3, r3, #2
 8003110:	4a84      	ldr	r2, [pc, #528]	@ (8003324 <Uart1ReceivedDataProcessCallback+0x280>)
 8003112:	441a      	add	r2, r3
 8003114:	2304      	movs	r3, #4
 8003116:	4981      	ldr	r1, [pc, #516]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 8003118:	4883      	ldr	r0, [pc, #524]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 800311a:	f7fe fdf1 	bl	8001d00 <WriteDataToBuffer>
		for(int i = 0; i < 3; i++)
 800311e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8003120:	3301      	adds	r3, #1
 8003122:	62bb      	str	r3, [r7, #40]	@ 0x28
 8003124:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8003126:	2b02      	cmp	r3, #2
 8003128:	ddf0      	ble.n	800310c <Uart1ReceivedDataProcessCallback+0x68>
		}
		for(int i = 0; i < 3; i++)
 800312a:	2300      	movs	r3, #0
 800312c:	627b      	str	r3, [r7, #36]	@ 0x24
 800312e:	e00d      	b.n	800314c <Uart1ReceivedDataProcessCallback+0xa8>
		{
			WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof(float));
 8003130:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003132:	3302      	adds	r3, #2
 8003134:	009b      	lsls	r3, r3, #2
 8003136:	4a7b      	ldr	r2, [pc, #492]	@ (8003324 <Uart1ReceivedDataProcessCallback+0x280>)
 8003138:	4413      	add	r3, r2
 800313a:	1d1a      	adds	r2, r3, #4
 800313c:	2304      	movs	r3, #4
 800313e:	4977      	ldr	r1, [pc, #476]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 8003140:	4879      	ldr	r0, [pc, #484]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 8003142:	f7fe fddd 	bl	8001d00 <WriteDataToBuffer>
		for(int i = 0; i < 3; i++)
 8003146:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003148:	3301      	adds	r3, #1
 800314a:	627b      	str	r3, [r7, #36]	@ 0x24
 800314c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800314e:	2b02      	cmp	r3, #2
 8003150:	ddee      	ble.n	8003130 <Uart1ReceivedDataProcessCallback+0x8c>
		}
		for(int i = 0; i < 3; i++)
 8003152:	2300      	movs	r3, #0
 8003154:	623b      	str	r3, [r7, #32]
 8003156:	e00c      	b.n	8003172 <Uart1ReceivedDataProcessCallback+0xce>
		{
			WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof(float));
 8003158:	6a3b      	ldr	r3, [r7, #32]
 800315a:	3306      	adds	r3, #6
 800315c:	009b      	lsls	r3, r3, #2
 800315e:	4a71      	ldr	r2, [pc, #452]	@ (8003324 <Uart1ReceivedDataProcessCallback+0x280>)
 8003160:	441a      	add	r2, r3
 8003162:	2304      	movs	r3, #4
 8003164:	496d      	ldr	r1, [pc, #436]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 8003166:	4870      	ldr	r0, [pc, #448]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 8003168:	f7fe fdca 	bl	8001d00 <WriteDataToBuffer>
		for(int i = 0; i < 3; i++)
 800316c:	6a3b      	ldr	r3, [r7, #32]
 800316e:	3301      	adds	r3, #1
 8003170:	623b      	str	r3, [r7, #32]
 8003172:	6a3b      	ldr	r3, [r7, #32]
 8003174:	2b02      	cmp	r3, #2
 8003176:	ddef      	ble.n	8003158 <Uart1ReceivedDataProcessCallback+0xb4>
		}
		for(int i = 0; i < 3; i++)
 8003178:	2300      	movs	r3, #0
 800317a:	61fb      	str	r3, [r7, #28]
 800317c:	e00d      	b.n	800319a <Uart1ReceivedDataProcessCallback+0xf6>
		{
			WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof(float));
 800317e:	69fb      	ldr	r3, [r7, #28]
 8003180:	3308      	adds	r3, #8
 8003182:	009b      	lsls	r3, r3, #2
 8003184:	4a67      	ldr	r2, [pc, #412]	@ (8003324 <Uart1ReceivedDataProcessCallback+0x280>)
 8003186:	4413      	add	r3, r2
 8003188:	1d1a      	adds	r2, r3, #4
 800318a:	2304      	movs	r3, #4
 800318c:	4963      	ldr	r1, [pc, #396]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 800318e:	4866      	ldr	r0, [pc, #408]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 8003190:	f7fe fdb6 	bl	8001d00 <WriteDataToBuffer>
		for(int i = 0; i < 3; i++)
 8003194:	69fb      	ldr	r3, [r7, #28]
 8003196:	3301      	adds	r3, #1
 8003198:	61fb      	str	r3, [r7, #28]
 800319a:	69fb      	ldr	r3, [r7, #28]
 800319c:	2b02      	cmp	r3, #2
 800319e:	ddee      	ble.n	800317e <Uart1ReceivedDataProcessCallback+0xda>
		}
		for(int i = 0; i < 3; i++)
 80031a0:	2300      	movs	r3, #0
 80031a2:	61bb      	str	r3, [r7, #24]
 80031a4:	e00c      	b.n	80031c0 <Uart1ReceivedDataProcessCallback+0x11c>
		{
			WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof(float));
 80031a6:	69bb      	ldr	r3, [r7, #24]
 80031a8:	330c      	adds	r3, #12
 80031aa:	009b      	lsls	r3, r3, #2
 80031ac:	4a5d      	ldr	r2, [pc, #372]	@ (8003324 <Uart1ReceivedDataProcessCallback+0x280>)
 80031ae:	441a      	add	r2, r3
 80031b0:	2304      	movs	r3, #4
 80031b2:	495a      	ldr	r1, [pc, #360]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 80031b4:	485c      	ldr	r0, [pc, #368]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 80031b6:	f7fe fda3 	bl	8001d00 <WriteDataToBuffer>
		for(int i = 0; i < 3; i++)
 80031ba:	69bb      	ldr	r3, [r7, #24]
 80031bc:	3301      	adds	r3, #1
 80031be:	61bb      	str	r3, [r7, #24]
 80031c0:	69bb      	ldr	r3, [r7, #24]
 80031c2:	2b02      	cmp	r3, #2
 80031c4:	ddef      	ble.n	80031a6 <Uart1ReceivedDataProcessCallback+0x102>
		}
        osMutexRelease(resMeasurementsMutex);
 80031c6:	4b56      	ldr	r3, [pc, #344]	@ (8003320 <Uart1ReceivedDataProcessCallback+0x27c>)
 80031c8:	681b      	ldr	r3, [r3, #0]
 80031ca:	4618      	mov	r0, r3
 80031cc:	f00c fbff 	bl	800f9ce <osMutexRelease>
        respStatus = spOK;
 80031d0:	2300      	movs	r3, #0
 80031d2:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
        break;
 80031d6:	e0cb      	b.n	8003370 <Uart1ReceivedDataProcessCallback+0x2cc>
    case spGetSensorMeasurments:
    	osMutexAcquire (sensorsInfoMutex, osWaitForever);
 80031d8:	4b54      	ldr	r3, [pc, #336]	@ (800332c <Uart1ReceivedDataProcessCallback+0x288>)
 80031da:	681b      	ldr	r3, [r3, #0]
 80031dc:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80031e0:	4618      	mov	r0, r3
 80031e2:	f00c fba9 	bl	800f938 <osMutexAcquire>
    	WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof(float));
 80031e6:	2304      	movs	r3, #4
 80031e8:	4a51      	ldr	r2, [pc, #324]	@ (8003330 <Uart1ReceivedDataProcessCallback+0x28c>)
 80031ea:	494c      	ldr	r1, [pc, #304]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 80031ec:	484e      	ldr	r0, [pc, #312]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 80031ee:	f7fe fd87 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof(float));
 80031f2:	2304      	movs	r3, #4
 80031f4:	4a4f      	ldr	r2, [pc, #316]	@ (8003334 <Uart1ReceivedDataProcessCallback+0x290>)
 80031f6:	4949      	ldr	r1, [pc, #292]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 80031f8:	484b      	ldr	r0, [pc, #300]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 80031fa:	f7fe fd81 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof(float));
 80031fe:	2304      	movs	r3, #4
 8003200:	4a4d      	ldr	r2, [pc, #308]	@ (8003338 <Uart1ReceivedDataProcessCallback+0x294>)
 8003202:	4946      	ldr	r1, [pc, #280]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 8003204:	4848      	ldr	r0, [pc, #288]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 8003206:	f7fe fd7b 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoder, sizeof(float));
 800320a:	2304      	movs	r3, #4
 800320c:	4a4b      	ldr	r2, [pc, #300]	@ (800333c <Uart1ReceivedDataProcessCallback+0x298>)
 800320e:	4943      	ldr	r1, [pc, #268]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 8003210:	4845      	ldr	r0, [pc, #276]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 8003212:	f7fe fd75 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof(uint8_t));
 8003216:	2301      	movs	r3, #1
 8003218:	4a49      	ldr	r2, [pc, #292]	@ (8003340 <Uart1ReceivedDataProcessCallback+0x29c>)
 800321a:	4940      	ldr	r1, [pc, #256]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 800321c:	4842      	ldr	r0, [pc, #264]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 800321e:	f7fe fd6f 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof(uint8_t));
 8003222:	2301      	movs	r3, #1
 8003224:	4a47      	ldr	r2, [pc, #284]	@ (8003344 <Uart1ReceivedDataProcessCallback+0x2a0>)
 8003226:	493d      	ldr	r1, [pc, #244]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 8003228:	483f      	ldr	r0, [pc, #252]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 800322a:	f7fe fd69 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof(float));
 800322e:	2304      	movs	r3, #4
 8003230:	4a45      	ldr	r2, [pc, #276]	@ (8003348 <Uart1ReceivedDataProcessCallback+0x2a4>)
 8003232:	493a      	ldr	r1, [pc, #232]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 8003234:	483c      	ldr	r0, [pc, #240]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 8003236:	f7fe fd63 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof(float));
 800323a:	2304      	movs	r3, #4
 800323c:	4a43      	ldr	r2, [pc, #268]	@ (800334c <Uart1ReceivedDataProcessCallback+0x2a8>)
 800323e:	4937      	ldr	r1, [pc, #220]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 8003240:	4839      	ldr	r0, [pc, #228]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 8003242:	f7fe fd5d 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof(float));
 8003246:	2304      	movs	r3, #4
 8003248:	4a41      	ldr	r2, [pc, #260]	@ (8003350 <Uart1ReceivedDataProcessCallback+0x2ac>)
 800324a:	4934      	ldr	r1, [pc, #208]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 800324c:	4836      	ldr	r0, [pc, #216]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 800324e:	f7fe fd57 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof(float));
 8003252:	2304      	movs	r3, #4
 8003254:	4a3f      	ldr	r2, [pc, #252]	@ (8003354 <Uart1ReceivedDataProcessCallback+0x2b0>)
 8003256:	4931      	ldr	r1, [pc, #196]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 8003258:	4833      	ldr	r0, [pc, #204]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 800325a:	f7fe fd51 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitSwitchUp, sizeof(uint8_t));
 800325e:	2301      	movs	r3, #1
 8003260:	4a3d      	ldr	r2, [pc, #244]	@ (8003358 <Uart1ReceivedDataProcessCallback+0x2b4>)
 8003262:	492e      	ldr	r1, [pc, #184]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 8003264:	4830      	ldr	r0, [pc, #192]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 8003266:	f7fe fd4b 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitSwitchDown, sizeof(uint8_t));
 800326a:	2301      	movs	r3, #1
 800326c:	4a3b      	ldr	r2, [pc, #236]	@ (800335c <Uart1ReceivedDataProcessCallback+0x2b8>)
 800326e:	492b      	ldr	r1, [pc, #172]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 8003270:	482d      	ldr	r0, [pc, #180]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 8003272:	f7fe fd45 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitSwitchCenter, sizeof(uint8_t));
 8003276:	2301      	movs	r3, #1
 8003278:	4a39      	ldr	r2, [pc, #228]	@ (8003360 <Uart1ReceivedDataProcessCallback+0x2bc>)
 800327a:	4928      	ldr	r1, [pc, #160]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 800327c:	482a      	ldr	r0, [pc, #168]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 800327e:	f7fe fd3f 	bl	8001d00 <WriteDataToBuffer>
		WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof(uint8_t));
 8003282:	2301      	movs	r3, #1
 8003284:	4a37      	ldr	r2, [pc, #220]	@ (8003364 <Uart1ReceivedDataProcessCallback+0x2c0>)
 8003286:	4925      	ldr	r1, [pc, #148]	@ (800331c <Uart1ReceivedDataProcessCallback+0x278>)
 8003288:	4827      	ldr	r0, [pc, #156]	@ (8003328 <Uart1ReceivedDataProcessCallback+0x284>)
 800328a:	f7fe fd39 	bl	8001d00 <WriteDataToBuffer>
    	osMutexRelease(sensorsInfoMutex);
 800328e:	4b27      	ldr	r3, [pc, #156]	@ (800332c <Uart1ReceivedDataProcessCallback+0x288>)
 8003290:	681b      	ldr	r3, [r3, #0]
 8003292:	4618      	mov	r0, r3
 8003294:	f00c fb9b 	bl	800f9ce <osMutexRelease>
    	respStatus = spOK;
 8003298:	2300      	movs	r3, #0
 800329a:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
    	break;
 800329e:	e067      	b.n	8003370 <Uart1ReceivedDataProcessCallback+0x2cc>
    case spSetFanSpeed:
    case spSetMotorXOn:
    case spSetMotorYOn:
    	respStatus = spOK;
 80032a0:	2300      	movs	r3, #0
 80032a2:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
        break;
 80032a6:	e063      	b.n	8003370 <Uart1ReceivedDataProcessCallback+0x2cc>
    case spSetDiodeOn:
    	respStatus = spOK;
 80032a8:	2300      	movs	r3, #0
 80032aa:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
    	break;
 80032ae:	e05f      	b.n	8003370 <Uart1ReceivedDataProcessCallback+0x2cc>
    case spSetmotorXMaxCurrent:
    case spSetmotorYMaxCurrent:
    	respStatus = spOK;
 80032b0:	2300      	movs	r3, #0
 80032b2:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
    	break;
 80032b6:	e05b      	b.n	8003370 <Uart1ReceivedDataProcessCallback+0x2cc>
    case spClearPeakMeasurments:
    	osMutexAcquire (resMeasurementsMutex, osWaitForever);
 80032b8:	4b19      	ldr	r3, [pc, #100]	@ (8003320 <Uart1ReceivedDataProcessCallback+0x27c>)
 80032ba:	681b      	ldr	r3, [r3, #0]
 80032bc:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80032c0:	4618      	mov	r0, r3
 80032c2:	f00c fb39 	bl	800f938 <osMutexAcquire>
		for(int i = 0; i < 3; i++)
 80032c6:	2300      	movs	r3, #0
 80032c8:	617b      	str	r3, [r7, #20]
 80032ca:	e01b      	b.n	8003304 <Uart1ReceivedDataProcessCallback+0x260>
		{
			resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i];
 80032cc:	4a15      	ldr	r2, [pc, #84]	@ (8003324 <Uart1ReceivedDataProcessCallback+0x280>)
 80032ce:	697b      	ldr	r3, [r7, #20]
 80032d0:	009b      	lsls	r3, r3, #2
 80032d2:	4413      	add	r3, r2
 80032d4:	681a      	ldr	r2, [r3, #0]
 80032d6:	4913      	ldr	r1, [pc, #76]	@ (8003324 <Uart1ReceivedDataProcessCallback+0x280>)
 80032d8:	697b      	ldr	r3, [r7, #20]
 80032da:	3302      	adds	r3, #2
 80032dc:	009b      	lsls	r3, r3, #2
 80032de:	440b      	add	r3, r1
 80032e0:	3304      	adds	r3, #4
 80032e2:	601a      	str	r2, [r3, #0]
			resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i];
 80032e4:	4a0f      	ldr	r2, [pc, #60]	@ (8003324 <Uart1ReceivedDataProcessCallback+0x280>)
 80032e6:	697b      	ldr	r3, [r7, #20]
 80032e8:	3306      	adds	r3, #6
 80032ea:	009b      	lsls	r3, r3, #2
 80032ec:	4413      	add	r3, r2
 80032ee:	681a      	ldr	r2, [r3, #0]
 80032f0:	490c      	ldr	r1, [pc, #48]	@ (8003324 <Uart1ReceivedDataProcessCallback+0x280>)
 80032f2:	697b      	ldr	r3, [r7, #20]
 80032f4:	3308      	adds	r3, #8
 80032f6:	009b      	lsls	r3, r3, #2
 80032f8:	440b      	add	r3, r1
 80032fa:	3304      	adds	r3, #4
 80032fc:	601a      	str	r2, [r3, #0]
		for(int i = 0; i < 3; i++)
 80032fe:	697b      	ldr	r3, [r7, #20]
 8003300:	3301      	adds	r3, #1
 8003302:	617b      	str	r3, [r7, #20]
 8003304:	697b      	ldr	r3, [r7, #20]
 8003306:	2b02      	cmp	r3, #2
 8003308:	dde0      	ble.n	80032cc <Uart1ReceivedDataProcessCallback+0x228>
		}
    	osMutexRelease(resMeasurementsMutex);
 800330a:	4b05      	ldr	r3, [pc, #20]	@ (8003320 <Uart1ReceivedDataProcessCallback+0x27c>)
 800330c:	681b      	ldr	r3, [r3, #0]
 800330e:	4618      	mov	r0, r3
 8003310:	f00c fb5d 	bl	800f9ce <osMutexRelease>
    	respStatus = spOK;
 8003314:	2300      	movs	r3, #0
 8003316:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
    	break;
 800331a:	e029      	b.n	8003370 <Uart1ReceivedDataProcessCallback+0x2cc>
 800331c:	24000a58 	.word	0x24000a58
 8003320:	240005a0 	.word	0x240005a0
 8003324:	240005ac 	.word	0x240005ac
 8003328:	240009d8 	.word	0x240009d8
 800332c:	240005a4 	.word	0x240005a4
 8003330:	240005e8 	.word	0x240005e8
 8003334:	240005ec 	.word	0x240005ec
 8003338:	240005f0 	.word	0x240005f0
 800333c:	240005f4 	.word	0x240005f4
 8003340:	240005f8 	.word	0x240005f8
 8003344:	240005f9 	.word	0x240005f9
 8003348:	240005fc 	.word	0x240005fc
 800334c:	24000600 	.word	0x24000600
 8003350:	24000604 	.word	0x24000604
 8003354:	24000608 	.word	0x24000608
 8003358:	2400060c 	.word	0x2400060c
 800335c:	2400060d 	.word	0x2400060d
 8003360:	2400060e 	.word	0x2400060e
 8003364:	2400060f 	.word	0x2400060f
    default:
    	respStatus = spUnknownCommand;
 8003368:	23fd      	movs	r3, #253	@ 0xfd
 800336a:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
    	break;
 800336e:	bf00      	nop
    }
    dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
 8003370:	693b      	ldr	r3, [r7, #16]
 8003372:	6898      	ldr	r0, [r3, #8]
 8003374:	683b      	ldr	r3, [r7, #0]
 8003376:	8819      	ldrh	r1, [r3, #0]
 8003378:	683b      	ldr	r3, [r7, #0]
 800337a:	789a      	ldrb	r2, [r3, #2]
 800337c:	4b11      	ldr	r3, [pc, #68]	@ (80033c4 <Uart1ReceivedDataProcessCallback+0x320>)
 800337e:	881b      	ldrh	r3, [r3, #0]
 8003380:	f997 402f 	ldrsb.w	r4, [r7, #47]	@ 0x2f
 8003384:	9301      	str	r3, [sp, #4]
 8003386:	4b10      	ldr	r3, [pc, #64]	@ (80033c8 <Uart1ReceivedDataProcessCallback+0x324>)
 8003388:	9300      	str	r3, [sp, #0]
 800338a:	4623      	mov	r3, r4
 800338c:	f7fe fcea 	bl	8001d64 <PrepareRespFrame>
 8003390:	4603      	mov	r3, r0
 8003392:	81fb      	strh	r3, [r7, #14]
    if (dataToSend > 0) {
 8003394:	89fb      	ldrh	r3, [r7, #14]
 8003396:	2b00      	cmp	r3, #0
 8003398:	d007      	beq.n	80033aa <Uart1ReceivedDataProcessCallback+0x306>
        HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend);
 800339a:	693b      	ldr	r3, [r7, #16]
 800339c:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 800339e:	693b      	ldr	r3, [r7, #16]
 80033a0:	689b      	ldr	r3, [r3, #8]
 80033a2:	89fa      	ldrh	r2, [r7, #14]
 80033a4:	4619      	mov	r1, r3
 80033a6:	f009 fb91 	bl	800cacc <HAL_UART_Transmit_IT>
    }
#if UART_TASK_LOGS
    printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend);
 80033aa:	693b      	ldr	r3, [r7, #16]
 80033ac:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 80033b0:	4619      	mov	r1, r3
 80033b2:	89fb      	ldrh	r3, [r7, #14]
 80033b4:	461a      	mov	r2, r3
 80033b6:	4805      	ldr	r0, [pc, #20]	@ (80033cc <Uart1ReceivedDataProcessCallback+0x328>)
 80033b8:	f010 f9c0 	bl	801373c <iprintf>
#endif
}
 80033bc:	bf00      	nop
 80033be:	3734      	adds	r7, #52	@ 0x34
 80033c0:	46bd      	mov	sp, r7
 80033c2:	bd90      	pop	{r4, r7, pc}
 80033c4:	24000a58 	.word	0x24000a58
 80033c8:	240009d8 	.word	0x240009d8
 80033cc:	0801458c 	.word	0x0801458c

080033d0 <Reset_Handler>:

    .section  .text.Reset_Handler
  .weak  Reset_Handler
  .type  Reset_Handler, %function
Reset_Handler:
  ldr   sp, =_estack      /* set stack pointer */
 80033d0:	f8df d034 	ldr.w	sp, [pc, #52]	@ 8003408 <LoopFillZerobss+0xe>

/* Call the clock system initialization function.*/
  bl  SystemInit
 80033d4:	f7ff fa26 	bl	8002824 <SystemInit>

/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 80033d8:	480c      	ldr	r0, [pc, #48]	@ (800340c <LoopFillZerobss+0x12>)
  ldr r1, =_edata
 80033da:	490d      	ldr	r1, [pc, #52]	@ (8003410 <LoopFillZerobss+0x16>)
  ldr r2, =_sidata
 80033dc:	4a0d      	ldr	r2, [pc, #52]	@ (8003414 <LoopFillZerobss+0x1a>)
  movs r3, #0
 80033de:	2300      	movs	r3, #0
  b LoopCopyDataInit
 80033e0:	e002      	b.n	80033e8 <LoopCopyDataInit>

080033e2 <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 80033e2:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 80033e4:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 80033e6:	3304      	adds	r3, #4

080033e8 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 80033e8:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 80033ea:	428c      	cmp	r4, r1
  bcc CopyDataInit
 80033ec:	d3f9      	bcc.n	80033e2 <CopyDataInit>
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 80033ee:	4a0a      	ldr	r2, [pc, #40]	@ (8003418 <LoopFillZerobss+0x1e>)
  ldr r4, =_ebss
 80033f0:	4c0a      	ldr	r4, [pc, #40]	@ (800341c <LoopFillZerobss+0x22>)
  movs r3, #0
 80033f2:	2300      	movs	r3, #0
  b LoopFillZerobss
 80033f4:	e001      	b.n	80033fa <LoopFillZerobss>

080033f6 <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 80033f6:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 80033f8:	3204      	adds	r2, #4

080033fa <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 80033fa:	42a2      	cmp	r2, r4
  bcc FillZerobss
 80033fc:	d3fb      	bcc.n	80033f6 <FillZerobss>

/* Call static constructors */
    bl __libc_init_array
 80033fe:	f010 fa9d 	bl	801393c <__libc_init_array>
/* Call the application's entry point.*/
  bl  main
 8003402:	f7fd f941 	bl	8000688 <main>
  bx  lr
 8003406:	4770      	bx	lr
  ldr   sp, =_estack      /* set stack pointer */
 8003408:	24060000 	.word	0x24060000
  ldr r0, =_sdata
 800340c:	24000000 	.word	0x24000000
  ldr r1, =_edata
 8003410:	240000a4 	.word	0x240000a4
  ldr r2, =_sidata
 8003414:	08014668 	.word	0x08014668
  ldr r2, =_sbss
 8003418:	240000c0 	.word	0x240000c0
  ldr r4, =_ebss
 800341c:	24012b94 	.word	0x24012b94

08003420 <ADC3_IRQHandler>:
 * @retval None
*/
    .section  .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b  Infinite_Loop
 8003420:	e7fe      	b.n	8003420 <ADC3_IRQHandler>
	...

08003424 <HAL_Init>:
  *         need to ensure that the SysTick time base is always set to 1 millisecond
  *         to have correct HAL operation.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 8003424:	b580      	push	{r7, lr}
 8003426:	b082      	sub	sp, #8
 8003428:	af00      	add	r7, sp, #0
   __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL);  /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
   __HAL_ART_ENABLE();                           /* Enable the Cortex-M4 ART */
#endif /* DUAL_CORE &&  CORE_CM4 */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 800342a:	2003      	movs	r0, #3
 800342c:	f001 fd2f 	bl	8004e8e <HAL_NVIC_SetPriorityGrouping>

  /* Update the SystemCoreClock global variable */
#if defined(RCC_D1CFGR_D1CPRE)
  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
 8003430:	f005 fe48 	bl	80090c4 <HAL_RCC_GetSysClockFreq>
 8003434:	4602      	mov	r2, r0
 8003436:	4b15      	ldr	r3, [pc, #84]	@ (800348c <HAL_Init+0x68>)
 8003438:	699b      	ldr	r3, [r3, #24]
 800343a:	0a1b      	lsrs	r3, r3, #8
 800343c:	f003 030f 	and.w	r3, r3, #15
 8003440:	4913      	ldr	r1, [pc, #76]	@ (8003490 <HAL_Init+0x6c>)
 8003442:	5ccb      	ldrb	r3, [r1, r3]
 8003444:	f003 031f 	and.w	r3, r3, #31
 8003448:	fa22 f303 	lsr.w	r3, r2, r3
 800344c:	607b      	str	r3, [r7, #4]
  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif

  /* Update the SystemD2Clock global variable */
#if defined(RCC_D1CFGR_HPRE)
  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 800344e:	4b0f      	ldr	r3, [pc, #60]	@ (800348c <HAL_Init+0x68>)
 8003450:	699b      	ldr	r3, [r3, #24]
 8003452:	f003 030f 	and.w	r3, r3, #15
 8003456:	4a0e      	ldr	r2, [pc, #56]	@ (8003490 <HAL_Init+0x6c>)
 8003458:	5cd3      	ldrb	r3, [r2, r3]
 800345a:	f003 031f 	and.w	r3, r3, #31
 800345e:	687a      	ldr	r2, [r7, #4]
 8003460:	fa22 f303 	lsr.w	r3, r2, r3
 8003464:	4a0b      	ldr	r2, [pc, #44]	@ (8003494 <HAL_Init+0x70>)
 8003466:	6013      	str	r3, [r2, #0]
#endif

#if defined(DUAL_CORE) && defined(CORE_CM4)
  SystemCoreClock = SystemD2Clock;
#else
  SystemCoreClock = common_system_clock;
 8003468:	4a0b      	ldr	r2, [pc, #44]	@ (8003498 <HAL_Init+0x74>)
 800346a:	687b      	ldr	r3, [r7, #4]
 800346c:	6013      	str	r3, [r2, #0]
#endif /* DUAL_CORE && CORE_CM4 */

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 800346e:	200f      	movs	r0, #15
 8003470:	f7ff f860 	bl	8002534 <HAL_InitTick>
 8003474:	4603      	mov	r3, r0
 8003476:	2b00      	cmp	r3, #0
 8003478:	d001      	beq.n	800347e <HAL_Init+0x5a>
  {
    return HAL_ERROR;
 800347a:	2301      	movs	r3, #1
 800347c:	e002      	b.n	8003484 <HAL_Init+0x60>
  }

  /* Init the low level hardware */
  HAL_MspInit();
 800347e:	f7fe fd0f 	bl	8001ea0 <HAL_MspInit>

  /* Return function status */
  return HAL_OK;
 8003482:	2300      	movs	r3, #0
}
 8003484:	4618      	mov	r0, r3
 8003486:	3708      	adds	r7, #8
 8003488:	46bd      	mov	sp, r7
 800348a:	bd80      	pop	{r7, pc}
 800348c:	58024400 	.word	0x58024400
 8003490:	080145e4 	.word	0x080145e4
 8003494:	24000038 	.word	0x24000038
 8003498:	24000034 	.word	0x24000034

0800349c <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 800349c:	b480      	push	{r7}
 800349e:	af00      	add	r7, sp, #0
  uwTick += (uint32_t)uwTickFreq;
 80034a0:	4b06      	ldr	r3, [pc, #24]	@ (80034bc <HAL_IncTick+0x20>)
 80034a2:	781b      	ldrb	r3, [r3, #0]
 80034a4:	461a      	mov	r2, r3
 80034a6:	4b06      	ldr	r3, [pc, #24]	@ (80034c0 <HAL_IncTick+0x24>)
 80034a8:	681b      	ldr	r3, [r3, #0]
 80034aa:	4413      	add	r3, r2
 80034ac:	4a04      	ldr	r2, [pc, #16]	@ (80034c0 <HAL_IncTick+0x24>)
 80034ae:	6013      	str	r3, [r2, #0]
}
 80034b0:	bf00      	nop
 80034b2:	46bd      	mov	sp, r7
 80034b4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80034b8:	4770      	bx	lr
 80034ba:	bf00      	nop
 80034bc:	24000040 	.word	0x24000040
 80034c0:	24000a5c 	.word	0x24000a5c

080034c4 <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 80034c4:	b480      	push	{r7}
 80034c6:	af00      	add	r7, sp, #0
  return uwTick;
 80034c8:	4b03      	ldr	r3, [pc, #12]	@ (80034d8 <HAL_GetTick+0x14>)
 80034ca:	681b      	ldr	r3, [r3, #0]
}
 80034cc:	4618      	mov	r0, r3
 80034ce:	46bd      	mov	sp, r7
 80034d0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80034d4:	4770      	bx	lr
 80034d6:	bf00      	nop
 80034d8:	24000a5c 	.word	0x24000a5c

080034dc <HAL_GetREVID>:
/**
  * @brief  Returns the device revision identifier.
  * @retval Device revision identifier
  */
uint32_t HAL_GetREVID(void)
{
 80034dc:	b480      	push	{r7}
 80034de:	af00      	add	r7, sp, #0
   return((DBGMCU->IDCODE) >> 16);
 80034e0:	4b03      	ldr	r3, [pc, #12]	@ (80034f0 <HAL_GetREVID+0x14>)
 80034e2:	681b      	ldr	r3, [r3, #0]
 80034e4:	0c1b      	lsrs	r3, r3, #16
}
 80034e6:	4618      	mov	r0, r3
 80034e8:	46bd      	mov	sp, r7
 80034ea:	f85d 7b04 	ldr.w	r7, [sp], #4
 80034ee:	4770      	bx	lr
 80034f0:	5c001000 	.word	0x5c001000

080034f4 <HAL_SYSCFG_AnalogSwitchConfig>:
  *   @arg SYSCFG_SWITCH_PC3_CLOSE
  * @retval None
  */

void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
{
 80034f4:	b480      	push	{r7}
 80034f6:	b083      	sub	sp, #12
 80034f8:	af00      	add	r7, sp, #0
 80034fa:	6078      	str	r0, [r7, #4]
 80034fc:	6039      	str	r1, [r7, #0]
  /* Check the parameter */
  assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
  assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));

  MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
 80034fe:	4b07      	ldr	r3, [pc, #28]	@ (800351c <HAL_SYSCFG_AnalogSwitchConfig+0x28>)
 8003500:	685a      	ldr	r2, [r3, #4]
 8003502:	687b      	ldr	r3, [r7, #4]
 8003504:	43db      	mvns	r3, r3
 8003506:	401a      	ands	r2, r3
 8003508:	4904      	ldr	r1, [pc, #16]	@ (800351c <HAL_SYSCFG_AnalogSwitchConfig+0x28>)
 800350a:	683b      	ldr	r3, [r7, #0]
 800350c:	4313      	orrs	r3, r2
 800350e:	604b      	str	r3, [r1, #4]
}
 8003510:	bf00      	nop
 8003512:	370c      	adds	r7, #12
 8003514:	46bd      	mov	sp, r7
 8003516:	f85d 7b04 	ldr.w	r7, [sp], #4
 800351a:	4770      	bx	lr
 800351c:	58000400 	.word	0x58000400

08003520 <LL_ADC_SetCommonClock>:
  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
  * @retval None
  */
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
 8003520:	b480      	push	{r7}
 8003522:	b083      	sub	sp, #12
 8003524:	af00      	add	r7, sp, #0
 8003526:	6078      	str	r0, [r7, #4]
 8003528:	6039      	str	r1, [r7, #0]
  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
 800352a:	687b      	ldr	r3, [r7, #4]
 800352c:	689b      	ldr	r3, [r3, #8]
 800352e:	f423 127c 	bic.w	r2, r3, #4128768	@ 0x3f0000
 8003532:	683b      	ldr	r3, [r7, #0]
 8003534:	431a      	orrs	r2, r3
 8003536:	687b      	ldr	r3, [r7, #4]
 8003538:	609a      	str	r2, [r3, #8]
}
 800353a:	bf00      	nop
 800353c:	370c      	adds	r7, #12
 800353e:	46bd      	mov	sp, r7
 8003540:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003544:	4770      	bx	lr

08003546 <LL_ADC_SetCommonPathInternalCh>:
  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
  * @retval None
  */
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
 8003546:	b480      	push	{r7}
 8003548:	b083      	sub	sp, #12
 800354a:	af00      	add	r7, sp, #0
 800354c:	6078      	str	r0, [r7, #4]
 800354e:	6039      	str	r1, [r7, #0]
  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
 8003550:	687b      	ldr	r3, [r7, #4]
 8003552:	689b      	ldr	r3, [r3, #8]
 8003554:	f023 72e0 	bic.w	r2, r3, #29360128	@ 0x1c00000
 8003558:	683b      	ldr	r3, [r7, #0]
 800355a:	431a      	orrs	r2, r3
 800355c:	687b      	ldr	r3, [r7, #4]
 800355e:	609a      	str	r2, [r3, #8]
}
 8003560:	bf00      	nop
 8003562:	370c      	adds	r7, #12
 8003564:	46bd      	mov	sp, r7
 8003566:	f85d 7b04 	ldr.w	r7, [sp], #4
 800356a:	4770      	bx	lr

0800356c <LL_ADC_GetCommonPathInternalCh>:
  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
  */
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
{
 800356c:	b480      	push	{r7}
 800356e:	b083      	sub	sp, #12
 8003570:	af00      	add	r7, sp, #0
 8003572:	6078      	str	r0, [r7, #4]
  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
 8003574:	687b      	ldr	r3, [r7, #4]
 8003576:	689b      	ldr	r3, [r3, #8]
 8003578:	f003 73e0 	and.w	r3, r3, #29360128	@ 0x1c00000
}
 800357c:	4618      	mov	r0, r3
 800357e:	370c      	adds	r7, #12
 8003580:	46bd      	mov	sp, r7
 8003582:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003586:	4770      	bx	lr

08003588 <LL_ADC_SetOffset>:
  *             Other channels are slow channels (conversion rate: refer to reference manual).
  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
  * @retval None
  */
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
 8003588:	b480      	push	{r7}
 800358a:	b087      	sub	sp, #28
 800358c:	af00      	add	r7, sp, #0
 800358e:	60f8      	str	r0, [r7, #12]
 8003590:	60b9      	str	r1, [r7, #8]
 8003592:	607a      	str	r2, [r7, #4]
 8003594:	603b      	str	r3, [r7, #0]
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
 8003596:	68fb      	ldr	r3, [r7, #12]
 8003598:	3360      	adds	r3, #96	@ 0x60
 800359a:	461a      	mov	r2, r3
 800359c:	68bb      	ldr	r3, [r7, #8]
 800359e:	009b      	lsls	r3, r3, #2
 80035a0:	4413      	add	r3, r2
 80035a2:	617b      	str	r3, [r7, #20]
               ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
  }
  else
#endif /* ADC_VER_V5_V90 */
  {
    MODIFY_REG(*preg,
 80035a4:	697b      	ldr	r3, [r7, #20]
 80035a6:	681b      	ldr	r3, [r3, #0]
 80035a8:	f003 4200 	and.w	r2, r3, #2147483648	@ 0x80000000
 80035ac:	687b      	ldr	r3, [r7, #4]
 80035ae:	f003 41f8 	and.w	r1, r3, #2080374784	@ 0x7c000000
 80035b2:	683b      	ldr	r3, [r7, #0]
 80035b4:	430b      	orrs	r3, r1
 80035b6:	431a      	orrs	r2, r3
 80035b8:	697b      	ldr	r3, [r7, #20]
 80035ba:	601a      	str	r2, [r3, #0]
               ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
               (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
  }
}
 80035bc:	bf00      	nop
 80035be:	371c      	adds	r7, #28
 80035c0:	46bd      	mov	sp, r7
 80035c2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80035c6:	4770      	bx	lr

080035c8 <LL_ADC_SetDataRightShift>:
  *         @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
  *         @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
  * @retval Returned None
  */
__STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
{
 80035c8:	b480      	push	{r7}
 80035ca:	b085      	sub	sp, #20
 80035cc:	af00      	add	r7, sp, #0
 80035ce:	60f8      	str	r0, [r7, #12]
 80035d0:	60b9      	str	r1, [r7, #8]
 80035d2:	607a      	str	r2, [r7, #4]
  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
 80035d4:	68fb      	ldr	r3, [r7, #12]
 80035d6:	691b      	ldr	r3, [r3, #16]
 80035d8:	f423 42f0 	bic.w	r2, r3, #30720	@ 0x7800
 80035dc:	68bb      	ldr	r3, [r7, #8]
 80035de:	f003 031f 	and.w	r3, r3, #31
 80035e2:	6879      	ldr	r1, [r7, #4]
 80035e4:	fa01 f303 	lsl.w	r3, r1, r3
 80035e8:	431a      	orrs	r2, r3
 80035ea:	68fb      	ldr	r3, [r7, #12]
 80035ec:	611a      	str	r2, [r3, #16]
}
 80035ee:	bf00      	nop
 80035f0:	3714      	adds	r7, #20
 80035f2:	46bd      	mov	sp, r7
 80035f4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80035f8:	4770      	bx	lr

080035fa <LL_ADC_SetOffsetSignedSaturation>:
  *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
  *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
  * @retval Returned None
  */
__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
{
 80035fa:	b480      	push	{r7}
 80035fc:	b087      	sub	sp, #28
 80035fe:	af00      	add	r7, sp, #0
 8003600:	60f8      	str	r0, [r7, #12]
 8003602:	60b9      	str	r1, [r7, #8]
 8003604:	607a      	str	r2, [r7, #4]
    /* Function not available on this instance */
  }
  else
#endif  /* ADC_VER_V5_V90 */
  {
    __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
 8003606:	68fb      	ldr	r3, [r7, #12]
 8003608:	3360      	adds	r3, #96	@ 0x60
 800360a:	461a      	mov	r2, r3
 800360c:	68bb      	ldr	r3, [r7, #8]
 800360e:	009b      	lsls	r3, r3, #2
 8003610:	4413      	add	r3, r2
 8003612:	617b      	str	r3, [r7, #20]
    MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
 8003614:	697b      	ldr	r3, [r7, #20]
 8003616:	681b      	ldr	r3, [r3, #0]
 8003618:	f023 4200 	bic.w	r2, r3, #2147483648	@ 0x80000000
 800361c:	687b      	ldr	r3, [r7, #4]
 800361e:	431a      	orrs	r2, r3
 8003620:	697b      	ldr	r3, [r7, #20]
 8003622:	601a      	str	r2, [r3, #0]
  }
}
 8003624:	bf00      	nop
 8003626:	371c      	adds	r7, #28
 8003628:	46bd      	mov	sp, r7
 800362a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800362e:	4770      	bx	lr

08003630 <LL_ADC_REG_IsTriggerSourceSWStart>:
  * @param  ADCx ADC instance
  * @retval Value "0" if trigger source external trigger
  *         Value "1" if trigger source SW start.
  */
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
 8003630:	b480      	push	{r7}
 8003632:	b083      	sub	sp, #12
 8003634:	af00      	add	r7, sp, #0
 8003636:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
 8003638:	687b      	ldr	r3, [r7, #4]
 800363a:	68db      	ldr	r3, [r3, #12]
 800363c:	f403 6340 	and.w	r3, r3, #3072	@ 0xc00
 8003640:	2b00      	cmp	r3, #0
 8003642:	d101      	bne.n	8003648 <LL_ADC_REG_IsTriggerSourceSWStart+0x18>
 8003644:	2301      	movs	r3, #1
 8003646:	e000      	b.n	800364a <LL_ADC_REG_IsTriggerSourceSWStart+0x1a>
 8003648:	2300      	movs	r3, #0
}
 800364a:	4618      	mov	r0, r3
 800364c:	370c      	adds	r7, #12
 800364e:	46bd      	mov	sp, r7
 8003650:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003654:	4770      	bx	lr

08003656 <LL_ADC_REG_SetSequencerRanks>:
  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
  *             Other channels are slow channels (conversion rate: refer to reference manual).
  * @retval None
  */
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
 8003656:	b480      	push	{r7}
 8003658:	b087      	sub	sp, #28
 800365a:	af00      	add	r7, sp, #0
 800365c:	60f8      	str	r0, [r7, #12]
 800365e:	60b9      	str	r1, [r7, #8]
 8003660:	607a      	str	r2, [r7, #4]
  /* Set bits with content of parameter "Channel" with bits position          */
  /* in register and register position depending on parameter "Rank".         */
  /* Parameters "Rank" and "Channel" are used with masks because containing   */
  /* other bits reserved for other purpose.                                   */
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
 8003662:	68fb      	ldr	r3, [r7, #12]
 8003664:	3330      	adds	r3, #48	@ 0x30
 8003666:	461a      	mov	r2, r3
 8003668:	68bb      	ldr	r3, [r7, #8]
 800366a:	0a1b      	lsrs	r3, r3, #8
 800366c:	009b      	lsls	r3, r3, #2
 800366e:	f003 030c 	and.w	r3, r3, #12
 8003672:	4413      	add	r3, r2
 8003674:	617b      	str	r3, [r7, #20]

  MODIFY_REG(*preg,
 8003676:	697b      	ldr	r3, [r7, #20]
 8003678:	681a      	ldr	r2, [r3, #0]
 800367a:	68bb      	ldr	r3, [r7, #8]
 800367c:	f003 031f 	and.w	r3, r3, #31
 8003680:	211f      	movs	r1, #31
 8003682:	fa01 f303 	lsl.w	r3, r1, r3
 8003686:	43db      	mvns	r3, r3
 8003688:	401a      	ands	r2, r3
 800368a:	687b      	ldr	r3, [r7, #4]
 800368c:	0e9b      	lsrs	r3, r3, #26
 800368e:	f003 011f 	and.w	r1, r3, #31
 8003692:	68bb      	ldr	r3, [r7, #8]
 8003694:	f003 031f 	and.w	r3, r3, #31
 8003698:	fa01 f303 	lsl.w	r3, r1, r3
 800369c:	431a      	orrs	r2, r3
 800369e:	697b      	ldr	r3, [r7, #20]
 80036a0:	601a      	str	r2, [r3, #0]
             ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
 80036a2:	bf00      	nop
 80036a4:	371c      	adds	r7, #28
 80036a6:	46bd      	mov	sp, r7
 80036a8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80036ac:	4770      	bx	lr

080036ae <LL_ADC_REG_SetDataTransferMode>:
  * @param  ADCx ADC instance
  * @param  DataTransferMode Select Data Management configuration
  * @retval None
  */
__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
{
 80036ae:	b480      	push	{r7}
 80036b0:	b083      	sub	sp, #12
 80036b2:	af00      	add	r7, sp, #0
 80036b4:	6078      	str	r0, [r7, #4]
 80036b6:	6039      	str	r1, [r7, #0]
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);
 80036b8:	687b      	ldr	r3, [r7, #4]
 80036ba:	68db      	ldr	r3, [r3, #12]
 80036bc:	f023 0203 	bic.w	r2, r3, #3
 80036c0:	683b      	ldr	r3, [r7, #0]
 80036c2:	431a      	orrs	r2, r3
 80036c4:	687b      	ldr	r3, [r7, #4]
 80036c6:	60da      	str	r2, [r3, #12]
}
 80036c8:	bf00      	nop
 80036ca:	370c      	adds	r7, #12
 80036cc:	46bd      	mov	sp, r7
 80036ce:	f85d 7b04 	ldr.w	r7, [sp], #4
 80036d2:	4770      	bx	lr

080036d4 <LL_ADC_SetChannelSamplingTime>:
  *         @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
  *         @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
  * @retval None
  */
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
 80036d4:	b480      	push	{r7}
 80036d6:	b087      	sub	sp, #28
 80036d8:	af00      	add	r7, sp, #0
 80036da:	60f8      	str	r0, [r7, #12]
 80036dc:	60b9      	str	r1, [r7, #8]
 80036de:	607a      	str	r2, [r7, #4]
  /* Set bits with content of parameter "SamplingTime" with bits position     */
  /* in register and register position depending on parameter "Channel".      */
  /* Parameter "Channel" is used with masks because containing                */
  /* other bits reserved for other purpose.                                   */
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
 80036e0:	68fb      	ldr	r3, [r7, #12]
 80036e2:	3314      	adds	r3, #20
 80036e4:	461a      	mov	r2, r3
 80036e6:	68bb      	ldr	r3, [r7, #8]
 80036e8:	0e5b      	lsrs	r3, r3, #25
 80036ea:	009b      	lsls	r3, r3, #2
 80036ec:	f003 0304 	and.w	r3, r3, #4
 80036f0:	4413      	add	r3, r2
 80036f2:	617b      	str	r3, [r7, #20]

  MODIFY_REG(*preg,
 80036f4:	697b      	ldr	r3, [r7, #20]
 80036f6:	681a      	ldr	r2, [r3, #0]
 80036f8:	68bb      	ldr	r3, [r7, #8]
 80036fa:	0d1b      	lsrs	r3, r3, #20
 80036fc:	f003 031f 	and.w	r3, r3, #31
 8003700:	2107      	movs	r1, #7
 8003702:	fa01 f303 	lsl.w	r3, r1, r3
 8003706:	43db      	mvns	r3, r3
 8003708:	401a      	ands	r2, r3
 800370a:	68bb      	ldr	r3, [r7, #8]
 800370c:	0d1b      	lsrs	r3, r3, #20
 800370e:	f003 031f 	and.w	r3, r3, #31
 8003712:	6879      	ldr	r1, [r7, #4]
 8003714:	fa01 f303 	lsl.w	r3, r1, r3
 8003718:	431a      	orrs	r2, r3
 800371a:	697b      	ldr	r3, [r7, #20]
 800371c:	601a      	str	r2, [r3, #0]
             ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
             SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
}
 800371e:	bf00      	nop
 8003720:	371c      	adds	r7, #28
 8003722:	46bd      	mov	sp, r7
 8003724:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003728:	4770      	bx	lr
	...

0800372c <LL_ADC_SetChannelSingleDiff>:
  *         @arg @ref LL_ADC_SINGLE_ENDED
  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
  * @retval None
  */
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
 800372c:	b480      	push	{r7}
 800372e:	b085      	sub	sp, #20
 8003730:	af00      	add	r7, sp, #0
 8003732:	60f8      	str	r0, [r7, #12]
 8003734:	60b9      	str	r1, [r7, #8]
 8003736:	607a      	str	r2, [r7, #4]
  }
#else  /* ADC_VER_V5_V90 */
  /* Bits of channels in single or differential mode are set only for         */
  /* differential mode (for single mode, mask of bits allowed to be set is    */
  /* shifted out of range of bits of channels in single or differential mode. */
  MODIFY_REG(ADCx->DIFSEL,
 8003738:	68fb      	ldr	r3, [r7, #12]
 800373a:	f8d3 20c0 	ldr.w	r2, [r3, #192]	@ 0xc0
 800373e:	68bb      	ldr	r3, [r7, #8]
 8003740:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8003744:	43db      	mvns	r3, r3
 8003746:	401a      	ands	r2, r3
 8003748:	687b      	ldr	r3, [r7, #4]
 800374a:	f003 0318 	and.w	r3, r3, #24
 800374e:	4908      	ldr	r1, [pc, #32]	@ (8003770 <LL_ADC_SetChannelSingleDiff+0x44>)
 8003750:	40d9      	lsrs	r1, r3
 8003752:	68bb      	ldr	r3, [r7, #8]
 8003754:	400b      	ands	r3, r1
 8003756:	f3c3 0313 	ubfx	r3, r3, #0, #20
 800375a:	431a      	orrs	r2, r3
 800375c:	68fb      	ldr	r3, [r7, #12]
 800375e:	f8c3 20c0 	str.w	r2, [r3, #192]	@ 0xc0
             Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
             (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
#endif /* ADC_VER_V5_V90 */
}
 8003762:	bf00      	nop
 8003764:	3714      	adds	r7, #20
 8003766:	46bd      	mov	sp, r7
 8003768:	f85d 7b04 	ldr.w	r7, [sp], #4
 800376c:	4770      	bx	lr
 800376e:	bf00      	nop
 8003770:	000fffff 	.word	0x000fffff

08003774 <LL_ADC_GetMultimode>:
  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
  */
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
{
 8003774:	b480      	push	{r7}
 8003776:	b083      	sub	sp, #12
 8003778:	af00      	add	r7, sp, #0
 800377a:	6078      	str	r0, [r7, #4]
  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
 800377c:	687b      	ldr	r3, [r7, #4]
 800377e:	689b      	ldr	r3, [r3, #8]
 8003780:	f003 031f 	and.w	r3, r3, #31
}
 8003784:	4618      	mov	r0, r3
 8003786:	370c      	adds	r7, #12
 8003788:	46bd      	mov	sp, r7
 800378a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800378e:	4770      	bx	lr

08003790 <LL_ADC_DisableDeepPowerDown>:
  * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
  * @param  ADCx ADC instance
  * @retval None
  */
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
{
 8003790:	b480      	push	{r7}
 8003792:	b083      	sub	sp, #12
 8003794:	af00      	add	r7, sp, #0
 8003796:	6078      	str	r0, [r7, #4]
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
 8003798:	687b      	ldr	r3, [r7, #4]
 800379a:	689a      	ldr	r2, [r3, #8]
 800379c:	4b04      	ldr	r3, [pc, #16]	@ (80037b0 <LL_ADC_DisableDeepPowerDown+0x20>)
 800379e:	4013      	ands	r3, r2
 80037a0:	687a      	ldr	r2, [r7, #4]
 80037a2:	6093      	str	r3, [r2, #8]
}
 80037a4:	bf00      	nop
 80037a6:	370c      	adds	r7, #12
 80037a8:	46bd      	mov	sp, r7
 80037aa:	f85d 7b04 	ldr.w	r7, [sp], #4
 80037ae:	4770      	bx	lr
 80037b0:	5fffffc0 	.word	0x5fffffc0

080037b4 <LL_ADC_IsDeepPowerDownEnabled>:
  * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
  * @param  ADCx ADC instance
  * @retval 0: deep power down is disabled, 1: deep power down is enabled.
  */
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
{
 80037b4:	b480      	push	{r7}
 80037b6:	b083      	sub	sp, #12
 80037b8:	af00      	add	r7, sp, #0
 80037ba:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
 80037bc:	687b      	ldr	r3, [r7, #4]
 80037be:	689b      	ldr	r3, [r3, #8]
 80037c0:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 80037c4:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 80037c8:	d101      	bne.n	80037ce <LL_ADC_IsDeepPowerDownEnabled+0x1a>
 80037ca:	2301      	movs	r3, #1
 80037cc:	e000      	b.n	80037d0 <LL_ADC_IsDeepPowerDownEnabled+0x1c>
 80037ce:	2300      	movs	r3, #0
}
 80037d0:	4618      	mov	r0, r3
 80037d2:	370c      	adds	r7, #12
 80037d4:	46bd      	mov	sp, r7
 80037d6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80037da:	4770      	bx	lr

080037dc <LL_ADC_EnableInternalRegulator>:
  * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
  * @param  ADCx ADC instance
  * @retval None
  */
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
 80037dc:	b480      	push	{r7}
 80037de:	b083      	sub	sp, #12
 80037e0:	af00      	add	r7, sp, #0
 80037e2:	6078      	str	r0, [r7, #4]
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
 80037e4:	687b      	ldr	r3, [r7, #4]
 80037e6:	689a      	ldr	r2, [r3, #8]
 80037e8:	4b05      	ldr	r3, [pc, #20]	@ (8003800 <LL_ADC_EnableInternalRegulator+0x24>)
 80037ea:	4013      	ands	r3, r2
 80037ec:	f043 5280 	orr.w	r2, r3, #268435456	@ 0x10000000
 80037f0:	687b      	ldr	r3, [r7, #4]
 80037f2:	609a      	str	r2, [r3, #8]
             ADC_CR_BITS_PROPERTY_RS,
             ADC_CR_ADVREGEN);
}
 80037f4:	bf00      	nop
 80037f6:	370c      	adds	r7, #12
 80037f8:	46bd      	mov	sp, r7
 80037fa:	f85d 7b04 	ldr.w	r7, [sp], #4
 80037fe:	4770      	bx	lr
 8003800:	6fffffc0 	.word	0x6fffffc0

08003804 <LL_ADC_IsInternalRegulatorEnabled>:
  * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
  * @param  ADCx ADC instance
  * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
  */
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
{
 8003804:	b480      	push	{r7}
 8003806:	b083      	sub	sp, #12
 8003808:	af00      	add	r7, sp, #0
 800380a:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
 800380c:	687b      	ldr	r3, [r7, #4]
 800380e:	689b      	ldr	r3, [r3, #8]
 8003810:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8003814:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 8003818:	d101      	bne.n	800381e <LL_ADC_IsInternalRegulatorEnabled+0x1a>
 800381a:	2301      	movs	r3, #1
 800381c:	e000      	b.n	8003820 <LL_ADC_IsInternalRegulatorEnabled+0x1c>
 800381e:	2300      	movs	r3, #0
}
 8003820:	4618      	mov	r0, r3
 8003822:	370c      	adds	r7, #12
 8003824:	46bd      	mov	sp, r7
 8003826:	f85d 7b04 	ldr.w	r7, [sp], #4
 800382a:	4770      	bx	lr

0800382c <LL_ADC_Enable>:
  * @rmtoll CR       ADEN           LL_ADC_Enable
  * @param  ADCx ADC instance
  * @retval None
  */
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
{
 800382c:	b480      	push	{r7}
 800382e:	b083      	sub	sp, #12
 8003830:	af00      	add	r7, sp, #0
 8003832:	6078      	str	r0, [r7, #4]
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
 8003834:	687b      	ldr	r3, [r7, #4]
 8003836:	689a      	ldr	r2, [r3, #8]
 8003838:	4b05      	ldr	r3, [pc, #20]	@ (8003850 <LL_ADC_Enable+0x24>)
 800383a:	4013      	ands	r3, r2
 800383c:	f043 0201 	orr.w	r2, r3, #1
 8003840:	687b      	ldr	r3, [r7, #4]
 8003842:	609a      	str	r2, [r3, #8]
             ADC_CR_BITS_PROPERTY_RS,
             ADC_CR_ADEN);
}
 8003844:	bf00      	nop
 8003846:	370c      	adds	r7, #12
 8003848:	46bd      	mov	sp, r7
 800384a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800384e:	4770      	bx	lr
 8003850:	7fffffc0 	.word	0x7fffffc0

08003854 <LL_ADC_Disable>:
  * @rmtoll CR       ADDIS          LL_ADC_Disable
  * @param  ADCx ADC instance
  * @retval None
  */
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
{
 8003854:	b480      	push	{r7}
 8003856:	b083      	sub	sp, #12
 8003858:	af00      	add	r7, sp, #0
 800385a:	6078      	str	r0, [r7, #4]
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
 800385c:	687b      	ldr	r3, [r7, #4]
 800385e:	689a      	ldr	r2, [r3, #8]
 8003860:	4b05      	ldr	r3, [pc, #20]	@ (8003878 <LL_ADC_Disable+0x24>)
 8003862:	4013      	ands	r3, r2
 8003864:	f043 0202 	orr.w	r2, r3, #2
 8003868:	687b      	ldr	r3, [r7, #4]
 800386a:	609a      	str	r2, [r3, #8]
             ADC_CR_BITS_PROPERTY_RS,
             ADC_CR_ADDIS);
}
 800386c:	bf00      	nop
 800386e:	370c      	adds	r7, #12
 8003870:	46bd      	mov	sp, r7
 8003872:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003876:	4770      	bx	lr
 8003878:	7fffffc0 	.word	0x7fffffc0

0800387c <LL_ADC_IsEnabled>:
  * @rmtoll CR       ADEN           LL_ADC_IsEnabled
  * @param  ADCx ADC instance
  * @retval 0: ADC is disabled, 1: ADC is enabled.
  */
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
{
 800387c:	b480      	push	{r7}
 800387e:	b083      	sub	sp, #12
 8003880:	af00      	add	r7, sp, #0
 8003882:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
 8003884:	687b      	ldr	r3, [r7, #4]
 8003886:	689b      	ldr	r3, [r3, #8]
 8003888:	f003 0301 	and.w	r3, r3, #1
 800388c:	2b01      	cmp	r3, #1
 800388e:	d101      	bne.n	8003894 <LL_ADC_IsEnabled+0x18>
 8003890:	2301      	movs	r3, #1
 8003892:	e000      	b.n	8003896 <LL_ADC_IsEnabled+0x1a>
 8003894:	2300      	movs	r3, #0
}
 8003896:	4618      	mov	r0, r3
 8003898:	370c      	adds	r7, #12
 800389a:	46bd      	mov	sp, r7
 800389c:	f85d 7b04 	ldr.w	r7, [sp], #4
 80038a0:	4770      	bx	lr

080038a2 <LL_ADC_IsDisableOngoing>:
  * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
  * @param  ADCx ADC instance
  * @retval 0: no ADC disable command on going.
  */
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
{
 80038a2:	b480      	push	{r7}
 80038a4:	b083      	sub	sp, #12
 80038a6:	af00      	add	r7, sp, #0
 80038a8:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
 80038aa:	687b      	ldr	r3, [r7, #4]
 80038ac:	689b      	ldr	r3, [r3, #8]
 80038ae:	f003 0302 	and.w	r3, r3, #2
 80038b2:	2b02      	cmp	r3, #2
 80038b4:	d101      	bne.n	80038ba <LL_ADC_IsDisableOngoing+0x18>
 80038b6:	2301      	movs	r3, #1
 80038b8:	e000      	b.n	80038bc <LL_ADC_IsDisableOngoing+0x1a>
 80038ba:	2300      	movs	r3, #0
}
 80038bc:	4618      	mov	r0, r3
 80038be:	370c      	adds	r7, #12
 80038c0:	46bd      	mov	sp, r7
 80038c2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80038c6:	4770      	bx	lr

080038c8 <LL_ADC_REG_StartConversion>:
  * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
  * @param  ADCx ADC instance
  * @retval None
  */
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
{
 80038c8:	b480      	push	{r7}
 80038ca:	b083      	sub	sp, #12
 80038cc:	af00      	add	r7, sp, #0
 80038ce:	6078      	str	r0, [r7, #4]
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
 80038d0:	687b      	ldr	r3, [r7, #4]
 80038d2:	689a      	ldr	r2, [r3, #8]
 80038d4:	4b05      	ldr	r3, [pc, #20]	@ (80038ec <LL_ADC_REG_StartConversion+0x24>)
 80038d6:	4013      	ands	r3, r2
 80038d8:	f043 0204 	orr.w	r2, r3, #4
 80038dc:	687b      	ldr	r3, [r7, #4]
 80038de:	609a      	str	r2, [r3, #8]
             ADC_CR_BITS_PROPERTY_RS,
             ADC_CR_ADSTART);
}
 80038e0:	bf00      	nop
 80038e2:	370c      	adds	r7, #12
 80038e4:	46bd      	mov	sp, r7
 80038e6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80038ea:	4770      	bx	lr
 80038ec:	7fffffc0 	.word	0x7fffffc0

080038f0 <LL_ADC_REG_IsConversionOngoing>:
  * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
  * @param  ADCx ADC instance
  * @retval 0: no conversion is on going on ADC group regular.
  */
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
{
 80038f0:	b480      	push	{r7}
 80038f2:	b083      	sub	sp, #12
 80038f4:	af00      	add	r7, sp, #0
 80038f6:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
 80038f8:	687b      	ldr	r3, [r7, #4]
 80038fa:	689b      	ldr	r3, [r3, #8]
 80038fc:	f003 0304 	and.w	r3, r3, #4
 8003900:	2b04      	cmp	r3, #4
 8003902:	d101      	bne.n	8003908 <LL_ADC_REG_IsConversionOngoing+0x18>
 8003904:	2301      	movs	r3, #1
 8003906:	e000      	b.n	800390a <LL_ADC_REG_IsConversionOngoing+0x1a>
 8003908:	2300      	movs	r3, #0
}
 800390a:	4618      	mov	r0, r3
 800390c:	370c      	adds	r7, #12
 800390e:	46bd      	mov	sp, r7
 8003910:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003914:	4770      	bx	lr

08003916 <LL_ADC_INJ_IsConversionOngoing>:
  * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
  * @param  ADCx ADC instance
  * @retval 0: no conversion is on going on ADC group injected.
  */
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
{
 8003916:	b480      	push	{r7}
 8003918:	b083      	sub	sp, #12
 800391a:	af00      	add	r7, sp, #0
 800391c:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
 800391e:	687b      	ldr	r3, [r7, #4]
 8003920:	689b      	ldr	r3, [r3, #8]
 8003922:	f003 0308 	and.w	r3, r3, #8
 8003926:	2b08      	cmp	r3, #8
 8003928:	d101      	bne.n	800392e <LL_ADC_INJ_IsConversionOngoing+0x18>
 800392a:	2301      	movs	r3, #1
 800392c:	e000      	b.n	8003930 <LL_ADC_INJ_IsConversionOngoing+0x1a>
 800392e:	2300      	movs	r3, #0
}
 8003930:	4618      	mov	r0, r3
 8003932:	370c      	adds	r7, #12
 8003934:	46bd      	mov	sp, r7
 8003936:	f85d 7b04 	ldr.w	r7, [sp], #4
 800393a:	4770      	bx	lr

0800393c <HAL_ADC_Init>:
  *         without  disabling the other ADCs.
  * @param hadc ADC handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
 800393c:	b590      	push	{r4, r7, lr}
 800393e:	b089      	sub	sp, #36	@ 0x24
 8003940:	af00      	add	r7, sp, #0
 8003942:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8003944:	2300      	movs	r3, #0
 8003946:	77fb      	strb	r3, [r7, #31]
  uint32_t tmpCFGR;
  uint32_t tmp_adc_reg_is_conversion_on_going;
  __IO uint32_t wait_loop_index = 0UL;
 8003948:	2300      	movs	r3, #0
 800394a:	60bb      	str	r3, [r7, #8]
  uint32_t tmp_adc_is_conversion_on_going_regular;
  uint32_t tmp_adc_is_conversion_on_going_injected;

  /* Check ADC handle */
  if (hadc == NULL)
 800394c:	687b      	ldr	r3, [r7, #4]
 800394e:	2b00      	cmp	r3, #0
 8003950:	d101      	bne.n	8003956 <HAL_ADC_Init+0x1a>
  {
    return HAL_ERROR;
 8003952:	2301      	movs	r3, #1
 8003954:	e18f      	b.n	8003c76 <HAL_ADC_Init+0x33a>
  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
  assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));

  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
 8003956:	687b      	ldr	r3, [r7, #4]
 8003958:	68db      	ldr	r3, [r3, #12]
 800395a:	2b00      	cmp	r3, #0
  /* DISCEN and CONT bits cannot be set at the same time */
  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));

  /* Actions performed only if ADC is coming from state reset:                */
  /* - Initialization of ADC MSP                                              */
  if (hadc->State == HAL_ADC_STATE_RESET)
 800395c:	687b      	ldr	r3, [r7, #4]
 800395e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8003960:	2b00      	cmp	r3, #0
 8003962:	d109      	bne.n	8003978 <HAL_ADC_Init+0x3c>

    /* Init the low level hardware */
    hadc->MspInitCallback(hadc);
#else
    /* Init the low level hardware */
    HAL_ADC_MspInit(hadc);
 8003964:	6878      	ldr	r0, [r7, #4]
 8003966:	f7fe fac1 	bl	8001eec <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */

    /* Set ADC error code to none */
    ADC_CLEAR_ERRORCODE(hadc);
 800396a:	687b      	ldr	r3, [r7, #4]
 800396c:	2200      	movs	r2, #0
 800396e:	659a      	str	r2, [r3, #88]	@ 0x58

    /* Initialize Lock */
    hadc->Lock = HAL_UNLOCKED;
 8003970:	687b      	ldr	r3, [r7, #4]
 8003972:	2200      	movs	r2, #0
 8003974:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50
  }

  /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
  if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
 8003978:	687b      	ldr	r3, [r7, #4]
 800397a:	681b      	ldr	r3, [r3, #0]
 800397c:	4618      	mov	r0, r3
 800397e:	f7ff ff19 	bl	80037b4 <LL_ADC_IsDeepPowerDownEnabled>
 8003982:	4603      	mov	r3, r0
 8003984:	2b00      	cmp	r3, #0
 8003986:	d004      	beq.n	8003992 <HAL_ADC_Init+0x56>
  {
    /* Disable ADC deep power down mode */
    LL_ADC_DisableDeepPowerDown(hadc->Instance);
 8003988:	687b      	ldr	r3, [r7, #4]
 800398a:	681b      	ldr	r3, [r3, #0]
 800398c:	4618      	mov	r0, r3
 800398e:	f7ff feff 	bl	8003790 <LL_ADC_DisableDeepPowerDown>
    /* System was in deep power down mode, calibration must
     be relaunched or a previously saved calibration factor
     re-applied once the ADC voltage regulator is enabled */
  }

  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
 8003992:	687b      	ldr	r3, [r7, #4]
 8003994:	681b      	ldr	r3, [r3, #0]
 8003996:	4618      	mov	r0, r3
 8003998:	f7ff ff34 	bl	8003804 <LL_ADC_IsInternalRegulatorEnabled>
 800399c:	4603      	mov	r3, r0
 800399e:	2b00      	cmp	r3, #0
 80039a0:	d114      	bne.n	80039cc <HAL_ADC_Init+0x90>
  {
    /* Enable ADC internal voltage regulator */
    LL_ADC_EnableInternalRegulator(hadc->Instance);
 80039a2:	687b      	ldr	r3, [r7, #4]
 80039a4:	681b      	ldr	r3, [r3, #0]
 80039a6:	4618      	mov	r0, r3
 80039a8:	f7ff ff18 	bl	80037dc <LL_ADC_EnableInternalRegulator>

    /* Note: Variable divided by 2 to compensate partially              */
    /*       CPU processing cycles, scaling in us split to not          */
    /*       exceed 32 bits register capacity and handle low frequency. */
    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
 80039ac:	4b87      	ldr	r3, [pc, #540]	@ (8003bcc <HAL_ADC_Init+0x290>)
 80039ae:	681b      	ldr	r3, [r3, #0]
 80039b0:	099b      	lsrs	r3, r3, #6
 80039b2:	4a87      	ldr	r2, [pc, #540]	@ (8003bd0 <HAL_ADC_Init+0x294>)
 80039b4:	fba2 2303 	umull	r2, r3, r2, r3
 80039b8:	099b      	lsrs	r3, r3, #6
 80039ba:	3301      	adds	r3, #1
 80039bc:	60bb      	str	r3, [r7, #8]
    while (wait_loop_index != 0UL)
 80039be:	e002      	b.n	80039c6 <HAL_ADC_Init+0x8a>
    {
      wait_loop_index--;
 80039c0:	68bb      	ldr	r3, [r7, #8]
 80039c2:	3b01      	subs	r3, #1
 80039c4:	60bb      	str	r3, [r7, #8]
    while (wait_loop_index != 0UL)
 80039c6:	68bb      	ldr	r3, [r7, #8]
 80039c8:	2b00      	cmp	r3, #0
 80039ca:	d1f9      	bne.n	80039c0 <HAL_ADC_Init+0x84>
  }

  /* Verification that ADC voltage regulator is correctly enabled, whether    */
  /* or not ADC is coming from state reset (if any potential problem of       */
  /* clocking, voltage regulator would not be enabled).                       */
  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
 80039cc:	687b      	ldr	r3, [r7, #4]
 80039ce:	681b      	ldr	r3, [r3, #0]
 80039d0:	4618      	mov	r0, r3
 80039d2:	f7ff ff17 	bl	8003804 <LL_ADC_IsInternalRegulatorEnabled>
 80039d6:	4603      	mov	r3, r0
 80039d8:	2b00      	cmp	r3, #0
 80039da:	d10d      	bne.n	80039f8 <HAL_ADC_Init+0xbc>
  {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 80039dc:	687b      	ldr	r3, [r7, #4]
 80039de:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80039e0:	f043 0210 	orr.w	r2, r3, #16
 80039e4:	687b      	ldr	r3, [r7, #4]
 80039e6:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Set ADC error code to ADC peripheral internal error */
    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80039e8:	687b      	ldr	r3, [r7, #4]
 80039ea:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80039ec:	f043 0201 	orr.w	r2, r3, #1
 80039f0:	687b      	ldr	r3, [r7, #4]
 80039f2:	659a      	str	r2, [r3, #88]	@ 0x58

    tmp_hal_status = HAL_ERROR;
 80039f4:	2301      	movs	r3, #1
 80039f6:	77fb      	strb	r3, [r7, #31]

  /* Configuration of ADC parameters if previous preliminary actions are      */
  /* correctly completed and if there is no conversion on going on regular    */
  /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
  /* called to update a parameter on the fly).                                */
  tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
 80039f8:	687b      	ldr	r3, [r7, #4]
 80039fa:	681b      	ldr	r3, [r3, #0]
 80039fc:	4618      	mov	r0, r3
 80039fe:	f7ff ff77 	bl	80038f0 <LL_ADC_REG_IsConversionOngoing>
 8003a02:	6178      	str	r0, [r7, #20]

  if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
 8003a04:	687b      	ldr	r3, [r7, #4]
 8003a06:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8003a08:	f003 0310 	and.w	r3, r3, #16
 8003a0c:	2b00      	cmp	r3, #0
 8003a0e:	f040 8129 	bne.w	8003c64 <HAL_ADC_Init+0x328>
      && (tmp_adc_reg_is_conversion_on_going == 0UL)
 8003a12:	697b      	ldr	r3, [r7, #20]
 8003a14:	2b00      	cmp	r3, #0
 8003a16:	f040 8125 	bne.w	8003c64 <HAL_ADC_Init+0x328>
     )
  {
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 8003a1a:	687b      	ldr	r3, [r7, #4]
 8003a1c:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8003a1e:	f423 7381 	bic.w	r3, r3, #258	@ 0x102
 8003a22:	f043 0202 	orr.w	r2, r3, #2
 8003a26:	687b      	ldr	r3, [r7, #4]
 8003a28:	655a      	str	r2, [r3, #84]	@ 0x54
    /* Configuration of common ADC parameters                                 */

    /* Parameters update conditioned to ADC state:                            */
    /* Parameters that can be updated only when ADC is disabled:              */
    /*  - clock configuration                                                 */
    if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
 8003a2a:	687b      	ldr	r3, [r7, #4]
 8003a2c:	681b      	ldr	r3, [r3, #0]
 8003a2e:	4618      	mov	r0, r3
 8003a30:	f7ff ff24 	bl	800387c <LL_ADC_IsEnabled>
 8003a34:	4603      	mov	r3, r0
 8003a36:	2b00      	cmp	r3, #0
 8003a38:	d136      	bne.n	8003aa8 <HAL_ADC_Init+0x16c>
    {
      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
 8003a3a:	687b      	ldr	r3, [r7, #4]
 8003a3c:	681b      	ldr	r3, [r3, #0]
 8003a3e:	4a65      	ldr	r2, [pc, #404]	@ (8003bd4 <HAL_ADC_Init+0x298>)
 8003a40:	4293      	cmp	r3, r2
 8003a42:	d004      	beq.n	8003a4e <HAL_ADC_Init+0x112>
 8003a44:	687b      	ldr	r3, [r7, #4]
 8003a46:	681b      	ldr	r3, [r3, #0]
 8003a48:	4a63      	ldr	r2, [pc, #396]	@ (8003bd8 <HAL_ADC_Init+0x29c>)
 8003a4a:	4293      	cmp	r3, r2
 8003a4c:	d10e      	bne.n	8003a6c <HAL_ADC_Init+0x130>
 8003a4e:	4861      	ldr	r0, [pc, #388]	@ (8003bd4 <HAL_ADC_Init+0x298>)
 8003a50:	f7ff ff14 	bl	800387c <LL_ADC_IsEnabled>
 8003a54:	4604      	mov	r4, r0
 8003a56:	4860      	ldr	r0, [pc, #384]	@ (8003bd8 <HAL_ADC_Init+0x29c>)
 8003a58:	f7ff ff10 	bl	800387c <LL_ADC_IsEnabled>
 8003a5c:	4603      	mov	r3, r0
 8003a5e:	4323      	orrs	r3, r4
 8003a60:	2b00      	cmp	r3, #0
 8003a62:	bf0c      	ite	eq
 8003a64:	2301      	moveq	r3, #1
 8003a66:	2300      	movne	r3, #0
 8003a68:	b2db      	uxtb	r3, r3
 8003a6a:	e008      	b.n	8003a7e <HAL_ADC_Init+0x142>
 8003a6c:	485b      	ldr	r0, [pc, #364]	@ (8003bdc <HAL_ADC_Init+0x2a0>)
 8003a6e:	f7ff ff05 	bl	800387c <LL_ADC_IsEnabled>
 8003a72:	4603      	mov	r3, r0
 8003a74:	2b00      	cmp	r3, #0
 8003a76:	bf0c      	ite	eq
 8003a78:	2301      	moveq	r3, #1
 8003a7a:	2300      	movne	r3, #0
 8003a7c:	b2db      	uxtb	r3, r3
 8003a7e:	2b00      	cmp	r3, #0
 8003a80:	d012      	beq.n	8003aa8 <HAL_ADC_Init+0x16c>
        /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
        /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
        /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
        /*     (set into HAL_ADC_ConfigChannel() or                             */
        /*     HAL_ADCEx_InjectedConfigChannel() )                              */
        LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
 8003a82:	687b      	ldr	r3, [r7, #4]
 8003a84:	681b      	ldr	r3, [r3, #0]
 8003a86:	4a53      	ldr	r2, [pc, #332]	@ (8003bd4 <HAL_ADC_Init+0x298>)
 8003a88:	4293      	cmp	r3, r2
 8003a8a:	d004      	beq.n	8003a96 <HAL_ADC_Init+0x15a>
 8003a8c:	687b      	ldr	r3, [r7, #4]
 8003a8e:	681b      	ldr	r3, [r3, #0]
 8003a90:	4a51      	ldr	r2, [pc, #324]	@ (8003bd8 <HAL_ADC_Init+0x29c>)
 8003a92:	4293      	cmp	r3, r2
 8003a94:	d101      	bne.n	8003a9a <HAL_ADC_Init+0x15e>
 8003a96:	4a52      	ldr	r2, [pc, #328]	@ (8003be0 <HAL_ADC_Init+0x2a4>)
 8003a98:	e000      	b.n	8003a9c <HAL_ADC_Init+0x160>
 8003a9a:	4a52      	ldr	r2, [pc, #328]	@ (8003be4 <HAL_ADC_Init+0x2a8>)
 8003a9c:	687b      	ldr	r3, [r7, #4]
 8003a9e:	685b      	ldr	r3, [r3, #4]
 8003aa0:	4619      	mov	r1, r3
 8003aa2:	4610      	mov	r0, r2
 8003aa4:	f7ff fd3c 	bl	8003520 <LL_ADC_SetCommonClock>
                  ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
    }

#else

    if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
 8003aa8:	f7ff fd18 	bl	80034dc <HAL_GetREVID>
 8003aac:	4603      	mov	r3, r0
 8003aae:	f241 0203 	movw	r2, #4099	@ 0x1003
 8003ab2:	4293      	cmp	r3, r2
 8003ab4:	d914      	bls.n	8003ae0 <HAL_ADC_Init+0x1a4>
 8003ab6:	687b      	ldr	r3, [r7, #4]
 8003ab8:	689b      	ldr	r3, [r3, #8]
 8003aba:	2b10      	cmp	r3, #16
 8003abc:	d110      	bne.n	8003ae0 <HAL_ADC_Init+0x1a4>
    {
      /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */
      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
 8003abe:	687b      	ldr	r3, [r7, #4]
 8003ac0:	7d5b      	ldrb	r3, [r3, #21]
 8003ac2:	035a      	lsls	r2, r3, #13
                  hadc->Init.Overrun                                                    |
 8003ac4:	687b      	ldr	r3, [r7, #4]
 8003ac6:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
 8003ac8:	431a      	orrs	r2, r3
                  hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)                |
 8003aca:	687b      	ldr	r3, [r7, #4]
 8003acc:	689b      	ldr	r3, [r3, #8]
                  hadc->Init.Overrun                                                    |
 8003ace:	431a      	orrs	r2, r3
                  ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
 8003ad0:	687b      	ldr	r3, [r7, #4]
 8003ad2:	7f1b      	ldrb	r3, [r3, #28]
 8003ad4:	041b      	lsls	r3, r3, #16
                  hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)                |
 8003ad6:	4313      	orrs	r3, r2
      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
 8003ad8:	f043 030c 	orr.w	r3, r3, #12
 8003adc:	61bb      	str	r3, [r7, #24]
 8003ade:	e00d      	b.n	8003afc <HAL_ADC_Init+0x1c0>
    }
    else
    {

      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
 8003ae0:	687b      	ldr	r3, [r7, #4]
 8003ae2:	7d5b      	ldrb	r3, [r3, #21]
 8003ae4:	035a      	lsls	r2, r3, #13
                  hadc->Init.Overrun                                                    |
 8003ae6:	687b      	ldr	r3, [r7, #4]
 8003ae8:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
 8003aea:	431a      	orrs	r2, r3
                  hadc->Init.Resolution                                                 |
 8003aec:	687b      	ldr	r3, [r7, #4]
 8003aee:	689b      	ldr	r3, [r3, #8]
                  hadc->Init.Overrun                                                    |
 8003af0:	431a      	orrs	r2, r3
                  ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
 8003af2:	687b      	ldr	r3, [r7, #4]
 8003af4:	7f1b      	ldrb	r3, [r3, #28]
 8003af6:	041b      	lsls	r3, r3, #16
      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
 8003af8:	4313      	orrs	r3, r2
 8003afa:	61bb      	str	r3, [r7, #24]
    }

#endif /* ADC_VER_V5_3 */

    if (hadc->Init.DiscontinuousConvMode == ENABLE)
 8003afc:	687b      	ldr	r3, [r7, #4]
 8003afe:	7f1b      	ldrb	r3, [r3, #28]
 8003b00:	2b01      	cmp	r3, #1
 8003b02:	d106      	bne.n	8003b12 <HAL_ADC_Init+0x1d6>
    {
      tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
 8003b04:	687b      	ldr	r3, [r7, #4]
 8003b06:	6a1b      	ldr	r3, [r3, #32]
 8003b08:	3b01      	subs	r3, #1
 8003b0a:	045b      	lsls	r3, r3, #17
 8003b0c:	69ba      	ldr	r2, [r7, #24]
 8003b0e:	4313      	orrs	r3, r2
 8003b10:	61bb      	str	r3, [r7, #24]
    /* Enable external trigger if trigger selection is different of software  */
    /* start.                                                                 */
    /* Note: This configuration keeps the hardware feature of parameter       */
    /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
    /*       software start.                                                  */
    if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
 8003b12:	687b      	ldr	r3, [r7, #4]
 8003b14:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8003b16:	2b00      	cmp	r3, #0
 8003b18:	d009      	beq.n	8003b2e <HAL_ADC_Init+0x1f2>
    {
      tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
 8003b1a:	687b      	ldr	r3, [r7, #4]
 8003b1c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8003b1e:	f403 7278 	and.w	r2, r3, #992	@ 0x3e0
                  | hadc->Init.ExternalTrigConvEdge
 8003b22:	687b      	ldr	r3, [r7, #4]
 8003b24:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8003b26:	4313      	orrs	r3, r2
      tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
 8003b28:	69ba      	ldr	r2, [r7, #24]
 8003b2a:	4313      	orrs	r3, r2
 8003b2c:	61bb      	str	r3, [r7, #24]
      /* Update Configuration Register CFGR */
      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
    }
#else
    /* Update Configuration Register CFGR */
    MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
 8003b2e:	687b      	ldr	r3, [r7, #4]
 8003b30:	681b      	ldr	r3, [r3, #0]
 8003b32:	68da      	ldr	r2, [r3, #12]
 8003b34:	4b2c      	ldr	r3, [pc, #176]	@ (8003be8 <HAL_ADC_Init+0x2ac>)
 8003b36:	4013      	ands	r3, r2
 8003b38:	687a      	ldr	r2, [r7, #4]
 8003b3a:	6812      	ldr	r2, [r2, #0]
 8003b3c:	69b9      	ldr	r1, [r7, #24]
 8003b3e:	430b      	orrs	r3, r1
 8003b40:	60d3      	str	r3, [r2, #12]
    /* Parameters that can be updated when ADC is disabled or enabled without */
    /* conversion on going on regular and injected groups:                    */
    /*  - Conversion data management      Init.ConversionDataManagement       */
    /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
    /*  - Oversampling parameters         Init.Oversampling                   */
    tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
 8003b42:	687b      	ldr	r3, [r7, #4]
 8003b44:	681b      	ldr	r3, [r3, #0]
 8003b46:	4618      	mov	r0, r3
 8003b48:	f7ff fed2 	bl	80038f0 <LL_ADC_REG_IsConversionOngoing>
 8003b4c:	6138      	str	r0, [r7, #16]
    tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
 8003b4e:	687b      	ldr	r3, [r7, #4]
 8003b50:	681b      	ldr	r3, [r3, #0]
 8003b52:	4618      	mov	r0, r3
 8003b54:	f7ff fedf 	bl	8003916 <LL_ADC_INJ_IsConversionOngoing>
 8003b58:	60f8      	str	r0, [r7, #12]
    if ((tmp_adc_is_conversion_on_going_regular == 0UL)
 8003b5a:	693b      	ldr	r3, [r7, #16]
 8003b5c:	2b00      	cmp	r3, #0
 8003b5e:	d15f      	bne.n	8003c20 <HAL_ADC_Init+0x2e4>
        && (tmp_adc_is_conversion_on_going_injected == 0UL)
 8003b60:	68fb      	ldr	r3, [r7, #12]
 8003b62:	2b00      	cmp	r3, #0
 8003b64:	d15c      	bne.n	8003c20 <HAL_ADC_Init+0x2e4>
                    ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
                    ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
      }
#else
      tmpCFGR = (
                  ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
 8003b66:	687b      	ldr	r3, [r7, #4]
 8003b68:	7d1b      	ldrb	r3, [r3, #20]
 8003b6a:	039a      	lsls	r2, r3, #14
                  ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
 8003b6c:	687b      	ldr	r3, [r7, #4]
 8003b6e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
      tmpCFGR = (
 8003b70:	4313      	orrs	r3, r2
 8003b72:	61bb      	str	r3, [r7, #24]
#endif

      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
 8003b74:	687b      	ldr	r3, [r7, #4]
 8003b76:	681b      	ldr	r3, [r3, #0]
 8003b78:	68da      	ldr	r2, [r3, #12]
 8003b7a:	4b1c      	ldr	r3, [pc, #112]	@ (8003bec <HAL_ADC_Init+0x2b0>)
 8003b7c:	4013      	ands	r3, r2
 8003b7e:	687a      	ldr	r2, [r7, #4]
 8003b80:	6812      	ldr	r2, [r2, #0]
 8003b82:	69b9      	ldr	r1, [r7, #24]
 8003b84:	430b      	orrs	r3, r1
 8003b86:	60d3      	str	r3, [r2, #12]

      if (hadc->Init.OversamplingMode == ENABLE)
 8003b88:	687b      	ldr	r3, [r7, #4]
 8003b8a:	f893 3038 	ldrb.w	r3, [r3, #56]	@ 0x38
 8003b8e:	2b01      	cmp	r3, #1
 8003b90:	d130      	bne.n	8003bf4 <HAL_ADC_Init+0x2b8>
#endif
        assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
        assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
        assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));

        if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
 8003b92:	687b      	ldr	r3, [r7, #4]
 8003b94:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8003b96:	2b00      	cmp	r3, #0
        /*  - Oversampling Ratio                                               */
        /*  - Right bit shift                                                  */
        /*  - Left bit shift                                                   */
        /*  - Triggered mode                                                   */
        /*  - Oversampling mode (continued/resumed)                            */
        MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
 8003b98:	687b      	ldr	r3, [r7, #4]
 8003b9a:	681b      	ldr	r3, [r3, #0]
 8003b9c:	691a      	ldr	r2, [r3, #16]
 8003b9e:	4b14      	ldr	r3, [pc, #80]	@ (8003bf0 <HAL_ADC_Init+0x2b4>)
 8003ba0:	4013      	ands	r3, r2
 8003ba2:	687a      	ldr	r2, [r7, #4]
 8003ba4:	6bd2      	ldr	r2, [r2, #60]	@ 0x3c
 8003ba6:	3a01      	subs	r2, #1
 8003ba8:	0411      	lsls	r1, r2, #16
 8003baa:	687a      	ldr	r2, [r7, #4]
 8003bac:	6c12      	ldr	r2, [r2, #64]	@ 0x40
 8003bae:	4311      	orrs	r1, r2
 8003bb0:	687a      	ldr	r2, [r7, #4]
 8003bb2:	6c52      	ldr	r2, [r2, #68]	@ 0x44
 8003bb4:	4311      	orrs	r1, r2
 8003bb6:	687a      	ldr	r2, [r7, #4]
 8003bb8:	6c92      	ldr	r2, [r2, #72]	@ 0x48
 8003bba:	430a      	orrs	r2, r1
 8003bbc:	431a      	orrs	r2, r3
 8003bbe:	687b      	ldr	r3, [r7, #4]
 8003bc0:	681b      	ldr	r3, [r3, #0]
 8003bc2:	f042 0201 	orr.w	r2, r2, #1
 8003bc6:	611a      	str	r2, [r3, #16]
 8003bc8:	e01c      	b.n	8003c04 <HAL_ADC_Init+0x2c8>
 8003bca:	bf00      	nop
 8003bcc:	24000034 	.word	0x24000034
 8003bd0:	053e2d63 	.word	0x053e2d63
 8003bd4:	40022000 	.word	0x40022000
 8003bd8:	40022100 	.word	0x40022100
 8003bdc:	58026000 	.word	0x58026000
 8003be0:	40022300 	.word	0x40022300
 8003be4:	58026300 	.word	0x58026300
 8003be8:	fff0c003 	.word	0xfff0c003
 8003bec:	ffffbffc 	.word	0xffffbffc
 8003bf0:	fc00f81e 	.word	0xfc00f81e

      }
      else
      {
        /* Disable ADC oversampling scope on ADC group regular */
        CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
 8003bf4:	687b      	ldr	r3, [r7, #4]
 8003bf6:	681b      	ldr	r3, [r3, #0]
 8003bf8:	691a      	ldr	r2, [r3, #16]
 8003bfa:	687b      	ldr	r3, [r7, #4]
 8003bfc:	681b      	ldr	r3, [r3, #0]
 8003bfe:	f022 0201 	bic.w	r2, r2, #1
 8003c02:	611a      	str	r2, [r3, #16]
      }

      /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
      MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
 8003c04:	687b      	ldr	r3, [r7, #4]
 8003c06:	681b      	ldr	r3, [r3, #0]
 8003c08:	691b      	ldr	r3, [r3, #16]
 8003c0a:	f023 4170 	bic.w	r1, r3, #4026531840	@ 0xf0000000
 8003c0e:	687b      	ldr	r3, [r7, #4]
 8003c10:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 8003c12:	687b      	ldr	r3, [r7, #4]
 8003c14:	681b      	ldr	r3, [r3, #0]
 8003c16:	430a      	orrs	r2, r1
 8003c18:	611a      	str	r2, [r3, #16]
        /* Configure the BOOST Mode */
        ADC_ConfigureBoostMode(hadc);
      }
#else
      /* Configure the BOOST Mode */
      ADC_ConfigureBoostMode(hadc);
 8003c1a:	6878      	ldr	r0, [r7, #4]
 8003c1c:	f000 fde2 	bl	80047e4 <ADC_ConfigureBoostMode>
    /*   Note: Scan mode is not present by hardware on this device, but       */
    /*   emulated by software for alignment over all STM32 devices.           */
    /* - if scan mode is enabled, regular channels sequence length is set to  */
    /*   parameter "NbrOfConversion".                                         */

    if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
 8003c20:	687b      	ldr	r3, [r7, #4]
 8003c22:	68db      	ldr	r3, [r3, #12]
 8003c24:	2b01      	cmp	r3, #1
 8003c26:	d10c      	bne.n	8003c42 <HAL_ADC_Init+0x306>
    {
      /* Set number of ranks in regular group sequencer */
      MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
 8003c28:	687b      	ldr	r3, [r7, #4]
 8003c2a:	681b      	ldr	r3, [r3, #0]
 8003c2c:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8003c2e:	f023 010f 	bic.w	r1, r3, #15
 8003c32:	687b      	ldr	r3, [r7, #4]
 8003c34:	699b      	ldr	r3, [r3, #24]
 8003c36:	1e5a      	subs	r2, r3, #1
 8003c38:	687b      	ldr	r3, [r7, #4]
 8003c3a:	681b      	ldr	r3, [r3, #0]
 8003c3c:	430a      	orrs	r2, r1
 8003c3e:	631a      	str	r2, [r3, #48]	@ 0x30
 8003c40:	e007      	b.n	8003c52 <HAL_ADC_Init+0x316>
    }
    else
    {
      CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
 8003c42:	687b      	ldr	r3, [r7, #4]
 8003c44:	681b      	ldr	r3, [r3, #0]
 8003c46:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
 8003c48:	687b      	ldr	r3, [r7, #4]
 8003c4a:	681b      	ldr	r3, [r3, #0]
 8003c4c:	f022 020f 	bic.w	r2, r2, #15
 8003c50:	631a      	str	r2, [r3, #48]	@ 0x30
    }

    /* Initialize the ADC state */
    /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
 8003c52:	687b      	ldr	r3, [r7, #4]
 8003c54:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8003c56:	f023 0303 	bic.w	r3, r3, #3
 8003c5a:	f043 0201 	orr.w	r2, r3, #1
 8003c5e:	687b      	ldr	r3, [r7, #4]
 8003c60:	655a      	str	r2, [r3, #84]	@ 0x54
 8003c62:	e007      	b.n	8003c74 <HAL_ADC_Init+0x338>
  }
  else
  {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8003c64:	687b      	ldr	r3, [r7, #4]
 8003c66:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8003c68:	f043 0210 	orr.w	r2, r3, #16
 8003c6c:	687b      	ldr	r3, [r7, #4]
 8003c6e:	655a      	str	r2, [r3, #84]	@ 0x54

    tmp_hal_status = HAL_ERROR;
 8003c70:	2301      	movs	r3, #1
 8003c72:	77fb      	strb	r3, [r7, #31]
  }

  /* Return function status */
  return tmp_hal_status;
 8003c74:	7ffb      	ldrb	r3, [r7, #31]
}
 8003c76:	4618      	mov	r0, r3
 8003c78:	3724      	adds	r7, #36	@ 0x24
 8003c7a:	46bd      	mov	sp, r7
 8003c7c:	bd90      	pop	{r4, r7, pc}
 8003c7e:	bf00      	nop

08003c80 <HAL_ADC_Start_DMA>:
  * @param pData Destination Buffer address.
  * @param Length Number of data to be transferred from ADC peripheral to memory
  * @retval HAL status.
  */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
{
 8003c80:	b580      	push	{r7, lr}
 8003c82:	b086      	sub	sp, #24
 8003c84:	af00      	add	r7, sp, #0
 8003c86:	60f8      	str	r0, [r7, #12]
 8003c88:	60b9      	str	r1, [r7, #8]
 8003c8a:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status;
  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
 8003c8c:	68fb      	ldr	r3, [r7, #12]
 8003c8e:	681b      	ldr	r3, [r3, #0]
 8003c90:	4a55      	ldr	r2, [pc, #340]	@ (8003de8 <HAL_ADC_Start_DMA+0x168>)
 8003c92:	4293      	cmp	r3, r2
 8003c94:	d004      	beq.n	8003ca0 <HAL_ADC_Start_DMA+0x20>
 8003c96:	68fb      	ldr	r3, [r7, #12]
 8003c98:	681b      	ldr	r3, [r3, #0]
 8003c9a:	4a54      	ldr	r2, [pc, #336]	@ (8003dec <HAL_ADC_Start_DMA+0x16c>)
 8003c9c:	4293      	cmp	r3, r2
 8003c9e:	d101      	bne.n	8003ca4 <HAL_ADC_Start_DMA+0x24>
 8003ca0:	4b53      	ldr	r3, [pc, #332]	@ (8003df0 <HAL_ADC_Start_DMA+0x170>)
 8003ca2:	e000      	b.n	8003ca6 <HAL_ADC_Start_DMA+0x26>
 8003ca4:	4b53      	ldr	r3, [pc, #332]	@ (8003df4 <HAL_ADC_Start_DMA+0x174>)
 8003ca6:	4618      	mov	r0, r3
 8003ca8:	f7ff fd64 	bl	8003774 <LL_ADC_GetMultimode>
 8003cac:	6138      	str	r0, [r7, #16]

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Perform ADC enable and conversion start if no conversion is on going */
  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
 8003cae:	68fb      	ldr	r3, [r7, #12]
 8003cb0:	681b      	ldr	r3, [r3, #0]
 8003cb2:	4618      	mov	r0, r3
 8003cb4:	f7ff fe1c 	bl	80038f0 <LL_ADC_REG_IsConversionOngoing>
 8003cb8:	4603      	mov	r3, r0
 8003cba:	2b00      	cmp	r3, #0
 8003cbc:	f040 808c 	bne.w	8003dd8 <HAL_ADC_Start_DMA+0x158>
  {
    /* Process locked */
    __HAL_LOCK(hadc);
 8003cc0:	68fb      	ldr	r3, [r7, #12]
 8003cc2:	f893 3050 	ldrb.w	r3, [r3, #80]	@ 0x50
 8003cc6:	2b01      	cmp	r3, #1
 8003cc8:	d101      	bne.n	8003cce <HAL_ADC_Start_DMA+0x4e>
 8003cca:	2302      	movs	r3, #2
 8003ccc:	e087      	b.n	8003dde <HAL_ADC_Start_DMA+0x15e>
 8003cce:	68fb      	ldr	r3, [r7, #12]
 8003cd0:	2201      	movs	r2, #1
 8003cd2:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

    /* Ensure that multimode regular conversions are not enabled.   */
    /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
    if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
 8003cd6:	693b      	ldr	r3, [r7, #16]
 8003cd8:	2b00      	cmp	r3, #0
 8003cda:	d005      	beq.n	8003ce8 <HAL_ADC_Start_DMA+0x68>
        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
 8003cdc:	693b      	ldr	r3, [r7, #16]
 8003cde:	2b05      	cmp	r3, #5
 8003ce0:	d002      	beq.n	8003ce8 <HAL_ADC_Start_DMA+0x68>
        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
 8003ce2:	693b      	ldr	r3, [r7, #16]
 8003ce4:	2b09      	cmp	r3, #9
 8003ce6:	d170      	bne.n	8003dca <HAL_ADC_Start_DMA+0x14a>
       )
    {
      /* Enable the ADC peripheral */
      tmp_hal_status = ADC_Enable(hadc);
 8003ce8:	68f8      	ldr	r0, [r7, #12]
 8003cea:	f000 fbfd 	bl	80044e8 <ADC_Enable>
 8003cee:	4603      	mov	r3, r0
 8003cf0:	75fb      	strb	r3, [r7, #23]

      /* Start conversion if ADC is effectively enabled */
      if (tmp_hal_status == HAL_OK)
 8003cf2:	7dfb      	ldrb	r3, [r7, #23]
 8003cf4:	2b00      	cmp	r3, #0
 8003cf6:	d163      	bne.n	8003dc0 <HAL_ADC_Start_DMA+0x140>
      {
        /* Set ADC state                                                        */
        /* - Clear state bitfield related to regular group conversion results   */
        /* - Set state bitfield related to regular operation                    */
        ADC_STATE_CLR_SET(hadc->State,
 8003cf8:	68fb      	ldr	r3, [r7, #12]
 8003cfa:	6d5a      	ldr	r2, [r3, #84]	@ 0x54
 8003cfc:	4b3e      	ldr	r3, [pc, #248]	@ (8003df8 <HAL_ADC_Start_DMA+0x178>)
 8003cfe:	4013      	ands	r3, r2
 8003d00:	f443 7280 	orr.w	r2, r3, #256	@ 0x100
 8003d04:	68fb      	ldr	r3, [r7, #12]
 8003d06:	655a      	str	r2, [r3, #84]	@ 0x54
                          HAL_ADC_STATE_REG_BUSY);

        /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
          - if ADC instance is master or if multimode feature is not available
          - if multimode setting is disabled (ADC instance slave in independent mode) */
        if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
 8003d08:	68fb      	ldr	r3, [r7, #12]
 8003d0a:	681b      	ldr	r3, [r3, #0]
 8003d0c:	4a37      	ldr	r2, [pc, #220]	@ (8003dec <HAL_ADC_Start_DMA+0x16c>)
 8003d0e:	4293      	cmp	r3, r2
 8003d10:	d002      	beq.n	8003d18 <HAL_ADC_Start_DMA+0x98>
 8003d12:	68fb      	ldr	r3, [r7, #12]
 8003d14:	681b      	ldr	r3, [r3, #0]
 8003d16:	e000      	b.n	8003d1a <HAL_ADC_Start_DMA+0x9a>
 8003d18:	4b33      	ldr	r3, [pc, #204]	@ (8003de8 <HAL_ADC_Start_DMA+0x168>)
 8003d1a:	68fa      	ldr	r2, [r7, #12]
 8003d1c:	6812      	ldr	r2, [r2, #0]
 8003d1e:	4293      	cmp	r3, r2
 8003d20:	d002      	beq.n	8003d28 <HAL_ADC_Start_DMA+0xa8>
            || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
 8003d22:	693b      	ldr	r3, [r7, #16]
 8003d24:	2b00      	cmp	r3, #0
 8003d26:	d105      	bne.n	8003d34 <HAL_ADC_Start_DMA+0xb4>
           )
        {
          CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
 8003d28:	68fb      	ldr	r3, [r7, #12]
 8003d2a:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8003d2c:	f423 1280 	bic.w	r2, r3, #1048576	@ 0x100000
 8003d30:	68fb      	ldr	r3, [r7, #12]
 8003d32:	655a      	str	r2, [r3, #84]	@ 0x54
        }

        /* Check if a conversion is on going on ADC group injected */
        if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
 8003d34:	68fb      	ldr	r3, [r7, #12]
 8003d36:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8003d38:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
 8003d3c:	2b00      	cmp	r3, #0
 8003d3e:	d006      	beq.n	8003d4e <HAL_ADC_Start_DMA+0xce>
        {
          /* Reset ADC error code fields related to regular conversions only */
          CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
 8003d40:	68fb      	ldr	r3, [r7, #12]
 8003d42:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003d44:	f023 0206 	bic.w	r2, r3, #6
 8003d48:	68fb      	ldr	r3, [r7, #12]
 8003d4a:	659a      	str	r2, [r3, #88]	@ 0x58
 8003d4c:	e002      	b.n	8003d54 <HAL_ADC_Start_DMA+0xd4>
        }
        else
        {
          /* Reset all ADC error code fields */
          ADC_CLEAR_ERRORCODE(hadc);
 8003d4e:	68fb      	ldr	r3, [r7, #12]
 8003d50:	2200      	movs	r2, #0
 8003d52:	659a      	str	r2, [r3, #88]	@ 0x58
        }

        /* Set the DMA transfer complete callback */
        hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
 8003d54:	68fb      	ldr	r3, [r7, #12]
 8003d56:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8003d58:	4a28      	ldr	r2, [pc, #160]	@ (8003dfc <HAL_ADC_Start_DMA+0x17c>)
 8003d5a:	63da      	str	r2, [r3, #60]	@ 0x3c

        /* Set the DMA half transfer complete callback */
        hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
 8003d5c:	68fb      	ldr	r3, [r7, #12]
 8003d5e:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8003d60:	4a27      	ldr	r2, [pc, #156]	@ (8003e00 <HAL_ADC_Start_DMA+0x180>)
 8003d62:	641a      	str	r2, [r3, #64]	@ 0x40

        /* Set the DMA error callback */
        hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
 8003d64:	68fb      	ldr	r3, [r7, #12]
 8003d66:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8003d68:	4a26      	ldr	r2, [pc, #152]	@ (8003e04 <HAL_ADC_Start_DMA+0x184>)
 8003d6a:	64da      	str	r2, [r3, #76]	@ 0x4c
        /* ADC start (in case of SW start):                                   */

        /* Clear regular group conversion flag and overrun flag               */
        /* (To ensure of no unknown state from potential previous ADC         */
        /* operations)                                                        */
        __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
 8003d6c:	68fb      	ldr	r3, [r7, #12]
 8003d6e:	681b      	ldr	r3, [r3, #0]
 8003d70:	221c      	movs	r2, #28
 8003d72:	601a      	str	r2, [r3, #0]

        /* Process unlocked */
        /* Unlock before starting ADC conversions: in case of potential         */
        /* interruption, to let the process to ADC IRQ Handler.                 */
        __HAL_UNLOCK(hadc);
 8003d74:	68fb      	ldr	r3, [r7, #12]
 8003d76:	2200      	movs	r2, #0
 8003d78:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

        /* With DMA, overrun event is always considered as an error even if
           hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
           ADC_IT_OVR is enabled. */
        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
 8003d7c:	68fb      	ldr	r3, [r7, #12]
 8003d7e:	681b      	ldr	r3, [r3, #0]
 8003d80:	685a      	ldr	r2, [r3, #4]
 8003d82:	68fb      	ldr	r3, [r7, #12]
 8003d84:	681b      	ldr	r3, [r3, #0]
 8003d86:	f042 0210 	orr.w	r2, r2, #16
 8003d8a:	605a      	str	r2, [r3, #4]
        {
          LL_ADC_REG_SetDataTransferMode(hadc->Instance, ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
        }

#else
        LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement);
 8003d8c:	68fb      	ldr	r3, [r7, #12]
 8003d8e:	681a      	ldr	r2, [r3, #0]
 8003d90:	68fb      	ldr	r3, [r7, #12]
 8003d92:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8003d94:	4619      	mov	r1, r3
 8003d96:	4610      	mov	r0, r2
 8003d98:	f7ff fc89 	bl	80036ae <LL_ADC_REG_SetDataTransferMode>
#endif


        /* Start the DMA channel */
        tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
 8003d9c:	68fb      	ldr	r3, [r7, #12]
 8003d9e:	6cd8      	ldr	r0, [r3, #76]	@ 0x4c
 8003da0:	68fb      	ldr	r3, [r7, #12]
 8003da2:	681b      	ldr	r3, [r3, #0]
 8003da4:	3340      	adds	r3, #64	@ 0x40
 8003da6:	4619      	mov	r1, r3
 8003da8:	68ba      	ldr	r2, [r7, #8]
 8003daa:	687b      	ldr	r3, [r7, #4]
 8003dac:	f001 fe7c 	bl	8005aa8 <HAL_DMA_Start_IT>
 8003db0:	4603      	mov	r3, r0
 8003db2:	75fb      	strb	r3, [r7, #23]
        /* Enable conversion of regular group.                                  */
        /* If software start has been selected, conversion starts immediately.  */
        /* If external trigger has been selected, conversion will start at next */
        /* trigger event.                                                       */
        /* Start ADC group regular conversion */
        LL_ADC_REG_StartConversion(hadc->Instance);
 8003db4:	68fb      	ldr	r3, [r7, #12]
 8003db6:	681b      	ldr	r3, [r3, #0]
 8003db8:	4618      	mov	r0, r3
 8003dba:	f7ff fd85 	bl	80038c8 <LL_ADC_REG_StartConversion>
      if (tmp_hal_status == HAL_OK)
 8003dbe:	e00d      	b.n	8003ddc <HAL_ADC_Start_DMA+0x15c>
      }
      else
      {
        /* Process unlocked */
        __HAL_UNLOCK(hadc);
 8003dc0:	68fb      	ldr	r3, [r7, #12]
 8003dc2:	2200      	movs	r2, #0
 8003dc4:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50
      if (tmp_hal_status == HAL_OK)
 8003dc8:	e008      	b.n	8003ddc <HAL_ADC_Start_DMA+0x15c>
      }

    }
    else
    {
      tmp_hal_status = HAL_ERROR;
 8003dca:	2301      	movs	r3, #1
 8003dcc:	75fb      	strb	r3, [r7, #23]
      /* Process unlocked */
      __HAL_UNLOCK(hadc);
 8003dce:	68fb      	ldr	r3, [r7, #12]
 8003dd0:	2200      	movs	r2, #0
 8003dd2:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50
 8003dd6:	e001      	b.n	8003ddc <HAL_ADC_Start_DMA+0x15c>
    }
  }
  else
  {
    tmp_hal_status = HAL_BUSY;
 8003dd8:	2302      	movs	r3, #2
 8003dda:	75fb      	strb	r3, [r7, #23]
  }

  /* Return function status */
  return tmp_hal_status;
 8003ddc:	7dfb      	ldrb	r3, [r7, #23]
}
 8003dde:	4618      	mov	r0, r3
 8003de0:	3718      	adds	r7, #24
 8003de2:	46bd      	mov	sp, r7
 8003de4:	bd80      	pop	{r7, pc}
 8003de6:	bf00      	nop
 8003de8:	40022000 	.word	0x40022000
 8003dec:	40022100 	.word	0x40022100
 8003df0:	40022300 	.word	0x40022300
 8003df4:	58026300 	.word	0x58026300
 8003df8:	fffff0fe 	.word	0xfffff0fe
 8003dfc:	080046bb 	.word	0x080046bb
 8003e00:	08004793 	.word	0x08004793
 8003e04:	080047af 	.word	0x080047af

08003e08 <HAL_ADC_ConvHalfCpltCallback>:
  * @brief  Conversion DMA half-transfer callback in non-blocking mode.
  * @param hadc ADC handle
  * @retval None
  */
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
{
 8003e08:	b480      	push	{r7}
 8003e0a:	b083      	sub	sp, #12
 8003e0c:	af00      	add	r7, sp, #0
 8003e0e:	6078      	str	r0, [r7, #4]
  UNUSED(hadc);

  /* NOTE : This function should not be modified. When the callback is needed,
            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
  */
}
 8003e10:	bf00      	nop
 8003e12:	370c      	adds	r7, #12
 8003e14:	46bd      	mov	sp, r7
 8003e16:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003e1a:	4770      	bx	lr

08003e1c <HAL_ADC_ErrorCallback>:
  *           (this function is also clearing overrun flag)
  * @param hadc ADC handle
  * @retval None
  */
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
 8003e1c:	b480      	push	{r7}
 8003e1e:	b083      	sub	sp, #12
 8003e20:	af00      	add	r7, sp, #0
 8003e22:	6078      	str	r0, [r7, #4]
  UNUSED(hadc);

  /* NOTE : This function should not be modified. When the callback is needed,
            function HAL_ADC_ErrorCallback must be implemented in the user file.
  */
}
 8003e24:	bf00      	nop
 8003e26:	370c      	adds	r7, #12
 8003e28:	46bd      	mov	sp, r7
 8003e2a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003e2e:	4770      	bx	lr

08003e30 <HAL_ADC_ConfigChannel>:
  * @param hadc ADC handle
  * @param sConfig Structure of ADC channel assigned to ADC group regular.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
{
 8003e30:	b590      	push	{r4, r7, lr}
 8003e32:	b0a1      	sub	sp, #132	@ 0x84
 8003e34:	af00      	add	r7, sp, #0
 8003e36:	6078      	str	r0, [r7, #4]
 8003e38:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8003e3a:	2300      	movs	r3, #0
 8003e3c:	f887 307f 	strb.w	r3, [r7, #127]	@ 0x7f
  uint32_t tmpOffsetShifted;
  uint32_t tmp_config_internal_channel;
  __IO uint32_t wait_loop_index = 0;
 8003e40:	2300      	movs	r3, #0
 8003e42:	60bb      	str	r3, [r7, #8]
  /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
     ignored (considered as reset) */
  assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));

  /* Verification of channel number */
  if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
 8003e44:	683b      	ldr	r3, [r7, #0]
 8003e46:	68db      	ldr	r3, [r3, #12]
 8003e48:	4a65      	ldr	r2, [pc, #404]	@ (8003fe0 <HAL_ADC_ConfigChannel+0x1b0>)
 8003e4a:	4293      	cmp	r3, r2
    }
#endif
  }

  /* Process locked */
  __HAL_LOCK(hadc);
 8003e4c:	687b      	ldr	r3, [r7, #4]
 8003e4e:	f893 3050 	ldrb.w	r3, [r3, #80]	@ 0x50
 8003e52:	2b01      	cmp	r3, #1
 8003e54:	d101      	bne.n	8003e5a <HAL_ADC_ConfigChannel+0x2a>
 8003e56:	2302      	movs	r3, #2
 8003e58:	e32e      	b.n	80044b8 <HAL_ADC_ConfigChannel+0x688>
 8003e5a:	687b      	ldr	r3, [r7, #4]
 8003e5c:	2201      	movs	r2, #1
 8003e5e:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50
  /* Parameters update conditioned to ADC state:                              */
  /* Parameters that can be updated when ADC is disabled or enabled without   */
  /* conversion on going on regular group:                                    */
  /*  - Channel number                                                        */
  /*  - Channel rank                                                          */
  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
 8003e62:	687b      	ldr	r3, [r7, #4]
 8003e64:	681b      	ldr	r3, [r3, #0]
 8003e66:	4618      	mov	r0, r3
 8003e68:	f7ff fd42 	bl	80038f0 <LL_ADC_REG_IsConversionOngoing>
 8003e6c:	4603      	mov	r3, r0
 8003e6e:	2b00      	cmp	r3, #0
 8003e70:	f040 8313 	bne.w	800449a <HAL_ADC_ConfigChannel+0x66a>
  {
    if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)))
 8003e74:	683b      	ldr	r3, [r7, #0]
 8003e76:	681b      	ldr	r3, [r3, #0]
 8003e78:	2b00      	cmp	r3, #0
 8003e7a:	db2c      	blt.n	8003ed6 <HAL_ADC_ConfigChannel+0xa6>
        /* ADC channels preselection */
        hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
      }
#else
      /* ADC channels preselection */
      hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
 8003e7c:	683b      	ldr	r3, [r7, #0]
 8003e7e:	681b      	ldr	r3, [r3, #0]
 8003e80:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8003e84:	2b00      	cmp	r3, #0
 8003e86:	d108      	bne.n	8003e9a <HAL_ADC_ConfigChannel+0x6a>
 8003e88:	683b      	ldr	r3, [r7, #0]
 8003e8a:	681b      	ldr	r3, [r3, #0]
 8003e8c:	0e9b      	lsrs	r3, r3, #26
 8003e8e:	f003 031f 	and.w	r3, r3, #31
 8003e92:	2201      	movs	r2, #1
 8003e94:	fa02 f303 	lsl.w	r3, r2, r3
 8003e98:	e016      	b.n	8003ec8 <HAL_ADC_ConfigChannel+0x98>
 8003e9a:	683b      	ldr	r3, [r7, #0]
 8003e9c:	681b      	ldr	r3, [r3, #0]
 8003e9e:	667b      	str	r3, [r7, #100]	@ 0x64
  uint32_t result;

#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 8003ea0:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 8003ea2:	fa93 f3a3 	rbit	r3, r3
 8003ea6:	663b      	str	r3, [r7, #96]	@ 0x60
    result |= value & 1U;
    s--;
  }
  result <<= s;                        /* shift when v's highest bits are zero */
#endif
  return result;
 8003ea8:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 8003eaa:	66bb      	str	r3, [r7, #104]	@ 0x68
     optimisations using the logic "value was passed to __builtin_clz, so it
     is non-zero".
     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
     single CLZ instruction.
   */
  if (value == 0U)
 8003eac:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 8003eae:	2b00      	cmp	r3, #0
 8003eb0:	d101      	bne.n	8003eb6 <HAL_ADC_ConfigChannel+0x86>
  {
    return 32U;
 8003eb2:	2320      	movs	r3, #32
 8003eb4:	e003      	b.n	8003ebe <HAL_ADC_ConfigChannel+0x8e>
  }
  return __builtin_clz(value);
 8003eb6:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 8003eb8:	fab3 f383 	clz	r3, r3
 8003ebc:	b2db      	uxtb	r3, r3
 8003ebe:	f003 031f 	and.w	r3, r3, #31
 8003ec2:	2201      	movs	r2, #1
 8003ec4:	fa02 f303 	lsl.w	r3, r2, r3
 8003ec8:	687a      	ldr	r2, [r7, #4]
 8003eca:	6812      	ldr	r2, [r2, #0]
 8003ecc:	69d1      	ldr	r1, [r2, #28]
 8003ece:	687a      	ldr	r2, [r7, #4]
 8003ed0:	6812      	ldr	r2, [r2, #0]
 8003ed2:	430b      	orrs	r3, r1
 8003ed4:	61d3      	str	r3, [r2, #28]
#endif /* ADC_VER_V5_V90 */
    }

    /* Set ADC group regular sequence: channel on the selected scan sequence rank */
    LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
 8003ed6:	687b      	ldr	r3, [r7, #4]
 8003ed8:	6818      	ldr	r0, [r3, #0]
 8003eda:	683b      	ldr	r3, [r7, #0]
 8003edc:	6859      	ldr	r1, [r3, #4]
 8003ede:	683b      	ldr	r3, [r7, #0]
 8003ee0:	681b      	ldr	r3, [r3, #0]
 8003ee2:	461a      	mov	r2, r3
 8003ee4:	f7ff fbb7 	bl	8003656 <LL_ADC_REG_SetSequencerRanks>
    /* Parameters update conditioned to ADC state:                              */
    /* Parameters that can be updated when ADC is disabled or enabled without   */
    /* conversion on going on regular group:                                    */
    /*  - Channel sampling time                                                 */
    /*  - Channel offset                                                        */
    tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
 8003ee8:	687b      	ldr	r3, [r7, #4]
 8003eea:	681b      	ldr	r3, [r3, #0]
 8003eec:	4618      	mov	r0, r3
 8003eee:	f7ff fcff 	bl	80038f0 <LL_ADC_REG_IsConversionOngoing>
 8003ef2:	67b8      	str	r0, [r7, #120]	@ 0x78
    tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
 8003ef4:	687b      	ldr	r3, [r7, #4]
 8003ef6:	681b      	ldr	r3, [r3, #0]
 8003ef8:	4618      	mov	r0, r3
 8003efa:	f7ff fd0c 	bl	8003916 <LL_ADC_INJ_IsConversionOngoing>
 8003efe:	6778      	str	r0, [r7, #116]	@ 0x74
    if ((tmp_adc_is_conversion_on_going_regular == 0UL)
 8003f00:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
 8003f02:	2b00      	cmp	r3, #0
 8003f04:	f040 80b8 	bne.w	8004078 <HAL_ADC_ConfigChannel+0x248>
        && (tmp_adc_is_conversion_on_going_injected == 0UL)
 8003f08:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
 8003f0a:	2b00      	cmp	r3, #0
 8003f0c:	f040 80b4 	bne.w	8004078 <HAL_ADC_ConfigChannel+0x248>
       )
    {
      /* Set sampling time of the selected ADC channel */
      LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
 8003f10:	687b      	ldr	r3, [r7, #4]
 8003f12:	6818      	ldr	r0, [r3, #0]
 8003f14:	683b      	ldr	r3, [r7, #0]
 8003f16:	6819      	ldr	r1, [r3, #0]
 8003f18:	683b      	ldr	r3, [r7, #0]
 8003f1a:	689b      	ldr	r3, [r3, #8]
 8003f1c:	461a      	mov	r2, r3
 8003f1e:	f7ff fbd9 	bl	80036d4 <LL_ADC_SetChannelSamplingTime>
        tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
      }
      else
#endif /* ADC_VER_V5_V90 */
      {
        tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
 8003f22:	4b30      	ldr	r3, [pc, #192]	@ (8003fe4 <HAL_ADC_ConfigChannel+0x1b4>)
 8003f24:	681b      	ldr	r3, [r3, #0]
 8003f26:	f003 4370 	and.w	r3, r3, #4026531840	@ 0xf0000000
 8003f2a:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 8003f2e:	d10b      	bne.n	8003f48 <HAL_ADC_ConfigChannel+0x118>
 8003f30:	683b      	ldr	r3, [r7, #0]
 8003f32:	695a      	ldr	r2, [r3, #20]
 8003f34:	687b      	ldr	r3, [r7, #4]
 8003f36:	681b      	ldr	r3, [r3, #0]
 8003f38:	68db      	ldr	r3, [r3, #12]
 8003f3a:	089b      	lsrs	r3, r3, #2
 8003f3c:	f003 0307 	and.w	r3, r3, #7
 8003f40:	005b      	lsls	r3, r3, #1
 8003f42:	fa02 f303 	lsl.w	r3, r2, r3
 8003f46:	e01d      	b.n	8003f84 <HAL_ADC_ConfigChannel+0x154>
 8003f48:	687b      	ldr	r3, [r7, #4]
 8003f4a:	681b      	ldr	r3, [r3, #0]
 8003f4c:	68db      	ldr	r3, [r3, #12]
 8003f4e:	f003 0310 	and.w	r3, r3, #16
 8003f52:	2b00      	cmp	r3, #0
 8003f54:	d10b      	bne.n	8003f6e <HAL_ADC_ConfigChannel+0x13e>
 8003f56:	683b      	ldr	r3, [r7, #0]
 8003f58:	695a      	ldr	r2, [r3, #20]
 8003f5a:	687b      	ldr	r3, [r7, #4]
 8003f5c:	681b      	ldr	r3, [r3, #0]
 8003f5e:	68db      	ldr	r3, [r3, #12]
 8003f60:	089b      	lsrs	r3, r3, #2
 8003f62:	f003 0307 	and.w	r3, r3, #7
 8003f66:	005b      	lsls	r3, r3, #1
 8003f68:	fa02 f303 	lsl.w	r3, r2, r3
 8003f6c:	e00a      	b.n	8003f84 <HAL_ADC_ConfigChannel+0x154>
 8003f6e:	683b      	ldr	r3, [r7, #0]
 8003f70:	695a      	ldr	r2, [r3, #20]
 8003f72:	687b      	ldr	r3, [r7, #4]
 8003f74:	681b      	ldr	r3, [r3, #0]
 8003f76:	68db      	ldr	r3, [r3, #12]
 8003f78:	089b      	lsrs	r3, r3, #2
 8003f7a:	f003 0304 	and.w	r3, r3, #4
 8003f7e:	005b      	lsls	r3, r3, #1
 8003f80:	fa02 f303 	lsl.w	r3, r2, r3
 8003f84:	673b      	str	r3, [r7, #112]	@ 0x70
      }
      
      if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
 8003f86:	683b      	ldr	r3, [r7, #0]
 8003f88:	691b      	ldr	r3, [r3, #16]
 8003f8a:	2b04      	cmp	r3, #4
 8003f8c:	d02c      	beq.n	8003fe8 <HAL_ADC_ConfigChannel+0x1b8>
      {
        /* Set ADC selected offset number */
        LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
 8003f8e:	687b      	ldr	r3, [r7, #4]
 8003f90:	6818      	ldr	r0, [r3, #0]
 8003f92:	683b      	ldr	r3, [r7, #0]
 8003f94:	6919      	ldr	r1, [r3, #16]
 8003f96:	683b      	ldr	r3, [r7, #0]
 8003f98:	681a      	ldr	r2, [r3, #0]
 8003f9a:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
 8003f9c:	f7ff faf4 	bl	8003588 <LL_ADC_SetOffset>
        else
#endif /* ADC_VER_V5_V90 */
        {
          assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation));
          /* Set ADC selected offset signed saturation */
          LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
 8003fa0:	687b      	ldr	r3, [r7, #4]
 8003fa2:	6818      	ldr	r0, [r3, #0]
 8003fa4:	683b      	ldr	r3, [r7, #0]
 8003fa6:	6919      	ldr	r1, [r3, #16]
 8003fa8:	683b      	ldr	r3, [r7, #0]
 8003faa:	7e5b      	ldrb	r3, [r3, #25]
 8003fac:	2b01      	cmp	r3, #1
 8003fae:	d102      	bne.n	8003fb6 <HAL_ADC_ConfigChannel+0x186>
 8003fb0:	f04f 4300 	mov.w	r3, #2147483648	@ 0x80000000
 8003fb4:	e000      	b.n	8003fb8 <HAL_ADC_ConfigChannel+0x188>
 8003fb6:	2300      	movs	r3, #0
 8003fb8:	461a      	mov	r2, r3
 8003fba:	f7ff fb1e 	bl	80035fa <LL_ADC_SetOffsetSignedSaturation>

          assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift));
          /* Set ADC selected offset right shift */
          LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
 8003fbe:	687b      	ldr	r3, [r7, #4]
 8003fc0:	6818      	ldr	r0, [r3, #0]
 8003fc2:	683b      	ldr	r3, [r7, #0]
 8003fc4:	6919      	ldr	r1, [r3, #16]
 8003fc6:	683b      	ldr	r3, [r7, #0]
 8003fc8:	7e1b      	ldrb	r3, [r3, #24]
 8003fca:	2b01      	cmp	r3, #1
 8003fcc:	d102      	bne.n	8003fd4 <HAL_ADC_ConfigChannel+0x1a4>
 8003fce:	f44f 6300 	mov.w	r3, #2048	@ 0x800
 8003fd2:	e000      	b.n	8003fd6 <HAL_ADC_ConfigChannel+0x1a6>
 8003fd4:	2300      	movs	r3, #0
 8003fd6:	461a      	mov	r2, r3
 8003fd8:	f7ff faf6 	bl	80035c8 <LL_ADC_SetDataRightShift>
 8003fdc:	e04c      	b.n	8004078 <HAL_ADC_ConfigChannel+0x248>
 8003fde:	bf00      	nop
 8003fe0:	47ff0000 	.word	0x47ff0000
 8003fe4:	5c001000 	.word	0x5c001000
          }
        }
        else
#endif /* ADC_VER_V5_V90 */
        {
          if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
 8003fe8:	687b      	ldr	r3, [r7, #4]
 8003fea:	681b      	ldr	r3, [r3, #0]
 8003fec:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8003fee:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 8003ff2:	683b      	ldr	r3, [r7, #0]
 8003ff4:	681b      	ldr	r3, [r3, #0]
 8003ff6:	069b      	lsls	r3, r3, #26
 8003ff8:	429a      	cmp	r2, r3
 8003ffa:	d107      	bne.n	800400c <HAL_ADC_ConfigChannel+0x1dc>
          {
            CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
 8003ffc:	687b      	ldr	r3, [r7, #4]
 8003ffe:	681b      	ldr	r3, [r3, #0]
 8004000:	6e1a      	ldr	r2, [r3, #96]	@ 0x60
 8004002:	687b      	ldr	r3, [r7, #4]
 8004004:	681b      	ldr	r3, [r3, #0]
 8004006:	f022 4200 	bic.w	r2, r2, #2147483648	@ 0x80000000
 800400a:	661a      	str	r2, [r3, #96]	@ 0x60
          }
          if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
 800400c:	687b      	ldr	r3, [r7, #4]
 800400e:	681b      	ldr	r3, [r3, #0]
 8004010:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8004012:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 8004016:	683b      	ldr	r3, [r7, #0]
 8004018:	681b      	ldr	r3, [r3, #0]
 800401a:	069b      	lsls	r3, r3, #26
 800401c:	429a      	cmp	r2, r3
 800401e:	d107      	bne.n	8004030 <HAL_ADC_ConfigChannel+0x200>
          {
            CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
 8004020:	687b      	ldr	r3, [r7, #4]
 8004022:	681b      	ldr	r3, [r3, #0]
 8004024:	6e5a      	ldr	r2, [r3, #100]	@ 0x64
 8004026:	687b      	ldr	r3, [r7, #4]
 8004028:	681b      	ldr	r3, [r3, #0]
 800402a:	f022 4200 	bic.w	r2, r2, #2147483648	@ 0x80000000
 800402e:	665a      	str	r2, [r3, #100]	@ 0x64
          }
          if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
 8004030:	687b      	ldr	r3, [r7, #4]
 8004032:	681b      	ldr	r3, [r3, #0]
 8004034:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 8004036:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 800403a:	683b      	ldr	r3, [r7, #0]
 800403c:	681b      	ldr	r3, [r3, #0]
 800403e:	069b      	lsls	r3, r3, #26
 8004040:	429a      	cmp	r2, r3
 8004042:	d107      	bne.n	8004054 <HAL_ADC_ConfigChannel+0x224>
          {
            CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
 8004044:	687b      	ldr	r3, [r7, #4]
 8004046:	681b      	ldr	r3, [r3, #0]
 8004048:	6e9a      	ldr	r2, [r3, #104]	@ 0x68
 800404a:	687b      	ldr	r3, [r7, #4]
 800404c:	681b      	ldr	r3, [r3, #0]
 800404e:	f022 4200 	bic.w	r2, r2, #2147483648	@ 0x80000000
 8004052:	669a      	str	r2, [r3, #104]	@ 0x68
          }
          if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
 8004054:	687b      	ldr	r3, [r7, #4]
 8004056:	681b      	ldr	r3, [r3, #0]
 8004058:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800405a:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 800405e:	683b      	ldr	r3, [r7, #0]
 8004060:	681b      	ldr	r3, [r3, #0]
 8004062:	069b      	lsls	r3, r3, #26
 8004064:	429a      	cmp	r2, r3
 8004066:	d107      	bne.n	8004078 <HAL_ADC_ConfigChannel+0x248>
          {
            CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
 8004068:	687b      	ldr	r3, [r7, #4]
 800406a:	681b      	ldr	r3, [r3, #0]
 800406c:	6eda      	ldr	r2, [r3, #108]	@ 0x6c
 800406e:	687b      	ldr	r3, [r7, #4]
 8004070:	681b      	ldr	r3, [r3, #0]
 8004072:	f022 4200 	bic.w	r2, r2, #2147483648	@ 0x80000000
 8004076:	66da      	str	r2, [r3, #108]	@ 0x6c

    /* Parameters update conditioned to ADC state:                              */
    /* Parameters that can be updated only when ADC is disabled:                */
    /*  - Single or differential mode                                           */
    /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
    if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
 8004078:	687b      	ldr	r3, [r7, #4]
 800407a:	681b      	ldr	r3, [r3, #0]
 800407c:	4618      	mov	r0, r3
 800407e:	f7ff fbfd 	bl	800387c <LL_ADC_IsEnabled>
 8004082:	4603      	mov	r3, r0
 8004084:	2b00      	cmp	r3, #0
 8004086:	f040 8211 	bne.w	80044ac <HAL_ADC_ConfigChannel+0x67c>
    {
      /* Set mode single-ended or differential input of the selected ADC channel */
      LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
 800408a:	687b      	ldr	r3, [r7, #4]
 800408c:	6818      	ldr	r0, [r3, #0]
 800408e:	683b      	ldr	r3, [r7, #0]
 8004090:	6819      	ldr	r1, [r3, #0]
 8004092:	683b      	ldr	r3, [r7, #0]
 8004094:	68db      	ldr	r3, [r3, #12]
 8004096:	461a      	mov	r2, r3
 8004098:	f7ff fb48 	bl	800372c <LL_ADC_SetChannelSingleDiff>

      /* Configuration of differential mode */
      if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
 800409c:	683b      	ldr	r3, [r7, #0]
 800409e:	68db      	ldr	r3, [r3, #12]
 80040a0:	4aa1      	ldr	r2, [pc, #644]	@ (8004328 <HAL_ADC_ConfigChannel+0x4f8>)
 80040a2:	4293      	cmp	r3, r2
 80040a4:	f040 812e 	bne.w	8004304 <HAL_ADC_ConfigChannel+0x4d4>
      {
        /* Set sampling time of the selected ADC channel */
        /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
        LL_ADC_SetChannelSamplingTime(hadc->Instance,
 80040a8:	687b      	ldr	r3, [r7, #4]
 80040aa:	6818      	ldr	r0, [r3, #0]
                                      (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
 80040ac:	683b      	ldr	r3, [r7, #0]
 80040ae:	681b      	ldr	r3, [r3, #0]
 80040b0:	f3c3 0313 	ubfx	r3, r3, #0, #20
 80040b4:	2b00      	cmp	r3, #0
 80040b6:	d10b      	bne.n	80040d0 <HAL_ADC_ConfigChannel+0x2a0>
 80040b8:	683b      	ldr	r3, [r7, #0]
 80040ba:	681b      	ldr	r3, [r3, #0]
 80040bc:	0e9b      	lsrs	r3, r3, #26
 80040be:	3301      	adds	r3, #1
 80040c0:	f003 031f 	and.w	r3, r3, #31
 80040c4:	2b09      	cmp	r3, #9
 80040c6:	bf94      	ite	ls
 80040c8:	2301      	movls	r3, #1
 80040ca:	2300      	movhi	r3, #0
 80040cc:	b2db      	uxtb	r3, r3
 80040ce:	e019      	b.n	8004104 <HAL_ADC_ConfigChannel+0x2d4>
 80040d0:	683b      	ldr	r3, [r7, #0]
 80040d2:	681b      	ldr	r3, [r3, #0]
 80040d4:	65bb      	str	r3, [r7, #88]	@ 0x58
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 80040d6:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
 80040d8:	fa93 f3a3 	rbit	r3, r3
 80040dc:	657b      	str	r3, [r7, #84]	@ 0x54
  return result;
 80040de:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 80040e0:	65fb      	str	r3, [r7, #92]	@ 0x5c
  if (value == 0U)
 80040e2:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 80040e4:	2b00      	cmp	r3, #0
 80040e6:	d101      	bne.n	80040ec <HAL_ADC_ConfigChannel+0x2bc>
    return 32U;
 80040e8:	2320      	movs	r3, #32
 80040ea:	e003      	b.n	80040f4 <HAL_ADC_ConfigChannel+0x2c4>
  return __builtin_clz(value);
 80040ec:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 80040ee:	fab3 f383 	clz	r3, r3
 80040f2:	b2db      	uxtb	r3, r3
 80040f4:	3301      	adds	r3, #1
 80040f6:	f003 031f 	and.w	r3, r3, #31
 80040fa:	2b09      	cmp	r3, #9
 80040fc:	bf94      	ite	ls
 80040fe:	2301      	movls	r3, #1
 8004100:	2300      	movhi	r3, #0
 8004102:	b2db      	uxtb	r3, r3
        LL_ADC_SetChannelSamplingTime(hadc->Instance,
 8004104:	2b00      	cmp	r3, #0
 8004106:	d079      	beq.n	80041fc <HAL_ADC_ConfigChannel+0x3cc>
                                      (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
 8004108:	683b      	ldr	r3, [r7, #0]
 800410a:	681b      	ldr	r3, [r3, #0]
 800410c:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8004110:	2b00      	cmp	r3, #0
 8004112:	d107      	bne.n	8004124 <HAL_ADC_ConfigChannel+0x2f4>
 8004114:	683b      	ldr	r3, [r7, #0]
 8004116:	681b      	ldr	r3, [r3, #0]
 8004118:	0e9b      	lsrs	r3, r3, #26
 800411a:	3301      	adds	r3, #1
 800411c:	069b      	lsls	r3, r3, #26
 800411e:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 8004122:	e015      	b.n	8004150 <HAL_ADC_ConfigChannel+0x320>
 8004124:	683b      	ldr	r3, [r7, #0]
 8004126:	681b      	ldr	r3, [r3, #0]
 8004128:	64fb      	str	r3, [r7, #76]	@ 0x4c
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 800412a:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 800412c:	fa93 f3a3 	rbit	r3, r3
 8004130:	64bb      	str	r3, [r7, #72]	@ 0x48
  return result;
 8004132:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 8004134:	653b      	str	r3, [r7, #80]	@ 0x50
  if (value == 0U)
 8004136:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 8004138:	2b00      	cmp	r3, #0
 800413a:	d101      	bne.n	8004140 <HAL_ADC_ConfigChannel+0x310>
    return 32U;
 800413c:	2320      	movs	r3, #32
 800413e:	e003      	b.n	8004148 <HAL_ADC_ConfigChannel+0x318>
  return __builtin_clz(value);
 8004140:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 8004142:	fab3 f383 	clz	r3, r3
 8004146:	b2db      	uxtb	r3, r3
 8004148:	3301      	adds	r3, #1
 800414a:	069b      	lsls	r3, r3, #26
 800414c:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 8004150:	683b      	ldr	r3, [r7, #0]
 8004152:	681b      	ldr	r3, [r3, #0]
 8004154:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8004158:	2b00      	cmp	r3, #0
 800415a:	d109      	bne.n	8004170 <HAL_ADC_ConfigChannel+0x340>
 800415c:	683b      	ldr	r3, [r7, #0]
 800415e:	681b      	ldr	r3, [r3, #0]
 8004160:	0e9b      	lsrs	r3, r3, #26
 8004162:	3301      	adds	r3, #1
 8004164:	f003 031f 	and.w	r3, r3, #31
 8004168:	2101      	movs	r1, #1
 800416a:	fa01 f303 	lsl.w	r3, r1, r3
 800416e:	e017      	b.n	80041a0 <HAL_ADC_ConfigChannel+0x370>
 8004170:	683b      	ldr	r3, [r7, #0]
 8004172:	681b      	ldr	r3, [r3, #0]
 8004174:	643b      	str	r3, [r7, #64]	@ 0x40
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 8004176:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 8004178:	fa93 f3a3 	rbit	r3, r3
 800417c:	63fb      	str	r3, [r7, #60]	@ 0x3c
  return result;
 800417e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8004180:	647b      	str	r3, [r7, #68]	@ 0x44
  if (value == 0U)
 8004182:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 8004184:	2b00      	cmp	r3, #0
 8004186:	d101      	bne.n	800418c <HAL_ADC_ConfigChannel+0x35c>
    return 32U;
 8004188:	2320      	movs	r3, #32
 800418a:	e003      	b.n	8004194 <HAL_ADC_ConfigChannel+0x364>
  return __builtin_clz(value);
 800418c:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 800418e:	fab3 f383 	clz	r3, r3
 8004192:	b2db      	uxtb	r3, r3
 8004194:	3301      	adds	r3, #1
 8004196:	f003 031f 	and.w	r3, r3, #31
 800419a:	2101      	movs	r1, #1
 800419c:	fa01 f303 	lsl.w	r3, r1, r3
 80041a0:	ea42 0103 	orr.w	r1, r2, r3
 80041a4:	683b      	ldr	r3, [r7, #0]
 80041a6:	681b      	ldr	r3, [r3, #0]
 80041a8:	f3c3 0313 	ubfx	r3, r3, #0, #20
 80041ac:	2b00      	cmp	r3, #0
 80041ae:	d10a      	bne.n	80041c6 <HAL_ADC_ConfigChannel+0x396>
 80041b0:	683b      	ldr	r3, [r7, #0]
 80041b2:	681b      	ldr	r3, [r3, #0]
 80041b4:	0e9b      	lsrs	r3, r3, #26
 80041b6:	3301      	adds	r3, #1
 80041b8:	f003 021f 	and.w	r2, r3, #31
 80041bc:	4613      	mov	r3, r2
 80041be:	005b      	lsls	r3, r3, #1
 80041c0:	4413      	add	r3, r2
 80041c2:	051b      	lsls	r3, r3, #20
 80041c4:	e018      	b.n	80041f8 <HAL_ADC_ConfigChannel+0x3c8>
 80041c6:	683b      	ldr	r3, [r7, #0]
 80041c8:	681b      	ldr	r3, [r3, #0]
 80041ca:	637b      	str	r3, [r7, #52]	@ 0x34
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 80041cc:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80041ce:	fa93 f3a3 	rbit	r3, r3
 80041d2:	633b      	str	r3, [r7, #48]	@ 0x30
  return result;
 80041d4:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80041d6:	63bb      	str	r3, [r7, #56]	@ 0x38
  if (value == 0U)
 80041d8:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80041da:	2b00      	cmp	r3, #0
 80041dc:	d101      	bne.n	80041e2 <HAL_ADC_ConfigChannel+0x3b2>
    return 32U;
 80041de:	2320      	movs	r3, #32
 80041e0:	e003      	b.n	80041ea <HAL_ADC_ConfigChannel+0x3ba>
  return __builtin_clz(value);
 80041e2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80041e4:	fab3 f383 	clz	r3, r3
 80041e8:	b2db      	uxtb	r3, r3
 80041ea:	3301      	adds	r3, #1
 80041ec:	f003 021f 	and.w	r2, r3, #31
 80041f0:	4613      	mov	r3, r2
 80041f2:	005b      	lsls	r3, r3, #1
 80041f4:	4413      	add	r3, r2
 80041f6:	051b      	lsls	r3, r3, #20
        LL_ADC_SetChannelSamplingTime(hadc->Instance,
 80041f8:	430b      	orrs	r3, r1
 80041fa:	e07e      	b.n	80042fa <HAL_ADC_ConfigChannel+0x4ca>
                                      (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
 80041fc:	683b      	ldr	r3, [r7, #0]
 80041fe:	681b      	ldr	r3, [r3, #0]
 8004200:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8004204:	2b00      	cmp	r3, #0
 8004206:	d107      	bne.n	8004218 <HAL_ADC_ConfigChannel+0x3e8>
 8004208:	683b      	ldr	r3, [r7, #0]
 800420a:	681b      	ldr	r3, [r3, #0]
 800420c:	0e9b      	lsrs	r3, r3, #26
 800420e:	3301      	adds	r3, #1
 8004210:	069b      	lsls	r3, r3, #26
 8004212:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 8004216:	e015      	b.n	8004244 <HAL_ADC_ConfigChannel+0x414>
 8004218:	683b      	ldr	r3, [r7, #0]
 800421a:	681b      	ldr	r3, [r3, #0]
 800421c:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 800421e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8004220:	fa93 f3a3 	rbit	r3, r3
 8004224:	627b      	str	r3, [r7, #36]	@ 0x24
  return result;
 8004226:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8004228:	62fb      	str	r3, [r7, #44]	@ 0x2c
  if (value == 0U)
 800422a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800422c:	2b00      	cmp	r3, #0
 800422e:	d101      	bne.n	8004234 <HAL_ADC_ConfigChannel+0x404>
    return 32U;
 8004230:	2320      	movs	r3, #32
 8004232:	e003      	b.n	800423c <HAL_ADC_ConfigChannel+0x40c>
  return __builtin_clz(value);
 8004234:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8004236:	fab3 f383 	clz	r3, r3
 800423a:	b2db      	uxtb	r3, r3
 800423c:	3301      	adds	r3, #1
 800423e:	069b      	lsls	r3, r3, #26
 8004240:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 8004244:	683b      	ldr	r3, [r7, #0]
 8004246:	681b      	ldr	r3, [r3, #0]
 8004248:	f3c3 0313 	ubfx	r3, r3, #0, #20
 800424c:	2b00      	cmp	r3, #0
 800424e:	d109      	bne.n	8004264 <HAL_ADC_ConfigChannel+0x434>
 8004250:	683b      	ldr	r3, [r7, #0]
 8004252:	681b      	ldr	r3, [r3, #0]
 8004254:	0e9b      	lsrs	r3, r3, #26
 8004256:	3301      	adds	r3, #1
 8004258:	f003 031f 	and.w	r3, r3, #31
 800425c:	2101      	movs	r1, #1
 800425e:	fa01 f303 	lsl.w	r3, r1, r3
 8004262:	e017      	b.n	8004294 <HAL_ADC_ConfigChannel+0x464>
 8004264:	683b      	ldr	r3, [r7, #0]
 8004266:	681b      	ldr	r3, [r3, #0]
 8004268:	61fb      	str	r3, [r7, #28]
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 800426a:	69fb      	ldr	r3, [r7, #28]
 800426c:	fa93 f3a3 	rbit	r3, r3
 8004270:	61bb      	str	r3, [r7, #24]
  return result;
 8004272:	69bb      	ldr	r3, [r7, #24]
 8004274:	623b      	str	r3, [r7, #32]
  if (value == 0U)
 8004276:	6a3b      	ldr	r3, [r7, #32]
 8004278:	2b00      	cmp	r3, #0
 800427a:	d101      	bne.n	8004280 <HAL_ADC_ConfigChannel+0x450>
    return 32U;
 800427c:	2320      	movs	r3, #32
 800427e:	e003      	b.n	8004288 <HAL_ADC_ConfigChannel+0x458>
  return __builtin_clz(value);
 8004280:	6a3b      	ldr	r3, [r7, #32]
 8004282:	fab3 f383 	clz	r3, r3
 8004286:	b2db      	uxtb	r3, r3
 8004288:	3301      	adds	r3, #1
 800428a:	f003 031f 	and.w	r3, r3, #31
 800428e:	2101      	movs	r1, #1
 8004290:	fa01 f303 	lsl.w	r3, r1, r3
 8004294:	ea42 0103 	orr.w	r1, r2, r3
 8004298:	683b      	ldr	r3, [r7, #0]
 800429a:	681b      	ldr	r3, [r3, #0]
 800429c:	f3c3 0313 	ubfx	r3, r3, #0, #20
 80042a0:	2b00      	cmp	r3, #0
 80042a2:	d10d      	bne.n	80042c0 <HAL_ADC_ConfigChannel+0x490>
 80042a4:	683b      	ldr	r3, [r7, #0]
 80042a6:	681b      	ldr	r3, [r3, #0]
 80042a8:	0e9b      	lsrs	r3, r3, #26
 80042aa:	3301      	adds	r3, #1
 80042ac:	f003 021f 	and.w	r2, r3, #31
 80042b0:	4613      	mov	r3, r2
 80042b2:	005b      	lsls	r3, r3, #1
 80042b4:	4413      	add	r3, r2
 80042b6:	3b1e      	subs	r3, #30
 80042b8:	051b      	lsls	r3, r3, #20
 80042ba:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
 80042be:	e01b      	b.n	80042f8 <HAL_ADC_ConfigChannel+0x4c8>
 80042c0:	683b      	ldr	r3, [r7, #0]
 80042c2:	681b      	ldr	r3, [r3, #0]
 80042c4:	613b      	str	r3, [r7, #16]
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 80042c6:	693b      	ldr	r3, [r7, #16]
 80042c8:	fa93 f3a3 	rbit	r3, r3
 80042cc:	60fb      	str	r3, [r7, #12]
  return result;
 80042ce:	68fb      	ldr	r3, [r7, #12]
 80042d0:	617b      	str	r3, [r7, #20]
  if (value == 0U)
 80042d2:	697b      	ldr	r3, [r7, #20]
 80042d4:	2b00      	cmp	r3, #0
 80042d6:	d101      	bne.n	80042dc <HAL_ADC_ConfigChannel+0x4ac>
    return 32U;
 80042d8:	2320      	movs	r3, #32
 80042da:	e003      	b.n	80042e4 <HAL_ADC_ConfigChannel+0x4b4>
  return __builtin_clz(value);
 80042dc:	697b      	ldr	r3, [r7, #20]
 80042de:	fab3 f383 	clz	r3, r3
 80042e2:	b2db      	uxtb	r3, r3
 80042e4:	3301      	adds	r3, #1
 80042e6:	f003 021f 	and.w	r2, r3, #31
 80042ea:	4613      	mov	r3, r2
 80042ec:	005b      	lsls	r3, r3, #1
 80042ee:	4413      	add	r3, r2
 80042f0:	3b1e      	subs	r3, #30
 80042f2:	051b      	lsls	r3, r3, #20
 80042f4:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
        LL_ADC_SetChannelSamplingTime(hadc->Instance,
 80042f8:	430b      	orrs	r3, r1
 80042fa:	683a      	ldr	r2, [r7, #0]
 80042fc:	6892      	ldr	r2, [r2, #8]
 80042fe:	4619      	mov	r1, r3
 8004300:	f7ff f9e8 	bl	80036d4 <LL_ADC_SetChannelSamplingTime>
      /* If internal channel selected, enable dedicated internal buffers and    */
      /* paths.                                                                 */
      /* Note: these internal measurement paths can be disabled using           */
      /* HAL_ADC_DeInit().                                                      */

      if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
 8004304:	683b      	ldr	r3, [r7, #0]
 8004306:	681b      	ldr	r3, [r3, #0]
 8004308:	2b00      	cmp	r3, #0
 800430a:	f280 80cf 	bge.w	80044ac <HAL_ADC_ConfigChannel+0x67c>
      {
        /* Configuration of common ADC parameters                                 */

        tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
 800430e:	687b      	ldr	r3, [r7, #4]
 8004310:	681b      	ldr	r3, [r3, #0]
 8004312:	4a06      	ldr	r2, [pc, #24]	@ (800432c <HAL_ADC_ConfigChannel+0x4fc>)
 8004314:	4293      	cmp	r3, r2
 8004316:	d004      	beq.n	8004322 <HAL_ADC_ConfigChannel+0x4f2>
 8004318:	687b      	ldr	r3, [r7, #4]
 800431a:	681b      	ldr	r3, [r3, #0]
 800431c:	4a04      	ldr	r2, [pc, #16]	@ (8004330 <HAL_ADC_ConfigChannel+0x500>)
 800431e:	4293      	cmp	r3, r2
 8004320:	d10a      	bne.n	8004338 <HAL_ADC_ConfigChannel+0x508>
 8004322:	4b04      	ldr	r3, [pc, #16]	@ (8004334 <HAL_ADC_ConfigChannel+0x504>)
 8004324:	e009      	b.n	800433a <HAL_ADC_ConfigChannel+0x50a>
 8004326:	bf00      	nop
 8004328:	47ff0000 	.word	0x47ff0000
 800432c:	40022000 	.word	0x40022000
 8004330:	40022100 	.word	0x40022100
 8004334:	40022300 	.word	0x40022300
 8004338:	4b61      	ldr	r3, [pc, #388]	@ (80044c0 <HAL_ADC_ConfigChannel+0x690>)
 800433a:	4618      	mov	r0, r3
 800433c:	f7ff f916 	bl	800356c <LL_ADC_GetCommonPathInternalCh>
 8004340:	66f8      	str	r0, [r7, #108]	@ 0x6c

        /* Software is allowed to change common parameters only when all ADCs   */
        /* of the common group are disabled.                                    */
        if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
 8004342:	687b      	ldr	r3, [r7, #4]
 8004344:	681b      	ldr	r3, [r3, #0]
 8004346:	4a5f      	ldr	r2, [pc, #380]	@ (80044c4 <HAL_ADC_ConfigChannel+0x694>)
 8004348:	4293      	cmp	r3, r2
 800434a:	d004      	beq.n	8004356 <HAL_ADC_ConfigChannel+0x526>
 800434c:	687b      	ldr	r3, [r7, #4]
 800434e:	681b      	ldr	r3, [r3, #0]
 8004350:	4a5d      	ldr	r2, [pc, #372]	@ (80044c8 <HAL_ADC_ConfigChannel+0x698>)
 8004352:	4293      	cmp	r3, r2
 8004354:	d10e      	bne.n	8004374 <HAL_ADC_ConfigChannel+0x544>
 8004356:	485b      	ldr	r0, [pc, #364]	@ (80044c4 <HAL_ADC_ConfigChannel+0x694>)
 8004358:	f7ff fa90 	bl	800387c <LL_ADC_IsEnabled>
 800435c:	4604      	mov	r4, r0
 800435e:	485a      	ldr	r0, [pc, #360]	@ (80044c8 <HAL_ADC_ConfigChannel+0x698>)
 8004360:	f7ff fa8c 	bl	800387c <LL_ADC_IsEnabled>
 8004364:	4603      	mov	r3, r0
 8004366:	4323      	orrs	r3, r4
 8004368:	2b00      	cmp	r3, #0
 800436a:	bf0c      	ite	eq
 800436c:	2301      	moveq	r3, #1
 800436e:	2300      	movne	r3, #0
 8004370:	b2db      	uxtb	r3, r3
 8004372:	e008      	b.n	8004386 <HAL_ADC_ConfigChannel+0x556>
 8004374:	4855      	ldr	r0, [pc, #340]	@ (80044cc <HAL_ADC_ConfigChannel+0x69c>)
 8004376:	f7ff fa81 	bl	800387c <LL_ADC_IsEnabled>
 800437a:	4603      	mov	r3, r0
 800437c:	2b00      	cmp	r3, #0
 800437e:	bf0c      	ite	eq
 8004380:	2301      	moveq	r3, #1
 8004382:	2300      	movne	r3, #0
 8004384:	b2db      	uxtb	r3, r3
 8004386:	2b00      	cmp	r3, #0
 8004388:	d07d      	beq.n	8004486 <HAL_ADC_ConfigChannel+0x656>
        {
          /* If the requested internal measurement path has already been enabled, */
          /* bypass the configuration processing.                                 */
          if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
 800438a:	683b      	ldr	r3, [r7, #0]
 800438c:	681b      	ldr	r3, [r3, #0]
 800438e:	4a50      	ldr	r2, [pc, #320]	@ (80044d0 <HAL_ADC_ConfigChannel+0x6a0>)
 8004390:	4293      	cmp	r3, r2
 8004392:	d130      	bne.n	80043f6 <HAL_ADC_ConfigChannel+0x5c6>
 8004394:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8004396:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 800439a:	2b00      	cmp	r3, #0
 800439c:	d12b      	bne.n	80043f6 <HAL_ADC_ConfigChannel+0x5c6>
          {
            if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
 800439e:	687b      	ldr	r3, [r7, #4]
 80043a0:	681b      	ldr	r3, [r3, #0]
 80043a2:	4a4a      	ldr	r2, [pc, #296]	@ (80044cc <HAL_ADC_ConfigChannel+0x69c>)
 80043a4:	4293      	cmp	r3, r2
 80043a6:	f040 8081 	bne.w	80044ac <HAL_ADC_ConfigChannel+0x67c>
            {
              LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
 80043aa:	687b      	ldr	r3, [r7, #4]
 80043ac:	681b      	ldr	r3, [r3, #0]
 80043ae:	4a45      	ldr	r2, [pc, #276]	@ (80044c4 <HAL_ADC_ConfigChannel+0x694>)
 80043b0:	4293      	cmp	r3, r2
 80043b2:	d004      	beq.n	80043be <HAL_ADC_ConfigChannel+0x58e>
 80043b4:	687b      	ldr	r3, [r7, #4]
 80043b6:	681b      	ldr	r3, [r3, #0]
 80043b8:	4a43      	ldr	r2, [pc, #268]	@ (80044c8 <HAL_ADC_ConfigChannel+0x698>)
 80043ba:	4293      	cmp	r3, r2
 80043bc:	d101      	bne.n	80043c2 <HAL_ADC_ConfigChannel+0x592>
 80043be:	4a45      	ldr	r2, [pc, #276]	@ (80044d4 <HAL_ADC_ConfigChannel+0x6a4>)
 80043c0:	e000      	b.n	80043c4 <HAL_ADC_ConfigChannel+0x594>
 80043c2:	4a3f      	ldr	r2, [pc, #252]	@ (80044c0 <HAL_ADC_ConfigChannel+0x690>)
 80043c4:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 80043c6:	f443 0300 	orr.w	r3, r3, #8388608	@ 0x800000
 80043ca:	4619      	mov	r1, r3
 80043cc:	4610      	mov	r0, r2
 80043ce:	f7ff f8ba 	bl	8003546 <LL_ADC_SetCommonPathInternalCh>
              /* Delay for temperature sensor stabilization time */
              /* Wait loop initialization and execution */
              /* Note: Variable divided by 2 to compensate partially              */
              /*       CPU processing cycles, scaling in us split to not          */
              /*       exceed 32 bits register capacity and handle low frequency. */
              wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
 80043d2:	4b41      	ldr	r3, [pc, #260]	@ (80044d8 <HAL_ADC_ConfigChannel+0x6a8>)
 80043d4:	681b      	ldr	r3, [r3, #0]
 80043d6:	099b      	lsrs	r3, r3, #6
 80043d8:	4a40      	ldr	r2, [pc, #256]	@ (80044dc <HAL_ADC_ConfigChannel+0x6ac>)
 80043da:	fba2 2303 	umull	r2, r3, r2, r3
 80043de:	099b      	lsrs	r3, r3, #6
 80043e0:	3301      	adds	r3, #1
 80043e2:	005b      	lsls	r3, r3, #1
 80043e4:	60bb      	str	r3, [r7, #8]
              while (wait_loop_index != 0UL)
 80043e6:	e002      	b.n	80043ee <HAL_ADC_ConfigChannel+0x5be>
              {
                wait_loop_index--;
 80043e8:	68bb      	ldr	r3, [r7, #8]
 80043ea:	3b01      	subs	r3, #1
 80043ec:	60bb      	str	r3, [r7, #8]
              while (wait_loop_index != 0UL)
 80043ee:	68bb      	ldr	r3, [r7, #8]
 80043f0:	2b00      	cmp	r3, #0
 80043f2:	d1f9      	bne.n	80043e8 <HAL_ADC_ConfigChannel+0x5b8>
            if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
 80043f4:	e05a      	b.n	80044ac <HAL_ADC_ConfigChannel+0x67c>
              }
            }
          }
          else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
 80043f6:	683b      	ldr	r3, [r7, #0]
 80043f8:	681b      	ldr	r3, [r3, #0]
 80043fa:	4a39      	ldr	r2, [pc, #228]	@ (80044e0 <HAL_ADC_ConfigChannel+0x6b0>)
 80043fc:	4293      	cmp	r3, r2
 80043fe:	d11e      	bne.n	800443e <HAL_ADC_ConfigChannel+0x60e>
 8004400:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8004402:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 8004406:	2b00      	cmp	r3, #0
 8004408:	d119      	bne.n	800443e <HAL_ADC_ConfigChannel+0x60e>
          {
            if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
 800440a:	687b      	ldr	r3, [r7, #4]
 800440c:	681b      	ldr	r3, [r3, #0]
 800440e:	4a2f      	ldr	r2, [pc, #188]	@ (80044cc <HAL_ADC_ConfigChannel+0x69c>)
 8004410:	4293      	cmp	r3, r2
 8004412:	d14b      	bne.n	80044ac <HAL_ADC_ConfigChannel+0x67c>
            {
              LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
 8004414:	687b      	ldr	r3, [r7, #4]
 8004416:	681b      	ldr	r3, [r3, #0]
 8004418:	4a2a      	ldr	r2, [pc, #168]	@ (80044c4 <HAL_ADC_ConfigChannel+0x694>)
 800441a:	4293      	cmp	r3, r2
 800441c:	d004      	beq.n	8004428 <HAL_ADC_ConfigChannel+0x5f8>
 800441e:	687b      	ldr	r3, [r7, #4]
 8004420:	681b      	ldr	r3, [r3, #0]
 8004422:	4a29      	ldr	r2, [pc, #164]	@ (80044c8 <HAL_ADC_ConfigChannel+0x698>)
 8004424:	4293      	cmp	r3, r2
 8004426:	d101      	bne.n	800442c <HAL_ADC_ConfigChannel+0x5fc>
 8004428:	4a2a      	ldr	r2, [pc, #168]	@ (80044d4 <HAL_ADC_ConfigChannel+0x6a4>)
 800442a:	e000      	b.n	800442e <HAL_ADC_ConfigChannel+0x5fe>
 800442c:	4a24      	ldr	r2, [pc, #144]	@ (80044c0 <HAL_ADC_ConfigChannel+0x690>)
 800442e:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8004430:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8004434:	4619      	mov	r1, r3
 8004436:	4610      	mov	r0, r2
 8004438:	f7ff f885 	bl	8003546 <LL_ADC_SetCommonPathInternalCh>
            if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
 800443c:	e036      	b.n	80044ac <HAL_ADC_ConfigChannel+0x67c>
            }
          }
          else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
 800443e:	683b      	ldr	r3, [r7, #0]
 8004440:	681b      	ldr	r3, [r3, #0]
 8004442:	4a28      	ldr	r2, [pc, #160]	@ (80044e4 <HAL_ADC_ConfigChannel+0x6b4>)
 8004444:	4293      	cmp	r3, r2
 8004446:	d131      	bne.n	80044ac <HAL_ADC_ConfigChannel+0x67c>
 8004448:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 800444a:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
 800444e:	2b00      	cmp	r3, #0
 8004450:	d12c      	bne.n	80044ac <HAL_ADC_ConfigChannel+0x67c>
          {
            if (ADC_VREFINT_INSTANCE(hadc))
 8004452:	687b      	ldr	r3, [r7, #4]
 8004454:	681b      	ldr	r3, [r3, #0]
 8004456:	4a1d      	ldr	r2, [pc, #116]	@ (80044cc <HAL_ADC_ConfigChannel+0x69c>)
 8004458:	4293      	cmp	r3, r2
 800445a:	d127      	bne.n	80044ac <HAL_ADC_ConfigChannel+0x67c>
            {
              LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
 800445c:	687b      	ldr	r3, [r7, #4]
 800445e:	681b      	ldr	r3, [r3, #0]
 8004460:	4a18      	ldr	r2, [pc, #96]	@ (80044c4 <HAL_ADC_ConfigChannel+0x694>)
 8004462:	4293      	cmp	r3, r2
 8004464:	d004      	beq.n	8004470 <HAL_ADC_ConfigChannel+0x640>
 8004466:	687b      	ldr	r3, [r7, #4]
 8004468:	681b      	ldr	r3, [r3, #0]
 800446a:	4a17      	ldr	r2, [pc, #92]	@ (80044c8 <HAL_ADC_ConfigChannel+0x698>)
 800446c:	4293      	cmp	r3, r2
 800446e:	d101      	bne.n	8004474 <HAL_ADC_ConfigChannel+0x644>
 8004470:	4a18      	ldr	r2, [pc, #96]	@ (80044d4 <HAL_ADC_ConfigChannel+0x6a4>)
 8004472:	e000      	b.n	8004476 <HAL_ADC_ConfigChannel+0x646>
 8004474:	4a12      	ldr	r2, [pc, #72]	@ (80044c0 <HAL_ADC_ConfigChannel+0x690>)
 8004476:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8004478:	f443 0380 	orr.w	r3, r3, #4194304	@ 0x400000
 800447c:	4619      	mov	r1, r3
 800447e:	4610      	mov	r0, r2
 8004480:	f7ff f861 	bl	8003546 <LL_ADC_SetCommonPathInternalCh>
 8004484:	e012      	b.n	80044ac <HAL_ADC_ConfigChannel+0x67c>
        /* enabled and other ADC of the common group are enabled, internal      */
        /* measurement paths cannot be enabled.                                 */
        else
        {
          /* Update ADC state machine to error */
          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 8004486:	687b      	ldr	r3, [r7, #4]
 8004488:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800448a:	f043 0220 	orr.w	r2, r3, #32
 800448e:	687b      	ldr	r3, [r7, #4]
 8004490:	655a      	str	r2, [r3, #84]	@ 0x54

          tmp_hal_status = HAL_ERROR;
 8004492:	2301      	movs	r3, #1
 8004494:	f887 307f 	strb.w	r3, [r7, #127]	@ 0x7f
 8004498:	e008      	b.n	80044ac <HAL_ADC_ConfigChannel+0x67c>
  /* channel could be done on neither of the channel configuration structure  */
  /* parameters.                                                              */
  else
  {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 800449a:	687b      	ldr	r3, [r7, #4]
 800449c:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800449e:	f043 0220 	orr.w	r2, r3, #32
 80044a2:	687b      	ldr	r3, [r7, #4]
 80044a4:	655a      	str	r2, [r3, #84]	@ 0x54

    tmp_hal_status = HAL_ERROR;
 80044a6:	2301      	movs	r3, #1
 80044a8:	f887 307f 	strb.w	r3, [r7, #127]	@ 0x7f
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 80044ac:	687b      	ldr	r3, [r7, #4]
 80044ae:	2200      	movs	r2, #0
 80044b0:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

  /* Return function status */
  return tmp_hal_status;
 80044b4:	f897 307f 	ldrb.w	r3, [r7, #127]	@ 0x7f
}
 80044b8:	4618      	mov	r0, r3
 80044ba:	3784      	adds	r7, #132	@ 0x84
 80044bc:	46bd      	mov	sp, r7
 80044be:	bd90      	pop	{r4, r7, pc}
 80044c0:	58026300 	.word	0x58026300
 80044c4:	40022000 	.word	0x40022000
 80044c8:	40022100 	.word	0x40022100
 80044cc:	58026000 	.word	0x58026000
 80044d0:	cb840000 	.word	0xcb840000
 80044d4:	40022300 	.word	0x40022300
 80044d8:	24000034 	.word	0x24000034
 80044dc:	053e2d63 	.word	0x053e2d63
 80044e0:	c7520000 	.word	0xc7520000
 80044e4:	cfb80000 	.word	0xcfb80000

080044e8 <ADC_Enable>:
  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
  * @param hadc ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
 80044e8:	b580      	push	{r7, lr}
 80044ea:	b084      	sub	sp, #16
 80044ec:	af00      	add	r7, sp, #0
 80044ee:	6078      	str	r0, [r7, #4]

  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
  /* enabling phase not yet completed: flag ADC ready not yet set).           */
  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
  /* causes: ADC clock not running, ...).                                     */
  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
 80044f0:	687b      	ldr	r3, [r7, #4]
 80044f2:	681b      	ldr	r3, [r3, #0]
 80044f4:	4618      	mov	r0, r3
 80044f6:	f7ff f9c1 	bl	800387c <LL_ADC_IsEnabled>
 80044fa:	4603      	mov	r3, r0
 80044fc:	2b00      	cmp	r3, #0
 80044fe:	d16e      	bne.n	80045de <ADC_Enable+0xf6>
  {
    /* Check if conditions to enable the ADC are fulfilled */
    if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
 8004500:	687b      	ldr	r3, [r7, #4]
 8004502:	681b      	ldr	r3, [r3, #0]
 8004504:	689a      	ldr	r2, [r3, #8]
 8004506:	4b38      	ldr	r3, [pc, #224]	@ (80045e8 <ADC_Enable+0x100>)
 8004508:	4013      	ands	r3, r2
 800450a:	2b00      	cmp	r3, #0
 800450c:	d00d      	beq.n	800452a <ADC_Enable+0x42>
    {
      /* Update ADC state machine to error */
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 800450e:	687b      	ldr	r3, [r7, #4]
 8004510:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8004512:	f043 0210 	orr.w	r2, r3, #16
 8004516:	687b      	ldr	r3, [r7, #4]
 8004518:	655a      	str	r2, [r3, #84]	@ 0x54

      /* Set ADC error code to ADC peripheral internal error */
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 800451a:	687b      	ldr	r3, [r7, #4]
 800451c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800451e:	f043 0201 	orr.w	r2, r3, #1
 8004522:	687b      	ldr	r3, [r7, #4]
 8004524:	659a      	str	r2, [r3, #88]	@ 0x58

      return HAL_ERROR;
 8004526:	2301      	movs	r3, #1
 8004528:	e05a      	b.n	80045e0 <ADC_Enable+0xf8>
    }

    /* Enable the ADC peripheral */
    LL_ADC_Enable(hadc->Instance);
 800452a:	687b      	ldr	r3, [r7, #4]
 800452c:	681b      	ldr	r3, [r3, #0]
 800452e:	4618      	mov	r0, r3
 8004530:	f7ff f97c 	bl	800382c <LL_ADC_Enable>

    /* Wait for ADC effectively enabled */
    tickstart = HAL_GetTick();
 8004534:	f7fe ffc6 	bl	80034c4 <HAL_GetTick>
 8004538:	60f8      	str	r0, [r7, #12]

    /* Poll for ADC ready flag raised except case of multimode enabled
       and ADC slave selected. */
    uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
 800453a:	687b      	ldr	r3, [r7, #4]
 800453c:	681b      	ldr	r3, [r3, #0]
 800453e:	4a2b      	ldr	r2, [pc, #172]	@ (80045ec <ADC_Enable+0x104>)
 8004540:	4293      	cmp	r3, r2
 8004542:	d004      	beq.n	800454e <ADC_Enable+0x66>
 8004544:	687b      	ldr	r3, [r7, #4]
 8004546:	681b      	ldr	r3, [r3, #0]
 8004548:	4a29      	ldr	r2, [pc, #164]	@ (80045f0 <ADC_Enable+0x108>)
 800454a:	4293      	cmp	r3, r2
 800454c:	d101      	bne.n	8004552 <ADC_Enable+0x6a>
 800454e:	4b29      	ldr	r3, [pc, #164]	@ (80045f4 <ADC_Enable+0x10c>)
 8004550:	e000      	b.n	8004554 <ADC_Enable+0x6c>
 8004552:	4b29      	ldr	r3, [pc, #164]	@ (80045f8 <ADC_Enable+0x110>)
 8004554:	4618      	mov	r0, r3
 8004556:	f7ff f90d 	bl	8003774 <LL_ADC_GetMultimode>
 800455a:	60b8      	str	r0, [r7, #8]
    if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
 800455c:	687b      	ldr	r3, [r7, #4]
 800455e:	681b      	ldr	r3, [r3, #0]
 8004560:	4a23      	ldr	r2, [pc, #140]	@ (80045f0 <ADC_Enable+0x108>)
 8004562:	4293      	cmp	r3, r2
 8004564:	d002      	beq.n	800456c <ADC_Enable+0x84>
 8004566:	687b      	ldr	r3, [r7, #4]
 8004568:	681b      	ldr	r3, [r3, #0]
 800456a:	e000      	b.n	800456e <ADC_Enable+0x86>
 800456c:	4b1f      	ldr	r3, [pc, #124]	@ (80045ec <ADC_Enable+0x104>)
 800456e:	687a      	ldr	r2, [r7, #4]
 8004570:	6812      	ldr	r2, [r2, #0]
 8004572:	4293      	cmp	r3, r2
 8004574:	d02c      	beq.n	80045d0 <ADC_Enable+0xe8>
        || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
 8004576:	68bb      	ldr	r3, [r7, #8]
 8004578:	2b00      	cmp	r3, #0
 800457a:	d130      	bne.n	80045de <ADC_Enable+0xf6>
       )
    {
      while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
 800457c:	e028      	b.n	80045d0 <ADC_Enable+0xe8>
            The workaround is to continue setting ADEN until ADRDY is becomes 1.
            Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
            4 ADC clock cycle duration */
        /* Note: Test of ADC enabled required due to hardware constraint to     */
        /*       not enable ADC if already enabled.                             */
        if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
 800457e:	687b      	ldr	r3, [r7, #4]
 8004580:	681b      	ldr	r3, [r3, #0]
 8004582:	4618      	mov	r0, r3
 8004584:	f7ff f97a 	bl	800387c <LL_ADC_IsEnabled>
 8004588:	4603      	mov	r3, r0
 800458a:	2b00      	cmp	r3, #0
 800458c:	d104      	bne.n	8004598 <ADC_Enable+0xb0>
        {
          LL_ADC_Enable(hadc->Instance);
 800458e:	687b      	ldr	r3, [r7, #4]
 8004590:	681b      	ldr	r3, [r3, #0]
 8004592:	4618      	mov	r0, r3
 8004594:	f7ff f94a 	bl	800382c <LL_ADC_Enable>
        }

        if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
 8004598:	f7fe ff94 	bl	80034c4 <HAL_GetTick>
 800459c:	4602      	mov	r2, r0
 800459e:	68fb      	ldr	r3, [r7, #12]
 80045a0:	1ad3      	subs	r3, r2, r3
 80045a2:	2b02      	cmp	r3, #2
 80045a4:	d914      	bls.n	80045d0 <ADC_Enable+0xe8>
        {
          /* New check to avoid false timeout detection in case of preemption */
          if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
 80045a6:	687b      	ldr	r3, [r7, #4]
 80045a8:	681b      	ldr	r3, [r3, #0]
 80045aa:	681b      	ldr	r3, [r3, #0]
 80045ac:	f003 0301 	and.w	r3, r3, #1
 80045b0:	2b01      	cmp	r3, #1
 80045b2:	d00d      	beq.n	80045d0 <ADC_Enable+0xe8>
          {
            /* Update ADC state machine to error */
            SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 80045b4:	687b      	ldr	r3, [r7, #4]
 80045b6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80045b8:	f043 0210 	orr.w	r2, r3, #16
 80045bc:	687b      	ldr	r3, [r7, #4]
 80045be:	655a      	str	r2, [r3, #84]	@ 0x54

            /* Set ADC error code to ADC peripheral internal error */
            SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80045c0:	687b      	ldr	r3, [r7, #4]
 80045c2:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80045c4:	f043 0201 	orr.w	r2, r3, #1
 80045c8:	687b      	ldr	r3, [r7, #4]
 80045ca:	659a      	str	r2, [r3, #88]	@ 0x58

            return HAL_ERROR;
 80045cc:	2301      	movs	r3, #1
 80045ce:	e007      	b.n	80045e0 <ADC_Enable+0xf8>
      while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
 80045d0:	687b      	ldr	r3, [r7, #4]
 80045d2:	681b      	ldr	r3, [r3, #0]
 80045d4:	681b      	ldr	r3, [r3, #0]
 80045d6:	f003 0301 	and.w	r3, r3, #1
 80045da:	2b01      	cmp	r3, #1
 80045dc:	d1cf      	bne.n	800457e <ADC_Enable+0x96>
      }
    }
  }

  /* Return HAL status */
  return HAL_OK;
 80045de:	2300      	movs	r3, #0
}
 80045e0:	4618      	mov	r0, r3
 80045e2:	3710      	adds	r7, #16
 80045e4:	46bd      	mov	sp, r7
 80045e6:	bd80      	pop	{r7, pc}
 80045e8:	8000003f 	.word	0x8000003f
 80045ec:	40022000 	.word	0x40022000
 80045f0:	40022100 	.word	0x40022100
 80045f4:	40022300 	.word	0x40022300
 80045f8:	58026300 	.word	0x58026300

080045fc <ADC_Disable>:
  *         stopped.
  * @param hadc ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
{
 80045fc:	b580      	push	{r7, lr}
 80045fe:	b084      	sub	sp, #16
 8004600:	af00      	add	r7, sp, #0
 8004602:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
 8004604:	687b      	ldr	r3, [r7, #4]
 8004606:	681b      	ldr	r3, [r3, #0]
 8004608:	4618      	mov	r0, r3
 800460a:	f7ff f94a 	bl	80038a2 <LL_ADC_IsDisableOngoing>
 800460e:	60f8      	str	r0, [r7, #12]

  /* Verification if ADC is not already disabled:                             */
  /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
  /*       disabled.                                                          */
  if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
 8004610:	687b      	ldr	r3, [r7, #4]
 8004612:	681b      	ldr	r3, [r3, #0]
 8004614:	4618      	mov	r0, r3
 8004616:	f7ff f931 	bl	800387c <LL_ADC_IsEnabled>
 800461a:	4603      	mov	r3, r0
 800461c:	2b00      	cmp	r3, #0
 800461e:	d047      	beq.n	80046b0 <ADC_Disable+0xb4>
      && (tmp_adc_is_disable_on_going == 0UL)
 8004620:	68fb      	ldr	r3, [r7, #12]
 8004622:	2b00      	cmp	r3, #0
 8004624:	d144      	bne.n	80046b0 <ADC_Disable+0xb4>
     )
  {
    /* Check if conditions to disable the ADC are fulfilled */
    if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
 8004626:	687b      	ldr	r3, [r7, #4]
 8004628:	681b      	ldr	r3, [r3, #0]
 800462a:	689b      	ldr	r3, [r3, #8]
 800462c:	f003 030d 	and.w	r3, r3, #13
 8004630:	2b01      	cmp	r3, #1
 8004632:	d10c      	bne.n	800464e <ADC_Disable+0x52>
    {
      /* Disable the ADC peripheral */
      LL_ADC_Disable(hadc->Instance);
 8004634:	687b      	ldr	r3, [r7, #4]
 8004636:	681b      	ldr	r3, [r3, #0]
 8004638:	4618      	mov	r0, r3
 800463a:	f7ff f90b 	bl	8003854 <LL_ADC_Disable>
      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
 800463e:	687b      	ldr	r3, [r7, #4]
 8004640:	681b      	ldr	r3, [r3, #0]
 8004642:	2203      	movs	r2, #3
 8004644:	601a      	str	r2, [r3, #0]
      return HAL_ERROR;
    }

    /* Wait for ADC effectively disabled */
    /* Get tick count */
    tickstart = HAL_GetTick();
 8004646:	f7fe ff3d 	bl	80034c4 <HAL_GetTick>
 800464a:	60b8      	str	r0, [r7, #8]

    while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
 800464c:	e029      	b.n	80046a2 <ADC_Disable+0xa6>
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 800464e:	687b      	ldr	r3, [r7, #4]
 8004650:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8004652:	f043 0210 	orr.w	r2, r3, #16
 8004656:	687b      	ldr	r3, [r7, #4]
 8004658:	655a      	str	r2, [r3, #84]	@ 0x54
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 800465a:	687b      	ldr	r3, [r7, #4]
 800465c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800465e:	f043 0201 	orr.w	r2, r3, #1
 8004662:	687b      	ldr	r3, [r7, #4]
 8004664:	659a      	str	r2, [r3, #88]	@ 0x58
      return HAL_ERROR;
 8004666:	2301      	movs	r3, #1
 8004668:	e023      	b.n	80046b2 <ADC_Disable+0xb6>
    {
      if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
 800466a:	f7fe ff2b 	bl	80034c4 <HAL_GetTick>
 800466e:	4602      	mov	r2, r0
 8004670:	68bb      	ldr	r3, [r7, #8]
 8004672:	1ad3      	subs	r3, r2, r3
 8004674:	2b02      	cmp	r3, #2
 8004676:	d914      	bls.n	80046a2 <ADC_Disable+0xa6>
      {
        /* New check to avoid false timeout detection in case of preemption */
        if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
 8004678:	687b      	ldr	r3, [r7, #4]
 800467a:	681b      	ldr	r3, [r3, #0]
 800467c:	689b      	ldr	r3, [r3, #8]
 800467e:	f003 0301 	and.w	r3, r3, #1
 8004682:	2b00      	cmp	r3, #0
 8004684:	d00d      	beq.n	80046a2 <ADC_Disable+0xa6>
        {
          /* Update ADC state machine to error */
          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8004686:	687b      	ldr	r3, [r7, #4]
 8004688:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800468a:	f043 0210 	orr.w	r2, r3, #16
 800468e:	687b      	ldr	r3, [r7, #4]
 8004690:	655a      	str	r2, [r3, #84]	@ 0x54

          /* Set ADC error code to ADC peripheral internal error */
          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8004692:	687b      	ldr	r3, [r7, #4]
 8004694:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8004696:	f043 0201 	orr.w	r2, r3, #1
 800469a:	687b      	ldr	r3, [r7, #4]
 800469c:	659a      	str	r2, [r3, #88]	@ 0x58

          return HAL_ERROR;
 800469e:	2301      	movs	r3, #1
 80046a0:	e007      	b.n	80046b2 <ADC_Disable+0xb6>
    while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
 80046a2:	687b      	ldr	r3, [r7, #4]
 80046a4:	681b      	ldr	r3, [r3, #0]
 80046a6:	689b      	ldr	r3, [r3, #8]
 80046a8:	f003 0301 	and.w	r3, r3, #1
 80046ac:	2b00      	cmp	r3, #0
 80046ae:	d1dc      	bne.n	800466a <ADC_Disable+0x6e>
      }
    }
  }

  /* Return HAL status */
  return HAL_OK;
 80046b0:	2300      	movs	r3, #0
}
 80046b2:	4618      	mov	r0, r3
 80046b4:	3710      	adds	r7, #16
 80046b6:	46bd      	mov	sp, r7
 80046b8:	bd80      	pop	{r7, pc}

080046ba <ADC_DMAConvCplt>:
  * @brief  DMA transfer complete callback.
  * @param hdma pointer to DMA handle.
  * @retval None
  */
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
 80046ba:	b580      	push	{r7, lr}
 80046bc:	b084      	sub	sp, #16
 80046be:	af00      	add	r7, sp, #0
 80046c0:	6078      	str	r0, [r7, #4]
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 80046c2:	687b      	ldr	r3, [r7, #4]
 80046c4:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 80046c6:	60fb      	str	r3, [r7, #12]

  /* Update state machine on conversion status if not in error state */
  if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
 80046c8:	68fb      	ldr	r3, [r7, #12]
 80046ca:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80046cc:	f003 0350 	and.w	r3, r3, #80	@ 0x50
 80046d0:	2b00      	cmp	r3, #0
 80046d2:	d14b      	bne.n	800476c <ADC_DMAConvCplt+0xb2>
  {
    /* Set ADC state */
    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
 80046d4:	68fb      	ldr	r3, [r7, #12]
 80046d6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80046d8:	f443 7200 	orr.w	r2, r3, #512	@ 0x200
 80046dc:	68fb      	ldr	r3, [r7, #12]
 80046de:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Determine whether any further conversion upcoming on group regular     */
    /* by external trigger, continuous mode or scan sequence on going         */
    /* to disable interruption.                                               */
    /* Is it the end of the regular sequence ? */
    if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
 80046e0:	68fb      	ldr	r3, [r7, #12]
 80046e2:	681b      	ldr	r3, [r3, #0]
 80046e4:	681b      	ldr	r3, [r3, #0]
 80046e6:	f003 0308 	and.w	r3, r3, #8
 80046ea:	2b00      	cmp	r3, #0
 80046ec:	d021      	beq.n	8004732 <ADC_DMAConvCplt+0x78>
    {
      /* Are conversions software-triggered ? */
      if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
 80046ee:	68fb      	ldr	r3, [r7, #12]
 80046f0:	681b      	ldr	r3, [r3, #0]
 80046f2:	4618      	mov	r0, r3
 80046f4:	f7fe ff9c 	bl	8003630 <LL_ADC_REG_IsTriggerSourceSWStart>
 80046f8:	4603      	mov	r3, r0
 80046fa:	2b00      	cmp	r3, #0
 80046fc:	d032      	beq.n	8004764 <ADC_DMAConvCplt+0xaa>
      {
        /* Is CONT bit set ? */
        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
 80046fe:	68fb      	ldr	r3, [r7, #12]
 8004700:	681b      	ldr	r3, [r3, #0]
 8004702:	68db      	ldr	r3, [r3, #12]
 8004704:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 8004708:	2b00      	cmp	r3, #0
 800470a:	d12b      	bne.n	8004764 <ADC_DMAConvCplt+0xaa>
        {
          /* CONT bit is not set, no more conversions expected */
          CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
 800470c:	68fb      	ldr	r3, [r7, #12]
 800470e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8004710:	f423 7280 	bic.w	r2, r3, #256	@ 0x100
 8004714:	68fb      	ldr	r3, [r7, #12]
 8004716:	655a      	str	r2, [r3, #84]	@ 0x54
          if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
 8004718:	68fb      	ldr	r3, [r7, #12]
 800471a:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800471c:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
 8004720:	2b00      	cmp	r3, #0
 8004722:	d11f      	bne.n	8004764 <ADC_DMAConvCplt+0xaa>
          {
            SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 8004724:	68fb      	ldr	r3, [r7, #12]
 8004726:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8004728:	f043 0201 	orr.w	r2, r3, #1
 800472c:	68fb      	ldr	r3, [r7, #12]
 800472e:	655a      	str	r2, [r3, #84]	@ 0x54
 8004730:	e018      	b.n	8004764 <ADC_DMAConvCplt+0xaa>
    }
    else
    {
      /* DMA End of Transfer interrupt was triggered but conversions sequence
         is not over. If DMACFG is set to 0, conversions are stopped. */
      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL)
 8004732:	68fb      	ldr	r3, [r7, #12]
 8004734:	681b      	ldr	r3, [r3, #0]
 8004736:	68db      	ldr	r3, [r3, #12]
 8004738:	f003 0303 	and.w	r3, r3, #3
 800473c:	2b00      	cmp	r3, #0
 800473e:	d111      	bne.n	8004764 <ADC_DMAConvCplt+0xaa>
      {
        /* DMACFG bit is not set, conversions are stopped. */
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
 8004740:	68fb      	ldr	r3, [r7, #12]
 8004742:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8004744:	f423 7280 	bic.w	r2, r3, #256	@ 0x100
 8004748:	68fb      	ldr	r3, [r7, #12]
 800474a:	655a      	str	r2, [r3, #84]	@ 0x54
        if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
 800474c:	68fb      	ldr	r3, [r7, #12]
 800474e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8004750:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
 8004754:	2b00      	cmp	r3, #0
 8004756:	d105      	bne.n	8004764 <ADC_DMAConvCplt+0xaa>
        {
          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 8004758:	68fb      	ldr	r3, [r7, #12]
 800475a:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800475c:	f043 0201 	orr.w	r2, r3, #1
 8004760:	68fb      	ldr	r3, [r7, #12]
 8004762:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
    hadc->ConvCpltCallback(hadc);
#else
    HAL_ADC_ConvCpltCallback(hadc);
 8004764:	68f8      	ldr	r0, [r7, #12]
 8004766:	f7fc fcf3 	bl	8001150 <HAL_ADC_ConvCpltCallback>
    {
      /* Call ADC DMA error callback */
      hadc->DMA_Handle->XferErrorCallback(hdma);
    }
  }
}
 800476a:	e00e      	b.n	800478a <ADC_DMAConvCplt+0xd0>
    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
 800476c:	68fb      	ldr	r3, [r7, #12]
 800476e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8004770:	f003 0310 	and.w	r3, r3, #16
 8004774:	2b00      	cmp	r3, #0
 8004776:	d003      	beq.n	8004780 <ADC_DMAConvCplt+0xc6>
      HAL_ADC_ErrorCallback(hadc);
 8004778:	68f8      	ldr	r0, [r7, #12]
 800477a:	f7ff fb4f 	bl	8003e1c <HAL_ADC_ErrorCallback>
}
 800477e:	e004      	b.n	800478a <ADC_DMAConvCplt+0xd0>
      hadc->DMA_Handle->XferErrorCallback(hdma);
 8004780:	68fb      	ldr	r3, [r7, #12]
 8004782:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8004784:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8004786:	6878      	ldr	r0, [r7, #4]
 8004788:	4798      	blx	r3
}
 800478a:	bf00      	nop
 800478c:	3710      	adds	r7, #16
 800478e:	46bd      	mov	sp, r7
 8004790:	bd80      	pop	{r7, pc}

08004792 <ADC_DMAHalfConvCplt>:
  * @brief  DMA half transfer complete callback.
  * @param hdma pointer to DMA handle.
  * @retval None
  */
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
 8004792:	b580      	push	{r7, lr}
 8004794:	b084      	sub	sp, #16
 8004796:	af00      	add	r7, sp, #0
 8004798:	6078      	str	r0, [r7, #4]
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 800479a:	687b      	ldr	r3, [r7, #4]
 800479c:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800479e:	60fb      	str	r3, [r7, #12]

  /* Half conversion callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  hadc->ConvHalfCpltCallback(hadc);
#else
  HAL_ADC_ConvHalfCpltCallback(hadc);
 80047a0:	68f8      	ldr	r0, [r7, #12]
 80047a2:	f7ff fb31 	bl	8003e08 <HAL_ADC_ConvHalfCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
 80047a6:	bf00      	nop
 80047a8:	3710      	adds	r7, #16
 80047aa:	46bd      	mov	sp, r7
 80047ac:	bd80      	pop	{r7, pc}

080047ae <ADC_DMAError>:
  * @brief  DMA error callback.
  * @param hdma pointer to DMA handle.
  * @retval None
  */
void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
 80047ae:	b580      	push	{r7, lr}
 80047b0:	b084      	sub	sp, #16
 80047b2:	af00      	add	r7, sp, #0
 80047b4:	6078      	str	r0, [r7, #4]
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 80047b6:	687b      	ldr	r3, [r7, #4]
 80047b8:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 80047ba:	60fb      	str	r3, [r7, #12]

  /* Set ADC state */
  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
 80047bc:	68fb      	ldr	r3, [r7, #12]
 80047be:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80047c0:	f043 0240 	orr.w	r2, r3, #64	@ 0x40
 80047c4:	68fb      	ldr	r3, [r7, #12]
 80047c6:	655a      	str	r2, [r3, #84]	@ 0x54

  /* Set ADC error code to DMA error */
  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
 80047c8:	68fb      	ldr	r3, [r7, #12]
 80047ca:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80047cc:	f043 0204 	orr.w	r2, r3, #4
 80047d0:	68fb      	ldr	r3, [r7, #12]
 80047d2:	659a      	str	r2, [r3, #88]	@ 0x58

  /* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  hadc->ErrorCallback(hadc);
#else
  HAL_ADC_ErrorCallback(hadc);
 80047d4:	68f8      	ldr	r0, [r7, #12]
 80047d6:	f7ff fb21 	bl	8003e1c <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
 80047da:	bf00      	nop
 80047dc:	3710      	adds	r7, #16
 80047de:	46bd      	mov	sp, r7
 80047e0:	bd80      	pop	{r7, pc}
	...

080047e4 <ADC_ConfigureBoostMode>:
  *         stopped.
  * @param  hadc ADC handle
  * @retval None.
  */
void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc)
{
 80047e4:	b580      	push	{r7, lr}
 80047e6:	b084      	sub	sp, #16
 80047e8:	af00      	add	r7, sp, #0
 80047ea:	6078      	str	r0, [r7, #4]
  uint32_t freq;
  if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
 80047ec:	687b      	ldr	r3, [r7, #4]
 80047ee:	681b      	ldr	r3, [r3, #0]
 80047f0:	4a7a      	ldr	r2, [pc, #488]	@ (80049dc <ADC_ConfigureBoostMode+0x1f8>)
 80047f2:	4293      	cmp	r3, r2
 80047f4:	d004      	beq.n	8004800 <ADC_ConfigureBoostMode+0x1c>
 80047f6:	687b      	ldr	r3, [r7, #4]
 80047f8:	681b      	ldr	r3, [r3, #0]
 80047fa:	4a79      	ldr	r2, [pc, #484]	@ (80049e0 <ADC_ConfigureBoostMode+0x1fc>)
 80047fc:	4293      	cmp	r3, r2
 80047fe:	d109      	bne.n	8004814 <ADC_ConfigureBoostMode+0x30>
 8004800:	4b78      	ldr	r3, [pc, #480]	@ (80049e4 <ADC_ConfigureBoostMode+0x200>)
 8004802:	689b      	ldr	r3, [r3, #8]
 8004804:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 8004808:	2b00      	cmp	r3, #0
 800480a:	bf14      	ite	ne
 800480c:	2301      	movne	r3, #1
 800480e:	2300      	moveq	r3, #0
 8004810:	b2db      	uxtb	r3, r3
 8004812:	e008      	b.n	8004826 <ADC_ConfigureBoostMode+0x42>
 8004814:	4b74      	ldr	r3, [pc, #464]	@ (80049e8 <ADC_ConfigureBoostMode+0x204>)
 8004816:	689b      	ldr	r3, [r3, #8]
 8004818:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 800481c:	2b00      	cmp	r3, #0
 800481e:	bf14      	ite	ne
 8004820:	2301      	movne	r3, #1
 8004822:	2300      	moveq	r3, #0
 8004824:	b2db      	uxtb	r3, r3
 8004826:	2b00      	cmp	r3, #0
 8004828:	d01c      	beq.n	8004864 <ADC_ConfigureBoostMode+0x80>
  {
    freq = HAL_RCC_GetHCLKFreq();
 800482a:	f004 fdc5 	bl	80093b8 <HAL_RCC_GetHCLKFreq>
 800482e:	60f8      	str	r0, [r7, #12]
    switch (hadc->Init.ClockPrescaler)
 8004830:	687b      	ldr	r3, [r7, #4]
 8004832:	685b      	ldr	r3, [r3, #4]
 8004834:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
 8004838:	d010      	beq.n	800485c <ADC_ConfigureBoostMode+0x78>
 800483a:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
 800483e:	d873      	bhi.n	8004928 <ADC_ConfigureBoostMode+0x144>
 8004840:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 8004844:	d002      	beq.n	800484c <ADC_ConfigureBoostMode+0x68>
 8004846:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800484a:	d16d      	bne.n	8004928 <ADC_ConfigureBoostMode+0x144>
    {
      case ADC_CLOCK_SYNC_PCLK_DIV1:
      case ADC_CLOCK_SYNC_PCLK_DIV2:
        freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos);
 800484c:	687b      	ldr	r3, [r7, #4]
 800484e:	685b      	ldr	r3, [r3, #4]
 8004850:	0c1b      	lsrs	r3, r3, #16
 8004852:	68fa      	ldr	r2, [r7, #12]
 8004854:	fbb2 f3f3 	udiv	r3, r2, r3
 8004858:	60fb      	str	r3, [r7, #12]
        break;
 800485a:	e068      	b.n	800492e <ADC_ConfigureBoostMode+0x14a>
      case ADC_CLOCK_SYNC_PCLK_DIV4:
        freq /= 4UL;
 800485c:	68fb      	ldr	r3, [r7, #12]
 800485e:	089b      	lsrs	r3, r3, #2
 8004860:	60fb      	str	r3, [r7, #12]
        break;
 8004862:	e064      	b.n	800492e <ADC_ConfigureBoostMode+0x14a>
        break;
    }
  }
  else
  {
    freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
 8004864:	f44f 2000 	mov.w	r0, #524288	@ 0x80000
 8004868:	f04f 0100 	mov.w	r1, #0
 800486c:	f006 f830 	bl	800a8d0 <HAL_RCCEx_GetPeriphCLKFreq>
 8004870:	60f8      	str	r0, [r7, #12]
    switch (hadc->Init.ClockPrescaler)
 8004872:	687b      	ldr	r3, [r7, #4]
 8004874:	685b      	ldr	r3, [r3, #4]
 8004876:	f5b3 1f30 	cmp.w	r3, #2883584	@ 0x2c0000
 800487a:	d051      	beq.n	8004920 <ADC_ConfigureBoostMode+0x13c>
 800487c:	f5b3 1f30 	cmp.w	r3, #2883584	@ 0x2c0000
 8004880:	d854      	bhi.n	800492c <ADC_ConfigureBoostMode+0x148>
 8004882:	f5b3 1f20 	cmp.w	r3, #2621440	@ 0x280000
 8004886:	d047      	beq.n	8004918 <ADC_ConfigureBoostMode+0x134>
 8004888:	f5b3 1f20 	cmp.w	r3, #2621440	@ 0x280000
 800488c:	d84e      	bhi.n	800492c <ADC_ConfigureBoostMode+0x148>
 800488e:	f5b3 1f10 	cmp.w	r3, #2359296	@ 0x240000
 8004892:	d03d      	beq.n	8004910 <ADC_ConfigureBoostMode+0x12c>
 8004894:	f5b3 1f10 	cmp.w	r3, #2359296	@ 0x240000
 8004898:	d848      	bhi.n	800492c <ADC_ConfigureBoostMode+0x148>
 800489a:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 800489e:	d033      	beq.n	8004908 <ADC_ConfigureBoostMode+0x124>
 80048a0:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 80048a4:	d842      	bhi.n	800492c <ADC_ConfigureBoostMode+0x148>
 80048a6:	f5b3 1fe0 	cmp.w	r3, #1835008	@ 0x1c0000
 80048aa:	d029      	beq.n	8004900 <ADC_ConfigureBoostMode+0x11c>
 80048ac:	f5b3 1fe0 	cmp.w	r3, #1835008	@ 0x1c0000
 80048b0:	d83c      	bhi.n	800492c <ADC_ConfigureBoostMode+0x148>
 80048b2:	f5b3 1fc0 	cmp.w	r3, #1572864	@ 0x180000
 80048b6:	d01a      	beq.n	80048ee <ADC_ConfigureBoostMode+0x10a>
 80048b8:	f5b3 1fc0 	cmp.w	r3, #1572864	@ 0x180000
 80048bc:	d836      	bhi.n	800492c <ADC_ConfigureBoostMode+0x148>
 80048be:	f5b3 1fa0 	cmp.w	r3, #1310720	@ 0x140000
 80048c2:	d014      	beq.n	80048ee <ADC_ConfigureBoostMode+0x10a>
 80048c4:	f5b3 1fa0 	cmp.w	r3, #1310720	@ 0x140000
 80048c8:	d830      	bhi.n	800492c <ADC_ConfigureBoostMode+0x148>
 80048ca:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 80048ce:	d00e      	beq.n	80048ee <ADC_ConfigureBoostMode+0x10a>
 80048d0:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 80048d4:	d82a      	bhi.n	800492c <ADC_ConfigureBoostMode+0x148>
 80048d6:	f5b3 2f40 	cmp.w	r3, #786432	@ 0xc0000
 80048da:	d008      	beq.n	80048ee <ADC_ConfigureBoostMode+0x10a>
 80048dc:	f5b3 2f40 	cmp.w	r3, #786432	@ 0xc0000
 80048e0:	d824      	bhi.n	800492c <ADC_ConfigureBoostMode+0x148>
 80048e2:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
 80048e6:	d002      	beq.n	80048ee <ADC_ConfigureBoostMode+0x10a>
 80048e8:	f5b3 2f00 	cmp.w	r3, #524288	@ 0x80000
 80048ec:	d11e      	bne.n	800492c <ADC_ConfigureBoostMode+0x148>
      case ADC_CLOCK_ASYNC_DIV4:
      case ADC_CLOCK_ASYNC_DIV6:
      case ADC_CLOCK_ASYNC_DIV8:
      case ADC_CLOCK_ASYNC_DIV10:
      case ADC_CLOCK_ASYNC_DIV12:
        freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL);
 80048ee:	687b      	ldr	r3, [r7, #4]
 80048f0:	685b      	ldr	r3, [r3, #4]
 80048f2:	0c9b      	lsrs	r3, r3, #18
 80048f4:	005b      	lsls	r3, r3, #1
 80048f6:	68fa      	ldr	r2, [r7, #12]
 80048f8:	fbb2 f3f3 	udiv	r3, r2, r3
 80048fc:	60fb      	str	r3, [r7, #12]
        break;
 80048fe:	e016      	b.n	800492e <ADC_ConfigureBoostMode+0x14a>
      case ADC_CLOCK_ASYNC_DIV16:
        freq /= 16UL;
 8004900:	68fb      	ldr	r3, [r7, #12]
 8004902:	091b      	lsrs	r3, r3, #4
 8004904:	60fb      	str	r3, [r7, #12]
        break;
 8004906:	e012      	b.n	800492e <ADC_ConfigureBoostMode+0x14a>
      case ADC_CLOCK_ASYNC_DIV32:
        freq /= 32UL;
 8004908:	68fb      	ldr	r3, [r7, #12]
 800490a:	095b      	lsrs	r3, r3, #5
 800490c:	60fb      	str	r3, [r7, #12]
        break;
 800490e:	e00e      	b.n	800492e <ADC_ConfigureBoostMode+0x14a>
      case ADC_CLOCK_ASYNC_DIV64:
        freq /= 64UL;
 8004910:	68fb      	ldr	r3, [r7, #12]
 8004912:	099b      	lsrs	r3, r3, #6
 8004914:	60fb      	str	r3, [r7, #12]
        break;
 8004916:	e00a      	b.n	800492e <ADC_ConfigureBoostMode+0x14a>
      case ADC_CLOCK_ASYNC_DIV128:
        freq /= 128UL;
 8004918:	68fb      	ldr	r3, [r7, #12]
 800491a:	09db      	lsrs	r3, r3, #7
 800491c:	60fb      	str	r3, [r7, #12]
        break;
 800491e:	e006      	b.n	800492e <ADC_ConfigureBoostMode+0x14a>
      case ADC_CLOCK_ASYNC_DIV256:
        freq /= 256UL;
 8004920:	68fb      	ldr	r3, [r7, #12]
 8004922:	0a1b      	lsrs	r3, r3, #8
 8004924:	60fb      	str	r3, [r7, #12]
        break;
 8004926:	e002      	b.n	800492e <ADC_ConfigureBoostMode+0x14a>
        break;
 8004928:	bf00      	nop
 800492a:	e000      	b.n	800492e <ADC_ConfigureBoostMode+0x14a>
      default:
        break;
 800492c:	bf00      	nop
  else /* if(freq > 25000000UL) */
  {
    MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
  }
#else
  if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
 800492e:	f7fe fdd5 	bl	80034dc <HAL_GetREVID>
 8004932:	4603      	mov	r3, r0
 8004934:	f241 0203 	movw	r2, #4099	@ 0x1003
 8004938:	4293      	cmp	r3, r2
 800493a:	d815      	bhi.n	8004968 <ADC_ConfigureBoostMode+0x184>
  {
    if (freq > 20000000UL)
 800493c:	68fb      	ldr	r3, [r7, #12]
 800493e:	4a2b      	ldr	r2, [pc, #172]	@ (80049ec <ADC_ConfigureBoostMode+0x208>)
 8004940:	4293      	cmp	r3, r2
 8004942:	d908      	bls.n	8004956 <ADC_ConfigureBoostMode+0x172>
    {
      SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
 8004944:	687b      	ldr	r3, [r7, #4]
 8004946:	681b      	ldr	r3, [r3, #0]
 8004948:	689a      	ldr	r2, [r3, #8]
 800494a:	687b      	ldr	r3, [r7, #4]
 800494c:	681b      	ldr	r3, [r3, #0]
 800494e:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
 8004952:	609a      	str	r2, [r3, #8]
    {
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
    }
  }
#endif /* ADC_VER_V5_3 */
}
 8004954:	e03e      	b.n	80049d4 <ADC_ConfigureBoostMode+0x1f0>
      CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
 8004956:	687b      	ldr	r3, [r7, #4]
 8004958:	681b      	ldr	r3, [r3, #0]
 800495a:	689a      	ldr	r2, [r3, #8]
 800495c:	687b      	ldr	r3, [r7, #4]
 800495e:	681b      	ldr	r3, [r3, #0]
 8004960:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
 8004964:	609a      	str	r2, [r3, #8]
}
 8004966:	e035      	b.n	80049d4 <ADC_ConfigureBoostMode+0x1f0>
    freq /= 2U; /* divider by 2 for Rev.V */
 8004968:	68fb      	ldr	r3, [r7, #12]
 800496a:	085b      	lsrs	r3, r3, #1
 800496c:	60fb      	str	r3, [r7, #12]
    if (freq <= 6250000UL)
 800496e:	68fb      	ldr	r3, [r7, #12]
 8004970:	4a1f      	ldr	r2, [pc, #124]	@ (80049f0 <ADC_ConfigureBoostMode+0x20c>)
 8004972:	4293      	cmp	r3, r2
 8004974:	d808      	bhi.n	8004988 <ADC_ConfigureBoostMode+0x1a4>
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
 8004976:	687b      	ldr	r3, [r7, #4]
 8004978:	681b      	ldr	r3, [r3, #0]
 800497a:	689a      	ldr	r2, [r3, #8]
 800497c:	687b      	ldr	r3, [r7, #4]
 800497e:	681b      	ldr	r3, [r3, #0]
 8004980:	f422 7240 	bic.w	r2, r2, #768	@ 0x300
 8004984:	609a      	str	r2, [r3, #8]
}
 8004986:	e025      	b.n	80049d4 <ADC_ConfigureBoostMode+0x1f0>
    else if (freq <= 12500000UL)
 8004988:	68fb      	ldr	r3, [r7, #12]
 800498a:	4a1a      	ldr	r2, [pc, #104]	@ (80049f4 <ADC_ConfigureBoostMode+0x210>)
 800498c:	4293      	cmp	r3, r2
 800498e:	d80a      	bhi.n	80049a6 <ADC_ConfigureBoostMode+0x1c2>
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
 8004990:	687b      	ldr	r3, [r7, #4]
 8004992:	681b      	ldr	r3, [r3, #0]
 8004994:	689b      	ldr	r3, [r3, #8]
 8004996:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
 800499a:	687b      	ldr	r3, [r7, #4]
 800499c:	681b      	ldr	r3, [r3, #0]
 800499e:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
 80049a2:	609a      	str	r2, [r3, #8]
}
 80049a4:	e016      	b.n	80049d4 <ADC_ConfigureBoostMode+0x1f0>
    else if (freq <= 25000000UL)
 80049a6:	68fb      	ldr	r3, [r7, #12]
 80049a8:	4a13      	ldr	r2, [pc, #76]	@ (80049f8 <ADC_ConfigureBoostMode+0x214>)
 80049aa:	4293      	cmp	r3, r2
 80049ac:	d80a      	bhi.n	80049c4 <ADC_ConfigureBoostMode+0x1e0>
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
 80049ae:	687b      	ldr	r3, [r7, #4]
 80049b0:	681b      	ldr	r3, [r3, #0]
 80049b2:	689b      	ldr	r3, [r3, #8]
 80049b4:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
 80049b8:	687b      	ldr	r3, [r7, #4]
 80049ba:	681b      	ldr	r3, [r3, #0]
 80049bc:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
 80049c0:	609a      	str	r2, [r3, #8]
}
 80049c2:	e007      	b.n	80049d4 <ADC_ConfigureBoostMode+0x1f0>
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
 80049c4:	687b      	ldr	r3, [r7, #4]
 80049c6:	681b      	ldr	r3, [r3, #0]
 80049c8:	689a      	ldr	r2, [r3, #8]
 80049ca:	687b      	ldr	r3, [r7, #4]
 80049cc:	681b      	ldr	r3, [r3, #0]
 80049ce:	f442 7240 	orr.w	r2, r2, #768	@ 0x300
 80049d2:	609a      	str	r2, [r3, #8]
}
 80049d4:	bf00      	nop
 80049d6:	3710      	adds	r7, #16
 80049d8:	46bd      	mov	sp, r7
 80049da:	bd80      	pop	{r7, pc}
 80049dc:	40022000 	.word	0x40022000
 80049e0:	40022100 	.word	0x40022100
 80049e4:	40022300 	.word	0x40022300
 80049e8:	58026300 	.word	0x58026300
 80049ec:	01312d00 	.word	0x01312d00
 80049f0:	005f5e10 	.word	0x005f5e10
 80049f4:	00bebc20 	.word	0x00bebc20
 80049f8:	017d7840 	.word	0x017d7840

080049fc <LL_ADC_IsEnabled>:
{
 80049fc:	b480      	push	{r7}
 80049fe:	b083      	sub	sp, #12
 8004a00:	af00      	add	r7, sp, #0
 8004a02:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
 8004a04:	687b      	ldr	r3, [r7, #4]
 8004a06:	689b      	ldr	r3, [r3, #8]
 8004a08:	f003 0301 	and.w	r3, r3, #1
 8004a0c:	2b01      	cmp	r3, #1
 8004a0e:	d101      	bne.n	8004a14 <LL_ADC_IsEnabled+0x18>
 8004a10:	2301      	movs	r3, #1
 8004a12:	e000      	b.n	8004a16 <LL_ADC_IsEnabled+0x1a>
 8004a14:	2300      	movs	r3, #0
}
 8004a16:	4618      	mov	r0, r3
 8004a18:	370c      	adds	r7, #12
 8004a1a:	46bd      	mov	sp, r7
 8004a1c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004a20:	4770      	bx	lr
	...

08004a24 <LL_ADC_StartCalibration>:
{
 8004a24:	b480      	push	{r7}
 8004a26:	b085      	sub	sp, #20
 8004a28:	af00      	add	r7, sp, #0
 8004a2a:	60f8      	str	r0, [r7, #12]
 8004a2c:	60b9      	str	r1, [r7, #8]
 8004a2e:	607a      	str	r2, [r7, #4]
  MODIFY_REG(ADCx->CR,
 8004a30:	68fb      	ldr	r3, [r7, #12]
 8004a32:	689a      	ldr	r2, [r3, #8]
 8004a34:	4b09      	ldr	r3, [pc, #36]	@ (8004a5c <LL_ADC_StartCalibration+0x38>)
 8004a36:	4013      	ands	r3, r2
 8004a38:	68ba      	ldr	r2, [r7, #8]
 8004a3a:	f402 3180 	and.w	r1, r2, #65536	@ 0x10000
 8004a3e:	687a      	ldr	r2, [r7, #4]
 8004a40:	f002 4280 	and.w	r2, r2, #1073741824	@ 0x40000000
 8004a44:	430a      	orrs	r2, r1
 8004a46:	4313      	orrs	r3, r2
 8004a48:	f043 4200 	orr.w	r2, r3, #2147483648	@ 0x80000000
 8004a4c:	68fb      	ldr	r3, [r7, #12]
 8004a4e:	609a      	str	r2, [r3, #8]
}
 8004a50:	bf00      	nop
 8004a52:	3714      	adds	r7, #20
 8004a54:	46bd      	mov	sp, r7
 8004a56:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004a5a:	4770      	bx	lr
 8004a5c:	3ffeffc0 	.word	0x3ffeffc0

08004a60 <LL_ADC_IsCalibrationOnGoing>:
{
 8004a60:	b480      	push	{r7}
 8004a62:	b083      	sub	sp, #12
 8004a64:	af00      	add	r7, sp, #0
 8004a66:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
 8004a68:	687b      	ldr	r3, [r7, #4]
 8004a6a:	689b      	ldr	r3, [r3, #8]
 8004a6c:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
 8004a70:	f1b3 4f00 	cmp.w	r3, #2147483648	@ 0x80000000
 8004a74:	d101      	bne.n	8004a7a <LL_ADC_IsCalibrationOnGoing+0x1a>
 8004a76:	2301      	movs	r3, #1
 8004a78:	e000      	b.n	8004a7c <LL_ADC_IsCalibrationOnGoing+0x1c>
 8004a7a:	2300      	movs	r3, #0
}
 8004a7c:	4618      	mov	r0, r3
 8004a7e:	370c      	adds	r7, #12
 8004a80:	46bd      	mov	sp, r7
 8004a82:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004a86:	4770      	bx	lr

08004a88 <LL_ADC_REG_IsConversionOngoing>:
{
 8004a88:	b480      	push	{r7}
 8004a8a:	b083      	sub	sp, #12
 8004a8c:	af00      	add	r7, sp, #0
 8004a8e:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
 8004a90:	687b      	ldr	r3, [r7, #4]
 8004a92:	689b      	ldr	r3, [r3, #8]
 8004a94:	f003 0304 	and.w	r3, r3, #4
 8004a98:	2b04      	cmp	r3, #4
 8004a9a:	d101      	bne.n	8004aa0 <LL_ADC_REG_IsConversionOngoing+0x18>
 8004a9c:	2301      	movs	r3, #1
 8004a9e:	e000      	b.n	8004aa2 <LL_ADC_REG_IsConversionOngoing+0x1a>
 8004aa0:	2300      	movs	r3, #0
}
 8004aa2:	4618      	mov	r0, r3
 8004aa4:	370c      	adds	r7, #12
 8004aa6:	46bd      	mov	sp, r7
 8004aa8:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004aac:	4770      	bx	lr
	...

08004ab0 <HAL_ADCEx_Calibration_Start>:
  *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
  *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
{
 8004ab0:	b580      	push	{r7, lr}
 8004ab2:	b086      	sub	sp, #24
 8004ab4:	af00      	add	r7, sp, #0
 8004ab6:	60f8      	str	r0, [r7, #12]
 8004ab8:	60b9      	str	r1, [r7, #8]
 8004aba:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status;
  __IO uint32_t wait_loop_index = 0UL;
 8004abc:	2300      	movs	r3, #0
 8004abe:	613b      	str	r3, [r7, #16]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));

  /* Process locked */
  __HAL_LOCK(hadc);
 8004ac0:	68fb      	ldr	r3, [r7, #12]
 8004ac2:	f893 3050 	ldrb.w	r3, [r3, #80]	@ 0x50
 8004ac6:	2b01      	cmp	r3, #1
 8004ac8:	d101      	bne.n	8004ace <HAL_ADCEx_Calibration_Start+0x1e>
 8004aca:	2302      	movs	r3, #2
 8004acc:	e04c      	b.n	8004b68 <HAL_ADCEx_Calibration_Start+0xb8>
 8004ace:	68fb      	ldr	r3, [r7, #12]
 8004ad0:	2201      	movs	r2, #1
 8004ad2:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

  /* Calibration prerequisite: ADC must be disabled. */

  /* Disable the ADC (if not already disabled) */
  tmp_hal_status = ADC_Disable(hadc);
 8004ad6:	68f8      	ldr	r0, [r7, #12]
 8004ad8:	f7ff fd90 	bl	80045fc <ADC_Disable>
 8004adc:	4603      	mov	r3, r0
 8004ade:	75fb      	strb	r3, [r7, #23]

  /* Check if ADC is effectively disabled */
  if (tmp_hal_status == HAL_OK)
 8004ae0:	7dfb      	ldrb	r3, [r7, #23]
 8004ae2:	2b00      	cmp	r3, #0
 8004ae4:	d135      	bne.n	8004b52 <HAL_ADCEx_Calibration_Start+0xa2>
  {
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 8004ae6:	68fb      	ldr	r3, [r7, #12]
 8004ae8:	6d5a      	ldr	r2, [r3, #84]	@ 0x54
 8004aea:	4b21      	ldr	r3, [pc, #132]	@ (8004b70 <HAL_ADCEx_Calibration_Start+0xc0>)
 8004aec:	4013      	ands	r3, r2
 8004aee:	f043 0202 	orr.w	r2, r3, #2
 8004af2:	68fb      	ldr	r3, [r7, #12]
 8004af4:	655a      	str	r2, [r3, #84]	@ 0x54
                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
                      HAL_ADC_STATE_BUSY_INTERNAL);

    /* Start ADC calibration in mode single-ended or differential */
    LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff);
 8004af6:	68fb      	ldr	r3, [r7, #12]
 8004af8:	681b      	ldr	r3, [r3, #0]
 8004afa:	687a      	ldr	r2, [r7, #4]
 8004afc:	68b9      	ldr	r1, [r7, #8]
 8004afe:	4618      	mov	r0, r3
 8004b00:	f7ff ff90 	bl	8004a24 <LL_ADC_StartCalibration>

    /* Wait for calibration completion */
    while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
 8004b04:	e014      	b.n	8004b30 <HAL_ADCEx_Calibration_Start+0x80>
    {
      wait_loop_index++;
 8004b06:	693b      	ldr	r3, [r7, #16]
 8004b08:	3301      	adds	r3, #1
 8004b0a:	613b      	str	r3, [r7, #16]
      if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
 8004b0c:	693b      	ldr	r3, [r7, #16]
 8004b0e:	4a19      	ldr	r2, [pc, #100]	@ (8004b74 <HAL_ADCEx_Calibration_Start+0xc4>)
 8004b10:	4293      	cmp	r3, r2
 8004b12:	d30d      	bcc.n	8004b30 <HAL_ADCEx_Calibration_Start+0x80>
      {
        /* Update ADC state machine to error */
        ADC_STATE_CLR_SET(hadc->State,
 8004b14:	68fb      	ldr	r3, [r7, #12]
 8004b16:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8004b18:	f023 0312 	bic.w	r3, r3, #18
 8004b1c:	f043 0210 	orr.w	r2, r3, #16
 8004b20:	68fb      	ldr	r3, [r7, #12]
 8004b22:	655a      	str	r2, [r3, #84]	@ 0x54
                          HAL_ADC_STATE_BUSY_INTERNAL,
                          HAL_ADC_STATE_ERROR_INTERNAL);

        /* Process unlocked */
        __HAL_UNLOCK(hadc);
 8004b24:	68fb      	ldr	r3, [r7, #12]
 8004b26:	2200      	movs	r2, #0
 8004b28:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

        return HAL_ERROR;
 8004b2c:	2301      	movs	r3, #1
 8004b2e:	e01b      	b.n	8004b68 <HAL_ADCEx_Calibration_Start+0xb8>
    while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
 8004b30:	68fb      	ldr	r3, [r7, #12]
 8004b32:	681b      	ldr	r3, [r3, #0]
 8004b34:	4618      	mov	r0, r3
 8004b36:	f7ff ff93 	bl	8004a60 <LL_ADC_IsCalibrationOnGoing>
 8004b3a:	4603      	mov	r3, r0
 8004b3c:	2b00      	cmp	r3, #0
 8004b3e:	d1e2      	bne.n	8004b06 <HAL_ADCEx_Calibration_Start+0x56>
      }
    }

    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 8004b40:	68fb      	ldr	r3, [r7, #12]
 8004b42:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8004b44:	f023 0303 	bic.w	r3, r3, #3
 8004b48:	f043 0201 	orr.w	r2, r3, #1
 8004b4c:	68fb      	ldr	r3, [r7, #12]
 8004b4e:	655a      	str	r2, [r3, #84]	@ 0x54
 8004b50:	e005      	b.n	8004b5e <HAL_ADCEx_Calibration_Start+0xae>
                      HAL_ADC_STATE_BUSY_INTERNAL,
                      HAL_ADC_STATE_READY);
  }
  else
  {
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8004b52:	68fb      	ldr	r3, [r7, #12]
 8004b54:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8004b56:	f043 0210 	orr.w	r2, r3, #16
 8004b5a:	68fb      	ldr	r3, [r7, #12]
 8004b5c:	655a      	str	r2, [r3, #84]	@ 0x54
    /* Note: No need to update variable "tmp_hal_status" here: already set    */
    /*       to state "HAL_ERROR" by function disabling the ADC.              */
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 8004b5e:	68fb      	ldr	r3, [r7, #12]
 8004b60:	2200      	movs	r2, #0
 8004b62:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

  /* Return function status */
  return tmp_hal_status;
 8004b66:	7dfb      	ldrb	r3, [r7, #23]
}
 8004b68:	4618      	mov	r0, r3
 8004b6a:	3718      	adds	r7, #24
 8004b6c:	46bd      	mov	sp, r7
 8004b6e:	bd80      	pop	{r7, pc}
 8004b70:	ffffeefd 	.word	0xffffeefd
 8004b74:	25c3f800 	.word	0x25c3f800

08004b78 <HAL_ADCEx_MultiModeConfigChannel>:
  * @param hadc Master ADC handle
  * @param multimode Structure of ADC multimode configuration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
{
 8004b78:	b590      	push	{r4, r7, lr}
 8004b7a:	b09f      	sub	sp, #124	@ 0x7c
 8004b7c:	af00      	add	r7, sp, #0
 8004b7e:	6078      	str	r0, [r7, #4]
 8004b80:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8004b82:	2300      	movs	r3, #0
 8004b84:	f887 3077 	strb.w	r3, [r7, #119]	@ 0x77
    assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData));
    assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
  }

  /* Process locked */
  __HAL_LOCK(hadc);
 8004b88:	687b      	ldr	r3, [r7, #4]
 8004b8a:	f893 3050 	ldrb.w	r3, [r3, #80]	@ 0x50
 8004b8e:	2b01      	cmp	r3, #1
 8004b90:	d101      	bne.n	8004b96 <HAL_ADCEx_MultiModeConfigChannel+0x1e>
 8004b92:	2302      	movs	r3, #2
 8004b94:	e0be      	b.n	8004d14 <HAL_ADCEx_MultiModeConfigChannel+0x19c>
 8004b96:	687b      	ldr	r3, [r7, #4]
 8004b98:	2201      	movs	r2, #1
 8004b9a:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

  tmphadcSlave.State = HAL_ADC_STATE_RESET;
 8004b9e:	2300      	movs	r3, #0
 8004ba0:	65fb      	str	r3, [r7, #92]	@ 0x5c
  tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
 8004ba2:	2300      	movs	r3, #0
 8004ba4:	663b      	str	r3, [r7, #96]	@ 0x60

  ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
 8004ba6:	687b      	ldr	r3, [r7, #4]
 8004ba8:	681b      	ldr	r3, [r3, #0]
 8004baa:	4a5c      	ldr	r2, [pc, #368]	@ (8004d1c <HAL_ADCEx_MultiModeConfigChannel+0x1a4>)
 8004bac:	4293      	cmp	r3, r2
 8004bae:	d102      	bne.n	8004bb6 <HAL_ADCEx_MultiModeConfigChannel+0x3e>
 8004bb0:	4b5b      	ldr	r3, [pc, #364]	@ (8004d20 <HAL_ADCEx_MultiModeConfigChannel+0x1a8>)
 8004bb2:	60bb      	str	r3, [r7, #8]
 8004bb4:	e001      	b.n	8004bba <HAL_ADCEx_MultiModeConfigChannel+0x42>
 8004bb6:	2300      	movs	r3, #0
 8004bb8:	60bb      	str	r3, [r7, #8]

  if (tmphadcSlave.Instance == NULL)
 8004bba:	68bb      	ldr	r3, [r7, #8]
 8004bbc:	2b00      	cmp	r3, #0
 8004bbe:	d10b      	bne.n	8004bd8 <HAL_ADCEx_MultiModeConfigChannel+0x60>
  {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 8004bc0:	687b      	ldr	r3, [r7, #4]
 8004bc2:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8004bc4:	f043 0220 	orr.w	r2, r3, #32
 8004bc8:	687b      	ldr	r3, [r7, #4]
 8004bca:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Process unlocked */
    __HAL_UNLOCK(hadc);
 8004bcc:	687b      	ldr	r3, [r7, #4]
 8004bce:	2200      	movs	r2, #0
 8004bd0:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

    return HAL_ERROR;
 8004bd4:	2301      	movs	r3, #1
 8004bd6:	e09d      	b.n	8004d14 <HAL_ADCEx_MultiModeConfigChannel+0x19c>

  /* Parameters update conditioned to ADC state:                              */
  /* Parameters that can be updated when ADC is disabled or enabled without   */
  /* conversion on going on regular group:                                    */
  /*  - Multimode DATA Format configuration                                   */
  tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
 8004bd8:	68bb      	ldr	r3, [r7, #8]
 8004bda:	4618      	mov	r0, r3
 8004bdc:	f7ff ff54 	bl	8004a88 <LL_ADC_REG_IsConversionOngoing>
 8004be0:	6738      	str	r0, [r7, #112]	@ 0x70
  if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
 8004be2:	687b      	ldr	r3, [r7, #4]
 8004be4:	681b      	ldr	r3, [r3, #0]
 8004be6:	4618      	mov	r0, r3
 8004be8:	f7ff ff4e 	bl	8004a88 <LL_ADC_REG_IsConversionOngoing>
 8004bec:	4603      	mov	r3, r0
 8004bee:	2b00      	cmp	r3, #0
 8004bf0:	d17f      	bne.n	8004cf2 <HAL_ADCEx_MultiModeConfigChannel+0x17a>
      && (tmphadcSlave_conversion_on_going == 0UL))
 8004bf2:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
 8004bf4:	2b00      	cmp	r3, #0
 8004bf6:	d17c      	bne.n	8004cf2 <HAL_ADCEx_MultiModeConfigChannel+0x17a>
  {
    /* Pointer to the common control register */
    tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
 8004bf8:	687b      	ldr	r3, [r7, #4]
 8004bfa:	681b      	ldr	r3, [r3, #0]
 8004bfc:	4a47      	ldr	r2, [pc, #284]	@ (8004d1c <HAL_ADCEx_MultiModeConfigChannel+0x1a4>)
 8004bfe:	4293      	cmp	r3, r2
 8004c00:	d004      	beq.n	8004c0c <HAL_ADCEx_MultiModeConfigChannel+0x94>
 8004c02:	687b      	ldr	r3, [r7, #4]
 8004c04:	681b      	ldr	r3, [r3, #0]
 8004c06:	4a46      	ldr	r2, [pc, #280]	@ (8004d20 <HAL_ADCEx_MultiModeConfigChannel+0x1a8>)
 8004c08:	4293      	cmp	r3, r2
 8004c0a:	d101      	bne.n	8004c10 <HAL_ADCEx_MultiModeConfigChannel+0x98>
 8004c0c:	4b45      	ldr	r3, [pc, #276]	@ (8004d24 <HAL_ADCEx_MultiModeConfigChannel+0x1ac>)
 8004c0e:	e000      	b.n	8004c12 <HAL_ADCEx_MultiModeConfigChannel+0x9a>
 8004c10:	4b45      	ldr	r3, [pc, #276]	@ (8004d28 <HAL_ADCEx_MultiModeConfigChannel+0x1b0>)
 8004c12:	66fb      	str	r3, [r7, #108]	@ 0x6c

    /* If multimode is selected, configure all multimode parameters.          */
    /* Otherwise, reset multimode parameters (can be used in case of          */
    /* transition from multimode to independent mode).                        */
    if (multimode->Mode != ADC_MODE_INDEPENDENT)
 8004c14:	683b      	ldr	r3, [r7, #0]
 8004c16:	681b      	ldr	r3, [r3, #0]
 8004c18:	2b00      	cmp	r3, #0
 8004c1a:	d039      	beq.n	8004c90 <HAL_ADCEx_MultiModeConfigChannel+0x118>
    {
      MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
 8004c1c:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8004c1e:	689b      	ldr	r3, [r3, #8]
 8004c20:	f423 4240 	bic.w	r2, r3, #49152	@ 0xc000
 8004c24:	683b      	ldr	r3, [r7, #0]
 8004c26:	685b      	ldr	r3, [r3, #4]
 8004c28:	431a      	orrs	r2, r3
 8004c2a:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8004c2c:	609a      	str	r2, [r3, #8]
      /*      from 1 to 8 clock cycles for 12 bits                              */
      /*      from 1 to 6 clock cycles for 10 and 8 bits                        */
      /*    If a higher delay is selected, it will be clipped to maximum delay  */
      /*    range                                                               */

      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
 8004c2e:	687b      	ldr	r3, [r7, #4]
 8004c30:	681b      	ldr	r3, [r3, #0]
 8004c32:	4a3a      	ldr	r2, [pc, #232]	@ (8004d1c <HAL_ADCEx_MultiModeConfigChannel+0x1a4>)
 8004c34:	4293      	cmp	r3, r2
 8004c36:	d004      	beq.n	8004c42 <HAL_ADCEx_MultiModeConfigChannel+0xca>
 8004c38:	687b      	ldr	r3, [r7, #4]
 8004c3a:	681b      	ldr	r3, [r3, #0]
 8004c3c:	4a38      	ldr	r2, [pc, #224]	@ (8004d20 <HAL_ADCEx_MultiModeConfigChannel+0x1a8>)
 8004c3e:	4293      	cmp	r3, r2
 8004c40:	d10e      	bne.n	8004c60 <HAL_ADCEx_MultiModeConfigChannel+0xe8>
 8004c42:	4836      	ldr	r0, [pc, #216]	@ (8004d1c <HAL_ADCEx_MultiModeConfigChannel+0x1a4>)
 8004c44:	f7ff feda 	bl	80049fc <LL_ADC_IsEnabled>
 8004c48:	4604      	mov	r4, r0
 8004c4a:	4835      	ldr	r0, [pc, #212]	@ (8004d20 <HAL_ADCEx_MultiModeConfigChannel+0x1a8>)
 8004c4c:	f7ff fed6 	bl	80049fc <LL_ADC_IsEnabled>
 8004c50:	4603      	mov	r3, r0
 8004c52:	4323      	orrs	r3, r4
 8004c54:	2b00      	cmp	r3, #0
 8004c56:	bf0c      	ite	eq
 8004c58:	2301      	moveq	r3, #1
 8004c5a:	2300      	movne	r3, #0
 8004c5c:	b2db      	uxtb	r3, r3
 8004c5e:	e008      	b.n	8004c72 <HAL_ADCEx_MultiModeConfigChannel+0xfa>
 8004c60:	4832      	ldr	r0, [pc, #200]	@ (8004d2c <HAL_ADCEx_MultiModeConfigChannel+0x1b4>)
 8004c62:	f7ff fecb 	bl	80049fc <LL_ADC_IsEnabled>
 8004c66:	4603      	mov	r3, r0
 8004c68:	2b00      	cmp	r3, #0
 8004c6a:	bf0c      	ite	eq
 8004c6c:	2301      	moveq	r3, #1
 8004c6e:	2300      	movne	r3, #0
 8004c70:	b2db      	uxtb	r3, r3
 8004c72:	2b00      	cmp	r3, #0
 8004c74:	d047      	beq.n	8004d06 <HAL_ADCEx_MultiModeConfigChannel+0x18e>
      {
        MODIFY_REG(tmpADC_Common->CCR,
 8004c76:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8004c78:	689a      	ldr	r2, [r3, #8]
 8004c7a:	4b2d      	ldr	r3, [pc, #180]	@ (8004d30 <HAL_ADCEx_MultiModeConfigChannel+0x1b8>)
 8004c7c:	4013      	ands	r3, r2
 8004c7e:	683a      	ldr	r2, [r7, #0]
 8004c80:	6811      	ldr	r1, [r2, #0]
 8004c82:	683a      	ldr	r2, [r7, #0]
 8004c84:	6892      	ldr	r2, [r2, #8]
 8004c86:	430a      	orrs	r2, r1
 8004c88:	431a      	orrs	r2, r3
 8004c8a:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8004c8c:	609a      	str	r2, [r3, #8]
    if (multimode->Mode != ADC_MODE_INDEPENDENT)
 8004c8e:	e03a      	b.n	8004d06 <HAL_ADCEx_MultiModeConfigChannel+0x18e>
                  );
      }
    }
    else /* ADC_MODE_INDEPENDENT */
    {
      CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
 8004c90:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8004c92:	689b      	ldr	r3, [r3, #8]
 8004c94:	f423 4240 	bic.w	r2, r3, #49152	@ 0xc000
 8004c98:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8004c9a:	609a      	str	r2, [r3, #8]

      /* Parameters that can be updated only when ADC is disabled:                */
      /*  - Multimode mode selection                                              */
      /*  - Multimode delay                                                       */
      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
 8004c9c:	687b      	ldr	r3, [r7, #4]
 8004c9e:	681b      	ldr	r3, [r3, #0]
 8004ca0:	4a1e      	ldr	r2, [pc, #120]	@ (8004d1c <HAL_ADCEx_MultiModeConfigChannel+0x1a4>)
 8004ca2:	4293      	cmp	r3, r2
 8004ca4:	d004      	beq.n	8004cb0 <HAL_ADCEx_MultiModeConfigChannel+0x138>
 8004ca6:	687b      	ldr	r3, [r7, #4]
 8004ca8:	681b      	ldr	r3, [r3, #0]
 8004caa:	4a1d      	ldr	r2, [pc, #116]	@ (8004d20 <HAL_ADCEx_MultiModeConfigChannel+0x1a8>)
 8004cac:	4293      	cmp	r3, r2
 8004cae:	d10e      	bne.n	8004cce <HAL_ADCEx_MultiModeConfigChannel+0x156>
 8004cb0:	481a      	ldr	r0, [pc, #104]	@ (8004d1c <HAL_ADCEx_MultiModeConfigChannel+0x1a4>)
 8004cb2:	f7ff fea3 	bl	80049fc <LL_ADC_IsEnabled>
 8004cb6:	4604      	mov	r4, r0
 8004cb8:	4819      	ldr	r0, [pc, #100]	@ (8004d20 <HAL_ADCEx_MultiModeConfigChannel+0x1a8>)
 8004cba:	f7ff fe9f 	bl	80049fc <LL_ADC_IsEnabled>
 8004cbe:	4603      	mov	r3, r0
 8004cc0:	4323      	orrs	r3, r4
 8004cc2:	2b00      	cmp	r3, #0
 8004cc4:	bf0c      	ite	eq
 8004cc6:	2301      	moveq	r3, #1
 8004cc8:	2300      	movne	r3, #0
 8004cca:	b2db      	uxtb	r3, r3
 8004ccc:	e008      	b.n	8004ce0 <HAL_ADCEx_MultiModeConfigChannel+0x168>
 8004cce:	4817      	ldr	r0, [pc, #92]	@ (8004d2c <HAL_ADCEx_MultiModeConfigChannel+0x1b4>)
 8004cd0:	f7ff fe94 	bl	80049fc <LL_ADC_IsEnabled>
 8004cd4:	4603      	mov	r3, r0
 8004cd6:	2b00      	cmp	r3, #0
 8004cd8:	bf0c      	ite	eq
 8004cda:	2301      	moveq	r3, #1
 8004cdc:	2300      	movne	r3, #0
 8004cde:	b2db      	uxtb	r3, r3
 8004ce0:	2b00      	cmp	r3, #0
 8004ce2:	d010      	beq.n	8004d06 <HAL_ADCEx_MultiModeConfigChannel+0x18e>
      {
        CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
 8004ce4:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8004ce6:	689a      	ldr	r2, [r3, #8]
 8004ce8:	4b11      	ldr	r3, [pc, #68]	@ (8004d30 <HAL_ADCEx_MultiModeConfigChannel+0x1b8>)
 8004cea:	4013      	ands	r3, r2
 8004cec:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
 8004cee:	6093      	str	r3, [r2, #8]
    if (multimode->Mode != ADC_MODE_INDEPENDENT)
 8004cf0:	e009      	b.n	8004d06 <HAL_ADCEx_MultiModeConfigChannel+0x18e>
  /* If one of the ADC sharing the same common group is enabled, no update    */
  /* could be done on neither of the multimode structure parameters.          */
  else
  {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 8004cf2:	687b      	ldr	r3, [r7, #4]
 8004cf4:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8004cf6:	f043 0220 	orr.w	r2, r3, #32
 8004cfa:	687b      	ldr	r3, [r7, #4]
 8004cfc:	655a      	str	r2, [r3, #84]	@ 0x54

    tmp_hal_status = HAL_ERROR;
 8004cfe:	2301      	movs	r3, #1
 8004d00:	f887 3077 	strb.w	r3, [r7, #119]	@ 0x77
 8004d04:	e000      	b.n	8004d08 <HAL_ADCEx_MultiModeConfigChannel+0x190>
    if (multimode->Mode != ADC_MODE_INDEPENDENT)
 8004d06:	bf00      	nop
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 8004d08:	687b      	ldr	r3, [r7, #4]
 8004d0a:	2200      	movs	r2, #0
 8004d0c:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

  /* Return function status */
  return tmp_hal_status;
 8004d10:	f897 3077 	ldrb.w	r3, [r7, #119]	@ 0x77
}
 8004d14:	4618      	mov	r0, r3
 8004d16:	377c      	adds	r7, #124	@ 0x7c
 8004d18:	46bd      	mov	sp, r7
 8004d1a:	bd90      	pop	{r4, r7, pc}
 8004d1c:	40022000 	.word	0x40022000
 8004d20:	40022100 	.word	0x40022100
 8004d24:	40022300 	.word	0x40022300
 8004d28:	58026300 	.word	0x58026300
 8004d2c:	58026000 	.word	0x58026000
 8004d30:	fffff0e0 	.word	0xfffff0e0

08004d34 <__NVIC_SetPriorityGrouping>:
{
 8004d34:	b480      	push	{r7}
 8004d36:	b085      	sub	sp, #20
 8004d38:	af00      	add	r7, sp, #0
 8004d3a:	6078      	str	r0, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 8004d3c:	687b      	ldr	r3, [r7, #4]
 8004d3e:	f003 0307 	and.w	r3, r3, #7
 8004d42:	60fb      	str	r3, [r7, #12]
  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8004d44:	4b0b      	ldr	r3, [pc, #44]	@ (8004d74 <__NVIC_SetPriorityGrouping+0x40>)
 8004d46:	68db      	ldr	r3, [r3, #12]
 8004d48:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8004d4a:	68ba      	ldr	r2, [r7, #8]
 8004d4c:	f64f 03ff 	movw	r3, #63743	@ 0xf8ff
 8004d50:	4013      	ands	r3, r2
 8004d52:	60bb      	str	r3, [r7, #8]
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 8004d54:	68fb      	ldr	r3, [r7, #12]
 8004d56:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 8004d58:	68bb      	ldr	r3, [r7, #8]
 8004d5a:	431a      	orrs	r2, r3
  reg_value  =  (reg_value                                   |
 8004d5c:	4b06      	ldr	r3, [pc, #24]	@ (8004d78 <__NVIC_SetPriorityGrouping+0x44>)
 8004d5e:	4313      	orrs	r3, r2
 8004d60:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 8004d62:	4a04      	ldr	r2, [pc, #16]	@ (8004d74 <__NVIC_SetPriorityGrouping+0x40>)
 8004d64:	68bb      	ldr	r3, [r7, #8]
 8004d66:	60d3      	str	r3, [r2, #12]
}
 8004d68:	bf00      	nop
 8004d6a:	3714      	adds	r7, #20
 8004d6c:	46bd      	mov	sp, r7
 8004d6e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004d72:	4770      	bx	lr
 8004d74:	e000ed00 	.word	0xe000ed00
 8004d78:	05fa0000 	.word	0x05fa0000

08004d7c <__NVIC_GetPriorityGrouping>:
{
 8004d7c:	b480      	push	{r7}
 8004d7e:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8004d80:	4b04      	ldr	r3, [pc, #16]	@ (8004d94 <__NVIC_GetPriorityGrouping+0x18>)
 8004d82:	68db      	ldr	r3, [r3, #12]
 8004d84:	0a1b      	lsrs	r3, r3, #8
 8004d86:	f003 0307 	and.w	r3, r3, #7
}
 8004d8a:	4618      	mov	r0, r3
 8004d8c:	46bd      	mov	sp, r7
 8004d8e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004d92:	4770      	bx	lr
 8004d94:	e000ed00 	.word	0xe000ed00

08004d98 <__NVIC_EnableIRQ>:
{
 8004d98:	b480      	push	{r7}
 8004d9a:	b083      	sub	sp, #12
 8004d9c:	af00      	add	r7, sp, #0
 8004d9e:	4603      	mov	r3, r0
 8004da0:	80fb      	strh	r3, [r7, #6]
  if ((int32_t)(IRQn) >= 0)
 8004da2:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 8004da6:	2b00      	cmp	r3, #0
 8004da8:	db0b      	blt.n	8004dc2 <__NVIC_EnableIRQ+0x2a>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 8004daa:	88fb      	ldrh	r3, [r7, #6]
 8004dac:	f003 021f 	and.w	r2, r3, #31
 8004db0:	4907      	ldr	r1, [pc, #28]	@ (8004dd0 <__NVIC_EnableIRQ+0x38>)
 8004db2:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 8004db6:	095b      	lsrs	r3, r3, #5
 8004db8:	2001      	movs	r0, #1
 8004dba:	fa00 f202 	lsl.w	r2, r0, r2
 8004dbe:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
}
 8004dc2:	bf00      	nop
 8004dc4:	370c      	adds	r7, #12
 8004dc6:	46bd      	mov	sp, r7
 8004dc8:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004dcc:	4770      	bx	lr
 8004dce:	bf00      	nop
 8004dd0:	e000e100 	.word	0xe000e100

08004dd4 <__NVIC_SetPriority>:
{
 8004dd4:	b480      	push	{r7}
 8004dd6:	b083      	sub	sp, #12
 8004dd8:	af00      	add	r7, sp, #0
 8004dda:	4603      	mov	r3, r0
 8004ddc:	6039      	str	r1, [r7, #0]
 8004dde:	80fb      	strh	r3, [r7, #6]
  if ((int32_t)(IRQn) >= 0)
 8004de0:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 8004de4:	2b00      	cmp	r3, #0
 8004de6:	db0a      	blt.n	8004dfe <__NVIC_SetPriority+0x2a>
    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8004de8:	683b      	ldr	r3, [r7, #0]
 8004dea:	b2da      	uxtb	r2, r3
 8004dec:	490c      	ldr	r1, [pc, #48]	@ (8004e20 <__NVIC_SetPriority+0x4c>)
 8004dee:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 8004df2:	0112      	lsls	r2, r2, #4
 8004df4:	b2d2      	uxtb	r2, r2
 8004df6:	440b      	add	r3, r1
 8004df8:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
}
 8004dfc:	e00a      	b.n	8004e14 <__NVIC_SetPriority+0x40>
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8004dfe:	683b      	ldr	r3, [r7, #0]
 8004e00:	b2da      	uxtb	r2, r3
 8004e02:	4908      	ldr	r1, [pc, #32]	@ (8004e24 <__NVIC_SetPriority+0x50>)
 8004e04:	88fb      	ldrh	r3, [r7, #6]
 8004e06:	f003 030f 	and.w	r3, r3, #15
 8004e0a:	3b04      	subs	r3, #4
 8004e0c:	0112      	lsls	r2, r2, #4
 8004e0e:	b2d2      	uxtb	r2, r2
 8004e10:	440b      	add	r3, r1
 8004e12:	761a      	strb	r2, [r3, #24]
}
 8004e14:	bf00      	nop
 8004e16:	370c      	adds	r7, #12
 8004e18:	46bd      	mov	sp, r7
 8004e1a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004e1e:	4770      	bx	lr
 8004e20:	e000e100 	.word	0xe000e100
 8004e24:	e000ed00 	.word	0xe000ed00

08004e28 <NVIC_EncodePriority>:
{
 8004e28:	b480      	push	{r7}
 8004e2a:	b089      	sub	sp, #36	@ 0x24
 8004e2c:	af00      	add	r7, sp, #0
 8004e2e:	60f8      	str	r0, [r7, #12]
 8004e30:	60b9      	str	r1, [r7, #8]
 8004e32:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 8004e34:	68fb      	ldr	r3, [r7, #12]
 8004e36:	f003 0307 	and.w	r3, r3, #7
 8004e3a:	61fb      	str	r3, [r7, #28]
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8004e3c:	69fb      	ldr	r3, [r7, #28]
 8004e3e:	f1c3 0307 	rsb	r3, r3, #7
 8004e42:	2b04      	cmp	r3, #4
 8004e44:	bf28      	it	cs
 8004e46:	2304      	movcs	r3, #4
 8004e48:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8004e4a:	69fb      	ldr	r3, [r7, #28]
 8004e4c:	3304      	adds	r3, #4
 8004e4e:	2b06      	cmp	r3, #6
 8004e50:	d902      	bls.n	8004e58 <NVIC_EncodePriority+0x30>
 8004e52:	69fb      	ldr	r3, [r7, #28]
 8004e54:	3b03      	subs	r3, #3
 8004e56:	e000      	b.n	8004e5a <NVIC_EncodePriority+0x32>
 8004e58:	2300      	movs	r3, #0
 8004e5a:	617b      	str	r3, [r7, #20]
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004e5c:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8004e60:	69bb      	ldr	r3, [r7, #24]
 8004e62:	fa02 f303 	lsl.w	r3, r2, r3
 8004e66:	43da      	mvns	r2, r3
 8004e68:	68bb      	ldr	r3, [r7, #8]
 8004e6a:	401a      	ands	r2, r3
 8004e6c:	697b      	ldr	r3, [r7, #20]
 8004e6e:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8004e70:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8004e74:	697b      	ldr	r3, [r7, #20]
 8004e76:	fa01 f303 	lsl.w	r3, r1, r3
 8004e7a:	43d9      	mvns	r1, r3
 8004e7c:	687b      	ldr	r3, [r7, #4]
 8004e7e:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004e80:	4313      	orrs	r3, r2
}
 8004e82:	4618      	mov	r0, r3
 8004e84:	3724      	adds	r7, #36	@ 0x24
 8004e86:	46bd      	mov	sp, r7
 8004e88:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004e8c:	4770      	bx	lr

08004e8e <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
  *         The pending IRQ priority will be managed only by the subpriority.
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8004e8e:	b580      	push	{r7, lr}
 8004e90:	b082      	sub	sp, #8
 8004e92:	af00      	add	r7, sp, #0
 8004e94:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));

  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 8004e96:	6878      	ldr	r0, [r7, #4]
 8004e98:	f7ff ff4c 	bl	8004d34 <__NVIC_SetPriorityGrouping>
}
 8004e9c:	bf00      	nop
 8004e9e:	3708      	adds	r7, #8
 8004ea0:	46bd      	mov	sp, r7
 8004ea2:	bd80      	pop	{r7, pc}

08004ea4 <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8004ea4:	b580      	push	{r7, lr}
 8004ea6:	b086      	sub	sp, #24
 8004ea8:	af00      	add	r7, sp, #0
 8004eaa:	4603      	mov	r3, r0
 8004eac:	60b9      	str	r1, [r7, #8]
 8004eae:	607a      	str	r2, [r7, #4]
 8004eb0:	81fb      	strh	r3, [r7, #14]

  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));

  prioritygroup = NVIC_GetPriorityGrouping();
 8004eb2:	f7ff ff63 	bl	8004d7c <__NVIC_GetPriorityGrouping>
 8004eb6:	6178      	str	r0, [r7, #20]

  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 8004eb8:	687a      	ldr	r2, [r7, #4]
 8004eba:	68b9      	ldr	r1, [r7, #8]
 8004ebc:	6978      	ldr	r0, [r7, #20]
 8004ebe:	f7ff ffb3 	bl	8004e28 <NVIC_EncodePriority>
 8004ec2:	4602      	mov	r2, r0
 8004ec4:	f9b7 300e 	ldrsh.w	r3, [r7, #14]
 8004ec8:	4611      	mov	r1, r2
 8004eca:	4618      	mov	r0, r3
 8004ecc:	f7ff ff82 	bl	8004dd4 <__NVIC_SetPriority>
}
 8004ed0:	bf00      	nop
 8004ed2:	3718      	adds	r7, #24
 8004ed4:	46bd      	mov	sp, r7
 8004ed6:	bd80      	pop	{r7, pc}

08004ed8 <HAL_NVIC_EnableIRQ>:
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
  * @retval None
  */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
 8004ed8:	b580      	push	{r7, lr}
 8004eda:	b082      	sub	sp, #8
 8004edc:	af00      	add	r7, sp, #0
 8004ede:	4603      	mov	r3, r0
 8004ee0:	80fb      	strh	r3, [r7, #6]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));

  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
 8004ee2:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 8004ee6:	4618      	mov	r0, r3
 8004ee8:	f7ff ff56 	bl	8004d98 <__NVIC_EnableIRQ>
}
 8004eec:	bf00      	nop
 8004eee:	3708      	adds	r7, #8
 8004ef0:	46bd      	mov	sp, r7
 8004ef2:	bd80      	pop	{r7, pc}

08004ef4 <HAL_MPU_Disable>:
/**
  * @brief  Disables the MPU
  * @retval None
  */
void HAL_MPU_Disable(void)
{
 8004ef4:	b480      	push	{r7}
 8004ef6:	af00      	add	r7, sp, #0
  __ASM volatile ("dmb 0xF":::"memory");
 8004ef8:	f3bf 8f5f 	dmb	sy
}
 8004efc:	bf00      	nop
  /* Make sure outstanding transfers are done */
  __DMB();

  /* Disable fault exceptions */
  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 8004efe:	4b07      	ldr	r3, [pc, #28]	@ (8004f1c <HAL_MPU_Disable+0x28>)
 8004f00:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004f02:	4a06      	ldr	r2, [pc, #24]	@ (8004f1c <HAL_MPU_Disable+0x28>)
 8004f04:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 8004f08:	6253      	str	r3, [r2, #36]	@ 0x24

  /* Disable the MPU and clear the control register*/
  MPU->CTRL = 0;
 8004f0a:	4b05      	ldr	r3, [pc, #20]	@ (8004f20 <HAL_MPU_Disable+0x2c>)
 8004f0c:	2200      	movs	r2, #0
 8004f0e:	605a      	str	r2, [r3, #4]
}
 8004f10:	bf00      	nop
 8004f12:	46bd      	mov	sp, r7
 8004f14:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004f18:	4770      	bx	lr
 8004f1a:	bf00      	nop
 8004f1c:	e000ed00 	.word	0xe000ed00
 8004f20:	e000ed90 	.word	0xe000ed90

08004f24 <HAL_MPU_Enable>:
  *            @arg MPU_PRIVILEGED_DEFAULT
  *            @arg MPU_HFNMI_PRIVDEF
  * @retval None
  */
void HAL_MPU_Enable(uint32_t MPU_Control)
{
 8004f24:	b480      	push	{r7}
 8004f26:	b083      	sub	sp, #12
 8004f28:	af00      	add	r7, sp, #0
 8004f2a:	6078      	str	r0, [r7, #4]
  /* Enable the MPU */
  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 8004f2c:	4a0b      	ldr	r2, [pc, #44]	@ (8004f5c <HAL_MPU_Enable+0x38>)
 8004f2e:	687b      	ldr	r3, [r7, #4]
 8004f30:	f043 0301 	orr.w	r3, r3, #1
 8004f34:	6053      	str	r3, [r2, #4]

  /* Enable fault exceptions */
  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 8004f36:	4b0a      	ldr	r3, [pc, #40]	@ (8004f60 <HAL_MPU_Enable+0x3c>)
 8004f38:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004f3a:	4a09      	ldr	r2, [pc, #36]	@ (8004f60 <HAL_MPU_Enable+0x3c>)
 8004f3c:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 8004f40:	6253      	str	r3, [r2, #36]	@ 0x24
  __ASM volatile ("dsb 0xF":::"memory");
 8004f42:	f3bf 8f4f 	dsb	sy
}
 8004f46:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 8004f48:	f3bf 8f6f 	isb	sy
}
 8004f4c:	bf00      	nop

  /* Ensure MPU setting take effects */
  __DSB();
  __ISB();
}
 8004f4e:	bf00      	nop
 8004f50:	370c      	adds	r7, #12
 8004f52:	46bd      	mov	sp, r7
 8004f54:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004f58:	4770      	bx	lr
 8004f5a:	bf00      	nop
 8004f5c:	e000ed90 	.word	0xe000ed90
 8004f60:	e000ed00 	.word	0xe000ed00

08004f64 <HAL_MPU_ConfigRegion>:
  * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
  *                the initialization and configuration information.
  * @retval None
  */
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
{
 8004f64:	b480      	push	{r7}
 8004f66:	b083      	sub	sp, #12
 8004f68:	af00      	add	r7, sp, #0
 8004f6a:	6078      	str	r0, [r7, #4]
  assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
  assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
  assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));

  /* Set the Region number */
  MPU->RNR = MPU_Init->Number;
 8004f6c:	687b      	ldr	r3, [r7, #4]
 8004f6e:	785a      	ldrb	r2, [r3, #1]
 8004f70:	4b1b      	ldr	r3, [pc, #108]	@ (8004fe0 <HAL_MPU_ConfigRegion+0x7c>)
 8004f72:	609a      	str	r2, [r3, #8]

  /* Disable the Region */
  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
 8004f74:	4b1a      	ldr	r3, [pc, #104]	@ (8004fe0 <HAL_MPU_ConfigRegion+0x7c>)
 8004f76:	691b      	ldr	r3, [r3, #16]
 8004f78:	4a19      	ldr	r2, [pc, #100]	@ (8004fe0 <HAL_MPU_ConfigRegion+0x7c>)
 8004f7a:	f023 0301 	bic.w	r3, r3, #1
 8004f7e:	6113      	str	r3, [r2, #16]

  /* Apply configuration */
  MPU->RBAR = MPU_Init->BaseAddress;
 8004f80:	4a17      	ldr	r2, [pc, #92]	@ (8004fe0 <HAL_MPU_ConfigRegion+0x7c>)
 8004f82:	687b      	ldr	r3, [r7, #4]
 8004f84:	685b      	ldr	r3, [r3, #4]
 8004f86:	60d3      	str	r3, [r2, #12]
  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 8004f88:	687b      	ldr	r3, [r7, #4]
 8004f8a:	7b1b      	ldrb	r3, [r3, #12]
 8004f8c:	071a      	lsls	r2, r3, #28
              ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
 8004f8e:	687b      	ldr	r3, [r7, #4]
 8004f90:	7adb      	ldrb	r3, [r3, #11]
 8004f92:	061b      	lsls	r3, r3, #24
  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 8004f94:	431a      	orrs	r2, r3
              ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
 8004f96:	687b      	ldr	r3, [r7, #4]
 8004f98:	7a9b      	ldrb	r3, [r3, #10]
 8004f9a:	04db      	lsls	r3, r3, #19
              ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
 8004f9c:	431a      	orrs	r2, r3
              ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
 8004f9e:	687b      	ldr	r3, [r7, #4]
 8004fa0:	7b5b      	ldrb	r3, [r3, #13]
 8004fa2:	049b      	lsls	r3, r3, #18
              ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
 8004fa4:	431a      	orrs	r2, r3
              ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
 8004fa6:	687b      	ldr	r3, [r7, #4]
 8004fa8:	7b9b      	ldrb	r3, [r3, #14]
 8004faa:	045b      	lsls	r3, r3, #17
              ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
 8004fac:	431a      	orrs	r2, r3
              ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
 8004fae:	687b      	ldr	r3, [r7, #4]
 8004fb0:	7bdb      	ldrb	r3, [r3, #15]
 8004fb2:	041b      	lsls	r3, r3, #16
              ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
 8004fb4:	431a      	orrs	r2, r3
              ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
 8004fb6:	687b      	ldr	r3, [r7, #4]
 8004fb8:	7a5b      	ldrb	r3, [r3, #9]
 8004fba:	021b      	lsls	r3, r3, #8
              ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
 8004fbc:	431a      	orrs	r2, r3
              ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
 8004fbe:	687b      	ldr	r3, [r7, #4]
 8004fc0:	7a1b      	ldrb	r3, [r3, #8]
 8004fc2:	005b      	lsls	r3, r3, #1
              ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
 8004fc4:	4313      	orrs	r3, r2
              ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
 8004fc6:	687a      	ldr	r2, [r7, #4]
 8004fc8:	7812      	ldrb	r2, [r2, #0]
 8004fca:	4611      	mov	r1, r2
  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 8004fcc:	4a04      	ldr	r2, [pc, #16]	@ (8004fe0 <HAL_MPU_ConfigRegion+0x7c>)
              ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
 8004fce:	430b      	orrs	r3, r1
  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 8004fd0:	6113      	str	r3, [r2, #16]
}
 8004fd2:	bf00      	nop
 8004fd4:	370c      	adds	r7, #12
 8004fd6:	46bd      	mov	sp, r7
 8004fd8:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004fdc:	4770      	bx	lr
 8004fde:	bf00      	nop
 8004fe0:	e000ed90 	.word	0xe000ed90

08004fe4 <HAL_CRC_Init>:
  *         parameters in the CRC_InitTypeDef and create the associated handle.
  * @param  hcrc CRC handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
 8004fe4:	b580      	push	{r7, lr}
 8004fe6:	b082      	sub	sp, #8
 8004fe8:	af00      	add	r7, sp, #0
 8004fea:	6078      	str	r0, [r7, #4]
  /* Check the CRC handle allocation */
  if (hcrc == NULL)
 8004fec:	687b      	ldr	r3, [r7, #4]
 8004fee:	2b00      	cmp	r3, #0
 8004ff0:	d101      	bne.n	8004ff6 <HAL_CRC_Init+0x12>
  {
    return HAL_ERROR;
 8004ff2:	2301      	movs	r3, #1
 8004ff4:	e054      	b.n	80050a0 <HAL_CRC_Init+0xbc>
  }

  /* Check the parameters */
  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));

  if (hcrc->State == HAL_CRC_STATE_RESET)
 8004ff6:	687b      	ldr	r3, [r7, #4]
 8004ff8:	7f5b      	ldrb	r3, [r3, #29]
 8004ffa:	b2db      	uxtb	r3, r3
 8004ffc:	2b00      	cmp	r3, #0
 8004ffe:	d105      	bne.n	800500c <HAL_CRC_Init+0x28>
  {
    /* Allocate lock resource and initialize it */
    hcrc->Lock = HAL_UNLOCKED;
 8005000:	687b      	ldr	r3, [r7, #4]
 8005002:	2200      	movs	r2, #0
 8005004:	771a      	strb	r2, [r3, #28]
    /* Init the low level hardware */
    HAL_CRC_MspInit(hcrc);
 8005006:	6878      	ldr	r0, [r7, #4]
 8005008:	f7fd f948 	bl	800229c <HAL_CRC_MspInit>
  }

  hcrc->State = HAL_CRC_STATE_BUSY;
 800500c:	687b      	ldr	r3, [r7, #4]
 800500e:	2202      	movs	r2, #2
 8005010:	775a      	strb	r2, [r3, #29]

  /* check whether or not non-default generating polynomial has been
   * picked up by user */
  assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
  if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
 8005012:	687b      	ldr	r3, [r7, #4]
 8005014:	791b      	ldrb	r3, [r3, #4]
 8005016:	2b00      	cmp	r3, #0
 8005018:	d10c      	bne.n	8005034 <HAL_CRC_Init+0x50>
  {
    /* initialize peripheral with default generating polynomial */
    WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
 800501a:	687b      	ldr	r3, [r7, #4]
 800501c:	681b      	ldr	r3, [r3, #0]
 800501e:	4a22      	ldr	r2, [pc, #136]	@ (80050a8 <HAL_CRC_Init+0xc4>)
 8005020:	615a      	str	r2, [r3, #20]
    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
 8005022:	687b      	ldr	r3, [r7, #4]
 8005024:	681b      	ldr	r3, [r3, #0]
 8005026:	689a      	ldr	r2, [r3, #8]
 8005028:	687b      	ldr	r3, [r7, #4]
 800502a:	681b      	ldr	r3, [r3, #0]
 800502c:	f022 0218 	bic.w	r2, r2, #24
 8005030:	609a      	str	r2, [r3, #8]
 8005032:	e00c      	b.n	800504e <HAL_CRC_Init+0x6a>
  }
  else
  {
    /* initialize CRC peripheral with generating polynomial defined by user */
    if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
 8005034:	687b      	ldr	r3, [r7, #4]
 8005036:	6899      	ldr	r1, [r3, #8]
 8005038:	687b      	ldr	r3, [r7, #4]
 800503a:	68db      	ldr	r3, [r3, #12]
 800503c:	461a      	mov	r2, r3
 800503e:	6878      	ldr	r0, [r7, #4]
 8005040:	f000 f948 	bl	80052d4 <HAL_CRCEx_Polynomial_Set>
 8005044:	4603      	mov	r3, r0
 8005046:	2b00      	cmp	r3, #0
 8005048:	d001      	beq.n	800504e <HAL_CRC_Init+0x6a>
    {
      return HAL_ERROR;
 800504a:	2301      	movs	r3, #1
 800504c:	e028      	b.n	80050a0 <HAL_CRC_Init+0xbc>
  }

  /* check whether or not non-default CRC initial value has been
   * picked up by user */
  assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
  if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
 800504e:	687b      	ldr	r3, [r7, #4]
 8005050:	795b      	ldrb	r3, [r3, #5]
 8005052:	2b00      	cmp	r3, #0
 8005054:	d105      	bne.n	8005062 <HAL_CRC_Init+0x7e>
  {
    WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
 8005056:	687b      	ldr	r3, [r7, #4]
 8005058:	681b      	ldr	r3, [r3, #0]
 800505a:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 800505e:	611a      	str	r2, [r3, #16]
 8005060:	e004      	b.n	800506c <HAL_CRC_Init+0x88>
  }
  else
  {
    WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
 8005062:	687b      	ldr	r3, [r7, #4]
 8005064:	681b      	ldr	r3, [r3, #0]
 8005066:	687a      	ldr	r2, [r7, #4]
 8005068:	6912      	ldr	r2, [r2, #16]
 800506a:	611a      	str	r2, [r3, #16]
  }


  /* set input data inversion mode */
  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
 800506c:	687b      	ldr	r3, [r7, #4]
 800506e:	681b      	ldr	r3, [r3, #0]
 8005070:	689b      	ldr	r3, [r3, #8]
 8005072:	f023 0160 	bic.w	r1, r3, #96	@ 0x60
 8005076:	687b      	ldr	r3, [r7, #4]
 8005078:	695a      	ldr	r2, [r3, #20]
 800507a:	687b      	ldr	r3, [r7, #4]
 800507c:	681b      	ldr	r3, [r3, #0]
 800507e:	430a      	orrs	r2, r1
 8005080:	609a      	str	r2, [r3, #8]

  /* set output data inversion mode */
  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
 8005082:	687b      	ldr	r3, [r7, #4]
 8005084:	681b      	ldr	r3, [r3, #0]
 8005086:	689b      	ldr	r3, [r3, #8]
 8005088:	f023 0180 	bic.w	r1, r3, #128	@ 0x80
 800508c:	687b      	ldr	r3, [r7, #4]
 800508e:	699a      	ldr	r2, [r3, #24]
 8005090:	687b      	ldr	r3, [r7, #4]
 8005092:	681b      	ldr	r3, [r3, #0]
 8005094:	430a      	orrs	r2, r1
 8005096:	609a      	str	r2, [r3, #8]
  /* makes sure the input data format (bytes, halfwords or words stream)
   * is properly specified by user */
  assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));

  /* Change CRC peripheral state */
  hcrc->State = HAL_CRC_STATE_READY;
 8005098:	687b      	ldr	r3, [r7, #4]
 800509a:	2201      	movs	r2, #1
 800509c:	775a      	strb	r2, [r3, #29]

  /* Return function status */
  return HAL_OK;
 800509e:	2300      	movs	r3, #0
}
 80050a0:	4618      	mov	r0, r3
 80050a2:	3708      	adds	r7, #8
 80050a4:	46bd      	mov	sp, r7
 80050a6:	bd80      	pop	{r7, pc}
 80050a8:	04c11db7 	.word	0x04c11db7

080050ac <HAL_CRC_Calculate>:
  *        and the API will internally adjust its input data processing based on the
  *        handle field hcrc->InputDataFormat.
  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
  */
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
 80050ac:	b580      	push	{r7, lr}
 80050ae:	b086      	sub	sp, #24
 80050b0:	af00      	add	r7, sp, #0
 80050b2:	60f8      	str	r0, [r7, #12]
 80050b4:	60b9      	str	r1, [r7, #8]
 80050b6:	607a      	str	r2, [r7, #4]
  uint32_t index;      /* CRC input data buffer index */
  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
 80050b8:	2300      	movs	r3, #0
 80050ba:	613b      	str	r3, [r7, #16]

  /* Change CRC peripheral state */
  hcrc->State = HAL_CRC_STATE_BUSY;
 80050bc:	68fb      	ldr	r3, [r7, #12]
 80050be:	2202      	movs	r2, #2
 80050c0:	775a      	strb	r2, [r3, #29]

  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
  *  written in hcrc->Instance->DR) */
  __HAL_CRC_DR_RESET(hcrc);
 80050c2:	68fb      	ldr	r3, [r7, #12]
 80050c4:	681b      	ldr	r3, [r3, #0]
 80050c6:	689a      	ldr	r2, [r3, #8]
 80050c8:	68fb      	ldr	r3, [r7, #12]
 80050ca:	681b      	ldr	r3, [r3, #0]
 80050cc:	f042 0201 	orr.w	r2, r2, #1
 80050d0:	609a      	str	r2, [r3, #8]

  switch (hcrc->InputDataFormat)
 80050d2:	68fb      	ldr	r3, [r7, #12]
 80050d4:	6a1b      	ldr	r3, [r3, #32]
 80050d6:	2b03      	cmp	r3, #3
 80050d8:	d006      	beq.n	80050e8 <HAL_CRC_Calculate+0x3c>
 80050da:	2b03      	cmp	r3, #3
 80050dc:	d829      	bhi.n	8005132 <HAL_CRC_Calculate+0x86>
 80050de:	2b01      	cmp	r3, #1
 80050e0:	d019      	beq.n	8005116 <HAL_CRC_Calculate+0x6a>
 80050e2:	2b02      	cmp	r3, #2
 80050e4:	d01e      	beq.n	8005124 <HAL_CRC_Calculate+0x78>
      /* Specific 16-bit input data handling  */
      temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
      break;

    default:
      break;
 80050e6:	e024      	b.n	8005132 <HAL_CRC_Calculate+0x86>
      for (index = 0U; index < BufferLength; index++)
 80050e8:	2300      	movs	r3, #0
 80050ea:	617b      	str	r3, [r7, #20]
 80050ec:	e00a      	b.n	8005104 <HAL_CRC_Calculate+0x58>
        hcrc->Instance->DR = pBuffer[index];
 80050ee:	697b      	ldr	r3, [r7, #20]
 80050f0:	009b      	lsls	r3, r3, #2
 80050f2:	68ba      	ldr	r2, [r7, #8]
 80050f4:	441a      	add	r2, r3
 80050f6:	68fb      	ldr	r3, [r7, #12]
 80050f8:	681b      	ldr	r3, [r3, #0]
 80050fa:	6812      	ldr	r2, [r2, #0]
 80050fc:	601a      	str	r2, [r3, #0]
      for (index = 0U; index < BufferLength; index++)
 80050fe:	697b      	ldr	r3, [r7, #20]
 8005100:	3301      	adds	r3, #1
 8005102:	617b      	str	r3, [r7, #20]
 8005104:	697a      	ldr	r2, [r7, #20]
 8005106:	687b      	ldr	r3, [r7, #4]
 8005108:	429a      	cmp	r2, r3
 800510a:	d3f0      	bcc.n	80050ee <HAL_CRC_Calculate+0x42>
      temp = hcrc->Instance->DR;
 800510c:	68fb      	ldr	r3, [r7, #12]
 800510e:	681b      	ldr	r3, [r3, #0]
 8005110:	681b      	ldr	r3, [r3, #0]
 8005112:	613b      	str	r3, [r7, #16]
      break;
 8005114:	e00e      	b.n	8005134 <HAL_CRC_Calculate+0x88>
      temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
 8005116:	687a      	ldr	r2, [r7, #4]
 8005118:	68b9      	ldr	r1, [r7, #8]
 800511a:	68f8      	ldr	r0, [r7, #12]
 800511c:	f000 f812 	bl	8005144 <CRC_Handle_8>
 8005120:	6138      	str	r0, [r7, #16]
      break;
 8005122:	e007      	b.n	8005134 <HAL_CRC_Calculate+0x88>
      temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
 8005124:	687a      	ldr	r2, [r7, #4]
 8005126:	68b9      	ldr	r1, [r7, #8]
 8005128:	68f8      	ldr	r0, [r7, #12]
 800512a:	f000 f899 	bl	8005260 <CRC_Handle_16>
 800512e:	6138      	str	r0, [r7, #16]
      break;
 8005130:	e000      	b.n	8005134 <HAL_CRC_Calculate+0x88>
      break;
 8005132:	bf00      	nop
  }

  /* Change CRC peripheral state */
  hcrc->State = HAL_CRC_STATE_READY;
 8005134:	68fb      	ldr	r3, [r7, #12]
 8005136:	2201      	movs	r2, #1
 8005138:	775a      	strb	r2, [r3, #29]

  /* Return the CRC computed value */
  return temp;
 800513a:	693b      	ldr	r3, [r7, #16]
}
 800513c:	4618      	mov	r0, r3
 800513e:	3718      	adds	r7, #24
 8005140:	46bd      	mov	sp, r7
 8005142:	bd80      	pop	{r7, pc}

08005144 <CRC_Handle_8>:
  * @param  pBuffer pointer to the input data buffer
  * @param  BufferLength input data buffer length
  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
  */
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
{
 8005144:	b480      	push	{r7}
 8005146:	b089      	sub	sp, #36	@ 0x24
 8005148:	af00      	add	r7, sp, #0
 800514a:	60f8      	str	r0, [r7, #12]
 800514c:	60b9      	str	r1, [r7, #8]
 800514e:	607a      	str	r2, [r7, #4]
  __IO uint16_t *pReg;

  /* Processing time optimization: 4 bytes are entered in a row with a single word write,
   * last bytes must be carefully fed to the CRC calculator to ensure a correct type
   * handling by the peripheral */
  for (i = 0U; i < (BufferLength / 4U); i++)
 8005150:	2300      	movs	r3, #0
 8005152:	61fb      	str	r3, [r7, #28]
 8005154:	e023      	b.n	800519e <CRC_Handle_8+0x5a>
  {
    hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
 8005156:	69fb      	ldr	r3, [r7, #28]
 8005158:	009b      	lsls	r3, r3, #2
 800515a:	68ba      	ldr	r2, [r7, #8]
 800515c:	4413      	add	r3, r2
 800515e:	781b      	ldrb	r3, [r3, #0]
 8005160:	061a      	lsls	r2, r3, #24
                         ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
 8005162:	69fb      	ldr	r3, [r7, #28]
 8005164:	009b      	lsls	r3, r3, #2
 8005166:	3301      	adds	r3, #1
 8005168:	68b9      	ldr	r1, [r7, #8]
 800516a:	440b      	add	r3, r1
 800516c:	781b      	ldrb	r3, [r3, #0]
 800516e:	041b      	lsls	r3, r3, #16
    hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
 8005170:	431a      	orrs	r2, r3
                         ((uint32_t)pBuffer[(4U * i) + 2U] << 8U)  | \
 8005172:	69fb      	ldr	r3, [r7, #28]
 8005174:	009b      	lsls	r3, r3, #2
 8005176:	3302      	adds	r3, #2
 8005178:	68b9      	ldr	r1, [r7, #8]
 800517a:	440b      	add	r3, r1
 800517c:	781b      	ldrb	r3, [r3, #0]
 800517e:	021b      	lsls	r3, r3, #8
                         ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
 8005180:	431a      	orrs	r2, r3
                         (uint32_t)pBuffer[(4U * i) + 3U];
 8005182:	69fb      	ldr	r3, [r7, #28]
 8005184:	009b      	lsls	r3, r3, #2
 8005186:	3303      	adds	r3, #3
 8005188:	68b9      	ldr	r1, [r7, #8]
 800518a:	440b      	add	r3, r1
 800518c:	781b      	ldrb	r3, [r3, #0]
 800518e:	4619      	mov	r1, r3
    hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
 8005190:	68fb      	ldr	r3, [r7, #12]
 8005192:	681b      	ldr	r3, [r3, #0]
                         ((uint32_t)pBuffer[(4U * i) + 2U] << 8U)  | \
 8005194:	430a      	orrs	r2, r1
    hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
 8005196:	601a      	str	r2, [r3, #0]
  for (i = 0U; i < (BufferLength / 4U); i++)
 8005198:	69fb      	ldr	r3, [r7, #28]
 800519a:	3301      	adds	r3, #1
 800519c:	61fb      	str	r3, [r7, #28]
 800519e:	687b      	ldr	r3, [r7, #4]
 80051a0:	089b      	lsrs	r3, r3, #2
 80051a2:	69fa      	ldr	r2, [r7, #28]
 80051a4:	429a      	cmp	r2, r3
 80051a6:	d3d6      	bcc.n	8005156 <CRC_Handle_8+0x12>
  }
  /* last bytes specific handling */
  if ((BufferLength % 4U) != 0U)
 80051a8:	687b      	ldr	r3, [r7, #4]
 80051aa:	f003 0303 	and.w	r3, r3, #3
 80051ae:	2b00      	cmp	r3, #0
 80051b0:	d04d      	beq.n	800524e <CRC_Handle_8+0x10a>
  {
    if ((BufferLength % 4U) == 1U)
 80051b2:	687b      	ldr	r3, [r7, #4]
 80051b4:	f003 0303 	and.w	r3, r3, #3
 80051b8:	2b01      	cmp	r3, #1
 80051ba:	d107      	bne.n	80051cc <CRC_Handle_8+0x88>
    {
      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i];         /* Derogation MisraC2012 R.11.5 */
 80051bc:	69fb      	ldr	r3, [r7, #28]
 80051be:	009b      	lsls	r3, r3, #2
 80051c0:	68ba      	ldr	r2, [r7, #8]
 80051c2:	4413      	add	r3, r2
 80051c4:	68fa      	ldr	r2, [r7, #12]
 80051c6:	6812      	ldr	r2, [r2, #0]
 80051c8:	781b      	ldrb	r3, [r3, #0]
 80051ca:	7013      	strb	r3, [r2, #0]
    }
    if ((BufferLength % 4U) == 2U)
 80051cc:	687b      	ldr	r3, [r7, #4]
 80051ce:	f003 0303 	and.w	r3, r3, #3
 80051d2:	2b02      	cmp	r3, #2
 80051d4:	d116      	bne.n	8005204 <CRC_Handle_8+0xc0>
    {
      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
 80051d6:	69fb      	ldr	r3, [r7, #28]
 80051d8:	009b      	lsls	r3, r3, #2
 80051da:	68ba      	ldr	r2, [r7, #8]
 80051dc:	4413      	add	r3, r2
 80051de:	781b      	ldrb	r3, [r3, #0]
 80051e0:	021b      	lsls	r3, r3, #8
 80051e2:	b21a      	sxth	r2, r3
 80051e4:	69fb      	ldr	r3, [r7, #28]
 80051e6:	009b      	lsls	r3, r3, #2
 80051e8:	3301      	adds	r3, #1
 80051ea:	68b9      	ldr	r1, [r7, #8]
 80051ec:	440b      	add	r3, r1
 80051ee:	781b      	ldrb	r3, [r3, #0]
 80051f0:	b21b      	sxth	r3, r3
 80051f2:	4313      	orrs	r3, r2
 80051f4:	b21b      	sxth	r3, r3
 80051f6:	837b      	strh	r3, [r7, #26]
      pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
 80051f8:	68fb      	ldr	r3, [r7, #12]
 80051fa:	681b      	ldr	r3, [r3, #0]
 80051fc:	617b      	str	r3, [r7, #20]
      *pReg = data;
 80051fe:	697b      	ldr	r3, [r7, #20]
 8005200:	8b7a      	ldrh	r2, [r7, #26]
 8005202:	801a      	strh	r2, [r3, #0]
    }
    if ((BufferLength % 4U) == 3U)
 8005204:	687b      	ldr	r3, [r7, #4]
 8005206:	f003 0303 	and.w	r3, r3, #3
 800520a:	2b03      	cmp	r3, #3
 800520c:	d11f      	bne.n	800524e <CRC_Handle_8+0x10a>
    {
      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
 800520e:	69fb      	ldr	r3, [r7, #28]
 8005210:	009b      	lsls	r3, r3, #2
 8005212:	68ba      	ldr	r2, [r7, #8]
 8005214:	4413      	add	r3, r2
 8005216:	781b      	ldrb	r3, [r3, #0]
 8005218:	021b      	lsls	r3, r3, #8
 800521a:	b21a      	sxth	r2, r3
 800521c:	69fb      	ldr	r3, [r7, #28]
 800521e:	009b      	lsls	r3, r3, #2
 8005220:	3301      	adds	r3, #1
 8005222:	68b9      	ldr	r1, [r7, #8]
 8005224:	440b      	add	r3, r1
 8005226:	781b      	ldrb	r3, [r3, #0]
 8005228:	b21b      	sxth	r3, r3
 800522a:	4313      	orrs	r3, r2
 800522c:	b21b      	sxth	r3, r3
 800522e:	837b      	strh	r3, [r7, #26]
      pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
 8005230:	68fb      	ldr	r3, [r7, #12]
 8005232:	681b      	ldr	r3, [r3, #0]
 8005234:	617b      	str	r3, [r7, #20]
      *pReg = data;
 8005236:	697b      	ldr	r3, [r7, #20]
 8005238:	8b7a      	ldrh	r2, [r7, #26]
 800523a:	801a      	strh	r2, [r3, #0]

      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U];  /* Derogation MisraC2012 R.11.5 */
 800523c:	69fb      	ldr	r3, [r7, #28]
 800523e:	009b      	lsls	r3, r3, #2
 8005240:	3302      	adds	r3, #2
 8005242:	68ba      	ldr	r2, [r7, #8]
 8005244:	4413      	add	r3, r2
 8005246:	68fa      	ldr	r2, [r7, #12]
 8005248:	6812      	ldr	r2, [r2, #0]
 800524a:	781b      	ldrb	r3, [r3, #0]
 800524c:	7013      	strb	r3, [r2, #0]
    }
  }

  /* Return the CRC computed value */
  return hcrc->Instance->DR;
 800524e:	68fb      	ldr	r3, [r7, #12]
 8005250:	681b      	ldr	r3, [r3, #0]
 8005252:	681b      	ldr	r3, [r3, #0]
}
 8005254:	4618      	mov	r0, r3
 8005256:	3724      	adds	r7, #36	@ 0x24
 8005258:	46bd      	mov	sp, r7
 800525a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800525e:	4770      	bx	lr

08005260 <CRC_Handle_16>:
  * @param  pBuffer pointer to the input data buffer
  * @param  BufferLength input data buffer length
  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
  */
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{
 8005260:	b480      	push	{r7}
 8005262:	b087      	sub	sp, #28
 8005264:	af00      	add	r7, sp, #0
 8005266:	60f8      	str	r0, [r7, #12]
 8005268:	60b9      	str	r1, [r7, #8]
 800526a:	607a      	str	r2, [r7, #4]
  __IO uint16_t *pReg;

  /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
   * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
   * a correct type handling by the peripheral */
  for (i = 0U; i < (BufferLength / 2U); i++)
 800526c:	2300      	movs	r3, #0
 800526e:	617b      	str	r3, [r7, #20]
 8005270:	e013      	b.n	800529a <CRC_Handle_16+0x3a>
  {
    hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
 8005272:	697b      	ldr	r3, [r7, #20]
 8005274:	009b      	lsls	r3, r3, #2
 8005276:	68ba      	ldr	r2, [r7, #8]
 8005278:	4413      	add	r3, r2
 800527a:	881b      	ldrh	r3, [r3, #0]
 800527c:	041a      	lsls	r2, r3, #16
 800527e:	697b      	ldr	r3, [r7, #20]
 8005280:	009b      	lsls	r3, r3, #2
 8005282:	3302      	adds	r3, #2
 8005284:	68b9      	ldr	r1, [r7, #8]
 8005286:	440b      	add	r3, r1
 8005288:	881b      	ldrh	r3, [r3, #0]
 800528a:	4619      	mov	r1, r3
 800528c:	68fb      	ldr	r3, [r7, #12]
 800528e:	681b      	ldr	r3, [r3, #0]
 8005290:	430a      	orrs	r2, r1
 8005292:	601a      	str	r2, [r3, #0]
  for (i = 0U; i < (BufferLength / 2U); i++)
 8005294:	697b      	ldr	r3, [r7, #20]
 8005296:	3301      	adds	r3, #1
 8005298:	617b      	str	r3, [r7, #20]
 800529a:	687b      	ldr	r3, [r7, #4]
 800529c:	085b      	lsrs	r3, r3, #1
 800529e:	697a      	ldr	r2, [r7, #20]
 80052a0:	429a      	cmp	r2, r3
 80052a2:	d3e6      	bcc.n	8005272 <CRC_Handle_16+0x12>
  }
  if ((BufferLength % 2U) != 0U)
 80052a4:	687b      	ldr	r3, [r7, #4]
 80052a6:	f003 0301 	and.w	r3, r3, #1
 80052aa:	2b00      	cmp	r3, #0
 80052ac:	d009      	beq.n	80052c2 <CRC_Handle_16+0x62>
  {
    pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                 /* Derogation MisraC2012 R.11.5 */
 80052ae:	68fb      	ldr	r3, [r7, #12]
 80052b0:	681b      	ldr	r3, [r3, #0]
 80052b2:	613b      	str	r3, [r7, #16]
    *pReg = pBuffer[2U * i];
 80052b4:	697b      	ldr	r3, [r7, #20]
 80052b6:	009b      	lsls	r3, r3, #2
 80052b8:	68ba      	ldr	r2, [r7, #8]
 80052ba:	4413      	add	r3, r2
 80052bc:	881a      	ldrh	r2, [r3, #0]
 80052be:	693b      	ldr	r3, [r7, #16]
 80052c0:	801a      	strh	r2, [r3, #0]
  }

  /* Return the CRC computed value */
  return hcrc->Instance->DR;
 80052c2:	68fb      	ldr	r3, [r7, #12]
 80052c4:	681b      	ldr	r3, [r3, #0]
 80052c6:	681b      	ldr	r3, [r3, #0]
}
 80052c8:	4618      	mov	r0, r3
 80052ca:	371c      	adds	r7, #28
 80052cc:	46bd      	mov	sp, r7
 80052ce:	f85d 7b04 	ldr.w	r7, [sp], #4
 80052d2:	4770      	bx	lr

080052d4 <HAL_CRCEx_Polynomial_Set>:
  *          @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
  *          @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
 80052d4:	b480      	push	{r7}
 80052d6:	b087      	sub	sp, #28
 80052d8:	af00      	add	r7, sp, #0
 80052da:	60f8      	str	r0, [r7, #12]
 80052dc:	60b9      	str	r1, [r7, #8]
 80052de:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 80052e0:	2300      	movs	r3, #0
 80052e2:	75fb      	strb	r3, [r7, #23]
  uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
 80052e4:	231f      	movs	r3, #31
 80052e6:	613b      	str	r3, [r7, #16]

  /* Check the parameters */
  assert_param(IS_CRC_POL_LENGTH(PolyLength));

  /* Ensure that the generating polynomial is odd */
  if ((Pol & (uint32_t)(0x1U)) ==  0U)
 80052e8:	68bb      	ldr	r3, [r7, #8]
 80052ea:	f003 0301 	and.w	r3, r3, #1
 80052ee:	2b00      	cmp	r3, #0
 80052f0:	d102      	bne.n	80052f8 <HAL_CRCEx_Polynomial_Set+0x24>
  {
    status =  HAL_ERROR;
 80052f2:	2301      	movs	r3, #1
 80052f4:	75fb      	strb	r3, [r7, #23]
 80052f6:	e063      	b.n	80053c0 <HAL_CRCEx_Polynomial_Set+0xec>
     * definition. HAL_ERROR is reported if Pol degree is
     * larger than that indicated by PolyLength.
     * Look for MSB position: msb will contain the degree of
     *  the second to the largest polynomial member. E.g., for
     *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
    while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
 80052f8:	bf00      	nop
 80052fa:	693b      	ldr	r3, [r7, #16]
 80052fc:	1e5a      	subs	r2, r3, #1
 80052fe:	613a      	str	r2, [r7, #16]
 8005300:	2b00      	cmp	r3, #0
 8005302:	d009      	beq.n	8005318 <HAL_CRCEx_Polynomial_Set+0x44>
 8005304:	693b      	ldr	r3, [r7, #16]
 8005306:	f003 031f 	and.w	r3, r3, #31
 800530a:	68ba      	ldr	r2, [r7, #8]
 800530c:	fa22 f303 	lsr.w	r3, r2, r3
 8005310:	f003 0301 	and.w	r3, r3, #1
 8005314:	2b00      	cmp	r3, #0
 8005316:	d0f0      	beq.n	80052fa <HAL_CRCEx_Polynomial_Set+0x26>
    {
    }

    switch (PolyLength)
 8005318:	687b      	ldr	r3, [r7, #4]
 800531a:	2b18      	cmp	r3, #24
 800531c:	d846      	bhi.n	80053ac <HAL_CRCEx_Polynomial_Set+0xd8>
 800531e:	a201      	add	r2, pc, #4	@ (adr r2, 8005324 <HAL_CRCEx_Polynomial_Set+0x50>)
 8005320:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8005324:	080053b3 	.word	0x080053b3
 8005328:	080053ad 	.word	0x080053ad
 800532c:	080053ad 	.word	0x080053ad
 8005330:	080053ad 	.word	0x080053ad
 8005334:	080053ad 	.word	0x080053ad
 8005338:	080053ad 	.word	0x080053ad
 800533c:	080053ad 	.word	0x080053ad
 8005340:	080053ad 	.word	0x080053ad
 8005344:	080053a1 	.word	0x080053a1
 8005348:	080053ad 	.word	0x080053ad
 800534c:	080053ad 	.word	0x080053ad
 8005350:	080053ad 	.word	0x080053ad
 8005354:	080053ad 	.word	0x080053ad
 8005358:	080053ad 	.word	0x080053ad
 800535c:	080053ad 	.word	0x080053ad
 8005360:	080053ad 	.word	0x080053ad
 8005364:	08005395 	.word	0x08005395
 8005368:	080053ad 	.word	0x080053ad
 800536c:	080053ad 	.word	0x080053ad
 8005370:	080053ad 	.word	0x080053ad
 8005374:	080053ad 	.word	0x080053ad
 8005378:	080053ad 	.word	0x080053ad
 800537c:	080053ad 	.word	0x080053ad
 8005380:	080053ad 	.word	0x080053ad
 8005384:	08005389 	.word	0x08005389
    {

      case CRC_POLYLENGTH_7B:
        if (msb >= HAL_CRC_LENGTH_7B)
 8005388:	693b      	ldr	r3, [r7, #16]
 800538a:	2b06      	cmp	r3, #6
 800538c:	d913      	bls.n	80053b6 <HAL_CRCEx_Polynomial_Set+0xe2>
        {
          status =   HAL_ERROR;
 800538e:	2301      	movs	r3, #1
 8005390:	75fb      	strb	r3, [r7, #23]
        }
        break;
 8005392:	e010      	b.n	80053b6 <HAL_CRCEx_Polynomial_Set+0xe2>
      case CRC_POLYLENGTH_8B:
        if (msb >= HAL_CRC_LENGTH_8B)
 8005394:	693b      	ldr	r3, [r7, #16]
 8005396:	2b07      	cmp	r3, #7
 8005398:	d90f      	bls.n	80053ba <HAL_CRCEx_Polynomial_Set+0xe6>
        {
          status =   HAL_ERROR;
 800539a:	2301      	movs	r3, #1
 800539c:	75fb      	strb	r3, [r7, #23]
        }
        break;
 800539e:	e00c      	b.n	80053ba <HAL_CRCEx_Polynomial_Set+0xe6>
      case CRC_POLYLENGTH_16B:
        if (msb >= HAL_CRC_LENGTH_16B)
 80053a0:	693b      	ldr	r3, [r7, #16]
 80053a2:	2b0f      	cmp	r3, #15
 80053a4:	d90b      	bls.n	80053be <HAL_CRCEx_Polynomial_Set+0xea>
        {
          status =   HAL_ERROR;
 80053a6:	2301      	movs	r3, #1
 80053a8:	75fb      	strb	r3, [r7, #23]
        }
        break;
 80053aa:	e008      	b.n	80053be <HAL_CRCEx_Polynomial_Set+0xea>

      case CRC_POLYLENGTH_32B:
        /* no polynomial definition vs. polynomial length issue possible */
        break;
      default:
        status =  HAL_ERROR;
 80053ac:	2301      	movs	r3, #1
 80053ae:	75fb      	strb	r3, [r7, #23]
        break;
 80053b0:	e006      	b.n	80053c0 <HAL_CRCEx_Polynomial_Set+0xec>
        break;
 80053b2:	bf00      	nop
 80053b4:	e004      	b.n	80053c0 <HAL_CRCEx_Polynomial_Set+0xec>
        break;
 80053b6:	bf00      	nop
 80053b8:	e002      	b.n	80053c0 <HAL_CRCEx_Polynomial_Set+0xec>
        break;
 80053ba:	bf00      	nop
 80053bc:	e000      	b.n	80053c0 <HAL_CRCEx_Polynomial_Set+0xec>
        break;
 80053be:	bf00      	nop
    }
  }
  if (status == HAL_OK)
 80053c0:	7dfb      	ldrb	r3, [r7, #23]
 80053c2:	2b00      	cmp	r3, #0
 80053c4:	d10d      	bne.n	80053e2 <HAL_CRCEx_Polynomial_Set+0x10e>
  {
    /* set generating polynomial */
    WRITE_REG(hcrc->Instance->POL, Pol);
 80053c6:	68fb      	ldr	r3, [r7, #12]
 80053c8:	681b      	ldr	r3, [r3, #0]
 80053ca:	68ba      	ldr	r2, [r7, #8]
 80053cc:	615a      	str	r2, [r3, #20]

    /* set generating polynomial size */
    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
 80053ce:	68fb      	ldr	r3, [r7, #12]
 80053d0:	681b      	ldr	r3, [r3, #0]
 80053d2:	689b      	ldr	r3, [r3, #8]
 80053d4:	f023 0118 	bic.w	r1, r3, #24
 80053d8:	68fb      	ldr	r3, [r7, #12]
 80053da:	681b      	ldr	r3, [r3, #0]
 80053dc:	687a      	ldr	r2, [r7, #4]
 80053de:	430a      	orrs	r2, r1
 80053e0:	609a      	str	r2, [r3, #8]
  }
  /* Return function status */
  return status;
 80053e2:	7dfb      	ldrb	r3, [r7, #23]
}
 80053e4:	4618      	mov	r0, r3
 80053e6:	371c      	adds	r7, #28
 80053e8:	46bd      	mov	sp, r7
 80053ea:	f85d 7b04 	ldr.w	r7, [sp], #4
 80053ee:	4770      	bx	lr

080053f0 <HAL_DMA_Init>:
  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Stream.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 80053f0:	b580      	push	{r7, lr}
 80053f2:	b086      	sub	sp, #24
 80053f4:	af00      	add	r7, sp, #0
 80053f6:	6078      	str	r0, [r7, #4]
  uint32_t registerValue;
  uint32_t tickstart = HAL_GetTick();
 80053f8:	f7fe f864 	bl	80034c4 <HAL_GetTick>
 80053fc:	6138      	str	r0, [r7, #16]
  DMA_Base_Registers *regs_dma;
  BDMA_Base_Registers *regs_bdma;

  /* Check the DMA peripheral handle */
  if(hdma == NULL)
 80053fe:	687b      	ldr	r3, [r7, #4]
 8005400:	2b00      	cmp	r3, #0
 8005402:	d101      	bne.n	8005408 <HAL_DMA_Init+0x18>
  {
    return HAL_ERROR;
 8005404:	2301      	movs	r3, #1
 8005406:	e316      	b.n	8005a36 <HAL_DMA_Init+0x646>
  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));

  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 8005408:	687b      	ldr	r3, [r7, #4]
 800540a:	681b      	ldr	r3, [r3, #0]
 800540c:	4a66      	ldr	r2, [pc, #408]	@ (80055a8 <HAL_DMA_Init+0x1b8>)
 800540e:	4293      	cmp	r3, r2
 8005410:	d04a      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 8005412:	687b      	ldr	r3, [r7, #4]
 8005414:	681b      	ldr	r3, [r3, #0]
 8005416:	4a65      	ldr	r2, [pc, #404]	@ (80055ac <HAL_DMA_Init+0x1bc>)
 8005418:	4293      	cmp	r3, r2
 800541a:	d045      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 800541c:	687b      	ldr	r3, [r7, #4]
 800541e:	681b      	ldr	r3, [r3, #0]
 8005420:	4a63      	ldr	r2, [pc, #396]	@ (80055b0 <HAL_DMA_Init+0x1c0>)
 8005422:	4293      	cmp	r3, r2
 8005424:	d040      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 8005426:	687b      	ldr	r3, [r7, #4]
 8005428:	681b      	ldr	r3, [r3, #0]
 800542a:	4a62      	ldr	r2, [pc, #392]	@ (80055b4 <HAL_DMA_Init+0x1c4>)
 800542c:	4293      	cmp	r3, r2
 800542e:	d03b      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 8005430:	687b      	ldr	r3, [r7, #4]
 8005432:	681b      	ldr	r3, [r3, #0]
 8005434:	4a60      	ldr	r2, [pc, #384]	@ (80055b8 <HAL_DMA_Init+0x1c8>)
 8005436:	4293      	cmp	r3, r2
 8005438:	d036      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 800543a:	687b      	ldr	r3, [r7, #4]
 800543c:	681b      	ldr	r3, [r3, #0]
 800543e:	4a5f      	ldr	r2, [pc, #380]	@ (80055bc <HAL_DMA_Init+0x1cc>)
 8005440:	4293      	cmp	r3, r2
 8005442:	d031      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 8005444:	687b      	ldr	r3, [r7, #4]
 8005446:	681b      	ldr	r3, [r3, #0]
 8005448:	4a5d      	ldr	r2, [pc, #372]	@ (80055c0 <HAL_DMA_Init+0x1d0>)
 800544a:	4293      	cmp	r3, r2
 800544c:	d02c      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 800544e:	687b      	ldr	r3, [r7, #4]
 8005450:	681b      	ldr	r3, [r3, #0]
 8005452:	4a5c      	ldr	r2, [pc, #368]	@ (80055c4 <HAL_DMA_Init+0x1d4>)
 8005454:	4293      	cmp	r3, r2
 8005456:	d027      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 8005458:	687b      	ldr	r3, [r7, #4]
 800545a:	681b      	ldr	r3, [r3, #0]
 800545c:	4a5a      	ldr	r2, [pc, #360]	@ (80055c8 <HAL_DMA_Init+0x1d8>)
 800545e:	4293      	cmp	r3, r2
 8005460:	d022      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 8005462:	687b      	ldr	r3, [r7, #4]
 8005464:	681b      	ldr	r3, [r3, #0]
 8005466:	4a59      	ldr	r2, [pc, #356]	@ (80055cc <HAL_DMA_Init+0x1dc>)
 8005468:	4293      	cmp	r3, r2
 800546a:	d01d      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 800546c:	687b      	ldr	r3, [r7, #4]
 800546e:	681b      	ldr	r3, [r3, #0]
 8005470:	4a57      	ldr	r2, [pc, #348]	@ (80055d0 <HAL_DMA_Init+0x1e0>)
 8005472:	4293      	cmp	r3, r2
 8005474:	d018      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 8005476:	687b      	ldr	r3, [r7, #4]
 8005478:	681b      	ldr	r3, [r3, #0]
 800547a:	4a56      	ldr	r2, [pc, #344]	@ (80055d4 <HAL_DMA_Init+0x1e4>)
 800547c:	4293      	cmp	r3, r2
 800547e:	d013      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 8005480:	687b      	ldr	r3, [r7, #4]
 8005482:	681b      	ldr	r3, [r3, #0]
 8005484:	4a54      	ldr	r2, [pc, #336]	@ (80055d8 <HAL_DMA_Init+0x1e8>)
 8005486:	4293      	cmp	r3, r2
 8005488:	d00e      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 800548a:	687b      	ldr	r3, [r7, #4]
 800548c:	681b      	ldr	r3, [r3, #0]
 800548e:	4a53      	ldr	r2, [pc, #332]	@ (80055dc <HAL_DMA_Init+0x1ec>)
 8005490:	4293      	cmp	r3, r2
 8005492:	d009      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 8005494:	687b      	ldr	r3, [r7, #4]
 8005496:	681b      	ldr	r3, [r3, #0]
 8005498:	4a51      	ldr	r2, [pc, #324]	@ (80055e0 <HAL_DMA_Init+0x1f0>)
 800549a:	4293      	cmp	r3, r2
 800549c:	d004      	beq.n	80054a8 <HAL_DMA_Init+0xb8>
 800549e:	687b      	ldr	r3, [r7, #4]
 80054a0:	681b      	ldr	r3, [r3, #0]
 80054a2:	4a50      	ldr	r2, [pc, #320]	@ (80055e4 <HAL_DMA_Init+0x1f4>)
 80054a4:	4293      	cmp	r3, r2
 80054a6:	d101      	bne.n	80054ac <HAL_DMA_Init+0xbc>
 80054a8:	2301      	movs	r3, #1
 80054aa:	e000      	b.n	80054ae <HAL_DMA_Init+0xbe>
 80054ac:	2300      	movs	r3, #0
 80054ae:	2b00      	cmp	r3, #0
 80054b0:	f000 813b 	beq.w	800572a <HAL_DMA_Init+0x33a>
      assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
      assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
    }

    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 80054b4:	687b      	ldr	r3, [r7, #4]
 80054b6:	2202      	movs	r2, #2
 80054b8:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

    /* Allocate lock resource */
    __HAL_UNLOCK(hdma);
 80054bc:	687b      	ldr	r3, [r7, #4]
 80054be:	2200      	movs	r2, #0
 80054c0:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);
 80054c4:	687b      	ldr	r3, [r7, #4]
 80054c6:	681b      	ldr	r3, [r3, #0]
 80054c8:	4a37      	ldr	r2, [pc, #220]	@ (80055a8 <HAL_DMA_Init+0x1b8>)
 80054ca:	4293      	cmp	r3, r2
 80054cc:	d04a      	beq.n	8005564 <HAL_DMA_Init+0x174>
 80054ce:	687b      	ldr	r3, [r7, #4]
 80054d0:	681b      	ldr	r3, [r3, #0]
 80054d2:	4a36      	ldr	r2, [pc, #216]	@ (80055ac <HAL_DMA_Init+0x1bc>)
 80054d4:	4293      	cmp	r3, r2
 80054d6:	d045      	beq.n	8005564 <HAL_DMA_Init+0x174>
 80054d8:	687b      	ldr	r3, [r7, #4]
 80054da:	681b      	ldr	r3, [r3, #0]
 80054dc:	4a34      	ldr	r2, [pc, #208]	@ (80055b0 <HAL_DMA_Init+0x1c0>)
 80054de:	4293      	cmp	r3, r2
 80054e0:	d040      	beq.n	8005564 <HAL_DMA_Init+0x174>
 80054e2:	687b      	ldr	r3, [r7, #4]
 80054e4:	681b      	ldr	r3, [r3, #0]
 80054e6:	4a33      	ldr	r2, [pc, #204]	@ (80055b4 <HAL_DMA_Init+0x1c4>)
 80054e8:	4293      	cmp	r3, r2
 80054ea:	d03b      	beq.n	8005564 <HAL_DMA_Init+0x174>
 80054ec:	687b      	ldr	r3, [r7, #4]
 80054ee:	681b      	ldr	r3, [r3, #0]
 80054f0:	4a31      	ldr	r2, [pc, #196]	@ (80055b8 <HAL_DMA_Init+0x1c8>)
 80054f2:	4293      	cmp	r3, r2
 80054f4:	d036      	beq.n	8005564 <HAL_DMA_Init+0x174>
 80054f6:	687b      	ldr	r3, [r7, #4]
 80054f8:	681b      	ldr	r3, [r3, #0]
 80054fa:	4a30      	ldr	r2, [pc, #192]	@ (80055bc <HAL_DMA_Init+0x1cc>)
 80054fc:	4293      	cmp	r3, r2
 80054fe:	d031      	beq.n	8005564 <HAL_DMA_Init+0x174>
 8005500:	687b      	ldr	r3, [r7, #4]
 8005502:	681b      	ldr	r3, [r3, #0]
 8005504:	4a2e      	ldr	r2, [pc, #184]	@ (80055c0 <HAL_DMA_Init+0x1d0>)
 8005506:	4293      	cmp	r3, r2
 8005508:	d02c      	beq.n	8005564 <HAL_DMA_Init+0x174>
 800550a:	687b      	ldr	r3, [r7, #4]
 800550c:	681b      	ldr	r3, [r3, #0]
 800550e:	4a2d      	ldr	r2, [pc, #180]	@ (80055c4 <HAL_DMA_Init+0x1d4>)
 8005510:	4293      	cmp	r3, r2
 8005512:	d027      	beq.n	8005564 <HAL_DMA_Init+0x174>
 8005514:	687b      	ldr	r3, [r7, #4]
 8005516:	681b      	ldr	r3, [r3, #0]
 8005518:	4a2b      	ldr	r2, [pc, #172]	@ (80055c8 <HAL_DMA_Init+0x1d8>)
 800551a:	4293      	cmp	r3, r2
 800551c:	d022      	beq.n	8005564 <HAL_DMA_Init+0x174>
 800551e:	687b      	ldr	r3, [r7, #4]
 8005520:	681b      	ldr	r3, [r3, #0]
 8005522:	4a2a      	ldr	r2, [pc, #168]	@ (80055cc <HAL_DMA_Init+0x1dc>)
 8005524:	4293      	cmp	r3, r2
 8005526:	d01d      	beq.n	8005564 <HAL_DMA_Init+0x174>
 8005528:	687b      	ldr	r3, [r7, #4]
 800552a:	681b      	ldr	r3, [r3, #0]
 800552c:	4a28      	ldr	r2, [pc, #160]	@ (80055d0 <HAL_DMA_Init+0x1e0>)
 800552e:	4293      	cmp	r3, r2
 8005530:	d018      	beq.n	8005564 <HAL_DMA_Init+0x174>
 8005532:	687b      	ldr	r3, [r7, #4]
 8005534:	681b      	ldr	r3, [r3, #0]
 8005536:	4a27      	ldr	r2, [pc, #156]	@ (80055d4 <HAL_DMA_Init+0x1e4>)
 8005538:	4293      	cmp	r3, r2
 800553a:	d013      	beq.n	8005564 <HAL_DMA_Init+0x174>
 800553c:	687b      	ldr	r3, [r7, #4]
 800553e:	681b      	ldr	r3, [r3, #0]
 8005540:	4a25      	ldr	r2, [pc, #148]	@ (80055d8 <HAL_DMA_Init+0x1e8>)
 8005542:	4293      	cmp	r3, r2
 8005544:	d00e      	beq.n	8005564 <HAL_DMA_Init+0x174>
 8005546:	687b      	ldr	r3, [r7, #4]
 8005548:	681b      	ldr	r3, [r3, #0]
 800554a:	4a24      	ldr	r2, [pc, #144]	@ (80055dc <HAL_DMA_Init+0x1ec>)
 800554c:	4293      	cmp	r3, r2
 800554e:	d009      	beq.n	8005564 <HAL_DMA_Init+0x174>
 8005550:	687b      	ldr	r3, [r7, #4]
 8005552:	681b      	ldr	r3, [r3, #0]
 8005554:	4a22      	ldr	r2, [pc, #136]	@ (80055e0 <HAL_DMA_Init+0x1f0>)
 8005556:	4293      	cmp	r3, r2
 8005558:	d004      	beq.n	8005564 <HAL_DMA_Init+0x174>
 800555a:	687b      	ldr	r3, [r7, #4]
 800555c:	681b      	ldr	r3, [r3, #0]
 800555e:	4a21      	ldr	r2, [pc, #132]	@ (80055e4 <HAL_DMA_Init+0x1f4>)
 8005560:	4293      	cmp	r3, r2
 8005562:	d108      	bne.n	8005576 <HAL_DMA_Init+0x186>
 8005564:	687b      	ldr	r3, [r7, #4]
 8005566:	681b      	ldr	r3, [r3, #0]
 8005568:	681a      	ldr	r2, [r3, #0]
 800556a:	687b      	ldr	r3, [r7, #4]
 800556c:	681b      	ldr	r3, [r3, #0]
 800556e:	f022 0201 	bic.w	r2, r2, #1
 8005572:	601a      	str	r2, [r3, #0]
 8005574:	e007      	b.n	8005586 <HAL_DMA_Init+0x196>
 8005576:	687b      	ldr	r3, [r7, #4]
 8005578:	681b      	ldr	r3, [r3, #0]
 800557a:	681a      	ldr	r2, [r3, #0]
 800557c:	687b      	ldr	r3, [r7, #4]
 800557e:	681b      	ldr	r3, [r3, #0]
 8005580:	f022 0201 	bic.w	r2, r2, #1
 8005584:	601a      	str	r2, [r3, #0]

    /* Check if the DMA Stream is effectively disabled */
    while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
 8005586:	e02f      	b.n	80055e8 <HAL_DMA_Init+0x1f8>
    {
      /* Check for the Timeout */
      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
 8005588:	f7fd ff9c 	bl	80034c4 <HAL_GetTick>
 800558c:	4602      	mov	r2, r0
 800558e:	693b      	ldr	r3, [r7, #16]
 8005590:	1ad3      	subs	r3, r2, r3
 8005592:	2b05      	cmp	r3, #5
 8005594:	d928      	bls.n	80055e8 <HAL_DMA_Init+0x1f8>
      {
        /* Update error code */
        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
 8005596:	687b      	ldr	r3, [r7, #4]
 8005598:	2220      	movs	r2, #32
 800559a:	655a      	str	r2, [r3, #84]	@ 0x54

        /* Change the DMA state */
        hdma->State = HAL_DMA_STATE_ERROR;
 800559c:	687b      	ldr	r3, [r7, #4]
 800559e:	2203      	movs	r2, #3
 80055a0:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

        return HAL_ERROR;
 80055a4:	2301      	movs	r3, #1
 80055a6:	e246      	b.n	8005a36 <HAL_DMA_Init+0x646>
 80055a8:	40020010 	.word	0x40020010
 80055ac:	40020028 	.word	0x40020028
 80055b0:	40020040 	.word	0x40020040
 80055b4:	40020058 	.word	0x40020058
 80055b8:	40020070 	.word	0x40020070
 80055bc:	40020088 	.word	0x40020088
 80055c0:	400200a0 	.word	0x400200a0
 80055c4:	400200b8 	.word	0x400200b8
 80055c8:	40020410 	.word	0x40020410
 80055cc:	40020428 	.word	0x40020428
 80055d0:	40020440 	.word	0x40020440
 80055d4:	40020458 	.word	0x40020458
 80055d8:	40020470 	.word	0x40020470
 80055dc:	40020488 	.word	0x40020488
 80055e0:	400204a0 	.word	0x400204a0
 80055e4:	400204b8 	.word	0x400204b8
    while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
 80055e8:	687b      	ldr	r3, [r7, #4]
 80055ea:	681b      	ldr	r3, [r3, #0]
 80055ec:	681b      	ldr	r3, [r3, #0]
 80055ee:	f003 0301 	and.w	r3, r3, #1
 80055f2:	2b00      	cmp	r3, #0
 80055f4:	d1c8      	bne.n	8005588 <HAL_DMA_Init+0x198>
      }
    }

    /* Get the CR register value */
    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->CR;
 80055f6:	687b      	ldr	r3, [r7, #4]
 80055f8:	681b      	ldr	r3, [r3, #0]
 80055fa:	681b      	ldr	r3, [r3, #0]
 80055fc:	617b      	str	r3, [r7, #20]

    /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
    registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
 80055fe:	697a      	ldr	r2, [r7, #20]
 8005600:	4b83      	ldr	r3, [pc, #524]	@ (8005810 <HAL_DMA_Init+0x420>)
 8005602:	4013      	ands	r3, r2
 8005604:	617b      	str	r3, [r7, #20]
                        DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
                        DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
                        DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));

    /* Prepare the DMA Stream configuration */
    registerValue |=  hdma->Init.Direction           |
 8005606:	687b      	ldr	r3, [r7, #4]
 8005608:	689a      	ldr	r2, [r3, #8]
            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 800560a:	687b      	ldr	r3, [r7, #4]
 800560c:	68db      	ldr	r3, [r3, #12]
    registerValue |=  hdma->Init.Direction           |
 800560e:	431a      	orrs	r2, r3
            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8005610:	687b      	ldr	r3, [r7, #4]
 8005612:	691b      	ldr	r3, [r3, #16]
 8005614:	431a      	orrs	r2, r3
            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8005616:	687b      	ldr	r3, [r7, #4]
 8005618:	695b      	ldr	r3, [r3, #20]
            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 800561a:	431a      	orrs	r2, r3
            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 800561c:	687b      	ldr	r3, [r7, #4]
 800561e:	699b      	ldr	r3, [r3, #24]
 8005620:	431a      	orrs	r2, r3
            hdma->Init.Mode                | hdma->Init.Priority;
 8005622:	687b      	ldr	r3, [r7, #4]
 8005624:	69db      	ldr	r3, [r3, #28]
            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8005626:	431a      	orrs	r2, r3
            hdma->Init.Mode                | hdma->Init.Priority;
 8005628:	687b      	ldr	r3, [r7, #4]
 800562a:	6a1b      	ldr	r3, [r3, #32]
 800562c:	4313      	orrs	r3, r2
    registerValue |=  hdma->Init.Direction           |
 800562e:	697a      	ldr	r2, [r7, #20]
 8005630:	4313      	orrs	r3, r2
 8005632:	617b      	str	r3, [r7, #20]

    /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
 8005634:	687b      	ldr	r3, [r7, #4]
 8005636:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8005638:	2b04      	cmp	r3, #4
 800563a:	d107      	bne.n	800564c <HAL_DMA_Init+0x25c>
    {
      /* Get memory burst and peripheral burst */
      registerValue |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
 800563c:	687b      	ldr	r3, [r7, #4]
 800563e:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8005640:	687b      	ldr	r3, [r7, #4]
 8005642:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8005644:	4313      	orrs	r3, r2
 8005646:	697a      	ldr	r2, [r7, #20]
 8005648:	4313      	orrs	r3, r2
 800564a:	617b      	str	r3, [r7, #20]
    }

    /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
                                    lock when transferring data to/from USART/UART */
#if (STM32H7_DEV_ID == 0x450UL)
    if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
 800564c:	4b71      	ldr	r3, [pc, #452]	@ (8005814 <HAL_DMA_Init+0x424>)
 800564e:	681a      	ldr	r2, [r3, #0]
 8005650:	4b71      	ldr	r3, [pc, #452]	@ (8005818 <HAL_DMA_Init+0x428>)
 8005652:	4013      	ands	r3, r2
 8005654:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 8005658:	d328      	bcc.n	80056ac <HAL_DMA_Init+0x2bc>
    {
#endif /* STM32H7_DEV_ID == 0x450UL */
      if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
 800565a:	687b      	ldr	r3, [r7, #4]
 800565c:	685b      	ldr	r3, [r3, #4]
 800565e:	2b28      	cmp	r3, #40	@ 0x28
 8005660:	d903      	bls.n	800566a <HAL_DMA_Init+0x27a>
 8005662:	687b      	ldr	r3, [r7, #4]
 8005664:	685b      	ldr	r3, [r3, #4]
 8005666:	2b2e      	cmp	r3, #46	@ 0x2e
 8005668:	d917      	bls.n	800569a <HAL_DMA_Init+0x2aa>
 800566a:	687b      	ldr	r3, [r7, #4]
 800566c:	685b      	ldr	r3, [r3, #4]
 800566e:	2b3e      	cmp	r3, #62	@ 0x3e
 8005670:	d903      	bls.n	800567a <HAL_DMA_Init+0x28a>
 8005672:	687b      	ldr	r3, [r7, #4]
 8005674:	685b      	ldr	r3, [r3, #4]
 8005676:	2b42      	cmp	r3, #66	@ 0x42
 8005678:	d90f      	bls.n	800569a <HAL_DMA_Init+0x2aa>
 800567a:	687b      	ldr	r3, [r7, #4]
 800567c:	685b      	ldr	r3, [r3, #4]
 800567e:	2b46      	cmp	r3, #70	@ 0x46
 8005680:	d903      	bls.n	800568a <HAL_DMA_Init+0x29a>
 8005682:	687b      	ldr	r3, [r7, #4]
 8005684:	685b      	ldr	r3, [r3, #4]
 8005686:	2b48      	cmp	r3, #72	@ 0x48
 8005688:	d907      	bls.n	800569a <HAL_DMA_Init+0x2aa>
 800568a:	687b      	ldr	r3, [r7, #4]
 800568c:	685b      	ldr	r3, [r3, #4]
 800568e:	2b4e      	cmp	r3, #78	@ 0x4e
 8005690:	d905      	bls.n	800569e <HAL_DMA_Init+0x2ae>
 8005692:	687b      	ldr	r3, [r7, #4]
 8005694:	685b      	ldr	r3, [r3, #4]
 8005696:	2b52      	cmp	r3, #82	@ 0x52
 8005698:	d801      	bhi.n	800569e <HAL_DMA_Init+0x2ae>
 800569a:	2301      	movs	r3, #1
 800569c:	e000      	b.n	80056a0 <HAL_DMA_Init+0x2b0>
 800569e:	2300      	movs	r3, #0
 80056a0:	2b00      	cmp	r3, #0
 80056a2:	d003      	beq.n	80056ac <HAL_DMA_Init+0x2bc>
      {
        registerValue |= DMA_SxCR_TRBUFF;
 80056a4:	697b      	ldr	r3, [r7, #20]
 80056a6:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 80056aa:	617b      	str	r3, [r7, #20]
#if (STM32H7_DEV_ID == 0x450UL)
    }
#endif /* STM32H7_DEV_ID == 0x450UL */

    /* Write to DMA Stream CR register */
    ((DMA_Stream_TypeDef   *)hdma->Instance)->CR = registerValue;
 80056ac:	687b      	ldr	r3, [r7, #4]
 80056ae:	681b      	ldr	r3, [r3, #0]
 80056b0:	697a      	ldr	r2, [r7, #20]
 80056b2:	601a      	str	r2, [r3, #0]

    /* Get the FCR register value */
    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR;
 80056b4:	687b      	ldr	r3, [r7, #4]
 80056b6:	681b      	ldr	r3, [r3, #0]
 80056b8:	695b      	ldr	r3, [r3, #20]
 80056ba:	617b      	str	r3, [r7, #20]

    /* Clear Direct mode and FIFO threshold bits */
    registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
 80056bc:	697b      	ldr	r3, [r7, #20]
 80056be:	f023 0307 	bic.w	r3, r3, #7
 80056c2:	617b      	str	r3, [r7, #20]

    /* Prepare the DMA Stream FIFO configuration */
    registerValue |= hdma->Init.FIFOMode;
 80056c4:	687b      	ldr	r3, [r7, #4]
 80056c6:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80056c8:	697a      	ldr	r2, [r7, #20]
 80056ca:	4313      	orrs	r3, r2
 80056cc:	617b      	str	r3, [r7, #20]

    /* the FIFO threshold is not used when the FIFO mode is disabled */
    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
 80056ce:	687b      	ldr	r3, [r7, #4]
 80056d0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80056d2:	2b04      	cmp	r3, #4
 80056d4:	d117      	bne.n	8005706 <HAL_DMA_Init+0x316>
    {
      /* Get the FIFO threshold */
      registerValue |= hdma->Init.FIFOThreshold;
 80056d6:	687b      	ldr	r3, [r7, #4]
 80056d8:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 80056da:	697a      	ldr	r2, [r7, #20]
 80056dc:	4313      	orrs	r3, r2
 80056de:	617b      	str	r3, [r7, #20]

      /* Check compatibility between FIFO threshold level and size of the memory burst */
      /* for INCR4, INCR8, INCR16 */
      if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)
 80056e0:	687b      	ldr	r3, [r7, #4]
 80056e2:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80056e4:	2b00      	cmp	r3, #0
 80056e6:	d00e      	beq.n	8005706 <HAL_DMA_Init+0x316>
      {
        if (DMA_CheckFifoParam(hdma) != HAL_OK)
 80056e8:	6878      	ldr	r0, [r7, #4]
 80056ea:	f002 fb33 	bl	8007d54 <DMA_CheckFifoParam>
 80056ee:	4603      	mov	r3, r0
 80056f0:	2b00      	cmp	r3, #0
 80056f2:	d008      	beq.n	8005706 <HAL_DMA_Init+0x316>
        {
          /* Update error code */
          hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
 80056f4:	687b      	ldr	r3, [r7, #4]
 80056f6:	2240      	movs	r2, #64	@ 0x40
 80056f8:	655a      	str	r2, [r3, #84]	@ 0x54

          /* Change the DMA state */
          hdma->State = HAL_DMA_STATE_READY;
 80056fa:	687b      	ldr	r3, [r7, #4]
 80056fc:	2201      	movs	r2, #1
 80056fe:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

          return HAL_ERROR;
 8005702:	2301      	movs	r3, #1
 8005704:	e197      	b.n	8005a36 <HAL_DMA_Init+0x646>
        }
      }
    }

    /* Write to DMA Stream FCR */
    ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR = registerValue;
 8005706:	687b      	ldr	r3, [r7, #4]
 8005708:	681b      	ldr	r3, [r3, #0]
 800570a:	697a      	ldr	r2, [r7, #20]
 800570c:	615a      	str	r2, [r3, #20]

    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
       DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
    regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
 800570e:	6878      	ldr	r0, [r7, #4]
 8005710:	f002 fa6e 	bl	8007bf0 <DMA_CalcBaseAndBitshift>
 8005714:	4603      	mov	r3, r0
 8005716:	60bb      	str	r3, [r7, #8]

    /* Clear all interrupt flags */
    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
 8005718:	687b      	ldr	r3, [r7, #4]
 800571a:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800571c:	f003 031f 	and.w	r3, r3, #31
 8005720:	223f      	movs	r2, #63	@ 0x3f
 8005722:	409a      	lsls	r2, r3
 8005724:	68bb      	ldr	r3, [r7, #8]
 8005726:	609a      	str	r2, [r3, #8]
 8005728:	e0cd      	b.n	80058c6 <HAL_DMA_Init+0x4d6>
  }
  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
 800572a:	687b      	ldr	r3, [r7, #4]
 800572c:	681b      	ldr	r3, [r3, #0]
 800572e:	4a3b      	ldr	r2, [pc, #236]	@ (800581c <HAL_DMA_Init+0x42c>)
 8005730:	4293      	cmp	r3, r2
 8005732:	d022      	beq.n	800577a <HAL_DMA_Init+0x38a>
 8005734:	687b      	ldr	r3, [r7, #4]
 8005736:	681b      	ldr	r3, [r3, #0]
 8005738:	4a39      	ldr	r2, [pc, #228]	@ (8005820 <HAL_DMA_Init+0x430>)
 800573a:	4293      	cmp	r3, r2
 800573c:	d01d      	beq.n	800577a <HAL_DMA_Init+0x38a>
 800573e:	687b      	ldr	r3, [r7, #4]
 8005740:	681b      	ldr	r3, [r3, #0]
 8005742:	4a38      	ldr	r2, [pc, #224]	@ (8005824 <HAL_DMA_Init+0x434>)
 8005744:	4293      	cmp	r3, r2
 8005746:	d018      	beq.n	800577a <HAL_DMA_Init+0x38a>
 8005748:	687b      	ldr	r3, [r7, #4]
 800574a:	681b      	ldr	r3, [r3, #0]
 800574c:	4a36      	ldr	r2, [pc, #216]	@ (8005828 <HAL_DMA_Init+0x438>)
 800574e:	4293      	cmp	r3, r2
 8005750:	d013      	beq.n	800577a <HAL_DMA_Init+0x38a>
 8005752:	687b      	ldr	r3, [r7, #4]
 8005754:	681b      	ldr	r3, [r3, #0]
 8005756:	4a35      	ldr	r2, [pc, #212]	@ (800582c <HAL_DMA_Init+0x43c>)
 8005758:	4293      	cmp	r3, r2
 800575a:	d00e      	beq.n	800577a <HAL_DMA_Init+0x38a>
 800575c:	687b      	ldr	r3, [r7, #4]
 800575e:	681b      	ldr	r3, [r3, #0]
 8005760:	4a33      	ldr	r2, [pc, #204]	@ (8005830 <HAL_DMA_Init+0x440>)
 8005762:	4293      	cmp	r3, r2
 8005764:	d009      	beq.n	800577a <HAL_DMA_Init+0x38a>
 8005766:	687b      	ldr	r3, [r7, #4]
 8005768:	681b      	ldr	r3, [r3, #0]
 800576a:	4a32      	ldr	r2, [pc, #200]	@ (8005834 <HAL_DMA_Init+0x444>)
 800576c:	4293      	cmp	r3, r2
 800576e:	d004      	beq.n	800577a <HAL_DMA_Init+0x38a>
 8005770:	687b      	ldr	r3, [r7, #4]
 8005772:	681b      	ldr	r3, [r3, #0]
 8005774:	4a30      	ldr	r2, [pc, #192]	@ (8005838 <HAL_DMA_Init+0x448>)
 8005776:	4293      	cmp	r3, r2
 8005778:	d101      	bne.n	800577e <HAL_DMA_Init+0x38e>
 800577a:	2301      	movs	r3, #1
 800577c:	e000      	b.n	8005780 <HAL_DMA_Init+0x390>
 800577e:	2300      	movs	r3, #0
 8005780:	2b00      	cmp	r3, #0
 8005782:	f000 8097 	beq.w	80058b4 <HAL_DMA_Init+0x4c4>
  {
    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
 8005786:	687b      	ldr	r3, [r7, #4]
 8005788:	681b      	ldr	r3, [r3, #0]
 800578a:	4a24      	ldr	r2, [pc, #144]	@ (800581c <HAL_DMA_Init+0x42c>)
 800578c:	4293      	cmp	r3, r2
 800578e:	d021      	beq.n	80057d4 <HAL_DMA_Init+0x3e4>
 8005790:	687b      	ldr	r3, [r7, #4]
 8005792:	681b      	ldr	r3, [r3, #0]
 8005794:	4a22      	ldr	r2, [pc, #136]	@ (8005820 <HAL_DMA_Init+0x430>)
 8005796:	4293      	cmp	r3, r2
 8005798:	d01c      	beq.n	80057d4 <HAL_DMA_Init+0x3e4>
 800579a:	687b      	ldr	r3, [r7, #4]
 800579c:	681b      	ldr	r3, [r3, #0]
 800579e:	4a21      	ldr	r2, [pc, #132]	@ (8005824 <HAL_DMA_Init+0x434>)
 80057a0:	4293      	cmp	r3, r2
 80057a2:	d017      	beq.n	80057d4 <HAL_DMA_Init+0x3e4>
 80057a4:	687b      	ldr	r3, [r7, #4]
 80057a6:	681b      	ldr	r3, [r3, #0]
 80057a8:	4a1f      	ldr	r2, [pc, #124]	@ (8005828 <HAL_DMA_Init+0x438>)
 80057aa:	4293      	cmp	r3, r2
 80057ac:	d012      	beq.n	80057d4 <HAL_DMA_Init+0x3e4>
 80057ae:	687b      	ldr	r3, [r7, #4]
 80057b0:	681b      	ldr	r3, [r3, #0]
 80057b2:	4a1e      	ldr	r2, [pc, #120]	@ (800582c <HAL_DMA_Init+0x43c>)
 80057b4:	4293      	cmp	r3, r2
 80057b6:	d00d      	beq.n	80057d4 <HAL_DMA_Init+0x3e4>
 80057b8:	687b      	ldr	r3, [r7, #4]
 80057ba:	681b      	ldr	r3, [r3, #0]
 80057bc:	4a1c      	ldr	r2, [pc, #112]	@ (8005830 <HAL_DMA_Init+0x440>)
 80057be:	4293      	cmp	r3, r2
 80057c0:	d008      	beq.n	80057d4 <HAL_DMA_Init+0x3e4>
 80057c2:	687b      	ldr	r3, [r7, #4]
 80057c4:	681b      	ldr	r3, [r3, #0]
 80057c6:	4a1b      	ldr	r2, [pc, #108]	@ (8005834 <HAL_DMA_Init+0x444>)
 80057c8:	4293      	cmp	r3, r2
 80057ca:	d003      	beq.n	80057d4 <HAL_DMA_Init+0x3e4>
 80057cc:	687b      	ldr	r3, [r7, #4]
 80057ce:	681b      	ldr	r3, [r3, #0]
 80057d0:	4a19      	ldr	r2, [pc, #100]	@ (8005838 <HAL_DMA_Init+0x448>)
 80057d2:	4293      	cmp	r3, r2
      /* Check the request parameter */
      assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
    }

    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 80057d4:	687b      	ldr	r3, [r7, #4]
 80057d6:	2202      	movs	r2, #2
 80057d8:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

    /* Allocate lock resource */
    __HAL_UNLOCK(hdma);
 80057dc:	687b      	ldr	r3, [r7, #4]
 80057de:	2200      	movs	r2, #0
 80057e0:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

    /* Get the CR register value */
    registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
 80057e4:	687b      	ldr	r3, [r7, #4]
 80057e6:	681b      	ldr	r3, [r3, #0]
 80057e8:	681b      	ldr	r3, [r3, #0]
 80057ea:	617b      	str	r3, [r7, #20]

    /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */
    registerValue &= ((uint32_t)~(BDMA_CCR_PL    | BDMA_CCR_MSIZE   | BDMA_CCR_PSIZE  | \
 80057ec:	697a      	ldr	r2, [r7, #20]
 80057ee:	4b13      	ldr	r3, [pc, #76]	@ (800583c <HAL_DMA_Init+0x44c>)
 80057f0:	4013      	ands	r3, r2
 80057f2:	617b      	str	r3, [r7, #20]
                                  BDMA_CCR_MINC  | BDMA_CCR_PINC    | BDMA_CCR_CIRC   | \
                                  BDMA_CCR_DIR   | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM    | \
                                  BDMA_CCR_CT));

    /* Prepare the DMA Channel configuration */
    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
 80057f4:	687b      	ldr	r3, [r7, #4]
 80057f6:	689b      	ldr	r3, [r3, #8]
 80057f8:	2b40      	cmp	r3, #64	@ 0x40
 80057fa:	d021      	beq.n	8005840 <HAL_DMA_Init+0x450>
 80057fc:	687b      	ldr	r3, [r7, #4]
 80057fe:	689b      	ldr	r3, [r3, #8]
 8005800:	2b80      	cmp	r3, #128	@ 0x80
 8005802:	d102      	bne.n	800580a <HAL_DMA_Init+0x41a>
 8005804:	f44f 4380 	mov.w	r3, #16384	@ 0x4000
 8005808:	e01b      	b.n	8005842 <HAL_DMA_Init+0x452>
 800580a:	2300      	movs	r3, #0
 800580c:	e019      	b.n	8005842 <HAL_DMA_Init+0x452>
 800580e:	bf00      	nop
 8005810:	fe10803f 	.word	0xfe10803f
 8005814:	5c001000 	.word	0x5c001000
 8005818:	ffff0000 	.word	0xffff0000
 800581c:	58025408 	.word	0x58025408
 8005820:	5802541c 	.word	0x5802541c
 8005824:	58025430 	.word	0x58025430
 8005828:	58025444 	.word	0x58025444
 800582c:	58025458 	.word	0x58025458
 8005830:	5802546c 	.word	0x5802546c
 8005834:	58025480 	.word	0x58025480
 8005838:	58025494 	.word	0x58025494
 800583c:	fffe000f 	.word	0xfffe000f
 8005840:	2310      	movs	r3, #16
                      DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
 8005842:	687a      	ldr	r2, [r7, #4]
 8005844:	68d2      	ldr	r2, [r2, #12]
 8005846:	08d2      	lsrs	r2, r2, #3
    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
 8005848:	431a      	orrs	r2, r3
                      DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
 800584a:	687b      	ldr	r3, [r7, #4]
 800584c:	691b      	ldr	r3, [r3, #16]
 800584e:	08db      	lsrs	r3, r3, #3
                      DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
 8005850:	431a      	orrs	r2, r3
                      DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
 8005852:	687b      	ldr	r3, [r7, #4]
 8005854:	695b      	ldr	r3, [r3, #20]
 8005856:	08db      	lsrs	r3, r3, #3
                      DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
 8005858:	431a      	orrs	r2, r3
                      DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
 800585a:	687b      	ldr	r3, [r7, #4]
 800585c:	699b      	ldr	r3, [r3, #24]
 800585e:	08db      	lsrs	r3, r3, #3
                      DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
 8005860:	431a      	orrs	r2, r3
                      DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
 8005862:	687b      	ldr	r3, [r7, #4]
 8005864:	69db      	ldr	r3, [r3, #28]
 8005866:	08db      	lsrs	r3, r3, #3
                      DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
 8005868:	431a      	orrs	r2, r3
                      DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);
 800586a:	687b      	ldr	r3, [r7, #4]
 800586c:	6a1b      	ldr	r3, [r3, #32]
 800586e:	091b      	lsrs	r3, r3, #4
                      DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
 8005870:	4313      	orrs	r3, r2
    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
 8005872:	697a      	ldr	r2, [r7, #20]
 8005874:	4313      	orrs	r3, r2
 8005876:	617b      	str	r3, [r7, #20]

    /* Write to DMA Channel CR register */
    ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;
 8005878:	687b      	ldr	r3, [r7, #4]
 800587a:	681b      	ldr	r3, [r3, #0]
 800587c:	697a      	ldr	r2, [r7, #20]
 800587e:	601a      	str	r2, [r3, #0]

    /* calculation of the channel index */
    hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
 8005880:	687b      	ldr	r3, [r7, #4]
 8005882:	681b      	ldr	r3, [r3, #0]
 8005884:	461a      	mov	r2, r3
 8005886:	4b6e      	ldr	r3, [pc, #440]	@ (8005a40 <HAL_DMA_Init+0x650>)
 8005888:	4413      	add	r3, r2
 800588a:	4a6e      	ldr	r2, [pc, #440]	@ (8005a44 <HAL_DMA_Init+0x654>)
 800588c:	fba2 2303 	umull	r2, r3, r2, r3
 8005890:	091b      	lsrs	r3, r3, #4
 8005892:	009a      	lsls	r2, r3, #2
 8005894:	687b      	ldr	r3, [r7, #4]
 8005896:	65da      	str	r2, [r3, #92]	@ 0x5c

    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
    DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
    regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
 8005898:	6878      	ldr	r0, [r7, #4]
 800589a:	f002 f9a9 	bl	8007bf0 <DMA_CalcBaseAndBitshift>
 800589e:	4603      	mov	r3, r0
 80058a0:	60fb      	str	r3, [r7, #12]

    /* Clear all interrupt flags */
    regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
 80058a2:	687b      	ldr	r3, [r7, #4]
 80058a4:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80058a6:	f003 031f 	and.w	r3, r3, #31
 80058aa:	2201      	movs	r2, #1
 80058ac:	409a      	lsls	r2, r3
 80058ae:	68fb      	ldr	r3, [r7, #12]
 80058b0:	605a      	str	r2, [r3, #4]
 80058b2:	e008      	b.n	80058c6 <HAL_DMA_Init+0x4d6>
  }
  else
  {
    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
 80058b4:	687b      	ldr	r3, [r7, #4]
 80058b6:	2240      	movs	r2, #64	@ 0x40
 80058b8:	655a      	str	r2, [r3, #84]	@ 0x54
    hdma->State     = HAL_DMA_STATE_ERROR;
 80058ba:	687b      	ldr	r3, [r7, #4]
 80058bc:	2203      	movs	r2, #3
 80058be:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

    return HAL_ERROR;
 80058c2:	2301      	movs	r3, #1
 80058c4:	e0b7      	b.n	8005a36 <HAL_DMA_Init+0x646>
  }

  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
 80058c6:	687b      	ldr	r3, [r7, #4]
 80058c8:	681b      	ldr	r3, [r3, #0]
 80058ca:	4a5f      	ldr	r2, [pc, #380]	@ (8005a48 <HAL_DMA_Init+0x658>)
 80058cc:	4293      	cmp	r3, r2
 80058ce:	d072      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 80058d0:	687b      	ldr	r3, [r7, #4]
 80058d2:	681b      	ldr	r3, [r3, #0]
 80058d4:	4a5d      	ldr	r2, [pc, #372]	@ (8005a4c <HAL_DMA_Init+0x65c>)
 80058d6:	4293      	cmp	r3, r2
 80058d8:	d06d      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 80058da:	687b      	ldr	r3, [r7, #4]
 80058dc:	681b      	ldr	r3, [r3, #0]
 80058de:	4a5c      	ldr	r2, [pc, #368]	@ (8005a50 <HAL_DMA_Init+0x660>)
 80058e0:	4293      	cmp	r3, r2
 80058e2:	d068      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 80058e4:	687b      	ldr	r3, [r7, #4]
 80058e6:	681b      	ldr	r3, [r3, #0]
 80058e8:	4a5a      	ldr	r2, [pc, #360]	@ (8005a54 <HAL_DMA_Init+0x664>)
 80058ea:	4293      	cmp	r3, r2
 80058ec:	d063      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 80058ee:	687b      	ldr	r3, [r7, #4]
 80058f0:	681b      	ldr	r3, [r3, #0]
 80058f2:	4a59      	ldr	r2, [pc, #356]	@ (8005a58 <HAL_DMA_Init+0x668>)
 80058f4:	4293      	cmp	r3, r2
 80058f6:	d05e      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 80058f8:	687b      	ldr	r3, [r7, #4]
 80058fa:	681b      	ldr	r3, [r3, #0]
 80058fc:	4a57      	ldr	r2, [pc, #348]	@ (8005a5c <HAL_DMA_Init+0x66c>)
 80058fe:	4293      	cmp	r3, r2
 8005900:	d059      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 8005902:	687b      	ldr	r3, [r7, #4]
 8005904:	681b      	ldr	r3, [r3, #0]
 8005906:	4a56      	ldr	r2, [pc, #344]	@ (8005a60 <HAL_DMA_Init+0x670>)
 8005908:	4293      	cmp	r3, r2
 800590a:	d054      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 800590c:	687b      	ldr	r3, [r7, #4]
 800590e:	681b      	ldr	r3, [r3, #0]
 8005910:	4a54      	ldr	r2, [pc, #336]	@ (8005a64 <HAL_DMA_Init+0x674>)
 8005912:	4293      	cmp	r3, r2
 8005914:	d04f      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 8005916:	687b      	ldr	r3, [r7, #4]
 8005918:	681b      	ldr	r3, [r3, #0]
 800591a:	4a53      	ldr	r2, [pc, #332]	@ (8005a68 <HAL_DMA_Init+0x678>)
 800591c:	4293      	cmp	r3, r2
 800591e:	d04a      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 8005920:	687b      	ldr	r3, [r7, #4]
 8005922:	681b      	ldr	r3, [r3, #0]
 8005924:	4a51      	ldr	r2, [pc, #324]	@ (8005a6c <HAL_DMA_Init+0x67c>)
 8005926:	4293      	cmp	r3, r2
 8005928:	d045      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 800592a:	687b      	ldr	r3, [r7, #4]
 800592c:	681b      	ldr	r3, [r3, #0]
 800592e:	4a50      	ldr	r2, [pc, #320]	@ (8005a70 <HAL_DMA_Init+0x680>)
 8005930:	4293      	cmp	r3, r2
 8005932:	d040      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 8005934:	687b      	ldr	r3, [r7, #4]
 8005936:	681b      	ldr	r3, [r3, #0]
 8005938:	4a4e      	ldr	r2, [pc, #312]	@ (8005a74 <HAL_DMA_Init+0x684>)
 800593a:	4293      	cmp	r3, r2
 800593c:	d03b      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 800593e:	687b      	ldr	r3, [r7, #4]
 8005940:	681b      	ldr	r3, [r3, #0]
 8005942:	4a4d      	ldr	r2, [pc, #308]	@ (8005a78 <HAL_DMA_Init+0x688>)
 8005944:	4293      	cmp	r3, r2
 8005946:	d036      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 8005948:	687b      	ldr	r3, [r7, #4]
 800594a:	681b      	ldr	r3, [r3, #0]
 800594c:	4a4b      	ldr	r2, [pc, #300]	@ (8005a7c <HAL_DMA_Init+0x68c>)
 800594e:	4293      	cmp	r3, r2
 8005950:	d031      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 8005952:	687b      	ldr	r3, [r7, #4]
 8005954:	681b      	ldr	r3, [r3, #0]
 8005956:	4a4a      	ldr	r2, [pc, #296]	@ (8005a80 <HAL_DMA_Init+0x690>)
 8005958:	4293      	cmp	r3, r2
 800595a:	d02c      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 800595c:	687b      	ldr	r3, [r7, #4]
 800595e:	681b      	ldr	r3, [r3, #0]
 8005960:	4a48      	ldr	r2, [pc, #288]	@ (8005a84 <HAL_DMA_Init+0x694>)
 8005962:	4293      	cmp	r3, r2
 8005964:	d027      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 8005966:	687b      	ldr	r3, [r7, #4]
 8005968:	681b      	ldr	r3, [r3, #0]
 800596a:	4a47      	ldr	r2, [pc, #284]	@ (8005a88 <HAL_DMA_Init+0x698>)
 800596c:	4293      	cmp	r3, r2
 800596e:	d022      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 8005970:	687b      	ldr	r3, [r7, #4]
 8005972:	681b      	ldr	r3, [r3, #0]
 8005974:	4a45      	ldr	r2, [pc, #276]	@ (8005a8c <HAL_DMA_Init+0x69c>)
 8005976:	4293      	cmp	r3, r2
 8005978:	d01d      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 800597a:	687b      	ldr	r3, [r7, #4]
 800597c:	681b      	ldr	r3, [r3, #0]
 800597e:	4a44      	ldr	r2, [pc, #272]	@ (8005a90 <HAL_DMA_Init+0x6a0>)
 8005980:	4293      	cmp	r3, r2
 8005982:	d018      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 8005984:	687b      	ldr	r3, [r7, #4]
 8005986:	681b      	ldr	r3, [r3, #0]
 8005988:	4a42      	ldr	r2, [pc, #264]	@ (8005a94 <HAL_DMA_Init+0x6a4>)
 800598a:	4293      	cmp	r3, r2
 800598c:	d013      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 800598e:	687b      	ldr	r3, [r7, #4]
 8005990:	681b      	ldr	r3, [r3, #0]
 8005992:	4a41      	ldr	r2, [pc, #260]	@ (8005a98 <HAL_DMA_Init+0x6a8>)
 8005994:	4293      	cmp	r3, r2
 8005996:	d00e      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 8005998:	687b      	ldr	r3, [r7, #4]
 800599a:	681b      	ldr	r3, [r3, #0]
 800599c:	4a3f      	ldr	r2, [pc, #252]	@ (8005a9c <HAL_DMA_Init+0x6ac>)
 800599e:	4293      	cmp	r3, r2
 80059a0:	d009      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 80059a2:	687b      	ldr	r3, [r7, #4]
 80059a4:	681b      	ldr	r3, [r3, #0]
 80059a6:	4a3e      	ldr	r2, [pc, #248]	@ (8005aa0 <HAL_DMA_Init+0x6b0>)
 80059a8:	4293      	cmp	r3, r2
 80059aa:	d004      	beq.n	80059b6 <HAL_DMA_Init+0x5c6>
 80059ac:	687b      	ldr	r3, [r7, #4]
 80059ae:	681b      	ldr	r3, [r3, #0]
 80059b0:	4a3c      	ldr	r2, [pc, #240]	@ (8005aa4 <HAL_DMA_Init+0x6b4>)
 80059b2:	4293      	cmp	r3, r2
 80059b4:	d101      	bne.n	80059ba <HAL_DMA_Init+0x5ca>
 80059b6:	2301      	movs	r3, #1
 80059b8:	e000      	b.n	80059bc <HAL_DMA_Init+0x5cc>
 80059ba:	2300      	movs	r3, #0
 80059bc:	2b00      	cmp	r3, #0
 80059be:	d032      	beq.n	8005a26 <HAL_DMA_Init+0x636>
  {
    /* Initialize parameters for DMAMUX channel :
    DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
    */
    DMA_CalcDMAMUXChannelBaseAndMask(hdma);
 80059c0:	6878      	ldr	r0, [r7, #4]
 80059c2:	f002 fa43 	bl	8007e4c <DMA_CalcDMAMUXChannelBaseAndMask>

    if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
 80059c6:	687b      	ldr	r3, [r7, #4]
 80059c8:	689b      	ldr	r3, [r3, #8]
 80059ca:	2b80      	cmp	r3, #128	@ 0x80
 80059cc:	d102      	bne.n	80059d4 <HAL_DMA_Init+0x5e4>
    {
      /* if memory to memory force the request to 0*/
      hdma->Init.Request = DMA_REQUEST_MEM2MEM;
 80059ce:	687b      	ldr	r3, [r7, #4]
 80059d0:	2200      	movs	r2, #0
 80059d2:	605a      	str	r2, [r3, #4]
    }

    /* Set peripheral request  to DMAMUX channel */
    hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
 80059d4:	687b      	ldr	r3, [r7, #4]
 80059d6:	685a      	ldr	r2, [r3, #4]
 80059d8:	687b      	ldr	r3, [r7, #4]
 80059da:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80059dc:	b2d2      	uxtb	r2, r2
 80059de:	601a      	str	r2, [r3, #0]

    /* Clear the DMAMUX synchro overrun flag */
    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 80059e0:	687b      	ldr	r3, [r7, #4]
 80059e2:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 80059e4:	687a      	ldr	r2, [r7, #4]
 80059e6:	6e92      	ldr	r2, [r2, #104]	@ 0x68
 80059e8:	605a      	str	r2, [r3, #4]

    /* Initialize parameters for DMAMUX request generator :
    if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
    */
    if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
 80059ea:	687b      	ldr	r3, [r7, #4]
 80059ec:	685b      	ldr	r3, [r3, #4]
 80059ee:	2b00      	cmp	r3, #0
 80059f0:	d010      	beq.n	8005a14 <HAL_DMA_Init+0x624>
 80059f2:	687b      	ldr	r3, [r7, #4]
 80059f4:	685b      	ldr	r3, [r3, #4]
 80059f6:	2b08      	cmp	r3, #8
 80059f8:	d80c      	bhi.n	8005a14 <HAL_DMA_Init+0x624>
    {
      /* Initialize parameters for DMAMUX request generator :
      DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
      DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
 80059fa:	6878      	ldr	r0, [r7, #4]
 80059fc:	f002 fac0 	bl	8007f80 <DMA_CalcDMAMUXRequestGenBaseAndMask>

      /* Reset the DMAMUX request generator register */
      hdma->DMAmuxRequestGen->RGCR = 0U;
 8005a00:	687b      	ldr	r3, [r7, #4]
 8005a02:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8005a04:	2200      	movs	r2, #0
 8005a06:	601a      	str	r2, [r3, #0]

      /* Clear the DMAMUX request generator overrun flag */
      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 8005a08:	687b      	ldr	r3, [r7, #4]
 8005a0a:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8005a0c:	687a      	ldr	r2, [r7, #4]
 8005a0e:	6f52      	ldr	r2, [r2, #116]	@ 0x74
 8005a10:	605a      	str	r2, [r3, #4]
 8005a12:	e008      	b.n	8005a26 <HAL_DMA_Init+0x636>
    }
    else
    {
      hdma->DMAmuxRequestGen = 0U;
 8005a14:	687b      	ldr	r3, [r7, #4]
 8005a16:	2200      	movs	r2, #0
 8005a18:	66da      	str	r2, [r3, #108]	@ 0x6c
      hdma->DMAmuxRequestGenStatus = 0U;
 8005a1a:	687b      	ldr	r3, [r7, #4]
 8005a1c:	2200      	movs	r2, #0
 8005a1e:	671a      	str	r2, [r3, #112]	@ 0x70
      hdma->DMAmuxRequestGenStatusMask = 0U;
 8005a20:	687b      	ldr	r3, [r7, #4]
 8005a22:	2200      	movs	r2, #0
 8005a24:	675a      	str	r2, [r3, #116]	@ 0x74
    }
  }

  /* Initialize the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8005a26:	687b      	ldr	r3, [r7, #4]
 8005a28:	2200      	movs	r2, #0
 8005a2a:	655a      	str	r2, [r3, #84]	@ 0x54

  /* Initialize the DMA state */
  hdma->State = HAL_DMA_STATE_READY;
 8005a2c:	687b      	ldr	r3, [r7, #4]
 8005a2e:	2201      	movs	r2, #1
 8005a30:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

  return HAL_OK;
 8005a34:	2300      	movs	r3, #0
}
 8005a36:	4618      	mov	r0, r3
 8005a38:	3718      	adds	r7, #24
 8005a3a:	46bd      	mov	sp, r7
 8005a3c:	bd80      	pop	{r7, pc}
 8005a3e:	bf00      	nop
 8005a40:	a7fdabf8 	.word	0xa7fdabf8
 8005a44:	cccccccd 	.word	0xcccccccd
 8005a48:	40020010 	.word	0x40020010
 8005a4c:	40020028 	.word	0x40020028
 8005a50:	40020040 	.word	0x40020040
 8005a54:	40020058 	.word	0x40020058
 8005a58:	40020070 	.word	0x40020070
 8005a5c:	40020088 	.word	0x40020088
 8005a60:	400200a0 	.word	0x400200a0
 8005a64:	400200b8 	.word	0x400200b8
 8005a68:	40020410 	.word	0x40020410
 8005a6c:	40020428 	.word	0x40020428
 8005a70:	40020440 	.word	0x40020440
 8005a74:	40020458 	.word	0x40020458
 8005a78:	40020470 	.word	0x40020470
 8005a7c:	40020488 	.word	0x40020488
 8005a80:	400204a0 	.word	0x400204a0
 8005a84:	400204b8 	.word	0x400204b8
 8005a88:	58025408 	.word	0x58025408
 8005a8c:	5802541c 	.word	0x5802541c
 8005a90:	58025430 	.word	0x58025430
 8005a94:	58025444 	.word	0x58025444
 8005a98:	58025458 	.word	0x58025458
 8005a9c:	5802546c 	.word	0x5802546c
 8005aa0:	58025480 	.word	0x58025480
 8005aa4:	58025494 	.word	0x58025494

08005aa8 <HAL_DMA_Start_IT>:
  * @param  DstAddress: The destination memory Buffer address
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 8005aa8:	b580      	push	{r7, lr}
 8005aaa:	b086      	sub	sp, #24
 8005aac:	af00      	add	r7, sp, #0
 8005aae:	60f8      	str	r0, [r7, #12]
 8005ab0:	60b9      	str	r1, [r7, #8]
 8005ab2:	607a      	str	r2, [r7, #4]
 8005ab4:	603b      	str	r3, [r7, #0]
  HAL_StatusTypeDef status = HAL_OK;
 8005ab6:	2300      	movs	r3, #0
 8005ab8:	75fb      	strb	r3, [r7, #23]

  /* Check the parameters */
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));

  /* Check the DMA peripheral handle */
  if(hdma == NULL)
 8005aba:	68fb      	ldr	r3, [r7, #12]
 8005abc:	2b00      	cmp	r3, #0
 8005abe:	d101      	bne.n	8005ac4 <HAL_DMA_Start_IT+0x1c>
  {
    return HAL_ERROR;
 8005ac0:	2301      	movs	r3, #1
 8005ac2:	e226      	b.n	8005f12 <HAL_DMA_Start_IT+0x46a>
  }

  /* Process locked */
  __HAL_LOCK(hdma);
 8005ac4:	68fb      	ldr	r3, [r7, #12]
 8005ac6:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8005aca:	2b01      	cmp	r3, #1
 8005acc:	d101      	bne.n	8005ad2 <HAL_DMA_Start_IT+0x2a>
 8005ace:	2302      	movs	r3, #2
 8005ad0:	e21f      	b.n	8005f12 <HAL_DMA_Start_IT+0x46a>
 8005ad2:	68fb      	ldr	r3, [r7, #12]
 8005ad4:	2201      	movs	r2, #1
 8005ad6:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

  if(HAL_DMA_STATE_READY == hdma->State)
 8005ada:	68fb      	ldr	r3, [r7, #12]
 8005adc:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
 8005ae0:	b2db      	uxtb	r3, r3
 8005ae2:	2b01      	cmp	r3, #1
 8005ae4:	f040 820a 	bne.w	8005efc <HAL_DMA_Start_IT+0x454>
  {
    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 8005ae8:	68fb      	ldr	r3, [r7, #12]
 8005aea:	2202      	movs	r2, #2
 8005aec:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

    /* Initialize the error code */
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8005af0:	68fb      	ldr	r3, [r7, #12]
 8005af2:	2200      	movs	r2, #0
 8005af4:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);
 8005af6:	68fb      	ldr	r3, [r7, #12]
 8005af8:	681b      	ldr	r3, [r3, #0]
 8005afa:	4a68      	ldr	r2, [pc, #416]	@ (8005c9c <HAL_DMA_Start_IT+0x1f4>)
 8005afc:	4293      	cmp	r3, r2
 8005afe:	d04a      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b00:	68fb      	ldr	r3, [r7, #12]
 8005b02:	681b      	ldr	r3, [r3, #0]
 8005b04:	4a66      	ldr	r2, [pc, #408]	@ (8005ca0 <HAL_DMA_Start_IT+0x1f8>)
 8005b06:	4293      	cmp	r3, r2
 8005b08:	d045      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b0a:	68fb      	ldr	r3, [r7, #12]
 8005b0c:	681b      	ldr	r3, [r3, #0]
 8005b0e:	4a65      	ldr	r2, [pc, #404]	@ (8005ca4 <HAL_DMA_Start_IT+0x1fc>)
 8005b10:	4293      	cmp	r3, r2
 8005b12:	d040      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b14:	68fb      	ldr	r3, [r7, #12]
 8005b16:	681b      	ldr	r3, [r3, #0]
 8005b18:	4a63      	ldr	r2, [pc, #396]	@ (8005ca8 <HAL_DMA_Start_IT+0x200>)
 8005b1a:	4293      	cmp	r3, r2
 8005b1c:	d03b      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b1e:	68fb      	ldr	r3, [r7, #12]
 8005b20:	681b      	ldr	r3, [r3, #0]
 8005b22:	4a62      	ldr	r2, [pc, #392]	@ (8005cac <HAL_DMA_Start_IT+0x204>)
 8005b24:	4293      	cmp	r3, r2
 8005b26:	d036      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b28:	68fb      	ldr	r3, [r7, #12]
 8005b2a:	681b      	ldr	r3, [r3, #0]
 8005b2c:	4a60      	ldr	r2, [pc, #384]	@ (8005cb0 <HAL_DMA_Start_IT+0x208>)
 8005b2e:	4293      	cmp	r3, r2
 8005b30:	d031      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b32:	68fb      	ldr	r3, [r7, #12]
 8005b34:	681b      	ldr	r3, [r3, #0]
 8005b36:	4a5f      	ldr	r2, [pc, #380]	@ (8005cb4 <HAL_DMA_Start_IT+0x20c>)
 8005b38:	4293      	cmp	r3, r2
 8005b3a:	d02c      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b3c:	68fb      	ldr	r3, [r7, #12]
 8005b3e:	681b      	ldr	r3, [r3, #0]
 8005b40:	4a5d      	ldr	r2, [pc, #372]	@ (8005cb8 <HAL_DMA_Start_IT+0x210>)
 8005b42:	4293      	cmp	r3, r2
 8005b44:	d027      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b46:	68fb      	ldr	r3, [r7, #12]
 8005b48:	681b      	ldr	r3, [r3, #0]
 8005b4a:	4a5c      	ldr	r2, [pc, #368]	@ (8005cbc <HAL_DMA_Start_IT+0x214>)
 8005b4c:	4293      	cmp	r3, r2
 8005b4e:	d022      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b50:	68fb      	ldr	r3, [r7, #12]
 8005b52:	681b      	ldr	r3, [r3, #0]
 8005b54:	4a5a      	ldr	r2, [pc, #360]	@ (8005cc0 <HAL_DMA_Start_IT+0x218>)
 8005b56:	4293      	cmp	r3, r2
 8005b58:	d01d      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b5a:	68fb      	ldr	r3, [r7, #12]
 8005b5c:	681b      	ldr	r3, [r3, #0]
 8005b5e:	4a59      	ldr	r2, [pc, #356]	@ (8005cc4 <HAL_DMA_Start_IT+0x21c>)
 8005b60:	4293      	cmp	r3, r2
 8005b62:	d018      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b64:	68fb      	ldr	r3, [r7, #12]
 8005b66:	681b      	ldr	r3, [r3, #0]
 8005b68:	4a57      	ldr	r2, [pc, #348]	@ (8005cc8 <HAL_DMA_Start_IT+0x220>)
 8005b6a:	4293      	cmp	r3, r2
 8005b6c:	d013      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b6e:	68fb      	ldr	r3, [r7, #12]
 8005b70:	681b      	ldr	r3, [r3, #0]
 8005b72:	4a56      	ldr	r2, [pc, #344]	@ (8005ccc <HAL_DMA_Start_IT+0x224>)
 8005b74:	4293      	cmp	r3, r2
 8005b76:	d00e      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b78:	68fb      	ldr	r3, [r7, #12]
 8005b7a:	681b      	ldr	r3, [r3, #0]
 8005b7c:	4a54      	ldr	r2, [pc, #336]	@ (8005cd0 <HAL_DMA_Start_IT+0x228>)
 8005b7e:	4293      	cmp	r3, r2
 8005b80:	d009      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b82:	68fb      	ldr	r3, [r7, #12]
 8005b84:	681b      	ldr	r3, [r3, #0]
 8005b86:	4a53      	ldr	r2, [pc, #332]	@ (8005cd4 <HAL_DMA_Start_IT+0x22c>)
 8005b88:	4293      	cmp	r3, r2
 8005b8a:	d004      	beq.n	8005b96 <HAL_DMA_Start_IT+0xee>
 8005b8c:	68fb      	ldr	r3, [r7, #12]
 8005b8e:	681b      	ldr	r3, [r3, #0]
 8005b90:	4a51      	ldr	r2, [pc, #324]	@ (8005cd8 <HAL_DMA_Start_IT+0x230>)
 8005b92:	4293      	cmp	r3, r2
 8005b94:	d108      	bne.n	8005ba8 <HAL_DMA_Start_IT+0x100>
 8005b96:	68fb      	ldr	r3, [r7, #12]
 8005b98:	681b      	ldr	r3, [r3, #0]
 8005b9a:	681a      	ldr	r2, [r3, #0]
 8005b9c:	68fb      	ldr	r3, [r7, #12]
 8005b9e:	681b      	ldr	r3, [r3, #0]
 8005ba0:	f022 0201 	bic.w	r2, r2, #1
 8005ba4:	601a      	str	r2, [r3, #0]
 8005ba6:	e007      	b.n	8005bb8 <HAL_DMA_Start_IT+0x110>
 8005ba8:	68fb      	ldr	r3, [r7, #12]
 8005baa:	681b      	ldr	r3, [r3, #0]
 8005bac:	681a      	ldr	r2, [r3, #0]
 8005bae:	68fb      	ldr	r3, [r7, #12]
 8005bb0:	681b      	ldr	r3, [r3, #0]
 8005bb2:	f022 0201 	bic.w	r2, r2, #1
 8005bb6:	601a      	str	r2, [r3, #0]

    /* Configure the source, destination address and the data length */
    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
 8005bb8:	683b      	ldr	r3, [r7, #0]
 8005bba:	687a      	ldr	r2, [r7, #4]
 8005bbc:	68b9      	ldr	r1, [r7, #8]
 8005bbe:	68f8      	ldr	r0, [r7, #12]
 8005bc0:	f001 fe6a 	bl	8007898 <DMA_SetConfig>

    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 8005bc4:	68fb      	ldr	r3, [r7, #12]
 8005bc6:	681b      	ldr	r3, [r3, #0]
 8005bc8:	4a34      	ldr	r2, [pc, #208]	@ (8005c9c <HAL_DMA_Start_IT+0x1f4>)
 8005bca:	4293      	cmp	r3, r2
 8005bcc:	d04a      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005bce:	68fb      	ldr	r3, [r7, #12]
 8005bd0:	681b      	ldr	r3, [r3, #0]
 8005bd2:	4a33      	ldr	r2, [pc, #204]	@ (8005ca0 <HAL_DMA_Start_IT+0x1f8>)
 8005bd4:	4293      	cmp	r3, r2
 8005bd6:	d045      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005bd8:	68fb      	ldr	r3, [r7, #12]
 8005bda:	681b      	ldr	r3, [r3, #0]
 8005bdc:	4a31      	ldr	r2, [pc, #196]	@ (8005ca4 <HAL_DMA_Start_IT+0x1fc>)
 8005bde:	4293      	cmp	r3, r2
 8005be0:	d040      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005be2:	68fb      	ldr	r3, [r7, #12]
 8005be4:	681b      	ldr	r3, [r3, #0]
 8005be6:	4a30      	ldr	r2, [pc, #192]	@ (8005ca8 <HAL_DMA_Start_IT+0x200>)
 8005be8:	4293      	cmp	r3, r2
 8005bea:	d03b      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005bec:	68fb      	ldr	r3, [r7, #12]
 8005bee:	681b      	ldr	r3, [r3, #0]
 8005bf0:	4a2e      	ldr	r2, [pc, #184]	@ (8005cac <HAL_DMA_Start_IT+0x204>)
 8005bf2:	4293      	cmp	r3, r2
 8005bf4:	d036      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005bf6:	68fb      	ldr	r3, [r7, #12]
 8005bf8:	681b      	ldr	r3, [r3, #0]
 8005bfa:	4a2d      	ldr	r2, [pc, #180]	@ (8005cb0 <HAL_DMA_Start_IT+0x208>)
 8005bfc:	4293      	cmp	r3, r2
 8005bfe:	d031      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005c00:	68fb      	ldr	r3, [r7, #12]
 8005c02:	681b      	ldr	r3, [r3, #0]
 8005c04:	4a2b      	ldr	r2, [pc, #172]	@ (8005cb4 <HAL_DMA_Start_IT+0x20c>)
 8005c06:	4293      	cmp	r3, r2
 8005c08:	d02c      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005c0a:	68fb      	ldr	r3, [r7, #12]
 8005c0c:	681b      	ldr	r3, [r3, #0]
 8005c0e:	4a2a      	ldr	r2, [pc, #168]	@ (8005cb8 <HAL_DMA_Start_IT+0x210>)
 8005c10:	4293      	cmp	r3, r2
 8005c12:	d027      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005c14:	68fb      	ldr	r3, [r7, #12]
 8005c16:	681b      	ldr	r3, [r3, #0]
 8005c18:	4a28      	ldr	r2, [pc, #160]	@ (8005cbc <HAL_DMA_Start_IT+0x214>)
 8005c1a:	4293      	cmp	r3, r2
 8005c1c:	d022      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005c1e:	68fb      	ldr	r3, [r7, #12]
 8005c20:	681b      	ldr	r3, [r3, #0]
 8005c22:	4a27      	ldr	r2, [pc, #156]	@ (8005cc0 <HAL_DMA_Start_IT+0x218>)
 8005c24:	4293      	cmp	r3, r2
 8005c26:	d01d      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005c28:	68fb      	ldr	r3, [r7, #12]
 8005c2a:	681b      	ldr	r3, [r3, #0]
 8005c2c:	4a25      	ldr	r2, [pc, #148]	@ (8005cc4 <HAL_DMA_Start_IT+0x21c>)
 8005c2e:	4293      	cmp	r3, r2
 8005c30:	d018      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005c32:	68fb      	ldr	r3, [r7, #12]
 8005c34:	681b      	ldr	r3, [r3, #0]
 8005c36:	4a24      	ldr	r2, [pc, #144]	@ (8005cc8 <HAL_DMA_Start_IT+0x220>)
 8005c38:	4293      	cmp	r3, r2
 8005c3a:	d013      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005c3c:	68fb      	ldr	r3, [r7, #12]
 8005c3e:	681b      	ldr	r3, [r3, #0]
 8005c40:	4a22      	ldr	r2, [pc, #136]	@ (8005ccc <HAL_DMA_Start_IT+0x224>)
 8005c42:	4293      	cmp	r3, r2
 8005c44:	d00e      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005c46:	68fb      	ldr	r3, [r7, #12]
 8005c48:	681b      	ldr	r3, [r3, #0]
 8005c4a:	4a21      	ldr	r2, [pc, #132]	@ (8005cd0 <HAL_DMA_Start_IT+0x228>)
 8005c4c:	4293      	cmp	r3, r2
 8005c4e:	d009      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005c50:	68fb      	ldr	r3, [r7, #12]
 8005c52:	681b      	ldr	r3, [r3, #0]
 8005c54:	4a1f      	ldr	r2, [pc, #124]	@ (8005cd4 <HAL_DMA_Start_IT+0x22c>)
 8005c56:	4293      	cmp	r3, r2
 8005c58:	d004      	beq.n	8005c64 <HAL_DMA_Start_IT+0x1bc>
 8005c5a:	68fb      	ldr	r3, [r7, #12]
 8005c5c:	681b      	ldr	r3, [r3, #0]
 8005c5e:	4a1e      	ldr	r2, [pc, #120]	@ (8005cd8 <HAL_DMA_Start_IT+0x230>)
 8005c60:	4293      	cmp	r3, r2
 8005c62:	d101      	bne.n	8005c68 <HAL_DMA_Start_IT+0x1c0>
 8005c64:	2301      	movs	r3, #1
 8005c66:	e000      	b.n	8005c6a <HAL_DMA_Start_IT+0x1c2>
 8005c68:	2300      	movs	r3, #0
 8005c6a:	2b00      	cmp	r3, #0
 8005c6c:	d036      	beq.n	8005cdc <HAL_DMA_Start_IT+0x234>
    {
      /* Enable Common interrupts*/
      MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
 8005c6e:	68fb      	ldr	r3, [r7, #12]
 8005c70:	681b      	ldr	r3, [r3, #0]
 8005c72:	681b      	ldr	r3, [r3, #0]
 8005c74:	f023 021e 	bic.w	r2, r3, #30
 8005c78:	68fb      	ldr	r3, [r7, #12]
 8005c7a:	681b      	ldr	r3, [r3, #0]
 8005c7c:	f042 0216 	orr.w	r2, r2, #22
 8005c80:	601a      	str	r2, [r3, #0]

      if(hdma->XferHalfCpltCallback != NULL)
 8005c82:	68fb      	ldr	r3, [r7, #12]
 8005c84:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005c86:	2b00      	cmp	r3, #0
 8005c88:	d03e      	beq.n	8005d08 <HAL_DMA_Start_IT+0x260>
      {
        /* Enable Half Transfer IT if corresponding Callback is set */
        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
 8005c8a:	68fb      	ldr	r3, [r7, #12]
 8005c8c:	681b      	ldr	r3, [r3, #0]
 8005c8e:	681a      	ldr	r2, [r3, #0]
 8005c90:	68fb      	ldr	r3, [r7, #12]
 8005c92:	681b      	ldr	r3, [r3, #0]
 8005c94:	f042 0208 	orr.w	r2, r2, #8
 8005c98:	601a      	str	r2, [r3, #0]
 8005c9a:	e035      	b.n	8005d08 <HAL_DMA_Start_IT+0x260>
 8005c9c:	40020010 	.word	0x40020010
 8005ca0:	40020028 	.word	0x40020028
 8005ca4:	40020040 	.word	0x40020040
 8005ca8:	40020058 	.word	0x40020058
 8005cac:	40020070 	.word	0x40020070
 8005cb0:	40020088 	.word	0x40020088
 8005cb4:	400200a0 	.word	0x400200a0
 8005cb8:	400200b8 	.word	0x400200b8
 8005cbc:	40020410 	.word	0x40020410
 8005cc0:	40020428 	.word	0x40020428
 8005cc4:	40020440 	.word	0x40020440
 8005cc8:	40020458 	.word	0x40020458
 8005ccc:	40020470 	.word	0x40020470
 8005cd0:	40020488 	.word	0x40020488
 8005cd4:	400204a0 	.word	0x400204a0
 8005cd8:	400204b8 	.word	0x400204b8
      }
    }
    else /* BDMA channel */
    {
      /* Enable Common interrupts */
      MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
 8005cdc:	68fb      	ldr	r3, [r7, #12]
 8005cde:	681b      	ldr	r3, [r3, #0]
 8005ce0:	681b      	ldr	r3, [r3, #0]
 8005ce2:	f023 020e 	bic.w	r2, r3, #14
 8005ce6:	68fb      	ldr	r3, [r7, #12]
 8005ce8:	681b      	ldr	r3, [r3, #0]
 8005cea:	f042 020a 	orr.w	r2, r2, #10
 8005cee:	601a      	str	r2, [r3, #0]

      if(hdma->XferHalfCpltCallback != NULL)
 8005cf0:	68fb      	ldr	r3, [r7, #12]
 8005cf2:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005cf4:	2b00      	cmp	r3, #0
 8005cf6:	d007      	beq.n	8005d08 <HAL_DMA_Start_IT+0x260>
      {
        /*Enable Half Transfer IT if corresponding Callback is set */
        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
 8005cf8:	68fb      	ldr	r3, [r7, #12]
 8005cfa:	681b      	ldr	r3, [r3, #0]
 8005cfc:	681a      	ldr	r2, [r3, #0]
 8005cfe:	68fb      	ldr	r3, [r7, #12]
 8005d00:	681b      	ldr	r3, [r3, #0]
 8005d02:	f042 0204 	orr.w	r2, r2, #4
 8005d06:	601a      	str	r2, [r3, #0]
      }
    }

    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
 8005d08:	68fb      	ldr	r3, [r7, #12]
 8005d0a:	681b      	ldr	r3, [r3, #0]
 8005d0c:	4a83      	ldr	r2, [pc, #524]	@ (8005f1c <HAL_DMA_Start_IT+0x474>)
 8005d0e:	4293      	cmp	r3, r2
 8005d10:	d072      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d12:	68fb      	ldr	r3, [r7, #12]
 8005d14:	681b      	ldr	r3, [r3, #0]
 8005d16:	4a82      	ldr	r2, [pc, #520]	@ (8005f20 <HAL_DMA_Start_IT+0x478>)
 8005d18:	4293      	cmp	r3, r2
 8005d1a:	d06d      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d1c:	68fb      	ldr	r3, [r7, #12]
 8005d1e:	681b      	ldr	r3, [r3, #0]
 8005d20:	4a80      	ldr	r2, [pc, #512]	@ (8005f24 <HAL_DMA_Start_IT+0x47c>)
 8005d22:	4293      	cmp	r3, r2
 8005d24:	d068      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d26:	68fb      	ldr	r3, [r7, #12]
 8005d28:	681b      	ldr	r3, [r3, #0]
 8005d2a:	4a7f      	ldr	r2, [pc, #508]	@ (8005f28 <HAL_DMA_Start_IT+0x480>)
 8005d2c:	4293      	cmp	r3, r2
 8005d2e:	d063      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d30:	68fb      	ldr	r3, [r7, #12]
 8005d32:	681b      	ldr	r3, [r3, #0]
 8005d34:	4a7d      	ldr	r2, [pc, #500]	@ (8005f2c <HAL_DMA_Start_IT+0x484>)
 8005d36:	4293      	cmp	r3, r2
 8005d38:	d05e      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d3a:	68fb      	ldr	r3, [r7, #12]
 8005d3c:	681b      	ldr	r3, [r3, #0]
 8005d3e:	4a7c      	ldr	r2, [pc, #496]	@ (8005f30 <HAL_DMA_Start_IT+0x488>)
 8005d40:	4293      	cmp	r3, r2
 8005d42:	d059      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d44:	68fb      	ldr	r3, [r7, #12]
 8005d46:	681b      	ldr	r3, [r3, #0]
 8005d48:	4a7a      	ldr	r2, [pc, #488]	@ (8005f34 <HAL_DMA_Start_IT+0x48c>)
 8005d4a:	4293      	cmp	r3, r2
 8005d4c:	d054      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d4e:	68fb      	ldr	r3, [r7, #12]
 8005d50:	681b      	ldr	r3, [r3, #0]
 8005d52:	4a79      	ldr	r2, [pc, #484]	@ (8005f38 <HAL_DMA_Start_IT+0x490>)
 8005d54:	4293      	cmp	r3, r2
 8005d56:	d04f      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d58:	68fb      	ldr	r3, [r7, #12]
 8005d5a:	681b      	ldr	r3, [r3, #0]
 8005d5c:	4a77      	ldr	r2, [pc, #476]	@ (8005f3c <HAL_DMA_Start_IT+0x494>)
 8005d5e:	4293      	cmp	r3, r2
 8005d60:	d04a      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d62:	68fb      	ldr	r3, [r7, #12]
 8005d64:	681b      	ldr	r3, [r3, #0]
 8005d66:	4a76      	ldr	r2, [pc, #472]	@ (8005f40 <HAL_DMA_Start_IT+0x498>)
 8005d68:	4293      	cmp	r3, r2
 8005d6a:	d045      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d6c:	68fb      	ldr	r3, [r7, #12]
 8005d6e:	681b      	ldr	r3, [r3, #0]
 8005d70:	4a74      	ldr	r2, [pc, #464]	@ (8005f44 <HAL_DMA_Start_IT+0x49c>)
 8005d72:	4293      	cmp	r3, r2
 8005d74:	d040      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d76:	68fb      	ldr	r3, [r7, #12]
 8005d78:	681b      	ldr	r3, [r3, #0]
 8005d7a:	4a73      	ldr	r2, [pc, #460]	@ (8005f48 <HAL_DMA_Start_IT+0x4a0>)
 8005d7c:	4293      	cmp	r3, r2
 8005d7e:	d03b      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d80:	68fb      	ldr	r3, [r7, #12]
 8005d82:	681b      	ldr	r3, [r3, #0]
 8005d84:	4a71      	ldr	r2, [pc, #452]	@ (8005f4c <HAL_DMA_Start_IT+0x4a4>)
 8005d86:	4293      	cmp	r3, r2
 8005d88:	d036      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d8a:	68fb      	ldr	r3, [r7, #12]
 8005d8c:	681b      	ldr	r3, [r3, #0]
 8005d8e:	4a70      	ldr	r2, [pc, #448]	@ (8005f50 <HAL_DMA_Start_IT+0x4a8>)
 8005d90:	4293      	cmp	r3, r2
 8005d92:	d031      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d94:	68fb      	ldr	r3, [r7, #12]
 8005d96:	681b      	ldr	r3, [r3, #0]
 8005d98:	4a6e      	ldr	r2, [pc, #440]	@ (8005f54 <HAL_DMA_Start_IT+0x4ac>)
 8005d9a:	4293      	cmp	r3, r2
 8005d9c:	d02c      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005d9e:	68fb      	ldr	r3, [r7, #12]
 8005da0:	681b      	ldr	r3, [r3, #0]
 8005da2:	4a6d      	ldr	r2, [pc, #436]	@ (8005f58 <HAL_DMA_Start_IT+0x4b0>)
 8005da4:	4293      	cmp	r3, r2
 8005da6:	d027      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005da8:	68fb      	ldr	r3, [r7, #12]
 8005daa:	681b      	ldr	r3, [r3, #0]
 8005dac:	4a6b      	ldr	r2, [pc, #428]	@ (8005f5c <HAL_DMA_Start_IT+0x4b4>)
 8005dae:	4293      	cmp	r3, r2
 8005db0:	d022      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005db2:	68fb      	ldr	r3, [r7, #12]
 8005db4:	681b      	ldr	r3, [r3, #0]
 8005db6:	4a6a      	ldr	r2, [pc, #424]	@ (8005f60 <HAL_DMA_Start_IT+0x4b8>)
 8005db8:	4293      	cmp	r3, r2
 8005dba:	d01d      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005dbc:	68fb      	ldr	r3, [r7, #12]
 8005dbe:	681b      	ldr	r3, [r3, #0]
 8005dc0:	4a68      	ldr	r2, [pc, #416]	@ (8005f64 <HAL_DMA_Start_IT+0x4bc>)
 8005dc2:	4293      	cmp	r3, r2
 8005dc4:	d018      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005dc6:	68fb      	ldr	r3, [r7, #12]
 8005dc8:	681b      	ldr	r3, [r3, #0]
 8005dca:	4a67      	ldr	r2, [pc, #412]	@ (8005f68 <HAL_DMA_Start_IT+0x4c0>)
 8005dcc:	4293      	cmp	r3, r2
 8005dce:	d013      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005dd0:	68fb      	ldr	r3, [r7, #12]
 8005dd2:	681b      	ldr	r3, [r3, #0]
 8005dd4:	4a65      	ldr	r2, [pc, #404]	@ (8005f6c <HAL_DMA_Start_IT+0x4c4>)
 8005dd6:	4293      	cmp	r3, r2
 8005dd8:	d00e      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005dda:	68fb      	ldr	r3, [r7, #12]
 8005ddc:	681b      	ldr	r3, [r3, #0]
 8005dde:	4a64      	ldr	r2, [pc, #400]	@ (8005f70 <HAL_DMA_Start_IT+0x4c8>)
 8005de0:	4293      	cmp	r3, r2
 8005de2:	d009      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005de4:	68fb      	ldr	r3, [r7, #12]
 8005de6:	681b      	ldr	r3, [r3, #0]
 8005de8:	4a62      	ldr	r2, [pc, #392]	@ (8005f74 <HAL_DMA_Start_IT+0x4cc>)
 8005dea:	4293      	cmp	r3, r2
 8005dec:	d004      	beq.n	8005df8 <HAL_DMA_Start_IT+0x350>
 8005dee:	68fb      	ldr	r3, [r7, #12]
 8005df0:	681b      	ldr	r3, [r3, #0]
 8005df2:	4a61      	ldr	r2, [pc, #388]	@ (8005f78 <HAL_DMA_Start_IT+0x4d0>)
 8005df4:	4293      	cmp	r3, r2
 8005df6:	d101      	bne.n	8005dfc <HAL_DMA_Start_IT+0x354>
 8005df8:	2301      	movs	r3, #1
 8005dfa:	e000      	b.n	8005dfe <HAL_DMA_Start_IT+0x356>
 8005dfc:	2300      	movs	r3, #0
 8005dfe:	2b00      	cmp	r3, #0
 8005e00:	d01a      	beq.n	8005e38 <HAL_DMA_Start_IT+0x390>
    {
      /* Check if DMAMUX Synchronization is enabled */
      if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
 8005e02:	68fb      	ldr	r3, [r7, #12]
 8005e04:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8005e06:	681b      	ldr	r3, [r3, #0]
 8005e08:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 8005e0c:	2b00      	cmp	r3, #0
 8005e0e:	d007      	beq.n	8005e20 <HAL_DMA_Start_IT+0x378>
      {
        /* Enable DMAMUX sync overrun IT*/
        hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
 8005e10:	68fb      	ldr	r3, [r7, #12]
 8005e12:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8005e14:	681a      	ldr	r2, [r3, #0]
 8005e16:	68fb      	ldr	r3, [r7, #12]
 8005e18:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8005e1a:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
 8005e1e:	601a      	str	r2, [r3, #0]
      }

      if(hdma->DMAmuxRequestGen != 0U)
 8005e20:	68fb      	ldr	r3, [r7, #12]
 8005e22:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8005e24:	2b00      	cmp	r3, #0
 8005e26:	d007      	beq.n	8005e38 <HAL_DMA_Start_IT+0x390>
      {
        /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
        /* enable the request gen overrun IT */
        hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
 8005e28:	68fb      	ldr	r3, [r7, #12]
 8005e2a:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8005e2c:	681a      	ldr	r2, [r3, #0]
 8005e2e:	68fb      	ldr	r3, [r7, #12]
 8005e30:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8005e32:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
 8005e36:	601a      	str	r2, [r3, #0]
      }
    }

    /* Enable the Peripheral */
    __HAL_DMA_ENABLE(hdma);
 8005e38:	68fb      	ldr	r3, [r7, #12]
 8005e3a:	681b      	ldr	r3, [r3, #0]
 8005e3c:	4a37      	ldr	r2, [pc, #220]	@ (8005f1c <HAL_DMA_Start_IT+0x474>)
 8005e3e:	4293      	cmp	r3, r2
 8005e40:	d04a      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005e42:	68fb      	ldr	r3, [r7, #12]
 8005e44:	681b      	ldr	r3, [r3, #0]
 8005e46:	4a36      	ldr	r2, [pc, #216]	@ (8005f20 <HAL_DMA_Start_IT+0x478>)
 8005e48:	4293      	cmp	r3, r2
 8005e4a:	d045      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005e4c:	68fb      	ldr	r3, [r7, #12]
 8005e4e:	681b      	ldr	r3, [r3, #0]
 8005e50:	4a34      	ldr	r2, [pc, #208]	@ (8005f24 <HAL_DMA_Start_IT+0x47c>)
 8005e52:	4293      	cmp	r3, r2
 8005e54:	d040      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005e56:	68fb      	ldr	r3, [r7, #12]
 8005e58:	681b      	ldr	r3, [r3, #0]
 8005e5a:	4a33      	ldr	r2, [pc, #204]	@ (8005f28 <HAL_DMA_Start_IT+0x480>)
 8005e5c:	4293      	cmp	r3, r2
 8005e5e:	d03b      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005e60:	68fb      	ldr	r3, [r7, #12]
 8005e62:	681b      	ldr	r3, [r3, #0]
 8005e64:	4a31      	ldr	r2, [pc, #196]	@ (8005f2c <HAL_DMA_Start_IT+0x484>)
 8005e66:	4293      	cmp	r3, r2
 8005e68:	d036      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005e6a:	68fb      	ldr	r3, [r7, #12]
 8005e6c:	681b      	ldr	r3, [r3, #0]
 8005e6e:	4a30      	ldr	r2, [pc, #192]	@ (8005f30 <HAL_DMA_Start_IT+0x488>)
 8005e70:	4293      	cmp	r3, r2
 8005e72:	d031      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005e74:	68fb      	ldr	r3, [r7, #12]
 8005e76:	681b      	ldr	r3, [r3, #0]
 8005e78:	4a2e      	ldr	r2, [pc, #184]	@ (8005f34 <HAL_DMA_Start_IT+0x48c>)
 8005e7a:	4293      	cmp	r3, r2
 8005e7c:	d02c      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005e7e:	68fb      	ldr	r3, [r7, #12]
 8005e80:	681b      	ldr	r3, [r3, #0]
 8005e82:	4a2d      	ldr	r2, [pc, #180]	@ (8005f38 <HAL_DMA_Start_IT+0x490>)
 8005e84:	4293      	cmp	r3, r2
 8005e86:	d027      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005e88:	68fb      	ldr	r3, [r7, #12]
 8005e8a:	681b      	ldr	r3, [r3, #0]
 8005e8c:	4a2b      	ldr	r2, [pc, #172]	@ (8005f3c <HAL_DMA_Start_IT+0x494>)
 8005e8e:	4293      	cmp	r3, r2
 8005e90:	d022      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005e92:	68fb      	ldr	r3, [r7, #12]
 8005e94:	681b      	ldr	r3, [r3, #0]
 8005e96:	4a2a      	ldr	r2, [pc, #168]	@ (8005f40 <HAL_DMA_Start_IT+0x498>)
 8005e98:	4293      	cmp	r3, r2
 8005e9a:	d01d      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005e9c:	68fb      	ldr	r3, [r7, #12]
 8005e9e:	681b      	ldr	r3, [r3, #0]
 8005ea0:	4a28      	ldr	r2, [pc, #160]	@ (8005f44 <HAL_DMA_Start_IT+0x49c>)
 8005ea2:	4293      	cmp	r3, r2
 8005ea4:	d018      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005ea6:	68fb      	ldr	r3, [r7, #12]
 8005ea8:	681b      	ldr	r3, [r3, #0]
 8005eaa:	4a27      	ldr	r2, [pc, #156]	@ (8005f48 <HAL_DMA_Start_IT+0x4a0>)
 8005eac:	4293      	cmp	r3, r2
 8005eae:	d013      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005eb0:	68fb      	ldr	r3, [r7, #12]
 8005eb2:	681b      	ldr	r3, [r3, #0]
 8005eb4:	4a25      	ldr	r2, [pc, #148]	@ (8005f4c <HAL_DMA_Start_IT+0x4a4>)
 8005eb6:	4293      	cmp	r3, r2
 8005eb8:	d00e      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005eba:	68fb      	ldr	r3, [r7, #12]
 8005ebc:	681b      	ldr	r3, [r3, #0]
 8005ebe:	4a24      	ldr	r2, [pc, #144]	@ (8005f50 <HAL_DMA_Start_IT+0x4a8>)
 8005ec0:	4293      	cmp	r3, r2
 8005ec2:	d009      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005ec4:	68fb      	ldr	r3, [r7, #12]
 8005ec6:	681b      	ldr	r3, [r3, #0]
 8005ec8:	4a22      	ldr	r2, [pc, #136]	@ (8005f54 <HAL_DMA_Start_IT+0x4ac>)
 8005eca:	4293      	cmp	r3, r2
 8005ecc:	d004      	beq.n	8005ed8 <HAL_DMA_Start_IT+0x430>
 8005ece:	68fb      	ldr	r3, [r7, #12]
 8005ed0:	681b      	ldr	r3, [r3, #0]
 8005ed2:	4a21      	ldr	r2, [pc, #132]	@ (8005f58 <HAL_DMA_Start_IT+0x4b0>)
 8005ed4:	4293      	cmp	r3, r2
 8005ed6:	d108      	bne.n	8005eea <HAL_DMA_Start_IT+0x442>
 8005ed8:	68fb      	ldr	r3, [r7, #12]
 8005eda:	681b      	ldr	r3, [r3, #0]
 8005edc:	681a      	ldr	r2, [r3, #0]
 8005ede:	68fb      	ldr	r3, [r7, #12]
 8005ee0:	681b      	ldr	r3, [r3, #0]
 8005ee2:	f042 0201 	orr.w	r2, r2, #1
 8005ee6:	601a      	str	r2, [r3, #0]
 8005ee8:	e012      	b.n	8005f10 <HAL_DMA_Start_IT+0x468>
 8005eea:	68fb      	ldr	r3, [r7, #12]
 8005eec:	681b      	ldr	r3, [r3, #0]
 8005eee:	681a      	ldr	r2, [r3, #0]
 8005ef0:	68fb      	ldr	r3, [r7, #12]
 8005ef2:	681b      	ldr	r3, [r3, #0]
 8005ef4:	f042 0201 	orr.w	r2, r2, #1
 8005ef8:	601a      	str	r2, [r3, #0]
 8005efa:	e009      	b.n	8005f10 <HAL_DMA_Start_IT+0x468>
  }
  else
  {
    /* Set the error code to busy */
    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
 8005efc:	68fb      	ldr	r3, [r7, #12]
 8005efe:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 8005f02:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Process unlocked */
    __HAL_UNLOCK(hdma);
 8005f04:	68fb      	ldr	r3, [r7, #12]
 8005f06:	2200      	movs	r2, #0
 8005f08:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

    /* Return error status */
    status = HAL_ERROR;
 8005f0c:	2301      	movs	r3, #1
 8005f0e:	75fb      	strb	r3, [r7, #23]
  }

  return status;
 8005f10:	7dfb      	ldrb	r3, [r7, #23]
}
 8005f12:	4618      	mov	r0, r3
 8005f14:	3718      	adds	r7, #24
 8005f16:	46bd      	mov	sp, r7
 8005f18:	bd80      	pop	{r7, pc}
 8005f1a:	bf00      	nop
 8005f1c:	40020010 	.word	0x40020010
 8005f20:	40020028 	.word	0x40020028
 8005f24:	40020040 	.word	0x40020040
 8005f28:	40020058 	.word	0x40020058
 8005f2c:	40020070 	.word	0x40020070
 8005f30:	40020088 	.word	0x40020088
 8005f34:	400200a0 	.word	0x400200a0
 8005f38:	400200b8 	.word	0x400200b8
 8005f3c:	40020410 	.word	0x40020410
 8005f40:	40020428 	.word	0x40020428
 8005f44:	40020440 	.word	0x40020440
 8005f48:	40020458 	.word	0x40020458
 8005f4c:	40020470 	.word	0x40020470
 8005f50:	40020488 	.word	0x40020488
 8005f54:	400204a0 	.word	0x400204a0
 8005f58:	400204b8 	.word	0x400204b8
 8005f5c:	58025408 	.word	0x58025408
 8005f60:	5802541c 	.word	0x5802541c
 8005f64:	58025430 	.word	0x58025430
 8005f68:	58025444 	.word	0x58025444
 8005f6c:	58025458 	.word	0x58025458
 8005f70:	5802546c 	.word	0x5802546c
 8005f74:	58025480 	.word	0x58025480
 8005f78:	58025494 	.word	0x58025494

08005f7c <HAL_DMA_Abort>:
  *        and the Stream will be effectively disabled only after the transfer of
  *        this single data is finished.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
 8005f7c:	b580      	push	{r7, lr}
 8005f7e:	b086      	sub	sp, #24
 8005f80:	af00      	add	r7, sp, #0
 8005f82:	6078      	str	r0, [r7, #4]
  /* calculate DMA base and stream number */
  DMA_Base_Registers *regs_dma;
  BDMA_Base_Registers *regs_bdma;
  const __IO uint32_t *enableRegister;

  uint32_t tickstart = HAL_GetTick();
 8005f84:	f7fd fa9e 	bl	80034c4 <HAL_GetTick>
 8005f88:	6138      	str	r0, [r7, #16]

 /* Check the DMA peripheral handle */
  if(hdma == NULL)
 8005f8a:	687b      	ldr	r3, [r7, #4]
 8005f8c:	2b00      	cmp	r3, #0
 8005f8e:	d101      	bne.n	8005f94 <HAL_DMA_Abort+0x18>
  {
    return HAL_ERROR;
 8005f90:	2301      	movs	r3, #1
 8005f92:	e2dc      	b.n	800654e <HAL_DMA_Abort+0x5d2>
  }

  /* Check the DMA peripheral state */
  if(hdma->State != HAL_DMA_STATE_BUSY)
 8005f94:	687b      	ldr	r3, [r7, #4]
 8005f96:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
 8005f9a:	b2db      	uxtb	r3, r3
 8005f9c:	2b02      	cmp	r3, #2
 8005f9e:	d008      	beq.n	8005fb2 <HAL_DMA_Abort+0x36>
  {
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 8005fa0:	687b      	ldr	r3, [r7, #4]
 8005fa2:	2280      	movs	r2, #128	@ 0x80
 8005fa4:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8005fa6:	687b      	ldr	r3, [r7, #4]
 8005fa8:	2200      	movs	r2, #0
 8005faa:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

    return HAL_ERROR;
 8005fae:	2301      	movs	r3, #1
 8005fb0:	e2cd      	b.n	800654e <HAL_DMA_Abort+0x5d2>
  }
  else
  {
    /* Disable all the transfer interrupts */
    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 8005fb2:	687b      	ldr	r3, [r7, #4]
 8005fb4:	681b      	ldr	r3, [r3, #0]
 8005fb6:	4a76      	ldr	r2, [pc, #472]	@ (8006190 <HAL_DMA_Abort+0x214>)
 8005fb8:	4293      	cmp	r3, r2
 8005fba:	d04a      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 8005fbc:	687b      	ldr	r3, [r7, #4]
 8005fbe:	681b      	ldr	r3, [r3, #0]
 8005fc0:	4a74      	ldr	r2, [pc, #464]	@ (8006194 <HAL_DMA_Abort+0x218>)
 8005fc2:	4293      	cmp	r3, r2
 8005fc4:	d045      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 8005fc6:	687b      	ldr	r3, [r7, #4]
 8005fc8:	681b      	ldr	r3, [r3, #0]
 8005fca:	4a73      	ldr	r2, [pc, #460]	@ (8006198 <HAL_DMA_Abort+0x21c>)
 8005fcc:	4293      	cmp	r3, r2
 8005fce:	d040      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 8005fd0:	687b      	ldr	r3, [r7, #4]
 8005fd2:	681b      	ldr	r3, [r3, #0]
 8005fd4:	4a71      	ldr	r2, [pc, #452]	@ (800619c <HAL_DMA_Abort+0x220>)
 8005fd6:	4293      	cmp	r3, r2
 8005fd8:	d03b      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 8005fda:	687b      	ldr	r3, [r7, #4]
 8005fdc:	681b      	ldr	r3, [r3, #0]
 8005fde:	4a70      	ldr	r2, [pc, #448]	@ (80061a0 <HAL_DMA_Abort+0x224>)
 8005fe0:	4293      	cmp	r3, r2
 8005fe2:	d036      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 8005fe4:	687b      	ldr	r3, [r7, #4]
 8005fe6:	681b      	ldr	r3, [r3, #0]
 8005fe8:	4a6e      	ldr	r2, [pc, #440]	@ (80061a4 <HAL_DMA_Abort+0x228>)
 8005fea:	4293      	cmp	r3, r2
 8005fec:	d031      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 8005fee:	687b      	ldr	r3, [r7, #4]
 8005ff0:	681b      	ldr	r3, [r3, #0]
 8005ff2:	4a6d      	ldr	r2, [pc, #436]	@ (80061a8 <HAL_DMA_Abort+0x22c>)
 8005ff4:	4293      	cmp	r3, r2
 8005ff6:	d02c      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 8005ff8:	687b      	ldr	r3, [r7, #4]
 8005ffa:	681b      	ldr	r3, [r3, #0]
 8005ffc:	4a6b      	ldr	r2, [pc, #428]	@ (80061ac <HAL_DMA_Abort+0x230>)
 8005ffe:	4293      	cmp	r3, r2
 8006000:	d027      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 8006002:	687b      	ldr	r3, [r7, #4]
 8006004:	681b      	ldr	r3, [r3, #0]
 8006006:	4a6a      	ldr	r2, [pc, #424]	@ (80061b0 <HAL_DMA_Abort+0x234>)
 8006008:	4293      	cmp	r3, r2
 800600a:	d022      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 800600c:	687b      	ldr	r3, [r7, #4]
 800600e:	681b      	ldr	r3, [r3, #0]
 8006010:	4a68      	ldr	r2, [pc, #416]	@ (80061b4 <HAL_DMA_Abort+0x238>)
 8006012:	4293      	cmp	r3, r2
 8006014:	d01d      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 8006016:	687b      	ldr	r3, [r7, #4]
 8006018:	681b      	ldr	r3, [r3, #0]
 800601a:	4a67      	ldr	r2, [pc, #412]	@ (80061b8 <HAL_DMA_Abort+0x23c>)
 800601c:	4293      	cmp	r3, r2
 800601e:	d018      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 8006020:	687b      	ldr	r3, [r7, #4]
 8006022:	681b      	ldr	r3, [r3, #0]
 8006024:	4a65      	ldr	r2, [pc, #404]	@ (80061bc <HAL_DMA_Abort+0x240>)
 8006026:	4293      	cmp	r3, r2
 8006028:	d013      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 800602a:	687b      	ldr	r3, [r7, #4]
 800602c:	681b      	ldr	r3, [r3, #0]
 800602e:	4a64      	ldr	r2, [pc, #400]	@ (80061c0 <HAL_DMA_Abort+0x244>)
 8006030:	4293      	cmp	r3, r2
 8006032:	d00e      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 8006034:	687b      	ldr	r3, [r7, #4]
 8006036:	681b      	ldr	r3, [r3, #0]
 8006038:	4a62      	ldr	r2, [pc, #392]	@ (80061c4 <HAL_DMA_Abort+0x248>)
 800603a:	4293      	cmp	r3, r2
 800603c:	d009      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 800603e:	687b      	ldr	r3, [r7, #4]
 8006040:	681b      	ldr	r3, [r3, #0]
 8006042:	4a61      	ldr	r2, [pc, #388]	@ (80061c8 <HAL_DMA_Abort+0x24c>)
 8006044:	4293      	cmp	r3, r2
 8006046:	d004      	beq.n	8006052 <HAL_DMA_Abort+0xd6>
 8006048:	687b      	ldr	r3, [r7, #4]
 800604a:	681b      	ldr	r3, [r3, #0]
 800604c:	4a5f      	ldr	r2, [pc, #380]	@ (80061cc <HAL_DMA_Abort+0x250>)
 800604e:	4293      	cmp	r3, r2
 8006050:	d101      	bne.n	8006056 <HAL_DMA_Abort+0xda>
 8006052:	2301      	movs	r3, #1
 8006054:	e000      	b.n	8006058 <HAL_DMA_Abort+0xdc>
 8006056:	2300      	movs	r3, #0
 8006058:	2b00      	cmp	r3, #0
 800605a:	d013      	beq.n	8006084 <HAL_DMA_Abort+0x108>
    {
       /* Disable DMA All Interrupts  */
      ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
 800605c:	687b      	ldr	r3, [r7, #4]
 800605e:	681b      	ldr	r3, [r3, #0]
 8006060:	681a      	ldr	r2, [r3, #0]
 8006062:	687b      	ldr	r3, [r7, #4]
 8006064:	681b      	ldr	r3, [r3, #0]
 8006066:	f022 021e 	bic.w	r2, r2, #30
 800606a:	601a      	str	r2, [r3, #0]
      ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
 800606c:	687b      	ldr	r3, [r7, #4]
 800606e:	681b      	ldr	r3, [r3, #0]
 8006070:	695a      	ldr	r2, [r3, #20]
 8006072:	687b      	ldr	r3, [r7, #4]
 8006074:	681b      	ldr	r3, [r3, #0]
 8006076:	f022 0280 	bic.w	r2, r2, #128	@ 0x80
 800607a:	615a      	str	r2, [r3, #20]

      enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef   *)hdma->Instance)->CR));
 800607c:	687b      	ldr	r3, [r7, #4]
 800607e:	681b      	ldr	r3, [r3, #0]
 8006080:	617b      	str	r3, [r7, #20]
 8006082:	e00a      	b.n	800609a <HAL_DMA_Abort+0x11e>
    }
    else /* BDMA channel */
    {
      /* Disable DMA All Interrupts */
      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
 8006084:	687b      	ldr	r3, [r7, #4]
 8006086:	681b      	ldr	r3, [r3, #0]
 8006088:	681a      	ldr	r2, [r3, #0]
 800608a:	687b      	ldr	r3, [r7, #4]
 800608c:	681b      	ldr	r3, [r3, #0]
 800608e:	f022 020e 	bic.w	r2, r2, #14
 8006092:	601a      	str	r2, [r3, #0]

      enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR));
 8006094:	687b      	ldr	r3, [r7, #4]
 8006096:	681b      	ldr	r3, [r3, #0]
 8006098:	617b      	str	r3, [r7, #20]
    }

    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
 800609a:	687b      	ldr	r3, [r7, #4]
 800609c:	681b      	ldr	r3, [r3, #0]
 800609e:	4a3c      	ldr	r2, [pc, #240]	@ (8006190 <HAL_DMA_Abort+0x214>)
 80060a0:	4293      	cmp	r3, r2
 80060a2:	d072      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 80060a4:	687b      	ldr	r3, [r7, #4]
 80060a6:	681b      	ldr	r3, [r3, #0]
 80060a8:	4a3a      	ldr	r2, [pc, #232]	@ (8006194 <HAL_DMA_Abort+0x218>)
 80060aa:	4293      	cmp	r3, r2
 80060ac:	d06d      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 80060ae:	687b      	ldr	r3, [r7, #4]
 80060b0:	681b      	ldr	r3, [r3, #0]
 80060b2:	4a39      	ldr	r2, [pc, #228]	@ (8006198 <HAL_DMA_Abort+0x21c>)
 80060b4:	4293      	cmp	r3, r2
 80060b6:	d068      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 80060b8:	687b      	ldr	r3, [r7, #4]
 80060ba:	681b      	ldr	r3, [r3, #0]
 80060bc:	4a37      	ldr	r2, [pc, #220]	@ (800619c <HAL_DMA_Abort+0x220>)
 80060be:	4293      	cmp	r3, r2
 80060c0:	d063      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 80060c2:	687b      	ldr	r3, [r7, #4]
 80060c4:	681b      	ldr	r3, [r3, #0]
 80060c6:	4a36      	ldr	r2, [pc, #216]	@ (80061a0 <HAL_DMA_Abort+0x224>)
 80060c8:	4293      	cmp	r3, r2
 80060ca:	d05e      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 80060cc:	687b      	ldr	r3, [r7, #4]
 80060ce:	681b      	ldr	r3, [r3, #0]
 80060d0:	4a34      	ldr	r2, [pc, #208]	@ (80061a4 <HAL_DMA_Abort+0x228>)
 80060d2:	4293      	cmp	r3, r2
 80060d4:	d059      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 80060d6:	687b      	ldr	r3, [r7, #4]
 80060d8:	681b      	ldr	r3, [r3, #0]
 80060da:	4a33      	ldr	r2, [pc, #204]	@ (80061a8 <HAL_DMA_Abort+0x22c>)
 80060dc:	4293      	cmp	r3, r2
 80060de:	d054      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 80060e0:	687b      	ldr	r3, [r7, #4]
 80060e2:	681b      	ldr	r3, [r3, #0]
 80060e4:	4a31      	ldr	r2, [pc, #196]	@ (80061ac <HAL_DMA_Abort+0x230>)
 80060e6:	4293      	cmp	r3, r2
 80060e8:	d04f      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 80060ea:	687b      	ldr	r3, [r7, #4]
 80060ec:	681b      	ldr	r3, [r3, #0]
 80060ee:	4a30      	ldr	r2, [pc, #192]	@ (80061b0 <HAL_DMA_Abort+0x234>)
 80060f0:	4293      	cmp	r3, r2
 80060f2:	d04a      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 80060f4:	687b      	ldr	r3, [r7, #4]
 80060f6:	681b      	ldr	r3, [r3, #0]
 80060f8:	4a2e      	ldr	r2, [pc, #184]	@ (80061b4 <HAL_DMA_Abort+0x238>)
 80060fa:	4293      	cmp	r3, r2
 80060fc:	d045      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 80060fe:	687b      	ldr	r3, [r7, #4]
 8006100:	681b      	ldr	r3, [r3, #0]
 8006102:	4a2d      	ldr	r2, [pc, #180]	@ (80061b8 <HAL_DMA_Abort+0x23c>)
 8006104:	4293      	cmp	r3, r2
 8006106:	d040      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 8006108:	687b      	ldr	r3, [r7, #4]
 800610a:	681b      	ldr	r3, [r3, #0]
 800610c:	4a2b      	ldr	r2, [pc, #172]	@ (80061bc <HAL_DMA_Abort+0x240>)
 800610e:	4293      	cmp	r3, r2
 8006110:	d03b      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 8006112:	687b      	ldr	r3, [r7, #4]
 8006114:	681b      	ldr	r3, [r3, #0]
 8006116:	4a2a      	ldr	r2, [pc, #168]	@ (80061c0 <HAL_DMA_Abort+0x244>)
 8006118:	4293      	cmp	r3, r2
 800611a:	d036      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 800611c:	687b      	ldr	r3, [r7, #4]
 800611e:	681b      	ldr	r3, [r3, #0]
 8006120:	4a28      	ldr	r2, [pc, #160]	@ (80061c4 <HAL_DMA_Abort+0x248>)
 8006122:	4293      	cmp	r3, r2
 8006124:	d031      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 8006126:	687b      	ldr	r3, [r7, #4]
 8006128:	681b      	ldr	r3, [r3, #0]
 800612a:	4a27      	ldr	r2, [pc, #156]	@ (80061c8 <HAL_DMA_Abort+0x24c>)
 800612c:	4293      	cmp	r3, r2
 800612e:	d02c      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 8006130:	687b      	ldr	r3, [r7, #4]
 8006132:	681b      	ldr	r3, [r3, #0]
 8006134:	4a25      	ldr	r2, [pc, #148]	@ (80061cc <HAL_DMA_Abort+0x250>)
 8006136:	4293      	cmp	r3, r2
 8006138:	d027      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 800613a:	687b      	ldr	r3, [r7, #4]
 800613c:	681b      	ldr	r3, [r3, #0]
 800613e:	4a24      	ldr	r2, [pc, #144]	@ (80061d0 <HAL_DMA_Abort+0x254>)
 8006140:	4293      	cmp	r3, r2
 8006142:	d022      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 8006144:	687b      	ldr	r3, [r7, #4]
 8006146:	681b      	ldr	r3, [r3, #0]
 8006148:	4a22      	ldr	r2, [pc, #136]	@ (80061d4 <HAL_DMA_Abort+0x258>)
 800614a:	4293      	cmp	r3, r2
 800614c:	d01d      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 800614e:	687b      	ldr	r3, [r7, #4]
 8006150:	681b      	ldr	r3, [r3, #0]
 8006152:	4a21      	ldr	r2, [pc, #132]	@ (80061d8 <HAL_DMA_Abort+0x25c>)
 8006154:	4293      	cmp	r3, r2
 8006156:	d018      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 8006158:	687b      	ldr	r3, [r7, #4]
 800615a:	681b      	ldr	r3, [r3, #0]
 800615c:	4a1f      	ldr	r2, [pc, #124]	@ (80061dc <HAL_DMA_Abort+0x260>)
 800615e:	4293      	cmp	r3, r2
 8006160:	d013      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 8006162:	687b      	ldr	r3, [r7, #4]
 8006164:	681b      	ldr	r3, [r3, #0]
 8006166:	4a1e      	ldr	r2, [pc, #120]	@ (80061e0 <HAL_DMA_Abort+0x264>)
 8006168:	4293      	cmp	r3, r2
 800616a:	d00e      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 800616c:	687b      	ldr	r3, [r7, #4]
 800616e:	681b      	ldr	r3, [r3, #0]
 8006170:	4a1c      	ldr	r2, [pc, #112]	@ (80061e4 <HAL_DMA_Abort+0x268>)
 8006172:	4293      	cmp	r3, r2
 8006174:	d009      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 8006176:	687b      	ldr	r3, [r7, #4]
 8006178:	681b      	ldr	r3, [r3, #0]
 800617a:	4a1b      	ldr	r2, [pc, #108]	@ (80061e8 <HAL_DMA_Abort+0x26c>)
 800617c:	4293      	cmp	r3, r2
 800617e:	d004      	beq.n	800618a <HAL_DMA_Abort+0x20e>
 8006180:	687b      	ldr	r3, [r7, #4]
 8006182:	681b      	ldr	r3, [r3, #0]
 8006184:	4a19      	ldr	r2, [pc, #100]	@ (80061ec <HAL_DMA_Abort+0x270>)
 8006186:	4293      	cmp	r3, r2
 8006188:	d132      	bne.n	80061f0 <HAL_DMA_Abort+0x274>
 800618a:	2301      	movs	r3, #1
 800618c:	e031      	b.n	80061f2 <HAL_DMA_Abort+0x276>
 800618e:	bf00      	nop
 8006190:	40020010 	.word	0x40020010
 8006194:	40020028 	.word	0x40020028
 8006198:	40020040 	.word	0x40020040
 800619c:	40020058 	.word	0x40020058
 80061a0:	40020070 	.word	0x40020070
 80061a4:	40020088 	.word	0x40020088
 80061a8:	400200a0 	.word	0x400200a0
 80061ac:	400200b8 	.word	0x400200b8
 80061b0:	40020410 	.word	0x40020410
 80061b4:	40020428 	.word	0x40020428
 80061b8:	40020440 	.word	0x40020440
 80061bc:	40020458 	.word	0x40020458
 80061c0:	40020470 	.word	0x40020470
 80061c4:	40020488 	.word	0x40020488
 80061c8:	400204a0 	.word	0x400204a0
 80061cc:	400204b8 	.word	0x400204b8
 80061d0:	58025408 	.word	0x58025408
 80061d4:	5802541c 	.word	0x5802541c
 80061d8:	58025430 	.word	0x58025430
 80061dc:	58025444 	.word	0x58025444
 80061e0:	58025458 	.word	0x58025458
 80061e4:	5802546c 	.word	0x5802546c
 80061e8:	58025480 	.word	0x58025480
 80061ec:	58025494 	.word	0x58025494
 80061f0:	2300      	movs	r3, #0
 80061f2:	2b00      	cmp	r3, #0
 80061f4:	d007      	beq.n	8006206 <HAL_DMA_Abort+0x28a>
    {
      /* disable the DMAMUX sync overrun IT */
      hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
 80061f6:	687b      	ldr	r3, [r7, #4]
 80061f8:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80061fa:	681a      	ldr	r2, [r3, #0]
 80061fc:	687b      	ldr	r3, [r7, #4]
 80061fe:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8006200:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
 8006204:	601a      	str	r2, [r3, #0]
    }

    /* Disable the stream */
    __HAL_DMA_DISABLE(hdma);
 8006206:	687b      	ldr	r3, [r7, #4]
 8006208:	681b      	ldr	r3, [r3, #0]
 800620a:	4a6d      	ldr	r2, [pc, #436]	@ (80063c0 <HAL_DMA_Abort+0x444>)
 800620c:	4293      	cmp	r3, r2
 800620e:	d04a      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 8006210:	687b      	ldr	r3, [r7, #4]
 8006212:	681b      	ldr	r3, [r3, #0]
 8006214:	4a6b      	ldr	r2, [pc, #428]	@ (80063c4 <HAL_DMA_Abort+0x448>)
 8006216:	4293      	cmp	r3, r2
 8006218:	d045      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 800621a:	687b      	ldr	r3, [r7, #4]
 800621c:	681b      	ldr	r3, [r3, #0]
 800621e:	4a6a      	ldr	r2, [pc, #424]	@ (80063c8 <HAL_DMA_Abort+0x44c>)
 8006220:	4293      	cmp	r3, r2
 8006222:	d040      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 8006224:	687b      	ldr	r3, [r7, #4]
 8006226:	681b      	ldr	r3, [r3, #0]
 8006228:	4a68      	ldr	r2, [pc, #416]	@ (80063cc <HAL_DMA_Abort+0x450>)
 800622a:	4293      	cmp	r3, r2
 800622c:	d03b      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 800622e:	687b      	ldr	r3, [r7, #4]
 8006230:	681b      	ldr	r3, [r3, #0]
 8006232:	4a67      	ldr	r2, [pc, #412]	@ (80063d0 <HAL_DMA_Abort+0x454>)
 8006234:	4293      	cmp	r3, r2
 8006236:	d036      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 8006238:	687b      	ldr	r3, [r7, #4]
 800623a:	681b      	ldr	r3, [r3, #0]
 800623c:	4a65      	ldr	r2, [pc, #404]	@ (80063d4 <HAL_DMA_Abort+0x458>)
 800623e:	4293      	cmp	r3, r2
 8006240:	d031      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 8006242:	687b      	ldr	r3, [r7, #4]
 8006244:	681b      	ldr	r3, [r3, #0]
 8006246:	4a64      	ldr	r2, [pc, #400]	@ (80063d8 <HAL_DMA_Abort+0x45c>)
 8006248:	4293      	cmp	r3, r2
 800624a:	d02c      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 800624c:	687b      	ldr	r3, [r7, #4]
 800624e:	681b      	ldr	r3, [r3, #0]
 8006250:	4a62      	ldr	r2, [pc, #392]	@ (80063dc <HAL_DMA_Abort+0x460>)
 8006252:	4293      	cmp	r3, r2
 8006254:	d027      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 8006256:	687b      	ldr	r3, [r7, #4]
 8006258:	681b      	ldr	r3, [r3, #0]
 800625a:	4a61      	ldr	r2, [pc, #388]	@ (80063e0 <HAL_DMA_Abort+0x464>)
 800625c:	4293      	cmp	r3, r2
 800625e:	d022      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 8006260:	687b      	ldr	r3, [r7, #4]
 8006262:	681b      	ldr	r3, [r3, #0]
 8006264:	4a5f      	ldr	r2, [pc, #380]	@ (80063e4 <HAL_DMA_Abort+0x468>)
 8006266:	4293      	cmp	r3, r2
 8006268:	d01d      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 800626a:	687b      	ldr	r3, [r7, #4]
 800626c:	681b      	ldr	r3, [r3, #0]
 800626e:	4a5e      	ldr	r2, [pc, #376]	@ (80063e8 <HAL_DMA_Abort+0x46c>)
 8006270:	4293      	cmp	r3, r2
 8006272:	d018      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 8006274:	687b      	ldr	r3, [r7, #4]
 8006276:	681b      	ldr	r3, [r3, #0]
 8006278:	4a5c      	ldr	r2, [pc, #368]	@ (80063ec <HAL_DMA_Abort+0x470>)
 800627a:	4293      	cmp	r3, r2
 800627c:	d013      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 800627e:	687b      	ldr	r3, [r7, #4]
 8006280:	681b      	ldr	r3, [r3, #0]
 8006282:	4a5b      	ldr	r2, [pc, #364]	@ (80063f0 <HAL_DMA_Abort+0x474>)
 8006284:	4293      	cmp	r3, r2
 8006286:	d00e      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 8006288:	687b      	ldr	r3, [r7, #4]
 800628a:	681b      	ldr	r3, [r3, #0]
 800628c:	4a59      	ldr	r2, [pc, #356]	@ (80063f4 <HAL_DMA_Abort+0x478>)
 800628e:	4293      	cmp	r3, r2
 8006290:	d009      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 8006292:	687b      	ldr	r3, [r7, #4]
 8006294:	681b      	ldr	r3, [r3, #0]
 8006296:	4a58      	ldr	r2, [pc, #352]	@ (80063f8 <HAL_DMA_Abort+0x47c>)
 8006298:	4293      	cmp	r3, r2
 800629a:	d004      	beq.n	80062a6 <HAL_DMA_Abort+0x32a>
 800629c:	687b      	ldr	r3, [r7, #4]
 800629e:	681b      	ldr	r3, [r3, #0]
 80062a0:	4a56      	ldr	r2, [pc, #344]	@ (80063fc <HAL_DMA_Abort+0x480>)
 80062a2:	4293      	cmp	r3, r2
 80062a4:	d108      	bne.n	80062b8 <HAL_DMA_Abort+0x33c>
 80062a6:	687b      	ldr	r3, [r7, #4]
 80062a8:	681b      	ldr	r3, [r3, #0]
 80062aa:	681a      	ldr	r2, [r3, #0]
 80062ac:	687b      	ldr	r3, [r7, #4]
 80062ae:	681b      	ldr	r3, [r3, #0]
 80062b0:	f022 0201 	bic.w	r2, r2, #1
 80062b4:	601a      	str	r2, [r3, #0]
 80062b6:	e007      	b.n	80062c8 <HAL_DMA_Abort+0x34c>
 80062b8:	687b      	ldr	r3, [r7, #4]
 80062ba:	681b      	ldr	r3, [r3, #0]
 80062bc:	681a      	ldr	r2, [r3, #0]
 80062be:	687b      	ldr	r3, [r7, #4]
 80062c0:	681b      	ldr	r3, [r3, #0]
 80062c2:	f022 0201 	bic.w	r2, r2, #1
 80062c6:	601a      	str	r2, [r3, #0]

    /* Check if the DMA Stream is effectively disabled */
    while(((*enableRegister) & DMA_SxCR_EN) != 0U)
 80062c8:	e013      	b.n	80062f2 <HAL_DMA_Abort+0x376>
    {
      /* Check for the Timeout */
      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
 80062ca:	f7fd f8fb 	bl	80034c4 <HAL_GetTick>
 80062ce:	4602      	mov	r2, r0
 80062d0:	693b      	ldr	r3, [r7, #16]
 80062d2:	1ad3      	subs	r3, r2, r3
 80062d4:	2b05      	cmp	r3, #5
 80062d6:	d90c      	bls.n	80062f2 <HAL_DMA_Abort+0x376>
      {
        /* Update error code */
        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
 80062d8:	687b      	ldr	r3, [r7, #4]
 80062da:	2220      	movs	r2, #32
 80062dc:	655a      	str	r2, [r3, #84]	@ 0x54

        /* Change the DMA state */
        hdma->State = HAL_DMA_STATE_ERROR;
 80062de:	687b      	ldr	r3, [r7, #4]
 80062e0:	2203      	movs	r2, #3
 80062e2:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

        /* Process Unlocked */
        __HAL_UNLOCK(hdma);
 80062e6:	687b      	ldr	r3, [r7, #4]
 80062e8:	2200      	movs	r2, #0
 80062ea:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

        return HAL_ERROR;
 80062ee:	2301      	movs	r3, #1
 80062f0:	e12d      	b.n	800654e <HAL_DMA_Abort+0x5d2>
    while(((*enableRegister) & DMA_SxCR_EN) != 0U)
 80062f2:	697b      	ldr	r3, [r7, #20]
 80062f4:	681b      	ldr	r3, [r3, #0]
 80062f6:	f003 0301 	and.w	r3, r3, #1
 80062fa:	2b00      	cmp	r3, #0
 80062fc:	d1e5      	bne.n	80062ca <HAL_DMA_Abort+0x34e>
      }
    }

    /* Clear all interrupt flags at correct offset within the register */
    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 80062fe:	687b      	ldr	r3, [r7, #4]
 8006300:	681b      	ldr	r3, [r3, #0]
 8006302:	4a2f      	ldr	r2, [pc, #188]	@ (80063c0 <HAL_DMA_Abort+0x444>)
 8006304:	4293      	cmp	r3, r2
 8006306:	d04a      	beq.n	800639e <HAL_DMA_Abort+0x422>
 8006308:	687b      	ldr	r3, [r7, #4]
 800630a:	681b      	ldr	r3, [r3, #0]
 800630c:	4a2d      	ldr	r2, [pc, #180]	@ (80063c4 <HAL_DMA_Abort+0x448>)
 800630e:	4293      	cmp	r3, r2
 8006310:	d045      	beq.n	800639e <HAL_DMA_Abort+0x422>
 8006312:	687b      	ldr	r3, [r7, #4]
 8006314:	681b      	ldr	r3, [r3, #0]
 8006316:	4a2c      	ldr	r2, [pc, #176]	@ (80063c8 <HAL_DMA_Abort+0x44c>)
 8006318:	4293      	cmp	r3, r2
 800631a:	d040      	beq.n	800639e <HAL_DMA_Abort+0x422>
 800631c:	687b      	ldr	r3, [r7, #4]
 800631e:	681b      	ldr	r3, [r3, #0]
 8006320:	4a2a      	ldr	r2, [pc, #168]	@ (80063cc <HAL_DMA_Abort+0x450>)
 8006322:	4293      	cmp	r3, r2
 8006324:	d03b      	beq.n	800639e <HAL_DMA_Abort+0x422>
 8006326:	687b      	ldr	r3, [r7, #4]
 8006328:	681b      	ldr	r3, [r3, #0]
 800632a:	4a29      	ldr	r2, [pc, #164]	@ (80063d0 <HAL_DMA_Abort+0x454>)
 800632c:	4293      	cmp	r3, r2
 800632e:	d036      	beq.n	800639e <HAL_DMA_Abort+0x422>
 8006330:	687b      	ldr	r3, [r7, #4]
 8006332:	681b      	ldr	r3, [r3, #0]
 8006334:	4a27      	ldr	r2, [pc, #156]	@ (80063d4 <HAL_DMA_Abort+0x458>)
 8006336:	4293      	cmp	r3, r2
 8006338:	d031      	beq.n	800639e <HAL_DMA_Abort+0x422>
 800633a:	687b      	ldr	r3, [r7, #4]
 800633c:	681b      	ldr	r3, [r3, #0]
 800633e:	4a26      	ldr	r2, [pc, #152]	@ (80063d8 <HAL_DMA_Abort+0x45c>)
 8006340:	4293      	cmp	r3, r2
 8006342:	d02c      	beq.n	800639e <HAL_DMA_Abort+0x422>
 8006344:	687b      	ldr	r3, [r7, #4]
 8006346:	681b      	ldr	r3, [r3, #0]
 8006348:	4a24      	ldr	r2, [pc, #144]	@ (80063dc <HAL_DMA_Abort+0x460>)
 800634a:	4293      	cmp	r3, r2
 800634c:	d027      	beq.n	800639e <HAL_DMA_Abort+0x422>
 800634e:	687b      	ldr	r3, [r7, #4]
 8006350:	681b      	ldr	r3, [r3, #0]
 8006352:	4a23      	ldr	r2, [pc, #140]	@ (80063e0 <HAL_DMA_Abort+0x464>)
 8006354:	4293      	cmp	r3, r2
 8006356:	d022      	beq.n	800639e <HAL_DMA_Abort+0x422>
 8006358:	687b      	ldr	r3, [r7, #4]
 800635a:	681b      	ldr	r3, [r3, #0]
 800635c:	4a21      	ldr	r2, [pc, #132]	@ (80063e4 <HAL_DMA_Abort+0x468>)
 800635e:	4293      	cmp	r3, r2
 8006360:	d01d      	beq.n	800639e <HAL_DMA_Abort+0x422>
 8006362:	687b      	ldr	r3, [r7, #4]
 8006364:	681b      	ldr	r3, [r3, #0]
 8006366:	4a20      	ldr	r2, [pc, #128]	@ (80063e8 <HAL_DMA_Abort+0x46c>)
 8006368:	4293      	cmp	r3, r2
 800636a:	d018      	beq.n	800639e <HAL_DMA_Abort+0x422>
 800636c:	687b      	ldr	r3, [r7, #4]
 800636e:	681b      	ldr	r3, [r3, #0]
 8006370:	4a1e      	ldr	r2, [pc, #120]	@ (80063ec <HAL_DMA_Abort+0x470>)
 8006372:	4293      	cmp	r3, r2
 8006374:	d013      	beq.n	800639e <HAL_DMA_Abort+0x422>
 8006376:	687b      	ldr	r3, [r7, #4]
 8006378:	681b      	ldr	r3, [r3, #0]
 800637a:	4a1d      	ldr	r2, [pc, #116]	@ (80063f0 <HAL_DMA_Abort+0x474>)
 800637c:	4293      	cmp	r3, r2
 800637e:	d00e      	beq.n	800639e <HAL_DMA_Abort+0x422>
 8006380:	687b      	ldr	r3, [r7, #4]
 8006382:	681b      	ldr	r3, [r3, #0]
 8006384:	4a1b      	ldr	r2, [pc, #108]	@ (80063f4 <HAL_DMA_Abort+0x478>)
 8006386:	4293      	cmp	r3, r2
 8006388:	d009      	beq.n	800639e <HAL_DMA_Abort+0x422>
 800638a:	687b      	ldr	r3, [r7, #4]
 800638c:	681b      	ldr	r3, [r3, #0]
 800638e:	4a1a      	ldr	r2, [pc, #104]	@ (80063f8 <HAL_DMA_Abort+0x47c>)
 8006390:	4293      	cmp	r3, r2
 8006392:	d004      	beq.n	800639e <HAL_DMA_Abort+0x422>
 8006394:	687b      	ldr	r3, [r7, #4]
 8006396:	681b      	ldr	r3, [r3, #0]
 8006398:	4a18      	ldr	r2, [pc, #96]	@ (80063fc <HAL_DMA_Abort+0x480>)
 800639a:	4293      	cmp	r3, r2
 800639c:	d101      	bne.n	80063a2 <HAL_DMA_Abort+0x426>
 800639e:	2301      	movs	r3, #1
 80063a0:	e000      	b.n	80063a4 <HAL_DMA_Abort+0x428>
 80063a2:	2300      	movs	r3, #0
 80063a4:	2b00      	cmp	r3, #0
 80063a6:	d02b      	beq.n	8006400 <HAL_DMA_Abort+0x484>
    {
      regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
 80063a8:	687b      	ldr	r3, [r7, #4]
 80063aa:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80063ac:	60bb      	str	r3, [r7, #8]
      regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
 80063ae:	687b      	ldr	r3, [r7, #4]
 80063b0:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80063b2:	f003 031f 	and.w	r3, r3, #31
 80063b6:	223f      	movs	r2, #63	@ 0x3f
 80063b8:	409a      	lsls	r2, r3
 80063ba:	68bb      	ldr	r3, [r7, #8]
 80063bc:	609a      	str	r2, [r3, #8]
 80063be:	e02a      	b.n	8006416 <HAL_DMA_Abort+0x49a>
 80063c0:	40020010 	.word	0x40020010
 80063c4:	40020028 	.word	0x40020028
 80063c8:	40020040 	.word	0x40020040
 80063cc:	40020058 	.word	0x40020058
 80063d0:	40020070 	.word	0x40020070
 80063d4:	40020088 	.word	0x40020088
 80063d8:	400200a0 	.word	0x400200a0
 80063dc:	400200b8 	.word	0x400200b8
 80063e0:	40020410 	.word	0x40020410
 80063e4:	40020428 	.word	0x40020428
 80063e8:	40020440 	.word	0x40020440
 80063ec:	40020458 	.word	0x40020458
 80063f0:	40020470 	.word	0x40020470
 80063f4:	40020488 	.word	0x40020488
 80063f8:	400204a0 	.word	0x400204a0
 80063fc:	400204b8 	.word	0x400204b8
    }
    else /* BDMA channel */
    {
      regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
 8006400:	687b      	ldr	r3, [r7, #4]
 8006402:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8006404:	60fb      	str	r3, [r7, #12]
      regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
 8006406:	687b      	ldr	r3, [r7, #4]
 8006408:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800640a:	f003 031f 	and.w	r3, r3, #31
 800640e:	2201      	movs	r2, #1
 8006410:	409a      	lsls	r2, r3
 8006412:	68fb      	ldr	r3, [r7, #12]
 8006414:	605a      	str	r2, [r3, #4]
    }

    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
 8006416:	687b      	ldr	r3, [r7, #4]
 8006418:	681b      	ldr	r3, [r3, #0]
 800641a:	4a4f      	ldr	r2, [pc, #316]	@ (8006558 <HAL_DMA_Abort+0x5dc>)
 800641c:	4293      	cmp	r3, r2
 800641e:	d072      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 8006420:	687b      	ldr	r3, [r7, #4]
 8006422:	681b      	ldr	r3, [r3, #0]
 8006424:	4a4d      	ldr	r2, [pc, #308]	@ (800655c <HAL_DMA_Abort+0x5e0>)
 8006426:	4293      	cmp	r3, r2
 8006428:	d06d      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 800642a:	687b      	ldr	r3, [r7, #4]
 800642c:	681b      	ldr	r3, [r3, #0]
 800642e:	4a4c      	ldr	r2, [pc, #304]	@ (8006560 <HAL_DMA_Abort+0x5e4>)
 8006430:	4293      	cmp	r3, r2
 8006432:	d068      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 8006434:	687b      	ldr	r3, [r7, #4]
 8006436:	681b      	ldr	r3, [r3, #0]
 8006438:	4a4a      	ldr	r2, [pc, #296]	@ (8006564 <HAL_DMA_Abort+0x5e8>)
 800643a:	4293      	cmp	r3, r2
 800643c:	d063      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 800643e:	687b      	ldr	r3, [r7, #4]
 8006440:	681b      	ldr	r3, [r3, #0]
 8006442:	4a49      	ldr	r2, [pc, #292]	@ (8006568 <HAL_DMA_Abort+0x5ec>)
 8006444:	4293      	cmp	r3, r2
 8006446:	d05e      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 8006448:	687b      	ldr	r3, [r7, #4]
 800644a:	681b      	ldr	r3, [r3, #0]
 800644c:	4a47      	ldr	r2, [pc, #284]	@ (800656c <HAL_DMA_Abort+0x5f0>)
 800644e:	4293      	cmp	r3, r2
 8006450:	d059      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 8006452:	687b      	ldr	r3, [r7, #4]
 8006454:	681b      	ldr	r3, [r3, #0]
 8006456:	4a46      	ldr	r2, [pc, #280]	@ (8006570 <HAL_DMA_Abort+0x5f4>)
 8006458:	4293      	cmp	r3, r2
 800645a:	d054      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 800645c:	687b      	ldr	r3, [r7, #4]
 800645e:	681b      	ldr	r3, [r3, #0]
 8006460:	4a44      	ldr	r2, [pc, #272]	@ (8006574 <HAL_DMA_Abort+0x5f8>)
 8006462:	4293      	cmp	r3, r2
 8006464:	d04f      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 8006466:	687b      	ldr	r3, [r7, #4]
 8006468:	681b      	ldr	r3, [r3, #0]
 800646a:	4a43      	ldr	r2, [pc, #268]	@ (8006578 <HAL_DMA_Abort+0x5fc>)
 800646c:	4293      	cmp	r3, r2
 800646e:	d04a      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 8006470:	687b      	ldr	r3, [r7, #4]
 8006472:	681b      	ldr	r3, [r3, #0]
 8006474:	4a41      	ldr	r2, [pc, #260]	@ (800657c <HAL_DMA_Abort+0x600>)
 8006476:	4293      	cmp	r3, r2
 8006478:	d045      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 800647a:	687b      	ldr	r3, [r7, #4]
 800647c:	681b      	ldr	r3, [r3, #0]
 800647e:	4a40      	ldr	r2, [pc, #256]	@ (8006580 <HAL_DMA_Abort+0x604>)
 8006480:	4293      	cmp	r3, r2
 8006482:	d040      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 8006484:	687b      	ldr	r3, [r7, #4]
 8006486:	681b      	ldr	r3, [r3, #0]
 8006488:	4a3e      	ldr	r2, [pc, #248]	@ (8006584 <HAL_DMA_Abort+0x608>)
 800648a:	4293      	cmp	r3, r2
 800648c:	d03b      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 800648e:	687b      	ldr	r3, [r7, #4]
 8006490:	681b      	ldr	r3, [r3, #0]
 8006492:	4a3d      	ldr	r2, [pc, #244]	@ (8006588 <HAL_DMA_Abort+0x60c>)
 8006494:	4293      	cmp	r3, r2
 8006496:	d036      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 8006498:	687b      	ldr	r3, [r7, #4]
 800649a:	681b      	ldr	r3, [r3, #0]
 800649c:	4a3b      	ldr	r2, [pc, #236]	@ (800658c <HAL_DMA_Abort+0x610>)
 800649e:	4293      	cmp	r3, r2
 80064a0:	d031      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 80064a2:	687b      	ldr	r3, [r7, #4]
 80064a4:	681b      	ldr	r3, [r3, #0]
 80064a6:	4a3a      	ldr	r2, [pc, #232]	@ (8006590 <HAL_DMA_Abort+0x614>)
 80064a8:	4293      	cmp	r3, r2
 80064aa:	d02c      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 80064ac:	687b      	ldr	r3, [r7, #4]
 80064ae:	681b      	ldr	r3, [r3, #0]
 80064b0:	4a38      	ldr	r2, [pc, #224]	@ (8006594 <HAL_DMA_Abort+0x618>)
 80064b2:	4293      	cmp	r3, r2
 80064b4:	d027      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 80064b6:	687b      	ldr	r3, [r7, #4]
 80064b8:	681b      	ldr	r3, [r3, #0]
 80064ba:	4a37      	ldr	r2, [pc, #220]	@ (8006598 <HAL_DMA_Abort+0x61c>)
 80064bc:	4293      	cmp	r3, r2
 80064be:	d022      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 80064c0:	687b      	ldr	r3, [r7, #4]
 80064c2:	681b      	ldr	r3, [r3, #0]
 80064c4:	4a35      	ldr	r2, [pc, #212]	@ (800659c <HAL_DMA_Abort+0x620>)
 80064c6:	4293      	cmp	r3, r2
 80064c8:	d01d      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 80064ca:	687b      	ldr	r3, [r7, #4]
 80064cc:	681b      	ldr	r3, [r3, #0]
 80064ce:	4a34      	ldr	r2, [pc, #208]	@ (80065a0 <HAL_DMA_Abort+0x624>)
 80064d0:	4293      	cmp	r3, r2
 80064d2:	d018      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 80064d4:	687b      	ldr	r3, [r7, #4]
 80064d6:	681b      	ldr	r3, [r3, #0]
 80064d8:	4a32      	ldr	r2, [pc, #200]	@ (80065a4 <HAL_DMA_Abort+0x628>)
 80064da:	4293      	cmp	r3, r2
 80064dc:	d013      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 80064de:	687b      	ldr	r3, [r7, #4]
 80064e0:	681b      	ldr	r3, [r3, #0]
 80064e2:	4a31      	ldr	r2, [pc, #196]	@ (80065a8 <HAL_DMA_Abort+0x62c>)
 80064e4:	4293      	cmp	r3, r2
 80064e6:	d00e      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 80064e8:	687b      	ldr	r3, [r7, #4]
 80064ea:	681b      	ldr	r3, [r3, #0]
 80064ec:	4a2f      	ldr	r2, [pc, #188]	@ (80065ac <HAL_DMA_Abort+0x630>)
 80064ee:	4293      	cmp	r3, r2
 80064f0:	d009      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 80064f2:	687b      	ldr	r3, [r7, #4]
 80064f4:	681b      	ldr	r3, [r3, #0]
 80064f6:	4a2e      	ldr	r2, [pc, #184]	@ (80065b0 <HAL_DMA_Abort+0x634>)
 80064f8:	4293      	cmp	r3, r2
 80064fa:	d004      	beq.n	8006506 <HAL_DMA_Abort+0x58a>
 80064fc:	687b      	ldr	r3, [r7, #4]
 80064fe:	681b      	ldr	r3, [r3, #0]
 8006500:	4a2c      	ldr	r2, [pc, #176]	@ (80065b4 <HAL_DMA_Abort+0x638>)
 8006502:	4293      	cmp	r3, r2
 8006504:	d101      	bne.n	800650a <HAL_DMA_Abort+0x58e>
 8006506:	2301      	movs	r3, #1
 8006508:	e000      	b.n	800650c <HAL_DMA_Abort+0x590>
 800650a:	2300      	movs	r3, #0
 800650c:	2b00      	cmp	r3, #0
 800650e:	d015      	beq.n	800653c <HAL_DMA_Abort+0x5c0>
    {
      /* Clear the DMAMUX synchro overrun flag */
      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 8006510:	687b      	ldr	r3, [r7, #4]
 8006512:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8006514:	687a      	ldr	r2, [r7, #4]
 8006516:	6e92      	ldr	r2, [r2, #104]	@ 0x68
 8006518:	605a      	str	r2, [r3, #4]

      if(hdma->DMAmuxRequestGen != 0U)
 800651a:	687b      	ldr	r3, [r7, #4]
 800651c:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800651e:	2b00      	cmp	r3, #0
 8006520:	d00c      	beq.n	800653c <HAL_DMA_Abort+0x5c0>
      {
        /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */
        /* disable the request gen overrun IT */
        hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
 8006522:	687b      	ldr	r3, [r7, #4]
 8006524:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8006526:	681a      	ldr	r2, [r3, #0]
 8006528:	687b      	ldr	r3, [r7, #4]
 800652a:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800652c:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
 8006530:	601a      	str	r2, [r3, #0]

        /* Clear the DMAMUX request generator overrun flag */
        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 8006532:	687b      	ldr	r3, [r7, #4]
 8006534:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8006536:	687a      	ldr	r2, [r7, #4]
 8006538:	6f52      	ldr	r2, [r2, #116]	@ 0x74
 800653a:	605a      	str	r2, [r3, #4]
      }
    }

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;
 800653c:	687b      	ldr	r3, [r7, #4]
 800653e:	2201      	movs	r2, #1
 8006540:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8006544:	687b      	ldr	r3, [r7, #4]
 8006546:	2200      	movs	r2, #0
 8006548:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
  }

  return HAL_OK;
 800654c:	2300      	movs	r3, #0
}
 800654e:	4618      	mov	r0, r3
 8006550:	3718      	adds	r7, #24
 8006552:	46bd      	mov	sp, r7
 8006554:	bd80      	pop	{r7, pc}
 8006556:	bf00      	nop
 8006558:	40020010 	.word	0x40020010
 800655c:	40020028 	.word	0x40020028
 8006560:	40020040 	.word	0x40020040
 8006564:	40020058 	.word	0x40020058
 8006568:	40020070 	.word	0x40020070
 800656c:	40020088 	.word	0x40020088
 8006570:	400200a0 	.word	0x400200a0
 8006574:	400200b8 	.word	0x400200b8
 8006578:	40020410 	.word	0x40020410
 800657c:	40020428 	.word	0x40020428
 8006580:	40020440 	.word	0x40020440
 8006584:	40020458 	.word	0x40020458
 8006588:	40020470 	.word	0x40020470
 800658c:	40020488 	.word	0x40020488
 8006590:	400204a0 	.word	0x400204a0
 8006594:	400204b8 	.word	0x400204b8
 8006598:	58025408 	.word	0x58025408
 800659c:	5802541c 	.word	0x5802541c
 80065a0:	58025430 	.word	0x58025430
 80065a4:	58025444 	.word	0x58025444
 80065a8:	58025458 	.word	0x58025458
 80065ac:	5802546c 	.word	0x5802546c
 80065b0:	58025480 	.word	0x58025480
 80065b4:	58025494 	.word	0x58025494

080065b8 <HAL_DMA_Abort_IT>:
  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
  *                 the configuration information for the specified DMA Stream.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
 80065b8:	b580      	push	{r7, lr}
 80065ba:	b084      	sub	sp, #16
 80065bc:	af00      	add	r7, sp, #0
 80065be:	6078      	str	r0, [r7, #4]
  BDMA_Base_Registers *regs_bdma;

  /* Check the DMA peripheral handle */
  if(hdma == NULL)
 80065c0:	687b      	ldr	r3, [r7, #4]
 80065c2:	2b00      	cmp	r3, #0
 80065c4:	d101      	bne.n	80065ca <HAL_DMA_Abort_IT+0x12>
  {
    return HAL_ERROR;
 80065c6:	2301      	movs	r3, #1
 80065c8:	e237      	b.n	8006a3a <HAL_DMA_Abort_IT+0x482>
  }

  if(hdma->State != HAL_DMA_STATE_BUSY)
 80065ca:	687b      	ldr	r3, [r7, #4]
 80065cc:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
 80065d0:	b2db      	uxtb	r3, r3
 80065d2:	2b02      	cmp	r3, #2
 80065d4:	d004      	beq.n	80065e0 <HAL_DMA_Abort_IT+0x28>
  {
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 80065d6:	687b      	ldr	r3, [r7, #4]
 80065d8:	2280      	movs	r2, #128	@ 0x80
 80065da:	655a      	str	r2, [r3, #84]	@ 0x54
    return HAL_ERROR;
 80065dc:	2301      	movs	r3, #1
 80065de:	e22c      	b.n	8006a3a <HAL_DMA_Abort_IT+0x482>
  }
  else
  {
    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 80065e0:	687b      	ldr	r3, [r7, #4]
 80065e2:	681b      	ldr	r3, [r3, #0]
 80065e4:	4a5c      	ldr	r2, [pc, #368]	@ (8006758 <HAL_DMA_Abort_IT+0x1a0>)
 80065e6:	4293      	cmp	r3, r2
 80065e8:	d04a      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 80065ea:	687b      	ldr	r3, [r7, #4]
 80065ec:	681b      	ldr	r3, [r3, #0]
 80065ee:	4a5b      	ldr	r2, [pc, #364]	@ (800675c <HAL_DMA_Abort_IT+0x1a4>)
 80065f0:	4293      	cmp	r3, r2
 80065f2:	d045      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 80065f4:	687b      	ldr	r3, [r7, #4]
 80065f6:	681b      	ldr	r3, [r3, #0]
 80065f8:	4a59      	ldr	r2, [pc, #356]	@ (8006760 <HAL_DMA_Abort_IT+0x1a8>)
 80065fa:	4293      	cmp	r3, r2
 80065fc:	d040      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 80065fe:	687b      	ldr	r3, [r7, #4]
 8006600:	681b      	ldr	r3, [r3, #0]
 8006602:	4a58      	ldr	r2, [pc, #352]	@ (8006764 <HAL_DMA_Abort_IT+0x1ac>)
 8006604:	4293      	cmp	r3, r2
 8006606:	d03b      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 8006608:	687b      	ldr	r3, [r7, #4]
 800660a:	681b      	ldr	r3, [r3, #0]
 800660c:	4a56      	ldr	r2, [pc, #344]	@ (8006768 <HAL_DMA_Abort_IT+0x1b0>)
 800660e:	4293      	cmp	r3, r2
 8006610:	d036      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 8006612:	687b      	ldr	r3, [r7, #4]
 8006614:	681b      	ldr	r3, [r3, #0]
 8006616:	4a55      	ldr	r2, [pc, #340]	@ (800676c <HAL_DMA_Abort_IT+0x1b4>)
 8006618:	4293      	cmp	r3, r2
 800661a:	d031      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 800661c:	687b      	ldr	r3, [r7, #4]
 800661e:	681b      	ldr	r3, [r3, #0]
 8006620:	4a53      	ldr	r2, [pc, #332]	@ (8006770 <HAL_DMA_Abort_IT+0x1b8>)
 8006622:	4293      	cmp	r3, r2
 8006624:	d02c      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 8006626:	687b      	ldr	r3, [r7, #4]
 8006628:	681b      	ldr	r3, [r3, #0]
 800662a:	4a52      	ldr	r2, [pc, #328]	@ (8006774 <HAL_DMA_Abort_IT+0x1bc>)
 800662c:	4293      	cmp	r3, r2
 800662e:	d027      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 8006630:	687b      	ldr	r3, [r7, #4]
 8006632:	681b      	ldr	r3, [r3, #0]
 8006634:	4a50      	ldr	r2, [pc, #320]	@ (8006778 <HAL_DMA_Abort_IT+0x1c0>)
 8006636:	4293      	cmp	r3, r2
 8006638:	d022      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 800663a:	687b      	ldr	r3, [r7, #4]
 800663c:	681b      	ldr	r3, [r3, #0]
 800663e:	4a4f      	ldr	r2, [pc, #316]	@ (800677c <HAL_DMA_Abort_IT+0x1c4>)
 8006640:	4293      	cmp	r3, r2
 8006642:	d01d      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 8006644:	687b      	ldr	r3, [r7, #4]
 8006646:	681b      	ldr	r3, [r3, #0]
 8006648:	4a4d      	ldr	r2, [pc, #308]	@ (8006780 <HAL_DMA_Abort_IT+0x1c8>)
 800664a:	4293      	cmp	r3, r2
 800664c:	d018      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 800664e:	687b      	ldr	r3, [r7, #4]
 8006650:	681b      	ldr	r3, [r3, #0]
 8006652:	4a4c      	ldr	r2, [pc, #304]	@ (8006784 <HAL_DMA_Abort_IT+0x1cc>)
 8006654:	4293      	cmp	r3, r2
 8006656:	d013      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 8006658:	687b      	ldr	r3, [r7, #4]
 800665a:	681b      	ldr	r3, [r3, #0]
 800665c:	4a4a      	ldr	r2, [pc, #296]	@ (8006788 <HAL_DMA_Abort_IT+0x1d0>)
 800665e:	4293      	cmp	r3, r2
 8006660:	d00e      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 8006662:	687b      	ldr	r3, [r7, #4]
 8006664:	681b      	ldr	r3, [r3, #0]
 8006666:	4a49      	ldr	r2, [pc, #292]	@ (800678c <HAL_DMA_Abort_IT+0x1d4>)
 8006668:	4293      	cmp	r3, r2
 800666a:	d009      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 800666c:	687b      	ldr	r3, [r7, #4]
 800666e:	681b      	ldr	r3, [r3, #0]
 8006670:	4a47      	ldr	r2, [pc, #284]	@ (8006790 <HAL_DMA_Abort_IT+0x1d8>)
 8006672:	4293      	cmp	r3, r2
 8006674:	d004      	beq.n	8006680 <HAL_DMA_Abort_IT+0xc8>
 8006676:	687b      	ldr	r3, [r7, #4]
 8006678:	681b      	ldr	r3, [r3, #0]
 800667a:	4a46      	ldr	r2, [pc, #280]	@ (8006794 <HAL_DMA_Abort_IT+0x1dc>)
 800667c:	4293      	cmp	r3, r2
 800667e:	d101      	bne.n	8006684 <HAL_DMA_Abort_IT+0xcc>
 8006680:	2301      	movs	r3, #1
 8006682:	e000      	b.n	8006686 <HAL_DMA_Abort_IT+0xce>
 8006684:	2300      	movs	r3, #0
 8006686:	2b00      	cmp	r3, #0
 8006688:	f000 8086 	beq.w	8006798 <HAL_DMA_Abort_IT+0x1e0>
    {
      /* Set Abort State  */
      hdma->State = HAL_DMA_STATE_ABORT;
 800668c:	687b      	ldr	r3, [r7, #4]
 800668e:	2204      	movs	r2, #4
 8006690:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

      /* Disable the stream */
      __HAL_DMA_DISABLE(hdma);
 8006694:	687b      	ldr	r3, [r7, #4]
 8006696:	681b      	ldr	r3, [r3, #0]
 8006698:	4a2f      	ldr	r2, [pc, #188]	@ (8006758 <HAL_DMA_Abort_IT+0x1a0>)
 800669a:	4293      	cmp	r3, r2
 800669c:	d04a      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 800669e:	687b      	ldr	r3, [r7, #4]
 80066a0:	681b      	ldr	r3, [r3, #0]
 80066a2:	4a2e      	ldr	r2, [pc, #184]	@ (800675c <HAL_DMA_Abort_IT+0x1a4>)
 80066a4:	4293      	cmp	r3, r2
 80066a6:	d045      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 80066a8:	687b      	ldr	r3, [r7, #4]
 80066aa:	681b      	ldr	r3, [r3, #0]
 80066ac:	4a2c      	ldr	r2, [pc, #176]	@ (8006760 <HAL_DMA_Abort_IT+0x1a8>)
 80066ae:	4293      	cmp	r3, r2
 80066b0:	d040      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 80066b2:	687b      	ldr	r3, [r7, #4]
 80066b4:	681b      	ldr	r3, [r3, #0]
 80066b6:	4a2b      	ldr	r2, [pc, #172]	@ (8006764 <HAL_DMA_Abort_IT+0x1ac>)
 80066b8:	4293      	cmp	r3, r2
 80066ba:	d03b      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 80066bc:	687b      	ldr	r3, [r7, #4]
 80066be:	681b      	ldr	r3, [r3, #0]
 80066c0:	4a29      	ldr	r2, [pc, #164]	@ (8006768 <HAL_DMA_Abort_IT+0x1b0>)
 80066c2:	4293      	cmp	r3, r2
 80066c4:	d036      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 80066c6:	687b      	ldr	r3, [r7, #4]
 80066c8:	681b      	ldr	r3, [r3, #0]
 80066ca:	4a28      	ldr	r2, [pc, #160]	@ (800676c <HAL_DMA_Abort_IT+0x1b4>)
 80066cc:	4293      	cmp	r3, r2
 80066ce:	d031      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 80066d0:	687b      	ldr	r3, [r7, #4]
 80066d2:	681b      	ldr	r3, [r3, #0]
 80066d4:	4a26      	ldr	r2, [pc, #152]	@ (8006770 <HAL_DMA_Abort_IT+0x1b8>)
 80066d6:	4293      	cmp	r3, r2
 80066d8:	d02c      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 80066da:	687b      	ldr	r3, [r7, #4]
 80066dc:	681b      	ldr	r3, [r3, #0]
 80066de:	4a25      	ldr	r2, [pc, #148]	@ (8006774 <HAL_DMA_Abort_IT+0x1bc>)
 80066e0:	4293      	cmp	r3, r2
 80066e2:	d027      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 80066e4:	687b      	ldr	r3, [r7, #4]
 80066e6:	681b      	ldr	r3, [r3, #0]
 80066e8:	4a23      	ldr	r2, [pc, #140]	@ (8006778 <HAL_DMA_Abort_IT+0x1c0>)
 80066ea:	4293      	cmp	r3, r2
 80066ec:	d022      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 80066ee:	687b      	ldr	r3, [r7, #4]
 80066f0:	681b      	ldr	r3, [r3, #0]
 80066f2:	4a22      	ldr	r2, [pc, #136]	@ (800677c <HAL_DMA_Abort_IT+0x1c4>)
 80066f4:	4293      	cmp	r3, r2
 80066f6:	d01d      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 80066f8:	687b      	ldr	r3, [r7, #4]
 80066fa:	681b      	ldr	r3, [r3, #0]
 80066fc:	4a20      	ldr	r2, [pc, #128]	@ (8006780 <HAL_DMA_Abort_IT+0x1c8>)
 80066fe:	4293      	cmp	r3, r2
 8006700:	d018      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 8006702:	687b      	ldr	r3, [r7, #4]
 8006704:	681b      	ldr	r3, [r3, #0]
 8006706:	4a1f      	ldr	r2, [pc, #124]	@ (8006784 <HAL_DMA_Abort_IT+0x1cc>)
 8006708:	4293      	cmp	r3, r2
 800670a:	d013      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 800670c:	687b      	ldr	r3, [r7, #4]
 800670e:	681b      	ldr	r3, [r3, #0]
 8006710:	4a1d      	ldr	r2, [pc, #116]	@ (8006788 <HAL_DMA_Abort_IT+0x1d0>)
 8006712:	4293      	cmp	r3, r2
 8006714:	d00e      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 8006716:	687b      	ldr	r3, [r7, #4]
 8006718:	681b      	ldr	r3, [r3, #0]
 800671a:	4a1c      	ldr	r2, [pc, #112]	@ (800678c <HAL_DMA_Abort_IT+0x1d4>)
 800671c:	4293      	cmp	r3, r2
 800671e:	d009      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 8006720:	687b      	ldr	r3, [r7, #4]
 8006722:	681b      	ldr	r3, [r3, #0]
 8006724:	4a1a      	ldr	r2, [pc, #104]	@ (8006790 <HAL_DMA_Abort_IT+0x1d8>)
 8006726:	4293      	cmp	r3, r2
 8006728:	d004      	beq.n	8006734 <HAL_DMA_Abort_IT+0x17c>
 800672a:	687b      	ldr	r3, [r7, #4]
 800672c:	681b      	ldr	r3, [r3, #0]
 800672e:	4a19      	ldr	r2, [pc, #100]	@ (8006794 <HAL_DMA_Abort_IT+0x1dc>)
 8006730:	4293      	cmp	r3, r2
 8006732:	d108      	bne.n	8006746 <HAL_DMA_Abort_IT+0x18e>
 8006734:	687b      	ldr	r3, [r7, #4]
 8006736:	681b      	ldr	r3, [r3, #0]
 8006738:	681a      	ldr	r2, [r3, #0]
 800673a:	687b      	ldr	r3, [r7, #4]
 800673c:	681b      	ldr	r3, [r3, #0]
 800673e:	f022 0201 	bic.w	r2, r2, #1
 8006742:	601a      	str	r2, [r3, #0]
 8006744:	e178      	b.n	8006a38 <HAL_DMA_Abort_IT+0x480>
 8006746:	687b      	ldr	r3, [r7, #4]
 8006748:	681b      	ldr	r3, [r3, #0]
 800674a:	681a      	ldr	r2, [r3, #0]
 800674c:	687b      	ldr	r3, [r7, #4]
 800674e:	681b      	ldr	r3, [r3, #0]
 8006750:	f022 0201 	bic.w	r2, r2, #1
 8006754:	601a      	str	r2, [r3, #0]
 8006756:	e16f      	b.n	8006a38 <HAL_DMA_Abort_IT+0x480>
 8006758:	40020010 	.word	0x40020010
 800675c:	40020028 	.word	0x40020028
 8006760:	40020040 	.word	0x40020040
 8006764:	40020058 	.word	0x40020058
 8006768:	40020070 	.word	0x40020070
 800676c:	40020088 	.word	0x40020088
 8006770:	400200a0 	.word	0x400200a0
 8006774:	400200b8 	.word	0x400200b8
 8006778:	40020410 	.word	0x40020410
 800677c:	40020428 	.word	0x40020428
 8006780:	40020440 	.word	0x40020440
 8006784:	40020458 	.word	0x40020458
 8006788:	40020470 	.word	0x40020470
 800678c:	40020488 	.word	0x40020488
 8006790:	400204a0 	.word	0x400204a0
 8006794:	400204b8 	.word	0x400204b8
    }
    else /* BDMA channel */
    {
      /* Disable DMA All Interrupts  */
      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
 8006798:	687b      	ldr	r3, [r7, #4]
 800679a:	681b      	ldr	r3, [r3, #0]
 800679c:	681a      	ldr	r2, [r3, #0]
 800679e:	687b      	ldr	r3, [r7, #4]
 80067a0:	681b      	ldr	r3, [r3, #0]
 80067a2:	f022 020e 	bic.w	r2, r2, #14
 80067a6:	601a      	str	r2, [r3, #0]

      /* Disable the channel */
      __HAL_DMA_DISABLE(hdma);
 80067a8:	687b      	ldr	r3, [r7, #4]
 80067aa:	681b      	ldr	r3, [r3, #0]
 80067ac:	4a6c      	ldr	r2, [pc, #432]	@ (8006960 <HAL_DMA_Abort_IT+0x3a8>)
 80067ae:	4293      	cmp	r3, r2
 80067b0:	d04a      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 80067b2:	687b      	ldr	r3, [r7, #4]
 80067b4:	681b      	ldr	r3, [r3, #0]
 80067b6:	4a6b      	ldr	r2, [pc, #428]	@ (8006964 <HAL_DMA_Abort_IT+0x3ac>)
 80067b8:	4293      	cmp	r3, r2
 80067ba:	d045      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 80067bc:	687b      	ldr	r3, [r7, #4]
 80067be:	681b      	ldr	r3, [r3, #0]
 80067c0:	4a69      	ldr	r2, [pc, #420]	@ (8006968 <HAL_DMA_Abort_IT+0x3b0>)
 80067c2:	4293      	cmp	r3, r2
 80067c4:	d040      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 80067c6:	687b      	ldr	r3, [r7, #4]
 80067c8:	681b      	ldr	r3, [r3, #0]
 80067ca:	4a68      	ldr	r2, [pc, #416]	@ (800696c <HAL_DMA_Abort_IT+0x3b4>)
 80067cc:	4293      	cmp	r3, r2
 80067ce:	d03b      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 80067d0:	687b      	ldr	r3, [r7, #4]
 80067d2:	681b      	ldr	r3, [r3, #0]
 80067d4:	4a66      	ldr	r2, [pc, #408]	@ (8006970 <HAL_DMA_Abort_IT+0x3b8>)
 80067d6:	4293      	cmp	r3, r2
 80067d8:	d036      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 80067da:	687b      	ldr	r3, [r7, #4]
 80067dc:	681b      	ldr	r3, [r3, #0]
 80067de:	4a65      	ldr	r2, [pc, #404]	@ (8006974 <HAL_DMA_Abort_IT+0x3bc>)
 80067e0:	4293      	cmp	r3, r2
 80067e2:	d031      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 80067e4:	687b      	ldr	r3, [r7, #4]
 80067e6:	681b      	ldr	r3, [r3, #0]
 80067e8:	4a63      	ldr	r2, [pc, #396]	@ (8006978 <HAL_DMA_Abort_IT+0x3c0>)
 80067ea:	4293      	cmp	r3, r2
 80067ec:	d02c      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 80067ee:	687b      	ldr	r3, [r7, #4]
 80067f0:	681b      	ldr	r3, [r3, #0]
 80067f2:	4a62      	ldr	r2, [pc, #392]	@ (800697c <HAL_DMA_Abort_IT+0x3c4>)
 80067f4:	4293      	cmp	r3, r2
 80067f6:	d027      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 80067f8:	687b      	ldr	r3, [r7, #4]
 80067fa:	681b      	ldr	r3, [r3, #0]
 80067fc:	4a60      	ldr	r2, [pc, #384]	@ (8006980 <HAL_DMA_Abort_IT+0x3c8>)
 80067fe:	4293      	cmp	r3, r2
 8006800:	d022      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 8006802:	687b      	ldr	r3, [r7, #4]
 8006804:	681b      	ldr	r3, [r3, #0]
 8006806:	4a5f      	ldr	r2, [pc, #380]	@ (8006984 <HAL_DMA_Abort_IT+0x3cc>)
 8006808:	4293      	cmp	r3, r2
 800680a:	d01d      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 800680c:	687b      	ldr	r3, [r7, #4]
 800680e:	681b      	ldr	r3, [r3, #0]
 8006810:	4a5d      	ldr	r2, [pc, #372]	@ (8006988 <HAL_DMA_Abort_IT+0x3d0>)
 8006812:	4293      	cmp	r3, r2
 8006814:	d018      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 8006816:	687b      	ldr	r3, [r7, #4]
 8006818:	681b      	ldr	r3, [r3, #0]
 800681a:	4a5c      	ldr	r2, [pc, #368]	@ (800698c <HAL_DMA_Abort_IT+0x3d4>)
 800681c:	4293      	cmp	r3, r2
 800681e:	d013      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 8006820:	687b      	ldr	r3, [r7, #4]
 8006822:	681b      	ldr	r3, [r3, #0]
 8006824:	4a5a      	ldr	r2, [pc, #360]	@ (8006990 <HAL_DMA_Abort_IT+0x3d8>)
 8006826:	4293      	cmp	r3, r2
 8006828:	d00e      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 800682a:	687b      	ldr	r3, [r7, #4]
 800682c:	681b      	ldr	r3, [r3, #0]
 800682e:	4a59      	ldr	r2, [pc, #356]	@ (8006994 <HAL_DMA_Abort_IT+0x3dc>)
 8006830:	4293      	cmp	r3, r2
 8006832:	d009      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 8006834:	687b      	ldr	r3, [r7, #4]
 8006836:	681b      	ldr	r3, [r3, #0]
 8006838:	4a57      	ldr	r2, [pc, #348]	@ (8006998 <HAL_DMA_Abort_IT+0x3e0>)
 800683a:	4293      	cmp	r3, r2
 800683c:	d004      	beq.n	8006848 <HAL_DMA_Abort_IT+0x290>
 800683e:	687b      	ldr	r3, [r7, #4]
 8006840:	681b      	ldr	r3, [r3, #0]
 8006842:	4a56      	ldr	r2, [pc, #344]	@ (800699c <HAL_DMA_Abort_IT+0x3e4>)
 8006844:	4293      	cmp	r3, r2
 8006846:	d108      	bne.n	800685a <HAL_DMA_Abort_IT+0x2a2>
 8006848:	687b      	ldr	r3, [r7, #4]
 800684a:	681b      	ldr	r3, [r3, #0]
 800684c:	681a      	ldr	r2, [r3, #0]
 800684e:	687b      	ldr	r3, [r7, #4]
 8006850:	681b      	ldr	r3, [r3, #0]
 8006852:	f022 0201 	bic.w	r2, r2, #1
 8006856:	601a      	str	r2, [r3, #0]
 8006858:	e007      	b.n	800686a <HAL_DMA_Abort_IT+0x2b2>
 800685a:	687b      	ldr	r3, [r7, #4]
 800685c:	681b      	ldr	r3, [r3, #0]
 800685e:	681a      	ldr	r2, [r3, #0]
 8006860:	687b      	ldr	r3, [r7, #4]
 8006862:	681b      	ldr	r3, [r3, #0]
 8006864:	f022 0201 	bic.w	r2, r2, #1
 8006868:	601a      	str	r2, [r3, #0]

      if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
 800686a:	687b      	ldr	r3, [r7, #4]
 800686c:	681b      	ldr	r3, [r3, #0]
 800686e:	4a3c      	ldr	r2, [pc, #240]	@ (8006960 <HAL_DMA_Abort_IT+0x3a8>)
 8006870:	4293      	cmp	r3, r2
 8006872:	d072      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 8006874:	687b      	ldr	r3, [r7, #4]
 8006876:	681b      	ldr	r3, [r3, #0]
 8006878:	4a3a      	ldr	r2, [pc, #232]	@ (8006964 <HAL_DMA_Abort_IT+0x3ac>)
 800687a:	4293      	cmp	r3, r2
 800687c:	d06d      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 800687e:	687b      	ldr	r3, [r7, #4]
 8006880:	681b      	ldr	r3, [r3, #0]
 8006882:	4a39      	ldr	r2, [pc, #228]	@ (8006968 <HAL_DMA_Abort_IT+0x3b0>)
 8006884:	4293      	cmp	r3, r2
 8006886:	d068      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 8006888:	687b      	ldr	r3, [r7, #4]
 800688a:	681b      	ldr	r3, [r3, #0]
 800688c:	4a37      	ldr	r2, [pc, #220]	@ (800696c <HAL_DMA_Abort_IT+0x3b4>)
 800688e:	4293      	cmp	r3, r2
 8006890:	d063      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 8006892:	687b      	ldr	r3, [r7, #4]
 8006894:	681b      	ldr	r3, [r3, #0]
 8006896:	4a36      	ldr	r2, [pc, #216]	@ (8006970 <HAL_DMA_Abort_IT+0x3b8>)
 8006898:	4293      	cmp	r3, r2
 800689a:	d05e      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 800689c:	687b      	ldr	r3, [r7, #4]
 800689e:	681b      	ldr	r3, [r3, #0]
 80068a0:	4a34      	ldr	r2, [pc, #208]	@ (8006974 <HAL_DMA_Abort_IT+0x3bc>)
 80068a2:	4293      	cmp	r3, r2
 80068a4:	d059      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 80068a6:	687b      	ldr	r3, [r7, #4]
 80068a8:	681b      	ldr	r3, [r3, #0]
 80068aa:	4a33      	ldr	r2, [pc, #204]	@ (8006978 <HAL_DMA_Abort_IT+0x3c0>)
 80068ac:	4293      	cmp	r3, r2
 80068ae:	d054      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 80068b0:	687b      	ldr	r3, [r7, #4]
 80068b2:	681b      	ldr	r3, [r3, #0]
 80068b4:	4a31      	ldr	r2, [pc, #196]	@ (800697c <HAL_DMA_Abort_IT+0x3c4>)
 80068b6:	4293      	cmp	r3, r2
 80068b8:	d04f      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 80068ba:	687b      	ldr	r3, [r7, #4]
 80068bc:	681b      	ldr	r3, [r3, #0]
 80068be:	4a30      	ldr	r2, [pc, #192]	@ (8006980 <HAL_DMA_Abort_IT+0x3c8>)
 80068c0:	4293      	cmp	r3, r2
 80068c2:	d04a      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 80068c4:	687b      	ldr	r3, [r7, #4]
 80068c6:	681b      	ldr	r3, [r3, #0]
 80068c8:	4a2e      	ldr	r2, [pc, #184]	@ (8006984 <HAL_DMA_Abort_IT+0x3cc>)
 80068ca:	4293      	cmp	r3, r2
 80068cc:	d045      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 80068ce:	687b      	ldr	r3, [r7, #4]
 80068d0:	681b      	ldr	r3, [r3, #0]
 80068d2:	4a2d      	ldr	r2, [pc, #180]	@ (8006988 <HAL_DMA_Abort_IT+0x3d0>)
 80068d4:	4293      	cmp	r3, r2
 80068d6:	d040      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 80068d8:	687b      	ldr	r3, [r7, #4]
 80068da:	681b      	ldr	r3, [r3, #0]
 80068dc:	4a2b      	ldr	r2, [pc, #172]	@ (800698c <HAL_DMA_Abort_IT+0x3d4>)
 80068de:	4293      	cmp	r3, r2
 80068e0:	d03b      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 80068e2:	687b      	ldr	r3, [r7, #4]
 80068e4:	681b      	ldr	r3, [r3, #0]
 80068e6:	4a2a      	ldr	r2, [pc, #168]	@ (8006990 <HAL_DMA_Abort_IT+0x3d8>)
 80068e8:	4293      	cmp	r3, r2
 80068ea:	d036      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 80068ec:	687b      	ldr	r3, [r7, #4]
 80068ee:	681b      	ldr	r3, [r3, #0]
 80068f0:	4a28      	ldr	r2, [pc, #160]	@ (8006994 <HAL_DMA_Abort_IT+0x3dc>)
 80068f2:	4293      	cmp	r3, r2
 80068f4:	d031      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 80068f6:	687b      	ldr	r3, [r7, #4]
 80068f8:	681b      	ldr	r3, [r3, #0]
 80068fa:	4a27      	ldr	r2, [pc, #156]	@ (8006998 <HAL_DMA_Abort_IT+0x3e0>)
 80068fc:	4293      	cmp	r3, r2
 80068fe:	d02c      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 8006900:	687b      	ldr	r3, [r7, #4]
 8006902:	681b      	ldr	r3, [r3, #0]
 8006904:	4a25      	ldr	r2, [pc, #148]	@ (800699c <HAL_DMA_Abort_IT+0x3e4>)
 8006906:	4293      	cmp	r3, r2
 8006908:	d027      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 800690a:	687b      	ldr	r3, [r7, #4]
 800690c:	681b      	ldr	r3, [r3, #0]
 800690e:	4a24      	ldr	r2, [pc, #144]	@ (80069a0 <HAL_DMA_Abort_IT+0x3e8>)
 8006910:	4293      	cmp	r3, r2
 8006912:	d022      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 8006914:	687b      	ldr	r3, [r7, #4]
 8006916:	681b      	ldr	r3, [r3, #0]
 8006918:	4a22      	ldr	r2, [pc, #136]	@ (80069a4 <HAL_DMA_Abort_IT+0x3ec>)
 800691a:	4293      	cmp	r3, r2
 800691c:	d01d      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 800691e:	687b      	ldr	r3, [r7, #4]
 8006920:	681b      	ldr	r3, [r3, #0]
 8006922:	4a21      	ldr	r2, [pc, #132]	@ (80069a8 <HAL_DMA_Abort_IT+0x3f0>)
 8006924:	4293      	cmp	r3, r2
 8006926:	d018      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 8006928:	687b      	ldr	r3, [r7, #4]
 800692a:	681b      	ldr	r3, [r3, #0]
 800692c:	4a1f      	ldr	r2, [pc, #124]	@ (80069ac <HAL_DMA_Abort_IT+0x3f4>)
 800692e:	4293      	cmp	r3, r2
 8006930:	d013      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 8006932:	687b      	ldr	r3, [r7, #4]
 8006934:	681b      	ldr	r3, [r3, #0]
 8006936:	4a1e      	ldr	r2, [pc, #120]	@ (80069b0 <HAL_DMA_Abort_IT+0x3f8>)
 8006938:	4293      	cmp	r3, r2
 800693a:	d00e      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 800693c:	687b      	ldr	r3, [r7, #4]
 800693e:	681b      	ldr	r3, [r3, #0]
 8006940:	4a1c      	ldr	r2, [pc, #112]	@ (80069b4 <HAL_DMA_Abort_IT+0x3fc>)
 8006942:	4293      	cmp	r3, r2
 8006944:	d009      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 8006946:	687b      	ldr	r3, [r7, #4]
 8006948:	681b      	ldr	r3, [r3, #0]
 800694a:	4a1b      	ldr	r2, [pc, #108]	@ (80069b8 <HAL_DMA_Abort_IT+0x400>)
 800694c:	4293      	cmp	r3, r2
 800694e:	d004      	beq.n	800695a <HAL_DMA_Abort_IT+0x3a2>
 8006950:	687b      	ldr	r3, [r7, #4]
 8006952:	681b      	ldr	r3, [r3, #0]
 8006954:	4a19      	ldr	r2, [pc, #100]	@ (80069bc <HAL_DMA_Abort_IT+0x404>)
 8006956:	4293      	cmp	r3, r2
 8006958:	d132      	bne.n	80069c0 <HAL_DMA_Abort_IT+0x408>
 800695a:	2301      	movs	r3, #1
 800695c:	e031      	b.n	80069c2 <HAL_DMA_Abort_IT+0x40a>
 800695e:	bf00      	nop
 8006960:	40020010 	.word	0x40020010
 8006964:	40020028 	.word	0x40020028
 8006968:	40020040 	.word	0x40020040
 800696c:	40020058 	.word	0x40020058
 8006970:	40020070 	.word	0x40020070
 8006974:	40020088 	.word	0x40020088
 8006978:	400200a0 	.word	0x400200a0
 800697c:	400200b8 	.word	0x400200b8
 8006980:	40020410 	.word	0x40020410
 8006984:	40020428 	.word	0x40020428
 8006988:	40020440 	.word	0x40020440
 800698c:	40020458 	.word	0x40020458
 8006990:	40020470 	.word	0x40020470
 8006994:	40020488 	.word	0x40020488
 8006998:	400204a0 	.word	0x400204a0
 800699c:	400204b8 	.word	0x400204b8
 80069a0:	58025408 	.word	0x58025408
 80069a4:	5802541c 	.word	0x5802541c
 80069a8:	58025430 	.word	0x58025430
 80069ac:	58025444 	.word	0x58025444
 80069b0:	58025458 	.word	0x58025458
 80069b4:	5802546c 	.word	0x5802546c
 80069b8:	58025480 	.word	0x58025480
 80069bc:	58025494 	.word	0x58025494
 80069c0:	2300      	movs	r3, #0
 80069c2:	2b00      	cmp	r3, #0
 80069c4:	d028      	beq.n	8006a18 <HAL_DMA_Abort_IT+0x460>
      {
        /* disable the DMAMUX sync overrun IT */
        hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
 80069c6:	687b      	ldr	r3, [r7, #4]
 80069c8:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80069ca:	681a      	ldr	r2, [r3, #0]
 80069cc:	687b      	ldr	r3, [r7, #4]
 80069ce:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80069d0:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
 80069d4:	601a      	str	r2, [r3, #0]

        /* Clear all flags */
        regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
 80069d6:	687b      	ldr	r3, [r7, #4]
 80069d8:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80069da:	60fb      	str	r3, [r7, #12]
        regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
 80069dc:	687b      	ldr	r3, [r7, #4]
 80069de:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80069e0:	f003 031f 	and.w	r3, r3, #31
 80069e4:	2201      	movs	r2, #1
 80069e6:	409a      	lsls	r2, r3
 80069e8:	68fb      	ldr	r3, [r7, #12]
 80069ea:	605a      	str	r2, [r3, #4]

        /* Clear the DMAMUX synchro overrun flag */
        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 80069ec:	687b      	ldr	r3, [r7, #4]
 80069ee:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 80069f0:	687a      	ldr	r2, [r7, #4]
 80069f2:	6e92      	ldr	r2, [r2, #104]	@ 0x68
 80069f4:	605a      	str	r2, [r3, #4]

        if(hdma->DMAmuxRequestGen != 0U)
 80069f6:	687b      	ldr	r3, [r7, #4]
 80069f8:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 80069fa:	2b00      	cmp	r3, #0
 80069fc:	d00c      	beq.n	8006a18 <HAL_DMA_Abort_IT+0x460>
        {
          /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
          /* disable the request gen overrun IT */
          hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
 80069fe:	687b      	ldr	r3, [r7, #4]
 8006a00:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8006a02:	681a      	ldr	r2, [r3, #0]
 8006a04:	687b      	ldr	r3, [r7, #4]
 8006a06:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8006a08:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
 8006a0c:	601a      	str	r2, [r3, #0]

          /* Clear the DMAMUX request generator overrun flag */
          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 8006a0e:	687b      	ldr	r3, [r7, #4]
 8006a10:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8006a12:	687a      	ldr	r2, [r7, #4]
 8006a14:	6f52      	ldr	r2, [r2, #116]	@ 0x74
 8006a16:	605a      	str	r2, [r3, #4]
        }
      }

      /* Change the DMA state */
      hdma->State = HAL_DMA_STATE_READY;
 8006a18:	687b      	ldr	r3, [r7, #4]
 8006a1a:	2201      	movs	r2, #1
 8006a1c:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

      /* Process Unlocked */
      __HAL_UNLOCK(hdma);
 8006a20:	687b      	ldr	r3, [r7, #4]
 8006a22:	2200      	movs	r2, #0
 8006a24:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

      /* Call User Abort callback */
      if(hdma->XferAbortCallback != NULL)
 8006a28:	687b      	ldr	r3, [r7, #4]
 8006a2a:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8006a2c:	2b00      	cmp	r3, #0
 8006a2e:	d003      	beq.n	8006a38 <HAL_DMA_Abort_IT+0x480>
      {
        hdma->XferAbortCallback(hdma);
 8006a30:	687b      	ldr	r3, [r7, #4]
 8006a32:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8006a34:	6878      	ldr	r0, [r7, #4]
 8006a36:	4798      	blx	r3
      }
    }
  }

  return HAL_OK;
 8006a38:	2300      	movs	r3, #0
}
 8006a3a:	4618      	mov	r0, r3
 8006a3c:	3710      	adds	r7, #16
 8006a3e:	46bd      	mov	sp, r7
 8006a40:	bd80      	pop	{r7, pc}
 8006a42:	bf00      	nop

08006a44 <HAL_DMA_IRQHandler>:
  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Stream.
  * @retval None
  */
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
 8006a44:	b580      	push	{r7, lr}
 8006a46:	b08a      	sub	sp, #40	@ 0x28
 8006a48:	af00      	add	r7, sp, #0
 8006a4a:	6078      	str	r0, [r7, #4]
  uint32_t tmpisr_dma, tmpisr_bdma;
  uint32_t ccr_reg;
  __IO uint32_t count = 0U;
 8006a4c:	2300      	movs	r3, #0
 8006a4e:	60fb      	str	r3, [r7, #12]
  uint32_t timeout = SystemCoreClock / 9600U;
 8006a50:	4b67      	ldr	r3, [pc, #412]	@ (8006bf0 <HAL_DMA_IRQHandler+0x1ac>)
 8006a52:	681b      	ldr	r3, [r3, #0]
 8006a54:	4a67      	ldr	r2, [pc, #412]	@ (8006bf4 <HAL_DMA_IRQHandler+0x1b0>)
 8006a56:	fba2 2303 	umull	r2, r3, r2, r3
 8006a5a:	0a9b      	lsrs	r3, r3, #10
 8006a5c:	627b      	str	r3, [r7, #36]	@ 0x24

  /* calculate DMA base and stream number */
  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
 8006a5e:	687b      	ldr	r3, [r7, #4]
 8006a60:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8006a62:	623b      	str	r3, [r7, #32]
  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
 8006a64:	687b      	ldr	r3, [r7, #4]
 8006a66:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8006a68:	61fb      	str	r3, [r7, #28]

  tmpisr_dma  = regs_dma->ISR;
 8006a6a:	6a3b      	ldr	r3, [r7, #32]
 8006a6c:	681b      	ldr	r3, [r3, #0]
 8006a6e:	61bb      	str	r3, [r7, #24]
  tmpisr_bdma = regs_bdma->ISR;
 8006a70:	69fb      	ldr	r3, [r7, #28]
 8006a72:	681b      	ldr	r3, [r3, #0]
 8006a74:	617b      	str	r3, [r7, #20]

  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U)  /* DMA1 or DMA2 instance */
 8006a76:	687b      	ldr	r3, [r7, #4]
 8006a78:	681b      	ldr	r3, [r3, #0]
 8006a7a:	4a5f      	ldr	r2, [pc, #380]	@ (8006bf8 <HAL_DMA_IRQHandler+0x1b4>)
 8006a7c:	4293      	cmp	r3, r2
 8006a7e:	d04a      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006a80:	687b      	ldr	r3, [r7, #4]
 8006a82:	681b      	ldr	r3, [r3, #0]
 8006a84:	4a5d      	ldr	r2, [pc, #372]	@ (8006bfc <HAL_DMA_IRQHandler+0x1b8>)
 8006a86:	4293      	cmp	r3, r2
 8006a88:	d045      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006a8a:	687b      	ldr	r3, [r7, #4]
 8006a8c:	681b      	ldr	r3, [r3, #0]
 8006a8e:	4a5c      	ldr	r2, [pc, #368]	@ (8006c00 <HAL_DMA_IRQHandler+0x1bc>)
 8006a90:	4293      	cmp	r3, r2
 8006a92:	d040      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006a94:	687b      	ldr	r3, [r7, #4]
 8006a96:	681b      	ldr	r3, [r3, #0]
 8006a98:	4a5a      	ldr	r2, [pc, #360]	@ (8006c04 <HAL_DMA_IRQHandler+0x1c0>)
 8006a9a:	4293      	cmp	r3, r2
 8006a9c:	d03b      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006a9e:	687b      	ldr	r3, [r7, #4]
 8006aa0:	681b      	ldr	r3, [r3, #0]
 8006aa2:	4a59      	ldr	r2, [pc, #356]	@ (8006c08 <HAL_DMA_IRQHandler+0x1c4>)
 8006aa4:	4293      	cmp	r3, r2
 8006aa6:	d036      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006aa8:	687b      	ldr	r3, [r7, #4]
 8006aaa:	681b      	ldr	r3, [r3, #0]
 8006aac:	4a57      	ldr	r2, [pc, #348]	@ (8006c0c <HAL_DMA_IRQHandler+0x1c8>)
 8006aae:	4293      	cmp	r3, r2
 8006ab0:	d031      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006ab2:	687b      	ldr	r3, [r7, #4]
 8006ab4:	681b      	ldr	r3, [r3, #0]
 8006ab6:	4a56      	ldr	r2, [pc, #344]	@ (8006c10 <HAL_DMA_IRQHandler+0x1cc>)
 8006ab8:	4293      	cmp	r3, r2
 8006aba:	d02c      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006abc:	687b      	ldr	r3, [r7, #4]
 8006abe:	681b      	ldr	r3, [r3, #0]
 8006ac0:	4a54      	ldr	r2, [pc, #336]	@ (8006c14 <HAL_DMA_IRQHandler+0x1d0>)
 8006ac2:	4293      	cmp	r3, r2
 8006ac4:	d027      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006ac6:	687b      	ldr	r3, [r7, #4]
 8006ac8:	681b      	ldr	r3, [r3, #0]
 8006aca:	4a53      	ldr	r2, [pc, #332]	@ (8006c18 <HAL_DMA_IRQHandler+0x1d4>)
 8006acc:	4293      	cmp	r3, r2
 8006ace:	d022      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006ad0:	687b      	ldr	r3, [r7, #4]
 8006ad2:	681b      	ldr	r3, [r3, #0]
 8006ad4:	4a51      	ldr	r2, [pc, #324]	@ (8006c1c <HAL_DMA_IRQHandler+0x1d8>)
 8006ad6:	4293      	cmp	r3, r2
 8006ad8:	d01d      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006ada:	687b      	ldr	r3, [r7, #4]
 8006adc:	681b      	ldr	r3, [r3, #0]
 8006ade:	4a50      	ldr	r2, [pc, #320]	@ (8006c20 <HAL_DMA_IRQHandler+0x1dc>)
 8006ae0:	4293      	cmp	r3, r2
 8006ae2:	d018      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006ae4:	687b      	ldr	r3, [r7, #4]
 8006ae6:	681b      	ldr	r3, [r3, #0]
 8006ae8:	4a4e      	ldr	r2, [pc, #312]	@ (8006c24 <HAL_DMA_IRQHandler+0x1e0>)
 8006aea:	4293      	cmp	r3, r2
 8006aec:	d013      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006aee:	687b      	ldr	r3, [r7, #4]
 8006af0:	681b      	ldr	r3, [r3, #0]
 8006af2:	4a4d      	ldr	r2, [pc, #308]	@ (8006c28 <HAL_DMA_IRQHandler+0x1e4>)
 8006af4:	4293      	cmp	r3, r2
 8006af6:	d00e      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006af8:	687b      	ldr	r3, [r7, #4]
 8006afa:	681b      	ldr	r3, [r3, #0]
 8006afc:	4a4b      	ldr	r2, [pc, #300]	@ (8006c2c <HAL_DMA_IRQHandler+0x1e8>)
 8006afe:	4293      	cmp	r3, r2
 8006b00:	d009      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006b02:	687b      	ldr	r3, [r7, #4]
 8006b04:	681b      	ldr	r3, [r3, #0]
 8006b06:	4a4a      	ldr	r2, [pc, #296]	@ (8006c30 <HAL_DMA_IRQHandler+0x1ec>)
 8006b08:	4293      	cmp	r3, r2
 8006b0a:	d004      	beq.n	8006b16 <HAL_DMA_IRQHandler+0xd2>
 8006b0c:	687b      	ldr	r3, [r7, #4]
 8006b0e:	681b      	ldr	r3, [r3, #0]
 8006b10:	4a48      	ldr	r2, [pc, #288]	@ (8006c34 <HAL_DMA_IRQHandler+0x1f0>)
 8006b12:	4293      	cmp	r3, r2
 8006b14:	d101      	bne.n	8006b1a <HAL_DMA_IRQHandler+0xd6>
 8006b16:	2301      	movs	r3, #1
 8006b18:	e000      	b.n	8006b1c <HAL_DMA_IRQHandler+0xd8>
 8006b1a:	2300      	movs	r3, #0
 8006b1c:	2b00      	cmp	r3, #0
 8006b1e:	f000 842b 	beq.w	8007378 <HAL_DMA_IRQHandler+0x934>
  {
    /* Transfer Error Interrupt management ***************************************/
    if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
 8006b22:	687b      	ldr	r3, [r7, #4]
 8006b24:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8006b26:	f003 031f 	and.w	r3, r3, #31
 8006b2a:	2208      	movs	r2, #8
 8006b2c:	409a      	lsls	r2, r3
 8006b2e:	69bb      	ldr	r3, [r7, #24]
 8006b30:	4013      	ands	r3, r2
 8006b32:	2b00      	cmp	r3, #0
 8006b34:	f000 80a2 	beq.w	8006c7c <HAL_DMA_IRQHandler+0x238>
    {
      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U)
 8006b38:	687b      	ldr	r3, [r7, #4]
 8006b3a:	681b      	ldr	r3, [r3, #0]
 8006b3c:	4a2e      	ldr	r2, [pc, #184]	@ (8006bf8 <HAL_DMA_IRQHandler+0x1b4>)
 8006b3e:	4293      	cmp	r3, r2
 8006b40:	d04a      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006b42:	687b      	ldr	r3, [r7, #4]
 8006b44:	681b      	ldr	r3, [r3, #0]
 8006b46:	4a2d      	ldr	r2, [pc, #180]	@ (8006bfc <HAL_DMA_IRQHandler+0x1b8>)
 8006b48:	4293      	cmp	r3, r2
 8006b4a:	d045      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006b4c:	687b      	ldr	r3, [r7, #4]
 8006b4e:	681b      	ldr	r3, [r3, #0]
 8006b50:	4a2b      	ldr	r2, [pc, #172]	@ (8006c00 <HAL_DMA_IRQHandler+0x1bc>)
 8006b52:	4293      	cmp	r3, r2
 8006b54:	d040      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006b56:	687b      	ldr	r3, [r7, #4]
 8006b58:	681b      	ldr	r3, [r3, #0]
 8006b5a:	4a2a      	ldr	r2, [pc, #168]	@ (8006c04 <HAL_DMA_IRQHandler+0x1c0>)
 8006b5c:	4293      	cmp	r3, r2
 8006b5e:	d03b      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006b60:	687b      	ldr	r3, [r7, #4]
 8006b62:	681b      	ldr	r3, [r3, #0]
 8006b64:	4a28      	ldr	r2, [pc, #160]	@ (8006c08 <HAL_DMA_IRQHandler+0x1c4>)
 8006b66:	4293      	cmp	r3, r2
 8006b68:	d036      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006b6a:	687b      	ldr	r3, [r7, #4]
 8006b6c:	681b      	ldr	r3, [r3, #0]
 8006b6e:	4a27      	ldr	r2, [pc, #156]	@ (8006c0c <HAL_DMA_IRQHandler+0x1c8>)
 8006b70:	4293      	cmp	r3, r2
 8006b72:	d031      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006b74:	687b      	ldr	r3, [r7, #4]
 8006b76:	681b      	ldr	r3, [r3, #0]
 8006b78:	4a25      	ldr	r2, [pc, #148]	@ (8006c10 <HAL_DMA_IRQHandler+0x1cc>)
 8006b7a:	4293      	cmp	r3, r2
 8006b7c:	d02c      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006b7e:	687b      	ldr	r3, [r7, #4]
 8006b80:	681b      	ldr	r3, [r3, #0]
 8006b82:	4a24      	ldr	r2, [pc, #144]	@ (8006c14 <HAL_DMA_IRQHandler+0x1d0>)
 8006b84:	4293      	cmp	r3, r2
 8006b86:	d027      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006b88:	687b      	ldr	r3, [r7, #4]
 8006b8a:	681b      	ldr	r3, [r3, #0]
 8006b8c:	4a22      	ldr	r2, [pc, #136]	@ (8006c18 <HAL_DMA_IRQHandler+0x1d4>)
 8006b8e:	4293      	cmp	r3, r2
 8006b90:	d022      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006b92:	687b      	ldr	r3, [r7, #4]
 8006b94:	681b      	ldr	r3, [r3, #0]
 8006b96:	4a21      	ldr	r2, [pc, #132]	@ (8006c1c <HAL_DMA_IRQHandler+0x1d8>)
 8006b98:	4293      	cmp	r3, r2
 8006b9a:	d01d      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006b9c:	687b      	ldr	r3, [r7, #4]
 8006b9e:	681b      	ldr	r3, [r3, #0]
 8006ba0:	4a1f      	ldr	r2, [pc, #124]	@ (8006c20 <HAL_DMA_IRQHandler+0x1dc>)
 8006ba2:	4293      	cmp	r3, r2
 8006ba4:	d018      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006ba6:	687b      	ldr	r3, [r7, #4]
 8006ba8:	681b      	ldr	r3, [r3, #0]
 8006baa:	4a1e      	ldr	r2, [pc, #120]	@ (8006c24 <HAL_DMA_IRQHandler+0x1e0>)
 8006bac:	4293      	cmp	r3, r2
 8006bae:	d013      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006bb0:	687b      	ldr	r3, [r7, #4]
 8006bb2:	681b      	ldr	r3, [r3, #0]
 8006bb4:	4a1c      	ldr	r2, [pc, #112]	@ (8006c28 <HAL_DMA_IRQHandler+0x1e4>)
 8006bb6:	4293      	cmp	r3, r2
 8006bb8:	d00e      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006bba:	687b      	ldr	r3, [r7, #4]
 8006bbc:	681b      	ldr	r3, [r3, #0]
 8006bbe:	4a1b      	ldr	r2, [pc, #108]	@ (8006c2c <HAL_DMA_IRQHandler+0x1e8>)
 8006bc0:	4293      	cmp	r3, r2
 8006bc2:	d009      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006bc4:	687b      	ldr	r3, [r7, #4]
 8006bc6:	681b      	ldr	r3, [r3, #0]
 8006bc8:	4a19      	ldr	r2, [pc, #100]	@ (8006c30 <HAL_DMA_IRQHandler+0x1ec>)
 8006bca:	4293      	cmp	r3, r2
 8006bcc:	d004      	beq.n	8006bd8 <HAL_DMA_IRQHandler+0x194>
 8006bce:	687b      	ldr	r3, [r7, #4]
 8006bd0:	681b      	ldr	r3, [r3, #0]
 8006bd2:	4a18      	ldr	r2, [pc, #96]	@ (8006c34 <HAL_DMA_IRQHandler+0x1f0>)
 8006bd4:	4293      	cmp	r3, r2
 8006bd6:	d12f      	bne.n	8006c38 <HAL_DMA_IRQHandler+0x1f4>
 8006bd8:	687b      	ldr	r3, [r7, #4]
 8006bda:	681b      	ldr	r3, [r3, #0]
 8006bdc:	681b      	ldr	r3, [r3, #0]
 8006bde:	f003 0304 	and.w	r3, r3, #4
 8006be2:	2b00      	cmp	r3, #0
 8006be4:	bf14      	ite	ne
 8006be6:	2301      	movne	r3, #1
 8006be8:	2300      	moveq	r3, #0
 8006bea:	b2db      	uxtb	r3, r3
 8006bec:	e02e      	b.n	8006c4c <HAL_DMA_IRQHandler+0x208>
 8006bee:	bf00      	nop
 8006bf0:	24000034 	.word	0x24000034
 8006bf4:	1b4e81b5 	.word	0x1b4e81b5
 8006bf8:	40020010 	.word	0x40020010
 8006bfc:	40020028 	.word	0x40020028
 8006c00:	40020040 	.word	0x40020040
 8006c04:	40020058 	.word	0x40020058
 8006c08:	40020070 	.word	0x40020070
 8006c0c:	40020088 	.word	0x40020088
 8006c10:	400200a0 	.word	0x400200a0
 8006c14:	400200b8 	.word	0x400200b8
 8006c18:	40020410 	.word	0x40020410
 8006c1c:	40020428 	.word	0x40020428
 8006c20:	40020440 	.word	0x40020440
 8006c24:	40020458 	.word	0x40020458
 8006c28:	40020470 	.word	0x40020470
 8006c2c:	40020488 	.word	0x40020488
 8006c30:	400204a0 	.word	0x400204a0
 8006c34:	400204b8 	.word	0x400204b8
 8006c38:	687b      	ldr	r3, [r7, #4]
 8006c3a:	681b      	ldr	r3, [r3, #0]
 8006c3c:	681b      	ldr	r3, [r3, #0]
 8006c3e:	f003 0308 	and.w	r3, r3, #8
 8006c42:	2b00      	cmp	r3, #0
 8006c44:	bf14      	ite	ne
 8006c46:	2301      	movne	r3, #1
 8006c48:	2300      	moveq	r3, #0
 8006c4a:	b2db      	uxtb	r3, r3
 8006c4c:	2b00      	cmp	r3, #0
 8006c4e:	d015      	beq.n	8006c7c <HAL_DMA_IRQHandler+0x238>
      {
        /* Disable the transfer error interrupt */
        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TE);
 8006c50:	687b      	ldr	r3, [r7, #4]
 8006c52:	681b      	ldr	r3, [r3, #0]
 8006c54:	681a      	ldr	r2, [r3, #0]
 8006c56:	687b      	ldr	r3, [r7, #4]
 8006c58:	681b      	ldr	r3, [r3, #0]
 8006c5a:	f022 0204 	bic.w	r2, r2, #4
 8006c5e:	601a      	str	r2, [r3, #0]

        /* Clear the transfer error flag */
        regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
 8006c60:	687b      	ldr	r3, [r7, #4]
 8006c62:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8006c64:	f003 031f 	and.w	r3, r3, #31
 8006c68:	2208      	movs	r2, #8
 8006c6a:	409a      	lsls	r2, r3
 8006c6c:	6a3b      	ldr	r3, [r7, #32]
 8006c6e:	609a      	str	r2, [r3, #8]

        /* Update error code */
        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
 8006c70:	687b      	ldr	r3, [r7, #4]
 8006c72:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006c74:	f043 0201 	orr.w	r2, r3, #1
 8006c78:	687b      	ldr	r3, [r7, #4]
 8006c7a:	655a      	str	r2, [r3, #84]	@ 0x54
      }
    }
    /* FIFO Error Interrupt management ******************************************/
    if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
 8006c7c:	687b      	ldr	r3, [r7, #4]
 8006c7e:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8006c80:	f003 031f 	and.w	r3, r3, #31
 8006c84:	69ba      	ldr	r2, [r7, #24]
 8006c86:	fa22 f303 	lsr.w	r3, r2, r3
 8006c8a:	f003 0301 	and.w	r3, r3, #1
 8006c8e:	2b00      	cmp	r3, #0
 8006c90:	d06e      	beq.n	8006d70 <HAL_DMA_IRQHandler+0x32c>
    {
      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
 8006c92:	687b      	ldr	r3, [r7, #4]
 8006c94:	681b      	ldr	r3, [r3, #0]
 8006c96:	4a69      	ldr	r2, [pc, #420]	@ (8006e3c <HAL_DMA_IRQHandler+0x3f8>)
 8006c98:	4293      	cmp	r3, r2
 8006c9a:	d04a      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006c9c:	687b      	ldr	r3, [r7, #4]
 8006c9e:	681b      	ldr	r3, [r3, #0]
 8006ca0:	4a67      	ldr	r2, [pc, #412]	@ (8006e40 <HAL_DMA_IRQHandler+0x3fc>)
 8006ca2:	4293      	cmp	r3, r2
 8006ca4:	d045      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006ca6:	687b      	ldr	r3, [r7, #4]
 8006ca8:	681b      	ldr	r3, [r3, #0]
 8006caa:	4a66      	ldr	r2, [pc, #408]	@ (8006e44 <HAL_DMA_IRQHandler+0x400>)
 8006cac:	4293      	cmp	r3, r2
 8006cae:	d040      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006cb0:	687b      	ldr	r3, [r7, #4]
 8006cb2:	681b      	ldr	r3, [r3, #0]
 8006cb4:	4a64      	ldr	r2, [pc, #400]	@ (8006e48 <HAL_DMA_IRQHandler+0x404>)
 8006cb6:	4293      	cmp	r3, r2
 8006cb8:	d03b      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006cba:	687b      	ldr	r3, [r7, #4]
 8006cbc:	681b      	ldr	r3, [r3, #0]
 8006cbe:	4a63      	ldr	r2, [pc, #396]	@ (8006e4c <HAL_DMA_IRQHandler+0x408>)
 8006cc0:	4293      	cmp	r3, r2
 8006cc2:	d036      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006cc4:	687b      	ldr	r3, [r7, #4]
 8006cc6:	681b      	ldr	r3, [r3, #0]
 8006cc8:	4a61      	ldr	r2, [pc, #388]	@ (8006e50 <HAL_DMA_IRQHandler+0x40c>)
 8006cca:	4293      	cmp	r3, r2
 8006ccc:	d031      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006cce:	687b      	ldr	r3, [r7, #4]
 8006cd0:	681b      	ldr	r3, [r3, #0]
 8006cd2:	4a60      	ldr	r2, [pc, #384]	@ (8006e54 <HAL_DMA_IRQHandler+0x410>)
 8006cd4:	4293      	cmp	r3, r2
 8006cd6:	d02c      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006cd8:	687b      	ldr	r3, [r7, #4]
 8006cda:	681b      	ldr	r3, [r3, #0]
 8006cdc:	4a5e      	ldr	r2, [pc, #376]	@ (8006e58 <HAL_DMA_IRQHandler+0x414>)
 8006cde:	4293      	cmp	r3, r2
 8006ce0:	d027      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006ce2:	687b      	ldr	r3, [r7, #4]
 8006ce4:	681b      	ldr	r3, [r3, #0]
 8006ce6:	4a5d      	ldr	r2, [pc, #372]	@ (8006e5c <HAL_DMA_IRQHandler+0x418>)
 8006ce8:	4293      	cmp	r3, r2
 8006cea:	d022      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006cec:	687b      	ldr	r3, [r7, #4]
 8006cee:	681b      	ldr	r3, [r3, #0]
 8006cf0:	4a5b      	ldr	r2, [pc, #364]	@ (8006e60 <HAL_DMA_IRQHandler+0x41c>)
 8006cf2:	4293      	cmp	r3, r2
 8006cf4:	d01d      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006cf6:	687b      	ldr	r3, [r7, #4]
 8006cf8:	681b      	ldr	r3, [r3, #0]
 8006cfa:	4a5a      	ldr	r2, [pc, #360]	@ (8006e64 <HAL_DMA_IRQHandler+0x420>)
 8006cfc:	4293      	cmp	r3, r2
 8006cfe:	d018      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006d00:	687b      	ldr	r3, [r7, #4]
 8006d02:	681b      	ldr	r3, [r3, #0]
 8006d04:	4a58      	ldr	r2, [pc, #352]	@ (8006e68 <HAL_DMA_IRQHandler+0x424>)
 8006d06:	4293      	cmp	r3, r2
 8006d08:	d013      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006d0a:	687b      	ldr	r3, [r7, #4]
 8006d0c:	681b      	ldr	r3, [r3, #0]
 8006d0e:	4a57      	ldr	r2, [pc, #348]	@ (8006e6c <HAL_DMA_IRQHandler+0x428>)
 8006d10:	4293      	cmp	r3, r2
 8006d12:	d00e      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006d14:	687b      	ldr	r3, [r7, #4]
 8006d16:	681b      	ldr	r3, [r3, #0]
 8006d18:	4a55      	ldr	r2, [pc, #340]	@ (8006e70 <HAL_DMA_IRQHandler+0x42c>)
 8006d1a:	4293      	cmp	r3, r2
 8006d1c:	d009      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006d1e:	687b      	ldr	r3, [r7, #4]
 8006d20:	681b      	ldr	r3, [r3, #0]
 8006d22:	4a54      	ldr	r2, [pc, #336]	@ (8006e74 <HAL_DMA_IRQHandler+0x430>)
 8006d24:	4293      	cmp	r3, r2
 8006d26:	d004      	beq.n	8006d32 <HAL_DMA_IRQHandler+0x2ee>
 8006d28:	687b      	ldr	r3, [r7, #4]
 8006d2a:	681b      	ldr	r3, [r3, #0]
 8006d2c:	4a52      	ldr	r2, [pc, #328]	@ (8006e78 <HAL_DMA_IRQHandler+0x434>)
 8006d2e:	4293      	cmp	r3, r2
 8006d30:	d10a      	bne.n	8006d48 <HAL_DMA_IRQHandler+0x304>
 8006d32:	687b      	ldr	r3, [r7, #4]
 8006d34:	681b      	ldr	r3, [r3, #0]
 8006d36:	695b      	ldr	r3, [r3, #20]
 8006d38:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8006d3c:	2b00      	cmp	r3, #0
 8006d3e:	bf14      	ite	ne
 8006d40:	2301      	movne	r3, #1
 8006d42:	2300      	moveq	r3, #0
 8006d44:	b2db      	uxtb	r3, r3
 8006d46:	e003      	b.n	8006d50 <HAL_DMA_IRQHandler+0x30c>
 8006d48:	687b      	ldr	r3, [r7, #4]
 8006d4a:	681b      	ldr	r3, [r3, #0]
 8006d4c:	681b      	ldr	r3, [r3, #0]
 8006d4e:	2300      	movs	r3, #0
 8006d50:	2b00      	cmp	r3, #0
 8006d52:	d00d      	beq.n	8006d70 <HAL_DMA_IRQHandler+0x32c>
      {
        /* Clear the FIFO error flag */
        regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
 8006d54:	687b      	ldr	r3, [r7, #4]
 8006d56:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8006d58:	f003 031f 	and.w	r3, r3, #31
 8006d5c:	2201      	movs	r2, #1
 8006d5e:	409a      	lsls	r2, r3
 8006d60:	6a3b      	ldr	r3, [r7, #32]
 8006d62:	609a      	str	r2, [r3, #8]

        /* Update error code */
        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
 8006d64:	687b      	ldr	r3, [r7, #4]
 8006d66:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006d68:	f043 0202 	orr.w	r2, r3, #2
 8006d6c:	687b      	ldr	r3, [r7, #4]
 8006d6e:	655a      	str	r2, [r3, #84]	@ 0x54
      }
    }
    /* Direct Mode Error Interrupt management ***********************************/
    if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
 8006d70:	687b      	ldr	r3, [r7, #4]
 8006d72:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8006d74:	f003 031f 	and.w	r3, r3, #31
 8006d78:	2204      	movs	r2, #4
 8006d7a:	409a      	lsls	r2, r3
 8006d7c:	69bb      	ldr	r3, [r7, #24]
 8006d7e:	4013      	ands	r3, r2
 8006d80:	2b00      	cmp	r3, #0
 8006d82:	f000 808f 	beq.w	8006ea4 <HAL_DMA_IRQHandler+0x460>
    {
      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)
 8006d86:	687b      	ldr	r3, [r7, #4]
 8006d88:	681b      	ldr	r3, [r3, #0]
 8006d8a:	4a2c      	ldr	r2, [pc, #176]	@ (8006e3c <HAL_DMA_IRQHandler+0x3f8>)
 8006d8c:	4293      	cmp	r3, r2
 8006d8e:	d04a      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006d90:	687b      	ldr	r3, [r7, #4]
 8006d92:	681b      	ldr	r3, [r3, #0]
 8006d94:	4a2a      	ldr	r2, [pc, #168]	@ (8006e40 <HAL_DMA_IRQHandler+0x3fc>)
 8006d96:	4293      	cmp	r3, r2
 8006d98:	d045      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006d9a:	687b      	ldr	r3, [r7, #4]
 8006d9c:	681b      	ldr	r3, [r3, #0]
 8006d9e:	4a29      	ldr	r2, [pc, #164]	@ (8006e44 <HAL_DMA_IRQHandler+0x400>)
 8006da0:	4293      	cmp	r3, r2
 8006da2:	d040      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006da4:	687b      	ldr	r3, [r7, #4]
 8006da6:	681b      	ldr	r3, [r3, #0]
 8006da8:	4a27      	ldr	r2, [pc, #156]	@ (8006e48 <HAL_DMA_IRQHandler+0x404>)
 8006daa:	4293      	cmp	r3, r2
 8006dac:	d03b      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006dae:	687b      	ldr	r3, [r7, #4]
 8006db0:	681b      	ldr	r3, [r3, #0]
 8006db2:	4a26      	ldr	r2, [pc, #152]	@ (8006e4c <HAL_DMA_IRQHandler+0x408>)
 8006db4:	4293      	cmp	r3, r2
 8006db6:	d036      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006db8:	687b      	ldr	r3, [r7, #4]
 8006dba:	681b      	ldr	r3, [r3, #0]
 8006dbc:	4a24      	ldr	r2, [pc, #144]	@ (8006e50 <HAL_DMA_IRQHandler+0x40c>)
 8006dbe:	4293      	cmp	r3, r2
 8006dc0:	d031      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006dc2:	687b      	ldr	r3, [r7, #4]
 8006dc4:	681b      	ldr	r3, [r3, #0]
 8006dc6:	4a23      	ldr	r2, [pc, #140]	@ (8006e54 <HAL_DMA_IRQHandler+0x410>)
 8006dc8:	4293      	cmp	r3, r2
 8006dca:	d02c      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006dcc:	687b      	ldr	r3, [r7, #4]
 8006dce:	681b      	ldr	r3, [r3, #0]
 8006dd0:	4a21      	ldr	r2, [pc, #132]	@ (8006e58 <HAL_DMA_IRQHandler+0x414>)
 8006dd2:	4293      	cmp	r3, r2
 8006dd4:	d027      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006dd6:	687b      	ldr	r3, [r7, #4]
 8006dd8:	681b      	ldr	r3, [r3, #0]
 8006dda:	4a20      	ldr	r2, [pc, #128]	@ (8006e5c <HAL_DMA_IRQHandler+0x418>)
 8006ddc:	4293      	cmp	r3, r2
 8006dde:	d022      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006de0:	687b      	ldr	r3, [r7, #4]
 8006de2:	681b      	ldr	r3, [r3, #0]
 8006de4:	4a1e      	ldr	r2, [pc, #120]	@ (8006e60 <HAL_DMA_IRQHandler+0x41c>)
 8006de6:	4293      	cmp	r3, r2
 8006de8:	d01d      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006dea:	687b      	ldr	r3, [r7, #4]
 8006dec:	681b      	ldr	r3, [r3, #0]
 8006dee:	4a1d      	ldr	r2, [pc, #116]	@ (8006e64 <HAL_DMA_IRQHandler+0x420>)
 8006df0:	4293      	cmp	r3, r2
 8006df2:	d018      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006df4:	687b      	ldr	r3, [r7, #4]
 8006df6:	681b      	ldr	r3, [r3, #0]
 8006df8:	4a1b      	ldr	r2, [pc, #108]	@ (8006e68 <HAL_DMA_IRQHandler+0x424>)
 8006dfa:	4293      	cmp	r3, r2
 8006dfc:	d013      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006dfe:	687b      	ldr	r3, [r7, #4]
 8006e00:	681b      	ldr	r3, [r3, #0]
 8006e02:	4a1a      	ldr	r2, [pc, #104]	@ (8006e6c <HAL_DMA_IRQHandler+0x428>)
 8006e04:	4293      	cmp	r3, r2
 8006e06:	d00e      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006e08:	687b      	ldr	r3, [r7, #4]
 8006e0a:	681b      	ldr	r3, [r3, #0]
 8006e0c:	4a18      	ldr	r2, [pc, #96]	@ (8006e70 <HAL_DMA_IRQHandler+0x42c>)
 8006e0e:	4293      	cmp	r3, r2
 8006e10:	d009      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006e12:	687b      	ldr	r3, [r7, #4]
 8006e14:	681b      	ldr	r3, [r3, #0]
 8006e16:	4a17      	ldr	r2, [pc, #92]	@ (8006e74 <HAL_DMA_IRQHandler+0x430>)
 8006e18:	4293      	cmp	r3, r2
 8006e1a:	d004      	beq.n	8006e26 <HAL_DMA_IRQHandler+0x3e2>
 8006e1c:	687b      	ldr	r3, [r7, #4]
 8006e1e:	681b      	ldr	r3, [r3, #0]
 8006e20:	4a15      	ldr	r2, [pc, #84]	@ (8006e78 <HAL_DMA_IRQHandler+0x434>)
 8006e22:	4293      	cmp	r3, r2
 8006e24:	d12a      	bne.n	8006e7c <HAL_DMA_IRQHandler+0x438>
 8006e26:	687b      	ldr	r3, [r7, #4]
 8006e28:	681b      	ldr	r3, [r3, #0]
 8006e2a:	681b      	ldr	r3, [r3, #0]
 8006e2c:	f003 0302 	and.w	r3, r3, #2
 8006e30:	2b00      	cmp	r3, #0
 8006e32:	bf14      	ite	ne
 8006e34:	2301      	movne	r3, #1
 8006e36:	2300      	moveq	r3, #0
 8006e38:	b2db      	uxtb	r3, r3
 8006e3a:	e023      	b.n	8006e84 <HAL_DMA_IRQHandler+0x440>
 8006e3c:	40020010 	.word	0x40020010
 8006e40:	40020028 	.word	0x40020028
 8006e44:	40020040 	.word	0x40020040
 8006e48:	40020058 	.word	0x40020058
 8006e4c:	40020070 	.word	0x40020070
 8006e50:	40020088 	.word	0x40020088
 8006e54:	400200a0 	.word	0x400200a0
 8006e58:	400200b8 	.word	0x400200b8
 8006e5c:	40020410 	.word	0x40020410
 8006e60:	40020428 	.word	0x40020428
 8006e64:	40020440 	.word	0x40020440
 8006e68:	40020458 	.word	0x40020458
 8006e6c:	40020470 	.word	0x40020470
 8006e70:	40020488 	.word	0x40020488
 8006e74:	400204a0 	.word	0x400204a0
 8006e78:	400204b8 	.word	0x400204b8
 8006e7c:	687b      	ldr	r3, [r7, #4]
 8006e7e:	681b      	ldr	r3, [r3, #0]
 8006e80:	681b      	ldr	r3, [r3, #0]
 8006e82:	2300      	movs	r3, #0
 8006e84:	2b00      	cmp	r3, #0
 8006e86:	d00d      	beq.n	8006ea4 <HAL_DMA_IRQHandler+0x460>
      {
        /* Clear the direct mode error flag */
        regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
 8006e88:	687b      	ldr	r3, [r7, #4]
 8006e8a:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8006e8c:	f003 031f 	and.w	r3, r3, #31
 8006e90:	2204      	movs	r2, #4
 8006e92:	409a      	lsls	r2, r3
 8006e94:	6a3b      	ldr	r3, [r7, #32]
 8006e96:	609a      	str	r2, [r3, #8]

        /* Update error code */
        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
 8006e98:	687b      	ldr	r3, [r7, #4]
 8006e9a:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006e9c:	f043 0204 	orr.w	r2, r3, #4
 8006ea0:	687b      	ldr	r3, [r7, #4]
 8006ea2:	655a      	str	r2, [r3, #84]	@ 0x54
      }
    }
    /* Half Transfer Complete Interrupt management ******************************/
    if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
 8006ea4:	687b      	ldr	r3, [r7, #4]
 8006ea6:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8006ea8:	f003 031f 	and.w	r3, r3, #31
 8006eac:	2210      	movs	r2, #16
 8006eae:	409a      	lsls	r2, r3
 8006eb0:	69bb      	ldr	r3, [r7, #24]
 8006eb2:	4013      	ands	r3, r2
 8006eb4:	2b00      	cmp	r3, #0
 8006eb6:	f000 80a6 	beq.w	8007006 <HAL_DMA_IRQHandler+0x5c2>
    {
      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
 8006eba:	687b      	ldr	r3, [r7, #4]
 8006ebc:	681b      	ldr	r3, [r3, #0]
 8006ebe:	4a85      	ldr	r2, [pc, #532]	@ (80070d4 <HAL_DMA_IRQHandler+0x690>)
 8006ec0:	4293      	cmp	r3, r2
 8006ec2:	d04a      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006ec4:	687b      	ldr	r3, [r7, #4]
 8006ec6:	681b      	ldr	r3, [r3, #0]
 8006ec8:	4a83      	ldr	r2, [pc, #524]	@ (80070d8 <HAL_DMA_IRQHandler+0x694>)
 8006eca:	4293      	cmp	r3, r2
 8006ecc:	d045      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006ece:	687b      	ldr	r3, [r7, #4]
 8006ed0:	681b      	ldr	r3, [r3, #0]
 8006ed2:	4a82      	ldr	r2, [pc, #520]	@ (80070dc <HAL_DMA_IRQHandler+0x698>)
 8006ed4:	4293      	cmp	r3, r2
 8006ed6:	d040      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006ed8:	687b      	ldr	r3, [r7, #4]
 8006eda:	681b      	ldr	r3, [r3, #0]
 8006edc:	4a80      	ldr	r2, [pc, #512]	@ (80070e0 <HAL_DMA_IRQHandler+0x69c>)
 8006ede:	4293      	cmp	r3, r2
 8006ee0:	d03b      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006ee2:	687b      	ldr	r3, [r7, #4]
 8006ee4:	681b      	ldr	r3, [r3, #0]
 8006ee6:	4a7f      	ldr	r2, [pc, #508]	@ (80070e4 <HAL_DMA_IRQHandler+0x6a0>)
 8006ee8:	4293      	cmp	r3, r2
 8006eea:	d036      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006eec:	687b      	ldr	r3, [r7, #4]
 8006eee:	681b      	ldr	r3, [r3, #0]
 8006ef0:	4a7d      	ldr	r2, [pc, #500]	@ (80070e8 <HAL_DMA_IRQHandler+0x6a4>)
 8006ef2:	4293      	cmp	r3, r2
 8006ef4:	d031      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006ef6:	687b      	ldr	r3, [r7, #4]
 8006ef8:	681b      	ldr	r3, [r3, #0]
 8006efa:	4a7c      	ldr	r2, [pc, #496]	@ (80070ec <HAL_DMA_IRQHandler+0x6a8>)
 8006efc:	4293      	cmp	r3, r2
 8006efe:	d02c      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006f00:	687b      	ldr	r3, [r7, #4]
 8006f02:	681b      	ldr	r3, [r3, #0]
 8006f04:	4a7a      	ldr	r2, [pc, #488]	@ (80070f0 <HAL_DMA_IRQHandler+0x6ac>)
 8006f06:	4293      	cmp	r3, r2
 8006f08:	d027      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006f0a:	687b      	ldr	r3, [r7, #4]
 8006f0c:	681b      	ldr	r3, [r3, #0]
 8006f0e:	4a79      	ldr	r2, [pc, #484]	@ (80070f4 <HAL_DMA_IRQHandler+0x6b0>)
 8006f10:	4293      	cmp	r3, r2
 8006f12:	d022      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006f14:	687b      	ldr	r3, [r7, #4]
 8006f16:	681b      	ldr	r3, [r3, #0]
 8006f18:	4a77      	ldr	r2, [pc, #476]	@ (80070f8 <HAL_DMA_IRQHandler+0x6b4>)
 8006f1a:	4293      	cmp	r3, r2
 8006f1c:	d01d      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006f1e:	687b      	ldr	r3, [r7, #4]
 8006f20:	681b      	ldr	r3, [r3, #0]
 8006f22:	4a76      	ldr	r2, [pc, #472]	@ (80070fc <HAL_DMA_IRQHandler+0x6b8>)
 8006f24:	4293      	cmp	r3, r2
 8006f26:	d018      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006f28:	687b      	ldr	r3, [r7, #4]
 8006f2a:	681b      	ldr	r3, [r3, #0]
 8006f2c:	4a74      	ldr	r2, [pc, #464]	@ (8007100 <HAL_DMA_IRQHandler+0x6bc>)
 8006f2e:	4293      	cmp	r3, r2
 8006f30:	d013      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006f32:	687b      	ldr	r3, [r7, #4]
 8006f34:	681b      	ldr	r3, [r3, #0]
 8006f36:	4a73      	ldr	r2, [pc, #460]	@ (8007104 <HAL_DMA_IRQHandler+0x6c0>)
 8006f38:	4293      	cmp	r3, r2
 8006f3a:	d00e      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006f3c:	687b      	ldr	r3, [r7, #4]
 8006f3e:	681b      	ldr	r3, [r3, #0]
 8006f40:	4a71      	ldr	r2, [pc, #452]	@ (8007108 <HAL_DMA_IRQHandler+0x6c4>)
 8006f42:	4293      	cmp	r3, r2
 8006f44:	d009      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006f46:	687b      	ldr	r3, [r7, #4]
 8006f48:	681b      	ldr	r3, [r3, #0]
 8006f4a:	4a70      	ldr	r2, [pc, #448]	@ (800710c <HAL_DMA_IRQHandler+0x6c8>)
 8006f4c:	4293      	cmp	r3, r2
 8006f4e:	d004      	beq.n	8006f5a <HAL_DMA_IRQHandler+0x516>
 8006f50:	687b      	ldr	r3, [r7, #4]
 8006f52:	681b      	ldr	r3, [r3, #0]
 8006f54:	4a6e      	ldr	r2, [pc, #440]	@ (8007110 <HAL_DMA_IRQHandler+0x6cc>)
 8006f56:	4293      	cmp	r3, r2
 8006f58:	d10a      	bne.n	8006f70 <HAL_DMA_IRQHandler+0x52c>
 8006f5a:	687b      	ldr	r3, [r7, #4]
 8006f5c:	681b      	ldr	r3, [r3, #0]
 8006f5e:	681b      	ldr	r3, [r3, #0]
 8006f60:	f003 0308 	and.w	r3, r3, #8
 8006f64:	2b00      	cmp	r3, #0
 8006f66:	bf14      	ite	ne
 8006f68:	2301      	movne	r3, #1
 8006f6a:	2300      	moveq	r3, #0
 8006f6c:	b2db      	uxtb	r3, r3
 8006f6e:	e009      	b.n	8006f84 <HAL_DMA_IRQHandler+0x540>
 8006f70:	687b      	ldr	r3, [r7, #4]
 8006f72:	681b      	ldr	r3, [r3, #0]
 8006f74:	681b      	ldr	r3, [r3, #0]
 8006f76:	f003 0304 	and.w	r3, r3, #4
 8006f7a:	2b00      	cmp	r3, #0
 8006f7c:	bf14      	ite	ne
 8006f7e:	2301      	movne	r3, #1
 8006f80:	2300      	moveq	r3, #0
 8006f82:	b2db      	uxtb	r3, r3
 8006f84:	2b00      	cmp	r3, #0
 8006f86:	d03e      	beq.n	8007006 <HAL_DMA_IRQHandler+0x5c2>
      {
        /* Clear the half transfer complete flag */
        regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
 8006f88:	687b      	ldr	r3, [r7, #4]
 8006f8a:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8006f8c:	f003 031f 	and.w	r3, r3, #31
 8006f90:	2210      	movs	r2, #16
 8006f92:	409a      	lsls	r2, r3
 8006f94:	6a3b      	ldr	r3, [r7, #32]
 8006f96:	609a      	str	r2, [r3, #8]

        /* Multi_Buffering mode enabled */
        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
 8006f98:	687b      	ldr	r3, [r7, #4]
 8006f9a:	681b      	ldr	r3, [r3, #0]
 8006f9c:	681b      	ldr	r3, [r3, #0]
 8006f9e:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 8006fa2:	2b00      	cmp	r3, #0
 8006fa4:	d018      	beq.n	8006fd8 <HAL_DMA_IRQHandler+0x594>
        {
          /* Current memory buffer used is Memory 0 */
          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
 8006fa6:	687b      	ldr	r3, [r7, #4]
 8006fa8:	681b      	ldr	r3, [r3, #0]
 8006faa:	681b      	ldr	r3, [r3, #0]
 8006fac:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
 8006fb0:	2b00      	cmp	r3, #0
 8006fb2:	d108      	bne.n	8006fc6 <HAL_DMA_IRQHandler+0x582>
          {
            if(hdma->XferHalfCpltCallback != NULL)
 8006fb4:	687b      	ldr	r3, [r7, #4]
 8006fb6:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8006fb8:	2b00      	cmp	r3, #0
 8006fba:	d024      	beq.n	8007006 <HAL_DMA_IRQHandler+0x5c2>
            {
              /* Half transfer callback */
              hdma->XferHalfCpltCallback(hdma);
 8006fbc:	687b      	ldr	r3, [r7, #4]
 8006fbe:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8006fc0:	6878      	ldr	r0, [r7, #4]
 8006fc2:	4798      	blx	r3
 8006fc4:	e01f      	b.n	8007006 <HAL_DMA_IRQHandler+0x5c2>
            }
          }
          /* Current memory buffer used is Memory 1 */
          else
          {
            if(hdma->XferM1HalfCpltCallback != NULL)
 8006fc6:	687b      	ldr	r3, [r7, #4]
 8006fc8:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8006fca:	2b00      	cmp	r3, #0
 8006fcc:	d01b      	beq.n	8007006 <HAL_DMA_IRQHandler+0x5c2>
            {
              /* Half transfer callback */
              hdma->XferM1HalfCpltCallback(hdma);
 8006fce:	687b      	ldr	r3, [r7, #4]
 8006fd0:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8006fd2:	6878      	ldr	r0, [r7, #4]
 8006fd4:	4798      	blx	r3
 8006fd6:	e016      	b.n	8007006 <HAL_DMA_IRQHandler+0x5c2>
          }
        }
        else
        {
          /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
 8006fd8:	687b      	ldr	r3, [r7, #4]
 8006fda:	681b      	ldr	r3, [r3, #0]
 8006fdc:	681b      	ldr	r3, [r3, #0]
 8006fde:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8006fe2:	2b00      	cmp	r3, #0
 8006fe4:	d107      	bne.n	8006ff6 <HAL_DMA_IRQHandler+0x5b2>
          {
            /* Disable the half transfer interrupt */
            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
 8006fe6:	687b      	ldr	r3, [r7, #4]
 8006fe8:	681b      	ldr	r3, [r3, #0]
 8006fea:	681a      	ldr	r2, [r3, #0]
 8006fec:	687b      	ldr	r3, [r7, #4]
 8006fee:	681b      	ldr	r3, [r3, #0]
 8006ff0:	f022 0208 	bic.w	r2, r2, #8
 8006ff4:	601a      	str	r2, [r3, #0]
          }

          if(hdma->XferHalfCpltCallback != NULL)
 8006ff6:	687b      	ldr	r3, [r7, #4]
 8006ff8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8006ffa:	2b00      	cmp	r3, #0
 8006ffc:	d003      	beq.n	8007006 <HAL_DMA_IRQHandler+0x5c2>
          {
            /* Half transfer callback */
            hdma->XferHalfCpltCallback(hdma);
 8006ffe:	687b      	ldr	r3, [r7, #4]
 8007000:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8007002:	6878      	ldr	r0, [r7, #4]
 8007004:	4798      	blx	r3
          }
        }
      }
    }
    /* Transfer Complete Interrupt management ***********************************/
    if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
 8007006:	687b      	ldr	r3, [r7, #4]
 8007008:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800700a:	f003 031f 	and.w	r3, r3, #31
 800700e:	2220      	movs	r2, #32
 8007010:	409a      	lsls	r2, r3
 8007012:	69bb      	ldr	r3, [r7, #24]
 8007014:	4013      	ands	r3, r2
 8007016:	2b00      	cmp	r3, #0
 8007018:	f000 8110 	beq.w	800723c <HAL_DMA_IRQHandler+0x7f8>
    {
      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
 800701c:	687b      	ldr	r3, [r7, #4]
 800701e:	681b      	ldr	r3, [r3, #0]
 8007020:	4a2c      	ldr	r2, [pc, #176]	@ (80070d4 <HAL_DMA_IRQHandler+0x690>)
 8007022:	4293      	cmp	r3, r2
 8007024:	d04a      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 8007026:	687b      	ldr	r3, [r7, #4]
 8007028:	681b      	ldr	r3, [r3, #0]
 800702a:	4a2b      	ldr	r2, [pc, #172]	@ (80070d8 <HAL_DMA_IRQHandler+0x694>)
 800702c:	4293      	cmp	r3, r2
 800702e:	d045      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 8007030:	687b      	ldr	r3, [r7, #4]
 8007032:	681b      	ldr	r3, [r3, #0]
 8007034:	4a29      	ldr	r2, [pc, #164]	@ (80070dc <HAL_DMA_IRQHandler+0x698>)
 8007036:	4293      	cmp	r3, r2
 8007038:	d040      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 800703a:	687b      	ldr	r3, [r7, #4]
 800703c:	681b      	ldr	r3, [r3, #0]
 800703e:	4a28      	ldr	r2, [pc, #160]	@ (80070e0 <HAL_DMA_IRQHandler+0x69c>)
 8007040:	4293      	cmp	r3, r2
 8007042:	d03b      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 8007044:	687b      	ldr	r3, [r7, #4]
 8007046:	681b      	ldr	r3, [r3, #0]
 8007048:	4a26      	ldr	r2, [pc, #152]	@ (80070e4 <HAL_DMA_IRQHandler+0x6a0>)
 800704a:	4293      	cmp	r3, r2
 800704c:	d036      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 800704e:	687b      	ldr	r3, [r7, #4]
 8007050:	681b      	ldr	r3, [r3, #0]
 8007052:	4a25      	ldr	r2, [pc, #148]	@ (80070e8 <HAL_DMA_IRQHandler+0x6a4>)
 8007054:	4293      	cmp	r3, r2
 8007056:	d031      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 8007058:	687b      	ldr	r3, [r7, #4]
 800705a:	681b      	ldr	r3, [r3, #0]
 800705c:	4a23      	ldr	r2, [pc, #140]	@ (80070ec <HAL_DMA_IRQHandler+0x6a8>)
 800705e:	4293      	cmp	r3, r2
 8007060:	d02c      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 8007062:	687b      	ldr	r3, [r7, #4]
 8007064:	681b      	ldr	r3, [r3, #0]
 8007066:	4a22      	ldr	r2, [pc, #136]	@ (80070f0 <HAL_DMA_IRQHandler+0x6ac>)
 8007068:	4293      	cmp	r3, r2
 800706a:	d027      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 800706c:	687b      	ldr	r3, [r7, #4]
 800706e:	681b      	ldr	r3, [r3, #0]
 8007070:	4a20      	ldr	r2, [pc, #128]	@ (80070f4 <HAL_DMA_IRQHandler+0x6b0>)
 8007072:	4293      	cmp	r3, r2
 8007074:	d022      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 8007076:	687b      	ldr	r3, [r7, #4]
 8007078:	681b      	ldr	r3, [r3, #0]
 800707a:	4a1f      	ldr	r2, [pc, #124]	@ (80070f8 <HAL_DMA_IRQHandler+0x6b4>)
 800707c:	4293      	cmp	r3, r2
 800707e:	d01d      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 8007080:	687b      	ldr	r3, [r7, #4]
 8007082:	681b      	ldr	r3, [r3, #0]
 8007084:	4a1d      	ldr	r2, [pc, #116]	@ (80070fc <HAL_DMA_IRQHandler+0x6b8>)
 8007086:	4293      	cmp	r3, r2
 8007088:	d018      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 800708a:	687b      	ldr	r3, [r7, #4]
 800708c:	681b      	ldr	r3, [r3, #0]
 800708e:	4a1c      	ldr	r2, [pc, #112]	@ (8007100 <HAL_DMA_IRQHandler+0x6bc>)
 8007090:	4293      	cmp	r3, r2
 8007092:	d013      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 8007094:	687b      	ldr	r3, [r7, #4]
 8007096:	681b      	ldr	r3, [r3, #0]
 8007098:	4a1a      	ldr	r2, [pc, #104]	@ (8007104 <HAL_DMA_IRQHandler+0x6c0>)
 800709a:	4293      	cmp	r3, r2
 800709c:	d00e      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 800709e:	687b      	ldr	r3, [r7, #4]
 80070a0:	681b      	ldr	r3, [r3, #0]
 80070a2:	4a19      	ldr	r2, [pc, #100]	@ (8007108 <HAL_DMA_IRQHandler+0x6c4>)
 80070a4:	4293      	cmp	r3, r2
 80070a6:	d009      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 80070a8:	687b      	ldr	r3, [r7, #4]
 80070aa:	681b      	ldr	r3, [r3, #0]
 80070ac:	4a17      	ldr	r2, [pc, #92]	@ (800710c <HAL_DMA_IRQHandler+0x6c8>)
 80070ae:	4293      	cmp	r3, r2
 80070b0:	d004      	beq.n	80070bc <HAL_DMA_IRQHandler+0x678>
 80070b2:	687b      	ldr	r3, [r7, #4]
 80070b4:	681b      	ldr	r3, [r3, #0]
 80070b6:	4a16      	ldr	r2, [pc, #88]	@ (8007110 <HAL_DMA_IRQHandler+0x6cc>)
 80070b8:	4293      	cmp	r3, r2
 80070ba:	d12b      	bne.n	8007114 <HAL_DMA_IRQHandler+0x6d0>
 80070bc:	687b      	ldr	r3, [r7, #4]
 80070be:	681b      	ldr	r3, [r3, #0]
 80070c0:	681b      	ldr	r3, [r3, #0]
 80070c2:	f003 0310 	and.w	r3, r3, #16
 80070c6:	2b00      	cmp	r3, #0
 80070c8:	bf14      	ite	ne
 80070ca:	2301      	movne	r3, #1
 80070cc:	2300      	moveq	r3, #0
 80070ce:	b2db      	uxtb	r3, r3
 80070d0:	e02a      	b.n	8007128 <HAL_DMA_IRQHandler+0x6e4>
 80070d2:	bf00      	nop
 80070d4:	40020010 	.word	0x40020010
 80070d8:	40020028 	.word	0x40020028
 80070dc:	40020040 	.word	0x40020040
 80070e0:	40020058 	.word	0x40020058
 80070e4:	40020070 	.word	0x40020070
 80070e8:	40020088 	.word	0x40020088
 80070ec:	400200a0 	.word	0x400200a0
 80070f0:	400200b8 	.word	0x400200b8
 80070f4:	40020410 	.word	0x40020410
 80070f8:	40020428 	.word	0x40020428
 80070fc:	40020440 	.word	0x40020440
 8007100:	40020458 	.word	0x40020458
 8007104:	40020470 	.word	0x40020470
 8007108:	40020488 	.word	0x40020488
 800710c:	400204a0 	.word	0x400204a0
 8007110:	400204b8 	.word	0x400204b8
 8007114:	687b      	ldr	r3, [r7, #4]
 8007116:	681b      	ldr	r3, [r3, #0]
 8007118:	681b      	ldr	r3, [r3, #0]
 800711a:	f003 0302 	and.w	r3, r3, #2
 800711e:	2b00      	cmp	r3, #0
 8007120:	bf14      	ite	ne
 8007122:	2301      	movne	r3, #1
 8007124:	2300      	moveq	r3, #0
 8007126:	b2db      	uxtb	r3, r3
 8007128:	2b00      	cmp	r3, #0
 800712a:	f000 8087 	beq.w	800723c <HAL_DMA_IRQHandler+0x7f8>
      {
        /* Clear the transfer complete flag */
        regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
 800712e:	687b      	ldr	r3, [r7, #4]
 8007130:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8007132:	f003 031f 	and.w	r3, r3, #31
 8007136:	2220      	movs	r2, #32
 8007138:	409a      	lsls	r2, r3
 800713a:	6a3b      	ldr	r3, [r7, #32]
 800713c:	609a      	str	r2, [r3, #8]

        if(HAL_DMA_STATE_ABORT == hdma->State)
 800713e:	687b      	ldr	r3, [r7, #4]
 8007140:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
 8007144:	b2db      	uxtb	r3, r3
 8007146:	2b04      	cmp	r3, #4
 8007148:	d139      	bne.n	80071be <HAL_DMA_IRQHandler+0x77a>
        {
          /* Disable all the transfer interrupts */
          ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
 800714a:	687b      	ldr	r3, [r7, #4]
 800714c:	681b      	ldr	r3, [r3, #0]
 800714e:	681a      	ldr	r2, [r3, #0]
 8007150:	687b      	ldr	r3, [r7, #4]
 8007152:	681b      	ldr	r3, [r3, #0]
 8007154:	f022 0216 	bic.w	r2, r2, #22
 8007158:	601a      	str	r2, [r3, #0]
          ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
 800715a:	687b      	ldr	r3, [r7, #4]
 800715c:	681b      	ldr	r3, [r3, #0]
 800715e:	695a      	ldr	r2, [r3, #20]
 8007160:	687b      	ldr	r3, [r7, #4]
 8007162:	681b      	ldr	r3, [r3, #0]
 8007164:	f022 0280 	bic.w	r2, r2, #128	@ 0x80
 8007168:	615a      	str	r2, [r3, #20]

          if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
 800716a:	687b      	ldr	r3, [r7, #4]
 800716c:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800716e:	2b00      	cmp	r3, #0
 8007170:	d103      	bne.n	800717a <HAL_DMA_IRQHandler+0x736>
 8007172:	687b      	ldr	r3, [r7, #4]
 8007174:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8007176:	2b00      	cmp	r3, #0
 8007178:	d007      	beq.n	800718a <HAL_DMA_IRQHandler+0x746>
          {
            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
 800717a:	687b      	ldr	r3, [r7, #4]
 800717c:	681b      	ldr	r3, [r3, #0]
 800717e:	681a      	ldr	r2, [r3, #0]
 8007180:	687b      	ldr	r3, [r7, #4]
 8007182:	681b      	ldr	r3, [r3, #0]
 8007184:	f022 0208 	bic.w	r2, r2, #8
 8007188:	601a      	str	r2, [r3, #0]
          }

          /* Clear all interrupt flags at correct offset within the register */
          regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
 800718a:	687b      	ldr	r3, [r7, #4]
 800718c:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800718e:	f003 031f 	and.w	r3, r3, #31
 8007192:	223f      	movs	r2, #63	@ 0x3f
 8007194:	409a      	lsls	r2, r3
 8007196:	6a3b      	ldr	r3, [r7, #32]
 8007198:	609a      	str	r2, [r3, #8]

          /* Change the DMA state */
          hdma->State = HAL_DMA_STATE_READY;
 800719a:	687b      	ldr	r3, [r7, #4]
 800719c:	2201      	movs	r2, #1
 800719e:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

          /* Process Unlocked */
          __HAL_UNLOCK(hdma);
 80071a2:	687b      	ldr	r3, [r7, #4]
 80071a4:	2200      	movs	r2, #0
 80071a6:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

          if(hdma->XferAbortCallback != NULL)
 80071aa:	687b      	ldr	r3, [r7, #4]
 80071ac:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80071ae:	2b00      	cmp	r3, #0
 80071b0:	f000 834a 	beq.w	8007848 <HAL_DMA_IRQHandler+0xe04>
          {
            hdma->XferAbortCallback(hdma);
 80071b4:	687b      	ldr	r3, [r7, #4]
 80071b6:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80071b8:	6878      	ldr	r0, [r7, #4]
 80071ba:	4798      	blx	r3
          }
          return;
 80071bc:	e344      	b.n	8007848 <HAL_DMA_IRQHandler+0xe04>
        }

        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
 80071be:	687b      	ldr	r3, [r7, #4]
 80071c0:	681b      	ldr	r3, [r3, #0]
 80071c2:	681b      	ldr	r3, [r3, #0]
 80071c4:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 80071c8:	2b00      	cmp	r3, #0
 80071ca:	d018      	beq.n	80071fe <HAL_DMA_IRQHandler+0x7ba>
        {
          /* Current memory buffer used is Memory 0 */
          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
 80071cc:	687b      	ldr	r3, [r7, #4]
 80071ce:	681b      	ldr	r3, [r3, #0]
 80071d0:	681b      	ldr	r3, [r3, #0]
 80071d2:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
 80071d6:	2b00      	cmp	r3, #0
 80071d8:	d108      	bne.n	80071ec <HAL_DMA_IRQHandler+0x7a8>
          {
            if(hdma->XferM1CpltCallback != NULL)
 80071da:	687b      	ldr	r3, [r7, #4]
 80071dc:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 80071de:	2b00      	cmp	r3, #0
 80071e0:	d02c      	beq.n	800723c <HAL_DMA_IRQHandler+0x7f8>
            {
              /* Transfer complete Callback for memory1 */
              hdma->XferM1CpltCallback(hdma);
 80071e2:	687b      	ldr	r3, [r7, #4]
 80071e4:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 80071e6:	6878      	ldr	r0, [r7, #4]
 80071e8:	4798      	blx	r3
 80071ea:	e027      	b.n	800723c <HAL_DMA_IRQHandler+0x7f8>
            }
          }
          /* Current memory buffer used is Memory 1 */
          else
          {
            if(hdma->XferCpltCallback != NULL)
 80071ec:	687b      	ldr	r3, [r7, #4]
 80071ee:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80071f0:	2b00      	cmp	r3, #0
 80071f2:	d023      	beq.n	800723c <HAL_DMA_IRQHandler+0x7f8>
            {
              /* Transfer complete Callback for memory0 */
              hdma->XferCpltCallback(hdma);
 80071f4:	687b      	ldr	r3, [r7, #4]
 80071f6:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80071f8:	6878      	ldr	r0, [r7, #4]
 80071fa:	4798      	blx	r3
 80071fc:	e01e      	b.n	800723c <HAL_DMA_IRQHandler+0x7f8>
          }
        }
        /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
        else
        {
          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
 80071fe:	687b      	ldr	r3, [r7, #4]
 8007200:	681b      	ldr	r3, [r3, #0]
 8007202:	681b      	ldr	r3, [r3, #0]
 8007204:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8007208:	2b00      	cmp	r3, #0
 800720a:	d10f      	bne.n	800722c <HAL_DMA_IRQHandler+0x7e8>
          {
            /* Disable the transfer complete interrupt */
            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
 800720c:	687b      	ldr	r3, [r7, #4]
 800720e:	681b      	ldr	r3, [r3, #0]
 8007210:	681a      	ldr	r2, [r3, #0]
 8007212:	687b      	ldr	r3, [r7, #4]
 8007214:	681b      	ldr	r3, [r3, #0]
 8007216:	f022 0210 	bic.w	r2, r2, #16
 800721a:	601a      	str	r2, [r3, #0]

            /* Change the DMA state */
            hdma->State = HAL_DMA_STATE_READY;
 800721c:	687b      	ldr	r3, [r7, #4]
 800721e:	2201      	movs	r2, #1
 8007220:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

            /* Process Unlocked */
            __HAL_UNLOCK(hdma);
 8007224:	687b      	ldr	r3, [r7, #4]
 8007226:	2200      	movs	r2, #0
 8007228:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
          }

          if(hdma->XferCpltCallback != NULL)
 800722c:	687b      	ldr	r3, [r7, #4]
 800722e:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8007230:	2b00      	cmp	r3, #0
 8007232:	d003      	beq.n	800723c <HAL_DMA_IRQHandler+0x7f8>
          {
            /* Transfer complete callback */
            hdma->XferCpltCallback(hdma);
 8007234:	687b      	ldr	r3, [r7, #4]
 8007236:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8007238:	6878      	ldr	r0, [r7, #4]
 800723a:	4798      	blx	r3
        }
      }
    }

    /* manage error case */
    if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
 800723c:	687b      	ldr	r3, [r7, #4]
 800723e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8007240:	2b00      	cmp	r3, #0
 8007242:	f000 8306 	beq.w	8007852 <HAL_DMA_IRQHandler+0xe0e>
    {
      if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)
 8007246:	687b      	ldr	r3, [r7, #4]
 8007248:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800724a:	f003 0301 	and.w	r3, r3, #1
 800724e:	2b00      	cmp	r3, #0
 8007250:	f000 8088 	beq.w	8007364 <HAL_DMA_IRQHandler+0x920>
      {
        hdma->State = HAL_DMA_STATE_ABORT;
 8007254:	687b      	ldr	r3, [r7, #4]
 8007256:	2204      	movs	r2, #4
 8007258:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

        /* Disable the stream */
        __HAL_DMA_DISABLE(hdma);
 800725c:	687b      	ldr	r3, [r7, #4]
 800725e:	681b      	ldr	r3, [r3, #0]
 8007260:	4a7a      	ldr	r2, [pc, #488]	@ (800744c <HAL_DMA_IRQHandler+0xa08>)
 8007262:	4293      	cmp	r3, r2
 8007264:	d04a      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 8007266:	687b      	ldr	r3, [r7, #4]
 8007268:	681b      	ldr	r3, [r3, #0]
 800726a:	4a79      	ldr	r2, [pc, #484]	@ (8007450 <HAL_DMA_IRQHandler+0xa0c>)
 800726c:	4293      	cmp	r3, r2
 800726e:	d045      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 8007270:	687b      	ldr	r3, [r7, #4]
 8007272:	681b      	ldr	r3, [r3, #0]
 8007274:	4a77      	ldr	r2, [pc, #476]	@ (8007454 <HAL_DMA_IRQHandler+0xa10>)
 8007276:	4293      	cmp	r3, r2
 8007278:	d040      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 800727a:	687b      	ldr	r3, [r7, #4]
 800727c:	681b      	ldr	r3, [r3, #0]
 800727e:	4a76      	ldr	r2, [pc, #472]	@ (8007458 <HAL_DMA_IRQHandler+0xa14>)
 8007280:	4293      	cmp	r3, r2
 8007282:	d03b      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 8007284:	687b      	ldr	r3, [r7, #4]
 8007286:	681b      	ldr	r3, [r3, #0]
 8007288:	4a74      	ldr	r2, [pc, #464]	@ (800745c <HAL_DMA_IRQHandler+0xa18>)
 800728a:	4293      	cmp	r3, r2
 800728c:	d036      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 800728e:	687b      	ldr	r3, [r7, #4]
 8007290:	681b      	ldr	r3, [r3, #0]
 8007292:	4a73      	ldr	r2, [pc, #460]	@ (8007460 <HAL_DMA_IRQHandler+0xa1c>)
 8007294:	4293      	cmp	r3, r2
 8007296:	d031      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 8007298:	687b      	ldr	r3, [r7, #4]
 800729a:	681b      	ldr	r3, [r3, #0]
 800729c:	4a71      	ldr	r2, [pc, #452]	@ (8007464 <HAL_DMA_IRQHandler+0xa20>)
 800729e:	4293      	cmp	r3, r2
 80072a0:	d02c      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 80072a2:	687b      	ldr	r3, [r7, #4]
 80072a4:	681b      	ldr	r3, [r3, #0]
 80072a6:	4a70      	ldr	r2, [pc, #448]	@ (8007468 <HAL_DMA_IRQHandler+0xa24>)
 80072a8:	4293      	cmp	r3, r2
 80072aa:	d027      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 80072ac:	687b      	ldr	r3, [r7, #4]
 80072ae:	681b      	ldr	r3, [r3, #0]
 80072b0:	4a6e      	ldr	r2, [pc, #440]	@ (800746c <HAL_DMA_IRQHandler+0xa28>)
 80072b2:	4293      	cmp	r3, r2
 80072b4:	d022      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 80072b6:	687b      	ldr	r3, [r7, #4]
 80072b8:	681b      	ldr	r3, [r3, #0]
 80072ba:	4a6d      	ldr	r2, [pc, #436]	@ (8007470 <HAL_DMA_IRQHandler+0xa2c>)
 80072bc:	4293      	cmp	r3, r2
 80072be:	d01d      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 80072c0:	687b      	ldr	r3, [r7, #4]
 80072c2:	681b      	ldr	r3, [r3, #0]
 80072c4:	4a6b      	ldr	r2, [pc, #428]	@ (8007474 <HAL_DMA_IRQHandler+0xa30>)
 80072c6:	4293      	cmp	r3, r2
 80072c8:	d018      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 80072ca:	687b      	ldr	r3, [r7, #4]
 80072cc:	681b      	ldr	r3, [r3, #0]
 80072ce:	4a6a      	ldr	r2, [pc, #424]	@ (8007478 <HAL_DMA_IRQHandler+0xa34>)
 80072d0:	4293      	cmp	r3, r2
 80072d2:	d013      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 80072d4:	687b      	ldr	r3, [r7, #4]
 80072d6:	681b      	ldr	r3, [r3, #0]
 80072d8:	4a68      	ldr	r2, [pc, #416]	@ (800747c <HAL_DMA_IRQHandler+0xa38>)
 80072da:	4293      	cmp	r3, r2
 80072dc:	d00e      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 80072de:	687b      	ldr	r3, [r7, #4]
 80072e0:	681b      	ldr	r3, [r3, #0]
 80072e2:	4a67      	ldr	r2, [pc, #412]	@ (8007480 <HAL_DMA_IRQHandler+0xa3c>)
 80072e4:	4293      	cmp	r3, r2
 80072e6:	d009      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 80072e8:	687b      	ldr	r3, [r7, #4]
 80072ea:	681b      	ldr	r3, [r3, #0]
 80072ec:	4a65      	ldr	r2, [pc, #404]	@ (8007484 <HAL_DMA_IRQHandler+0xa40>)
 80072ee:	4293      	cmp	r3, r2
 80072f0:	d004      	beq.n	80072fc <HAL_DMA_IRQHandler+0x8b8>
 80072f2:	687b      	ldr	r3, [r7, #4]
 80072f4:	681b      	ldr	r3, [r3, #0]
 80072f6:	4a64      	ldr	r2, [pc, #400]	@ (8007488 <HAL_DMA_IRQHandler+0xa44>)
 80072f8:	4293      	cmp	r3, r2
 80072fa:	d108      	bne.n	800730e <HAL_DMA_IRQHandler+0x8ca>
 80072fc:	687b      	ldr	r3, [r7, #4]
 80072fe:	681b      	ldr	r3, [r3, #0]
 8007300:	681a      	ldr	r2, [r3, #0]
 8007302:	687b      	ldr	r3, [r7, #4]
 8007304:	681b      	ldr	r3, [r3, #0]
 8007306:	f022 0201 	bic.w	r2, r2, #1
 800730a:	601a      	str	r2, [r3, #0]
 800730c:	e007      	b.n	800731e <HAL_DMA_IRQHandler+0x8da>
 800730e:	687b      	ldr	r3, [r7, #4]
 8007310:	681b      	ldr	r3, [r3, #0]
 8007312:	681a      	ldr	r2, [r3, #0]
 8007314:	687b      	ldr	r3, [r7, #4]
 8007316:	681b      	ldr	r3, [r3, #0]
 8007318:	f022 0201 	bic.w	r2, r2, #1
 800731c:	601a      	str	r2, [r3, #0]

        do
        {
          if (++count > timeout)
 800731e:	68fb      	ldr	r3, [r7, #12]
 8007320:	3301      	adds	r3, #1
 8007322:	60fb      	str	r3, [r7, #12]
 8007324:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8007326:	429a      	cmp	r2, r3
 8007328:	d307      	bcc.n	800733a <HAL_DMA_IRQHandler+0x8f6>
          {
            break;
          }
        }
        while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
 800732a:	687b      	ldr	r3, [r7, #4]
 800732c:	681b      	ldr	r3, [r3, #0]
 800732e:	681b      	ldr	r3, [r3, #0]
 8007330:	f003 0301 	and.w	r3, r3, #1
 8007334:	2b00      	cmp	r3, #0
 8007336:	d1f2      	bne.n	800731e <HAL_DMA_IRQHandler+0x8da>
 8007338:	e000      	b.n	800733c <HAL_DMA_IRQHandler+0x8f8>
            break;
 800733a:	bf00      	nop

        if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
 800733c:	687b      	ldr	r3, [r7, #4]
 800733e:	681b      	ldr	r3, [r3, #0]
 8007340:	681b      	ldr	r3, [r3, #0]
 8007342:	f003 0301 	and.w	r3, r3, #1
 8007346:	2b00      	cmp	r3, #0
 8007348:	d004      	beq.n	8007354 <HAL_DMA_IRQHandler+0x910>
        {
          /* Change the DMA state to error if DMA disable fails */
          hdma->State = HAL_DMA_STATE_ERROR;
 800734a:	687b      	ldr	r3, [r7, #4]
 800734c:	2203      	movs	r2, #3
 800734e:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
 8007352:	e003      	b.n	800735c <HAL_DMA_IRQHandler+0x918>
        }
        else
        {
          /* Change the DMA state to Ready if DMA disable success */
          hdma->State = HAL_DMA_STATE_READY;
 8007354:	687b      	ldr	r3, [r7, #4]
 8007356:	2201      	movs	r2, #1
 8007358:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
        }

        /* Process Unlocked */
        __HAL_UNLOCK(hdma);
 800735c:	687b      	ldr	r3, [r7, #4]
 800735e:	2200      	movs	r2, #0
 8007360:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
      }

      if(hdma->XferErrorCallback != NULL)
 8007364:	687b      	ldr	r3, [r7, #4]
 8007366:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8007368:	2b00      	cmp	r3, #0
 800736a:	f000 8272 	beq.w	8007852 <HAL_DMA_IRQHandler+0xe0e>
      {
        /* Transfer error callback */
        hdma->XferErrorCallback(hdma);
 800736e:	687b      	ldr	r3, [r7, #4]
 8007370:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8007372:	6878      	ldr	r0, [r7, #4]
 8007374:	4798      	blx	r3
 8007376:	e26c      	b.n	8007852 <HAL_DMA_IRQHandler+0xe0e>
      }
    }
  }
  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U)  /* BDMA instance(s) */
 8007378:	687b      	ldr	r3, [r7, #4]
 800737a:	681b      	ldr	r3, [r3, #0]
 800737c:	4a43      	ldr	r2, [pc, #268]	@ (800748c <HAL_DMA_IRQHandler+0xa48>)
 800737e:	4293      	cmp	r3, r2
 8007380:	d022      	beq.n	80073c8 <HAL_DMA_IRQHandler+0x984>
 8007382:	687b      	ldr	r3, [r7, #4]
 8007384:	681b      	ldr	r3, [r3, #0]
 8007386:	4a42      	ldr	r2, [pc, #264]	@ (8007490 <HAL_DMA_IRQHandler+0xa4c>)
 8007388:	4293      	cmp	r3, r2
 800738a:	d01d      	beq.n	80073c8 <HAL_DMA_IRQHandler+0x984>
 800738c:	687b      	ldr	r3, [r7, #4]
 800738e:	681b      	ldr	r3, [r3, #0]
 8007390:	4a40      	ldr	r2, [pc, #256]	@ (8007494 <HAL_DMA_IRQHandler+0xa50>)
 8007392:	4293      	cmp	r3, r2
 8007394:	d018      	beq.n	80073c8 <HAL_DMA_IRQHandler+0x984>
 8007396:	687b      	ldr	r3, [r7, #4]
 8007398:	681b      	ldr	r3, [r3, #0]
 800739a:	4a3f      	ldr	r2, [pc, #252]	@ (8007498 <HAL_DMA_IRQHandler+0xa54>)
 800739c:	4293      	cmp	r3, r2
 800739e:	d013      	beq.n	80073c8 <HAL_DMA_IRQHandler+0x984>
 80073a0:	687b      	ldr	r3, [r7, #4]
 80073a2:	681b      	ldr	r3, [r3, #0]
 80073a4:	4a3d      	ldr	r2, [pc, #244]	@ (800749c <HAL_DMA_IRQHandler+0xa58>)
 80073a6:	4293      	cmp	r3, r2
 80073a8:	d00e      	beq.n	80073c8 <HAL_DMA_IRQHandler+0x984>
 80073aa:	687b      	ldr	r3, [r7, #4]
 80073ac:	681b      	ldr	r3, [r3, #0]
 80073ae:	4a3c      	ldr	r2, [pc, #240]	@ (80074a0 <HAL_DMA_IRQHandler+0xa5c>)
 80073b0:	4293      	cmp	r3, r2
 80073b2:	d009      	beq.n	80073c8 <HAL_DMA_IRQHandler+0x984>
 80073b4:	687b      	ldr	r3, [r7, #4]
 80073b6:	681b      	ldr	r3, [r3, #0]
 80073b8:	4a3a      	ldr	r2, [pc, #232]	@ (80074a4 <HAL_DMA_IRQHandler+0xa60>)
 80073ba:	4293      	cmp	r3, r2
 80073bc:	d004      	beq.n	80073c8 <HAL_DMA_IRQHandler+0x984>
 80073be:	687b      	ldr	r3, [r7, #4]
 80073c0:	681b      	ldr	r3, [r3, #0]
 80073c2:	4a39      	ldr	r2, [pc, #228]	@ (80074a8 <HAL_DMA_IRQHandler+0xa64>)
 80073c4:	4293      	cmp	r3, r2
 80073c6:	d101      	bne.n	80073cc <HAL_DMA_IRQHandler+0x988>
 80073c8:	2301      	movs	r3, #1
 80073ca:	e000      	b.n	80073ce <HAL_DMA_IRQHandler+0x98a>
 80073cc:	2300      	movs	r3, #0
 80073ce:	2b00      	cmp	r3, #0
 80073d0:	f000 823f 	beq.w	8007852 <HAL_DMA_IRQHandler+0xe0e>
  {
    ccr_reg = (((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR);
 80073d4:	687b      	ldr	r3, [r7, #4]
 80073d6:	681b      	ldr	r3, [r3, #0]
 80073d8:	681b      	ldr	r3, [r3, #0]
 80073da:	613b      	str	r3, [r7, #16]

    /* Half Transfer Complete Interrupt management ******************************/
    if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U))
 80073dc:	687b      	ldr	r3, [r7, #4]
 80073de:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80073e0:	f003 031f 	and.w	r3, r3, #31
 80073e4:	2204      	movs	r2, #4
 80073e6:	409a      	lsls	r2, r3
 80073e8:	697b      	ldr	r3, [r7, #20]
 80073ea:	4013      	ands	r3, r2
 80073ec:	2b00      	cmp	r3, #0
 80073ee:	f000 80cd 	beq.w	800758c <HAL_DMA_IRQHandler+0xb48>
 80073f2:	693b      	ldr	r3, [r7, #16]
 80073f4:	f003 0304 	and.w	r3, r3, #4
 80073f8:	2b00      	cmp	r3, #0
 80073fa:	f000 80c7 	beq.w	800758c <HAL_DMA_IRQHandler+0xb48>
    {
      /* Clear the half transfer complete flag */
      regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU));
 80073fe:	687b      	ldr	r3, [r7, #4]
 8007400:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8007402:	f003 031f 	and.w	r3, r3, #31
 8007406:	2204      	movs	r2, #4
 8007408:	409a      	lsls	r2, r3
 800740a:	69fb      	ldr	r3, [r7, #28]
 800740c:	605a      	str	r2, [r3, #4]

      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 800740e:	693b      	ldr	r3, [r7, #16]
 8007410:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 8007414:	2b00      	cmp	r3, #0
 8007416:	d049      	beq.n	80074ac <HAL_DMA_IRQHandler+0xa68>
      {
        /* Current memory buffer used is Memory 0 */
        if((ccr_reg & BDMA_CCR_CT) == 0U)
 8007418:	693b      	ldr	r3, [r7, #16]
 800741a:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 800741e:	2b00      	cmp	r3, #0
 8007420:	d109      	bne.n	8007436 <HAL_DMA_IRQHandler+0x9f2>
        {
          if(hdma->XferM1HalfCpltCallback != NULL)
 8007422:	687b      	ldr	r3, [r7, #4]
 8007424:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8007426:	2b00      	cmp	r3, #0
 8007428:	f000 8210 	beq.w	800784c <HAL_DMA_IRQHandler+0xe08>
          {
            /* Half transfer Callback for Memory 1 */
            hdma->XferM1HalfCpltCallback(hdma);
 800742c:	687b      	ldr	r3, [r7, #4]
 800742e:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8007430:	6878      	ldr	r0, [r7, #4]
 8007432:	4798      	blx	r3
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8007434:	e20a      	b.n	800784c <HAL_DMA_IRQHandler+0xe08>
          }
        }
        /* Current memory buffer used is Memory 1 */
        else
        {
          if(hdma->XferHalfCpltCallback != NULL)
 8007436:	687b      	ldr	r3, [r7, #4]
 8007438:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800743a:	2b00      	cmp	r3, #0
 800743c:	f000 8206 	beq.w	800784c <HAL_DMA_IRQHandler+0xe08>
          {
            /* Half transfer Callback for Memory 0 */
            hdma->XferHalfCpltCallback(hdma);
 8007440:	687b      	ldr	r3, [r7, #4]
 8007442:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8007444:	6878      	ldr	r0, [r7, #4]
 8007446:	4798      	blx	r3
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8007448:	e200      	b.n	800784c <HAL_DMA_IRQHandler+0xe08>
 800744a:	bf00      	nop
 800744c:	40020010 	.word	0x40020010
 8007450:	40020028 	.word	0x40020028
 8007454:	40020040 	.word	0x40020040
 8007458:	40020058 	.word	0x40020058
 800745c:	40020070 	.word	0x40020070
 8007460:	40020088 	.word	0x40020088
 8007464:	400200a0 	.word	0x400200a0
 8007468:	400200b8 	.word	0x400200b8
 800746c:	40020410 	.word	0x40020410
 8007470:	40020428 	.word	0x40020428
 8007474:	40020440 	.word	0x40020440
 8007478:	40020458 	.word	0x40020458
 800747c:	40020470 	.word	0x40020470
 8007480:	40020488 	.word	0x40020488
 8007484:	400204a0 	.word	0x400204a0
 8007488:	400204b8 	.word	0x400204b8
 800748c:	58025408 	.word	0x58025408
 8007490:	5802541c 	.word	0x5802541c
 8007494:	58025430 	.word	0x58025430
 8007498:	58025444 	.word	0x58025444
 800749c:	58025458 	.word	0x58025458
 80074a0:	5802546c 	.word	0x5802546c
 80074a4:	58025480 	.word	0x58025480
 80074a8:	58025494 	.word	0x58025494
          }
        }
      }
      else
      {
        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
 80074ac:	693b      	ldr	r3, [r7, #16]
 80074ae:	f003 0320 	and.w	r3, r3, #32
 80074b2:	2b00      	cmp	r3, #0
 80074b4:	d160      	bne.n	8007578 <HAL_DMA_IRQHandler+0xb34>
        {
          /* Disable the half transfer interrupt */
          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 80074b6:	687b      	ldr	r3, [r7, #4]
 80074b8:	681b      	ldr	r3, [r3, #0]
 80074ba:	4a7f      	ldr	r2, [pc, #508]	@ (80076b8 <HAL_DMA_IRQHandler+0xc74>)
 80074bc:	4293      	cmp	r3, r2
 80074be:	d04a      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 80074c0:	687b      	ldr	r3, [r7, #4]
 80074c2:	681b      	ldr	r3, [r3, #0]
 80074c4:	4a7d      	ldr	r2, [pc, #500]	@ (80076bc <HAL_DMA_IRQHandler+0xc78>)
 80074c6:	4293      	cmp	r3, r2
 80074c8:	d045      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 80074ca:	687b      	ldr	r3, [r7, #4]
 80074cc:	681b      	ldr	r3, [r3, #0]
 80074ce:	4a7c      	ldr	r2, [pc, #496]	@ (80076c0 <HAL_DMA_IRQHandler+0xc7c>)
 80074d0:	4293      	cmp	r3, r2
 80074d2:	d040      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 80074d4:	687b      	ldr	r3, [r7, #4]
 80074d6:	681b      	ldr	r3, [r3, #0]
 80074d8:	4a7a      	ldr	r2, [pc, #488]	@ (80076c4 <HAL_DMA_IRQHandler+0xc80>)
 80074da:	4293      	cmp	r3, r2
 80074dc:	d03b      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 80074de:	687b      	ldr	r3, [r7, #4]
 80074e0:	681b      	ldr	r3, [r3, #0]
 80074e2:	4a79      	ldr	r2, [pc, #484]	@ (80076c8 <HAL_DMA_IRQHandler+0xc84>)
 80074e4:	4293      	cmp	r3, r2
 80074e6:	d036      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 80074e8:	687b      	ldr	r3, [r7, #4]
 80074ea:	681b      	ldr	r3, [r3, #0]
 80074ec:	4a77      	ldr	r2, [pc, #476]	@ (80076cc <HAL_DMA_IRQHandler+0xc88>)
 80074ee:	4293      	cmp	r3, r2
 80074f0:	d031      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 80074f2:	687b      	ldr	r3, [r7, #4]
 80074f4:	681b      	ldr	r3, [r3, #0]
 80074f6:	4a76      	ldr	r2, [pc, #472]	@ (80076d0 <HAL_DMA_IRQHandler+0xc8c>)
 80074f8:	4293      	cmp	r3, r2
 80074fa:	d02c      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 80074fc:	687b      	ldr	r3, [r7, #4]
 80074fe:	681b      	ldr	r3, [r3, #0]
 8007500:	4a74      	ldr	r2, [pc, #464]	@ (80076d4 <HAL_DMA_IRQHandler+0xc90>)
 8007502:	4293      	cmp	r3, r2
 8007504:	d027      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 8007506:	687b      	ldr	r3, [r7, #4]
 8007508:	681b      	ldr	r3, [r3, #0]
 800750a:	4a73      	ldr	r2, [pc, #460]	@ (80076d8 <HAL_DMA_IRQHandler+0xc94>)
 800750c:	4293      	cmp	r3, r2
 800750e:	d022      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 8007510:	687b      	ldr	r3, [r7, #4]
 8007512:	681b      	ldr	r3, [r3, #0]
 8007514:	4a71      	ldr	r2, [pc, #452]	@ (80076dc <HAL_DMA_IRQHandler+0xc98>)
 8007516:	4293      	cmp	r3, r2
 8007518:	d01d      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 800751a:	687b      	ldr	r3, [r7, #4]
 800751c:	681b      	ldr	r3, [r3, #0]
 800751e:	4a70      	ldr	r2, [pc, #448]	@ (80076e0 <HAL_DMA_IRQHandler+0xc9c>)
 8007520:	4293      	cmp	r3, r2
 8007522:	d018      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 8007524:	687b      	ldr	r3, [r7, #4]
 8007526:	681b      	ldr	r3, [r3, #0]
 8007528:	4a6e      	ldr	r2, [pc, #440]	@ (80076e4 <HAL_DMA_IRQHandler+0xca0>)
 800752a:	4293      	cmp	r3, r2
 800752c:	d013      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 800752e:	687b      	ldr	r3, [r7, #4]
 8007530:	681b      	ldr	r3, [r3, #0]
 8007532:	4a6d      	ldr	r2, [pc, #436]	@ (80076e8 <HAL_DMA_IRQHandler+0xca4>)
 8007534:	4293      	cmp	r3, r2
 8007536:	d00e      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 8007538:	687b      	ldr	r3, [r7, #4]
 800753a:	681b      	ldr	r3, [r3, #0]
 800753c:	4a6b      	ldr	r2, [pc, #428]	@ (80076ec <HAL_DMA_IRQHandler+0xca8>)
 800753e:	4293      	cmp	r3, r2
 8007540:	d009      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 8007542:	687b      	ldr	r3, [r7, #4]
 8007544:	681b      	ldr	r3, [r3, #0]
 8007546:	4a6a      	ldr	r2, [pc, #424]	@ (80076f0 <HAL_DMA_IRQHandler+0xcac>)
 8007548:	4293      	cmp	r3, r2
 800754a:	d004      	beq.n	8007556 <HAL_DMA_IRQHandler+0xb12>
 800754c:	687b      	ldr	r3, [r7, #4]
 800754e:	681b      	ldr	r3, [r3, #0]
 8007550:	4a68      	ldr	r2, [pc, #416]	@ (80076f4 <HAL_DMA_IRQHandler+0xcb0>)
 8007552:	4293      	cmp	r3, r2
 8007554:	d108      	bne.n	8007568 <HAL_DMA_IRQHandler+0xb24>
 8007556:	687b      	ldr	r3, [r7, #4]
 8007558:	681b      	ldr	r3, [r3, #0]
 800755a:	681a      	ldr	r2, [r3, #0]
 800755c:	687b      	ldr	r3, [r7, #4]
 800755e:	681b      	ldr	r3, [r3, #0]
 8007560:	f022 0208 	bic.w	r2, r2, #8
 8007564:	601a      	str	r2, [r3, #0]
 8007566:	e007      	b.n	8007578 <HAL_DMA_IRQHandler+0xb34>
 8007568:	687b      	ldr	r3, [r7, #4]
 800756a:	681b      	ldr	r3, [r3, #0]
 800756c:	681a      	ldr	r2, [r3, #0]
 800756e:	687b      	ldr	r3, [r7, #4]
 8007570:	681b      	ldr	r3, [r3, #0]
 8007572:	f022 0204 	bic.w	r2, r2, #4
 8007576:	601a      	str	r2, [r3, #0]
        }

        /* DMA peripheral state is not updated in Half Transfer */
        /* but in Transfer Complete case */

       if(hdma->XferHalfCpltCallback != NULL)
 8007578:	687b      	ldr	r3, [r7, #4]
 800757a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800757c:	2b00      	cmp	r3, #0
 800757e:	f000 8165 	beq.w	800784c <HAL_DMA_IRQHandler+0xe08>
        {
          /* Half transfer callback */
          hdma->XferHalfCpltCallback(hdma);
 8007582:	687b      	ldr	r3, [r7, #4]
 8007584:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8007586:	6878      	ldr	r0, [r7, #4]
 8007588:	4798      	blx	r3
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 800758a:	e15f      	b.n	800784c <HAL_DMA_IRQHandler+0xe08>
        }
      }
    }

    /* Transfer Complete Interrupt management ***********************************/
    else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U))
 800758c:	687b      	ldr	r3, [r7, #4]
 800758e:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8007590:	f003 031f 	and.w	r3, r3, #31
 8007594:	2202      	movs	r2, #2
 8007596:	409a      	lsls	r2, r3
 8007598:	697b      	ldr	r3, [r7, #20]
 800759a:	4013      	ands	r3, r2
 800759c:	2b00      	cmp	r3, #0
 800759e:	f000 80c5 	beq.w	800772c <HAL_DMA_IRQHandler+0xce8>
 80075a2:	693b      	ldr	r3, [r7, #16]
 80075a4:	f003 0302 	and.w	r3, r3, #2
 80075a8:	2b00      	cmp	r3, #0
 80075aa:	f000 80bf 	beq.w	800772c <HAL_DMA_IRQHandler+0xce8>
    {
      /* Clear the transfer complete flag */
      regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU);
 80075ae:	687b      	ldr	r3, [r7, #4]
 80075b0:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80075b2:	f003 031f 	and.w	r3, r3, #31
 80075b6:	2202      	movs	r2, #2
 80075b8:	409a      	lsls	r2, r3
 80075ba:	69fb      	ldr	r3, [r7, #28]
 80075bc:	605a      	str	r2, [r3, #4]

      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 80075be:	693b      	ldr	r3, [r7, #16]
 80075c0:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 80075c4:	2b00      	cmp	r3, #0
 80075c6:	d018      	beq.n	80075fa <HAL_DMA_IRQHandler+0xbb6>
      {
        /* Current memory buffer used is Memory 0 */
        if((ccr_reg & BDMA_CCR_CT) == 0U)
 80075c8:	693b      	ldr	r3, [r7, #16]
 80075ca:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 80075ce:	2b00      	cmp	r3, #0
 80075d0:	d109      	bne.n	80075e6 <HAL_DMA_IRQHandler+0xba2>
        {
          if(hdma->XferM1CpltCallback != NULL)
 80075d2:	687b      	ldr	r3, [r7, #4]
 80075d4:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 80075d6:	2b00      	cmp	r3, #0
 80075d8:	f000 813a 	beq.w	8007850 <HAL_DMA_IRQHandler+0xe0c>
          {
            /* Transfer complete Callback for Memory 1 */
            hdma->XferM1CpltCallback(hdma);
 80075dc:	687b      	ldr	r3, [r7, #4]
 80075de:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 80075e0:	6878      	ldr	r0, [r7, #4]
 80075e2:	4798      	blx	r3
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 80075e4:	e134      	b.n	8007850 <HAL_DMA_IRQHandler+0xe0c>
          }
        }
        /* Current memory buffer used is Memory 1 */
        else
        {
          if(hdma->XferCpltCallback != NULL)
 80075e6:	687b      	ldr	r3, [r7, #4]
 80075e8:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80075ea:	2b00      	cmp	r3, #0
 80075ec:	f000 8130 	beq.w	8007850 <HAL_DMA_IRQHandler+0xe0c>
          {
            /* Transfer complete Callback for Memory 0 */
            hdma->XferCpltCallback(hdma);
 80075f0:	687b      	ldr	r3, [r7, #4]
 80075f2:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80075f4:	6878      	ldr	r0, [r7, #4]
 80075f6:	4798      	blx	r3
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 80075f8:	e12a      	b.n	8007850 <HAL_DMA_IRQHandler+0xe0c>
          }
        }
      }
      else
      {
        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
 80075fa:	693b      	ldr	r3, [r7, #16]
 80075fc:	f003 0320 	and.w	r3, r3, #32
 8007600:	2b00      	cmp	r3, #0
 8007602:	f040 8089 	bne.w	8007718 <HAL_DMA_IRQHandler+0xcd4>
        {
          /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */
          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
 8007606:	687b      	ldr	r3, [r7, #4]
 8007608:	681b      	ldr	r3, [r3, #0]
 800760a:	4a2b      	ldr	r2, [pc, #172]	@ (80076b8 <HAL_DMA_IRQHandler+0xc74>)
 800760c:	4293      	cmp	r3, r2
 800760e:	d04a      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 8007610:	687b      	ldr	r3, [r7, #4]
 8007612:	681b      	ldr	r3, [r3, #0]
 8007614:	4a29      	ldr	r2, [pc, #164]	@ (80076bc <HAL_DMA_IRQHandler+0xc78>)
 8007616:	4293      	cmp	r3, r2
 8007618:	d045      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 800761a:	687b      	ldr	r3, [r7, #4]
 800761c:	681b      	ldr	r3, [r3, #0]
 800761e:	4a28      	ldr	r2, [pc, #160]	@ (80076c0 <HAL_DMA_IRQHandler+0xc7c>)
 8007620:	4293      	cmp	r3, r2
 8007622:	d040      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 8007624:	687b      	ldr	r3, [r7, #4]
 8007626:	681b      	ldr	r3, [r3, #0]
 8007628:	4a26      	ldr	r2, [pc, #152]	@ (80076c4 <HAL_DMA_IRQHandler+0xc80>)
 800762a:	4293      	cmp	r3, r2
 800762c:	d03b      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 800762e:	687b      	ldr	r3, [r7, #4]
 8007630:	681b      	ldr	r3, [r3, #0]
 8007632:	4a25      	ldr	r2, [pc, #148]	@ (80076c8 <HAL_DMA_IRQHandler+0xc84>)
 8007634:	4293      	cmp	r3, r2
 8007636:	d036      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 8007638:	687b      	ldr	r3, [r7, #4]
 800763a:	681b      	ldr	r3, [r3, #0]
 800763c:	4a23      	ldr	r2, [pc, #140]	@ (80076cc <HAL_DMA_IRQHandler+0xc88>)
 800763e:	4293      	cmp	r3, r2
 8007640:	d031      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 8007642:	687b      	ldr	r3, [r7, #4]
 8007644:	681b      	ldr	r3, [r3, #0]
 8007646:	4a22      	ldr	r2, [pc, #136]	@ (80076d0 <HAL_DMA_IRQHandler+0xc8c>)
 8007648:	4293      	cmp	r3, r2
 800764a:	d02c      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 800764c:	687b      	ldr	r3, [r7, #4]
 800764e:	681b      	ldr	r3, [r3, #0]
 8007650:	4a20      	ldr	r2, [pc, #128]	@ (80076d4 <HAL_DMA_IRQHandler+0xc90>)
 8007652:	4293      	cmp	r3, r2
 8007654:	d027      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 8007656:	687b      	ldr	r3, [r7, #4]
 8007658:	681b      	ldr	r3, [r3, #0]
 800765a:	4a1f      	ldr	r2, [pc, #124]	@ (80076d8 <HAL_DMA_IRQHandler+0xc94>)
 800765c:	4293      	cmp	r3, r2
 800765e:	d022      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 8007660:	687b      	ldr	r3, [r7, #4]
 8007662:	681b      	ldr	r3, [r3, #0]
 8007664:	4a1d      	ldr	r2, [pc, #116]	@ (80076dc <HAL_DMA_IRQHandler+0xc98>)
 8007666:	4293      	cmp	r3, r2
 8007668:	d01d      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 800766a:	687b      	ldr	r3, [r7, #4]
 800766c:	681b      	ldr	r3, [r3, #0]
 800766e:	4a1c      	ldr	r2, [pc, #112]	@ (80076e0 <HAL_DMA_IRQHandler+0xc9c>)
 8007670:	4293      	cmp	r3, r2
 8007672:	d018      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 8007674:	687b      	ldr	r3, [r7, #4]
 8007676:	681b      	ldr	r3, [r3, #0]
 8007678:	4a1a      	ldr	r2, [pc, #104]	@ (80076e4 <HAL_DMA_IRQHandler+0xca0>)
 800767a:	4293      	cmp	r3, r2
 800767c:	d013      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 800767e:	687b      	ldr	r3, [r7, #4]
 8007680:	681b      	ldr	r3, [r3, #0]
 8007682:	4a19      	ldr	r2, [pc, #100]	@ (80076e8 <HAL_DMA_IRQHandler+0xca4>)
 8007684:	4293      	cmp	r3, r2
 8007686:	d00e      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 8007688:	687b      	ldr	r3, [r7, #4]
 800768a:	681b      	ldr	r3, [r3, #0]
 800768c:	4a17      	ldr	r2, [pc, #92]	@ (80076ec <HAL_DMA_IRQHandler+0xca8>)
 800768e:	4293      	cmp	r3, r2
 8007690:	d009      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 8007692:	687b      	ldr	r3, [r7, #4]
 8007694:	681b      	ldr	r3, [r3, #0]
 8007696:	4a16      	ldr	r2, [pc, #88]	@ (80076f0 <HAL_DMA_IRQHandler+0xcac>)
 8007698:	4293      	cmp	r3, r2
 800769a:	d004      	beq.n	80076a6 <HAL_DMA_IRQHandler+0xc62>
 800769c:	687b      	ldr	r3, [r7, #4]
 800769e:	681b      	ldr	r3, [r3, #0]
 80076a0:	4a14      	ldr	r2, [pc, #80]	@ (80076f4 <HAL_DMA_IRQHandler+0xcb0>)
 80076a2:	4293      	cmp	r3, r2
 80076a4:	d128      	bne.n	80076f8 <HAL_DMA_IRQHandler+0xcb4>
 80076a6:	687b      	ldr	r3, [r7, #4]
 80076a8:	681b      	ldr	r3, [r3, #0]
 80076aa:	681a      	ldr	r2, [r3, #0]
 80076ac:	687b      	ldr	r3, [r7, #4]
 80076ae:	681b      	ldr	r3, [r3, #0]
 80076b0:	f022 0214 	bic.w	r2, r2, #20
 80076b4:	601a      	str	r2, [r3, #0]
 80076b6:	e027      	b.n	8007708 <HAL_DMA_IRQHandler+0xcc4>
 80076b8:	40020010 	.word	0x40020010
 80076bc:	40020028 	.word	0x40020028
 80076c0:	40020040 	.word	0x40020040
 80076c4:	40020058 	.word	0x40020058
 80076c8:	40020070 	.word	0x40020070
 80076cc:	40020088 	.word	0x40020088
 80076d0:	400200a0 	.word	0x400200a0
 80076d4:	400200b8 	.word	0x400200b8
 80076d8:	40020410 	.word	0x40020410
 80076dc:	40020428 	.word	0x40020428
 80076e0:	40020440 	.word	0x40020440
 80076e4:	40020458 	.word	0x40020458
 80076e8:	40020470 	.word	0x40020470
 80076ec:	40020488 	.word	0x40020488
 80076f0:	400204a0 	.word	0x400204a0
 80076f4:	400204b8 	.word	0x400204b8
 80076f8:	687b      	ldr	r3, [r7, #4]
 80076fa:	681b      	ldr	r3, [r3, #0]
 80076fc:	681a      	ldr	r2, [r3, #0]
 80076fe:	687b      	ldr	r3, [r7, #4]
 8007700:	681b      	ldr	r3, [r3, #0]
 8007702:	f022 020a 	bic.w	r2, r2, #10
 8007706:	601a      	str	r2, [r3, #0]

          /* Change the DMA state */
          hdma->State = HAL_DMA_STATE_READY;
 8007708:	687b      	ldr	r3, [r7, #4]
 800770a:	2201      	movs	r2, #1
 800770c:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

          /* Process Unlocked */
          __HAL_UNLOCK(hdma);
 8007710:	687b      	ldr	r3, [r7, #4]
 8007712:	2200      	movs	r2, #0
 8007714:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
        }

        if(hdma->XferCpltCallback != NULL)
 8007718:	687b      	ldr	r3, [r7, #4]
 800771a:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 800771c:	2b00      	cmp	r3, #0
 800771e:	f000 8097 	beq.w	8007850 <HAL_DMA_IRQHandler+0xe0c>
        {
          /* Transfer complete callback */
          hdma->XferCpltCallback(hdma);
 8007722:	687b      	ldr	r3, [r7, #4]
 8007724:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8007726:	6878      	ldr	r0, [r7, #4]
 8007728:	4798      	blx	r3
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 800772a:	e091      	b.n	8007850 <HAL_DMA_IRQHandler+0xe0c>
        }
      }
    }
    /* Transfer Error Interrupt management **************************************/
    else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))
 800772c:	687b      	ldr	r3, [r7, #4]
 800772e:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8007730:	f003 031f 	and.w	r3, r3, #31
 8007734:	2208      	movs	r2, #8
 8007736:	409a      	lsls	r2, r3
 8007738:	697b      	ldr	r3, [r7, #20]
 800773a:	4013      	ands	r3, r2
 800773c:	2b00      	cmp	r3, #0
 800773e:	f000 8088 	beq.w	8007852 <HAL_DMA_IRQHandler+0xe0e>
 8007742:	693b      	ldr	r3, [r7, #16]
 8007744:	f003 0308 	and.w	r3, r3, #8
 8007748:	2b00      	cmp	r3, #0
 800774a:	f000 8082 	beq.w	8007852 <HAL_DMA_IRQHandler+0xe0e>
    {
      /* When a DMA transfer error occurs */
      /* A hardware clear of its EN bits is performed */
      /* Disable ALL DMA IT */
      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 800774e:	687b      	ldr	r3, [r7, #4]
 8007750:	681b      	ldr	r3, [r3, #0]
 8007752:	4a41      	ldr	r2, [pc, #260]	@ (8007858 <HAL_DMA_IRQHandler+0xe14>)
 8007754:	4293      	cmp	r3, r2
 8007756:	d04a      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 8007758:	687b      	ldr	r3, [r7, #4]
 800775a:	681b      	ldr	r3, [r3, #0]
 800775c:	4a3f      	ldr	r2, [pc, #252]	@ (800785c <HAL_DMA_IRQHandler+0xe18>)
 800775e:	4293      	cmp	r3, r2
 8007760:	d045      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 8007762:	687b      	ldr	r3, [r7, #4]
 8007764:	681b      	ldr	r3, [r3, #0]
 8007766:	4a3e      	ldr	r2, [pc, #248]	@ (8007860 <HAL_DMA_IRQHandler+0xe1c>)
 8007768:	4293      	cmp	r3, r2
 800776a:	d040      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 800776c:	687b      	ldr	r3, [r7, #4]
 800776e:	681b      	ldr	r3, [r3, #0]
 8007770:	4a3c      	ldr	r2, [pc, #240]	@ (8007864 <HAL_DMA_IRQHandler+0xe20>)
 8007772:	4293      	cmp	r3, r2
 8007774:	d03b      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 8007776:	687b      	ldr	r3, [r7, #4]
 8007778:	681b      	ldr	r3, [r3, #0]
 800777a:	4a3b      	ldr	r2, [pc, #236]	@ (8007868 <HAL_DMA_IRQHandler+0xe24>)
 800777c:	4293      	cmp	r3, r2
 800777e:	d036      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 8007780:	687b      	ldr	r3, [r7, #4]
 8007782:	681b      	ldr	r3, [r3, #0]
 8007784:	4a39      	ldr	r2, [pc, #228]	@ (800786c <HAL_DMA_IRQHandler+0xe28>)
 8007786:	4293      	cmp	r3, r2
 8007788:	d031      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 800778a:	687b      	ldr	r3, [r7, #4]
 800778c:	681b      	ldr	r3, [r3, #0]
 800778e:	4a38      	ldr	r2, [pc, #224]	@ (8007870 <HAL_DMA_IRQHandler+0xe2c>)
 8007790:	4293      	cmp	r3, r2
 8007792:	d02c      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 8007794:	687b      	ldr	r3, [r7, #4]
 8007796:	681b      	ldr	r3, [r3, #0]
 8007798:	4a36      	ldr	r2, [pc, #216]	@ (8007874 <HAL_DMA_IRQHandler+0xe30>)
 800779a:	4293      	cmp	r3, r2
 800779c:	d027      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 800779e:	687b      	ldr	r3, [r7, #4]
 80077a0:	681b      	ldr	r3, [r3, #0]
 80077a2:	4a35      	ldr	r2, [pc, #212]	@ (8007878 <HAL_DMA_IRQHandler+0xe34>)
 80077a4:	4293      	cmp	r3, r2
 80077a6:	d022      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 80077a8:	687b      	ldr	r3, [r7, #4]
 80077aa:	681b      	ldr	r3, [r3, #0]
 80077ac:	4a33      	ldr	r2, [pc, #204]	@ (800787c <HAL_DMA_IRQHandler+0xe38>)
 80077ae:	4293      	cmp	r3, r2
 80077b0:	d01d      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 80077b2:	687b      	ldr	r3, [r7, #4]
 80077b4:	681b      	ldr	r3, [r3, #0]
 80077b6:	4a32      	ldr	r2, [pc, #200]	@ (8007880 <HAL_DMA_IRQHandler+0xe3c>)
 80077b8:	4293      	cmp	r3, r2
 80077ba:	d018      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 80077bc:	687b      	ldr	r3, [r7, #4]
 80077be:	681b      	ldr	r3, [r3, #0]
 80077c0:	4a30      	ldr	r2, [pc, #192]	@ (8007884 <HAL_DMA_IRQHandler+0xe40>)
 80077c2:	4293      	cmp	r3, r2
 80077c4:	d013      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 80077c6:	687b      	ldr	r3, [r7, #4]
 80077c8:	681b      	ldr	r3, [r3, #0]
 80077ca:	4a2f      	ldr	r2, [pc, #188]	@ (8007888 <HAL_DMA_IRQHandler+0xe44>)
 80077cc:	4293      	cmp	r3, r2
 80077ce:	d00e      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 80077d0:	687b      	ldr	r3, [r7, #4]
 80077d2:	681b      	ldr	r3, [r3, #0]
 80077d4:	4a2d      	ldr	r2, [pc, #180]	@ (800788c <HAL_DMA_IRQHandler+0xe48>)
 80077d6:	4293      	cmp	r3, r2
 80077d8:	d009      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 80077da:	687b      	ldr	r3, [r7, #4]
 80077dc:	681b      	ldr	r3, [r3, #0]
 80077de:	4a2c      	ldr	r2, [pc, #176]	@ (8007890 <HAL_DMA_IRQHandler+0xe4c>)
 80077e0:	4293      	cmp	r3, r2
 80077e2:	d004      	beq.n	80077ee <HAL_DMA_IRQHandler+0xdaa>
 80077e4:	687b      	ldr	r3, [r7, #4]
 80077e6:	681b      	ldr	r3, [r3, #0]
 80077e8:	4a2a      	ldr	r2, [pc, #168]	@ (8007894 <HAL_DMA_IRQHandler+0xe50>)
 80077ea:	4293      	cmp	r3, r2
 80077ec:	d108      	bne.n	8007800 <HAL_DMA_IRQHandler+0xdbc>
 80077ee:	687b      	ldr	r3, [r7, #4]
 80077f0:	681b      	ldr	r3, [r3, #0]
 80077f2:	681a      	ldr	r2, [r3, #0]
 80077f4:	687b      	ldr	r3, [r7, #4]
 80077f6:	681b      	ldr	r3, [r3, #0]
 80077f8:	f022 021c 	bic.w	r2, r2, #28
 80077fc:	601a      	str	r2, [r3, #0]
 80077fe:	e007      	b.n	8007810 <HAL_DMA_IRQHandler+0xdcc>
 8007800:	687b      	ldr	r3, [r7, #4]
 8007802:	681b      	ldr	r3, [r3, #0]
 8007804:	681a      	ldr	r2, [r3, #0]
 8007806:	687b      	ldr	r3, [r7, #4]
 8007808:	681b      	ldr	r3, [r3, #0]
 800780a:	f022 020e 	bic.w	r2, r2, #14
 800780e:	601a      	str	r2, [r3, #0]

      /* Clear all flags */
      regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
 8007810:	687b      	ldr	r3, [r7, #4]
 8007812:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8007814:	f003 031f 	and.w	r3, r3, #31
 8007818:	2201      	movs	r2, #1
 800781a:	409a      	lsls	r2, r3
 800781c:	69fb      	ldr	r3, [r7, #28]
 800781e:	605a      	str	r2, [r3, #4]

      /* Update error code */
      hdma->ErrorCode = HAL_DMA_ERROR_TE;
 8007820:	687b      	ldr	r3, [r7, #4]
 8007822:	2201      	movs	r2, #1
 8007824:	655a      	str	r2, [r3, #84]	@ 0x54

      /* Change the DMA state */
      hdma->State = HAL_DMA_STATE_READY;
 8007826:	687b      	ldr	r3, [r7, #4]
 8007828:	2201      	movs	r2, #1
 800782a:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

      /* Process Unlocked */
      __HAL_UNLOCK(hdma);
 800782e:	687b      	ldr	r3, [r7, #4]
 8007830:	2200      	movs	r2, #0
 8007832:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

      if (hdma->XferErrorCallback != NULL)
 8007836:	687b      	ldr	r3, [r7, #4]
 8007838:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800783a:	2b00      	cmp	r3, #0
 800783c:	d009      	beq.n	8007852 <HAL_DMA_IRQHandler+0xe0e>
      {
        /* Transfer error callback */
        hdma->XferErrorCallback(hdma);
 800783e:	687b      	ldr	r3, [r7, #4]
 8007840:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8007842:	6878      	ldr	r0, [r7, #4]
 8007844:	4798      	blx	r3
 8007846:	e004      	b.n	8007852 <HAL_DMA_IRQHandler+0xe0e>
          return;
 8007848:	bf00      	nop
 800784a:	e002      	b.n	8007852 <HAL_DMA_IRQHandler+0xe0e>
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 800784c:	bf00      	nop
 800784e:	e000      	b.n	8007852 <HAL_DMA_IRQHandler+0xe0e>
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8007850:	bf00      	nop
  }
  else
  {
    /* Nothing To Do */
  }
}
 8007852:	3728      	adds	r7, #40	@ 0x28
 8007854:	46bd      	mov	sp, r7
 8007856:	bd80      	pop	{r7, pc}
 8007858:	40020010 	.word	0x40020010
 800785c:	40020028 	.word	0x40020028
 8007860:	40020040 	.word	0x40020040
 8007864:	40020058 	.word	0x40020058
 8007868:	40020070 	.word	0x40020070
 800786c:	40020088 	.word	0x40020088
 8007870:	400200a0 	.word	0x400200a0
 8007874:	400200b8 	.word	0x400200b8
 8007878:	40020410 	.word	0x40020410
 800787c:	40020428 	.word	0x40020428
 8007880:	40020440 	.word	0x40020440
 8007884:	40020458 	.word	0x40020458
 8007888:	40020470 	.word	0x40020470
 800788c:	40020488 	.word	0x40020488
 8007890:	400204a0 	.word	0x400204a0
 8007894:	400204b8 	.word	0x400204b8

08007898 <DMA_SetConfig>:
  * @param  DstAddress: The destination memory Buffer address
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval None
  */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 8007898:	b480      	push	{r7}
 800789a:	b087      	sub	sp, #28
 800789c:	af00      	add	r7, sp, #0
 800789e:	60f8      	str	r0, [r7, #12]
 80078a0:	60b9      	str	r1, [r7, #8]
 80078a2:	607a      	str	r2, [r7, #4]
 80078a4:	603b      	str	r3, [r7, #0]
  /* calculate DMA base and stream number */
  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
 80078a6:	68fb      	ldr	r3, [r7, #12]
 80078a8:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80078aa:	617b      	str	r3, [r7, #20]
  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
 80078ac:	68fb      	ldr	r3, [r7, #12]
 80078ae:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80078b0:	613b      	str	r3, [r7, #16]

  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
 80078b2:	68fb      	ldr	r3, [r7, #12]
 80078b4:	681b      	ldr	r3, [r3, #0]
 80078b6:	4a7f      	ldr	r2, [pc, #508]	@ (8007ab4 <DMA_SetConfig+0x21c>)
 80078b8:	4293      	cmp	r3, r2
 80078ba:	d072      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 80078bc:	68fb      	ldr	r3, [r7, #12]
 80078be:	681b      	ldr	r3, [r3, #0]
 80078c0:	4a7d      	ldr	r2, [pc, #500]	@ (8007ab8 <DMA_SetConfig+0x220>)
 80078c2:	4293      	cmp	r3, r2
 80078c4:	d06d      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 80078c6:	68fb      	ldr	r3, [r7, #12]
 80078c8:	681b      	ldr	r3, [r3, #0]
 80078ca:	4a7c      	ldr	r2, [pc, #496]	@ (8007abc <DMA_SetConfig+0x224>)
 80078cc:	4293      	cmp	r3, r2
 80078ce:	d068      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 80078d0:	68fb      	ldr	r3, [r7, #12]
 80078d2:	681b      	ldr	r3, [r3, #0]
 80078d4:	4a7a      	ldr	r2, [pc, #488]	@ (8007ac0 <DMA_SetConfig+0x228>)
 80078d6:	4293      	cmp	r3, r2
 80078d8:	d063      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 80078da:	68fb      	ldr	r3, [r7, #12]
 80078dc:	681b      	ldr	r3, [r3, #0]
 80078de:	4a79      	ldr	r2, [pc, #484]	@ (8007ac4 <DMA_SetConfig+0x22c>)
 80078e0:	4293      	cmp	r3, r2
 80078e2:	d05e      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 80078e4:	68fb      	ldr	r3, [r7, #12]
 80078e6:	681b      	ldr	r3, [r3, #0]
 80078e8:	4a77      	ldr	r2, [pc, #476]	@ (8007ac8 <DMA_SetConfig+0x230>)
 80078ea:	4293      	cmp	r3, r2
 80078ec:	d059      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 80078ee:	68fb      	ldr	r3, [r7, #12]
 80078f0:	681b      	ldr	r3, [r3, #0]
 80078f2:	4a76      	ldr	r2, [pc, #472]	@ (8007acc <DMA_SetConfig+0x234>)
 80078f4:	4293      	cmp	r3, r2
 80078f6:	d054      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 80078f8:	68fb      	ldr	r3, [r7, #12]
 80078fa:	681b      	ldr	r3, [r3, #0]
 80078fc:	4a74      	ldr	r2, [pc, #464]	@ (8007ad0 <DMA_SetConfig+0x238>)
 80078fe:	4293      	cmp	r3, r2
 8007900:	d04f      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 8007902:	68fb      	ldr	r3, [r7, #12]
 8007904:	681b      	ldr	r3, [r3, #0]
 8007906:	4a73      	ldr	r2, [pc, #460]	@ (8007ad4 <DMA_SetConfig+0x23c>)
 8007908:	4293      	cmp	r3, r2
 800790a:	d04a      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 800790c:	68fb      	ldr	r3, [r7, #12]
 800790e:	681b      	ldr	r3, [r3, #0]
 8007910:	4a71      	ldr	r2, [pc, #452]	@ (8007ad8 <DMA_SetConfig+0x240>)
 8007912:	4293      	cmp	r3, r2
 8007914:	d045      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 8007916:	68fb      	ldr	r3, [r7, #12]
 8007918:	681b      	ldr	r3, [r3, #0]
 800791a:	4a70      	ldr	r2, [pc, #448]	@ (8007adc <DMA_SetConfig+0x244>)
 800791c:	4293      	cmp	r3, r2
 800791e:	d040      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 8007920:	68fb      	ldr	r3, [r7, #12]
 8007922:	681b      	ldr	r3, [r3, #0]
 8007924:	4a6e      	ldr	r2, [pc, #440]	@ (8007ae0 <DMA_SetConfig+0x248>)
 8007926:	4293      	cmp	r3, r2
 8007928:	d03b      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 800792a:	68fb      	ldr	r3, [r7, #12]
 800792c:	681b      	ldr	r3, [r3, #0]
 800792e:	4a6d      	ldr	r2, [pc, #436]	@ (8007ae4 <DMA_SetConfig+0x24c>)
 8007930:	4293      	cmp	r3, r2
 8007932:	d036      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 8007934:	68fb      	ldr	r3, [r7, #12]
 8007936:	681b      	ldr	r3, [r3, #0]
 8007938:	4a6b      	ldr	r2, [pc, #428]	@ (8007ae8 <DMA_SetConfig+0x250>)
 800793a:	4293      	cmp	r3, r2
 800793c:	d031      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 800793e:	68fb      	ldr	r3, [r7, #12]
 8007940:	681b      	ldr	r3, [r3, #0]
 8007942:	4a6a      	ldr	r2, [pc, #424]	@ (8007aec <DMA_SetConfig+0x254>)
 8007944:	4293      	cmp	r3, r2
 8007946:	d02c      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 8007948:	68fb      	ldr	r3, [r7, #12]
 800794a:	681b      	ldr	r3, [r3, #0]
 800794c:	4a68      	ldr	r2, [pc, #416]	@ (8007af0 <DMA_SetConfig+0x258>)
 800794e:	4293      	cmp	r3, r2
 8007950:	d027      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 8007952:	68fb      	ldr	r3, [r7, #12]
 8007954:	681b      	ldr	r3, [r3, #0]
 8007956:	4a67      	ldr	r2, [pc, #412]	@ (8007af4 <DMA_SetConfig+0x25c>)
 8007958:	4293      	cmp	r3, r2
 800795a:	d022      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 800795c:	68fb      	ldr	r3, [r7, #12]
 800795e:	681b      	ldr	r3, [r3, #0]
 8007960:	4a65      	ldr	r2, [pc, #404]	@ (8007af8 <DMA_SetConfig+0x260>)
 8007962:	4293      	cmp	r3, r2
 8007964:	d01d      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 8007966:	68fb      	ldr	r3, [r7, #12]
 8007968:	681b      	ldr	r3, [r3, #0]
 800796a:	4a64      	ldr	r2, [pc, #400]	@ (8007afc <DMA_SetConfig+0x264>)
 800796c:	4293      	cmp	r3, r2
 800796e:	d018      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 8007970:	68fb      	ldr	r3, [r7, #12]
 8007972:	681b      	ldr	r3, [r3, #0]
 8007974:	4a62      	ldr	r2, [pc, #392]	@ (8007b00 <DMA_SetConfig+0x268>)
 8007976:	4293      	cmp	r3, r2
 8007978:	d013      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 800797a:	68fb      	ldr	r3, [r7, #12]
 800797c:	681b      	ldr	r3, [r3, #0]
 800797e:	4a61      	ldr	r2, [pc, #388]	@ (8007b04 <DMA_SetConfig+0x26c>)
 8007980:	4293      	cmp	r3, r2
 8007982:	d00e      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 8007984:	68fb      	ldr	r3, [r7, #12]
 8007986:	681b      	ldr	r3, [r3, #0]
 8007988:	4a5f      	ldr	r2, [pc, #380]	@ (8007b08 <DMA_SetConfig+0x270>)
 800798a:	4293      	cmp	r3, r2
 800798c:	d009      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 800798e:	68fb      	ldr	r3, [r7, #12]
 8007990:	681b      	ldr	r3, [r3, #0]
 8007992:	4a5e      	ldr	r2, [pc, #376]	@ (8007b0c <DMA_SetConfig+0x274>)
 8007994:	4293      	cmp	r3, r2
 8007996:	d004      	beq.n	80079a2 <DMA_SetConfig+0x10a>
 8007998:	68fb      	ldr	r3, [r7, #12]
 800799a:	681b      	ldr	r3, [r3, #0]
 800799c:	4a5c      	ldr	r2, [pc, #368]	@ (8007b10 <DMA_SetConfig+0x278>)
 800799e:	4293      	cmp	r3, r2
 80079a0:	d101      	bne.n	80079a6 <DMA_SetConfig+0x10e>
 80079a2:	2301      	movs	r3, #1
 80079a4:	e000      	b.n	80079a8 <DMA_SetConfig+0x110>
 80079a6:	2300      	movs	r3, #0
 80079a8:	2b00      	cmp	r3, #0
 80079aa:	d00d      	beq.n	80079c8 <DMA_SetConfig+0x130>
  {
    /* Clear the DMAMUX synchro overrun flag */
    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 80079ac:	68fb      	ldr	r3, [r7, #12]
 80079ae:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 80079b0:	68fa      	ldr	r2, [r7, #12]
 80079b2:	6e92      	ldr	r2, [r2, #104]	@ 0x68
 80079b4:	605a      	str	r2, [r3, #4]

    if(hdma->DMAmuxRequestGen != 0U)
 80079b6:	68fb      	ldr	r3, [r7, #12]
 80079b8:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 80079ba:	2b00      	cmp	r3, #0
 80079bc:	d004      	beq.n	80079c8 <DMA_SetConfig+0x130>
    {
      /* Clear the DMAMUX request generator overrun flag */
      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 80079be:	68fb      	ldr	r3, [r7, #12]
 80079c0:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 80079c2:	68fa      	ldr	r2, [r7, #12]
 80079c4:	6f52      	ldr	r2, [r2, #116]	@ 0x74
 80079c6:	605a      	str	r2, [r3, #4]
    }
  }

  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 80079c8:	68fb      	ldr	r3, [r7, #12]
 80079ca:	681b      	ldr	r3, [r3, #0]
 80079cc:	4a39      	ldr	r2, [pc, #228]	@ (8007ab4 <DMA_SetConfig+0x21c>)
 80079ce:	4293      	cmp	r3, r2
 80079d0:	d04a      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 80079d2:	68fb      	ldr	r3, [r7, #12]
 80079d4:	681b      	ldr	r3, [r3, #0]
 80079d6:	4a38      	ldr	r2, [pc, #224]	@ (8007ab8 <DMA_SetConfig+0x220>)
 80079d8:	4293      	cmp	r3, r2
 80079da:	d045      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 80079dc:	68fb      	ldr	r3, [r7, #12]
 80079de:	681b      	ldr	r3, [r3, #0]
 80079e0:	4a36      	ldr	r2, [pc, #216]	@ (8007abc <DMA_SetConfig+0x224>)
 80079e2:	4293      	cmp	r3, r2
 80079e4:	d040      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 80079e6:	68fb      	ldr	r3, [r7, #12]
 80079e8:	681b      	ldr	r3, [r3, #0]
 80079ea:	4a35      	ldr	r2, [pc, #212]	@ (8007ac0 <DMA_SetConfig+0x228>)
 80079ec:	4293      	cmp	r3, r2
 80079ee:	d03b      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 80079f0:	68fb      	ldr	r3, [r7, #12]
 80079f2:	681b      	ldr	r3, [r3, #0]
 80079f4:	4a33      	ldr	r2, [pc, #204]	@ (8007ac4 <DMA_SetConfig+0x22c>)
 80079f6:	4293      	cmp	r3, r2
 80079f8:	d036      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 80079fa:	68fb      	ldr	r3, [r7, #12]
 80079fc:	681b      	ldr	r3, [r3, #0]
 80079fe:	4a32      	ldr	r2, [pc, #200]	@ (8007ac8 <DMA_SetConfig+0x230>)
 8007a00:	4293      	cmp	r3, r2
 8007a02:	d031      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 8007a04:	68fb      	ldr	r3, [r7, #12]
 8007a06:	681b      	ldr	r3, [r3, #0]
 8007a08:	4a30      	ldr	r2, [pc, #192]	@ (8007acc <DMA_SetConfig+0x234>)
 8007a0a:	4293      	cmp	r3, r2
 8007a0c:	d02c      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 8007a0e:	68fb      	ldr	r3, [r7, #12]
 8007a10:	681b      	ldr	r3, [r3, #0]
 8007a12:	4a2f      	ldr	r2, [pc, #188]	@ (8007ad0 <DMA_SetConfig+0x238>)
 8007a14:	4293      	cmp	r3, r2
 8007a16:	d027      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 8007a18:	68fb      	ldr	r3, [r7, #12]
 8007a1a:	681b      	ldr	r3, [r3, #0]
 8007a1c:	4a2d      	ldr	r2, [pc, #180]	@ (8007ad4 <DMA_SetConfig+0x23c>)
 8007a1e:	4293      	cmp	r3, r2
 8007a20:	d022      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 8007a22:	68fb      	ldr	r3, [r7, #12]
 8007a24:	681b      	ldr	r3, [r3, #0]
 8007a26:	4a2c      	ldr	r2, [pc, #176]	@ (8007ad8 <DMA_SetConfig+0x240>)
 8007a28:	4293      	cmp	r3, r2
 8007a2a:	d01d      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 8007a2c:	68fb      	ldr	r3, [r7, #12]
 8007a2e:	681b      	ldr	r3, [r3, #0]
 8007a30:	4a2a      	ldr	r2, [pc, #168]	@ (8007adc <DMA_SetConfig+0x244>)
 8007a32:	4293      	cmp	r3, r2
 8007a34:	d018      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 8007a36:	68fb      	ldr	r3, [r7, #12]
 8007a38:	681b      	ldr	r3, [r3, #0]
 8007a3a:	4a29      	ldr	r2, [pc, #164]	@ (8007ae0 <DMA_SetConfig+0x248>)
 8007a3c:	4293      	cmp	r3, r2
 8007a3e:	d013      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 8007a40:	68fb      	ldr	r3, [r7, #12]
 8007a42:	681b      	ldr	r3, [r3, #0]
 8007a44:	4a27      	ldr	r2, [pc, #156]	@ (8007ae4 <DMA_SetConfig+0x24c>)
 8007a46:	4293      	cmp	r3, r2
 8007a48:	d00e      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 8007a4a:	68fb      	ldr	r3, [r7, #12]
 8007a4c:	681b      	ldr	r3, [r3, #0]
 8007a4e:	4a26      	ldr	r2, [pc, #152]	@ (8007ae8 <DMA_SetConfig+0x250>)
 8007a50:	4293      	cmp	r3, r2
 8007a52:	d009      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 8007a54:	68fb      	ldr	r3, [r7, #12]
 8007a56:	681b      	ldr	r3, [r3, #0]
 8007a58:	4a24      	ldr	r2, [pc, #144]	@ (8007aec <DMA_SetConfig+0x254>)
 8007a5a:	4293      	cmp	r3, r2
 8007a5c:	d004      	beq.n	8007a68 <DMA_SetConfig+0x1d0>
 8007a5e:	68fb      	ldr	r3, [r7, #12]
 8007a60:	681b      	ldr	r3, [r3, #0]
 8007a62:	4a23      	ldr	r2, [pc, #140]	@ (8007af0 <DMA_SetConfig+0x258>)
 8007a64:	4293      	cmp	r3, r2
 8007a66:	d101      	bne.n	8007a6c <DMA_SetConfig+0x1d4>
 8007a68:	2301      	movs	r3, #1
 8007a6a:	e000      	b.n	8007a6e <DMA_SetConfig+0x1d6>
 8007a6c:	2300      	movs	r3, #0
 8007a6e:	2b00      	cmp	r3, #0
 8007a70:	d059      	beq.n	8007b26 <DMA_SetConfig+0x28e>
  {
    /* Clear all interrupt flags at correct offset within the register */
    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
 8007a72:	68fb      	ldr	r3, [r7, #12]
 8007a74:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8007a76:	f003 031f 	and.w	r3, r3, #31
 8007a7a:	223f      	movs	r2, #63	@ 0x3f
 8007a7c:	409a      	lsls	r2, r3
 8007a7e:	697b      	ldr	r3, [r7, #20]
 8007a80:	609a      	str	r2, [r3, #8]

    /* Clear DBM bit */
    ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);
 8007a82:	68fb      	ldr	r3, [r7, #12]
 8007a84:	681b      	ldr	r3, [r3, #0]
 8007a86:	681a      	ldr	r2, [r3, #0]
 8007a88:	68fb      	ldr	r3, [r7, #12]
 8007a8a:	681b      	ldr	r3, [r3, #0]
 8007a8c:	f422 2280 	bic.w	r2, r2, #262144	@ 0x40000
 8007a90:	601a      	str	r2, [r3, #0]

    /* Configure DMA Stream data length */
    ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
 8007a92:	68fb      	ldr	r3, [r7, #12]
 8007a94:	681b      	ldr	r3, [r3, #0]
 8007a96:	683a      	ldr	r2, [r7, #0]
 8007a98:	605a      	str	r2, [r3, #4]

    /* Peripheral to Memory */
    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 8007a9a:	68fb      	ldr	r3, [r7, #12]
 8007a9c:	689b      	ldr	r3, [r3, #8]
 8007a9e:	2b40      	cmp	r3, #64	@ 0x40
 8007aa0:	d138      	bne.n	8007b14 <DMA_SetConfig+0x27c>
    {
      /* Configure DMA Stream destination address */
      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
 8007aa2:	68fb      	ldr	r3, [r7, #12]
 8007aa4:	681b      	ldr	r3, [r3, #0]
 8007aa6:	687a      	ldr	r2, [r7, #4]
 8007aa8:	609a      	str	r2, [r3, #8]

      /* Configure DMA Stream source address */
      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
 8007aaa:	68fb      	ldr	r3, [r7, #12]
 8007aac:	681b      	ldr	r3, [r3, #0]
 8007aae:	68ba      	ldr	r2, [r7, #8]
 8007ab0:	60da      	str	r2, [r3, #12]
  }
  else
  {
    /* Nothing To Do */
  }
}
 8007ab2:	e086      	b.n	8007bc2 <DMA_SetConfig+0x32a>
 8007ab4:	40020010 	.word	0x40020010
 8007ab8:	40020028 	.word	0x40020028
 8007abc:	40020040 	.word	0x40020040
 8007ac0:	40020058 	.word	0x40020058
 8007ac4:	40020070 	.word	0x40020070
 8007ac8:	40020088 	.word	0x40020088
 8007acc:	400200a0 	.word	0x400200a0
 8007ad0:	400200b8 	.word	0x400200b8
 8007ad4:	40020410 	.word	0x40020410
 8007ad8:	40020428 	.word	0x40020428
 8007adc:	40020440 	.word	0x40020440
 8007ae0:	40020458 	.word	0x40020458
 8007ae4:	40020470 	.word	0x40020470
 8007ae8:	40020488 	.word	0x40020488
 8007aec:	400204a0 	.word	0x400204a0
 8007af0:	400204b8 	.word	0x400204b8
 8007af4:	58025408 	.word	0x58025408
 8007af8:	5802541c 	.word	0x5802541c
 8007afc:	58025430 	.word	0x58025430
 8007b00:	58025444 	.word	0x58025444
 8007b04:	58025458 	.word	0x58025458
 8007b08:	5802546c 	.word	0x5802546c
 8007b0c:	58025480 	.word	0x58025480
 8007b10:	58025494 	.word	0x58025494
      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
 8007b14:	68fb      	ldr	r3, [r7, #12]
 8007b16:	681b      	ldr	r3, [r3, #0]
 8007b18:	68ba      	ldr	r2, [r7, #8]
 8007b1a:	609a      	str	r2, [r3, #8]
      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
 8007b1c:	68fb      	ldr	r3, [r7, #12]
 8007b1e:	681b      	ldr	r3, [r3, #0]
 8007b20:	687a      	ldr	r2, [r7, #4]
 8007b22:	60da      	str	r2, [r3, #12]
}
 8007b24:	e04d      	b.n	8007bc2 <DMA_SetConfig+0x32a>
  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
 8007b26:	68fb      	ldr	r3, [r7, #12]
 8007b28:	681b      	ldr	r3, [r3, #0]
 8007b2a:	4a29      	ldr	r2, [pc, #164]	@ (8007bd0 <DMA_SetConfig+0x338>)
 8007b2c:	4293      	cmp	r3, r2
 8007b2e:	d022      	beq.n	8007b76 <DMA_SetConfig+0x2de>
 8007b30:	68fb      	ldr	r3, [r7, #12]
 8007b32:	681b      	ldr	r3, [r3, #0]
 8007b34:	4a27      	ldr	r2, [pc, #156]	@ (8007bd4 <DMA_SetConfig+0x33c>)
 8007b36:	4293      	cmp	r3, r2
 8007b38:	d01d      	beq.n	8007b76 <DMA_SetConfig+0x2de>
 8007b3a:	68fb      	ldr	r3, [r7, #12]
 8007b3c:	681b      	ldr	r3, [r3, #0]
 8007b3e:	4a26      	ldr	r2, [pc, #152]	@ (8007bd8 <DMA_SetConfig+0x340>)
 8007b40:	4293      	cmp	r3, r2
 8007b42:	d018      	beq.n	8007b76 <DMA_SetConfig+0x2de>
 8007b44:	68fb      	ldr	r3, [r7, #12]
 8007b46:	681b      	ldr	r3, [r3, #0]
 8007b48:	4a24      	ldr	r2, [pc, #144]	@ (8007bdc <DMA_SetConfig+0x344>)
 8007b4a:	4293      	cmp	r3, r2
 8007b4c:	d013      	beq.n	8007b76 <DMA_SetConfig+0x2de>
 8007b4e:	68fb      	ldr	r3, [r7, #12]
 8007b50:	681b      	ldr	r3, [r3, #0]
 8007b52:	4a23      	ldr	r2, [pc, #140]	@ (8007be0 <DMA_SetConfig+0x348>)
 8007b54:	4293      	cmp	r3, r2
 8007b56:	d00e      	beq.n	8007b76 <DMA_SetConfig+0x2de>
 8007b58:	68fb      	ldr	r3, [r7, #12]
 8007b5a:	681b      	ldr	r3, [r3, #0]
 8007b5c:	4a21      	ldr	r2, [pc, #132]	@ (8007be4 <DMA_SetConfig+0x34c>)
 8007b5e:	4293      	cmp	r3, r2
 8007b60:	d009      	beq.n	8007b76 <DMA_SetConfig+0x2de>
 8007b62:	68fb      	ldr	r3, [r7, #12]
 8007b64:	681b      	ldr	r3, [r3, #0]
 8007b66:	4a20      	ldr	r2, [pc, #128]	@ (8007be8 <DMA_SetConfig+0x350>)
 8007b68:	4293      	cmp	r3, r2
 8007b6a:	d004      	beq.n	8007b76 <DMA_SetConfig+0x2de>
 8007b6c:	68fb      	ldr	r3, [r7, #12]
 8007b6e:	681b      	ldr	r3, [r3, #0]
 8007b70:	4a1e      	ldr	r2, [pc, #120]	@ (8007bec <DMA_SetConfig+0x354>)
 8007b72:	4293      	cmp	r3, r2
 8007b74:	d101      	bne.n	8007b7a <DMA_SetConfig+0x2e2>
 8007b76:	2301      	movs	r3, #1
 8007b78:	e000      	b.n	8007b7c <DMA_SetConfig+0x2e4>
 8007b7a:	2300      	movs	r3, #0
 8007b7c:	2b00      	cmp	r3, #0
 8007b7e:	d020      	beq.n	8007bc2 <DMA_SetConfig+0x32a>
    regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
 8007b80:	68fb      	ldr	r3, [r7, #12]
 8007b82:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8007b84:	f003 031f 	and.w	r3, r3, #31
 8007b88:	2201      	movs	r2, #1
 8007b8a:	409a      	lsls	r2, r3
 8007b8c:	693b      	ldr	r3, [r7, #16]
 8007b8e:	605a      	str	r2, [r3, #4]
    ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
 8007b90:	68fb      	ldr	r3, [r7, #12]
 8007b92:	681b      	ldr	r3, [r3, #0]
 8007b94:	683a      	ldr	r2, [r7, #0]
 8007b96:	605a      	str	r2, [r3, #4]
    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 8007b98:	68fb      	ldr	r3, [r7, #12]
 8007b9a:	689b      	ldr	r3, [r3, #8]
 8007b9c:	2b40      	cmp	r3, #64	@ 0x40
 8007b9e:	d108      	bne.n	8007bb2 <DMA_SetConfig+0x31a>
      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
 8007ba0:	68fb      	ldr	r3, [r7, #12]
 8007ba2:	681b      	ldr	r3, [r3, #0]
 8007ba4:	687a      	ldr	r2, [r7, #4]
 8007ba6:	609a      	str	r2, [r3, #8]
      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
 8007ba8:	68fb      	ldr	r3, [r7, #12]
 8007baa:	681b      	ldr	r3, [r3, #0]
 8007bac:	68ba      	ldr	r2, [r7, #8]
 8007bae:	60da      	str	r2, [r3, #12]
}
 8007bb0:	e007      	b.n	8007bc2 <DMA_SetConfig+0x32a>
      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
 8007bb2:	68fb      	ldr	r3, [r7, #12]
 8007bb4:	681b      	ldr	r3, [r3, #0]
 8007bb6:	68ba      	ldr	r2, [r7, #8]
 8007bb8:	609a      	str	r2, [r3, #8]
      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
 8007bba:	68fb      	ldr	r3, [r7, #12]
 8007bbc:	681b      	ldr	r3, [r3, #0]
 8007bbe:	687a      	ldr	r2, [r7, #4]
 8007bc0:	60da      	str	r2, [r3, #12]
}
 8007bc2:	bf00      	nop
 8007bc4:	371c      	adds	r7, #28
 8007bc6:	46bd      	mov	sp, r7
 8007bc8:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007bcc:	4770      	bx	lr
 8007bce:	bf00      	nop
 8007bd0:	58025408 	.word	0x58025408
 8007bd4:	5802541c 	.word	0x5802541c
 8007bd8:	58025430 	.word	0x58025430
 8007bdc:	58025444 	.word	0x58025444
 8007be0:	58025458 	.word	0x58025458
 8007be4:	5802546c 	.word	0x5802546c
 8007be8:	58025480 	.word	0x58025480
 8007bec:	58025494 	.word	0x58025494

08007bf0 <DMA_CalcBaseAndBitshift>:
  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
  *                     the configuration information for the specified DMA Stream.
  * @retval Stream base address
  */
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
{
 8007bf0:	b480      	push	{r7}
 8007bf2:	b085      	sub	sp, #20
 8007bf4:	af00      	add	r7, sp, #0
 8007bf6:	6078      	str	r0, [r7, #4]
  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 8007bf8:	687b      	ldr	r3, [r7, #4]
 8007bfa:	681b      	ldr	r3, [r3, #0]
 8007bfc:	4a42      	ldr	r2, [pc, #264]	@ (8007d08 <DMA_CalcBaseAndBitshift+0x118>)
 8007bfe:	4293      	cmp	r3, r2
 8007c00:	d04a      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c02:	687b      	ldr	r3, [r7, #4]
 8007c04:	681b      	ldr	r3, [r3, #0]
 8007c06:	4a41      	ldr	r2, [pc, #260]	@ (8007d0c <DMA_CalcBaseAndBitshift+0x11c>)
 8007c08:	4293      	cmp	r3, r2
 8007c0a:	d045      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c0c:	687b      	ldr	r3, [r7, #4]
 8007c0e:	681b      	ldr	r3, [r3, #0]
 8007c10:	4a3f      	ldr	r2, [pc, #252]	@ (8007d10 <DMA_CalcBaseAndBitshift+0x120>)
 8007c12:	4293      	cmp	r3, r2
 8007c14:	d040      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c16:	687b      	ldr	r3, [r7, #4]
 8007c18:	681b      	ldr	r3, [r3, #0]
 8007c1a:	4a3e      	ldr	r2, [pc, #248]	@ (8007d14 <DMA_CalcBaseAndBitshift+0x124>)
 8007c1c:	4293      	cmp	r3, r2
 8007c1e:	d03b      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c20:	687b      	ldr	r3, [r7, #4]
 8007c22:	681b      	ldr	r3, [r3, #0]
 8007c24:	4a3c      	ldr	r2, [pc, #240]	@ (8007d18 <DMA_CalcBaseAndBitshift+0x128>)
 8007c26:	4293      	cmp	r3, r2
 8007c28:	d036      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c2a:	687b      	ldr	r3, [r7, #4]
 8007c2c:	681b      	ldr	r3, [r3, #0]
 8007c2e:	4a3b      	ldr	r2, [pc, #236]	@ (8007d1c <DMA_CalcBaseAndBitshift+0x12c>)
 8007c30:	4293      	cmp	r3, r2
 8007c32:	d031      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c34:	687b      	ldr	r3, [r7, #4]
 8007c36:	681b      	ldr	r3, [r3, #0]
 8007c38:	4a39      	ldr	r2, [pc, #228]	@ (8007d20 <DMA_CalcBaseAndBitshift+0x130>)
 8007c3a:	4293      	cmp	r3, r2
 8007c3c:	d02c      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c3e:	687b      	ldr	r3, [r7, #4]
 8007c40:	681b      	ldr	r3, [r3, #0]
 8007c42:	4a38      	ldr	r2, [pc, #224]	@ (8007d24 <DMA_CalcBaseAndBitshift+0x134>)
 8007c44:	4293      	cmp	r3, r2
 8007c46:	d027      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c48:	687b      	ldr	r3, [r7, #4]
 8007c4a:	681b      	ldr	r3, [r3, #0]
 8007c4c:	4a36      	ldr	r2, [pc, #216]	@ (8007d28 <DMA_CalcBaseAndBitshift+0x138>)
 8007c4e:	4293      	cmp	r3, r2
 8007c50:	d022      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c52:	687b      	ldr	r3, [r7, #4]
 8007c54:	681b      	ldr	r3, [r3, #0]
 8007c56:	4a35      	ldr	r2, [pc, #212]	@ (8007d2c <DMA_CalcBaseAndBitshift+0x13c>)
 8007c58:	4293      	cmp	r3, r2
 8007c5a:	d01d      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c5c:	687b      	ldr	r3, [r7, #4]
 8007c5e:	681b      	ldr	r3, [r3, #0]
 8007c60:	4a33      	ldr	r2, [pc, #204]	@ (8007d30 <DMA_CalcBaseAndBitshift+0x140>)
 8007c62:	4293      	cmp	r3, r2
 8007c64:	d018      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c66:	687b      	ldr	r3, [r7, #4]
 8007c68:	681b      	ldr	r3, [r3, #0]
 8007c6a:	4a32      	ldr	r2, [pc, #200]	@ (8007d34 <DMA_CalcBaseAndBitshift+0x144>)
 8007c6c:	4293      	cmp	r3, r2
 8007c6e:	d013      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c70:	687b      	ldr	r3, [r7, #4]
 8007c72:	681b      	ldr	r3, [r3, #0]
 8007c74:	4a30      	ldr	r2, [pc, #192]	@ (8007d38 <DMA_CalcBaseAndBitshift+0x148>)
 8007c76:	4293      	cmp	r3, r2
 8007c78:	d00e      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c7a:	687b      	ldr	r3, [r7, #4]
 8007c7c:	681b      	ldr	r3, [r3, #0]
 8007c7e:	4a2f      	ldr	r2, [pc, #188]	@ (8007d3c <DMA_CalcBaseAndBitshift+0x14c>)
 8007c80:	4293      	cmp	r3, r2
 8007c82:	d009      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c84:	687b      	ldr	r3, [r7, #4]
 8007c86:	681b      	ldr	r3, [r3, #0]
 8007c88:	4a2d      	ldr	r2, [pc, #180]	@ (8007d40 <DMA_CalcBaseAndBitshift+0x150>)
 8007c8a:	4293      	cmp	r3, r2
 8007c8c:	d004      	beq.n	8007c98 <DMA_CalcBaseAndBitshift+0xa8>
 8007c8e:	687b      	ldr	r3, [r7, #4]
 8007c90:	681b      	ldr	r3, [r3, #0]
 8007c92:	4a2c      	ldr	r2, [pc, #176]	@ (8007d44 <DMA_CalcBaseAndBitshift+0x154>)
 8007c94:	4293      	cmp	r3, r2
 8007c96:	d101      	bne.n	8007c9c <DMA_CalcBaseAndBitshift+0xac>
 8007c98:	2301      	movs	r3, #1
 8007c9a:	e000      	b.n	8007c9e <DMA_CalcBaseAndBitshift+0xae>
 8007c9c:	2300      	movs	r3, #0
 8007c9e:	2b00      	cmp	r3, #0
 8007ca0:	d024      	beq.n	8007cec <DMA_CalcBaseAndBitshift+0xfc>
  {
    uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
 8007ca2:	687b      	ldr	r3, [r7, #4]
 8007ca4:	681b      	ldr	r3, [r3, #0]
 8007ca6:	b2db      	uxtb	r3, r3
 8007ca8:	3b10      	subs	r3, #16
 8007caa:	4a27      	ldr	r2, [pc, #156]	@ (8007d48 <DMA_CalcBaseAndBitshift+0x158>)
 8007cac:	fba2 2303 	umull	r2, r3, r2, r3
 8007cb0:	091b      	lsrs	r3, r3, #4
 8007cb2:	60fb      	str	r3, [r7, #12]

    /* lookup table for necessary bitshift of flags within status registers */
    static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
    hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
 8007cb4:	68fb      	ldr	r3, [r7, #12]
 8007cb6:	f003 0307 	and.w	r3, r3, #7
 8007cba:	4a24      	ldr	r2, [pc, #144]	@ (8007d4c <DMA_CalcBaseAndBitshift+0x15c>)
 8007cbc:	5cd3      	ldrb	r3, [r2, r3]
 8007cbe:	461a      	mov	r2, r3
 8007cc0:	687b      	ldr	r3, [r7, #4]
 8007cc2:	65da      	str	r2, [r3, #92]	@ 0x5c

    if (stream_number > 3U)
 8007cc4:	68fb      	ldr	r3, [r7, #12]
 8007cc6:	2b03      	cmp	r3, #3
 8007cc8:	d908      	bls.n	8007cdc <DMA_CalcBaseAndBitshift+0xec>
    {
      /* return pointer to HISR and HIFCR */
      hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U);
 8007cca:	687b      	ldr	r3, [r7, #4]
 8007ccc:	681b      	ldr	r3, [r3, #0]
 8007cce:	461a      	mov	r2, r3
 8007cd0:	4b1f      	ldr	r3, [pc, #124]	@ (8007d50 <DMA_CalcBaseAndBitshift+0x160>)
 8007cd2:	4013      	ands	r3, r2
 8007cd4:	1d1a      	adds	r2, r3, #4
 8007cd6:	687b      	ldr	r3, [r7, #4]
 8007cd8:	659a      	str	r2, [r3, #88]	@ 0x58
 8007cda:	e00d      	b.n	8007cf8 <DMA_CalcBaseAndBitshift+0x108>
    }
    else
    {
      /* return pointer to LISR and LIFCR */
      hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU));
 8007cdc:	687b      	ldr	r3, [r7, #4]
 8007cde:	681b      	ldr	r3, [r3, #0]
 8007ce0:	461a      	mov	r2, r3
 8007ce2:	4b1b      	ldr	r3, [pc, #108]	@ (8007d50 <DMA_CalcBaseAndBitshift+0x160>)
 8007ce4:	4013      	ands	r3, r2
 8007ce6:	687a      	ldr	r2, [r7, #4]
 8007ce8:	6593      	str	r3, [r2, #88]	@ 0x58
 8007cea:	e005      	b.n	8007cf8 <DMA_CalcBaseAndBitshift+0x108>
    }
  }
  else /* BDMA instance(s) */
  {
    /* return pointer to ISR and IFCR */
    hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU));
 8007cec:	687b      	ldr	r3, [r7, #4]
 8007cee:	681b      	ldr	r3, [r3, #0]
 8007cf0:	f023 02ff 	bic.w	r2, r3, #255	@ 0xff
 8007cf4:	687b      	ldr	r3, [r7, #4]
 8007cf6:	659a      	str	r2, [r3, #88]	@ 0x58
  }

  return hdma->StreamBaseAddress;
 8007cf8:	687b      	ldr	r3, [r7, #4]
 8007cfa:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
}
 8007cfc:	4618      	mov	r0, r3
 8007cfe:	3714      	adds	r7, #20
 8007d00:	46bd      	mov	sp, r7
 8007d02:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007d06:	4770      	bx	lr
 8007d08:	40020010 	.word	0x40020010
 8007d0c:	40020028 	.word	0x40020028
 8007d10:	40020040 	.word	0x40020040
 8007d14:	40020058 	.word	0x40020058
 8007d18:	40020070 	.word	0x40020070
 8007d1c:	40020088 	.word	0x40020088
 8007d20:	400200a0 	.word	0x400200a0
 8007d24:	400200b8 	.word	0x400200b8
 8007d28:	40020410 	.word	0x40020410
 8007d2c:	40020428 	.word	0x40020428
 8007d30:	40020440 	.word	0x40020440
 8007d34:	40020458 	.word	0x40020458
 8007d38:	40020470 	.word	0x40020470
 8007d3c:	40020488 	.word	0x40020488
 8007d40:	400204a0 	.word	0x400204a0
 8007d44:	400204b8 	.word	0x400204b8
 8007d48:	aaaaaaab 	.word	0xaaaaaaab
 8007d4c:	080145f4 	.word	0x080145f4
 8007d50:	fffffc00 	.word	0xfffffc00

08007d54 <DMA_CheckFifoParam>:
  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
  *                     the configuration information for the specified DMA Stream.
  * @retval HAL status
  */
static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{
 8007d54:	b480      	push	{r7}
 8007d56:	b085      	sub	sp, #20
 8007d58:	af00      	add	r7, sp, #0
 8007d5a:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 8007d5c:	2300      	movs	r3, #0
 8007d5e:	73fb      	strb	r3, [r7, #15]

  /* Memory Data size equal to Byte */
  if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
 8007d60:	687b      	ldr	r3, [r7, #4]
 8007d62:	699b      	ldr	r3, [r3, #24]
 8007d64:	2b00      	cmp	r3, #0
 8007d66:	d120      	bne.n	8007daa <DMA_CheckFifoParam+0x56>
  {
    switch (hdma->Init.FIFOThreshold)
 8007d68:	687b      	ldr	r3, [r7, #4]
 8007d6a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8007d6c:	2b03      	cmp	r3, #3
 8007d6e:	d858      	bhi.n	8007e22 <DMA_CheckFifoParam+0xce>
 8007d70:	a201      	add	r2, pc, #4	@ (adr r2, 8007d78 <DMA_CheckFifoParam+0x24>)
 8007d72:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8007d76:	bf00      	nop
 8007d78:	08007d89 	.word	0x08007d89
 8007d7c:	08007d9b 	.word	0x08007d9b
 8007d80:	08007d89 	.word	0x08007d89
 8007d84:	08007e23 	.word	0x08007e23
    {
      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:

        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
 8007d88:	687b      	ldr	r3, [r7, #4]
 8007d8a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8007d8c:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 8007d90:	2b00      	cmp	r3, #0
 8007d92:	d048      	beq.n	8007e26 <DMA_CheckFifoParam+0xd2>
        {
          status = HAL_ERROR;
 8007d94:	2301      	movs	r3, #1
 8007d96:	73fb      	strb	r3, [r7, #15]
        }
        break;
 8007d98:	e045      	b.n	8007e26 <DMA_CheckFifoParam+0xd2>

      case DMA_FIFO_THRESHOLD_HALFFULL:
        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
 8007d9a:	687b      	ldr	r3, [r7, #4]
 8007d9c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8007d9e:	f1b3 7fc0 	cmp.w	r3, #25165824	@ 0x1800000
 8007da2:	d142      	bne.n	8007e2a <DMA_CheckFifoParam+0xd6>
        {
          status = HAL_ERROR;
 8007da4:	2301      	movs	r3, #1
 8007da6:	73fb      	strb	r3, [r7, #15]
        }
        break;
 8007da8:	e03f      	b.n	8007e2a <DMA_CheckFifoParam+0xd6>
        break;
    }
  }

  /* Memory Data size equal to Half-Word */
  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
 8007daa:	687b      	ldr	r3, [r7, #4]
 8007dac:	699b      	ldr	r3, [r3, #24]
 8007dae:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 8007db2:	d123      	bne.n	8007dfc <DMA_CheckFifoParam+0xa8>
  {
    switch (hdma->Init.FIFOThreshold)
 8007db4:	687b      	ldr	r3, [r7, #4]
 8007db6:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8007db8:	2b03      	cmp	r3, #3
 8007dba:	d838      	bhi.n	8007e2e <DMA_CheckFifoParam+0xda>
 8007dbc:	a201      	add	r2, pc, #4	@ (adr r2, 8007dc4 <DMA_CheckFifoParam+0x70>)
 8007dbe:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8007dc2:	bf00      	nop
 8007dc4:	08007dd5 	.word	0x08007dd5
 8007dc8:	08007ddb 	.word	0x08007ddb
 8007dcc:	08007dd5 	.word	0x08007dd5
 8007dd0:	08007ded 	.word	0x08007ded
    {
      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
        status = HAL_ERROR;
 8007dd4:	2301      	movs	r3, #1
 8007dd6:	73fb      	strb	r3, [r7, #15]
        break;
 8007dd8:	e030      	b.n	8007e3c <DMA_CheckFifoParam+0xe8>

      case DMA_FIFO_THRESHOLD_HALFFULL:
        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
 8007dda:	687b      	ldr	r3, [r7, #4]
 8007ddc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8007dde:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 8007de2:	2b00      	cmp	r3, #0
 8007de4:	d025      	beq.n	8007e32 <DMA_CheckFifoParam+0xde>
        {
          status = HAL_ERROR;
 8007de6:	2301      	movs	r3, #1
 8007de8:	73fb      	strb	r3, [r7, #15]
        }
        break;
 8007dea:	e022      	b.n	8007e32 <DMA_CheckFifoParam+0xde>

      case DMA_FIFO_THRESHOLD_FULL:
        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
 8007dec:	687b      	ldr	r3, [r7, #4]
 8007dee:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8007df0:	f1b3 7fc0 	cmp.w	r3, #25165824	@ 0x1800000
 8007df4:	d11f      	bne.n	8007e36 <DMA_CheckFifoParam+0xe2>
        {
          status = HAL_ERROR;
 8007df6:	2301      	movs	r3, #1
 8007df8:	73fb      	strb	r3, [r7, #15]
        }
        break;
 8007dfa:	e01c      	b.n	8007e36 <DMA_CheckFifoParam+0xe2>
  }

  /* Memory Data size equal to Word */
  else
  {
    switch (hdma->Init.FIFOThreshold)
 8007dfc:	687b      	ldr	r3, [r7, #4]
 8007dfe:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8007e00:	2b02      	cmp	r3, #2
 8007e02:	d902      	bls.n	8007e0a <DMA_CheckFifoParam+0xb6>
 8007e04:	2b03      	cmp	r3, #3
 8007e06:	d003      	beq.n	8007e10 <DMA_CheckFifoParam+0xbc>
          status = HAL_ERROR;
        }
    break;

      default:
        break;
 8007e08:	e018      	b.n	8007e3c <DMA_CheckFifoParam+0xe8>
        status = HAL_ERROR;
 8007e0a:	2301      	movs	r3, #1
 8007e0c:	73fb      	strb	r3, [r7, #15]
        break;
 8007e0e:	e015      	b.n	8007e3c <DMA_CheckFifoParam+0xe8>
        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
 8007e10:	687b      	ldr	r3, [r7, #4]
 8007e12:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8007e14:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 8007e18:	2b00      	cmp	r3, #0
 8007e1a:	d00e      	beq.n	8007e3a <DMA_CheckFifoParam+0xe6>
          status = HAL_ERROR;
 8007e1c:	2301      	movs	r3, #1
 8007e1e:	73fb      	strb	r3, [r7, #15]
    break;
 8007e20:	e00b      	b.n	8007e3a <DMA_CheckFifoParam+0xe6>
        break;
 8007e22:	bf00      	nop
 8007e24:	e00a      	b.n	8007e3c <DMA_CheckFifoParam+0xe8>
        break;
 8007e26:	bf00      	nop
 8007e28:	e008      	b.n	8007e3c <DMA_CheckFifoParam+0xe8>
        break;
 8007e2a:	bf00      	nop
 8007e2c:	e006      	b.n	8007e3c <DMA_CheckFifoParam+0xe8>
        break;
 8007e2e:	bf00      	nop
 8007e30:	e004      	b.n	8007e3c <DMA_CheckFifoParam+0xe8>
        break;
 8007e32:	bf00      	nop
 8007e34:	e002      	b.n	8007e3c <DMA_CheckFifoParam+0xe8>
        break;
 8007e36:	bf00      	nop
 8007e38:	e000      	b.n	8007e3c <DMA_CheckFifoParam+0xe8>
    break;
 8007e3a:	bf00      	nop
    }
  }

  return status;
 8007e3c:	7bfb      	ldrb	r3, [r7, #15]
}
 8007e3e:	4618      	mov	r0, r3
 8007e40:	3714      	adds	r7, #20
 8007e42:	46bd      	mov	sp, r7
 8007e44:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007e48:	4770      	bx	lr
 8007e4a:	bf00      	nop

08007e4c <DMA_CalcDMAMUXChannelBaseAndMask>:
  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
  *                     the configuration information for the specified DMA Stream.
  * @retval HAL status
  */
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
{
 8007e4c:	b480      	push	{r7}
 8007e4e:	b085      	sub	sp, #20
 8007e50:	af00      	add	r7, sp, #0
 8007e52:	6078      	str	r0, [r7, #4]
  uint32_t stream_number;
  uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance);
 8007e54:	687b      	ldr	r3, [r7, #4]
 8007e56:	681b      	ldr	r3, [r3, #0]
 8007e58:	60bb      	str	r3, [r7, #8]

  if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
 8007e5a:	687b      	ldr	r3, [r7, #4]
 8007e5c:	681b      	ldr	r3, [r3, #0]
 8007e5e:	4a38      	ldr	r2, [pc, #224]	@ (8007f40 <DMA_CalcDMAMUXChannelBaseAndMask+0xf4>)
 8007e60:	4293      	cmp	r3, r2
 8007e62:	d022      	beq.n	8007eaa <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 8007e64:	687b      	ldr	r3, [r7, #4]
 8007e66:	681b      	ldr	r3, [r3, #0]
 8007e68:	4a36      	ldr	r2, [pc, #216]	@ (8007f44 <DMA_CalcDMAMUXChannelBaseAndMask+0xf8>)
 8007e6a:	4293      	cmp	r3, r2
 8007e6c:	d01d      	beq.n	8007eaa <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 8007e6e:	687b      	ldr	r3, [r7, #4]
 8007e70:	681b      	ldr	r3, [r3, #0]
 8007e72:	4a35      	ldr	r2, [pc, #212]	@ (8007f48 <DMA_CalcDMAMUXChannelBaseAndMask+0xfc>)
 8007e74:	4293      	cmp	r3, r2
 8007e76:	d018      	beq.n	8007eaa <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 8007e78:	687b      	ldr	r3, [r7, #4]
 8007e7a:	681b      	ldr	r3, [r3, #0]
 8007e7c:	4a33      	ldr	r2, [pc, #204]	@ (8007f4c <DMA_CalcDMAMUXChannelBaseAndMask+0x100>)
 8007e7e:	4293      	cmp	r3, r2
 8007e80:	d013      	beq.n	8007eaa <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 8007e82:	687b      	ldr	r3, [r7, #4]
 8007e84:	681b      	ldr	r3, [r3, #0]
 8007e86:	4a32      	ldr	r2, [pc, #200]	@ (8007f50 <DMA_CalcDMAMUXChannelBaseAndMask+0x104>)
 8007e88:	4293      	cmp	r3, r2
 8007e8a:	d00e      	beq.n	8007eaa <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 8007e8c:	687b      	ldr	r3, [r7, #4]
 8007e8e:	681b      	ldr	r3, [r3, #0]
 8007e90:	4a30      	ldr	r2, [pc, #192]	@ (8007f54 <DMA_CalcDMAMUXChannelBaseAndMask+0x108>)
 8007e92:	4293      	cmp	r3, r2
 8007e94:	d009      	beq.n	8007eaa <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 8007e96:	687b      	ldr	r3, [r7, #4]
 8007e98:	681b      	ldr	r3, [r3, #0]
 8007e9a:	4a2f      	ldr	r2, [pc, #188]	@ (8007f58 <DMA_CalcDMAMUXChannelBaseAndMask+0x10c>)
 8007e9c:	4293      	cmp	r3, r2
 8007e9e:	d004      	beq.n	8007eaa <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 8007ea0:	687b      	ldr	r3, [r7, #4]
 8007ea2:	681b      	ldr	r3, [r3, #0]
 8007ea4:	4a2d      	ldr	r2, [pc, #180]	@ (8007f5c <DMA_CalcDMAMUXChannelBaseAndMask+0x110>)
 8007ea6:	4293      	cmp	r3, r2
 8007ea8:	d101      	bne.n	8007eae <DMA_CalcDMAMUXChannelBaseAndMask+0x62>
 8007eaa:	2301      	movs	r3, #1
 8007eac:	e000      	b.n	8007eb0 <DMA_CalcDMAMUXChannelBaseAndMask+0x64>
 8007eae:	2300      	movs	r3, #0
 8007eb0:	2b00      	cmp	r3, #0
 8007eb2:	d01a      	beq.n	8007eea <DMA_CalcDMAMUXChannelBaseAndMask+0x9e>
  {
    /* BDMA Channels are connected to DMAMUX2 channels */
    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U;
 8007eb4:	687b      	ldr	r3, [r7, #4]
 8007eb6:	681b      	ldr	r3, [r3, #0]
 8007eb8:	b2db      	uxtb	r3, r3
 8007eba:	3b08      	subs	r3, #8
 8007ebc:	4a28      	ldr	r2, [pc, #160]	@ (8007f60 <DMA_CalcDMAMUXChannelBaseAndMask+0x114>)
 8007ebe:	fba2 2303 	umull	r2, r3, r2, r3
 8007ec2:	091b      	lsrs	r3, r3, #4
 8007ec4:	60fb      	str	r3, [r7, #12]
    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
 8007ec6:	68fa      	ldr	r2, [r7, #12]
 8007ec8:	4b26      	ldr	r3, [pc, #152]	@ (8007f64 <DMA_CalcDMAMUXChannelBaseAndMask+0x118>)
 8007eca:	4413      	add	r3, r2
 8007ecc:	009b      	lsls	r3, r3, #2
 8007ece:	461a      	mov	r2, r3
 8007ed0:	687b      	ldr	r3, [r7, #4]
 8007ed2:	661a      	str	r2, [r3, #96]	@ 0x60
    hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;
 8007ed4:	687b      	ldr	r3, [r7, #4]
 8007ed6:	4a24      	ldr	r2, [pc, #144]	@ (8007f68 <DMA_CalcDMAMUXChannelBaseAndMask+0x11c>)
 8007ed8:	665a      	str	r2, [r3, #100]	@ 0x64
    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
 8007eda:	68fb      	ldr	r3, [r7, #12]
 8007edc:	f003 031f 	and.w	r3, r3, #31
 8007ee0:	2201      	movs	r2, #1
 8007ee2:	409a      	lsls	r2, r3
 8007ee4:	687b      	ldr	r3, [r7, #4]
 8007ee6:	669a      	str	r2, [r3, #104]	@ 0x68
    }
    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
    hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
  }
}
 8007ee8:	e024      	b.n	8007f34 <DMA_CalcDMAMUXChannelBaseAndMask+0xe8>
    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
 8007eea:	687b      	ldr	r3, [r7, #4]
 8007eec:	681b      	ldr	r3, [r3, #0]
 8007eee:	b2db      	uxtb	r3, r3
 8007ef0:	3b10      	subs	r3, #16
 8007ef2:	4a1e      	ldr	r2, [pc, #120]	@ (8007f6c <DMA_CalcDMAMUXChannelBaseAndMask+0x120>)
 8007ef4:	fba2 2303 	umull	r2, r3, r2, r3
 8007ef8:	091b      	lsrs	r3, r3, #4
 8007efa:	60fb      	str	r3, [r7, #12]
    if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
 8007efc:	68bb      	ldr	r3, [r7, #8]
 8007efe:	4a1c      	ldr	r2, [pc, #112]	@ (8007f70 <DMA_CalcDMAMUXChannelBaseAndMask+0x124>)
 8007f00:	4293      	cmp	r3, r2
 8007f02:	d806      	bhi.n	8007f12 <DMA_CalcDMAMUXChannelBaseAndMask+0xc6>
 8007f04:	68bb      	ldr	r3, [r7, #8]
 8007f06:	4a1b      	ldr	r2, [pc, #108]	@ (8007f74 <DMA_CalcDMAMUXChannelBaseAndMask+0x128>)
 8007f08:	4293      	cmp	r3, r2
 8007f0a:	d902      	bls.n	8007f12 <DMA_CalcDMAMUXChannelBaseAndMask+0xc6>
      stream_number += 8U;
 8007f0c:	68fb      	ldr	r3, [r7, #12]
 8007f0e:	3308      	adds	r3, #8
 8007f10:	60fb      	str	r3, [r7, #12]
    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
 8007f12:	68fa      	ldr	r2, [r7, #12]
 8007f14:	4b18      	ldr	r3, [pc, #96]	@ (8007f78 <DMA_CalcDMAMUXChannelBaseAndMask+0x12c>)
 8007f16:	4413      	add	r3, r2
 8007f18:	009b      	lsls	r3, r3, #2
 8007f1a:	461a      	mov	r2, r3
 8007f1c:	687b      	ldr	r3, [r7, #4]
 8007f1e:	661a      	str	r2, [r3, #96]	@ 0x60
    hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
 8007f20:	687b      	ldr	r3, [r7, #4]
 8007f22:	4a16      	ldr	r2, [pc, #88]	@ (8007f7c <DMA_CalcDMAMUXChannelBaseAndMask+0x130>)
 8007f24:	665a      	str	r2, [r3, #100]	@ 0x64
    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
 8007f26:	68fb      	ldr	r3, [r7, #12]
 8007f28:	f003 031f 	and.w	r3, r3, #31
 8007f2c:	2201      	movs	r2, #1
 8007f2e:	409a      	lsls	r2, r3
 8007f30:	687b      	ldr	r3, [r7, #4]
 8007f32:	669a      	str	r2, [r3, #104]	@ 0x68
}
 8007f34:	bf00      	nop
 8007f36:	3714      	adds	r7, #20
 8007f38:	46bd      	mov	sp, r7
 8007f3a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007f3e:	4770      	bx	lr
 8007f40:	58025408 	.word	0x58025408
 8007f44:	5802541c 	.word	0x5802541c
 8007f48:	58025430 	.word	0x58025430
 8007f4c:	58025444 	.word	0x58025444
 8007f50:	58025458 	.word	0x58025458
 8007f54:	5802546c 	.word	0x5802546c
 8007f58:	58025480 	.word	0x58025480
 8007f5c:	58025494 	.word	0x58025494
 8007f60:	cccccccd 	.word	0xcccccccd
 8007f64:	16009600 	.word	0x16009600
 8007f68:	58025880 	.word	0x58025880
 8007f6c:	aaaaaaab 	.word	0xaaaaaaab
 8007f70:	400204b8 	.word	0x400204b8
 8007f74:	4002040f 	.word	0x4002040f
 8007f78:	10008200 	.word	0x10008200
 8007f7c:	40020880 	.word	0x40020880

08007f80 <DMA_CalcDMAMUXRequestGenBaseAndMask>:
  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
  *                     the configuration information for the specified DMA Stream.
  * @retval HAL status
  */
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
{
 8007f80:	b480      	push	{r7}
 8007f82:	b085      	sub	sp, #20
 8007f84:	af00      	add	r7, sp, #0
 8007f86:	6078      	str	r0, [r7, #4]
  uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
 8007f88:	687b      	ldr	r3, [r7, #4]
 8007f8a:	685b      	ldr	r3, [r3, #4]
 8007f8c:	b2db      	uxtb	r3, r3
 8007f8e:	60fb      	str	r3, [r7, #12]

  if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
 8007f90:	68fb      	ldr	r3, [r7, #12]
 8007f92:	2b00      	cmp	r3, #0
 8007f94:	d04a      	beq.n	800802c <DMA_CalcDMAMUXRequestGenBaseAndMask+0xac>
 8007f96:	68fb      	ldr	r3, [r7, #12]
 8007f98:	2b08      	cmp	r3, #8
 8007f9a:	d847      	bhi.n	800802c <DMA_CalcDMAMUXRequestGenBaseAndMask+0xac>
  {
    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
 8007f9c:	687b      	ldr	r3, [r7, #4]
 8007f9e:	681b      	ldr	r3, [r3, #0]
 8007fa0:	4a25      	ldr	r2, [pc, #148]	@ (8008038 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xb8>)
 8007fa2:	4293      	cmp	r3, r2
 8007fa4:	d022      	beq.n	8007fec <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 8007fa6:	687b      	ldr	r3, [r7, #4]
 8007fa8:	681b      	ldr	r3, [r3, #0]
 8007faa:	4a24      	ldr	r2, [pc, #144]	@ (800803c <DMA_CalcDMAMUXRequestGenBaseAndMask+0xbc>)
 8007fac:	4293      	cmp	r3, r2
 8007fae:	d01d      	beq.n	8007fec <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 8007fb0:	687b      	ldr	r3, [r7, #4]
 8007fb2:	681b      	ldr	r3, [r3, #0]
 8007fb4:	4a22      	ldr	r2, [pc, #136]	@ (8008040 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xc0>)
 8007fb6:	4293      	cmp	r3, r2
 8007fb8:	d018      	beq.n	8007fec <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 8007fba:	687b      	ldr	r3, [r7, #4]
 8007fbc:	681b      	ldr	r3, [r3, #0]
 8007fbe:	4a21      	ldr	r2, [pc, #132]	@ (8008044 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xc4>)
 8007fc0:	4293      	cmp	r3, r2
 8007fc2:	d013      	beq.n	8007fec <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 8007fc4:	687b      	ldr	r3, [r7, #4]
 8007fc6:	681b      	ldr	r3, [r3, #0]
 8007fc8:	4a1f      	ldr	r2, [pc, #124]	@ (8008048 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xc8>)
 8007fca:	4293      	cmp	r3, r2
 8007fcc:	d00e      	beq.n	8007fec <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 8007fce:	687b      	ldr	r3, [r7, #4]
 8007fd0:	681b      	ldr	r3, [r3, #0]
 8007fd2:	4a1e      	ldr	r2, [pc, #120]	@ (800804c <DMA_CalcDMAMUXRequestGenBaseAndMask+0xcc>)
 8007fd4:	4293      	cmp	r3, r2
 8007fd6:	d009      	beq.n	8007fec <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 8007fd8:	687b      	ldr	r3, [r7, #4]
 8007fda:	681b      	ldr	r3, [r3, #0]
 8007fdc:	4a1c      	ldr	r2, [pc, #112]	@ (8008050 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xd0>)
 8007fde:	4293      	cmp	r3, r2
 8007fe0:	d004      	beq.n	8007fec <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 8007fe2:	687b      	ldr	r3, [r7, #4]
 8007fe4:	681b      	ldr	r3, [r3, #0]
 8007fe6:	4a1b      	ldr	r2, [pc, #108]	@ (8008054 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xd4>)
 8007fe8:	4293      	cmp	r3, r2
 8007fea:	d101      	bne.n	8007ff0 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x70>
 8007fec:	2301      	movs	r3, #1
 8007fee:	e000      	b.n	8007ff2 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x72>
 8007ff0:	2300      	movs	r3, #0
 8007ff2:	2b00      	cmp	r3, #0
 8007ff4:	d00a      	beq.n	800800c <DMA_CalcDMAMUXRequestGenBaseAndMask+0x8c>
    {
      /* BDMA Channels are connected to DMAMUX2 request generator blocks */
      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
 8007ff6:	68fa      	ldr	r2, [r7, #12]
 8007ff8:	4b17      	ldr	r3, [pc, #92]	@ (8008058 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xd8>)
 8007ffa:	4413      	add	r3, r2
 8007ffc:	009b      	lsls	r3, r3, #2
 8007ffe:	461a      	mov	r2, r3
 8008000:	687b      	ldr	r3, [r7, #4]
 8008002:	66da      	str	r2, [r3, #108]	@ 0x6c

      hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;
 8008004:	687b      	ldr	r3, [r7, #4]
 8008006:	4a15      	ldr	r2, [pc, #84]	@ (800805c <DMA_CalcDMAMUXRequestGenBaseAndMask+0xdc>)
 8008008:	671a      	str	r2, [r3, #112]	@ 0x70
 800800a:	e009      	b.n	8008020 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xa0>
    }
    else
    {
      /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */
      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
 800800c:	68fa      	ldr	r2, [r7, #12]
 800800e:	4b14      	ldr	r3, [pc, #80]	@ (8008060 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xe0>)
 8008010:	4413      	add	r3, r2
 8008012:	009b      	lsls	r3, r3, #2
 8008014:	461a      	mov	r2, r3
 8008016:	687b      	ldr	r3, [r7, #4]
 8008018:	66da      	str	r2, [r3, #108]	@ 0x6c

      hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
 800801a:	687b      	ldr	r3, [r7, #4]
 800801c:	4a11      	ldr	r2, [pc, #68]	@ (8008064 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xe4>)
 800801e:	671a      	str	r2, [r3, #112]	@ 0x70
    }

    hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);
 8008020:	68fb      	ldr	r3, [r7, #12]
 8008022:	3b01      	subs	r3, #1
 8008024:	2201      	movs	r2, #1
 8008026:	409a      	lsls	r2, r3
 8008028:	687b      	ldr	r3, [r7, #4]
 800802a:	675a      	str	r2, [r3, #116]	@ 0x74
  }
}
 800802c:	bf00      	nop
 800802e:	3714      	adds	r7, #20
 8008030:	46bd      	mov	sp, r7
 8008032:	f85d 7b04 	ldr.w	r7, [sp], #4
 8008036:	4770      	bx	lr
 8008038:	58025408 	.word	0x58025408
 800803c:	5802541c 	.word	0x5802541c
 8008040:	58025430 	.word	0x58025430
 8008044:	58025444 	.word	0x58025444
 8008048:	58025458 	.word	0x58025458
 800804c:	5802546c 	.word	0x5802546c
 8008050:	58025480 	.word	0x58025480
 8008054:	58025494 	.word	0x58025494
 8008058:	1600963f 	.word	0x1600963f
 800805c:	58025940 	.word	0x58025940
 8008060:	1000823f 	.word	0x1000823f
 8008064:	40020940 	.word	0x40020940

08008068 <HAL_GPIO_Init>:
  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8008068:	b480      	push	{r7}
 800806a:	b089      	sub	sp, #36	@ 0x24
 800806c:	af00      	add	r7, sp, #0
 800806e:	6078      	str	r0, [r7, #4]
 8008070:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00U;
 8008072:	2300      	movs	r3, #0
 8008074:	61fb      	str	r3, [r7, #28]
  EXTI_Core_TypeDef *EXTI_CurrentCPU;

#if defined(DUAL_CORE) && defined(CORE_CM4)
  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
#else
  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
 8008076:	4b89      	ldr	r3, [pc, #548]	@ (800829c <HAL_GPIO_Init+0x234>)
 8008078:	617b      	str	r3, [r7, #20]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0x00U)
 800807a:	e194      	b.n	80083a6 <HAL_GPIO_Init+0x33e>
  {
    /* Get current io position */
    iocurrent = (GPIO_Init->Pin) & (1UL << position);
 800807c:	683b      	ldr	r3, [r7, #0]
 800807e:	681a      	ldr	r2, [r3, #0]
 8008080:	2101      	movs	r1, #1
 8008082:	69fb      	ldr	r3, [r7, #28]
 8008084:	fa01 f303 	lsl.w	r3, r1, r3
 8008088:	4013      	ands	r3, r2
 800808a:	613b      	str	r3, [r7, #16]

    if (iocurrent != 0x00U)
 800808c:	693b      	ldr	r3, [r7, #16]
 800808e:	2b00      	cmp	r3, #0
 8008090:	f000 8186 	beq.w	80083a0 <HAL_GPIO_Init+0x338>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
 8008094:	683b      	ldr	r3, [r7, #0]
 8008096:	685b      	ldr	r3, [r3, #4]
 8008098:	f003 0303 	and.w	r3, r3, #3
 800809c:	2b01      	cmp	r3, #1
 800809e:	d005      	beq.n	80080ac <HAL_GPIO_Init+0x44>
 80080a0:	683b      	ldr	r3, [r7, #0]
 80080a2:	685b      	ldr	r3, [r3, #4]
 80080a4:	f003 0303 	and.w	r3, r3, #3
 80080a8:	2b02      	cmp	r3, #2
 80080aa:	d130      	bne.n	800810e <HAL_GPIO_Init+0xa6>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));

        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR;
 80080ac:	687b      	ldr	r3, [r7, #4]
 80080ae:	689b      	ldr	r3, [r3, #8]
 80080b0:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
 80080b2:	69fb      	ldr	r3, [r7, #28]
 80080b4:	005b      	lsls	r3, r3, #1
 80080b6:	2203      	movs	r2, #3
 80080b8:	fa02 f303 	lsl.w	r3, r2, r3
 80080bc:	43db      	mvns	r3, r3
 80080be:	69ba      	ldr	r2, [r7, #24]
 80080c0:	4013      	ands	r3, r2
 80080c2:	61bb      	str	r3, [r7, #24]
        temp |= (GPIO_Init->Speed << (position * 2U));
 80080c4:	683b      	ldr	r3, [r7, #0]
 80080c6:	68da      	ldr	r2, [r3, #12]
 80080c8:	69fb      	ldr	r3, [r7, #28]
 80080ca:	005b      	lsls	r3, r3, #1
 80080cc:	fa02 f303 	lsl.w	r3, r2, r3
 80080d0:	69ba      	ldr	r2, [r7, #24]
 80080d2:	4313      	orrs	r3, r2
 80080d4:	61bb      	str	r3, [r7, #24]
        GPIOx->OSPEEDR = temp;
 80080d6:	687b      	ldr	r3, [r7, #4]
 80080d8:	69ba      	ldr	r2, [r7, #24]
 80080da:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 80080dc:	687b      	ldr	r3, [r7, #4]
 80080de:	685b      	ldr	r3, [r3, #4]
 80080e0:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OTYPER_OT0 << position) ;
 80080e2:	2201      	movs	r2, #1
 80080e4:	69fb      	ldr	r3, [r7, #28]
 80080e6:	fa02 f303 	lsl.w	r3, r2, r3
 80080ea:	43db      	mvns	r3, r3
 80080ec:	69ba      	ldr	r2, [r7, #24]
 80080ee:	4013      	ands	r3, r2
 80080f0:	61bb      	str	r3, [r7, #24]
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 80080f2:	683b      	ldr	r3, [r7, #0]
 80080f4:	685b      	ldr	r3, [r3, #4]
 80080f6:	091b      	lsrs	r3, r3, #4
 80080f8:	f003 0201 	and.w	r2, r3, #1
 80080fc:	69fb      	ldr	r3, [r7, #28]
 80080fe:	fa02 f303 	lsl.w	r3, r2, r3
 8008102:	69ba      	ldr	r2, [r7, #24]
 8008104:	4313      	orrs	r3, r2
 8008106:	61bb      	str	r3, [r7, #24]
        GPIOx->OTYPER = temp;
 8008108:	687b      	ldr	r3, [r7, #4]
 800810a:	69ba      	ldr	r2, [r7, #24]
 800810c:	605a      	str	r2, [r3, #4]
      }

      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 800810e:	683b      	ldr	r3, [r7, #0]
 8008110:	685b      	ldr	r3, [r3, #4]
 8008112:	f003 0303 	and.w	r3, r3, #3
 8008116:	2b03      	cmp	r3, #3
 8008118:	d017      	beq.n	800814a <HAL_GPIO_Init+0xe2>
      {
       /* Check the Pull parameter */
       assert_param(IS_GPIO_PULL(GPIO_Init->Pull));

      /* Activate the Pull-up or Pull down resistor for the current IO */
      temp = GPIOx->PUPDR;
 800811a:	687b      	ldr	r3, [r7, #4]
 800811c:	68db      	ldr	r3, [r3, #12]
 800811e:	61bb      	str	r3, [r7, #24]
      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
 8008120:	69fb      	ldr	r3, [r7, #28]
 8008122:	005b      	lsls	r3, r3, #1
 8008124:	2203      	movs	r2, #3
 8008126:	fa02 f303 	lsl.w	r3, r2, r3
 800812a:	43db      	mvns	r3, r3
 800812c:	69ba      	ldr	r2, [r7, #24]
 800812e:	4013      	ands	r3, r2
 8008130:	61bb      	str	r3, [r7, #24]
      temp |= ((GPIO_Init->Pull) << (position * 2U));
 8008132:	683b      	ldr	r3, [r7, #0]
 8008134:	689a      	ldr	r2, [r3, #8]
 8008136:	69fb      	ldr	r3, [r7, #28]
 8008138:	005b      	lsls	r3, r3, #1
 800813a:	fa02 f303 	lsl.w	r3, r2, r3
 800813e:	69ba      	ldr	r2, [r7, #24]
 8008140:	4313      	orrs	r3, r2
 8008142:	61bb      	str	r3, [r7, #24]
      GPIOx->PUPDR = temp;
 8008144:	687b      	ldr	r3, [r7, #4]
 8008146:	69ba      	ldr	r2, [r7, #24]
 8008148:	60da      	str	r2, [r3, #12]
      }

      /* In case of Alternate function mode selection */
      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 800814a:	683b      	ldr	r3, [r7, #0]
 800814c:	685b      	ldr	r3, [r3, #4]
 800814e:	f003 0303 	and.w	r3, r3, #3
 8008152:	2b02      	cmp	r3, #2
 8008154:	d123      	bne.n	800819e <HAL_GPIO_Init+0x136>
        /* Check the Alternate function parameters */
        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));

        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3U];
 8008156:	69fb      	ldr	r3, [r7, #28]
 8008158:	08da      	lsrs	r2, r3, #3
 800815a:	687b      	ldr	r3, [r7, #4]
 800815c:	3208      	adds	r2, #8
 800815e:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 8008162:	61bb      	str	r3, [r7, #24]
        temp &= ~(0xFU << ((position & 0x07U) * 4U));
 8008164:	69fb      	ldr	r3, [r7, #28]
 8008166:	f003 0307 	and.w	r3, r3, #7
 800816a:	009b      	lsls	r3, r3, #2
 800816c:	220f      	movs	r2, #15
 800816e:	fa02 f303 	lsl.w	r3, r2, r3
 8008172:	43db      	mvns	r3, r3
 8008174:	69ba      	ldr	r2, [r7, #24]
 8008176:	4013      	ands	r3, r2
 8008178:	61bb      	str	r3, [r7, #24]
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
 800817a:	683b      	ldr	r3, [r7, #0]
 800817c:	691a      	ldr	r2, [r3, #16]
 800817e:	69fb      	ldr	r3, [r7, #28]
 8008180:	f003 0307 	and.w	r3, r3, #7
 8008184:	009b      	lsls	r3, r3, #2
 8008186:	fa02 f303 	lsl.w	r3, r2, r3
 800818a:	69ba      	ldr	r2, [r7, #24]
 800818c:	4313      	orrs	r3, r2
 800818e:	61bb      	str	r3, [r7, #24]
        GPIOx->AFR[position >> 3U] = temp;
 8008190:	69fb      	ldr	r3, [r7, #28]
 8008192:	08da      	lsrs	r2, r3, #3
 8008194:	687b      	ldr	r3, [r7, #4]
 8008196:	3208      	adds	r2, #8
 8008198:	69b9      	ldr	r1, [r7, #24]
 800819a:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 800819e:	687b      	ldr	r3, [r7, #4]
 80081a0:	681b      	ldr	r3, [r3, #0]
 80081a2:	61bb      	str	r3, [r7, #24]
      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
 80081a4:	69fb      	ldr	r3, [r7, #28]
 80081a6:	005b      	lsls	r3, r3, #1
 80081a8:	2203      	movs	r2, #3
 80081aa:	fa02 f303 	lsl.w	r3, r2, r3
 80081ae:	43db      	mvns	r3, r3
 80081b0:	69ba      	ldr	r2, [r7, #24]
 80081b2:	4013      	ands	r3, r2
 80081b4:	61bb      	str	r3, [r7, #24]
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
 80081b6:	683b      	ldr	r3, [r7, #0]
 80081b8:	685b      	ldr	r3, [r3, #4]
 80081ba:	f003 0203 	and.w	r2, r3, #3
 80081be:	69fb      	ldr	r3, [r7, #28]
 80081c0:	005b      	lsls	r3, r3, #1
 80081c2:	fa02 f303 	lsl.w	r3, r2, r3
 80081c6:	69ba      	ldr	r2, [r7, #24]
 80081c8:	4313      	orrs	r3, r2
 80081ca:	61bb      	str	r3, [r7, #24]
      GPIOx->MODER = temp;
 80081cc:	687b      	ldr	r3, [r7, #4]
 80081ce:	69ba      	ldr	r2, [r7, #24]
 80081d0:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
 80081d2:	683b      	ldr	r3, [r7, #0]
 80081d4:	685b      	ldr	r3, [r3, #4]
 80081d6:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 80081da:	2b00      	cmp	r3, #0
 80081dc:	f000 80e0 	beq.w	80083a0 <HAL_GPIO_Init+0x338>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 80081e0:	4b2f      	ldr	r3, [pc, #188]	@ (80082a0 <HAL_GPIO_Init+0x238>)
 80081e2:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 80081e6:	4a2e      	ldr	r2, [pc, #184]	@ (80082a0 <HAL_GPIO_Init+0x238>)
 80081e8:	f043 0302 	orr.w	r3, r3, #2
 80081ec:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
 80081f0:	4b2b      	ldr	r3, [pc, #172]	@ (80082a0 <HAL_GPIO_Init+0x238>)
 80081f2:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 80081f6:	f003 0302 	and.w	r3, r3, #2
 80081fa:	60fb      	str	r3, [r7, #12]
 80081fc:	68fb      	ldr	r3, [r7, #12]

        temp = SYSCFG->EXTICR[position >> 2U];
 80081fe:	4a29      	ldr	r2, [pc, #164]	@ (80082a4 <HAL_GPIO_Init+0x23c>)
 8008200:	69fb      	ldr	r3, [r7, #28]
 8008202:	089b      	lsrs	r3, r3, #2
 8008204:	3302      	adds	r3, #2
 8008206:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 800820a:	61bb      	str	r3, [r7, #24]
        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
 800820c:	69fb      	ldr	r3, [r7, #28]
 800820e:	f003 0303 	and.w	r3, r3, #3
 8008212:	009b      	lsls	r3, r3, #2
 8008214:	220f      	movs	r2, #15
 8008216:	fa02 f303 	lsl.w	r3, r2, r3
 800821a:	43db      	mvns	r3, r3
 800821c:	69ba      	ldr	r2, [r7, #24]
 800821e:	4013      	ands	r3, r2
 8008220:	61bb      	str	r3, [r7, #24]
        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
 8008222:	687b      	ldr	r3, [r7, #4]
 8008224:	4a20      	ldr	r2, [pc, #128]	@ (80082a8 <HAL_GPIO_Init+0x240>)
 8008226:	4293      	cmp	r3, r2
 8008228:	d052      	beq.n	80082d0 <HAL_GPIO_Init+0x268>
 800822a:	687b      	ldr	r3, [r7, #4]
 800822c:	4a1f      	ldr	r2, [pc, #124]	@ (80082ac <HAL_GPIO_Init+0x244>)
 800822e:	4293      	cmp	r3, r2
 8008230:	d031      	beq.n	8008296 <HAL_GPIO_Init+0x22e>
 8008232:	687b      	ldr	r3, [r7, #4]
 8008234:	4a1e      	ldr	r2, [pc, #120]	@ (80082b0 <HAL_GPIO_Init+0x248>)
 8008236:	4293      	cmp	r3, r2
 8008238:	d02b      	beq.n	8008292 <HAL_GPIO_Init+0x22a>
 800823a:	687b      	ldr	r3, [r7, #4]
 800823c:	4a1d      	ldr	r2, [pc, #116]	@ (80082b4 <HAL_GPIO_Init+0x24c>)
 800823e:	4293      	cmp	r3, r2
 8008240:	d025      	beq.n	800828e <HAL_GPIO_Init+0x226>
 8008242:	687b      	ldr	r3, [r7, #4]
 8008244:	4a1c      	ldr	r2, [pc, #112]	@ (80082b8 <HAL_GPIO_Init+0x250>)
 8008246:	4293      	cmp	r3, r2
 8008248:	d01f      	beq.n	800828a <HAL_GPIO_Init+0x222>
 800824a:	687b      	ldr	r3, [r7, #4]
 800824c:	4a1b      	ldr	r2, [pc, #108]	@ (80082bc <HAL_GPIO_Init+0x254>)
 800824e:	4293      	cmp	r3, r2
 8008250:	d019      	beq.n	8008286 <HAL_GPIO_Init+0x21e>
 8008252:	687b      	ldr	r3, [r7, #4]
 8008254:	4a1a      	ldr	r2, [pc, #104]	@ (80082c0 <HAL_GPIO_Init+0x258>)
 8008256:	4293      	cmp	r3, r2
 8008258:	d013      	beq.n	8008282 <HAL_GPIO_Init+0x21a>
 800825a:	687b      	ldr	r3, [r7, #4]
 800825c:	4a19      	ldr	r2, [pc, #100]	@ (80082c4 <HAL_GPIO_Init+0x25c>)
 800825e:	4293      	cmp	r3, r2
 8008260:	d00d      	beq.n	800827e <HAL_GPIO_Init+0x216>
 8008262:	687b      	ldr	r3, [r7, #4]
 8008264:	4a18      	ldr	r2, [pc, #96]	@ (80082c8 <HAL_GPIO_Init+0x260>)
 8008266:	4293      	cmp	r3, r2
 8008268:	d007      	beq.n	800827a <HAL_GPIO_Init+0x212>
 800826a:	687b      	ldr	r3, [r7, #4]
 800826c:	4a17      	ldr	r2, [pc, #92]	@ (80082cc <HAL_GPIO_Init+0x264>)
 800826e:	4293      	cmp	r3, r2
 8008270:	d101      	bne.n	8008276 <HAL_GPIO_Init+0x20e>
 8008272:	2309      	movs	r3, #9
 8008274:	e02d      	b.n	80082d2 <HAL_GPIO_Init+0x26a>
 8008276:	230a      	movs	r3, #10
 8008278:	e02b      	b.n	80082d2 <HAL_GPIO_Init+0x26a>
 800827a:	2308      	movs	r3, #8
 800827c:	e029      	b.n	80082d2 <HAL_GPIO_Init+0x26a>
 800827e:	2307      	movs	r3, #7
 8008280:	e027      	b.n	80082d2 <HAL_GPIO_Init+0x26a>
 8008282:	2306      	movs	r3, #6
 8008284:	e025      	b.n	80082d2 <HAL_GPIO_Init+0x26a>
 8008286:	2305      	movs	r3, #5
 8008288:	e023      	b.n	80082d2 <HAL_GPIO_Init+0x26a>
 800828a:	2304      	movs	r3, #4
 800828c:	e021      	b.n	80082d2 <HAL_GPIO_Init+0x26a>
 800828e:	2303      	movs	r3, #3
 8008290:	e01f      	b.n	80082d2 <HAL_GPIO_Init+0x26a>
 8008292:	2302      	movs	r3, #2
 8008294:	e01d      	b.n	80082d2 <HAL_GPIO_Init+0x26a>
 8008296:	2301      	movs	r3, #1
 8008298:	e01b      	b.n	80082d2 <HAL_GPIO_Init+0x26a>
 800829a:	bf00      	nop
 800829c:	58000080 	.word	0x58000080
 80082a0:	58024400 	.word	0x58024400
 80082a4:	58000400 	.word	0x58000400
 80082a8:	58020000 	.word	0x58020000
 80082ac:	58020400 	.word	0x58020400
 80082b0:	58020800 	.word	0x58020800
 80082b4:	58020c00 	.word	0x58020c00
 80082b8:	58021000 	.word	0x58021000
 80082bc:	58021400 	.word	0x58021400
 80082c0:	58021800 	.word	0x58021800
 80082c4:	58021c00 	.word	0x58021c00
 80082c8:	58022000 	.word	0x58022000
 80082cc:	58022400 	.word	0x58022400
 80082d0:	2300      	movs	r3, #0
 80082d2:	69fa      	ldr	r2, [r7, #28]
 80082d4:	f002 0203 	and.w	r2, r2, #3
 80082d8:	0092      	lsls	r2, r2, #2
 80082da:	4093      	lsls	r3, r2
 80082dc:	69ba      	ldr	r2, [r7, #24]
 80082de:	4313      	orrs	r3, r2
 80082e0:	61bb      	str	r3, [r7, #24]
        SYSCFG->EXTICR[position >> 2U] = temp;
 80082e2:	4938      	ldr	r1, [pc, #224]	@ (80083c4 <HAL_GPIO_Init+0x35c>)
 80082e4:	69fb      	ldr	r3, [r7, #28]
 80082e6:	089b      	lsrs	r3, r3, #2
 80082e8:	3302      	adds	r3, #2
 80082ea:	69ba      	ldr	r2, [r7, #24]
 80082ec:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR1;
 80082f0:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 80082f4:	681b      	ldr	r3, [r3, #0]
 80082f6:	61bb      	str	r3, [r7, #24]
        temp &= ~(iocurrent);
 80082f8:	693b      	ldr	r3, [r7, #16]
 80082fa:	43db      	mvns	r3, r3
 80082fc:	69ba      	ldr	r2, [r7, #24]
 80082fe:	4013      	ands	r3, r2
 8008300:	61bb      	str	r3, [r7, #24]
        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
 8008302:	683b      	ldr	r3, [r7, #0]
 8008304:	685b      	ldr	r3, [r3, #4]
 8008306:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
 800830a:	2b00      	cmp	r3, #0
 800830c:	d003      	beq.n	8008316 <HAL_GPIO_Init+0x2ae>
        {
          temp |= iocurrent;
 800830e:	69ba      	ldr	r2, [r7, #24]
 8008310:	693b      	ldr	r3, [r7, #16]
 8008312:	4313      	orrs	r3, r2
 8008314:	61bb      	str	r3, [r7, #24]
        }
        EXTI->RTSR1 = temp;
 8008316:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800831a:	69bb      	ldr	r3, [r7, #24]
 800831c:	6013      	str	r3, [r2, #0]

        temp = EXTI->FTSR1;
 800831e:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8008322:	685b      	ldr	r3, [r3, #4]
 8008324:	61bb      	str	r3, [r7, #24]
        temp &= ~(iocurrent);
 8008326:	693b      	ldr	r3, [r7, #16]
 8008328:	43db      	mvns	r3, r3
 800832a:	69ba      	ldr	r2, [r7, #24]
 800832c:	4013      	ands	r3, r2
 800832e:	61bb      	str	r3, [r7, #24]
        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
 8008330:	683b      	ldr	r3, [r7, #0]
 8008332:	685b      	ldr	r3, [r3, #4]
 8008334:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
 8008338:	2b00      	cmp	r3, #0
 800833a:	d003      	beq.n	8008344 <HAL_GPIO_Init+0x2dc>
        {
          temp |= iocurrent;
 800833c:	69ba      	ldr	r2, [r7, #24]
 800833e:	693b      	ldr	r3, [r7, #16]
 8008340:	4313      	orrs	r3, r2
 8008342:	61bb      	str	r3, [r7, #24]
        }
        EXTI->FTSR1 = temp;
 8008344:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 8008348:	69bb      	ldr	r3, [r7, #24]
 800834a:	6053      	str	r3, [r2, #4]

        temp = EXTI_CurrentCPU->EMR1;
 800834c:	697b      	ldr	r3, [r7, #20]
 800834e:	685b      	ldr	r3, [r3, #4]
 8008350:	61bb      	str	r3, [r7, #24]
        temp &= ~(iocurrent);
 8008352:	693b      	ldr	r3, [r7, #16]
 8008354:	43db      	mvns	r3, r3
 8008356:	69ba      	ldr	r2, [r7, #24]
 8008358:	4013      	ands	r3, r2
 800835a:	61bb      	str	r3, [r7, #24]
        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
 800835c:	683b      	ldr	r3, [r7, #0]
 800835e:	685b      	ldr	r3, [r3, #4]
 8008360:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8008364:	2b00      	cmp	r3, #0
 8008366:	d003      	beq.n	8008370 <HAL_GPIO_Init+0x308>
        {
          temp |= iocurrent;
 8008368:	69ba      	ldr	r2, [r7, #24]
 800836a:	693b      	ldr	r3, [r7, #16]
 800836c:	4313      	orrs	r3, r2
 800836e:	61bb      	str	r3, [r7, #24]
        }
        EXTI_CurrentCPU->EMR1 = temp;
 8008370:	697b      	ldr	r3, [r7, #20]
 8008372:	69ba      	ldr	r2, [r7, #24]
 8008374:	605a      	str	r2, [r3, #4]

        /* Clear EXTI line configuration */
        temp = EXTI_CurrentCPU->IMR1;
 8008376:	697b      	ldr	r3, [r7, #20]
 8008378:	681b      	ldr	r3, [r3, #0]
 800837a:	61bb      	str	r3, [r7, #24]
        temp &= ~(iocurrent);
 800837c:	693b      	ldr	r3, [r7, #16]
 800837e:	43db      	mvns	r3, r3
 8008380:	69ba      	ldr	r2, [r7, #24]
 8008382:	4013      	ands	r3, r2
 8008384:	61bb      	str	r3, [r7, #24]
        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
 8008386:	683b      	ldr	r3, [r7, #0]
 8008388:	685b      	ldr	r3, [r3, #4]
 800838a:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 800838e:	2b00      	cmp	r3, #0
 8008390:	d003      	beq.n	800839a <HAL_GPIO_Init+0x332>
        {
          temp |= iocurrent;
 8008392:	69ba      	ldr	r2, [r7, #24]
 8008394:	693b      	ldr	r3, [r7, #16]
 8008396:	4313      	orrs	r3, r2
 8008398:	61bb      	str	r3, [r7, #24]
        }
        EXTI_CurrentCPU->IMR1 = temp;
 800839a:	697b      	ldr	r3, [r7, #20]
 800839c:	69ba      	ldr	r2, [r7, #24]
 800839e:	601a      	str	r2, [r3, #0]
      }
    }

    position++;
 80083a0:	69fb      	ldr	r3, [r7, #28]
 80083a2:	3301      	adds	r3, #1
 80083a4:	61fb      	str	r3, [r7, #28]
  while (((GPIO_Init->Pin) >> position) != 0x00U)
 80083a6:	683b      	ldr	r3, [r7, #0]
 80083a8:	681a      	ldr	r2, [r3, #0]
 80083aa:	69fb      	ldr	r3, [r7, #28]
 80083ac:	fa22 f303 	lsr.w	r3, r2, r3
 80083b0:	2b00      	cmp	r3, #0
 80083b2:	f47f ae63 	bne.w	800807c <HAL_GPIO_Init+0x14>
  }
}
 80083b6:	bf00      	nop
 80083b8:	bf00      	nop
 80083ba:	3724      	adds	r7, #36	@ 0x24
 80083bc:	46bd      	mov	sp, r7
 80083be:	f85d 7b04 	ldr.w	r7, [sp], #4
 80083c2:	4770      	bx	lr
 80083c4:	58000400 	.word	0x58000400

080083c8 <HAL_GPIO_WritePin>:
  *            @arg GPIO_PIN_RESET: to clear the port pin
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
 80083c8:	b480      	push	{r7}
 80083ca:	b083      	sub	sp, #12
 80083cc:	af00      	add	r7, sp, #0
 80083ce:	6078      	str	r0, [r7, #4]
 80083d0:	460b      	mov	r3, r1
 80083d2:	807b      	strh	r3, [r7, #2]
 80083d4:	4613      	mov	r3, r2
 80083d6:	707b      	strb	r3, [r7, #1]
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 80083d8:	787b      	ldrb	r3, [r7, #1]
 80083da:	2b00      	cmp	r3, #0
 80083dc:	d003      	beq.n	80083e6 <HAL_GPIO_WritePin+0x1e>
  {
    GPIOx->BSRR = GPIO_Pin;
 80083de:	887a      	ldrh	r2, [r7, #2]
 80083e0:	687b      	ldr	r3, [r7, #4]
 80083e2:	619a      	str	r2, [r3, #24]
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
  }
}
 80083e4:	e003      	b.n	80083ee <HAL_GPIO_WritePin+0x26>
    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
 80083e6:	887b      	ldrh	r3, [r7, #2]
 80083e8:	041a      	lsls	r2, r3, #16
 80083ea:	687b      	ldr	r3, [r7, #4]
 80083ec:	619a      	str	r2, [r3, #24]
}
 80083ee:	bf00      	nop
 80083f0:	370c      	adds	r7, #12
 80083f2:	46bd      	mov	sp, r7
 80083f4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80083f8:	4770      	bx	lr

080083fa <HAL_GPIO_TogglePin>:
  * @param  GPIOx: Where x can be (A..K) to select the GPIO peripheral.
  * @param  GPIO_Pin: Specifies the pins to be toggled.
  * @retval None
  */
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
 80083fa:	b480      	push	{r7}
 80083fc:	b085      	sub	sp, #20
 80083fe:	af00      	add	r7, sp, #0
 8008400:	6078      	str	r0, [r7, #4]
 8008402:	460b      	mov	r3, r1
 8008404:	807b      	strh	r3, [r7, #2]

  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  /* get current Output Data Register value */
  odr = GPIOx->ODR;
 8008406:	687b      	ldr	r3, [r7, #4]
 8008408:	695b      	ldr	r3, [r3, #20]
 800840a:	60fb      	str	r3, [r7, #12]

  /* Set selected pins that were at low level, and reset ones that were high */
  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
 800840c:	887a      	ldrh	r2, [r7, #2]
 800840e:	68fb      	ldr	r3, [r7, #12]
 8008410:	4013      	ands	r3, r2
 8008412:	041a      	lsls	r2, r3, #16
 8008414:	68fb      	ldr	r3, [r7, #12]
 8008416:	43d9      	mvns	r1, r3
 8008418:	887b      	ldrh	r3, [r7, #2]
 800841a:	400b      	ands	r3, r1
 800841c:	431a      	orrs	r2, r3
 800841e:	687b      	ldr	r3, [r7, #4]
 8008420:	619a      	str	r2, [r3, #24]
}
 8008422:	bf00      	nop
 8008424:	3714      	adds	r7, #20
 8008426:	46bd      	mov	sp, r7
 8008428:	f85d 7b04 	ldr.w	r7, [sp], #4
 800842c:	4770      	bx	lr
	...

08008430 <HAL_PWREx_ConfigSupply>:
  *         PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
  *         regulator.
  * @retval HAL status.
  */
HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
{
 8008430:	b580      	push	{r7, lr}
 8008432:	b084      	sub	sp, #16
 8008434:	af00      	add	r7, sp, #0
 8008436:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param (IS_PWR_SUPPLY (SupplySource));

  /* Check if supply source was configured */
#if defined (PWR_FLAG_SCUEN)
  if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
 8008438:	4b19      	ldr	r3, [pc, #100]	@ (80084a0 <HAL_PWREx_ConfigSupply+0x70>)
 800843a:	68db      	ldr	r3, [r3, #12]
 800843c:	f003 0304 	and.w	r3, r3, #4
 8008440:	2b04      	cmp	r3, #4
 8008442:	d00a      	beq.n	800845a <HAL_PWREx_ConfigSupply+0x2a>
#else
  if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
#endif /* defined (PWR_FLAG_SCUEN) */
  {
    /* Check supply configuration */
    if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
 8008444:	4b16      	ldr	r3, [pc, #88]	@ (80084a0 <HAL_PWREx_ConfigSupply+0x70>)
 8008446:	68db      	ldr	r3, [r3, #12]
 8008448:	f003 0307 	and.w	r3, r3, #7
 800844c:	687a      	ldr	r2, [r7, #4]
 800844e:	429a      	cmp	r2, r3
 8008450:	d001      	beq.n	8008456 <HAL_PWREx_ConfigSupply+0x26>
    {
      /* Supply configuration update locked, can't apply a new supply config */
      return HAL_ERROR;
 8008452:	2301      	movs	r3, #1
 8008454:	e01f      	b.n	8008496 <HAL_PWREx_ConfigSupply+0x66>
    else
    {
      /* Supply configuration update locked, but new supply configuration
         matches with old supply configuration : nothing to do
      */
      return HAL_OK;
 8008456:	2300      	movs	r3, #0
 8008458:	e01d      	b.n	8008496 <HAL_PWREx_ConfigSupply+0x66>
    }
  }

  /* Set the power supply configuration */
  MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
 800845a:	4b11      	ldr	r3, [pc, #68]	@ (80084a0 <HAL_PWREx_ConfigSupply+0x70>)
 800845c:	68db      	ldr	r3, [r3, #12]
 800845e:	f023 0207 	bic.w	r2, r3, #7
 8008462:	490f      	ldr	r1, [pc, #60]	@ (80084a0 <HAL_PWREx_ConfigSupply+0x70>)
 8008464:	687b      	ldr	r3, [r7, #4]
 8008466:	4313      	orrs	r3, r2
 8008468:	60cb      	str	r3, [r1, #12]

  /* Get tick */
  tickstart = HAL_GetTick ();
 800846a:	f7fb f82b 	bl	80034c4 <HAL_GetTick>
 800846e:	60f8      	str	r0, [r7, #12]

  /* Wait till voltage level flag is set */
  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
 8008470:	e009      	b.n	8008486 <HAL_PWREx_ConfigSupply+0x56>
  {
    if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
 8008472:	f7fb f827 	bl	80034c4 <HAL_GetTick>
 8008476:	4602      	mov	r2, r0
 8008478:	68fb      	ldr	r3, [r7, #12]
 800847a:	1ad3      	subs	r3, r2, r3
 800847c:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
 8008480:	d901      	bls.n	8008486 <HAL_PWREx_ConfigSupply+0x56>
    {
      return HAL_ERROR;
 8008482:	2301      	movs	r3, #1
 8008484:	e007      	b.n	8008496 <HAL_PWREx_ConfigSupply+0x66>
  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
 8008486:	4b06      	ldr	r3, [pc, #24]	@ (80084a0 <HAL_PWREx_ConfigSupply+0x70>)
 8008488:	685b      	ldr	r3, [r3, #4]
 800848a:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 800848e:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 8008492:	d1ee      	bne.n	8008472 <HAL_PWREx_ConfigSupply+0x42>
      }
    }
  }
#endif /* defined (SMPS) */

  return HAL_OK;
 8008494:	2300      	movs	r3, #0
}
 8008496:	4618      	mov	r0, r3
 8008498:	3710      	adds	r7, #16
 800849a:	46bd      	mov	sp, r7
 800849c:	bd80      	pop	{r7, pc}
 800849e:	bf00      	nop
 80084a0:	58024800 	.word	0x58024800

080084a4 <HAL_RCC_OscConfig>:
  *         supported by this function. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 80084a4:	b580      	push	{r7, lr}
 80084a6:	b08c      	sub	sp, #48	@ 0x30
 80084a8:	af00      	add	r7, sp, #0
 80084aa:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  uint32_t temp1_pllckcfg, temp2_pllckcfg;

  /* Check Null pointer */
  if (RCC_OscInitStruct == NULL)
 80084ac:	687b      	ldr	r3, [r7, #4]
 80084ae:	2b00      	cmp	r3, #0
 80084b0:	d102      	bne.n	80084b8 <HAL_RCC_OscConfig+0x14>
  {
    return HAL_ERROR;
 80084b2:	2301      	movs	r3, #1
 80084b4:	f000 bc48 	b.w	8008d48 <HAL_RCC_OscConfig+0x8a4>
  }

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  /*------------------------------- HSE Configuration ------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 80084b8:	687b      	ldr	r3, [r7, #4]
 80084ba:	681b      	ldr	r3, [r3, #0]
 80084bc:	f003 0301 	and.w	r3, r3, #1
 80084c0:	2b00      	cmp	r3, #0
 80084c2:	f000 8088 	beq.w	80085d6 <HAL_RCC_OscConfig+0x132>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
 80084c6:	4b99      	ldr	r3, [pc, #612]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 80084c8:	691b      	ldr	r3, [r3, #16]
 80084ca:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 80084ce:	62fb      	str	r3, [r7, #44]	@ 0x2c
    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
 80084d0:	4b96      	ldr	r3, [pc, #600]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 80084d2:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 80084d4:	62bb      	str	r3, [r7, #40]	@ 0x28
    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
    if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
 80084d6:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80084d8:	2b10      	cmp	r3, #16
 80084da:	d007      	beq.n	80084ec <HAL_RCC_OscConfig+0x48>
 80084dc:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80084de:	2b18      	cmp	r3, #24
 80084e0:	d111      	bne.n	8008506 <HAL_RCC_OscConfig+0x62>
 80084e2:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80084e4:	f003 0303 	and.w	r3, r3, #3
 80084e8:	2b02      	cmp	r3, #2
 80084ea:	d10c      	bne.n	8008506 <HAL_RCC_OscConfig+0x62>
    {
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 80084ec:	4b8f      	ldr	r3, [pc, #572]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 80084ee:	681b      	ldr	r3, [r3, #0]
 80084f0:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 80084f4:	2b00      	cmp	r3, #0
 80084f6:	d06d      	beq.n	80085d4 <HAL_RCC_OscConfig+0x130>
 80084f8:	687b      	ldr	r3, [r7, #4]
 80084fa:	685b      	ldr	r3, [r3, #4]
 80084fc:	2b00      	cmp	r3, #0
 80084fe:	d169      	bne.n	80085d4 <HAL_RCC_OscConfig+0x130>
      {
        return HAL_ERROR;
 8008500:	2301      	movs	r3, #1
 8008502:	f000 bc21 	b.w	8008d48 <HAL_RCC_OscConfig+0x8a4>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8008506:	687b      	ldr	r3, [r7, #4]
 8008508:	685b      	ldr	r3, [r3, #4]
 800850a:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800850e:	d106      	bne.n	800851e <HAL_RCC_OscConfig+0x7a>
 8008510:	4b86      	ldr	r3, [pc, #536]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008512:	681b      	ldr	r3, [r3, #0]
 8008514:	4a85      	ldr	r2, [pc, #532]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008516:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800851a:	6013      	str	r3, [r2, #0]
 800851c:	e02e      	b.n	800857c <HAL_RCC_OscConfig+0xd8>
 800851e:	687b      	ldr	r3, [r7, #4]
 8008520:	685b      	ldr	r3, [r3, #4]
 8008522:	2b00      	cmp	r3, #0
 8008524:	d10c      	bne.n	8008540 <HAL_RCC_OscConfig+0x9c>
 8008526:	4b81      	ldr	r3, [pc, #516]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008528:	681b      	ldr	r3, [r3, #0]
 800852a:	4a80      	ldr	r2, [pc, #512]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 800852c:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 8008530:	6013      	str	r3, [r2, #0]
 8008532:	4b7e      	ldr	r3, [pc, #504]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008534:	681b      	ldr	r3, [r3, #0]
 8008536:	4a7d      	ldr	r2, [pc, #500]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008538:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
 800853c:	6013      	str	r3, [r2, #0]
 800853e:	e01d      	b.n	800857c <HAL_RCC_OscConfig+0xd8>
 8008540:	687b      	ldr	r3, [r7, #4]
 8008542:	685b      	ldr	r3, [r3, #4]
 8008544:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 8008548:	d10c      	bne.n	8008564 <HAL_RCC_OscConfig+0xc0>
 800854a:	4b78      	ldr	r3, [pc, #480]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 800854c:	681b      	ldr	r3, [r3, #0]
 800854e:	4a77      	ldr	r2, [pc, #476]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008550:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
 8008554:	6013      	str	r3, [r2, #0]
 8008556:	4b75      	ldr	r3, [pc, #468]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008558:	681b      	ldr	r3, [r3, #0]
 800855a:	4a74      	ldr	r2, [pc, #464]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 800855c:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 8008560:	6013      	str	r3, [r2, #0]
 8008562:	e00b      	b.n	800857c <HAL_RCC_OscConfig+0xd8>
 8008564:	4b71      	ldr	r3, [pc, #452]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008566:	681b      	ldr	r3, [r3, #0]
 8008568:	4a70      	ldr	r2, [pc, #448]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 800856a:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800856e:	6013      	str	r3, [r2, #0]
 8008570:	4b6e      	ldr	r3, [pc, #440]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008572:	681b      	ldr	r3, [r3, #0]
 8008574:	4a6d      	ldr	r2, [pc, #436]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008576:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
 800857a:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 800857c:	687b      	ldr	r3, [r7, #4]
 800857e:	685b      	ldr	r3, [r3, #4]
 8008580:	2b00      	cmp	r3, #0
 8008582:	d013      	beq.n	80085ac <HAL_RCC_OscConfig+0x108>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8008584:	f7fa ff9e 	bl	80034c4 <HAL_GetTick>
 8008588:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till HSE is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 800858a:	e008      	b.n	800859e <HAL_RCC_OscConfig+0xfa>
        {
          if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 800858c:	f7fa ff9a 	bl	80034c4 <HAL_GetTick>
 8008590:	4602      	mov	r2, r0
 8008592:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008594:	1ad3      	subs	r3, r2, r3
 8008596:	2b64      	cmp	r3, #100	@ 0x64
 8008598:	d901      	bls.n	800859e <HAL_RCC_OscConfig+0xfa>
          {
            return HAL_TIMEOUT;
 800859a:	2303      	movs	r3, #3
 800859c:	e3d4      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 800859e:	4b63      	ldr	r3, [pc, #396]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 80085a0:	681b      	ldr	r3, [r3, #0]
 80085a2:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 80085a6:	2b00      	cmp	r3, #0
 80085a8:	d0f0      	beq.n	800858c <HAL_RCC_OscConfig+0xe8>
 80085aa:	e014      	b.n	80085d6 <HAL_RCC_OscConfig+0x132>
        }
      }
      else
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80085ac:	f7fa ff8a 	bl	80034c4 <HAL_GetTick>
 80085b0:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till HSE is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
 80085b2:	e008      	b.n	80085c6 <HAL_RCC_OscConfig+0x122>
        {
          if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 80085b4:	f7fa ff86 	bl	80034c4 <HAL_GetTick>
 80085b8:	4602      	mov	r2, r0
 80085ba:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80085bc:	1ad3      	subs	r3, r2, r3
 80085be:	2b64      	cmp	r3, #100	@ 0x64
 80085c0:	d901      	bls.n	80085c6 <HAL_RCC_OscConfig+0x122>
          {
            return HAL_TIMEOUT;
 80085c2:	2303      	movs	r3, #3
 80085c4:	e3c0      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
 80085c6:	4b59      	ldr	r3, [pc, #356]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 80085c8:	681b      	ldr	r3, [r3, #0]
 80085ca:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 80085ce:	2b00      	cmp	r3, #0
 80085d0:	d1f0      	bne.n	80085b4 <HAL_RCC_OscConfig+0x110>
 80085d2:	e000      	b.n	80085d6 <HAL_RCC_OscConfig+0x132>
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 80085d4:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 80085d6:	687b      	ldr	r3, [r7, #4]
 80085d8:	681b      	ldr	r3, [r3, #0]
 80085da:	f003 0302 	and.w	r3, r3, #2
 80085de:	2b00      	cmp	r3, #0
 80085e0:	f000 80ca 	beq.w	8008778 <HAL_RCC_OscConfig+0x2d4>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* When the HSI is used as system clock it will not be disabled */
    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
 80085e4:	4b51      	ldr	r3, [pc, #324]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 80085e6:	691b      	ldr	r3, [r3, #16]
 80085e8:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 80085ec:	623b      	str	r3, [r7, #32]
    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
 80085ee:	4b4f      	ldr	r3, [pc, #316]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 80085f0:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 80085f2:	61fb      	str	r3, [r7, #28]
    if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
 80085f4:	6a3b      	ldr	r3, [r7, #32]
 80085f6:	2b00      	cmp	r3, #0
 80085f8:	d007      	beq.n	800860a <HAL_RCC_OscConfig+0x166>
 80085fa:	6a3b      	ldr	r3, [r7, #32]
 80085fc:	2b18      	cmp	r3, #24
 80085fe:	d156      	bne.n	80086ae <HAL_RCC_OscConfig+0x20a>
 8008600:	69fb      	ldr	r3, [r7, #28]
 8008602:	f003 0303 	and.w	r3, r3, #3
 8008606:	2b00      	cmp	r3, #0
 8008608:	d151      	bne.n	80086ae <HAL_RCC_OscConfig+0x20a>
    {
      /* When HSI is used as system clock it will not be disabled */
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 800860a:	4b48      	ldr	r3, [pc, #288]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 800860c:	681b      	ldr	r3, [r3, #0]
 800860e:	f003 0304 	and.w	r3, r3, #4
 8008612:	2b00      	cmp	r3, #0
 8008614:	d005      	beq.n	8008622 <HAL_RCC_OscConfig+0x17e>
 8008616:	687b      	ldr	r3, [r7, #4]
 8008618:	68db      	ldr	r3, [r3, #12]
 800861a:	2b00      	cmp	r3, #0
 800861c:	d101      	bne.n	8008622 <HAL_RCC_OscConfig+0x17e>
      {
        return HAL_ERROR;
 800861e:	2301      	movs	r3, #1
 8008620:	e392      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
      }
      /* Otherwise, only HSI division and calibration are allowed */
      else
      {
        /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */
        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
 8008622:	4b42      	ldr	r3, [pc, #264]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008624:	681b      	ldr	r3, [r3, #0]
 8008626:	f023 0219 	bic.w	r2, r3, #25
 800862a:	687b      	ldr	r3, [r7, #4]
 800862c:	68db      	ldr	r3, [r3, #12]
 800862e:	493f      	ldr	r1, [pc, #252]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008630:	4313      	orrs	r3, r2
 8008632:	600b      	str	r3, [r1, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8008634:	f7fa ff46 	bl	80034c4 <HAL_GetTick>
 8008638:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till HSI is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 800863a:	e008      	b.n	800864e <HAL_RCC_OscConfig+0x1aa>
        {
          if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 800863c:	f7fa ff42 	bl	80034c4 <HAL_GetTick>
 8008640:	4602      	mov	r2, r0
 8008642:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008644:	1ad3      	subs	r3, r2, r3
 8008646:	2b02      	cmp	r3, #2
 8008648:	d901      	bls.n	800864e <HAL_RCC_OscConfig+0x1aa>
          {
            return HAL_TIMEOUT;
 800864a:	2303      	movs	r3, #3
 800864c:	e37c      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 800864e:	4b37      	ldr	r3, [pc, #220]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008650:	681b      	ldr	r3, [r3, #0]
 8008652:	f003 0304 	and.w	r3, r3, #4
 8008656:	2b00      	cmp	r3, #0
 8008658:	d0f0      	beq.n	800863c <HAL_RCC_OscConfig+0x198>
          }
        }
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 800865a:	f7fa ff3f 	bl	80034dc <HAL_GetREVID>
 800865e:	4603      	mov	r3, r0
 8008660:	f241 0203 	movw	r2, #4099	@ 0x1003
 8008664:	4293      	cmp	r3, r2
 8008666:	d817      	bhi.n	8008698 <HAL_RCC_OscConfig+0x1f4>
 8008668:	687b      	ldr	r3, [r7, #4]
 800866a:	691b      	ldr	r3, [r3, #16]
 800866c:	2b40      	cmp	r3, #64	@ 0x40
 800866e:	d108      	bne.n	8008682 <HAL_RCC_OscConfig+0x1de>
 8008670:	4b2e      	ldr	r3, [pc, #184]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008672:	685b      	ldr	r3, [r3, #4]
 8008674:	f423 337c 	bic.w	r3, r3, #258048	@ 0x3f000
 8008678:	4a2c      	ldr	r2, [pc, #176]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 800867a:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800867e:	6053      	str	r3, [r2, #4]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 8008680:	e07a      	b.n	8008778 <HAL_RCC_OscConfig+0x2d4>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8008682:	4b2a      	ldr	r3, [pc, #168]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008684:	685b      	ldr	r3, [r3, #4]
 8008686:	f423 327c 	bic.w	r2, r3, #258048	@ 0x3f000
 800868a:	687b      	ldr	r3, [r7, #4]
 800868c:	691b      	ldr	r3, [r3, #16]
 800868e:	031b      	lsls	r3, r3, #12
 8008690:	4926      	ldr	r1, [pc, #152]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008692:	4313      	orrs	r3, r2
 8008694:	604b      	str	r3, [r1, #4]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 8008696:	e06f      	b.n	8008778 <HAL_RCC_OscConfig+0x2d4>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8008698:	4b24      	ldr	r3, [pc, #144]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 800869a:	685b      	ldr	r3, [r3, #4]
 800869c:	f023 42fe 	bic.w	r2, r3, #2130706432	@ 0x7f000000
 80086a0:	687b      	ldr	r3, [r7, #4]
 80086a2:	691b      	ldr	r3, [r3, #16]
 80086a4:	061b      	lsls	r3, r3, #24
 80086a6:	4921      	ldr	r1, [pc, #132]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 80086a8:	4313      	orrs	r3, r2
 80086aa:	604b      	str	r3, [r1, #4]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 80086ac:	e064      	b.n	8008778 <HAL_RCC_OscConfig+0x2d4>
    }

    else
    {
      /* Check the HSI State */
      if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
 80086ae:	687b      	ldr	r3, [r7, #4]
 80086b0:	68db      	ldr	r3, [r3, #12]
 80086b2:	2b00      	cmp	r3, #0
 80086b4:	d047      	beq.n	8008746 <HAL_RCC_OscConfig+0x2a2>
      {
        /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
 80086b6:	4b1d      	ldr	r3, [pc, #116]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 80086b8:	681b      	ldr	r3, [r3, #0]
 80086ba:	f023 0219 	bic.w	r2, r3, #25
 80086be:	687b      	ldr	r3, [r7, #4]
 80086c0:	68db      	ldr	r3, [r3, #12]
 80086c2:	491a      	ldr	r1, [pc, #104]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 80086c4:	4313      	orrs	r3, r2
 80086c6:	600b      	str	r3, [r1, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80086c8:	f7fa fefc 	bl	80034c4 <HAL_GetTick>
 80086cc:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till HSI is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 80086ce:	e008      	b.n	80086e2 <HAL_RCC_OscConfig+0x23e>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 80086d0:	f7fa fef8 	bl	80034c4 <HAL_GetTick>
 80086d4:	4602      	mov	r2, r0
 80086d6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80086d8:	1ad3      	subs	r3, r2, r3
 80086da:	2b02      	cmp	r3, #2
 80086dc:	d901      	bls.n	80086e2 <HAL_RCC_OscConfig+0x23e>
          {
            return HAL_TIMEOUT;
 80086de:	2303      	movs	r3, #3
 80086e0:	e332      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 80086e2:	4b12      	ldr	r3, [pc, #72]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 80086e4:	681b      	ldr	r3, [r3, #0]
 80086e6:	f003 0304 	and.w	r3, r3, #4
 80086ea:	2b00      	cmp	r3, #0
 80086ec:	d0f0      	beq.n	80086d0 <HAL_RCC_OscConfig+0x22c>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80086ee:	f7fa fef5 	bl	80034dc <HAL_GetREVID>
 80086f2:	4603      	mov	r3, r0
 80086f4:	f241 0203 	movw	r2, #4099	@ 0x1003
 80086f8:	4293      	cmp	r3, r2
 80086fa:	d819      	bhi.n	8008730 <HAL_RCC_OscConfig+0x28c>
 80086fc:	687b      	ldr	r3, [r7, #4]
 80086fe:	691b      	ldr	r3, [r3, #16]
 8008700:	2b40      	cmp	r3, #64	@ 0x40
 8008702:	d108      	bne.n	8008716 <HAL_RCC_OscConfig+0x272>
 8008704:	4b09      	ldr	r3, [pc, #36]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008706:	685b      	ldr	r3, [r3, #4]
 8008708:	f423 337c 	bic.w	r3, r3, #258048	@ 0x3f000
 800870c:	4a07      	ldr	r2, [pc, #28]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 800870e:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 8008712:	6053      	str	r3, [r2, #4]
 8008714:	e030      	b.n	8008778 <HAL_RCC_OscConfig+0x2d4>
 8008716:	4b05      	ldr	r3, [pc, #20]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008718:	685b      	ldr	r3, [r3, #4]
 800871a:	f423 327c 	bic.w	r2, r3, #258048	@ 0x3f000
 800871e:	687b      	ldr	r3, [r7, #4]
 8008720:	691b      	ldr	r3, [r3, #16]
 8008722:	031b      	lsls	r3, r3, #12
 8008724:	4901      	ldr	r1, [pc, #4]	@ (800872c <HAL_RCC_OscConfig+0x288>)
 8008726:	4313      	orrs	r3, r2
 8008728:	604b      	str	r3, [r1, #4]
 800872a:	e025      	b.n	8008778 <HAL_RCC_OscConfig+0x2d4>
 800872c:	58024400 	.word	0x58024400
 8008730:	4b9a      	ldr	r3, [pc, #616]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008732:	685b      	ldr	r3, [r3, #4]
 8008734:	f023 42fe 	bic.w	r2, r3, #2130706432	@ 0x7f000000
 8008738:	687b      	ldr	r3, [r7, #4]
 800873a:	691b      	ldr	r3, [r3, #16]
 800873c:	061b      	lsls	r3, r3, #24
 800873e:	4997      	ldr	r1, [pc, #604]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008740:	4313      	orrs	r3, r2
 8008742:	604b      	str	r3, [r1, #4]
 8008744:	e018      	b.n	8008778 <HAL_RCC_OscConfig+0x2d4>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 8008746:	4b95      	ldr	r3, [pc, #596]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008748:	681b      	ldr	r3, [r3, #0]
 800874a:	4a94      	ldr	r2, [pc, #592]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 800874c:	f023 0301 	bic.w	r3, r3, #1
 8008750:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8008752:	f7fa feb7 	bl	80034c4 <HAL_GetTick>
 8008756:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till HSI is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
 8008758:	e008      	b.n	800876c <HAL_RCC_OscConfig+0x2c8>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 800875a:	f7fa feb3 	bl	80034c4 <HAL_GetTick>
 800875e:	4602      	mov	r2, r0
 8008760:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008762:	1ad3      	subs	r3, r2, r3
 8008764:	2b02      	cmp	r3, #2
 8008766:	d901      	bls.n	800876c <HAL_RCC_OscConfig+0x2c8>
          {
            return HAL_TIMEOUT;
 8008768:	2303      	movs	r3, #3
 800876a:	e2ed      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
 800876c:	4b8b      	ldr	r3, [pc, #556]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 800876e:	681b      	ldr	r3, [r3, #0]
 8008770:	f003 0304 	and.w	r3, r3, #4
 8008774:	2b00      	cmp	r3, #0
 8008776:	d1f0      	bne.n	800875a <HAL_RCC_OscConfig+0x2b6>
        }
      }
    }
  }
  /*----------------------------- CSI Configuration --------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
 8008778:	687b      	ldr	r3, [r7, #4]
 800877a:	681b      	ldr	r3, [r3, #0]
 800877c:	f003 0310 	and.w	r3, r3, #16
 8008780:	2b00      	cmp	r3, #0
 8008782:	f000 80a9 	beq.w	80088d8 <HAL_RCC_OscConfig+0x434>
    /* Check the parameters */
    assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
    assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));

    /* When the CSI is used as system clock it will not disabled */
    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
 8008786:	4b85      	ldr	r3, [pc, #532]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008788:	691b      	ldr	r3, [r3, #16]
 800878a:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 800878e:	61bb      	str	r3, [r7, #24]
    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
 8008790:	4b82      	ldr	r3, [pc, #520]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008792:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8008794:	617b      	str	r3, [r7, #20]
    if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
 8008796:	69bb      	ldr	r3, [r7, #24]
 8008798:	2b08      	cmp	r3, #8
 800879a:	d007      	beq.n	80087ac <HAL_RCC_OscConfig+0x308>
 800879c:	69bb      	ldr	r3, [r7, #24]
 800879e:	2b18      	cmp	r3, #24
 80087a0:	d13a      	bne.n	8008818 <HAL_RCC_OscConfig+0x374>
 80087a2:	697b      	ldr	r3, [r7, #20]
 80087a4:	f003 0303 	and.w	r3, r3, #3
 80087a8:	2b01      	cmp	r3, #1
 80087aa:	d135      	bne.n	8008818 <HAL_RCC_OscConfig+0x374>
    {
      /* When CSI is used as system clock it will not disabled */
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
 80087ac:	4b7b      	ldr	r3, [pc, #492]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 80087ae:	681b      	ldr	r3, [r3, #0]
 80087b0:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 80087b4:	2b00      	cmp	r3, #0
 80087b6:	d005      	beq.n	80087c4 <HAL_RCC_OscConfig+0x320>
 80087b8:	687b      	ldr	r3, [r7, #4]
 80087ba:	69db      	ldr	r3, [r3, #28]
 80087bc:	2b80      	cmp	r3, #128	@ 0x80
 80087be:	d001      	beq.n	80087c4 <HAL_RCC_OscConfig+0x320>
      {
        return HAL_ERROR;
 80087c0:	2301      	movs	r3, #1
 80087c2:	e2c1      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
 80087c4:	f7fa fe8a 	bl	80034dc <HAL_GetREVID>
 80087c8:	4603      	mov	r3, r0
 80087ca:	f241 0203 	movw	r2, #4099	@ 0x1003
 80087ce:	4293      	cmp	r3, r2
 80087d0:	d817      	bhi.n	8008802 <HAL_RCC_OscConfig+0x35e>
 80087d2:	687b      	ldr	r3, [r7, #4]
 80087d4:	6a1b      	ldr	r3, [r3, #32]
 80087d6:	2b20      	cmp	r3, #32
 80087d8:	d108      	bne.n	80087ec <HAL_RCC_OscConfig+0x348>
 80087da:	4b70      	ldr	r3, [pc, #448]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 80087dc:	685b      	ldr	r3, [r3, #4]
 80087de:	f023 43f8 	bic.w	r3, r3, #2080374784	@ 0x7c000000
 80087e2:	4a6e      	ldr	r2, [pc, #440]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 80087e4:	f043 4380 	orr.w	r3, r3, #1073741824	@ 0x40000000
 80087e8:	6053      	str	r3, [r2, #4]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
 80087ea:	e075      	b.n	80088d8 <HAL_RCC_OscConfig+0x434>
        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
 80087ec:	4b6b      	ldr	r3, [pc, #428]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 80087ee:	685b      	ldr	r3, [r3, #4]
 80087f0:	f023 42f8 	bic.w	r2, r3, #2080374784	@ 0x7c000000
 80087f4:	687b      	ldr	r3, [r7, #4]
 80087f6:	6a1b      	ldr	r3, [r3, #32]
 80087f8:	069b      	lsls	r3, r3, #26
 80087fa:	4968      	ldr	r1, [pc, #416]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 80087fc:	4313      	orrs	r3, r2
 80087fe:	604b      	str	r3, [r1, #4]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
 8008800:	e06a      	b.n	80088d8 <HAL_RCC_OscConfig+0x434>
        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
 8008802:	4b66      	ldr	r3, [pc, #408]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008804:	68db      	ldr	r3, [r3, #12]
 8008806:	f023 527c 	bic.w	r2, r3, #1056964608	@ 0x3f000000
 800880a:	687b      	ldr	r3, [r7, #4]
 800880c:	6a1b      	ldr	r3, [r3, #32]
 800880e:	061b      	lsls	r3, r3, #24
 8008810:	4962      	ldr	r1, [pc, #392]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008812:	4313      	orrs	r3, r2
 8008814:	60cb      	str	r3, [r1, #12]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
 8008816:	e05f      	b.n	80088d8 <HAL_RCC_OscConfig+0x434>
      }
    }
    else
    {
      /* Check the CSI State */
      if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
 8008818:	687b      	ldr	r3, [r7, #4]
 800881a:	69db      	ldr	r3, [r3, #28]
 800881c:	2b00      	cmp	r3, #0
 800881e:	d042      	beq.n	80088a6 <HAL_RCC_OscConfig+0x402>
      {
        /* Enable the Internal High Speed oscillator (CSI). */
        __HAL_RCC_CSI_ENABLE();
 8008820:	4b5e      	ldr	r3, [pc, #376]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008822:	681b      	ldr	r3, [r3, #0]
 8008824:	4a5d      	ldr	r2, [pc, #372]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008826:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 800882a:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800882c:	f7fa fe4a 	bl	80034c4 <HAL_GetTick>
 8008830:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till CSI is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
 8008832:	e008      	b.n	8008846 <HAL_RCC_OscConfig+0x3a2>
        {
          if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
 8008834:	f7fa fe46 	bl	80034c4 <HAL_GetTick>
 8008838:	4602      	mov	r2, r0
 800883a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800883c:	1ad3      	subs	r3, r2, r3
 800883e:	2b02      	cmp	r3, #2
 8008840:	d901      	bls.n	8008846 <HAL_RCC_OscConfig+0x3a2>
          {
            return HAL_TIMEOUT;
 8008842:	2303      	movs	r3, #3
 8008844:	e280      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
 8008846:	4b55      	ldr	r3, [pc, #340]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008848:	681b      	ldr	r3, [r3, #0]
 800884a:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800884e:	2b00      	cmp	r3, #0
 8008850:	d0f0      	beq.n	8008834 <HAL_RCC_OscConfig+0x390>
          }
        }

        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
 8008852:	f7fa fe43 	bl	80034dc <HAL_GetREVID>
 8008856:	4603      	mov	r3, r0
 8008858:	f241 0203 	movw	r2, #4099	@ 0x1003
 800885c:	4293      	cmp	r3, r2
 800885e:	d817      	bhi.n	8008890 <HAL_RCC_OscConfig+0x3ec>
 8008860:	687b      	ldr	r3, [r7, #4]
 8008862:	6a1b      	ldr	r3, [r3, #32]
 8008864:	2b20      	cmp	r3, #32
 8008866:	d108      	bne.n	800887a <HAL_RCC_OscConfig+0x3d6>
 8008868:	4b4c      	ldr	r3, [pc, #304]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 800886a:	685b      	ldr	r3, [r3, #4]
 800886c:	f023 43f8 	bic.w	r3, r3, #2080374784	@ 0x7c000000
 8008870:	4a4a      	ldr	r2, [pc, #296]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008872:	f043 4380 	orr.w	r3, r3, #1073741824	@ 0x40000000
 8008876:	6053      	str	r3, [r2, #4]
 8008878:	e02e      	b.n	80088d8 <HAL_RCC_OscConfig+0x434>
 800887a:	4b48      	ldr	r3, [pc, #288]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 800887c:	685b      	ldr	r3, [r3, #4]
 800887e:	f023 42f8 	bic.w	r2, r3, #2080374784	@ 0x7c000000
 8008882:	687b      	ldr	r3, [r7, #4]
 8008884:	6a1b      	ldr	r3, [r3, #32]
 8008886:	069b      	lsls	r3, r3, #26
 8008888:	4944      	ldr	r1, [pc, #272]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 800888a:	4313      	orrs	r3, r2
 800888c:	604b      	str	r3, [r1, #4]
 800888e:	e023      	b.n	80088d8 <HAL_RCC_OscConfig+0x434>
 8008890:	4b42      	ldr	r3, [pc, #264]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008892:	68db      	ldr	r3, [r3, #12]
 8008894:	f023 527c 	bic.w	r2, r3, #1056964608	@ 0x3f000000
 8008898:	687b      	ldr	r3, [r7, #4]
 800889a:	6a1b      	ldr	r3, [r3, #32]
 800889c:	061b      	lsls	r3, r3, #24
 800889e:	493f      	ldr	r1, [pc, #252]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 80088a0:	4313      	orrs	r3, r2
 80088a2:	60cb      	str	r3, [r1, #12]
 80088a4:	e018      	b.n	80088d8 <HAL_RCC_OscConfig+0x434>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (CSI). */
        __HAL_RCC_CSI_DISABLE();
 80088a6:	4b3d      	ldr	r3, [pc, #244]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 80088a8:	681b      	ldr	r3, [r3, #0]
 80088aa:	4a3c      	ldr	r2, [pc, #240]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 80088ac:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 80088b0:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80088b2:	f7fa fe07 	bl	80034c4 <HAL_GetTick>
 80088b6:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till CSI is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
 80088b8:	e008      	b.n	80088cc <HAL_RCC_OscConfig+0x428>
        {
          if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
 80088ba:	f7fa fe03 	bl	80034c4 <HAL_GetTick>
 80088be:	4602      	mov	r2, r0
 80088c0:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80088c2:	1ad3      	subs	r3, r2, r3
 80088c4:	2b02      	cmp	r3, #2
 80088c6:	d901      	bls.n	80088cc <HAL_RCC_OscConfig+0x428>
          {
            return HAL_TIMEOUT;
 80088c8:	2303      	movs	r3, #3
 80088ca:	e23d      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
 80088cc:	4b33      	ldr	r3, [pc, #204]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 80088ce:	681b      	ldr	r3, [r3, #0]
 80088d0:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 80088d4:	2b00      	cmp	r3, #0
 80088d6:	d1f0      	bne.n	80088ba <HAL_RCC_OscConfig+0x416>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 80088d8:	687b      	ldr	r3, [r7, #4]
 80088da:	681b      	ldr	r3, [r3, #0]
 80088dc:	f003 0308 	and.w	r3, r3, #8
 80088e0:	2b00      	cmp	r3, #0
 80088e2:	d036      	beq.n	8008952 <HAL_RCC_OscConfig+0x4ae>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
 80088e4:	687b      	ldr	r3, [r7, #4]
 80088e6:	695b      	ldr	r3, [r3, #20]
 80088e8:	2b00      	cmp	r3, #0
 80088ea:	d019      	beq.n	8008920 <HAL_RCC_OscConfig+0x47c>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 80088ec:	4b2b      	ldr	r3, [pc, #172]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 80088ee:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 80088f0:	4a2a      	ldr	r2, [pc, #168]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 80088f2:	f043 0301 	orr.w	r3, r3, #1
 80088f6:	6753      	str	r3, [r2, #116]	@ 0x74

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 80088f8:	f7fa fde4 	bl	80034c4 <HAL_GetTick>
 80088fc:	6278      	str	r0, [r7, #36]	@ 0x24

      /* Wait till LSI is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
 80088fe:	e008      	b.n	8008912 <HAL_RCC_OscConfig+0x46e>
      {
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8008900:	f7fa fde0 	bl	80034c4 <HAL_GetTick>
 8008904:	4602      	mov	r2, r0
 8008906:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008908:	1ad3      	subs	r3, r2, r3
 800890a:	2b02      	cmp	r3, #2
 800890c:	d901      	bls.n	8008912 <HAL_RCC_OscConfig+0x46e>
        {
          return HAL_TIMEOUT;
 800890e:	2303      	movs	r3, #3
 8008910:	e21a      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
 8008912:	4b22      	ldr	r3, [pc, #136]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008914:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 8008916:	f003 0302 	and.w	r3, r3, #2
 800891a:	2b00      	cmp	r3, #0
 800891c:	d0f0      	beq.n	8008900 <HAL_RCC_OscConfig+0x45c>
 800891e:	e018      	b.n	8008952 <HAL_RCC_OscConfig+0x4ae>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8008920:	4b1e      	ldr	r3, [pc, #120]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008922:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 8008924:	4a1d      	ldr	r2, [pc, #116]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008926:	f023 0301 	bic.w	r3, r3, #1
 800892a:	6753      	str	r3, [r2, #116]	@ 0x74

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 800892c:	f7fa fdca 	bl	80034c4 <HAL_GetTick>
 8008930:	6278      	str	r0, [r7, #36]	@ 0x24

      /* Wait till LSI is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
 8008932:	e008      	b.n	8008946 <HAL_RCC_OscConfig+0x4a2>
      {
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8008934:	f7fa fdc6 	bl	80034c4 <HAL_GetTick>
 8008938:	4602      	mov	r2, r0
 800893a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800893c:	1ad3      	subs	r3, r2, r3
 800893e:	2b02      	cmp	r3, #2
 8008940:	d901      	bls.n	8008946 <HAL_RCC_OscConfig+0x4a2>
        {
          return HAL_TIMEOUT;
 8008942:	2303      	movs	r3, #3
 8008944:	e200      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
 8008946:	4b15      	ldr	r3, [pc, #84]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008948:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 800894a:	f003 0302 	and.w	r3, r3, #2
 800894e:	2b00      	cmp	r3, #0
 8008950:	d1f0      	bne.n	8008934 <HAL_RCC_OscConfig+0x490>
      }
    }
  }

  /*------------------------------ HSI48 Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
 8008952:	687b      	ldr	r3, [r7, #4]
 8008954:	681b      	ldr	r3, [r3, #0]
 8008956:	f003 0320 	and.w	r3, r3, #32
 800895a:	2b00      	cmp	r3, #0
 800895c:	d039      	beq.n	80089d2 <HAL_RCC_OscConfig+0x52e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));

    /* Check the HSI48 State */
    if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
 800895e:	687b      	ldr	r3, [r7, #4]
 8008960:	699b      	ldr	r3, [r3, #24]
 8008962:	2b00      	cmp	r3, #0
 8008964:	d01c      	beq.n	80089a0 <HAL_RCC_OscConfig+0x4fc>
    {
      /* Enable the Internal Low Speed oscillator (HSI48). */
      __HAL_RCC_HSI48_ENABLE();
 8008966:	4b0d      	ldr	r3, [pc, #52]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 8008968:	681b      	ldr	r3, [r3, #0]
 800896a:	4a0c      	ldr	r2, [pc, #48]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 800896c:	f443 5380 	orr.w	r3, r3, #4096	@ 0x1000
 8008970:	6013      	str	r3, [r2, #0]

      /* Get time-out */
      tickstart = HAL_GetTick();
 8008972:	f7fa fda7 	bl	80034c4 <HAL_GetTick>
 8008976:	6278      	str	r0, [r7, #36]	@ 0x24

      /* Wait till HSI48 is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
 8008978:	e008      	b.n	800898c <HAL_RCC_OscConfig+0x4e8>
      {
        if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
 800897a:	f7fa fda3 	bl	80034c4 <HAL_GetTick>
 800897e:	4602      	mov	r2, r0
 8008980:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008982:	1ad3      	subs	r3, r2, r3
 8008984:	2b02      	cmp	r3, #2
 8008986:	d901      	bls.n	800898c <HAL_RCC_OscConfig+0x4e8>
        {
          return HAL_TIMEOUT;
 8008988:	2303      	movs	r3, #3
 800898a:	e1dd      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
 800898c:	4b03      	ldr	r3, [pc, #12]	@ (800899c <HAL_RCC_OscConfig+0x4f8>)
 800898e:	681b      	ldr	r3, [r3, #0]
 8008990:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 8008994:	2b00      	cmp	r3, #0
 8008996:	d0f0      	beq.n	800897a <HAL_RCC_OscConfig+0x4d6>
 8008998:	e01b      	b.n	80089d2 <HAL_RCC_OscConfig+0x52e>
 800899a:	bf00      	nop
 800899c:	58024400 	.word	0x58024400
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (HSI48). */
      __HAL_RCC_HSI48_DISABLE();
 80089a0:	4b9b      	ldr	r3, [pc, #620]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 80089a2:	681b      	ldr	r3, [r3, #0]
 80089a4:	4a9a      	ldr	r2, [pc, #616]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 80089a6:	f423 5380 	bic.w	r3, r3, #4096	@ 0x1000
 80089aa:	6013      	str	r3, [r2, #0]

      /* Get time-out */
      tickstart = HAL_GetTick();
 80089ac:	f7fa fd8a 	bl	80034c4 <HAL_GetTick>
 80089b0:	6278      	str	r0, [r7, #36]	@ 0x24

      /* Wait till HSI48 is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
 80089b2:	e008      	b.n	80089c6 <HAL_RCC_OscConfig+0x522>
      {
        if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
 80089b4:	f7fa fd86 	bl	80034c4 <HAL_GetTick>
 80089b8:	4602      	mov	r2, r0
 80089ba:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80089bc:	1ad3      	subs	r3, r2, r3
 80089be:	2b02      	cmp	r3, #2
 80089c0:	d901      	bls.n	80089c6 <HAL_RCC_OscConfig+0x522>
        {
          return HAL_TIMEOUT;
 80089c2:	2303      	movs	r3, #3
 80089c4:	e1c0      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
 80089c6:	4b92      	ldr	r3, [pc, #584]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 80089c8:	681b      	ldr	r3, [r3, #0]
 80089ca:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 80089ce:	2b00      	cmp	r3, #0
 80089d0:	d1f0      	bne.n	80089b4 <HAL_RCC_OscConfig+0x510>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 80089d2:	687b      	ldr	r3, [r7, #4]
 80089d4:	681b      	ldr	r3, [r3, #0]
 80089d6:	f003 0304 	and.w	r3, r3, #4
 80089da:	2b00      	cmp	r3, #0
 80089dc:	f000 8081 	beq.w	8008ae2 <HAL_RCC_OscConfig+0x63e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Enable write access to Backup domain */
    PWR->CR1 |= PWR_CR1_DBP;
 80089e0:	4b8c      	ldr	r3, [pc, #560]	@ (8008c14 <HAL_RCC_OscConfig+0x770>)
 80089e2:	681b      	ldr	r3, [r3, #0]
 80089e4:	4a8b      	ldr	r2, [pc, #556]	@ (8008c14 <HAL_RCC_OscConfig+0x770>)
 80089e6:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 80089ea:	6013      	str	r3, [r2, #0]

    /* Wait for Backup domain Write protection disable */
    tickstart = HAL_GetTick();
 80089ec:	f7fa fd6a 	bl	80034c4 <HAL_GetTick>
 80089f0:	6278      	str	r0, [r7, #36]	@ 0x24

    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
 80089f2:	e008      	b.n	8008a06 <HAL_RCC_OscConfig+0x562>
    {
      if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 80089f4:	f7fa fd66 	bl	80034c4 <HAL_GetTick>
 80089f8:	4602      	mov	r2, r0
 80089fa:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80089fc:	1ad3      	subs	r3, r2, r3
 80089fe:	2b64      	cmp	r3, #100	@ 0x64
 8008a00:	d901      	bls.n	8008a06 <HAL_RCC_OscConfig+0x562>
      {
        return HAL_TIMEOUT;
 8008a02:	2303      	movs	r3, #3
 8008a04:	e1a0      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
 8008a06:	4b83      	ldr	r3, [pc, #524]	@ (8008c14 <HAL_RCC_OscConfig+0x770>)
 8008a08:	681b      	ldr	r3, [r3, #0]
 8008a0a:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8008a0e:	2b00      	cmp	r3, #0
 8008a10:	d0f0      	beq.n	80089f4 <HAL_RCC_OscConfig+0x550>
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8008a12:	687b      	ldr	r3, [r7, #4]
 8008a14:	689b      	ldr	r3, [r3, #8]
 8008a16:	2b01      	cmp	r3, #1
 8008a18:	d106      	bne.n	8008a28 <HAL_RCC_OscConfig+0x584>
 8008a1a:	4b7d      	ldr	r3, [pc, #500]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a1c:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8008a1e:	4a7c      	ldr	r2, [pc, #496]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a20:	f043 0301 	orr.w	r3, r3, #1
 8008a24:	6713      	str	r3, [r2, #112]	@ 0x70
 8008a26:	e02d      	b.n	8008a84 <HAL_RCC_OscConfig+0x5e0>
 8008a28:	687b      	ldr	r3, [r7, #4]
 8008a2a:	689b      	ldr	r3, [r3, #8]
 8008a2c:	2b00      	cmp	r3, #0
 8008a2e:	d10c      	bne.n	8008a4a <HAL_RCC_OscConfig+0x5a6>
 8008a30:	4b77      	ldr	r3, [pc, #476]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a32:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8008a34:	4a76      	ldr	r2, [pc, #472]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a36:	f023 0301 	bic.w	r3, r3, #1
 8008a3a:	6713      	str	r3, [r2, #112]	@ 0x70
 8008a3c:	4b74      	ldr	r3, [pc, #464]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a3e:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8008a40:	4a73      	ldr	r2, [pc, #460]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a42:	f023 0304 	bic.w	r3, r3, #4
 8008a46:	6713      	str	r3, [r2, #112]	@ 0x70
 8008a48:	e01c      	b.n	8008a84 <HAL_RCC_OscConfig+0x5e0>
 8008a4a:	687b      	ldr	r3, [r7, #4]
 8008a4c:	689b      	ldr	r3, [r3, #8]
 8008a4e:	2b05      	cmp	r3, #5
 8008a50:	d10c      	bne.n	8008a6c <HAL_RCC_OscConfig+0x5c8>
 8008a52:	4b6f      	ldr	r3, [pc, #444]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a54:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8008a56:	4a6e      	ldr	r2, [pc, #440]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a58:	f043 0304 	orr.w	r3, r3, #4
 8008a5c:	6713      	str	r3, [r2, #112]	@ 0x70
 8008a5e:	4b6c      	ldr	r3, [pc, #432]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a60:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8008a62:	4a6b      	ldr	r2, [pc, #428]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a64:	f043 0301 	orr.w	r3, r3, #1
 8008a68:	6713      	str	r3, [r2, #112]	@ 0x70
 8008a6a:	e00b      	b.n	8008a84 <HAL_RCC_OscConfig+0x5e0>
 8008a6c:	4b68      	ldr	r3, [pc, #416]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a6e:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8008a70:	4a67      	ldr	r2, [pc, #412]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a72:	f023 0301 	bic.w	r3, r3, #1
 8008a76:	6713      	str	r3, [r2, #112]	@ 0x70
 8008a78:	4b65      	ldr	r3, [pc, #404]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a7a:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8008a7c:	4a64      	ldr	r2, [pc, #400]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008a7e:	f023 0304 	bic.w	r3, r3, #4
 8008a82:	6713      	str	r3, [r2, #112]	@ 0x70
    /* Check the LSE State */
    if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
 8008a84:	687b      	ldr	r3, [r7, #4]
 8008a86:	689b      	ldr	r3, [r3, #8]
 8008a88:	2b00      	cmp	r3, #0
 8008a8a:	d015      	beq.n	8008ab8 <HAL_RCC_OscConfig+0x614>
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8008a8c:	f7fa fd1a 	bl	80034c4 <HAL_GetTick>
 8008a90:	6278      	str	r0, [r7, #36]	@ 0x24

      /* Wait till LSE is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 8008a92:	e00a      	b.n	8008aaa <HAL_RCC_OscConfig+0x606>
      {
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8008a94:	f7fa fd16 	bl	80034c4 <HAL_GetTick>
 8008a98:	4602      	mov	r2, r0
 8008a9a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008a9c:	1ad3      	subs	r3, r2, r3
 8008a9e:	f241 3288 	movw	r2, #5000	@ 0x1388
 8008aa2:	4293      	cmp	r3, r2
 8008aa4:	d901      	bls.n	8008aaa <HAL_RCC_OscConfig+0x606>
        {
          return HAL_TIMEOUT;
 8008aa6:	2303      	movs	r3, #3
 8008aa8:	e14e      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 8008aaa:	4b59      	ldr	r3, [pc, #356]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008aac:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8008aae:	f003 0302 	and.w	r3, r3, #2
 8008ab2:	2b00      	cmp	r3, #0
 8008ab4:	d0ee      	beq.n	8008a94 <HAL_RCC_OscConfig+0x5f0>
 8008ab6:	e014      	b.n	8008ae2 <HAL_RCC_OscConfig+0x63e>
      }
    }
    else
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8008ab8:	f7fa fd04 	bl	80034c4 <HAL_GetTick>
 8008abc:	6278      	str	r0, [r7, #36]	@ 0x24

      /* Wait till LSE is disabled */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
 8008abe:	e00a      	b.n	8008ad6 <HAL_RCC_OscConfig+0x632>
      {
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8008ac0:	f7fa fd00 	bl	80034c4 <HAL_GetTick>
 8008ac4:	4602      	mov	r2, r0
 8008ac6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008ac8:	1ad3      	subs	r3, r2, r3
 8008aca:	f241 3288 	movw	r2, #5000	@ 0x1388
 8008ace:	4293      	cmp	r3, r2
 8008ad0:	d901      	bls.n	8008ad6 <HAL_RCC_OscConfig+0x632>
        {
          return HAL_TIMEOUT;
 8008ad2:	2303      	movs	r3, #3
 8008ad4:	e138      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
 8008ad6:	4b4e      	ldr	r3, [pc, #312]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008ad8:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8008ada:	f003 0302 	and.w	r3, r3, #2
 8008ade:	2b00      	cmp	r3, #0
 8008ae0:	d1ee      	bne.n	8008ac0 <HAL_RCC_OscConfig+0x61c>
    }
  }
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8008ae2:	687b      	ldr	r3, [r7, #4]
 8008ae4:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8008ae6:	2b00      	cmp	r3, #0
 8008ae8:	f000 812d 	beq.w	8008d46 <HAL_RCC_OscConfig+0x8a2>
  {
    /* Check if the PLL is used as system clock or not */
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
 8008aec:	4b48      	ldr	r3, [pc, #288]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008aee:	691b      	ldr	r3, [r3, #16]
 8008af0:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 8008af4:	2b18      	cmp	r3, #24
 8008af6:	f000 80bd 	beq.w	8008c74 <HAL_RCC_OscConfig+0x7d0>
    {
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8008afa:	687b      	ldr	r3, [r7, #4]
 8008afc:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8008afe:	2b02      	cmp	r3, #2
 8008b00:	f040 809e 	bne.w	8008c40 <HAL_RCC_OscConfig+0x79c>
        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
        assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8008b04:	4b42      	ldr	r3, [pc, #264]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008b06:	681b      	ldr	r3, [r3, #0]
 8008b08:	4a41      	ldr	r2, [pc, #260]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008b0a:	f023 7380 	bic.w	r3, r3, #16777216	@ 0x1000000
 8008b0e:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8008b10:	f7fa fcd8 	bl	80034c4 <HAL_GetTick>
 8008b14:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till PLL is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 8008b16:	e008      	b.n	8008b2a <HAL_RCC_OscConfig+0x686>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8008b18:	f7fa fcd4 	bl	80034c4 <HAL_GetTick>
 8008b1c:	4602      	mov	r2, r0
 8008b1e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008b20:	1ad3      	subs	r3, r2, r3
 8008b22:	2b02      	cmp	r3, #2
 8008b24:	d901      	bls.n	8008b2a <HAL_RCC_OscConfig+0x686>
          {
            return HAL_TIMEOUT;
 8008b26:	2303      	movs	r3, #3
 8008b28:	e10e      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 8008b2a:	4b39      	ldr	r3, [pc, #228]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008b2c:	681b      	ldr	r3, [r3, #0]
 8008b2e:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8008b32:	2b00      	cmp	r3, #0
 8008b34:	d1f0      	bne.n	8008b18 <HAL_RCC_OscConfig+0x674>
          }
        }

        /* Configure the main PLL clock source, multiplication and division factors. */
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8008b36:	4b36      	ldr	r3, [pc, #216]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008b38:	6a9a      	ldr	r2, [r3, #40]	@ 0x28
 8008b3a:	4b37      	ldr	r3, [pc, #220]	@ (8008c18 <HAL_RCC_OscConfig+0x774>)
 8008b3c:	4013      	ands	r3, r2
 8008b3e:	687a      	ldr	r2, [r7, #4]
 8008b40:	6a91      	ldr	r1, [r2, #40]	@ 0x28
 8008b42:	687a      	ldr	r2, [r7, #4]
 8008b44:	6ad2      	ldr	r2, [r2, #44]	@ 0x2c
 8008b46:	0112      	lsls	r2, r2, #4
 8008b48:	430a      	orrs	r2, r1
 8008b4a:	4931      	ldr	r1, [pc, #196]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008b4c:	4313      	orrs	r3, r2
 8008b4e:	628b      	str	r3, [r1, #40]	@ 0x28
 8008b50:	687b      	ldr	r3, [r7, #4]
 8008b52:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8008b54:	3b01      	subs	r3, #1
 8008b56:	f3c3 0208 	ubfx	r2, r3, #0, #9
 8008b5a:	687b      	ldr	r3, [r7, #4]
 8008b5c:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 8008b5e:	3b01      	subs	r3, #1
 8008b60:	025b      	lsls	r3, r3, #9
 8008b62:	b29b      	uxth	r3, r3
 8008b64:	431a      	orrs	r2, r3
 8008b66:	687b      	ldr	r3, [r7, #4]
 8008b68:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8008b6a:	3b01      	subs	r3, #1
 8008b6c:	041b      	lsls	r3, r3, #16
 8008b6e:	f403 03fe 	and.w	r3, r3, #8323072	@ 0x7f0000
 8008b72:	431a      	orrs	r2, r3
 8008b74:	687b      	ldr	r3, [r7, #4]
 8008b76:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8008b78:	3b01      	subs	r3, #1
 8008b7a:	061b      	lsls	r3, r3, #24
 8008b7c:	f003 43fe 	and.w	r3, r3, #2130706432	@ 0x7f000000
 8008b80:	4923      	ldr	r1, [pc, #140]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008b82:	4313      	orrs	r3, r2
 8008b84:	630b      	str	r3, [r1, #48]	@ 0x30
                             RCC_OscInitStruct->PLL.PLLP,
                             RCC_OscInitStruct->PLL.PLLQ,
                             RCC_OscInitStruct->PLL.PLLR);

        /* Disable PLLFRACN . */
        __HAL_RCC_PLLFRACN_DISABLE();
 8008b86:	4b22      	ldr	r3, [pc, #136]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008b88:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8008b8a:	4a21      	ldr	r2, [pc, #132]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008b8c:	f023 0301 	bic.w	r3, r3, #1
 8008b90:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* Configure PLL PLL1FRACN */
        __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
 8008b92:	4b1f      	ldr	r3, [pc, #124]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008b94:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 8008b96:	4b21      	ldr	r3, [pc, #132]	@ (8008c1c <HAL_RCC_OscConfig+0x778>)
 8008b98:	4013      	ands	r3, r2
 8008b9a:	687a      	ldr	r2, [r7, #4]
 8008b9c:	6c92      	ldr	r2, [r2, #72]	@ 0x48
 8008b9e:	00d2      	lsls	r2, r2, #3
 8008ba0:	491b      	ldr	r1, [pc, #108]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008ba2:	4313      	orrs	r3, r2
 8008ba4:	634b      	str	r3, [r1, #52]	@ 0x34

        /* Select PLL1 input reference frequency range: VCI */
        __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
 8008ba6:	4b1a      	ldr	r3, [pc, #104]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008ba8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8008baa:	f023 020c 	bic.w	r2, r3, #12
 8008bae:	687b      	ldr	r3, [r7, #4]
 8008bb0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8008bb2:	4917      	ldr	r1, [pc, #92]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008bb4:	4313      	orrs	r3, r2
 8008bb6:	62cb      	str	r3, [r1, #44]	@ 0x2c

        /* Select PLL1 output frequency range : VCO */
        __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
 8008bb8:	4b15      	ldr	r3, [pc, #84]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008bba:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8008bbc:	f023 0202 	bic.w	r2, r3, #2
 8008bc0:	687b      	ldr	r3, [r7, #4]
 8008bc2:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 8008bc4:	4912      	ldr	r1, [pc, #72]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008bc6:	4313      	orrs	r3, r2
 8008bc8:	62cb      	str	r3, [r1, #44]	@ 0x2c

        /* Enable PLL System Clock output. */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
 8008bca:	4b11      	ldr	r3, [pc, #68]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008bcc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8008bce:	4a10      	ldr	r2, [pc, #64]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008bd0:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 8008bd4:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* Enable PLL1Q Clock output. */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 8008bd6:	4b0e      	ldr	r3, [pc, #56]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008bd8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8008bda:	4a0d      	ldr	r2, [pc, #52]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008bdc:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 8008be0:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* Enable PLL1R  Clock output. */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
 8008be2:	4b0b      	ldr	r3, [pc, #44]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008be4:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8008be6:	4a0a      	ldr	r2, [pc, #40]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008be8:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
 8008bec:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* Enable PLL1FRACN . */
        __HAL_RCC_PLLFRACN_ENABLE();
 8008bee:	4b08      	ldr	r3, [pc, #32]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008bf0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8008bf2:	4a07      	ldr	r2, [pc, #28]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008bf4:	f043 0301 	orr.w	r3, r3, #1
 8008bf8:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 8008bfa:	4b05      	ldr	r3, [pc, #20]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008bfc:	681b      	ldr	r3, [r3, #0]
 8008bfe:	4a04      	ldr	r2, [pc, #16]	@ (8008c10 <HAL_RCC_OscConfig+0x76c>)
 8008c00:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8008c04:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8008c06:	f7fa fc5d 	bl	80034c4 <HAL_GetTick>
 8008c0a:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till PLL is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 8008c0c:	e011      	b.n	8008c32 <HAL_RCC_OscConfig+0x78e>
 8008c0e:	bf00      	nop
 8008c10:	58024400 	.word	0x58024400
 8008c14:	58024800 	.word	0x58024800
 8008c18:	fffffc0c 	.word	0xfffffc0c
 8008c1c:	ffff0007 	.word	0xffff0007
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8008c20:	f7fa fc50 	bl	80034c4 <HAL_GetTick>
 8008c24:	4602      	mov	r2, r0
 8008c26:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008c28:	1ad3      	subs	r3, r2, r3
 8008c2a:	2b02      	cmp	r3, #2
 8008c2c:	d901      	bls.n	8008c32 <HAL_RCC_OscConfig+0x78e>
          {
            return HAL_TIMEOUT;
 8008c2e:	2303      	movs	r3, #3
 8008c30:	e08a      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 8008c32:	4b47      	ldr	r3, [pc, #284]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008c34:	681b      	ldr	r3, [r3, #0]
 8008c36:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8008c3a:	2b00      	cmp	r3, #0
 8008c3c:	d0f0      	beq.n	8008c20 <HAL_RCC_OscConfig+0x77c>
 8008c3e:	e082      	b.n	8008d46 <HAL_RCC_OscConfig+0x8a2>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8008c40:	4b43      	ldr	r3, [pc, #268]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008c42:	681b      	ldr	r3, [r3, #0]
 8008c44:	4a42      	ldr	r2, [pc, #264]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008c46:	f023 7380 	bic.w	r3, r3, #16777216	@ 0x1000000
 8008c4a:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8008c4c:	f7fa fc3a 	bl	80034c4 <HAL_GetTick>
 8008c50:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till PLL is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 8008c52:	e008      	b.n	8008c66 <HAL_RCC_OscConfig+0x7c2>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8008c54:	f7fa fc36 	bl	80034c4 <HAL_GetTick>
 8008c58:	4602      	mov	r2, r0
 8008c5a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008c5c:	1ad3      	subs	r3, r2, r3
 8008c5e:	2b02      	cmp	r3, #2
 8008c60:	d901      	bls.n	8008c66 <HAL_RCC_OscConfig+0x7c2>
          {
            return HAL_TIMEOUT;
 8008c62:	2303      	movs	r3, #3
 8008c64:	e070      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 8008c66:	4b3a      	ldr	r3, [pc, #232]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008c68:	681b      	ldr	r3, [r3, #0]
 8008c6a:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8008c6e:	2b00      	cmp	r3, #0
 8008c70:	d1f0      	bne.n	8008c54 <HAL_RCC_OscConfig+0x7b0>
 8008c72:	e068      	b.n	8008d46 <HAL_RCC_OscConfig+0x8a2>
      }
    }
    else
    {
      /* Do not return HAL_ERROR if request repeats the current configuration */
      temp1_pllckcfg = RCC->PLLCKSELR;
 8008c74:	4b36      	ldr	r3, [pc, #216]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008c76:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8008c78:	613b      	str	r3, [r7, #16]
      temp2_pllckcfg = RCC->PLL1DIVR;
 8008c7a:	4b35      	ldr	r3, [pc, #212]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008c7c:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8008c7e:	60fb      	str	r3, [r7, #12]
      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
 8008c80:	687b      	ldr	r3, [r7, #4]
 8008c82:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8008c84:	2b01      	cmp	r3, #1
 8008c86:	d031      	beq.n	8008cec <HAL_RCC_OscConfig+0x848>
          (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8008c88:	693b      	ldr	r3, [r7, #16]
 8008c8a:	f003 0203 	and.w	r2, r3, #3
 8008c8e:	687b      	ldr	r3, [r7, #4]
 8008c90:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
 8008c92:	429a      	cmp	r2, r3
 8008c94:	d12a      	bne.n	8008cec <HAL_RCC_OscConfig+0x848>
          ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
 8008c96:	693b      	ldr	r3, [r7, #16]
 8008c98:	091b      	lsrs	r3, r3, #4
 8008c9a:	f003 023f 	and.w	r2, r3, #63	@ 0x3f
 8008c9e:	687b      	ldr	r3, [r7, #4]
 8008ca0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
          (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8008ca2:	429a      	cmp	r2, r3
 8008ca4:	d122      	bne.n	8008cec <HAL_RCC_OscConfig+0x848>
          (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
 8008ca6:	68fb      	ldr	r3, [r7, #12]
 8008ca8:	f3c3 0208 	ubfx	r2, r3, #0, #9
 8008cac:	687b      	ldr	r3, [r7, #4]
 8008cae:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8008cb0:	3b01      	subs	r3, #1
          ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
 8008cb2:	429a      	cmp	r2, r3
 8008cb4:	d11a      	bne.n	8008cec <HAL_RCC_OscConfig+0x848>
          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
 8008cb6:	68fb      	ldr	r3, [r7, #12]
 8008cb8:	0a5b      	lsrs	r3, r3, #9
 8008cba:	f003 027f 	and.w	r2, r3, #127	@ 0x7f
 8008cbe:	687b      	ldr	r3, [r7, #4]
 8008cc0:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 8008cc2:	3b01      	subs	r3, #1
          (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
 8008cc4:	429a      	cmp	r2, r3
 8008cc6:	d111      	bne.n	8008cec <HAL_RCC_OscConfig+0x848>
          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
 8008cc8:	68fb      	ldr	r3, [r7, #12]
 8008cca:	0c1b      	lsrs	r3, r3, #16
 8008ccc:	f003 027f 	and.w	r2, r3, #127	@ 0x7f
 8008cd0:	687b      	ldr	r3, [r7, #4]
 8008cd2:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8008cd4:	3b01      	subs	r3, #1
          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
 8008cd6:	429a      	cmp	r2, r3
 8008cd8:	d108      	bne.n	8008cec <HAL_RCC_OscConfig+0x848>
          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
 8008cda:	68fb      	ldr	r3, [r7, #12]
 8008cdc:	0e1b      	lsrs	r3, r3, #24
 8008cde:	f003 027f 	and.w	r2, r3, #127	@ 0x7f
 8008ce2:	687b      	ldr	r3, [r7, #4]
 8008ce4:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8008ce6:	3b01      	subs	r3, #1
          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
 8008ce8:	429a      	cmp	r2, r3
 8008cea:	d001      	beq.n	8008cf0 <HAL_RCC_OscConfig+0x84c>
      {
        return HAL_ERROR;
 8008cec:	2301      	movs	r3, #1
 8008cee:	e02b      	b.n	8008d48 <HAL_RCC_OscConfig+0x8a4>
      }
      else
      {
        /* Check if only fractional part needs to be updated  */
        temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
 8008cf0:	4b17      	ldr	r3, [pc, #92]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008cf2:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 8008cf4:	08db      	lsrs	r3, r3, #3
 8008cf6:	f3c3 030c 	ubfx	r3, r3, #0, #13
 8008cfa:	613b      	str	r3, [r7, #16]
        if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
 8008cfc:	687b      	ldr	r3, [r7, #4]
 8008cfe:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8008d00:	693a      	ldr	r2, [r7, #16]
 8008d02:	429a      	cmp	r2, r3
 8008d04:	d01f      	beq.n	8008d46 <HAL_RCC_OscConfig+0x8a2>
        {
          assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
          /* Disable PLL1FRACEN */
          __HAL_RCC_PLLFRACN_DISABLE();
 8008d06:	4b12      	ldr	r3, [pc, #72]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008d08:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8008d0a:	4a11      	ldr	r2, [pc, #68]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008d0c:	f023 0301 	bic.w	r3, r3, #1
 8008d10:	62d3      	str	r3, [r2, #44]	@ 0x2c
          /* Get Start Tick*/
          tickstart = HAL_GetTick();
 8008d12:	f7fa fbd7 	bl	80034c4 <HAL_GetTick>
 8008d16:	6278      	str	r0, [r7, #36]	@ 0x24
          /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */
          while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE)
 8008d18:	bf00      	nop
 8008d1a:	f7fa fbd3 	bl	80034c4 <HAL_GetTick>
 8008d1e:	4602      	mov	r2, r0
 8008d20:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8008d22:	4293      	cmp	r3, r2
 8008d24:	d0f9      	beq.n	8008d1a <HAL_RCC_OscConfig+0x876>
          {
          }
          /* Configure PLL1 PLL1FRACN */
          __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
 8008d26:	4b0a      	ldr	r3, [pc, #40]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008d28:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 8008d2a:	4b0a      	ldr	r3, [pc, #40]	@ (8008d54 <HAL_RCC_OscConfig+0x8b0>)
 8008d2c:	4013      	ands	r3, r2
 8008d2e:	687a      	ldr	r2, [r7, #4]
 8008d30:	6c92      	ldr	r2, [r2, #72]	@ 0x48
 8008d32:	00d2      	lsls	r2, r2, #3
 8008d34:	4906      	ldr	r1, [pc, #24]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008d36:	4313      	orrs	r3, r2
 8008d38:	634b      	str	r3, [r1, #52]	@ 0x34
          /* Enable PLL1FRACEN to latch new value. */
          __HAL_RCC_PLLFRACN_ENABLE();
 8008d3a:	4b05      	ldr	r3, [pc, #20]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008d3c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8008d3e:	4a04      	ldr	r2, [pc, #16]	@ (8008d50 <HAL_RCC_OscConfig+0x8ac>)
 8008d40:	f043 0301 	orr.w	r3, r3, #1
 8008d44:	62d3      	str	r3, [r2, #44]	@ 0x2c
        }
      }
    }
  }
  return HAL_OK;
 8008d46:	2300      	movs	r3, #0
}
 8008d48:	4618      	mov	r0, r3
 8008d4a:	3730      	adds	r7, #48	@ 0x30
 8008d4c:	46bd      	mov	sp, r7
 8008d4e:	bd80      	pop	{r7, pc}
 8008d50:	58024400 	.word	0x58024400
 8008d54:	ffff0007 	.word	0xffff0007

08008d58 <HAL_RCC_ClockConfig>:
  *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 8008d58:	b580      	push	{r7, lr}
 8008d5a:	b086      	sub	sp, #24
 8008d5c:	af00      	add	r7, sp, #0
 8008d5e:	6078      	str	r0, [r7, #4]
 8008d60:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef halstatus;
  uint32_t tickstart;
  uint32_t common_system_clock;

  /* Check Null pointer */
  if (RCC_ClkInitStruct == NULL)
 8008d62:	687b      	ldr	r3, [r7, #4]
 8008d64:	2b00      	cmp	r3, #0
 8008d66:	d101      	bne.n	8008d6c <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 8008d68:	2301      	movs	r3, #1
 8008d6a:	e19c      	b.n	80090a6 <HAL_RCC_ClockConfig+0x34e>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the CPU clock
    (HCLK) and the supply voltage of the device. */

  /* Increasing the CPU frequency */
  if (FLatency > __HAL_FLASH_GET_LATENCY())
 8008d6c:	4b8a      	ldr	r3, [pc, #552]	@ (8008f98 <HAL_RCC_ClockConfig+0x240>)
 8008d6e:	681b      	ldr	r3, [r3, #0]
 8008d70:	f003 030f 	and.w	r3, r3, #15
 8008d74:	683a      	ldr	r2, [r7, #0]
 8008d76:	429a      	cmp	r2, r3
 8008d78:	d910      	bls.n	8008d9c <HAL_RCC_ClockConfig+0x44>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8008d7a:	4b87      	ldr	r3, [pc, #540]	@ (8008f98 <HAL_RCC_ClockConfig+0x240>)
 8008d7c:	681b      	ldr	r3, [r3, #0]
 8008d7e:	f023 020f 	bic.w	r2, r3, #15
 8008d82:	4985      	ldr	r1, [pc, #532]	@ (8008f98 <HAL_RCC_ClockConfig+0x240>)
 8008d84:	683b      	ldr	r3, [r7, #0]
 8008d86:	4313      	orrs	r3, r2
 8008d88:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 8008d8a:	4b83      	ldr	r3, [pc, #524]	@ (8008f98 <HAL_RCC_ClockConfig+0x240>)
 8008d8c:	681b      	ldr	r3, [r3, #0]
 8008d8e:	f003 030f 	and.w	r3, r3, #15
 8008d92:	683a      	ldr	r2, [r7, #0]
 8008d94:	429a      	cmp	r2, r3
 8008d96:	d001      	beq.n	8008d9c <HAL_RCC_ClockConfig+0x44>
    {
      return HAL_ERROR;
 8008d98:	2301      	movs	r3, #1
 8008d9a:	e184      	b.n	80090a6 <HAL_RCC_ClockConfig+0x34e>

  }

  /* Increasing the BUS frequency divider */
  /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
 8008d9c:	687b      	ldr	r3, [r7, #4]
 8008d9e:	681b      	ldr	r3, [r3, #0]
 8008da0:	f003 0304 	and.w	r3, r3, #4
 8008da4:	2b00      	cmp	r3, #0
 8008da6:	d010      	beq.n	8008dca <HAL_RCC_ClockConfig+0x72>
  {
#if defined (RCC_D1CFGR_D1PPRE)
    if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
 8008da8:	687b      	ldr	r3, [r7, #4]
 8008daa:	691a      	ldr	r2, [r3, #16]
 8008dac:	4b7b      	ldr	r3, [pc, #492]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008dae:	699b      	ldr	r3, [r3, #24]
 8008db0:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 8008db4:	429a      	cmp	r2, r3
 8008db6:	d908      	bls.n	8008dca <HAL_RCC_ClockConfig+0x72>
    {
      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
 8008db8:	4b78      	ldr	r3, [pc, #480]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008dba:	699b      	ldr	r3, [r3, #24]
 8008dbc:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
 8008dc0:	687b      	ldr	r3, [r7, #4]
 8008dc2:	691b      	ldr	r3, [r3, #16]
 8008dc4:	4975      	ldr	r1, [pc, #468]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008dc6:	4313      	orrs	r3, r2
 8008dc8:	618b      	str	r3, [r1, #24]
    }
#endif
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8008dca:	687b      	ldr	r3, [r7, #4]
 8008dcc:	681b      	ldr	r3, [r3, #0]
 8008dce:	f003 0308 	and.w	r3, r3, #8
 8008dd2:	2b00      	cmp	r3, #0
 8008dd4:	d010      	beq.n	8008df8 <HAL_RCC_ClockConfig+0xa0>
  {
#if defined (RCC_D2CFGR_D2PPRE1)
    if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
 8008dd6:	687b      	ldr	r3, [r7, #4]
 8008dd8:	695a      	ldr	r2, [r3, #20]
 8008dda:	4b70      	ldr	r3, [pc, #448]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008ddc:	69db      	ldr	r3, [r3, #28]
 8008dde:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 8008de2:	429a      	cmp	r2, r3
 8008de4:	d908      	bls.n	8008df8 <HAL_RCC_ClockConfig+0xa0>
    {
      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
 8008de6:	4b6d      	ldr	r3, [pc, #436]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008de8:	69db      	ldr	r3, [r3, #28]
 8008dea:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
 8008dee:	687b      	ldr	r3, [r7, #4]
 8008df0:	695b      	ldr	r3, [r3, #20]
 8008df2:	496a      	ldr	r1, [pc, #424]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008df4:	4313      	orrs	r3, r2
 8008df6:	61cb      	str	r3, [r1, #28]
      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
    }
#endif
  }
  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8008df8:	687b      	ldr	r3, [r7, #4]
 8008dfa:	681b      	ldr	r3, [r3, #0]
 8008dfc:	f003 0310 	and.w	r3, r3, #16
 8008e00:	2b00      	cmp	r3, #0
 8008e02:	d010      	beq.n	8008e26 <HAL_RCC_ClockConfig+0xce>
  {
#if defined(RCC_D2CFGR_D2PPRE2)
    if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
 8008e04:	687b      	ldr	r3, [r7, #4]
 8008e06:	699a      	ldr	r2, [r3, #24]
 8008e08:	4b64      	ldr	r3, [pc, #400]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008e0a:	69db      	ldr	r3, [r3, #28]
 8008e0c:	f403 63e0 	and.w	r3, r3, #1792	@ 0x700
 8008e10:	429a      	cmp	r2, r3
 8008e12:	d908      	bls.n	8008e26 <HAL_RCC_ClockConfig+0xce>
    {
      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
 8008e14:	4b61      	ldr	r3, [pc, #388]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008e16:	69db      	ldr	r3, [r3, #28]
 8008e18:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
 8008e1c:	687b      	ldr	r3, [r7, #4]
 8008e1e:	699b      	ldr	r3, [r3, #24]
 8008e20:	495e      	ldr	r1, [pc, #376]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008e22:	4313      	orrs	r3, r2
 8008e24:	61cb      	str	r3, [r1, #28]
    }
#endif
  }

  /*-------------------------- D3PCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
 8008e26:	687b      	ldr	r3, [r7, #4]
 8008e28:	681b      	ldr	r3, [r3, #0]
 8008e2a:	f003 0320 	and.w	r3, r3, #32
 8008e2e:	2b00      	cmp	r3, #0
 8008e30:	d010      	beq.n	8008e54 <HAL_RCC_ClockConfig+0xfc>
  {
#if defined(RCC_D3CFGR_D3PPRE)
    if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
 8008e32:	687b      	ldr	r3, [r7, #4]
 8008e34:	69da      	ldr	r2, [r3, #28]
 8008e36:	4b59      	ldr	r3, [pc, #356]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008e38:	6a1b      	ldr	r3, [r3, #32]
 8008e3a:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 8008e3e:	429a      	cmp	r2, r3
 8008e40:	d908      	bls.n	8008e54 <HAL_RCC_ClockConfig+0xfc>
    {
      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
 8008e42:	4b56      	ldr	r3, [pc, #344]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008e44:	6a1b      	ldr	r3, [r3, #32]
 8008e46:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
 8008e4a:	687b      	ldr	r3, [r7, #4]
 8008e4c:	69db      	ldr	r3, [r3, #28]
 8008e4e:	4953      	ldr	r1, [pc, #332]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008e50:	4313      	orrs	r3, r2
 8008e52:	620b      	str	r3, [r1, #32]
    }
#endif
  }

  /*-------------------------- HCLK Configuration --------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8008e54:	687b      	ldr	r3, [r7, #4]
 8008e56:	681b      	ldr	r3, [r3, #0]
 8008e58:	f003 0302 	and.w	r3, r3, #2
 8008e5c:	2b00      	cmp	r3, #0
 8008e5e:	d010      	beq.n	8008e82 <HAL_RCC_ClockConfig+0x12a>
  {
#if defined (RCC_D1CFGR_HPRE)
    if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
 8008e60:	687b      	ldr	r3, [r7, #4]
 8008e62:	68da      	ldr	r2, [r3, #12]
 8008e64:	4b4d      	ldr	r3, [pc, #308]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008e66:	699b      	ldr	r3, [r3, #24]
 8008e68:	f003 030f 	and.w	r3, r3, #15
 8008e6c:	429a      	cmp	r2, r3
 8008e6e:	d908      	bls.n	8008e82 <HAL_RCC_ClockConfig+0x12a>
    {
      /* Set the new HCLK clock divider */
      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8008e70:	4b4a      	ldr	r3, [pc, #296]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008e72:	699b      	ldr	r3, [r3, #24]
 8008e74:	f023 020f 	bic.w	r2, r3, #15
 8008e78:	687b      	ldr	r3, [r7, #4]
 8008e7a:	68db      	ldr	r3, [r3, #12]
 8008e7c:	4947      	ldr	r1, [pc, #284]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008e7e:	4313      	orrs	r3, r2
 8008e80:	618b      	str	r3, [r1, #24]
    }
#endif
  }

  /*------------------------- SYSCLK Configuration -------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8008e82:	687b      	ldr	r3, [r7, #4]
 8008e84:	681b      	ldr	r3, [r3, #0]
 8008e86:	f003 0301 	and.w	r3, r3, #1
 8008e8a:	2b00      	cmp	r3, #0
 8008e8c:	d055      	beq.n	8008f3a <HAL_RCC_ClockConfig+0x1e2>
  {
    assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
#if defined(RCC_D1CFGR_D1CPRE)
    MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
 8008e8e:	4b43      	ldr	r3, [pc, #268]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008e90:	699b      	ldr	r3, [r3, #24]
 8008e92:	f423 6270 	bic.w	r2, r3, #3840	@ 0xf00
 8008e96:	687b      	ldr	r3, [r7, #4]
 8008e98:	689b      	ldr	r3, [r3, #8]
 8008e9a:	4940      	ldr	r1, [pc, #256]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008e9c:	4313      	orrs	r3, r2
 8008e9e:	618b      	str	r3, [r1, #24]
#else
    MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
#endif
    /* HSE is selected as System Clock Source */
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8008ea0:	687b      	ldr	r3, [r7, #4]
 8008ea2:	685b      	ldr	r3, [r3, #4]
 8008ea4:	2b02      	cmp	r3, #2
 8008ea6:	d107      	bne.n	8008eb8 <HAL_RCC_ClockConfig+0x160>
    {
      /* Check the HSE ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 8008ea8:	4b3c      	ldr	r3, [pc, #240]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008eaa:	681b      	ldr	r3, [r3, #0]
 8008eac:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8008eb0:	2b00      	cmp	r3, #0
 8008eb2:	d121      	bne.n	8008ef8 <HAL_RCC_ClockConfig+0x1a0>
      {
        return HAL_ERROR;
 8008eb4:	2301      	movs	r3, #1
 8008eb6:	e0f6      	b.n	80090a6 <HAL_RCC_ClockConfig+0x34e>
      }
    }
    /* PLL is selected as System Clock Source */
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8008eb8:	687b      	ldr	r3, [r7, #4]
 8008eba:	685b      	ldr	r3, [r3, #4]
 8008ebc:	2b03      	cmp	r3, #3
 8008ebe:	d107      	bne.n	8008ed0 <HAL_RCC_ClockConfig+0x178>
    {
      /* Check the PLL ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 8008ec0:	4b36      	ldr	r3, [pc, #216]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008ec2:	681b      	ldr	r3, [r3, #0]
 8008ec4:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8008ec8:	2b00      	cmp	r3, #0
 8008eca:	d115      	bne.n	8008ef8 <HAL_RCC_ClockConfig+0x1a0>
      {
        return HAL_ERROR;
 8008ecc:	2301      	movs	r3, #1
 8008ece:	e0ea      	b.n	80090a6 <HAL_RCC_ClockConfig+0x34e>
      }
    }
    /* CSI is selected as System Clock Source */
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
 8008ed0:	687b      	ldr	r3, [r7, #4]
 8008ed2:	685b      	ldr	r3, [r3, #4]
 8008ed4:	2b01      	cmp	r3, #1
 8008ed6:	d107      	bne.n	8008ee8 <HAL_RCC_ClockConfig+0x190>
    {
      /* Check the PLL ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
 8008ed8:	4b30      	ldr	r3, [pc, #192]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008eda:	681b      	ldr	r3, [r3, #0]
 8008edc:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8008ee0:	2b00      	cmp	r3, #0
 8008ee2:	d109      	bne.n	8008ef8 <HAL_RCC_ClockConfig+0x1a0>
      {
        return HAL_ERROR;
 8008ee4:	2301      	movs	r3, #1
 8008ee6:	e0de      	b.n	80090a6 <HAL_RCC_ClockConfig+0x34e>
    }
    /* HSI is selected as System Clock Source */
    else
    {
      /* Check the HSI ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 8008ee8:	4b2c      	ldr	r3, [pc, #176]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008eea:	681b      	ldr	r3, [r3, #0]
 8008eec:	f003 0304 	and.w	r3, r3, #4
 8008ef0:	2b00      	cmp	r3, #0
 8008ef2:	d101      	bne.n	8008ef8 <HAL_RCC_ClockConfig+0x1a0>
      {
        return HAL_ERROR;
 8008ef4:	2301      	movs	r3, #1
 8008ef6:	e0d6      	b.n	80090a6 <HAL_RCC_ClockConfig+0x34e>
      }
    }
    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 8008ef8:	4b28      	ldr	r3, [pc, #160]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008efa:	691b      	ldr	r3, [r3, #16]
 8008efc:	f023 0207 	bic.w	r2, r3, #7
 8008f00:	687b      	ldr	r3, [r7, #4]
 8008f02:	685b      	ldr	r3, [r3, #4]
 8008f04:	4925      	ldr	r1, [pc, #148]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008f06:	4313      	orrs	r3, r2
 8008f08:	610b      	str	r3, [r1, #16]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 8008f0a:	f7fa fadb 	bl	80034c4 <HAL_GetTick>
 8008f0e:	6178      	str	r0, [r7, #20]

    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8008f10:	e00a      	b.n	8008f28 <HAL_RCC_ClockConfig+0x1d0>
    {
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8008f12:	f7fa fad7 	bl	80034c4 <HAL_GetTick>
 8008f16:	4602      	mov	r2, r0
 8008f18:	697b      	ldr	r3, [r7, #20]
 8008f1a:	1ad3      	subs	r3, r2, r3
 8008f1c:	f241 3288 	movw	r2, #5000	@ 0x1388
 8008f20:	4293      	cmp	r3, r2
 8008f22:	d901      	bls.n	8008f28 <HAL_RCC_ClockConfig+0x1d0>
      {
        return HAL_TIMEOUT;
 8008f24:	2303      	movs	r3, #3
 8008f26:	e0be      	b.n	80090a6 <HAL_RCC_ClockConfig+0x34e>
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8008f28:	4b1c      	ldr	r3, [pc, #112]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008f2a:	691b      	ldr	r3, [r3, #16]
 8008f2c:	f003 0238 	and.w	r2, r3, #56	@ 0x38
 8008f30:	687b      	ldr	r3, [r7, #4]
 8008f32:	685b      	ldr	r3, [r3, #4]
 8008f34:	00db      	lsls	r3, r3, #3
 8008f36:	429a      	cmp	r2, r3
 8008f38:	d1eb      	bne.n	8008f12 <HAL_RCC_ClockConfig+0x1ba>

  }

  /* Decreasing the BUS frequency divider */
  /*-------------------------- HCLK Configuration --------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8008f3a:	687b      	ldr	r3, [r7, #4]
 8008f3c:	681b      	ldr	r3, [r3, #0]
 8008f3e:	f003 0302 	and.w	r3, r3, #2
 8008f42:	2b00      	cmp	r3, #0
 8008f44:	d010      	beq.n	8008f68 <HAL_RCC_ClockConfig+0x210>
  {
#if defined(RCC_D1CFGR_HPRE)
    if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
 8008f46:	687b      	ldr	r3, [r7, #4]
 8008f48:	68da      	ldr	r2, [r3, #12]
 8008f4a:	4b14      	ldr	r3, [pc, #80]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008f4c:	699b      	ldr	r3, [r3, #24]
 8008f4e:	f003 030f 	and.w	r3, r3, #15
 8008f52:	429a      	cmp	r2, r3
 8008f54:	d208      	bcs.n	8008f68 <HAL_RCC_ClockConfig+0x210>
    {
      /* Set the new HCLK clock divider */
      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8008f56:	4b11      	ldr	r3, [pc, #68]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008f58:	699b      	ldr	r3, [r3, #24]
 8008f5a:	f023 020f 	bic.w	r2, r3, #15
 8008f5e:	687b      	ldr	r3, [r7, #4]
 8008f60:	68db      	ldr	r3, [r3, #12]
 8008f62:	490e      	ldr	r1, [pc, #56]	@ (8008f9c <HAL_RCC_ClockConfig+0x244>)
 8008f64:	4313      	orrs	r3, r2
 8008f66:	618b      	str	r3, [r1, #24]
    }
#endif
  }

  /* Decreasing the number of wait states because of lower CPU frequency */
  if (FLatency < __HAL_FLASH_GET_LATENCY())
 8008f68:	4b0b      	ldr	r3, [pc, #44]	@ (8008f98 <HAL_RCC_ClockConfig+0x240>)
 8008f6a:	681b      	ldr	r3, [r3, #0]
 8008f6c:	f003 030f 	and.w	r3, r3, #15
 8008f70:	683a      	ldr	r2, [r7, #0]
 8008f72:	429a      	cmp	r2, r3
 8008f74:	d214      	bcs.n	8008fa0 <HAL_RCC_ClockConfig+0x248>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8008f76:	4b08      	ldr	r3, [pc, #32]	@ (8008f98 <HAL_RCC_ClockConfig+0x240>)
 8008f78:	681b      	ldr	r3, [r3, #0]
 8008f7a:	f023 020f 	bic.w	r2, r3, #15
 8008f7e:	4906      	ldr	r1, [pc, #24]	@ (8008f98 <HAL_RCC_ClockConfig+0x240>)
 8008f80:	683b      	ldr	r3, [r7, #0]
 8008f82:	4313      	orrs	r3, r2
 8008f84:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 8008f86:	4b04      	ldr	r3, [pc, #16]	@ (8008f98 <HAL_RCC_ClockConfig+0x240>)
 8008f88:	681b      	ldr	r3, [r3, #0]
 8008f8a:	f003 030f 	and.w	r3, r3, #15
 8008f8e:	683a      	ldr	r2, [r7, #0]
 8008f90:	429a      	cmp	r2, r3
 8008f92:	d005      	beq.n	8008fa0 <HAL_RCC_ClockConfig+0x248>
    {
      return HAL_ERROR;
 8008f94:	2301      	movs	r3, #1
 8008f96:	e086      	b.n	80090a6 <HAL_RCC_ClockConfig+0x34e>
 8008f98:	52002000 	.word	0x52002000
 8008f9c:	58024400 	.word	0x58024400
    }
  }

  /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
 8008fa0:	687b      	ldr	r3, [r7, #4]
 8008fa2:	681b      	ldr	r3, [r3, #0]
 8008fa4:	f003 0304 	and.w	r3, r3, #4
 8008fa8:	2b00      	cmp	r3, #0
 8008faa:	d010      	beq.n	8008fce <HAL_RCC_ClockConfig+0x276>
  {
#if defined(RCC_D1CFGR_D1PPRE)
    if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
 8008fac:	687b      	ldr	r3, [r7, #4]
 8008fae:	691a      	ldr	r2, [r3, #16]
 8008fb0:	4b3f      	ldr	r3, [pc, #252]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 8008fb2:	699b      	ldr	r3, [r3, #24]
 8008fb4:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 8008fb8:	429a      	cmp	r2, r3
 8008fba:	d208      	bcs.n	8008fce <HAL_RCC_ClockConfig+0x276>
    {
      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
 8008fbc:	4b3c      	ldr	r3, [pc, #240]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 8008fbe:	699b      	ldr	r3, [r3, #24]
 8008fc0:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
 8008fc4:	687b      	ldr	r3, [r7, #4]
 8008fc6:	691b      	ldr	r3, [r3, #16]
 8008fc8:	4939      	ldr	r1, [pc, #228]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 8008fca:	4313      	orrs	r3, r2
 8008fcc:	618b      	str	r3, [r1, #24]
    }
#endif
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8008fce:	687b      	ldr	r3, [r7, #4]
 8008fd0:	681b      	ldr	r3, [r3, #0]
 8008fd2:	f003 0308 	and.w	r3, r3, #8
 8008fd6:	2b00      	cmp	r3, #0
 8008fd8:	d010      	beq.n	8008ffc <HAL_RCC_ClockConfig+0x2a4>
  {
#if defined(RCC_D2CFGR_D2PPRE1)
    if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
 8008fda:	687b      	ldr	r3, [r7, #4]
 8008fdc:	695a      	ldr	r2, [r3, #20]
 8008fde:	4b34      	ldr	r3, [pc, #208]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 8008fe0:	69db      	ldr	r3, [r3, #28]
 8008fe2:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 8008fe6:	429a      	cmp	r2, r3
 8008fe8:	d208      	bcs.n	8008ffc <HAL_RCC_ClockConfig+0x2a4>
    {
      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
 8008fea:	4b31      	ldr	r3, [pc, #196]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 8008fec:	69db      	ldr	r3, [r3, #28]
 8008fee:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
 8008ff2:	687b      	ldr	r3, [r7, #4]
 8008ff4:	695b      	ldr	r3, [r3, #20]
 8008ff6:	492e      	ldr	r1, [pc, #184]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 8008ff8:	4313      	orrs	r3, r2
 8008ffa:	61cb      	str	r3, [r1, #28]
    }
#endif
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8008ffc:	687b      	ldr	r3, [r7, #4]
 8008ffe:	681b      	ldr	r3, [r3, #0]
 8009000:	f003 0310 	and.w	r3, r3, #16
 8009004:	2b00      	cmp	r3, #0
 8009006:	d010      	beq.n	800902a <HAL_RCC_ClockConfig+0x2d2>
  {
#if defined (RCC_D2CFGR_D2PPRE2)
    if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
 8009008:	687b      	ldr	r3, [r7, #4]
 800900a:	699a      	ldr	r2, [r3, #24]
 800900c:	4b28      	ldr	r3, [pc, #160]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 800900e:	69db      	ldr	r3, [r3, #28]
 8009010:	f403 63e0 	and.w	r3, r3, #1792	@ 0x700
 8009014:	429a      	cmp	r2, r3
 8009016:	d208      	bcs.n	800902a <HAL_RCC_ClockConfig+0x2d2>
    {
      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
 8009018:	4b25      	ldr	r3, [pc, #148]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 800901a:	69db      	ldr	r3, [r3, #28]
 800901c:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
 8009020:	687b      	ldr	r3, [r7, #4]
 8009022:	699b      	ldr	r3, [r3, #24]
 8009024:	4922      	ldr	r1, [pc, #136]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 8009026:	4313      	orrs	r3, r2
 8009028:	61cb      	str	r3, [r1, #28]
    }
#endif
  }

  /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
 800902a:	687b      	ldr	r3, [r7, #4]
 800902c:	681b      	ldr	r3, [r3, #0]
 800902e:	f003 0320 	and.w	r3, r3, #32
 8009032:	2b00      	cmp	r3, #0
 8009034:	d010      	beq.n	8009058 <HAL_RCC_ClockConfig+0x300>
  {
#if defined(RCC_D3CFGR_D3PPRE)
    if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
 8009036:	687b      	ldr	r3, [r7, #4]
 8009038:	69da      	ldr	r2, [r3, #28]
 800903a:	4b1d      	ldr	r3, [pc, #116]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 800903c:	6a1b      	ldr	r3, [r3, #32]
 800903e:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 8009042:	429a      	cmp	r2, r3
 8009044:	d208      	bcs.n	8009058 <HAL_RCC_ClockConfig+0x300>
    {
      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
 8009046:	4b1a      	ldr	r3, [pc, #104]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 8009048:	6a1b      	ldr	r3, [r3, #32]
 800904a:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
 800904e:	687b      	ldr	r3, [r7, #4]
 8009050:	69db      	ldr	r3, [r3, #28]
 8009052:	4917      	ldr	r1, [pc, #92]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 8009054:	4313      	orrs	r3, r2
 8009056:	620b      	str	r3, [r1, #32]
#endif
  }

  /* Update the SystemCoreClock global variable */
#if defined(RCC_D1CFGR_D1CPRE)
  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
 8009058:	f000 f834 	bl	80090c4 <HAL_RCC_GetSysClockFreq>
 800905c:	4602      	mov	r2, r0
 800905e:	4b14      	ldr	r3, [pc, #80]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 8009060:	699b      	ldr	r3, [r3, #24]
 8009062:	0a1b      	lsrs	r3, r3, #8
 8009064:	f003 030f 	and.w	r3, r3, #15
 8009068:	4912      	ldr	r1, [pc, #72]	@ (80090b4 <HAL_RCC_ClockConfig+0x35c>)
 800906a:	5ccb      	ldrb	r3, [r1, r3]
 800906c:	f003 031f 	and.w	r3, r3, #31
 8009070:	fa22 f303 	lsr.w	r3, r2, r3
 8009074:	613b      	str	r3, [r7, #16]
#else
  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif

#if defined(RCC_D1CFGR_HPRE)
  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 8009076:	4b0e      	ldr	r3, [pc, #56]	@ (80090b0 <HAL_RCC_ClockConfig+0x358>)
 8009078:	699b      	ldr	r3, [r3, #24]
 800907a:	f003 030f 	and.w	r3, r3, #15
 800907e:	4a0d      	ldr	r2, [pc, #52]	@ (80090b4 <HAL_RCC_ClockConfig+0x35c>)
 8009080:	5cd3      	ldrb	r3, [r2, r3]
 8009082:	f003 031f 	and.w	r3, r3, #31
 8009086:	693a      	ldr	r2, [r7, #16]
 8009088:	fa22 f303 	lsr.w	r3, r2, r3
 800908c:	4a0a      	ldr	r2, [pc, #40]	@ (80090b8 <HAL_RCC_ClockConfig+0x360>)
 800908e:	6013      	str	r3, [r2, #0]
#endif

#if defined(DUAL_CORE) && defined(CORE_CM4)
  SystemCoreClock = SystemD2Clock;
#else
  SystemCoreClock = common_system_clock;
 8009090:	4a0a      	ldr	r2, [pc, #40]	@ (80090bc <HAL_RCC_ClockConfig+0x364>)
 8009092:	693b      	ldr	r3, [r7, #16]
 8009094:	6013      	str	r3, [r2, #0]
#endif /* DUAL_CORE && CORE_CM4 */

  /* Configure the source of time base considering new system clocks settings*/
  halstatus = HAL_InitTick(uwTickPrio);
 8009096:	4b0a      	ldr	r3, [pc, #40]	@ (80090c0 <HAL_RCC_ClockConfig+0x368>)
 8009098:	681b      	ldr	r3, [r3, #0]
 800909a:	4618      	mov	r0, r3
 800909c:	f7f9 fa4a 	bl	8002534 <HAL_InitTick>
 80090a0:	4603      	mov	r3, r0
 80090a2:	73fb      	strb	r3, [r7, #15]

  return halstatus;
 80090a4:	7bfb      	ldrb	r3, [r7, #15]
}
 80090a6:	4618      	mov	r0, r3
 80090a8:	3718      	adds	r7, #24
 80090aa:	46bd      	mov	sp, r7
 80090ac:	bd80      	pop	{r7, pc}
 80090ae:	bf00      	nop
 80090b0:	58024400 	.word	0x58024400
 80090b4:	080145e4 	.word	0x080145e4
 80090b8:	24000038 	.word	0x24000038
 80090bc:	24000034 	.word	0x24000034
 80090c0:	2400003c 	.word	0x2400003c

080090c4 <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 80090c4:	b480      	push	{r7}
 80090c6:	b089      	sub	sp, #36	@ 0x24
 80090c8:	af00      	add	r7, sp, #0
  float_t fracn1, pllvco;
  uint32_t sysclockfreq;

  /* Get SYSCLK source -------------------------------------------------------*/

  switch (RCC->CFGR & RCC_CFGR_SWS)
 80090ca:	4bb3      	ldr	r3, [pc, #716]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 80090cc:	691b      	ldr	r3, [r3, #16]
 80090ce:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 80090d2:	2b18      	cmp	r3, #24
 80090d4:	f200 8155 	bhi.w	8009382 <HAL_RCC_GetSysClockFreq+0x2be>
 80090d8:	a201      	add	r2, pc, #4	@ (adr r2, 80090e0 <HAL_RCC_GetSysClockFreq+0x1c>)
 80090da:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80090de:	bf00      	nop
 80090e0:	08009145 	.word	0x08009145
 80090e4:	08009383 	.word	0x08009383
 80090e8:	08009383 	.word	0x08009383
 80090ec:	08009383 	.word	0x08009383
 80090f0:	08009383 	.word	0x08009383
 80090f4:	08009383 	.word	0x08009383
 80090f8:	08009383 	.word	0x08009383
 80090fc:	08009383 	.word	0x08009383
 8009100:	0800916b 	.word	0x0800916b
 8009104:	08009383 	.word	0x08009383
 8009108:	08009383 	.word	0x08009383
 800910c:	08009383 	.word	0x08009383
 8009110:	08009383 	.word	0x08009383
 8009114:	08009383 	.word	0x08009383
 8009118:	08009383 	.word	0x08009383
 800911c:	08009383 	.word	0x08009383
 8009120:	08009171 	.word	0x08009171
 8009124:	08009383 	.word	0x08009383
 8009128:	08009383 	.word	0x08009383
 800912c:	08009383 	.word	0x08009383
 8009130:	08009383 	.word	0x08009383
 8009134:	08009383 	.word	0x08009383
 8009138:	08009383 	.word	0x08009383
 800913c:	08009383 	.word	0x08009383
 8009140:	08009177 	.word	0x08009177
  {
    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */

      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 8009144:	4b94      	ldr	r3, [pc, #592]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8009146:	681b      	ldr	r3, [r3, #0]
 8009148:	f003 0320 	and.w	r3, r3, #32
 800914c:	2b00      	cmp	r3, #0
 800914e:	d009      	beq.n	8009164 <HAL_RCC_GetSysClockFreq+0xa0>
      {
        sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 8009150:	4b91      	ldr	r3, [pc, #580]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8009152:	681b      	ldr	r3, [r3, #0]
 8009154:	08db      	lsrs	r3, r3, #3
 8009156:	f003 0303 	and.w	r3, r3, #3
 800915a:	4a90      	ldr	r2, [pc, #576]	@ (800939c <HAL_RCC_GetSysClockFreq+0x2d8>)
 800915c:	fa22 f303 	lsr.w	r3, r2, r3
 8009160:	61bb      	str	r3, [r7, #24]
      else
      {
        sysclockfreq = (uint32_t) HSI_VALUE;
      }

      break;
 8009162:	e111      	b.n	8009388 <HAL_RCC_GetSysClockFreq+0x2c4>
        sysclockfreq = (uint32_t) HSI_VALUE;
 8009164:	4b8d      	ldr	r3, [pc, #564]	@ (800939c <HAL_RCC_GetSysClockFreq+0x2d8>)
 8009166:	61bb      	str	r3, [r7, #24]
      break;
 8009168:	e10e      	b.n	8009388 <HAL_RCC_GetSysClockFreq+0x2c4>

    case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
      sysclockfreq = CSI_VALUE;
 800916a:	4b8d      	ldr	r3, [pc, #564]	@ (80093a0 <HAL_RCC_GetSysClockFreq+0x2dc>)
 800916c:	61bb      	str	r3, [r7, #24]
      break;
 800916e:	e10b      	b.n	8009388 <HAL_RCC_GetSysClockFreq+0x2c4>

    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
      sysclockfreq = HSE_VALUE;
 8009170:	4b8c      	ldr	r3, [pc, #560]	@ (80093a4 <HAL_RCC_GetSysClockFreq+0x2e0>)
 8009172:	61bb      	str	r3, [r7, #24]
      break;
 8009174:	e108      	b.n	8009388 <HAL_RCC_GetSysClockFreq+0x2c4>
    case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */

      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
      SYSCLK = PLL_VCO / PLLR
      */
      pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
 8009176:	4b88      	ldr	r3, [pc, #544]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8009178:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800917a:	f003 0303 	and.w	r3, r3, #3
 800917e:	617b      	str	r3, [r7, #20]
      pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4)  ;
 8009180:	4b85      	ldr	r3, [pc, #532]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8009182:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8009184:	091b      	lsrs	r3, r3, #4
 8009186:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
 800918a:	613b      	str	r3, [r7, #16]
      pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
 800918c:	4b82      	ldr	r3, [pc, #520]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800918e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8009190:	f003 0301 	and.w	r3, r3, #1
 8009194:	60fb      	str	r3, [r7, #12]
      fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
 8009196:	4b80      	ldr	r3, [pc, #512]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8009198:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 800919a:	08db      	lsrs	r3, r3, #3
 800919c:	f3c3 030c 	ubfx	r3, r3, #0, #13
 80091a0:	68fa      	ldr	r2, [r7, #12]
 80091a2:	fb02 f303 	mul.w	r3, r2, r3
 80091a6:	ee07 3a90 	vmov	s15, r3
 80091aa:	eef8 7a67 	vcvt.f32.u32	s15, s15
 80091ae:	edc7 7a02 	vstr	s15, [r7, #8]

      if (pllm != 0U)
 80091b2:	693b      	ldr	r3, [r7, #16]
 80091b4:	2b00      	cmp	r3, #0
 80091b6:	f000 80e1 	beq.w	800937c <HAL_RCC_GetSysClockFreq+0x2b8>
 80091ba:	697b      	ldr	r3, [r7, #20]
 80091bc:	2b02      	cmp	r3, #2
 80091be:	f000 8083 	beq.w	80092c8 <HAL_RCC_GetSysClockFreq+0x204>
 80091c2:	697b      	ldr	r3, [r7, #20]
 80091c4:	2b02      	cmp	r3, #2
 80091c6:	f200 80a1 	bhi.w	800930c <HAL_RCC_GetSysClockFreq+0x248>
 80091ca:	697b      	ldr	r3, [r7, #20]
 80091cc:	2b00      	cmp	r3, #0
 80091ce:	d003      	beq.n	80091d8 <HAL_RCC_GetSysClockFreq+0x114>
 80091d0:	697b      	ldr	r3, [r7, #20]
 80091d2:	2b01      	cmp	r3, #1
 80091d4:	d056      	beq.n	8009284 <HAL_RCC_GetSysClockFreq+0x1c0>
 80091d6:	e099      	b.n	800930c <HAL_RCC_GetSysClockFreq+0x248>
      {
        switch (pllsource)
        {
          case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */

            if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 80091d8:	4b6f      	ldr	r3, [pc, #444]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 80091da:	681b      	ldr	r3, [r3, #0]
 80091dc:	f003 0320 	and.w	r3, r3, #32
 80091e0:	2b00      	cmp	r3, #0
 80091e2:	d02d      	beq.n	8009240 <HAL_RCC_GetSysClockFreq+0x17c>
            {
              hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 80091e4:	4b6c      	ldr	r3, [pc, #432]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 80091e6:	681b      	ldr	r3, [r3, #0]
 80091e8:	08db      	lsrs	r3, r3, #3
 80091ea:	f003 0303 	and.w	r3, r3, #3
 80091ee:	4a6b      	ldr	r2, [pc, #428]	@ (800939c <HAL_RCC_GetSysClockFreq+0x2d8>)
 80091f0:	fa22 f303 	lsr.w	r3, r2, r3
 80091f4:	607b      	str	r3, [r7, #4]
              pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 80091f6:	687b      	ldr	r3, [r7, #4]
 80091f8:	ee07 3a90 	vmov	s15, r3
 80091fc:	eef8 6a67 	vcvt.f32.u32	s13, s15
 8009200:	693b      	ldr	r3, [r7, #16]
 8009202:	ee07 3a90 	vmov	s15, r3
 8009206:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800920a:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800920e:	4b62      	ldr	r3, [pc, #392]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8009210:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8009212:	f3c3 0308 	ubfx	r3, r3, #0, #9
 8009216:	ee07 3a90 	vmov	s15, r3
 800921a:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800921e:	ed97 6a02 	vldr	s12, [r7, #8]
 8009222:	eddf 5a61 	vldr	s11, [pc, #388]	@ 80093a8 <HAL_RCC_GetSysClockFreq+0x2e4>
 8009226:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800922a:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800922e:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 8009232:	ee77 7aa6 	vadd.f32	s15, s15, s13
 8009236:	ee67 7a27 	vmul.f32	s15, s14, s15
 800923a:	edc7 7a07 	vstr	s15, [r7, #28]
            }
            else
            {
              pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
            }
            break;
 800923e:	e087      	b.n	8009350 <HAL_RCC_GetSysClockFreq+0x28c>
              pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 8009240:	693b      	ldr	r3, [r7, #16]
 8009242:	ee07 3a90 	vmov	s15, r3
 8009246:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800924a:	eddf 6a58 	vldr	s13, [pc, #352]	@ 80093ac <HAL_RCC_GetSysClockFreq+0x2e8>
 800924e:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 8009252:	4b51      	ldr	r3, [pc, #324]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8009254:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8009256:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800925a:	ee07 3a90 	vmov	s15, r3
 800925e:	eef8 6a67 	vcvt.f32.u32	s13, s15
 8009262:	ed97 6a02 	vldr	s12, [r7, #8]
 8009266:	eddf 5a50 	vldr	s11, [pc, #320]	@ 80093a8 <HAL_RCC_GetSysClockFreq+0x2e4>
 800926a:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800926e:	ee76 7aa7 	vadd.f32	s15, s13, s15
 8009272:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 8009276:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800927a:	ee67 7a27 	vmul.f32	s15, s14, s15
 800927e:	edc7 7a07 	vstr	s15, [r7, #28]
            break;
 8009282:	e065      	b.n	8009350 <HAL_RCC_GetSysClockFreq+0x28c>

          case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
            pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 8009284:	693b      	ldr	r3, [r7, #16]
 8009286:	ee07 3a90 	vmov	s15, r3
 800928a:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800928e:	eddf 6a48 	vldr	s13, [pc, #288]	@ 80093b0 <HAL_RCC_GetSysClockFreq+0x2ec>
 8009292:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 8009296:	4b40      	ldr	r3, [pc, #256]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8009298:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800929a:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800929e:	ee07 3a90 	vmov	s15, r3
 80092a2:	eef8 6a67 	vcvt.f32.u32	s13, s15
 80092a6:	ed97 6a02 	vldr	s12, [r7, #8]
 80092aa:	eddf 5a3f 	vldr	s11, [pc, #252]	@ 80093a8 <HAL_RCC_GetSysClockFreq+0x2e4>
 80092ae:	eec6 7a25 	vdiv.f32	s15, s12, s11
 80092b2:	ee76 7aa7 	vadd.f32	s15, s13, s15
 80092b6:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 80092ba:	ee77 7aa6 	vadd.f32	s15, s15, s13
 80092be:	ee67 7a27 	vmul.f32	s15, s14, s15
 80092c2:	edc7 7a07 	vstr	s15, [r7, #28]
            break;
 80092c6:	e043      	b.n	8009350 <HAL_RCC_GetSysClockFreq+0x28c>

          case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
            pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 80092c8:	693b      	ldr	r3, [r7, #16]
 80092ca:	ee07 3a90 	vmov	s15, r3
 80092ce:	eef8 7a67 	vcvt.f32.u32	s15, s15
 80092d2:	eddf 6a38 	vldr	s13, [pc, #224]	@ 80093b4 <HAL_RCC_GetSysClockFreq+0x2f0>
 80092d6:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 80092da:	4b2f      	ldr	r3, [pc, #188]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 80092dc:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 80092de:	f3c3 0308 	ubfx	r3, r3, #0, #9
 80092e2:	ee07 3a90 	vmov	s15, r3
 80092e6:	eef8 6a67 	vcvt.f32.u32	s13, s15
 80092ea:	ed97 6a02 	vldr	s12, [r7, #8]
 80092ee:	eddf 5a2e 	vldr	s11, [pc, #184]	@ 80093a8 <HAL_RCC_GetSysClockFreq+0x2e4>
 80092f2:	eec6 7a25 	vdiv.f32	s15, s12, s11
 80092f6:	ee76 7aa7 	vadd.f32	s15, s13, s15
 80092fa:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 80092fe:	ee77 7aa6 	vadd.f32	s15, s15, s13
 8009302:	ee67 7a27 	vmul.f32	s15, s14, s15
 8009306:	edc7 7a07 	vstr	s15, [r7, #28]
            break;
 800930a:	e021      	b.n	8009350 <HAL_RCC_GetSysClockFreq+0x28c>

          default:
            pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800930c:	693b      	ldr	r3, [r7, #16]
 800930e:	ee07 3a90 	vmov	s15, r3
 8009312:	eef8 7a67 	vcvt.f32.u32	s15, s15
 8009316:	eddf 6a26 	vldr	s13, [pc, #152]	@ 80093b0 <HAL_RCC_GetSysClockFreq+0x2ec>
 800931a:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800931e:	4b1e      	ldr	r3, [pc, #120]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8009320:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8009322:	f3c3 0308 	ubfx	r3, r3, #0, #9
 8009326:	ee07 3a90 	vmov	s15, r3
 800932a:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800932e:	ed97 6a02 	vldr	s12, [r7, #8]
 8009332:	eddf 5a1d 	vldr	s11, [pc, #116]	@ 80093a8 <HAL_RCC_GetSysClockFreq+0x2e4>
 8009336:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800933a:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800933e:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 8009342:	ee77 7aa6 	vadd.f32	s15, s15, s13
 8009346:	ee67 7a27 	vmul.f32	s15, s14, s15
 800934a:	edc7 7a07 	vstr	s15, [r7, #28]
            break;
 800934e:	bf00      	nop
        }
        pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
 8009350:	4b11      	ldr	r3, [pc, #68]	@ (8009398 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8009352:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8009354:	0a5b      	lsrs	r3, r3, #9
 8009356:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800935a:	3301      	adds	r3, #1
 800935c:	603b      	str	r3, [r7, #0]
        sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
 800935e:	683b      	ldr	r3, [r7, #0]
 8009360:	ee07 3a90 	vmov	s15, r3
 8009364:	eeb8 7a67 	vcvt.f32.u32	s14, s15
 8009368:	edd7 6a07 	vldr	s13, [r7, #28]
 800936c:	eec6 7a87 	vdiv.f32	s15, s13, s14
 8009370:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 8009374:	ee17 3a90 	vmov	r3, s15
 8009378:	61bb      	str	r3, [r7, #24]
      }
      else
      {
        sysclockfreq = 0U;
      }
      break;
 800937a:	e005      	b.n	8009388 <HAL_RCC_GetSysClockFreq+0x2c4>
        sysclockfreq = 0U;
 800937c:	2300      	movs	r3, #0
 800937e:	61bb      	str	r3, [r7, #24]
      break;
 8009380:	e002      	b.n	8009388 <HAL_RCC_GetSysClockFreq+0x2c4>

    default:
      sysclockfreq = CSI_VALUE;
 8009382:	4b07      	ldr	r3, [pc, #28]	@ (80093a0 <HAL_RCC_GetSysClockFreq+0x2dc>)
 8009384:	61bb      	str	r3, [r7, #24]
      break;
 8009386:	bf00      	nop
  }

  return sysclockfreq;
 8009388:	69bb      	ldr	r3, [r7, #24]
}
 800938a:	4618      	mov	r0, r3
 800938c:	3724      	adds	r7, #36	@ 0x24
 800938e:	46bd      	mov	sp, r7
 8009390:	f85d 7b04 	ldr.w	r7, [sp], #4
 8009394:	4770      	bx	lr
 8009396:	bf00      	nop
 8009398:	58024400 	.word	0x58024400
 800939c:	03d09000 	.word	0x03d09000
 80093a0:	003d0900 	.word	0x003d0900
 80093a4:	017d7840 	.word	0x017d7840
 80093a8:	46000000 	.word	0x46000000
 80093ac:	4c742400 	.word	0x4c742400
 80093b0:	4a742400 	.word	0x4a742400
 80093b4:	4bbebc20 	.word	0x4bbebc20

080093b8 <HAL_RCC_GetHCLKFreq>:
  * @note   The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
  *         and updated within this function
  * @retval HCLK frequency
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 80093b8:	b580      	push	{r7, lr}
 80093ba:	b082      	sub	sp, #8
 80093bc:	af00      	add	r7, sp, #0
  uint32_t common_system_clock;

#if defined(RCC_D1CFGR_D1CPRE)
  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
 80093be:	f7ff fe81 	bl	80090c4 <HAL_RCC_GetSysClockFreq>
 80093c2:	4602      	mov	r2, r0
 80093c4:	4b10      	ldr	r3, [pc, #64]	@ (8009408 <HAL_RCC_GetHCLKFreq+0x50>)
 80093c6:	699b      	ldr	r3, [r3, #24]
 80093c8:	0a1b      	lsrs	r3, r3, #8
 80093ca:	f003 030f 	and.w	r3, r3, #15
 80093ce:	490f      	ldr	r1, [pc, #60]	@ (800940c <HAL_RCC_GetHCLKFreq+0x54>)
 80093d0:	5ccb      	ldrb	r3, [r1, r3]
 80093d2:	f003 031f 	and.w	r3, r3, #31
 80093d6:	fa22 f303 	lsr.w	r3, r2, r3
 80093da:	607b      	str	r3, [r7, #4]
#else
  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
#endif

#if defined(RCC_D1CFGR_HPRE)
  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 80093dc:	4b0a      	ldr	r3, [pc, #40]	@ (8009408 <HAL_RCC_GetHCLKFreq+0x50>)
 80093de:	699b      	ldr	r3, [r3, #24]
 80093e0:	f003 030f 	and.w	r3, r3, #15
 80093e4:	4a09      	ldr	r2, [pc, #36]	@ (800940c <HAL_RCC_GetHCLKFreq+0x54>)
 80093e6:	5cd3      	ldrb	r3, [r2, r3]
 80093e8:	f003 031f 	and.w	r3, r3, #31
 80093ec:	687a      	ldr	r2, [r7, #4]
 80093ee:	fa22 f303 	lsr.w	r3, r2, r3
 80093f2:	4a07      	ldr	r2, [pc, #28]	@ (8009410 <HAL_RCC_GetHCLKFreq+0x58>)
 80093f4:	6013      	str	r3, [r2, #0]
#endif

#if defined(DUAL_CORE) && defined(CORE_CM4)
  SystemCoreClock = SystemD2Clock;
#else
  SystemCoreClock = common_system_clock;
 80093f6:	4a07      	ldr	r2, [pc, #28]	@ (8009414 <HAL_RCC_GetHCLKFreq+0x5c>)
 80093f8:	687b      	ldr	r3, [r7, #4]
 80093fa:	6013      	str	r3, [r2, #0]
#endif /* DUAL_CORE && CORE_CM4 */

  return SystemD2Clock;
 80093fc:	4b04      	ldr	r3, [pc, #16]	@ (8009410 <HAL_RCC_GetHCLKFreq+0x58>)
 80093fe:	681b      	ldr	r3, [r3, #0]
}
 8009400:	4618      	mov	r0, r3
 8009402:	3708      	adds	r7, #8
 8009404:	46bd      	mov	sp, r7
 8009406:	bd80      	pop	{r7, pc}
 8009408:	58024400 	.word	0x58024400
 800940c:	080145e4 	.word	0x080145e4
 8009410:	24000038 	.word	0x24000038
 8009414:	24000034 	.word	0x24000034

08009418 <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 8009418:	b580      	push	{r7, lr}
 800941a:	af00      	add	r7, sp, #0
#if defined (RCC_D2CFGR_D2PPRE1)
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
 800941c:	f7ff ffcc 	bl	80093b8 <HAL_RCC_GetHCLKFreq>
 8009420:	4602      	mov	r2, r0
 8009422:	4b06      	ldr	r3, [pc, #24]	@ (800943c <HAL_RCC_GetPCLK1Freq+0x24>)
 8009424:	69db      	ldr	r3, [r3, #28]
 8009426:	091b      	lsrs	r3, r3, #4
 8009428:	f003 0307 	and.w	r3, r3, #7
 800942c:	4904      	ldr	r1, [pc, #16]	@ (8009440 <HAL_RCC_GetPCLK1Freq+0x28>)
 800942e:	5ccb      	ldrb	r3, [r1, r3]
 8009430:	f003 031f 	and.w	r3, r3, #31
 8009434:	fa22 f303 	lsr.w	r3, r2, r3
#else
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
#endif
}
 8009438:	4618      	mov	r0, r3
 800943a:	bd80      	pop	{r7, pc}
 800943c:	58024400 	.word	0x58024400
 8009440:	080145e4 	.word	0x080145e4

08009444 <HAL_RCC_GetPCLK2Freq>:
  * @note   Each time PCLK2 changes, this function must be called to update the
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
 8009444:	b580      	push	{r7, lr}
 8009446:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
#if defined(RCC_D2CFGR_D2PPRE2)
  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
 8009448:	f7ff ffb6 	bl	80093b8 <HAL_RCC_GetHCLKFreq>
 800944c:	4602      	mov	r2, r0
 800944e:	4b06      	ldr	r3, [pc, #24]	@ (8009468 <HAL_RCC_GetPCLK2Freq+0x24>)
 8009450:	69db      	ldr	r3, [r3, #28]
 8009452:	0a1b      	lsrs	r3, r3, #8
 8009454:	f003 0307 	and.w	r3, r3, #7
 8009458:	4904      	ldr	r1, [pc, #16]	@ (800946c <HAL_RCC_GetPCLK2Freq+0x28>)
 800945a:	5ccb      	ldrb	r3, [r1, r3]
 800945c:	f003 031f 	and.w	r3, r3, #31
 8009460:	fa22 f303 	lsr.w	r3, r2, r3
#else
  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
#endif
}
 8009464:	4618      	mov	r0, r3
 8009466:	bd80      	pop	{r7, pc}
 8009468:	58024400 	.word	0x58024400
 800946c:	080145e4 	.word	0x080145e4

08009470 <HAL_RCC_GetClockConfig>:
  * will be configured.
  * @param  pFLatency: Pointer on the Flash Latency.
  * @retval None
  */
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
{
 8009470:	b480      	push	{r7}
 8009472:	b083      	sub	sp, #12
 8009474:	af00      	add	r7, sp, #0
 8009476:	6078      	str	r0, [r7, #4]
 8009478:	6039      	str	r1, [r7, #0]
  /* Set all possible values for the Clock type parameter --------------------*/
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
 800947a:	687b      	ldr	r3, [r7, #4]
 800947c:	223f      	movs	r2, #63	@ 0x3f
 800947e:	601a      	str	r2, [r3, #0]
                                 RCC_CLOCKTYPE_PCLK2 |  RCC_CLOCKTYPE_D3PCLK1  ;

  /* Get the SYSCLK configuration --------------------------------------------*/
  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
 8009480:	4b1a      	ldr	r3, [pc, #104]	@ (80094ec <HAL_RCC_GetClockConfig+0x7c>)
 8009482:	691b      	ldr	r3, [r3, #16]
 8009484:	f003 0207 	and.w	r2, r3, #7
 8009488:	687b      	ldr	r3, [r7, #4]
 800948a:	605a      	str	r2, [r3, #4]

#if defined(RCC_D1CFGR_D1CPRE)
  /* Get the SYSCLK configuration ----------------------------------------------*/
  RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
 800948c:	4b17      	ldr	r3, [pc, #92]	@ (80094ec <HAL_RCC_GetClockConfig+0x7c>)
 800948e:	699b      	ldr	r3, [r3, #24]
 8009490:	f403 6270 	and.w	r2, r3, #3840	@ 0xf00
 8009494:	687b      	ldr	r3, [r7, #4]
 8009496:	609a      	str	r2, [r3, #8]

  /* Get the D1HCLK configuration ----------------------------------------------*/
  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
 8009498:	4b14      	ldr	r3, [pc, #80]	@ (80094ec <HAL_RCC_GetClockConfig+0x7c>)
 800949a:	699b      	ldr	r3, [r3, #24]
 800949c:	f003 020f 	and.w	r2, r3, #15
 80094a0:	687b      	ldr	r3, [r7, #4]
 80094a2:	60da      	str	r2, [r3, #12]

  /* Get the APB3 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
 80094a4:	4b11      	ldr	r3, [pc, #68]	@ (80094ec <HAL_RCC_GetClockConfig+0x7c>)
 80094a6:	699b      	ldr	r3, [r3, #24]
 80094a8:	f003 0270 	and.w	r2, r3, #112	@ 0x70
 80094ac:	687b      	ldr	r3, [r7, #4]
 80094ae:	611a      	str	r2, [r3, #16]

  /* Get the APB1 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
 80094b0:	4b0e      	ldr	r3, [pc, #56]	@ (80094ec <HAL_RCC_GetClockConfig+0x7c>)
 80094b2:	69db      	ldr	r3, [r3, #28]
 80094b4:	f003 0270 	and.w	r2, r3, #112	@ 0x70
 80094b8:	687b      	ldr	r3, [r7, #4]
 80094ba:	615a      	str	r2, [r3, #20]

  /* Get the APB2 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
 80094bc:	4b0b      	ldr	r3, [pc, #44]	@ (80094ec <HAL_RCC_GetClockConfig+0x7c>)
 80094be:	69db      	ldr	r3, [r3, #28]
 80094c0:	f403 62e0 	and.w	r2, r3, #1792	@ 0x700
 80094c4:	687b      	ldr	r3, [r7, #4]
 80094c6:	619a      	str	r2, [r3, #24]

  /* Get the APB4 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
 80094c8:	4b08      	ldr	r3, [pc, #32]	@ (80094ec <HAL_RCC_GetClockConfig+0x7c>)
 80094ca:	6a1b      	ldr	r3, [r3, #32]
 80094cc:	f003 0270 	and.w	r2, r3, #112	@ 0x70
 80094d0:	687b      	ldr	r3, [r7, #4]
 80094d2:	61da      	str	r2, [r3, #28]
  /* Get the APB4 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE);
#endif

  /* Get the Flash Wait State (Latency) configuration ------------------------*/
  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
 80094d4:	4b06      	ldr	r3, [pc, #24]	@ (80094f0 <HAL_RCC_GetClockConfig+0x80>)
 80094d6:	681b      	ldr	r3, [r3, #0]
 80094d8:	f003 020f 	and.w	r2, r3, #15
 80094dc:	683b      	ldr	r3, [r7, #0]
 80094de:	601a      	str	r2, [r3, #0]
}
 80094e0:	bf00      	nop
 80094e2:	370c      	adds	r7, #12
 80094e4:	46bd      	mov	sp, r7
 80094e6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80094ea:	4770      	bx	lr
 80094ec:	58024400 	.word	0x58024400
 80094f0:	52002000 	.word	0x52002000

080094f4 <HAL_RCCEx_PeriphCLKConfig>:
  * (*) : Available on some STM32H7 lines only.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
 80094f4:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 80094f8:	b0c8      	sub	sp, #288	@ 0x120
 80094fa:	af00      	add	r7, sp, #0
 80094fc:	f8c7 010c 	str.w	r0, [r7, #268]	@ 0x10c
  uint32_t tmpreg;
  uint32_t tickstart;
  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
 8009500:	2300      	movs	r3, #0
 8009502:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
 8009506:	2300      	movs	r3, #0
 8009508:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e

  /*---------------------------- SPDIFRX configuration -------------------------------*/

  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
 800950c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009510:	e9d3 2300 	ldrd	r2, r3, [r3]
 8009514:	f002 6400 	and.w	r4, r2, #134217728	@ 0x8000000
 8009518:	2500      	movs	r5, #0
 800951a:	ea54 0305 	orrs.w	r3, r4, r5
 800951e:	d049      	beq.n	80095b4 <HAL_RCCEx_PeriphCLKConfig+0xc0>
  {

    switch (PeriphClkInit->SpdifrxClockSelection)
 8009520:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009524:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 8009526:	f5b3 1f40 	cmp.w	r3, #3145728	@ 0x300000
 800952a:	d02f      	beq.n	800958c <HAL_RCCEx_PeriphCLKConfig+0x98>
 800952c:	f5b3 1f40 	cmp.w	r3, #3145728	@ 0x300000
 8009530:	d828      	bhi.n	8009584 <HAL_RCCEx_PeriphCLKConfig+0x90>
 8009532:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 8009536:	d01a      	beq.n	800956e <HAL_RCCEx_PeriphCLKConfig+0x7a>
 8009538:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 800953c:	d822      	bhi.n	8009584 <HAL_RCCEx_PeriphCLKConfig+0x90>
 800953e:	2b00      	cmp	r3, #0
 8009540:	d003      	beq.n	800954a <HAL_RCCEx_PeriphCLKConfig+0x56>
 8009542:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 8009546:	d007      	beq.n	8009558 <HAL_RCCEx_PeriphCLKConfig+0x64>
 8009548:	e01c      	b.n	8009584 <HAL_RCCEx_PeriphCLKConfig+0x90>
    {
      case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
        /* Enable PLL1Q Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800954a:	4bb8      	ldr	r3, [pc, #736]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800954c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800954e:	4ab7      	ldr	r2, [pc, #732]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 8009550:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 8009554:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SPDIFRX clock source configuration done later after clock selection check */
        break;
 8009556:	e01a      	b.n	800958e <HAL_RCCEx_PeriphCLKConfig+0x9a>

      case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 8009558:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800955c:	3308      	adds	r3, #8
 800955e:	2102      	movs	r1, #2
 8009560:	4618      	mov	r0, r3
 8009562:	f002 fb45 	bl	800bbf0 <RCCEx_PLL2_Config>
 8009566:	4603      	mov	r3, r0
 8009568:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SPDIFRX clock source configuration done later after clock selection check */
        break;
 800956c:	e00f      	b.n	800958e <HAL_RCCEx_PeriphCLKConfig+0x9a>

      case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 800956e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009572:	3328      	adds	r3, #40	@ 0x28
 8009574:	2102      	movs	r1, #2
 8009576:	4618      	mov	r0, r3
 8009578:	f002 fbec 	bl	800bd54 <RCCEx_PLL3_Config>
 800957c:	4603      	mov	r3, r0
 800957e:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SPDIFRX clock source configuration done later after clock selection check */
        break;
 8009582:	e004      	b.n	800958e <HAL_RCCEx_PeriphCLKConfig+0x9a>
        /* Internal OSC clock is used as source of SPDIFRX clock*/
        /* SPDIFRX clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 8009584:	2301      	movs	r3, #1
 8009586:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800958a:	e000      	b.n	800958e <HAL_RCCEx_PeriphCLKConfig+0x9a>
        break;
 800958c:	bf00      	nop
    }

    if (ret == HAL_OK)
 800958e:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009592:	2b00      	cmp	r3, #0
 8009594:	d10a      	bne.n	80095ac <HAL_RCCEx_PeriphCLKConfig+0xb8>
    {
      /* Set the source of SPDIFRX clock*/
      __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
 8009596:	4ba5      	ldr	r3, [pc, #660]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 8009598:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800959a:	f423 1140 	bic.w	r1, r3, #3145728	@ 0x300000
 800959e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80095a2:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 80095a4:	4aa1      	ldr	r2, [pc, #644]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 80095a6:	430b      	orrs	r3, r1
 80095a8:	6513      	str	r3, [r2, #80]	@ 0x50
 80095aa:	e003      	b.n	80095b4 <HAL_RCCEx_PeriphCLKConfig+0xc0>
    }
    else
    {
      /* set overall return value */
      status = ret;
 80095ac:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 80095b0:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- SAI1 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
 80095b4:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80095b8:	e9d3 2300 	ldrd	r2, r3, [r3]
 80095bc:	f402 7880 	and.w	r8, r2, #256	@ 0x100
 80095c0:	f04f 0900 	mov.w	r9, #0
 80095c4:	ea58 0309 	orrs.w	r3, r8, r9
 80095c8:	d047      	beq.n	800965a <HAL_RCCEx_PeriphCLKConfig+0x166>
  {
    switch (PeriphClkInit->Sai1ClockSelection)
 80095ca:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80095ce:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80095d0:	2b04      	cmp	r3, #4
 80095d2:	d82a      	bhi.n	800962a <HAL_RCCEx_PeriphCLKConfig+0x136>
 80095d4:	a201      	add	r2, pc, #4	@ (adr r2, 80095dc <HAL_RCCEx_PeriphCLKConfig+0xe8>)
 80095d6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80095da:	bf00      	nop
 80095dc:	080095f1 	.word	0x080095f1
 80095e0:	080095ff 	.word	0x080095ff
 80095e4:	08009615 	.word	0x08009615
 80095e8:	08009633 	.word	0x08009633
 80095ec:	08009633 	.word	0x08009633
    {
      case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
        /* Enable SAI Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 80095f0:	4b8e      	ldr	r3, [pc, #568]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 80095f2:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80095f4:	4a8d      	ldr	r2, [pc, #564]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 80095f6:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 80095fa:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 80095fc:	e01a      	b.n	8009634 <HAL_RCCEx_PeriphCLKConfig+0x140>

      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 80095fe:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009602:	3308      	adds	r3, #8
 8009604:	2100      	movs	r1, #0
 8009606:	4618      	mov	r0, r3
 8009608:	f002 faf2 	bl	800bbf0 <RCCEx_PLL2_Config>
 800960c:	4603      	mov	r3, r0
 800960e:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 8009612:	e00f      	b.n	8009634 <HAL_RCCEx_PeriphCLKConfig+0x140>

      case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 8009614:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009618:	3328      	adds	r3, #40	@ 0x28
 800961a:	2100      	movs	r1, #0
 800961c:	4618      	mov	r0, r3
 800961e:	f002 fb99 	bl	800bd54 <RCCEx_PLL3_Config>
 8009622:	4603      	mov	r3, r0
 8009624:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 8009628:	e004      	b.n	8009634 <HAL_RCCEx_PeriphCLKConfig+0x140>
        /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
        /* SAI1 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800962a:	2301      	movs	r3, #1
 800962c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 8009630:	e000      	b.n	8009634 <HAL_RCCEx_PeriphCLKConfig+0x140>
        break;
 8009632:	bf00      	nop
    }

    if (ret == HAL_OK)
 8009634:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009638:	2b00      	cmp	r3, #0
 800963a:	d10a      	bne.n	8009652 <HAL_RCCEx_PeriphCLKConfig+0x15e>
    {
      /* Set the source of SAI1 clock*/
      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
 800963c:	4b7b      	ldr	r3, [pc, #492]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800963e:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8009640:	f023 0107 	bic.w	r1, r3, #7
 8009644:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009648:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800964a:	4a78      	ldr	r2, [pc, #480]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800964c:	430b      	orrs	r3, r1
 800964e:	6513      	str	r3, [r2, #80]	@ 0x50
 8009650:	e003      	b.n	800965a <HAL_RCCEx_PeriphCLKConfig+0x166>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8009652:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009656:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

#if defined(SAI3)
  /*---------------------------- SAI2/3 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
 800965a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800965e:	e9d3 2300 	ldrd	r2, r3, [r3]
 8009662:	f402 7a00 	and.w	sl, r2, #512	@ 0x200
 8009666:	f04f 0b00 	mov.w	fp, #0
 800966a:	ea5a 030b 	orrs.w	r3, sl, fp
 800966e:	d04c      	beq.n	800970a <HAL_RCCEx_PeriphCLKConfig+0x216>
  {
    switch (PeriphClkInit->Sai23ClockSelection)
 8009670:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009674:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8009676:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800967a:	d030      	beq.n	80096de <HAL_RCCEx_PeriphCLKConfig+0x1ea>
 800967c:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 8009680:	d829      	bhi.n	80096d6 <HAL_RCCEx_PeriphCLKConfig+0x1e2>
 8009682:	2bc0      	cmp	r3, #192	@ 0xc0
 8009684:	d02d      	beq.n	80096e2 <HAL_RCCEx_PeriphCLKConfig+0x1ee>
 8009686:	2bc0      	cmp	r3, #192	@ 0xc0
 8009688:	d825      	bhi.n	80096d6 <HAL_RCCEx_PeriphCLKConfig+0x1e2>
 800968a:	2b80      	cmp	r3, #128	@ 0x80
 800968c:	d018      	beq.n	80096c0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
 800968e:	2b80      	cmp	r3, #128	@ 0x80
 8009690:	d821      	bhi.n	80096d6 <HAL_RCCEx_PeriphCLKConfig+0x1e2>
 8009692:	2b00      	cmp	r3, #0
 8009694:	d002      	beq.n	800969c <HAL_RCCEx_PeriphCLKConfig+0x1a8>
 8009696:	2b40      	cmp	r3, #64	@ 0x40
 8009698:	d007      	beq.n	80096aa <HAL_RCCEx_PeriphCLKConfig+0x1b6>
 800969a:	e01c      	b.n	80096d6 <HAL_RCCEx_PeriphCLKConfig+0x1e2>
    {
      case RCC_SAI23CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2/3 */
        /* Enable SAI Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800969c:	4b63      	ldr	r3, [pc, #396]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800969e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80096a0:	4a62      	ldr	r2, [pc, #392]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 80096a2:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 80096a6:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SAI2/3 clock source configuration done later after clock selection check */
        break;
 80096a8:	e01c      	b.n	80096e4 <HAL_RCCEx_PeriphCLKConfig+0x1f0>

      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 80096aa:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80096ae:	3308      	adds	r3, #8
 80096b0:	2100      	movs	r1, #0
 80096b2:	4618      	mov	r0, r3
 80096b4:	f002 fa9c 	bl	800bbf0 <RCCEx_PLL2_Config>
 80096b8:	4603      	mov	r3, r0
 80096ba:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI2/3 clock source configuration done later after clock selection check */
        break;
 80096be:	e011      	b.n	80096e4 <HAL_RCCEx_PeriphCLKConfig+0x1f0>

      case RCC_SAI23CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2/3 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 80096c0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80096c4:	3328      	adds	r3, #40	@ 0x28
 80096c6:	2100      	movs	r1, #0
 80096c8:	4618      	mov	r0, r3
 80096ca:	f002 fb43 	bl	800bd54 <RCCEx_PLL3_Config>
 80096ce:	4603      	mov	r3, r0
 80096d0:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI2/3 clock source configuration done later after clock selection check */
        break;
 80096d4:	e006      	b.n	80096e4 <HAL_RCCEx_PeriphCLKConfig+0x1f0>
        /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
        /* SAI2/3 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 80096d6:	2301      	movs	r3, #1
 80096d8:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 80096dc:	e002      	b.n	80096e4 <HAL_RCCEx_PeriphCLKConfig+0x1f0>
        break;
 80096de:	bf00      	nop
 80096e0:	e000      	b.n	80096e4 <HAL_RCCEx_PeriphCLKConfig+0x1f0>
        break;
 80096e2:	bf00      	nop
    }

    if (ret == HAL_OK)
 80096e4:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 80096e8:	2b00      	cmp	r3, #0
 80096ea:	d10a      	bne.n	8009702 <HAL_RCCEx_PeriphCLKConfig+0x20e>
    {
      /* Set the source of SAI2/3 clock*/
      __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
 80096ec:	4b4f      	ldr	r3, [pc, #316]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 80096ee:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80096f0:	f423 71e0 	bic.w	r1, r3, #448	@ 0x1c0
 80096f4:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80096f8:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80096fa:	4a4c      	ldr	r2, [pc, #304]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 80096fc:	430b      	orrs	r3, r1
 80096fe:	6513      	str	r3, [r2, #80]	@ 0x50
 8009700:	e003      	b.n	800970a <HAL_RCCEx_PeriphCLKConfig+0x216>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8009702:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009706:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
  }
#endif  /*SAI2B*/

#if defined(SAI4)
  /*---------------------------- SAI4A configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
 800970a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800970e:	e9d3 2300 	ldrd	r2, r3, [r3]
 8009712:	f402 6380 	and.w	r3, r2, #1024	@ 0x400
 8009716:	f8c7 3100 	str.w	r3, [r7, #256]	@ 0x100
 800971a:	2300      	movs	r3, #0
 800971c:	f8c7 3104 	str.w	r3, [r7, #260]	@ 0x104
 8009720:	e9d7 1240 	ldrd	r1, r2, [r7, #256]	@ 0x100
 8009724:	460b      	mov	r3, r1
 8009726:	4313      	orrs	r3, r2
 8009728:	d053      	beq.n	80097d2 <HAL_RCCEx_PeriphCLKConfig+0x2de>
  {
    switch (PeriphClkInit->Sai4AClockSelection)
 800972a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800972e:	f8d3 30a8 	ldr.w	r3, [r3, #168]	@ 0xa8
 8009732:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 8009736:	d035      	beq.n	80097a4 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
 8009738:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 800973c:	d82e      	bhi.n	800979c <HAL_RCCEx_PeriphCLKConfig+0x2a8>
 800973e:	f5b3 0fc0 	cmp.w	r3, #6291456	@ 0x600000
 8009742:	d031      	beq.n	80097a8 <HAL_RCCEx_PeriphCLKConfig+0x2b4>
 8009744:	f5b3 0fc0 	cmp.w	r3, #6291456	@ 0x600000
 8009748:	d828      	bhi.n	800979c <HAL_RCCEx_PeriphCLKConfig+0x2a8>
 800974a:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
 800974e:	d01a      	beq.n	8009786 <HAL_RCCEx_PeriphCLKConfig+0x292>
 8009750:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
 8009754:	d822      	bhi.n	800979c <HAL_RCCEx_PeriphCLKConfig+0x2a8>
 8009756:	2b00      	cmp	r3, #0
 8009758:	d003      	beq.n	8009762 <HAL_RCCEx_PeriphCLKConfig+0x26e>
 800975a:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 800975e:	d007      	beq.n	8009770 <HAL_RCCEx_PeriphCLKConfig+0x27c>
 8009760:	e01c      	b.n	800979c <HAL_RCCEx_PeriphCLKConfig+0x2a8>
    {
      case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
        /* Enable SAI Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 8009762:	4b32      	ldr	r3, [pc, #200]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 8009764:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8009766:	4a31      	ldr	r2, [pc, #196]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 8009768:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800976c:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 800976e:	e01c      	b.n	80097aa <HAL_RCCEx_PeriphCLKConfig+0x2b6>

      case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 8009770:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009774:	3308      	adds	r3, #8
 8009776:	2100      	movs	r1, #0
 8009778:	4618      	mov	r0, r3
 800977a:	f002 fa39 	bl	800bbf0 <RCCEx_PLL2_Config>
 800977e:	4603      	mov	r3, r0
 8009780:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI2 clock source configuration done later after clock selection check */
        break;
 8009784:	e011      	b.n	80097aa <HAL_RCCEx_PeriphCLKConfig+0x2b6>

      case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 8009786:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800978a:	3328      	adds	r3, #40	@ 0x28
 800978c:	2100      	movs	r1, #0
 800978e:	4618      	mov	r0, r3
 8009790:	f002 fae0 	bl	800bd54 <RCCEx_PLL3_Config>
 8009794:	4603      	mov	r3, r0
 8009796:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 800979a:	e006      	b.n	80097aa <HAL_RCCEx_PeriphCLKConfig+0x2b6>
        /* SAI4A clock source configuration done later after clock selection check */
        break;
#endif /* RCC_VER_3_0 */

      default:
        ret = HAL_ERROR;
 800979c:	2301      	movs	r3, #1
 800979e:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 80097a2:	e002      	b.n	80097aa <HAL_RCCEx_PeriphCLKConfig+0x2b6>
        break;
 80097a4:	bf00      	nop
 80097a6:	e000      	b.n	80097aa <HAL_RCCEx_PeriphCLKConfig+0x2b6>
        break;
 80097a8:	bf00      	nop
    }

    if (ret == HAL_OK)
 80097aa:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 80097ae:	2b00      	cmp	r3, #0
 80097b0:	d10b      	bne.n	80097ca <HAL_RCCEx_PeriphCLKConfig+0x2d6>
    {
      /* Set the source of SAI4A clock*/
      __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
 80097b2:	4b1e      	ldr	r3, [pc, #120]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 80097b4:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80097b6:	f423 0160 	bic.w	r1, r3, #14680064	@ 0xe00000
 80097ba:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80097be:	f8d3 30a8 	ldr.w	r3, [r3, #168]	@ 0xa8
 80097c2:	4a1a      	ldr	r2, [pc, #104]	@ (800982c <HAL_RCCEx_PeriphCLKConfig+0x338>)
 80097c4:	430b      	orrs	r3, r1
 80097c6:	6593      	str	r3, [r2, #88]	@ 0x58
 80097c8:	e003      	b.n	80097d2 <HAL_RCCEx_PeriphCLKConfig+0x2de>
    }
    else
    {
      /* set overall return value */
      status = ret;
 80097ca:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 80097ce:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
  /*---------------------------- SAI4B configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
 80097d2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80097d6:	e9d3 2300 	ldrd	r2, r3, [r3]
 80097da:	f402 6300 	and.w	r3, r2, #2048	@ 0x800
 80097de:	f8c7 30f8 	str.w	r3, [r7, #248]	@ 0xf8
 80097e2:	2300      	movs	r3, #0
 80097e4:	f8c7 30fc 	str.w	r3, [r7, #252]	@ 0xfc
 80097e8:	e9d7 123e 	ldrd	r1, r2, [r7, #248]	@ 0xf8
 80097ec:	460b      	mov	r3, r1
 80097ee:	4313      	orrs	r3, r2
 80097f0:	d056      	beq.n	80098a0 <HAL_RCCEx_PeriphCLKConfig+0x3ac>
  {
    switch (PeriphClkInit->Sai4BClockSelection)
 80097f2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80097f6:	f8d3 30ac 	ldr.w	r3, [r3, #172]	@ 0xac
 80097fa:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 80097fe:	d038      	beq.n	8009872 <HAL_RCCEx_PeriphCLKConfig+0x37e>
 8009800:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 8009804:	d831      	bhi.n	800986a <HAL_RCCEx_PeriphCLKConfig+0x376>
 8009806:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
 800980a:	d034      	beq.n	8009876 <HAL_RCCEx_PeriphCLKConfig+0x382>
 800980c:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
 8009810:	d82b      	bhi.n	800986a <HAL_RCCEx_PeriphCLKConfig+0x376>
 8009812:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 8009816:	d01d      	beq.n	8009854 <HAL_RCCEx_PeriphCLKConfig+0x360>
 8009818:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800981c:	d825      	bhi.n	800986a <HAL_RCCEx_PeriphCLKConfig+0x376>
 800981e:	2b00      	cmp	r3, #0
 8009820:	d006      	beq.n	8009830 <HAL_RCCEx_PeriphCLKConfig+0x33c>
 8009822:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
 8009826:	d00a      	beq.n	800983e <HAL_RCCEx_PeriphCLKConfig+0x34a>
 8009828:	e01f      	b.n	800986a <HAL_RCCEx_PeriphCLKConfig+0x376>
 800982a:	bf00      	nop
 800982c:	58024400 	.word	0x58024400
    {
      case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
        /* Enable SAI Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 8009830:	4ba2      	ldr	r3, [pc, #648]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 8009832:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8009834:	4aa1      	ldr	r2, [pc, #644]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 8009836:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800983a:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 800983c:	e01c      	b.n	8009878 <HAL_RCCEx_PeriphCLKConfig+0x384>

      case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800983e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009842:	3308      	adds	r3, #8
 8009844:	2100      	movs	r1, #0
 8009846:	4618      	mov	r0, r3
 8009848:	f002 f9d2 	bl	800bbf0 <RCCEx_PLL2_Config>
 800984c:	4603      	mov	r3, r0
 800984e:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI2 clock source configuration done later after clock selection check */
        break;
 8009852:	e011      	b.n	8009878 <HAL_RCCEx_PeriphCLKConfig+0x384>

      case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 8009854:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009858:	3328      	adds	r3, #40	@ 0x28
 800985a:	2100      	movs	r1, #0
 800985c:	4618      	mov	r0, r3
 800985e:	f002 fa79 	bl	800bd54 <RCCEx_PLL3_Config>
 8009862:	4603      	mov	r3, r0
 8009864:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 8009868:	e006      	b.n	8009878 <HAL_RCCEx_PeriphCLKConfig+0x384>
        /* SAI4B clock source configuration done later after clock selection check */
        break;
#endif /* RCC_VER_3_0 */

      default:
        ret = HAL_ERROR;
 800986a:	2301      	movs	r3, #1
 800986c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 8009870:	e002      	b.n	8009878 <HAL_RCCEx_PeriphCLKConfig+0x384>
        break;
 8009872:	bf00      	nop
 8009874:	e000      	b.n	8009878 <HAL_RCCEx_PeriphCLKConfig+0x384>
        break;
 8009876:	bf00      	nop
    }

    if (ret == HAL_OK)
 8009878:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800987c:	2b00      	cmp	r3, #0
 800987e:	d10b      	bne.n	8009898 <HAL_RCCEx_PeriphCLKConfig+0x3a4>
    {
      /* Set the source of SAI4B clock*/
      __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
 8009880:	4b8e      	ldr	r3, [pc, #568]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 8009882:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8009884:	f023 61e0 	bic.w	r1, r3, #117440512	@ 0x7000000
 8009888:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800988c:	f8d3 30ac 	ldr.w	r3, [r3, #172]	@ 0xac
 8009890:	4a8a      	ldr	r2, [pc, #552]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 8009892:	430b      	orrs	r3, r1
 8009894:	6593      	str	r3, [r2, #88]	@ 0x58
 8009896:	e003      	b.n	80098a0 <HAL_RCCEx_PeriphCLKConfig+0x3ac>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8009898:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800989c:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
  }
#endif  /*SAI4*/

#if defined(QUADSPI)
  /*---------------------------- QSPI configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
 80098a0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80098a4:	e9d3 2300 	ldrd	r2, r3, [r3]
 80098a8:	f002 7300 	and.w	r3, r2, #33554432	@ 0x2000000
 80098ac:	f8c7 30f0 	str.w	r3, [r7, #240]	@ 0xf0
 80098b0:	2300      	movs	r3, #0
 80098b2:	f8c7 30f4 	str.w	r3, [r7, #244]	@ 0xf4
 80098b6:	e9d7 123c 	ldrd	r1, r2, [r7, #240]	@ 0xf0
 80098ba:	460b      	mov	r3, r1
 80098bc:	4313      	orrs	r3, r2
 80098be:	d03a      	beq.n	8009936 <HAL_RCCEx_PeriphCLKConfig+0x442>
  {
    switch (PeriphClkInit->QspiClockSelection)
 80098c0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80098c4:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 80098c6:	2b30      	cmp	r3, #48	@ 0x30
 80098c8:	d01f      	beq.n	800990a <HAL_RCCEx_PeriphCLKConfig+0x416>
 80098ca:	2b30      	cmp	r3, #48	@ 0x30
 80098cc:	d819      	bhi.n	8009902 <HAL_RCCEx_PeriphCLKConfig+0x40e>
 80098ce:	2b20      	cmp	r3, #32
 80098d0:	d00c      	beq.n	80098ec <HAL_RCCEx_PeriphCLKConfig+0x3f8>
 80098d2:	2b20      	cmp	r3, #32
 80098d4:	d815      	bhi.n	8009902 <HAL_RCCEx_PeriphCLKConfig+0x40e>
 80098d6:	2b00      	cmp	r3, #0
 80098d8:	d019      	beq.n	800990e <HAL_RCCEx_PeriphCLKConfig+0x41a>
 80098da:	2b10      	cmp	r3, #16
 80098dc:	d111      	bne.n	8009902 <HAL_RCCEx_PeriphCLKConfig+0x40e>
    {
      case RCC_QSPICLKSOURCE_PLL:      /* PLL is used as clock source for QSPI*/
        /* Enable QSPI Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 80098de:	4b77      	ldr	r3, [pc, #476]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 80098e0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80098e2:	4a76      	ldr	r2, [pc, #472]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 80098e4:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 80098e8:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* QSPI clock source configuration done later after clock selection check */
        break;
 80098ea:	e011      	b.n	8009910 <HAL_RCCEx_PeriphCLKConfig+0x41c>

      case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 80098ec:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80098f0:	3308      	adds	r3, #8
 80098f2:	2102      	movs	r1, #2
 80098f4:	4618      	mov	r0, r3
 80098f6:	f002 f97b 	bl	800bbf0 <RCCEx_PLL2_Config>
 80098fa:	4603      	mov	r3, r0
 80098fc:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* QSPI clock source configuration done later after clock selection check */
        break;
 8009900:	e006      	b.n	8009910 <HAL_RCCEx_PeriphCLKConfig+0x41c>
      case RCC_QSPICLKSOURCE_D1HCLK:
        /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
        break;

      default:
        ret = HAL_ERROR;
 8009902:	2301      	movs	r3, #1
 8009904:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 8009908:	e002      	b.n	8009910 <HAL_RCCEx_PeriphCLKConfig+0x41c>
        break;
 800990a:	bf00      	nop
 800990c:	e000      	b.n	8009910 <HAL_RCCEx_PeriphCLKConfig+0x41c>
        break;
 800990e:	bf00      	nop
    }

    if (ret == HAL_OK)
 8009910:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009914:	2b00      	cmp	r3, #0
 8009916:	d10a      	bne.n	800992e <HAL_RCCEx_PeriphCLKConfig+0x43a>
    {
      /* Set the source of QSPI clock*/
      __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
 8009918:	4b68      	ldr	r3, [pc, #416]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800991a:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800991c:	f023 0130 	bic.w	r1, r3, #48	@ 0x30
 8009920:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009924:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8009926:	4a65      	ldr	r2, [pc, #404]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 8009928:	430b      	orrs	r3, r1
 800992a:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800992c:	e003      	b.n	8009936 <HAL_RCCEx_PeriphCLKConfig+0x442>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800992e:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009932:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
#endif  /*OCTOSPI*/

  /*---------------------------- SPI1/2/3 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
 8009936:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800993a:	e9d3 2300 	ldrd	r2, r3, [r3]
 800993e:	f402 5380 	and.w	r3, r2, #4096	@ 0x1000
 8009942:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
 8009946:	2300      	movs	r3, #0
 8009948:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
 800994c:	e9d7 123a 	ldrd	r1, r2, [r7, #232]	@ 0xe8
 8009950:	460b      	mov	r3, r1
 8009952:	4313      	orrs	r3, r2
 8009954:	d051      	beq.n	80099fa <HAL_RCCEx_PeriphCLKConfig+0x506>
  {
    switch (PeriphClkInit->Spi123ClockSelection)
 8009956:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800995a:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 800995c:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 8009960:	d035      	beq.n	80099ce <HAL_RCCEx_PeriphCLKConfig+0x4da>
 8009962:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 8009966:	d82e      	bhi.n	80099c6 <HAL_RCCEx_PeriphCLKConfig+0x4d2>
 8009968:	f5b3 5f40 	cmp.w	r3, #12288	@ 0x3000
 800996c:	d031      	beq.n	80099d2 <HAL_RCCEx_PeriphCLKConfig+0x4de>
 800996e:	f5b3 5f40 	cmp.w	r3, #12288	@ 0x3000
 8009972:	d828      	bhi.n	80099c6 <HAL_RCCEx_PeriphCLKConfig+0x4d2>
 8009974:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 8009978:	d01a      	beq.n	80099b0 <HAL_RCCEx_PeriphCLKConfig+0x4bc>
 800997a:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800997e:	d822      	bhi.n	80099c6 <HAL_RCCEx_PeriphCLKConfig+0x4d2>
 8009980:	2b00      	cmp	r3, #0
 8009982:	d003      	beq.n	800998c <HAL_RCCEx_PeriphCLKConfig+0x498>
 8009984:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 8009988:	d007      	beq.n	800999a <HAL_RCCEx_PeriphCLKConfig+0x4a6>
 800998a:	e01c      	b.n	80099c6 <HAL_RCCEx_PeriphCLKConfig+0x4d2>
    {
      case RCC_SPI123CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1/2/3 */
        /* Enable SPI Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800998c:	4b4b      	ldr	r3, [pc, #300]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800998e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8009990:	4a4a      	ldr	r2, [pc, #296]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 8009992:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 8009996:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SPI1/2/3 clock source configuration done later after clock selection check */
        break;
 8009998:	e01c      	b.n	80099d4 <HAL_RCCEx_PeriphCLKConfig+0x4e0>

      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800999a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800999e:	3308      	adds	r3, #8
 80099a0:	2100      	movs	r1, #0
 80099a2:	4618      	mov	r0, r3
 80099a4:	f002 f924 	bl	800bbf0 <RCCEx_PLL2_Config>
 80099a8:	4603      	mov	r3, r0
 80099aa:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SPI1/2/3 clock source configuration done later after clock selection check */
        break;
 80099ae:	e011      	b.n	80099d4 <HAL_RCCEx_PeriphCLKConfig+0x4e0>

      case RCC_SPI123CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1/2/3 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 80099b0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80099b4:	3328      	adds	r3, #40	@ 0x28
 80099b6:	2100      	movs	r1, #0
 80099b8:	4618      	mov	r0, r3
 80099ba:	f002 f9cb 	bl	800bd54 <RCCEx_PLL3_Config>
 80099be:	4603      	mov	r3, r0
 80099c0:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SPI1/2/3 clock source configuration done later after clock selection check */
        break;
 80099c4:	e006      	b.n	80099d4 <HAL_RCCEx_PeriphCLKConfig+0x4e0>
        /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
        /* SPI1/2/3 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 80099c6:	2301      	movs	r3, #1
 80099c8:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 80099cc:	e002      	b.n	80099d4 <HAL_RCCEx_PeriphCLKConfig+0x4e0>
        break;
 80099ce:	bf00      	nop
 80099d0:	e000      	b.n	80099d4 <HAL_RCCEx_PeriphCLKConfig+0x4e0>
        break;
 80099d2:	bf00      	nop
    }

    if (ret == HAL_OK)
 80099d4:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 80099d8:	2b00      	cmp	r3, #0
 80099da:	d10a      	bne.n	80099f2 <HAL_RCCEx_PeriphCLKConfig+0x4fe>
    {
      /* Set the source of SPI1/2/3 clock*/
      __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
 80099dc:	4b37      	ldr	r3, [pc, #220]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 80099de:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80099e0:	f423 41e0 	bic.w	r1, r3, #28672	@ 0x7000
 80099e4:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80099e8:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80099ea:	4a34      	ldr	r2, [pc, #208]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 80099ec:	430b      	orrs	r3, r1
 80099ee:	6513      	str	r3, [r2, #80]	@ 0x50
 80099f0:	e003      	b.n	80099fa <HAL_RCCEx_PeriphCLKConfig+0x506>
    }
    else
    {
      /* set overall return value */
      status = ret;
 80099f2:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 80099f6:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- SPI4/5 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
 80099fa:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 80099fe:	e9d3 2300 	ldrd	r2, r3, [r3]
 8009a02:	f402 5300 	and.w	r3, r2, #8192	@ 0x2000
 8009a06:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
 8009a0a:	2300      	movs	r3, #0
 8009a0c:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
 8009a10:	e9d7 1238 	ldrd	r1, r2, [r7, #224]	@ 0xe0
 8009a14:	460b      	mov	r3, r1
 8009a16:	4313      	orrs	r3, r2
 8009a18:	d056      	beq.n	8009ac8 <HAL_RCCEx_PeriphCLKConfig+0x5d4>
  {
    switch (PeriphClkInit->Spi45ClockSelection)
 8009a1a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009a1e:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8009a20:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 8009a24:	d033      	beq.n	8009a8e <HAL_RCCEx_PeriphCLKConfig+0x59a>
 8009a26:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 8009a2a:	d82c      	bhi.n	8009a86 <HAL_RCCEx_PeriphCLKConfig+0x592>
 8009a2c:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
 8009a30:	d02f      	beq.n	8009a92 <HAL_RCCEx_PeriphCLKConfig+0x59e>
 8009a32:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
 8009a36:	d826      	bhi.n	8009a86 <HAL_RCCEx_PeriphCLKConfig+0x592>
 8009a38:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
 8009a3c:	d02b      	beq.n	8009a96 <HAL_RCCEx_PeriphCLKConfig+0x5a2>
 8009a3e:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
 8009a42:	d820      	bhi.n	8009a86 <HAL_RCCEx_PeriphCLKConfig+0x592>
 8009a44:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 8009a48:	d012      	beq.n	8009a70 <HAL_RCCEx_PeriphCLKConfig+0x57c>
 8009a4a:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 8009a4e:	d81a      	bhi.n	8009a86 <HAL_RCCEx_PeriphCLKConfig+0x592>
 8009a50:	2b00      	cmp	r3, #0
 8009a52:	d022      	beq.n	8009a9a <HAL_RCCEx_PeriphCLKConfig+0x5a6>
 8009a54:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 8009a58:	d115      	bne.n	8009a86 <HAL_RCCEx_PeriphCLKConfig+0x592>
        /* SPI4/5 clock source configuration done later after clock selection check */
        break;

      case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 8009a5a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009a5e:	3308      	adds	r3, #8
 8009a60:	2101      	movs	r1, #1
 8009a62:	4618      	mov	r0, r3
 8009a64:	f002 f8c4 	bl	800bbf0 <RCCEx_PLL2_Config>
 8009a68:	4603      	mov	r3, r0
 8009a6a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SPI4/5 clock source configuration done later after clock selection check */
        break;
 8009a6e:	e015      	b.n	8009a9c <HAL_RCCEx_PeriphCLKConfig+0x5a8>
      case RCC_SPI45CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4/5 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 8009a70:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009a74:	3328      	adds	r3, #40	@ 0x28
 8009a76:	2101      	movs	r1, #1
 8009a78:	4618      	mov	r0, r3
 8009a7a:	f002 f96b 	bl	800bd54 <RCCEx_PLL3_Config>
 8009a7e:	4603      	mov	r3, r0
 8009a80:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* SPI4/5 clock source configuration done later after clock selection check */
        break;
 8009a84:	e00a      	b.n	8009a9c <HAL_RCCEx_PeriphCLKConfig+0x5a8>
        /* HSE,  oscillator is used as source of SPI4/5 clock */
        /* SPI4/5 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 8009a86:	2301      	movs	r3, #1
 8009a88:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 8009a8c:	e006      	b.n	8009a9c <HAL_RCCEx_PeriphCLKConfig+0x5a8>
        break;
 8009a8e:	bf00      	nop
 8009a90:	e004      	b.n	8009a9c <HAL_RCCEx_PeriphCLKConfig+0x5a8>
        break;
 8009a92:	bf00      	nop
 8009a94:	e002      	b.n	8009a9c <HAL_RCCEx_PeriphCLKConfig+0x5a8>
        break;
 8009a96:	bf00      	nop
 8009a98:	e000      	b.n	8009a9c <HAL_RCCEx_PeriphCLKConfig+0x5a8>
        break;
 8009a9a:	bf00      	nop
    }

    if (ret == HAL_OK)
 8009a9c:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009aa0:	2b00      	cmp	r3, #0
 8009aa2:	d10d      	bne.n	8009ac0 <HAL_RCCEx_PeriphCLKConfig+0x5cc>
    {
      /* Set the source of SPI4/5 clock*/
      __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
 8009aa4:	4b05      	ldr	r3, [pc, #20]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 8009aa6:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8009aa8:	f423 21e0 	bic.w	r1, r3, #458752	@ 0x70000
 8009aac:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009ab0:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8009ab2:	4a02      	ldr	r2, [pc, #8]	@ (8009abc <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 8009ab4:	430b      	orrs	r3, r1
 8009ab6:	6513      	str	r3, [r2, #80]	@ 0x50
 8009ab8:	e006      	b.n	8009ac8 <HAL_RCCEx_PeriphCLKConfig+0x5d4>
 8009aba:	bf00      	nop
 8009abc:	58024400 	.word	0x58024400
    }
    else
    {
      /* set overall return value */
      status = ret;
 8009ac0:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009ac4:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- SPI6 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
 8009ac8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009acc:	e9d3 2300 	ldrd	r2, r3, [r3]
 8009ad0:	f402 4380 	and.w	r3, r2, #16384	@ 0x4000
 8009ad4:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
 8009ad8:	2300      	movs	r3, #0
 8009ada:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
 8009ade:	e9d7 1236 	ldrd	r1, r2, [r7, #216]	@ 0xd8
 8009ae2:	460b      	mov	r3, r1
 8009ae4:	4313      	orrs	r3, r2
 8009ae6:	d055      	beq.n	8009b94 <HAL_RCCEx_PeriphCLKConfig+0x6a0>
  {
    switch (PeriphClkInit->Spi6ClockSelection)
 8009ae8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009aec:	f8d3 30b0 	ldr.w	r3, [r3, #176]	@ 0xb0
 8009af0:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 8009af4:	d033      	beq.n	8009b5e <HAL_RCCEx_PeriphCLKConfig+0x66a>
 8009af6:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 8009afa:	d82c      	bhi.n	8009b56 <HAL_RCCEx_PeriphCLKConfig+0x662>
 8009afc:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8009b00:	d02f      	beq.n	8009b62 <HAL_RCCEx_PeriphCLKConfig+0x66e>
 8009b02:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8009b06:	d826      	bhi.n	8009b56 <HAL_RCCEx_PeriphCLKConfig+0x662>
 8009b08:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
 8009b0c:	d02b      	beq.n	8009b66 <HAL_RCCEx_PeriphCLKConfig+0x672>
 8009b0e:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
 8009b12:	d820      	bhi.n	8009b56 <HAL_RCCEx_PeriphCLKConfig+0x662>
 8009b14:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 8009b18:	d012      	beq.n	8009b40 <HAL_RCCEx_PeriphCLKConfig+0x64c>
 8009b1a:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 8009b1e:	d81a      	bhi.n	8009b56 <HAL_RCCEx_PeriphCLKConfig+0x662>
 8009b20:	2b00      	cmp	r3, #0
 8009b22:	d022      	beq.n	8009b6a <HAL_RCCEx_PeriphCLKConfig+0x676>
 8009b24:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 8009b28:	d115      	bne.n	8009b56 <HAL_RCCEx_PeriphCLKConfig+0x662>
        /* SPI6 clock source configuration done later after clock selection check */
        break;

      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 8009b2a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009b2e:	3308      	adds	r3, #8
 8009b30:	2101      	movs	r1, #1
 8009b32:	4618      	mov	r0, r3
 8009b34:	f002 f85c 	bl	800bbf0 <RCCEx_PLL2_Config>
 8009b38:	4603      	mov	r3, r0
 8009b3a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SPI6 clock source configuration done later after clock selection check */
        break;
 8009b3e:	e015      	b.n	8009b6c <HAL_RCCEx_PeriphCLKConfig+0x678>
      case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 8009b40:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009b44:	3328      	adds	r3, #40	@ 0x28
 8009b46:	2101      	movs	r1, #1
 8009b48:	4618      	mov	r0, r3
 8009b4a:	f002 f903 	bl	800bd54 <RCCEx_PLL3_Config>
 8009b4e:	4603      	mov	r3, r0
 8009b50:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* SPI6 clock source configuration done later after clock selection check */
        break;
 8009b54:	e00a      	b.n	8009b6c <HAL_RCCEx_PeriphCLKConfig+0x678>
        /* SPI6 clock source configuration done later after clock selection check */
        break;
#endif

      default:
        ret = HAL_ERROR;
 8009b56:	2301      	movs	r3, #1
 8009b58:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 8009b5c:	e006      	b.n	8009b6c <HAL_RCCEx_PeriphCLKConfig+0x678>
        break;
 8009b5e:	bf00      	nop
 8009b60:	e004      	b.n	8009b6c <HAL_RCCEx_PeriphCLKConfig+0x678>
        break;
 8009b62:	bf00      	nop
 8009b64:	e002      	b.n	8009b6c <HAL_RCCEx_PeriphCLKConfig+0x678>
        break;
 8009b66:	bf00      	nop
 8009b68:	e000      	b.n	8009b6c <HAL_RCCEx_PeriphCLKConfig+0x678>
        break;
 8009b6a:	bf00      	nop
    }

    if (ret == HAL_OK)
 8009b6c:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009b70:	2b00      	cmp	r3, #0
 8009b72:	d10b      	bne.n	8009b8c <HAL_RCCEx_PeriphCLKConfig+0x698>
    {
      /* Set the source of SPI6 clock*/
      __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
 8009b74:	4ba3      	ldr	r3, [pc, #652]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009b76:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8009b78:	f023 41e0 	bic.w	r1, r3, #1879048192	@ 0x70000000
 8009b7c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009b80:	f8d3 30b0 	ldr.w	r3, [r3, #176]	@ 0xb0
 8009b84:	4a9f      	ldr	r2, [pc, #636]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009b86:	430b      	orrs	r3, r1
 8009b88:	6593      	str	r3, [r2, #88]	@ 0x58
 8009b8a:	e003      	b.n	8009b94 <HAL_RCCEx_PeriphCLKConfig+0x6a0>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8009b8c:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009b90:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
  }
#endif /*DSI*/

#if defined(FDCAN1) || defined(FDCAN2)
  /*---------------------------- FDCAN configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
 8009b94:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009b98:	e9d3 2300 	ldrd	r2, r3, [r3]
 8009b9c:	f402 4300 	and.w	r3, r2, #32768	@ 0x8000
 8009ba0:	f8c7 30d0 	str.w	r3, [r7, #208]	@ 0xd0
 8009ba4:	2300      	movs	r3, #0
 8009ba6:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
 8009baa:	e9d7 1234 	ldrd	r1, r2, [r7, #208]	@ 0xd0
 8009bae:	460b      	mov	r3, r1
 8009bb0:	4313      	orrs	r3, r2
 8009bb2:	d037      	beq.n	8009c24 <HAL_RCCEx_PeriphCLKConfig+0x730>
  {
    switch (PeriphClkInit->FdcanClockSelection)
 8009bb4:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009bb8:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8009bba:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 8009bbe:	d00e      	beq.n	8009bde <HAL_RCCEx_PeriphCLKConfig+0x6ea>
 8009bc0:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 8009bc4:	d816      	bhi.n	8009bf4 <HAL_RCCEx_PeriphCLKConfig+0x700>
 8009bc6:	2b00      	cmp	r3, #0
 8009bc8:	d018      	beq.n	8009bfc <HAL_RCCEx_PeriphCLKConfig+0x708>
 8009bca:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 8009bce:	d111      	bne.n	8009bf4 <HAL_RCCEx_PeriphCLKConfig+0x700>
    {
      case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
        /* Enable FDCAN Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 8009bd0:	4b8c      	ldr	r3, [pc, #560]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009bd2:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8009bd4:	4a8b      	ldr	r2, [pc, #556]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009bd6:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 8009bda:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* FDCAN clock source configuration done later after clock selection check */
        break;
 8009bdc:	e00f      	b.n	8009bfe <HAL_RCCEx_PeriphCLKConfig+0x70a>

      case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 8009bde:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009be2:	3308      	adds	r3, #8
 8009be4:	2101      	movs	r1, #1
 8009be6:	4618      	mov	r0, r3
 8009be8:	f002 f802 	bl	800bbf0 <RCCEx_PLL2_Config>
 8009bec:	4603      	mov	r3, r0
 8009bee:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* FDCAN clock source configuration done later after clock selection check */
        break;
 8009bf2:	e004      	b.n	8009bfe <HAL_RCCEx_PeriphCLKConfig+0x70a>
        /* HSE is used as clock source for FDCAN*/
        /* FDCAN clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 8009bf4:	2301      	movs	r3, #1
 8009bf6:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 8009bfa:	e000      	b.n	8009bfe <HAL_RCCEx_PeriphCLKConfig+0x70a>
        break;
 8009bfc:	bf00      	nop
    }

    if (ret == HAL_OK)
 8009bfe:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009c02:	2b00      	cmp	r3, #0
 8009c04:	d10a      	bne.n	8009c1c <HAL_RCCEx_PeriphCLKConfig+0x728>
    {
      /* Set the source of FDCAN clock*/
      __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
 8009c06:	4b7f      	ldr	r3, [pc, #508]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009c08:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8009c0a:	f023 5140 	bic.w	r1, r3, #805306368	@ 0x30000000
 8009c0e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009c12:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8009c14:	4a7b      	ldr	r2, [pc, #492]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009c16:	430b      	orrs	r3, r1
 8009c18:	6513      	str	r3, [r2, #80]	@ 0x50
 8009c1a:	e003      	b.n	8009c24 <HAL_RCCEx_PeriphCLKConfig+0x730>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8009c1c:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009c20:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
#endif /*FDCAN1 || FDCAN2*/

  /*---------------------------- FMC configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
 8009c24:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009c28:	e9d3 2300 	ldrd	r2, r3, [r3]
 8009c2c:	f002 7380 	and.w	r3, r2, #16777216	@ 0x1000000
 8009c30:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
 8009c34:	2300      	movs	r3, #0
 8009c36:	f8c7 30cc 	str.w	r3, [r7, #204]	@ 0xcc
 8009c3a:	e9d7 1232 	ldrd	r1, r2, [r7, #200]	@ 0xc8
 8009c3e:	460b      	mov	r3, r1
 8009c40:	4313      	orrs	r3, r2
 8009c42:	d039      	beq.n	8009cb8 <HAL_RCCEx_PeriphCLKConfig+0x7c4>
  {
    switch (PeriphClkInit->FmcClockSelection)
 8009c44:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009c48:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8009c4a:	2b03      	cmp	r3, #3
 8009c4c:	d81c      	bhi.n	8009c88 <HAL_RCCEx_PeriphCLKConfig+0x794>
 8009c4e:	a201      	add	r2, pc, #4	@ (adr r2, 8009c54 <HAL_RCCEx_PeriphCLKConfig+0x760>)
 8009c50:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8009c54:	08009c91 	.word	0x08009c91
 8009c58:	08009c65 	.word	0x08009c65
 8009c5c:	08009c73 	.word	0x08009c73
 8009c60:	08009c91 	.word	0x08009c91
    {
      case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
        /* Enable FMC Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 8009c64:	4b67      	ldr	r3, [pc, #412]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009c66:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8009c68:	4a66      	ldr	r2, [pc, #408]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009c6a:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 8009c6e:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* FMC clock source configuration done later after clock selection check */
        break;
 8009c70:	e00f      	b.n	8009c92 <HAL_RCCEx_PeriphCLKConfig+0x79e>

      case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 8009c72:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009c76:	3308      	adds	r3, #8
 8009c78:	2102      	movs	r1, #2
 8009c7a:	4618      	mov	r0, r3
 8009c7c:	f001 ffb8 	bl	800bbf0 <RCCEx_PLL2_Config>
 8009c80:	4603      	mov	r3, r0
 8009c82:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* FMC clock source configuration done later after clock selection check */
        break;
 8009c86:	e004      	b.n	8009c92 <HAL_RCCEx_PeriphCLKConfig+0x79e>
      case RCC_FMCCLKSOURCE_HCLK:
        /* D1/CD HCLK  clock selected as FMC kernel peripheral clock */
        break;

      default:
        ret = HAL_ERROR;
 8009c88:	2301      	movs	r3, #1
 8009c8a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 8009c8e:	e000      	b.n	8009c92 <HAL_RCCEx_PeriphCLKConfig+0x79e>
        break;
 8009c90:	bf00      	nop
    }

    if (ret == HAL_OK)
 8009c92:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009c96:	2b00      	cmp	r3, #0
 8009c98:	d10a      	bne.n	8009cb0 <HAL_RCCEx_PeriphCLKConfig+0x7bc>
    {
      /* Set the source of FMC clock*/
      __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
 8009c9a:	4b5a      	ldr	r3, [pc, #360]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009c9c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8009c9e:	f023 0103 	bic.w	r1, r3, #3
 8009ca2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009ca6:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8009ca8:	4a56      	ldr	r2, [pc, #344]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009caa:	430b      	orrs	r3, r1
 8009cac:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8009cae:	e003      	b.n	8009cb8 <HAL_RCCEx_PeriphCLKConfig+0x7c4>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8009cb0:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009cb4:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- RTC configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
 8009cb8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009cbc:	e9d3 2300 	ldrd	r2, r3, [r3]
 8009cc0:	f402 0380 	and.w	r3, r2, #4194304	@ 0x400000
 8009cc4:	f8c7 30c0 	str.w	r3, [r7, #192]	@ 0xc0
 8009cc8:	2300      	movs	r3, #0
 8009cca:	f8c7 30c4 	str.w	r3, [r7, #196]	@ 0xc4
 8009cce:	e9d7 1230 	ldrd	r1, r2, [r7, #192]	@ 0xc0
 8009cd2:	460b      	mov	r3, r1
 8009cd4:	4313      	orrs	r3, r2
 8009cd6:	f000 809f 	beq.w	8009e18 <HAL_RCCEx_PeriphCLKConfig+0x924>
  {
    /* check for RTC Parameters used to output RTCCLK */
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));

    /* Enable write access to Backup domain */
    SET_BIT(PWR->CR1, PWR_CR1_DBP);
 8009cda:	4b4b      	ldr	r3, [pc, #300]	@ (8009e08 <HAL_RCCEx_PeriphCLKConfig+0x914>)
 8009cdc:	681b      	ldr	r3, [r3, #0]
 8009cde:	4a4a      	ldr	r2, [pc, #296]	@ (8009e08 <HAL_RCCEx_PeriphCLKConfig+0x914>)
 8009ce0:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8009ce4:	6013      	str	r3, [r2, #0]

    /* Wait for Backup domain Write protection disable */
    tickstart = HAL_GetTick();
 8009ce6:	f7f9 fbed 	bl	80034c4 <HAL_GetTick>
 8009cea:	f8c7 0118 	str.w	r0, [r7, #280]	@ 0x118

    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
 8009cee:	e00b      	b.n	8009d08 <HAL_RCCEx_PeriphCLKConfig+0x814>
    {
      if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8009cf0:	f7f9 fbe8 	bl	80034c4 <HAL_GetTick>
 8009cf4:	4602      	mov	r2, r0
 8009cf6:	f8d7 3118 	ldr.w	r3, [r7, #280]	@ 0x118
 8009cfa:	1ad3      	subs	r3, r2, r3
 8009cfc:	2b64      	cmp	r3, #100	@ 0x64
 8009cfe:	d903      	bls.n	8009d08 <HAL_RCCEx_PeriphCLKConfig+0x814>
      {
        ret = HAL_TIMEOUT;
 8009d00:	2303      	movs	r3, #3
 8009d02:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 8009d06:	e005      	b.n	8009d14 <HAL_RCCEx_PeriphCLKConfig+0x820>
    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
 8009d08:	4b3f      	ldr	r3, [pc, #252]	@ (8009e08 <HAL_RCCEx_PeriphCLKConfig+0x914>)
 8009d0a:	681b      	ldr	r3, [r3, #0]
 8009d0c:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8009d10:	2b00      	cmp	r3, #0
 8009d12:	d0ed      	beq.n	8009cf0 <HAL_RCCEx_PeriphCLKConfig+0x7fc>
      }
    }

    if (ret == HAL_OK)
 8009d14:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009d18:	2b00      	cmp	r3, #0
 8009d1a:	d179      	bne.n	8009e10 <HAL_RCCEx_PeriphCLKConfig+0x91c>
    {
      /* Reset the Backup domain only if the RTC Clock source selection is modified */
      if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
 8009d1c:	4b39      	ldr	r3, [pc, #228]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009d1e:	6f1a      	ldr	r2, [r3, #112]	@ 0x70
 8009d20:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009d24:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
 8009d28:	4053      	eors	r3, r2
 8009d2a:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 8009d2e:	2b00      	cmp	r3, #0
 8009d30:	d015      	beq.n	8009d5e <HAL_RCCEx_PeriphCLKConfig+0x86a>
      {
        /* Store the content of BDCR register before the reset of Backup Domain */
        tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 8009d32:	4b34      	ldr	r3, [pc, #208]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009d34:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8009d36:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 8009d3a:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
        /* RTC Clock selection can be changed only if the Backup Domain is reset */
        __HAL_RCC_BACKUPRESET_FORCE();
 8009d3e:	4b31      	ldr	r3, [pc, #196]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009d40:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8009d42:	4a30      	ldr	r2, [pc, #192]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009d44:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 8009d48:	6713      	str	r3, [r2, #112]	@ 0x70
        __HAL_RCC_BACKUPRESET_RELEASE();
 8009d4a:	4b2e      	ldr	r3, [pc, #184]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009d4c:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8009d4e:	4a2d      	ldr	r2, [pc, #180]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009d50:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 8009d54:	6713      	str	r3, [r2, #112]	@ 0x70
        /* Restore the Content of BDCR register */
        RCC->BDCR = tmpreg;
 8009d56:	4a2b      	ldr	r2, [pc, #172]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009d58:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
 8009d5c:	6713      	str	r3, [r2, #112]	@ 0x70
      }

      /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
      if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
 8009d5e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009d62:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
 8009d66:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 8009d6a:	d118      	bne.n	8009d9e <HAL_RCCEx_PeriphCLKConfig+0x8aa>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8009d6c:	f7f9 fbaa 	bl	80034c4 <HAL_GetTick>
 8009d70:	f8c7 0118 	str.w	r0, [r7, #280]	@ 0x118

        /* Wait till LSE is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 8009d74:	e00d      	b.n	8009d92 <HAL_RCCEx_PeriphCLKConfig+0x89e>
        {
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8009d76:	f7f9 fba5 	bl	80034c4 <HAL_GetTick>
 8009d7a:	4602      	mov	r2, r0
 8009d7c:	f8d7 3118 	ldr.w	r3, [r7, #280]	@ 0x118
 8009d80:	1ad2      	subs	r2, r2, r3
 8009d82:	f241 3388 	movw	r3, #5000	@ 0x1388
 8009d86:	429a      	cmp	r2, r3
 8009d88:	d903      	bls.n	8009d92 <HAL_RCCEx_PeriphCLKConfig+0x89e>
          {
            ret = HAL_TIMEOUT;
 8009d8a:	2303      	movs	r3, #3
 8009d8c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
            break;
 8009d90:	e005      	b.n	8009d9e <HAL_RCCEx_PeriphCLKConfig+0x8aa>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 8009d92:	4b1c      	ldr	r3, [pc, #112]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009d94:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8009d96:	f003 0302 	and.w	r3, r3, #2
 8009d9a:	2b00      	cmp	r3, #0
 8009d9c:	d0eb      	beq.n	8009d76 <HAL_RCCEx_PeriphCLKConfig+0x882>
          }
        }
      }

      if (ret == HAL_OK)
 8009d9e:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009da2:	2b00      	cmp	r3, #0
 8009da4:	d129      	bne.n	8009dfa <HAL_RCCEx_PeriphCLKConfig+0x906>
      {
        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 8009da6:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009daa:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
 8009dae:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 8009db2:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 8009db6:	d10e      	bne.n	8009dd6 <HAL_RCCEx_PeriphCLKConfig+0x8e2>
 8009db8:	4b12      	ldr	r3, [pc, #72]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009dba:	691b      	ldr	r3, [r3, #16]
 8009dbc:	f423 517c 	bic.w	r1, r3, #16128	@ 0x3f00
 8009dc0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009dc4:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
 8009dc8:	091a      	lsrs	r2, r3, #4
 8009dca:	4b10      	ldr	r3, [pc, #64]	@ (8009e0c <HAL_RCCEx_PeriphCLKConfig+0x918>)
 8009dcc:	4013      	ands	r3, r2
 8009dce:	4a0d      	ldr	r2, [pc, #52]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009dd0:	430b      	orrs	r3, r1
 8009dd2:	6113      	str	r3, [r2, #16]
 8009dd4:	e005      	b.n	8009de2 <HAL_RCCEx_PeriphCLKConfig+0x8ee>
 8009dd6:	4b0b      	ldr	r3, [pc, #44]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009dd8:	691b      	ldr	r3, [r3, #16]
 8009dda:	4a0a      	ldr	r2, [pc, #40]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009ddc:	f423 537c 	bic.w	r3, r3, #16128	@ 0x3f00
 8009de0:	6113      	str	r3, [r2, #16]
 8009de2:	4b08      	ldr	r3, [pc, #32]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009de4:	6f19      	ldr	r1, [r3, #112]	@ 0x70
 8009de6:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009dea:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
 8009dee:	f3c3 030b 	ubfx	r3, r3, #0, #12
 8009df2:	4a04      	ldr	r2, [pc, #16]	@ (8009e04 <HAL_RCCEx_PeriphCLKConfig+0x910>)
 8009df4:	430b      	orrs	r3, r1
 8009df6:	6713      	str	r3, [r2, #112]	@ 0x70
 8009df8:	e00e      	b.n	8009e18 <HAL_RCCEx_PeriphCLKConfig+0x924>
      }
      else
      {
        /* set overall return value */
        status = ret;
 8009dfa:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009dfe:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
 8009e02:	e009      	b.n	8009e18 <HAL_RCCEx_PeriphCLKConfig+0x924>
 8009e04:	58024400 	.word	0x58024400
 8009e08:	58024800 	.word	0x58024800
 8009e0c:	00ffffcf 	.word	0x00ffffcf
      }
    }
    else
    {
      /* set overall return value */
      status = ret;
 8009e10:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009e14:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }


  /*-------------------------- USART1/6 configuration --------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
 8009e18:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009e1c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8009e20:	f002 0301 	and.w	r3, r2, #1
 8009e24:	f8c7 30b8 	str.w	r3, [r7, #184]	@ 0xb8
 8009e28:	2300      	movs	r3, #0
 8009e2a:	f8c7 30bc 	str.w	r3, [r7, #188]	@ 0xbc
 8009e2e:	e9d7 122e 	ldrd	r1, r2, [r7, #184]	@ 0xb8
 8009e32:	460b      	mov	r3, r1
 8009e34:	4313      	orrs	r3, r2
 8009e36:	f000 8089 	beq.w	8009f4c <HAL_RCCEx_PeriphCLKConfig+0xa58>
  {
    switch (PeriphClkInit->Usart16ClockSelection)
 8009e3a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009e3e:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 8009e40:	2b28      	cmp	r3, #40	@ 0x28
 8009e42:	d86b      	bhi.n	8009f1c <HAL_RCCEx_PeriphCLKConfig+0xa28>
 8009e44:	a201      	add	r2, pc, #4	@ (adr r2, 8009e4c <HAL_RCCEx_PeriphCLKConfig+0x958>)
 8009e46:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8009e4a:	bf00      	nop
 8009e4c:	08009f25 	.word	0x08009f25
 8009e50:	08009f1d 	.word	0x08009f1d
 8009e54:	08009f1d 	.word	0x08009f1d
 8009e58:	08009f1d 	.word	0x08009f1d
 8009e5c:	08009f1d 	.word	0x08009f1d
 8009e60:	08009f1d 	.word	0x08009f1d
 8009e64:	08009f1d 	.word	0x08009f1d
 8009e68:	08009f1d 	.word	0x08009f1d
 8009e6c:	08009ef1 	.word	0x08009ef1
 8009e70:	08009f1d 	.word	0x08009f1d
 8009e74:	08009f1d 	.word	0x08009f1d
 8009e78:	08009f1d 	.word	0x08009f1d
 8009e7c:	08009f1d 	.word	0x08009f1d
 8009e80:	08009f1d 	.word	0x08009f1d
 8009e84:	08009f1d 	.word	0x08009f1d
 8009e88:	08009f1d 	.word	0x08009f1d
 8009e8c:	08009f07 	.word	0x08009f07
 8009e90:	08009f1d 	.word	0x08009f1d
 8009e94:	08009f1d 	.word	0x08009f1d
 8009e98:	08009f1d 	.word	0x08009f1d
 8009e9c:	08009f1d 	.word	0x08009f1d
 8009ea0:	08009f1d 	.word	0x08009f1d
 8009ea4:	08009f1d 	.word	0x08009f1d
 8009ea8:	08009f1d 	.word	0x08009f1d
 8009eac:	08009f25 	.word	0x08009f25
 8009eb0:	08009f1d 	.word	0x08009f1d
 8009eb4:	08009f1d 	.word	0x08009f1d
 8009eb8:	08009f1d 	.word	0x08009f1d
 8009ebc:	08009f1d 	.word	0x08009f1d
 8009ec0:	08009f1d 	.word	0x08009f1d
 8009ec4:	08009f1d 	.word	0x08009f1d
 8009ec8:	08009f1d 	.word	0x08009f1d
 8009ecc:	08009f25 	.word	0x08009f25
 8009ed0:	08009f1d 	.word	0x08009f1d
 8009ed4:	08009f1d 	.word	0x08009f1d
 8009ed8:	08009f1d 	.word	0x08009f1d
 8009edc:	08009f1d 	.word	0x08009f1d
 8009ee0:	08009f1d 	.word	0x08009f1d
 8009ee4:	08009f1d 	.word	0x08009f1d
 8009ee8:	08009f1d 	.word	0x08009f1d
 8009eec:	08009f25 	.word	0x08009f25
      case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
        /* USART1/6 clock source configuration done later after clock selection check */
        break;

      case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 8009ef0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009ef4:	3308      	adds	r3, #8
 8009ef6:	2101      	movs	r1, #1
 8009ef8:	4618      	mov	r0, r3
 8009efa:	f001 fe79 	bl	800bbf0 <RCCEx_PLL2_Config>
 8009efe:	4603      	mov	r3, r0
 8009f00:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* USART1/6 clock source configuration done later after clock selection check */
        break;
 8009f04:	e00f      	b.n	8009f26 <HAL_RCCEx_PeriphCLKConfig+0xa32>

      case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 8009f06:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009f0a:	3328      	adds	r3, #40	@ 0x28
 8009f0c:	2101      	movs	r1, #1
 8009f0e:	4618      	mov	r0, r3
 8009f10:	f001 ff20 	bl	800bd54 <RCCEx_PLL3_Config>
 8009f14:	4603      	mov	r3, r0
 8009f16:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* USART1/6 clock source configuration done later after clock selection check */
        break;
 8009f1a:	e004      	b.n	8009f26 <HAL_RCCEx_PeriphCLKConfig+0xa32>
        /* LSE,  oscillator is used as source of USART1/6 clock */
        /* USART1/6 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 8009f1c:	2301      	movs	r3, #1
 8009f1e:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 8009f22:	e000      	b.n	8009f26 <HAL_RCCEx_PeriphCLKConfig+0xa32>
        break;
 8009f24:	bf00      	nop
    }

    if (ret == HAL_OK)
 8009f26:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009f2a:	2b00      	cmp	r3, #0
 8009f2c:	d10a      	bne.n	8009f44 <HAL_RCCEx_PeriphCLKConfig+0xa50>
    {
      /* Set the source of USART1/6 clock */
      __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
 8009f2e:	4bbf      	ldr	r3, [pc, #764]	@ (800a22c <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 8009f30:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8009f32:	f023 0138 	bic.w	r1, r3, #56	@ 0x38
 8009f36:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009f3a:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 8009f3c:	4abb      	ldr	r2, [pc, #748]	@ (800a22c <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 8009f3e:	430b      	orrs	r3, r1
 8009f40:	6553      	str	r3, [r2, #84]	@ 0x54
 8009f42:	e003      	b.n	8009f4c <HAL_RCCEx_PeriphCLKConfig+0xa58>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8009f44:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009f48:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
 8009f4c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009f50:	e9d3 2300 	ldrd	r2, r3, [r3]
 8009f54:	f002 0302 	and.w	r3, r2, #2
 8009f58:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
 8009f5c:	2300      	movs	r3, #0
 8009f5e:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
 8009f62:	e9d7 122c 	ldrd	r1, r2, [r7, #176]	@ 0xb0
 8009f66:	460b      	mov	r3, r1
 8009f68:	4313      	orrs	r3, r2
 8009f6a:	d041      	beq.n	8009ff0 <HAL_RCCEx_PeriphCLKConfig+0xafc>
  {
    switch (PeriphClkInit->Usart234578ClockSelection)
 8009f6c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009f70:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 8009f72:	2b05      	cmp	r3, #5
 8009f74:	d824      	bhi.n	8009fc0 <HAL_RCCEx_PeriphCLKConfig+0xacc>
 8009f76:	a201      	add	r2, pc, #4	@ (adr r2, 8009f7c <HAL_RCCEx_PeriphCLKConfig+0xa88>)
 8009f78:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8009f7c:	08009fc9 	.word	0x08009fc9
 8009f80:	08009f95 	.word	0x08009f95
 8009f84:	08009fab 	.word	0x08009fab
 8009f88:	08009fc9 	.word	0x08009fc9
 8009f8c:	08009fc9 	.word	0x08009fc9
 8009f90:	08009fc9 	.word	0x08009fc9
      case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
        break;

      case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 8009f94:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009f98:	3308      	adds	r3, #8
 8009f9a:	2101      	movs	r1, #1
 8009f9c:	4618      	mov	r0, r3
 8009f9e:	f001 fe27 	bl	800bbf0 <RCCEx_PLL2_Config>
 8009fa2:	4603      	mov	r3, r0
 8009fa4:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
        break;
 8009fa8:	e00f      	b.n	8009fca <HAL_RCCEx_PeriphCLKConfig+0xad6>

      case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 8009faa:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009fae:	3328      	adds	r3, #40	@ 0x28
 8009fb0:	2101      	movs	r1, #1
 8009fb2:	4618      	mov	r0, r3
 8009fb4:	f001 fece 	bl	800bd54 <RCCEx_PLL3_Config>
 8009fb8:	4603      	mov	r3, r0
 8009fba:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
        break;
 8009fbe:	e004      	b.n	8009fca <HAL_RCCEx_PeriphCLKConfig+0xad6>
        /* LSE,  oscillator is used as source of USART2/3/4/5/7/8 clock */
        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 8009fc0:	2301      	movs	r3, #1
 8009fc2:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 8009fc6:	e000      	b.n	8009fca <HAL_RCCEx_PeriphCLKConfig+0xad6>
        break;
 8009fc8:	bf00      	nop
    }

    if (ret == HAL_OK)
 8009fca:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009fce:	2b00      	cmp	r3, #0
 8009fd0:	d10a      	bne.n	8009fe8 <HAL_RCCEx_PeriphCLKConfig+0xaf4>
    {
      /* Set the source of USART2/3/4/5/7/8 clock */
      __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
 8009fd2:	4b96      	ldr	r3, [pc, #600]	@ (800a22c <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 8009fd4:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8009fd6:	f023 0107 	bic.w	r1, r3, #7
 8009fda:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009fde:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 8009fe0:	4a92      	ldr	r2, [pc, #584]	@ (800a22c <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 8009fe2:	430b      	orrs	r3, r1
 8009fe4:	6553      	str	r3, [r2, #84]	@ 0x54
 8009fe6:	e003      	b.n	8009ff0 <HAL_RCCEx_PeriphCLKConfig+0xafc>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8009fe8:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 8009fec:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*-------------------------- LPUART1 Configuration -------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
 8009ff0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 8009ff4:	e9d3 2300 	ldrd	r2, r3, [r3]
 8009ff8:	f002 0304 	and.w	r3, r2, #4
 8009ffc:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
 800a000:	2300      	movs	r3, #0
 800a002:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
 800a006:	e9d7 122a 	ldrd	r1, r2, [r7, #168]	@ 0xa8
 800a00a:	460b      	mov	r3, r1
 800a00c:	4313      	orrs	r3, r2
 800a00e:	d044      	beq.n	800a09a <HAL_RCCEx_PeriphCLKConfig+0xba6>
  {
    switch (PeriphClkInit->Lpuart1ClockSelection)
 800a010:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a014:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 800a018:	2b05      	cmp	r3, #5
 800a01a:	d825      	bhi.n	800a068 <HAL_RCCEx_PeriphCLKConfig+0xb74>
 800a01c:	a201      	add	r2, pc, #4	@ (adr r2, 800a024 <HAL_RCCEx_PeriphCLKConfig+0xb30>)
 800a01e:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800a022:	bf00      	nop
 800a024:	0800a071 	.word	0x0800a071
 800a028:	0800a03d 	.word	0x0800a03d
 800a02c:	0800a053 	.word	0x0800a053
 800a030:	0800a071 	.word	0x0800a071
 800a034:	0800a071 	.word	0x0800a071
 800a038:	0800a071 	.word	0x0800a071
      case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
        /* LPUART1 clock source configuration done later after clock selection check */
        break;

      case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 800a03c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a040:	3308      	adds	r3, #8
 800a042:	2101      	movs	r1, #1
 800a044:	4618      	mov	r0, r3
 800a046:	f001 fdd3 	bl	800bbf0 <RCCEx_PLL2_Config>
 800a04a:	4603      	mov	r3, r0
 800a04c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* LPUART1 clock source configuration done later after clock selection check */
        break;
 800a050:	e00f      	b.n	800a072 <HAL_RCCEx_PeriphCLKConfig+0xb7e>

      case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 800a052:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a056:	3328      	adds	r3, #40	@ 0x28
 800a058:	2101      	movs	r1, #1
 800a05a:	4618      	mov	r0, r3
 800a05c:	f001 fe7a 	bl	800bd54 <RCCEx_PLL3_Config>
 800a060:	4603      	mov	r3, r0
 800a062:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* LPUART1 clock source configuration done later after clock selection check */
        break;
 800a066:	e004      	b.n	800a072 <HAL_RCCEx_PeriphCLKConfig+0xb7e>
        /* LSE,  oscillator is used as source of LPUART1 clock */
        /* LPUART1 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800a068:	2301      	movs	r3, #1
 800a06a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800a06e:	e000      	b.n	800a072 <HAL_RCCEx_PeriphCLKConfig+0xb7e>
        break;
 800a070:	bf00      	nop
    }

    if (ret == HAL_OK)
 800a072:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a076:	2b00      	cmp	r3, #0
 800a078:	d10b      	bne.n	800a092 <HAL_RCCEx_PeriphCLKConfig+0xb9e>
    {
      /* Set the source of LPUART1 clock */
      __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
 800a07a:	4b6c      	ldr	r3, [pc, #432]	@ (800a22c <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800a07c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800a07e:	f023 0107 	bic.w	r1, r3, #7
 800a082:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a086:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 800a08a:	4a68      	ldr	r2, [pc, #416]	@ (800a22c <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800a08c:	430b      	orrs	r3, r1
 800a08e:	6593      	str	r3, [r2, #88]	@ 0x58
 800a090:	e003      	b.n	800a09a <HAL_RCCEx_PeriphCLKConfig+0xba6>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a092:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a096:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- LPTIM1 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
 800a09a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a09e:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a0a2:	f002 0320 	and.w	r3, r2, #32
 800a0a6:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
 800a0aa:	2300      	movs	r3, #0
 800a0ac:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
 800a0b0:	e9d7 1228 	ldrd	r1, r2, [r7, #160]	@ 0xa0
 800a0b4:	460b      	mov	r3, r1
 800a0b6:	4313      	orrs	r3, r2
 800a0b8:	d055      	beq.n	800a166 <HAL_RCCEx_PeriphCLKConfig+0xc72>
  {
    switch (PeriphClkInit->Lptim1ClockSelection)
 800a0ba:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a0be:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800a0c2:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 800a0c6:	d033      	beq.n	800a130 <HAL_RCCEx_PeriphCLKConfig+0xc3c>
 800a0c8:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 800a0cc:	d82c      	bhi.n	800a128 <HAL_RCCEx_PeriphCLKConfig+0xc34>
 800a0ce:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800a0d2:	d02f      	beq.n	800a134 <HAL_RCCEx_PeriphCLKConfig+0xc40>
 800a0d4:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800a0d8:	d826      	bhi.n	800a128 <HAL_RCCEx_PeriphCLKConfig+0xc34>
 800a0da:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
 800a0de:	d02b      	beq.n	800a138 <HAL_RCCEx_PeriphCLKConfig+0xc44>
 800a0e0:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
 800a0e4:	d820      	bhi.n	800a128 <HAL_RCCEx_PeriphCLKConfig+0xc34>
 800a0e6:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800a0ea:	d012      	beq.n	800a112 <HAL_RCCEx_PeriphCLKConfig+0xc1e>
 800a0ec:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800a0f0:	d81a      	bhi.n	800a128 <HAL_RCCEx_PeriphCLKConfig+0xc34>
 800a0f2:	2b00      	cmp	r3, #0
 800a0f4:	d022      	beq.n	800a13c <HAL_RCCEx_PeriphCLKConfig+0xc48>
 800a0f6:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800a0fa:	d115      	bne.n	800a128 <HAL_RCCEx_PeriphCLKConfig+0xc34>
        /* LPTIM1 clock source configuration done later after clock selection check */
        break;

      case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800a0fc:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a100:	3308      	adds	r3, #8
 800a102:	2100      	movs	r1, #0
 800a104:	4618      	mov	r0, r3
 800a106:	f001 fd73 	bl	800bbf0 <RCCEx_PLL2_Config>
 800a10a:	4603      	mov	r3, r0
 800a10c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* LPTIM1 clock source configuration done later after clock selection check */
        break;
 800a110:	e015      	b.n	800a13e <HAL_RCCEx_PeriphCLKConfig+0xc4a>

      case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 800a112:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a116:	3328      	adds	r3, #40	@ 0x28
 800a118:	2102      	movs	r1, #2
 800a11a:	4618      	mov	r0, r3
 800a11c:	f001 fe1a 	bl	800bd54 <RCCEx_PLL3_Config>
 800a120:	4603      	mov	r3, r0
 800a122:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* LPTIM1 clock source configuration done later after clock selection check */
        break;
 800a126:	e00a      	b.n	800a13e <HAL_RCCEx_PeriphCLKConfig+0xc4a>
        /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
        /* LPTIM1 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800a128:	2301      	movs	r3, #1
 800a12a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800a12e:	e006      	b.n	800a13e <HAL_RCCEx_PeriphCLKConfig+0xc4a>
        break;
 800a130:	bf00      	nop
 800a132:	e004      	b.n	800a13e <HAL_RCCEx_PeriphCLKConfig+0xc4a>
        break;
 800a134:	bf00      	nop
 800a136:	e002      	b.n	800a13e <HAL_RCCEx_PeriphCLKConfig+0xc4a>
        break;
 800a138:	bf00      	nop
 800a13a:	e000      	b.n	800a13e <HAL_RCCEx_PeriphCLKConfig+0xc4a>
        break;
 800a13c:	bf00      	nop
    }

    if (ret == HAL_OK)
 800a13e:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a142:	2b00      	cmp	r3, #0
 800a144:	d10b      	bne.n	800a15e <HAL_RCCEx_PeriphCLKConfig+0xc6a>
    {
      /* Set the source of LPTIM1 clock*/
      __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
 800a146:	4b39      	ldr	r3, [pc, #228]	@ (800a22c <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800a148:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800a14a:	f023 41e0 	bic.w	r1, r3, #1879048192	@ 0x70000000
 800a14e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a152:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800a156:	4a35      	ldr	r2, [pc, #212]	@ (800a22c <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800a158:	430b      	orrs	r3, r1
 800a15a:	6553      	str	r3, [r2, #84]	@ 0x54
 800a15c:	e003      	b.n	800a166 <HAL_RCCEx_PeriphCLKConfig+0xc72>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a15e:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a162:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- LPTIM2 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
 800a166:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a16a:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a16e:	f002 0340 	and.w	r3, r2, #64	@ 0x40
 800a172:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
 800a176:	2300      	movs	r3, #0
 800a178:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
 800a17c:	e9d7 1226 	ldrd	r1, r2, [r7, #152]	@ 0x98
 800a180:	460b      	mov	r3, r1
 800a182:	4313      	orrs	r3, r2
 800a184:	d058      	beq.n	800a238 <HAL_RCCEx_PeriphCLKConfig+0xd44>
  {
    switch (PeriphClkInit->Lptim2ClockSelection)
 800a186:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a18a:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
 800a18e:	f5b3 5fa0 	cmp.w	r3, #5120	@ 0x1400
 800a192:	d033      	beq.n	800a1fc <HAL_RCCEx_PeriphCLKConfig+0xd08>
 800a194:	f5b3 5fa0 	cmp.w	r3, #5120	@ 0x1400
 800a198:	d82c      	bhi.n	800a1f4 <HAL_RCCEx_PeriphCLKConfig+0xd00>
 800a19a:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800a19e:	d02f      	beq.n	800a200 <HAL_RCCEx_PeriphCLKConfig+0xd0c>
 800a1a0:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800a1a4:	d826      	bhi.n	800a1f4 <HAL_RCCEx_PeriphCLKConfig+0xd00>
 800a1a6:	f5b3 6f40 	cmp.w	r3, #3072	@ 0xc00
 800a1aa:	d02b      	beq.n	800a204 <HAL_RCCEx_PeriphCLKConfig+0xd10>
 800a1ac:	f5b3 6f40 	cmp.w	r3, #3072	@ 0xc00
 800a1b0:	d820      	bhi.n	800a1f4 <HAL_RCCEx_PeriphCLKConfig+0xd00>
 800a1b2:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 800a1b6:	d012      	beq.n	800a1de <HAL_RCCEx_PeriphCLKConfig+0xcea>
 800a1b8:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 800a1bc:	d81a      	bhi.n	800a1f4 <HAL_RCCEx_PeriphCLKConfig+0xd00>
 800a1be:	2b00      	cmp	r3, #0
 800a1c0:	d022      	beq.n	800a208 <HAL_RCCEx_PeriphCLKConfig+0xd14>
 800a1c2:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 800a1c6:	d115      	bne.n	800a1f4 <HAL_RCCEx_PeriphCLKConfig+0xd00>
        /* LPTIM2 clock source configuration done later after clock selection check */
        break;

      case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800a1c8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a1cc:	3308      	adds	r3, #8
 800a1ce:	2100      	movs	r1, #0
 800a1d0:	4618      	mov	r0, r3
 800a1d2:	f001 fd0d 	bl	800bbf0 <RCCEx_PLL2_Config>
 800a1d6:	4603      	mov	r3, r0
 800a1d8:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* LPTIM2 clock source configuration done later after clock selection check */
        break;
 800a1dc:	e015      	b.n	800a20a <HAL_RCCEx_PeriphCLKConfig+0xd16>

      case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 800a1de:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a1e2:	3328      	adds	r3, #40	@ 0x28
 800a1e4:	2102      	movs	r1, #2
 800a1e6:	4618      	mov	r0, r3
 800a1e8:	f001 fdb4 	bl	800bd54 <RCCEx_PLL3_Config>
 800a1ec:	4603      	mov	r3, r0
 800a1ee:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* LPTIM2 clock source configuration done later after clock selection check */
        break;
 800a1f2:	e00a      	b.n	800a20a <HAL_RCCEx_PeriphCLKConfig+0xd16>
        /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
        /* LPTIM2 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800a1f4:	2301      	movs	r3, #1
 800a1f6:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800a1fa:	e006      	b.n	800a20a <HAL_RCCEx_PeriphCLKConfig+0xd16>
        break;
 800a1fc:	bf00      	nop
 800a1fe:	e004      	b.n	800a20a <HAL_RCCEx_PeriphCLKConfig+0xd16>
        break;
 800a200:	bf00      	nop
 800a202:	e002      	b.n	800a20a <HAL_RCCEx_PeriphCLKConfig+0xd16>
        break;
 800a204:	bf00      	nop
 800a206:	e000      	b.n	800a20a <HAL_RCCEx_PeriphCLKConfig+0xd16>
        break;
 800a208:	bf00      	nop
    }

    if (ret == HAL_OK)
 800a20a:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a20e:	2b00      	cmp	r3, #0
 800a210:	d10e      	bne.n	800a230 <HAL_RCCEx_PeriphCLKConfig+0xd3c>
    {
      /* Set the source of LPTIM2 clock*/
      __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
 800a212:	4b06      	ldr	r3, [pc, #24]	@ (800a22c <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800a214:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800a216:	f423 51e0 	bic.w	r1, r3, #7168	@ 0x1c00
 800a21a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a21e:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
 800a222:	4a02      	ldr	r2, [pc, #8]	@ (800a22c <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800a224:	430b      	orrs	r3, r1
 800a226:	6593      	str	r3, [r2, #88]	@ 0x58
 800a228:	e006      	b.n	800a238 <HAL_RCCEx_PeriphCLKConfig+0xd44>
 800a22a:	bf00      	nop
 800a22c:	58024400 	.word	0x58024400
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a230:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a234:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- LPTIM345 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
 800a238:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a23c:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a240:	f002 0380 	and.w	r3, r2, #128	@ 0x80
 800a244:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
 800a248:	2300      	movs	r3, #0
 800a24a:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
 800a24e:	e9d7 1224 	ldrd	r1, r2, [r7, #144]	@ 0x90
 800a252:	460b      	mov	r3, r1
 800a254:	4313      	orrs	r3, r2
 800a256:	d055      	beq.n	800a304 <HAL_RCCEx_PeriphCLKConfig+0xe10>
  {
    switch (PeriphClkInit->Lptim345ClockSelection)
 800a258:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a25c:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 800a260:	f5b3 4f20 	cmp.w	r3, #40960	@ 0xa000
 800a264:	d033      	beq.n	800a2ce <HAL_RCCEx_PeriphCLKConfig+0xdda>
 800a266:	f5b3 4f20 	cmp.w	r3, #40960	@ 0xa000
 800a26a:	d82c      	bhi.n	800a2c6 <HAL_RCCEx_PeriphCLKConfig+0xdd2>
 800a26c:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
 800a270:	d02f      	beq.n	800a2d2 <HAL_RCCEx_PeriphCLKConfig+0xdde>
 800a272:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
 800a276:	d826      	bhi.n	800a2c6 <HAL_RCCEx_PeriphCLKConfig+0xdd2>
 800a278:	f5b3 4fc0 	cmp.w	r3, #24576	@ 0x6000
 800a27c:	d02b      	beq.n	800a2d6 <HAL_RCCEx_PeriphCLKConfig+0xde2>
 800a27e:	f5b3 4fc0 	cmp.w	r3, #24576	@ 0x6000
 800a282:	d820      	bhi.n	800a2c6 <HAL_RCCEx_PeriphCLKConfig+0xdd2>
 800a284:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 800a288:	d012      	beq.n	800a2b0 <HAL_RCCEx_PeriphCLKConfig+0xdbc>
 800a28a:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 800a28e:	d81a      	bhi.n	800a2c6 <HAL_RCCEx_PeriphCLKConfig+0xdd2>
 800a290:	2b00      	cmp	r3, #0
 800a292:	d022      	beq.n	800a2da <HAL_RCCEx_PeriphCLKConfig+0xde6>
 800a294:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800a298:	d115      	bne.n	800a2c6 <HAL_RCCEx_PeriphCLKConfig+0xdd2>
      case RCC_LPTIM345CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
        break;

      case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800a29a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a29e:	3308      	adds	r3, #8
 800a2a0:	2100      	movs	r1, #0
 800a2a2:	4618      	mov	r0, r3
 800a2a4:	f001 fca4 	bl	800bbf0 <RCCEx_PLL2_Config>
 800a2a8:	4603      	mov	r3, r0
 800a2aa:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
        break;
 800a2ae:	e015      	b.n	800a2dc <HAL_RCCEx_PeriphCLKConfig+0xde8>

      case RCC_LPTIM345CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3/4/5 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 800a2b0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a2b4:	3328      	adds	r3, #40	@ 0x28
 800a2b6:	2102      	movs	r1, #2
 800a2b8:	4618      	mov	r0, r3
 800a2ba:	f001 fd4b 	bl	800bd54 <RCCEx_PLL3_Config>
 800a2be:	4603      	mov	r3, r0
 800a2c0:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
        break;
 800a2c4:	e00a      	b.n	800a2dc <HAL_RCCEx_PeriphCLKConfig+0xde8>
        /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800a2c6:	2301      	movs	r3, #1
 800a2c8:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800a2cc:	e006      	b.n	800a2dc <HAL_RCCEx_PeriphCLKConfig+0xde8>
        break;
 800a2ce:	bf00      	nop
 800a2d0:	e004      	b.n	800a2dc <HAL_RCCEx_PeriphCLKConfig+0xde8>
        break;
 800a2d2:	bf00      	nop
 800a2d4:	e002      	b.n	800a2dc <HAL_RCCEx_PeriphCLKConfig+0xde8>
        break;
 800a2d6:	bf00      	nop
 800a2d8:	e000      	b.n	800a2dc <HAL_RCCEx_PeriphCLKConfig+0xde8>
        break;
 800a2da:	bf00      	nop
    }

    if (ret == HAL_OK)
 800a2dc:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a2e0:	2b00      	cmp	r3, #0
 800a2e2:	d10b      	bne.n	800a2fc <HAL_RCCEx_PeriphCLKConfig+0xe08>
    {
      /* Set the source of LPTIM3/4/5 clock */
      __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
 800a2e4:	4bbb      	ldr	r3, [pc, #748]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a2e6:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800a2e8:	f423 4160 	bic.w	r1, r3, #57344	@ 0xe000
 800a2ec:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a2f0:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 800a2f4:	4ab7      	ldr	r2, [pc, #732]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a2f6:	430b      	orrs	r3, r1
 800a2f8:	6593      	str	r3, [r2, #88]	@ 0x58
 800a2fa:	e003      	b.n	800a304 <HAL_RCCEx_PeriphCLKConfig+0xe10>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a2fc:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a300:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e

    __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection);

  }
#else
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
 800a304:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a308:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a30c:	f002 0308 	and.w	r3, r2, #8
 800a310:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
 800a314:	2300      	movs	r3, #0
 800a316:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
 800a31a:	e9d7 1222 	ldrd	r1, r2, [r7, #136]	@ 0x88
 800a31e:	460b      	mov	r3, r1
 800a320:	4313      	orrs	r3, r2
 800a322:	d01e      	beq.n	800a362 <HAL_RCCEx_PeriphCLKConfig+0xe6e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));

    if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3)
 800a324:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a328:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 800a32c:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800a330:	d10c      	bne.n	800a34c <HAL_RCCEx_PeriphCLKConfig+0xe58>
    {
      if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
 800a332:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a336:	3328      	adds	r3, #40	@ 0x28
 800a338:	2102      	movs	r1, #2
 800a33a:	4618      	mov	r0, r3
 800a33c:	f001 fd0a 	bl	800bd54 <RCCEx_PLL3_Config>
 800a340:	4603      	mov	r3, r0
 800a342:	2b00      	cmp	r3, #0
 800a344:	d002      	beq.n	800a34c <HAL_RCCEx_PeriphCLKConfig+0xe58>
      {
        status = HAL_ERROR;
 800a346:	2301      	movs	r3, #1
 800a348:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
      }
    }

    __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
 800a34c:	4ba1      	ldr	r3, [pc, #644]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a34e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800a350:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
 800a354:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a358:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 800a35c:	4a9d      	ldr	r2, [pc, #628]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a35e:	430b      	orrs	r3, r1
 800a360:	6553      	str	r3, [r2, #84]	@ 0x54

  }
#endif /* I2C5 */

  /*------------------------------ I2C4 Configuration ------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
 800a362:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a366:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a36a:	f002 0310 	and.w	r3, r2, #16
 800a36e:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
 800a372:	2300      	movs	r3, #0
 800a374:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
 800a378:	e9d7 1220 	ldrd	r1, r2, [r7, #128]	@ 0x80
 800a37c:	460b      	mov	r3, r1
 800a37e:	4313      	orrs	r3, r2
 800a380:	d01e      	beq.n	800a3c0 <HAL_RCCEx_PeriphCLKConfig+0xecc>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));

    if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3)
 800a382:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a386:	f8d3 3098 	ldr.w	r3, [r3, #152]	@ 0x98
 800a38a:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800a38e:	d10c      	bne.n	800a3aa <HAL_RCCEx_PeriphCLKConfig+0xeb6>
    {
      if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
 800a390:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a394:	3328      	adds	r3, #40	@ 0x28
 800a396:	2102      	movs	r1, #2
 800a398:	4618      	mov	r0, r3
 800a39a:	f001 fcdb 	bl	800bd54 <RCCEx_PLL3_Config>
 800a39e:	4603      	mov	r3, r0
 800a3a0:	2b00      	cmp	r3, #0
 800a3a2:	d002      	beq.n	800a3aa <HAL_RCCEx_PeriphCLKConfig+0xeb6>
      {
        status = HAL_ERROR;
 800a3a4:	2301      	movs	r3, #1
 800a3a6:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
      }
    }

    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
 800a3aa:	4b8a      	ldr	r3, [pc, #552]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a3ac:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800a3ae:	f423 7140 	bic.w	r1, r3, #768	@ 0x300
 800a3b2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a3b6:	f8d3 3098 	ldr.w	r3, [r3, #152]	@ 0x98
 800a3ba:	4a86      	ldr	r2, [pc, #536]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a3bc:	430b      	orrs	r3, r1
 800a3be:	6593      	str	r3, [r2, #88]	@ 0x58

  }

  /*---------------------------- ADC configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 800a3c0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a3c4:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a3c8:	f402 2300 	and.w	r3, r2, #524288	@ 0x80000
 800a3cc:	67bb      	str	r3, [r7, #120]	@ 0x78
 800a3ce:	2300      	movs	r3, #0
 800a3d0:	67fb      	str	r3, [r7, #124]	@ 0x7c
 800a3d2:	e9d7 121e 	ldrd	r1, r2, [r7, #120]	@ 0x78
 800a3d6:	460b      	mov	r3, r1
 800a3d8:	4313      	orrs	r3, r2
 800a3da:	d03e      	beq.n	800a45a <HAL_RCCEx_PeriphCLKConfig+0xf66>
  {
    switch (PeriphClkInit->AdcClockSelection)
 800a3dc:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a3e0:	f8d3 30a4 	ldr.w	r3, [r3, #164]	@ 0xa4
 800a3e4:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800a3e8:	d022      	beq.n	800a430 <HAL_RCCEx_PeriphCLKConfig+0xf3c>
 800a3ea:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800a3ee:	d81b      	bhi.n	800a428 <HAL_RCCEx_PeriphCLKConfig+0xf34>
 800a3f0:	2b00      	cmp	r3, #0
 800a3f2:	d003      	beq.n	800a3fc <HAL_RCCEx_PeriphCLKConfig+0xf08>
 800a3f4:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800a3f8:	d00b      	beq.n	800a412 <HAL_RCCEx_PeriphCLKConfig+0xf1e>
 800a3fa:	e015      	b.n	800a428 <HAL_RCCEx_PeriphCLKConfig+0xf34>
    {

      case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800a3fc:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a400:	3308      	adds	r3, #8
 800a402:	2100      	movs	r1, #0
 800a404:	4618      	mov	r0, r3
 800a406:	f001 fbf3 	bl	800bbf0 <RCCEx_PLL2_Config>
 800a40a:	4603      	mov	r3, r0
 800a40c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* ADC clock source configuration done later after clock selection check */
        break;
 800a410:	e00f      	b.n	800a432 <HAL_RCCEx_PeriphCLKConfig+0xf3e>

      case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 800a412:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a416:	3328      	adds	r3, #40	@ 0x28
 800a418:	2102      	movs	r1, #2
 800a41a:	4618      	mov	r0, r3
 800a41c:	f001 fc9a 	bl	800bd54 <RCCEx_PLL3_Config>
 800a420:	4603      	mov	r3, r0
 800a422:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* ADC clock source configuration done later after clock selection check */
        break;
 800a426:	e004      	b.n	800a432 <HAL_RCCEx_PeriphCLKConfig+0xf3e>
        /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
        /* ADC clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800a428:	2301      	movs	r3, #1
 800a42a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800a42e:	e000      	b.n	800a432 <HAL_RCCEx_PeriphCLKConfig+0xf3e>
        break;
 800a430:	bf00      	nop
    }

    if (ret == HAL_OK)
 800a432:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a436:	2b00      	cmp	r3, #0
 800a438:	d10b      	bne.n	800a452 <HAL_RCCEx_PeriphCLKConfig+0xf5e>
    {
      /* Set the source of ADC clock*/
      __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 800a43a:	4b66      	ldr	r3, [pc, #408]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a43c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800a43e:	f423 3140 	bic.w	r1, r3, #196608	@ 0x30000
 800a442:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a446:	f8d3 30a4 	ldr.w	r3, [r3, #164]	@ 0xa4
 800a44a:	4a62      	ldr	r2, [pc, #392]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a44c:	430b      	orrs	r3, r1
 800a44e:	6593      	str	r3, [r2, #88]	@ 0x58
 800a450:	e003      	b.n	800a45a <HAL_RCCEx_PeriphCLKConfig+0xf66>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a452:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a456:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*------------------------------ USB Configuration -------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
 800a45a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a45e:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a462:	f402 2380 	and.w	r3, r2, #262144	@ 0x40000
 800a466:	673b      	str	r3, [r7, #112]	@ 0x70
 800a468:	2300      	movs	r3, #0
 800a46a:	677b      	str	r3, [r7, #116]	@ 0x74
 800a46c:	e9d7 121c 	ldrd	r1, r2, [r7, #112]	@ 0x70
 800a470:	460b      	mov	r3, r1
 800a472:	4313      	orrs	r3, r2
 800a474:	d03b      	beq.n	800a4ee <HAL_RCCEx_PeriphCLKConfig+0xffa>
  {

    switch (PeriphClkInit->UsbClockSelection)
 800a476:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a47a:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800a47e:	f5b3 1f40 	cmp.w	r3, #3145728	@ 0x300000
 800a482:	d01f      	beq.n	800a4c4 <HAL_RCCEx_PeriphCLKConfig+0xfd0>
 800a484:	f5b3 1f40 	cmp.w	r3, #3145728	@ 0x300000
 800a488:	d818      	bhi.n	800a4bc <HAL_RCCEx_PeriphCLKConfig+0xfc8>
 800a48a:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 800a48e:	d003      	beq.n	800a498 <HAL_RCCEx_PeriphCLKConfig+0xfa4>
 800a490:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 800a494:	d007      	beq.n	800a4a6 <HAL_RCCEx_PeriphCLKConfig+0xfb2>
 800a496:	e011      	b.n	800a4bc <HAL_RCCEx_PeriphCLKConfig+0xfc8>
    {
      case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
        /* Enable USB Clock output generated form System USB . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800a498:	4b4e      	ldr	r3, [pc, #312]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a49a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800a49c:	4a4d      	ldr	r2, [pc, #308]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a49e:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800a4a2:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* USB clock source configuration done later after clock selection check */
        break;
 800a4a4:	e00f      	b.n	800a4c6 <HAL_RCCEx_PeriphCLKConfig+0xfd2>

      case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/

        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 800a4a6:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a4aa:	3328      	adds	r3, #40	@ 0x28
 800a4ac:	2101      	movs	r1, #1
 800a4ae:	4618      	mov	r0, r3
 800a4b0:	f001 fc50 	bl	800bd54 <RCCEx_PLL3_Config>
 800a4b4:	4603      	mov	r3, r0
 800a4b6:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* USB clock source configuration done later after clock selection check */
        break;
 800a4ba:	e004      	b.n	800a4c6 <HAL_RCCEx_PeriphCLKConfig+0xfd2>
        /* HSI48 oscillator is used as source of USB clock */
        /* USB clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800a4bc:	2301      	movs	r3, #1
 800a4be:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800a4c2:	e000      	b.n	800a4c6 <HAL_RCCEx_PeriphCLKConfig+0xfd2>
        break;
 800a4c4:	bf00      	nop
    }

    if (ret == HAL_OK)
 800a4c6:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a4ca:	2b00      	cmp	r3, #0
 800a4cc:	d10b      	bne.n	800a4e6 <HAL_RCCEx_PeriphCLKConfig+0xff2>
    {
      /* Set the source of USB clock*/
      __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 800a4ce:	4b41      	ldr	r3, [pc, #260]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a4d0:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800a4d2:	f423 1140 	bic.w	r1, r3, #3145728	@ 0x300000
 800a4d6:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a4da:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800a4de:	4a3d      	ldr	r2, [pc, #244]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a4e0:	430b      	orrs	r3, r1
 800a4e2:	6553      	str	r3, [r2, #84]	@ 0x54
 800a4e4:	e003      	b.n	800a4ee <HAL_RCCEx_PeriphCLKConfig+0xffa>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a4e6:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a4ea:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }

  }

  /*------------------------------------- SDMMC Configuration ------------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
 800a4ee:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a4f2:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a4f6:	f402 3380 	and.w	r3, r2, #65536	@ 0x10000
 800a4fa:	66bb      	str	r3, [r7, #104]	@ 0x68
 800a4fc:	2300      	movs	r3, #0
 800a4fe:	66fb      	str	r3, [r7, #108]	@ 0x6c
 800a500:	e9d7 121a 	ldrd	r1, r2, [r7, #104]	@ 0x68
 800a504:	460b      	mov	r3, r1
 800a506:	4313      	orrs	r3, r2
 800a508:	d031      	beq.n	800a56e <HAL_RCCEx_PeriphCLKConfig+0x107a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));

    switch (PeriphClkInit->SdmmcClockSelection)
 800a50a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a50e:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800a510:	2b00      	cmp	r3, #0
 800a512:	d003      	beq.n	800a51c <HAL_RCCEx_PeriphCLKConfig+0x1028>
 800a514:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800a518:	d007      	beq.n	800a52a <HAL_RCCEx_PeriphCLKConfig+0x1036>
 800a51a:	e011      	b.n	800a540 <HAL_RCCEx_PeriphCLKConfig+0x104c>
    {
      case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
        /* Enable SDMMC Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800a51c:	4b2d      	ldr	r3, [pc, #180]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a51e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800a520:	4a2c      	ldr	r2, [pc, #176]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a522:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800a526:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SDMMC clock source configuration done later after clock selection check */
        break;
 800a528:	e00e      	b.n	800a548 <HAL_RCCEx_PeriphCLKConfig+0x1054>

      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 800a52a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a52e:	3308      	adds	r3, #8
 800a530:	2102      	movs	r1, #2
 800a532:	4618      	mov	r0, r3
 800a534:	f001 fb5c 	bl	800bbf0 <RCCEx_PLL2_Config>
 800a538:	4603      	mov	r3, r0
 800a53a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SDMMC clock source configuration done later after clock selection check */
        break;
 800a53e:	e003      	b.n	800a548 <HAL_RCCEx_PeriphCLKConfig+0x1054>

      default:
        ret = HAL_ERROR;
 800a540:	2301      	movs	r3, #1
 800a542:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800a546:	bf00      	nop
    }

    if (ret == HAL_OK)
 800a548:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a54c:	2b00      	cmp	r3, #0
 800a54e:	d10a      	bne.n	800a566 <HAL_RCCEx_PeriphCLKConfig+0x1072>
    {
      /* Set the source of SDMMC clock*/
      __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
 800a550:	4b20      	ldr	r3, [pc, #128]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a552:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800a554:	f423 3180 	bic.w	r1, r3, #65536	@ 0x10000
 800a558:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a55c:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800a55e:	4a1d      	ldr	r2, [pc, #116]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a560:	430b      	orrs	r3, r1
 800a562:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800a564:	e003      	b.n	800a56e <HAL_RCCEx_PeriphCLKConfig+0x107a>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a566:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a56a:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
#endif /* LTDC */

  /*------------------------------ RNG Configuration -------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
 800a56e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a572:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a576:	f402 3300 	and.w	r3, r2, #131072	@ 0x20000
 800a57a:	663b      	str	r3, [r7, #96]	@ 0x60
 800a57c:	2300      	movs	r3, #0
 800a57e:	667b      	str	r3, [r7, #100]	@ 0x64
 800a580:	e9d7 1218 	ldrd	r1, r2, [r7, #96]	@ 0x60
 800a584:	460b      	mov	r3, r1
 800a586:	4313      	orrs	r3, r2
 800a588:	d03b      	beq.n	800a602 <HAL_RCCEx_PeriphCLKConfig+0x110e>
  {

    switch (PeriphClkInit->RngClockSelection)
 800a58a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a58e:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800a592:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 800a596:	d018      	beq.n	800a5ca <HAL_RCCEx_PeriphCLKConfig+0x10d6>
 800a598:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 800a59c:	d811      	bhi.n	800a5c2 <HAL_RCCEx_PeriphCLKConfig+0x10ce>
 800a59e:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 800a5a2:	d014      	beq.n	800a5ce <HAL_RCCEx_PeriphCLKConfig+0x10da>
 800a5a4:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 800a5a8:	d80b      	bhi.n	800a5c2 <HAL_RCCEx_PeriphCLKConfig+0x10ce>
 800a5aa:	2b00      	cmp	r3, #0
 800a5ac:	d014      	beq.n	800a5d8 <HAL_RCCEx_PeriphCLKConfig+0x10e4>
 800a5ae:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800a5b2:	d106      	bne.n	800a5c2 <HAL_RCCEx_PeriphCLKConfig+0x10ce>
    {
      case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
        /* Enable RNG Clock output generated form System RNG . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800a5b4:	4b07      	ldr	r3, [pc, #28]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a5b6:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800a5b8:	4a06      	ldr	r2, [pc, #24]	@ (800a5d4 <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800a5ba:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800a5be:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* RNG clock source configuration done later after clock selection check */
        break;
 800a5c0:	e00b      	b.n	800a5da <HAL_RCCEx_PeriphCLKConfig+0x10e6>
        /* HSI48 oscillator is used as source of RNG clock */
        /* RNG clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800a5c2:	2301      	movs	r3, #1
 800a5c4:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800a5c8:	e007      	b.n	800a5da <HAL_RCCEx_PeriphCLKConfig+0x10e6>
        break;
 800a5ca:	bf00      	nop
 800a5cc:	e005      	b.n	800a5da <HAL_RCCEx_PeriphCLKConfig+0x10e6>
        break;
 800a5ce:	bf00      	nop
 800a5d0:	e003      	b.n	800a5da <HAL_RCCEx_PeriphCLKConfig+0x10e6>
 800a5d2:	bf00      	nop
 800a5d4:	58024400 	.word	0x58024400
        break;
 800a5d8:	bf00      	nop
    }

    if (ret == HAL_OK)
 800a5da:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a5de:	2b00      	cmp	r3, #0
 800a5e0:	d10b      	bne.n	800a5fa <HAL_RCCEx_PeriphCLKConfig+0x1106>
    {
      /* Set the source of RNG clock*/
      __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
 800a5e2:	4bba      	ldr	r3, [pc, #744]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a5e4:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800a5e6:	f423 7140 	bic.w	r1, r3, #768	@ 0x300
 800a5ea:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a5ee:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800a5f2:	4ab6      	ldr	r2, [pc, #728]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a5f4:	430b      	orrs	r3, r1
 800a5f6:	6553      	str	r3, [r2, #84]	@ 0x54
 800a5f8:	e003      	b.n	800a602 <HAL_RCCEx_PeriphCLKConfig+0x110e>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a5fa:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a5fe:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }

  }

  /*------------------------------ SWPMI1 Configuration ------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
 800a602:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a606:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a60a:	f402 1380 	and.w	r3, r2, #1048576	@ 0x100000
 800a60e:	65bb      	str	r3, [r7, #88]	@ 0x58
 800a610:	2300      	movs	r3, #0
 800a612:	65fb      	str	r3, [r7, #92]	@ 0x5c
 800a614:	e9d7 1216 	ldrd	r1, r2, [r7, #88]	@ 0x58
 800a618:	460b      	mov	r3, r1
 800a61a:	4313      	orrs	r3, r2
 800a61c:	d009      	beq.n	800a632 <HAL_RCCEx_PeriphCLKConfig+0x113e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));

    /* Configure the SWPMI1 interface clock source */
    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
 800a61e:	4bab      	ldr	r3, [pc, #684]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a620:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800a622:	f023 4100 	bic.w	r1, r3, #2147483648	@ 0x80000000
 800a626:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a62a:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 800a62c:	4aa7      	ldr	r2, [pc, #668]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a62e:	430b      	orrs	r3, r1
 800a630:	6513      	str	r3, [r2, #80]	@ 0x50
  }
#if defined(HRTIM1)
  /*------------------------------ HRTIM1 clock Configuration ----------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
 800a632:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a636:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a63a:	f002 5380 	and.w	r3, r2, #268435456	@ 0x10000000
 800a63e:	653b      	str	r3, [r7, #80]	@ 0x50
 800a640:	2300      	movs	r3, #0
 800a642:	657b      	str	r3, [r7, #84]	@ 0x54
 800a644:	e9d7 1214 	ldrd	r1, r2, [r7, #80]	@ 0x50
 800a648:	460b      	mov	r3, r1
 800a64a:	4313      	orrs	r3, r2
 800a64c:	d00a      	beq.n	800a664 <HAL_RCCEx_PeriphCLKConfig+0x1170>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));

    /* Configure the HRTIM1 clock source */
    __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
 800a64e:	4b9f      	ldr	r3, [pc, #636]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a650:	691b      	ldr	r3, [r3, #16]
 800a652:	f423 4180 	bic.w	r1, r3, #16384	@ 0x4000
 800a656:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a65a:	f8d3 30b8 	ldr.w	r3, [r3, #184]	@ 0xb8
 800a65e:	4a9b      	ldr	r2, [pc, #620]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a660:	430b      	orrs	r3, r1
 800a662:	6113      	str	r3, [r2, #16]
  }
#endif  /*HRTIM1*/
  /*------------------------------ DFSDM1 Configuration ------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
 800a664:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a668:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a66c:	f402 1300 	and.w	r3, r2, #2097152	@ 0x200000
 800a670:	64bb      	str	r3, [r7, #72]	@ 0x48
 800a672:	2300      	movs	r3, #0
 800a674:	64fb      	str	r3, [r7, #76]	@ 0x4c
 800a676:	e9d7 1212 	ldrd	r1, r2, [r7, #72]	@ 0x48
 800a67a:	460b      	mov	r3, r1
 800a67c:	4313      	orrs	r3, r2
 800a67e:	d009      	beq.n	800a694 <HAL_RCCEx_PeriphCLKConfig+0x11a0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));

    /* Configure the DFSDM1 interface clock source */
    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
 800a680:	4b92      	ldr	r3, [pc, #584]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a682:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800a684:	f023 7180 	bic.w	r1, r3, #16777216	@ 0x1000000
 800a688:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a68c:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800a68e:	4a8f      	ldr	r2, [pc, #572]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a690:	430b      	orrs	r3, r1
 800a692:	6513      	str	r3, [r2, #80]	@ 0x50
    __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
  }
#endif  /* DFSDM2 */

  /*------------------------------------ TIM configuration --------------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
 800a694:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a698:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a69c:	f002 4380 	and.w	r3, r2, #1073741824	@ 0x40000000
 800a6a0:	643b      	str	r3, [r7, #64]	@ 0x40
 800a6a2:	2300      	movs	r3, #0
 800a6a4:	647b      	str	r3, [r7, #68]	@ 0x44
 800a6a6:	e9d7 1210 	ldrd	r1, r2, [r7, #64]	@ 0x40
 800a6aa:	460b      	mov	r3, r1
 800a6ac:	4313      	orrs	r3, r2
 800a6ae:	d00e      	beq.n	800a6ce <HAL_RCCEx_PeriphCLKConfig+0x11da>
  {
    /* Check the parameters */
    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));

    /* Configure Timer Prescaler */
    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
 800a6b0:	4b86      	ldr	r3, [pc, #536]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a6b2:	691b      	ldr	r3, [r3, #16]
 800a6b4:	4a85      	ldr	r2, [pc, #532]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a6b6:	f423 4300 	bic.w	r3, r3, #32768	@ 0x8000
 800a6ba:	6113      	str	r3, [r2, #16]
 800a6bc:	4b83      	ldr	r3, [pc, #524]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a6be:	6919      	ldr	r1, [r3, #16]
 800a6c0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a6c4:	f8d3 30bc 	ldr.w	r3, [r3, #188]	@ 0xbc
 800a6c8:	4a80      	ldr	r2, [pc, #512]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a6ca:	430b      	orrs	r3, r1
 800a6cc:	6113      	str	r3, [r2, #16]
  }

  /*------------------------------------ CKPER configuration --------------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
 800a6ce:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a6d2:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a6d6:	f002 4300 	and.w	r3, r2, #2147483648	@ 0x80000000
 800a6da:	63bb      	str	r3, [r7, #56]	@ 0x38
 800a6dc:	2300      	movs	r3, #0
 800a6de:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800a6e0:	e9d7 120e 	ldrd	r1, r2, [r7, #56]	@ 0x38
 800a6e4:	460b      	mov	r3, r1
 800a6e6:	4313      	orrs	r3, r2
 800a6e8:	d009      	beq.n	800a6fe <HAL_RCCEx_PeriphCLKConfig+0x120a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));

    /* Configure the CKPER clock source */
    __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
 800a6ea:	4b78      	ldr	r3, [pc, #480]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a6ec:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800a6ee:	f023 5140 	bic.w	r1, r3, #805306368	@ 0x30000000
 800a6f2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a6f6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800a6f8:	4a74      	ldr	r2, [pc, #464]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a6fa:	430b      	orrs	r3, r1
 800a6fc:	64d3      	str	r3, [r2, #76]	@ 0x4c
  }

  /*------------------------------ CEC Configuration ------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
 800a6fe:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a702:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a706:	f402 0300 	and.w	r3, r2, #8388608	@ 0x800000
 800a70a:	633b      	str	r3, [r7, #48]	@ 0x30
 800a70c:	2300      	movs	r3, #0
 800a70e:	637b      	str	r3, [r7, #52]	@ 0x34
 800a710:	e9d7 120c 	ldrd	r1, r2, [r7, #48]	@ 0x30
 800a714:	460b      	mov	r3, r1
 800a716:	4313      	orrs	r3, r2
 800a718:	d00a      	beq.n	800a730 <HAL_RCCEx_PeriphCLKConfig+0x123c>
  {
    /* Check the parameters */
    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));

    /* Configure the CEC interface clock source */
    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
 800a71a:	4b6c      	ldr	r3, [pc, #432]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a71c:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800a71e:	f423 0140 	bic.w	r1, r3, #12582912	@ 0xc00000
 800a722:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a726:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 800a72a:	4a68      	ldr	r2, [pc, #416]	@ (800a8cc <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800a72c:	430b      	orrs	r3, r1
 800a72e:	6553      	str	r3, [r2, #84]	@ 0x54
  }

  /*---------------------------- PLL2 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP)
 800a730:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a734:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a738:	2100      	movs	r1, #0
 800a73a:	62b9      	str	r1, [r7, #40]	@ 0x28
 800a73c:	f003 0301 	and.w	r3, r3, #1
 800a740:	62fb      	str	r3, [r7, #44]	@ 0x2c
 800a742:	e9d7 120a 	ldrd	r1, r2, [r7, #40]	@ 0x28
 800a746:	460b      	mov	r3, r1
 800a748:	4313      	orrs	r3, r2
 800a74a:	d011      	beq.n	800a770 <HAL_RCCEx_PeriphCLKConfig+0x127c>
  {
    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800a74c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a750:	3308      	adds	r3, #8
 800a752:	2100      	movs	r1, #0
 800a754:	4618      	mov	r0, r3
 800a756:	f001 fa4b 	bl	800bbf0 <RCCEx_PLL2_Config>
 800a75a:	4603      	mov	r3, r0
 800a75c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
    
    if (ret == HAL_OK)
 800a760:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a764:	2b00      	cmp	r3, #0
 800a766:	d003      	beq.n	800a770 <HAL_RCCEx_PeriphCLKConfig+0x127c>
      /*Nothing to do*/
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a768:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a76c:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    } 
  }
  
  
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
 800a770:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a774:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a778:	2100      	movs	r1, #0
 800a77a:	6239      	str	r1, [r7, #32]
 800a77c:	f003 0302 	and.w	r3, r3, #2
 800a780:	627b      	str	r3, [r7, #36]	@ 0x24
 800a782:	e9d7 1208 	ldrd	r1, r2, [r7, #32]
 800a786:	460b      	mov	r3, r1
 800a788:	4313      	orrs	r3, r2
 800a78a:	d011      	beq.n	800a7b0 <HAL_RCCEx_PeriphCLKConfig+0x12bc>
  {
    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 800a78c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a790:	3308      	adds	r3, #8
 800a792:	2101      	movs	r1, #1
 800a794:	4618      	mov	r0, r3
 800a796:	f001 fa2b 	bl	800bbf0 <RCCEx_PLL2_Config>
 800a79a:	4603      	mov	r3, r0
 800a79c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
    
    if (ret == HAL_OK)
 800a7a0:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a7a4:	2b00      	cmp	r3, #0
 800a7a6:	d003      	beq.n	800a7b0 <HAL_RCCEx_PeriphCLKConfig+0x12bc>
      /*Nothing to do*/
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a7a8:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a7ac:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
  
  
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
 800a7b0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a7b4:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a7b8:	2100      	movs	r1, #0
 800a7ba:	61b9      	str	r1, [r7, #24]
 800a7bc:	f003 0304 	and.w	r3, r3, #4
 800a7c0:	61fb      	str	r3, [r7, #28]
 800a7c2:	e9d7 1206 	ldrd	r1, r2, [r7, #24]
 800a7c6:	460b      	mov	r3, r1
 800a7c8:	4313      	orrs	r3, r2
 800a7ca:	d011      	beq.n	800a7f0 <HAL_RCCEx_PeriphCLKConfig+0x12fc>
  {
    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 800a7cc:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a7d0:	3308      	adds	r3, #8
 800a7d2:	2102      	movs	r1, #2
 800a7d4:	4618      	mov	r0, r3
 800a7d6:	f001 fa0b 	bl	800bbf0 <RCCEx_PLL2_Config>
 800a7da:	4603      	mov	r3, r0
 800a7dc:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
    
    if (ret == HAL_OK)
 800a7e0:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a7e4:	2b00      	cmp	r3, #0
 800a7e6:	d003      	beq.n	800a7f0 <HAL_RCCEx_PeriphCLKConfig+0x12fc>
      /*Nothing to do*/
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a7e8:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a7ec:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
  

  /*---------------------------- PLL3 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
 800a7f0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a7f4:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a7f8:	2100      	movs	r1, #0
 800a7fa:	6139      	str	r1, [r7, #16]
 800a7fc:	f003 0308 	and.w	r3, r3, #8
 800a800:	617b      	str	r3, [r7, #20]
 800a802:	e9d7 1204 	ldrd	r1, r2, [r7, #16]
 800a806:	460b      	mov	r3, r1
 800a808:	4313      	orrs	r3, r2
 800a80a:	d011      	beq.n	800a830 <HAL_RCCEx_PeriphCLKConfig+0x133c>
  {
    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 800a80c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a810:	3328      	adds	r3, #40	@ 0x28
 800a812:	2100      	movs	r1, #0
 800a814:	4618      	mov	r0, r3
 800a816:	f001 fa9d 	bl	800bd54 <RCCEx_PLL3_Config>
 800a81a:	4603      	mov	r3, r0
 800a81c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
  
    if (ret == HAL_OK)
 800a820:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a824:	2b00      	cmp	r3, #0
 800a826:	d003      	beq.n	800a830 <HAL_RCCEx_PeriphCLKConfig+0x133c>
      /*Nothing to do*/
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a828:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a82c:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
  
  
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
 800a830:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a834:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a838:	2100      	movs	r1, #0
 800a83a:	60b9      	str	r1, [r7, #8]
 800a83c:	f003 0310 	and.w	r3, r3, #16
 800a840:	60fb      	str	r3, [r7, #12]
 800a842:	e9d7 1202 	ldrd	r1, r2, [r7, #8]
 800a846:	460b      	mov	r3, r1
 800a848:	4313      	orrs	r3, r2
 800a84a:	d011      	beq.n	800a870 <HAL_RCCEx_PeriphCLKConfig+0x137c>
  {
    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 800a84c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a850:	3328      	adds	r3, #40	@ 0x28
 800a852:	2101      	movs	r1, #1
 800a854:	4618      	mov	r0, r3
 800a856:	f001 fa7d 	bl	800bd54 <RCCEx_PLL3_Config>
 800a85a:	4603      	mov	r3, r0
 800a85c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
    
    if (ret == HAL_OK)
 800a860:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a864:	2b00      	cmp	r3, #0
 800a866:	d003      	beq.n	800a870 <HAL_RCCEx_PeriphCLKConfig+0x137c>
      /*Nothing to do*/
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a868:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a86c:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
  
  
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
 800a870:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a874:	e9d3 2300 	ldrd	r2, r3, [r3]
 800a878:	2100      	movs	r1, #0
 800a87a:	6039      	str	r1, [r7, #0]
 800a87c:	f003 0320 	and.w	r3, r3, #32
 800a880:	607b      	str	r3, [r7, #4]
 800a882:	e9d7 1200 	ldrd	r1, r2, [r7]
 800a886:	460b      	mov	r3, r1
 800a888:	4313      	orrs	r3, r2
 800a88a:	d011      	beq.n	800a8b0 <HAL_RCCEx_PeriphCLKConfig+0x13bc>
  {
    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 800a88c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800a890:	3328      	adds	r3, #40	@ 0x28
 800a892:	2102      	movs	r1, #2
 800a894:	4618      	mov	r0, r3
 800a896:	f001 fa5d 	bl	800bd54 <RCCEx_PLL3_Config>
 800a89a:	4603      	mov	r3, r0
 800a89c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
    
    if (ret == HAL_OK)
 800a8a0:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a8a4:	2b00      	cmp	r3, #0
 800a8a6:	d003      	beq.n	800a8b0 <HAL_RCCEx_PeriphCLKConfig+0x13bc>
      /*Nothing to do*/
    }
    else
    {
      /* set overall return value */
      status = ret;
 800a8a8:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800a8ac:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    } 
  }

  if (status == HAL_OK)
 800a8b0:	f897 311e 	ldrb.w	r3, [r7, #286]	@ 0x11e
 800a8b4:	2b00      	cmp	r3, #0
 800a8b6:	d101      	bne.n	800a8bc <HAL_RCCEx_PeriphCLKConfig+0x13c8>
  {
    return HAL_OK;
 800a8b8:	2300      	movs	r3, #0
 800a8ba:	e000      	b.n	800a8be <HAL_RCCEx_PeriphCLKConfig+0x13ca>
  }
  return HAL_ERROR;
 800a8bc:	2301      	movs	r3, #1
}
 800a8be:	4618      	mov	r0, r3
 800a8c0:	f507 7790 	add.w	r7, r7, #288	@ 0x120
 800a8c4:	46bd      	mov	sp, r7
 800a8c6:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 800a8ca:	bf00      	nop
 800a8cc:	58024400 	.word	0x58024400

0800a8d0 <HAL_RCCEx_GetPeriphCLKFreq>:
  * @retval Frequency in KHz
  *
  *  (*) : Available on some STM32H7 lines only.
  */
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
{
 800a8d0:	b580      	push	{r7, lr}
 800a8d2:	b090      	sub	sp, #64	@ 0x40
 800a8d4:	af00      	add	r7, sp, #0
 800a8d6:	e9c7 0100 	strd	r0, r1, [r7]
  /* This variable is used to store the SAI and CKP clock source */
  uint32_t saiclocksource;
  uint32_t ckpclocksource;
  uint32_t srcclk;

  if (PeriphClk == RCC_PERIPHCLK_SAI1)
 800a8da:	e9d7 2300 	ldrd	r2, r3, [r7]
 800a8de:	f5a2 7180 	sub.w	r1, r2, #256	@ 0x100
 800a8e2:	430b      	orrs	r3, r1
 800a8e4:	f040 8094 	bne.w	800aa10 <HAL_RCCEx_GetPeriphCLKFreq+0x140>
  {

    saiclocksource = __HAL_RCC_GET_SAI1_SOURCE();
 800a8e8:	4b9e      	ldr	r3, [pc, #632]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800a8ea:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800a8ec:	f003 0307 	and.w	r3, r3, #7
 800a8f0:	633b      	str	r3, [r7, #48]	@ 0x30

    switch (saiclocksource)
 800a8f2:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800a8f4:	2b04      	cmp	r3, #4
 800a8f6:	f200 8087 	bhi.w	800aa08 <HAL_RCCEx_GetPeriphCLKFreq+0x138>
 800a8fa:	a201      	add	r2, pc, #4	@ (adr r2, 800a900 <HAL_RCCEx_GetPeriphCLKFreq+0x30>)
 800a8fc:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800a900:	0800a915 	.word	0x0800a915
 800a904:	0800a93d 	.word	0x0800a93d
 800a908:	0800a965 	.word	0x0800a965
 800a90c:	0800aa01 	.word	0x0800aa01
 800a910:	0800a98d 	.word	0x0800a98d
    {
      case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800a914:	4b93      	ldr	r3, [pc, #588]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800a916:	681b      	ldr	r3, [r3, #0]
 800a918:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800a91c:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800a920:	d108      	bne.n	800a934 <HAL_RCCEx_GetPeriphCLKFreq+0x64>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800a922:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800a926:	4618      	mov	r0, r3
 800a928:	f001 f810 	bl	800b94c <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800a92c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800a92e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800a930:	f000 bd45 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800a934:	2300      	movs	r3, #0
 800a936:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800a938:	f000 bd41 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800a93c:	4b89      	ldr	r3, [pc, #548]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800a93e:	681b      	ldr	r3, [r3, #0]
 800a940:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800a944:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800a948:	d108      	bne.n	800a95c <HAL_RCCEx_GetPeriphCLKFreq+0x8c>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800a94a:	f107 0318 	add.w	r3, r7, #24
 800a94e:	4618      	mov	r0, r3
 800a950:	f000 fd54 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_P_Frequency;
 800a954:	69bb      	ldr	r3, [r7, #24]
 800a956:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800a958:	f000 bd31 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800a95c:	2300      	movs	r3, #0
 800a95e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800a960:	f000 bd2d 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800a964:	4b7f      	ldr	r3, [pc, #508]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800a966:	681b      	ldr	r3, [r3, #0]
 800a968:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800a96c:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800a970:	d108      	bne.n	800a984 <HAL_RCCEx_GetPeriphCLKFreq+0xb4>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800a972:	f107 030c 	add.w	r3, r7, #12
 800a976:	4618      	mov	r0, r3
 800a978:	f000 fe94 	bl	800b6a4 <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_P_Frequency;
 800a97c:	68fb      	ldr	r3, [r7, #12]
 800a97e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800a980:	f000 bd1d 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800a984:	2300      	movs	r3, #0
 800a986:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800a988:	f000 bd19 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
      {

        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
 800a98c:	4b75      	ldr	r3, [pc, #468]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800a98e:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800a990:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800a994:	637b      	str	r3, [r7, #52]	@ 0x34

        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
 800a996:	4b73      	ldr	r3, [pc, #460]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800a998:	681b      	ldr	r3, [r3, #0]
 800a99a:	f003 0304 	and.w	r3, r3, #4
 800a99e:	2b04      	cmp	r3, #4
 800a9a0:	d10c      	bne.n	800a9bc <HAL_RCCEx_GetPeriphCLKFreq+0xec>
 800a9a2:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800a9a4:	2b00      	cmp	r3, #0
 800a9a6:	d109      	bne.n	800a9bc <HAL_RCCEx_GetPeriphCLKFreq+0xec>
        {
          /* In Case the CKPER Source is HSI */
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800a9a8:	4b6e      	ldr	r3, [pc, #440]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800a9aa:	681b      	ldr	r3, [r3, #0]
 800a9ac:	08db      	lsrs	r3, r3, #3
 800a9ae:	f003 0303 	and.w	r3, r3, #3
 800a9b2:	4a6d      	ldr	r2, [pc, #436]	@ (800ab68 <HAL_RCCEx_GetPeriphCLKFreq+0x298>)
 800a9b4:	fa22 f303 	lsr.w	r3, r2, r3
 800a9b8:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800a9ba:	e01f      	b.n	800a9fc <HAL_RCCEx_GetPeriphCLKFreq+0x12c>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
 800a9bc:	4b69      	ldr	r3, [pc, #420]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800a9be:	681b      	ldr	r3, [r3, #0]
 800a9c0:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800a9c4:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800a9c8:	d106      	bne.n	800a9d8 <HAL_RCCEx_GetPeriphCLKFreq+0x108>
 800a9ca:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800a9cc:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800a9d0:	d102      	bne.n	800a9d8 <HAL_RCCEx_GetPeriphCLKFreq+0x108>
        {
          /* In Case the CKPER Source is CSI */
          frequency = CSI_VALUE;
 800a9d2:	4b66      	ldr	r3, [pc, #408]	@ (800ab6c <HAL_RCCEx_GetPeriphCLKFreq+0x29c>)
 800a9d4:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800a9d6:	e011      	b.n	800a9fc <HAL_RCCEx_GetPeriphCLKFreq+0x12c>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
 800a9d8:	4b62      	ldr	r3, [pc, #392]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800a9da:	681b      	ldr	r3, [r3, #0]
 800a9dc:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800a9e0:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800a9e4:	d106      	bne.n	800a9f4 <HAL_RCCEx_GetPeriphCLKFreq+0x124>
 800a9e6:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800a9e8:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800a9ec:	d102      	bne.n	800a9f4 <HAL_RCCEx_GetPeriphCLKFreq+0x124>
        {
          /* In Case the CKPER Source is HSE */
          frequency = HSE_VALUE;
 800a9ee:	4b60      	ldr	r3, [pc, #384]	@ (800ab70 <HAL_RCCEx_GetPeriphCLKFreq+0x2a0>)
 800a9f0:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800a9f2:	e003      	b.n	800a9fc <HAL_RCCEx_GetPeriphCLKFreq+0x12c>
        }

        else
        {
          /* In Case the CKPER is disabled*/
          frequency = 0;
 800a9f4:	2300      	movs	r3, #0
 800a9f6:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }

        break;
 800a9f8:	f000 bce1 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800a9fc:	f000 bcdf 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
      {
        frequency = EXTERNAL_CLOCK_VALUE;
 800aa00:	4b5c      	ldr	r3, [pc, #368]	@ (800ab74 <HAL_RCCEx_GetPeriphCLKFreq+0x2a4>)
 800aa02:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800aa04:	f000 bcdb 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      default :
      {
        frequency = 0;
 800aa08:	2300      	movs	r3, #0
 800aa0a:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800aa0c:	f000 bcd7 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }

#if defined(SAI3)
  else if (PeriphClk == RCC_PERIPHCLK_SAI23)
 800aa10:	e9d7 2300 	ldrd	r2, r3, [r7]
 800aa14:	f5a2 7100 	sub.w	r1, r2, #512	@ 0x200
 800aa18:	430b      	orrs	r3, r1
 800aa1a:	f040 80ad 	bne.w	800ab78 <HAL_RCCEx_GetPeriphCLKFreq+0x2a8>
  {

    saiclocksource = __HAL_RCC_GET_SAI23_SOURCE();
 800aa1e:	4b51      	ldr	r3, [pc, #324]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800aa20:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800aa22:	f403 73e0 	and.w	r3, r3, #448	@ 0x1c0
 800aa26:	633b      	str	r3, [r7, #48]	@ 0x30

    switch (saiclocksource)
 800aa28:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800aa2a:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800aa2e:	d056      	beq.n	800aade <HAL_RCCEx_GetPeriphCLKFreq+0x20e>
 800aa30:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800aa32:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800aa36:	f200 8090 	bhi.w	800ab5a <HAL_RCCEx_GetPeriphCLKFreq+0x28a>
 800aa3a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800aa3c:	2bc0      	cmp	r3, #192	@ 0xc0
 800aa3e:	f000 8088 	beq.w	800ab52 <HAL_RCCEx_GetPeriphCLKFreq+0x282>
 800aa42:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800aa44:	2bc0      	cmp	r3, #192	@ 0xc0
 800aa46:	f200 8088 	bhi.w	800ab5a <HAL_RCCEx_GetPeriphCLKFreq+0x28a>
 800aa4a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800aa4c:	2b80      	cmp	r3, #128	@ 0x80
 800aa4e:	d032      	beq.n	800aab6 <HAL_RCCEx_GetPeriphCLKFreq+0x1e6>
 800aa50:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800aa52:	2b80      	cmp	r3, #128	@ 0x80
 800aa54:	f200 8081 	bhi.w	800ab5a <HAL_RCCEx_GetPeriphCLKFreq+0x28a>
 800aa58:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800aa5a:	2b00      	cmp	r3, #0
 800aa5c:	d003      	beq.n	800aa66 <HAL_RCCEx_GetPeriphCLKFreq+0x196>
 800aa5e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800aa60:	2b40      	cmp	r3, #64	@ 0x40
 800aa62:	d014      	beq.n	800aa8e <HAL_RCCEx_GetPeriphCLKFreq+0x1be>
 800aa64:	e079      	b.n	800ab5a <HAL_RCCEx_GetPeriphCLKFreq+0x28a>
    {
      case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800aa66:	4b3f      	ldr	r3, [pc, #252]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800aa68:	681b      	ldr	r3, [r3, #0]
 800aa6a:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800aa6e:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800aa72:	d108      	bne.n	800aa86 <HAL_RCCEx_GetPeriphCLKFreq+0x1b6>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800aa74:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800aa78:	4618      	mov	r0, r3
 800aa7a:	f000 ff67 	bl	800b94c <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800aa7e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800aa80:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800aa82:	f000 bc9c 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800aa86:	2300      	movs	r3, #0
 800aa88:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800aa8a:	f000 bc98 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800aa8e:	4b35      	ldr	r3, [pc, #212]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800aa90:	681b      	ldr	r3, [r3, #0]
 800aa92:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800aa96:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800aa9a:	d108      	bne.n	800aaae <HAL_RCCEx_GetPeriphCLKFreq+0x1de>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800aa9c:	f107 0318 	add.w	r3, r7, #24
 800aaa0:	4618      	mov	r0, r3
 800aaa2:	f000 fcab 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_P_Frequency;
 800aaa6:	69bb      	ldr	r3, [r7, #24]
 800aaa8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800aaaa:	f000 bc88 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800aaae:	2300      	movs	r3, #0
 800aab0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800aab2:	f000 bc84 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800aab6:	4b2b      	ldr	r3, [pc, #172]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800aab8:	681b      	ldr	r3, [r3, #0]
 800aaba:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800aabe:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800aac2:	d108      	bne.n	800aad6 <HAL_RCCEx_GetPeriphCLKFreq+0x206>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800aac4:	f107 030c 	add.w	r3, r7, #12
 800aac8:	4618      	mov	r0, r3
 800aaca:	f000 fdeb 	bl	800b6a4 <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_P_Frequency;
 800aace:	68fb      	ldr	r3, [r7, #12]
 800aad0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800aad2:	f000 bc74 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800aad6:	2300      	movs	r3, #0
 800aad8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800aada:	f000 bc70 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
      {

        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
 800aade:	4b21      	ldr	r3, [pc, #132]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800aae0:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800aae2:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800aae6:	637b      	str	r3, [r7, #52]	@ 0x34

        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
 800aae8:	4b1e      	ldr	r3, [pc, #120]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800aaea:	681b      	ldr	r3, [r3, #0]
 800aaec:	f003 0304 	and.w	r3, r3, #4
 800aaf0:	2b04      	cmp	r3, #4
 800aaf2:	d10c      	bne.n	800ab0e <HAL_RCCEx_GetPeriphCLKFreq+0x23e>
 800aaf4:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800aaf6:	2b00      	cmp	r3, #0
 800aaf8:	d109      	bne.n	800ab0e <HAL_RCCEx_GetPeriphCLKFreq+0x23e>
        {
          /* In Case the CKPER Source is HSI */
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800aafa:	4b1a      	ldr	r3, [pc, #104]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800aafc:	681b      	ldr	r3, [r3, #0]
 800aafe:	08db      	lsrs	r3, r3, #3
 800ab00:	f003 0303 	and.w	r3, r3, #3
 800ab04:	4a18      	ldr	r2, [pc, #96]	@ (800ab68 <HAL_RCCEx_GetPeriphCLKFreq+0x298>)
 800ab06:	fa22 f303 	lsr.w	r3, r2, r3
 800ab0a:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800ab0c:	e01f      	b.n	800ab4e <HAL_RCCEx_GetPeriphCLKFreq+0x27e>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
 800ab0e:	4b15      	ldr	r3, [pc, #84]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800ab10:	681b      	ldr	r3, [r3, #0]
 800ab12:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800ab16:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800ab1a:	d106      	bne.n	800ab2a <HAL_RCCEx_GetPeriphCLKFreq+0x25a>
 800ab1c:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800ab1e:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800ab22:	d102      	bne.n	800ab2a <HAL_RCCEx_GetPeriphCLKFreq+0x25a>
        {
          /* In Case the CKPER Source is CSI */
          frequency = CSI_VALUE;
 800ab24:	4b11      	ldr	r3, [pc, #68]	@ (800ab6c <HAL_RCCEx_GetPeriphCLKFreq+0x29c>)
 800ab26:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800ab28:	e011      	b.n	800ab4e <HAL_RCCEx_GetPeriphCLKFreq+0x27e>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
 800ab2a:	4b0e      	ldr	r3, [pc, #56]	@ (800ab64 <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800ab2c:	681b      	ldr	r3, [r3, #0]
 800ab2e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800ab32:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800ab36:	d106      	bne.n	800ab46 <HAL_RCCEx_GetPeriphCLKFreq+0x276>
 800ab38:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800ab3a:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800ab3e:	d102      	bne.n	800ab46 <HAL_RCCEx_GetPeriphCLKFreq+0x276>
        {
          /* In Case the CKPER Source is HSE */
          frequency = HSE_VALUE;
 800ab40:	4b0b      	ldr	r3, [pc, #44]	@ (800ab70 <HAL_RCCEx_GetPeriphCLKFreq+0x2a0>)
 800ab42:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800ab44:	e003      	b.n	800ab4e <HAL_RCCEx_GetPeriphCLKFreq+0x27e>
        }

        else
        {
          /* In Case the CKPER is disabled*/
          frequency = 0;
 800ab46:	2300      	movs	r3, #0
 800ab48:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }

        break;
 800ab4a:	f000 bc38 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800ab4e:	f000 bc36 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
      {
        frequency = EXTERNAL_CLOCK_VALUE;
 800ab52:	4b08      	ldr	r3, [pc, #32]	@ (800ab74 <HAL_RCCEx_GetPeriphCLKFreq+0x2a4>)
 800ab54:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ab56:	f000 bc32 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      default :
      {
        frequency = 0;
 800ab5a:	2300      	movs	r3, #0
 800ab5c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ab5e:	f000 bc2e 	b.w	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800ab62:	bf00      	nop
 800ab64:	58024400 	.word	0x58024400
 800ab68:	03d09000 	.word	0x03d09000
 800ab6c:	003d0900 	.word	0x003d0900
 800ab70:	017d7840 	.word	0x017d7840
 800ab74:	00bb8000 	.word	0x00bb8000
    }
  }
#endif

#if defined(SAI4)
  else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
 800ab78:	e9d7 2300 	ldrd	r2, r3, [r7]
 800ab7c:	f5a2 6180 	sub.w	r1, r2, #1024	@ 0x400
 800ab80:	430b      	orrs	r3, r1
 800ab82:	f040 809c 	bne.w	800acbe <HAL_RCCEx_GetPeriphCLKFreq+0x3ee>
  {

    saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE();
 800ab86:	4b9e      	ldr	r3, [pc, #632]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ab88:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800ab8a:	f403 0360 	and.w	r3, r3, #14680064	@ 0xe00000
 800ab8e:	633b      	str	r3, [r7, #48]	@ 0x30

    switch (saiclocksource)
 800ab90:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800ab92:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 800ab96:	d054      	beq.n	800ac42 <HAL_RCCEx_GetPeriphCLKFreq+0x372>
 800ab98:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800ab9a:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 800ab9e:	f200 808b 	bhi.w	800acb8 <HAL_RCCEx_GetPeriphCLKFreq+0x3e8>
 800aba2:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800aba4:	f5b3 0fc0 	cmp.w	r3, #6291456	@ 0x600000
 800aba8:	f000 8083 	beq.w	800acb2 <HAL_RCCEx_GetPeriphCLKFreq+0x3e2>
 800abac:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800abae:	f5b3 0fc0 	cmp.w	r3, #6291456	@ 0x600000
 800abb2:	f200 8081 	bhi.w	800acb8 <HAL_RCCEx_GetPeriphCLKFreq+0x3e8>
 800abb6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800abb8:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
 800abbc:	d02f      	beq.n	800ac1e <HAL_RCCEx_GetPeriphCLKFreq+0x34e>
 800abbe:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800abc0:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
 800abc4:	d878      	bhi.n	800acb8 <HAL_RCCEx_GetPeriphCLKFreq+0x3e8>
 800abc6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800abc8:	2b00      	cmp	r3, #0
 800abca:	d004      	beq.n	800abd6 <HAL_RCCEx_GetPeriphCLKFreq+0x306>
 800abcc:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800abce:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 800abd2:	d012      	beq.n	800abfa <HAL_RCCEx_GetPeriphCLKFreq+0x32a>
 800abd4:	e070      	b.n	800acb8 <HAL_RCCEx_GetPeriphCLKFreq+0x3e8>
    {
      case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800abd6:	4b8a      	ldr	r3, [pc, #552]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800abd8:	681b      	ldr	r3, [r3, #0]
 800abda:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800abde:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800abe2:	d107      	bne.n	800abf4 <HAL_RCCEx_GetPeriphCLKFreq+0x324>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800abe4:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800abe8:	4618      	mov	r0, r3
 800abea:	f000 feaf 	bl	800b94c <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800abee:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800abf0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800abf2:	e3e4      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800abf4:	2300      	movs	r3, #0
 800abf6:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800abf8:	e3e1      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800abfa:	4b81      	ldr	r3, [pc, #516]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800abfc:	681b      	ldr	r3, [r3, #0]
 800abfe:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800ac02:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800ac06:	d107      	bne.n	800ac18 <HAL_RCCEx_GetPeriphCLKFreq+0x348>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800ac08:	f107 0318 	add.w	r3, r7, #24
 800ac0c:	4618      	mov	r0, r3
 800ac0e:	f000 fbf5 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_P_Frequency;
 800ac12:	69bb      	ldr	r3, [r7, #24]
 800ac14:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800ac16:	e3d2      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800ac18:	2300      	movs	r3, #0
 800ac1a:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ac1c:	e3cf      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800ac1e:	4b78      	ldr	r3, [pc, #480]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ac20:	681b      	ldr	r3, [r3, #0]
 800ac22:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800ac26:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800ac2a:	d107      	bne.n	800ac3c <HAL_RCCEx_GetPeriphCLKFreq+0x36c>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800ac2c:	f107 030c 	add.w	r3, r7, #12
 800ac30:	4618      	mov	r0, r3
 800ac32:	f000 fd37 	bl	800b6a4 <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_P_Frequency;
 800ac36:	68fb      	ldr	r3, [r7, #12]
 800ac38:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800ac3a:	e3c0      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800ac3c:	2300      	movs	r3, #0
 800ac3e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ac40:	e3bd      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/
      {

        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
 800ac42:	4b6f      	ldr	r3, [pc, #444]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ac44:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800ac46:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800ac4a:	637b      	str	r3, [r7, #52]	@ 0x34

        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
 800ac4c:	4b6c      	ldr	r3, [pc, #432]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ac4e:	681b      	ldr	r3, [r3, #0]
 800ac50:	f003 0304 	and.w	r3, r3, #4
 800ac54:	2b04      	cmp	r3, #4
 800ac56:	d10c      	bne.n	800ac72 <HAL_RCCEx_GetPeriphCLKFreq+0x3a2>
 800ac58:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800ac5a:	2b00      	cmp	r3, #0
 800ac5c:	d109      	bne.n	800ac72 <HAL_RCCEx_GetPeriphCLKFreq+0x3a2>
        {
          /* In Case the CKPER Source is HSI */
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800ac5e:	4b68      	ldr	r3, [pc, #416]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ac60:	681b      	ldr	r3, [r3, #0]
 800ac62:	08db      	lsrs	r3, r3, #3
 800ac64:	f003 0303 	and.w	r3, r3, #3
 800ac68:	4a66      	ldr	r2, [pc, #408]	@ (800ae04 <HAL_RCCEx_GetPeriphCLKFreq+0x534>)
 800ac6a:	fa22 f303 	lsr.w	r3, r2, r3
 800ac6e:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800ac70:	e01e      	b.n	800acb0 <HAL_RCCEx_GetPeriphCLKFreq+0x3e0>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
 800ac72:	4b63      	ldr	r3, [pc, #396]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ac74:	681b      	ldr	r3, [r3, #0]
 800ac76:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800ac7a:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800ac7e:	d106      	bne.n	800ac8e <HAL_RCCEx_GetPeriphCLKFreq+0x3be>
 800ac80:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800ac82:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800ac86:	d102      	bne.n	800ac8e <HAL_RCCEx_GetPeriphCLKFreq+0x3be>
        {
          /* In Case the CKPER Source is CSI */
          frequency = CSI_VALUE;
 800ac88:	4b5f      	ldr	r3, [pc, #380]	@ (800ae08 <HAL_RCCEx_GetPeriphCLKFreq+0x538>)
 800ac8a:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800ac8c:	e010      	b.n	800acb0 <HAL_RCCEx_GetPeriphCLKFreq+0x3e0>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
 800ac8e:	4b5c      	ldr	r3, [pc, #368]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ac90:	681b      	ldr	r3, [r3, #0]
 800ac92:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800ac96:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800ac9a:	d106      	bne.n	800acaa <HAL_RCCEx_GetPeriphCLKFreq+0x3da>
 800ac9c:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800ac9e:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800aca2:	d102      	bne.n	800acaa <HAL_RCCEx_GetPeriphCLKFreq+0x3da>
        {
          /* In Case the CKPER Source is HSE */
          frequency = HSE_VALUE;
 800aca4:	4b59      	ldr	r3, [pc, #356]	@ (800ae0c <HAL_RCCEx_GetPeriphCLKFreq+0x53c>)
 800aca6:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800aca8:	e002      	b.n	800acb0 <HAL_RCCEx_GetPeriphCLKFreq+0x3e0>
        }

        else
        {
          /* In Case the CKPER is disabled*/
          frequency = 0;
 800acaa:	2300      	movs	r3, #0
 800acac:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }

        break;
 800acae:	e386      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800acb0:	e385      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */
      {
        frequency = EXTERNAL_CLOCK_VALUE;
 800acb2:	4b57      	ldr	r3, [pc, #348]	@ (800ae10 <HAL_RCCEx_GetPeriphCLKFreq+0x540>)
 800acb4:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800acb6:	e382      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      default :
      {
        frequency = 0;
 800acb8:	2300      	movs	r3, #0
 800acba:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800acbc:	e37f      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }

  else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
 800acbe:	e9d7 2300 	ldrd	r2, r3, [r7]
 800acc2:	f5a2 6100 	sub.w	r1, r2, #2048	@ 0x800
 800acc6:	430b      	orrs	r3, r1
 800acc8:	f040 80a7 	bne.w	800ae1a <HAL_RCCEx_GetPeriphCLKFreq+0x54a>
  {

    saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE();
 800accc:	4b4c      	ldr	r3, [pc, #304]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800acce:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800acd0:	f003 63e0 	and.w	r3, r3, #117440512	@ 0x7000000
 800acd4:	633b      	str	r3, [r7, #48]	@ 0x30

    switch (saiclocksource)
 800acd6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800acd8:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 800acdc:	d055      	beq.n	800ad8a <HAL_RCCEx_GetPeriphCLKFreq+0x4ba>
 800acde:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800ace0:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 800ace4:	f200 8096 	bhi.w	800ae14 <HAL_RCCEx_GetPeriphCLKFreq+0x544>
 800ace8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800acea:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
 800acee:	f000 8084 	beq.w	800adfa <HAL_RCCEx_GetPeriphCLKFreq+0x52a>
 800acf2:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800acf4:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
 800acf8:	f200 808c 	bhi.w	800ae14 <HAL_RCCEx_GetPeriphCLKFreq+0x544>
 800acfc:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800acfe:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800ad02:	d030      	beq.n	800ad66 <HAL_RCCEx_GetPeriphCLKFreq+0x496>
 800ad04:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800ad06:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800ad0a:	f200 8083 	bhi.w	800ae14 <HAL_RCCEx_GetPeriphCLKFreq+0x544>
 800ad0e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800ad10:	2b00      	cmp	r3, #0
 800ad12:	d004      	beq.n	800ad1e <HAL_RCCEx_GetPeriphCLKFreq+0x44e>
 800ad14:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800ad16:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
 800ad1a:	d012      	beq.n	800ad42 <HAL_RCCEx_GetPeriphCLKFreq+0x472>
 800ad1c:	e07a      	b.n	800ae14 <HAL_RCCEx_GetPeriphCLKFreq+0x544>
    {
      case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800ad1e:	4b38      	ldr	r3, [pc, #224]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ad20:	681b      	ldr	r3, [r3, #0]
 800ad22:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800ad26:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800ad2a:	d107      	bne.n	800ad3c <HAL_RCCEx_GetPeriphCLKFreq+0x46c>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800ad2c:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800ad30:	4618      	mov	r0, r3
 800ad32:	f000 fe0b 	bl	800b94c <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800ad36:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800ad38:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800ad3a:	e340      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800ad3c:	2300      	movs	r3, #0
 800ad3e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ad40:	e33d      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800ad42:	4b2f      	ldr	r3, [pc, #188]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ad44:	681b      	ldr	r3, [r3, #0]
 800ad46:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800ad4a:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800ad4e:	d107      	bne.n	800ad60 <HAL_RCCEx_GetPeriphCLKFreq+0x490>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800ad50:	f107 0318 	add.w	r3, r7, #24
 800ad54:	4618      	mov	r0, r3
 800ad56:	f000 fb51 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_P_Frequency;
 800ad5a:	69bb      	ldr	r3, [r7, #24]
 800ad5c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800ad5e:	e32e      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800ad60:	2300      	movs	r3, #0
 800ad62:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ad64:	e32b      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800ad66:	4b26      	ldr	r3, [pc, #152]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ad68:	681b      	ldr	r3, [r3, #0]
 800ad6a:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800ad6e:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800ad72:	d107      	bne.n	800ad84 <HAL_RCCEx_GetPeriphCLKFreq+0x4b4>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800ad74:	f107 030c 	add.w	r3, r7, #12
 800ad78:	4618      	mov	r0, r3
 800ad7a:	f000 fc93 	bl	800b6a4 <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_P_Frequency;
 800ad7e:	68fb      	ldr	r3, [r7, #12]
 800ad80:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800ad82:	e31c      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800ad84:	2300      	movs	r3, #0
 800ad86:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ad88:	e319      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/
      {

        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
 800ad8a:	4b1d      	ldr	r3, [pc, #116]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ad8c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800ad8e:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800ad92:	637b      	str	r3, [r7, #52]	@ 0x34

        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
 800ad94:	4b1a      	ldr	r3, [pc, #104]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ad96:	681b      	ldr	r3, [r3, #0]
 800ad98:	f003 0304 	and.w	r3, r3, #4
 800ad9c:	2b04      	cmp	r3, #4
 800ad9e:	d10c      	bne.n	800adba <HAL_RCCEx_GetPeriphCLKFreq+0x4ea>
 800ada0:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800ada2:	2b00      	cmp	r3, #0
 800ada4:	d109      	bne.n	800adba <HAL_RCCEx_GetPeriphCLKFreq+0x4ea>
        {
          /* In Case the CKPER Source is HSI */
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800ada6:	4b16      	ldr	r3, [pc, #88]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800ada8:	681b      	ldr	r3, [r3, #0]
 800adaa:	08db      	lsrs	r3, r3, #3
 800adac:	f003 0303 	and.w	r3, r3, #3
 800adb0:	4a14      	ldr	r2, [pc, #80]	@ (800ae04 <HAL_RCCEx_GetPeriphCLKFreq+0x534>)
 800adb2:	fa22 f303 	lsr.w	r3, r2, r3
 800adb6:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800adb8:	e01e      	b.n	800adf8 <HAL_RCCEx_GetPeriphCLKFreq+0x528>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
 800adba:	4b11      	ldr	r3, [pc, #68]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800adbc:	681b      	ldr	r3, [r3, #0]
 800adbe:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800adc2:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800adc6:	d106      	bne.n	800add6 <HAL_RCCEx_GetPeriphCLKFreq+0x506>
 800adc8:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800adca:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800adce:	d102      	bne.n	800add6 <HAL_RCCEx_GetPeriphCLKFreq+0x506>
        {
          /* In Case the CKPER Source is CSI */
          frequency = CSI_VALUE;
 800add0:	4b0d      	ldr	r3, [pc, #52]	@ (800ae08 <HAL_RCCEx_GetPeriphCLKFreq+0x538>)
 800add2:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800add4:	e010      	b.n	800adf8 <HAL_RCCEx_GetPeriphCLKFreq+0x528>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
 800add6:	4b0a      	ldr	r3, [pc, #40]	@ (800ae00 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800add8:	681b      	ldr	r3, [r3, #0]
 800adda:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800adde:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800ade2:	d106      	bne.n	800adf2 <HAL_RCCEx_GetPeriphCLKFreq+0x522>
 800ade4:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800ade6:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800adea:	d102      	bne.n	800adf2 <HAL_RCCEx_GetPeriphCLKFreq+0x522>
        {
          /* In Case the CKPER Source is HSE */
          frequency = HSE_VALUE;
 800adec:	4b07      	ldr	r3, [pc, #28]	@ (800ae0c <HAL_RCCEx_GetPeriphCLKFreq+0x53c>)
 800adee:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800adf0:	e002      	b.n	800adf8 <HAL_RCCEx_GetPeriphCLKFreq+0x528>
        }

        else
        {
          /* In Case the CKPER is disabled*/
          frequency = 0;
 800adf2:	2300      	movs	r3, #0
 800adf4:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }

        break;
 800adf6:	e2e2      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800adf8:	e2e1      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */
      {
        frequency = EXTERNAL_CLOCK_VALUE;
 800adfa:	4b05      	ldr	r3, [pc, #20]	@ (800ae10 <HAL_RCCEx_GetPeriphCLKFreq+0x540>)
 800adfc:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800adfe:	e2de      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800ae00:	58024400 	.word	0x58024400
 800ae04:	03d09000 	.word	0x03d09000
 800ae08:	003d0900 	.word	0x003d0900
 800ae0c:	017d7840 	.word	0x017d7840
 800ae10:	00bb8000 	.word	0x00bb8000
      }

      default :
      {
        frequency = 0;
 800ae14:	2300      	movs	r3, #0
 800ae16:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ae18:	e2d1      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }
#endif /*SAI4*/
  else if (PeriphClk == RCC_PERIPHCLK_SPI123)
 800ae1a:	e9d7 2300 	ldrd	r2, r3, [r7]
 800ae1e:	f5a2 5180 	sub.w	r1, r2, #4096	@ 0x1000
 800ae22:	430b      	orrs	r3, r1
 800ae24:	f040 809c 	bne.w	800af60 <HAL_RCCEx_GetPeriphCLKFreq+0x690>
  {
    /* Get SPI1/2/3 clock source */
    srcclk = __HAL_RCC_GET_SPI123_SOURCE();
 800ae28:	4b93      	ldr	r3, [pc, #588]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800ae2a:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800ae2c:	f403 43e0 	and.w	r3, r3, #28672	@ 0x7000
 800ae30:	63bb      	str	r3, [r7, #56]	@ 0x38

    switch (srcclk)
 800ae32:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800ae34:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 800ae38:	d054      	beq.n	800aee4 <HAL_RCCEx_GetPeriphCLKFreq+0x614>
 800ae3a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800ae3c:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 800ae40:	f200 808b 	bhi.w	800af5a <HAL_RCCEx_GetPeriphCLKFreq+0x68a>
 800ae44:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800ae46:	f5b3 5f40 	cmp.w	r3, #12288	@ 0x3000
 800ae4a:	f000 8083 	beq.w	800af54 <HAL_RCCEx_GetPeriphCLKFreq+0x684>
 800ae4e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800ae50:	f5b3 5f40 	cmp.w	r3, #12288	@ 0x3000
 800ae54:	f200 8081 	bhi.w	800af5a <HAL_RCCEx_GetPeriphCLKFreq+0x68a>
 800ae58:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800ae5a:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800ae5e:	d02f      	beq.n	800aec0 <HAL_RCCEx_GetPeriphCLKFreq+0x5f0>
 800ae60:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800ae62:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800ae66:	d878      	bhi.n	800af5a <HAL_RCCEx_GetPeriphCLKFreq+0x68a>
 800ae68:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800ae6a:	2b00      	cmp	r3, #0
 800ae6c:	d004      	beq.n	800ae78 <HAL_RCCEx_GetPeriphCLKFreq+0x5a8>
 800ae6e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800ae70:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800ae74:	d012      	beq.n	800ae9c <HAL_RCCEx_GetPeriphCLKFreq+0x5cc>
 800ae76:	e070      	b.n	800af5a <HAL_RCCEx_GetPeriphCLKFreq+0x68a>
    {
      case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800ae78:	4b7f      	ldr	r3, [pc, #508]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800ae7a:	681b      	ldr	r3, [r3, #0]
 800ae7c:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800ae80:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800ae84:	d107      	bne.n	800ae96 <HAL_RCCEx_GetPeriphCLKFreq+0x5c6>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800ae86:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800ae8a:	4618      	mov	r0, r3
 800ae8c:	f000 fd5e 	bl	800b94c <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800ae90:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800ae92:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800ae94:	e293      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800ae96:	2300      	movs	r3, #0
 800ae98:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ae9a:	e290      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800ae9c:	4b76      	ldr	r3, [pc, #472]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800ae9e:	681b      	ldr	r3, [r3, #0]
 800aea0:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800aea4:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800aea8:	d107      	bne.n	800aeba <HAL_RCCEx_GetPeriphCLKFreq+0x5ea>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800aeaa:	f107 0318 	add.w	r3, r7, #24
 800aeae:	4618      	mov	r0, r3
 800aeb0:	f000 faa4 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_P_Frequency;
 800aeb4:	69bb      	ldr	r3, [r7, #24]
 800aeb6:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800aeb8:	e281      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800aeba:	2300      	movs	r3, #0
 800aebc:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800aebe:	e27e      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800aec0:	4b6d      	ldr	r3, [pc, #436]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800aec2:	681b      	ldr	r3, [r3, #0]
 800aec4:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800aec8:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800aecc:	d107      	bne.n	800aede <HAL_RCCEx_GetPeriphCLKFreq+0x60e>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800aece:	f107 030c 	add.w	r3, r7, #12
 800aed2:	4618      	mov	r0, r3
 800aed4:	f000 fbe6 	bl	800b6a4 <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_P_Frequency;
 800aed8:	68fb      	ldr	r3, [r7, #12]
 800aeda:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800aedc:	e26f      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800aede:	2300      	movs	r3, #0
 800aee0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800aee2:	e26c      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */
      {

        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
 800aee4:	4b64      	ldr	r3, [pc, #400]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800aee6:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800aee8:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800aeec:	637b      	str	r3, [r7, #52]	@ 0x34

        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
 800aeee:	4b62      	ldr	r3, [pc, #392]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800aef0:	681b      	ldr	r3, [r3, #0]
 800aef2:	f003 0304 	and.w	r3, r3, #4
 800aef6:	2b04      	cmp	r3, #4
 800aef8:	d10c      	bne.n	800af14 <HAL_RCCEx_GetPeriphCLKFreq+0x644>
 800aefa:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800aefc:	2b00      	cmp	r3, #0
 800aefe:	d109      	bne.n	800af14 <HAL_RCCEx_GetPeriphCLKFreq+0x644>
        {
          /* In Case the CKPER Source is HSI */
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800af00:	4b5d      	ldr	r3, [pc, #372]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800af02:	681b      	ldr	r3, [r3, #0]
 800af04:	08db      	lsrs	r3, r3, #3
 800af06:	f003 0303 	and.w	r3, r3, #3
 800af0a:	4a5c      	ldr	r2, [pc, #368]	@ (800b07c <HAL_RCCEx_GetPeriphCLKFreq+0x7ac>)
 800af0c:	fa22 f303 	lsr.w	r3, r2, r3
 800af10:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800af12:	e01e      	b.n	800af52 <HAL_RCCEx_GetPeriphCLKFreq+0x682>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
 800af14:	4b58      	ldr	r3, [pc, #352]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800af16:	681b      	ldr	r3, [r3, #0]
 800af18:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800af1c:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800af20:	d106      	bne.n	800af30 <HAL_RCCEx_GetPeriphCLKFreq+0x660>
 800af22:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800af24:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800af28:	d102      	bne.n	800af30 <HAL_RCCEx_GetPeriphCLKFreq+0x660>
        {
          /* In Case the CKPER Source is CSI */
          frequency = CSI_VALUE;
 800af2a:	4b55      	ldr	r3, [pc, #340]	@ (800b080 <HAL_RCCEx_GetPeriphCLKFreq+0x7b0>)
 800af2c:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800af2e:	e010      	b.n	800af52 <HAL_RCCEx_GetPeriphCLKFreq+0x682>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
 800af30:	4b51      	ldr	r3, [pc, #324]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800af32:	681b      	ldr	r3, [r3, #0]
 800af34:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800af38:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800af3c:	d106      	bne.n	800af4c <HAL_RCCEx_GetPeriphCLKFreq+0x67c>
 800af3e:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800af40:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800af44:	d102      	bne.n	800af4c <HAL_RCCEx_GetPeriphCLKFreq+0x67c>
        {
          /* In Case the CKPER Source is HSE */
          frequency = HSE_VALUE;
 800af46:	4b4f      	ldr	r3, [pc, #316]	@ (800b084 <HAL_RCCEx_GetPeriphCLKFreq+0x7b4>)
 800af48:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800af4a:	e002      	b.n	800af52 <HAL_RCCEx_GetPeriphCLKFreq+0x682>
        }

        else
        {
          /* In Case the CKPER is disabled*/
          frequency = 0;
 800af4c:	2300      	movs	r3, #0
 800af4e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }

        break;
 800af50:	e235      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800af52:	e234      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
      {
        frequency = EXTERNAL_CLOCK_VALUE;
 800af54:	4b4c      	ldr	r3, [pc, #304]	@ (800b088 <HAL_RCCEx_GetPeriphCLKFreq+0x7b8>)
 800af56:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800af58:	e231      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      default :
      {
        frequency = 0;
 800af5a:	2300      	movs	r3, #0
 800af5c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800af5e:	e22e      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }
  else if (PeriphClk == RCC_PERIPHCLK_SPI45)
 800af60:	e9d7 2300 	ldrd	r2, r3, [r7]
 800af64:	f5a2 5100 	sub.w	r1, r2, #8192	@ 0x2000
 800af68:	430b      	orrs	r3, r1
 800af6a:	f040 808f 	bne.w	800b08c <HAL_RCCEx_GetPeriphCLKFreq+0x7bc>
  {
    /* Get SPI45 clock source */
    srcclk = __HAL_RCC_GET_SPI45_SOURCE();
 800af6e:	4b42      	ldr	r3, [pc, #264]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800af70:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800af72:	f403 23e0 	and.w	r3, r3, #458752	@ 0x70000
 800af76:	63bb      	str	r3, [r7, #56]	@ 0x38
    switch (srcclk)
 800af78:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800af7a:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 800af7e:	d06b      	beq.n	800b058 <HAL_RCCEx_GetPeriphCLKFreq+0x788>
 800af80:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800af82:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 800af86:	d874      	bhi.n	800b072 <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
 800af88:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800af8a:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
 800af8e:	d056      	beq.n	800b03e <HAL_RCCEx_GetPeriphCLKFreq+0x76e>
 800af90:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800af92:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
 800af96:	d86c      	bhi.n	800b072 <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
 800af98:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800af9a:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
 800af9e:	d03b      	beq.n	800b018 <HAL_RCCEx_GetPeriphCLKFreq+0x748>
 800afa0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800afa2:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
 800afa6:	d864      	bhi.n	800b072 <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
 800afa8:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800afaa:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800afae:	d021      	beq.n	800aff4 <HAL_RCCEx_GetPeriphCLKFreq+0x724>
 800afb0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800afb2:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800afb6:	d85c      	bhi.n	800b072 <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
 800afb8:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800afba:	2b00      	cmp	r3, #0
 800afbc:	d004      	beq.n	800afc8 <HAL_RCCEx_GetPeriphCLKFreq+0x6f8>
 800afbe:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800afc0:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800afc4:	d004      	beq.n	800afd0 <HAL_RCCEx_GetPeriphCLKFreq+0x700>
 800afc6:	e054      	b.n	800b072 <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
    {
      case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */
      {
        frequency = HAL_RCC_GetPCLK1Freq();
 800afc8:	f7fe fa26 	bl	8009418 <HAL_RCC_GetPCLK1Freq>
 800afcc:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 800afce:	e1f6      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800afd0:	4b29      	ldr	r3, [pc, #164]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800afd2:	681b      	ldr	r3, [r3, #0]
 800afd4:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800afd8:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800afdc:	d107      	bne.n	800afee <HAL_RCCEx_GetPeriphCLKFreq+0x71e>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800afde:	f107 0318 	add.w	r3, r7, #24
 800afe2:	4618      	mov	r0, r3
 800afe4:	f000 fa0a 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_Q_Frequency;
 800afe8:	69fb      	ldr	r3, [r7, #28]
 800afea:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800afec:	e1e7      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800afee:	2300      	movs	r3, #0
 800aff0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800aff2:	e1e4      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800aff4:	4b20      	ldr	r3, [pc, #128]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800aff6:	681b      	ldr	r3, [r3, #0]
 800aff8:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800affc:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800b000:	d107      	bne.n	800b012 <HAL_RCCEx_GetPeriphCLKFreq+0x742>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800b002:	f107 030c 	add.w	r3, r7, #12
 800b006:	4618      	mov	r0, r3
 800b008:	f000 fb4c 	bl	800b6a4 <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_Q_Frequency;
 800b00c:	693b      	ldr	r3, [r7, #16]
 800b00e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b010:	e1d5      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b012:	2300      	movs	r3, #0
 800b014:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b016:	e1d2      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
 800b018:	4b17      	ldr	r3, [pc, #92]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800b01a:	681b      	ldr	r3, [r3, #0]
 800b01c:	f003 0304 	and.w	r3, r3, #4
 800b020:	2b04      	cmp	r3, #4
 800b022:	d109      	bne.n	800b038 <HAL_RCCEx_GetPeriphCLKFreq+0x768>
        {
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800b024:	4b14      	ldr	r3, [pc, #80]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800b026:	681b      	ldr	r3, [r3, #0]
 800b028:	08db      	lsrs	r3, r3, #3
 800b02a:	f003 0303 	and.w	r3, r3, #3
 800b02e:	4a13      	ldr	r2, [pc, #76]	@ (800b07c <HAL_RCCEx_GetPeriphCLKFreq+0x7ac>)
 800b030:	fa22 f303 	lsr.w	r3, r2, r3
 800b034:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b036:	e1c2      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b038:	2300      	movs	r3, #0
 800b03a:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b03c:	e1bf      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
 800b03e:	4b0e      	ldr	r3, [pc, #56]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800b040:	681b      	ldr	r3, [r3, #0]
 800b042:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800b046:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800b04a:	d102      	bne.n	800b052 <HAL_RCCEx_GetPeriphCLKFreq+0x782>
        {
          frequency = CSI_VALUE;
 800b04c:	4b0c      	ldr	r3, [pc, #48]	@ (800b080 <HAL_RCCEx_GetPeriphCLKFreq+0x7b0>)
 800b04e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b050:	e1b5      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b052:	2300      	movs	r3, #0
 800b054:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b056:	e1b2      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
 800b058:	4b07      	ldr	r3, [pc, #28]	@ (800b078 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800b05a:	681b      	ldr	r3, [r3, #0]
 800b05c:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800b060:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800b064:	d102      	bne.n	800b06c <HAL_RCCEx_GetPeriphCLKFreq+0x79c>
        {
          frequency = HSE_VALUE;
 800b066:	4b07      	ldr	r3, [pc, #28]	@ (800b084 <HAL_RCCEx_GetPeriphCLKFreq+0x7b4>)
 800b068:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b06a:	e1a8      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b06c:	2300      	movs	r3, #0
 800b06e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b070:	e1a5      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      default :
      {
        frequency = 0;
 800b072:	2300      	movs	r3, #0
 800b074:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b076:	e1a2      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800b078:	58024400 	.word	0x58024400
 800b07c:	03d09000 	.word	0x03d09000
 800b080:	003d0900 	.word	0x003d0900
 800b084:	017d7840 	.word	0x017d7840
 800b088:	00bb8000 	.word	0x00bb8000
      }
    }
  }
  else if (PeriphClk == RCC_PERIPHCLK_ADC)
 800b08c:	e9d7 2300 	ldrd	r2, r3, [r7]
 800b090:	f5a2 2100 	sub.w	r1, r2, #524288	@ 0x80000
 800b094:	430b      	orrs	r3, r1
 800b096:	d173      	bne.n	800b180 <HAL_RCCEx_GetPeriphCLKFreq+0x8b0>
  {
    /* Get ADC clock source */
    srcclk = __HAL_RCC_GET_ADC_SOURCE();
 800b098:	4b9c      	ldr	r3, [pc, #624]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b09a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800b09c:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 800b0a0:	63bb      	str	r3, [r7, #56]	@ 0x38

    switch (srcclk)
 800b0a2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b0a4:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800b0a8:	d02f      	beq.n	800b10a <HAL_RCCEx_GetPeriphCLKFreq+0x83a>
 800b0aa:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b0ac:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800b0b0:	d863      	bhi.n	800b17a <HAL_RCCEx_GetPeriphCLKFreq+0x8aa>
 800b0b2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b0b4:	2b00      	cmp	r3, #0
 800b0b6:	d004      	beq.n	800b0c2 <HAL_RCCEx_GetPeriphCLKFreq+0x7f2>
 800b0b8:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b0ba:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800b0be:	d012      	beq.n	800b0e6 <HAL_RCCEx_GetPeriphCLKFreq+0x816>
 800b0c0:	e05b      	b.n	800b17a <HAL_RCCEx_GetPeriphCLKFreq+0x8aa>
    {
      case RCC_ADCCLKSOURCE_PLL2:
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800b0c2:	4b92      	ldr	r3, [pc, #584]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b0c4:	681b      	ldr	r3, [r3, #0]
 800b0c6:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800b0ca:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800b0ce:	d107      	bne.n	800b0e0 <HAL_RCCEx_GetPeriphCLKFreq+0x810>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800b0d0:	f107 0318 	add.w	r3, r7, #24
 800b0d4:	4618      	mov	r0, r3
 800b0d6:	f000 f991 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_P_Frequency;
 800b0da:	69bb      	ldr	r3, [r7, #24]
 800b0dc:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b0de:	e16e      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b0e0:	2300      	movs	r3, #0
 800b0e2:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b0e4:	e16b      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_ADCCLKSOURCE_PLL3:
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800b0e6:	4b89      	ldr	r3, [pc, #548]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b0e8:	681b      	ldr	r3, [r3, #0]
 800b0ea:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800b0ee:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800b0f2:	d107      	bne.n	800b104 <HAL_RCCEx_GetPeriphCLKFreq+0x834>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800b0f4:	f107 030c 	add.w	r3, r7, #12
 800b0f8:	4618      	mov	r0, r3
 800b0fa:	f000 fad3 	bl	800b6a4 <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_R_Frequency;
 800b0fe:	697b      	ldr	r3, [r7, #20]
 800b100:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b102:	e15c      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b104:	2300      	movs	r3, #0
 800b106:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b108:	e159      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_ADCCLKSOURCE_CLKP:
      {

        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
 800b10a:	4b80      	ldr	r3, [pc, #512]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b10c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800b10e:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800b112:	637b      	str	r3, [r7, #52]	@ 0x34

        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
 800b114:	4b7d      	ldr	r3, [pc, #500]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b116:	681b      	ldr	r3, [r3, #0]
 800b118:	f003 0304 	and.w	r3, r3, #4
 800b11c:	2b04      	cmp	r3, #4
 800b11e:	d10c      	bne.n	800b13a <HAL_RCCEx_GetPeriphCLKFreq+0x86a>
 800b120:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800b122:	2b00      	cmp	r3, #0
 800b124:	d109      	bne.n	800b13a <HAL_RCCEx_GetPeriphCLKFreq+0x86a>
        {
          /* In Case the CKPER Source is HSI */
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800b126:	4b79      	ldr	r3, [pc, #484]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b128:	681b      	ldr	r3, [r3, #0]
 800b12a:	08db      	lsrs	r3, r3, #3
 800b12c:	f003 0303 	and.w	r3, r3, #3
 800b130:	4a77      	ldr	r2, [pc, #476]	@ (800b310 <HAL_RCCEx_GetPeriphCLKFreq+0xa40>)
 800b132:	fa22 f303 	lsr.w	r3, r2, r3
 800b136:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800b138:	e01e      	b.n	800b178 <HAL_RCCEx_GetPeriphCLKFreq+0x8a8>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
 800b13a:	4b74      	ldr	r3, [pc, #464]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b13c:	681b      	ldr	r3, [r3, #0]
 800b13e:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800b142:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800b146:	d106      	bne.n	800b156 <HAL_RCCEx_GetPeriphCLKFreq+0x886>
 800b148:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800b14a:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800b14e:	d102      	bne.n	800b156 <HAL_RCCEx_GetPeriphCLKFreq+0x886>
        {
          /* In Case the CKPER Source is CSI */
          frequency = CSI_VALUE;
 800b150:	4b70      	ldr	r3, [pc, #448]	@ (800b314 <HAL_RCCEx_GetPeriphCLKFreq+0xa44>)
 800b152:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800b154:	e010      	b.n	800b178 <HAL_RCCEx_GetPeriphCLKFreq+0x8a8>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
 800b156:	4b6d      	ldr	r3, [pc, #436]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b158:	681b      	ldr	r3, [r3, #0]
 800b15a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800b15e:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800b162:	d106      	bne.n	800b172 <HAL_RCCEx_GetPeriphCLKFreq+0x8a2>
 800b164:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800b166:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800b16a:	d102      	bne.n	800b172 <HAL_RCCEx_GetPeriphCLKFreq+0x8a2>
        {
          /* In Case the CKPER Source is HSE */
          frequency = HSE_VALUE;
 800b16c:	4b6a      	ldr	r3, [pc, #424]	@ (800b318 <HAL_RCCEx_GetPeriphCLKFreq+0xa48>)
 800b16e:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800b170:	e002      	b.n	800b178 <HAL_RCCEx_GetPeriphCLKFreq+0x8a8>
        }

        else
        {
          /* In Case the CKPER is disabled*/
          frequency = 0;
 800b172:	2300      	movs	r3, #0
 800b174:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }

        break;
 800b176:	e122      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800b178:	e121      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      default :
      {
        frequency = 0;
 800b17a:	2300      	movs	r3, #0
 800b17c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b17e:	e11e      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }
  else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
 800b180:	e9d7 2300 	ldrd	r2, r3, [r7]
 800b184:	f5a2 3180 	sub.w	r1, r2, #65536	@ 0x10000
 800b188:	430b      	orrs	r3, r1
 800b18a:	d133      	bne.n	800b1f4 <HAL_RCCEx_GetPeriphCLKFreq+0x924>
  {
    /* Get SDMMC clock source */
    srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
 800b18c:	4b5f      	ldr	r3, [pc, #380]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b18e:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800b190:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 800b194:	63bb      	str	r3, [r7, #56]	@ 0x38

    switch (srcclk)
 800b196:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b198:	2b00      	cmp	r3, #0
 800b19a:	d004      	beq.n	800b1a6 <HAL_RCCEx_GetPeriphCLKFreq+0x8d6>
 800b19c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b19e:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800b1a2:	d012      	beq.n	800b1ca <HAL_RCCEx_GetPeriphCLKFreq+0x8fa>
 800b1a4:	e023      	b.n	800b1ee <HAL_RCCEx_GetPeriphCLKFreq+0x91e>
    {
      case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800b1a6:	4b59      	ldr	r3, [pc, #356]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b1a8:	681b      	ldr	r3, [r3, #0]
 800b1aa:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800b1ae:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800b1b2:	d107      	bne.n	800b1c4 <HAL_RCCEx_GetPeriphCLKFreq+0x8f4>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800b1b4:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800b1b8:	4618      	mov	r0, r3
 800b1ba:	f000 fbc7 	bl	800b94c <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800b1be:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800b1c0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b1c2:	e0fc      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b1c4:	2300      	movs	r3, #0
 800b1c6:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b1c8:	e0f9      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800b1ca:	4b50      	ldr	r3, [pc, #320]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b1cc:	681b      	ldr	r3, [r3, #0]
 800b1ce:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800b1d2:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800b1d6:	d107      	bne.n	800b1e8 <HAL_RCCEx_GetPeriphCLKFreq+0x918>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800b1d8:	f107 0318 	add.w	r3, r7, #24
 800b1dc:	4618      	mov	r0, r3
 800b1de:	f000 f90d 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_R_Frequency;
 800b1e2:	6a3b      	ldr	r3, [r7, #32]
 800b1e4:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b1e6:	e0ea      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b1e8:	2300      	movs	r3, #0
 800b1ea:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b1ec:	e0e7      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      default :
      {
        frequency = 0;
 800b1ee:	2300      	movs	r3, #0
 800b1f0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b1f2:	e0e4      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }
  else if (PeriphClk == RCC_PERIPHCLK_SPI6)
 800b1f4:	e9d7 2300 	ldrd	r2, r3, [r7]
 800b1f8:	f5a2 4180 	sub.w	r1, r2, #16384	@ 0x4000
 800b1fc:	430b      	orrs	r3, r1
 800b1fe:	f040 808d 	bne.w	800b31c <HAL_RCCEx_GetPeriphCLKFreq+0xa4c>
  {
    /* Get SPI6 clock source */
    srcclk = __HAL_RCC_GET_SPI6_SOURCE();
 800b202:	4b42      	ldr	r3, [pc, #264]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b204:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800b206:	f003 43e0 	and.w	r3, r3, #1879048192	@ 0x70000000
 800b20a:	63bb      	str	r3, [r7, #56]	@ 0x38

    switch (srcclk)
 800b20c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b20e:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 800b212:	d06b      	beq.n	800b2ec <HAL_RCCEx_GetPeriphCLKFreq+0xa1c>
 800b214:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b216:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 800b21a:	d874      	bhi.n	800b306 <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
 800b21c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b21e:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800b222:	d056      	beq.n	800b2d2 <HAL_RCCEx_GetPeriphCLKFreq+0xa02>
 800b224:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b226:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800b22a:	d86c      	bhi.n	800b306 <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
 800b22c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b22e:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
 800b232:	d03b      	beq.n	800b2ac <HAL_RCCEx_GetPeriphCLKFreq+0x9dc>
 800b234:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b236:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
 800b23a:	d864      	bhi.n	800b306 <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
 800b23c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b23e:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800b242:	d021      	beq.n	800b288 <HAL_RCCEx_GetPeriphCLKFreq+0x9b8>
 800b244:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b246:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800b24a:	d85c      	bhi.n	800b306 <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
 800b24c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b24e:	2b00      	cmp	r3, #0
 800b250:	d004      	beq.n	800b25c <HAL_RCCEx_GetPeriphCLKFreq+0x98c>
 800b252:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b254:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800b258:	d004      	beq.n	800b264 <HAL_RCCEx_GetPeriphCLKFreq+0x994>
 800b25a:	e054      	b.n	800b306 <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
    {
      case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
      {
        frequency = HAL_RCCEx_GetD3PCLK1Freq();
 800b25c:	f000 f8b8 	bl	800b3d0 <HAL_RCCEx_GetD3PCLK1Freq>
 800b260:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 800b262:	e0ac      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800b264:	4b29      	ldr	r3, [pc, #164]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b266:	681b      	ldr	r3, [r3, #0]
 800b268:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800b26c:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800b270:	d107      	bne.n	800b282 <HAL_RCCEx_GetPeriphCLKFreq+0x9b2>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800b272:	f107 0318 	add.w	r3, r7, #24
 800b276:	4618      	mov	r0, r3
 800b278:	f000 f8c0 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_Q_Frequency;
 800b27c:	69fb      	ldr	r3, [r7, #28]
 800b27e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b280:	e09d      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b282:	2300      	movs	r3, #0
 800b284:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b286:	e09a      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800b288:	4b20      	ldr	r3, [pc, #128]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b28a:	681b      	ldr	r3, [r3, #0]
 800b28c:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800b290:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800b294:	d107      	bne.n	800b2a6 <HAL_RCCEx_GetPeriphCLKFreq+0x9d6>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800b296:	f107 030c 	add.w	r3, r7, #12
 800b29a:	4618      	mov	r0, r3
 800b29c:	f000 fa02 	bl	800b6a4 <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_Q_Frequency;
 800b2a0:	693b      	ldr	r3, [r7, #16]
 800b2a2:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b2a4:	e08b      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b2a6:	2300      	movs	r3, #0
 800b2a8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b2aa:	e088      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
 800b2ac:	4b17      	ldr	r3, [pc, #92]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b2ae:	681b      	ldr	r3, [r3, #0]
 800b2b0:	f003 0304 	and.w	r3, r3, #4
 800b2b4:	2b04      	cmp	r3, #4
 800b2b6:	d109      	bne.n	800b2cc <HAL_RCCEx_GetPeriphCLKFreq+0x9fc>
        {
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800b2b8:	4b14      	ldr	r3, [pc, #80]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b2ba:	681b      	ldr	r3, [r3, #0]
 800b2bc:	08db      	lsrs	r3, r3, #3
 800b2be:	f003 0303 	and.w	r3, r3, #3
 800b2c2:	4a13      	ldr	r2, [pc, #76]	@ (800b310 <HAL_RCCEx_GetPeriphCLKFreq+0xa40>)
 800b2c4:	fa22 f303 	lsr.w	r3, r2, r3
 800b2c8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b2ca:	e078      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b2cc:	2300      	movs	r3, #0
 800b2ce:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b2d0:	e075      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
 800b2d2:	4b0e      	ldr	r3, [pc, #56]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b2d4:	681b      	ldr	r3, [r3, #0]
 800b2d6:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800b2da:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800b2de:	d102      	bne.n	800b2e6 <HAL_RCCEx_GetPeriphCLKFreq+0xa16>
        {
          frequency = CSI_VALUE;
 800b2e0:	4b0c      	ldr	r3, [pc, #48]	@ (800b314 <HAL_RCCEx_GetPeriphCLKFreq+0xa44>)
 800b2e2:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b2e4:	e06b      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b2e6:	2300      	movs	r3, #0
 800b2e8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b2ea:	e068      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
 800b2ec:	4b07      	ldr	r3, [pc, #28]	@ (800b30c <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800b2ee:	681b      	ldr	r3, [r3, #0]
 800b2f0:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800b2f4:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800b2f8:	d102      	bne.n	800b300 <HAL_RCCEx_GetPeriphCLKFreq+0xa30>
        {
          frequency = HSE_VALUE;
 800b2fa:	4b07      	ldr	r3, [pc, #28]	@ (800b318 <HAL_RCCEx_GetPeriphCLKFreq+0xa48>)
 800b2fc:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b2fe:	e05e      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b300:	2300      	movs	r3, #0
 800b302:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b304:	e05b      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
        break;
      }
#endif /* RCC_SPI6CLKSOURCE_PIN */
      default :
      {
        frequency = 0;
 800b306:	2300      	movs	r3, #0
 800b308:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b30a:	e058      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800b30c:	58024400 	.word	0x58024400
 800b310:	03d09000 	.word	0x03d09000
 800b314:	003d0900 	.word	0x003d0900
 800b318:	017d7840 	.word	0x017d7840
      }
    }
  }
  else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
 800b31c:	e9d7 2300 	ldrd	r2, r3, [r7]
 800b320:	f5a2 4100 	sub.w	r1, r2, #32768	@ 0x8000
 800b324:	430b      	orrs	r3, r1
 800b326:	d148      	bne.n	800b3ba <HAL_RCCEx_GetPeriphCLKFreq+0xaea>
  {
    /* Get FDCAN clock source */
    srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
 800b328:	4b27      	ldr	r3, [pc, #156]	@ (800b3c8 <HAL_RCCEx_GetPeriphCLKFreq+0xaf8>)
 800b32a:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800b32c:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800b330:	63bb      	str	r3, [r7, #56]	@ 0x38

    switch (srcclk)
 800b332:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b334:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800b338:	d02a      	beq.n	800b390 <HAL_RCCEx_GetPeriphCLKFreq+0xac0>
 800b33a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b33c:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800b340:	d838      	bhi.n	800b3b4 <HAL_RCCEx_GetPeriphCLKFreq+0xae4>
 800b342:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b344:	2b00      	cmp	r3, #0
 800b346:	d004      	beq.n	800b352 <HAL_RCCEx_GetPeriphCLKFreq+0xa82>
 800b348:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800b34a:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800b34e:	d00d      	beq.n	800b36c <HAL_RCCEx_GetPeriphCLKFreq+0xa9c>
 800b350:	e030      	b.n	800b3b4 <HAL_RCCEx_GetPeriphCLKFreq+0xae4>
    {
      case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
 800b352:	4b1d      	ldr	r3, [pc, #116]	@ (800b3c8 <HAL_RCCEx_GetPeriphCLKFreq+0xaf8>)
 800b354:	681b      	ldr	r3, [r3, #0]
 800b356:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800b35a:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800b35e:	d102      	bne.n	800b366 <HAL_RCCEx_GetPeriphCLKFreq+0xa96>
        {
          frequency = HSE_VALUE;
 800b360:	4b1a      	ldr	r3, [pc, #104]	@ (800b3cc <HAL_RCCEx_GetPeriphCLKFreq+0xafc>)
 800b362:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b364:	e02b      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b366:	2300      	movs	r3, #0
 800b368:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b36a:	e028      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800b36c:	4b16      	ldr	r3, [pc, #88]	@ (800b3c8 <HAL_RCCEx_GetPeriphCLKFreq+0xaf8>)
 800b36e:	681b      	ldr	r3, [r3, #0]
 800b370:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800b374:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800b378:	d107      	bne.n	800b38a <HAL_RCCEx_GetPeriphCLKFreq+0xaba>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800b37a:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800b37e:	4618      	mov	r0, r3
 800b380:	f000 fae4 	bl	800b94c <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800b384:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800b386:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b388:	e019      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b38a:	2300      	movs	r3, #0
 800b38c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b38e:	e016      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800b390:	4b0d      	ldr	r3, [pc, #52]	@ (800b3c8 <HAL_RCCEx_GetPeriphCLKFreq+0xaf8>)
 800b392:	681b      	ldr	r3, [r3, #0]
 800b394:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800b398:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800b39c:	d107      	bne.n	800b3ae <HAL_RCCEx_GetPeriphCLKFreq+0xade>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800b39e:	f107 0318 	add.w	r3, r7, #24
 800b3a2:	4618      	mov	r0, r3
 800b3a4:	f000 f82a 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_Q_Frequency;
 800b3a8:	69fb      	ldr	r3, [r7, #28]
 800b3aa:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800b3ac:	e007      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800b3ae:	2300      	movs	r3, #0
 800b3b0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b3b2:	e004      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      default :
      {
        frequency = 0;
 800b3b4:	2300      	movs	r3, #0
 800b3b6:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800b3b8:	e001      	b.n	800b3be <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }
  else
  {
    frequency = 0;
 800b3ba:	2300      	movs	r3, #0
 800b3bc:	63fb      	str	r3, [r7, #60]	@ 0x3c
  }

  return frequency;
 800b3be:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
}
 800b3c0:	4618      	mov	r0, r3
 800b3c2:	3740      	adds	r7, #64	@ 0x40
 800b3c4:	46bd      	mov	sp, r7
 800b3c6:	bd80      	pop	{r7, pc}
 800b3c8:	58024400 	.word	0x58024400
 800b3cc:	017d7840 	.word	0x017d7840

0800b3d0 <HAL_RCCEx_GetD3PCLK1Freq>:
  * @note   Each time D3PCLK1 changes, this function must be called to update the
  *         right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval D3PCLK1 frequency
  */
uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
{
 800b3d0:	b580      	push	{r7, lr}
 800b3d2:	af00      	add	r7, sp, #0
#if defined(RCC_D3CFGR_D3PPRE)
  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
 800b3d4:	f7fd fff0 	bl	80093b8 <HAL_RCC_GetHCLKFreq>
 800b3d8:	4602      	mov	r2, r0
 800b3da:	4b06      	ldr	r3, [pc, #24]	@ (800b3f4 <HAL_RCCEx_GetD3PCLK1Freq+0x24>)
 800b3dc:	6a1b      	ldr	r3, [r3, #32]
 800b3de:	091b      	lsrs	r3, r3, #4
 800b3e0:	f003 0307 	and.w	r3, r3, #7
 800b3e4:	4904      	ldr	r1, [pc, #16]	@ (800b3f8 <HAL_RCCEx_GetD3PCLK1Freq+0x28>)
 800b3e6:	5ccb      	ldrb	r3, [r1, r3]
 800b3e8:	f003 031f 	and.w	r3, r3, #31
 800b3ec:	fa22 f303 	lsr.w	r3, r2, r3
#else
  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
#endif
}
 800b3f0:	4618      	mov	r0, r3
 800b3f2:	bd80      	pop	{r7, pc}
 800b3f4:	58024400 	.word	0x58024400
 800b3f8:	080145e4 	.word	0x080145e4

0800b3fc <HAL_RCCEx_GetPLL2ClockFreq>:
  *         right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
  * @param  PLL2_Clocks structure.
  * @retval None
  */
void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
{
 800b3fc:	b480      	push	{r7}
 800b3fe:	b089      	sub	sp, #36	@ 0x24
 800b400:	af00      	add	r7, sp, #0
 800b402:	6078      	str	r0, [r7, #4]
  float_t fracn2, pll2vco;

  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
     PLL2xCLK = PLL2_VCO / PLL2x
  */
  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
 800b404:	4ba1      	ldr	r3, [pc, #644]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b406:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800b408:	f003 0303 	and.w	r3, r3, #3
 800b40c:	61bb      	str	r3, [r7, #24]
  pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12);
 800b40e:	4b9f      	ldr	r3, [pc, #636]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b410:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800b412:	0b1b      	lsrs	r3, r3, #12
 800b414:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
 800b418:	617b      	str	r3, [r7, #20]
  pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
 800b41a:	4b9c      	ldr	r3, [pc, #624]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b41c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800b41e:	091b      	lsrs	r3, r3, #4
 800b420:	f003 0301 	and.w	r3, r3, #1
 800b424:	613b      	str	r3, [r7, #16]
  fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
 800b426:	4b99      	ldr	r3, [pc, #612]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b428:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 800b42a:	08db      	lsrs	r3, r3, #3
 800b42c:	f3c3 030c 	ubfx	r3, r3, #0, #13
 800b430:	693a      	ldr	r2, [r7, #16]
 800b432:	fb02 f303 	mul.w	r3, r2, r3
 800b436:	ee07 3a90 	vmov	s15, r3
 800b43a:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b43e:	edc7 7a03 	vstr	s15, [r7, #12]

  if (pll2m != 0U)
 800b442:	697b      	ldr	r3, [r7, #20]
 800b444:	2b00      	cmp	r3, #0
 800b446:	f000 8111 	beq.w	800b66c <HAL_RCCEx_GetPLL2ClockFreq+0x270>
  {
    switch (pllsource)
 800b44a:	69bb      	ldr	r3, [r7, #24]
 800b44c:	2b02      	cmp	r3, #2
 800b44e:	f000 8083 	beq.w	800b558 <HAL_RCCEx_GetPLL2ClockFreq+0x15c>
 800b452:	69bb      	ldr	r3, [r7, #24]
 800b454:	2b02      	cmp	r3, #2
 800b456:	f200 80a1 	bhi.w	800b59c <HAL_RCCEx_GetPLL2ClockFreq+0x1a0>
 800b45a:	69bb      	ldr	r3, [r7, #24]
 800b45c:	2b00      	cmp	r3, #0
 800b45e:	d003      	beq.n	800b468 <HAL_RCCEx_GetPLL2ClockFreq+0x6c>
 800b460:	69bb      	ldr	r3, [r7, #24]
 800b462:	2b01      	cmp	r3, #1
 800b464:	d056      	beq.n	800b514 <HAL_RCCEx_GetPLL2ClockFreq+0x118>
 800b466:	e099      	b.n	800b59c <HAL_RCCEx_GetPLL2ClockFreq+0x1a0>
    {

      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */

        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 800b468:	4b88      	ldr	r3, [pc, #544]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b46a:	681b      	ldr	r3, [r3, #0]
 800b46c:	f003 0320 	and.w	r3, r3, #32
 800b470:	2b00      	cmp	r3, #0
 800b472:	d02d      	beq.n	800b4d0 <HAL_RCCEx_GetPLL2ClockFreq+0xd4>
        {
          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800b474:	4b85      	ldr	r3, [pc, #532]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b476:	681b      	ldr	r3, [r3, #0]
 800b478:	08db      	lsrs	r3, r3, #3
 800b47a:	f003 0303 	and.w	r3, r3, #3
 800b47e:	4a84      	ldr	r2, [pc, #528]	@ (800b690 <HAL_RCCEx_GetPLL2ClockFreq+0x294>)
 800b480:	fa22 f303 	lsr.w	r3, r2, r3
 800b484:	60bb      	str	r3, [r7, #8]
          pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
 800b486:	68bb      	ldr	r3, [r7, #8]
 800b488:	ee07 3a90 	vmov	s15, r3
 800b48c:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b490:	697b      	ldr	r3, [r7, #20]
 800b492:	ee07 3a90 	vmov	s15, r3
 800b496:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b49a:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800b49e:	4b7b      	ldr	r3, [pc, #492]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b4a0:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800b4a2:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800b4a6:	ee07 3a90 	vmov	s15, r3
 800b4aa:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b4ae:	ed97 6a03 	vldr	s12, [r7, #12]
 800b4b2:	eddf 5a78 	vldr	s11, [pc, #480]	@ 800b694 <HAL_RCCEx_GetPLL2ClockFreq+0x298>
 800b4b6:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800b4ba:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800b4be:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800b4c2:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800b4c6:	ee67 7a27 	vmul.f32	s15, s14, s15
 800b4ca:	edc7 7a07 	vstr	s15, [r7, #28]
        }
        else
        {
          pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
        }
        break;
 800b4ce:	e087      	b.n	800b5e0 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>
          pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
 800b4d0:	697b      	ldr	r3, [r7, #20]
 800b4d2:	ee07 3a90 	vmov	s15, r3
 800b4d6:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b4da:	eddf 6a6f 	vldr	s13, [pc, #444]	@ 800b698 <HAL_RCCEx_GetPLL2ClockFreq+0x29c>
 800b4de:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800b4e2:	4b6a      	ldr	r3, [pc, #424]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b4e4:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800b4e6:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800b4ea:	ee07 3a90 	vmov	s15, r3
 800b4ee:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b4f2:	ed97 6a03 	vldr	s12, [r7, #12]
 800b4f6:	eddf 5a67 	vldr	s11, [pc, #412]	@ 800b694 <HAL_RCCEx_GetPLL2ClockFreq+0x298>
 800b4fa:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800b4fe:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800b502:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800b506:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800b50a:	ee67 7a27 	vmul.f32	s15, s14, s15
 800b50e:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800b512:	e065      	b.n	800b5e0 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>

      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
        pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
 800b514:	697b      	ldr	r3, [r7, #20]
 800b516:	ee07 3a90 	vmov	s15, r3
 800b51a:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b51e:	eddf 6a5f 	vldr	s13, [pc, #380]	@ 800b69c <HAL_RCCEx_GetPLL2ClockFreq+0x2a0>
 800b522:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800b526:	4b59      	ldr	r3, [pc, #356]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b528:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800b52a:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800b52e:	ee07 3a90 	vmov	s15, r3
 800b532:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b536:	ed97 6a03 	vldr	s12, [r7, #12]
 800b53a:	eddf 5a56 	vldr	s11, [pc, #344]	@ 800b694 <HAL_RCCEx_GetPLL2ClockFreq+0x298>
 800b53e:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800b542:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800b546:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800b54a:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800b54e:	ee67 7a27 	vmul.f32	s15, s14, s15
 800b552:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800b556:	e043      	b.n	800b5e0 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>

      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
        pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
 800b558:	697b      	ldr	r3, [r7, #20]
 800b55a:	ee07 3a90 	vmov	s15, r3
 800b55e:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b562:	eddf 6a4f 	vldr	s13, [pc, #316]	@ 800b6a0 <HAL_RCCEx_GetPLL2ClockFreq+0x2a4>
 800b566:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800b56a:	4b48      	ldr	r3, [pc, #288]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b56c:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800b56e:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800b572:	ee07 3a90 	vmov	s15, r3
 800b576:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b57a:	ed97 6a03 	vldr	s12, [r7, #12]
 800b57e:	eddf 5a45 	vldr	s11, [pc, #276]	@ 800b694 <HAL_RCCEx_GetPLL2ClockFreq+0x298>
 800b582:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800b586:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800b58a:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800b58e:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800b592:	ee67 7a27 	vmul.f32	s15, s14, s15
 800b596:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800b59a:	e021      	b.n	800b5e0 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>

      default:
        pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
 800b59c:	697b      	ldr	r3, [r7, #20]
 800b59e:	ee07 3a90 	vmov	s15, r3
 800b5a2:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b5a6:	eddf 6a3d 	vldr	s13, [pc, #244]	@ 800b69c <HAL_RCCEx_GetPLL2ClockFreq+0x2a0>
 800b5aa:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800b5ae:	4b37      	ldr	r3, [pc, #220]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b5b0:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800b5b2:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800b5b6:	ee07 3a90 	vmov	s15, r3
 800b5ba:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b5be:	ed97 6a03 	vldr	s12, [r7, #12]
 800b5c2:	eddf 5a34 	vldr	s11, [pc, #208]	@ 800b694 <HAL_RCCEx_GetPLL2ClockFreq+0x298>
 800b5c6:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800b5ca:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800b5ce:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800b5d2:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800b5d6:	ee67 7a27 	vmul.f32	s15, s14, s15
 800b5da:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800b5de:	bf00      	nop
    }
    PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9)  + (float_t)1)) ;
 800b5e0:	4b2a      	ldr	r3, [pc, #168]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b5e2:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800b5e4:	0a5b      	lsrs	r3, r3, #9
 800b5e6:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800b5ea:	ee07 3a90 	vmov	s15, r3
 800b5ee:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b5f2:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800b5f6:	ee37 7a87 	vadd.f32	s14, s15, s14
 800b5fa:	edd7 6a07 	vldr	s13, [r7, #28]
 800b5fe:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800b602:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800b606:	ee17 2a90 	vmov	r2, s15
 800b60a:	687b      	ldr	r3, [r7, #4]
 800b60c:	601a      	str	r2, [r3, #0]
    PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ;
 800b60e:	4b1f      	ldr	r3, [pc, #124]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b610:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800b612:	0c1b      	lsrs	r3, r3, #16
 800b614:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800b618:	ee07 3a90 	vmov	s15, r3
 800b61c:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b620:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800b624:	ee37 7a87 	vadd.f32	s14, s15, s14
 800b628:	edd7 6a07 	vldr	s13, [r7, #28]
 800b62c:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800b630:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800b634:	ee17 2a90 	vmov	r2, s15
 800b638:	687b      	ldr	r3, [r7, #4]
 800b63a:	605a      	str	r2, [r3, #4]
    PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ;
 800b63c:	4b13      	ldr	r3, [pc, #76]	@ (800b68c <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800b63e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800b640:	0e1b      	lsrs	r3, r3, #24
 800b642:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800b646:	ee07 3a90 	vmov	s15, r3
 800b64a:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b64e:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800b652:	ee37 7a87 	vadd.f32	s14, s15, s14
 800b656:	edd7 6a07 	vldr	s13, [r7, #28]
 800b65a:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800b65e:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800b662:	ee17 2a90 	vmov	r2, s15
 800b666:	687b      	ldr	r3, [r7, #4]
 800b668:	609a      	str	r2, [r3, #8]
  {
    PLL2_Clocks->PLL2_P_Frequency = 0U;
    PLL2_Clocks->PLL2_Q_Frequency = 0U;
    PLL2_Clocks->PLL2_R_Frequency = 0U;
  }
}
 800b66a:	e008      	b.n	800b67e <HAL_RCCEx_GetPLL2ClockFreq+0x282>
    PLL2_Clocks->PLL2_P_Frequency = 0U;
 800b66c:	687b      	ldr	r3, [r7, #4]
 800b66e:	2200      	movs	r2, #0
 800b670:	601a      	str	r2, [r3, #0]
    PLL2_Clocks->PLL2_Q_Frequency = 0U;
 800b672:	687b      	ldr	r3, [r7, #4]
 800b674:	2200      	movs	r2, #0
 800b676:	605a      	str	r2, [r3, #4]
    PLL2_Clocks->PLL2_R_Frequency = 0U;
 800b678:	687b      	ldr	r3, [r7, #4]
 800b67a:	2200      	movs	r2, #0
 800b67c:	609a      	str	r2, [r3, #8]
}
 800b67e:	bf00      	nop
 800b680:	3724      	adds	r7, #36	@ 0x24
 800b682:	46bd      	mov	sp, r7
 800b684:	f85d 7b04 	ldr.w	r7, [sp], #4
 800b688:	4770      	bx	lr
 800b68a:	bf00      	nop
 800b68c:	58024400 	.word	0x58024400
 800b690:	03d09000 	.word	0x03d09000
 800b694:	46000000 	.word	0x46000000
 800b698:	4c742400 	.word	0x4c742400
 800b69c:	4a742400 	.word	0x4a742400
 800b6a0:	4bbebc20 	.word	0x4bbebc20

0800b6a4 <HAL_RCCEx_GetPLL3ClockFreq>:
  *         right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
  * @param  PLL3_Clocks structure.
  * @retval None
  */
void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
{
 800b6a4:	b480      	push	{r7}
 800b6a6:	b089      	sub	sp, #36	@ 0x24
 800b6a8:	af00      	add	r7, sp, #0
 800b6aa:	6078      	str	r0, [r7, #4]
  float_t fracn3, pll3vco;

  /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
     PLL3xCLK = PLL3_VCO / PLLxR
  */
  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
 800b6ac:	4ba1      	ldr	r3, [pc, #644]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b6ae:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800b6b0:	f003 0303 	and.w	r3, r3, #3
 800b6b4:	61bb      	str	r3, [r7, #24]
  pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20)  ;
 800b6b6:	4b9f      	ldr	r3, [pc, #636]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b6b8:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800b6ba:	0d1b      	lsrs	r3, r3, #20
 800b6bc:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
 800b6c0:	617b      	str	r3, [r7, #20]
  pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
 800b6c2:	4b9c      	ldr	r3, [pc, #624]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b6c4:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800b6c6:	0a1b      	lsrs	r3, r3, #8
 800b6c8:	f003 0301 	and.w	r3, r3, #1
 800b6cc:	613b      	str	r3, [r7, #16]
  fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
 800b6ce:	4b99      	ldr	r3, [pc, #612]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b6d0:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 800b6d2:	08db      	lsrs	r3, r3, #3
 800b6d4:	f3c3 030c 	ubfx	r3, r3, #0, #13
 800b6d8:	693a      	ldr	r2, [r7, #16]
 800b6da:	fb02 f303 	mul.w	r3, r2, r3
 800b6de:	ee07 3a90 	vmov	s15, r3
 800b6e2:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b6e6:	edc7 7a03 	vstr	s15, [r7, #12]

  if (pll3m != 0U)
 800b6ea:	697b      	ldr	r3, [r7, #20]
 800b6ec:	2b00      	cmp	r3, #0
 800b6ee:	f000 8111 	beq.w	800b914 <HAL_RCCEx_GetPLL3ClockFreq+0x270>
  {
    switch (pllsource)
 800b6f2:	69bb      	ldr	r3, [r7, #24]
 800b6f4:	2b02      	cmp	r3, #2
 800b6f6:	f000 8083 	beq.w	800b800 <HAL_RCCEx_GetPLL3ClockFreq+0x15c>
 800b6fa:	69bb      	ldr	r3, [r7, #24]
 800b6fc:	2b02      	cmp	r3, #2
 800b6fe:	f200 80a1 	bhi.w	800b844 <HAL_RCCEx_GetPLL3ClockFreq+0x1a0>
 800b702:	69bb      	ldr	r3, [r7, #24]
 800b704:	2b00      	cmp	r3, #0
 800b706:	d003      	beq.n	800b710 <HAL_RCCEx_GetPLL3ClockFreq+0x6c>
 800b708:	69bb      	ldr	r3, [r7, #24]
 800b70a:	2b01      	cmp	r3, #1
 800b70c:	d056      	beq.n	800b7bc <HAL_RCCEx_GetPLL3ClockFreq+0x118>
 800b70e:	e099      	b.n	800b844 <HAL_RCCEx_GetPLL3ClockFreq+0x1a0>
    {
      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */

        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 800b710:	4b88      	ldr	r3, [pc, #544]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b712:	681b      	ldr	r3, [r3, #0]
 800b714:	f003 0320 	and.w	r3, r3, #32
 800b718:	2b00      	cmp	r3, #0
 800b71a:	d02d      	beq.n	800b778 <HAL_RCCEx_GetPLL3ClockFreq+0xd4>
        {
          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800b71c:	4b85      	ldr	r3, [pc, #532]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b71e:	681b      	ldr	r3, [r3, #0]
 800b720:	08db      	lsrs	r3, r3, #3
 800b722:	f003 0303 	and.w	r3, r3, #3
 800b726:	4a84      	ldr	r2, [pc, #528]	@ (800b938 <HAL_RCCEx_GetPLL3ClockFreq+0x294>)
 800b728:	fa22 f303 	lsr.w	r3, r2, r3
 800b72c:	60bb      	str	r3, [r7, #8]
          pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
 800b72e:	68bb      	ldr	r3, [r7, #8]
 800b730:	ee07 3a90 	vmov	s15, r3
 800b734:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b738:	697b      	ldr	r3, [r7, #20]
 800b73a:	ee07 3a90 	vmov	s15, r3
 800b73e:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b742:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800b746:	4b7b      	ldr	r3, [pc, #492]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b748:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800b74a:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800b74e:	ee07 3a90 	vmov	s15, r3
 800b752:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b756:	ed97 6a03 	vldr	s12, [r7, #12]
 800b75a:	eddf 5a78 	vldr	s11, [pc, #480]	@ 800b93c <HAL_RCCEx_GetPLL3ClockFreq+0x298>
 800b75e:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800b762:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800b766:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800b76a:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800b76e:	ee67 7a27 	vmul.f32	s15, s14, s15
 800b772:	edc7 7a07 	vstr	s15, [r7, #28]
        }
        else
        {
          pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
        }
        break;
 800b776:	e087      	b.n	800b888 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>
          pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
 800b778:	697b      	ldr	r3, [r7, #20]
 800b77a:	ee07 3a90 	vmov	s15, r3
 800b77e:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b782:	eddf 6a6f 	vldr	s13, [pc, #444]	@ 800b940 <HAL_RCCEx_GetPLL3ClockFreq+0x29c>
 800b786:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800b78a:	4b6a      	ldr	r3, [pc, #424]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b78c:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800b78e:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800b792:	ee07 3a90 	vmov	s15, r3
 800b796:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b79a:	ed97 6a03 	vldr	s12, [r7, #12]
 800b79e:	eddf 5a67 	vldr	s11, [pc, #412]	@ 800b93c <HAL_RCCEx_GetPLL3ClockFreq+0x298>
 800b7a2:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800b7a6:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800b7aa:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800b7ae:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800b7b2:	ee67 7a27 	vmul.f32	s15, s14, s15
 800b7b6:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800b7ba:	e065      	b.n	800b888 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>
      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
        pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
 800b7bc:	697b      	ldr	r3, [r7, #20]
 800b7be:	ee07 3a90 	vmov	s15, r3
 800b7c2:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b7c6:	eddf 6a5f 	vldr	s13, [pc, #380]	@ 800b944 <HAL_RCCEx_GetPLL3ClockFreq+0x2a0>
 800b7ca:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800b7ce:	4b59      	ldr	r3, [pc, #356]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b7d0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800b7d2:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800b7d6:	ee07 3a90 	vmov	s15, r3
 800b7da:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b7de:	ed97 6a03 	vldr	s12, [r7, #12]
 800b7e2:	eddf 5a56 	vldr	s11, [pc, #344]	@ 800b93c <HAL_RCCEx_GetPLL3ClockFreq+0x298>
 800b7e6:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800b7ea:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800b7ee:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800b7f2:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800b7f6:	ee67 7a27 	vmul.f32	s15, s14, s15
 800b7fa:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800b7fe:	e043      	b.n	800b888 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>

      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
        pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
 800b800:	697b      	ldr	r3, [r7, #20]
 800b802:	ee07 3a90 	vmov	s15, r3
 800b806:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b80a:	eddf 6a4f 	vldr	s13, [pc, #316]	@ 800b948 <HAL_RCCEx_GetPLL3ClockFreq+0x2a4>
 800b80e:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800b812:	4b48      	ldr	r3, [pc, #288]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b814:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800b816:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800b81a:	ee07 3a90 	vmov	s15, r3
 800b81e:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b822:	ed97 6a03 	vldr	s12, [r7, #12]
 800b826:	eddf 5a45 	vldr	s11, [pc, #276]	@ 800b93c <HAL_RCCEx_GetPLL3ClockFreq+0x298>
 800b82a:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800b82e:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800b832:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800b836:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800b83a:	ee67 7a27 	vmul.f32	s15, s14, s15
 800b83e:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800b842:	e021      	b.n	800b888 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>

      default:
        pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
 800b844:	697b      	ldr	r3, [r7, #20]
 800b846:	ee07 3a90 	vmov	s15, r3
 800b84a:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b84e:	eddf 6a3d 	vldr	s13, [pc, #244]	@ 800b944 <HAL_RCCEx_GetPLL3ClockFreq+0x2a0>
 800b852:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800b856:	4b37      	ldr	r3, [pc, #220]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b858:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800b85a:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800b85e:	ee07 3a90 	vmov	s15, r3
 800b862:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b866:	ed97 6a03 	vldr	s12, [r7, #12]
 800b86a:	eddf 5a34 	vldr	s11, [pc, #208]	@ 800b93c <HAL_RCCEx_GetPLL3ClockFreq+0x298>
 800b86e:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800b872:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800b876:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800b87a:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800b87e:	ee67 7a27 	vmul.f32	s15, s14, s15
 800b882:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800b886:	bf00      	nop
    }
    PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9)  + (float_t)1)) ;
 800b888:	4b2a      	ldr	r3, [pc, #168]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b88a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800b88c:	0a5b      	lsrs	r3, r3, #9
 800b88e:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800b892:	ee07 3a90 	vmov	s15, r3
 800b896:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b89a:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800b89e:	ee37 7a87 	vadd.f32	s14, s15, s14
 800b8a2:	edd7 6a07 	vldr	s13, [r7, #28]
 800b8a6:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800b8aa:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800b8ae:	ee17 2a90 	vmov	r2, s15
 800b8b2:	687b      	ldr	r3, [r7, #4]
 800b8b4:	601a      	str	r2, [r3, #0]
    PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ;
 800b8b6:	4b1f      	ldr	r3, [pc, #124]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b8b8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800b8ba:	0c1b      	lsrs	r3, r3, #16
 800b8bc:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800b8c0:	ee07 3a90 	vmov	s15, r3
 800b8c4:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b8c8:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800b8cc:	ee37 7a87 	vadd.f32	s14, s15, s14
 800b8d0:	edd7 6a07 	vldr	s13, [r7, #28]
 800b8d4:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800b8d8:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800b8dc:	ee17 2a90 	vmov	r2, s15
 800b8e0:	687b      	ldr	r3, [r7, #4]
 800b8e2:	605a      	str	r2, [r3, #4]
    PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ;
 800b8e4:	4b13      	ldr	r3, [pc, #76]	@ (800b934 <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800b8e6:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800b8e8:	0e1b      	lsrs	r3, r3, #24
 800b8ea:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800b8ee:	ee07 3a90 	vmov	s15, r3
 800b8f2:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b8f6:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800b8fa:	ee37 7a87 	vadd.f32	s14, s15, s14
 800b8fe:	edd7 6a07 	vldr	s13, [r7, #28]
 800b902:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800b906:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800b90a:	ee17 2a90 	vmov	r2, s15
 800b90e:	687b      	ldr	r3, [r7, #4]
 800b910:	609a      	str	r2, [r3, #8]
    PLL3_Clocks->PLL3_P_Frequency = 0U;
    PLL3_Clocks->PLL3_Q_Frequency = 0U;
    PLL3_Clocks->PLL3_R_Frequency = 0U;
  }

}
 800b912:	e008      	b.n	800b926 <HAL_RCCEx_GetPLL3ClockFreq+0x282>
    PLL3_Clocks->PLL3_P_Frequency = 0U;
 800b914:	687b      	ldr	r3, [r7, #4]
 800b916:	2200      	movs	r2, #0
 800b918:	601a      	str	r2, [r3, #0]
    PLL3_Clocks->PLL3_Q_Frequency = 0U;
 800b91a:	687b      	ldr	r3, [r7, #4]
 800b91c:	2200      	movs	r2, #0
 800b91e:	605a      	str	r2, [r3, #4]
    PLL3_Clocks->PLL3_R_Frequency = 0U;
 800b920:	687b      	ldr	r3, [r7, #4]
 800b922:	2200      	movs	r2, #0
 800b924:	609a      	str	r2, [r3, #8]
}
 800b926:	bf00      	nop
 800b928:	3724      	adds	r7, #36	@ 0x24
 800b92a:	46bd      	mov	sp, r7
 800b92c:	f85d 7b04 	ldr.w	r7, [sp], #4
 800b930:	4770      	bx	lr
 800b932:	bf00      	nop
 800b934:	58024400 	.word	0x58024400
 800b938:	03d09000 	.word	0x03d09000
 800b93c:	46000000 	.word	0x46000000
 800b940:	4c742400 	.word	0x4c742400
 800b944:	4a742400 	.word	0x4a742400
 800b948:	4bbebc20 	.word	0x4bbebc20

0800b94c <HAL_RCCEx_GetPLL1ClockFreq>:
  *         right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
  * @param  PLL1_Clocks structure.
  * @retval None
  */
void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
{
 800b94c:	b480      	push	{r7}
 800b94e:	b089      	sub	sp, #36	@ 0x24
 800b950:	af00      	add	r7, sp, #0
 800b952:	6078      	str	r0, [r7, #4]
  uint32_t pllsource, pll1m, pll1fracen, hsivalue;
  float_t fracn1, pll1vco;

  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
 800b954:	4ba0      	ldr	r3, [pc, #640]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800b956:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800b958:	f003 0303 	and.w	r3, r3, #3
 800b95c:	61bb      	str	r3, [r7, #24]
  pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
 800b95e:	4b9e      	ldr	r3, [pc, #632]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800b960:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800b962:	091b      	lsrs	r3, r3, #4
 800b964:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
 800b968:	617b      	str	r3, [r7, #20]
  pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
 800b96a:	4b9b      	ldr	r3, [pc, #620]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800b96c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800b96e:	f003 0301 	and.w	r3, r3, #1
 800b972:	613b      	str	r3, [r7, #16]
  fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
 800b974:	4b98      	ldr	r3, [pc, #608]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800b976:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 800b978:	08db      	lsrs	r3, r3, #3
 800b97a:	f3c3 030c 	ubfx	r3, r3, #0, #13
 800b97e:	693a      	ldr	r2, [r7, #16]
 800b980:	fb02 f303 	mul.w	r3, r2, r3
 800b984:	ee07 3a90 	vmov	s15, r3
 800b988:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b98c:	edc7 7a03 	vstr	s15, [r7, #12]

  if (pll1m != 0U)
 800b990:	697b      	ldr	r3, [r7, #20]
 800b992:	2b00      	cmp	r3, #0
 800b994:	f000 8111 	beq.w	800bbba <HAL_RCCEx_GetPLL1ClockFreq+0x26e>
  {
    switch (pllsource)
 800b998:	69bb      	ldr	r3, [r7, #24]
 800b99a:	2b02      	cmp	r3, #2
 800b99c:	f000 8083 	beq.w	800baa6 <HAL_RCCEx_GetPLL1ClockFreq+0x15a>
 800b9a0:	69bb      	ldr	r3, [r7, #24]
 800b9a2:	2b02      	cmp	r3, #2
 800b9a4:	f200 80a1 	bhi.w	800baea <HAL_RCCEx_GetPLL1ClockFreq+0x19e>
 800b9a8:	69bb      	ldr	r3, [r7, #24]
 800b9aa:	2b00      	cmp	r3, #0
 800b9ac:	d003      	beq.n	800b9b6 <HAL_RCCEx_GetPLL1ClockFreq+0x6a>
 800b9ae:	69bb      	ldr	r3, [r7, #24]
 800b9b0:	2b01      	cmp	r3, #1
 800b9b2:	d056      	beq.n	800ba62 <HAL_RCCEx_GetPLL1ClockFreq+0x116>
 800b9b4:	e099      	b.n	800baea <HAL_RCCEx_GetPLL1ClockFreq+0x19e>
    {

      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */

        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 800b9b6:	4b88      	ldr	r3, [pc, #544]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800b9b8:	681b      	ldr	r3, [r3, #0]
 800b9ba:	f003 0320 	and.w	r3, r3, #32
 800b9be:	2b00      	cmp	r3, #0
 800b9c0:	d02d      	beq.n	800ba1e <HAL_RCCEx_GetPLL1ClockFreq+0xd2>
        {
          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800b9c2:	4b85      	ldr	r3, [pc, #532]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800b9c4:	681b      	ldr	r3, [r3, #0]
 800b9c6:	08db      	lsrs	r3, r3, #3
 800b9c8:	f003 0303 	and.w	r3, r3, #3
 800b9cc:	4a83      	ldr	r2, [pc, #524]	@ (800bbdc <HAL_RCCEx_GetPLL1ClockFreq+0x290>)
 800b9ce:	fa22 f303 	lsr.w	r3, r2, r3
 800b9d2:	60bb      	str	r3, [r7, #8]
          pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800b9d4:	68bb      	ldr	r3, [r7, #8]
 800b9d6:	ee07 3a90 	vmov	s15, r3
 800b9da:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b9de:	697b      	ldr	r3, [r7, #20]
 800b9e0:	ee07 3a90 	vmov	s15, r3
 800b9e4:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800b9e8:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800b9ec:	4b7a      	ldr	r3, [pc, #488]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800b9ee:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800b9f0:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800b9f4:	ee07 3a90 	vmov	s15, r3
 800b9f8:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800b9fc:	ed97 6a03 	vldr	s12, [r7, #12]
 800ba00:	eddf 5a77 	vldr	s11, [pc, #476]	@ 800bbe0 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
 800ba04:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800ba08:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800ba0c:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800ba10:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800ba14:	ee67 7a27 	vmul.f32	s15, s14, s15
 800ba18:	edc7 7a07 	vstr	s15, [r7, #28]
        }
        else
        {
          pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
        }
        break;
 800ba1c:	e087      	b.n	800bb2e <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>
          pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800ba1e:	697b      	ldr	r3, [r7, #20]
 800ba20:	ee07 3a90 	vmov	s15, r3
 800ba24:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800ba28:	eddf 6a6e 	vldr	s13, [pc, #440]	@ 800bbe4 <HAL_RCCEx_GetPLL1ClockFreq+0x298>
 800ba2c:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800ba30:	4b69      	ldr	r3, [pc, #420]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800ba32:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800ba34:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800ba38:	ee07 3a90 	vmov	s15, r3
 800ba3c:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800ba40:	ed97 6a03 	vldr	s12, [r7, #12]
 800ba44:	eddf 5a66 	vldr	s11, [pc, #408]	@ 800bbe0 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
 800ba48:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800ba4c:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800ba50:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800ba54:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800ba58:	ee67 7a27 	vmul.f32	s15, s14, s15
 800ba5c:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800ba60:	e065      	b.n	800bb2e <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>
      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
        pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800ba62:	697b      	ldr	r3, [r7, #20]
 800ba64:	ee07 3a90 	vmov	s15, r3
 800ba68:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800ba6c:	eddf 6a5e 	vldr	s13, [pc, #376]	@ 800bbe8 <HAL_RCCEx_GetPLL1ClockFreq+0x29c>
 800ba70:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800ba74:	4b58      	ldr	r3, [pc, #352]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800ba76:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800ba78:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800ba7c:	ee07 3a90 	vmov	s15, r3
 800ba80:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800ba84:	ed97 6a03 	vldr	s12, [r7, #12]
 800ba88:	eddf 5a55 	vldr	s11, [pc, #340]	@ 800bbe0 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
 800ba8c:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800ba90:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800ba94:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800ba98:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800ba9c:	ee67 7a27 	vmul.f32	s15, s14, s15
 800baa0:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800baa4:	e043      	b.n	800bb2e <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>

      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
        pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800baa6:	697b      	ldr	r3, [r7, #20]
 800baa8:	ee07 3a90 	vmov	s15, r3
 800baac:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800bab0:	eddf 6a4e 	vldr	s13, [pc, #312]	@ 800bbec <HAL_RCCEx_GetPLL1ClockFreq+0x2a0>
 800bab4:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800bab8:	4b47      	ldr	r3, [pc, #284]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800baba:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800babc:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800bac0:	ee07 3a90 	vmov	s15, r3
 800bac4:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800bac8:	ed97 6a03 	vldr	s12, [r7, #12]
 800bacc:	eddf 5a44 	vldr	s11, [pc, #272]	@ 800bbe0 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
 800bad0:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800bad4:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800bad8:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800badc:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800bae0:	ee67 7a27 	vmul.f32	s15, s14, s15
 800bae4:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800bae8:	e021      	b.n	800bb2e <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>

      default:
        pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800baea:	697b      	ldr	r3, [r7, #20]
 800baec:	ee07 3a90 	vmov	s15, r3
 800baf0:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800baf4:	eddf 6a3b 	vldr	s13, [pc, #236]	@ 800bbe4 <HAL_RCCEx_GetPLL1ClockFreq+0x298>
 800baf8:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800bafc:	4b36      	ldr	r3, [pc, #216]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800bafe:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800bb00:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800bb04:	ee07 3a90 	vmov	s15, r3
 800bb08:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800bb0c:	ed97 6a03 	vldr	s12, [r7, #12]
 800bb10:	eddf 5a33 	vldr	s11, [pc, #204]	@ 800bbe0 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
 800bb14:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800bb18:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800bb1c:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800bb20:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800bb24:	ee67 7a27 	vmul.f32	s15, s14, s15
 800bb28:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800bb2c:	bf00      	nop
    }

    PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9)  + (float_t)1)) ;
 800bb2e:	4b2a      	ldr	r3, [pc, #168]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800bb30:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800bb32:	0a5b      	lsrs	r3, r3, #9
 800bb34:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800bb38:	ee07 3a90 	vmov	s15, r3
 800bb3c:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800bb40:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800bb44:	ee37 7a87 	vadd.f32	s14, s15, s14
 800bb48:	edd7 6a07 	vldr	s13, [r7, #28]
 800bb4c:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800bb50:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800bb54:	ee17 2a90 	vmov	r2, s15
 800bb58:	687b      	ldr	r3, [r7, #4]
 800bb5a:	601a      	str	r2, [r3, #0]
    PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ;
 800bb5c:	4b1e      	ldr	r3, [pc, #120]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800bb5e:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800bb60:	0c1b      	lsrs	r3, r3, #16
 800bb62:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800bb66:	ee07 3a90 	vmov	s15, r3
 800bb6a:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800bb6e:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800bb72:	ee37 7a87 	vadd.f32	s14, s15, s14
 800bb76:	edd7 6a07 	vldr	s13, [r7, #28]
 800bb7a:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800bb7e:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800bb82:	ee17 2a90 	vmov	r2, s15
 800bb86:	687b      	ldr	r3, [r7, #4]
 800bb88:	605a      	str	r2, [r3, #4]
    PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ;
 800bb8a:	4b13      	ldr	r3, [pc, #76]	@ (800bbd8 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800bb8c:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800bb8e:	0e1b      	lsrs	r3, r3, #24
 800bb90:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800bb94:	ee07 3a90 	vmov	s15, r3
 800bb98:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800bb9c:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800bba0:	ee37 7a87 	vadd.f32	s14, s15, s14
 800bba4:	edd7 6a07 	vldr	s13, [r7, #28]
 800bba8:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800bbac:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800bbb0:	ee17 2a90 	vmov	r2, s15
 800bbb4:	687b      	ldr	r3, [r7, #4]
 800bbb6:	609a      	str	r2, [r3, #8]
    PLL1_Clocks->PLL1_P_Frequency = 0U;
    PLL1_Clocks->PLL1_Q_Frequency = 0U;
    PLL1_Clocks->PLL1_R_Frequency = 0U;
  }

}
 800bbb8:	e008      	b.n	800bbcc <HAL_RCCEx_GetPLL1ClockFreq+0x280>
    PLL1_Clocks->PLL1_P_Frequency = 0U;
 800bbba:	687b      	ldr	r3, [r7, #4]
 800bbbc:	2200      	movs	r2, #0
 800bbbe:	601a      	str	r2, [r3, #0]
    PLL1_Clocks->PLL1_Q_Frequency = 0U;
 800bbc0:	687b      	ldr	r3, [r7, #4]
 800bbc2:	2200      	movs	r2, #0
 800bbc4:	605a      	str	r2, [r3, #4]
    PLL1_Clocks->PLL1_R_Frequency = 0U;
 800bbc6:	687b      	ldr	r3, [r7, #4]
 800bbc8:	2200      	movs	r2, #0
 800bbca:	609a      	str	r2, [r3, #8]
}
 800bbcc:	bf00      	nop
 800bbce:	3724      	adds	r7, #36	@ 0x24
 800bbd0:	46bd      	mov	sp, r7
 800bbd2:	f85d 7b04 	ldr.w	r7, [sp], #4
 800bbd6:	4770      	bx	lr
 800bbd8:	58024400 	.word	0x58024400
 800bbdc:	03d09000 	.word	0x03d09000
 800bbe0:	46000000 	.word	0x46000000
 800bbe4:	4c742400 	.word	0x4c742400
 800bbe8:	4a742400 	.word	0x4a742400
 800bbec:	4bbebc20 	.word	0x4bbebc20

0800bbf0 <RCCEx_PLL2_Config>:
  * @note   PLL2 is temporary disabled to apply new parameters
  *
  * @retval HAL status
  */
static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
{
 800bbf0:	b580      	push	{r7, lr}
 800bbf2:	b084      	sub	sp, #16
 800bbf4:	af00      	add	r7, sp, #0
 800bbf6:	6078      	str	r0, [r7, #4]
 800bbf8:	6039      	str	r1, [r7, #0]

  uint32_t tickstart;
  HAL_StatusTypeDef status = HAL_OK;
 800bbfa:	2300      	movs	r3, #0
 800bbfc:	73fb      	strb	r3, [r7, #15]
  assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
  assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
  assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));

  /* Check that PLL2 OSC clock source is already set */
  if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
 800bbfe:	4b53      	ldr	r3, [pc, #332]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bc00:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800bc02:	f003 0303 	and.w	r3, r3, #3
 800bc06:	2b03      	cmp	r3, #3
 800bc08:	d101      	bne.n	800bc0e <RCCEx_PLL2_Config+0x1e>
  {
    return HAL_ERROR;
 800bc0a:	2301      	movs	r3, #1
 800bc0c:	e099      	b.n	800bd42 <RCCEx_PLL2_Config+0x152>


  else
  {
    /* Disable  PLL2. */
    __HAL_RCC_PLL2_DISABLE();
 800bc0e:	4b4f      	ldr	r3, [pc, #316]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bc10:	681b      	ldr	r3, [r3, #0]
 800bc12:	4a4e      	ldr	r2, [pc, #312]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bc14:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 800bc18:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 800bc1a:	f7f7 fc53 	bl	80034c4 <HAL_GetTick>
 800bc1e:	60b8      	str	r0, [r7, #8]

    /* Wait till PLL is disabled */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
 800bc20:	e008      	b.n	800bc34 <RCCEx_PLL2_Config+0x44>
    {
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
 800bc22:	f7f7 fc4f 	bl	80034c4 <HAL_GetTick>
 800bc26:	4602      	mov	r2, r0
 800bc28:	68bb      	ldr	r3, [r7, #8]
 800bc2a:	1ad3      	subs	r3, r2, r3
 800bc2c:	2b02      	cmp	r3, #2
 800bc2e:	d901      	bls.n	800bc34 <RCCEx_PLL2_Config+0x44>
      {
        return HAL_TIMEOUT;
 800bc30:	2303      	movs	r3, #3
 800bc32:	e086      	b.n	800bd42 <RCCEx_PLL2_Config+0x152>
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
 800bc34:	4b45      	ldr	r3, [pc, #276]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bc36:	681b      	ldr	r3, [r3, #0]
 800bc38:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800bc3c:	2b00      	cmp	r3, #0
 800bc3e:	d1f0      	bne.n	800bc22 <RCCEx_PLL2_Config+0x32>
      }
    }

    /* Configure PLL2 multiplication and division factors. */
    __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
 800bc40:	4b42      	ldr	r3, [pc, #264]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bc42:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800bc44:	f423 327c 	bic.w	r2, r3, #258048	@ 0x3f000
 800bc48:	687b      	ldr	r3, [r7, #4]
 800bc4a:	681b      	ldr	r3, [r3, #0]
 800bc4c:	031b      	lsls	r3, r3, #12
 800bc4e:	493f      	ldr	r1, [pc, #252]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bc50:	4313      	orrs	r3, r2
 800bc52:	628b      	str	r3, [r1, #40]	@ 0x28
 800bc54:	687b      	ldr	r3, [r7, #4]
 800bc56:	685b      	ldr	r3, [r3, #4]
 800bc58:	3b01      	subs	r3, #1
 800bc5a:	f3c3 0208 	ubfx	r2, r3, #0, #9
 800bc5e:	687b      	ldr	r3, [r7, #4]
 800bc60:	689b      	ldr	r3, [r3, #8]
 800bc62:	3b01      	subs	r3, #1
 800bc64:	025b      	lsls	r3, r3, #9
 800bc66:	b29b      	uxth	r3, r3
 800bc68:	431a      	orrs	r2, r3
 800bc6a:	687b      	ldr	r3, [r7, #4]
 800bc6c:	68db      	ldr	r3, [r3, #12]
 800bc6e:	3b01      	subs	r3, #1
 800bc70:	041b      	lsls	r3, r3, #16
 800bc72:	f403 03fe 	and.w	r3, r3, #8323072	@ 0x7f0000
 800bc76:	431a      	orrs	r2, r3
 800bc78:	687b      	ldr	r3, [r7, #4]
 800bc7a:	691b      	ldr	r3, [r3, #16]
 800bc7c:	3b01      	subs	r3, #1
 800bc7e:	061b      	lsls	r3, r3, #24
 800bc80:	f003 43fe 	and.w	r3, r3, #2130706432	@ 0x7f000000
 800bc84:	4931      	ldr	r1, [pc, #196]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bc86:	4313      	orrs	r3, r2
 800bc88:	638b      	str	r3, [r1, #56]	@ 0x38
                          pll2->PLL2P,
                          pll2->PLL2Q,
                          pll2->PLL2R);

    /* Select PLL2 input reference frequency range: VCI */
    __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
 800bc8a:	4b30      	ldr	r3, [pc, #192]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bc8c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800bc8e:	f023 02c0 	bic.w	r2, r3, #192	@ 0xc0
 800bc92:	687b      	ldr	r3, [r7, #4]
 800bc94:	695b      	ldr	r3, [r3, #20]
 800bc96:	492d      	ldr	r1, [pc, #180]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bc98:	4313      	orrs	r3, r2
 800bc9a:	62cb      	str	r3, [r1, #44]	@ 0x2c

    /* Select PLL2 output frequency range : VCO */
    __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
 800bc9c:	4b2b      	ldr	r3, [pc, #172]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bc9e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800bca0:	f023 0220 	bic.w	r2, r3, #32
 800bca4:	687b      	ldr	r3, [r7, #4]
 800bca6:	699b      	ldr	r3, [r3, #24]
 800bca8:	4928      	ldr	r1, [pc, #160]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bcaa:	4313      	orrs	r3, r2
 800bcac:	62cb      	str	r3, [r1, #44]	@ 0x2c

    /* Disable PLL2FRACN . */
    __HAL_RCC_PLL2FRACN_DISABLE();
 800bcae:	4b27      	ldr	r3, [pc, #156]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bcb0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800bcb2:	4a26      	ldr	r2, [pc, #152]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bcb4:	f023 0310 	bic.w	r3, r3, #16
 800bcb8:	62d3      	str	r3, [r2, #44]	@ 0x2c

    /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
    __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
 800bcba:	4b24      	ldr	r3, [pc, #144]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bcbc:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 800bcbe:	4b24      	ldr	r3, [pc, #144]	@ (800bd50 <RCCEx_PLL2_Config+0x160>)
 800bcc0:	4013      	ands	r3, r2
 800bcc2:	687a      	ldr	r2, [r7, #4]
 800bcc4:	69d2      	ldr	r2, [r2, #28]
 800bcc6:	00d2      	lsls	r2, r2, #3
 800bcc8:	4920      	ldr	r1, [pc, #128]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bcca:	4313      	orrs	r3, r2
 800bccc:	63cb      	str	r3, [r1, #60]	@ 0x3c

    /* Enable PLL2FRACN . */
    __HAL_RCC_PLL2FRACN_ENABLE();
 800bcce:	4b1f      	ldr	r3, [pc, #124]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bcd0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800bcd2:	4a1e      	ldr	r2, [pc, #120]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bcd4:	f043 0310 	orr.w	r3, r3, #16
 800bcd8:	62d3      	str	r3, [r2, #44]	@ 0x2c

    /* Enable the PLL2 clock output */
    if (Divider == DIVIDER_P_UPDATE)
 800bcda:	683b      	ldr	r3, [r7, #0]
 800bcdc:	2b00      	cmp	r3, #0
 800bcde:	d106      	bne.n	800bcee <RCCEx_PLL2_Config+0xfe>
    {
      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
 800bce0:	4b1a      	ldr	r3, [pc, #104]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bce2:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800bce4:	4a19      	ldr	r2, [pc, #100]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bce6:	f443 2300 	orr.w	r3, r3, #524288	@ 0x80000
 800bcea:	62d3      	str	r3, [r2, #44]	@ 0x2c
 800bcec:	e00f      	b.n	800bd0e <RCCEx_PLL2_Config+0x11e>
    }
    else if (Divider == DIVIDER_Q_UPDATE)
 800bcee:	683b      	ldr	r3, [r7, #0]
 800bcf0:	2b01      	cmp	r3, #1
 800bcf2:	d106      	bne.n	800bd02 <RCCEx_PLL2_Config+0x112>
    {
      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
 800bcf4:	4b15      	ldr	r3, [pc, #84]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bcf6:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800bcf8:	4a14      	ldr	r2, [pc, #80]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bcfa:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 800bcfe:	62d3      	str	r3, [r2, #44]	@ 0x2c
 800bd00:	e005      	b.n	800bd0e <RCCEx_PLL2_Config+0x11e>
    }
    else
    {
      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
 800bd02:	4b12      	ldr	r3, [pc, #72]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bd04:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800bd06:	4a11      	ldr	r2, [pc, #68]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bd08:	f443 1300 	orr.w	r3, r3, #2097152	@ 0x200000
 800bd0c:	62d3      	str	r3, [r2, #44]	@ 0x2c
    }

    /* Enable  PLL2. */
    __HAL_RCC_PLL2_ENABLE();
 800bd0e:	4b0f      	ldr	r3, [pc, #60]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bd10:	681b      	ldr	r3, [r3, #0]
 800bd12:	4a0e      	ldr	r2, [pc, #56]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bd14:	f043 6380 	orr.w	r3, r3, #67108864	@ 0x4000000
 800bd18:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 800bd1a:	f7f7 fbd3 	bl	80034c4 <HAL_GetTick>
 800bd1e:	60b8      	str	r0, [r7, #8]

    /* Wait till PLL2 is ready */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
 800bd20:	e008      	b.n	800bd34 <RCCEx_PLL2_Config+0x144>
    {
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
 800bd22:	f7f7 fbcf 	bl	80034c4 <HAL_GetTick>
 800bd26:	4602      	mov	r2, r0
 800bd28:	68bb      	ldr	r3, [r7, #8]
 800bd2a:	1ad3      	subs	r3, r2, r3
 800bd2c:	2b02      	cmp	r3, #2
 800bd2e:	d901      	bls.n	800bd34 <RCCEx_PLL2_Config+0x144>
      {
        return HAL_TIMEOUT;
 800bd30:	2303      	movs	r3, #3
 800bd32:	e006      	b.n	800bd42 <RCCEx_PLL2_Config+0x152>
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
 800bd34:	4b05      	ldr	r3, [pc, #20]	@ (800bd4c <RCCEx_PLL2_Config+0x15c>)
 800bd36:	681b      	ldr	r3, [r3, #0]
 800bd38:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800bd3c:	2b00      	cmp	r3, #0
 800bd3e:	d0f0      	beq.n	800bd22 <RCCEx_PLL2_Config+0x132>
    }

  }


  return status;
 800bd40:	7bfb      	ldrb	r3, [r7, #15]
}
 800bd42:	4618      	mov	r0, r3
 800bd44:	3710      	adds	r7, #16
 800bd46:	46bd      	mov	sp, r7
 800bd48:	bd80      	pop	{r7, pc}
 800bd4a:	bf00      	nop
 800bd4c:	58024400 	.word	0x58024400
 800bd50:	ffff0007 	.word	0xffff0007

0800bd54 <RCCEx_PLL3_Config>:
  * @note   PLL3 is temporary disabled to apply new parameters
  *
  * @retval HAL status
  */
static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
{
 800bd54:	b580      	push	{r7, lr}
 800bd56:	b084      	sub	sp, #16
 800bd58:	af00      	add	r7, sp, #0
 800bd5a:	6078      	str	r0, [r7, #4]
 800bd5c:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;
  HAL_StatusTypeDef status = HAL_OK;
 800bd5e:	2300      	movs	r3, #0
 800bd60:	73fb      	strb	r3, [r7, #15]
  assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
  assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
  assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));

  /* Check that PLL3 OSC clock source is already set */
  if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
 800bd62:	4b53      	ldr	r3, [pc, #332]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800bd64:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800bd66:	f003 0303 	and.w	r3, r3, #3
 800bd6a:	2b03      	cmp	r3, #3
 800bd6c:	d101      	bne.n	800bd72 <RCCEx_PLL3_Config+0x1e>
  {
    return HAL_ERROR;
 800bd6e:	2301      	movs	r3, #1
 800bd70:	e099      	b.n	800bea6 <RCCEx_PLL3_Config+0x152>


  else
  {
    /* Disable  PLL3. */
    __HAL_RCC_PLL3_DISABLE();
 800bd72:	4b4f      	ldr	r3, [pc, #316]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800bd74:	681b      	ldr	r3, [r3, #0]
 800bd76:	4a4e      	ldr	r2, [pc, #312]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800bd78:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 800bd7c:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 800bd7e:	f7f7 fba1 	bl	80034c4 <HAL_GetTick>
 800bd82:	60b8      	str	r0, [r7, #8]
    /* Wait till PLL3 is ready */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
 800bd84:	e008      	b.n	800bd98 <RCCEx_PLL3_Config+0x44>
    {
      if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
 800bd86:	f7f7 fb9d 	bl	80034c4 <HAL_GetTick>
 800bd8a:	4602      	mov	r2, r0
 800bd8c:	68bb      	ldr	r3, [r7, #8]
 800bd8e:	1ad3      	subs	r3, r2, r3
 800bd90:	2b02      	cmp	r3, #2
 800bd92:	d901      	bls.n	800bd98 <RCCEx_PLL3_Config+0x44>
      {
        return HAL_TIMEOUT;
 800bd94:	2303      	movs	r3, #3
 800bd96:	e086      	b.n	800bea6 <RCCEx_PLL3_Config+0x152>
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
 800bd98:	4b45      	ldr	r3, [pc, #276]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800bd9a:	681b      	ldr	r3, [r3, #0]
 800bd9c:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800bda0:	2b00      	cmp	r3, #0
 800bda2:	d1f0      	bne.n	800bd86 <RCCEx_PLL3_Config+0x32>
      }
    }

    /* Configure the PLL3  multiplication and division factors. */
    __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
 800bda4:	4b42      	ldr	r3, [pc, #264]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800bda6:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800bda8:	f023 727c 	bic.w	r2, r3, #66060288	@ 0x3f00000
 800bdac:	687b      	ldr	r3, [r7, #4]
 800bdae:	681b      	ldr	r3, [r3, #0]
 800bdb0:	051b      	lsls	r3, r3, #20
 800bdb2:	493f      	ldr	r1, [pc, #252]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800bdb4:	4313      	orrs	r3, r2
 800bdb6:	628b      	str	r3, [r1, #40]	@ 0x28
 800bdb8:	687b      	ldr	r3, [r7, #4]
 800bdba:	685b      	ldr	r3, [r3, #4]
 800bdbc:	3b01      	subs	r3, #1
 800bdbe:	f3c3 0208 	ubfx	r2, r3, #0, #9
 800bdc2:	687b      	ldr	r3, [r7, #4]
 800bdc4:	689b      	ldr	r3, [r3, #8]
 800bdc6:	3b01      	subs	r3, #1
 800bdc8:	025b      	lsls	r3, r3, #9
 800bdca:	b29b      	uxth	r3, r3
 800bdcc:	431a      	orrs	r2, r3
 800bdce:	687b      	ldr	r3, [r7, #4]
 800bdd0:	68db      	ldr	r3, [r3, #12]
 800bdd2:	3b01      	subs	r3, #1
 800bdd4:	041b      	lsls	r3, r3, #16
 800bdd6:	f403 03fe 	and.w	r3, r3, #8323072	@ 0x7f0000
 800bdda:	431a      	orrs	r2, r3
 800bddc:	687b      	ldr	r3, [r7, #4]
 800bdde:	691b      	ldr	r3, [r3, #16]
 800bde0:	3b01      	subs	r3, #1
 800bde2:	061b      	lsls	r3, r3, #24
 800bde4:	f003 43fe 	and.w	r3, r3, #2130706432	@ 0x7f000000
 800bde8:	4931      	ldr	r1, [pc, #196]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800bdea:	4313      	orrs	r3, r2
 800bdec:	640b      	str	r3, [r1, #64]	@ 0x40
                          pll3->PLL3P,
                          pll3->PLL3Q,
                          pll3->PLL3R);

    /* Select PLL3 input reference frequency range: VCI */
    __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
 800bdee:	4b30      	ldr	r3, [pc, #192]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800bdf0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800bdf2:	f423 6240 	bic.w	r2, r3, #3072	@ 0xc00
 800bdf6:	687b      	ldr	r3, [r7, #4]
 800bdf8:	695b      	ldr	r3, [r3, #20]
 800bdfa:	492d      	ldr	r1, [pc, #180]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800bdfc:	4313      	orrs	r3, r2
 800bdfe:	62cb      	str	r3, [r1, #44]	@ 0x2c

    /* Select PLL3 output frequency range : VCO */
    __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
 800be00:	4b2b      	ldr	r3, [pc, #172]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be02:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800be04:	f423 7200 	bic.w	r2, r3, #512	@ 0x200
 800be08:	687b      	ldr	r3, [r7, #4]
 800be0a:	699b      	ldr	r3, [r3, #24]
 800be0c:	4928      	ldr	r1, [pc, #160]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be0e:	4313      	orrs	r3, r2
 800be10:	62cb      	str	r3, [r1, #44]	@ 0x2c

    /* Disable PLL3FRACN . */
    __HAL_RCC_PLL3FRACN_DISABLE();
 800be12:	4b27      	ldr	r3, [pc, #156]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be14:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800be16:	4a26      	ldr	r2, [pc, #152]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be18:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 800be1c:	62d3      	str	r3, [r2, #44]	@ 0x2c

    /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
    __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
 800be1e:	4b24      	ldr	r3, [pc, #144]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be20:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
 800be22:	4b24      	ldr	r3, [pc, #144]	@ (800beb4 <RCCEx_PLL3_Config+0x160>)
 800be24:	4013      	ands	r3, r2
 800be26:	687a      	ldr	r2, [r7, #4]
 800be28:	69d2      	ldr	r2, [r2, #28]
 800be2a:	00d2      	lsls	r2, r2, #3
 800be2c:	4920      	ldr	r1, [pc, #128]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be2e:	4313      	orrs	r3, r2
 800be30:	644b      	str	r3, [r1, #68]	@ 0x44

    /* Enable PLL3FRACN . */
    __HAL_RCC_PLL3FRACN_ENABLE();
 800be32:	4b1f      	ldr	r3, [pc, #124]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be34:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800be36:	4a1e      	ldr	r2, [pc, #120]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be38:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 800be3c:	62d3      	str	r3, [r2, #44]	@ 0x2c

    /* Enable the PLL3 clock output */
    if (Divider == DIVIDER_P_UPDATE)
 800be3e:	683b      	ldr	r3, [r7, #0]
 800be40:	2b00      	cmp	r3, #0
 800be42:	d106      	bne.n	800be52 <RCCEx_PLL3_Config+0xfe>
    {
      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
 800be44:	4b1a      	ldr	r3, [pc, #104]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be46:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800be48:	4a19      	ldr	r2, [pc, #100]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be4a:	f443 0380 	orr.w	r3, r3, #4194304	@ 0x400000
 800be4e:	62d3      	str	r3, [r2, #44]	@ 0x2c
 800be50:	e00f      	b.n	800be72 <RCCEx_PLL3_Config+0x11e>
    }
    else if (Divider == DIVIDER_Q_UPDATE)
 800be52:	683b      	ldr	r3, [r7, #0]
 800be54:	2b01      	cmp	r3, #1
 800be56:	d106      	bne.n	800be66 <RCCEx_PLL3_Config+0x112>
    {
      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
 800be58:	4b15      	ldr	r3, [pc, #84]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be5a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800be5c:	4a14      	ldr	r2, [pc, #80]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be5e:	f443 0300 	orr.w	r3, r3, #8388608	@ 0x800000
 800be62:	62d3      	str	r3, [r2, #44]	@ 0x2c
 800be64:	e005      	b.n	800be72 <RCCEx_PLL3_Config+0x11e>
    }
    else
    {
      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
 800be66:	4b12      	ldr	r3, [pc, #72]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be68:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800be6a:	4a11      	ldr	r2, [pc, #68]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be6c:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 800be70:	62d3      	str	r3, [r2, #44]	@ 0x2c
    }

    /* Enable  PLL3. */
    __HAL_RCC_PLL3_ENABLE();
 800be72:	4b0f      	ldr	r3, [pc, #60]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be74:	681b      	ldr	r3, [r3, #0]
 800be76:	4a0e      	ldr	r2, [pc, #56]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be78:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 800be7c:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 800be7e:	f7f7 fb21 	bl	80034c4 <HAL_GetTick>
 800be82:	60b8      	str	r0, [r7, #8]

    /* Wait till PLL3 is ready */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
 800be84:	e008      	b.n	800be98 <RCCEx_PLL3_Config+0x144>
    {
      if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
 800be86:	f7f7 fb1d 	bl	80034c4 <HAL_GetTick>
 800be8a:	4602      	mov	r2, r0
 800be8c:	68bb      	ldr	r3, [r7, #8]
 800be8e:	1ad3      	subs	r3, r2, r3
 800be90:	2b02      	cmp	r3, #2
 800be92:	d901      	bls.n	800be98 <RCCEx_PLL3_Config+0x144>
      {
        return HAL_TIMEOUT;
 800be94:	2303      	movs	r3, #3
 800be96:	e006      	b.n	800bea6 <RCCEx_PLL3_Config+0x152>
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
 800be98:	4b05      	ldr	r3, [pc, #20]	@ (800beb0 <RCCEx_PLL3_Config+0x15c>)
 800be9a:	681b      	ldr	r3, [r3, #0]
 800be9c:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800bea0:	2b00      	cmp	r3, #0
 800bea2:	d0f0      	beq.n	800be86 <RCCEx_PLL3_Config+0x132>
    }

  }


  return status;
 800bea4:	7bfb      	ldrb	r3, [r7, #15]
}
 800bea6:	4618      	mov	r0, r3
 800bea8:	3710      	adds	r7, #16
 800beaa:	46bd      	mov	sp, r7
 800beac:	bd80      	pop	{r7, pc}
 800beae:	bf00      	nop
 800beb0:	58024400 	.word	0x58024400
 800beb4:	ffff0007 	.word	0xffff0007

0800beb8 <HAL_RNG_Init>:
  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
  *                the configuration information for RNG.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
 800beb8:	b580      	push	{r7, lr}
 800beba:	b084      	sub	sp, #16
 800bebc:	af00      	add	r7, sp, #0
 800bebe:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  /* Check the RNG handle allocation */
  if (hrng == NULL)
 800bec0:	687b      	ldr	r3, [r7, #4]
 800bec2:	2b00      	cmp	r3, #0
 800bec4:	d101      	bne.n	800beca <HAL_RNG_Init+0x12>
  {
    return HAL_ERROR;
 800bec6:	2301      	movs	r3, #1
 800bec8:	e054      	b.n	800bf74 <HAL_RNG_Init+0xbc>

    /* Init the low level hardware */
    hrng->MspInitCallback(hrng);
  }
#else
  if (hrng->State == HAL_RNG_STATE_RESET)
 800beca:	687b      	ldr	r3, [r7, #4]
 800becc:	7a5b      	ldrb	r3, [r3, #9]
 800bece:	b2db      	uxtb	r3, r3
 800bed0:	2b00      	cmp	r3, #0
 800bed2:	d105      	bne.n	800bee0 <HAL_RNG_Init+0x28>
  {
    /* Allocate lock resource and initialize it */
    hrng->Lock = HAL_UNLOCKED;
 800bed4:	687b      	ldr	r3, [r7, #4]
 800bed6:	2200      	movs	r2, #0
 800bed8:	721a      	strb	r2, [r3, #8]

    /* Init the low level hardware */
    HAL_RNG_MspInit(hrng);
 800beda:	6878      	ldr	r0, [r7, #4]
 800bedc:	f7f6 fa00 	bl	80022e0 <HAL_RNG_MspInit>
  }
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */

  /* Change RNG peripheral state */
  hrng->State = HAL_RNG_STATE_BUSY;
 800bee0:	687b      	ldr	r3, [r7, #4]
 800bee2:	2202      	movs	r2, #2
 800bee4:	725a      	strb	r2, [r3, #9]
      }
    }
  }
#else
  /* Clock Error Detection Configuration */
  MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
 800bee6:	687b      	ldr	r3, [r7, #4]
 800bee8:	681b      	ldr	r3, [r3, #0]
 800beea:	681b      	ldr	r3, [r3, #0]
 800beec:	f023 0120 	bic.w	r1, r3, #32
 800bef0:	687b      	ldr	r3, [r7, #4]
 800bef2:	685a      	ldr	r2, [r3, #4]
 800bef4:	687b      	ldr	r3, [r7, #4]
 800bef6:	681b      	ldr	r3, [r3, #0]
 800bef8:	430a      	orrs	r2, r1
 800befa:	601a      	str	r2, [r3, #0]
#endif /* RNG_CR_CONDRST */

  /* Enable the RNG Peripheral */
  __HAL_RNG_ENABLE(hrng);
 800befc:	687b      	ldr	r3, [r7, #4]
 800befe:	681b      	ldr	r3, [r3, #0]
 800bf00:	681a      	ldr	r2, [r3, #0]
 800bf02:	687b      	ldr	r3, [r7, #4]
 800bf04:	681b      	ldr	r3, [r3, #0]
 800bf06:	f042 0204 	orr.w	r2, r2, #4
 800bf0a:	601a      	str	r2, [r3, #0]

  /* verify that no seed error */
  if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
 800bf0c:	687b      	ldr	r3, [r7, #4]
 800bf0e:	681b      	ldr	r3, [r3, #0]
 800bf10:	685b      	ldr	r3, [r3, #4]
 800bf12:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800bf16:	2b40      	cmp	r3, #64	@ 0x40
 800bf18:	d104      	bne.n	800bf24 <HAL_RNG_Init+0x6c>
  {
    hrng->State = HAL_RNG_STATE_ERROR;
 800bf1a:	687b      	ldr	r3, [r7, #4]
 800bf1c:	2204      	movs	r2, #4
 800bf1e:	725a      	strb	r2, [r3, #9]
    return HAL_ERROR;
 800bf20:	2301      	movs	r3, #1
 800bf22:	e027      	b.n	800bf74 <HAL_RNG_Init+0xbc>
  }
  /* Get tick */
  tickstart = HAL_GetTick();
 800bf24:	f7f7 face 	bl	80034c4 <HAL_GetTick>
 800bf28:	60f8      	str	r0, [r7, #12]
  /* Check if data register contains valid random data */
  while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
 800bf2a:	e015      	b.n	800bf58 <HAL_RNG_Init+0xa0>
  {
    if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
 800bf2c:	f7f7 faca 	bl	80034c4 <HAL_GetTick>
 800bf30:	4602      	mov	r2, r0
 800bf32:	68fb      	ldr	r3, [r7, #12]
 800bf34:	1ad3      	subs	r3, r2, r3
 800bf36:	2b02      	cmp	r3, #2
 800bf38:	d90e      	bls.n	800bf58 <HAL_RNG_Init+0xa0>
    {
      /* New check to avoid false timeout detection in case of preemption */
      if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
 800bf3a:	687b      	ldr	r3, [r7, #4]
 800bf3c:	681b      	ldr	r3, [r3, #0]
 800bf3e:	685b      	ldr	r3, [r3, #4]
 800bf40:	f003 0304 	and.w	r3, r3, #4
 800bf44:	2b04      	cmp	r3, #4
 800bf46:	d107      	bne.n	800bf58 <HAL_RNG_Init+0xa0>
      {
        hrng->State = HAL_RNG_STATE_ERROR;
 800bf48:	687b      	ldr	r3, [r7, #4]
 800bf4a:	2204      	movs	r2, #4
 800bf4c:	725a      	strb	r2, [r3, #9]
        hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
 800bf4e:	687b      	ldr	r3, [r7, #4]
 800bf50:	2202      	movs	r2, #2
 800bf52:	60da      	str	r2, [r3, #12]
        return HAL_ERROR;
 800bf54:	2301      	movs	r3, #1
 800bf56:	e00d      	b.n	800bf74 <HAL_RNG_Init+0xbc>
  while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
 800bf58:	687b      	ldr	r3, [r7, #4]
 800bf5a:	681b      	ldr	r3, [r3, #0]
 800bf5c:	685b      	ldr	r3, [r3, #4]
 800bf5e:	f003 0304 	and.w	r3, r3, #4
 800bf62:	2b04      	cmp	r3, #4
 800bf64:	d0e2      	beq.n	800bf2c <HAL_RNG_Init+0x74>
      }
    }
  }

  /* Initialize the RNG state */
  hrng->State = HAL_RNG_STATE_READY;
 800bf66:	687b      	ldr	r3, [r7, #4]
 800bf68:	2201      	movs	r2, #1
 800bf6a:	725a      	strb	r2, [r3, #9]

  /* Initialise the error code */
  hrng->ErrorCode = HAL_RNG_ERROR_NONE;
 800bf6c:	687b      	ldr	r3, [r7, #4]
 800bf6e:	2200      	movs	r2, #0
 800bf70:	60da      	str	r2, [r3, #12]

  /* Return function status */
  return HAL_OK;
 800bf72:	2300      	movs	r3, #0
}
 800bf74:	4618      	mov	r0, r3
 800bf76:	3710      	adds	r7, #16
 800bf78:	46bd      	mov	sp, r7
 800bf7a:	bd80      	pop	{r7, pc}

0800bf7c <HAL_TIM_Base_Init>:
  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
 800bf7c:	b580      	push	{r7, lr}
 800bf7e:	b082      	sub	sp, #8
 800bf80:	af00      	add	r7, sp, #0
 800bf82:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 800bf84:	687b      	ldr	r3, [r7, #4]
 800bf86:	2b00      	cmp	r3, #0
 800bf88:	d101      	bne.n	800bf8e <HAL_TIM_Base_Init+0x12>
  {
    return HAL_ERROR;
 800bf8a:	2301      	movs	r3, #1
 800bf8c:	e049      	b.n	800c022 <HAL_TIM_Base_Init+0xa6>
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 800bf8e:	687b      	ldr	r3, [r7, #4]
 800bf90:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 800bf94:	b2db      	uxtb	r3, r3
 800bf96:	2b00      	cmp	r3, #0
 800bf98:	d106      	bne.n	800bfa8 <HAL_TIM_Base_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 800bf9a:	687b      	ldr	r3, [r7, #4]
 800bf9c:	2200      	movs	r2, #0
 800bf9e:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->Base_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_TIM_Base_MspInit(htim);
 800bfa2:	6878      	ldr	r0, [r7, #4]
 800bfa4:	f7f6 f9d6 	bl	8002354 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 800bfa8:	687b      	ldr	r3, [r7, #4]
 800bfaa:	2202      	movs	r2, #2
 800bfac:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Set the Time Base configuration */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 800bfb0:	687b      	ldr	r3, [r7, #4]
 800bfb2:	681a      	ldr	r2, [r3, #0]
 800bfb4:	687b      	ldr	r3, [r7, #4]
 800bfb6:	3304      	adds	r3, #4
 800bfb8:	4619      	mov	r1, r3
 800bfba:	4610      	mov	r0, r2
 800bfbc:	f000 fb46 	bl	800c64c <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 800bfc0:	687b      	ldr	r3, [r7, #4]
 800bfc2:	2201      	movs	r2, #1
 800bfc4:	f883 2048 	strb.w	r2, [r3, #72]	@ 0x48

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 800bfc8:	687b      	ldr	r3, [r7, #4]
 800bfca:	2201      	movs	r2, #1
 800bfcc:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 800bfd0:	687b      	ldr	r3, [r7, #4]
 800bfd2:	2201      	movs	r2, #1
 800bfd4:	f883 203f 	strb.w	r2, [r3, #63]	@ 0x3f
 800bfd8:	687b      	ldr	r3, [r7, #4]
 800bfda:	2201      	movs	r2, #1
 800bfdc:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 800bfe0:	687b      	ldr	r3, [r7, #4]
 800bfe2:	2201      	movs	r2, #1
 800bfe4:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 800bfe8:	687b      	ldr	r3, [r7, #4]
 800bfea:	2201      	movs	r2, #1
 800bfec:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
 800bff0:	687b      	ldr	r3, [r7, #4]
 800bff2:	2201      	movs	r2, #1
 800bff4:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 800bff8:	687b      	ldr	r3, [r7, #4]
 800bffa:	2201      	movs	r2, #1
 800bffc:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 800c000:	687b      	ldr	r3, [r7, #4]
 800c002:	2201      	movs	r2, #1
 800c004:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 800c008:	687b      	ldr	r3, [r7, #4]
 800c00a:	2201      	movs	r2, #1
 800c00c:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
 800c010:	687b      	ldr	r3, [r7, #4]
 800c012:	2201      	movs	r2, #1
 800c014:	f883 2047 	strb.w	r2, [r3, #71]	@ 0x47

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 800c018:	687b      	ldr	r3, [r7, #4]
 800c01a:	2201      	movs	r2, #1
 800c01c:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  return HAL_OK;
 800c020:	2300      	movs	r3, #0
}
 800c022:	4618      	mov	r0, r3
 800c024:	3708      	adds	r7, #8
 800c026:	46bd      	mov	sp, r7
 800c028:	bd80      	pop	{r7, pc}
	...

0800c02c <HAL_TIM_Base_Start>:
  * @brief  Starts the TIM Base generation.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
{
 800c02c:	b480      	push	{r7}
 800c02e:	b085      	sub	sp, #20
 800c030:	af00      	add	r7, sp, #0
 800c032:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY)
 800c034:	687b      	ldr	r3, [r7, #4]
 800c036:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 800c03a:	b2db      	uxtb	r3, r3
 800c03c:	2b01      	cmp	r3, #1
 800c03e:	d001      	beq.n	800c044 <HAL_TIM_Base_Start+0x18>
  {
    return HAL_ERROR;
 800c040:	2301      	movs	r3, #1
 800c042:	e04c      	b.n	800c0de <HAL_TIM_Base_Start+0xb2>
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 800c044:	687b      	ldr	r3, [r7, #4]
 800c046:	2202      	movs	r2, #2
 800c048:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 800c04c:	687b      	ldr	r3, [r7, #4]
 800c04e:	681b      	ldr	r3, [r3, #0]
 800c050:	4a26      	ldr	r2, [pc, #152]	@ (800c0ec <HAL_TIM_Base_Start+0xc0>)
 800c052:	4293      	cmp	r3, r2
 800c054:	d022      	beq.n	800c09c <HAL_TIM_Base_Start+0x70>
 800c056:	687b      	ldr	r3, [r7, #4]
 800c058:	681b      	ldr	r3, [r3, #0]
 800c05a:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800c05e:	d01d      	beq.n	800c09c <HAL_TIM_Base_Start+0x70>
 800c060:	687b      	ldr	r3, [r7, #4]
 800c062:	681b      	ldr	r3, [r3, #0]
 800c064:	4a22      	ldr	r2, [pc, #136]	@ (800c0f0 <HAL_TIM_Base_Start+0xc4>)
 800c066:	4293      	cmp	r3, r2
 800c068:	d018      	beq.n	800c09c <HAL_TIM_Base_Start+0x70>
 800c06a:	687b      	ldr	r3, [r7, #4]
 800c06c:	681b      	ldr	r3, [r3, #0]
 800c06e:	4a21      	ldr	r2, [pc, #132]	@ (800c0f4 <HAL_TIM_Base_Start+0xc8>)
 800c070:	4293      	cmp	r3, r2
 800c072:	d013      	beq.n	800c09c <HAL_TIM_Base_Start+0x70>
 800c074:	687b      	ldr	r3, [r7, #4]
 800c076:	681b      	ldr	r3, [r3, #0]
 800c078:	4a1f      	ldr	r2, [pc, #124]	@ (800c0f8 <HAL_TIM_Base_Start+0xcc>)
 800c07a:	4293      	cmp	r3, r2
 800c07c:	d00e      	beq.n	800c09c <HAL_TIM_Base_Start+0x70>
 800c07e:	687b      	ldr	r3, [r7, #4]
 800c080:	681b      	ldr	r3, [r3, #0]
 800c082:	4a1e      	ldr	r2, [pc, #120]	@ (800c0fc <HAL_TIM_Base_Start+0xd0>)
 800c084:	4293      	cmp	r3, r2
 800c086:	d009      	beq.n	800c09c <HAL_TIM_Base_Start+0x70>
 800c088:	687b      	ldr	r3, [r7, #4]
 800c08a:	681b      	ldr	r3, [r3, #0]
 800c08c:	4a1c      	ldr	r2, [pc, #112]	@ (800c100 <HAL_TIM_Base_Start+0xd4>)
 800c08e:	4293      	cmp	r3, r2
 800c090:	d004      	beq.n	800c09c <HAL_TIM_Base_Start+0x70>
 800c092:	687b      	ldr	r3, [r7, #4]
 800c094:	681b      	ldr	r3, [r3, #0]
 800c096:	4a1b      	ldr	r2, [pc, #108]	@ (800c104 <HAL_TIM_Base_Start+0xd8>)
 800c098:	4293      	cmp	r3, r2
 800c09a:	d115      	bne.n	800c0c8 <HAL_TIM_Base_Start+0x9c>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 800c09c:	687b      	ldr	r3, [r7, #4]
 800c09e:	681b      	ldr	r3, [r3, #0]
 800c0a0:	689a      	ldr	r2, [r3, #8]
 800c0a2:	4b19      	ldr	r3, [pc, #100]	@ (800c108 <HAL_TIM_Base_Start+0xdc>)
 800c0a4:	4013      	ands	r3, r2
 800c0a6:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800c0a8:	68fb      	ldr	r3, [r7, #12]
 800c0aa:	2b06      	cmp	r3, #6
 800c0ac:	d015      	beq.n	800c0da <HAL_TIM_Base_Start+0xae>
 800c0ae:	68fb      	ldr	r3, [r7, #12]
 800c0b0:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800c0b4:	d011      	beq.n	800c0da <HAL_TIM_Base_Start+0xae>
    {
      __HAL_TIM_ENABLE(htim);
 800c0b6:	687b      	ldr	r3, [r7, #4]
 800c0b8:	681b      	ldr	r3, [r3, #0]
 800c0ba:	681a      	ldr	r2, [r3, #0]
 800c0bc:	687b      	ldr	r3, [r7, #4]
 800c0be:	681b      	ldr	r3, [r3, #0]
 800c0c0:	f042 0201 	orr.w	r2, r2, #1
 800c0c4:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800c0c6:	e008      	b.n	800c0da <HAL_TIM_Base_Start+0xae>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 800c0c8:	687b      	ldr	r3, [r7, #4]
 800c0ca:	681b      	ldr	r3, [r3, #0]
 800c0cc:	681a      	ldr	r2, [r3, #0]
 800c0ce:	687b      	ldr	r3, [r7, #4]
 800c0d0:	681b      	ldr	r3, [r3, #0]
 800c0d2:	f042 0201 	orr.w	r2, r2, #1
 800c0d6:	601a      	str	r2, [r3, #0]
 800c0d8:	e000      	b.n	800c0dc <HAL_TIM_Base_Start+0xb0>
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800c0da:	bf00      	nop
  }

  /* Return function status */
  return HAL_OK;
 800c0dc:	2300      	movs	r3, #0
}
 800c0de:	4618      	mov	r0, r3
 800c0e0:	3714      	adds	r7, #20
 800c0e2:	46bd      	mov	sp, r7
 800c0e4:	f85d 7b04 	ldr.w	r7, [sp], #4
 800c0e8:	4770      	bx	lr
 800c0ea:	bf00      	nop
 800c0ec:	40010000 	.word	0x40010000
 800c0f0:	40000400 	.word	0x40000400
 800c0f4:	40000800 	.word	0x40000800
 800c0f8:	40000c00 	.word	0x40000c00
 800c0fc:	40010400 	.word	0x40010400
 800c100:	40001800 	.word	0x40001800
 800c104:	40014000 	.word	0x40014000
 800c108:	00010007 	.word	0x00010007

0800c10c <HAL_TIM_Base_Start_IT>:
  * @brief  Starts the TIM Base generation in interrupt mode.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
 800c10c:	b480      	push	{r7}
 800c10e:	b085      	sub	sp, #20
 800c110:	af00      	add	r7, sp, #0
 800c112:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY)
 800c114:	687b      	ldr	r3, [r7, #4]
 800c116:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 800c11a:	b2db      	uxtb	r3, r3
 800c11c:	2b01      	cmp	r3, #1
 800c11e:	d001      	beq.n	800c124 <HAL_TIM_Base_Start_IT+0x18>
  {
    return HAL_ERROR;
 800c120:	2301      	movs	r3, #1
 800c122:	e054      	b.n	800c1ce <HAL_TIM_Base_Start_IT+0xc2>
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 800c124:	687b      	ldr	r3, [r7, #4]
 800c126:	2202      	movs	r2, #2
 800c128:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Enable the TIM Update interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 800c12c:	687b      	ldr	r3, [r7, #4]
 800c12e:	681b      	ldr	r3, [r3, #0]
 800c130:	68da      	ldr	r2, [r3, #12]
 800c132:	687b      	ldr	r3, [r7, #4]
 800c134:	681b      	ldr	r3, [r3, #0]
 800c136:	f042 0201 	orr.w	r2, r2, #1
 800c13a:	60da      	str	r2, [r3, #12]

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 800c13c:	687b      	ldr	r3, [r7, #4]
 800c13e:	681b      	ldr	r3, [r3, #0]
 800c140:	4a26      	ldr	r2, [pc, #152]	@ (800c1dc <HAL_TIM_Base_Start_IT+0xd0>)
 800c142:	4293      	cmp	r3, r2
 800c144:	d022      	beq.n	800c18c <HAL_TIM_Base_Start_IT+0x80>
 800c146:	687b      	ldr	r3, [r7, #4]
 800c148:	681b      	ldr	r3, [r3, #0]
 800c14a:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800c14e:	d01d      	beq.n	800c18c <HAL_TIM_Base_Start_IT+0x80>
 800c150:	687b      	ldr	r3, [r7, #4]
 800c152:	681b      	ldr	r3, [r3, #0]
 800c154:	4a22      	ldr	r2, [pc, #136]	@ (800c1e0 <HAL_TIM_Base_Start_IT+0xd4>)
 800c156:	4293      	cmp	r3, r2
 800c158:	d018      	beq.n	800c18c <HAL_TIM_Base_Start_IT+0x80>
 800c15a:	687b      	ldr	r3, [r7, #4]
 800c15c:	681b      	ldr	r3, [r3, #0]
 800c15e:	4a21      	ldr	r2, [pc, #132]	@ (800c1e4 <HAL_TIM_Base_Start_IT+0xd8>)
 800c160:	4293      	cmp	r3, r2
 800c162:	d013      	beq.n	800c18c <HAL_TIM_Base_Start_IT+0x80>
 800c164:	687b      	ldr	r3, [r7, #4]
 800c166:	681b      	ldr	r3, [r3, #0]
 800c168:	4a1f      	ldr	r2, [pc, #124]	@ (800c1e8 <HAL_TIM_Base_Start_IT+0xdc>)
 800c16a:	4293      	cmp	r3, r2
 800c16c:	d00e      	beq.n	800c18c <HAL_TIM_Base_Start_IT+0x80>
 800c16e:	687b      	ldr	r3, [r7, #4]
 800c170:	681b      	ldr	r3, [r3, #0]
 800c172:	4a1e      	ldr	r2, [pc, #120]	@ (800c1ec <HAL_TIM_Base_Start_IT+0xe0>)
 800c174:	4293      	cmp	r3, r2
 800c176:	d009      	beq.n	800c18c <HAL_TIM_Base_Start_IT+0x80>
 800c178:	687b      	ldr	r3, [r7, #4]
 800c17a:	681b      	ldr	r3, [r3, #0]
 800c17c:	4a1c      	ldr	r2, [pc, #112]	@ (800c1f0 <HAL_TIM_Base_Start_IT+0xe4>)
 800c17e:	4293      	cmp	r3, r2
 800c180:	d004      	beq.n	800c18c <HAL_TIM_Base_Start_IT+0x80>
 800c182:	687b      	ldr	r3, [r7, #4]
 800c184:	681b      	ldr	r3, [r3, #0]
 800c186:	4a1b      	ldr	r2, [pc, #108]	@ (800c1f4 <HAL_TIM_Base_Start_IT+0xe8>)
 800c188:	4293      	cmp	r3, r2
 800c18a:	d115      	bne.n	800c1b8 <HAL_TIM_Base_Start_IT+0xac>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 800c18c:	687b      	ldr	r3, [r7, #4]
 800c18e:	681b      	ldr	r3, [r3, #0]
 800c190:	689a      	ldr	r2, [r3, #8]
 800c192:	4b19      	ldr	r3, [pc, #100]	@ (800c1f8 <HAL_TIM_Base_Start_IT+0xec>)
 800c194:	4013      	ands	r3, r2
 800c196:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800c198:	68fb      	ldr	r3, [r7, #12]
 800c19a:	2b06      	cmp	r3, #6
 800c19c:	d015      	beq.n	800c1ca <HAL_TIM_Base_Start_IT+0xbe>
 800c19e:	68fb      	ldr	r3, [r7, #12]
 800c1a0:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800c1a4:	d011      	beq.n	800c1ca <HAL_TIM_Base_Start_IT+0xbe>
    {
      __HAL_TIM_ENABLE(htim);
 800c1a6:	687b      	ldr	r3, [r7, #4]
 800c1a8:	681b      	ldr	r3, [r3, #0]
 800c1aa:	681a      	ldr	r2, [r3, #0]
 800c1ac:	687b      	ldr	r3, [r7, #4]
 800c1ae:	681b      	ldr	r3, [r3, #0]
 800c1b0:	f042 0201 	orr.w	r2, r2, #1
 800c1b4:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800c1b6:	e008      	b.n	800c1ca <HAL_TIM_Base_Start_IT+0xbe>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 800c1b8:	687b      	ldr	r3, [r7, #4]
 800c1ba:	681b      	ldr	r3, [r3, #0]
 800c1bc:	681a      	ldr	r2, [r3, #0]
 800c1be:	687b      	ldr	r3, [r7, #4]
 800c1c0:	681b      	ldr	r3, [r3, #0]
 800c1c2:	f042 0201 	orr.w	r2, r2, #1
 800c1c6:	601a      	str	r2, [r3, #0]
 800c1c8:	e000      	b.n	800c1cc <HAL_TIM_Base_Start_IT+0xc0>
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800c1ca:	bf00      	nop
  }

  /* Return function status */
  return HAL_OK;
 800c1cc:	2300      	movs	r3, #0
}
 800c1ce:	4618      	mov	r0, r3
 800c1d0:	3714      	adds	r7, #20
 800c1d2:	46bd      	mov	sp, r7
 800c1d4:	f85d 7b04 	ldr.w	r7, [sp], #4
 800c1d8:	4770      	bx	lr
 800c1da:	bf00      	nop
 800c1dc:	40010000 	.word	0x40010000
 800c1e0:	40000400 	.word	0x40000400
 800c1e4:	40000800 	.word	0x40000800
 800c1e8:	40000c00 	.word	0x40000c00
 800c1ec:	40010400 	.word	0x40010400
 800c1f0:	40001800 	.word	0x40001800
 800c1f4:	40014000 	.word	0x40014000
 800c1f8:	00010007 	.word	0x00010007

0800c1fc <HAL_TIM_IRQHandler>:
  * @brief  This function handles TIM interrupts requests.
  * @param  htim TIM  handle
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
 800c1fc:	b580      	push	{r7, lr}
 800c1fe:	b084      	sub	sp, #16
 800c200:	af00      	add	r7, sp, #0
 800c202:	6078      	str	r0, [r7, #4]
  uint32_t itsource = htim->Instance->DIER;
 800c204:	687b      	ldr	r3, [r7, #4]
 800c206:	681b      	ldr	r3, [r3, #0]
 800c208:	68db      	ldr	r3, [r3, #12]
 800c20a:	60fb      	str	r3, [r7, #12]
  uint32_t itflag   = htim->Instance->SR;
 800c20c:	687b      	ldr	r3, [r7, #4]
 800c20e:	681b      	ldr	r3, [r3, #0]
 800c210:	691b      	ldr	r3, [r3, #16]
 800c212:	60bb      	str	r3, [r7, #8]

  /* Capture compare 1 event */
  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
 800c214:	68bb      	ldr	r3, [r7, #8]
 800c216:	f003 0302 	and.w	r3, r3, #2
 800c21a:	2b00      	cmp	r3, #0
 800c21c:	d020      	beq.n	800c260 <HAL_TIM_IRQHandler+0x64>
  {
    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
 800c21e:	68fb      	ldr	r3, [r7, #12]
 800c220:	f003 0302 	and.w	r3, r3, #2
 800c224:	2b00      	cmp	r3, #0
 800c226:	d01b      	beq.n	800c260 <HAL_TIM_IRQHandler+0x64>
    {
      {
        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
 800c228:	687b      	ldr	r3, [r7, #4]
 800c22a:	681b      	ldr	r3, [r3, #0]
 800c22c:	f06f 0202 	mvn.w	r2, #2
 800c230:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 800c232:	687b      	ldr	r3, [r7, #4]
 800c234:	2201      	movs	r2, #1
 800c236:	771a      	strb	r2, [r3, #28]

        /* Input capture event */
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 800c238:	687b      	ldr	r3, [r7, #4]
 800c23a:	681b      	ldr	r3, [r3, #0]
 800c23c:	699b      	ldr	r3, [r3, #24]
 800c23e:	f003 0303 	and.w	r3, r3, #3
 800c242:	2b00      	cmp	r3, #0
 800c244:	d003      	beq.n	800c24e <HAL_TIM_IRQHandler+0x52>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->IC_CaptureCallback(htim);
#else
          HAL_TIM_IC_CaptureCallback(htim);
 800c246:	6878      	ldr	r0, [r7, #4]
 800c248:	f000 f9e2 	bl	800c610 <HAL_TIM_IC_CaptureCallback>
 800c24c:	e005      	b.n	800c25a <HAL_TIM_IRQHandler+0x5e>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->OC_DelayElapsedCallback(htim);
          htim->PWM_PulseFinishedCallback(htim);
#else
          HAL_TIM_OC_DelayElapsedCallback(htim);
 800c24e:	6878      	ldr	r0, [r7, #4]
 800c250:	f000 f9d4 	bl	800c5fc <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 800c254:	6878      	ldr	r0, [r7, #4]
 800c256:	f000 f9e5 	bl	800c624 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800c25a:	687b      	ldr	r3, [r7, #4]
 800c25c:	2200      	movs	r2, #0
 800c25e:	771a      	strb	r2, [r3, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
 800c260:	68bb      	ldr	r3, [r7, #8]
 800c262:	f003 0304 	and.w	r3, r3, #4
 800c266:	2b00      	cmp	r3, #0
 800c268:	d020      	beq.n	800c2ac <HAL_TIM_IRQHandler+0xb0>
  {
    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
 800c26a:	68fb      	ldr	r3, [r7, #12]
 800c26c:	f003 0304 	and.w	r3, r3, #4
 800c270:	2b00      	cmp	r3, #0
 800c272:	d01b      	beq.n	800c2ac <HAL_TIM_IRQHandler+0xb0>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
 800c274:	687b      	ldr	r3, [r7, #4]
 800c276:	681b      	ldr	r3, [r3, #0]
 800c278:	f06f 0204 	mvn.w	r2, #4
 800c27c:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 800c27e:	687b      	ldr	r3, [r7, #4]
 800c280:	2202      	movs	r2, #2
 800c282:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 800c284:	687b      	ldr	r3, [r7, #4]
 800c286:	681b      	ldr	r3, [r3, #0]
 800c288:	699b      	ldr	r3, [r3, #24]
 800c28a:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 800c28e:	2b00      	cmp	r3, #0
 800c290:	d003      	beq.n	800c29a <HAL_TIM_IRQHandler+0x9e>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800c292:	6878      	ldr	r0, [r7, #4]
 800c294:	f000 f9bc 	bl	800c610 <HAL_TIM_IC_CaptureCallback>
 800c298:	e005      	b.n	800c2a6 <HAL_TIM_IRQHandler+0xaa>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 800c29a:	6878      	ldr	r0, [r7, #4]
 800c29c:	f000 f9ae 	bl	800c5fc <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 800c2a0:	6878      	ldr	r0, [r7, #4]
 800c2a2:	f000 f9bf 	bl	800c624 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800c2a6:	687b      	ldr	r3, [r7, #4]
 800c2a8:	2200      	movs	r2, #0
 800c2aa:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 3 event */
  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
 800c2ac:	68bb      	ldr	r3, [r7, #8]
 800c2ae:	f003 0308 	and.w	r3, r3, #8
 800c2b2:	2b00      	cmp	r3, #0
 800c2b4:	d020      	beq.n	800c2f8 <HAL_TIM_IRQHandler+0xfc>
  {
    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
 800c2b6:	68fb      	ldr	r3, [r7, #12]
 800c2b8:	f003 0308 	and.w	r3, r3, #8
 800c2bc:	2b00      	cmp	r3, #0
 800c2be:	d01b      	beq.n	800c2f8 <HAL_TIM_IRQHandler+0xfc>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
 800c2c0:	687b      	ldr	r3, [r7, #4]
 800c2c2:	681b      	ldr	r3, [r3, #0]
 800c2c4:	f06f 0208 	mvn.w	r2, #8
 800c2c8:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 800c2ca:	687b      	ldr	r3, [r7, #4]
 800c2cc:	2204      	movs	r2, #4
 800c2ce:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 800c2d0:	687b      	ldr	r3, [r7, #4]
 800c2d2:	681b      	ldr	r3, [r3, #0]
 800c2d4:	69db      	ldr	r3, [r3, #28]
 800c2d6:	f003 0303 	and.w	r3, r3, #3
 800c2da:	2b00      	cmp	r3, #0
 800c2dc:	d003      	beq.n	800c2e6 <HAL_TIM_IRQHandler+0xea>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800c2de:	6878      	ldr	r0, [r7, #4]
 800c2e0:	f000 f996 	bl	800c610 <HAL_TIM_IC_CaptureCallback>
 800c2e4:	e005      	b.n	800c2f2 <HAL_TIM_IRQHandler+0xf6>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 800c2e6:	6878      	ldr	r0, [r7, #4]
 800c2e8:	f000 f988 	bl	800c5fc <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 800c2ec:	6878      	ldr	r0, [r7, #4]
 800c2ee:	f000 f999 	bl	800c624 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800c2f2:	687b      	ldr	r3, [r7, #4]
 800c2f4:	2200      	movs	r2, #0
 800c2f6:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 4 event */
  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
 800c2f8:	68bb      	ldr	r3, [r7, #8]
 800c2fa:	f003 0310 	and.w	r3, r3, #16
 800c2fe:	2b00      	cmp	r3, #0
 800c300:	d020      	beq.n	800c344 <HAL_TIM_IRQHandler+0x148>
  {
    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
 800c302:	68fb      	ldr	r3, [r7, #12]
 800c304:	f003 0310 	and.w	r3, r3, #16
 800c308:	2b00      	cmp	r3, #0
 800c30a:	d01b      	beq.n	800c344 <HAL_TIM_IRQHandler+0x148>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
 800c30c:	687b      	ldr	r3, [r7, #4]
 800c30e:	681b      	ldr	r3, [r3, #0]
 800c310:	f06f 0210 	mvn.w	r2, #16
 800c314:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 800c316:	687b      	ldr	r3, [r7, #4]
 800c318:	2208      	movs	r2, #8
 800c31a:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 800c31c:	687b      	ldr	r3, [r7, #4]
 800c31e:	681b      	ldr	r3, [r3, #0]
 800c320:	69db      	ldr	r3, [r3, #28]
 800c322:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 800c326:	2b00      	cmp	r3, #0
 800c328:	d003      	beq.n	800c332 <HAL_TIM_IRQHandler+0x136>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800c32a:	6878      	ldr	r0, [r7, #4]
 800c32c:	f000 f970 	bl	800c610 <HAL_TIM_IC_CaptureCallback>
 800c330:	e005      	b.n	800c33e <HAL_TIM_IRQHandler+0x142>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 800c332:	6878      	ldr	r0, [r7, #4]
 800c334:	f000 f962 	bl	800c5fc <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 800c338:	6878      	ldr	r0, [r7, #4]
 800c33a:	f000 f973 	bl	800c624 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800c33e:	687b      	ldr	r3, [r7, #4]
 800c340:	2200      	movs	r2, #0
 800c342:	771a      	strb	r2, [r3, #28]
    }
  }
  /* TIM Update event */
  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
 800c344:	68bb      	ldr	r3, [r7, #8]
 800c346:	f003 0301 	and.w	r3, r3, #1
 800c34a:	2b00      	cmp	r3, #0
 800c34c:	d00c      	beq.n	800c368 <HAL_TIM_IRQHandler+0x16c>
  {
    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
 800c34e:	68fb      	ldr	r3, [r7, #12]
 800c350:	f003 0301 	and.w	r3, r3, #1
 800c354:	2b00      	cmp	r3, #0
 800c356:	d007      	beq.n	800c368 <HAL_TIM_IRQHandler+0x16c>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
 800c358:	687b      	ldr	r3, [r7, #4]
 800c35a:	681b      	ldr	r3, [r3, #0]
 800c35c:	f06f 0201 	mvn.w	r2, #1
 800c360:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->PeriodElapsedCallback(htim);
#else
      HAL_TIM_PeriodElapsedCallback(htim);
 800c362:	6878      	ldr	r0, [r7, #4]
 800c364:	f7f5 f882 	bl	800146c <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break input event */
  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
 800c368:	68bb      	ldr	r3, [r7, #8]
 800c36a:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 800c36e:	2b00      	cmp	r3, #0
 800c370:	d104      	bne.n	800c37c <HAL_TIM_IRQHandler+0x180>
      ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
 800c372:	68bb      	ldr	r3, [r7, #8]
 800c374:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
 800c378:	2b00      	cmp	r3, #0
 800c37a:	d00c      	beq.n	800c396 <HAL_TIM_IRQHandler+0x19a>
  {
    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
 800c37c:	68fb      	ldr	r3, [r7, #12]
 800c37e:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 800c382:	2b00      	cmp	r3, #0
 800c384:	d007      	beq.n	800c396 <HAL_TIM_IRQHandler+0x19a>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
 800c386:	687b      	ldr	r3, [r7, #4]
 800c388:	681b      	ldr	r3, [r3, #0]
 800c38a:	f46f 5202 	mvn.w	r2, #8320	@ 0x2080
 800c38e:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->BreakCallback(htim);
#else
      HAL_TIMEx_BreakCallback(htim);
 800c390:	6878      	ldr	r0, [r7, #4]
 800c392:	f000 fb37 	bl	800ca04 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break2 input event */
  if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
 800c396:	68bb      	ldr	r3, [r7, #8]
 800c398:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800c39c:	2b00      	cmp	r3, #0
 800c39e:	d00c      	beq.n	800c3ba <HAL_TIM_IRQHandler+0x1be>
  {
    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
 800c3a0:	68fb      	ldr	r3, [r7, #12]
 800c3a2:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 800c3a6:	2b00      	cmp	r3, #0
 800c3a8:	d007      	beq.n	800c3ba <HAL_TIM_IRQHandler+0x1be>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
 800c3aa:	687b      	ldr	r3, [r7, #4]
 800c3ac:	681b      	ldr	r3, [r3, #0]
 800c3ae:	f46f 7280 	mvn.w	r2, #256	@ 0x100
 800c3b2:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->Break2Callback(htim);
#else
      HAL_TIMEx_Break2Callback(htim);
 800c3b4:	6878      	ldr	r0, [r7, #4]
 800c3b6:	f000 fb2f 	bl	800ca18 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Trigger detection event */
  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
 800c3ba:	68bb      	ldr	r3, [r7, #8]
 800c3bc:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800c3c0:	2b00      	cmp	r3, #0
 800c3c2:	d00c      	beq.n	800c3de <HAL_TIM_IRQHandler+0x1e2>
  {
    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
 800c3c4:	68fb      	ldr	r3, [r7, #12]
 800c3c6:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800c3ca:	2b00      	cmp	r3, #0
 800c3cc:	d007      	beq.n	800c3de <HAL_TIM_IRQHandler+0x1e2>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
 800c3ce:	687b      	ldr	r3, [r7, #4]
 800c3d0:	681b      	ldr	r3, [r3, #0]
 800c3d2:	f06f 0240 	mvn.w	r2, #64	@ 0x40
 800c3d6:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->TriggerCallback(htim);
#else
      HAL_TIM_TriggerCallback(htim);
 800c3d8:	6878      	ldr	r0, [r7, #4]
 800c3da:	f000 f92d 	bl	800c638 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM commutation event */
  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
 800c3de:	68bb      	ldr	r3, [r7, #8]
 800c3e0:	f003 0320 	and.w	r3, r3, #32
 800c3e4:	2b00      	cmp	r3, #0
 800c3e6:	d00c      	beq.n	800c402 <HAL_TIM_IRQHandler+0x206>
  {
    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
 800c3e8:	68fb      	ldr	r3, [r7, #12]
 800c3ea:	f003 0320 	and.w	r3, r3, #32
 800c3ee:	2b00      	cmp	r3, #0
 800c3f0:	d007      	beq.n	800c402 <HAL_TIM_IRQHandler+0x206>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
 800c3f2:	687b      	ldr	r3, [r7, #4]
 800c3f4:	681b      	ldr	r3, [r3, #0]
 800c3f6:	f06f 0220 	mvn.w	r2, #32
 800c3fa:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->CommutationCallback(htim);
#else
      HAL_TIMEx_CommutCallback(htim);
 800c3fc:	6878      	ldr	r0, [r7, #4]
 800c3fe:	f000 faf7 	bl	800c9f0 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
}
 800c402:	bf00      	nop
 800c404:	3710      	adds	r7, #16
 800c406:	46bd      	mov	sp, r7
 800c408:	bd80      	pop	{r7, pc}
	...

0800c40c <HAL_TIM_ConfigClockSource>:
  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
  *         contains the clock source information for the TIM peripheral.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
 800c40c:	b580      	push	{r7, lr}
 800c40e:	b084      	sub	sp, #16
 800c410:	af00      	add	r7, sp, #0
 800c412:	6078      	str	r0, [r7, #4]
 800c414:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef status = HAL_OK;
 800c416:	2300      	movs	r3, #0
 800c418:	73fb      	strb	r3, [r7, #15]
  uint32_t tmpsmcr;

  /* Process Locked */
  __HAL_LOCK(htim);
 800c41a:	687b      	ldr	r3, [r7, #4]
 800c41c:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
 800c420:	2b01      	cmp	r3, #1
 800c422:	d101      	bne.n	800c428 <HAL_TIM_ConfigClockSource+0x1c>
 800c424:	2302      	movs	r3, #2
 800c426:	e0dc      	b.n	800c5e2 <HAL_TIM_ConfigClockSource+0x1d6>
 800c428:	687b      	ldr	r3, [r7, #4]
 800c42a:	2201      	movs	r2, #1
 800c42c:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  htim->State = HAL_TIM_STATE_BUSY;
 800c430:	687b      	ldr	r3, [r7, #4]
 800c432:	2202      	movs	r2, #2
 800c434:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Check the parameters */
  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));

  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
  tmpsmcr = htim->Instance->SMCR;
 800c438:	687b      	ldr	r3, [r7, #4]
 800c43a:	681b      	ldr	r3, [r3, #0]
 800c43c:	689b      	ldr	r3, [r3, #8]
 800c43e:	60bb      	str	r3, [r7, #8]
  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
 800c440:	68ba      	ldr	r2, [r7, #8]
 800c442:	4b6a      	ldr	r3, [pc, #424]	@ (800c5ec <HAL_TIM_ConfigClockSource+0x1e0>)
 800c444:	4013      	ands	r3, r2
 800c446:	60bb      	str	r3, [r7, #8]
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 800c448:	68bb      	ldr	r3, [r7, #8]
 800c44a:	f423 437f 	bic.w	r3, r3, #65280	@ 0xff00
 800c44e:	60bb      	str	r3, [r7, #8]
  htim->Instance->SMCR = tmpsmcr;
 800c450:	687b      	ldr	r3, [r7, #4]
 800c452:	681b      	ldr	r3, [r3, #0]
 800c454:	68ba      	ldr	r2, [r7, #8]
 800c456:	609a      	str	r2, [r3, #8]

  switch (sClockSourceConfig->ClockSource)
 800c458:	683b      	ldr	r3, [r7, #0]
 800c45a:	681b      	ldr	r3, [r3, #0]
 800c45c:	4a64      	ldr	r2, [pc, #400]	@ (800c5f0 <HAL_TIM_ConfigClockSource+0x1e4>)
 800c45e:	4293      	cmp	r3, r2
 800c460:	f000 80a9 	beq.w	800c5b6 <HAL_TIM_ConfigClockSource+0x1aa>
 800c464:	4a62      	ldr	r2, [pc, #392]	@ (800c5f0 <HAL_TIM_ConfigClockSource+0x1e4>)
 800c466:	4293      	cmp	r3, r2
 800c468:	f200 80ae 	bhi.w	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c46c:	4a61      	ldr	r2, [pc, #388]	@ (800c5f4 <HAL_TIM_ConfigClockSource+0x1e8>)
 800c46e:	4293      	cmp	r3, r2
 800c470:	f000 80a1 	beq.w	800c5b6 <HAL_TIM_ConfigClockSource+0x1aa>
 800c474:	4a5f      	ldr	r2, [pc, #380]	@ (800c5f4 <HAL_TIM_ConfigClockSource+0x1e8>)
 800c476:	4293      	cmp	r3, r2
 800c478:	f200 80a6 	bhi.w	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c47c:	4a5e      	ldr	r2, [pc, #376]	@ (800c5f8 <HAL_TIM_ConfigClockSource+0x1ec>)
 800c47e:	4293      	cmp	r3, r2
 800c480:	f000 8099 	beq.w	800c5b6 <HAL_TIM_ConfigClockSource+0x1aa>
 800c484:	4a5c      	ldr	r2, [pc, #368]	@ (800c5f8 <HAL_TIM_ConfigClockSource+0x1ec>)
 800c486:	4293      	cmp	r3, r2
 800c488:	f200 809e 	bhi.w	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c48c:	f1b3 1f10 	cmp.w	r3, #1048592	@ 0x100010
 800c490:	f000 8091 	beq.w	800c5b6 <HAL_TIM_ConfigClockSource+0x1aa>
 800c494:	f1b3 1f10 	cmp.w	r3, #1048592	@ 0x100010
 800c498:	f200 8096 	bhi.w	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c49c:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 800c4a0:	f000 8089 	beq.w	800c5b6 <HAL_TIM_ConfigClockSource+0x1aa>
 800c4a4:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 800c4a8:	f200 808e 	bhi.w	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c4ac:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800c4b0:	d03e      	beq.n	800c530 <HAL_TIM_ConfigClockSource+0x124>
 800c4b2:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800c4b6:	f200 8087 	bhi.w	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c4ba:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800c4be:	f000 8086 	beq.w	800c5ce <HAL_TIM_ConfigClockSource+0x1c2>
 800c4c2:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800c4c6:	d87f      	bhi.n	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c4c8:	2b70      	cmp	r3, #112	@ 0x70
 800c4ca:	d01a      	beq.n	800c502 <HAL_TIM_ConfigClockSource+0xf6>
 800c4cc:	2b70      	cmp	r3, #112	@ 0x70
 800c4ce:	d87b      	bhi.n	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c4d0:	2b60      	cmp	r3, #96	@ 0x60
 800c4d2:	d050      	beq.n	800c576 <HAL_TIM_ConfigClockSource+0x16a>
 800c4d4:	2b60      	cmp	r3, #96	@ 0x60
 800c4d6:	d877      	bhi.n	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c4d8:	2b50      	cmp	r3, #80	@ 0x50
 800c4da:	d03c      	beq.n	800c556 <HAL_TIM_ConfigClockSource+0x14a>
 800c4dc:	2b50      	cmp	r3, #80	@ 0x50
 800c4de:	d873      	bhi.n	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c4e0:	2b40      	cmp	r3, #64	@ 0x40
 800c4e2:	d058      	beq.n	800c596 <HAL_TIM_ConfigClockSource+0x18a>
 800c4e4:	2b40      	cmp	r3, #64	@ 0x40
 800c4e6:	d86f      	bhi.n	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c4e8:	2b30      	cmp	r3, #48	@ 0x30
 800c4ea:	d064      	beq.n	800c5b6 <HAL_TIM_ConfigClockSource+0x1aa>
 800c4ec:	2b30      	cmp	r3, #48	@ 0x30
 800c4ee:	d86b      	bhi.n	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c4f0:	2b20      	cmp	r3, #32
 800c4f2:	d060      	beq.n	800c5b6 <HAL_TIM_ConfigClockSource+0x1aa>
 800c4f4:	2b20      	cmp	r3, #32
 800c4f6:	d867      	bhi.n	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
 800c4f8:	2b00      	cmp	r3, #0
 800c4fa:	d05c      	beq.n	800c5b6 <HAL_TIM_ConfigClockSource+0x1aa>
 800c4fc:	2b10      	cmp	r3, #16
 800c4fe:	d05a      	beq.n	800c5b6 <HAL_TIM_ConfigClockSource+0x1aa>
 800c500:	e062      	b.n	800c5c8 <HAL_TIM_ConfigClockSource+0x1bc>
      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      /* Configure the ETR Clock source */
      TIM_ETR_SetConfig(htim->Instance,
 800c502:	687b      	ldr	r3, [r7, #4]
 800c504:	6818      	ldr	r0, [r3, #0]
                        sClockSourceConfig->ClockPrescaler,
 800c506:	683b      	ldr	r3, [r7, #0]
 800c508:	6899      	ldr	r1, [r3, #8]
                        sClockSourceConfig->ClockPolarity,
 800c50a:	683b      	ldr	r3, [r7, #0]
 800c50c:	685a      	ldr	r2, [r3, #4]
                        sClockSourceConfig->ClockFilter);
 800c50e:	683b      	ldr	r3, [r7, #0]
 800c510:	68db      	ldr	r3, [r3, #12]
      TIM_ETR_SetConfig(htim->Instance,
 800c512:	f000 f9bf 	bl	800c894 <TIM_ETR_SetConfig>

      /* Select the External clock mode1 and the ETRF trigger */
      tmpsmcr = htim->Instance->SMCR;
 800c516:	687b      	ldr	r3, [r7, #4]
 800c518:	681b      	ldr	r3, [r3, #0]
 800c51a:	689b      	ldr	r3, [r3, #8]
 800c51c:	60bb      	str	r3, [r7, #8]
      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
 800c51e:	68bb      	ldr	r3, [r7, #8]
 800c520:	f043 0377 	orr.w	r3, r3, #119	@ 0x77
 800c524:	60bb      	str	r3, [r7, #8]
      /* Write to TIMx SMCR */
      htim->Instance->SMCR = tmpsmcr;
 800c526:	687b      	ldr	r3, [r7, #4]
 800c528:	681b      	ldr	r3, [r3, #0]
 800c52a:	68ba      	ldr	r2, [r7, #8]
 800c52c:	609a      	str	r2, [r3, #8]
      break;
 800c52e:	e04f      	b.n	800c5d0 <HAL_TIM_ConfigClockSource+0x1c4>
      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      /* Configure the ETR Clock source */
      TIM_ETR_SetConfig(htim->Instance,
 800c530:	687b      	ldr	r3, [r7, #4]
 800c532:	6818      	ldr	r0, [r3, #0]
                        sClockSourceConfig->ClockPrescaler,
 800c534:	683b      	ldr	r3, [r7, #0]
 800c536:	6899      	ldr	r1, [r3, #8]
                        sClockSourceConfig->ClockPolarity,
 800c538:	683b      	ldr	r3, [r7, #0]
 800c53a:	685a      	ldr	r2, [r3, #4]
                        sClockSourceConfig->ClockFilter);
 800c53c:	683b      	ldr	r3, [r7, #0]
 800c53e:	68db      	ldr	r3, [r3, #12]
      TIM_ETR_SetConfig(htim->Instance,
 800c540:	f000 f9a8 	bl	800c894 <TIM_ETR_SetConfig>
      /* Enable the External clock mode2 */
      htim->Instance->SMCR |= TIM_SMCR_ECE;
 800c544:	687b      	ldr	r3, [r7, #4]
 800c546:	681b      	ldr	r3, [r3, #0]
 800c548:	689a      	ldr	r2, [r3, #8]
 800c54a:	687b      	ldr	r3, [r7, #4]
 800c54c:	681b      	ldr	r3, [r3, #0]
 800c54e:	f442 4280 	orr.w	r2, r2, #16384	@ 0x4000
 800c552:	609a      	str	r2, [r3, #8]
      break;
 800c554:	e03c      	b.n	800c5d0 <HAL_TIM_ConfigClockSource+0x1c4>

      /* Check TI1 input conditioning related parameters */
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      TIM_TI1_ConfigInputStage(htim->Instance,
 800c556:	687b      	ldr	r3, [r7, #4]
 800c558:	6818      	ldr	r0, [r3, #0]
                               sClockSourceConfig->ClockPolarity,
 800c55a:	683b      	ldr	r3, [r7, #0]
 800c55c:	6859      	ldr	r1, [r3, #4]
                               sClockSourceConfig->ClockFilter);
 800c55e:	683b      	ldr	r3, [r7, #0]
 800c560:	68db      	ldr	r3, [r3, #12]
      TIM_TI1_ConfigInputStage(htim->Instance,
 800c562:	461a      	mov	r2, r3
 800c564:	f000 f918 	bl	800c798 <TIM_TI1_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
 800c568:	687b      	ldr	r3, [r7, #4]
 800c56a:	681b      	ldr	r3, [r3, #0]
 800c56c:	2150      	movs	r1, #80	@ 0x50
 800c56e:	4618      	mov	r0, r3
 800c570:	f000 f972 	bl	800c858 <TIM_ITRx_SetConfig>
      break;
 800c574:	e02c      	b.n	800c5d0 <HAL_TIM_ConfigClockSource+0x1c4>

      /* Check TI2 input conditioning related parameters */
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      TIM_TI2_ConfigInputStage(htim->Instance,
 800c576:	687b      	ldr	r3, [r7, #4]
 800c578:	6818      	ldr	r0, [r3, #0]
                               sClockSourceConfig->ClockPolarity,
 800c57a:	683b      	ldr	r3, [r7, #0]
 800c57c:	6859      	ldr	r1, [r3, #4]
                               sClockSourceConfig->ClockFilter);
 800c57e:	683b      	ldr	r3, [r7, #0]
 800c580:	68db      	ldr	r3, [r3, #12]
      TIM_TI2_ConfigInputStage(htim->Instance,
 800c582:	461a      	mov	r2, r3
 800c584:	f000 f937 	bl	800c7f6 <TIM_TI2_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
 800c588:	687b      	ldr	r3, [r7, #4]
 800c58a:	681b      	ldr	r3, [r3, #0]
 800c58c:	2160      	movs	r1, #96	@ 0x60
 800c58e:	4618      	mov	r0, r3
 800c590:	f000 f962 	bl	800c858 <TIM_ITRx_SetConfig>
      break;
 800c594:	e01c      	b.n	800c5d0 <HAL_TIM_ConfigClockSource+0x1c4>

      /* Check TI1 input conditioning related parameters */
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      TIM_TI1_ConfigInputStage(htim->Instance,
 800c596:	687b      	ldr	r3, [r7, #4]
 800c598:	6818      	ldr	r0, [r3, #0]
                               sClockSourceConfig->ClockPolarity,
 800c59a:	683b      	ldr	r3, [r7, #0]
 800c59c:	6859      	ldr	r1, [r3, #4]
                               sClockSourceConfig->ClockFilter);
 800c59e:	683b      	ldr	r3, [r7, #0]
 800c5a0:	68db      	ldr	r3, [r3, #12]
      TIM_TI1_ConfigInputStage(htim->Instance,
 800c5a2:	461a      	mov	r2, r3
 800c5a4:	f000 f8f8 	bl	800c798 <TIM_TI1_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
 800c5a8:	687b      	ldr	r3, [r7, #4]
 800c5aa:	681b      	ldr	r3, [r3, #0]
 800c5ac:	2140      	movs	r1, #64	@ 0x40
 800c5ae:	4618      	mov	r0, r3
 800c5b0:	f000 f952 	bl	800c858 <TIM_ITRx_SetConfig>
      break;
 800c5b4:	e00c      	b.n	800c5d0 <HAL_TIM_ConfigClockSource+0x1c4>
    case TIM_CLOCKSOURCE_ITR8:
    {
      /* Check whether or not the timer instance supports internal trigger input */
      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));

      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
 800c5b6:	687b      	ldr	r3, [r7, #4]
 800c5b8:	681a      	ldr	r2, [r3, #0]
 800c5ba:	683b      	ldr	r3, [r7, #0]
 800c5bc:	681b      	ldr	r3, [r3, #0]
 800c5be:	4619      	mov	r1, r3
 800c5c0:	4610      	mov	r0, r2
 800c5c2:	f000 f949 	bl	800c858 <TIM_ITRx_SetConfig>
      break;
 800c5c6:	e003      	b.n	800c5d0 <HAL_TIM_ConfigClockSource+0x1c4>
    }

    default:
      status = HAL_ERROR;
 800c5c8:	2301      	movs	r3, #1
 800c5ca:	73fb      	strb	r3, [r7, #15]
      break;
 800c5cc:	e000      	b.n	800c5d0 <HAL_TIM_ConfigClockSource+0x1c4>
      break;
 800c5ce:	bf00      	nop
  }
  htim->State = HAL_TIM_STATE_READY;
 800c5d0:	687b      	ldr	r3, [r7, #4]
 800c5d2:	2201      	movs	r2, #1
 800c5d4:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  __HAL_UNLOCK(htim);
 800c5d8:	687b      	ldr	r3, [r7, #4]
 800c5da:	2200      	movs	r2, #0
 800c5dc:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  return status;
 800c5e0:	7bfb      	ldrb	r3, [r7, #15]
}
 800c5e2:	4618      	mov	r0, r3
 800c5e4:	3710      	adds	r7, #16
 800c5e6:	46bd      	mov	sp, r7
 800c5e8:	bd80      	pop	{r7, pc}
 800c5ea:	bf00      	nop
 800c5ec:	ffceff88 	.word	0xffceff88
 800c5f0:	00100040 	.word	0x00100040
 800c5f4:	00100030 	.word	0x00100030
 800c5f8:	00100020 	.word	0x00100020

0800c5fc <HAL_TIM_OC_DelayElapsedCallback>:
  * @brief  Output Compare callback in non-blocking mode
  * @param  htim TIM OC handle
  * @retval None
  */
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
 800c5fc:	b480      	push	{r7}
 800c5fe:	b083      	sub	sp, #12
 800c600:	af00      	add	r7, sp, #0
 800c602:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
   */
}
 800c604:	bf00      	nop
 800c606:	370c      	adds	r7, #12
 800c608:	46bd      	mov	sp, r7
 800c60a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800c60e:	4770      	bx	lr

0800c610 <HAL_TIM_IC_CaptureCallback>:
  * @brief  Input Capture callback in non-blocking mode
  * @param  htim TIM IC handle
  * @retval None
  */
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
 800c610:	b480      	push	{r7}
 800c612:	b083      	sub	sp, #12
 800c614:	af00      	add	r7, sp, #0
 800c616:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
   */
}
 800c618:	bf00      	nop
 800c61a:	370c      	adds	r7, #12
 800c61c:	46bd      	mov	sp, r7
 800c61e:	f85d 7b04 	ldr.w	r7, [sp], #4
 800c622:	4770      	bx	lr

0800c624 <HAL_TIM_PWM_PulseFinishedCallback>:
  * @brief  PWM Pulse finished callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
 800c624:	b480      	push	{r7}
 800c626:	b083      	sub	sp, #12
 800c628:	af00      	add	r7, sp, #0
 800c62a:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
   */
}
 800c62c:	bf00      	nop
 800c62e:	370c      	adds	r7, #12
 800c630:	46bd      	mov	sp, r7
 800c632:	f85d 7b04 	ldr.w	r7, [sp], #4
 800c636:	4770      	bx	lr

0800c638 <HAL_TIM_TriggerCallback>:
  * @brief  Hall Trigger detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
 800c638:	b480      	push	{r7}
 800c63a:	b083      	sub	sp, #12
 800c63c:	af00      	add	r7, sp, #0
 800c63e:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_TriggerCallback could be implemented in the user file
   */
}
 800c640:	bf00      	nop
 800c642:	370c      	adds	r7, #12
 800c644:	46bd      	mov	sp, r7
 800c646:	f85d 7b04 	ldr.w	r7, [sp], #4
 800c64a:	4770      	bx	lr

0800c64c <TIM_Base_SetConfig>:
  * @param  TIMx TIM peripheral
  * @param  Structure TIM Base configuration structure
  * @retval None
  */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
 800c64c:	b480      	push	{r7}
 800c64e:	b085      	sub	sp, #20
 800c650:	af00      	add	r7, sp, #0
 800c652:	6078      	str	r0, [r7, #4]
 800c654:	6039      	str	r1, [r7, #0]
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;
 800c656:	687b      	ldr	r3, [r7, #4]
 800c658:	681b      	ldr	r3, [r3, #0]
 800c65a:	60fb      	str	r3, [r7, #12]

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 800c65c:	687b      	ldr	r3, [r7, #4]
 800c65e:	4a46      	ldr	r2, [pc, #280]	@ (800c778 <TIM_Base_SetConfig+0x12c>)
 800c660:	4293      	cmp	r3, r2
 800c662:	d013      	beq.n	800c68c <TIM_Base_SetConfig+0x40>
 800c664:	687b      	ldr	r3, [r7, #4]
 800c666:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800c66a:	d00f      	beq.n	800c68c <TIM_Base_SetConfig+0x40>
 800c66c:	687b      	ldr	r3, [r7, #4]
 800c66e:	4a43      	ldr	r2, [pc, #268]	@ (800c77c <TIM_Base_SetConfig+0x130>)
 800c670:	4293      	cmp	r3, r2
 800c672:	d00b      	beq.n	800c68c <TIM_Base_SetConfig+0x40>
 800c674:	687b      	ldr	r3, [r7, #4]
 800c676:	4a42      	ldr	r2, [pc, #264]	@ (800c780 <TIM_Base_SetConfig+0x134>)
 800c678:	4293      	cmp	r3, r2
 800c67a:	d007      	beq.n	800c68c <TIM_Base_SetConfig+0x40>
 800c67c:	687b      	ldr	r3, [r7, #4]
 800c67e:	4a41      	ldr	r2, [pc, #260]	@ (800c784 <TIM_Base_SetConfig+0x138>)
 800c680:	4293      	cmp	r3, r2
 800c682:	d003      	beq.n	800c68c <TIM_Base_SetConfig+0x40>
 800c684:	687b      	ldr	r3, [r7, #4]
 800c686:	4a40      	ldr	r2, [pc, #256]	@ (800c788 <TIM_Base_SetConfig+0x13c>)
 800c688:	4293      	cmp	r3, r2
 800c68a:	d108      	bne.n	800c69e <TIM_Base_SetConfig+0x52>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 800c68c:	68fb      	ldr	r3, [r7, #12]
 800c68e:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
 800c692:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= Structure->CounterMode;
 800c694:	683b      	ldr	r3, [r7, #0]
 800c696:	685b      	ldr	r3, [r3, #4]
 800c698:	68fa      	ldr	r2, [r7, #12]
 800c69a:	4313      	orrs	r3, r2
 800c69c:	60fb      	str	r3, [r7, #12]
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 800c69e:	687b      	ldr	r3, [r7, #4]
 800c6a0:	4a35      	ldr	r2, [pc, #212]	@ (800c778 <TIM_Base_SetConfig+0x12c>)
 800c6a2:	4293      	cmp	r3, r2
 800c6a4:	d01f      	beq.n	800c6e6 <TIM_Base_SetConfig+0x9a>
 800c6a6:	687b      	ldr	r3, [r7, #4]
 800c6a8:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800c6ac:	d01b      	beq.n	800c6e6 <TIM_Base_SetConfig+0x9a>
 800c6ae:	687b      	ldr	r3, [r7, #4]
 800c6b0:	4a32      	ldr	r2, [pc, #200]	@ (800c77c <TIM_Base_SetConfig+0x130>)
 800c6b2:	4293      	cmp	r3, r2
 800c6b4:	d017      	beq.n	800c6e6 <TIM_Base_SetConfig+0x9a>
 800c6b6:	687b      	ldr	r3, [r7, #4]
 800c6b8:	4a31      	ldr	r2, [pc, #196]	@ (800c780 <TIM_Base_SetConfig+0x134>)
 800c6ba:	4293      	cmp	r3, r2
 800c6bc:	d013      	beq.n	800c6e6 <TIM_Base_SetConfig+0x9a>
 800c6be:	687b      	ldr	r3, [r7, #4]
 800c6c0:	4a30      	ldr	r2, [pc, #192]	@ (800c784 <TIM_Base_SetConfig+0x138>)
 800c6c2:	4293      	cmp	r3, r2
 800c6c4:	d00f      	beq.n	800c6e6 <TIM_Base_SetConfig+0x9a>
 800c6c6:	687b      	ldr	r3, [r7, #4]
 800c6c8:	4a2f      	ldr	r2, [pc, #188]	@ (800c788 <TIM_Base_SetConfig+0x13c>)
 800c6ca:	4293      	cmp	r3, r2
 800c6cc:	d00b      	beq.n	800c6e6 <TIM_Base_SetConfig+0x9a>
 800c6ce:	687b      	ldr	r3, [r7, #4]
 800c6d0:	4a2e      	ldr	r2, [pc, #184]	@ (800c78c <TIM_Base_SetConfig+0x140>)
 800c6d2:	4293      	cmp	r3, r2
 800c6d4:	d007      	beq.n	800c6e6 <TIM_Base_SetConfig+0x9a>
 800c6d6:	687b      	ldr	r3, [r7, #4]
 800c6d8:	4a2d      	ldr	r2, [pc, #180]	@ (800c790 <TIM_Base_SetConfig+0x144>)
 800c6da:	4293      	cmp	r3, r2
 800c6dc:	d003      	beq.n	800c6e6 <TIM_Base_SetConfig+0x9a>
 800c6de:	687b      	ldr	r3, [r7, #4]
 800c6e0:	4a2c      	ldr	r2, [pc, #176]	@ (800c794 <TIM_Base_SetConfig+0x148>)
 800c6e2:	4293      	cmp	r3, r2
 800c6e4:	d108      	bne.n	800c6f8 <TIM_Base_SetConfig+0xac>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
 800c6e6:	68fb      	ldr	r3, [r7, #12]
 800c6e8:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 800c6ec:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 800c6ee:	683b      	ldr	r3, [r7, #0]
 800c6f0:	68db      	ldr	r3, [r3, #12]
 800c6f2:	68fa      	ldr	r2, [r7, #12]
 800c6f4:	4313      	orrs	r3, r2
 800c6f6:	60fb      	str	r3, [r7, #12]
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 800c6f8:	68fb      	ldr	r3, [r7, #12]
 800c6fa:	f023 0280 	bic.w	r2, r3, #128	@ 0x80
 800c6fe:	683b      	ldr	r3, [r7, #0]
 800c700:	695b      	ldr	r3, [r3, #20]
 800c702:	4313      	orrs	r3, r2
 800c704:	60fb      	str	r3, [r7, #12]

  TIMx->CR1 = tmpcr1;
 800c706:	687b      	ldr	r3, [r7, #4]
 800c708:	68fa      	ldr	r2, [r7, #12]
 800c70a:	601a      	str	r2, [r3, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 800c70c:	683b      	ldr	r3, [r7, #0]
 800c70e:	689a      	ldr	r2, [r3, #8]
 800c710:	687b      	ldr	r3, [r7, #4]
 800c712:	62da      	str	r2, [r3, #44]	@ 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 800c714:	683b      	ldr	r3, [r7, #0]
 800c716:	681a      	ldr	r2, [r3, #0]
 800c718:	687b      	ldr	r3, [r7, #4]
 800c71a:	629a      	str	r2, [r3, #40]	@ 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 800c71c:	687b      	ldr	r3, [r7, #4]
 800c71e:	4a16      	ldr	r2, [pc, #88]	@ (800c778 <TIM_Base_SetConfig+0x12c>)
 800c720:	4293      	cmp	r3, r2
 800c722:	d00f      	beq.n	800c744 <TIM_Base_SetConfig+0xf8>
 800c724:	687b      	ldr	r3, [r7, #4]
 800c726:	4a18      	ldr	r2, [pc, #96]	@ (800c788 <TIM_Base_SetConfig+0x13c>)
 800c728:	4293      	cmp	r3, r2
 800c72a:	d00b      	beq.n	800c744 <TIM_Base_SetConfig+0xf8>
 800c72c:	687b      	ldr	r3, [r7, #4]
 800c72e:	4a17      	ldr	r2, [pc, #92]	@ (800c78c <TIM_Base_SetConfig+0x140>)
 800c730:	4293      	cmp	r3, r2
 800c732:	d007      	beq.n	800c744 <TIM_Base_SetConfig+0xf8>
 800c734:	687b      	ldr	r3, [r7, #4]
 800c736:	4a16      	ldr	r2, [pc, #88]	@ (800c790 <TIM_Base_SetConfig+0x144>)
 800c738:	4293      	cmp	r3, r2
 800c73a:	d003      	beq.n	800c744 <TIM_Base_SetConfig+0xf8>
 800c73c:	687b      	ldr	r3, [r7, #4]
 800c73e:	4a15      	ldr	r2, [pc, #84]	@ (800c794 <TIM_Base_SetConfig+0x148>)
 800c740:	4293      	cmp	r3, r2
 800c742:	d103      	bne.n	800c74c <TIM_Base_SetConfig+0x100>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 800c744:	683b      	ldr	r3, [r7, #0]
 800c746:	691a      	ldr	r2, [r3, #16]
 800c748:	687b      	ldr	r3, [r7, #4]
 800c74a:	631a      	str	r2, [r3, #48]	@ 0x30
  }

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 800c74c:	687b      	ldr	r3, [r7, #4]
 800c74e:	2201      	movs	r2, #1
 800c750:	615a      	str	r2, [r3, #20]

  /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
  if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
 800c752:	687b      	ldr	r3, [r7, #4]
 800c754:	691b      	ldr	r3, [r3, #16]
 800c756:	f003 0301 	and.w	r3, r3, #1
 800c75a:	2b01      	cmp	r3, #1
 800c75c:	d105      	bne.n	800c76a <TIM_Base_SetConfig+0x11e>
  {
    /* Clear the update flag */
    CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
 800c75e:	687b      	ldr	r3, [r7, #4]
 800c760:	691b      	ldr	r3, [r3, #16]
 800c762:	f023 0201 	bic.w	r2, r3, #1
 800c766:	687b      	ldr	r3, [r7, #4]
 800c768:	611a      	str	r2, [r3, #16]
  }
}
 800c76a:	bf00      	nop
 800c76c:	3714      	adds	r7, #20
 800c76e:	46bd      	mov	sp, r7
 800c770:	f85d 7b04 	ldr.w	r7, [sp], #4
 800c774:	4770      	bx	lr
 800c776:	bf00      	nop
 800c778:	40010000 	.word	0x40010000
 800c77c:	40000400 	.word	0x40000400
 800c780:	40000800 	.word	0x40000800
 800c784:	40000c00 	.word	0x40000c00
 800c788:	40010400 	.word	0x40010400
 800c78c:	40014000 	.word	0x40014000
 800c790:	40014400 	.word	0x40014400
 800c794:	40014800 	.word	0x40014800

0800c798 <TIM_TI1_ConfigInputStage>:
  * @param  TIM_ICFilter Specifies the Input Capture Filter.
  *          This parameter must be a value between 0x00 and 0x0F.
  * @retval None
  */
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
 800c798:	b480      	push	{r7}
 800c79a:	b087      	sub	sp, #28
 800c79c:	af00      	add	r7, sp, #0
 800c79e:	60f8      	str	r0, [r7, #12]
 800c7a0:	60b9      	str	r1, [r7, #8]
 800c7a2:	607a      	str	r2, [r7, #4]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 1: Reset the CC1E Bit */
  tmpccer = TIMx->CCER;
 800c7a4:	68fb      	ldr	r3, [r7, #12]
 800c7a6:	6a1b      	ldr	r3, [r3, #32]
 800c7a8:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC1E;
 800c7aa:	68fb      	ldr	r3, [r7, #12]
 800c7ac:	6a1b      	ldr	r3, [r3, #32]
 800c7ae:	f023 0201 	bic.w	r2, r3, #1
 800c7b2:	68fb      	ldr	r3, [r7, #12]
 800c7b4:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 800c7b6:	68fb      	ldr	r3, [r7, #12]
 800c7b8:	699b      	ldr	r3, [r3, #24]
 800c7ba:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC1F;
 800c7bc:	693b      	ldr	r3, [r7, #16]
 800c7be:	f023 03f0 	bic.w	r3, r3, #240	@ 0xf0
 800c7c2:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= (TIM_ICFilter << 4U);
 800c7c4:	687b      	ldr	r3, [r7, #4]
 800c7c6:	011b      	lsls	r3, r3, #4
 800c7c8:	693a      	ldr	r2, [r7, #16]
 800c7ca:	4313      	orrs	r3, r2
 800c7cc:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC1E Bit */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
 800c7ce:	697b      	ldr	r3, [r7, #20]
 800c7d0:	f023 030a 	bic.w	r3, r3, #10
 800c7d4:	617b      	str	r3, [r7, #20]
  tmpccer |= TIM_ICPolarity;
 800c7d6:	697a      	ldr	r2, [r7, #20]
 800c7d8:	68bb      	ldr	r3, [r7, #8]
 800c7da:	4313      	orrs	r3, r2
 800c7dc:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
 800c7de:	68fb      	ldr	r3, [r7, #12]
 800c7e0:	693a      	ldr	r2, [r7, #16]
 800c7e2:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 800c7e4:	68fb      	ldr	r3, [r7, #12]
 800c7e6:	697a      	ldr	r2, [r7, #20]
 800c7e8:	621a      	str	r2, [r3, #32]
}
 800c7ea:	bf00      	nop
 800c7ec:	371c      	adds	r7, #28
 800c7ee:	46bd      	mov	sp, r7
 800c7f0:	f85d 7b04 	ldr.w	r7, [sp], #4
 800c7f4:	4770      	bx	lr

0800c7f6 <TIM_TI2_ConfigInputStage>:
  * @param  TIM_ICFilter Specifies the Input Capture Filter.
  *          This parameter must be a value between 0x00 and 0x0F.
  * @retval None
  */
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
 800c7f6:	b480      	push	{r7}
 800c7f8:	b087      	sub	sp, #28
 800c7fa:	af00      	add	r7, sp, #0
 800c7fc:	60f8      	str	r0, [r7, #12]
 800c7fe:	60b9      	str	r1, [r7, #8]
 800c800:	607a      	str	r2, [r7, #4]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 2: Reset the CC2E Bit */
  tmpccer = TIMx->CCER;
 800c802:	68fb      	ldr	r3, [r7, #12]
 800c804:	6a1b      	ldr	r3, [r3, #32]
 800c806:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC2E;
 800c808:	68fb      	ldr	r3, [r7, #12]
 800c80a:	6a1b      	ldr	r3, [r3, #32]
 800c80c:	f023 0210 	bic.w	r2, r3, #16
 800c810:	68fb      	ldr	r3, [r7, #12]
 800c812:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 800c814:	68fb      	ldr	r3, [r7, #12]
 800c816:	699b      	ldr	r3, [r3, #24]
 800c818:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC2F;
 800c81a:	693b      	ldr	r3, [r7, #16]
 800c81c:	f423 4370 	bic.w	r3, r3, #61440	@ 0xf000
 800c820:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= (TIM_ICFilter << 12U);
 800c822:	687b      	ldr	r3, [r7, #4]
 800c824:	031b      	lsls	r3, r3, #12
 800c826:	693a      	ldr	r2, [r7, #16]
 800c828:	4313      	orrs	r3, r2
 800c82a:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC2E Bit */
  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
 800c82c:	697b      	ldr	r3, [r7, #20]
 800c82e:	f023 03a0 	bic.w	r3, r3, #160	@ 0xa0
 800c832:	617b      	str	r3, [r7, #20]
  tmpccer |= (TIM_ICPolarity << 4U);
 800c834:	68bb      	ldr	r3, [r7, #8]
 800c836:	011b      	lsls	r3, r3, #4
 800c838:	697a      	ldr	r2, [r7, #20]
 800c83a:	4313      	orrs	r3, r2
 800c83c:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1 ;
 800c83e:	68fb      	ldr	r3, [r7, #12]
 800c840:	693a      	ldr	r2, [r7, #16]
 800c842:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 800c844:	68fb      	ldr	r3, [r7, #12]
 800c846:	697a      	ldr	r2, [r7, #20]
 800c848:	621a      	str	r2, [r3, #32]
}
 800c84a:	bf00      	nop
 800c84c:	371c      	adds	r7, #28
 800c84e:	46bd      	mov	sp, r7
 800c850:	f85d 7b04 	ldr.w	r7, [sp], #4
 800c854:	4770      	bx	lr
	...

0800c858 <TIM_ITRx_SetConfig>:
  *       (*)  Value not defined in all devices.
  *
  * @retval None
  */
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
 800c858:	b480      	push	{r7}
 800c85a:	b085      	sub	sp, #20
 800c85c:	af00      	add	r7, sp, #0
 800c85e:	6078      	str	r0, [r7, #4]
 800c860:	6039      	str	r1, [r7, #0]
  uint32_t tmpsmcr;

  /* Get the TIMx SMCR register value */
  tmpsmcr = TIMx->SMCR;
 800c862:	687b      	ldr	r3, [r7, #4]
 800c864:	689b      	ldr	r3, [r3, #8]
 800c866:	60fb      	str	r3, [r7, #12]
  /* Reset the TS Bits */
  tmpsmcr &= ~TIM_SMCR_TS;
 800c868:	68fa      	ldr	r2, [r7, #12]
 800c86a:	4b09      	ldr	r3, [pc, #36]	@ (800c890 <TIM_ITRx_SetConfig+0x38>)
 800c86c:	4013      	ands	r3, r2
 800c86e:	60fb      	str	r3, [r7, #12]
  /* Set the Input Trigger source and the slave mode*/
  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
 800c870:	683a      	ldr	r2, [r7, #0]
 800c872:	68fb      	ldr	r3, [r7, #12]
 800c874:	4313      	orrs	r3, r2
 800c876:	f043 0307 	orr.w	r3, r3, #7
 800c87a:	60fb      	str	r3, [r7, #12]
  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
 800c87c:	687b      	ldr	r3, [r7, #4]
 800c87e:	68fa      	ldr	r2, [r7, #12]
 800c880:	609a      	str	r2, [r3, #8]
}
 800c882:	bf00      	nop
 800c884:	3714      	adds	r7, #20
 800c886:	46bd      	mov	sp, r7
 800c888:	f85d 7b04 	ldr.w	r7, [sp], #4
 800c88c:	4770      	bx	lr
 800c88e:	bf00      	nop
 800c890:	ffcfff8f 	.word	0xffcfff8f

0800c894 <TIM_ETR_SetConfig>:
  *          This parameter must be a value between 0x00 and 0x0F
  * @retval None
  */
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
 800c894:	b480      	push	{r7}
 800c896:	b087      	sub	sp, #28
 800c898:	af00      	add	r7, sp, #0
 800c89a:	60f8      	str	r0, [r7, #12]
 800c89c:	60b9      	str	r1, [r7, #8]
 800c89e:	607a      	str	r2, [r7, #4]
 800c8a0:	603b      	str	r3, [r7, #0]
  uint32_t tmpsmcr;

  tmpsmcr = TIMx->SMCR;
 800c8a2:	68fb      	ldr	r3, [r7, #12]
 800c8a4:	689b      	ldr	r3, [r3, #8]
 800c8a6:	617b      	str	r3, [r7, #20]

  /* Reset the ETR Bits */
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 800c8a8:	697b      	ldr	r3, [r7, #20]
 800c8aa:	f423 437f 	bic.w	r3, r3, #65280	@ 0xff00
 800c8ae:	617b      	str	r3, [r7, #20]

  /* Set the Prescaler, the Filter value and the Polarity */
  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
 800c8b0:	683b      	ldr	r3, [r7, #0]
 800c8b2:	021a      	lsls	r2, r3, #8
 800c8b4:	687b      	ldr	r3, [r7, #4]
 800c8b6:	431a      	orrs	r2, r3
 800c8b8:	68bb      	ldr	r3, [r7, #8]
 800c8ba:	4313      	orrs	r3, r2
 800c8bc:	697a      	ldr	r2, [r7, #20]
 800c8be:	4313      	orrs	r3, r2
 800c8c0:	617b      	str	r3, [r7, #20]

  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
 800c8c2:	68fb      	ldr	r3, [r7, #12]
 800c8c4:	697a      	ldr	r2, [r7, #20]
 800c8c6:	609a      	str	r2, [r3, #8]
}
 800c8c8:	bf00      	nop
 800c8ca:	371c      	adds	r7, #28
 800c8cc:	46bd      	mov	sp, r7
 800c8ce:	f85d 7b04 	ldr.w	r7, [sp], #4
 800c8d2:	4770      	bx	lr

0800c8d4 <HAL_TIMEx_MasterConfigSynchronization>:
  *         mode.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
{
 800c8d4:	b480      	push	{r7}
 800c8d6:	b085      	sub	sp, #20
 800c8d8:	af00      	add	r7, sp, #0
 800c8da:	6078      	str	r0, [r7, #4]
 800c8dc:	6039      	str	r1, [r7, #0]
  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  /* Check input state */
  __HAL_LOCK(htim);
 800c8de:	687b      	ldr	r3, [r7, #4]
 800c8e0:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
 800c8e4:	2b01      	cmp	r3, #1
 800c8e6:	d101      	bne.n	800c8ec <HAL_TIMEx_MasterConfigSynchronization+0x18>
 800c8e8:	2302      	movs	r3, #2
 800c8ea:	e06d      	b.n	800c9c8 <HAL_TIMEx_MasterConfigSynchronization+0xf4>
 800c8ec:	687b      	ldr	r3, [r7, #4]
 800c8ee:	2201      	movs	r2, #1
 800c8f0:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  /* Change the handler state */
  htim->State = HAL_TIM_STATE_BUSY;
 800c8f4:	687b      	ldr	r3, [r7, #4]
 800c8f6:	2202      	movs	r2, #2
 800c8f8:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Get the TIMx CR2 register value */
  tmpcr2 = htim->Instance->CR2;
 800c8fc:	687b      	ldr	r3, [r7, #4]
 800c8fe:	681b      	ldr	r3, [r3, #0]
 800c900:	685b      	ldr	r3, [r3, #4]
 800c902:	60fb      	str	r3, [r7, #12]

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;
 800c904:	687b      	ldr	r3, [r7, #4]
 800c906:	681b      	ldr	r3, [r3, #0]
 800c908:	689b      	ldr	r3, [r3, #8]
 800c90a:	60bb      	str	r3, [r7, #8]

  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
 800c90c:	687b      	ldr	r3, [r7, #4]
 800c90e:	681b      	ldr	r3, [r3, #0]
 800c910:	4a30      	ldr	r2, [pc, #192]	@ (800c9d4 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
 800c912:	4293      	cmp	r3, r2
 800c914:	d004      	beq.n	800c920 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
 800c916:	687b      	ldr	r3, [r7, #4]
 800c918:	681b      	ldr	r3, [r3, #0]
 800c91a:	4a2f      	ldr	r2, [pc, #188]	@ (800c9d8 <HAL_TIMEx_MasterConfigSynchronization+0x104>)
 800c91c:	4293      	cmp	r3, r2
 800c91e:	d108      	bne.n	800c932 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
  {
    /* Check the parameters */
    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));

    /* Clear the MMS2 bits */
    tmpcr2 &= ~TIM_CR2_MMS2;
 800c920:	68fb      	ldr	r3, [r7, #12]
 800c922:	f423 0370 	bic.w	r3, r3, #15728640	@ 0xf00000
 800c926:	60fb      	str	r3, [r7, #12]
    /* Select the TRGO2 source*/
    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
 800c928:	683b      	ldr	r3, [r7, #0]
 800c92a:	685b      	ldr	r3, [r3, #4]
 800c92c:	68fa      	ldr	r2, [r7, #12]
 800c92e:	4313      	orrs	r3, r2
 800c930:	60fb      	str	r3, [r7, #12]
  }

  /* Reset the MMS Bits */
  tmpcr2 &= ~TIM_CR2_MMS;
 800c932:	68fb      	ldr	r3, [r7, #12]
 800c934:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
 800c938:	60fb      	str	r3, [r7, #12]
  /* Select the TRGO source */
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 800c93a:	683b      	ldr	r3, [r7, #0]
 800c93c:	681b      	ldr	r3, [r3, #0]
 800c93e:	68fa      	ldr	r2, [r7, #12]
 800c940:	4313      	orrs	r3, r2
 800c942:	60fb      	str	r3, [r7, #12]

  /* Update TIMx CR2 */
  htim->Instance->CR2 = tmpcr2;
 800c944:	687b      	ldr	r3, [r7, #4]
 800c946:	681b      	ldr	r3, [r3, #0]
 800c948:	68fa      	ldr	r2, [r7, #12]
 800c94a:	605a      	str	r2, [r3, #4]

  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 800c94c:	687b      	ldr	r3, [r7, #4]
 800c94e:	681b      	ldr	r3, [r3, #0]
 800c950:	4a20      	ldr	r2, [pc, #128]	@ (800c9d4 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
 800c952:	4293      	cmp	r3, r2
 800c954:	d022      	beq.n	800c99c <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 800c956:	687b      	ldr	r3, [r7, #4]
 800c958:	681b      	ldr	r3, [r3, #0]
 800c95a:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800c95e:	d01d      	beq.n	800c99c <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 800c960:	687b      	ldr	r3, [r7, #4]
 800c962:	681b      	ldr	r3, [r3, #0]
 800c964:	4a1d      	ldr	r2, [pc, #116]	@ (800c9dc <HAL_TIMEx_MasterConfigSynchronization+0x108>)
 800c966:	4293      	cmp	r3, r2
 800c968:	d018      	beq.n	800c99c <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 800c96a:	687b      	ldr	r3, [r7, #4]
 800c96c:	681b      	ldr	r3, [r3, #0]
 800c96e:	4a1c      	ldr	r2, [pc, #112]	@ (800c9e0 <HAL_TIMEx_MasterConfigSynchronization+0x10c>)
 800c970:	4293      	cmp	r3, r2
 800c972:	d013      	beq.n	800c99c <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 800c974:	687b      	ldr	r3, [r7, #4]
 800c976:	681b      	ldr	r3, [r3, #0]
 800c978:	4a1a      	ldr	r2, [pc, #104]	@ (800c9e4 <HAL_TIMEx_MasterConfigSynchronization+0x110>)
 800c97a:	4293      	cmp	r3, r2
 800c97c:	d00e      	beq.n	800c99c <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 800c97e:	687b      	ldr	r3, [r7, #4]
 800c980:	681b      	ldr	r3, [r3, #0]
 800c982:	4a15      	ldr	r2, [pc, #84]	@ (800c9d8 <HAL_TIMEx_MasterConfigSynchronization+0x104>)
 800c984:	4293      	cmp	r3, r2
 800c986:	d009      	beq.n	800c99c <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 800c988:	687b      	ldr	r3, [r7, #4]
 800c98a:	681b      	ldr	r3, [r3, #0]
 800c98c:	4a16      	ldr	r2, [pc, #88]	@ (800c9e8 <HAL_TIMEx_MasterConfigSynchronization+0x114>)
 800c98e:	4293      	cmp	r3, r2
 800c990:	d004      	beq.n	800c99c <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 800c992:	687b      	ldr	r3, [r7, #4]
 800c994:	681b      	ldr	r3, [r3, #0]
 800c996:	4a15      	ldr	r2, [pc, #84]	@ (800c9ec <HAL_TIMEx_MasterConfigSynchronization+0x118>)
 800c998:	4293      	cmp	r3, r2
 800c99a:	d10c      	bne.n	800c9b6 <HAL_TIMEx_MasterConfigSynchronization+0xe2>
  {
    /* Reset the MSM Bit */
    tmpsmcr &= ~TIM_SMCR_MSM;
 800c99c:	68bb      	ldr	r3, [r7, #8]
 800c99e:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 800c9a2:	60bb      	str	r3, [r7, #8]
    /* Set master mode */
    tmpsmcr |= sMasterConfig->MasterSlaveMode;
 800c9a4:	683b      	ldr	r3, [r7, #0]
 800c9a6:	689b      	ldr	r3, [r3, #8]
 800c9a8:	68ba      	ldr	r2, [r7, #8]
 800c9aa:	4313      	orrs	r3, r2
 800c9ac:	60bb      	str	r3, [r7, #8]

    /* Update TIMx SMCR */
    htim->Instance->SMCR = tmpsmcr;
 800c9ae:	687b      	ldr	r3, [r7, #4]
 800c9b0:	681b      	ldr	r3, [r3, #0]
 800c9b2:	68ba      	ldr	r2, [r7, #8]
 800c9b4:	609a      	str	r2, [r3, #8]
  }

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;
 800c9b6:	687b      	ldr	r3, [r7, #4]
 800c9b8:	2201      	movs	r2, #1
 800c9ba:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  __HAL_UNLOCK(htim);
 800c9be:	687b      	ldr	r3, [r7, #4]
 800c9c0:	2200      	movs	r2, #0
 800c9c2:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  return HAL_OK;
 800c9c6:	2300      	movs	r3, #0
}
 800c9c8:	4618      	mov	r0, r3
 800c9ca:	3714      	adds	r7, #20
 800c9cc:	46bd      	mov	sp, r7
 800c9ce:	f85d 7b04 	ldr.w	r7, [sp], #4
 800c9d2:	4770      	bx	lr
 800c9d4:	40010000 	.word	0x40010000
 800c9d8:	40010400 	.word	0x40010400
 800c9dc:	40000400 	.word	0x40000400
 800c9e0:	40000800 	.word	0x40000800
 800c9e4:	40000c00 	.word	0x40000c00
 800c9e8:	40001800 	.word	0x40001800
 800c9ec:	40014000 	.word	0x40014000

0800c9f0 <HAL_TIMEx_CommutCallback>:
  * @brief  Commutation callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
 800c9f0:	b480      	push	{r7}
 800c9f2:	b083      	sub	sp, #12
 800c9f4:	af00      	add	r7, sp, #0
 800c9f6:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_CommutCallback could be implemented in the user file
   */
}
 800c9f8:	bf00      	nop
 800c9fa:	370c      	adds	r7, #12
 800c9fc:	46bd      	mov	sp, r7
 800c9fe:	f85d 7b04 	ldr.w	r7, [sp], #4
 800ca02:	4770      	bx	lr

0800ca04 <HAL_TIMEx_BreakCallback>:
  * @brief  Break detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 800ca04:	b480      	push	{r7}
 800ca06:	b083      	sub	sp, #12
 800ca08:	af00      	add	r7, sp, #0
 800ca0a:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_BreakCallback could be implemented in the user file
   */
}
 800ca0c:	bf00      	nop
 800ca0e:	370c      	adds	r7, #12
 800ca10:	46bd      	mov	sp, r7
 800ca12:	f85d 7b04 	ldr.w	r7, [sp], #4
 800ca16:	4770      	bx	lr

0800ca18 <HAL_TIMEx_Break2Callback>:
  * @brief  Break2 detection callback in non blocking mode
  * @param  htim: TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
 800ca18:	b480      	push	{r7}
 800ca1a:	b083      	sub	sp, #12
 800ca1c:	af00      	add	r7, sp, #0
 800ca1e:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_TIMEx_Break2Callback could be implemented in the user file
   */
}
 800ca20:	bf00      	nop
 800ca22:	370c      	adds	r7, #12
 800ca24:	46bd      	mov	sp, r7
 800ca26:	f85d 7b04 	ldr.w	r7, [sp], #4
 800ca2a:	4770      	bx	lr

0800ca2c <HAL_UART_Init>:
  *        parameters in the UART_InitTypeDef and initialize the associated handle.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
 800ca2c:	b580      	push	{r7, lr}
 800ca2e:	b082      	sub	sp, #8
 800ca30:	af00      	add	r7, sp, #0
 800ca32:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 800ca34:	687b      	ldr	r3, [r7, #4]
 800ca36:	2b00      	cmp	r3, #0
 800ca38:	d101      	bne.n	800ca3e <HAL_UART_Init+0x12>
  {
    return HAL_ERROR;
 800ca3a:	2301      	movs	r3, #1
 800ca3c:	e042      	b.n	800cac4 <HAL_UART_Init+0x98>
  {
    /* Check the parameters */
    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
  }

  if (huart->gState == HAL_UART_STATE_RESET)
 800ca3e:	687b      	ldr	r3, [r7, #4]
 800ca40:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800ca44:	2b00      	cmp	r3, #0
 800ca46:	d106      	bne.n	800ca56 <HAL_UART_Init+0x2a>
  {
    /* Allocate lock resource and initialize it */
    huart->Lock = HAL_UNLOCKED;
 800ca48:	687b      	ldr	r3, [r7, #4]
 800ca4a:	2200      	movs	r2, #0
 800ca4c:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

    /* Init the low level hardware */
    huart->MspInitCallback(huart);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_UART_MspInit(huart);
 800ca50:	6878      	ldr	r0, [r7, #4]
 800ca52:	f7f5 fca5 	bl	80023a0 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  }

  huart->gState = HAL_UART_STATE_BUSY;
 800ca56:	687b      	ldr	r3, [r7, #4]
 800ca58:	2224      	movs	r2, #36	@ 0x24
 800ca5a:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  __HAL_UART_DISABLE(huart);
 800ca5e:	687b      	ldr	r3, [r7, #4]
 800ca60:	681b      	ldr	r3, [r3, #0]
 800ca62:	681a      	ldr	r2, [r3, #0]
 800ca64:	687b      	ldr	r3, [r7, #4]
 800ca66:	681b      	ldr	r3, [r3, #0]
 800ca68:	f022 0201 	bic.w	r2, r2, #1
 800ca6c:	601a      	str	r2, [r3, #0]

  /* Perform advanced settings configuration */
  /* For some items, configuration requires to be done prior TE and RE bits are set */
  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
 800ca6e:	687b      	ldr	r3, [r7, #4]
 800ca70:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800ca72:	2b00      	cmp	r3, #0
 800ca74:	d002      	beq.n	800ca7c <HAL_UART_Init+0x50>
  {
    UART_AdvFeatureConfig(huart);
 800ca76:	6878      	ldr	r0, [r7, #4]
 800ca78:	f001 f9e8 	bl	800de4c <UART_AdvFeatureConfig>
  }

  /* Set the UART Communication parameters */
  if (UART_SetConfig(huart) == HAL_ERROR)
 800ca7c:	6878      	ldr	r0, [r7, #4]
 800ca7e:	f000 fc7d 	bl	800d37c <UART_SetConfig>
 800ca82:	4603      	mov	r3, r0
 800ca84:	2b01      	cmp	r3, #1
 800ca86:	d101      	bne.n	800ca8c <HAL_UART_Init+0x60>
  {
    return HAL_ERROR;
 800ca88:	2301      	movs	r3, #1
 800ca8a:	e01b      	b.n	800cac4 <HAL_UART_Init+0x98>
  }

  /* In asynchronous mode, the following bits must be kept cleared:
  - LINEN and CLKEN bits in the USART_CR2 register,
  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 800ca8c:	687b      	ldr	r3, [r7, #4]
 800ca8e:	681b      	ldr	r3, [r3, #0]
 800ca90:	685a      	ldr	r2, [r3, #4]
 800ca92:	687b      	ldr	r3, [r7, #4]
 800ca94:	681b      	ldr	r3, [r3, #0]
 800ca96:	f422 4290 	bic.w	r2, r2, #18432	@ 0x4800
 800ca9a:	605a      	str	r2, [r3, #4]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 800ca9c:	687b      	ldr	r3, [r7, #4]
 800ca9e:	681b      	ldr	r3, [r3, #0]
 800caa0:	689a      	ldr	r2, [r3, #8]
 800caa2:	687b      	ldr	r3, [r7, #4]
 800caa4:	681b      	ldr	r3, [r3, #0]
 800caa6:	f022 022a 	bic.w	r2, r2, #42	@ 0x2a
 800caaa:	609a      	str	r2, [r3, #8]

  __HAL_UART_ENABLE(huart);
 800caac:	687b      	ldr	r3, [r7, #4]
 800caae:	681b      	ldr	r3, [r3, #0]
 800cab0:	681a      	ldr	r2, [r3, #0]
 800cab2:	687b      	ldr	r3, [r7, #4]
 800cab4:	681b      	ldr	r3, [r3, #0]
 800cab6:	f042 0201 	orr.w	r2, r2, #1
 800caba:	601a      	str	r2, [r3, #0]

  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
  return (UART_CheckIdleState(huart));
 800cabc:	6878      	ldr	r0, [r7, #4]
 800cabe:	f001 fa67 	bl	800df90 <UART_CheckIdleState>
 800cac2:	4603      	mov	r3, r0
}
 800cac4:	4618      	mov	r0, r3
 800cac6:	3708      	adds	r7, #8
 800cac8:	46bd      	mov	sp, r7
 800caca:	bd80      	pop	{r7, pc}

0800cacc <HAL_UART_Transmit_IT>:
  * @param pData Pointer to data buffer (u8 or u16 data elements).
  * @param Size  Amount of data elements (u8 or u16) to be sent.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
 800cacc:	b480      	push	{r7}
 800cace:	b091      	sub	sp, #68	@ 0x44
 800cad0:	af00      	add	r7, sp, #0
 800cad2:	60f8      	str	r0, [r7, #12]
 800cad4:	60b9      	str	r1, [r7, #8]
 800cad6:	4613      	mov	r3, r2
 800cad8:	80fb      	strh	r3, [r7, #6]
  /* Check that a Tx process is not already ongoing */
  if (huart->gState == HAL_UART_STATE_READY)
 800cada:	68fb      	ldr	r3, [r7, #12]
 800cadc:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800cae0:	2b20      	cmp	r3, #32
 800cae2:	d178      	bne.n	800cbd6 <HAL_UART_Transmit_IT+0x10a>
  {
    if ((pData == NULL) || (Size == 0U))
 800cae4:	68bb      	ldr	r3, [r7, #8]
 800cae6:	2b00      	cmp	r3, #0
 800cae8:	d002      	beq.n	800caf0 <HAL_UART_Transmit_IT+0x24>
 800caea:	88fb      	ldrh	r3, [r7, #6]
 800caec:	2b00      	cmp	r3, #0
 800caee:	d101      	bne.n	800caf4 <HAL_UART_Transmit_IT+0x28>
    {
      return HAL_ERROR;
 800caf0:	2301      	movs	r3, #1
 800caf2:	e071      	b.n	800cbd8 <HAL_UART_Transmit_IT+0x10c>
    }

    huart->pTxBuffPtr  = pData;
 800caf4:	68fb      	ldr	r3, [r7, #12]
 800caf6:	68ba      	ldr	r2, [r7, #8]
 800caf8:	651a      	str	r2, [r3, #80]	@ 0x50
    huart->TxXferSize  = Size;
 800cafa:	68fb      	ldr	r3, [r7, #12]
 800cafc:	88fa      	ldrh	r2, [r7, #6]
 800cafe:	f8a3 2054 	strh.w	r2, [r3, #84]	@ 0x54
    huart->TxXferCount = Size;
 800cb02:	68fb      	ldr	r3, [r7, #12]
 800cb04:	88fa      	ldrh	r2, [r7, #6]
 800cb06:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
    huart->TxISR       = NULL;
 800cb0a:	68fb      	ldr	r3, [r7, #12]
 800cb0c:	2200      	movs	r2, #0
 800cb0e:	679a      	str	r2, [r3, #120]	@ 0x78

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 800cb10:	68fb      	ldr	r3, [r7, #12]
 800cb12:	2200      	movs	r2, #0
 800cb14:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    huart->gState = HAL_UART_STATE_BUSY_TX;
 800cb18:	68fb      	ldr	r3, [r7, #12]
 800cb1a:	2221      	movs	r2, #33	@ 0x21
 800cb1c:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

    /* Configure Tx interrupt processing */
    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
 800cb20:	68fb      	ldr	r3, [r7, #12]
 800cb22:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 800cb24:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800cb28:	d12a      	bne.n	800cb80 <HAL_UART_Transmit_IT+0xb4>
    {
      /* Set the Tx ISR function pointer according to the data word length */
      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 800cb2a:	68fb      	ldr	r3, [r7, #12]
 800cb2c:	689b      	ldr	r3, [r3, #8]
 800cb2e:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800cb32:	d107      	bne.n	800cb44 <HAL_UART_Transmit_IT+0x78>
 800cb34:	68fb      	ldr	r3, [r7, #12]
 800cb36:	691b      	ldr	r3, [r3, #16]
 800cb38:	2b00      	cmp	r3, #0
 800cb3a:	d103      	bne.n	800cb44 <HAL_UART_Transmit_IT+0x78>
      {
        huart->TxISR = UART_TxISR_16BIT_FIFOEN;
 800cb3c:	68fb      	ldr	r3, [r7, #12]
 800cb3e:	4a29      	ldr	r2, [pc, #164]	@ (800cbe4 <HAL_UART_Transmit_IT+0x118>)
 800cb40:	679a      	str	r2, [r3, #120]	@ 0x78
 800cb42:	e002      	b.n	800cb4a <HAL_UART_Transmit_IT+0x7e>
      }
      else
      {
        huart->TxISR = UART_TxISR_8BIT_FIFOEN;
 800cb44:	68fb      	ldr	r3, [r7, #12]
 800cb46:	4a28      	ldr	r2, [pc, #160]	@ (800cbe8 <HAL_UART_Transmit_IT+0x11c>)
 800cb48:	679a      	str	r2, [r3, #120]	@ 0x78
      }

      /* Enable the TX FIFO threshold interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
 800cb4a:	68fb      	ldr	r3, [r7, #12]
 800cb4c:	681b      	ldr	r3, [r3, #0]
 800cb4e:	3308      	adds	r3, #8
 800cb50:	62bb      	str	r3, [r7, #40]	@ 0x28
 */
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
    uint32_t result;

   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800cb52:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800cb54:	e853 3f00 	ldrex	r3, [r3]
 800cb58:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 800cb5a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800cb5c:	f443 0300 	orr.w	r3, r3, #8388608	@ 0x800000
 800cb60:	63bb      	str	r3, [r7, #56]	@ 0x38
 800cb62:	68fb      	ldr	r3, [r7, #12]
 800cb64:	681b      	ldr	r3, [r3, #0]
 800cb66:	3308      	adds	r3, #8
 800cb68:	6bba      	ldr	r2, [r7, #56]	@ 0x38
 800cb6a:	637a      	str	r2, [r7, #52]	@ 0x34
 800cb6c:	633b      	str	r3, [r7, #48]	@ 0x30
 */
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
   uint32_t result;

   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800cb6e:	6b39      	ldr	r1, [r7, #48]	@ 0x30
 800cb70:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 800cb72:	e841 2300 	strex	r3, r2, [r1]
 800cb76:	62fb      	str	r3, [r7, #44]	@ 0x2c
   return(result);
 800cb78:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800cb7a:	2b00      	cmp	r3, #0
 800cb7c:	d1e5      	bne.n	800cb4a <HAL_UART_Transmit_IT+0x7e>
 800cb7e:	e028      	b.n	800cbd2 <HAL_UART_Transmit_IT+0x106>
    }
    else
    {
      /* Set the Tx ISR function pointer according to the data word length */
      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 800cb80:	68fb      	ldr	r3, [r7, #12]
 800cb82:	689b      	ldr	r3, [r3, #8]
 800cb84:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800cb88:	d107      	bne.n	800cb9a <HAL_UART_Transmit_IT+0xce>
 800cb8a:	68fb      	ldr	r3, [r7, #12]
 800cb8c:	691b      	ldr	r3, [r3, #16]
 800cb8e:	2b00      	cmp	r3, #0
 800cb90:	d103      	bne.n	800cb9a <HAL_UART_Transmit_IT+0xce>
      {
        huart->TxISR = UART_TxISR_16BIT;
 800cb92:	68fb      	ldr	r3, [r7, #12]
 800cb94:	4a15      	ldr	r2, [pc, #84]	@ (800cbec <HAL_UART_Transmit_IT+0x120>)
 800cb96:	679a      	str	r2, [r3, #120]	@ 0x78
 800cb98:	e002      	b.n	800cba0 <HAL_UART_Transmit_IT+0xd4>
      }
      else
      {
        huart->TxISR = UART_TxISR_8BIT;
 800cb9a:	68fb      	ldr	r3, [r7, #12]
 800cb9c:	4a14      	ldr	r2, [pc, #80]	@ (800cbf0 <HAL_UART_Transmit_IT+0x124>)
 800cb9e:	679a      	str	r2, [r3, #120]	@ 0x78
      }

      /* Enable the Transmit Data Register Empty interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
 800cba0:	68fb      	ldr	r3, [r7, #12]
 800cba2:	681b      	ldr	r3, [r3, #0]
 800cba4:	617b      	str	r3, [r7, #20]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800cba6:	697b      	ldr	r3, [r7, #20]
 800cba8:	e853 3f00 	ldrex	r3, [r3]
 800cbac:	613b      	str	r3, [r7, #16]
   return(result);
 800cbae:	693b      	ldr	r3, [r7, #16]
 800cbb0:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 800cbb4:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800cbb6:	68fb      	ldr	r3, [r7, #12]
 800cbb8:	681b      	ldr	r3, [r3, #0]
 800cbba:	461a      	mov	r2, r3
 800cbbc:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800cbbe:	623b      	str	r3, [r7, #32]
 800cbc0:	61fa      	str	r2, [r7, #28]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800cbc2:	69f9      	ldr	r1, [r7, #28]
 800cbc4:	6a3a      	ldr	r2, [r7, #32]
 800cbc6:	e841 2300 	strex	r3, r2, [r1]
 800cbca:	61bb      	str	r3, [r7, #24]
   return(result);
 800cbcc:	69bb      	ldr	r3, [r7, #24]
 800cbce:	2b00      	cmp	r3, #0
 800cbd0:	d1e6      	bne.n	800cba0 <HAL_UART_Transmit_IT+0xd4>
    }

    return HAL_OK;
 800cbd2:	2300      	movs	r3, #0
 800cbd4:	e000      	b.n	800cbd8 <HAL_UART_Transmit_IT+0x10c>
  }
  else
  {
    return HAL_BUSY;
 800cbd6:	2302      	movs	r3, #2
  }
}
 800cbd8:	4618      	mov	r0, r3
 800cbda:	3744      	adds	r7, #68	@ 0x44
 800cbdc:	46bd      	mov	sp, r7
 800cbde:	f85d 7b04 	ldr.w	r7, [sp], #4
 800cbe2:	4770      	bx	lr
 800cbe4:	0800e757 	.word	0x0800e757
 800cbe8:	0800e677 	.word	0x0800e677
 800cbec:	0800e5b5 	.word	0x0800e5b5
 800cbf0:	0800e4fd 	.word	0x0800e4fd

0800cbf4 <HAL_UART_IRQHandler>:
  * @brief Handle UART interrupt request.
  * @param huart UART handle.
  * @retval None
  */
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
 800cbf4:	b580      	push	{r7, lr}
 800cbf6:	b0ba      	sub	sp, #232	@ 0xe8
 800cbf8:	af00      	add	r7, sp, #0
 800cbfa:	6078      	str	r0, [r7, #4]
  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
 800cbfc:	687b      	ldr	r3, [r7, #4]
 800cbfe:	681b      	ldr	r3, [r3, #0]
 800cc00:	69db      	ldr	r3, [r3, #28]
 800cc02:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
 800cc06:	687b      	ldr	r3, [r7, #4]
 800cc08:	681b      	ldr	r3, [r3, #0]
 800cc0a:	681b      	ldr	r3, [r3, #0]
 800cc0c:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
 800cc10:	687b      	ldr	r3, [r7, #4]
 800cc12:	681b      	ldr	r3, [r3, #0]
 800cc14:	689b      	ldr	r3, [r3, #8]
 800cc16:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc

  uint32_t errorflags;
  uint32_t errorcode;

  /* If no error occurs */
  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
 800cc1a:	f8d7 20e4 	ldr.w	r2, [r7, #228]	@ 0xe4
 800cc1e:	f640 030f 	movw	r3, #2063	@ 0x80f
 800cc22:	4013      	ands	r3, r2
 800cc24:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
  if (errorflags == 0U)
 800cc28:	f8d7 30d8 	ldr.w	r3, [r7, #216]	@ 0xd8
 800cc2c:	2b00      	cmp	r3, #0
 800cc2e:	d11b      	bne.n	800cc68 <HAL_UART_IRQHandler+0x74>
  {
    /* UART in mode Receiver ---------------------------------------------------*/
    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
 800cc30:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800cc34:	f003 0320 	and.w	r3, r3, #32
 800cc38:	2b00      	cmp	r3, #0
 800cc3a:	d015      	beq.n	800cc68 <HAL_UART_IRQHandler+0x74>
        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
 800cc3c:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800cc40:	f003 0320 	and.w	r3, r3, #32
 800cc44:	2b00      	cmp	r3, #0
 800cc46:	d105      	bne.n	800cc54 <HAL_UART_IRQHandler+0x60>
            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
 800cc48:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 800cc4c:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 800cc50:	2b00      	cmp	r3, #0
 800cc52:	d009      	beq.n	800cc68 <HAL_UART_IRQHandler+0x74>
    {
      if (huart->RxISR != NULL)
 800cc54:	687b      	ldr	r3, [r7, #4]
 800cc56:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 800cc58:	2b00      	cmp	r3, #0
 800cc5a:	f000 8377 	beq.w	800d34c <HAL_UART_IRQHandler+0x758>
      {
        huart->RxISR(huart);
 800cc5e:	687b      	ldr	r3, [r7, #4]
 800cc60:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 800cc62:	6878      	ldr	r0, [r7, #4]
 800cc64:	4798      	blx	r3
      }
      return;
 800cc66:	e371      	b.n	800d34c <HAL_UART_IRQHandler+0x758>
    }
  }

  /* If some errors occur */
  if ((errorflags != 0U)
 800cc68:	f8d7 30d8 	ldr.w	r3, [r7, #216]	@ 0xd8
 800cc6c:	2b00      	cmp	r3, #0
 800cc6e:	f000 8123 	beq.w	800ceb8 <HAL_UART_IRQHandler+0x2c4>
      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
 800cc72:	f8d7 20dc 	ldr.w	r2, [r7, #220]	@ 0xdc
 800cc76:	4b8d      	ldr	r3, [pc, #564]	@ (800ceac <HAL_UART_IRQHandler+0x2b8>)
 800cc78:	4013      	ands	r3, r2
 800cc7a:	2b00      	cmp	r3, #0
 800cc7c:	d106      	bne.n	800cc8c <HAL_UART_IRQHandler+0x98>
           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
 800cc7e:	f8d7 20e0 	ldr.w	r2, [r7, #224]	@ 0xe0
 800cc82:	4b8b      	ldr	r3, [pc, #556]	@ (800ceb0 <HAL_UART_IRQHandler+0x2bc>)
 800cc84:	4013      	ands	r3, r2
 800cc86:	2b00      	cmp	r3, #0
 800cc88:	f000 8116 	beq.w	800ceb8 <HAL_UART_IRQHandler+0x2c4>
  {
    /* UART parity error interrupt occurred -------------------------------------*/
    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
 800cc8c:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800cc90:	f003 0301 	and.w	r3, r3, #1
 800cc94:	2b00      	cmp	r3, #0
 800cc96:	d011      	beq.n	800ccbc <HAL_UART_IRQHandler+0xc8>
 800cc98:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800cc9c:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800cca0:	2b00      	cmp	r3, #0
 800cca2:	d00b      	beq.n	800ccbc <HAL_UART_IRQHandler+0xc8>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
 800cca4:	687b      	ldr	r3, [r7, #4]
 800cca6:	681b      	ldr	r3, [r3, #0]
 800cca8:	2201      	movs	r2, #1
 800ccaa:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_PE;
 800ccac:	687b      	ldr	r3, [r7, #4]
 800ccae:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800ccb2:	f043 0201 	orr.w	r2, r3, #1
 800ccb6:	687b      	ldr	r3, [r7, #4]
 800ccb8:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    }

    /* UART frame error interrupt occurred --------------------------------------*/
    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 800ccbc:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800ccc0:	f003 0302 	and.w	r3, r3, #2
 800ccc4:	2b00      	cmp	r3, #0
 800ccc6:	d011      	beq.n	800ccec <HAL_UART_IRQHandler+0xf8>
 800ccc8:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 800cccc:	f003 0301 	and.w	r3, r3, #1
 800ccd0:	2b00      	cmp	r3, #0
 800ccd2:	d00b      	beq.n	800ccec <HAL_UART_IRQHandler+0xf8>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
 800ccd4:	687b      	ldr	r3, [r7, #4]
 800ccd6:	681b      	ldr	r3, [r3, #0]
 800ccd8:	2202      	movs	r2, #2
 800ccda:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_FE;
 800ccdc:	687b      	ldr	r3, [r7, #4]
 800ccde:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800cce2:	f043 0204 	orr.w	r2, r3, #4
 800cce6:	687b      	ldr	r3, [r7, #4]
 800cce8:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    }

    /* UART noise error interrupt occurred --------------------------------------*/
    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 800ccec:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800ccf0:	f003 0304 	and.w	r3, r3, #4
 800ccf4:	2b00      	cmp	r3, #0
 800ccf6:	d011      	beq.n	800cd1c <HAL_UART_IRQHandler+0x128>
 800ccf8:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 800ccfc:	f003 0301 	and.w	r3, r3, #1
 800cd00:	2b00      	cmp	r3, #0
 800cd02:	d00b      	beq.n	800cd1c <HAL_UART_IRQHandler+0x128>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
 800cd04:	687b      	ldr	r3, [r7, #4]
 800cd06:	681b      	ldr	r3, [r3, #0]
 800cd08:	2204      	movs	r2, #4
 800cd0a:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_NE;
 800cd0c:	687b      	ldr	r3, [r7, #4]
 800cd0e:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800cd12:	f043 0202 	orr.w	r2, r3, #2
 800cd16:	687b      	ldr	r3, [r7, #4]
 800cd18:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    }

    /* UART Over-Run interrupt occurred -----------------------------------------*/
    if (((isrflags & USART_ISR_ORE) != 0U)
 800cd1c:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800cd20:	f003 0308 	and.w	r3, r3, #8
 800cd24:	2b00      	cmp	r3, #0
 800cd26:	d017      	beq.n	800cd58 <HAL_UART_IRQHandler+0x164>
        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
 800cd28:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800cd2c:	f003 0320 	and.w	r3, r3, #32
 800cd30:	2b00      	cmp	r3, #0
 800cd32:	d105      	bne.n	800cd40 <HAL_UART_IRQHandler+0x14c>
            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
 800cd34:	f8d7 20dc 	ldr.w	r2, [r7, #220]	@ 0xdc
 800cd38:	4b5c      	ldr	r3, [pc, #368]	@ (800ceac <HAL_UART_IRQHandler+0x2b8>)
 800cd3a:	4013      	ands	r3, r2
        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
 800cd3c:	2b00      	cmp	r3, #0
 800cd3e:	d00b      	beq.n	800cd58 <HAL_UART_IRQHandler+0x164>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 800cd40:	687b      	ldr	r3, [r7, #4]
 800cd42:	681b      	ldr	r3, [r3, #0]
 800cd44:	2208      	movs	r2, #8
 800cd46:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_ORE;
 800cd48:	687b      	ldr	r3, [r7, #4]
 800cd4a:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800cd4e:	f043 0208 	orr.w	r2, r3, #8
 800cd52:	687b      	ldr	r3, [r7, #4]
 800cd54:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    }

    /* UART Receiver Timeout interrupt occurred ---------------------------------*/
    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
 800cd58:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800cd5c:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 800cd60:	2b00      	cmp	r3, #0
 800cd62:	d012      	beq.n	800cd8a <HAL_UART_IRQHandler+0x196>
 800cd64:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800cd68:	f003 6380 	and.w	r3, r3, #67108864	@ 0x4000000
 800cd6c:	2b00      	cmp	r3, #0
 800cd6e:	d00c      	beq.n	800cd8a <HAL_UART_IRQHandler+0x196>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 800cd70:	687b      	ldr	r3, [r7, #4]
 800cd72:	681b      	ldr	r3, [r3, #0]
 800cd74:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 800cd78:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_RTO;
 800cd7a:	687b      	ldr	r3, [r7, #4]
 800cd7c:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800cd80:	f043 0220 	orr.w	r2, r3, #32
 800cd84:	687b      	ldr	r3, [r7, #4]
 800cd86:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    }

    /* Call UART Error Call back function if need be ----------------------------*/
    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
 800cd8a:	687b      	ldr	r3, [r7, #4]
 800cd8c:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800cd90:	2b00      	cmp	r3, #0
 800cd92:	f000 82dd 	beq.w	800d350 <HAL_UART_IRQHandler+0x75c>
    {
      /* UART in mode Receiver --------------------------------------------------*/
      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
 800cd96:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800cd9a:	f003 0320 	and.w	r3, r3, #32
 800cd9e:	2b00      	cmp	r3, #0
 800cda0:	d013      	beq.n	800cdca <HAL_UART_IRQHandler+0x1d6>
          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
 800cda2:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800cda6:	f003 0320 	and.w	r3, r3, #32
 800cdaa:	2b00      	cmp	r3, #0
 800cdac:	d105      	bne.n	800cdba <HAL_UART_IRQHandler+0x1c6>
              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
 800cdae:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 800cdb2:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 800cdb6:	2b00      	cmp	r3, #0
 800cdb8:	d007      	beq.n	800cdca <HAL_UART_IRQHandler+0x1d6>
      {
        if (huart->RxISR != NULL)
 800cdba:	687b      	ldr	r3, [r7, #4]
 800cdbc:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 800cdbe:	2b00      	cmp	r3, #0
 800cdc0:	d003      	beq.n	800cdca <HAL_UART_IRQHandler+0x1d6>
        {
          huart->RxISR(huart);
 800cdc2:	687b      	ldr	r3, [r7, #4]
 800cdc4:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 800cdc6:	6878      	ldr	r0, [r7, #4]
 800cdc8:	4798      	blx	r3
      /* If Error is to be considered as blocking :
          - Receiver Timeout error in Reception
          - Overrun error in Reception
          - any error occurs in DMA mode reception
      */
      errorcode = huart->ErrorCode;
 800cdca:	687b      	ldr	r3, [r7, #4]
 800cdcc:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800cdd0:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
 800cdd4:	687b      	ldr	r3, [r7, #4]
 800cdd6:	681b      	ldr	r3, [r3, #0]
 800cdd8:	689b      	ldr	r3, [r3, #8]
 800cdda:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800cdde:	2b40      	cmp	r3, #64	@ 0x40
 800cde0:	d005      	beq.n	800cdee <HAL_UART_IRQHandler+0x1fa>
          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
 800cde2:	f8d7 30d4 	ldr.w	r3, [r7, #212]	@ 0xd4
 800cde6:	f003 0328 	and.w	r3, r3, #40	@ 0x28
      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
 800cdea:	2b00      	cmp	r3, #0
 800cdec:	d054      	beq.n	800ce98 <HAL_UART_IRQHandler+0x2a4>
      {
        /* Blocking error : transfer is aborted
           Set the UART state ready to be able to start again the process,
           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
        UART_EndRxTransfer(huart);
 800cdee:	6878      	ldr	r0, [r7, #4]
 800cdf0:	f001 fb08 	bl	800e404 <UART_EndRxTransfer>

        /* Abort the UART DMA Rx channel if enabled */
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 800cdf4:	687b      	ldr	r3, [r7, #4]
 800cdf6:	681b      	ldr	r3, [r3, #0]
 800cdf8:	689b      	ldr	r3, [r3, #8]
 800cdfa:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800cdfe:	2b40      	cmp	r3, #64	@ 0x40
 800ce00:	d146      	bne.n	800ce90 <HAL_UART_IRQHandler+0x29c>
        {
          /* Disable the UART DMA Rx request if enabled */
          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 800ce02:	687b      	ldr	r3, [r7, #4]
 800ce04:	681b      	ldr	r3, [r3, #0]
 800ce06:	3308      	adds	r3, #8
 800ce08:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800ce0c:	f8d7 309c 	ldr.w	r3, [r7, #156]	@ 0x9c
 800ce10:	e853 3f00 	ldrex	r3, [r3]
 800ce14:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
   return(result);
 800ce18:	f8d7 3098 	ldr.w	r3, [r7, #152]	@ 0x98
 800ce1c:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
 800ce20:	f8c7 30d0 	str.w	r3, [r7, #208]	@ 0xd0
 800ce24:	687b      	ldr	r3, [r7, #4]
 800ce26:	681b      	ldr	r3, [r3, #0]
 800ce28:	3308      	adds	r3, #8
 800ce2a:	f8d7 20d0 	ldr.w	r2, [r7, #208]	@ 0xd0
 800ce2e:	f8c7 20a8 	str.w	r2, [r7, #168]	@ 0xa8
 800ce32:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800ce36:	f8d7 10a4 	ldr.w	r1, [r7, #164]	@ 0xa4
 800ce3a:	f8d7 20a8 	ldr.w	r2, [r7, #168]	@ 0xa8
 800ce3e:	e841 2300 	strex	r3, r2, [r1]
 800ce42:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
   return(result);
 800ce46:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
 800ce4a:	2b00      	cmp	r3, #0
 800ce4c:	d1d9      	bne.n	800ce02 <HAL_UART_IRQHandler+0x20e>

          /* Abort the UART DMA Rx channel */
          if (huart->hdmarx != NULL)
 800ce4e:	687b      	ldr	r3, [r7, #4]
 800ce50:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800ce54:	2b00      	cmp	r3, #0
 800ce56:	d017      	beq.n	800ce88 <HAL_UART_IRQHandler+0x294>
          {
            /* Set the UART DMA Abort callback :
               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
 800ce58:	687b      	ldr	r3, [r7, #4]
 800ce5a:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800ce5e:	4a15      	ldr	r2, [pc, #84]	@ (800ceb4 <HAL_UART_IRQHandler+0x2c0>)
 800ce60:	651a      	str	r2, [r3, #80]	@ 0x50

            /* Abort DMA RX */
            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
 800ce62:	687b      	ldr	r3, [r7, #4]
 800ce64:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800ce68:	4618      	mov	r0, r3
 800ce6a:	f7f9 fba5 	bl	80065b8 <HAL_DMA_Abort_IT>
 800ce6e:	4603      	mov	r3, r0
 800ce70:	2b00      	cmp	r3, #0
 800ce72:	d019      	beq.n	800cea8 <HAL_UART_IRQHandler+0x2b4>
            {
              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 800ce74:	687b      	ldr	r3, [r7, #4]
 800ce76:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800ce7a:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800ce7c:	687a      	ldr	r2, [r7, #4]
 800ce7e:	f8d2 2080 	ldr.w	r2, [r2, #128]	@ 0x80
 800ce82:	4610      	mov	r0, r2
 800ce84:	4798      	blx	r3
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 800ce86:	e00f      	b.n	800cea8 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
            /*Call registered error callback*/
            huart->ErrorCallback(huart);
#else
            /*Call legacy weak error callback*/
            HAL_UART_ErrorCallback(huart);
 800ce88:	6878      	ldr	r0, [r7, #4]
 800ce8a:	f000 fa6d 	bl	800d368 <HAL_UART_ErrorCallback>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 800ce8e:	e00b      	b.n	800cea8 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered error callback*/
          huart->ErrorCallback(huart);
#else
          /*Call legacy weak error callback*/
          HAL_UART_ErrorCallback(huart);
 800ce90:	6878      	ldr	r0, [r7, #4]
 800ce92:	f000 fa69 	bl	800d368 <HAL_UART_ErrorCallback>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 800ce96:	e007      	b.n	800cea8 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered error callback*/
        huart->ErrorCallback(huart);
#else
        /*Call legacy weak error callback*/
        HAL_UART_ErrorCallback(huart);
 800ce98:	6878      	ldr	r0, [r7, #4]
 800ce9a:	f000 fa65 	bl	800d368 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
        huart->ErrorCode = HAL_UART_ERROR_NONE;
 800ce9e:	687b      	ldr	r3, [r7, #4]
 800cea0:	2200      	movs	r2, #0
 800cea2:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
      }
    }
    return;
 800cea6:	e253      	b.n	800d350 <HAL_UART_IRQHandler+0x75c>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 800cea8:	bf00      	nop
    return;
 800ceaa:	e251      	b.n	800d350 <HAL_UART_IRQHandler+0x75c>
 800ceac:	10000001 	.word	0x10000001
 800ceb0:	04000120 	.word	0x04000120
 800ceb4:	0800e4d1 	.word	0x0800e4d1

  } /* End if some error occurs */

  /* Check current reception Mode :
     If Reception till IDLE event has been selected : */
  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 800ceb8:	687b      	ldr	r3, [r7, #4]
 800ceba:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800cebc:	2b01      	cmp	r3, #1
 800cebe:	f040 81e7 	bne.w	800d290 <HAL_UART_IRQHandler+0x69c>
      && ((isrflags & USART_ISR_IDLE) != 0U)
 800cec2:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800cec6:	f003 0310 	and.w	r3, r3, #16
 800ceca:	2b00      	cmp	r3, #0
 800cecc:	f000 81e0 	beq.w	800d290 <HAL_UART_IRQHandler+0x69c>
      && ((cr1its & USART_ISR_IDLE) != 0U))
 800ced0:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800ced4:	f003 0310 	and.w	r3, r3, #16
 800ced8:	2b00      	cmp	r3, #0
 800ceda:	f000 81d9 	beq.w	800d290 <HAL_UART_IRQHandler+0x69c>
  {
    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 800cede:	687b      	ldr	r3, [r7, #4]
 800cee0:	681b      	ldr	r3, [r3, #0]
 800cee2:	2210      	movs	r2, #16
 800cee4:	621a      	str	r2, [r3, #32]

    /* Check if DMA mode is enabled in UART */
    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 800cee6:	687b      	ldr	r3, [r7, #4]
 800cee8:	681b      	ldr	r3, [r3, #0]
 800ceea:	689b      	ldr	r3, [r3, #8]
 800ceec:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800cef0:	2b40      	cmp	r3, #64	@ 0x40
 800cef2:	f040 8151 	bne.w	800d198 <HAL_UART_IRQHandler+0x5a4>
    {
      /* DMA mode enabled */
      /* Check received length : If all expected data are received, do nothing,
         (DMA cplt callback will be called).
         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
 800cef6:	687b      	ldr	r3, [r7, #4]
 800cef8:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cefc:	681b      	ldr	r3, [r3, #0]
 800cefe:	4a96      	ldr	r2, [pc, #600]	@ (800d158 <HAL_UART_IRQHandler+0x564>)
 800cf00:	4293      	cmp	r3, r2
 800cf02:	d068      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cf04:	687b      	ldr	r3, [r7, #4]
 800cf06:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cf0a:	681b      	ldr	r3, [r3, #0]
 800cf0c:	4a93      	ldr	r2, [pc, #588]	@ (800d15c <HAL_UART_IRQHandler+0x568>)
 800cf0e:	4293      	cmp	r3, r2
 800cf10:	d061      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cf12:	687b      	ldr	r3, [r7, #4]
 800cf14:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cf18:	681b      	ldr	r3, [r3, #0]
 800cf1a:	4a91      	ldr	r2, [pc, #580]	@ (800d160 <HAL_UART_IRQHandler+0x56c>)
 800cf1c:	4293      	cmp	r3, r2
 800cf1e:	d05a      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cf20:	687b      	ldr	r3, [r7, #4]
 800cf22:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cf26:	681b      	ldr	r3, [r3, #0]
 800cf28:	4a8e      	ldr	r2, [pc, #568]	@ (800d164 <HAL_UART_IRQHandler+0x570>)
 800cf2a:	4293      	cmp	r3, r2
 800cf2c:	d053      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cf2e:	687b      	ldr	r3, [r7, #4]
 800cf30:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cf34:	681b      	ldr	r3, [r3, #0]
 800cf36:	4a8c      	ldr	r2, [pc, #560]	@ (800d168 <HAL_UART_IRQHandler+0x574>)
 800cf38:	4293      	cmp	r3, r2
 800cf3a:	d04c      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cf3c:	687b      	ldr	r3, [r7, #4]
 800cf3e:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cf42:	681b      	ldr	r3, [r3, #0]
 800cf44:	4a89      	ldr	r2, [pc, #548]	@ (800d16c <HAL_UART_IRQHandler+0x578>)
 800cf46:	4293      	cmp	r3, r2
 800cf48:	d045      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cf4a:	687b      	ldr	r3, [r7, #4]
 800cf4c:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cf50:	681b      	ldr	r3, [r3, #0]
 800cf52:	4a87      	ldr	r2, [pc, #540]	@ (800d170 <HAL_UART_IRQHandler+0x57c>)
 800cf54:	4293      	cmp	r3, r2
 800cf56:	d03e      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cf58:	687b      	ldr	r3, [r7, #4]
 800cf5a:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cf5e:	681b      	ldr	r3, [r3, #0]
 800cf60:	4a84      	ldr	r2, [pc, #528]	@ (800d174 <HAL_UART_IRQHandler+0x580>)
 800cf62:	4293      	cmp	r3, r2
 800cf64:	d037      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cf66:	687b      	ldr	r3, [r7, #4]
 800cf68:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cf6c:	681b      	ldr	r3, [r3, #0]
 800cf6e:	4a82      	ldr	r2, [pc, #520]	@ (800d178 <HAL_UART_IRQHandler+0x584>)
 800cf70:	4293      	cmp	r3, r2
 800cf72:	d030      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cf74:	687b      	ldr	r3, [r7, #4]
 800cf76:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cf7a:	681b      	ldr	r3, [r3, #0]
 800cf7c:	4a7f      	ldr	r2, [pc, #508]	@ (800d17c <HAL_UART_IRQHandler+0x588>)
 800cf7e:	4293      	cmp	r3, r2
 800cf80:	d029      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cf82:	687b      	ldr	r3, [r7, #4]
 800cf84:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cf88:	681b      	ldr	r3, [r3, #0]
 800cf8a:	4a7d      	ldr	r2, [pc, #500]	@ (800d180 <HAL_UART_IRQHandler+0x58c>)
 800cf8c:	4293      	cmp	r3, r2
 800cf8e:	d022      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cf90:	687b      	ldr	r3, [r7, #4]
 800cf92:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cf96:	681b      	ldr	r3, [r3, #0]
 800cf98:	4a7a      	ldr	r2, [pc, #488]	@ (800d184 <HAL_UART_IRQHandler+0x590>)
 800cf9a:	4293      	cmp	r3, r2
 800cf9c:	d01b      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cf9e:	687b      	ldr	r3, [r7, #4]
 800cfa0:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cfa4:	681b      	ldr	r3, [r3, #0]
 800cfa6:	4a78      	ldr	r2, [pc, #480]	@ (800d188 <HAL_UART_IRQHandler+0x594>)
 800cfa8:	4293      	cmp	r3, r2
 800cfaa:	d014      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cfac:	687b      	ldr	r3, [r7, #4]
 800cfae:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cfb2:	681b      	ldr	r3, [r3, #0]
 800cfb4:	4a75      	ldr	r2, [pc, #468]	@ (800d18c <HAL_UART_IRQHandler+0x598>)
 800cfb6:	4293      	cmp	r3, r2
 800cfb8:	d00d      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cfba:	687b      	ldr	r3, [r7, #4]
 800cfbc:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cfc0:	681b      	ldr	r3, [r3, #0]
 800cfc2:	4a73      	ldr	r2, [pc, #460]	@ (800d190 <HAL_UART_IRQHandler+0x59c>)
 800cfc4:	4293      	cmp	r3, r2
 800cfc6:	d006      	beq.n	800cfd6 <HAL_UART_IRQHandler+0x3e2>
 800cfc8:	687b      	ldr	r3, [r7, #4]
 800cfca:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cfce:	681b      	ldr	r3, [r3, #0]
 800cfd0:	4a70      	ldr	r2, [pc, #448]	@ (800d194 <HAL_UART_IRQHandler+0x5a0>)
 800cfd2:	4293      	cmp	r3, r2
 800cfd4:	d106      	bne.n	800cfe4 <HAL_UART_IRQHandler+0x3f0>
 800cfd6:	687b      	ldr	r3, [r7, #4]
 800cfd8:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cfdc:	681b      	ldr	r3, [r3, #0]
 800cfde:	685b      	ldr	r3, [r3, #4]
 800cfe0:	b29b      	uxth	r3, r3
 800cfe2:	e005      	b.n	800cff0 <HAL_UART_IRQHandler+0x3fc>
 800cfe4:	687b      	ldr	r3, [r7, #4]
 800cfe6:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cfea:	681b      	ldr	r3, [r3, #0]
 800cfec:	685b      	ldr	r3, [r3, #4]
 800cfee:	b29b      	uxth	r3, r3
 800cff0:	f8a7 30be 	strh.w	r3, [r7, #190]	@ 0xbe
      if ((nb_remaining_rx_data > 0U)
 800cff4:	f8b7 30be 	ldrh.w	r3, [r7, #190]	@ 0xbe
 800cff8:	2b00      	cmp	r3, #0
 800cffa:	f000 81ab 	beq.w	800d354 <HAL_UART_IRQHandler+0x760>
          && (nb_remaining_rx_data < huart->RxXferSize))
 800cffe:	687b      	ldr	r3, [r7, #4]
 800d000:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
 800d004:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
 800d008:	429a      	cmp	r2, r3
 800d00a:	f080 81a3 	bcs.w	800d354 <HAL_UART_IRQHandler+0x760>
      {
        /* Reception is not complete */
        huart->RxXferCount = nb_remaining_rx_data;
 800d00e:	687b      	ldr	r3, [r7, #4]
 800d010:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
 800d014:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e

        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
        if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
 800d018:	687b      	ldr	r3, [r7, #4]
 800d01a:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800d01e:	69db      	ldr	r3, [r3, #28]
 800d020:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800d024:	f000 8087 	beq.w	800d136 <HAL_UART_IRQHandler+0x542>
        {
          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 800d028:	687b      	ldr	r3, [r7, #4]
 800d02a:	681b      	ldr	r3, [r3, #0]
 800d02c:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800d030:	f8d7 3088 	ldr.w	r3, [r7, #136]	@ 0x88
 800d034:	e853 3f00 	ldrex	r3, [r3]
 800d038:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
   return(result);
 800d03c:	f8d7 3084 	ldr.w	r3, [r7, #132]	@ 0x84
 800d040:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 800d044:	f8c7 30b8 	str.w	r3, [r7, #184]	@ 0xb8
 800d048:	687b      	ldr	r3, [r7, #4]
 800d04a:	681b      	ldr	r3, [r3, #0]
 800d04c:	461a      	mov	r2, r3
 800d04e:	f8d7 30b8 	ldr.w	r3, [r7, #184]	@ 0xb8
 800d052:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
 800d056:	f8c7 2090 	str.w	r2, [r7, #144]	@ 0x90
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800d05a:	f8d7 1090 	ldr.w	r1, [r7, #144]	@ 0x90
 800d05e:	f8d7 2094 	ldr.w	r2, [r7, #148]	@ 0x94
 800d062:	e841 2300 	strex	r3, r2, [r1]
 800d066:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
   return(result);
 800d06a:	f8d7 308c 	ldr.w	r3, [r7, #140]	@ 0x8c
 800d06e:	2b00      	cmp	r3, #0
 800d070:	d1da      	bne.n	800d028 <HAL_UART_IRQHandler+0x434>
          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800d072:	687b      	ldr	r3, [r7, #4]
 800d074:	681b      	ldr	r3, [r3, #0]
 800d076:	3308      	adds	r3, #8
 800d078:	677b      	str	r3, [r7, #116]	@ 0x74
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800d07a:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
 800d07c:	e853 3f00 	ldrex	r3, [r3]
 800d080:	673b      	str	r3, [r7, #112]	@ 0x70
   return(result);
 800d082:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
 800d084:	f023 0301 	bic.w	r3, r3, #1
 800d088:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
 800d08c:	687b      	ldr	r3, [r7, #4]
 800d08e:	681b      	ldr	r3, [r3, #0]
 800d090:	3308      	adds	r3, #8
 800d092:	f8d7 20b4 	ldr.w	r2, [r7, #180]	@ 0xb4
 800d096:	f8c7 2080 	str.w	r2, [r7, #128]	@ 0x80
 800d09a:	67fb      	str	r3, [r7, #124]	@ 0x7c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800d09c:	6ff9      	ldr	r1, [r7, #124]	@ 0x7c
 800d09e:	f8d7 2080 	ldr.w	r2, [r7, #128]	@ 0x80
 800d0a2:	e841 2300 	strex	r3, r2, [r1]
 800d0a6:	67bb      	str	r3, [r7, #120]	@ 0x78
   return(result);
 800d0a8:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
 800d0aa:	2b00      	cmp	r3, #0
 800d0ac:	d1e1      	bne.n	800d072 <HAL_UART_IRQHandler+0x47e>

          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
             in the UART CR3 register */
          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 800d0ae:	687b      	ldr	r3, [r7, #4]
 800d0b0:	681b      	ldr	r3, [r3, #0]
 800d0b2:	3308      	adds	r3, #8
 800d0b4:	663b      	str	r3, [r7, #96]	@ 0x60
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800d0b6:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 800d0b8:	e853 3f00 	ldrex	r3, [r3]
 800d0bc:	65fb      	str	r3, [r7, #92]	@ 0x5c
   return(result);
 800d0be:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 800d0c0:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
 800d0c4:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
 800d0c8:	687b      	ldr	r3, [r7, #4]
 800d0ca:	681b      	ldr	r3, [r3, #0]
 800d0cc:	3308      	adds	r3, #8
 800d0ce:	f8d7 20b0 	ldr.w	r2, [r7, #176]	@ 0xb0
 800d0d2:	66fa      	str	r2, [r7, #108]	@ 0x6c
 800d0d4:	66bb      	str	r3, [r7, #104]	@ 0x68
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800d0d6:	6eb9      	ldr	r1, [r7, #104]	@ 0x68
 800d0d8:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
 800d0da:	e841 2300 	strex	r3, r2, [r1]
 800d0de:	667b      	str	r3, [r7, #100]	@ 0x64
   return(result);
 800d0e0:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 800d0e2:	2b00      	cmp	r3, #0
 800d0e4:	d1e3      	bne.n	800d0ae <HAL_UART_IRQHandler+0x4ba>

          /* At end of Rx process, restore huart->RxState to Ready */
          huart->RxState = HAL_UART_STATE_READY;
 800d0e6:	687b      	ldr	r3, [r7, #4]
 800d0e8:	2220      	movs	r2, #32
 800d0ea:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800d0ee:	687b      	ldr	r3, [r7, #4]
 800d0f0:	2200      	movs	r2, #0
 800d0f2:	66da      	str	r2, [r3, #108]	@ 0x6c

          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 800d0f4:	687b      	ldr	r3, [r7, #4]
 800d0f6:	681b      	ldr	r3, [r3, #0]
 800d0f8:	64fb      	str	r3, [r7, #76]	@ 0x4c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800d0fa:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 800d0fc:	e853 3f00 	ldrex	r3, [r3]
 800d100:	64bb      	str	r3, [r7, #72]	@ 0x48
   return(result);
 800d102:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 800d104:	f023 0310 	bic.w	r3, r3, #16
 800d108:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
 800d10c:	687b      	ldr	r3, [r7, #4]
 800d10e:	681b      	ldr	r3, [r3, #0]
 800d110:	461a      	mov	r2, r3
 800d112:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 800d116:	65bb      	str	r3, [r7, #88]	@ 0x58
 800d118:	657a      	str	r2, [r7, #84]	@ 0x54
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800d11a:	6d79      	ldr	r1, [r7, #84]	@ 0x54
 800d11c:	6dba      	ldr	r2, [r7, #88]	@ 0x58
 800d11e:	e841 2300 	strex	r3, r2, [r1]
 800d122:	653b      	str	r3, [r7, #80]	@ 0x50
   return(result);
 800d124:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 800d126:	2b00      	cmp	r3, #0
 800d128:	d1e4      	bne.n	800d0f4 <HAL_UART_IRQHandler+0x500>

          /* Last bytes received, so no need as the abort is immediate */
          (void)HAL_DMA_Abort(huart->hdmarx);
 800d12a:	687b      	ldr	r3, [r7, #4]
 800d12c:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800d130:	4618      	mov	r0, r3
 800d132:	f7f8 ff23 	bl	8005f7c <HAL_DMA_Abort>
        }

        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
           In this case, Rx Event type is Idle Event */
        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
 800d136:	687b      	ldr	r3, [r7, #4]
 800d138:	2202      	movs	r2, #2
 800d13a:	671a      	str	r2, [r3, #112]	@ 0x70
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered Rx Event callback*/
        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
        /*Call legacy weak Rx Event callback*/
        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
 800d13c:	687b      	ldr	r3, [r7, #4]
 800d13e:	f8b3 205c 	ldrh.w	r2, [r3, #92]	@ 0x5c
 800d142:	687b      	ldr	r3, [r7, #4]
 800d144:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800d148:	b29b      	uxth	r3, r3
 800d14a:	1ad3      	subs	r3, r2, r3
 800d14c:	b29b      	uxth	r3, r3
 800d14e:	4619      	mov	r1, r3
 800d150:	6878      	ldr	r0, [r7, #4]
 800d152:	f7f5 fc4f 	bl	80029f4 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
      }
      return;
 800d156:	e0fd      	b.n	800d354 <HAL_UART_IRQHandler+0x760>
 800d158:	40020010 	.word	0x40020010
 800d15c:	40020028 	.word	0x40020028
 800d160:	40020040 	.word	0x40020040
 800d164:	40020058 	.word	0x40020058
 800d168:	40020070 	.word	0x40020070
 800d16c:	40020088 	.word	0x40020088
 800d170:	400200a0 	.word	0x400200a0
 800d174:	400200b8 	.word	0x400200b8
 800d178:	40020410 	.word	0x40020410
 800d17c:	40020428 	.word	0x40020428
 800d180:	40020440 	.word	0x40020440
 800d184:	40020458 	.word	0x40020458
 800d188:	40020470 	.word	0x40020470
 800d18c:	40020488 	.word	0x40020488
 800d190:	400204a0 	.word	0x400204a0
 800d194:	400204b8 	.word	0x400204b8
    else
    {
      /* DMA mode not enabled */
      /* Check received length : If all expected data are received, do nothing.
         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
 800d198:	687b      	ldr	r3, [r7, #4]
 800d19a:	f8b3 205c 	ldrh.w	r2, [r3, #92]	@ 0x5c
 800d19e:	687b      	ldr	r3, [r7, #4]
 800d1a0:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800d1a4:	b29b      	uxth	r3, r3
 800d1a6:	1ad3      	subs	r3, r2, r3
 800d1a8:	f8a7 30ce 	strh.w	r3, [r7, #206]	@ 0xce
      if ((huart->RxXferCount > 0U)
 800d1ac:	687b      	ldr	r3, [r7, #4]
 800d1ae:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800d1b2:	b29b      	uxth	r3, r3
 800d1b4:	2b00      	cmp	r3, #0
 800d1b6:	f000 80cf 	beq.w	800d358 <HAL_UART_IRQHandler+0x764>
          && (nb_rx_data > 0U))
 800d1ba:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
 800d1be:	2b00      	cmp	r3, #0
 800d1c0:	f000 80ca 	beq.w	800d358 <HAL_UART_IRQHandler+0x764>
      {
        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 800d1c4:	687b      	ldr	r3, [r7, #4]
 800d1c6:	681b      	ldr	r3, [r3, #0]
 800d1c8:	63bb      	str	r3, [r7, #56]	@ 0x38
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800d1ca:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d1cc:	e853 3f00 	ldrex	r3, [r3]
 800d1d0:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 800d1d2:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d1d4:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 800d1d8:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
 800d1dc:	687b      	ldr	r3, [r7, #4]
 800d1de:	681b      	ldr	r3, [r3, #0]
 800d1e0:	461a      	mov	r2, r3
 800d1e2:	f8d7 30c8 	ldr.w	r3, [r7, #200]	@ 0xc8
 800d1e6:	647b      	str	r3, [r7, #68]	@ 0x44
 800d1e8:	643a      	str	r2, [r7, #64]	@ 0x40
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800d1ea:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 800d1ec:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 800d1ee:	e841 2300 	strex	r3, r2, [r1]
 800d1f2:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 800d1f4:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800d1f6:	2b00      	cmp	r3, #0
 800d1f8:	d1e4      	bne.n	800d1c4 <HAL_UART_IRQHandler+0x5d0>

        /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 800d1fa:	687b      	ldr	r3, [r7, #4]
 800d1fc:	681b      	ldr	r3, [r3, #0]
 800d1fe:	3308      	adds	r3, #8
 800d200:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800d202:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800d204:	e853 3f00 	ldrex	r3, [r3]
 800d208:	623b      	str	r3, [r7, #32]
   return(result);
 800d20a:	6a3a      	ldr	r2, [r7, #32]
 800d20c:	4b55      	ldr	r3, [pc, #340]	@ (800d364 <HAL_UART_IRQHandler+0x770>)
 800d20e:	4013      	ands	r3, r2
 800d210:	f8c7 30c4 	str.w	r3, [r7, #196]	@ 0xc4
 800d214:	687b      	ldr	r3, [r7, #4]
 800d216:	681b      	ldr	r3, [r3, #0]
 800d218:	3308      	adds	r3, #8
 800d21a:	f8d7 20c4 	ldr.w	r2, [r7, #196]	@ 0xc4
 800d21e:	633a      	str	r2, [r7, #48]	@ 0x30
 800d220:	62fb      	str	r3, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800d222:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 800d224:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 800d226:	e841 2300 	strex	r3, r2, [r1]
 800d22a:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 800d22c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800d22e:	2b00      	cmp	r3, #0
 800d230:	d1e3      	bne.n	800d1fa <HAL_UART_IRQHandler+0x606>

        /* Rx process is completed, restore huart->RxState to Ready */
        huart->RxState = HAL_UART_STATE_READY;
 800d232:	687b      	ldr	r3, [r7, #4]
 800d234:	2220      	movs	r2, #32
 800d236:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800d23a:	687b      	ldr	r3, [r7, #4]
 800d23c:	2200      	movs	r2, #0
 800d23e:	66da      	str	r2, [r3, #108]	@ 0x6c

        /* Clear RxISR function pointer */
        huart->RxISR = NULL;
 800d240:	687b      	ldr	r3, [r7, #4]
 800d242:	2200      	movs	r2, #0
 800d244:	675a      	str	r2, [r3, #116]	@ 0x74

        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 800d246:	687b      	ldr	r3, [r7, #4]
 800d248:	681b      	ldr	r3, [r3, #0]
 800d24a:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800d24c:	693b      	ldr	r3, [r7, #16]
 800d24e:	e853 3f00 	ldrex	r3, [r3]
 800d252:	60fb      	str	r3, [r7, #12]
   return(result);
 800d254:	68fb      	ldr	r3, [r7, #12]
 800d256:	f023 0310 	bic.w	r3, r3, #16
 800d25a:	f8c7 30c0 	str.w	r3, [r7, #192]	@ 0xc0
 800d25e:	687b      	ldr	r3, [r7, #4]
 800d260:	681b      	ldr	r3, [r3, #0]
 800d262:	461a      	mov	r2, r3
 800d264:	f8d7 30c0 	ldr.w	r3, [r7, #192]	@ 0xc0
 800d268:	61fb      	str	r3, [r7, #28]
 800d26a:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800d26c:	69b9      	ldr	r1, [r7, #24]
 800d26e:	69fa      	ldr	r2, [r7, #28]
 800d270:	e841 2300 	strex	r3, r2, [r1]
 800d274:	617b      	str	r3, [r7, #20]
   return(result);
 800d276:	697b      	ldr	r3, [r7, #20]
 800d278:	2b00      	cmp	r3, #0
 800d27a:	d1e4      	bne.n	800d246 <HAL_UART_IRQHandler+0x652>

        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
           In this case, Rx Event type is Idle Event */
        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
 800d27c:	687b      	ldr	r3, [r7, #4]
 800d27e:	2202      	movs	r2, #2
 800d280:	671a      	str	r2, [r3, #112]	@ 0x70
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered Rx complete callback*/
        huart->RxEventCallback(huart, nb_rx_data);
#else
        /*Call legacy weak Rx Event callback*/
        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
 800d282:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
 800d286:	4619      	mov	r1, r3
 800d288:	6878      	ldr	r0, [r7, #4]
 800d28a:	f7f5 fbb3 	bl	80029f4 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
      }
      return;
 800d28e:	e063      	b.n	800d358 <HAL_UART_IRQHandler+0x764>
    }
  }

  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
 800d290:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800d294:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
 800d298:	2b00      	cmp	r3, #0
 800d29a:	d00e      	beq.n	800d2ba <HAL_UART_IRQHandler+0x6c6>
 800d29c:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 800d2a0:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
 800d2a4:	2b00      	cmp	r3, #0
 800d2a6:	d008      	beq.n	800d2ba <HAL_UART_IRQHandler+0x6c6>
  {
    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
 800d2a8:	687b      	ldr	r3, [r7, #4]
 800d2aa:	681b      	ldr	r3, [r3, #0]
 800d2ac:	f44f 1280 	mov.w	r2, #1048576	@ 0x100000
 800d2b0:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
    /* Call registered Wakeup Callback */
    huart->WakeupCallback(huart);
#else
    /* Call legacy weak Wakeup Callback */
    HAL_UARTEx_WakeupCallback(huart);
 800d2b2:	6878      	ldr	r0, [r7, #4]
 800d2b4:	f002 f80c 	bl	800f2d0 <HAL_UARTEx_WakeupCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
    return;
 800d2b8:	e051      	b.n	800d35e <HAL_UART_IRQHandler+0x76a>
  }

  /* UART in mode Transmitter ------------------------------------------------*/
  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
 800d2ba:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800d2be:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 800d2c2:	2b00      	cmp	r3, #0
 800d2c4:	d014      	beq.n	800d2f0 <HAL_UART_IRQHandler+0x6fc>
      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
 800d2c6:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800d2ca:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 800d2ce:	2b00      	cmp	r3, #0
 800d2d0:	d105      	bne.n	800d2de <HAL_UART_IRQHandler+0x6ea>
          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
 800d2d2:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 800d2d6:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 800d2da:	2b00      	cmp	r3, #0
 800d2dc:	d008      	beq.n	800d2f0 <HAL_UART_IRQHandler+0x6fc>
  {
    if (huart->TxISR != NULL)
 800d2de:	687b      	ldr	r3, [r7, #4]
 800d2e0:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 800d2e2:	2b00      	cmp	r3, #0
 800d2e4:	d03a      	beq.n	800d35c <HAL_UART_IRQHandler+0x768>
    {
      huart->TxISR(huart);
 800d2e6:	687b      	ldr	r3, [r7, #4]
 800d2e8:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 800d2ea:	6878      	ldr	r0, [r7, #4]
 800d2ec:	4798      	blx	r3
    }
    return;
 800d2ee:	e035      	b.n	800d35c <HAL_UART_IRQHandler+0x768>
  }

  /* UART in mode Transmitter (transmission end) -----------------------------*/
  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
 800d2f0:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800d2f4:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800d2f8:	2b00      	cmp	r3, #0
 800d2fa:	d009      	beq.n	800d310 <HAL_UART_IRQHandler+0x71c>
 800d2fc:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800d300:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800d304:	2b00      	cmp	r3, #0
 800d306:	d003      	beq.n	800d310 <HAL_UART_IRQHandler+0x71c>
  {
    UART_EndTransmit_IT(huart);
 800d308:	6878      	ldr	r0, [r7, #4]
 800d30a:	f001 fa99 	bl	800e840 <UART_EndTransmit_IT>
    return;
 800d30e:	e026      	b.n	800d35e <HAL_UART_IRQHandler+0x76a>
  }

  /* UART TX Fifo Empty occurred ----------------------------------------------*/
  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
 800d310:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800d314:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 800d318:	2b00      	cmp	r3, #0
 800d31a:	d009      	beq.n	800d330 <HAL_UART_IRQHandler+0x73c>
 800d31c:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800d320:	f003 4380 	and.w	r3, r3, #1073741824	@ 0x40000000
 800d324:	2b00      	cmp	r3, #0
 800d326:	d003      	beq.n	800d330 <HAL_UART_IRQHandler+0x73c>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
    /* Call registered Tx Fifo Empty Callback */
    huart->TxFifoEmptyCallback(huart);
#else
    /* Call legacy weak Tx Fifo Empty Callback */
    HAL_UARTEx_TxFifoEmptyCallback(huart);
 800d328:	6878      	ldr	r0, [r7, #4]
 800d32a:	f001 ffe5 	bl	800f2f8 <HAL_UARTEx_TxFifoEmptyCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
    return;
 800d32e:	e016      	b.n	800d35e <HAL_UART_IRQHandler+0x76a>
  }

  /* UART RX Fifo Full occurred ----------------------------------------------*/
  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
 800d330:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 800d334:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 800d338:	2b00      	cmp	r3, #0
 800d33a:	d010      	beq.n	800d35e <HAL_UART_IRQHandler+0x76a>
 800d33c:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 800d340:	2b00      	cmp	r3, #0
 800d342:	da0c      	bge.n	800d35e <HAL_UART_IRQHandler+0x76a>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
    /* Call registered Rx Fifo Full Callback */
    huart->RxFifoFullCallback(huart);
#else
    /* Call legacy weak Rx Fifo Full Callback */
    HAL_UARTEx_RxFifoFullCallback(huart);
 800d344:	6878      	ldr	r0, [r7, #4]
 800d346:	f001 ffcd 	bl	800f2e4 <HAL_UARTEx_RxFifoFullCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
    return;
 800d34a:	e008      	b.n	800d35e <HAL_UART_IRQHandler+0x76a>
      return;
 800d34c:	bf00      	nop
 800d34e:	e006      	b.n	800d35e <HAL_UART_IRQHandler+0x76a>
    return;
 800d350:	bf00      	nop
 800d352:	e004      	b.n	800d35e <HAL_UART_IRQHandler+0x76a>
      return;
 800d354:	bf00      	nop
 800d356:	e002      	b.n	800d35e <HAL_UART_IRQHandler+0x76a>
      return;
 800d358:	bf00      	nop
 800d35a:	e000      	b.n	800d35e <HAL_UART_IRQHandler+0x76a>
    return;
 800d35c:	bf00      	nop
  }
}
 800d35e:	37e8      	adds	r7, #232	@ 0xe8
 800d360:	46bd      	mov	sp, r7
 800d362:	bd80      	pop	{r7, pc}
 800d364:	effffffe 	.word	0xeffffffe

0800d368 <HAL_UART_ErrorCallback>:
  * @brief  UART error callback.
  * @param  huart UART handle.
  * @retval None
  */
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
 800d368:	b480      	push	{r7}
 800d36a:	b083      	sub	sp, #12
 800d36c:	af00      	add	r7, sp, #0
 800d36e:	6078      	str	r0, [r7, #4]
  UNUSED(huart);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_UART_ErrorCallback can be implemented in the user file.
   */
}
 800d370:	bf00      	nop
 800d372:	370c      	adds	r7, #12
 800d374:	46bd      	mov	sp, r7
 800d376:	f85d 7b04 	ldr.w	r7, [sp], #4
 800d37a:	4770      	bx	lr

0800d37c <UART_SetConfig>:
  * @brief Configure the UART peripheral.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
 800d37c:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 800d380:	b092      	sub	sp, #72	@ 0x48
 800d382:	af00      	add	r7, sp, #0
 800d384:	6178      	str	r0, [r7, #20]
  uint32_t tmpreg;
  uint16_t brrtemp;
  UART_ClockSourceTypeDef clocksource;
  uint32_t usartdiv;
  HAL_StatusTypeDef ret               = HAL_OK;
 800d386:	2300      	movs	r3, #0
 800d388:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
  *  the UART Word Length, Parity, Mode and oversampling:
  *  set the M bits according to huart->Init.WordLength value
  *  set PCE and PS bits according to huart->Init.Parity value
  *  set TE and RE bits according to huart->Init.Mode value
  *  set OVER8 bit according to huart->Init.OverSampling value */
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
 800d38c:	697b      	ldr	r3, [r7, #20]
 800d38e:	689a      	ldr	r2, [r3, #8]
 800d390:	697b      	ldr	r3, [r7, #20]
 800d392:	691b      	ldr	r3, [r3, #16]
 800d394:	431a      	orrs	r2, r3
 800d396:	697b      	ldr	r3, [r7, #20]
 800d398:	695b      	ldr	r3, [r3, #20]
 800d39a:	431a      	orrs	r2, r3
 800d39c:	697b      	ldr	r3, [r7, #20]
 800d39e:	69db      	ldr	r3, [r3, #28]
 800d3a0:	4313      	orrs	r3, r2
 800d3a2:	647b      	str	r3, [r7, #68]	@ 0x44
  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
 800d3a4:	697b      	ldr	r3, [r7, #20]
 800d3a6:	681b      	ldr	r3, [r3, #0]
 800d3a8:	681a      	ldr	r2, [r3, #0]
 800d3aa:	4bbe      	ldr	r3, [pc, #760]	@ (800d6a4 <UART_SetConfig+0x328>)
 800d3ac:	4013      	ands	r3, r2
 800d3ae:	697a      	ldr	r2, [r7, #20]
 800d3b0:	6812      	ldr	r2, [r2, #0]
 800d3b2:	6c79      	ldr	r1, [r7, #68]	@ 0x44
 800d3b4:	430b      	orrs	r3, r1
 800d3b6:	6013      	str	r3, [r2, #0]

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
  * to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 800d3b8:	697b      	ldr	r3, [r7, #20]
 800d3ba:	681b      	ldr	r3, [r3, #0]
 800d3bc:	685b      	ldr	r3, [r3, #4]
 800d3be:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
 800d3c2:	697b      	ldr	r3, [r7, #20]
 800d3c4:	68da      	ldr	r2, [r3, #12]
 800d3c6:	697b      	ldr	r3, [r7, #20]
 800d3c8:	681b      	ldr	r3, [r3, #0]
 800d3ca:	430a      	orrs	r2, r1
 800d3cc:	605a      	str	r2, [r3, #4]
  /* Configure
  * - UART HardWare Flow Control: set CTSE and RTSE bits according
  *   to huart->Init.HwFlowCtl value
  * - one-bit sampling method versus three samples' majority rule according
  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
 800d3ce:	697b      	ldr	r3, [r7, #20]
 800d3d0:	699b      	ldr	r3, [r3, #24]
 800d3d2:	647b      	str	r3, [r7, #68]	@ 0x44

  if (!(UART_INSTANCE_LOWPOWER(huart)))
 800d3d4:	697b      	ldr	r3, [r7, #20]
 800d3d6:	681b      	ldr	r3, [r3, #0]
 800d3d8:	4ab3      	ldr	r2, [pc, #716]	@ (800d6a8 <UART_SetConfig+0x32c>)
 800d3da:	4293      	cmp	r3, r2
 800d3dc:	d004      	beq.n	800d3e8 <UART_SetConfig+0x6c>
  {
    tmpreg |= huart->Init.OneBitSampling;
 800d3de:	697b      	ldr	r3, [r7, #20]
 800d3e0:	6a1b      	ldr	r3, [r3, #32]
 800d3e2:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 800d3e4:	4313      	orrs	r3, r2
 800d3e6:	647b      	str	r3, [r7, #68]	@ 0x44
  }
  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
 800d3e8:	697b      	ldr	r3, [r7, #20]
 800d3ea:	681b      	ldr	r3, [r3, #0]
 800d3ec:	689a      	ldr	r2, [r3, #8]
 800d3ee:	4baf      	ldr	r3, [pc, #700]	@ (800d6ac <UART_SetConfig+0x330>)
 800d3f0:	4013      	ands	r3, r2
 800d3f2:	697a      	ldr	r2, [r7, #20]
 800d3f4:	6812      	ldr	r2, [r2, #0]
 800d3f6:	6c79      	ldr	r1, [r7, #68]	@ 0x44
 800d3f8:	430b      	orrs	r3, r1
 800d3fa:	6093      	str	r3, [r2, #8]

  /*-------------------------- USART PRESC Configuration -----------------------*/
  /* Configure
  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
 800d3fc:	697b      	ldr	r3, [r7, #20]
 800d3fe:	681b      	ldr	r3, [r3, #0]
 800d400:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800d402:	f023 010f 	bic.w	r1, r3, #15
 800d406:	697b      	ldr	r3, [r7, #20]
 800d408:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
 800d40a:	697b      	ldr	r3, [r7, #20]
 800d40c:	681b      	ldr	r3, [r3, #0]
 800d40e:	430a      	orrs	r2, r1
 800d410:	62da      	str	r2, [r3, #44]	@ 0x2c

  /*-------------------------- USART BRR Configuration -----------------------*/
  UART_GETCLOCKSOURCE(huart, clocksource);
 800d412:	697b      	ldr	r3, [r7, #20]
 800d414:	681b      	ldr	r3, [r3, #0]
 800d416:	4aa6      	ldr	r2, [pc, #664]	@ (800d6b0 <UART_SetConfig+0x334>)
 800d418:	4293      	cmp	r3, r2
 800d41a:	d177      	bne.n	800d50c <UART_SetConfig+0x190>
 800d41c:	4ba5      	ldr	r3, [pc, #660]	@ (800d6b4 <UART_SetConfig+0x338>)
 800d41e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800d420:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 800d424:	2b28      	cmp	r3, #40	@ 0x28
 800d426:	d86d      	bhi.n	800d504 <UART_SetConfig+0x188>
 800d428:	a201      	add	r2, pc, #4	@ (adr r2, 800d430 <UART_SetConfig+0xb4>)
 800d42a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800d42e:	bf00      	nop
 800d430:	0800d4d5 	.word	0x0800d4d5
 800d434:	0800d505 	.word	0x0800d505
 800d438:	0800d505 	.word	0x0800d505
 800d43c:	0800d505 	.word	0x0800d505
 800d440:	0800d505 	.word	0x0800d505
 800d444:	0800d505 	.word	0x0800d505
 800d448:	0800d505 	.word	0x0800d505
 800d44c:	0800d505 	.word	0x0800d505
 800d450:	0800d4dd 	.word	0x0800d4dd
 800d454:	0800d505 	.word	0x0800d505
 800d458:	0800d505 	.word	0x0800d505
 800d45c:	0800d505 	.word	0x0800d505
 800d460:	0800d505 	.word	0x0800d505
 800d464:	0800d505 	.word	0x0800d505
 800d468:	0800d505 	.word	0x0800d505
 800d46c:	0800d505 	.word	0x0800d505
 800d470:	0800d4e5 	.word	0x0800d4e5
 800d474:	0800d505 	.word	0x0800d505
 800d478:	0800d505 	.word	0x0800d505
 800d47c:	0800d505 	.word	0x0800d505
 800d480:	0800d505 	.word	0x0800d505
 800d484:	0800d505 	.word	0x0800d505
 800d488:	0800d505 	.word	0x0800d505
 800d48c:	0800d505 	.word	0x0800d505
 800d490:	0800d4ed 	.word	0x0800d4ed
 800d494:	0800d505 	.word	0x0800d505
 800d498:	0800d505 	.word	0x0800d505
 800d49c:	0800d505 	.word	0x0800d505
 800d4a0:	0800d505 	.word	0x0800d505
 800d4a4:	0800d505 	.word	0x0800d505
 800d4a8:	0800d505 	.word	0x0800d505
 800d4ac:	0800d505 	.word	0x0800d505
 800d4b0:	0800d4f5 	.word	0x0800d4f5
 800d4b4:	0800d505 	.word	0x0800d505
 800d4b8:	0800d505 	.word	0x0800d505
 800d4bc:	0800d505 	.word	0x0800d505
 800d4c0:	0800d505 	.word	0x0800d505
 800d4c4:	0800d505 	.word	0x0800d505
 800d4c8:	0800d505 	.word	0x0800d505
 800d4cc:	0800d505 	.word	0x0800d505
 800d4d0:	0800d4fd 	.word	0x0800d4fd
 800d4d4:	2301      	movs	r3, #1
 800d4d6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d4da:	e222      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d4dc:	2304      	movs	r3, #4
 800d4de:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d4e2:	e21e      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d4e4:	2308      	movs	r3, #8
 800d4e6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d4ea:	e21a      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d4ec:	2310      	movs	r3, #16
 800d4ee:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d4f2:	e216      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d4f4:	2320      	movs	r3, #32
 800d4f6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d4fa:	e212      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d4fc:	2340      	movs	r3, #64	@ 0x40
 800d4fe:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d502:	e20e      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d504:	2380      	movs	r3, #128	@ 0x80
 800d506:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d50a:	e20a      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d50c:	697b      	ldr	r3, [r7, #20]
 800d50e:	681b      	ldr	r3, [r3, #0]
 800d510:	4a69      	ldr	r2, [pc, #420]	@ (800d6b8 <UART_SetConfig+0x33c>)
 800d512:	4293      	cmp	r3, r2
 800d514:	d130      	bne.n	800d578 <UART_SetConfig+0x1fc>
 800d516:	4b67      	ldr	r3, [pc, #412]	@ (800d6b4 <UART_SetConfig+0x338>)
 800d518:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800d51a:	f003 0307 	and.w	r3, r3, #7
 800d51e:	2b05      	cmp	r3, #5
 800d520:	d826      	bhi.n	800d570 <UART_SetConfig+0x1f4>
 800d522:	a201      	add	r2, pc, #4	@ (adr r2, 800d528 <UART_SetConfig+0x1ac>)
 800d524:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800d528:	0800d541 	.word	0x0800d541
 800d52c:	0800d549 	.word	0x0800d549
 800d530:	0800d551 	.word	0x0800d551
 800d534:	0800d559 	.word	0x0800d559
 800d538:	0800d561 	.word	0x0800d561
 800d53c:	0800d569 	.word	0x0800d569
 800d540:	2300      	movs	r3, #0
 800d542:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d546:	e1ec      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d548:	2304      	movs	r3, #4
 800d54a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d54e:	e1e8      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d550:	2308      	movs	r3, #8
 800d552:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d556:	e1e4      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d558:	2310      	movs	r3, #16
 800d55a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d55e:	e1e0      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d560:	2320      	movs	r3, #32
 800d562:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d566:	e1dc      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d568:	2340      	movs	r3, #64	@ 0x40
 800d56a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d56e:	e1d8      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d570:	2380      	movs	r3, #128	@ 0x80
 800d572:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d576:	e1d4      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d578:	697b      	ldr	r3, [r7, #20]
 800d57a:	681b      	ldr	r3, [r3, #0]
 800d57c:	4a4f      	ldr	r2, [pc, #316]	@ (800d6bc <UART_SetConfig+0x340>)
 800d57e:	4293      	cmp	r3, r2
 800d580:	d130      	bne.n	800d5e4 <UART_SetConfig+0x268>
 800d582:	4b4c      	ldr	r3, [pc, #304]	@ (800d6b4 <UART_SetConfig+0x338>)
 800d584:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800d586:	f003 0307 	and.w	r3, r3, #7
 800d58a:	2b05      	cmp	r3, #5
 800d58c:	d826      	bhi.n	800d5dc <UART_SetConfig+0x260>
 800d58e:	a201      	add	r2, pc, #4	@ (adr r2, 800d594 <UART_SetConfig+0x218>)
 800d590:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800d594:	0800d5ad 	.word	0x0800d5ad
 800d598:	0800d5b5 	.word	0x0800d5b5
 800d59c:	0800d5bd 	.word	0x0800d5bd
 800d5a0:	0800d5c5 	.word	0x0800d5c5
 800d5a4:	0800d5cd 	.word	0x0800d5cd
 800d5a8:	0800d5d5 	.word	0x0800d5d5
 800d5ac:	2300      	movs	r3, #0
 800d5ae:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d5b2:	e1b6      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d5b4:	2304      	movs	r3, #4
 800d5b6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d5ba:	e1b2      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d5bc:	2308      	movs	r3, #8
 800d5be:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d5c2:	e1ae      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d5c4:	2310      	movs	r3, #16
 800d5c6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d5ca:	e1aa      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d5cc:	2320      	movs	r3, #32
 800d5ce:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d5d2:	e1a6      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d5d4:	2340      	movs	r3, #64	@ 0x40
 800d5d6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d5da:	e1a2      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d5dc:	2380      	movs	r3, #128	@ 0x80
 800d5de:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d5e2:	e19e      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d5e4:	697b      	ldr	r3, [r7, #20]
 800d5e6:	681b      	ldr	r3, [r3, #0]
 800d5e8:	4a35      	ldr	r2, [pc, #212]	@ (800d6c0 <UART_SetConfig+0x344>)
 800d5ea:	4293      	cmp	r3, r2
 800d5ec:	d130      	bne.n	800d650 <UART_SetConfig+0x2d4>
 800d5ee:	4b31      	ldr	r3, [pc, #196]	@ (800d6b4 <UART_SetConfig+0x338>)
 800d5f0:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800d5f2:	f003 0307 	and.w	r3, r3, #7
 800d5f6:	2b05      	cmp	r3, #5
 800d5f8:	d826      	bhi.n	800d648 <UART_SetConfig+0x2cc>
 800d5fa:	a201      	add	r2, pc, #4	@ (adr r2, 800d600 <UART_SetConfig+0x284>)
 800d5fc:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800d600:	0800d619 	.word	0x0800d619
 800d604:	0800d621 	.word	0x0800d621
 800d608:	0800d629 	.word	0x0800d629
 800d60c:	0800d631 	.word	0x0800d631
 800d610:	0800d639 	.word	0x0800d639
 800d614:	0800d641 	.word	0x0800d641
 800d618:	2300      	movs	r3, #0
 800d61a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d61e:	e180      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d620:	2304      	movs	r3, #4
 800d622:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d626:	e17c      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d628:	2308      	movs	r3, #8
 800d62a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d62e:	e178      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d630:	2310      	movs	r3, #16
 800d632:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d636:	e174      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d638:	2320      	movs	r3, #32
 800d63a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d63e:	e170      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d640:	2340      	movs	r3, #64	@ 0x40
 800d642:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d646:	e16c      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d648:	2380      	movs	r3, #128	@ 0x80
 800d64a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d64e:	e168      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d650:	697b      	ldr	r3, [r7, #20]
 800d652:	681b      	ldr	r3, [r3, #0]
 800d654:	4a1b      	ldr	r2, [pc, #108]	@ (800d6c4 <UART_SetConfig+0x348>)
 800d656:	4293      	cmp	r3, r2
 800d658:	d142      	bne.n	800d6e0 <UART_SetConfig+0x364>
 800d65a:	4b16      	ldr	r3, [pc, #88]	@ (800d6b4 <UART_SetConfig+0x338>)
 800d65c:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800d65e:	f003 0307 	and.w	r3, r3, #7
 800d662:	2b05      	cmp	r3, #5
 800d664:	d838      	bhi.n	800d6d8 <UART_SetConfig+0x35c>
 800d666:	a201      	add	r2, pc, #4	@ (adr r2, 800d66c <UART_SetConfig+0x2f0>)
 800d668:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800d66c:	0800d685 	.word	0x0800d685
 800d670:	0800d68d 	.word	0x0800d68d
 800d674:	0800d695 	.word	0x0800d695
 800d678:	0800d69d 	.word	0x0800d69d
 800d67c:	0800d6c9 	.word	0x0800d6c9
 800d680:	0800d6d1 	.word	0x0800d6d1
 800d684:	2300      	movs	r3, #0
 800d686:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d68a:	e14a      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d68c:	2304      	movs	r3, #4
 800d68e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d692:	e146      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d694:	2308      	movs	r3, #8
 800d696:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d69a:	e142      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d69c:	2310      	movs	r3, #16
 800d69e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d6a2:	e13e      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d6a4:	cfff69f3 	.word	0xcfff69f3
 800d6a8:	58000c00 	.word	0x58000c00
 800d6ac:	11fff4ff 	.word	0x11fff4ff
 800d6b0:	40011000 	.word	0x40011000
 800d6b4:	58024400 	.word	0x58024400
 800d6b8:	40004400 	.word	0x40004400
 800d6bc:	40004800 	.word	0x40004800
 800d6c0:	40004c00 	.word	0x40004c00
 800d6c4:	40005000 	.word	0x40005000
 800d6c8:	2320      	movs	r3, #32
 800d6ca:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d6ce:	e128      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d6d0:	2340      	movs	r3, #64	@ 0x40
 800d6d2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d6d6:	e124      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d6d8:	2380      	movs	r3, #128	@ 0x80
 800d6da:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d6de:	e120      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d6e0:	697b      	ldr	r3, [r7, #20]
 800d6e2:	681b      	ldr	r3, [r3, #0]
 800d6e4:	4acb      	ldr	r2, [pc, #812]	@ (800da14 <UART_SetConfig+0x698>)
 800d6e6:	4293      	cmp	r3, r2
 800d6e8:	d176      	bne.n	800d7d8 <UART_SetConfig+0x45c>
 800d6ea:	4bcb      	ldr	r3, [pc, #812]	@ (800da18 <UART_SetConfig+0x69c>)
 800d6ec:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800d6ee:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 800d6f2:	2b28      	cmp	r3, #40	@ 0x28
 800d6f4:	d86c      	bhi.n	800d7d0 <UART_SetConfig+0x454>
 800d6f6:	a201      	add	r2, pc, #4	@ (adr r2, 800d6fc <UART_SetConfig+0x380>)
 800d6f8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800d6fc:	0800d7a1 	.word	0x0800d7a1
 800d700:	0800d7d1 	.word	0x0800d7d1
 800d704:	0800d7d1 	.word	0x0800d7d1
 800d708:	0800d7d1 	.word	0x0800d7d1
 800d70c:	0800d7d1 	.word	0x0800d7d1
 800d710:	0800d7d1 	.word	0x0800d7d1
 800d714:	0800d7d1 	.word	0x0800d7d1
 800d718:	0800d7d1 	.word	0x0800d7d1
 800d71c:	0800d7a9 	.word	0x0800d7a9
 800d720:	0800d7d1 	.word	0x0800d7d1
 800d724:	0800d7d1 	.word	0x0800d7d1
 800d728:	0800d7d1 	.word	0x0800d7d1
 800d72c:	0800d7d1 	.word	0x0800d7d1
 800d730:	0800d7d1 	.word	0x0800d7d1
 800d734:	0800d7d1 	.word	0x0800d7d1
 800d738:	0800d7d1 	.word	0x0800d7d1
 800d73c:	0800d7b1 	.word	0x0800d7b1
 800d740:	0800d7d1 	.word	0x0800d7d1
 800d744:	0800d7d1 	.word	0x0800d7d1
 800d748:	0800d7d1 	.word	0x0800d7d1
 800d74c:	0800d7d1 	.word	0x0800d7d1
 800d750:	0800d7d1 	.word	0x0800d7d1
 800d754:	0800d7d1 	.word	0x0800d7d1
 800d758:	0800d7d1 	.word	0x0800d7d1
 800d75c:	0800d7b9 	.word	0x0800d7b9
 800d760:	0800d7d1 	.word	0x0800d7d1
 800d764:	0800d7d1 	.word	0x0800d7d1
 800d768:	0800d7d1 	.word	0x0800d7d1
 800d76c:	0800d7d1 	.word	0x0800d7d1
 800d770:	0800d7d1 	.word	0x0800d7d1
 800d774:	0800d7d1 	.word	0x0800d7d1
 800d778:	0800d7d1 	.word	0x0800d7d1
 800d77c:	0800d7c1 	.word	0x0800d7c1
 800d780:	0800d7d1 	.word	0x0800d7d1
 800d784:	0800d7d1 	.word	0x0800d7d1
 800d788:	0800d7d1 	.word	0x0800d7d1
 800d78c:	0800d7d1 	.word	0x0800d7d1
 800d790:	0800d7d1 	.word	0x0800d7d1
 800d794:	0800d7d1 	.word	0x0800d7d1
 800d798:	0800d7d1 	.word	0x0800d7d1
 800d79c:	0800d7c9 	.word	0x0800d7c9
 800d7a0:	2301      	movs	r3, #1
 800d7a2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d7a6:	e0bc      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d7a8:	2304      	movs	r3, #4
 800d7aa:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d7ae:	e0b8      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d7b0:	2308      	movs	r3, #8
 800d7b2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d7b6:	e0b4      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d7b8:	2310      	movs	r3, #16
 800d7ba:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d7be:	e0b0      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d7c0:	2320      	movs	r3, #32
 800d7c2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d7c6:	e0ac      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d7c8:	2340      	movs	r3, #64	@ 0x40
 800d7ca:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d7ce:	e0a8      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d7d0:	2380      	movs	r3, #128	@ 0x80
 800d7d2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d7d6:	e0a4      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d7d8:	697b      	ldr	r3, [r7, #20]
 800d7da:	681b      	ldr	r3, [r3, #0]
 800d7dc:	4a8f      	ldr	r2, [pc, #572]	@ (800da1c <UART_SetConfig+0x6a0>)
 800d7de:	4293      	cmp	r3, r2
 800d7e0:	d130      	bne.n	800d844 <UART_SetConfig+0x4c8>
 800d7e2:	4b8d      	ldr	r3, [pc, #564]	@ (800da18 <UART_SetConfig+0x69c>)
 800d7e4:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800d7e6:	f003 0307 	and.w	r3, r3, #7
 800d7ea:	2b05      	cmp	r3, #5
 800d7ec:	d826      	bhi.n	800d83c <UART_SetConfig+0x4c0>
 800d7ee:	a201      	add	r2, pc, #4	@ (adr r2, 800d7f4 <UART_SetConfig+0x478>)
 800d7f0:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800d7f4:	0800d80d 	.word	0x0800d80d
 800d7f8:	0800d815 	.word	0x0800d815
 800d7fc:	0800d81d 	.word	0x0800d81d
 800d800:	0800d825 	.word	0x0800d825
 800d804:	0800d82d 	.word	0x0800d82d
 800d808:	0800d835 	.word	0x0800d835
 800d80c:	2300      	movs	r3, #0
 800d80e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d812:	e086      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d814:	2304      	movs	r3, #4
 800d816:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d81a:	e082      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d81c:	2308      	movs	r3, #8
 800d81e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d822:	e07e      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d824:	2310      	movs	r3, #16
 800d826:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d82a:	e07a      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d82c:	2320      	movs	r3, #32
 800d82e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d832:	e076      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d834:	2340      	movs	r3, #64	@ 0x40
 800d836:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d83a:	e072      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d83c:	2380      	movs	r3, #128	@ 0x80
 800d83e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d842:	e06e      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d844:	697b      	ldr	r3, [r7, #20]
 800d846:	681b      	ldr	r3, [r3, #0]
 800d848:	4a75      	ldr	r2, [pc, #468]	@ (800da20 <UART_SetConfig+0x6a4>)
 800d84a:	4293      	cmp	r3, r2
 800d84c:	d130      	bne.n	800d8b0 <UART_SetConfig+0x534>
 800d84e:	4b72      	ldr	r3, [pc, #456]	@ (800da18 <UART_SetConfig+0x69c>)
 800d850:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800d852:	f003 0307 	and.w	r3, r3, #7
 800d856:	2b05      	cmp	r3, #5
 800d858:	d826      	bhi.n	800d8a8 <UART_SetConfig+0x52c>
 800d85a:	a201      	add	r2, pc, #4	@ (adr r2, 800d860 <UART_SetConfig+0x4e4>)
 800d85c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800d860:	0800d879 	.word	0x0800d879
 800d864:	0800d881 	.word	0x0800d881
 800d868:	0800d889 	.word	0x0800d889
 800d86c:	0800d891 	.word	0x0800d891
 800d870:	0800d899 	.word	0x0800d899
 800d874:	0800d8a1 	.word	0x0800d8a1
 800d878:	2300      	movs	r3, #0
 800d87a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d87e:	e050      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d880:	2304      	movs	r3, #4
 800d882:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d886:	e04c      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d888:	2308      	movs	r3, #8
 800d88a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d88e:	e048      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d890:	2310      	movs	r3, #16
 800d892:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d896:	e044      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d898:	2320      	movs	r3, #32
 800d89a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d89e:	e040      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d8a0:	2340      	movs	r3, #64	@ 0x40
 800d8a2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d8a6:	e03c      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d8a8:	2380      	movs	r3, #128	@ 0x80
 800d8aa:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d8ae:	e038      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d8b0:	697b      	ldr	r3, [r7, #20]
 800d8b2:	681b      	ldr	r3, [r3, #0]
 800d8b4:	4a5b      	ldr	r2, [pc, #364]	@ (800da24 <UART_SetConfig+0x6a8>)
 800d8b6:	4293      	cmp	r3, r2
 800d8b8:	d130      	bne.n	800d91c <UART_SetConfig+0x5a0>
 800d8ba:	4b57      	ldr	r3, [pc, #348]	@ (800da18 <UART_SetConfig+0x69c>)
 800d8bc:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800d8be:	f003 0307 	and.w	r3, r3, #7
 800d8c2:	2b05      	cmp	r3, #5
 800d8c4:	d826      	bhi.n	800d914 <UART_SetConfig+0x598>
 800d8c6:	a201      	add	r2, pc, #4	@ (adr r2, 800d8cc <UART_SetConfig+0x550>)
 800d8c8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800d8cc:	0800d8e5 	.word	0x0800d8e5
 800d8d0:	0800d8ed 	.word	0x0800d8ed
 800d8d4:	0800d8f5 	.word	0x0800d8f5
 800d8d8:	0800d8fd 	.word	0x0800d8fd
 800d8dc:	0800d905 	.word	0x0800d905
 800d8e0:	0800d90d 	.word	0x0800d90d
 800d8e4:	2302      	movs	r3, #2
 800d8e6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d8ea:	e01a      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d8ec:	2304      	movs	r3, #4
 800d8ee:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d8f2:	e016      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d8f4:	2308      	movs	r3, #8
 800d8f6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d8fa:	e012      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d8fc:	2310      	movs	r3, #16
 800d8fe:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d902:	e00e      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d904:	2320      	movs	r3, #32
 800d906:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d90a:	e00a      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d90c:	2340      	movs	r3, #64	@ 0x40
 800d90e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d912:	e006      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d914:	2380      	movs	r3, #128	@ 0x80
 800d916:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 800d91a:	e002      	b.n	800d922 <UART_SetConfig+0x5a6>
 800d91c:	2380      	movs	r3, #128	@ 0x80
 800d91e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43

  /* Check LPUART instance */
  if (UART_INSTANCE_LOWPOWER(huart))
 800d922:	697b      	ldr	r3, [r7, #20]
 800d924:	681b      	ldr	r3, [r3, #0]
 800d926:	4a3f      	ldr	r2, [pc, #252]	@ (800da24 <UART_SetConfig+0x6a8>)
 800d928:	4293      	cmp	r3, r2
 800d92a:	f040 80f8 	bne.w	800db1e <UART_SetConfig+0x7a2>
  {
    /* Retrieve frequency clock */
    switch (clocksource)
 800d92e:	f897 3043 	ldrb.w	r3, [r7, #67]	@ 0x43
 800d932:	2b20      	cmp	r3, #32
 800d934:	dc46      	bgt.n	800d9c4 <UART_SetConfig+0x648>
 800d936:	2b02      	cmp	r3, #2
 800d938:	f2c0 8082 	blt.w	800da40 <UART_SetConfig+0x6c4>
 800d93c:	3b02      	subs	r3, #2
 800d93e:	2b1e      	cmp	r3, #30
 800d940:	d87e      	bhi.n	800da40 <UART_SetConfig+0x6c4>
 800d942:	a201      	add	r2, pc, #4	@ (adr r2, 800d948 <UART_SetConfig+0x5cc>)
 800d944:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800d948:	0800d9cb 	.word	0x0800d9cb
 800d94c:	0800da41 	.word	0x0800da41
 800d950:	0800d9d3 	.word	0x0800d9d3
 800d954:	0800da41 	.word	0x0800da41
 800d958:	0800da41 	.word	0x0800da41
 800d95c:	0800da41 	.word	0x0800da41
 800d960:	0800d9e3 	.word	0x0800d9e3
 800d964:	0800da41 	.word	0x0800da41
 800d968:	0800da41 	.word	0x0800da41
 800d96c:	0800da41 	.word	0x0800da41
 800d970:	0800da41 	.word	0x0800da41
 800d974:	0800da41 	.word	0x0800da41
 800d978:	0800da41 	.word	0x0800da41
 800d97c:	0800da41 	.word	0x0800da41
 800d980:	0800d9f3 	.word	0x0800d9f3
 800d984:	0800da41 	.word	0x0800da41
 800d988:	0800da41 	.word	0x0800da41
 800d98c:	0800da41 	.word	0x0800da41
 800d990:	0800da41 	.word	0x0800da41
 800d994:	0800da41 	.word	0x0800da41
 800d998:	0800da41 	.word	0x0800da41
 800d99c:	0800da41 	.word	0x0800da41
 800d9a0:	0800da41 	.word	0x0800da41
 800d9a4:	0800da41 	.word	0x0800da41
 800d9a8:	0800da41 	.word	0x0800da41
 800d9ac:	0800da41 	.word	0x0800da41
 800d9b0:	0800da41 	.word	0x0800da41
 800d9b4:	0800da41 	.word	0x0800da41
 800d9b8:	0800da41 	.word	0x0800da41
 800d9bc:	0800da41 	.word	0x0800da41
 800d9c0:	0800da33 	.word	0x0800da33
 800d9c4:	2b40      	cmp	r3, #64	@ 0x40
 800d9c6:	d037      	beq.n	800da38 <UART_SetConfig+0x6bc>
 800d9c8:	e03a      	b.n	800da40 <UART_SetConfig+0x6c4>
    {
      case UART_CLOCKSOURCE_D3PCLK1:
        pclk = HAL_RCCEx_GetD3PCLK1Freq();
 800d9ca:	f7fd fd01 	bl	800b3d0 <HAL_RCCEx_GetD3PCLK1Freq>
 800d9ce:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 800d9d0:	e03c      	b.n	800da4c <UART_SetConfig+0x6d0>
      case UART_CLOCKSOURCE_PLL2:
        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800d9d2:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800d9d6:	4618      	mov	r0, r3
 800d9d8:	f7fd fd10 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
        pclk = pll2_clocks.PLL2_Q_Frequency;
 800d9dc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800d9de:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d9e0:	e034      	b.n	800da4c <UART_SetConfig+0x6d0>
      case UART_CLOCKSOURCE_PLL3:
        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800d9e2:	f107 0318 	add.w	r3, r7, #24
 800d9e6:	4618      	mov	r0, r3
 800d9e8:	f7fd fe5c 	bl	800b6a4 <HAL_RCCEx_GetPLL3ClockFreq>
        pclk = pll3_clocks.PLL3_Q_Frequency;
 800d9ec:	69fb      	ldr	r3, [r7, #28]
 800d9ee:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d9f0:	e02c      	b.n	800da4c <UART_SetConfig+0x6d0>
      case UART_CLOCKSOURCE_HSI:
        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 800d9f2:	4b09      	ldr	r3, [pc, #36]	@ (800da18 <UART_SetConfig+0x69c>)
 800d9f4:	681b      	ldr	r3, [r3, #0]
 800d9f6:	f003 0320 	and.w	r3, r3, #32
 800d9fa:	2b00      	cmp	r3, #0
 800d9fc:	d016      	beq.n	800da2c <UART_SetConfig+0x6b0>
        {
          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
 800d9fe:	4b06      	ldr	r3, [pc, #24]	@ (800da18 <UART_SetConfig+0x69c>)
 800da00:	681b      	ldr	r3, [r3, #0]
 800da02:	08db      	lsrs	r3, r3, #3
 800da04:	f003 0303 	and.w	r3, r3, #3
 800da08:	4a07      	ldr	r2, [pc, #28]	@ (800da28 <UART_SetConfig+0x6ac>)
 800da0a:	fa22 f303 	lsr.w	r3, r2, r3
 800da0e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          pclk = (uint32_t) HSI_VALUE;
        }
        break;
 800da10:	e01c      	b.n	800da4c <UART_SetConfig+0x6d0>
 800da12:	bf00      	nop
 800da14:	40011400 	.word	0x40011400
 800da18:	58024400 	.word	0x58024400
 800da1c:	40007800 	.word	0x40007800
 800da20:	40007c00 	.word	0x40007c00
 800da24:	58000c00 	.word	0x58000c00
 800da28:	03d09000 	.word	0x03d09000
          pclk = (uint32_t) HSI_VALUE;
 800da2c:	4b9d      	ldr	r3, [pc, #628]	@ (800dca4 <UART_SetConfig+0x928>)
 800da2e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800da30:	e00c      	b.n	800da4c <UART_SetConfig+0x6d0>
      case UART_CLOCKSOURCE_CSI:
        pclk = (uint32_t) CSI_VALUE;
 800da32:	4b9d      	ldr	r3, [pc, #628]	@ (800dca8 <UART_SetConfig+0x92c>)
 800da34:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800da36:	e009      	b.n	800da4c <UART_SetConfig+0x6d0>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 800da38:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 800da3c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800da3e:	e005      	b.n	800da4c <UART_SetConfig+0x6d0>
      default:
        pclk = 0U;
 800da40:	2300      	movs	r3, #0
 800da42:	63fb      	str	r3, [r7, #60]	@ 0x3c
        ret = HAL_ERROR;
 800da44:	2301      	movs	r3, #1
 800da46:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
        break;
 800da4a:	bf00      	nop
    }

    /* If proper clock source reported */
    if (pclk != 0U)
 800da4c:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800da4e:	2b00      	cmp	r3, #0
 800da50:	f000 81de 	beq.w	800de10 <UART_SetConfig+0xa94>
    {
      /* Compute clock after Prescaler */
      lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
 800da54:	697b      	ldr	r3, [r7, #20]
 800da56:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800da58:	4a94      	ldr	r2, [pc, #592]	@ (800dcac <UART_SetConfig+0x930>)
 800da5a:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
 800da5e:	461a      	mov	r2, r3
 800da60:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800da62:	fbb3 f3f2 	udiv	r3, r3, r2
 800da66:	633b      	str	r3, [r7, #48]	@ 0x30

      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
 800da68:	697b      	ldr	r3, [r7, #20]
 800da6a:	685a      	ldr	r2, [r3, #4]
 800da6c:	4613      	mov	r3, r2
 800da6e:	005b      	lsls	r3, r3, #1
 800da70:	4413      	add	r3, r2
 800da72:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 800da74:	429a      	cmp	r2, r3
 800da76:	d305      	bcc.n	800da84 <UART_SetConfig+0x708>
          (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
 800da78:	697b      	ldr	r3, [r7, #20]
 800da7a:	685b      	ldr	r3, [r3, #4]
 800da7c:	031b      	lsls	r3, r3, #12
      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
 800da7e:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 800da80:	429a      	cmp	r2, r3
 800da82:	d903      	bls.n	800da8c <UART_SetConfig+0x710>
      {
        ret = HAL_ERROR;
 800da84:	2301      	movs	r3, #1
 800da86:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
 800da8a:	e1c1      	b.n	800de10 <UART_SetConfig+0xa94>
      }
      else
      {
        /* Check computed UsartDiv value is in allocated range
           (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
 800da8c:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800da8e:	2200      	movs	r2, #0
 800da90:	60bb      	str	r3, [r7, #8]
 800da92:	60fa      	str	r2, [r7, #12]
 800da94:	697b      	ldr	r3, [r7, #20]
 800da96:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800da98:	4a84      	ldr	r2, [pc, #528]	@ (800dcac <UART_SetConfig+0x930>)
 800da9a:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
 800da9e:	b29b      	uxth	r3, r3
 800daa0:	2200      	movs	r2, #0
 800daa2:	603b      	str	r3, [r7, #0]
 800daa4:	607a      	str	r2, [r7, #4]
 800daa6:	e9d7 2300 	ldrd	r2, r3, [r7]
 800daaa:	e9d7 0102 	ldrd	r0, r1, [r7, #8]
 800daae:	f7f2 fc67 	bl	8000380 <__aeabi_uldivmod>
 800dab2:	4602      	mov	r2, r0
 800dab4:	460b      	mov	r3, r1
 800dab6:	4610      	mov	r0, r2
 800dab8:	4619      	mov	r1, r3
 800daba:	f04f 0200 	mov.w	r2, #0
 800dabe:	f04f 0300 	mov.w	r3, #0
 800dac2:	020b      	lsls	r3, r1, #8
 800dac4:	ea43 6310 	orr.w	r3, r3, r0, lsr #24
 800dac8:	0202      	lsls	r2, r0, #8
 800daca:	6979      	ldr	r1, [r7, #20]
 800dacc:	6849      	ldr	r1, [r1, #4]
 800dace:	0849      	lsrs	r1, r1, #1
 800dad0:	2000      	movs	r0, #0
 800dad2:	460c      	mov	r4, r1
 800dad4:	4605      	mov	r5, r0
 800dad6:	eb12 0804 	adds.w	r8, r2, r4
 800dada:	eb43 0905 	adc.w	r9, r3, r5
 800dade:	697b      	ldr	r3, [r7, #20]
 800dae0:	685b      	ldr	r3, [r3, #4]
 800dae2:	2200      	movs	r2, #0
 800dae4:	469a      	mov	sl, r3
 800dae6:	4693      	mov	fp, r2
 800dae8:	4652      	mov	r2, sl
 800daea:	465b      	mov	r3, fp
 800daec:	4640      	mov	r0, r8
 800daee:	4649      	mov	r1, r9
 800daf0:	f7f2 fc46 	bl	8000380 <__aeabi_uldivmod>
 800daf4:	4602      	mov	r2, r0
 800daf6:	460b      	mov	r3, r1
 800daf8:	4613      	mov	r3, r2
 800dafa:	63bb      	str	r3, [r7, #56]	@ 0x38
        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
 800dafc:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dafe:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 800db02:	d308      	bcc.n	800db16 <UART_SetConfig+0x79a>
 800db04:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800db06:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 800db0a:	d204      	bcs.n	800db16 <UART_SetConfig+0x79a>
        {
          huart->Instance->BRR = usartdiv;
 800db0c:	697b      	ldr	r3, [r7, #20]
 800db0e:	681b      	ldr	r3, [r3, #0]
 800db10:	6bba      	ldr	r2, [r7, #56]	@ 0x38
 800db12:	60da      	str	r2, [r3, #12]
 800db14:	e17c      	b.n	800de10 <UART_SetConfig+0xa94>
        }
        else
        {
          ret = HAL_ERROR;
 800db16:	2301      	movs	r3, #1
 800db18:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
 800db1c:	e178      	b.n	800de10 <UART_SetConfig+0xa94>
      } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
                (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
    } /* if (pclk != 0) */
  }
  /* Check UART Over Sampling to set Baud Rate Register */
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 800db1e:	697b      	ldr	r3, [r7, #20]
 800db20:	69db      	ldr	r3, [r3, #28]
 800db22:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
 800db26:	f040 80c5 	bne.w	800dcb4 <UART_SetConfig+0x938>
  {
    switch (clocksource)
 800db2a:	f897 3043 	ldrb.w	r3, [r7, #67]	@ 0x43
 800db2e:	2b20      	cmp	r3, #32
 800db30:	dc48      	bgt.n	800dbc4 <UART_SetConfig+0x848>
 800db32:	2b00      	cmp	r3, #0
 800db34:	db7b      	blt.n	800dc2e <UART_SetConfig+0x8b2>
 800db36:	2b20      	cmp	r3, #32
 800db38:	d879      	bhi.n	800dc2e <UART_SetConfig+0x8b2>
 800db3a:	a201      	add	r2, pc, #4	@ (adr r2, 800db40 <UART_SetConfig+0x7c4>)
 800db3c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800db40:	0800dbcb 	.word	0x0800dbcb
 800db44:	0800dbd3 	.word	0x0800dbd3
 800db48:	0800dc2f 	.word	0x0800dc2f
 800db4c:	0800dc2f 	.word	0x0800dc2f
 800db50:	0800dbdb 	.word	0x0800dbdb
 800db54:	0800dc2f 	.word	0x0800dc2f
 800db58:	0800dc2f 	.word	0x0800dc2f
 800db5c:	0800dc2f 	.word	0x0800dc2f
 800db60:	0800dbeb 	.word	0x0800dbeb
 800db64:	0800dc2f 	.word	0x0800dc2f
 800db68:	0800dc2f 	.word	0x0800dc2f
 800db6c:	0800dc2f 	.word	0x0800dc2f
 800db70:	0800dc2f 	.word	0x0800dc2f
 800db74:	0800dc2f 	.word	0x0800dc2f
 800db78:	0800dc2f 	.word	0x0800dc2f
 800db7c:	0800dc2f 	.word	0x0800dc2f
 800db80:	0800dbfb 	.word	0x0800dbfb
 800db84:	0800dc2f 	.word	0x0800dc2f
 800db88:	0800dc2f 	.word	0x0800dc2f
 800db8c:	0800dc2f 	.word	0x0800dc2f
 800db90:	0800dc2f 	.word	0x0800dc2f
 800db94:	0800dc2f 	.word	0x0800dc2f
 800db98:	0800dc2f 	.word	0x0800dc2f
 800db9c:	0800dc2f 	.word	0x0800dc2f
 800dba0:	0800dc2f 	.word	0x0800dc2f
 800dba4:	0800dc2f 	.word	0x0800dc2f
 800dba8:	0800dc2f 	.word	0x0800dc2f
 800dbac:	0800dc2f 	.word	0x0800dc2f
 800dbb0:	0800dc2f 	.word	0x0800dc2f
 800dbb4:	0800dc2f 	.word	0x0800dc2f
 800dbb8:	0800dc2f 	.word	0x0800dc2f
 800dbbc:	0800dc2f 	.word	0x0800dc2f
 800dbc0:	0800dc21 	.word	0x0800dc21
 800dbc4:	2b40      	cmp	r3, #64	@ 0x40
 800dbc6:	d02e      	beq.n	800dc26 <UART_SetConfig+0x8aa>
 800dbc8:	e031      	b.n	800dc2e <UART_SetConfig+0x8b2>
    {
      case UART_CLOCKSOURCE_D2PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 800dbca:	f7fb fc25 	bl	8009418 <HAL_RCC_GetPCLK1Freq>
 800dbce:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 800dbd0:	e033      	b.n	800dc3a <UART_SetConfig+0x8be>
      case UART_CLOCKSOURCE_D2PCLK2:
        pclk = HAL_RCC_GetPCLK2Freq();
 800dbd2:	f7fb fc37 	bl	8009444 <HAL_RCC_GetPCLK2Freq>
 800dbd6:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 800dbd8:	e02f      	b.n	800dc3a <UART_SetConfig+0x8be>
      case UART_CLOCKSOURCE_PLL2:
        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800dbda:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800dbde:	4618      	mov	r0, r3
 800dbe0:	f7fd fc0c 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
        pclk = pll2_clocks.PLL2_Q_Frequency;
 800dbe4:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800dbe6:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dbe8:	e027      	b.n	800dc3a <UART_SetConfig+0x8be>
      case UART_CLOCKSOURCE_PLL3:
        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800dbea:	f107 0318 	add.w	r3, r7, #24
 800dbee:	4618      	mov	r0, r3
 800dbf0:	f7fd fd58 	bl	800b6a4 <HAL_RCCEx_GetPLL3ClockFreq>
        pclk = pll3_clocks.PLL3_Q_Frequency;
 800dbf4:	69fb      	ldr	r3, [r7, #28]
 800dbf6:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dbf8:	e01f      	b.n	800dc3a <UART_SetConfig+0x8be>
      case UART_CLOCKSOURCE_HSI:
        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 800dbfa:	4b2d      	ldr	r3, [pc, #180]	@ (800dcb0 <UART_SetConfig+0x934>)
 800dbfc:	681b      	ldr	r3, [r3, #0]
 800dbfe:	f003 0320 	and.w	r3, r3, #32
 800dc02:	2b00      	cmp	r3, #0
 800dc04:	d009      	beq.n	800dc1a <UART_SetConfig+0x89e>
        {
          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
 800dc06:	4b2a      	ldr	r3, [pc, #168]	@ (800dcb0 <UART_SetConfig+0x934>)
 800dc08:	681b      	ldr	r3, [r3, #0]
 800dc0a:	08db      	lsrs	r3, r3, #3
 800dc0c:	f003 0303 	and.w	r3, r3, #3
 800dc10:	4a24      	ldr	r2, [pc, #144]	@ (800dca4 <UART_SetConfig+0x928>)
 800dc12:	fa22 f303 	lsr.w	r3, r2, r3
 800dc16:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          pclk = (uint32_t) HSI_VALUE;
        }
        break;
 800dc18:	e00f      	b.n	800dc3a <UART_SetConfig+0x8be>
          pclk = (uint32_t) HSI_VALUE;
 800dc1a:	4b22      	ldr	r3, [pc, #136]	@ (800dca4 <UART_SetConfig+0x928>)
 800dc1c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dc1e:	e00c      	b.n	800dc3a <UART_SetConfig+0x8be>
      case UART_CLOCKSOURCE_CSI:
        pclk = (uint32_t) CSI_VALUE;
 800dc20:	4b21      	ldr	r3, [pc, #132]	@ (800dca8 <UART_SetConfig+0x92c>)
 800dc22:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dc24:	e009      	b.n	800dc3a <UART_SetConfig+0x8be>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 800dc26:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 800dc2a:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dc2c:	e005      	b.n	800dc3a <UART_SetConfig+0x8be>
      default:
        pclk = 0U;
 800dc2e:	2300      	movs	r3, #0
 800dc30:	63fb      	str	r3, [r7, #60]	@ 0x3c
        ret = HAL_ERROR;
 800dc32:	2301      	movs	r3, #1
 800dc34:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
        break;
 800dc38:	bf00      	nop
    }

    /* USARTDIV must be greater than or equal to 0d16 */
    if (pclk != 0U)
 800dc3a:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800dc3c:	2b00      	cmp	r3, #0
 800dc3e:	f000 80e7 	beq.w	800de10 <UART_SetConfig+0xa94>
    {
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
 800dc42:	697b      	ldr	r3, [r7, #20]
 800dc44:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800dc46:	4a19      	ldr	r2, [pc, #100]	@ (800dcac <UART_SetConfig+0x930>)
 800dc48:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
 800dc4c:	461a      	mov	r2, r3
 800dc4e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800dc50:	fbb3 f3f2 	udiv	r3, r3, r2
 800dc54:	005a      	lsls	r2, r3, #1
 800dc56:	697b      	ldr	r3, [r7, #20]
 800dc58:	685b      	ldr	r3, [r3, #4]
 800dc5a:	085b      	lsrs	r3, r3, #1
 800dc5c:	441a      	add	r2, r3
 800dc5e:	697b      	ldr	r3, [r7, #20]
 800dc60:	685b      	ldr	r3, [r3, #4]
 800dc62:	fbb2 f3f3 	udiv	r3, r2, r3
 800dc66:	63bb      	str	r3, [r7, #56]	@ 0x38
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 800dc68:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc6a:	2b0f      	cmp	r3, #15
 800dc6c:	d916      	bls.n	800dc9c <UART_SetConfig+0x920>
 800dc6e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc70:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800dc74:	d212      	bcs.n	800dc9c <UART_SetConfig+0x920>
      {
        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
 800dc76:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc78:	b29b      	uxth	r3, r3
 800dc7a:	f023 030f 	bic.w	r3, r3, #15
 800dc7e:	86fb      	strh	r3, [r7, #54]	@ 0x36
        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
 800dc80:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc82:	085b      	lsrs	r3, r3, #1
 800dc84:	b29b      	uxth	r3, r3
 800dc86:	f003 0307 	and.w	r3, r3, #7
 800dc8a:	b29a      	uxth	r2, r3
 800dc8c:	8efb      	ldrh	r3, [r7, #54]	@ 0x36
 800dc8e:	4313      	orrs	r3, r2
 800dc90:	86fb      	strh	r3, [r7, #54]	@ 0x36
        huart->Instance->BRR = brrtemp;
 800dc92:	697b      	ldr	r3, [r7, #20]
 800dc94:	681b      	ldr	r3, [r3, #0]
 800dc96:	8efa      	ldrh	r2, [r7, #54]	@ 0x36
 800dc98:	60da      	str	r2, [r3, #12]
 800dc9a:	e0b9      	b.n	800de10 <UART_SetConfig+0xa94>
      }
      else
      {
        ret = HAL_ERROR;
 800dc9c:	2301      	movs	r3, #1
 800dc9e:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
 800dca2:	e0b5      	b.n	800de10 <UART_SetConfig+0xa94>
 800dca4:	03d09000 	.word	0x03d09000
 800dca8:	003d0900 	.word	0x003d0900
 800dcac:	080145fc 	.word	0x080145fc
 800dcb0:	58024400 	.word	0x58024400
      }
    }
  }
  else
  {
    switch (clocksource)
 800dcb4:	f897 3043 	ldrb.w	r3, [r7, #67]	@ 0x43
 800dcb8:	2b20      	cmp	r3, #32
 800dcba:	dc49      	bgt.n	800dd50 <UART_SetConfig+0x9d4>
 800dcbc:	2b00      	cmp	r3, #0
 800dcbe:	db7c      	blt.n	800ddba <UART_SetConfig+0xa3e>
 800dcc0:	2b20      	cmp	r3, #32
 800dcc2:	d87a      	bhi.n	800ddba <UART_SetConfig+0xa3e>
 800dcc4:	a201      	add	r2, pc, #4	@ (adr r2, 800dccc <UART_SetConfig+0x950>)
 800dcc6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800dcca:	bf00      	nop
 800dccc:	0800dd57 	.word	0x0800dd57
 800dcd0:	0800dd5f 	.word	0x0800dd5f
 800dcd4:	0800ddbb 	.word	0x0800ddbb
 800dcd8:	0800ddbb 	.word	0x0800ddbb
 800dcdc:	0800dd67 	.word	0x0800dd67
 800dce0:	0800ddbb 	.word	0x0800ddbb
 800dce4:	0800ddbb 	.word	0x0800ddbb
 800dce8:	0800ddbb 	.word	0x0800ddbb
 800dcec:	0800dd77 	.word	0x0800dd77
 800dcf0:	0800ddbb 	.word	0x0800ddbb
 800dcf4:	0800ddbb 	.word	0x0800ddbb
 800dcf8:	0800ddbb 	.word	0x0800ddbb
 800dcfc:	0800ddbb 	.word	0x0800ddbb
 800dd00:	0800ddbb 	.word	0x0800ddbb
 800dd04:	0800ddbb 	.word	0x0800ddbb
 800dd08:	0800ddbb 	.word	0x0800ddbb
 800dd0c:	0800dd87 	.word	0x0800dd87
 800dd10:	0800ddbb 	.word	0x0800ddbb
 800dd14:	0800ddbb 	.word	0x0800ddbb
 800dd18:	0800ddbb 	.word	0x0800ddbb
 800dd1c:	0800ddbb 	.word	0x0800ddbb
 800dd20:	0800ddbb 	.word	0x0800ddbb
 800dd24:	0800ddbb 	.word	0x0800ddbb
 800dd28:	0800ddbb 	.word	0x0800ddbb
 800dd2c:	0800ddbb 	.word	0x0800ddbb
 800dd30:	0800ddbb 	.word	0x0800ddbb
 800dd34:	0800ddbb 	.word	0x0800ddbb
 800dd38:	0800ddbb 	.word	0x0800ddbb
 800dd3c:	0800ddbb 	.word	0x0800ddbb
 800dd40:	0800ddbb 	.word	0x0800ddbb
 800dd44:	0800ddbb 	.word	0x0800ddbb
 800dd48:	0800ddbb 	.word	0x0800ddbb
 800dd4c:	0800ddad 	.word	0x0800ddad
 800dd50:	2b40      	cmp	r3, #64	@ 0x40
 800dd52:	d02e      	beq.n	800ddb2 <UART_SetConfig+0xa36>
 800dd54:	e031      	b.n	800ddba <UART_SetConfig+0xa3e>
    {
      case UART_CLOCKSOURCE_D2PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 800dd56:	f7fb fb5f 	bl	8009418 <HAL_RCC_GetPCLK1Freq>
 800dd5a:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 800dd5c:	e033      	b.n	800ddc6 <UART_SetConfig+0xa4a>
      case UART_CLOCKSOURCE_D2PCLK2:
        pclk = HAL_RCC_GetPCLK2Freq();
 800dd5e:	f7fb fb71 	bl	8009444 <HAL_RCC_GetPCLK2Freq>
 800dd62:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 800dd64:	e02f      	b.n	800ddc6 <UART_SetConfig+0xa4a>
      case UART_CLOCKSOURCE_PLL2:
        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800dd66:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800dd6a:	4618      	mov	r0, r3
 800dd6c:	f7fd fb46 	bl	800b3fc <HAL_RCCEx_GetPLL2ClockFreq>
        pclk = pll2_clocks.PLL2_Q_Frequency;
 800dd70:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800dd72:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dd74:	e027      	b.n	800ddc6 <UART_SetConfig+0xa4a>
      case UART_CLOCKSOURCE_PLL3:
        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800dd76:	f107 0318 	add.w	r3, r7, #24
 800dd7a:	4618      	mov	r0, r3
 800dd7c:	f7fd fc92 	bl	800b6a4 <HAL_RCCEx_GetPLL3ClockFreq>
        pclk = pll3_clocks.PLL3_Q_Frequency;
 800dd80:	69fb      	ldr	r3, [r7, #28]
 800dd82:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dd84:	e01f      	b.n	800ddc6 <UART_SetConfig+0xa4a>
      case UART_CLOCKSOURCE_HSI:
        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 800dd86:	4b2d      	ldr	r3, [pc, #180]	@ (800de3c <UART_SetConfig+0xac0>)
 800dd88:	681b      	ldr	r3, [r3, #0]
 800dd8a:	f003 0320 	and.w	r3, r3, #32
 800dd8e:	2b00      	cmp	r3, #0
 800dd90:	d009      	beq.n	800dda6 <UART_SetConfig+0xa2a>
        {
          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
 800dd92:	4b2a      	ldr	r3, [pc, #168]	@ (800de3c <UART_SetConfig+0xac0>)
 800dd94:	681b      	ldr	r3, [r3, #0]
 800dd96:	08db      	lsrs	r3, r3, #3
 800dd98:	f003 0303 	and.w	r3, r3, #3
 800dd9c:	4a28      	ldr	r2, [pc, #160]	@ (800de40 <UART_SetConfig+0xac4>)
 800dd9e:	fa22 f303 	lsr.w	r3, r2, r3
 800dda2:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          pclk = (uint32_t) HSI_VALUE;
        }
        break;
 800dda4:	e00f      	b.n	800ddc6 <UART_SetConfig+0xa4a>
          pclk = (uint32_t) HSI_VALUE;
 800dda6:	4b26      	ldr	r3, [pc, #152]	@ (800de40 <UART_SetConfig+0xac4>)
 800dda8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ddaa:	e00c      	b.n	800ddc6 <UART_SetConfig+0xa4a>
      case UART_CLOCKSOURCE_CSI:
        pclk = (uint32_t) CSI_VALUE;
 800ddac:	4b25      	ldr	r3, [pc, #148]	@ (800de44 <UART_SetConfig+0xac8>)
 800ddae:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ddb0:	e009      	b.n	800ddc6 <UART_SetConfig+0xa4a>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 800ddb2:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 800ddb6:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ddb8:	e005      	b.n	800ddc6 <UART_SetConfig+0xa4a>
      default:
        pclk = 0U;
 800ddba:	2300      	movs	r3, #0
 800ddbc:	63fb      	str	r3, [r7, #60]	@ 0x3c
        ret = HAL_ERROR;
 800ddbe:	2301      	movs	r3, #1
 800ddc0:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
        break;
 800ddc4:	bf00      	nop
    }

    if (pclk != 0U)
 800ddc6:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800ddc8:	2b00      	cmp	r3, #0
 800ddca:	d021      	beq.n	800de10 <UART_SetConfig+0xa94>
    {
      /* USARTDIV must be greater than or equal to 0d16 */
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
 800ddcc:	697b      	ldr	r3, [r7, #20]
 800ddce:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800ddd0:	4a1d      	ldr	r2, [pc, #116]	@ (800de48 <UART_SetConfig+0xacc>)
 800ddd2:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
 800ddd6:	461a      	mov	r2, r3
 800ddd8:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800ddda:	fbb3 f2f2 	udiv	r2, r3, r2
 800ddde:	697b      	ldr	r3, [r7, #20]
 800dde0:	685b      	ldr	r3, [r3, #4]
 800dde2:	085b      	lsrs	r3, r3, #1
 800dde4:	441a      	add	r2, r3
 800dde6:	697b      	ldr	r3, [r7, #20]
 800dde8:	685b      	ldr	r3, [r3, #4]
 800ddea:	fbb2 f3f3 	udiv	r3, r2, r3
 800ddee:	63bb      	str	r3, [r7, #56]	@ 0x38
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 800ddf0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800ddf2:	2b0f      	cmp	r3, #15
 800ddf4:	d909      	bls.n	800de0a <UART_SetConfig+0xa8e>
 800ddf6:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800ddf8:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800ddfc:	d205      	bcs.n	800de0a <UART_SetConfig+0xa8e>
      {
        huart->Instance->BRR = (uint16_t)usartdiv;
 800ddfe:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800de00:	b29a      	uxth	r2, r3
 800de02:	697b      	ldr	r3, [r7, #20]
 800de04:	681b      	ldr	r3, [r3, #0]
 800de06:	60da      	str	r2, [r3, #12]
 800de08:	e002      	b.n	800de10 <UART_SetConfig+0xa94>
      }
      else
      {
        ret = HAL_ERROR;
 800de0a:	2301      	movs	r3, #1
 800de0c:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
      }
    }
  }

  /* Initialize the number of data to process during RX/TX ISR execution */
  huart->NbTxDataToProcess = 1;
 800de10:	697b      	ldr	r3, [r7, #20]
 800de12:	2201      	movs	r2, #1
 800de14:	f8a3 206a 	strh.w	r2, [r3, #106]	@ 0x6a
  huart->NbRxDataToProcess = 1;
 800de18:	697b      	ldr	r3, [r7, #20]
 800de1a:	2201      	movs	r2, #1
 800de1c:	f8a3 2068 	strh.w	r2, [r3, #104]	@ 0x68

  /* Clear ISR function pointers */
  huart->RxISR = NULL;
 800de20:	697b      	ldr	r3, [r7, #20]
 800de22:	2200      	movs	r2, #0
 800de24:	675a      	str	r2, [r3, #116]	@ 0x74
  huart->TxISR = NULL;
 800de26:	697b      	ldr	r3, [r7, #20]
 800de28:	2200      	movs	r2, #0
 800de2a:	679a      	str	r2, [r3, #120]	@ 0x78

  return ret;
 800de2c:	f897 3042 	ldrb.w	r3, [r7, #66]	@ 0x42
}
 800de30:	4618      	mov	r0, r3
 800de32:	3748      	adds	r7, #72	@ 0x48
 800de34:	46bd      	mov	sp, r7
 800de36:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 800de3a:	bf00      	nop
 800de3c:	58024400 	.word	0x58024400
 800de40:	03d09000 	.word	0x03d09000
 800de44:	003d0900 	.word	0x003d0900
 800de48:	080145fc 	.word	0x080145fc

0800de4c <UART_AdvFeatureConfig>:
  * @brief Configure the UART peripheral advanced features.
  * @param huart UART handle.
  * @retval None
  */
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
 800de4c:	b480      	push	{r7}
 800de4e:	b083      	sub	sp, #12
 800de50:	af00      	add	r7, sp, #0
 800de52:	6078      	str	r0, [r7, #4]
  /* Check whether the set of advanced features to configure is properly set */
  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));

  /* if required, configure RX/TX pins swap */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
 800de54:	687b      	ldr	r3, [r7, #4]
 800de56:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800de58:	f003 0308 	and.w	r3, r3, #8
 800de5c:	2b00      	cmp	r3, #0
 800de5e:	d00a      	beq.n	800de76 <UART_AdvFeatureConfig+0x2a>
  {
    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
 800de60:	687b      	ldr	r3, [r7, #4]
 800de62:	681b      	ldr	r3, [r3, #0]
 800de64:	685b      	ldr	r3, [r3, #4]
 800de66:	f423 4100 	bic.w	r1, r3, #32768	@ 0x8000
 800de6a:	687b      	ldr	r3, [r7, #4]
 800de6c:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 800de6e:	687b      	ldr	r3, [r7, #4]
 800de70:	681b      	ldr	r3, [r3, #0]
 800de72:	430a      	orrs	r2, r1
 800de74:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure TX pin active level inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
 800de76:	687b      	ldr	r3, [r7, #4]
 800de78:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800de7a:	f003 0301 	and.w	r3, r3, #1
 800de7e:	2b00      	cmp	r3, #0
 800de80:	d00a      	beq.n	800de98 <UART_AdvFeatureConfig+0x4c>
  {
    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
 800de82:	687b      	ldr	r3, [r7, #4]
 800de84:	681b      	ldr	r3, [r3, #0]
 800de86:	685b      	ldr	r3, [r3, #4]
 800de88:	f423 3100 	bic.w	r1, r3, #131072	@ 0x20000
 800de8c:	687b      	ldr	r3, [r7, #4]
 800de8e:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 800de90:	687b      	ldr	r3, [r7, #4]
 800de92:	681b      	ldr	r3, [r3, #0]
 800de94:	430a      	orrs	r2, r1
 800de96:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX pin active level inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
 800de98:	687b      	ldr	r3, [r7, #4]
 800de9a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800de9c:	f003 0302 	and.w	r3, r3, #2
 800dea0:	2b00      	cmp	r3, #0
 800dea2:	d00a      	beq.n	800deba <UART_AdvFeatureConfig+0x6e>
  {
    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
 800dea4:	687b      	ldr	r3, [r7, #4]
 800dea6:	681b      	ldr	r3, [r3, #0]
 800dea8:	685b      	ldr	r3, [r3, #4]
 800deaa:	f423 3180 	bic.w	r1, r3, #65536	@ 0x10000
 800deae:	687b      	ldr	r3, [r7, #4]
 800deb0:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
 800deb2:	687b      	ldr	r3, [r7, #4]
 800deb4:	681b      	ldr	r3, [r3, #0]
 800deb6:	430a      	orrs	r2, r1
 800deb8:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure data inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
 800deba:	687b      	ldr	r3, [r7, #4]
 800debc:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800debe:	f003 0304 	and.w	r3, r3, #4
 800dec2:	2b00      	cmp	r3, #0
 800dec4:	d00a      	beq.n	800dedc <UART_AdvFeatureConfig+0x90>
  {
    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
 800dec6:	687b      	ldr	r3, [r7, #4]
 800dec8:	681b      	ldr	r3, [r3, #0]
 800deca:	685b      	ldr	r3, [r3, #4]
 800decc:	f423 2180 	bic.w	r1, r3, #262144	@ 0x40000
 800ded0:	687b      	ldr	r3, [r7, #4]
 800ded2:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 800ded4:	687b      	ldr	r3, [r7, #4]
 800ded6:	681b      	ldr	r3, [r3, #0]
 800ded8:	430a      	orrs	r2, r1
 800deda:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX overrun detection disabling */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
 800dedc:	687b      	ldr	r3, [r7, #4]
 800dede:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800dee0:	f003 0310 	and.w	r3, r3, #16
 800dee4:	2b00      	cmp	r3, #0
 800dee6:	d00a      	beq.n	800defe <UART_AdvFeatureConfig+0xb2>
  {
    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
 800dee8:	687b      	ldr	r3, [r7, #4]
 800deea:	681b      	ldr	r3, [r3, #0]
 800deec:	689b      	ldr	r3, [r3, #8]
 800deee:	f423 5180 	bic.w	r1, r3, #4096	@ 0x1000
 800def2:	687b      	ldr	r3, [r7, #4]
 800def4:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 800def6:	687b      	ldr	r3, [r7, #4]
 800def8:	681b      	ldr	r3, [r3, #0]
 800defa:	430a      	orrs	r2, r1
 800defc:	609a      	str	r2, [r3, #8]
  }

  /* if required, configure DMA disabling on reception error */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
 800defe:	687b      	ldr	r3, [r7, #4]
 800df00:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800df02:	f003 0320 	and.w	r3, r3, #32
 800df06:	2b00      	cmp	r3, #0
 800df08:	d00a      	beq.n	800df20 <UART_AdvFeatureConfig+0xd4>
  {
    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
 800df0a:	687b      	ldr	r3, [r7, #4]
 800df0c:	681b      	ldr	r3, [r3, #0]
 800df0e:	689b      	ldr	r3, [r3, #8]
 800df10:	f423 5100 	bic.w	r1, r3, #8192	@ 0x2000
 800df14:	687b      	ldr	r3, [r7, #4]
 800df16:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
 800df18:	687b      	ldr	r3, [r7, #4]
 800df1a:	681b      	ldr	r3, [r3, #0]
 800df1c:	430a      	orrs	r2, r1
 800df1e:	609a      	str	r2, [r3, #8]
  }

  /* if required, configure auto Baud rate detection scheme */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
 800df20:	687b      	ldr	r3, [r7, #4]
 800df22:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800df24:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800df28:	2b00      	cmp	r3, #0
 800df2a:	d01a      	beq.n	800df62 <UART_AdvFeatureConfig+0x116>
  {
    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
 800df2c:	687b      	ldr	r3, [r7, #4]
 800df2e:	681b      	ldr	r3, [r3, #0]
 800df30:	685b      	ldr	r3, [r3, #4]
 800df32:	f423 1180 	bic.w	r1, r3, #1048576	@ 0x100000
 800df36:	687b      	ldr	r3, [r7, #4]
 800df38:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
 800df3a:	687b      	ldr	r3, [r7, #4]
 800df3c:	681b      	ldr	r3, [r3, #0]
 800df3e:	430a      	orrs	r2, r1
 800df40:	605a      	str	r2, [r3, #4]
    /* set auto Baudrate detection parameters if detection is enabled */
    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
 800df42:	687b      	ldr	r3, [r7, #4]
 800df44:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 800df46:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 800df4a:	d10a      	bne.n	800df62 <UART_AdvFeatureConfig+0x116>
    {
      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
 800df4c:	687b      	ldr	r3, [r7, #4]
 800df4e:	681b      	ldr	r3, [r3, #0]
 800df50:	685b      	ldr	r3, [r3, #4]
 800df52:	f423 01c0 	bic.w	r1, r3, #6291456	@ 0x600000
 800df56:	687b      	ldr	r3, [r7, #4]
 800df58:	6c9a      	ldr	r2, [r3, #72]	@ 0x48
 800df5a:	687b      	ldr	r3, [r7, #4]
 800df5c:	681b      	ldr	r3, [r3, #0]
 800df5e:	430a      	orrs	r2, r1
 800df60:	605a      	str	r2, [r3, #4]
    }
  }

  /* if required, configure MSB first on communication line */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
 800df62:	687b      	ldr	r3, [r7, #4]
 800df64:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800df66:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 800df6a:	2b00      	cmp	r3, #0
 800df6c:	d00a      	beq.n	800df84 <UART_AdvFeatureConfig+0x138>
  {
    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
 800df6e:	687b      	ldr	r3, [r7, #4]
 800df70:	681b      	ldr	r3, [r3, #0]
 800df72:	685b      	ldr	r3, [r3, #4]
 800df74:	f423 2100 	bic.w	r1, r3, #524288	@ 0x80000
 800df78:	687b      	ldr	r3, [r7, #4]
 800df7a:	6cda      	ldr	r2, [r3, #76]	@ 0x4c
 800df7c:	687b      	ldr	r3, [r7, #4]
 800df7e:	681b      	ldr	r3, [r3, #0]
 800df80:	430a      	orrs	r2, r1
 800df82:	605a      	str	r2, [r3, #4]
  }
}
 800df84:	bf00      	nop
 800df86:	370c      	adds	r7, #12
 800df88:	46bd      	mov	sp, r7
 800df8a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800df8e:	4770      	bx	lr

0800df90 <UART_CheckIdleState>:
  * @brief Check the UART Idle State.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
 800df90:	b580      	push	{r7, lr}
 800df92:	b098      	sub	sp, #96	@ 0x60
 800df94:	af02      	add	r7, sp, #8
 800df96:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;

  /* Initialize the UART ErrorCode */
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 800df98:	687b      	ldr	r3, [r7, #4]
 800df9a:	2200      	movs	r2, #0
 800df9c:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90

  /* Init tickstart for timeout management */
  tickstart = HAL_GetTick();
 800dfa0:	f7f5 fa90 	bl	80034c4 <HAL_GetTick>
 800dfa4:	6578      	str	r0, [r7, #84]	@ 0x54

  /* Check if the Transmitter is enabled */
  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
 800dfa6:	687b      	ldr	r3, [r7, #4]
 800dfa8:	681b      	ldr	r3, [r3, #0]
 800dfaa:	681b      	ldr	r3, [r3, #0]
 800dfac:	f003 0308 	and.w	r3, r3, #8
 800dfb0:	2b08      	cmp	r3, #8
 800dfb2:	d12f      	bne.n	800e014 <UART_CheckIdleState+0x84>
  {
    /* Wait until TEACK flag is set */
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 800dfb4:	f06f 437e 	mvn.w	r3, #4261412864	@ 0xfe000000
 800dfb8:	9300      	str	r3, [sp, #0]
 800dfba:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 800dfbc:	2200      	movs	r2, #0
 800dfbe:	f44f 1100 	mov.w	r1, #2097152	@ 0x200000
 800dfc2:	6878      	ldr	r0, [r7, #4]
 800dfc4:	f000 f88e 	bl	800e0e4 <UART_WaitOnFlagUntilTimeout>
 800dfc8:	4603      	mov	r3, r0
 800dfca:	2b00      	cmp	r3, #0
 800dfcc:	d022      	beq.n	800e014 <UART_CheckIdleState+0x84>
    {
      /* Disable TXE interrupt for the interrupt process */
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
 800dfce:	687b      	ldr	r3, [r7, #4]
 800dfd0:	681b      	ldr	r3, [r3, #0]
 800dfd2:	63bb      	str	r3, [r7, #56]	@ 0x38
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800dfd4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dfd6:	e853 3f00 	ldrex	r3, [r3]
 800dfda:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 800dfdc:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800dfde:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 800dfe2:	653b      	str	r3, [r7, #80]	@ 0x50
 800dfe4:	687b      	ldr	r3, [r7, #4]
 800dfe6:	681b      	ldr	r3, [r3, #0]
 800dfe8:	461a      	mov	r2, r3
 800dfea:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 800dfec:	647b      	str	r3, [r7, #68]	@ 0x44
 800dfee:	643a      	str	r2, [r7, #64]	@ 0x40
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800dff0:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 800dff2:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 800dff4:	e841 2300 	strex	r3, r2, [r1]
 800dff8:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 800dffa:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800dffc:	2b00      	cmp	r3, #0
 800dffe:	d1e6      	bne.n	800dfce <UART_CheckIdleState+0x3e>

      huart->gState = HAL_UART_STATE_READY;
 800e000:	687b      	ldr	r3, [r7, #4]
 800e002:	2220      	movs	r2, #32
 800e004:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

      __HAL_UNLOCK(huart);
 800e008:	687b      	ldr	r3, [r7, #4]
 800e00a:	2200      	movs	r2, #0
 800e00c:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

      /* Timeout occurred */
      return HAL_TIMEOUT;
 800e010:	2303      	movs	r3, #3
 800e012:	e063      	b.n	800e0dc <UART_CheckIdleState+0x14c>
    }
  }

  /* Check if the Receiver is enabled */
  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
 800e014:	687b      	ldr	r3, [r7, #4]
 800e016:	681b      	ldr	r3, [r3, #0]
 800e018:	681b      	ldr	r3, [r3, #0]
 800e01a:	f003 0304 	and.w	r3, r3, #4
 800e01e:	2b04      	cmp	r3, #4
 800e020:	d149      	bne.n	800e0b6 <UART_CheckIdleState+0x126>
  {
    /* Wait until REACK flag is set */
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 800e022:	f06f 437e 	mvn.w	r3, #4261412864	@ 0xfe000000
 800e026:	9300      	str	r3, [sp, #0]
 800e028:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 800e02a:	2200      	movs	r2, #0
 800e02c:	f44f 0180 	mov.w	r1, #4194304	@ 0x400000
 800e030:	6878      	ldr	r0, [r7, #4]
 800e032:	f000 f857 	bl	800e0e4 <UART_WaitOnFlagUntilTimeout>
 800e036:	4603      	mov	r3, r0
 800e038:	2b00      	cmp	r3, #0
 800e03a:	d03c      	beq.n	800e0b6 <UART_CheckIdleState+0x126>
    {
      /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
      interrupts for the interrupt process */
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 800e03c:	687b      	ldr	r3, [r7, #4]
 800e03e:	681b      	ldr	r3, [r3, #0]
 800e040:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e042:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800e044:	e853 3f00 	ldrex	r3, [r3]
 800e048:	623b      	str	r3, [r7, #32]
   return(result);
 800e04a:	6a3b      	ldr	r3, [r7, #32]
 800e04c:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 800e050:	64fb      	str	r3, [r7, #76]	@ 0x4c
 800e052:	687b      	ldr	r3, [r7, #4]
 800e054:	681b      	ldr	r3, [r3, #0]
 800e056:	461a      	mov	r2, r3
 800e058:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 800e05a:	633b      	str	r3, [r7, #48]	@ 0x30
 800e05c:	62fa      	str	r2, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e05e:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 800e060:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 800e062:	e841 2300 	strex	r3, r2, [r1]
 800e066:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 800e068:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800e06a:	2b00      	cmp	r3, #0
 800e06c:	d1e6      	bne.n	800e03c <UART_CheckIdleState+0xac>
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800e06e:	687b      	ldr	r3, [r7, #4]
 800e070:	681b      	ldr	r3, [r3, #0]
 800e072:	3308      	adds	r3, #8
 800e074:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e076:	693b      	ldr	r3, [r7, #16]
 800e078:	e853 3f00 	ldrex	r3, [r3]
 800e07c:	60fb      	str	r3, [r7, #12]
   return(result);
 800e07e:	68fb      	ldr	r3, [r7, #12]
 800e080:	f023 0301 	bic.w	r3, r3, #1
 800e084:	64bb      	str	r3, [r7, #72]	@ 0x48
 800e086:	687b      	ldr	r3, [r7, #4]
 800e088:	681b      	ldr	r3, [r3, #0]
 800e08a:	3308      	adds	r3, #8
 800e08c:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 800e08e:	61fa      	str	r2, [r7, #28]
 800e090:	61bb      	str	r3, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e092:	69b9      	ldr	r1, [r7, #24]
 800e094:	69fa      	ldr	r2, [r7, #28]
 800e096:	e841 2300 	strex	r3, r2, [r1]
 800e09a:	617b      	str	r3, [r7, #20]
   return(result);
 800e09c:	697b      	ldr	r3, [r7, #20]
 800e09e:	2b00      	cmp	r3, #0
 800e0a0:	d1e5      	bne.n	800e06e <UART_CheckIdleState+0xde>

      huart->RxState = HAL_UART_STATE_READY;
 800e0a2:	687b      	ldr	r3, [r7, #4]
 800e0a4:	2220      	movs	r2, #32
 800e0a6:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c

      __HAL_UNLOCK(huart);
 800e0aa:	687b      	ldr	r3, [r7, #4]
 800e0ac:	2200      	movs	r2, #0
 800e0ae:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

      /* Timeout occurred */
      return HAL_TIMEOUT;
 800e0b2:	2303      	movs	r3, #3
 800e0b4:	e012      	b.n	800e0dc <UART_CheckIdleState+0x14c>
    }
  }

  /* Initialize the UART State */
  huart->gState = HAL_UART_STATE_READY;
 800e0b6:	687b      	ldr	r3, [r7, #4]
 800e0b8:	2220      	movs	r2, #32
 800e0ba:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
  huart->RxState = HAL_UART_STATE_READY;
 800e0be:	687b      	ldr	r3, [r7, #4]
 800e0c0:	2220      	movs	r2, #32
 800e0c2:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800e0c6:	687b      	ldr	r3, [r7, #4]
 800e0c8:	2200      	movs	r2, #0
 800e0ca:	66da      	str	r2, [r3, #108]	@ 0x6c
  huart->RxEventType = HAL_UART_RXEVENT_TC;
 800e0cc:	687b      	ldr	r3, [r7, #4]
 800e0ce:	2200      	movs	r2, #0
 800e0d0:	671a      	str	r2, [r3, #112]	@ 0x70

  __HAL_UNLOCK(huart);
 800e0d2:	687b      	ldr	r3, [r7, #4]
 800e0d4:	2200      	movs	r2, #0
 800e0d6:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  return HAL_OK;
 800e0da:	2300      	movs	r3, #0
}
 800e0dc:	4618      	mov	r0, r3
 800e0de:	3758      	adds	r7, #88	@ 0x58
 800e0e0:	46bd      	mov	sp, r7
 800e0e2:	bd80      	pop	{r7, pc}

0800e0e4 <UART_WaitOnFlagUntilTimeout>:
  * @param Timeout   Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
                                              uint32_t Tickstart, uint32_t Timeout)
{
 800e0e4:	b580      	push	{r7, lr}
 800e0e6:	b084      	sub	sp, #16
 800e0e8:	af00      	add	r7, sp, #0
 800e0ea:	60f8      	str	r0, [r7, #12]
 800e0ec:	60b9      	str	r1, [r7, #8]
 800e0ee:	603b      	str	r3, [r7, #0]
 800e0f0:	4613      	mov	r3, r2
 800e0f2:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is set */
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 800e0f4:	e04f      	b.n	800e196 <UART_WaitOnFlagUntilTimeout+0xb2>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 800e0f6:	69bb      	ldr	r3, [r7, #24]
 800e0f8:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 800e0fc:	d04b      	beq.n	800e196 <UART_WaitOnFlagUntilTimeout+0xb2>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 800e0fe:	f7f5 f9e1 	bl	80034c4 <HAL_GetTick>
 800e102:	4602      	mov	r2, r0
 800e104:	683b      	ldr	r3, [r7, #0]
 800e106:	1ad3      	subs	r3, r2, r3
 800e108:	69ba      	ldr	r2, [r7, #24]
 800e10a:	429a      	cmp	r2, r3
 800e10c:	d302      	bcc.n	800e114 <UART_WaitOnFlagUntilTimeout+0x30>
 800e10e:	69bb      	ldr	r3, [r7, #24]
 800e110:	2b00      	cmp	r3, #0
 800e112:	d101      	bne.n	800e118 <UART_WaitOnFlagUntilTimeout+0x34>
      {

        return HAL_TIMEOUT;
 800e114:	2303      	movs	r3, #3
 800e116:	e04e      	b.n	800e1b6 <UART_WaitOnFlagUntilTimeout+0xd2>
      }

      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
 800e118:	68fb      	ldr	r3, [r7, #12]
 800e11a:	681b      	ldr	r3, [r3, #0]
 800e11c:	681b      	ldr	r3, [r3, #0]
 800e11e:	f003 0304 	and.w	r3, r3, #4
 800e122:	2b00      	cmp	r3, #0
 800e124:	d037      	beq.n	800e196 <UART_WaitOnFlagUntilTimeout+0xb2>
 800e126:	68bb      	ldr	r3, [r7, #8]
 800e128:	2b80      	cmp	r3, #128	@ 0x80
 800e12a:	d034      	beq.n	800e196 <UART_WaitOnFlagUntilTimeout+0xb2>
 800e12c:	68bb      	ldr	r3, [r7, #8]
 800e12e:	2b40      	cmp	r3, #64	@ 0x40
 800e130:	d031      	beq.n	800e196 <UART_WaitOnFlagUntilTimeout+0xb2>
      {
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
 800e132:	68fb      	ldr	r3, [r7, #12]
 800e134:	681b      	ldr	r3, [r3, #0]
 800e136:	69db      	ldr	r3, [r3, #28]
 800e138:	f003 0308 	and.w	r3, r3, #8
 800e13c:	2b08      	cmp	r3, #8
 800e13e:	d110      	bne.n	800e162 <UART_WaitOnFlagUntilTimeout+0x7e>
        {
          /* Clear Overrun Error flag*/
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 800e140:	68fb      	ldr	r3, [r7, #12]
 800e142:	681b      	ldr	r3, [r3, #0]
 800e144:	2208      	movs	r2, #8
 800e146:	621a      	str	r2, [r3, #32]

          /* Blocking error : transfer is aborted
          Set the UART state ready to be able to start again the process,
          Disable Rx Interrupts if ongoing */
          UART_EndRxTransfer(huart);
 800e148:	68f8      	ldr	r0, [r7, #12]
 800e14a:	f000 f95b 	bl	800e404 <UART_EndRxTransfer>

          huart->ErrorCode = HAL_UART_ERROR_ORE;
 800e14e:	68fb      	ldr	r3, [r7, #12]
 800e150:	2208      	movs	r2, #8
 800e152:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90

          /* Process Unlocked */
          __HAL_UNLOCK(huart);
 800e156:	68fb      	ldr	r3, [r7, #12]
 800e158:	2200      	movs	r2, #0
 800e15a:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

          return HAL_ERROR;
 800e15e:	2301      	movs	r3, #1
 800e160:	e029      	b.n	800e1b6 <UART_WaitOnFlagUntilTimeout+0xd2>
        }
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
 800e162:	68fb      	ldr	r3, [r7, #12]
 800e164:	681b      	ldr	r3, [r3, #0]
 800e166:	69db      	ldr	r3, [r3, #28]
 800e168:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 800e16c:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 800e170:	d111      	bne.n	800e196 <UART_WaitOnFlagUntilTimeout+0xb2>
        {
          /* Clear Receiver Timeout flag*/
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 800e172:	68fb      	ldr	r3, [r7, #12]
 800e174:	681b      	ldr	r3, [r3, #0]
 800e176:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 800e17a:	621a      	str	r2, [r3, #32]

          /* Blocking error : transfer is aborted
          Set the UART state ready to be able to start again the process,
          Disable Rx Interrupts if ongoing */
          UART_EndRxTransfer(huart);
 800e17c:	68f8      	ldr	r0, [r7, #12]
 800e17e:	f000 f941 	bl	800e404 <UART_EndRxTransfer>

          huart->ErrorCode = HAL_UART_ERROR_RTO;
 800e182:	68fb      	ldr	r3, [r7, #12]
 800e184:	2220      	movs	r2, #32
 800e186:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90

          /* Process Unlocked */
          __HAL_UNLOCK(huart);
 800e18a:	68fb      	ldr	r3, [r7, #12]
 800e18c:	2200      	movs	r2, #0
 800e18e:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

          return HAL_TIMEOUT;
 800e192:	2303      	movs	r3, #3
 800e194:	e00f      	b.n	800e1b6 <UART_WaitOnFlagUntilTimeout+0xd2>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 800e196:	68fb      	ldr	r3, [r7, #12]
 800e198:	681b      	ldr	r3, [r3, #0]
 800e19a:	69da      	ldr	r2, [r3, #28]
 800e19c:	68bb      	ldr	r3, [r7, #8]
 800e19e:	4013      	ands	r3, r2
 800e1a0:	68ba      	ldr	r2, [r7, #8]
 800e1a2:	429a      	cmp	r2, r3
 800e1a4:	bf0c      	ite	eq
 800e1a6:	2301      	moveq	r3, #1
 800e1a8:	2300      	movne	r3, #0
 800e1aa:	b2db      	uxtb	r3, r3
 800e1ac:	461a      	mov	r2, r3
 800e1ae:	79fb      	ldrb	r3, [r7, #7]
 800e1b0:	429a      	cmp	r2, r3
 800e1b2:	d0a0      	beq.n	800e0f6 <UART_WaitOnFlagUntilTimeout+0x12>
        }
      }
    }
  }
  return HAL_OK;
 800e1b4:	2300      	movs	r3, #0
}
 800e1b6:	4618      	mov	r0, r3
 800e1b8:	3710      	adds	r7, #16
 800e1ba:	46bd      	mov	sp, r7
 800e1bc:	bd80      	pop	{r7, pc}
	...

0800e1c0 <UART_Start_Receive_IT>:
  * @param  pData Pointer to data buffer (u8 or u16 data elements).
  * @param  Size  Amount of data elements (u8 or u16) to be received.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
 800e1c0:	b480      	push	{r7}
 800e1c2:	b0a3      	sub	sp, #140	@ 0x8c
 800e1c4:	af00      	add	r7, sp, #0
 800e1c6:	60f8      	str	r0, [r7, #12]
 800e1c8:	60b9      	str	r1, [r7, #8]
 800e1ca:	4613      	mov	r3, r2
 800e1cc:	80fb      	strh	r3, [r7, #6]
  huart->pRxBuffPtr  = pData;
 800e1ce:	68fb      	ldr	r3, [r7, #12]
 800e1d0:	68ba      	ldr	r2, [r7, #8]
 800e1d2:	659a      	str	r2, [r3, #88]	@ 0x58
  huart->RxXferSize  = Size;
 800e1d4:	68fb      	ldr	r3, [r7, #12]
 800e1d6:	88fa      	ldrh	r2, [r7, #6]
 800e1d8:	f8a3 205c 	strh.w	r2, [r3, #92]	@ 0x5c
  huart->RxXferCount = Size;
 800e1dc:	68fb      	ldr	r3, [r7, #12]
 800e1de:	88fa      	ldrh	r2, [r7, #6]
 800e1e0:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
  huart->RxISR       = NULL;
 800e1e4:	68fb      	ldr	r3, [r7, #12]
 800e1e6:	2200      	movs	r2, #0
 800e1e8:	675a      	str	r2, [r3, #116]	@ 0x74

  /* Computation of UART mask to apply to RDR register */
  UART_MASK_COMPUTATION(huart);
 800e1ea:	68fb      	ldr	r3, [r7, #12]
 800e1ec:	689b      	ldr	r3, [r3, #8]
 800e1ee:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800e1f2:	d10e      	bne.n	800e212 <UART_Start_Receive_IT+0x52>
 800e1f4:	68fb      	ldr	r3, [r7, #12]
 800e1f6:	691b      	ldr	r3, [r3, #16]
 800e1f8:	2b00      	cmp	r3, #0
 800e1fa:	d105      	bne.n	800e208 <UART_Start_Receive_IT+0x48>
 800e1fc:	68fb      	ldr	r3, [r7, #12]
 800e1fe:	f240 12ff 	movw	r2, #511	@ 0x1ff
 800e202:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
 800e206:	e02d      	b.n	800e264 <UART_Start_Receive_IT+0xa4>
 800e208:	68fb      	ldr	r3, [r7, #12]
 800e20a:	22ff      	movs	r2, #255	@ 0xff
 800e20c:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
 800e210:	e028      	b.n	800e264 <UART_Start_Receive_IT+0xa4>
 800e212:	68fb      	ldr	r3, [r7, #12]
 800e214:	689b      	ldr	r3, [r3, #8]
 800e216:	2b00      	cmp	r3, #0
 800e218:	d10d      	bne.n	800e236 <UART_Start_Receive_IT+0x76>
 800e21a:	68fb      	ldr	r3, [r7, #12]
 800e21c:	691b      	ldr	r3, [r3, #16]
 800e21e:	2b00      	cmp	r3, #0
 800e220:	d104      	bne.n	800e22c <UART_Start_Receive_IT+0x6c>
 800e222:	68fb      	ldr	r3, [r7, #12]
 800e224:	22ff      	movs	r2, #255	@ 0xff
 800e226:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
 800e22a:	e01b      	b.n	800e264 <UART_Start_Receive_IT+0xa4>
 800e22c:	68fb      	ldr	r3, [r7, #12]
 800e22e:	227f      	movs	r2, #127	@ 0x7f
 800e230:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
 800e234:	e016      	b.n	800e264 <UART_Start_Receive_IT+0xa4>
 800e236:	68fb      	ldr	r3, [r7, #12]
 800e238:	689b      	ldr	r3, [r3, #8]
 800e23a:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800e23e:	d10d      	bne.n	800e25c <UART_Start_Receive_IT+0x9c>
 800e240:	68fb      	ldr	r3, [r7, #12]
 800e242:	691b      	ldr	r3, [r3, #16]
 800e244:	2b00      	cmp	r3, #0
 800e246:	d104      	bne.n	800e252 <UART_Start_Receive_IT+0x92>
 800e248:	68fb      	ldr	r3, [r7, #12]
 800e24a:	227f      	movs	r2, #127	@ 0x7f
 800e24c:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
 800e250:	e008      	b.n	800e264 <UART_Start_Receive_IT+0xa4>
 800e252:	68fb      	ldr	r3, [r7, #12]
 800e254:	223f      	movs	r2, #63	@ 0x3f
 800e256:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
 800e25a:	e003      	b.n	800e264 <UART_Start_Receive_IT+0xa4>
 800e25c:	68fb      	ldr	r3, [r7, #12]
 800e25e:	2200      	movs	r2, #0
 800e260:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60

  huart->ErrorCode = HAL_UART_ERROR_NONE;
 800e264:	68fb      	ldr	r3, [r7, #12]
 800e266:	2200      	movs	r2, #0
 800e268:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
  huart->RxState = HAL_UART_STATE_BUSY_RX;
 800e26c:	68fb      	ldr	r3, [r7, #12]
 800e26e:	2222      	movs	r2, #34	@ 0x22
 800e270:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c

  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800e274:	68fb      	ldr	r3, [r7, #12]
 800e276:	681b      	ldr	r3, [r3, #0]
 800e278:	3308      	adds	r3, #8
 800e27a:	667b      	str	r3, [r7, #100]	@ 0x64
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e27c:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 800e27e:	e853 3f00 	ldrex	r3, [r3]
 800e282:	663b      	str	r3, [r7, #96]	@ 0x60
   return(result);
 800e284:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 800e286:	f043 0301 	orr.w	r3, r3, #1
 800e28a:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
 800e28e:	68fb      	ldr	r3, [r7, #12]
 800e290:	681b      	ldr	r3, [r3, #0]
 800e292:	3308      	adds	r3, #8
 800e294:	f8d7 2084 	ldr.w	r2, [r7, #132]	@ 0x84
 800e298:	673a      	str	r2, [r7, #112]	@ 0x70
 800e29a:	66fb      	str	r3, [r7, #108]	@ 0x6c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e29c:	6ef9      	ldr	r1, [r7, #108]	@ 0x6c
 800e29e:	6f3a      	ldr	r2, [r7, #112]	@ 0x70
 800e2a0:	e841 2300 	strex	r3, r2, [r1]
 800e2a4:	66bb      	str	r3, [r7, #104]	@ 0x68
   return(result);
 800e2a6:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 800e2a8:	2b00      	cmp	r3, #0
 800e2aa:	d1e3      	bne.n	800e274 <UART_Start_Receive_IT+0xb4>

  /* Configure Rx interrupt processing */
  if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
 800e2ac:	68fb      	ldr	r3, [r7, #12]
 800e2ae:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 800e2b0:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800e2b4:	d14f      	bne.n	800e356 <UART_Start_Receive_IT+0x196>
 800e2b6:	68fb      	ldr	r3, [r7, #12]
 800e2b8:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
 800e2bc:	88fa      	ldrh	r2, [r7, #6]
 800e2be:	429a      	cmp	r2, r3
 800e2c0:	d349      	bcc.n	800e356 <UART_Start_Receive_IT+0x196>
  {
    /* Set the Rx ISR function pointer according to the data word length */
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 800e2c2:	68fb      	ldr	r3, [r7, #12]
 800e2c4:	689b      	ldr	r3, [r3, #8]
 800e2c6:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800e2ca:	d107      	bne.n	800e2dc <UART_Start_Receive_IT+0x11c>
 800e2cc:	68fb      	ldr	r3, [r7, #12]
 800e2ce:	691b      	ldr	r3, [r3, #16]
 800e2d0:	2b00      	cmp	r3, #0
 800e2d2:	d103      	bne.n	800e2dc <UART_Start_Receive_IT+0x11c>
    {
      huart->RxISR = UART_RxISR_16BIT_FIFOEN;
 800e2d4:	68fb      	ldr	r3, [r7, #12]
 800e2d6:	4a47      	ldr	r2, [pc, #284]	@ (800e3f4 <UART_Start_Receive_IT+0x234>)
 800e2d8:	675a      	str	r2, [r3, #116]	@ 0x74
 800e2da:	e002      	b.n	800e2e2 <UART_Start_Receive_IT+0x122>
    }
    else
    {
      huart->RxISR = UART_RxISR_8BIT_FIFOEN;
 800e2dc:	68fb      	ldr	r3, [r7, #12]
 800e2de:	4a46      	ldr	r2, [pc, #280]	@ (800e3f8 <UART_Start_Receive_IT+0x238>)
 800e2e0:	675a      	str	r2, [r3, #116]	@ 0x74
    }

    /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
    if (huart->Init.Parity != UART_PARITY_NONE)
 800e2e2:	68fb      	ldr	r3, [r7, #12]
 800e2e4:	691b      	ldr	r3, [r3, #16]
 800e2e6:	2b00      	cmp	r3, #0
 800e2e8:	d01a      	beq.n	800e320 <UART_Start_Receive_IT+0x160>
    {
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 800e2ea:	68fb      	ldr	r3, [r7, #12]
 800e2ec:	681b      	ldr	r3, [r3, #0]
 800e2ee:	653b      	str	r3, [r7, #80]	@ 0x50
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e2f0:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 800e2f2:	e853 3f00 	ldrex	r3, [r3]
 800e2f6:	64fb      	str	r3, [r7, #76]	@ 0x4c
   return(result);
 800e2f8:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 800e2fa:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 800e2fe:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
 800e302:	68fb      	ldr	r3, [r7, #12]
 800e304:	681b      	ldr	r3, [r3, #0]
 800e306:	461a      	mov	r2, r3
 800e308:	f8d7 3080 	ldr.w	r3, [r7, #128]	@ 0x80
 800e30c:	65fb      	str	r3, [r7, #92]	@ 0x5c
 800e30e:	65ba      	str	r2, [r7, #88]	@ 0x58
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e310:	6db9      	ldr	r1, [r7, #88]	@ 0x58
 800e312:	6dfa      	ldr	r2, [r7, #92]	@ 0x5c
 800e314:	e841 2300 	strex	r3, r2, [r1]
 800e318:	657b      	str	r3, [r7, #84]	@ 0x54
   return(result);
 800e31a:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 800e31c:	2b00      	cmp	r3, #0
 800e31e:	d1e4      	bne.n	800e2ea <UART_Start_Receive_IT+0x12a>
    }
    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
 800e320:	68fb      	ldr	r3, [r7, #12]
 800e322:	681b      	ldr	r3, [r3, #0]
 800e324:	3308      	adds	r3, #8
 800e326:	63fb      	str	r3, [r7, #60]	@ 0x3c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e328:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800e32a:	e853 3f00 	ldrex	r3, [r3]
 800e32e:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 800e330:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800e332:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 800e336:	67fb      	str	r3, [r7, #124]	@ 0x7c
 800e338:	68fb      	ldr	r3, [r7, #12]
 800e33a:	681b      	ldr	r3, [r3, #0]
 800e33c:	3308      	adds	r3, #8
 800e33e:	6ffa      	ldr	r2, [r7, #124]	@ 0x7c
 800e340:	64ba      	str	r2, [r7, #72]	@ 0x48
 800e342:	647b      	str	r3, [r7, #68]	@ 0x44
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e344:	6c79      	ldr	r1, [r7, #68]	@ 0x44
 800e346:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 800e348:	e841 2300 	strex	r3, r2, [r1]
 800e34c:	643b      	str	r3, [r7, #64]	@ 0x40
   return(result);
 800e34e:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 800e350:	2b00      	cmp	r3, #0
 800e352:	d1e5      	bne.n	800e320 <UART_Start_Receive_IT+0x160>
 800e354:	e046      	b.n	800e3e4 <UART_Start_Receive_IT+0x224>
  }
  else
  {
    /* Set the Rx ISR function pointer according to the data word length */
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 800e356:	68fb      	ldr	r3, [r7, #12]
 800e358:	689b      	ldr	r3, [r3, #8]
 800e35a:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800e35e:	d107      	bne.n	800e370 <UART_Start_Receive_IT+0x1b0>
 800e360:	68fb      	ldr	r3, [r7, #12]
 800e362:	691b      	ldr	r3, [r3, #16]
 800e364:	2b00      	cmp	r3, #0
 800e366:	d103      	bne.n	800e370 <UART_Start_Receive_IT+0x1b0>
    {
      huart->RxISR = UART_RxISR_16BIT;
 800e368:	68fb      	ldr	r3, [r7, #12]
 800e36a:	4a24      	ldr	r2, [pc, #144]	@ (800e3fc <UART_Start_Receive_IT+0x23c>)
 800e36c:	675a      	str	r2, [r3, #116]	@ 0x74
 800e36e:	e002      	b.n	800e376 <UART_Start_Receive_IT+0x1b6>
    }
    else
    {
      huart->RxISR = UART_RxISR_8BIT;
 800e370:	68fb      	ldr	r3, [r7, #12]
 800e372:	4a23      	ldr	r2, [pc, #140]	@ (800e400 <UART_Start_Receive_IT+0x240>)
 800e374:	675a      	str	r2, [r3, #116]	@ 0x74
    }

    /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
    if (huart->Init.Parity != UART_PARITY_NONE)
 800e376:	68fb      	ldr	r3, [r7, #12]
 800e378:	691b      	ldr	r3, [r3, #16]
 800e37a:	2b00      	cmp	r3, #0
 800e37c:	d019      	beq.n	800e3b2 <UART_Start_Receive_IT+0x1f2>
    {
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
 800e37e:	68fb      	ldr	r3, [r7, #12]
 800e380:	681b      	ldr	r3, [r3, #0]
 800e382:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e384:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800e386:	e853 3f00 	ldrex	r3, [r3]
 800e38a:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 800e38c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800e38e:	f443 7390 	orr.w	r3, r3, #288	@ 0x120
 800e392:	677b      	str	r3, [r7, #116]	@ 0x74
 800e394:	68fb      	ldr	r3, [r7, #12]
 800e396:	681b      	ldr	r3, [r3, #0]
 800e398:	461a      	mov	r2, r3
 800e39a:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
 800e39c:	637b      	str	r3, [r7, #52]	@ 0x34
 800e39e:	633a      	str	r2, [r7, #48]	@ 0x30
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e3a0:	6b39      	ldr	r1, [r7, #48]	@ 0x30
 800e3a2:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 800e3a4:	e841 2300 	strex	r3, r2, [r1]
 800e3a8:	62fb      	str	r3, [r7, #44]	@ 0x2c
   return(result);
 800e3aa:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800e3ac:	2b00      	cmp	r3, #0
 800e3ae:	d1e6      	bne.n	800e37e <UART_Start_Receive_IT+0x1be>
 800e3b0:	e018      	b.n	800e3e4 <UART_Start_Receive_IT+0x224>
    }
    else
    {
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
 800e3b2:	68fb      	ldr	r3, [r7, #12]
 800e3b4:	681b      	ldr	r3, [r3, #0]
 800e3b6:	617b      	str	r3, [r7, #20]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e3b8:	697b      	ldr	r3, [r7, #20]
 800e3ba:	e853 3f00 	ldrex	r3, [r3]
 800e3be:	613b      	str	r3, [r7, #16]
   return(result);
 800e3c0:	693b      	ldr	r3, [r7, #16]
 800e3c2:	f043 0320 	orr.w	r3, r3, #32
 800e3c6:	67bb      	str	r3, [r7, #120]	@ 0x78
 800e3c8:	68fb      	ldr	r3, [r7, #12]
 800e3ca:	681b      	ldr	r3, [r3, #0]
 800e3cc:	461a      	mov	r2, r3
 800e3ce:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
 800e3d0:	623b      	str	r3, [r7, #32]
 800e3d2:	61fa      	str	r2, [r7, #28]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e3d4:	69f9      	ldr	r1, [r7, #28]
 800e3d6:	6a3a      	ldr	r2, [r7, #32]
 800e3d8:	e841 2300 	strex	r3, r2, [r1]
 800e3dc:	61bb      	str	r3, [r7, #24]
   return(result);
 800e3de:	69bb      	ldr	r3, [r7, #24]
 800e3e0:	2b00      	cmp	r3, #0
 800e3e2:	d1e6      	bne.n	800e3b2 <UART_Start_Receive_IT+0x1f2>
    }
  }
  return HAL_OK;
 800e3e4:	2300      	movs	r3, #0
}
 800e3e6:	4618      	mov	r0, r3
 800e3e8:	378c      	adds	r7, #140	@ 0x8c
 800e3ea:	46bd      	mov	sp, r7
 800e3ec:	f85d 7b04 	ldr.w	r7, [sp], #4
 800e3f0:	4770      	bx	lr
 800e3f2:	bf00      	nop
 800e3f4:	0800ef69 	.word	0x0800ef69
 800e3f8:	0800ec09 	.word	0x0800ec09
 800e3fc:	0800ea51 	.word	0x0800ea51
 800e400:	0800e899 	.word	0x0800e899

0800e404 <UART_EndRxTransfer>:
  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
  * @param  huart UART handle.
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
 800e404:	b480      	push	{r7}
 800e406:	b095      	sub	sp, #84	@ 0x54
 800e408:	af00      	add	r7, sp, #0
 800e40a:	6078      	str	r0, [r7, #4]
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 800e40c:	687b      	ldr	r3, [r7, #4]
 800e40e:	681b      	ldr	r3, [r3, #0]
 800e410:	637b      	str	r3, [r7, #52]	@ 0x34
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e412:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800e414:	e853 3f00 	ldrex	r3, [r3]
 800e418:	633b      	str	r3, [r7, #48]	@ 0x30
   return(result);
 800e41a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800e41c:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 800e420:	64fb      	str	r3, [r7, #76]	@ 0x4c
 800e422:	687b      	ldr	r3, [r7, #4]
 800e424:	681b      	ldr	r3, [r3, #0]
 800e426:	461a      	mov	r2, r3
 800e428:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 800e42a:	643b      	str	r3, [r7, #64]	@ 0x40
 800e42c:	63fa      	str	r2, [r7, #60]	@ 0x3c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e42e:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
 800e430:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
 800e432:	e841 2300 	strex	r3, r2, [r1]
 800e436:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 800e438:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800e43a:	2b00      	cmp	r3, #0
 800e43c:	d1e6      	bne.n	800e40c <UART_EndRxTransfer+0x8>
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 800e43e:	687b      	ldr	r3, [r7, #4]
 800e440:	681b      	ldr	r3, [r3, #0]
 800e442:	3308      	adds	r3, #8
 800e444:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e446:	6a3b      	ldr	r3, [r7, #32]
 800e448:	e853 3f00 	ldrex	r3, [r3]
 800e44c:	61fb      	str	r3, [r7, #28]
   return(result);
 800e44e:	69fa      	ldr	r2, [r7, #28]
 800e450:	4b1e      	ldr	r3, [pc, #120]	@ (800e4cc <UART_EndRxTransfer+0xc8>)
 800e452:	4013      	ands	r3, r2
 800e454:	64bb      	str	r3, [r7, #72]	@ 0x48
 800e456:	687b      	ldr	r3, [r7, #4]
 800e458:	681b      	ldr	r3, [r3, #0]
 800e45a:	3308      	adds	r3, #8
 800e45c:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 800e45e:	62fa      	str	r2, [r7, #44]	@ 0x2c
 800e460:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e462:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 800e464:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 800e466:	e841 2300 	strex	r3, r2, [r1]
 800e46a:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 800e46c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800e46e:	2b00      	cmp	r3, #0
 800e470:	d1e5      	bne.n	800e43e <UART_EndRxTransfer+0x3a>

  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 800e472:	687b      	ldr	r3, [r7, #4]
 800e474:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800e476:	2b01      	cmp	r3, #1
 800e478:	d118      	bne.n	800e4ac <UART_EndRxTransfer+0xa8>
  {
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 800e47a:	687b      	ldr	r3, [r7, #4]
 800e47c:	681b      	ldr	r3, [r3, #0]
 800e47e:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e480:	68fb      	ldr	r3, [r7, #12]
 800e482:	e853 3f00 	ldrex	r3, [r3]
 800e486:	60bb      	str	r3, [r7, #8]
   return(result);
 800e488:	68bb      	ldr	r3, [r7, #8]
 800e48a:	f023 0310 	bic.w	r3, r3, #16
 800e48e:	647b      	str	r3, [r7, #68]	@ 0x44
 800e490:	687b      	ldr	r3, [r7, #4]
 800e492:	681b      	ldr	r3, [r3, #0]
 800e494:	461a      	mov	r2, r3
 800e496:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 800e498:	61bb      	str	r3, [r7, #24]
 800e49a:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e49c:	6979      	ldr	r1, [r7, #20]
 800e49e:	69ba      	ldr	r2, [r7, #24]
 800e4a0:	e841 2300 	strex	r3, r2, [r1]
 800e4a4:	613b      	str	r3, [r7, #16]
   return(result);
 800e4a6:	693b      	ldr	r3, [r7, #16]
 800e4a8:	2b00      	cmp	r3, #0
 800e4aa:	d1e6      	bne.n	800e47a <UART_EndRxTransfer+0x76>
  }

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 800e4ac:	687b      	ldr	r3, [r7, #4]
 800e4ae:	2220      	movs	r2, #32
 800e4b0:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800e4b4:	687b      	ldr	r3, [r7, #4]
 800e4b6:	2200      	movs	r2, #0
 800e4b8:	66da      	str	r2, [r3, #108]	@ 0x6c

  /* Reset RxIsr function pointer */
  huart->RxISR = NULL;
 800e4ba:	687b      	ldr	r3, [r7, #4]
 800e4bc:	2200      	movs	r2, #0
 800e4be:	675a      	str	r2, [r3, #116]	@ 0x74
}
 800e4c0:	bf00      	nop
 800e4c2:	3754      	adds	r7, #84	@ 0x54
 800e4c4:	46bd      	mov	sp, r7
 800e4c6:	f85d 7b04 	ldr.w	r7, [sp], #4
 800e4ca:	4770      	bx	lr
 800e4cc:	effffffe 	.word	0xeffffffe

0800e4d0 <UART_DMAAbortOnError>:
  *         (To be called at end of DMA Abort procedure following error occurrence).
  * @param  hdma DMA handle.
  * @retval None
  */
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
 800e4d0:	b580      	push	{r7, lr}
 800e4d2:	b084      	sub	sp, #16
 800e4d4:	af00      	add	r7, sp, #0
 800e4d6:	6078      	str	r0, [r7, #4]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
 800e4d8:	687b      	ldr	r3, [r7, #4]
 800e4da:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800e4dc:	60fb      	str	r3, [r7, #12]
  huart->RxXferCount = 0U;
 800e4de:	68fb      	ldr	r3, [r7, #12]
 800e4e0:	2200      	movs	r2, #0
 800e4e2:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
  huart->TxXferCount = 0U;
 800e4e6:	68fb      	ldr	r3, [r7, #12]
 800e4e8:	2200      	movs	r2, #0
 800e4ea:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  /*Call registered error callback*/
  huart->ErrorCallback(huart);
#else
  /*Call legacy weak error callback*/
  HAL_UART_ErrorCallback(huart);
 800e4ee:	68f8      	ldr	r0, [r7, #12]
 800e4f0:	f7fe ff3a 	bl	800d368 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
 800e4f4:	bf00      	nop
 800e4f6:	3710      	adds	r7, #16
 800e4f8:	46bd      	mov	sp, r7
 800e4fa:	bd80      	pop	{r7, pc}

0800e4fc <UART_TxISR_8BIT>:
  *         interruptions have been enabled by HAL_UART_Transmit_IT().
  * @param huart UART handle.
  * @retval None
  */
static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
{
 800e4fc:	b480      	push	{r7}
 800e4fe:	b08f      	sub	sp, #60	@ 0x3c
 800e500:	af00      	add	r7, sp, #0
 800e502:	6078      	str	r0, [r7, #4]
  /* Check that a Tx process is ongoing */
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 800e504:	687b      	ldr	r3, [r7, #4]
 800e506:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800e50a:	2b21      	cmp	r3, #33	@ 0x21
 800e50c:	d14c      	bne.n	800e5a8 <UART_TxISR_8BIT+0xac>
  {
    if (huart->TxXferCount == 0U)
 800e50e:	687b      	ldr	r3, [r7, #4]
 800e510:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 800e514:	b29b      	uxth	r3, r3
 800e516:	2b00      	cmp	r3, #0
 800e518:	d132      	bne.n	800e580 <UART_TxISR_8BIT+0x84>
    {
      /* Disable the UART Transmit Data Register Empty Interrupt */
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
 800e51a:	687b      	ldr	r3, [r7, #4]
 800e51c:	681b      	ldr	r3, [r3, #0]
 800e51e:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e520:	6a3b      	ldr	r3, [r7, #32]
 800e522:	e853 3f00 	ldrex	r3, [r3]
 800e526:	61fb      	str	r3, [r7, #28]
   return(result);
 800e528:	69fb      	ldr	r3, [r7, #28]
 800e52a:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 800e52e:	637b      	str	r3, [r7, #52]	@ 0x34
 800e530:	687b      	ldr	r3, [r7, #4]
 800e532:	681b      	ldr	r3, [r3, #0]
 800e534:	461a      	mov	r2, r3
 800e536:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800e538:	62fb      	str	r3, [r7, #44]	@ 0x2c
 800e53a:	62ba      	str	r2, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e53c:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 800e53e:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 800e540:	e841 2300 	strex	r3, r2, [r1]
 800e544:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 800e546:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800e548:	2b00      	cmp	r3, #0
 800e54a:	d1e6      	bne.n	800e51a <UART_TxISR_8BIT+0x1e>

      /* Enable the UART Transmit Complete Interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 800e54c:	687b      	ldr	r3, [r7, #4]
 800e54e:	681b      	ldr	r3, [r3, #0]
 800e550:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e552:	68fb      	ldr	r3, [r7, #12]
 800e554:	e853 3f00 	ldrex	r3, [r3]
 800e558:	60bb      	str	r3, [r7, #8]
   return(result);
 800e55a:	68bb      	ldr	r3, [r7, #8]
 800e55c:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 800e560:	633b      	str	r3, [r7, #48]	@ 0x30
 800e562:	687b      	ldr	r3, [r7, #4]
 800e564:	681b      	ldr	r3, [r3, #0]
 800e566:	461a      	mov	r2, r3
 800e568:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800e56a:	61bb      	str	r3, [r7, #24]
 800e56c:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e56e:	6979      	ldr	r1, [r7, #20]
 800e570:	69ba      	ldr	r2, [r7, #24]
 800e572:	e841 2300 	strex	r3, r2, [r1]
 800e576:	613b      	str	r3, [r7, #16]
   return(result);
 800e578:	693b      	ldr	r3, [r7, #16]
 800e57a:	2b00      	cmp	r3, #0
 800e57c:	d1e6      	bne.n	800e54c <UART_TxISR_8BIT+0x50>
      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
      huart->pTxBuffPtr++;
      huart->TxXferCount--;
    }
  }
}
 800e57e:	e013      	b.n	800e5a8 <UART_TxISR_8BIT+0xac>
      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
 800e580:	687b      	ldr	r3, [r7, #4]
 800e582:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800e584:	781a      	ldrb	r2, [r3, #0]
 800e586:	687b      	ldr	r3, [r7, #4]
 800e588:	681b      	ldr	r3, [r3, #0]
 800e58a:	629a      	str	r2, [r3, #40]	@ 0x28
      huart->pTxBuffPtr++;
 800e58c:	687b      	ldr	r3, [r7, #4]
 800e58e:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800e590:	1c5a      	adds	r2, r3, #1
 800e592:	687b      	ldr	r3, [r7, #4]
 800e594:	651a      	str	r2, [r3, #80]	@ 0x50
      huart->TxXferCount--;
 800e596:	687b      	ldr	r3, [r7, #4]
 800e598:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 800e59c:	b29b      	uxth	r3, r3
 800e59e:	3b01      	subs	r3, #1
 800e5a0:	b29a      	uxth	r2, r3
 800e5a2:	687b      	ldr	r3, [r7, #4]
 800e5a4:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
}
 800e5a8:	bf00      	nop
 800e5aa:	373c      	adds	r7, #60	@ 0x3c
 800e5ac:	46bd      	mov	sp, r7
 800e5ae:	f85d 7b04 	ldr.w	r7, [sp], #4
 800e5b2:	4770      	bx	lr

0800e5b4 <UART_TxISR_16BIT>:
  *         interruptions have been enabled by HAL_UART_Transmit_IT().
  * @param huart UART handle.
  * @retval None
  */
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
{
 800e5b4:	b480      	push	{r7}
 800e5b6:	b091      	sub	sp, #68	@ 0x44
 800e5b8:	af00      	add	r7, sp, #0
 800e5ba:	6078      	str	r0, [r7, #4]
  const uint16_t *tmp;

  /* Check that a Tx process is ongoing */
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 800e5bc:	687b      	ldr	r3, [r7, #4]
 800e5be:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800e5c2:	2b21      	cmp	r3, #33	@ 0x21
 800e5c4:	d151      	bne.n	800e66a <UART_TxISR_16BIT+0xb6>
  {
    if (huart->TxXferCount == 0U)
 800e5c6:	687b      	ldr	r3, [r7, #4]
 800e5c8:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 800e5cc:	b29b      	uxth	r3, r3
 800e5ce:	2b00      	cmp	r3, #0
 800e5d0:	d132      	bne.n	800e638 <UART_TxISR_16BIT+0x84>
    {
      /* Disable the UART Transmit Data Register Empty Interrupt */
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
 800e5d2:	687b      	ldr	r3, [r7, #4]
 800e5d4:	681b      	ldr	r3, [r3, #0]
 800e5d6:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e5d8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800e5da:	e853 3f00 	ldrex	r3, [r3]
 800e5de:	623b      	str	r3, [r7, #32]
   return(result);
 800e5e0:	6a3b      	ldr	r3, [r7, #32]
 800e5e2:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 800e5e6:	63bb      	str	r3, [r7, #56]	@ 0x38
 800e5e8:	687b      	ldr	r3, [r7, #4]
 800e5ea:	681b      	ldr	r3, [r3, #0]
 800e5ec:	461a      	mov	r2, r3
 800e5ee:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800e5f0:	633b      	str	r3, [r7, #48]	@ 0x30
 800e5f2:	62fa      	str	r2, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e5f4:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 800e5f6:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 800e5f8:	e841 2300 	strex	r3, r2, [r1]
 800e5fc:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 800e5fe:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800e600:	2b00      	cmp	r3, #0
 800e602:	d1e6      	bne.n	800e5d2 <UART_TxISR_16BIT+0x1e>

      /* Enable the UART Transmit Complete Interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 800e604:	687b      	ldr	r3, [r7, #4]
 800e606:	681b      	ldr	r3, [r3, #0]
 800e608:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e60a:	693b      	ldr	r3, [r7, #16]
 800e60c:	e853 3f00 	ldrex	r3, [r3]
 800e610:	60fb      	str	r3, [r7, #12]
   return(result);
 800e612:	68fb      	ldr	r3, [r7, #12]
 800e614:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 800e618:	637b      	str	r3, [r7, #52]	@ 0x34
 800e61a:	687b      	ldr	r3, [r7, #4]
 800e61c:	681b      	ldr	r3, [r3, #0]
 800e61e:	461a      	mov	r2, r3
 800e620:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800e622:	61fb      	str	r3, [r7, #28]
 800e624:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e626:	69b9      	ldr	r1, [r7, #24]
 800e628:	69fa      	ldr	r2, [r7, #28]
 800e62a:	e841 2300 	strex	r3, r2, [r1]
 800e62e:	617b      	str	r3, [r7, #20]
   return(result);
 800e630:	697b      	ldr	r3, [r7, #20]
 800e632:	2b00      	cmp	r3, #0
 800e634:	d1e6      	bne.n	800e604 <UART_TxISR_16BIT+0x50>
      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
      huart->pTxBuffPtr += 2U;
      huart->TxXferCount--;
    }
  }
}
 800e636:	e018      	b.n	800e66a <UART_TxISR_16BIT+0xb6>
      tmp = (const uint16_t *) huart->pTxBuffPtr;
 800e638:	687b      	ldr	r3, [r7, #4]
 800e63a:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800e63c:	63fb      	str	r3, [r7, #60]	@ 0x3c
      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
 800e63e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800e640:	881b      	ldrh	r3, [r3, #0]
 800e642:	461a      	mov	r2, r3
 800e644:	687b      	ldr	r3, [r7, #4]
 800e646:	681b      	ldr	r3, [r3, #0]
 800e648:	f3c2 0208 	ubfx	r2, r2, #0, #9
 800e64c:	629a      	str	r2, [r3, #40]	@ 0x28
      huart->pTxBuffPtr += 2U;
 800e64e:	687b      	ldr	r3, [r7, #4]
 800e650:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800e652:	1c9a      	adds	r2, r3, #2
 800e654:	687b      	ldr	r3, [r7, #4]
 800e656:	651a      	str	r2, [r3, #80]	@ 0x50
      huart->TxXferCount--;
 800e658:	687b      	ldr	r3, [r7, #4]
 800e65a:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 800e65e:	b29b      	uxth	r3, r3
 800e660:	3b01      	subs	r3, #1
 800e662:	b29a      	uxth	r2, r3
 800e664:	687b      	ldr	r3, [r7, #4]
 800e666:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
}
 800e66a:	bf00      	nop
 800e66c:	3744      	adds	r7, #68	@ 0x44
 800e66e:	46bd      	mov	sp, r7
 800e670:	f85d 7b04 	ldr.w	r7, [sp], #4
 800e674:	4770      	bx	lr

0800e676 <UART_TxISR_8BIT_FIFOEN>:
  *         interruptions have been enabled by HAL_UART_Transmit_IT().
  * @param huart UART handle.
  * @retval None
  */
static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
{
 800e676:	b480      	push	{r7}
 800e678:	b091      	sub	sp, #68	@ 0x44
 800e67a:	af00      	add	r7, sp, #0
 800e67c:	6078      	str	r0, [r7, #4]
  uint16_t  nb_tx_data;

  /* Check that a Tx process is ongoing */
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 800e67e:	687b      	ldr	r3, [r7, #4]
 800e680:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800e684:	2b21      	cmp	r3, #33	@ 0x21
 800e686:	d160      	bne.n	800e74a <UART_TxISR_8BIT_FIFOEN+0xd4>
  {
    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
 800e688:	687b      	ldr	r3, [r7, #4]
 800e68a:	f8b3 306a 	ldrh.w	r3, [r3, #106]	@ 0x6a
 800e68e:	87fb      	strh	r3, [r7, #62]	@ 0x3e
 800e690:	e057      	b.n	800e742 <UART_TxISR_8BIT_FIFOEN+0xcc>
    {
      if (huart->TxXferCount == 0U)
 800e692:	687b      	ldr	r3, [r7, #4]
 800e694:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 800e698:	b29b      	uxth	r3, r3
 800e69a:	2b00      	cmp	r3, #0
 800e69c:	d133      	bne.n	800e706 <UART_TxISR_8BIT_FIFOEN+0x90>
      {
        /* Disable the TX FIFO threshold interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
 800e69e:	687b      	ldr	r3, [r7, #4]
 800e6a0:	681b      	ldr	r3, [r3, #0]
 800e6a2:	3308      	adds	r3, #8
 800e6a4:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e6a6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800e6a8:	e853 3f00 	ldrex	r3, [r3]
 800e6ac:	623b      	str	r3, [r7, #32]
   return(result);
 800e6ae:	6a3b      	ldr	r3, [r7, #32]
 800e6b0:	f423 0300 	bic.w	r3, r3, #8388608	@ 0x800000
 800e6b4:	63bb      	str	r3, [r7, #56]	@ 0x38
 800e6b6:	687b      	ldr	r3, [r7, #4]
 800e6b8:	681b      	ldr	r3, [r3, #0]
 800e6ba:	3308      	adds	r3, #8
 800e6bc:	6bba      	ldr	r2, [r7, #56]	@ 0x38
 800e6be:	633a      	str	r2, [r7, #48]	@ 0x30
 800e6c0:	62fb      	str	r3, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e6c2:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 800e6c4:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 800e6c6:	e841 2300 	strex	r3, r2, [r1]
 800e6ca:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 800e6cc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800e6ce:	2b00      	cmp	r3, #0
 800e6d0:	d1e5      	bne.n	800e69e <UART_TxISR_8BIT_FIFOEN+0x28>

        /* Enable the UART Transmit Complete Interrupt */
        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 800e6d2:	687b      	ldr	r3, [r7, #4]
 800e6d4:	681b      	ldr	r3, [r3, #0]
 800e6d6:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e6d8:	693b      	ldr	r3, [r7, #16]
 800e6da:	e853 3f00 	ldrex	r3, [r3]
 800e6de:	60fb      	str	r3, [r7, #12]
   return(result);
 800e6e0:	68fb      	ldr	r3, [r7, #12]
 800e6e2:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 800e6e6:	637b      	str	r3, [r7, #52]	@ 0x34
 800e6e8:	687b      	ldr	r3, [r7, #4]
 800e6ea:	681b      	ldr	r3, [r3, #0]
 800e6ec:	461a      	mov	r2, r3
 800e6ee:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800e6f0:	61fb      	str	r3, [r7, #28]
 800e6f2:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e6f4:	69b9      	ldr	r1, [r7, #24]
 800e6f6:	69fa      	ldr	r2, [r7, #28]
 800e6f8:	e841 2300 	strex	r3, r2, [r1]
 800e6fc:	617b      	str	r3, [r7, #20]
   return(result);
 800e6fe:	697b      	ldr	r3, [r7, #20]
 800e700:	2b00      	cmp	r3, #0
 800e702:	d1e6      	bne.n	800e6d2 <UART_TxISR_8BIT_FIFOEN+0x5c>

        break; /* force exit loop */
 800e704:	e021      	b.n	800e74a <UART_TxISR_8BIT_FIFOEN+0xd4>
      }
      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
 800e706:	687b      	ldr	r3, [r7, #4]
 800e708:	681b      	ldr	r3, [r3, #0]
 800e70a:	69db      	ldr	r3, [r3, #28]
 800e70c:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 800e710:	2b00      	cmp	r3, #0
 800e712:	d013      	beq.n	800e73c <UART_TxISR_8BIT_FIFOEN+0xc6>
      {
        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
 800e714:	687b      	ldr	r3, [r7, #4]
 800e716:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800e718:	781a      	ldrb	r2, [r3, #0]
 800e71a:	687b      	ldr	r3, [r7, #4]
 800e71c:	681b      	ldr	r3, [r3, #0]
 800e71e:	629a      	str	r2, [r3, #40]	@ 0x28
        huart->pTxBuffPtr++;
 800e720:	687b      	ldr	r3, [r7, #4]
 800e722:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800e724:	1c5a      	adds	r2, r3, #1
 800e726:	687b      	ldr	r3, [r7, #4]
 800e728:	651a      	str	r2, [r3, #80]	@ 0x50
        huart->TxXferCount--;
 800e72a:	687b      	ldr	r3, [r7, #4]
 800e72c:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 800e730:	b29b      	uxth	r3, r3
 800e732:	3b01      	subs	r3, #1
 800e734:	b29a      	uxth	r2, r3
 800e736:	687b      	ldr	r3, [r7, #4]
 800e738:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
 800e73c:	8ffb      	ldrh	r3, [r7, #62]	@ 0x3e
 800e73e:	3b01      	subs	r3, #1
 800e740:	87fb      	strh	r3, [r7, #62]	@ 0x3e
 800e742:	8ffb      	ldrh	r3, [r7, #62]	@ 0x3e
 800e744:	2b00      	cmp	r3, #0
 800e746:	d1a4      	bne.n	800e692 <UART_TxISR_8BIT_FIFOEN+0x1c>
      {
        /* Nothing to do */
      }
    }
  }
}
 800e748:	e7ff      	b.n	800e74a <UART_TxISR_8BIT_FIFOEN+0xd4>
 800e74a:	bf00      	nop
 800e74c:	3744      	adds	r7, #68	@ 0x44
 800e74e:	46bd      	mov	sp, r7
 800e750:	f85d 7b04 	ldr.w	r7, [sp], #4
 800e754:	4770      	bx	lr

0800e756 <UART_TxISR_16BIT_FIFOEN>:
  *         interruptions have been enabled by HAL_UART_Transmit_IT().
  * @param huart UART handle.
  * @retval None
  */
static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
{
 800e756:	b480      	push	{r7}
 800e758:	b091      	sub	sp, #68	@ 0x44
 800e75a:	af00      	add	r7, sp, #0
 800e75c:	6078      	str	r0, [r7, #4]
  const uint16_t *tmp;
  uint16_t  nb_tx_data;

  /* Check that a Tx process is ongoing */
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 800e75e:	687b      	ldr	r3, [r7, #4]
 800e760:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800e764:	2b21      	cmp	r3, #33	@ 0x21
 800e766:	d165      	bne.n	800e834 <UART_TxISR_16BIT_FIFOEN+0xde>
  {
    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
 800e768:	687b      	ldr	r3, [r7, #4]
 800e76a:	f8b3 306a 	ldrh.w	r3, [r3, #106]	@ 0x6a
 800e76e:	87fb      	strh	r3, [r7, #62]	@ 0x3e
 800e770:	e05c      	b.n	800e82c <UART_TxISR_16BIT_FIFOEN+0xd6>
    {
      if (huart->TxXferCount == 0U)
 800e772:	687b      	ldr	r3, [r7, #4]
 800e774:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 800e778:	b29b      	uxth	r3, r3
 800e77a:	2b00      	cmp	r3, #0
 800e77c:	d133      	bne.n	800e7e6 <UART_TxISR_16BIT_FIFOEN+0x90>
      {
        /* Disable the TX FIFO threshold interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
 800e77e:	687b      	ldr	r3, [r7, #4]
 800e780:	681b      	ldr	r3, [r3, #0]
 800e782:	3308      	adds	r3, #8
 800e784:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e786:	6a3b      	ldr	r3, [r7, #32]
 800e788:	e853 3f00 	ldrex	r3, [r3]
 800e78c:	61fb      	str	r3, [r7, #28]
   return(result);
 800e78e:	69fb      	ldr	r3, [r7, #28]
 800e790:	f423 0300 	bic.w	r3, r3, #8388608	@ 0x800000
 800e794:	637b      	str	r3, [r7, #52]	@ 0x34
 800e796:	687b      	ldr	r3, [r7, #4]
 800e798:	681b      	ldr	r3, [r3, #0]
 800e79a:	3308      	adds	r3, #8
 800e79c:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 800e79e:	62fa      	str	r2, [r7, #44]	@ 0x2c
 800e7a0:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e7a2:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 800e7a4:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 800e7a6:	e841 2300 	strex	r3, r2, [r1]
 800e7aa:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 800e7ac:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800e7ae:	2b00      	cmp	r3, #0
 800e7b0:	d1e5      	bne.n	800e77e <UART_TxISR_16BIT_FIFOEN+0x28>

        /* Enable the UART Transmit Complete Interrupt */
        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 800e7b2:	687b      	ldr	r3, [r7, #4]
 800e7b4:	681b      	ldr	r3, [r3, #0]
 800e7b6:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e7b8:	68fb      	ldr	r3, [r7, #12]
 800e7ba:	e853 3f00 	ldrex	r3, [r3]
 800e7be:	60bb      	str	r3, [r7, #8]
   return(result);
 800e7c0:	68bb      	ldr	r3, [r7, #8]
 800e7c2:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 800e7c6:	633b      	str	r3, [r7, #48]	@ 0x30
 800e7c8:	687b      	ldr	r3, [r7, #4]
 800e7ca:	681b      	ldr	r3, [r3, #0]
 800e7cc:	461a      	mov	r2, r3
 800e7ce:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800e7d0:	61bb      	str	r3, [r7, #24]
 800e7d2:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e7d4:	6979      	ldr	r1, [r7, #20]
 800e7d6:	69ba      	ldr	r2, [r7, #24]
 800e7d8:	e841 2300 	strex	r3, r2, [r1]
 800e7dc:	613b      	str	r3, [r7, #16]
   return(result);
 800e7de:	693b      	ldr	r3, [r7, #16]
 800e7e0:	2b00      	cmp	r3, #0
 800e7e2:	d1e6      	bne.n	800e7b2 <UART_TxISR_16BIT_FIFOEN+0x5c>

        break; /* force exit loop */
 800e7e4:	e026      	b.n	800e834 <UART_TxISR_16BIT_FIFOEN+0xde>
      }
      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
 800e7e6:	687b      	ldr	r3, [r7, #4]
 800e7e8:	681b      	ldr	r3, [r3, #0]
 800e7ea:	69db      	ldr	r3, [r3, #28]
 800e7ec:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 800e7f0:	2b00      	cmp	r3, #0
 800e7f2:	d018      	beq.n	800e826 <UART_TxISR_16BIT_FIFOEN+0xd0>
      {
        tmp = (const uint16_t *) huart->pTxBuffPtr;
 800e7f4:	687b      	ldr	r3, [r7, #4]
 800e7f6:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800e7f8:	63bb      	str	r3, [r7, #56]	@ 0x38
        huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
 800e7fa:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800e7fc:	881b      	ldrh	r3, [r3, #0]
 800e7fe:	461a      	mov	r2, r3
 800e800:	687b      	ldr	r3, [r7, #4]
 800e802:	681b      	ldr	r3, [r3, #0]
 800e804:	f3c2 0208 	ubfx	r2, r2, #0, #9
 800e808:	629a      	str	r2, [r3, #40]	@ 0x28
        huart->pTxBuffPtr += 2U;
 800e80a:	687b      	ldr	r3, [r7, #4]
 800e80c:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800e80e:	1c9a      	adds	r2, r3, #2
 800e810:	687b      	ldr	r3, [r7, #4]
 800e812:	651a      	str	r2, [r3, #80]	@ 0x50
        huart->TxXferCount--;
 800e814:	687b      	ldr	r3, [r7, #4]
 800e816:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 800e81a:	b29b      	uxth	r3, r3
 800e81c:	3b01      	subs	r3, #1
 800e81e:	b29a      	uxth	r2, r3
 800e820:	687b      	ldr	r3, [r7, #4]
 800e822:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
 800e826:	8ffb      	ldrh	r3, [r7, #62]	@ 0x3e
 800e828:	3b01      	subs	r3, #1
 800e82a:	87fb      	strh	r3, [r7, #62]	@ 0x3e
 800e82c:	8ffb      	ldrh	r3, [r7, #62]	@ 0x3e
 800e82e:	2b00      	cmp	r3, #0
 800e830:	d19f      	bne.n	800e772 <UART_TxISR_16BIT_FIFOEN+0x1c>
      {
        /* Nothing to do */
      }
    }
  }
}
 800e832:	e7ff      	b.n	800e834 <UART_TxISR_16BIT_FIFOEN+0xde>
 800e834:	bf00      	nop
 800e836:	3744      	adds	r7, #68	@ 0x44
 800e838:	46bd      	mov	sp, r7
 800e83a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800e83e:	4770      	bx	lr

0800e840 <UART_EndTransmit_IT>:
  * @param  huart pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
 800e840:	b580      	push	{r7, lr}
 800e842:	b088      	sub	sp, #32
 800e844:	af00      	add	r7, sp, #0
 800e846:	6078      	str	r0, [r7, #4]
  /* Disable the UART Transmit Complete Interrupt */
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 800e848:	687b      	ldr	r3, [r7, #4]
 800e84a:	681b      	ldr	r3, [r3, #0]
 800e84c:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e84e:	68fb      	ldr	r3, [r7, #12]
 800e850:	e853 3f00 	ldrex	r3, [r3]
 800e854:	60bb      	str	r3, [r7, #8]
   return(result);
 800e856:	68bb      	ldr	r3, [r7, #8]
 800e858:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
 800e85c:	61fb      	str	r3, [r7, #28]
 800e85e:	687b      	ldr	r3, [r7, #4]
 800e860:	681b      	ldr	r3, [r3, #0]
 800e862:	461a      	mov	r2, r3
 800e864:	69fb      	ldr	r3, [r7, #28]
 800e866:	61bb      	str	r3, [r7, #24]
 800e868:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e86a:	6979      	ldr	r1, [r7, #20]
 800e86c:	69ba      	ldr	r2, [r7, #24]
 800e86e:	e841 2300 	strex	r3, r2, [r1]
 800e872:	613b      	str	r3, [r7, #16]
   return(result);
 800e874:	693b      	ldr	r3, [r7, #16]
 800e876:	2b00      	cmp	r3, #0
 800e878:	d1e6      	bne.n	800e848 <UART_EndTransmit_IT+0x8>

  /* Tx process is ended, restore huart->gState to Ready */
  huart->gState = HAL_UART_STATE_READY;
 800e87a:	687b      	ldr	r3, [r7, #4]
 800e87c:	2220      	movs	r2, #32
 800e87e:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Cleat TxISR function pointer */
  huart->TxISR = NULL;
 800e882:	687b      	ldr	r3, [r7, #4]
 800e884:	2200      	movs	r2, #0
 800e886:	679a      	str	r2, [r3, #120]	@ 0x78
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  /*Call registered Tx complete callback*/
  huart->TxCpltCallback(huart);
#else
  /*Call legacy weak Tx complete callback*/
  HAL_UART_TxCpltCallback(huart);
 800e888:	6878      	ldr	r0, [r7, #4]
 800e88a:	f7f4 f8dd 	bl	8002a48 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
 800e88e:	bf00      	nop
 800e890:	3720      	adds	r7, #32
 800e892:	46bd      	mov	sp, r7
 800e894:	bd80      	pop	{r7, pc}
	...

0800e898 <UART_RxISR_8BIT>:
  * @brief RX interrupt handler for 7 or 8 bits data word length .
  * @param huart UART handle.
  * @retval None
  */
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
{
 800e898:	b580      	push	{r7, lr}
 800e89a:	b09c      	sub	sp, #112	@ 0x70
 800e89c:	af00      	add	r7, sp, #0
 800e89e:	6078      	str	r0, [r7, #4]
  uint16_t uhMask = huart->Mask;
 800e8a0:	687b      	ldr	r3, [r7, #4]
 800e8a2:	f8b3 3060 	ldrh.w	r3, [r3, #96]	@ 0x60
 800e8a6:	f8a7 306e 	strh.w	r3, [r7, #110]	@ 0x6e
  uint16_t  uhdata;

  /* Check that a Rx process is ongoing */
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 800e8aa:	687b      	ldr	r3, [r7, #4]
 800e8ac:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 800e8b0:	2b22      	cmp	r3, #34	@ 0x22
 800e8b2:	f040 80be 	bne.w	800ea32 <UART_RxISR_8BIT+0x19a>
  {
    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
 800e8b6:	687b      	ldr	r3, [r7, #4]
 800e8b8:	681b      	ldr	r3, [r3, #0]
 800e8ba:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800e8bc:	f8a7 306c 	strh.w	r3, [r7, #108]	@ 0x6c
    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
 800e8c0:	f8b7 306c 	ldrh.w	r3, [r7, #108]	@ 0x6c
 800e8c4:	b2d9      	uxtb	r1, r3
 800e8c6:	f8b7 306e 	ldrh.w	r3, [r7, #110]	@ 0x6e
 800e8ca:	b2da      	uxtb	r2, r3
 800e8cc:	687b      	ldr	r3, [r7, #4]
 800e8ce:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800e8d0:	400a      	ands	r2, r1
 800e8d2:	b2d2      	uxtb	r2, r2
 800e8d4:	701a      	strb	r2, [r3, #0]
    huart->pRxBuffPtr++;
 800e8d6:	687b      	ldr	r3, [r7, #4]
 800e8d8:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800e8da:	1c5a      	adds	r2, r3, #1
 800e8dc:	687b      	ldr	r3, [r7, #4]
 800e8de:	659a      	str	r2, [r3, #88]	@ 0x58
    huart->RxXferCount--;
 800e8e0:	687b      	ldr	r3, [r7, #4]
 800e8e2:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800e8e6:	b29b      	uxth	r3, r3
 800e8e8:	3b01      	subs	r3, #1
 800e8ea:	b29a      	uxth	r2, r3
 800e8ec:	687b      	ldr	r3, [r7, #4]
 800e8ee:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e

    if (huart->RxXferCount == 0U)
 800e8f2:	687b      	ldr	r3, [r7, #4]
 800e8f4:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800e8f8:	b29b      	uxth	r3, r3
 800e8fa:	2b00      	cmp	r3, #0
 800e8fc:	f040 80a1 	bne.w	800ea42 <UART_RxISR_8BIT+0x1aa>
    {
      /* Disable the UART Parity Error Interrupt and RXNE interrupts */
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 800e900:	687b      	ldr	r3, [r7, #4]
 800e902:	681b      	ldr	r3, [r3, #0]
 800e904:	64fb      	str	r3, [r7, #76]	@ 0x4c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e906:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 800e908:	e853 3f00 	ldrex	r3, [r3]
 800e90c:	64bb      	str	r3, [r7, #72]	@ 0x48
   return(result);
 800e90e:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 800e910:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 800e914:	66bb      	str	r3, [r7, #104]	@ 0x68
 800e916:	687b      	ldr	r3, [r7, #4]
 800e918:	681b      	ldr	r3, [r3, #0]
 800e91a:	461a      	mov	r2, r3
 800e91c:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 800e91e:	65bb      	str	r3, [r7, #88]	@ 0x58
 800e920:	657a      	str	r2, [r7, #84]	@ 0x54
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e922:	6d79      	ldr	r1, [r7, #84]	@ 0x54
 800e924:	6dba      	ldr	r2, [r7, #88]	@ 0x58
 800e926:	e841 2300 	strex	r3, r2, [r1]
 800e92a:	653b      	str	r3, [r7, #80]	@ 0x50
   return(result);
 800e92c:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 800e92e:	2b00      	cmp	r3, #0
 800e930:	d1e6      	bne.n	800e900 <UART_RxISR_8BIT+0x68>

      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800e932:	687b      	ldr	r3, [r7, #4]
 800e934:	681b      	ldr	r3, [r3, #0]
 800e936:	3308      	adds	r3, #8
 800e938:	63bb      	str	r3, [r7, #56]	@ 0x38
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e93a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800e93c:	e853 3f00 	ldrex	r3, [r3]
 800e940:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 800e942:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800e944:	f023 0301 	bic.w	r3, r3, #1
 800e948:	667b      	str	r3, [r7, #100]	@ 0x64
 800e94a:	687b      	ldr	r3, [r7, #4]
 800e94c:	681b      	ldr	r3, [r3, #0]
 800e94e:	3308      	adds	r3, #8
 800e950:	6e7a      	ldr	r2, [r7, #100]	@ 0x64
 800e952:	647a      	str	r2, [r7, #68]	@ 0x44
 800e954:	643b      	str	r3, [r7, #64]	@ 0x40
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e956:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 800e958:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 800e95a:	e841 2300 	strex	r3, r2, [r1]
 800e95e:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 800e960:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800e962:	2b00      	cmp	r3, #0
 800e964:	d1e5      	bne.n	800e932 <UART_RxISR_8BIT+0x9a>

      /* Rx process is completed, restore huart->RxState to Ready */
      huart->RxState = HAL_UART_STATE_READY;
 800e966:	687b      	ldr	r3, [r7, #4]
 800e968:	2220      	movs	r2, #32
 800e96a:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c

      /* Clear RxISR function pointer */
      huart->RxISR = NULL;
 800e96e:	687b      	ldr	r3, [r7, #4]
 800e970:	2200      	movs	r2, #0
 800e972:	675a      	str	r2, [r3, #116]	@ 0x74

      /* Initialize type of RxEvent to Transfer Complete */
      huart->RxEventType = HAL_UART_RXEVENT_TC;
 800e974:	687b      	ldr	r3, [r7, #4]
 800e976:	2200      	movs	r2, #0
 800e978:	671a      	str	r2, [r3, #112]	@ 0x70

      if (!(IS_LPUART_INSTANCE(huart->Instance)))
 800e97a:	687b      	ldr	r3, [r7, #4]
 800e97c:	681b      	ldr	r3, [r3, #0]
 800e97e:	4a33      	ldr	r2, [pc, #204]	@ (800ea4c <UART_RxISR_8BIT+0x1b4>)
 800e980:	4293      	cmp	r3, r2
 800e982:	d01f      	beq.n	800e9c4 <UART_RxISR_8BIT+0x12c>
      {
        /* Check that USART RTOEN bit is set */
        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
 800e984:	687b      	ldr	r3, [r7, #4]
 800e986:	681b      	ldr	r3, [r3, #0]
 800e988:	685b      	ldr	r3, [r3, #4]
 800e98a:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 800e98e:	2b00      	cmp	r3, #0
 800e990:	d018      	beq.n	800e9c4 <UART_RxISR_8BIT+0x12c>
        {
          /* Enable the UART Receiver Timeout Interrupt */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
 800e992:	687b      	ldr	r3, [r7, #4]
 800e994:	681b      	ldr	r3, [r3, #0]
 800e996:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e998:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800e99a:	e853 3f00 	ldrex	r3, [r3]
 800e99e:	623b      	str	r3, [r7, #32]
   return(result);
 800e9a0:	6a3b      	ldr	r3, [r7, #32]
 800e9a2:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 800e9a6:	663b      	str	r3, [r7, #96]	@ 0x60
 800e9a8:	687b      	ldr	r3, [r7, #4]
 800e9aa:	681b      	ldr	r3, [r3, #0]
 800e9ac:	461a      	mov	r2, r3
 800e9ae:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 800e9b0:	633b      	str	r3, [r7, #48]	@ 0x30
 800e9b2:	62fa      	str	r2, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e9b4:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 800e9b6:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 800e9b8:	e841 2300 	strex	r3, r2, [r1]
 800e9bc:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 800e9be:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800e9c0:	2b00      	cmp	r3, #0
 800e9c2:	d1e6      	bne.n	800e992 <UART_RxISR_8BIT+0xfa>
        }
      }

      /* Check current reception Mode :
         If Reception till IDLE event has been selected : */
      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 800e9c4:	687b      	ldr	r3, [r7, #4]
 800e9c6:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800e9c8:	2b01      	cmp	r3, #1
 800e9ca:	d12e      	bne.n	800ea2a <UART_RxISR_8BIT+0x192>
      {
        /* Set reception type to Standard */
        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800e9cc:	687b      	ldr	r3, [r7, #4]
 800e9ce:	2200      	movs	r2, #0
 800e9d0:	66da      	str	r2, [r3, #108]	@ 0x6c

        /* Disable IDLE interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 800e9d2:	687b      	ldr	r3, [r7, #4]
 800e9d4:	681b      	ldr	r3, [r3, #0]
 800e9d6:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800e9d8:	693b      	ldr	r3, [r7, #16]
 800e9da:	e853 3f00 	ldrex	r3, [r3]
 800e9de:	60fb      	str	r3, [r7, #12]
   return(result);
 800e9e0:	68fb      	ldr	r3, [r7, #12]
 800e9e2:	f023 0310 	bic.w	r3, r3, #16
 800e9e6:	65fb      	str	r3, [r7, #92]	@ 0x5c
 800e9e8:	687b      	ldr	r3, [r7, #4]
 800e9ea:	681b      	ldr	r3, [r3, #0]
 800e9ec:	461a      	mov	r2, r3
 800e9ee:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 800e9f0:	61fb      	str	r3, [r7, #28]
 800e9f2:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800e9f4:	69b9      	ldr	r1, [r7, #24]
 800e9f6:	69fa      	ldr	r2, [r7, #28]
 800e9f8:	e841 2300 	strex	r3, r2, [r1]
 800e9fc:	617b      	str	r3, [r7, #20]
   return(result);
 800e9fe:	697b      	ldr	r3, [r7, #20]
 800ea00:	2b00      	cmp	r3, #0
 800ea02:	d1e6      	bne.n	800e9d2 <UART_RxISR_8BIT+0x13a>

        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
 800ea04:	687b      	ldr	r3, [r7, #4]
 800ea06:	681b      	ldr	r3, [r3, #0]
 800ea08:	69db      	ldr	r3, [r3, #28]
 800ea0a:	f003 0310 	and.w	r3, r3, #16
 800ea0e:	2b10      	cmp	r3, #16
 800ea10:	d103      	bne.n	800ea1a <UART_RxISR_8BIT+0x182>
        {
          /* Clear IDLE Flag */
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 800ea12:	687b      	ldr	r3, [r7, #4]
 800ea14:	681b      	ldr	r3, [r3, #0]
 800ea16:	2210      	movs	r2, #16
 800ea18:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered Rx Event callback*/
        huart->RxEventCallback(huart, huart->RxXferSize);
#else
        /*Call legacy weak Rx Event callback*/
        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
 800ea1a:	687b      	ldr	r3, [r7, #4]
 800ea1c:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
 800ea20:	4619      	mov	r1, r3
 800ea22:	6878      	ldr	r0, [r7, #4]
 800ea24:	f7f3 ffe6 	bl	80029f4 <HAL_UARTEx_RxEventCallback>
  else
  {
    /* Clear RXNE interrupt flag */
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  }
}
 800ea28:	e00b      	b.n	800ea42 <UART_RxISR_8BIT+0x1aa>
        HAL_UART_RxCpltCallback(huart);
 800ea2a:	6878      	ldr	r0, [r7, #4]
 800ea2c:	f7f3 ffd8 	bl	80029e0 <HAL_UART_RxCpltCallback>
}
 800ea30:	e007      	b.n	800ea42 <UART_RxISR_8BIT+0x1aa>
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
 800ea32:	687b      	ldr	r3, [r7, #4]
 800ea34:	681b      	ldr	r3, [r3, #0]
 800ea36:	699a      	ldr	r2, [r3, #24]
 800ea38:	687b      	ldr	r3, [r7, #4]
 800ea3a:	681b      	ldr	r3, [r3, #0]
 800ea3c:	f042 0208 	orr.w	r2, r2, #8
 800ea40:	619a      	str	r2, [r3, #24]
}
 800ea42:	bf00      	nop
 800ea44:	3770      	adds	r7, #112	@ 0x70
 800ea46:	46bd      	mov	sp, r7
 800ea48:	bd80      	pop	{r7, pc}
 800ea4a:	bf00      	nop
 800ea4c:	58000c00 	.word	0x58000c00

0800ea50 <UART_RxISR_16BIT>:
  *         interruptions have been enabled by HAL_UART_Receive_IT()
  * @param huart UART handle.
  * @retval None
  */
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
{
 800ea50:	b580      	push	{r7, lr}
 800ea52:	b09c      	sub	sp, #112	@ 0x70
 800ea54:	af00      	add	r7, sp, #0
 800ea56:	6078      	str	r0, [r7, #4]
  uint16_t *tmp;
  uint16_t uhMask = huart->Mask;
 800ea58:	687b      	ldr	r3, [r7, #4]
 800ea5a:	f8b3 3060 	ldrh.w	r3, [r3, #96]	@ 0x60
 800ea5e:	f8a7 306e 	strh.w	r3, [r7, #110]	@ 0x6e
  uint16_t  uhdata;

  /* Check that a Rx process is ongoing */
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 800ea62:	687b      	ldr	r3, [r7, #4]
 800ea64:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 800ea68:	2b22      	cmp	r3, #34	@ 0x22
 800ea6a:	f040 80be 	bne.w	800ebea <UART_RxISR_16BIT+0x19a>
  {
    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
 800ea6e:	687b      	ldr	r3, [r7, #4]
 800ea70:	681b      	ldr	r3, [r3, #0]
 800ea72:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800ea74:	f8a7 306c 	strh.w	r3, [r7, #108]	@ 0x6c
    tmp = (uint16_t *) huart->pRxBuffPtr ;
 800ea78:	687b      	ldr	r3, [r7, #4]
 800ea7a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800ea7c:	66bb      	str	r3, [r7, #104]	@ 0x68
    *tmp = (uint16_t)(uhdata & uhMask);
 800ea7e:	f8b7 206c 	ldrh.w	r2, [r7, #108]	@ 0x6c
 800ea82:	f8b7 306e 	ldrh.w	r3, [r7, #110]	@ 0x6e
 800ea86:	4013      	ands	r3, r2
 800ea88:	b29a      	uxth	r2, r3
 800ea8a:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 800ea8c:	801a      	strh	r2, [r3, #0]
    huart->pRxBuffPtr += 2U;
 800ea8e:	687b      	ldr	r3, [r7, #4]
 800ea90:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800ea92:	1c9a      	adds	r2, r3, #2
 800ea94:	687b      	ldr	r3, [r7, #4]
 800ea96:	659a      	str	r2, [r3, #88]	@ 0x58
    huart->RxXferCount--;
 800ea98:	687b      	ldr	r3, [r7, #4]
 800ea9a:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800ea9e:	b29b      	uxth	r3, r3
 800eaa0:	3b01      	subs	r3, #1
 800eaa2:	b29a      	uxth	r2, r3
 800eaa4:	687b      	ldr	r3, [r7, #4]
 800eaa6:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e

    if (huart->RxXferCount == 0U)
 800eaaa:	687b      	ldr	r3, [r7, #4]
 800eaac:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800eab0:	b29b      	uxth	r3, r3
 800eab2:	2b00      	cmp	r3, #0
 800eab4:	f040 80a1 	bne.w	800ebfa <UART_RxISR_16BIT+0x1aa>
    {
      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 800eab8:	687b      	ldr	r3, [r7, #4]
 800eaba:	681b      	ldr	r3, [r3, #0]
 800eabc:	64bb      	str	r3, [r7, #72]	@ 0x48
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800eabe:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 800eac0:	e853 3f00 	ldrex	r3, [r3]
 800eac4:	647b      	str	r3, [r7, #68]	@ 0x44
   return(result);
 800eac6:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 800eac8:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 800eacc:	667b      	str	r3, [r7, #100]	@ 0x64
 800eace:	687b      	ldr	r3, [r7, #4]
 800ead0:	681b      	ldr	r3, [r3, #0]
 800ead2:	461a      	mov	r2, r3
 800ead4:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 800ead6:	657b      	str	r3, [r7, #84]	@ 0x54
 800ead8:	653a      	str	r2, [r7, #80]	@ 0x50
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800eada:	6d39      	ldr	r1, [r7, #80]	@ 0x50
 800eadc:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
 800eade:	e841 2300 	strex	r3, r2, [r1]
 800eae2:	64fb      	str	r3, [r7, #76]	@ 0x4c
   return(result);
 800eae4:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 800eae6:	2b00      	cmp	r3, #0
 800eae8:	d1e6      	bne.n	800eab8 <UART_RxISR_16BIT+0x68>

      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800eaea:	687b      	ldr	r3, [r7, #4]
 800eaec:	681b      	ldr	r3, [r3, #0]
 800eaee:	3308      	adds	r3, #8
 800eaf0:	637b      	str	r3, [r7, #52]	@ 0x34
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800eaf2:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800eaf4:	e853 3f00 	ldrex	r3, [r3]
 800eaf8:	633b      	str	r3, [r7, #48]	@ 0x30
   return(result);
 800eafa:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800eafc:	f023 0301 	bic.w	r3, r3, #1
 800eb00:	663b      	str	r3, [r7, #96]	@ 0x60
 800eb02:	687b      	ldr	r3, [r7, #4]
 800eb04:	681b      	ldr	r3, [r3, #0]
 800eb06:	3308      	adds	r3, #8
 800eb08:	6e3a      	ldr	r2, [r7, #96]	@ 0x60
 800eb0a:	643a      	str	r2, [r7, #64]	@ 0x40
 800eb0c:	63fb      	str	r3, [r7, #60]	@ 0x3c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800eb0e:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
 800eb10:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
 800eb12:	e841 2300 	strex	r3, r2, [r1]
 800eb16:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 800eb18:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800eb1a:	2b00      	cmp	r3, #0
 800eb1c:	d1e5      	bne.n	800eaea <UART_RxISR_16BIT+0x9a>

      /* Rx process is completed, restore huart->RxState to Ready */
      huart->RxState = HAL_UART_STATE_READY;
 800eb1e:	687b      	ldr	r3, [r7, #4]
 800eb20:	2220      	movs	r2, #32
 800eb22:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c

      /* Clear RxISR function pointer */
      huart->RxISR = NULL;
 800eb26:	687b      	ldr	r3, [r7, #4]
 800eb28:	2200      	movs	r2, #0
 800eb2a:	675a      	str	r2, [r3, #116]	@ 0x74

      /* Initialize type of RxEvent to Transfer Complete */
      huart->RxEventType = HAL_UART_RXEVENT_TC;
 800eb2c:	687b      	ldr	r3, [r7, #4]
 800eb2e:	2200      	movs	r2, #0
 800eb30:	671a      	str	r2, [r3, #112]	@ 0x70

      if (!(IS_LPUART_INSTANCE(huart->Instance)))
 800eb32:	687b      	ldr	r3, [r7, #4]
 800eb34:	681b      	ldr	r3, [r3, #0]
 800eb36:	4a33      	ldr	r2, [pc, #204]	@ (800ec04 <UART_RxISR_16BIT+0x1b4>)
 800eb38:	4293      	cmp	r3, r2
 800eb3a:	d01f      	beq.n	800eb7c <UART_RxISR_16BIT+0x12c>
      {
        /* Check that USART RTOEN bit is set */
        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
 800eb3c:	687b      	ldr	r3, [r7, #4]
 800eb3e:	681b      	ldr	r3, [r3, #0]
 800eb40:	685b      	ldr	r3, [r3, #4]
 800eb42:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 800eb46:	2b00      	cmp	r3, #0
 800eb48:	d018      	beq.n	800eb7c <UART_RxISR_16BIT+0x12c>
        {
          /* Enable the UART Receiver Timeout Interrupt */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
 800eb4a:	687b      	ldr	r3, [r7, #4]
 800eb4c:	681b      	ldr	r3, [r3, #0]
 800eb4e:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800eb50:	6a3b      	ldr	r3, [r7, #32]
 800eb52:	e853 3f00 	ldrex	r3, [r3]
 800eb56:	61fb      	str	r3, [r7, #28]
   return(result);
 800eb58:	69fb      	ldr	r3, [r7, #28]
 800eb5a:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 800eb5e:	65fb      	str	r3, [r7, #92]	@ 0x5c
 800eb60:	687b      	ldr	r3, [r7, #4]
 800eb62:	681b      	ldr	r3, [r3, #0]
 800eb64:	461a      	mov	r2, r3
 800eb66:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 800eb68:	62fb      	str	r3, [r7, #44]	@ 0x2c
 800eb6a:	62ba      	str	r2, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800eb6c:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 800eb6e:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 800eb70:	e841 2300 	strex	r3, r2, [r1]
 800eb74:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 800eb76:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800eb78:	2b00      	cmp	r3, #0
 800eb7a:	d1e6      	bne.n	800eb4a <UART_RxISR_16BIT+0xfa>
        }
      }

      /* Check current reception Mode :
         If Reception till IDLE event has been selected : */
      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 800eb7c:	687b      	ldr	r3, [r7, #4]
 800eb7e:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800eb80:	2b01      	cmp	r3, #1
 800eb82:	d12e      	bne.n	800ebe2 <UART_RxISR_16BIT+0x192>
      {
        /* Set reception type to Standard */
        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800eb84:	687b      	ldr	r3, [r7, #4]
 800eb86:	2200      	movs	r2, #0
 800eb88:	66da      	str	r2, [r3, #108]	@ 0x6c

        /* Disable IDLE interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 800eb8a:	687b      	ldr	r3, [r7, #4]
 800eb8c:	681b      	ldr	r3, [r3, #0]
 800eb8e:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800eb90:	68fb      	ldr	r3, [r7, #12]
 800eb92:	e853 3f00 	ldrex	r3, [r3]
 800eb96:	60bb      	str	r3, [r7, #8]
   return(result);
 800eb98:	68bb      	ldr	r3, [r7, #8]
 800eb9a:	f023 0310 	bic.w	r3, r3, #16
 800eb9e:	65bb      	str	r3, [r7, #88]	@ 0x58
 800eba0:	687b      	ldr	r3, [r7, #4]
 800eba2:	681b      	ldr	r3, [r3, #0]
 800eba4:	461a      	mov	r2, r3
 800eba6:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
 800eba8:	61bb      	str	r3, [r7, #24]
 800ebaa:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800ebac:	6979      	ldr	r1, [r7, #20]
 800ebae:	69ba      	ldr	r2, [r7, #24]
 800ebb0:	e841 2300 	strex	r3, r2, [r1]
 800ebb4:	613b      	str	r3, [r7, #16]
   return(result);
 800ebb6:	693b      	ldr	r3, [r7, #16]
 800ebb8:	2b00      	cmp	r3, #0
 800ebba:	d1e6      	bne.n	800eb8a <UART_RxISR_16BIT+0x13a>

        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
 800ebbc:	687b      	ldr	r3, [r7, #4]
 800ebbe:	681b      	ldr	r3, [r3, #0]
 800ebc0:	69db      	ldr	r3, [r3, #28]
 800ebc2:	f003 0310 	and.w	r3, r3, #16
 800ebc6:	2b10      	cmp	r3, #16
 800ebc8:	d103      	bne.n	800ebd2 <UART_RxISR_16BIT+0x182>
        {
          /* Clear IDLE Flag */
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 800ebca:	687b      	ldr	r3, [r7, #4]
 800ebcc:	681b      	ldr	r3, [r3, #0]
 800ebce:	2210      	movs	r2, #16
 800ebd0:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered Rx Event callback*/
        huart->RxEventCallback(huart, huart->RxXferSize);
#else
        /*Call legacy weak Rx Event callback*/
        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
 800ebd2:	687b      	ldr	r3, [r7, #4]
 800ebd4:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
 800ebd8:	4619      	mov	r1, r3
 800ebda:	6878      	ldr	r0, [r7, #4]
 800ebdc:	f7f3 ff0a 	bl	80029f4 <HAL_UARTEx_RxEventCallback>
  else
  {
    /* Clear RXNE interrupt flag */
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  }
}
 800ebe0:	e00b      	b.n	800ebfa <UART_RxISR_16BIT+0x1aa>
        HAL_UART_RxCpltCallback(huart);
 800ebe2:	6878      	ldr	r0, [r7, #4]
 800ebe4:	f7f3 fefc 	bl	80029e0 <HAL_UART_RxCpltCallback>
}
 800ebe8:	e007      	b.n	800ebfa <UART_RxISR_16BIT+0x1aa>
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
 800ebea:	687b      	ldr	r3, [r7, #4]
 800ebec:	681b      	ldr	r3, [r3, #0]
 800ebee:	699a      	ldr	r2, [r3, #24]
 800ebf0:	687b      	ldr	r3, [r7, #4]
 800ebf2:	681b      	ldr	r3, [r3, #0]
 800ebf4:	f042 0208 	orr.w	r2, r2, #8
 800ebf8:	619a      	str	r2, [r3, #24]
}
 800ebfa:	bf00      	nop
 800ebfc:	3770      	adds	r7, #112	@ 0x70
 800ebfe:	46bd      	mov	sp, r7
 800ec00:	bd80      	pop	{r7, pc}
 800ec02:	bf00      	nop
 800ec04:	58000c00 	.word	0x58000c00

0800ec08 <UART_RxISR_8BIT_FIFOEN>:
  *         interruptions have been enabled by HAL_UART_Receive_IT()
  * @param huart UART handle.
  * @retval None
  */
static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
{
 800ec08:	b580      	push	{r7, lr}
 800ec0a:	b0ac      	sub	sp, #176	@ 0xb0
 800ec0c:	af00      	add	r7, sp, #0
 800ec0e:	6078      	str	r0, [r7, #4]
  uint16_t  uhMask = huart->Mask;
 800ec10:	687b      	ldr	r3, [r7, #4]
 800ec12:	f8b3 3060 	ldrh.w	r3, [r3, #96]	@ 0x60
 800ec16:	f8a7 30aa 	strh.w	r3, [r7, #170]	@ 0xaa
  uint16_t  uhdata;
  uint16_t  nb_rx_data;
  uint16_t  rxdatacount;
  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
 800ec1a:	687b      	ldr	r3, [r7, #4]
 800ec1c:	681b      	ldr	r3, [r3, #0]
 800ec1e:	69db      	ldr	r3, [r3, #28]
 800ec20:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
 800ec24:	687b      	ldr	r3, [r7, #4]
 800ec26:	681b      	ldr	r3, [r3, #0]
 800ec28:	681b      	ldr	r3, [r3, #0]
 800ec2a:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
 800ec2e:	687b      	ldr	r3, [r7, #4]
 800ec30:	681b      	ldr	r3, [r3, #0]
 800ec32:	689b      	ldr	r3, [r3, #8]
 800ec34:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0

  /* Check that a Rx process is ongoing */
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 800ec38:	687b      	ldr	r3, [r7, #4]
 800ec3a:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 800ec3e:	2b22      	cmp	r3, #34	@ 0x22
 800ec40:	f040 8180 	bne.w	800ef44 <UART_RxISR_8BIT_FIFOEN+0x33c>
  {
    nb_rx_data = huart->NbRxDataToProcess;
 800ec44:	687b      	ldr	r3, [r7, #4]
 800ec46:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
 800ec4a:	f8a7 309e 	strh.w	r3, [r7, #158]	@ 0x9e
    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
 800ec4e:	e123      	b.n	800ee98 <UART_RxISR_8BIT_FIFOEN+0x290>
    {
      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
 800ec50:	687b      	ldr	r3, [r7, #4]
 800ec52:	681b      	ldr	r3, [r3, #0]
 800ec54:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800ec56:	f8a7 309c 	strh.w	r3, [r7, #156]	@ 0x9c
      *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
 800ec5a:	f8b7 309c 	ldrh.w	r3, [r7, #156]	@ 0x9c
 800ec5e:	b2d9      	uxtb	r1, r3
 800ec60:	f8b7 30aa 	ldrh.w	r3, [r7, #170]	@ 0xaa
 800ec64:	b2da      	uxtb	r2, r3
 800ec66:	687b      	ldr	r3, [r7, #4]
 800ec68:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800ec6a:	400a      	ands	r2, r1
 800ec6c:	b2d2      	uxtb	r2, r2
 800ec6e:	701a      	strb	r2, [r3, #0]
      huart->pRxBuffPtr++;
 800ec70:	687b      	ldr	r3, [r7, #4]
 800ec72:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800ec74:	1c5a      	adds	r2, r3, #1
 800ec76:	687b      	ldr	r3, [r7, #4]
 800ec78:	659a      	str	r2, [r3, #88]	@ 0x58
      huart->RxXferCount--;
 800ec7a:	687b      	ldr	r3, [r7, #4]
 800ec7c:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800ec80:	b29b      	uxth	r3, r3
 800ec82:	3b01      	subs	r3, #1
 800ec84:	b29a      	uxth	r2, r3
 800ec86:	687b      	ldr	r3, [r7, #4]
 800ec88:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
      isrflags = READ_REG(huart->Instance->ISR);
 800ec8c:	687b      	ldr	r3, [r7, #4]
 800ec8e:	681b      	ldr	r3, [r3, #0]
 800ec90:	69db      	ldr	r3, [r3, #28]
 800ec92:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac

      /* If some non blocking errors occurred */
      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
 800ec96:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 800ec9a:	f003 0307 	and.w	r3, r3, #7
 800ec9e:	2b00      	cmp	r3, #0
 800eca0:	d053      	beq.n	800ed4a <UART_RxISR_8BIT_FIFOEN+0x142>
      {
        /* UART parity error interrupt occurred -------------------------------------*/
        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
 800eca2:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 800eca6:	f003 0301 	and.w	r3, r3, #1
 800ecaa:	2b00      	cmp	r3, #0
 800ecac:	d011      	beq.n	800ecd2 <UART_RxISR_8BIT_FIFOEN+0xca>
 800ecae:	f8d7 30a4 	ldr.w	r3, [r7, #164]	@ 0xa4
 800ecb2:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800ecb6:	2b00      	cmp	r3, #0
 800ecb8:	d00b      	beq.n	800ecd2 <UART_RxISR_8BIT_FIFOEN+0xca>
        {
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
 800ecba:	687b      	ldr	r3, [r7, #4]
 800ecbc:	681b      	ldr	r3, [r3, #0]
 800ecbe:	2201      	movs	r2, #1
 800ecc0:	621a      	str	r2, [r3, #32]

          huart->ErrorCode |= HAL_UART_ERROR_PE;
 800ecc2:	687b      	ldr	r3, [r7, #4]
 800ecc4:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800ecc8:	f043 0201 	orr.w	r2, r3, #1
 800eccc:	687b      	ldr	r3, [r7, #4]
 800ecce:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }

        /* UART frame error interrupt occurred --------------------------------------*/
        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 800ecd2:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 800ecd6:	f003 0302 	and.w	r3, r3, #2
 800ecda:	2b00      	cmp	r3, #0
 800ecdc:	d011      	beq.n	800ed02 <UART_RxISR_8BIT_FIFOEN+0xfa>
 800ecde:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
 800ece2:	f003 0301 	and.w	r3, r3, #1
 800ece6:	2b00      	cmp	r3, #0
 800ece8:	d00b      	beq.n	800ed02 <UART_RxISR_8BIT_FIFOEN+0xfa>
        {
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
 800ecea:	687b      	ldr	r3, [r7, #4]
 800ecec:	681b      	ldr	r3, [r3, #0]
 800ecee:	2202      	movs	r2, #2
 800ecf0:	621a      	str	r2, [r3, #32]

          huart->ErrorCode |= HAL_UART_ERROR_FE;
 800ecf2:	687b      	ldr	r3, [r7, #4]
 800ecf4:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800ecf8:	f043 0204 	orr.w	r2, r3, #4
 800ecfc:	687b      	ldr	r3, [r7, #4]
 800ecfe:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }

        /* UART noise error interrupt occurred --------------------------------------*/
        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 800ed02:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 800ed06:	f003 0304 	and.w	r3, r3, #4
 800ed0a:	2b00      	cmp	r3, #0
 800ed0c:	d011      	beq.n	800ed32 <UART_RxISR_8BIT_FIFOEN+0x12a>
 800ed0e:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
 800ed12:	f003 0301 	and.w	r3, r3, #1
 800ed16:	2b00      	cmp	r3, #0
 800ed18:	d00b      	beq.n	800ed32 <UART_RxISR_8BIT_FIFOEN+0x12a>
        {
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
 800ed1a:	687b      	ldr	r3, [r7, #4]
 800ed1c:	681b      	ldr	r3, [r3, #0]
 800ed1e:	2204      	movs	r2, #4
 800ed20:	621a      	str	r2, [r3, #32]

          huart->ErrorCode |= HAL_UART_ERROR_NE;
 800ed22:	687b      	ldr	r3, [r7, #4]
 800ed24:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800ed28:	f043 0202 	orr.w	r2, r3, #2
 800ed2c:	687b      	ldr	r3, [r7, #4]
 800ed2e:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }

        /* Call UART Error Call back function if need be ----------------------------*/
        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
 800ed32:	687b      	ldr	r3, [r7, #4]
 800ed34:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800ed38:	2b00      	cmp	r3, #0
 800ed3a:	d006      	beq.n	800ed4a <UART_RxISR_8BIT_FIFOEN+0x142>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered error callback*/
          huart->ErrorCallback(huart);
#else
          /*Call legacy weak error callback*/
          HAL_UART_ErrorCallback(huart);
 800ed3c:	6878      	ldr	r0, [r7, #4]
 800ed3e:	f7fe fb13 	bl	800d368 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
          huart->ErrorCode = HAL_UART_ERROR_NONE;
 800ed42:	687b      	ldr	r3, [r7, #4]
 800ed44:	2200      	movs	r2, #0
 800ed46:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }
      }

      if (huart->RxXferCount == 0U)
 800ed4a:	687b      	ldr	r3, [r7, #4]
 800ed4c:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800ed50:	b29b      	uxth	r3, r3
 800ed52:	2b00      	cmp	r3, #0
 800ed54:	f040 80a0 	bne.w	800ee98 <UART_RxISR_8BIT_FIFOEN+0x290>
      {
        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 800ed58:	687b      	ldr	r3, [r7, #4]
 800ed5a:	681b      	ldr	r3, [r3, #0]
 800ed5c:	673b      	str	r3, [r7, #112]	@ 0x70
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800ed5e:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
 800ed60:	e853 3f00 	ldrex	r3, [r3]
 800ed64:	66fb      	str	r3, [r7, #108]	@ 0x6c
   return(result);
 800ed66:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 800ed68:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 800ed6c:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
 800ed70:	687b      	ldr	r3, [r7, #4]
 800ed72:	681b      	ldr	r3, [r3, #0]
 800ed74:	461a      	mov	r2, r3
 800ed76:	f8d7 3098 	ldr.w	r3, [r7, #152]	@ 0x98
 800ed7a:	67fb      	str	r3, [r7, #124]	@ 0x7c
 800ed7c:	67ba      	str	r2, [r7, #120]	@ 0x78
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800ed7e:	6fb9      	ldr	r1, [r7, #120]	@ 0x78
 800ed80:	6ffa      	ldr	r2, [r7, #124]	@ 0x7c
 800ed82:	e841 2300 	strex	r3, r2, [r1]
 800ed86:	677b      	str	r3, [r7, #116]	@ 0x74
   return(result);
 800ed88:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
 800ed8a:	2b00      	cmp	r3, #0
 800ed8c:	d1e4      	bne.n	800ed58 <UART_RxISR_8BIT_FIFOEN+0x150>

        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
           and RX FIFO Threshold interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 800ed8e:	687b      	ldr	r3, [r7, #4]
 800ed90:	681b      	ldr	r3, [r3, #0]
 800ed92:	3308      	adds	r3, #8
 800ed94:	65fb      	str	r3, [r7, #92]	@ 0x5c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800ed96:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 800ed98:	e853 3f00 	ldrex	r3, [r3]
 800ed9c:	65bb      	str	r3, [r7, #88]	@ 0x58
   return(result);
 800ed9e:	6dba      	ldr	r2, [r7, #88]	@ 0x58
 800eda0:	4b6e      	ldr	r3, [pc, #440]	@ (800ef5c <UART_RxISR_8BIT_FIFOEN+0x354>)
 800eda2:	4013      	ands	r3, r2
 800eda4:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
 800eda8:	687b      	ldr	r3, [r7, #4]
 800edaa:	681b      	ldr	r3, [r3, #0]
 800edac:	3308      	adds	r3, #8
 800edae:	f8d7 2094 	ldr.w	r2, [r7, #148]	@ 0x94
 800edb2:	66ba      	str	r2, [r7, #104]	@ 0x68
 800edb4:	667b      	str	r3, [r7, #100]	@ 0x64
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800edb6:	6e79      	ldr	r1, [r7, #100]	@ 0x64
 800edb8:	6eba      	ldr	r2, [r7, #104]	@ 0x68
 800edba:	e841 2300 	strex	r3, r2, [r1]
 800edbe:	663b      	str	r3, [r7, #96]	@ 0x60
   return(result);
 800edc0:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 800edc2:	2b00      	cmp	r3, #0
 800edc4:	d1e3      	bne.n	800ed8e <UART_RxISR_8BIT_FIFOEN+0x186>

        /* Rx process is completed, restore huart->RxState to Ready */
        huart->RxState = HAL_UART_STATE_READY;
 800edc6:	687b      	ldr	r3, [r7, #4]
 800edc8:	2220      	movs	r2, #32
 800edca:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c

        /* Clear RxISR function pointer */
        huart->RxISR = NULL;
 800edce:	687b      	ldr	r3, [r7, #4]
 800edd0:	2200      	movs	r2, #0
 800edd2:	675a      	str	r2, [r3, #116]	@ 0x74

        /* Initialize type of RxEvent to Transfer Complete */
        huart->RxEventType = HAL_UART_RXEVENT_TC;
 800edd4:	687b      	ldr	r3, [r7, #4]
 800edd6:	2200      	movs	r2, #0
 800edd8:	671a      	str	r2, [r3, #112]	@ 0x70

        if (!(IS_LPUART_INSTANCE(huart->Instance)))
 800edda:	687b      	ldr	r3, [r7, #4]
 800eddc:	681b      	ldr	r3, [r3, #0]
 800edde:	4a60      	ldr	r2, [pc, #384]	@ (800ef60 <UART_RxISR_8BIT_FIFOEN+0x358>)
 800ede0:	4293      	cmp	r3, r2
 800ede2:	d021      	beq.n	800ee28 <UART_RxISR_8BIT_FIFOEN+0x220>
        {
          /* Check that USART RTOEN bit is set */
          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
 800ede4:	687b      	ldr	r3, [r7, #4]
 800ede6:	681b      	ldr	r3, [r3, #0]
 800ede8:	685b      	ldr	r3, [r3, #4]
 800edea:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 800edee:	2b00      	cmp	r3, #0
 800edf0:	d01a      	beq.n	800ee28 <UART_RxISR_8BIT_FIFOEN+0x220>
          {
            /* Enable the UART Receiver Timeout Interrupt */
            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
 800edf2:	687b      	ldr	r3, [r7, #4]
 800edf4:	681b      	ldr	r3, [r3, #0]
 800edf6:	64bb      	str	r3, [r7, #72]	@ 0x48
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800edf8:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 800edfa:	e853 3f00 	ldrex	r3, [r3]
 800edfe:	647b      	str	r3, [r7, #68]	@ 0x44
   return(result);
 800ee00:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 800ee02:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 800ee06:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
 800ee0a:	687b      	ldr	r3, [r7, #4]
 800ee0c:	681b      	ldr	r3, [r3, #0]
 800ee0e:	461a      	mov	r2, r3
 800ee10:	f8d7 3090 	ldr.w	r3, [r7, #144]	@ 0x90
 800ee14:	657b      	str	r3, [r7, #84]	@ 0x54
 800ee16:	653a      	str	r2, [r7, #80]	@ 0x50
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800ee18:	6d39      	ldr	r1, [r7, #80]	@ 0x50
 800ee1a:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
 800ee1c:	e841 2300 	strex	r3, r2, [r1]
 800ee20:	64fb      	str	r3, [r7, #76]	@ 0x4c
   return(result);
 800ee22:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 800ee24:	2b00      	cmp	r3, #0
 800ee26:	d1e4      	bne.n	800edf2 <UART_RxISR_8BIT_FIFOEN+0x1ea>
          }
        }

        /* Check current reception Mode :
           If Reception till IDLE event has been selected : */
        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 800ee28:	687b      	ldr	r3, [r7, #4]
 800ee2a:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800ee2c:	2b01      	cmp	r3, #1
 800ee2e:	d130      	bne.n	800ee92 <UART_RxISR_8BIT_FIFOEN+0x28a>
        {
          /* Set reception type to Standard */
          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800ee30:	687b      	ldr	r3, [r7, #4]
 800ee32:	2200      	movs	r2, #0
 800ee34:	66da      	str	r2, [r3, #108]	@ 0x6c

          /* Disable IDLE interrupt */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 800ee36:	687b      	ldr	r3, [r7, #4]
 800ee38:	681b      	ldr	r3, [r3, #0]
 800ee3a:	637b      	str	r3, [r7, #52]	@ 0x34
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800ee3c:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800ee3e:	e853 3f00 	ldrex	r3, [r3]
 800ee42:	633b      	str	r3, [r7, #48]	@ 0x30
   return(result);
 800ee44:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800ee46:	f023 0310 	bic.w	r3, r3, #16
 800ee4a:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
 800ee4e:	687b      	ldr	r3, [r7, #4]
 800ee50:	681b      	ldr	r3, [r3, #0]
 800ee52:	461a      	mov	r2, r3
 800ee54:	f8d7 308c 	ldr.w	r3, [r7, #140]	@ 0x8c
 800ee58:	643b      	str	r3, [r7, #64]	@ 0x40
 800ee5a:	63fa      	str	r2, [r7, #60]	@ 0x3c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800ee5c:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
 800ee5e:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
 800ee60:	e841 2300 	strex	r3, r2, [r1]
 800ee64:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 800ee66:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800ee68:	2b00      	cmp	r3, #0
 800ee6a:	d1e4      	bne.n	800ee36 <UART_RxISR_8BIT_FIFOEN+0x22e>

          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
 800ee6c:	687b      	ldr	r3, [r7, #4]
 800ee6e:	681b      	ldr	r3, [r3, #0]
 800ee70:	69db      	ldr	r3, [r3, #28]
 800ee72:	f003 0310 	and.w	r3, r3, #16
 800ee76:	2b10      	cmp	r3, #16
 800ee78:	d103      	bne.n	800ee82 <UART_RxISR_8BIT_FIFOEN+0x27a>
          {
            /* Clear IDLE Flag */
            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 800ee7a:	687b      	ldr	r3, [r7, #4]
 800ee7c:	681b      	ldr	r3, [r3, #0]
 800ee7e:	2210      	movs	r2, #16
 800ee80:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered Rx Event callback*/
          huart->RxEventCallback(huart, huart->RxXferSize);
#else
          /*Call legacy weak Rx Event callback*/
          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
 800ee82:	687b      	ldr	r3, [r7, #4]
 800ee84:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
 800ee88:	4619      	mov	r1, r3
 800ee8a:	6878      	ldr	r0, [r7, #4]
 800ee8c:	f7f3 fdb2 	bl	80029f4 <HAL_UARTEx_RxEventCallback>
 800ee90:	e002      	b.n	800ee98 <UART_RxISR_8BIT_FIFOEN+0x290>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered Rx complete callback*/
          huart->RxCpltCallback(huart);
#else
          /*Call legacy weak Rx complete callback*/
          HAL_UART_RxCpltCallback(huart);
 800ee92:	6878      	ldr	r0, [r7, #4]
 800ee94:	f7f3 fda4 	bl	80029e0 <HAL_UART_RxCpltCallback>
    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
 800ee98:	f8b7 309e 	ldrh.w	r3, [r7, #158]	@ 0x9e
 800ee9c:	2b00      	cmp	r3, #0
 800ee9e:	d006      	beq.n	800eeae <UART_RxISR_8BIT_FIFOEN+0x2a6>
 800eea0:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 800eea4:	f003 0320 	and.w	r3, r3, #32
 800eea8:	2b00      	cmp	r3, #0
 800eeaa:	f47f aed1 	bne.w	800ec50 <UART_RxISR_8BIT_FIFOEN+0x48>

    /* When remaining number of bytes to receive is less than the RX FIFO
    threshold, next incoming frames are processed as if FIFO mode was
    disabled (i.e. one interrupt per received frame).
    */
    rxdatacount = huart->RxXferCount;
 800eeae:	687b      	ldr	r3, [r7, #4]
 800eeb0:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800eeb4:	f8a7 308a 	strh.w	r3, [r7, #138]	@ 0x8a
    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
 800eeb8:	f8b7 308a 	ldrh.w	r3, [r7, #138]	@ 0x8a
 800eebc:	2b00      	cmp	r3, #0
 800eebe:	d049      	beq.n	800ef54 <UART_RxISR_8BIT_FIFOEN+0x34c>
 800eec0:	687b      	ldr	r3, [r7, #4]
 800eec2:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
 800eec6:	f8b7 208a 	ldrh.w	r2, [r7, #138]	@ 0x8a
 800eeca:	429a      	cmp	r2, r3
 800eecc:	d242      	bcs.n	800ef54 <UART_RxISR_8BIT_FIFOEN+0x34c>
    {
      /* Disable the UART RXFT interrupt*/
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
 800eece:	687b      	ldr	r3, [r7, #4]
 800eed0:	681b      	ldr	r3, [r3, #0]
 800eed2:	3308      	adds	r3, #8
 800eed4:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800eed6:	6a3b      	ldr	r3, [r7, #32]
 800eed8:	e853 3f00 	ldrex	r3, [r3]
 800eedc:	61fb      	str	r3, [r7, #28]
   return(result);
 800eede:	69fb      	ldr	r3, [r7, #28]
 800eee0:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 800eee4:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
 800eee8:	687b      	ldr	r3, [r7, #4]
 800eeea:	681b      	ldr	r3, [r3, #0]
 800eeec:	3308      	adds	r3, #8
 800eeee:	f8d7 2084 	ldr.w	r2, [r7, #132]	@ 0x84
 800eef2:	62fa      	str	r2, [r7, #44]	@ 0x2c
 800eef4:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800eef6:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 800eef8:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 800eefa:	e841 2300 	strex	r3, r2, [r1]
 800eefe:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 800ef00:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800ef02:	2b00      	cmp	r3, #0
 800ef04:	d1e3      	bne.n	800eece <UART_RxISR_8BIT_FIFOEN+0x2c6>

      /* Update the RxISR function pointer */
      huart->RxISR = UART_RxISR_8BIT;
 800ef06:	687b      	ldr	r3, [r7, #4]
 800ef08:	4a16      	ldr	r2, [pc, #88]	@ (800ef64 <UART_RxISR_8BIT_FIFOEN+0x35c>)
 800ef0a:	675a      	str	r2, [r3, #116]	@ 0x74

      /* Enable the UART Data Register Not Empty interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
 800ef0c:	687b      	ldr	r3, [r7, #4]
 800ef0e:	681b      	ldr	r3, [r3, #0]
 800ef10:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800ef12:	68fb      	ldr	r3, [r7, #12]
 800ef14:	e853 3f00 	ldrex	r3, [r3]
 800ef18:	60bb      	str	r3, [r7, #8]
   return(result);
 800ef1a:	68bb      	ldr	r3, [r7, #8]
 800ef1c:	f043 0320 	orr.w	r3, r3, #32
 800ef20:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
 800ef24:	687b      	ldr	r3, [r7, #4]
 800ef26:	681b      	ldr	r3, [r3, #0]
 800ef28:	461a      	mov	r2, r3
 800ef2a:	f8d7 3080 	ldr.w	r3, [r7, #128]	@ 0x80
 800ef2e:	61bb      	str	r3, [r7, #24]
 800ef30:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800ef32:	6979      	ldr	r1, [r7, #20]
 800ef34:	69ba      	ldr	r2, [r7, #24]
 800ef36:	e841 2300 	strex	r3, r2, [r1]
 800ef3a:	613b      	str	r3, [r7, #16]
   return(result);
 800ef3c:	693b      	ldr	r3, [r7, #16]
 800ef3e:	2b00      	cmp	r3, #0
 800ef40:	d1e4      	bne.n	800ef0c <UART_RxISR_8BIT_FIFOEN+0x304>
  else
  {
    /* Clear RXNE interrupt flag */
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  }
}
 800ef42:	e007      	b.n	800ef54 <UART_RxISR_8BIT_FIFOEN+0x34c>
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
 800ef44:	687b      	ldr	r3, [r7, #4]
 800ef46:	681b      	ldr	r3, [r3, #0]
 800ef48:	699a      	ldr	r2, [r3, #24]
 800ef4a:	687b      	ldr	r3, [r7, #4]
 800ef4c:	681b      	ldr	r3, [r3, #0]
 800ef4e:	f042 0208 	orr.w	r2, r2, #8
 800ef52:	619a      	str	r2, [r3, #24]
}
 800ef54:	bf00      	nop
 800ef56:	37b0      	adds	r7, #176	@ 0xb0
 800ef58:	46bd      	mov	sp, r7
 800ef5a:	bd80      	pop	{r7, pc}
 800ef5c:	effffffe 	.word	0xeffffffe
 800ef60:	58000c00 	.word	0x58000c00
 800ef64:	0800e899 	.word	0x0800e899

0800ef68 <UART_RxISR_16BIT_FIFOEN>:
  *         interruptions have been enabled by HAL_UART_Receive_IT()
  * @param huart UART handle.
  * @retval None
  */
static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
{
 800ef68:	b580      	push	{r7, lr}
 800ef6a:	b0ae      	sub	sp, #184	@ 0xb8
 800ef6c:	af00      	add	r7, sp, #0
 800ef6e:	6078      	str	r0, [r7, #4]
  uint16_t *tmp;
  uint16_t  uhMask = huart->Mask;
 800ef70:	687b      	ldr	r3, [r7, #4]
 800ef72:	f8b3 3060 	ldrh.w	r3, [r3, #96]	@ 0x60
 800ef76:	f8a7 30b2 	strh.w	r3, [r7, #178]	@ 0xb2
  uint16_t  uhdata;
  uint16_t  nb_rx_data;
  uint16_t  rxdatacount;
  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
 800ef7a:	687b      	ldr	r3, [r7, #4]
 800ef7c:	681b      	ldr	r3, [r3, #0]
 800ef7e:	69db      	ldr	r3, [r3, #28]
 800ef80:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
 800ef84:	687b      	ldr	r3, [r7, #4]
 800ef86:	681b      	ldr	r3, [r3, #0]
 800ef88:	681b      	ldr	r3, [r3, #0]
 800ef8a:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
 800ef8e:	687b      	ldr	r3, [r7, #4]
 800ef90:	681b      	ldr	r3, [r3, #0]
 800ef92:	689b      	ldr	r3, [r3, #8]
 800ef94:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8

  /* Check that a Rx process is ongoing */
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 800ef98:	687b      	ldr	r3, [r7, #4]
 800ef9a:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 800ef9e:	2b22      	cmp	r3, #34	@ 0x22
 800efa0:	f040 8184 	bne.w	800f2ac <UART_RxISR_16BIT_FIFOEN+0x344>
  {
    nb_rx_data = huart->NbRxDataToProcess;
 800efa4:	687b      	ldr	r3, [r7, #4]
 800efa6:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
 800efaa:	f8a7 30a6 	strh.w	r3, [r7, #166]	@ 0xa6
    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
 800efae:	e127      	b.n	800f200 <UART_RxISR_16BIT_FIFOEN+0x298>
    {
      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
 800efb0:	687b      	ldr	r3, [r7, #4]
 800efb2:	681b      	ldr	r3, [r3, #0]
 800efb4:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800efb6:	f8a7 30a4 	strh.w	r3, [r7, #164]	@ 0xa4
      tmp = (uint16_t *) huart->pRxBuffPtr ;
 800efba:	687b      	ldr	r3, [r7, #4]
 800efbc:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800efbe:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
      *tmp = (uint16_t)(uhdata & uhMask);
 800efc2:	f8b7 20a4 	ldrh.w	r2, [r7, #164]	@ 0xa4
 800efc6:	f8b7 30b2 	ldrh.w	r3, [r7, #178]	@ 0xb2
 800efca:	4013      	ands	r3, r2
 800efcc:	b29a      	uxth	r2, r3
 800efce:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
 800efd2:	801a      	strh	r2, [r3, #0]
      huart->pRxBuffPtr += 2U;
 800efd4:	687b      	ldr	r3, [r7, #4]
 800efd6:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800efd8:	1c9a      	adds	r2, r3, #2
 800efda:	687b      	ldr	r3, [r7, #4]
 800efdc:	659a      	str	r2, [r3, #88]	@ 0x58
      huart->RxXferCount--;
 800efde:	687b      	ldr	r3, [r7, #4]
 800efe0:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800efe4:	b29b      	uxth	r3, r3
 800efe6:	3b01      	subs	r3, #1
 800efe8:	b29a      	uxth	r2, r3
 800efea:	687b      	ldr	r3, [r7, #4]
 800efec:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
      isrflags = READ_REG(huart->Instance->ISR);
 800eff0:	687b      	ldr	r3, [r7, #4]
 800eff2:	681b      	ldr	r3, [r3, #0]
 800eff4:	69db      	ldr	r3, [r3, #28]
 800eff6:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4

      /* If some non blocking errors occurred */
      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
 800effa:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
 800effe:	f003 0307 	and.w	r3, r3, #7
 800f002:	2b00      	cmp	r3, #0
 800f004:	d053      	beq.n	800f0ae <UART_RxISR_16BIT_FIFOEN+0x146>
      {
        /* UART parity error interrupt occurred -------------------------------------*/
        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
 800f006:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
 800f00a:	f003 0301 	and.w	r3, r3, #1
 800f00e:	2b00      	cmp	r3, #0
 800f010:	d011      	beq.n	800f036 <UART_RxISR_16BIT_FIFOEN+0xce>
 800f012:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 800f016:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800f01a:	2b00      	cmp	r3, #0
 800f01c:	d00b      	beq.n	800f036 <UART_RxISR_16BIT_FIFOEN+0xce>
        {
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
 800f01e:	687b      	ldr	r3, [r7, #4]
 800f020:	681b      	ldr	r3, [r3, #0]
 800f022:	2201      	movs	r2, #1
 800f024:	621a      	str	r2, [r3, #32]

          huart->ErrorCode |= HAL_UART_ERROR_PE;
 800f026:	687b      	ldr	r3, [r7, #4]
 800f028:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800f02c:	f043 0201 	orr.w	r2, r3, #1
 800f030:	687b      	ldr	r3, [r7, #4]
 800f032:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }

        /* UART frame error interrupt occurred --------------------------------------*/
        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 800f036:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
 800f03a:	f003 0302 	and.w	r3, r3, #2
 800f03e:	2b00      	cmp	r3, #0
 800f040:	d011      	beq.n	800f066 <UART_RxISR_16BIT_FIFOEN+0xfe>
 800f042:	f8d7 30a8 	ldr.w	r3, [r7, #168]	@ 0xa8
 800f046:	f003 0301 	and.w	r3, r3, #1
 800f04a:	2b00      	cmp	r3, #0
 800f04c:	d00b      	beq.n	800f066 <UART_RxISR_16BIT_FIFOEN+0xfe>
        {
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
 800f04e:	687b      	ldr	r3, [r7, #4]
 800f050:	681b      	ldr	r3, [r3, #0]
 800f052:	2202      	movs	r2, #2
 800f054:	621a      	str	r2, [r3, #32]

          huart->ErrorCode |= HAL_UART_ERROR_FE;
 800f056:	687b      	ldr	r3, [r7, #4]
 800f058:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800f05c:	f043 0204 	orr.w	r2, r3, #4
 800f060:	687b      	ldr	r3, [r7, #4]
 800f062:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }

        /* UART noise error interrupt occurred --------------------------------------*/
        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 800f066:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
 800f06a:	f003 0304 	and.w	r3, r3, #4
 800f06e:	2b00      	cmp	r3, #0
 800f070:	d011      	beq.n	800f096 <UART_RxISR_16BIT_FIFOEN+0x12e>
 800f072:	f8d7 30a8 	ldr.w	r3, [r7, #168]	@ 0xa8
 800f076:	f003 0301 	and.w	r3, r3, #1
 800f07a:	2b00      	cmp	r3, #0
 800f07c:	d00b      	beq.n	800f096 <UART_RxISR_16BIT_FIFOEN+0x12e>
        {
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
 800f07e:	687b      	ldr	r3, [r7, #4]
 800f080:	681b      	ldr	r3, [r3, #0]
 800f082:	2204      	movs	r2, #4
 800f084:	621a      	str	r2, [r3, #32]

          huart->ErrorCode |= HAL_UART_ERROR_NE;
 800f086:	687b      	ldr	r3, [r7, #4]
 800f088:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800f08c:	f043 0202 	orr.w	r2, r3, #2
 800f090:	687b      	ldr	r3, [r7, #4]
 800f092:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }

        /* Call UART Error Call back function if need be ----------------------------*/
        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
 800f096:	687b      	ldr	r3, [r7, #4]
 800f098:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800f09c:	2b00      	cmp	r3, #0
 800f09e:	d006      	beq.n	800f0ae <UART_RxISR_16BIT_FIFOEN+0x146>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered error callback*/
          huart->ErrorCallback(huart);
#else
          /*Call legacy weak error callback*/
          HAL_UART_ErrorCallback(huart);
 800f0a0:	6878      	ldr	r0, [r7, #4]
 800f0a2:	f7fe f961 	bl	800d368 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
          huart->ErrorCode = HAL_UART_ERROR_NONE;
 800f0a6:	687b      	ldr	r3, [r7, #4]
 800f0a8:	2200      	movs	r2, #0
 800f0aa:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }
      }

      if (huart->RxXferCount == 0U)
 800f0ae:	687b      	ldr	r3, [r7, #4]
 800f0b0:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800f0b4:	b29b      	uxth	r3, r3
 800f0b6:	2b00      	cmp	r3, #0
 800f0b8:	f040 80a2 	bne.w	800f200 <UART_RxISR_16BIT_FIFOEN+0x298>
      {
        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 800f0bc:	687b      	ldr	r3, [r7, #4]
 800f0be:	681b      	ldr	r3, [r3, #0]
 800f0c0:	677b      	str	r3, [r7, #116]	@ 0x74
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800f0c2:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
 800f0c4:	e853 3f00 	ldrex	r3, [r3]
 800f0c8:	673b      	str	r3, [r7, #112]	@ 0x70
   return(result);
 800f0ca:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
 800f0cc:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 800f0d0:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
 800f0d4:	687b      	ldr	r3, [r7, #4]
 800f0d6:	681b      	ldr	r3, [r3, #0]
 800f0d8:	461a      	mov	r2, r3
 800f0da:	f8d7 309c 	ldr.w	r3, [r7, #156]	@ 0x9c
 800f0de:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
 800f0e2:	67fa      	str	r2, [r7, #124]	@ 0x7c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800f0e4:	6ff9      	ldr	r1, [r7, #124]	@ 0x7c
 800f0e6:	f8d7 2080 	ldr.w	r2, [r7, #128]	@ 0x80
 800f0ea:	e841 2300 	strex	r3, r2, [r1]
 800f0ee:	67bb      	str	r3, [r7, #120]	@ 0x78
   return(result);
 800f0f0:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
 800f0f2:	2b00      	cmp	r3, #0
 800f0f4:	d1e2      	bne.n	800f0bc <UART_RxISR_16BIT_FIFOEN+0x154>

        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
           and RX FIFO Threshold interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 800f0f6:	687b      	ldr	r3, [r7, #4]
 800f0f8:	681b      	ldr	r3, [r3, #0]
 800f0fa:	3308      	adds	r3, #8
 800f0fc:	663b      	str	r3, [r7, #96]	@ 0x60
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800f0fe:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 800f100:	e853 3f00 	ldrex	r3, [r3]
 800f104:	65fb      	str	r3, [r7, #92]	@ 0x5c
   return(result);
 800f106:	6dfa      	ldr	r2, [r7, #92]	@ 0x5c
 800f108:	4b6e      	ldr	r3, [pc, #440]	@ (800f2c4 <UART_RxISR_16BIT_FIFOEN+0x35c>)
 800f10a:	4013      	ands	r3, r2
 800f10c:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
 800f110:	687b      	ldr	r3, [r7, #4]
 800f112:	681b      	ldr	r3, [r3, #0]
 800f114:	3308      	adds	r3, #8
 800f116:	f8d7 2098 	ldr.w	r2, [r7, #152]	@ 0x98
 800f11a:	66fa      	str	r2, [r7, #108]	@ 0x6c
 800f11c:	66bb      	str	r3, [r7, #104]	@ 0x68
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800f11e:	6eb9      	ldr	r1, [r7, #104]	@ 0x68
 800f120:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
 800f122:	e841 2300 	strex	r3, r2, [r1]
 800f126:	667b      	str	r3, [r7, #100]	@ 0x64
   return(result);
 800f128:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 800f12a:	2b00      	cmp	r3, #0
 800f12c:	d1e3      	bne.n	800f0f6 <UART_RxISR_16BIT_FIFOEN+0x18e>

        /* Rx process is completed, restore huart->RxState to Ready */
        huart->RxState = HAL_UART_STATE_READY;
 800f12e:	687b      	ldr	r3, [r7, #4]
 800f130:	2220      	movs	r2, #32
 800f132:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c

        /* Clear RxISR function pointer */
        huart->RxISR = NULL;
 800f136:	687b      	ldr	r3, [r7, #4]
 800f138:	2200      	movs	r2, #0
 800f13a:	675a      	str	r2, [r3, #116]	@ 0x74

        /* Initialize type of RxEvent to Transfer Complete */
        huart->RxEventType = HAL_UART_RXEVENT_TC;
 800f13c:	687b      	ldr	r3, [r7, #4]
 800f13e:	2200      	movs	r2, #0
 800f140:	671a      	str	r2, [r3, #112]	@ 0x70

        if (!(IS_LPUART_INSTANCE(huart->Instance)))
 800f142:	687b      	ldr	r3, [r7, #4]
 800f144:	681b      	ldr	r3, [r3, #0]
 800f146:	4a60      	ldr	r2, [pc, #384]	@ (800f2c8 <UART_RxISR_16BIT_FIFOEN+0x360>)
 800f148:	4293      	cmp	r3, r2
 800f14a:	d021      	beq.n	800f190 <UART_RxISR_16BIT_FIFOEN+0x228>
        {
          /* Check that USART RTOEN bit is set */
          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
 800f14c:	687b      	ldr	r3, [r7, #4]
 800f14e:	681b      	ldr	r3, [r3, #0]
 800f150:	685b      	ldr	r3, [r3, #4]
 800f152:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 800f156:	2b00      	cmp	r3, #0
 800f158:	d01a      	beq.n	800f190 <UART_RxISR_16BIT_FIFOEN+0x228>
          {
            /* Enable the UART Receiver Timeout Interrupt */
            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
 800f15a:	687b      	ldr	r3, [r7, #4]
 800f15c:	681b      	ldr	r3, [r3, #0]
 800f15e:	64fb      	str	r3, [r7, #76]	@ 0x4c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800f160:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 800f162:	e853 3f00 	ldrex	r3, [r3]
 800f166:	64bb      	str	r3, [r7, #72]	@ 0x48
   return(result);
 800f168:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 800f16a:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 800f16e:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
 800f172:	687b      	ldr	r3, [r7, #4]
 800f174:	681b      	ldr	r3, [r3, #0]
 800f176:	461a      	mov	r2, r3
 800f178:	f8d7 3094 	ldr.w	r3, [r7, #148]	@ 0x94
 800f17c:	65bb      	str	r3, [r7, #88]	@ 0x58
 800f17e:	657a      	str	r2, [r7, #84]	@ 0x54
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800f180:	6d79      	ldr	r1, [r7, #84]	@ 0x54
 800f182:	6dba      	ldr	r2, [r7, #88]	@ 0x58
 800f184:	e841 2300 	strex	r3, r2, [r1]
 800f188:	653b      	str	r3, [r7, #80]	@ 0x50
   return(result);
 800f18a:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 800f18c:	2b00      	cmp	r3, #0
 800f18e:	d1e4      	bne.n	800f15a <UART_RxISR_16BIT_FIFOEN+0x1f2>
          }
        }

        /* Check current reception Mode :
           If Reception till IDLE event has been selected : */
        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 800f190:	687b      	ldr	r3, [r7, #4]
 800f192:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800f194:	2b01      	cmp	r3, #1
 800f196:	d130      	bne.n	800f1fa <UART_RxISR_16BIT_FIFOEN+0x292>
        {
          /* Set reception type to Standard */
          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800f198:	687b      	ldr	r3, [r7, #4]
 800f19a:	2200      	movs	r2, #0
 800f19c:	66da      	str	r2, [r3, #108]	@ 0x6c

          /* Disable IDLE interrupt */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 800f19e:	687b      	ldr	r3, [r7, #4]
 800f1a0:	681b      	ldr	r3, [r3, #0]
 800f1a2:	63bb      	str	r3, [r7, #56]	@ 0x38
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800f1a4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800f1a6:	e853 3f00 	ldrex	r3, [r3]
 800f1aa:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 800f1ac:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800f1ae:	f023 0310 	bic.w	r3, r3, #16
 800f1b2:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
 800f1b6:	687b      	ldr	r3, [r7, #4]
 800f1b8:	681b      	ldr	r3, [r3, #0]
 800f1ba:	461a      	mov	r2, r3
 800f1bc:	f8d7 3090 	ldr.w	r3, [r7, #144]	@ 0x90
 800f1c0:	647b      	str	r3, [r7, #68]	@ 0x44
 800f1c2:	643a      	str	r2, [r7, #64]	@ 0x40
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800f1c4:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 800f1c6:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 800f1c8:	e841 2300 	strex	r3, r2, [r1]
 800f1cc:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 800f1ce:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800f1d0:	2b00      	cmp	r3, #0
 800f1d2:	d1e4      	bne.n	800f19e <UART_RxISR_16BIT_FIFOEN+0x236>

          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
 800f1d4:	687b      	ldr	r3, [r7, #4]
 800f1d6:	681b      	ldr	r3, [r3, #0]
 800f1d8:	69db      	ldr	r3, [r3, #28]
 800f1da:	f003 0310 	and.w	r3, r3, #16
 800f1de:	2b10      	cmp	r3, #16
 800f1e0:	d103      	bne.n	800f1ea <UART_RxISR_16BIT_FIFOEN+0x282>
          {
            /* Clear IDLE Flag */
            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 800f1e2:	687b      	ldr	r3, [r7, #4]
 800f1e4:	681b      	ldr	r3, [r3, #0]
 800f1e6:	2210      	movs	r2, #16
 800f1e8:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered Rx Event callback*/
          huart->RxEventCallback(huart, huart->RxXferSize);
#else
          /*Call legacy weak Rx Event callback*/
          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
 800f1ea:	687b      	ldr	r3, [r7, #4]
 800f1ec:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
 800f1f0:	4619      	mov	r1, r3
 800f1f2:	6878      	ldr	r0, [r7, #4]
 800f1f4:	f7f3 fbfe 	bl	80029f4 <HAL_UARTEx_RxEventCallback>
 800f1f8:	e002      	b.n	800f200 <UART_RxISR_16BIT_FIFOEN+0x298>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered Rx complete callback*/
          huart->RxCpltCallback(huart);
#else
          /*Call legacy weak Rx complete callback*/
          HAL_UART_RxCpltCallback(huart);
 800f1fa:	6878      	ldr	r0, [r7, #4]
 800f1fc:	f7f3 fbf0 	bl	80029e0 <HAL_UART_RxCpltCallback>
    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
 800f200:	f8b7 30a6 	ldrh.w	r3, [r7, #166]	@ 0xa6
 800f204:	2b00      	cmp	r3, #0
 800f206:	d006      	beq.n	800f216 <UART_RxISR_16BIT_FIFOEN+0x2ae>
 800f208:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
 800f20c:	f003 0320 	and.w	r3, r3, #32
 800f210:	2b00      	cmp	r3, #0
 800f212:	f47f aecd 	bne.w	800efb0 <UART_RxISR_16BIT_FIFOEN+0x48>

    /* When remaining number of bytes to receive is less than the RX FIFO
    threshold, next incoming frames are processed as if FIFO mode was
    disabled (i.e. one interrupt per received frame).
    */
    rxdatacount = huart->RxXferCount;
 800f216:	687b      	ldr	r3, [r7, #4]
 800f218:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 800f21c:	f8a7 308e 	strh.w	r3, [r7, #142]	@ 0x8e
    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
 800f220:	f8b7 308e 	ldrh.w	r3, [r7, #142]	@ 0x8e
 800f224:	2b00      	cmp	r3, #0
 800f226:	d049      	beq.n	800f2bc <UART_RxISR_16BIT_FIFOEN+0x354>
 800f228:	687b      	ldr	r3, [r7, #4]
 800f22a:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
 800f22e:	f8b7 208e 	ldrh.w	r2, [r7, #142]	@ 0x8e
 800f232:	429a      	cmp	r2, r3
 800f234:	d242      	bcs.n	800f2bc <UART_RxISR_16BIT_FIFOEN+0x354>
    {
      /* Disable the UART RXFT interrupt*/
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
 800f236:	687b      	ldr	r3, [r7, #4]
 800f238:	681b      	ldr	r3, [r3, #0]
 800f23a:	3308      	adds	r3, #8
 800f23c:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800f23e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800f240:	e853 3f00 	ldrex	r3, [r3]
 800f244:	623b      	str	r3, [r7, #32]
   return(result);
 800f246:	6a3b      	ldr	r3, [r7, #32]
 800f248:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 800f24c:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
 800f250:	687b      	ldr	r3, [r7, #4]
 800f252:	681b      	ldr	r3, [r3, #0]
 800f254:	3308      	adds	r3, #8
 800f256:	f8d7 2088 	ldr.w	r2, [r7, #136]	@ 0x88
 800f25a:	633a      	str	r2, [r7, #48]	@ 0x30
 800f25c:	62fb      	str	r3, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800f25e:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 800f260:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 800f262:	e841 2300 	strex	r3, r2, [r1]
 800f266:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 800f268:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800f26a:	2b00      	cmp	r3, #0
 800f26c:	d1e3      	bne.n	800f236 <UART_RxISR_16BIT_FIFOEN+0x2ce>

      /* Update the RxISR function pointer */
      huart->RxISR = UART_RxISR_16BIT;
 800f26e:	687b      	ldr	r3, [r7, #4]
 800f270:	4a16      	ldr	r2, [pc, #88]	@ (800f2cc <UART_RxISR_16BIT_FIFOEN+0x364>)
 800f272:	675a      	str	r2, [r3, #116]	@ 0x74

      /* Enable the UART Data Register Not Empty interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
 800f274:	687b      	ldr	r3, [r7, #4]
 800f276:	681b      	ldr	r3, [r3, #0]
 800f278:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800f27a:	693b      	ldr	r3, [r7, #16]
 800f27c:	e853 3f00 	ldrex	r3, [r3]
 800f280:	60fb      	str	r3, [r7, #12]
   return(result);
 800f282:	68fb      	ldr	r3, [r7, #12]
 800f284:	f043 0320 	orr.w	r3, r3, #32
 800f288:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
 800f28c:	687b      	ldr	r3, [r7, #4]
 800f28e:	681b      	ldr	r3, [r3, #0]
 800f290:	461a      	mov	r2, r3
 800f292:	f8d7 3084 	ldr.w	r3, [r7, #132]	@ 0x84
 800f296:	61fb      	str	r3, [r7, #28]
 800f298:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800f29a:	69b9      	ldr	r1, [r7, #24]
 800f29c:	69fa      	ldr	r2, [r7, #28]
 800f29e:	e841 2300 	strex	r3, r2, [r1]
 800f2a2:	617b      	str	r3, [r7, #20]
   return(result);
 800f2a4:	697b      	ldr	r3, [r7, #20]
 800f2a6:	2b00      	cmp	r3, #0
 800f2a8:	d1e4      	bne.n	800f274 <UART_RxISR_16BIT_FIFOEN+0x30c>
  else
  {
    /* Clear RXNE interrupt flag */
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  }
}
 800f2aa:	e007      	b.n	800f2bc <UART_RxISR_16BIT_FIFOEN+0x354>
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
 800f2ac:	687b      	ldr	r3, [r7, #4]
 800f2ae:	681b      	ldr	r3, [r3, #0]
 800f2b0:	699a      	ldr	r2, [r3, #24]
 800f2b2:	687b      	ldr	r3, [r7, #4]
 800f2b4:	681b      	ldr	r3, [r3, #0]
 800f2b6:	f042 0208 	orr.w	r2, r2, #8
 800f2ba:	619a      	str	r2, [r3, #24]
}
 800f2bc:	bf00      	nop
 800f2be:	37b8      	adds	r7, #184	@ 0xb8
 800f2c0:	46bd      	mov	sp, r7
 800f2c2:	bd80      	pop	{r7, pc}
 800f2c4:	effffffe 	.word	0xeffffffe
 800f2c8:	58000c00 	.word	0x58000c00
 800f2cc:	0800ea51 	.word	0x0800ea51

0800f2d0 <HAL_UARTEx_WakeupCallback>:
  * @brief UART wakeup from Stop mode callback.
  * @param huart UART handle.
  * @retval None
  */
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
 800f2d0:	b480      	push	{r7}
 800f2d2:	b083      	sub	sp, #12
 800f2d4:	af00      	add	r7, sp, #0
 800f2d6:	6078      	str	r0, [r7, #4]
  UNUSED(huart);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
   */
}
 800f2d8:	bf00      	nop
 800f2da:	370c      	adds	r7, #12
 800f2dc:	46bd      	mov	sp, r7
 800f2de:	f85d 7b04 	ldr.w	r7, [sp], #4
 800f2e2:	4770      	bx	lr

0800f2e4 <HAL_UARTEx_RxFifoFullCallback>:
  * @brief  UART RX Fifo full callback.
  * @param  huart UART handle.
  * @retval None
  */
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
{
 800f2e4:	b480      	push	{r7}
 800f2e6:	b083      	sub	sp, #12
 800f2e8:	af00      	add	r7, sp, #0
 800f2ea:	6078      	str	r0, [r7, #4]
  UNUSED(huart);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
   */
}
 800f2ec:	bf00      	nop
 800f2ee:	370c      	adds	r7, #12
 800f2f0:	46bd      	mov	sp, r7
 800f2f2:	f85d 7b04 	ldr.w	r7, [sp], #4
 800f2f6:	4770      	bx	lr

0800f2f8 <HAL_UARTEx_TxFifoEmptyCallback>:
  * @brief  UART TX Fifo empty callback.
  * @param  huart UART handle.
  * @retval None
  */
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
{
 800f2f8:	b480      	push	{r7}
 800f2fa:	b083      	sub	sp, #12
 800f2fc:	af00      	add	r7, sp, #0
 800f2fe:	6078      	str	r0, [r7, #4]
  UNUSED(huart);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
   */
}
 800f300:	bf00      	nop
 800f302:	370c      	adds	r7, #12
 800f304:	46bd      	mov	sp, r7
 800f306:	f85d 7b04 	ldr.w	r7, [sp], #4
 800f30a:	4770      	bx	lr

0800f30c <HAL_UARTEx_DisableFifoMode>:
  * @brief  Disable the FIFO mode.
  * @param huart      UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
{
 800f30c:	b480      	push	{r7}
 800f30e:	b085      	sub	sp, #20
 800f310:	af00      	add	r7, sp, #0
 800f312:	6078      	str	r0, [r7, #4]

  /* Check parameters */
  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));

  /* Process Locked */
  __HAL_LOCK(huart);
 800f314:	687b      	ldr	r3, [r7, #4]
 800f316:	f893 3084 	ldrb.w	r3, [r3, #132]	@ 0x84
 800f31a:	2b01      	cmp	r3, #1
 800f31c:	d101      	bne.n	800f322 <HAL_UARTEx_DisableFifoMode+0x16>
 800f31e:	2302      	movs	r3, #2
 800f320:	e027      	b.n	800f372 <HAL_UARTEx_DisableFifoMode+0x66>
 800f322:	687b      	ldr	r3, [r7, #4]
 800f324:	2201      	movs	r2, #1
 800f326:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  huart->gState = HAL_UART_STATE_BUSY;
 800f32a:	687b      	ldr	r3, [r7, #4]
 800f32c:	2224      	movs	r2, #36	@ 0x24
 800f32e:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Save actual UART configuration */
  tmpcr1 = READ_REG(huart->Instance->CR1);
 800f332:	687b      	ldr	r3, [r7, #4]
 800f334:	681b      	ldr	r3, [r3, #0]
 800f336:	681b      	ldr	r3, [r3, #0]
 800f338:	60fb      	str	r3, [r7, #12]

  /* Disable UART */
  __HAL_UART_DISABLE(huart);
 800f33a:	687b      	ldr	r3, [r7, #4]
 800f33c:	681b      	ldr	r3, [r3, #0]
 800f33e:	681a      	ldr	r2, [r3, #0]
 800f340:	687b      	ldr	r3, [r7, #4]
 800f342:	681b      	ldr	r3, [r3, #0]
 800f344:	f022 0201 	bic.w	r2, r2, #1
 800f348:	601a      	str	r2, [r3, #0]

  /* Enable FIFO mode */
  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
 800f34a:	68fb      	ldr	r3, [r7, #12]
 800f34c:	f023 5300 	bic.w	r3, r3, #536870912	@ 0x20000000
 800f350:	60fb      	str	r3, [r7, #12]
  huart->FifoMode = UART_FIFOMODE_DISABLE;
 800f352:	687b      	ldr	r3, [r7, #4]
 800f354:	2200      	movs	r2, #0
 800f356:	665a      	str	r2, [r3, #100]	@ 0x64

  /* Restore UART configuration */
  WRITE_REG(huart->Instance->CR1, tmpcr1);
 800f358:	687b      	ldr	r3, [r7, #4]
 800f35a:	681b      	ldr	r3, [r3, #0]
 800f35c:	68fa      	ldr	r2, [r7, #12]
 800f35e:	601a      	str	r2, [r3, #0]

  huart->gState = HAL_UART_STATE_READY;
 800f360:	687b      	ldr	r3, [r7, #4]
 800f362:	2220      	movs	r2, #32
 800f364:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Process Unlocked */
  __HAL_UNLOCK(huart);
 800f368:	687b      	ldr	r3, [r7, #4]
 800f36a:	2200      	movs	r2, #0
 800f36c:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  return HAL_OK;
 800f370:	2300      	movs	r3, #0
}
 800f372:	4618      	mov	r0, r3
 800f374:	3714      	adds	r7, #20
 800f376:	46bd      	mov	sp, r7
 800f378:	f85d 7b04 	ldr.w	r7, [sp], #4
 800f37c:	4770      	bx	lr

0800f37e <HAL_UARTEx_SetTxFifoThreshold>:
  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
 800f37e:	b580      	push	{r7, lr}
 800f380:	b084      	sub	sp, #16
 800f382:	af00      	add	r7, sp, #0
 800f384:	6078      	str	r0, [r7, #4]
 800f386:	6039      	str	r1, [r7, #0]
  /* Check parameters */
  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));

  /* Process Locked */
  __HAL_LOCK(huart);
 800f388:	687b      	ldr	r3, [r7, #4]
 800f38a:	f893 3084 	ldrb.w	r3, [r3, #132]	@ 0x84
 800f38e:	2b01      	cmp	r3, #1
 800f390:	d101      	bne.n	800f396 <HAL_UARTEx_SetTxFifoThreshold+0x18>
 800f392:	2302      	movs	r3, #2
 800f394:	e02d      	b.n	800f3f2 <HAL_UARTEx_SetTxFifoThreshold+0x74>
 800f396:	687b      	ldr	r3, [r7, #4]
 800f398:	2201      	movs	r2, #1
 800f39a:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  huart->gState = HAL_UART_STATE_BUSY;
 800f39e:	687b      	ldr	r3, [r7, #4]
 800f3a0:	2224      	movs	r2, #36	@ 0x24
 800f3a2:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Save actual UART configuration */
  tmpcr1 = READ_REG(huart->Instance->CR1);
 800f3a6:	687b      	ldr	r3, [r7, #4]
 800f3a8:	681b      	ldr	r3, [r3, #0]
 800f3aa:	681b      	ldr	r3, [r3, #0]
 800f3ac:	60fb      	str	r3, [r7, #12]

  /* Disable UART */
  __HAL_UART_DISABLE(huart);
 800f3ae:	687b      	ldr	r3, [r7, #4]
 800f3b0:	681b      	ldr	r3, [r3, #0]
 800f3b2:	681a      	ldr	r2, [r3, #0]
 800f3b4:	687b      	ldr	r3, [r7, #4]
 800f3b6:	681b      	ldr	r3, [r3, #0]
 800f3b8:	f022 0201 	bic.w	r2, r2, #1
 800f3bc:	601a      	str	r2, [r3, #0]

  /* Update TX threshold configuration */
  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
 800f3be:	687b      	ldr	r3, [r7, #4]
 800f3c0:	681b      	ldr	r3, [r3, #0]
 800f3c2:	689b      	ldr	r3, [r3, #8]
 800f3c4:	f023 4160 	bic.w	r1, r3, #3758096384	@ 0xe0000000
 800f3c8:	687b      	ldr	r3, [r7, #4]
 800f3ca:	681b      	ldr	r3, [r3, #0]
 800f3cc:	683a      	ldr	r2, [r7, #0]
 800f3ce:	430a      	orrs	r2, r1
 800f3d0:	609a      	str	r2, [r3, #8]

  /* Determine the number of data to process during RX/TX ISR execution */
  UARTEx_SetNbDataToProcess(huart);
 800f3d2:	6878      	ldr	r0, [r7, #4]
 800f3d4:	f000 f8a0 	bl	800f518 <UARTEx_SetNbDataToProcess>

  /* Restore UART configuration */
  WRITE_REG(huart->Instance->CR1, tmpcr1);
 800f3d8:	687b      	ldr	r3, [r7, #4]
 800f3da:	681b      	ldr	r3, [r3, #0]
 800f3dc:	68fa      	ldr	r2, [r7, #12]
 800f3de:	601a      	str	r2, [r3, #0]

  huart->gState = HAL_UART_STATE_READY;
 800f3e0:	687b      	ldr	r3, [r7, #4]
 800f3e2:	2220      	movs	r2, #32
 800f3e4:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Process Unlocked */
  __HAL_UNLOCK(huart);
 800f3e8:	687b      	ldr	r3, [r7, #4]
 800f3ea:	2200      	movs	r2, #0
 800f3ec:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  return HAL_OK;
 800f3f0:	2300      	movs	r3, #0
}
 800f3f2:	4618      	mov	r0, r3
 800f3f4:	3710      	adds	r7, #16
 800f3f6:	46bd      	mov	sp, r7
 800f3f8:	bd80      	pop	{r7, pc}

0800f3fa <HAL_UARTEx_SetRxFifoThreshold>:
  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
 800f3fa:	b580      	push	{r7, lr}
 800f3fc:	b084      	sub	sp, #16
 800f3fe:	af00      	add	r7, sp, #0
 800f400:	6078      	str	r0, [r7, #4]
 800f402:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));

  /* Process Locked */
  __HAL_LOCK(huart);
 800f404:	687b      	ldr	r3, [r7, #4]
 800f406:	f893 3084 	ldrb.w	r3, [r3, #132]	@ 0x84
 800f40a:	2b01      	cmp	r3, #1
 800f40c:	d101      	bne.n	800f412 <HAL_UARTEx_SetRxFifoThreshold+0x18>
 800f40e:	2302      	movs	r3, #2
 800f410:	e02d      	b.n	800f46e <HAL_UARTEx_SetRxFifoThreshold+0x74>
 800f412:	687b      	ldr	r3, [r7, #4]
 800f414:	2201      	movs	r2, #1
 800f416:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  huart->gState = HAL_UART_STATE_BUSY;
 800f41a:	687b      	ldr	r3, [r7, #4]
 800f41c:	2224      	movs	r2, #36	@ 0x24
 800f41e:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Save actual UART configuration */
  tmpcr1 = READ_REG(huart->Instance->CR1);
 800f422:	687b      	ldr	r3, [r7, #4]
 800f424:	681b      	ldr	r3, [r3, #0]
 800f426:	681b      	ldr	r3, [r3, #0]
 800f428:	60fb      	str	r3, [r7, #12]

  /* Disable UART */
  __HAL_UART_DISABLE(huart);
 800f42a:	687b      	ldr	r3, [r7, #4]
 800f42c:	681b      	ldr	r3, [r3, #0]
 800f42e:	681a      	ldr	r2, [r3, #0]
 800f430:	687b      	ldr	r3, [r7, #4]
 800f432:	681b      	ldr	r3, [r3, #0]
 800f434:	f022 0201 	bic.w	r2, r2, #1
 800f438:	601a      	str	r2, [r3, #0]

  /* Update RX threshold configuration */
  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
 800f43a:	687b      	ldr	r3, [r7, #4]
 800f43c:	681b      	ldr	r3, [r3, #0]
 800f43e:	689b      	ldr	r3, [r3, #8]
 800f440:	f023 6160 	bic.w	r1, r3, #234881024	@ 0xe000000
 800f444:	687b      	ldr	r3, [r7, #4]
 800f446:	681b      	ldr	r3, [r3, #0]
 800f448:	683a      	ldr	r2, [r7, #0]
 800f44a:	430a      	orrs	r2, r1
 800f44c:	609a      	str	r2, [r3, #8]

  /* Determine the number of data to process during RX/TX ISR execution */
  UARTEx_SetNbDataToProcess(huart);
 800f44e:	6878      	ldr	r0, [r7, #4]
 800f450:	f000 f862 	bl	800f518 <UARTEx_SetNbDataToProcess>

  /* Restore UART configuration */
  WRITE_REG(huart->Instance->CR1, tmpcr1);
 800f454:	687b      	ldr	r3, [r7, #4]
 800f456:	681b      	ldr	r3, [r3, #0]
 800f458:	68fa      	ldr	r2, [r7, #12]
 800f45a:	601a      	str	r2, [r3, #0]

  huart->gState = HAL_UART_STATE_READY;
 800f45c:	687b      	ldr	r3, [r7, #4]
 800f45e:	2220      	movs	r2, #32
 800f460:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Process Unlocked */
  __HAL_UNLOCK(huart);
 800f464:	687b      	ldr	r3, [r7, #4]
 800f466:	2200      	movs	r2, #0
 800f468:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  return HAL_OK;
 800f46c:	2300      	movs	r3, #0
}
 800f46e:	4618      	mov	r0, r3
 800f470:	3710      	adds	r7, #16
 800f472:	46bd      	mov	sp, r7
 800f474:	bd80      	pop	{r7, pc}

0800f476 <HAL_UARTEx_ReceiveToIdle_IT>:
  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
 800f476:	b580      	push	{r7, lr}
 800f478:	b08c      	sub	sp, #48	@ 0x30
 800f47a:	af00      	add	r7, sp, #0
 800f47c:	60f8      	str	r0, [r7, #12]
 800f47e:	60b9      	str	r1, [r7, #8]
 800f480:	4613      	mov	r3, r2
 800f482:	80fb      	strh	r3, [r7, #6]
  HAL_StatusTypeDef status = HAL_OK;
 800f484:	2300      	movs	r3, #0
 800f486:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f

  /* Check that a Rx process is not already ongoing */
  if (huart->RxState == HAL_UART_STATE_READY)
 800f48a:	68fb      	ldr	r3, [r7, #12]
 800f48c:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 800f490:	2b20      	cmp	r3, #32
 800f492:	d13b      	bne.n	800f50c <HAL_UARTEx_ReceiveToIdle_IT+0x96>
  {
    if ((pData == NULL) || (Size == 0U))
 800f494:	68bb      	ldr	r3, [r7, #8]
 800f496:	2b00      	cmp	r3, #0
 800f498:	d002      	beq.n	800f4a0 <HAL_UARTEx_ReceiveToIdle_IT+0x2a>
 800f49a:	88fb      	ldrh	r3, [r7, #6]
 800f49c:	2b00      	cmp	r3, #0
 800f49e:	d101      	bne.n	800f4a4 <HAL_UARTEx_ReceiveToIdle_IT+0x2e>
    {
      return HAL_ERROR;
 800f4a0:	2301      	movs	r3, #1
 800f4a2:	e034      	b.n	800f50e <HAL_UARTEx_ReceiveToIdle_IT+0x98>
    }

    /* Set Reception type to reception till IDLE Event*/
    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
 800f4a4:	68fb      	ldr	r3, [r7, #12]
 800f4a6:	2201      	movs	r2, #1
 800f4a8:	66da      	str	r2, [r3, #108]	@ 0x6c
    huart->RxEventType = HAL_UART_RXEVENT_TC;
 800f4aa:	68fb      	ldr	r3, [r7, #12]
 800f4ac:	2200      	movs	r2, #0
 800f4ae:	671a      	str	r2, [r3, #112]	@ 0x70

    (void)UART_Start_Receive_IT(huart, pData, Size);
 800f4b0:	88fb      	ldrh	r3, [r7, #6]
 800f4b2:	461a      	mov	r2, r3
 800f4b4:	68b9      	ldr	r1, [r7, #8]
 800f4b6:	68f8      	ldr	r0, [r7, #12]
 800f4b8:	f7fe fe82 	bl	800e1c0 <UART_Start_Receive_IT>

    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 800f4bc:	68fb      	ldr	r3, [r7, #12]
 800f4be:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800f4c0:	2b01      	cmp	r3, #1
 800f4c2:	d11d      	bne.n	800f500 <HAL_UARTEx_ReceiveToIdle_IT+0x8a>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 800f4c4:	68fb      	ldr	r3, [r7, #12]
 800f4c6:	681b      	ldr	r3, [r3, #0]
 800f4c8:	2210      	movs	r2, #16
 800f4ca:	621a      	str	r2, [r3, #32]
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 800f4cc:	68fb      	ldr	r3, [r7, #12]
 800f4ce:	681b      	ldr	r3, [r3, #0]
 800f4d0:	61bb      	str	r3, [r7, #24]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800f4d2:	69bb      	ldr	r3, [r7, #24]
 800f4d4:	e853 3f00 	ldrex	r3, [r3]
 800f4d8:	617b      	str	r3, [r7, #20]
   return(result);
 800f4da:	697b      	ldr	r3, [r7, #20]
 800f4dc:	f043 0310 	orr.w	r3, r3, #16
 800f4e0:	62bb      	str	r3, [r7, #40]	@ 0x28
 800f4e2:	68fb      	ldr	r3, [r7, #12]
 800f4e4:	681b      	ldr	r3, [r3, #0]
 800f4e6:	461a      	mov	r2, r3
 800f4e8:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800f4ea:	627b      	str	r3, [r7, #36]	@ 0x24
 800f4ec:	623a      	str	r2, [r7, #32]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800f4ee:	6a39      	ldr	r1, [r7, #32]
 800f4f0:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 800f4f2:	e841 2300 	strex	r3, r2, [r1]
 800f4f6:	61fb      	str	r3, [r7, #28]
   return(result);
 800f4f8:	69fb      	ldr	r3, [r7, #28]
 800f4fa:	2b00      	cmp	r3, #0
 800f4fc:	d1e6      	bne.n	800f4cc <HAL_UARTEx_ReceiveToIdle_IT+0x56>
 800f4fe:	e002      	b.n	800f506 <HAL_UARTEx_ReceiveToIdle_IT+0x90>
    {
      /* In case of errors already pending when reception is started,
         Interrupts may have already been raised and lead to reception abortion.
         (Overrun error for instance).
         In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
      status = HAL_ERROR;
 800f500:	2301      	movs	r3, #1
 800f502:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
    }

    return status;
 800f506:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
 800f50a:	e000      	b.n	800f50e <HAL_UARTEx_ReceiveToIdle_IT+0x98>
  }
  else
  {
    return HAL_BUSY;
 800f50c:	2302      	movs	r3, #2
  }
}
 800f50e:	4618      	mov	r0, r3
 800f510:	3730      	adds	r7, #48	@ 0x30
 800f512:	46bd      	mov	sp, r7
 800f514:	bd80      	pop	{r7, pc}
	...

0800f518 <UARTEx_SetNbDataToProcess>:
  *       the UART configuration registers.
  * @param huart UART handle.
  * @retval None
  */
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
{
 800f518:	b480      	push	{r7}
 800f51a:	b085      	sub	sp, #20
 800f51c:	af00      	add	r7, sp, #0
 800f51e:	6078      	str	r0, [r7, #4]
  uint8_t rx_fifo_threshold;
  uint8_t tx_fifo_threshold;
  static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};

  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
 800f520:	687b      	ldr	r3, [r7, #4]
 800f522:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 800f524:	2b00      	cmp	r3, #0
 800f526:	d108      	bne.n	800f53a <UARTEx_SetNbDataToProcess+0x22>
  {
    huart->NbTxDataToProcess = 1U;
 800f528:	687b      	ldr	r3, [r7, #4]
 800f52a:	2201      	movs	r2, #1
 800f52c:	f8a3 206a 	strh.w	r2, [r3, #106]	@ 0x6a
    huart->NbRxDataToProcess = 1U;
 800f530:	687b      	ldr	r3, [r7, #4]
 800f532:	2201      	movs	r2, #1
 800f534:	f8a3 2068 	strh.w	r2, [r3, #104]	@ 0x68
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
                               (uint16_t)denominator[tx_fifo_threshold];
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
                               (uint16_t)denominator[rx_fifo_threshold];
  }
}
 800f538:	e031      	b.n	800f59e <UARTEx_SetNbDataToProcess+0x86>
    rx_fifo_depth = RX_FIFO_DEPTH;
 800f53a:	2310      	movs	r3, #16
 800f53c:	73fb      	strb	r3, [r7, #15]
    tx_fifo_depth = TX_FIFO_DEPTH;
 800f53e:	2310      	movs	r3, #16
 800f540:	73bb      	strb	r3, [r7, #14]
    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
 800f542:	687b      	ldr	r3, [r7, #4]
 800f544:	681b      	ldr	r3, [r3, #0]
 800f546:	689b      	ldr	r3, [r3, #8]
 800f548:	0e5b      	lsrs	r3, r3, #25
 800f54a:	b2db      	uxtb	r3, r3
 800f54c:	f003 0307 	and.w	r3, r3, #7
 800f550:	737b      	strb	r3, [r7, #13]
    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
 800f552:	687b      	ldr	r3, [r7, #4]
 800f554:	681b      	ldr	r3, [r3, #0]
 800f556:	689b      	ldr	r3, [r3, #8]
 800f558:	0f5b      	lsrs	r3, r3, #29
 800f55a:	b2db      	uxtb	r3, r3
 800f55c:	f003 0307 	and.w	r3, r3, #7
 800f560:	733b      	strb	r3, [r7, #12]
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
 800f562:	7bbb      	ldrb	r3, [r7, #14]
 800f564:	7b3a      	ldrb	r2, [r7, #12]
 800f566:	4911      	ldr	r1, [pc, #68]	@ (800f5ac <UARTEx_SetNbDataToProcess+0x94>)
 800f568:	5c8a      	ldrb	r2, [r1, r2]
 800f56a:	fb02 f303 	mul.w	r3, r2, r3
                               (uint16_t)denominator[tx_fifo_threshold];
 800f56e:	7b3a      	ldrb	r2, [r7, #12]
 800f570:	490f      	ldr	r1, [pc, #60]	@ (800f5b0 <UARTEx_SetNbDataToProcess+0x98>)
 800f572:	5c8a      	ldrb	r2, [r1, r2]
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
 800f574:	fb93 f3f2 	sdiv	r3, r3, r2
 800f578:	b29a      	uxth	r2, r3
 800f57a:	687b      	ldr	r3, [r7, #4]
 800f57c:	f8a3 206a 	strh.w	r2, [r3, #106]	@ 0x6a
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
 800f580:	7bfb      	ldrb	r3, [r7, #15]
 800f582:	7b7a      	ldrb	r2, [r7, #13]
 800f584:	4909      	ldr	r1, [pc, #36]	@ (800f5ac <UARTEx_SetNbDataToProcess+0x94>)
 800f586:	5c8a      	ldrb	r2, [r1, r2]
 800f588:	fb02 f303 	mul.w	r3, r2, r3
                               (uint16_t)denominator[rx_fifo_threshold];
 800f58c:	7b7a      	ldrb	r2, [r7, #13]
 800f58e:	4908      	ldr	r1, [pc, #32]	@ (800f5b0 <UARTEx_SetNbDataToProcess+0x98>)
 800f590:	5c8a      	ldrb	r2, [r1, r2]
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
 800f592:	fb93 f3f2 	sdiv	r3, r3, r2
 800f596:	b29a      	uxth	r2, r3
 800f598:	687b      	ldr	r3, [r7, #4]
 800f59a:	f8a3 2068 	strh.w	r2, [r3, #104]	@ 0x68
}
 800f59e:	bf00      	nop
 800f5a0:	3714      	adds	r7, #20
 800f5a2:	46bd      	mov	sp, r7
 800f5a4:	f85d 7b04 	ldr.w	r7, [sp], #4
 800f5a8:	4770      	bx	lr
 800f5aa:	bf00      	nop
 800f5ac:	08014614 	.word	0x08014614
 800f5b0:	0801461c 	.word	0x0801461c

0800f5b4 <__NVIC_SetPriority>:
{
 800f5b4:	b480      	push	{r7}
 800f5b6:	b083      	sub	sp, #12
 800f5b8:	af00      	add	r7, sp, #0
 800f5ba:	4603      	mov	r3, r0
 800f5bc:	6039      	str	r1, [r7, #0]
 800f5be:	80fb      	strh	r3, [r7, #6]
  if ((int32_t)(IRQn) >= 0)
 800f5c0:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 800f5c4:	2b00      	cmp	r3, #0
 800f5c6:	db0a      	blt.n	800f5de <__NVIC_SetPriority+0x2a>
    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800f5c8:	683b      	ldr	r3, [r7, #0]
 800f5ca:	b2da      	uxtb	r2, r3
 800f5cc:	490c      	ldr	r1, [pc, #48]	@ (800f600 <__NVIC_SetPriority+0x4c>)
 800f5ce:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 800f5d2:	0112      	lsls	r2, r2, #4
 800f5d4:	b2d2      	uxtb	r2, r2
 800f5d6:	440b      	add	r3, r1
 800f5d8:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
}
 800f5dc:	e00a      	b.n	800f5f4 <__NVIC_SetPriority+0x40>
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800f5de:	683b      	ldr	r3, [r7, #0]
 800f5e0:	b2da      	uxtb	r2, r3
 800f5e2:	4908      	ldr	r1, [pc, #32]	@ (800f604 <__NVIC_SetPriority+0x50>)
 800f5e4:	88fb      	ldrh	r3, [r7, #6]
 800f5e6:	f003 030f 	and.w	r3, r3, #15
 800f5ea:	3b04      	subs	r3, #4
 800f5ec:	0112      	lsls	r2, r2, #4
 800f5ee:	b2d2      	uxtb	r2, r2
 800f5f0:	440b      	add	r3, r1
 800f5f2:	761a      	strb	r2, [r3, #24]
}
 800f5f4:	bf00      	nop
 800f5f6:	370c      	adds	r7, #12
 800f5f8:	46bd      	mov	sp, r7
 800f5fa:	f85d 7b04 	ldr.w	r7, [sp], #4
 800f5fe:	4770      	bx	lr
 800f600:	e000e100 	.word	0xe000e100
 800f604:	e000ed00 	.word	0xe000ed00

0800f608 <SysTick_Handler>:

/*
  SysTick handler implementation that also clears overflow flag.
*/
#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
void SysTick_Handler (void) {
 800f608:	b580      	push	{r7, lr}
 800f60a:	af00      	add	r7, sp, #0
  /* Clear overflow flag */
  SysTick->CTRL;
 800f60c:	4b05      	ldr	r3, [pc, #20]	@ (800f624 <SysTick_Handler+0x1c>)
 800f60e:	681b      	ldr	r3, [r3, #0]

  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
 800f610:	f002 fc28 	bl	8011e64 <xTaskGetSchedulerState>
 800f614:	4603      	mov	r3, r0
 800f616:	2b01      	cmp	r3, #1
 800f618:	d001      	beq.n	800f61e <SysTick_Handler+0x16>
    /* Call tick handler */
    xPortSysTickHandler();
 800f61a:	f003 fd4d 	bl	80130b8 <xPortSysTickHandler>
  }
}
 800f61e:	bf00      	nop
 800f620:	bd80      	pop	{r7, pc}
 800f622:	bf00      	nop
 800f624:	e000e010 	.word	0xe000e010

0800f628 <SVC_Setup>:
#endif /* SysTick */

/*
  Setup SVC to reset value.
*/
__STATIC_INLINE void SVC_Setup (void) {
 800f628:	b580      	push	{r7, lr}
 800f62a:	af00      	add	r7, sp, #0
#if (__ARM_ARCH_7A__ == 0U)
  /* Service Call interrupt might be configured before kernel start     */
  /* and when its priority is lower or equal to BASEPRI, svc intruction */
  /* causes a Hard Fault.                                               */
  NVIC_SetPriority (SVCall_IRQ_NBR, 0U);
 800f62c:	2100      	movs	r1, #0
 800f62e:	f06f 0004 	mvn.w	r0, #4
 800f632:	f7ff ffbf 	bl	800f5b4 <__NVIC_SetPriority>
#endif
}
 800f636:	bf00      	nop
 800f638:	bd80      	pop	{r7, pc}
	...

0800f63c <osKernelInitialize>:
static uint32_t OS_Tick_GetOverflow (void);
/* Get OS Tick interval */
static uint32_t OS_Tick_GetInterval (void);
/*---------------------------------------------------------------------------*/

osStatus_t osKernelInitialize (void) {
 800f63c:	b480      	push	{r7}
 800f63e:	b083      	sub	sp, #12
 800f640:	af00      	add	r7, sp, #0
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800f642:	f3ef 8305 	mrs	r3, IPSR
 800f646:	603b      	str	r3, [r7, #0]
  return(result);
 800f648:	683b      	ldr	r3, [r7, #0]
  osStatus_t stat;

  if (IS_IRQ()) {
 800f64a:	2b00      	cmp	r3, #0
 800f64c:	d003      	beq.n	800f656 <osKernelInitialize+0x1a>
    stat = osErrorISR;
 800f64e:	f06f 0305 	mvn.w	r3, #5
 800f652:	607b      	str	r3, [r7, #4]
 800f654:	e00c      	b.n	800f670 <osKernelInitialize+0x34>
  }
  else {
    if (KernelState == osKernelInactive) {
 800f656:	4b0a      	ldr	r3, [pc, #40]	@ (800f680 <osKernelInitialize+0x44>)
 800f658:	681b      	ldr	r3, [r3, #0]
 800f65a:	2b00      	cmp	r3, #0
 800f65c:	d105      	bne.n	800f66a <osKernelInitialize+0x2e>
        EvrFreeRTOSSetup(0U);
      #endif
      #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
        vPortDefineHeapRegions (configHEAP_5_REGIONS);
      #endif
      KernelState = osKernelReady;
 800f65e:	4b08      	ldr	r3, [pc, #32]	@ (800f680 <osKernelInitialize+0x44>)
 800f660:	2201      	movs	r2, #1
 800f662:	601a      	str	r2, [r3, #0]
      stat = osOK;
 800f664:	2300      	movs	r3, #0
 800f666:	607b      	str	r3, [r7, #4]
 800f668:	e002      	b.n	800f670 <osKernelInitialize+0x34>
    } else {
      stat = osError;
 800f66a:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 800f66e:	607b      	str	r3, [r7, #4]
    }
  }

  return (stat);
 800f670:	687b      	ldr	r3, [r7, #4]
}
 800f672:	4618      	mov	r0, r3
 800f674:	370c      	adds	r7, #12
 800f676:	46bd      	mov	sp, r7
 800f678:	f85d 7b04 	ldr.w	r7, [sp], #4
 800f67c:	4770      	bx	lr
 800f67e:	bf00      	nop
 800f680:	24000a60 	.word	0x24000a60

0800f684 <osKernelStart>:
  }

  return (state);
}

osStatus_t osKernelStart (void) {
 800f684:	b580      	push	{r7, lr}
 800f686:	b082      	sub	sp, #8
 800f688:	af00      	add	r7, sp, #0
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800f68a:	f3ef 8305 	mrs	r3, IPSR
 800f68e:	603b      	str	r3, [r7, #0]
  return(result);
 800f690:	683b      	ldr	r3, [r7, #0]
  osStatus_t stat;

  if (IS_IRQ()) {
 800f692:	2b00      	cmp	r3, #0
 800f694:	d003      	beq.n	800f69e <osKernelStart+0x1a>
    stat = osErrorISR;
 800f696:	f06f 0305 	mvn.w	r3, #5
 800f69a:	607b      	str	r3, [r7, #4]
 800f69c:	e010      	b.n	800f6c0 <osKernelStart+0x3c>
  }
  else {
    if (KernelState == osKernelReady) {
 800f69e:	4b0b      	ldr	r3, [pc, #44]	@ (800f6cc <osKernelStart+0x48>)
 800f6a0:	681b      	ldr	r3, [r3, #0]
 800f6a2:	2b01      	cmp	r3, #1
 800f6a4:	d109      	bne.n	800f6ba <osKernelStart+0x36>
      /* Ensure SVC priority is at the reset value */
      SVC_Setup();
 800f6a6:	f7ff ffbf 	bl	800f628 <SVC_Setup>
      /* Change state to enable IRQ masking check */
      KernelState = osKernelRunning;
 800f6aa:	4b08      	ldr	r3, [pc, #32]	@ (800f6cc <osKernelStart+0x48>)
 800f6ac:	2202      	movs	r2, #2
 800f6ae:	601a      	str	r2, [r3, #0]
      /* Start the kernel scheduler */
      vTaskStartScheduler();
 800f6b0:	f001 ff2e 	bl	8011510 <vTaskStartScheduler>
      stat = osOK;
 800f6b4:	2300      	movs	r3, #0
 800f6b6:	607b      	str	r3, [r7, #4]
 800f6b8:	e002      	b.n	800f6c0 <osKernelStart+0x3c>
    } else {
      stat = osError;
 800f6ba:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 800f6be:	607b      	str	r3, [r7, #4]
    }
  }

  return (stat);
 800f6c0:	687b      	ldr	r3, [r7, #4]
}
 800f6c2:	4618      	mov	r0, r3
 800f6c4:	3708      	adds	r7, #8
 800f6c6:	46bd      	mov	sp, r7
 800f6c8:	bd80      	pop	{r7, pc}
 800f6ca:	bf00      	nop
 800f6cc:	24000a60 	.word	0x24000a60

0800f6d0 <osThreadNew>:
  return (configCPU_CLOCK_HZ);
}

/*---------------------------------------------------------------------------*/

osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
 800f6d0:	b580      	push	{r7, lr}
 800f6d2:	b08e      	sub	sp, #56	@ 0x38
 800f6d4:	af04      	add	r7, sp, #16
 800f6d6:	60f8      	str	r0, [r7, #12]
 800f6d8:	60b9      	str	r1, [r7, #8]
 800f6da:	607a      	str	r2, [r7, #4]
  uint32_t stack;
  TaskHandle_t hTask;
  UBaseType_t prio;
  int32_t mem;

  hTask = NULL;
 800f6dc:	2300      	movs	r3, #0
 800f6de:	613b      	str	r3, [r7, #16]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800f6e0:	f3ef 8305 	mrs	r3, IPSR
 800f6e4:	617b      	str	r3, [r7, #20]
  return(result);
 800f6e6:	697b      	ldr	r3, [r7, #20]

  if (!IS_IRQ() && (func != NULL)) {
 800f6e8:	2b00      	cmp	r3, #0
 800f6ea:	d17f      	bne.n	800f7ec <osThreadNew+0x11c>
 800f6ec:	68fb      	ldr	r3, [r7, #12]
 800f6ee:	2b00      	cmp	r3, #0
 800f6f0:	d07c      	beq.n	800f7ec <osThreadNew+0x11c>
    stack = configMINIMAL_STACK_SIZE;
 800f6f2:	f44f 7300 	mov.w	r3, #512	@ 0x200
 800f6f6:	623b      	str	r3, [r7, #32]
    prio  = (UBaseType_t)osPriorityNormal;
 800f6f8:	2318      	movs	r3, #24
 800f6fa:	61fb      	str	r3, [r7, #28]

    name = NULL;
 800f6fc:	2300      	movs	r3, #0
 800f6fe:	627b      	str	r3, [r7, #36]	@ 0x24
    mem  = -1;
 800f700:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 800f704:	61bb      	str	r3, [r7, #24]

    if (attr != NULL) {
 800f706:	687b      	ldr	r3, [r7, #4]
 800f708:	2b00      	cmp	r3, #0
 800f70a:	d045      	beq.n	800f798 <osThreadNew+0xc8>
      if (attr->name != NULL) {
 800f70c:	687b      	ldr	r3, [r7, #4]
 800f70e:	681b      	ldr	r3, [r3, #0]
 800f710:	2b00      	cmp	r3, #0
 800f712:	d002      	beq.n	800f71a <osThreadNew+0x4a>
        name = attr->name;
 800f714:	687b      	ldr	r3, [r7, #4]
 800f716:	681b      	ldr	r3, [r3, #0]
 800f718:	627b      	str	r3, [r7, #36]	@ 0x24
      }
      if (attr->priority != osPriorityNone) {
 800f71a:	687b      	ldr	r3, [r7, #4]
 800f71c:	699b      	ldr	r3, [r3, #24]
 800f71e:	2b00      	cmp	r3, #0
 800f720:	d002      	beq.n	800f728 <osThreadNew+0x58>
        prio = (UBaseType_t)attr->priority;
 800f722:	687b      	ldr	r3, [r7, #4]
 800f724:	699b      	ldr	r3, [r3, #24]
 800f726:	61fb      	str	r3, [r7, #28]
      }

      if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
 800f728:	69fb      	ldr	r3, [r7, #28]
 800f72a:	2b00      	cmp	r3, #0
 800f72c:	d008      	beq.n	800f740 <osThreadNew+0x70>
 800f72e:	69fb      	ldr	r3, [r7, #28]
 800f730:	2b38      	cmp	r3, #56	@ 0x38
 800f732:	d805      	bhi.n	800f740 <osThreadNew+0x70>
 800f734:	687b      	ldr	r3, [r7, #4]
 800f736:	685b      	ldr	r3, [r3, #4]
 800f738:	f003 0301 	and.w	r3, r3, #1
 800f73c:	2b00      	cmp	r3, #0
 800f73e:	d001      	beq.n	800f744 <osThreadNew+0x74>
        return (NULL);
 800f740:	2300      	movs	r3, #0
 800f742:	e054      	b.n	800f7ee <osThreadNew+0x11e>
      }

      if (attr->stack_size > 0U) {
 800f744:	687b      	ldr	r3, [r7, #4]
 800f746:	695b      	ldr	r3, [r3, #20]
 800f748:	2b00      	cmp	r3, #0
 800f74a:	d003      	beq.n	800f754 <osThreadNew+0x84>
        /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports.       */
        /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
        stack = attr->stack_size / sizeof(StackType_t);
 800f74c:	687b      	ldr	r3, [r7, #4]
 800f74e:	695b      	ldr	r3, [r3, #20]
 800f750:	089b      	lsrs	r3, r3, #2
 800f752:	623b      	str	r3, [r7, #32]
      }

      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
 800f754:	687b      	ldr	r3, [r7, #4]
 800f756:	689b      	ldr	r3, [r3, #8]
 800f758:	2b00      	cmp	r3, #0
 800f75a:	d00e      	beq.n	800f77a <osThreadNew+0xaa>
 800f75c:	687b      	ldr	r3, [r7, #4]
 800f75e:	68db      	ldr	r3, [r3, #12]
 800f760:	2ba7      	cmp	r3, #167	@ 0xa7
 800f762:	d90a      	bls.n	800f77a <osThreadNew+0xaa>
          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
 800f764:	687b      	ldr	r3, [r7, #4]
 800f766:	691b      	ldr	r3, [r3, #16]
      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
 800f768:	2b00      	cmp	r3, #0
 800f76a:	d006      	beq.n	800f77a <osThreadNew+0xaa>
          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
 800f76c:	687b      	ldr	r3, [r7, #4]
 800f76e:	695b      	ldr	r3, [r3, #20]
 800f770:	2b00      	cmp	r3, #0
 800f772:	d002      	beq.n	800f77a <osThreadNew+0xaa>
        mem = 1;
 800f774:	2301      	movs	r3, #1
 800f776:	61bb      	str	r3, [r7, #24]
 800f778:	e010      	b.n	800f79c <osThreadNew+0xcc>
      }
      else {
        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
 800f77a:	687b      	ldr	r3, [r7, #4]
 800f77c:	689b      	ldr	r3, [r3, #8]
 800f77e:	2b00      	cmp	r3, #0
 800f780:	d10c      	bne.n	800f79c <osThreadNew+0xcc>
 800f782:	687b      	ldr	r3, [r7, #4]
 800f784:	68db      	ldr	r3, [r3, #12]
 800f786:	2b00      	cmp	r3, #0
 800f788:	d108      	bne.n	800f79c <osThreadNew+0xcc>
 800f78a:	687b      	ldr	r3, [r7, #4]
 800f78c:	691b      	ldr	r3, [r3, #16]
 800f78e:	2b00      	cmp	r3, #0
 800f790:	d104      	bne.n	800f79c <osThreadNew+0xcc>
          mem = 0;
 800f792:	2300      	movs	r3, #0
 800f794:	61bb      	str	r3, [r7, #24]
 800f796:	e001      	b.n	800f79c <osThreadNew+0xcc>
        }
      }
    }
    else {
      mem = 0;
 800f798:	2300      	movs	r3, #0
 800f79a:	61bb      	str	r3, [r7, #24]
    }

    if (mem == 1) {
 800f79c:	69bb      	ldr	r3, [r7, #24]
 800f79e:	2b01      	cmp	r3, #1
 800f7a0:	d110      	bne.n	800f7c4 <osThreadNew+0xf4>
      #if (configSUPPORT_STATIC_ALLOCATION == 1)
        hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
 800f7a2:	687b      	ldr	r3, [r7, #4]
 800f7a4:	691b      	ldr	r3, [r3, #16]
                                                                                      (StaticTask_t *)attr->cb_mem);
 800f7a6:	687a      	ldr	r2, [r7, #4]
 800f7a8:	6892      	ldr	r2, [r2, #8]
        hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
 800f7aa:	9202      	str	r2, [sp, #8]
 800f7ac:	9301      	str	r3, [sp, #4]
 800f7ae:	69fb      	ldr	r3, [r7, #28]
 800f7b0:	9300      	str	r3, [sp, #0]
 800f7b2:	68bb      	ldr	r3, [r7, #8]
 800f7b4:	6a3a      	ldr	r2, [r7, #32]
 800f7b6:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 800f7b8:	68f8      	ldr	r0, [r7, #12]
 800f7ba:	f001 fcb6 	bl	801112a <xTaskCreateStatic>
 800f7be:	4603      	mov	r3, r0
 800f7c0:	613b      	str	r3, [r7, #16]
 800f7c2:	e013      	b.n	800f7ec <osThreadNew+0x11c>
      #endif
    }
    else {
      if (mem == 0) {
 800f7c4:	69bb      	ldr	r3, [r7, #24]
 800f7c6:	2b00      	cmp	r3, #0
 800f7c8:	d110      	bne.n	800f7ec <osThreadNew+0x11c>
        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
          if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
 800f7ca:	6a3b      	ldr	r3, [r7, #32]
 800f7cc:	b29a      	uxth	r2, r3
 800f7ce:	f107 0310 	add.w	r3, r7, #16
 800f7d2:	9301      	str	r3, [sp, #4]
 800f7d4:	69fb      	ldr	r3, [r7, #28]
 800f7d6:	9300      	str	r3, [sp, #0]
 800f7d8:	68bb      	ldr	r3, [r7, #8]
 800f7da:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 800f7dc:	68f8      	ldr	r0, [r7, #12]
 800f7de:	f001 fd04 	bl	80111ea <xTaskCreate>
 800f7e2:	4603      	mov	r3, r0
 800f7e4:	2b01      	cmp	r3, #1
 800f7e6:	d001      	beq.n	800f7ec <osThreadNew+0x11c>
            hTask = NULL;
 800f7e8:	2300      	movs	r3, #0
 800f7ea:	613b      	str	r3, [r7, #16]
        #endif
      }
    }
  }

  return ((osThreadId_t)hTask);
 800f7ec:	693b      	ldr	r3, [r7, #16]
}
 800f7ee:	4618      	mov	r0, r3
 800f7f0:	3728      	adds	r7, #40	@ 0x28
 800f7f2:	46bd      	mov	sp, r7
 800f7f4:	bd80      	pop	{r7, pc}

0800f7f6 <osDelay>:
  /* Return flags before clearing */
  return (rflags);
}
#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */

osStatus_t osDelay (uint32_t ticks) {
 800f7f6:	b580      	push	{r7, lr}
 800f7f8:	b084      	sub	sp, #16
 800f7fa:	af00      	add	r7, sp, #0
 800f7fc:	6078      	str	r0, [r7, #4]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800f7fe:	f3ef 8305 	mrs	r3, IPSR
 800f802:	60bb      	str	r3, [r7, #8]
  return(result);
 800f804:	68bb      	ldr	r3, [r7, #8]
  osStatus_t stat;

  if (IS_IRQ()) {
 800f806:	2b00      	cmp	r3, #0
 800f808:	d003      	beq.n	800f812 <osDelay+0x1c>
    stat = osErrorISR;
 800f80a:	f06f 0305 	mvn.w	r3, #5
 800f80e:	60fb      	str	r3, [r7, #12]
 800f810:	e007      	b.n	800f822 <osDelay+0x2c>
  }
  else {
    stat = osOK;
 800f812:	2300      	movs	r3, #0
 800f814:	60fb      	str	r3, [r7, #12]

    if (ticks != 0U) {
 800f816:	687b      	ldr	r3, [r7, #4]
 800f818:	2b00      	cmp	r3, #0
 800f81a:	d002      	beq.n	800f822 <osDelay+0x2c>
      vTaskDelay(ticks);
 800f81c:	6878      	ldr	r0, [r7, #4]
 800f81e:	f001 fe41 	bl	80114a4 <vTaskDelay>
    }
  }

  return (stat);
 800f822:	68fb      	ldr	r3, [r7, #12]
}
 800f824:	4618      	mov	r0, r3
 800f826:	3710      	adds	r7, #16
 800f828:	46bd      	mov	sp, r7
 800f82a:	bd80      	pop	{r7, pc}

0800f82c <osMutexNew>:
}

/*---------------------------------------------------------------------------*/
#if (configUSE_OS2_MUTEX == 1)

osMutexId_t osMutexNew (const osMutexAttr_t *attr) {
 800f82c:	b580      	push	{r7, lr}
 800f82e:	b088      	sub	sp, #32
 800f830:	af00      	add	r7, sp, #0
 800f832:	6078      	str	r0, [r7, #4]
  int32_t  mem;
  #if (configQUEUE_REGISTRY_SIZE > 0)
  const char *name;
  #endif

  hMutex = NULL;
 800f834:	2300      	movs	r3, #0
 800f836:	61fb      	str	r3, [r7, #28]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800f838:	f3ef 8305 	mrs	r3, IPSR
 800f83c:	60bb      	str	r3, [r7, #8]
  return(result);
 800f83e:	68bb      	ldr	r3, [r7, #8]

  if (!IS_IRQ()) {
 800f840:	2b00      	cmp	r3, #0
 800f842:	d174      	bne.n	800f92e <osMutexNew+0x102>
    if (attr != NULL) {
 800f844:	687b      	ldr	r3, [r7, #4]
 800f846:	2b00      	cmp	r3, #0
 800f848:	d003      	beq.n	800f852 <osMutexNew+0x26>
      type = attr->attr_bits;
 800f84a:	687b      	ldr	r3, [r7, #4]
 800f84c:	685b      	ldr	r3, [r3, #4]
 800f84e:	61bb      	str	r3, [r7, #24]
 800f850:	e001      	b.n	800f856 <osMutexNew+0x2a>
    } else {
      type = 0U;
 800f852:	2300      	movs	r3, #0
 800f854:	61bb      	str	r3, [r7, #24]
    }

    if ((type & osMutexRecursive) == osMutexRecursive) {
 800f856:	69bb      	ldr	r3, [r7, #24]
 800f858:	f003 0301 	and.w	r3, r3, #1
 800f85c:	2b00      	cmp	r3, #0
 800f85e:	d002      	beq.n	800f866 <osMutexNew+0x3a>
      rmtx = 1U;
 800f860:	2301      	movs	r3, #1
 800f862:	617b      	str	r3, [r7, #20]
 800f864:	e001      	b.n	800f86a <osMutexNew+0x3e>
    } else {
      rmtx = 0U;
 800f866:	2300      	movs	r3, #0
 800f868:	617b      	str	r3, [r7, #20]
    }

    if ((type & osMutexRobust) != osMutexRobust) {
 800f86a:	69bb      	ldr	r3, [r7, #24]
 800f86c:	f003 0308 	and.w	r3, r3, #8
 800f870:	2b00      	cmp	r3, #0
 800f872:	d15c      	bne.n	800f92e <osMutexNew+0x102>
      mem = -1;
 800f874:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 800f878:	613b      	str	r3, [r7, #16]

      if (attr != NULL) {
 800f87a:	687b      	ldr	r3, [r7, #4]
 800f87c:	2b00      	cmp	r3, #0
 800f87e:	d015      	beq.n	800f8ac <osMutexNew+0x80>
        if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {
 800f880:	687b      	ldr	r3, [r7, #4]
 800f882:	689b      	ldr	r3, [r3, #8]
 800f884:	2b00      	cmp	r3, #0
 800f886:	d006      	beq.n	800f896 <osMutexNew+0x6a>
 800f888:	687b      	ldr	r3, [r7, #4]
 800f88a:	68db      	ldr	r3, [r3, #12]
 800f88c:	2b4f      	cmp	r3, #79	@ 0x4f
 800f88e:	d902      	bls.n	800f896 <osMutexNew+0x6a>
          mem = 1;
 800f890:	2301      	movs	r3, #1
 800f892:	613b      	str	r3, [r7, #16]
 800f894:	e00c      	b.n	800f8b0 <osMutexNew+0x84>
        }
        else {
          if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
 800f896:	687b      	ldr	r3, [r7, #4]
 800f898:	689b      	ldr	r3, [r3, #8]
 800f89a:	2b00      	cmp	r3, #0
 800f89c:	d108      	bne.n	800f8b0 <osMutexNew+0x84>
 800f89e:	687b      	ldr	r3, [r7, #4]
 800f8a0:	68db      	ldr	r3, [r3, #12]
 800f8a2:	2b00      	cmp	r3, #0
 800f8a4:	d104      	bne.n	800f8b0 <osMutexNew+0x84>
            mem = 0;
 800f8a6:	2300      	movs	r3, #0
 800f8a8:	613b      	str	r3, [r7, #16]
 800f8aa:	e001      	b.n	800f8b0 <osMutexNew+0x84>
          }
        }
      }
      else {
        mem = 0;
 800f8ac:	2300      	movs	r3, #0
 800f8ae:	613b      	str	r3, [r7, #16]
      }

      if (mem == 1) {
 800f8b0:	693b      	ldr	r3, [r7, #16]
 800f8b2:	2b01      	cmp	r3, #1
 800f8b4:	d112      	bne.n	800f8dc <osMutexNew+0xb0>
        #if (configSUPPORT_STATIC_ALLOCATION == 1)
          if (rmtx != 0U) {
 800f8b6:	697b      	ldr	r3, [r7, #20]
 800f8b8:	2b00      	cmp	r3, #0
 800f8ba:	d007      	beq.n	800f8cc <osMutexNew+0xa0>
            #if (configUSE_RECURSIVE_MUTEXES == 1)
            hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem);
 800f8bc:	687b      	ldr	r3, [r7, #4]
 800f8be:	689b      	ldr	r3, [r3, #8]
 800f8c0:	4619      	mov	r1, r3
 800f8c2:	2004      	movs	r0, #4
 800f8c4:	f000 fc51 	bl	801016a <xQueueCreateMutexStatic>
 800f8c8:	61f8      	str	r0, [r7, #28]
 800f8ca:	e016      	b.n	800f8fa <osMutexNew+0xce>
            #endif
          }
          else {
            hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem);
 800f8cc:	687b      	ldr	r3, [r7, #4]
 800f8ce:	689b      	ldr	r3, [r3, #8]
 800f8d0:	4619      	mov	r1, r3
 800f8d2:	2001      	movs	r0, #1
 800f8d4:	f000 fc49 	bl	801016a <xQueueCreateMutexStatic>
 800f8d8:	61f8      	str	r0, [r7, #28]
 800f8da:	e00e      	b.n	800f8fa <osMutexNew+0xce>
          }
        #endif
      }
      else {
        if (mem == 0) {
 800f8dc:	693b      	ldr	r3, [r7, #16]
 800f8de:	2b00      	cmp	r3, #0
 800f8e0:	d10b      	bne.n	800f8fa <osMutexNew+0xce>
          #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
            if (rmtx != 0U) {
 800f8e2:	697b      	ldr	r3, [r7, #20]
 800f8e4:	2b00      	cmp	r3, #0
 800f8e6:	d004      	beq.n	800f8f2 <osMutexNew+0xc6>
              #if (configUSE_RECURSIVE_MUTEXES == 1)
              hMutex = xSemaphoreCreateRecursiveMutex ();
 800f8e8:	2004      	movs	r0, #4
 800f8ea:	f000 fc26 	bl	801013a <xQueueCreateMutex>
 800f8ee:	61f8      	str	r0, [r7, #28]
 800f8f0:	e003      	b.n	800f8fa <osMutexNew+0xce>
              #endif
            } else {
              hMutex = xSemaphoreCreateMutex ();
 800f8f2:	2001      	movs	r0, #1
 800f8f4:	f000 fc21 	bl	801013a <xQueueCreateMutex>
 800f8f8:	61f8      	str	r0, [r7, #28]
          #endif
        }
      }

      #if (configQUEUE_REGISTRY_SIZE > 0)
      if (hMutex != NULL) {
 800f8fa:	69fb      	ldr	r3, [r7, #28]
 800f8fc:	2b00      	cmp	r3, #0
 800f8fe:	d00c      	beq.n	800f91a <osMutexNew+0xee>
        if (attr != NULL) {
 800f900:	687b      	ldr	r3, [r7, #4]
 800f902:	2b00      	cmp	r3, #0
 800f904:	d003      	beq.n	800f90e <osMutexNew+0xe2>
          name = attr->name;
 800f906:	687b      	ldr	r3, [r7, #4]
 800f908:	681b      	ldr	r3, [r3, #0]
 800f90a:	60fb      	str	r3, [r7, #12]
 800f90c:	e001      	b.n	800f912 <osMutexNew+0xe6>
        } else {
          name = NULL;
 800f90e:	2300      	movs	r3, #0
 800f910:	60fb      	str	r3, [r7, #12]
        }
        vQueueAddToRegistry (hMutex, name);
 800f912:	68f9      	ldr	r1, [r7, #12]
 800f914:	69f8      	ldr	r0, [r7, #28]
 800f916:	f001 f9eb 	bl	8010cf0 <vQueueAddToRegistry>
      }
      #endif

      if ((hMutex != NULL) && (rmtx != 0U)) {
 800f91a:	69fb      	ldr	r3, [r7, #28]
 800f91c:	2b00      	cmp	r3, #0
 800f91e:	d006      	beq.n	800f92e <osMutexNew+0x102>
 800f920:	697b      	ldr	r3, [r7, #20]
 800f922:	2b00      	cmp	r3, #0
 800f924:	d003      	beq.n	800f92e <osMutexNew+0x102>
        hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U);
 800f926:	69fb      	ldr	r3, [r7, #28]
 800f928:	f043 0301 	orr.w	r3, r3, #1
 800f92c:	61fb      	str	r3, [r7, #28]
      }
    }
  }

  return ((osMutexId_t)hMutex);
 800f92e:	69fb      	ldr	r3, [r7, #28]
}
 800f930:	4618      	mov	r0, r3
 800f932:	3720      	adds	r7, #32
 800f934:	46bd      	mov	sp, r7
 800f936:	bd80      	pop	{r7, pc}

0800f938 <osMutexAcquire>:

osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
 800f938:	b580      	push	{r7, lr}
 800f93a:	b086      	sub	sp, #24
 800f93c:	af00      	add	r7, sp, #0
 800f93e:	6078      	str	r0, [r7, #4]
 800f940:	6039      	str	r1, [r7, #0]
  SemaphoreHandle_t hMutex;
  osStatus_t stat;
  uint32_t rmtx;

  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
 800f942:	687b      	ldr	r3, [r7, #4]
 800f944:	f023 0301 	bic.w	r3, r3, #1
 800f948:	613b      	str	r3, [r7, #16]

  rmtx = (uint32_t)mutex_id & 1U;
 800f94a:	687b      	ldr	r3, [r7, #4]
 800f94c:	f003 0301 	and.w	r3, r3, #1
 800f950:	60fb      	str	r3, [r7, #12]

  stat = osOK;
 800f952:	2300      	movs	r3, #0
 800f954:	617b      	str	r3, [r7, #20]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800f956:	f3ef 8305 	mrs	r3, IPSR
 800f95a:	60bb      	str	r3, [r7, #8]
  return(result);
 800f95c:	68bb      	ldr	r3, [r7, #8]

  if (IS_IRQ()) {
 800f95e:	2b00      	cmp	r3, #0
 800f960:	d003      	beq.n	800f96a <osMutexAcquire+0x32>
    stat = osErrorISR;
 800f962:	f06f 0305 	mvn.w	r3, #5
 800f966:	617b      	str	r3, [r7, #20]
 800f968:	e02c      	b.n	800f9c4 <osMutexAcquire+0x8c>
  }
  else if (hMutex == NULL) {
 800f96a:	693b      	ldr	r3, [r7, #16]
 800f96c:	2b00      	cmp	r3, #0
 800f96e:	d103      	bne.n	800f978 <osMutexAcquire+0x40>
    stat = osErrorParameter;
 800f970:	f06f 0303 	mvn.w	r3, #3
 800f974:	617b      	str	r3, [r7, #20]
 800f976:	e025      	b.n	800f9c4 <osMutexAcquire+0x8c>
  }
  else {
    if (rmtx != 0U) {
 800f978:	68fb      	ldr	r3, [r7, #12]
 800f97a:	2b00      	cmp	r3, #0
 800f97c:	d011      	beq.n	800f9a2 <osMutexAcquire+0x6a>
      #if (configUSE_RECURSIVE_MUTEXES == 1)
      if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) {
 800f97e:	6839      	ldr	r1, [r7, #0]
 800f980:	6938      	ldr	r0, [r7, #16]
 800f982:	f000 fc42 	bl	801020a <xQueueTakeMutexRecursive>
 800f986:	4603      	mov	r3, r0
 800f988:	2b01      	cmp	r3, #1
 800f98a:	d01b      	beq.n	800f9c4 <osMutexAcquire+0x8c>
        if (timeout != 0U) {
 800f98c:	683b      	ldr	r3, [r7, #0]
 800f98e:	2b00      	cmp	r3, #0
 800f990:	d003      	beq.n	800f99a <osMutexAcquire+0x62>
          stat = osErrorTimeout;
 800f992:	f06f 0301 	mvn.w	r3, #1
 800f996:	617b      	str	r3, [r7, #20]
 800f998:	e014      	b.n	800f9c4 <osMutexAcquire+0x8c>
        } else {
          stat = osErrorResource;
 800f99a:	f06f 0302 	mvn.w	r3, #2
 800f99e:	617b      	str	r3, [r7, #20]
 800f9a0:	e010      	b.n	800f9c4 <osMutexAcquire+0x8c>
        }
      }
      #endif
    }
    else {
      if (xSemaphoreTake (hMutex, timeout) != pdPASS) {
 800f9a2:	6839      	ldr	r1, [r7, #0]
 800f9a4:	6938      	ldr	r0, [r7, #16]
 800f9a6:	f000 fee9 	bl	801077c <xQueueSemaphoreTake>
 800f9aa:	4603      	mov	r3, r0
 800f9ac:	2b01      	cmp	r3, #1
 800f9ae:	d009      	beq.n	800f9c4 <osMutexAcquire+0x8c>
        if (timeout != 0U) {
 800f9b0:	683b      	ldr	r3, [r7, #0]
 800f9b2:	2b00      	cmp	r3, #0
 800f9b4:	d003      	beq.n	800f9be <osMutexAcquire+0x86>
          stat = osErrorTimeout;
 800f9b6:	f06f 0301 	mvn.w	r3, #1
 800f9ba:	617b      	str	r3, [r7, #20]
 800f9bc:	e002      	b.n	800f9c4 <osMutexAcquire+0x8c>
        } else {
          stat = osErrorResource;
 800f9be:	f06f 0302 	mvn.w	r3, #2
 800f9c2:	617b      	str	r3, [r7, #20]
        }
      }
    }
  }

  return (stat);
 800f9c4:	697b      	ldr	r3, [r7, #20]
}
 800f9c6:	4618      	mov	r0, r3
 800f9c8:	3718      	adds	r7, #24
 800f9ca:	46bd      	mov	sp, r7
 800f9cc:	bd80      	pop	{r7, pc}

0800f9ce <osMutexRelease>:

osStatus_t osMutexRelease (osMutexId_t mutex_id) {
 800f9ce:	b580      	push	{r7, lr}
 800f9d0:	b086      	sub	sp, #24
 800f9d2:	af00      	add	r7, sp, #0
 800f9d4:	6078      	str	r0, [r7, #4]
  SemaphoreHandle_t hMutex;
  osStatus_t stat;
  uint32_t rmtx;

  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
 800f9d6:	687b      	ldr	r3, [r7, #4]
 800f9d8:	f023 0301 	bic.w	r3, r3, #1
 800f9dc:	613b      	str	r3, [r7, #16]

  rmtx = (uint32_t)mutex_id & 1U;
 800f9de:	687b      	ldr	r3, [r7, #4]
 800f9e0:	f003 0301 	and.w	r3, r3, #1
 800f9e4:	60fb      	str	r3, [r7, #12]

  stat = osOK;
 800f9e6:	2300      	movs	r3, #0
 800f9e8:	617b      	str	r3, [r7, #20]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800f9ea:	f3ef 8305 	mrs	r3, IPSR
 800f9ee:	60bb      	str	r3, [r7, #8]
  return(result);
 800f9f0:	68bb      	ldr	r3, [r7, #8]

  if (IS_IRQ()) {
 800f9f2:	2b00      	cmp	r3, #0
 800f9f4:	d003      	beq.n	800f9fe <osMutexRelease+0x30>
    stat = osErrorISR;
 800f9f6:	f06f 0305 	mvn.w	r3, #5
 800f9fa:	617b      	str	r3, [r7, #20]
 800f9fc:	e01f      	b.n	800fa3e <osMutexRelease+0x70>
  }
  else if (hMutex == NULL) {
 800f9fe:	693b      	ldr	r3, [r7, #16]
 800fa00:	2b00      	cmp	r3, #0
 800fa02:	d103      	bne.n	800fa0c <osMutexRelease+0x3e>
    stat = osErrorParameter;
 800fa04:	f06f 0303 	mvn.w	r3, #3
 800fa08:	617b      	str	r3, [r7, #20]
 800fa0a:	e018      	b.n	800fa3e <osMutexRelease+0x70>
  }
  else {
    if (rmtx != 0U) {
 800fa0c:	68fb      	ldr	r3, [r7, #12]
 800fa0e:	2b00      	cmp	r3, #0
 800fa10:	d009      	beq.n	800fa26 <osMutexRelease+0x58>
      #if (configUSE_RECURSIVE_MUTEXES == 1)
      if (xSemaphoreGiveRecursive (hMutex) != pdPASS) {
 800fa12:	6938      	ldr	r0, [r7, #16]
 800fa14:	f000 fbc4 	bl	80101a0 <xQueueGiveMutexRecursive>
 800fa18:	4603      	mov	r3, r0
 800fa1a:	2b01      	cmp	r3, #1
 800fa1c:	d00f      	beq.n	800fa3e <osMutexRelease+0x70>
        stat = osErrorResource;
 800fa1e:	f06f 0302 	mvn.w	r3, #2
 800fa22:	617b      	str	r3, [r7, #20]
 800fa24:	e00b      	b.n	800fa3e <osMutexRelease+0x70>
      }
      #endif
    }
    else {
      if (xSemaphoreGive (hMutex) != pdPASS) {
 800fa26:	2300      	movs	r3, #0
 800fa28:	2200      	movs	r2, #0
 800fa2a:	2100      	movs	r1, #0
 800fa2c:	6938      	ldr	r0, [r7, #16]
 800fa2e:	f000 fc23 	bl	8010278 <xQueueGenericSend>
 800fa32:	4603      	mov	r3, r0
 800fa34:	2b01      	cmp	r3, #1
 800fa36:	d002      	beq.n	800fa3e <osMutexRelease+0x70>
        stat = osErrorResource;
 800fa38:	f06f 0302 	mvn.w	r3, #2
 800fa3c:	617b      	str	r3, [r7, #20]
      }
    }
  }

  return (stat);
 800fa3e:	697b      	ldr	r3, [r7, #20]
}
 800fa40:	4618      	mov	r0, r3
 800fa42:	3718      	adds	r7, #24
 800fa44:	46bd      	mov	sp, r7
 800fa46:	bd80      	pop	{r7, pc}

0800fa48 <osMessageQueueNew>:
  return (stat);
}

/*---------------------------------------------------------------------------*/

osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
 800fa48:	b580      	push	{r7, lr}
 800fa4a:	b08a      	sub	sp, #40	@ 0x28
 800fa4c:	af02      	add	r7, sp, #8
 800fa4e:	60f8      	str	r0, [r7, #12]
 800fa50:	60b9      	str	r1, [r7, #8]
 800fa52:	607a      	str	r2, [r7, #4]
  int32_t mem;
  #if (configQUEUE_REGISTRY_SIZE > 0)
  const char *name;
  #endif

  hQueue = NULL;
 800fa54:	2300      	movs	r3, #0
 800fa56:	61fb      	str	r3, [r7, #28]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800fa58:	f3ef 8305 	mrs	r3, IPSR
 800fa5c:	613b      	str	r3, [r7, #16]
  return(result);
 800fa5e:	693b      	ldr	r3, [r7, #16]

  if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) {
 800fa60:	2b00      	cmp	r3, #0
 800fa62:	d15f      	bne.n	800fb24 <osMessageQueueNew+0xdc>
 800fa64:	68fb      	ldr	r3, [r7, #12]
 800fa66:	2b00      	cmp	r3, #0
 800fa68:	d05c      	beq.n	800fb24 <osMessageQueueNew+0xdc>
 800fa6a:	68bb      	ldr	r3, [r7, #8]
 800fa6c:	2b00      	cmp	r3, #0
 800fa6e:	d059      	beq.n	800fb24 <osMessageQueueNew+0xdc>
    mem = -1;
 800fa70:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 800fa74:	61bb      	str	r3, [r7, #24]

    if (attr != NULL) {
 800fa76:	687b      	ldr	r3, [r7, #4]
 800fa78:	2b00      	cmp	r3, #0
 800fa7a:	d029      	beq.n	800fad0 <osMessageQueueNew+0x88>
      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&
 800fa7c:	687b      	ldr	r3, [r7, #4]
 800fa7e:	689b      	ldr	r3, [r3, #8]
 800fa80:	2b00      	cmp	r3, #0
 800fa82:	d012      	beq.n	800faaa <osMessageQueueNew+0x62>
 800fa84:	687b      	ldr	r3, [r7, #4]
 800fa86:	68db      	ldr	r3, [r3, #12]
 800fa88:	2b4f      	cmp	r3, #79	@ 0x4f
 800fa8a:	d90e      	bls.n	800faaa <osMessageQueueNew+0x62>
          (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {
 800fa8c:	687b      	ldr	r3, [r7, #4]
 800fa8e:	691b      	ldr	r3, [r3, #16]
      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&
 800fa90:	2b00      	cmp	r3, #0
 800fa92:	d00a      	beq.n	800faaa <osMessageQueueNew+0x62>
          (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {
 800fa94:	687b      	ldr	r3, [r7, #4]
 800fa96:	695a      	ldr	r2, [r3, #20]
 800fa98:	68fb      	ldr	r3, [r7, #12]
 800fa9a:	68b9      	ldr	r1, [r7, #8]
 800fa9c:	fb01 f303 	mul.w	r3, r1, r3
 800faa0:	429a      	cmp	r2, r3
 800faa2:	d302      	bcc.n	800faaa <osMessageQueueNew+0x62>
        mem = 1;
 800faa4:	2301      	movs	r3, #1
 800faa6:	61bb      	str	r3, [r7, #24]
 800faa8:	e014      	b.n	800fad4 <osMessageQueueNew+0x8c>
      }
      else {
        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&
 800faaa:	687b      	ldr	r3, [r7, #4]
 800faac:	689b      	ldr	r3, [r3, #8]
 800faae:	2b00      	cmp	r3, #0
 800fab0:	d110      	bne.n	800fad4 <osMessageQueueNew+0x8c>
 800fab2:	687b      	ldr	r3, [r7, #4]
 800fab4:	68db      	ldr	r3, [r3, #12]
 800fab6:	2b00      	cmp	r3, #0
 800fab8:	d10c      	bne.n	800fad4 <osMessageQueueNew+0x8c>
            (attr->mq_mem == NULL) && (attr->mq_size == 0U)) {
 800faba:	687b      	ldr	r3, [r7, #4]
 800fabc:	691b      	ldr	r3, [r3, #16]
        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&
 800fabe:	2b00      	cmp	r3, #0
 800fac0:	d108      	bne.n	800fad4 <osMessageQueueNew+0x8c>
            (attr->mq_mem == NULL) && (attr->mq_size == 0U)) {
 800fac2:	687b      	ldr	r3, [r7, #4]
 800fac4:	695b      	ldr	r3, [r3, #20]
 800fac6:	2b00      	cmp	r3, #0
 800fac8:	d104      	bne.n	800fad4 <osMessageQueueNew+0x8c>
          mem = 0;
 800faca:	2300      	movs	r3, #0
 800facc:	61bb      	str	r3, [r7, #24]
 800face:	e001      	b.n	800fad4 <osMessageQueueNew+0x8c>
        }
      }
    }
    else {
      mem = 0;
 800fad0:	2300      	movs	r3, #0
 800fad2:	61bb      	str	r3, [r7, #24]
    }

    if (mem == 1) {
 800fad4:	69bb      	ldr	r3, [r7, #24]
 800fad6:	2b01      	cmp	r3, #1
 800fad8:	d10b      	bne.n	800faf2 <osMessageQueueNew+0xaa>
      #if (configSUPPORT_STATIC_ALLOCATION == 1)
        hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem);
 800fada:	687b      	ldr	r3, [r7, #4]
 800fadc:	691a      	ldr	r2, [r3, #16]
 800fade:	687b      	ldr	r3, [r7, #4]
 800fae0:	689b      	ldr	r3, [r3, #8]
 800fae2:	2100      	movs	r1, #0
 800fae4:	9100      	str	r1, [sp, #0]
 800fae6:	68b9      	ldr	r1, [r7, #8]
 800fae8:	68f8      	ldr	r0, [r7, #12]
 800faea:	f000 fa31 	bl	800ff50 <xQueueGenericCreateStatic>
 800faee:	61f8      	str	r0, [r7, #28]
 800faf0:	e008      	b.n	800fb04 <osMessageQueueNew+0xbc>
      #endif
    }
    else {
      if (mem == 0) {
 800faf2:	69bb      	ldr	r3, [r7, #24]
 800faf4:	2b00      	cmp	r3, #0
 800faf6:	d105      	bne.n	800fb04 <osMessageQueueNew+0xbc>
        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
          hQueue = xQueueCreate (msg_count, msg_size);
 800faf8:	2200      	movs	r2, #0
 800fafa:	68b9      	ldr	r1, [r7, #8]
 800fafc:	68f8      	ldr	r0, [r7, #12]
 800fafe:	f000 faa4 	bl	801004a <xQueueGenericCreate>
 800fb02:	61f8      	str	r0, [r7, #28]
        #endif
      }
    }

    #if (configQUEUE_REGISTRY_SIZE > 0)
    if (hQueue != NULL) {
 800fb04:	69fb      	ldr	r3, [r7, #28]
 800fb06:	2b00      	cmp	r3, #0
 800fb08:	d00c      	beq.n	800fb24 <osMessageQueueNew+0xdc>
      if (attr != NULL) {
 800fb0a:	687b      	ldr	r3, [r7, #4]
 800fb0c:	2b00      	cmp	r3, #0
 800fb0e:	d003      	beq.n	800fb18 <osMessageQueueNew+0xd0>
        name = attr->name;
 800fb10:	687b      	ldr	r3, [r7, #4]
 800fb12:	681b      	ldr	r3, [r3, #0]
 800fb14:	617b      	str	r3, [r7, #20]
 800fb16:	e001      	b.n	800fb1c <osMessageQueueNew+0xd4>
      } else {
        name = NULL;
 800fb18:	2300      	movs	r3, #0
 800fb1a:	617b      	str	r3, [r7, #20]
      }
      vQueueAddToRegistry (hQueue, name);
 800fb1c:	6979      	ldr	r1, [r7, #20]
 800fb1e:	69f8      	ldr	r0, [r7, #28]
 800fb20:	f001 f8e6 	bl	8010cf0 <vQueueAddToRegistry>
    }
    #endif

  }

  return ((osMessageQueueId_t)hQueue);
 800fb24:	69fb      	ldr	r3, [r7, #28]
}
 800fb26:	4618      	mov	r0, r3
 800fb28:	3720      	adds	r7, #32
 800fb2a:	46bd      	mov	sp, r7
 800fb2c:	bd80      	pop	{r7, pc}
	...

0800fb30 <osMessageQueuePut>:

osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
 800fb30:	b580      	push	{r7, lr}
 800fb32:	b088      	sub	sp, #32
 800fb34:	af00      	add	r7, sp, #0
 800fb36:	60f8      	str	r0, [r7, #12]
 800fb38:	60b9      	str	r1, [r7, #8]
 800fb3a:	603b      	str	r3, [r7, #0]
 800fb3c:	4613      	mov	r3, r2
 800fb3e:	71fb      	strb	r3, [r7, #7]
  QueueHandle_t hQueue = (QueueHandle_t)mq_id;
 800fb40:	68fb      	ldr	r3, [r7, #12]
 800fb42:	61bb      	str	r3, [r7, #24]
  osStatus_t stat;
  BaseType_t yield;

  (void)msg_prio; /* Message priority is ignored */

  stat = osOK;
 800fb44:	2300      	movs	r3, #0
 800fb46:	61fb      	str	r3, [r7, #28]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800fb48:	f3ef 8305 	mrs	r3, IPSR
 800fb4c:	617b      	str	r3, [r7, #20]
  return(result);
 800fb4e:	697b      	ldr	r3, [r7, #20]

  if (IS_IRQ()) {
 800fb50:	2b00      	cmp	r3, #0
 800fb52:	d028      	beq.n	800fba6 <osMessageQueuePut+0x76>
    if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
 800fb54:	69bb      	ldr	r3, [r7, #24]
 800fb56:	2b00      	cmp	r3, #0
 800fb58:	d005      	beq.n	800fb66 <osMessageQueuePut+0x36>
 800fb5a:	68bb      	ldr	r3, [r7, #8]
 800fb5c:	2b00      	cmp	r3, #0
 800fb5e:	d002      	beq.n	800fb66 <osMessageQueuePut+0x36>
 800fb60:	683b      	ldr	r3, [r7, #0]
 800fb62:	2b00      	cmp	r3, #0
 800fb64:	d003      	beq.n	800fb6e <osMessageQueuePut+0x3e>
      stat = osErrorParameter;
 800fb66:	f06f 0303 	mvn.w	r3, #3
 800fb6a:	61fb      	str	r3, [r7, #28]
 800fb6c:	e038      	b.n	800fbe0 <osMessageQueuePut+0xb0>
    }
    else {
      yield = pdFALSE;
 800fb6e:	2300      	movs	r3, #0
 800fb70:	613b      	str	r3, [r7, #16]

      if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) {
 800fb72:	f107 0210 	add.w	r2, r7, #16
 800fb76:	2300      	movs	r3, #0
 800fb78:	68b9      	ldr	r1, [r7, #8]
 800fb7a:	69b8      	ldr	r0, [r7, #24]
 800fb7c:	f000 fc7e 	bl	801047c <xQueueGenericSendFromISR>
 800fb80:	4603      	mov	r3, r0
 800fb82:	2b01      	cmp	r3, #1
 800fb84:	d003      	beq.n	800fb8e <osMessageQueuePut+0x5e>
        stat = osErrorResource;
 800fb86:	f06f 0302 	mvn.w	r3, #2
 800fb8a:	61fb      	str	r3, [r7, #28]
 800fb8c:	e028      	b.n	800fbe0 <osMessageQueuePut+0xb0>
      } else {
        portYIELD_FROM_ISR (yield);
 800fb8e:	693b      	ldr	r3, [r7, #16]
 800fb90:	2b00      	cmp	r3, #0
 800fb92:	d025      	beq.n	800fbe0 <osMessageQueuePut+0xb0>
 800fb94:	4b15      	ldr	r3, [pc, #84]	@ (800fbec <osMessageQueuePut+0xbc>)
 800fb96:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 800fb9a:	601a      	str	r2, [r3, #0]
 800fb9c:	f3bf 8f4f 	dsb	sy
 800fba0:	f3bf 8f6f 	isb	sy
 800fba4:	e01c      	b.n	800fbe0 <osMessageQueuePut+0xb0>
      }
    }
  }
  else {
    if ((hQueue == NULL) || (msg_ptr == NULL)) {
 800fba6:	69bb      	ldr	r3, [r7, #24]
 800fba8:	2b00      	cmp	r3, #0
 800fbaa:	d002      	beq.n	800fbb2 <osMessageQueuePut+0x82>
 800fbac:	68bb      	ldr	r3, [r7, #8]
 800fbae:	2b00      	cmp	r3, #0
 800fbb0:	d103      	bne.n	800fbba <osMessageQueuePut+0x8a>
      stat = osErrorParameter;
 800fbb2:	f06f 0303 	mvn.w	r3, #3
 800fbb6:	61fb      	str	r3, [r7, #28]
 800fbb8:	e012      	b.n	800fbe0 <osMessageQueuePut+0xb0>
    }
    else {
      if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
 800fbba:	2300      	movs	r3, #0
 800fbbc:	683a      	ldr	r2, [r7, #0]
 800fbbe:	68b9      	ldr	r1, [r7, #8]
 800fbc0:	69b8      	ldr	r0, [r7, #24]
 800fbc2:	f000 fb59 	bl	8010278 <xQueueGenericSend>
 800fbc6:	4603      	mov	r3, r0
 800fbc8:	2b01      	cmp	r3, #1
 800fbca:	d009      	beq.n	800fbe0 <osMessageQueuePut+0xb0>
        if (timeout != 0U) {
 800fbcc:	683b      	ldr	r3, [r7, #0]
 800fbce:	2b00      	cmp	r3, #0
 800fbd0:	d003      	beq.n	800fbda <osMessageQueuePut+0xaa>
          stat = osErrorTimeout;
 800fbd2:	f06f 0301 	mvn.w	r3, #1
 800fbd6:	61fb      	str	r3, [r7, #28]
 800fbd8:	e002      	b.n	800fbe0 <osMessageQueuePut+0xb0>
        } else {
          stat = osErrorResource;
 800fbda:	f06f 0302 	mvn.w	r3, #2
 800fbde:	61fb      	str	r3, [r7, #28]
        }
      }
    }
  }

  return (stat);
 800fbe0:	69fb      	ldr	r3, [r7, #28]
}
 800fbe2:	4618      	mov	r0, r3
 800fbe4:	3720      	adds	r7, #32
 800fbe6:	46bd      	mov	sp, r7
 800fbe8:	bd80      	pop	{r7, pc}
 800fbea:	bf00      	nop
 800fbec:	e000ed04 	.word	0xe000ed04

0800fbf0 <osMessageQueueGet>:

osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
 800fbf0:	b580      	push	{r7, lr}
 800fbf2:	b088      	sub	sp, #32
 800fbf4:	af00      	add	r7, sp, #0
 800fbf6:	60f8      	str	r0, [r7, #12]
 800fbf8:	60b9      	str	r1, [r7, #8]
 800fbfa:	607a      	str	r2, [r7, #4]
 800fbfc:	603b      	str	r3, [r7, #0]
  QueueHandle_t hQueue = (QueueHandle_t)mq_id;
 800fbfe:	68fb      	ldr	r3, [r7, #12]
 800fc00:	61bb      	str	r3, [r7, #24]
  osStatus_t stat;
  BaseType_t yield;

  (void)msg_prio; /* Message priority is ignored */

  stat = osOK;
 800fc02:	2300      	movs	r3, #0
 800fc04:	61fb      	str	r3, [r7, #28]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800fc06:	f3ef 8305 	mrs	r3, IPSR
 800fc0a:	617b      	str	r3, [r7, #20]
  return(result);
 800fc0c:	697b      	ldr	r3, [r7, #20]

  if (IS_IRQ()) {
 800fc0e:	2b00      	cmp	r3, #0
 800fc10:	d028      	beq.n	800fc64 <osMessageQueueGet+0x74>
    if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
 800fc12:	69bb      	ldr	r3, [r7, #24]
 800fc14:	2b00      	cmp	r3, #0
 800fc16:	d005      	beq.n	800fc24 <osMessageQueueGet+0x34>
 800fc18:	68bb      	ldr	r3, [r7, #8]
 800fc1a:	2b00      	cmp	r3, #0
 800fc1c:	d002      	beq.n	800fc24 <osMessageQueueGet+0x34>
 800fc1e:	683b      	ldr	r3, [r7, #0]
 800fc20:	2b00      	cmp	r3, #0
 800fc22:	d003      	beq.n	800fc2c <osMessageQueueGet+0x3c>
      stat = osErrorParameter;
 800fc24:	f06f 0303 	mvn.w	r3, #3
 800fc28:	61fb      	str	r3, [r7, #28]
 800fc2a:	e037      	b.n	800fc9c <osMessageQueueGet+0xac>
    }
    else {
      yield = pdFALSE;
 800fc2c:	2300      	movs	r3, #0
 800fc2e:	613b      	str	r3, [r7, #16]

      if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) {
 800fc30:	f107 0310 	add.w	r3, r7, #16
 800fc34:	461a      	mov	r2, r3
 800fc36:	68b9      	ldr	r1, [r7, #8]
 800fc38:	69b8      	ldr	r0, [r7, #24]
 800fc3a:	f000 feaf 	bl	801099c <xQueueReceiveFromISR>
 800fc3e:	4603      	mov	r3, r0
 800fc40:	2b01      	cmp	r3, #1
 800fc42:	d003      	beq.n	800fc4c <osMessageQueueGet+0x5c>
        stat = osErrorResource;
 800fc44:	f06f 0302 	mvn.w	r3, #2
 800fc48:	61fb      	str	r3, [r7, #28]
 800fc4a:	e027      	b.n	800fc9c <osMessageQueueGet+0xac>
      } else {
        portYIELD_FROM_ISR (yield);
 800fc4c:	693b      	ldr	r3, [r7, #16]
 800fc4e:	2b00      	cmp	r3, #0
 800fc50:	d024      	beq.n	800fc9c <osMessageQueueGet+0xac>
 800fc52:	4b15      	ldr	r3, [pc, #84]	@ (800fca8 <osMessageQueueGet+0xb8>)
 800fc54:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 800fc58:	601a      	str	r2, [r3, #0]
 800fc5a:	f3bf 8f4f 	dsb	sy
 800fc5e:	f3bf 8f6f 	isb	sy
 800fc62:	e01b      	b.n	800fc9c <osMessageQueueGet+0xac>
      }
    }
  }
  else {
    if ((hQueue == NULL) || (msg_ptr == NULL)) {
 800fc64:	69bb      	ldr	r3, [r7, #24]
 800fc66:	2b00      	cmp	r3, #0
 800fc68:	d002      	beq.n	800fc70 <osMessageQueueGet+0x80>
 800fc6a:	68bb      	ldr	r3, [r7, #8]
 800fc6c:	2b00      	cmp	r3, #0
 800fc6e:	d103      	bne.n	800fc78 <osMessageQueueGet+0x88>
      stat = osErrorParameter;
 800fc70:	f06f 0303 	mvn.w	r3, #3
 800fc74:	61fb      	str	r3, [r7, #28]
 800fc76:	e011      	b.n	800fc9c <osMessageQueueGet+0xac>
    }
    else {
      if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
 800fc78:	683a      	ldr	r2, [r7, #0]
 800fc7a:	68b9      	ldr	r1, [r7, #8]
 800fc7c:	69b8      	ldr	r0, [r7, #24]
 800fc7e:	f000 fc9b 	bl	80105b8 <xQueueReceive>
 800fc82:	4603      	mov	r3, r0
 800fc84:	2b01      	cmp	r3, #1
 800fc86:	d009      	beq.n	800fc9c <osMessageQueueGet+0xac>
        if (timeout != 0U) {
 800fc88:	683b      	ldr	r3, [r7, #0]
 800fc8a:	2b00      	cmp	r3, #0
 800fc8c:	d003      	beq.n	800fc96 <osMessageQueueGet+0xa6>
          stat = osErrorTimeout;
 800fc8e:	f06f 0301 	mvn.w	r3, #1
 800fc92:	61fb      	str	r3, [r7, #28]
 800fc94:	e002      	b.n	800fc9c <osMessageQueueGet+0xac>
        } else {
          stat = osErrorResource;
 800fc96:	f06f 0302 	mvn.w	r3, #2
 800fc9a:	61fb      	str	r3, [r7, #28]
        }
      }
    }
  }

  return (stat);
 800fc9c:	69fb      	ldr	r3, [r7, #28]
}
 800fc9e:	4618      	mov	r0, r3
 800fca0:	3720      	adds	r7, #32
 800fca2:	46bd      	mov	sp, r7
 800fca4:	bd80      	pop	{r7, pc}
 800fca6:	bf00      	nop
 800fca8:	e000ed04 	.word	0xe000ed04

0800fcac <vApplicationGetIdleTaskMemory>:

/*
  vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
  equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
 800fcac:	b480      	push	{r7}
 800fcae:	b085      	sub	sp, #20
 800fcb0:	af00      	add	r7, sp, #0
 800fcb2:	60f8      	str	r0, [r7, #12]
 800fcb4:	60b9      	str	r1, [r7, #8]
 800fcb6:	607a      	str	r2, [r7, #4]
  /* Idle task control block and stack */
  static StaticTask_t Idle_TCB;
  static StackType_t  Idle_Stack[configMINIMAL_STACK_SIZE];

  *ppxIdleTaskTCBBuffer   = &Idle_TCB;
 800fcb8:	68fb      	ldr	r3, [r7, #12]
 800fcba:	4a07      	ldr	r2, [pc, #28]	@ (800fcd8 <vApplicationGetIdleTaskMemory+0x2c>)
 800fcbc:	601a      	str	r2, [r3, #0]
  *ppxIdleTaskStackBuffer = &Idle_Stack[0];
 800fcbe:	68bb      	ldr	r3, [r7, #8]
 800fcc0:	4a06      	ldr	r2, [pc, #24]	@ (800fcdc <vApplicationGetIdleTaskMemory+0x30>)
 800fcc2:	601a      	str	r2, [r3, #0]
  *pulIdleTaskStackSize   = (uint32_t)configMINIMAL_STACK_SIZE;
 800fcc4:	687b      	ldr	r3, [r7, #4]
 800fcc6:	f44f 7200 	mov.w	r2, #512	@ 0x200
 800fcca:	601a      	str	r2, [r3, #0]
}
 800fccc:	bf00      	nop
 800fcce:	3714      	adds	r7, #20
 800fcd0:	46bd      	mov	sp, r7
 800fcd2:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fcd6:	4770      	bx	lr
 800fcd8:	24000a64 	.word	0x24000a64
 800fcdc:	24000b0c 	.word	0x24000b0c

0800fce0 <vApplicationGetTimerTaskMemory>:

/*
  vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
  equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
 800fce0:	b480      	push	{r7}
 800fce2:	b085      	sub	sp, #20
 800fce4:	af00      	add	r7, sp, #0
 800fce6:	60f8      	str	r0, [r7, #12]
 800fce8:	60b9      	str	r1, [r7, #8]
 800fcea:	607a      	str	r2, [r7, #4]
  /* Timer task control block and stack */
  static StaticTask_t Timer_TCB;
  static StackType_t  Timer_Stack[configTIMER_TASK_STACK_DEPTH];

  *ppxTimerTaskTCBBuffer   = &Timer_TCB;
 800fcec:	68fb      	ldr	r3, [r7, #12]
 800fcee:	4a07      	ldr	r2, [pc, #28]	@ (800fd0c <vApplicationGetTimerTaskMemory+0x2c>)
 800fcf0:	601a      	str	r2, [r3, #0]
  *ppxTimerTaskStackBuffer = &Timer_Stack[0];
 800fcf2:	68bb      	ldr	r3, [r7, #8]
 800fcf4:	4a06      	ldr	r2, [pc, #24]	@ (800fd10 <vApplicationGetTimerTaskMemory+0x30>)
 800fcf6:	601a      	str	r2, [r3, #0]
  *pulTimerTaskStackSize   = (uint32_t)configTIMER_TASK_STACK_DEPTH;
 800fcf8:	687b      	ldr	r3, [r7, #4]
 800fcfa:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 800fcfe:	601a      	str	r2, [r3, #0]
}
 800fd00:	bf00      	nop
 800fd02:	3714      	adds	r7, #20
 800fd04:	46bd      	mov	sp, r7
 800fd06:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fd0a:	4770      	bx	lr
 800fd0c:	2400130c 	.word	0x2400130c
 800fd10:	240013b4 	.word	0x240013b4

0800fd14 <vListInitialise>:
/*-----------------------------------------------------------
 * PUBLIC LIST API documented in list.h
 *----------------------------------------------------------*/

void vListInitialise( List_t * const pxList )
{
 800fd14:	b480      	push	{r7}
 800fd16:	b083      	sub	sp, #12
 800fd18:	af00      	add	r7, sp, #0
 800fd1a:	6078      	str	r0, [r7, #4]
	/* The list structure contains a list item which is used to mark the
	end of the list.  To initialise the list the list end is inserted
	as the only list entry. */
	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 800fd1c:	687b      	ldr	r3, [r7, #4]
 800fd1e:	f103 0208 	add.w	r2, r3, #8
 800fd22:	687b      	ldr	r3, [r7, #4]
 800fd24:	605a      	str	r2, [r3, #4]

	/* The list end value is the highest possible value in the list to
	ensure it remains at the end of the list. */
	pxList->xListEnd.xItemValue = portMAX_DELAY;
 800fd26:	687b      	ldr	r3, [r7, #4]
 800fd28:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 800fd2c:	609a      	str	r2, [r3, #8]

	/* The list end next and previous pointers point to itself so we know
	when the list is empty. */
	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 800fd2e:	687b      	ldr	r3, [r7, #4]
 800fd30:	f103 0208 	add.w	r2, r3, #8
 800fd34:	687b      	ldr	r3, [r7, #4]
 800fd36:	60da      	str	r2, [r3, #12]
	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 800fd38:	687b      	ldr	r3, [r7, #4]
 800fd3a:	f103 0208 	add.w	r2, r3, #8
 800fd3e:	687b      	ldr	r3, [r7, #4]
 800fd40:	611a      	str	r2, [r3, #16]

	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
 800fd42:	687b      	ldr	r3, [r7, #4]
 800fd44:	2200      	movs	r2, #0
 800fd46:	601a      	str	r2, [r3, #0]

	/* Write known values into the list if
	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
 800fd48:	bf00      	nop
 800fd4a:	370c      	adds	r7, #12
 800fd4c:	46bd      	mov	sp, r7
 800fd4e:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fd52:	4770      	bx	lr

0800fd54 <vListInitialiseItem>:
/*-----------------------------------------------------------*/

void vListInitialiseItem( ListItem_t * const pxItem )
{
 800fd54:	b480      	push	{r7}
 800fd56:	b083      	sub	sp, #12
 800fd58:	af00      	add	r7, sp, #0
 800fd5a:	6078      	str	r0, [r7, #4]
	/* Make sure the list item is not recorded as being on a list. */
	pxItem->pxContainer = NULL;
 800fd5c:	687b      	ldr	r3, [r7, #4]
 800fd5e:	2200      	movs	r2, #0
 800fd60:	611a      	str	r2, [r3, #16]

	/* Write known values into the list item if
	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
 800fd62:	bf00      	nop
 800fd64:	370c      	adds	r7, #12
 800fd66:	46bd      	mov	sp, r7
 800fd68:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fd6c:	4770      	bx	lr

0800fd6e <vListInsertEnd>:
/*-----------------------------------------------------------*/

void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
 800fd6e:	b480      	push	{r7}
 800fd70:	b085      	sub	sp, #20
 800fd72:	af00      	add	r7, sp, #0
 800fd74:	6078      	str	r0, [r7, #4]
 800fd76:	6039      	str	r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
 800fd78:	687b      	ldr	r3, [r7, #4]
 800fd7a:	685b      	ldr	r3, [r3, #4]
 800fd7c:	60fb      	str	r3, [r7, #12]
	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );

	/* Insert a new list item into pxList, but rather than sort the list,
	makes the new list item the last item to be removed by a call to
	listGET_OWNER_OF_NEXT_ENTRY(). */
	pxNewListItem->pxNext = pxIndex;
 800fd7e:	683b      	ldr	r3, [r7, #0]
 800fd80:	68fa      	ldr	r2, [r7, #12]
 800fd82:	605a      	str	r2, [r3, #4]
	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
 800fd84:	68fb      	ldr	r3, [r7, #12]
 800fd86:	689a      	ldr	r2, [r3, #8]
 800fd88:	683b      	ldr	r3, [r7, #0]
 800fd8a:	609a      	str	r2, [r3, #8]

	/* Only used during decision coverage testing. */
	mtCOVERAGE_TEST_DELAY();

	pxIndex->pxPrevious->pxNext = pxNewListItem;
 800fd8c:	68fb      	ldr	r3, [r7, #12]
 800fd8e:	689b      	ldr	r3, [r3, #8]
 800fd90:	683a      	ldr	r2, [r7, #0]
 800fd92:	605a      	str	r2, [r3, #4]
	pxIndex->pxPrevious = pxNewListItem;
 800fd94:	68fb      	ldr	r3, [r7, #12]
 800fd96:	683a      	ldr	r2, [r7, #0]
 800fd98:	609a      	str	r2, [r3, #8]

	/* Remember which list the item is in. */
	pxNewListItem->pxContainer = pxList;
 800fd9a:	683b      	ldr	r3, [r7, #0]
 800fd9c:	687a      	ldr	r2, [r7, #4]
 800fd9e:	611a      	str	r2, [r3, #16]

	( pxList->uxNumberOfItems )++;
 800fda0:	687b      	ldr	r3, [r7, #4]
 800fda2:	681b      	ldr	r3, [r3, #0]
 800fda4:	1c5a      	adds	r2, r3, #1
 800fda6:	687b      	ldr	r3, [r7, #4]
 800fda8:	601a      	str	r2, [r3, #0]
}
 800fdaa:	bf00      	nop
 800fdac:	3714      	adds	r7, #20
 800fdae:	46bd      	mov	sp, r7
 800fdb0:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fdb4:	4770      	bx	lr

0800fdb6 <vListInsert>:
/*-----------------------------------------------------------*/

void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
 800fdb6:	b480      	push	{r7}
 800fdb8:	b085      	sub	sp, #20
 800fdba:	af00      	add	r7, sp, #0
 800fdbc:	6078      	str	r0, [r7, #4]
 800fdbe:	6039      	str	r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 800fdc0:	683b      	ldr	r3, [r7, #0]
 800fdc2:	681b      	ldr	r3, [r3, #0]
 800fdc4:	60bb      	str	r3, [r7, #8]
	new list item should be placed after it.  This ensures that TCBs which are
	stored in ready lists (all of which have the same xItemValue value) get a
	share of the CPU.  However, if the xItemValue is the same as the back marker
	the iteration loop below will not end.  Therefore the value is checked
	first, and the algorithm slightly modified if necessary. */
	if( xValueOfInsertion == portMAX_DELAY )
 800fdc6:	68bb      	ldr	r3, [r7, #8]
 800fdc8:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 800fdcc:	d103      	bne.n	800fdd6 <vListInsert+0x20>
	{
		pxIterator = pxList->xListEnd.pxPrevious;
 800fdce:	687b      	ldr	r3, [r7, #4]
 800fdd0:	691b      	ldr	r3, [r3, #16]
 800fdd2:	60fb      	str	r3, [r7, #12]
 800fdd4:	e00c      	b.n	800fdf0 <vListInsert+0x3a>
			4) Using a queue or semaphore before it has been initialised or
			   before the scheduler has been started (are interrupts firing
			   before vTaskStartScheduler() has been called?).
		**********************************************************************/

		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
 800fdd6:	687b      	ldr	r3, [r7, #4]
 800fdd8:	3308      	adds	r3, #8
 800fdda:	60fb      	str	r3, [r7, #12]
 800fddc:	e002      	b.n	800fde4 <vListInsert+0x2e>
 800fdde:	68fb      	ldr	r3, [r7, #12]
 800fde0:	685b      	ldr	r3, [r3, #4]
 800fde2:	60fb      	str	r3, [r7, #12]
 800fde4:	68fb      	ldr	r3, [r7, #12]
 800fde6:	685b      	ldr	r3, [r3, #4]
 800fde8:	681b      	ldr	r3, [r3, #0]
 800fdea:	68ba      	ldr	r2, [r7, #8]
 800fdec:	429a      	cmp	r2, r3
 800fdee:	d2f6      	bcs.n	800fdde <vListInsert+0x28>
			/* There is nothing to do here, just iterating to the wanted
			insertion position. */
		}
	}

	pxNewListItem->pxNext = pxIterator->pxNext;
 800fdf0:	68fb      	ldr	r3, [r7, #12]
 800fdf2:	685a      	ldr	r2, [r3, #4]
 800fdf4:	683b      	ldr	r3, [r7, #0]
 800fdf6:	605a      	str	r2, [r3, #4]
	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
 800fdf8:	683b      	ldr	r3, [r7, #0]
 800fdfa:	685b      	ldr	r3, [r3, #4]
 800fdfc:	683a      	ldr	r2, [r7, #0]
 800fdfe:	609a      	str	r2, [r3, #8]
	pxNewListItem->pxPrevious = pxIterator;
 800fe00:	683b      	ldr	r3, [r7, #0]
 800fe02:	68fa      	ldr	r2, [r7, #12]
 800fe04:	609a      	str	r2, [r3, #8]
	pxIterator->pxNext = pxNewListItem;
 800fe06:	68fb      	ldr	r3, [r7, #12]
 800fe08:	683a      	ldr	r2, [r7, #0]
 800fe0a:	605a      	str	r2, [r3, #4]

	/* Remember which list the item is in.  This allows fast removal of the
	item later. */
	pxNewListItem->pxContainer = pxList;
 800fe0c:	683b      	ldr	r3, [r7, #0]
 800fe0e:	687a      	ldr	r2, [r7, #4]
 800fe10:	611a      	str	r2, [r3, #16]

	( pxList->uxNumberOfItems )++;
 800fe12:	687b      	ldr	r3, [r7, #4]
 800fe14:	681b      	ldr	r3, [r3, #0]
 800fe16:	1c5a      	adds	r2, r3, #1
 800fe18:	687b      	ldr	r3, [r7, #4]
 800fe1a:	601a      	str	r2, [r3, #0]
}
 800fe1c:	bf00      	nop
 800fe1e:	3714      	adds	r7, #20
 800fe20:	46bd      	mov	sp, r7
 800fe22:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fe26:	4770      	bx	lr

0800fe28 <uxListRemove>:
/*-----------------------------------------------------------*/

UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
 800fe28:	b480      	push	{r7}
 800fe2a:	b085      	sub	sp, #20
 800fe2c:	af00      	add	r7, sp, #0
 800fe2e:	6078      	str	r0, [r7, #4]
/* The list item knows which list it is in.  Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
 800fe30:	687b      	ldr	r3, [r7, #4]
 800fe32:	691b      	ldr	r3, [r3, #16]
 800fe34:	60fb      	str	r3, [r7, #12]

	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
 800fe36:	687b      	ldr	r3, [r7, #4]
 800fe38:	685b      	ldr	r3, [r3, #4]
 800fe3a:	687a      	ldr	r2, [r7, #4]
 800fe3c:	6892      	ldr	r2, [r2, #8]
 800fe3e:	609a      	str	r2, [r3, #8]
	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
 800fe40:	687b      	ldr	r3, [r7, #4]
 800fe42:	689b      	ldr	r3, [r3, #8]
 800fe44:	687a      	ldr	r2, [r7, #4]
 800fe46:	6852      	ldr	r2, [r2, #4]
 800fe48:	605a      	str	r2, [r3, #4]

	/* Only used during decision coverage testing. */
	mtCOVERAGE_TEST_DELAY();

	/* Make sure the index is left pointing to a valid item. */
	if( pxList->pxIndex == pxItemToRemove )
 800fe4a:	68fb      	ldr	r3, [r7, #12]
 800fe4c:	685b      	ldr	r3, [r3, #4]
 800fe4e:	687a      	ldr	r2, [r7, #4]
 800fe50:	429a      	cmp	r2, r3
 800fe52:	d103      	bne.n	800fe5c <uxListRemove+0x34>
	{
		pxList->pxIndex = pxItemToRemove->pxPrevious;
 800fe54:	687b      	ldr	r3, [r7, #4]
 800fe56:	689a      	ldr	r2, [r3, #8]
 800fe58:	68fb      	ldr	r3, [r7, #12]
 800fe5a:	605a      	str	r2, [r3, #4]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxItemToRemove->pxContainer = NULL;
 800fe5c:	687b      	ldr	r3, [r7, #4]
 800fe5e:	2200      	movs	r2, #0
 800fe60:	611a      	str	r2, [r3, #16]
	( pxList->uxNumberOfItems )--;
 800fe62:	68fb      	ldr	r3, [r7, #12]
 800fe64:	681b      	ldr	r3, [r3, #0]
 800fe66:	1e5a      	subs	r2, r3, #1
 800fe68:	68fb      	ldr	r3, [r7, #12]
 800fe6a:	601a      	str	r2, [r3, #0]

	return pxList->uxNumberOfItems;
 800fe6c:	68fb      	ldr	r3, [r7, #12]
 800fe6e:	681b      	ldr	r3, [r3, #0]
}
 800fe70:	4618      	mov	r0, r3
 800fe72:	3714      	adds	r7, #20
 800fe74:	46bd      	mov	sp, r7
 800fe76:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fe7a:	4770      	bx	lr

0800fe7c <xQueueGenericReset>:
	}														\
	taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
 800fe7c:	b580      	push	{r7, lr}
 800fe7e:	b084      	sub	sp, #16
 800fe80:	af00      	add	r7, sp, #0
 800fe82:	6078      	str	r0, [r7, #4]
 800fe84:	6039      	str	r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
 800fe86:	687b      	ldr	r3, [r7, #4]
 800fe88:	60fb      	str	r3, [r7, #12]

	configASSERT( pxQueue );
 800fe8a:	68fb      	ldr	r3, [r7, #12]
 800fe8c:	2b00      	cmp	r3, #0
 800fe8e:	d10b      	bne.n	800fea8 <xQueueGenericReset+0x2c>

portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;

	__asm volatile
 800fe90:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800fe94:	f383 8811 	msr	BASEPRI, r3
 800fe98:	f3bf 8f6f 	isb	sy
 800fe9c:	f3bf 8f4f 	dsb	sy
 800fea0:	60bb      	str	r3, [r7, #8]
		"	msr basepri, %0											\n" \
		"	isb														\n" \
		"	dsb														\n" \
		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
	);
}
 800fea2:	bf00      	nop
 800fea4:	bf00      	nop
 800fea6:	e7fd      	b.n	800fea4 <xQueueGenericReset+0x28>

	taskENTER_CRITICAL();
 800fea8:	f003 f876 	bl	8012f98 <vPortEnterCritical>
	{
		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 800feac:	68fb      	ldr	r3, [r7, #12]
 800feae:	681a      	ldr	r2, [r3, #0]
 800feb0:	68fb      	ldr	r3, [r7, #12]
 800feb2:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 800feb4:	68f9      	ldr	r1, [r7, #12]
 800feb6:	6c09      	ldr	r1, [r1, #64]	@ 0x40
 800feb8:	fb01 f303 	mul.w	r3, r1, r3
 800febc:	441a      	add	r2, r3
 800febe:	68fb      	ldr	r3, [r7, #12]
 800fec0:	609a      	str	r2, [r3, #8]
		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
 800fec2:	68fb      	ldr	r3, [r7, #12]
 800fec4:	2200      	movs	r2, #0
 800fec6:	639a      	str	r2, [r3, #56]	@ 0x38
		pxQueue->pcWriteTo = pxQueue->pcHead;
 800fec8:	68fb      	ldr	r3, [r7, #12]
 800feca:	681a      	ldr	r2, [r3, #0]
 800fecc:	68fb      	ldr	r3, [r7, #12]
 800fece:	605a      	str	r2, [r3, #4]
		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 800fed0:	68fb      	ldr	r3, [r7, #12]
 800fed2:	681a      	ldr	r2, [r3, #0]
 800fed4:	68fb      	ldr	r3, [r7, #12]
 800fed6:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 800fed8:	3b01      	subs	r3, #1
 800feda:	68f9      	ldr	r1, [r7, #12]
 800fedc:	6c09      	ldr	r1, [r1, #64]	@ 0x40
 800fede:	fb01 f303 	mul.w	r3, r1, r3
 800fee2:	441a      	add	r2, r3
 800fee4:	68fb      	ldr	r3, [r7, #12]
 800fee6:	60da      	str	r2, [r3, #12]
		pxQueue->cRxLock = queueUNLOCKED;
 800fee8:	68fb      	ldr	r3, [r7, #12]
 800feea:	22ff      	movs	r2, #255	@ 0xff
 800feec:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
		pxQueue->cTxLock = queueUNLOCKED;
 800fef0:	68fb      	ldr	r3, [r7, #12]
 800fef2:	22ff      	movs	r2, #255	@ 0xff
 800fef4:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45

		if( xNewQueue == pdFALSE )
 800fef8:	683b      	ldr	r3, [r7, #0]
 800fefa:	2b00      	cmp	r3, #0
 800fefc:	d114      	bne.n	800ff28 <xQueueGenericReset+0xac>
			/* If there are tasks blocked waiting to read from the queue, then
			the tasks will remain blocked as after this function exits the queue
			will still be empty.  If there are tasks blocked waiting to write to
			the queue, then one should be unblocked as after this function exits
			it will be possible to write to it. */
			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 800fefe:	68fb      	ldr	r3, [r7, #12]
 800ff00:	691b      	ldr	r3, [r3, #16]
 800ff02:	2b00      	cmp	r3, #0
 800ff04:	d01a      	beq.n	800ff3c <xQueueGenericReset+0xc0>
			{
				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 800ff06:	68fb      	ldr	r3, [r7, #12]
 800ff08:	3310      	adds	r3, #16
 800ff0a:	4618      	mov	r0, r3
 800ff0c:	f001 fdac 	bl	8011a68 <xTaskRemoveFromEventList>
 800ff10:	4603      	mov	r3, r0
 800ff12:	2b00      	cmp	r3, #0
 800ff14:	d012      	beq.n	800ff3c <xQueueGenericReset+0xc0>
				{
					queueYIELD_IF_USING_PREEMPTION();
 800ff16:	4b0d      	ldr	r3, [pc, #52]	@ (800ff4c <xQueueGenericReset+0xd0>)
 800ff18:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 800ff1c:	601a      	str	r2, [r3, #0]
 800ff1e:	f3bf 8f4f 	dsb	sy
 800ff22:	f3bf 8f6f 	isb	sy
 800ff26:	e009      	b.n	800ff3c <xQueueGenericReset+0xc0>
			}
		}
		else
		{
			/* Ensure the event queues start in the correct state. */
			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
 800ff28:	68fb      	ldr	r3, [r7, #12]
 800ff2a:	3310      	adds	r3, #16
 800ff2c:	4618      	mov	r0, r3
 800ff2e:	f7ff fef1 	bl	800fd14 <vListInitialise>
			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
 800ff32:	68fb      	ldr	r3, [r7, #12]
 800ff34:	3324      	adds	r3, #36	@ 0x24
 800ff36:	4618      	mov	r0, r3
 800ff38:	f7ff feec 	bl	800fd14 <vListInitialise>
		}
	}
	taskEXIT_CRITICAL();
 800ff3c:	f003 f85e 	bl	8012ffc <vPortExitCritical>

	/* A value is returned for calling semantic consistency with previous
	versions. */
	return pdPASS;
 800ff40:	2301      	movs	r3, #1
}
 800ff42:	4618      	mov	r0, r3
 800ff44:	3710      	adds	r7, #16
 800ff46:	46bd      	mov	sp, r7
 800ff48:	bd80      	pop	{r7, pc}
 800ff4a:	bf00      	nop
 800ff4c:	e000ed04 	.word	0xe000ed04

0800ff50 <xQueueGenericCreateStatic>:
/*-----------------------------------------------------------*/

#if( configSUPPORT_STATIC_ALLOCATION == 1 )

	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
	{
 800ff50:	b580      	push	{r7, lr}
 800ff52:	b08e      	sub	sp, #56	@ 0x38
 800ff54:	af02      	add	r7, sp, #8
 800ff56:	60f8      	str	r0, [r7, #12]
 800ff58:	60b9      	str	r1, [r7, #8]
 800ff5a:	607a      	str	r2, [r7, #4]
 800ff5c:	603b      	str	r3, [r7, #0]
	Queue_t *pxNewQueue;

		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
 800ff5e:	68fb      	ldr	r3, [r7, #12]
 800ff60:	2b00      	cmp	r3, #0
 800ff62:	d10b      	bne.n	800ff7c <xQueueGenericCreateStatic+0x2c>
	__asm volatile
 800ff64:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800ff68:	f383 8811 	msr	BASEPRI, r3
 800ff6c:	f3bf 8f6f 	isb	sy
 800ff70:	f3bf 8f4f 	dsb	sy
 800ff74:	62bb      	str	r3, [r7, #40]	@ 0x28
}
 800ff76:	bf00      	nop
 800ff78:	bf00      	nop
 800ff7a:	e7fd      	b.n	800ff78 <xQueueGenericCreateStatic+0x28>

		/* The StaticQueue_t structure and the queue storage area must be
		supplied. */
		configASSERT( pxStaticQueue != NULL );
 800ff7c:	683b      	ldr	r3, [r7, #0]
 800ff7e:	2b00      	cmp	r3, #0
 800ff80:	d10b      	bne.n	800ff9a <xQueueGenericCreateStatic+0x4a>
	__asm volatile
 800ff82:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800ff86:	f383 8811 	msr	BASEPRI, r3
 800ff8a:	f3bf 8f6f 	isb	sy
 800ff8e:	f3bf 8f4f 	dsb	sy
 800ff92:	627b      	str	r3, [r7, #36]	@ 0x24
}
 800ff94:	bf00      	nop
 800ff96:	bf00      	nop
 800ff98:	e7fd      	b.n	800ff96 <xQueueGenericCreateStatic+0x46>

		/* A queue storage area should be provided if the item size is not 0, and
		should not be provided if the item size is 0. */
		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
 800ff9a:	687b      	ldr	r3, [r7, #4]
 800ff9c:	2b00      	cmp	r3, #0
 800ff9e:	d002      	beq.n	800ffa6 <xQueueGenericCreateStatic+0x56>
 800ffa0:	68bb      	ldr	r3, [r7, #8]
 800ffa2:	2b00      	cmp	r3, #0
 800ffa4:	d001      	beq.n	800ffaa <xQueueGenericCreateStatic+0x5a>
 800ffa6:	2301      	movs	r3, #1
 800ffa8:	e000      	b.n	800ffac <xQueueGenericCreateStatic+0x5c>
 800ffaa:	2300      	movs	r3, #0
 800ffac:	2b00      	cmp	r3, #0
 800ffae:	d10b      	bne.n	800ffc8 <xQueueGenericCreateStatic+0x78>
	__asm volatile
 800ffb0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800ffb4:	f383 8811 	msr	BASEPRI, r3
 800ffb8:	f3bf 8f6f 	isb	sy
 800ffbc:	f3bf 8f4f 	dsb	sy
 800ffc0:	623b      	str	r3, [r7, #32]
}
 800ffc2:	bf00      	nop
 800ffc4:	bf00      	nop
 800ffc6:	e7fd      	b.n	800ffc4 <xQueueGenericCreateStatic+0x74>
		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
 800ffc8:	687b      	ldr	r3, [r7, #4]
 800ffca:	2b00      	cmp	r3, #0
 800ffcc:	d102      	bne.n	800ffd4 <xQueueGenericCreateStatic+0x84>
 800ffce:	68bb      	ldr	r3, [r7, #8]
 800ffd0:	2b00      	cmp	r3, #0
 800ffd2:	d101      	bne.n	800ffd8 <xQueueGenericCreateStatic+0x88>
 800ffd4:	2301      	movs	r3, #1
 800ffd6:	e000      	b.n	800ffda <xQueueGenericCreateStatic+0x8a>
 800ffd8:	2300      	movs	r3, #0
 800ffda:	2b00      	cmp	r3, #0
 800ffdc:	d10b      	bne.n	800fff6 <xQueueGenericCreateStatic+0xa6>
	__asm volatile
 800ffde:	f04f 0350 	mov.w	r3, #80	@ 0x50
 800ffe2:	f383 8811 	msr	BASEPRI, r3
 800ffe6:	f3bf 8f6f 	isb	sy
 800ffea:	f3bf 8f4f 	dsb	sy
 800ffee:	61fb      	str	r3, [r7, #28]
}
 800fff0:	bf00      	nop
 800fff2:	bf00      	nop
 800fff4:	e7fd      	b.n	800fff2 <xQueueGenericCreateStatic+0xa2>
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
			the real queue and semaphore structures. */
			volatile size_t xSize = sizeof( StaticQueue_t );
 800fff6:	2350      	movs	r3, #80	@ 0x50
 800fff8:	617b      	str	r3, [r7, #20]
			configASSERT( xSize == sizeof( Queue_t ) );
 800fffa:	697b      	ldr	r3, [r7, #20]
 800fffc:	2b50      	cmp	r3, #80	@ 0x50
 800fffe:	d00b      	beq.n	8010018 <xQueueGenericCreateStatic+0xc8>
	__asm volatile
 8010000:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010004:	f383 8811 	msr	BASEPRI, r3
 8010008:	f3bf 8f6f 	isb	sy
 801000c:	f3bf 8f4f 	dsb	sy
 8010010:	61bb      	str	r3, [r7, #24]
}
 8010012:	bf00      	nop
 8010014:	bf00      	nop
 8010016:	e7fd      	b.n	8010014 <xQueueGenericCreateStatic+0xc4>
			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
 8010018:	697b      	ldr	r3, [r7, #20]
		#endif /* configASSERT_DEFINED */

		/* The address of a statically allocated queue was passed in, use it.
		The address of a statically allocated storage area was also passed in
		but is already set. */
		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 801001a:	683b      	ldr	r3, [r7, #0]
 801001c:	62fb      	str	r3, [r7, #44]	@ 0x2c

		if( pxNewQueue != NULL )
 801001e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010020:	2b00      	cmp	r3, #0
 8010022:	d00d      	beq.n	8010040 <xQueueGenericCreateStatic+0xf0>
			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
			{
				/* Queues can be allocated wither statically or dynamically, so
				note this queue was allocated statically in case the queue is
				later deleted. */
				pxNewQueue->ucStaticallyAllocated = pdTRUE;
 8010024:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010026:	2201      	movs	r2, #1
 8010028:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
			}
			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */

			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
 801002c:	f897 2038 	ldrb.w	r2, [r7, #56]	@ 0x38
 8010030:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010032:	9300      	str	r3, [sp, #0]
 8010034:	4613      	mov	r3, r2
 8010036:	687a      	ldr	r2, [r7, #4]
 8010038:	68b9      	ldr	r1, [r7, #8]
 801003a:	68f8      	ldr	r0, [r7, #12]
 801003c:	f000 f840 	bl	80100c0 <prvInitialiseNewQueue>
		{
			traceQUEUE_CREATE_FAILED( ucQueueType );
			mtCOVERAGE_TEST_MARKER();
		}

		return pxNewQueue;
 8010040:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
	}
 8010042:	4618      	mov	r0, r3
 8010044:	3730      	adds	r7, #48	@ 0x30
 8010046:	46bd      	mov	sp, r7
 8010048:	bd80      	pop	{r7, pc}

0801004a <xQueueGenericCreate>:
/*-----------------------------------------------------------*/

#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )

	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
	{
 801004a:	b580      	push	{r7, lr}
 801004c:	b08a      	sub	sp, #40	@ 0x28
 801004e:	af02      	add	r7, sp, #8
 8010050:	60f8      	str	r0, [r7, #12]
 8010052:	60b9      	str	r1, [r7, #8]
 8010054:	4613      	mov	r3, r2
 8010056:	71fb      	strb	r3, [r7, #7]
	Queue_t *pxNewQueue;
	size_t xQueueSizeInBytes;
	uint8_t *pucQueueStorage;

		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
 8010058:	68fb      	ldr	r3, [r7, #12]
 801005a:	2b00      	cmp	r3, #0
 801005c:	d10b      	bne.n	8010076 <xQueueGenericCreate+0x2c>
	__asm volatile
 801005e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010062:	f383 8811 	msr	BASEPRI, r3
 8010066:	f3bf 8f6f 	isb	sy
 801006a:	f3bf 8f4f 	dsb	sy
 801006e:	613b      	str	r3, [r7, #16]
}
 8010070:	bf00      	nop
 8010072:	bf00      	nop
 8010074:	e7fd      	b.n	8010072 <xQueueGenericCreate+0x28>

		/* Allocate enough space to hold the maximum number of items that
		can be in the queue at any time.  It is valid for uxItemSize to be
		zero in the case the queue is used as a semaphore. */
		xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8010076:	68fb      	ldr	r3, [r7, #12]
 8010078:	68ba      	ldr	r2, [r7, #8]
 801007a:	fb02 f303 	mul.w	r3, r2, r3
 801007e:	61fb      	str	r3, [r7, #28]
		alignment requirements of the Queue_t structure - which in this case
		is an int8_t *.  Therefore, whenever the stack alignment requirements
		are greater than or equal to the pointer to char requirements the cast
		is safe.  In other cases alignment requirements are not strict (one or
		two bytes). */
		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
 8010080:	69fb      	ldr	r3, [r7, #28]
 8010082:	3350      	adds	r3, #80	@ 0x50
 8010084:	4618      	mov	r0, r3
 8010086:	f003 f8a9 	bl	80131dc <pvPortMalloc>
 801008a:	61b8      	str	r0, [r7, #24]

		if( pxNewQueue != NULL )
 801008c:	69bb      	ldr	r3, [r7, #24]
 801008e:	2b00      	cmp	r3, #0
 8010090:	d011      	beq.n	80100b6 <xQueueGenericCreate+0x6c>
		{
			/* Jump past the queue structure to find the location of the queue
			storage area. */
			pucQueueStorage = ( uint8_t * ) pxNewQueue;
 8010092:	69bb      	ldr	r3, [r7, #24]
 8010094:	617b      	str	r3, [r7, #20]
			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 8010096:	697b      	ldr	r3, [r7, #20]
 8010098:	3350      	adds	r3, #80	@ 0x50
 801009a:	617b      	str	r3, [r7, #20]
			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
			{
				/* Queues can be created either statically or dynamically, so
				note this task was created dynamically in case it is later
				deleted. */
				pxNewQueue->ucStaticallyAllocated = pdFALSE;
 801009c:	69bb      	ldr	r3, [r7, #24]
 801009e:	2200      	movs	r2, #0
 80100a0:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
			}
			#endif /* configSUPPORT_STATIC_ALLOCATION */

			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
 80100a4:	79fa      	ldrb	r2, [r7, #7]
 80100a6:	69bb      	ldr	r3, [r7, #24]
 80100a8:	9300      	str	r3, [sp, #0]
 80100aa:	4613      	mov	r3, r2
 80100ac:	697a      	ldr	r2, [r7, #20]
 80100ae:	68b9      	ldr	r1, [r7, #8]
 80100b0:	68f8      	ldr	r0, [r7, #12]
 80100b2:	f000 f805 	bl	80100c0 <prvInitialiseNewQueue>
		{
			traceQUEUE_CREATE_FAILED( ucQueueType );
			mtCOVERAGE_TEST_MARKER();
		}

		return pxNewQueue;
 80100b6:	69bb      	ldr	r3, [r7, #24]
	}
 80100b8:	4618      	mov	r0, r3
 80100ba:	3720      	adds	r7, #32
 80100bc:	46bd      	mov	sp, r7
 80100be:	bd80      	pop	{r7, pc}

080100c0 <prvInitialiseNewQueue>:

#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
 80100c0:	b580      	push	{r7, lr}
 80100c2:	b084      	sub	sp, #16
 80100c4:	af00      	add	r7, sp, #0
 80100c6:	60f8      	str	r0, [r7, #12]
 80100c8:	60b9      	str	r1, [r7, #8]
 80100ca:	607a      	str	r2, [r7, #4]
 80100cc:	70fb      	strb	r3, [r7, #3]
	/* Remove compiler warnings about unused parameters should
	configUSE_TRACE_FACILITY not be set to 1. */
	( void ) ucQueueType;

	if( uxItemSize == ( UBaseType_t ) 0 )
 80100ce:	68bb      	ldr	r3, [r7, #8]
 80100d0:	2b00      	cmp	r3, #0
 80100d2:	d103      	bne.n	80100dc <prvInitialiseNewQueue+0x1c>
	{
		/* No RAM was allocated for the queue storage area, but PC head cannot
		be set to NULL because NULL is used as a key to say the queue is used as
		a mutex.  Therefore just set pcHead to point to the queue as a benign
		value that is known to be within the memory map. */
		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
 80100d4:	69bb      	ldr	r3, [r7, #24]
 80100d6:	69ba      	ldr	r2, [r7, #24]
 80100d8:	601a      	str	r2, [r3, #0]
 80100da:	e002      	b.n	80100e2 <prvInitialiseNewQueue+0x22>
	}
	else
	{
		/* Set the head to the start of the queue storage area. */
		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
 80100dc:	69bb      	ldr	r3, [r7, #24]
 80100de:	687a      	ldr	r2, [r7, #4]
 80100e0:	601a      	str	r2, [r3, #0]
	}

	/* Initialise the queue members as described where the queue type is
	defined. */
	pxNewQueue->uxLength = uxQueueLength;
 80100e2:	69bb      	ldr	r3, [r7, #24]
 80100e4:	68fa      	ldr	r2, [r7, #12]
 80100e6:	63da      	str	r2, [r3, #60]	@ 0x3c
	pxNewQueue->uxItemSize = uxItemSize;
 80100e8:	69bb      	ldr	r3, [r7, #24]
 80100ea:	68ba      	ldr	r2, [r7, #8]
 80100ec:	641a      	str	r2, [r3, #64]	@ 0x40
	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
 80100ee:	2101      	movs	r1, #1
 80100f0:	69b8      	ldr	r0, [r7, #24]
 80100f2:	f7ff fec3 	bl	800fe7c <xQueueGenericReset>

	#if ( configUSE_TRACE_FACILITY == 1 )
	{
		pxNewQueue->ucQueueType = ucQueueType;
 80100f6:	69bb      	ldr	r3, [r7, #24]
 80100f8:	78fa      	ldrb	r2, [r7, #3]
 80100fa:	f883 204c 	strb.w	r2, [r3, #76]	@ 0x4c
		pxNewQueue->pxQueueSetContainer = NULL;
	}
	#endif /* configUSE_QUEUE_SETS */

	traceQUEUE_CREATE( pxNewQueue );
}
 80100fe:	bf00      	nop
 8010100:	3710      	adds	r7, #16
 8010102:	46bd      	mov	sp, r7
 8010104:	bd80      	pop	{r7, pc}

08010106 <prvInitialiseMutex>:
/*-----------------------------------------------------------*/

#if( configUSE_MUTEXES == 1 )

	static void prvInitialiseMutex( Queue_t *pxNewQueue )
	{
 8010106:	b580      	push	{r7, lr}
 8010108:	b082      	sub	sp, #8
 801010a:	af00      	add	r7, sp, #0
 801010c:	6078      	str	r0, [r7, #4]
		if( pxNewQueue != NULL )
 801010e:	687b      	ldr	r3, [r7, #4]
 8010110:	2b00      	cmp	r3, #0
 8010112:	d00e      	beq.n	8010132 <prvInitialiseMutex+0x2c>
		{
			/* The queue create function will set all the queue structure members
			correctly for a generic queue, but this function is creating a
			mutex.  Overwrite those members that need to be set differently -
			in particular the information required for priority inheritance. */
			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
 8010114:	687b      	ldr	r3, [r7, #4]
 8010116:	2200      	movs	r2, #0
 8010118:	609a      	str	r2, [r3, #8]
			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
 801011a:	687b      	ldr	r3, [r7, #4]
 801011c:	2200      	movs	r2, #0
 801011e:	601a      	str	r2, [r3, #0]

			/* In case this is a recursive mutex. */
			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
 8010120:	687b      	ldr	r3, [r7, #4]
 8010122:	2200      	movs	r2, #0
 8010124:	60da      	str	r2, [r3, #12]

			traceCREATE_MUTEX( pxNewQueue );

			/* Start with the semaphore in the expected state. */
			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
 8010126:	2300      	movs	r3, #0
 8010128:	2200      	movs	r2, #0
 801012a:	2100      	movs	r1, #0
 801012c:	6878      	ldr	r0, [r7, #4]
 801012e:	f000 f8a3 	bl	8010278 <xQueueGenericSend>
		}
		else
		{
			traceCREATE_MUTEX_FAILED();
		}
	}
 8010132:	bf00      	nop
 8010134:	3708      	adds	r7, #8
 8010136:	46bd      	mov	sp, r7
 8010138:	bd80      	pop	{r7, pc}

0801013a <xQueueCreateMutex>:
/*-----------------------------------------------------------*/

#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )

	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
	{
 801013a:	b580      	push	{r7, lr}
 801013c:	b086      	sub	sp, #24
 801013e:	af00      	add	r7, sp, #0
 8010140:	4603      	mov	r3, r0
 8010142:	71fb      	strb	r3, [r7, #7]
	QueueHandle_t xNewQueue;
	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
 8010144:	2301      	movs	r3, #1
 8010146:	617b      	str	r3, [r7, #20]
 8010148:	2300      	movs	r3, #0
 801014a:	613b      	str	r3, [r7, #16]

		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
 801014c:	79fb      	ldrb	r3, [r7, #7]
 801014e:	461a      	mov	r2, r3
 8010150:	6939      	ldr	r1, [r7, #16]
 8010152:	6978      	ldr	r0, [r7, #20]
 8010154:	f7ff ff79 	bl	801004a <xQueueGenericCreate>
 8010158:	60f8      	str	r0, [r7, #12]
		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
 801015a:	68f8      	ldr	r0, [r7, #12]
 801015c:	f7ff ffd3 	bl	8010106 <prvInitialiseMutex>

		return xNewQueue;
 8010160:	68fb      	ldr	r3, [r7, #12]
	}
 8010162:	4618      	mov	r0, r3
 8010164:	3718      	adds	r7, #24
 8010166:	46bd      	mov	sp, r7
 8010168:	bd80      	pop	{r7, pc}

0801016a <xQueueCreateMutexStatic>:
/*-----------------------------------------------------------*/

#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )

	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
	{
 801016a:	b580      	push	{r7, lr}
 801016c:	b088      	sub	sp, #32
 801016e:	af02      	add	r7, sp, #8
 8010170:	4603      	mov	r3, r0
 8010172:	6039      	str	r1, [r7, #0]
 8010174:	71fb      	strb	r3, [r7, #7]
	QueueHandle_t xNewQueue;
	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
 8010176:	2301      	movs	r3, #1
 8010178:	617b      	str	r3, [r7, #20]
 801017a:	2300      	movs	r3, #0
 801017c:	613b      	str	r3, [r7, #16]

		/* Prevent compiler warnings about unused parameters if
		configUSE_TRACE_FACILITY does not equal 1. */
		( void ) ucQueueType;

		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
 801017e:	79fb      	ldrb	r3, [r7, #7]
 8010180:	9300      	str	r3, [sp, #0]
 8010182:	683b      	ldr	r3, [r7, #0]
 8010184:	2200      	movs	r2, #0
 8010186:	6939      	ldr	r1, [r7, #16]
 8010188:	6978      	ldr	r0, [r7, #20]
 801018a:	f7ff fee1 	bl	800ff50 <xQueueGenericCreateStatic>
 801018e:	60f8      	str	r0, [r7, #12]
		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
 8010190:	68f8      	ldr	r0, [r7, #12]
 8010192:	f7ff ffb8 	bl	8010106 <prvInitialiseMutex>

		return xNewQueue;
 8010196:	68fb      	ldr	r3, [r7, #12]
	}
 8010198:	4618      	mov	r0, r3
 801019a:	3718      	adds	r7, #24
 801019c:	46bd      	mov	sp, r7
 801019e:	bd80      	pop	{r7, pc}

080101a0 <xQueueGiveMutexRecursive>:
/*-----------------------------------------------------------*/

#if ( configUSE_RECURSIVE_MUTEXES == 1 )

	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
	{
 80101a0:	b590      	push	{r4, r7, lr}
 80101a2:	b087      	sub	sp, #28
 80101a4:	af00      	add	r7, sp, #0
 80101a6:	6078      	str	r0, [r7, #4]
	BaseType_t xReturn;
	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
 80101a8:	687b      	ldr	r3, [r7, #4]
 80101aa:	613b      	str	r3, [r7, #16]

		configASSERT( pxMutex );
 80101ac:	693b      	ldr	r3, [r7, #16]
 80101ae:	2b00      	cmp	r3, #0
 80101b0:	d10b      	bne.n	80101ca <xQueueGiveMutexRecursive+0x2a>
	__asm volatile
 80101b2:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80101b6:	f383 8811 	msr	BASEPRI, r3
 80101ba:	f3bf 8f6f 	isb	sy
 80101be:	f3bf 8f4f 	dsb	sy
 80101c2:	60fb      	str	r3, [r7, #12]
}
 80101c4:	bf00      	nop
 80101c6:	bf00      	nop
 80101c8:	e7fd      	b.n	80101c6 <xQueueGiveMutexRecursive+0x26>
		change outside of this task.  If this task does not hold the mutex then
		pxMutexHolder can never coincidentally equal the tasks handle, and as
		this is the only condition we are interested in it does not matter if
		pxMutexHolder is accessed simultaneously by another task.  Therefore no
		mutual exclusion is required to test the pxMutexHolder variable. */
		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
 80101ca:	693b      	ldr	r3, [r7, #16]
 80101cc:	689c      	ldr	r4, [r3, #8]
 80101ce:	f001 fe39 	bl	8011e44 <xTaskGetCurrentTaskHandle>
 80101d2:	4603      	mov	r3, r0
 80101d4:	429c      	cmp	r4, r3
 80101d6:	d111      	bne.n	80101fc <xQueueGiveMutexRecursive+0x5c>
			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
			the task handle, therefore no underflow check is required.  Also,
			uxRecursiveCallCount is only modified by the mutex holder, and as
			there can only be one, no mutual exclusion is required to modify the
			uxRecursiveCallCount member. */
			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
 80101d8:	693b      	ldr	r3, [r7, #16]
 80101da:	68db      	ldr	r3, [r3, #12]
 80101dc:	1e5a      	subs	r2, r3, #1
 80101de:	693b      	ldr	r3, [r7, #16]
 80101e0:	60da      	str	r2, [r3, #12]

			/* Has the recursive call count unwound to 0? */
			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
 80101e2:	693b      	ldr	r3, [r7, #16]
 80101e4:	68db      	ldr	r3, [r3, #12]
 80101e6:	2b00      	cmp	r3, #0
 80101e8:	d105      	bne.n	80101f6 <xQueueGiveMutexRecursive+0x56>
			{
				/* Return the mutex.  This will automatically unblock any other
				task that might be waiting to access the mutex. */
				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
 80101ea:	2300      	movs	r3, #0
 80101ec:	2200      	movs	r2, #0
 80101ee:	2100      	movs	r1, #0
 80101f0:	6938      	ldr	r0, [r7, #16]
 80101f2:	f000 f841 	bl	8010278 <xQueueGenericSend>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}

			xReturn = pdPASS;
 80101f6:	2301      	movs	r3, #1
 80101f8:	617b      	str	r3, [r7, #20]
 80101fa:	e001      	b.n	8010200 <xQueueGiveMutexRecursive+0x60>
		}
		else
		{
			/* The mutex cannot be given because the calling task is not the
			holder. */
			xReturn = pdFAIL;
 80101fc:	2300      	movs	r3, #0
 80101fe:	617b      	str	r3, [r7, #20]

			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
		}

		return xReturn;
 8010200:	697b      	ldr	r3, [r7, #20]
	}
 8010202:	4618      	mov	r0, r3
 8010204:	371c      	adds	r7, #28
 8010206:	46bd      	mov	sp, r7
 8010208:	bd90      	pop	{r4, r7, pc}

0801020a <xQueueTakeMutexRecursive>:
/*-----------------------------------------------------------*/

#if ( configUSE_RECURSIVE_MUTEXES == 1 )

	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
	{
 801020a:	b590      	push	{r4, r7, lr}
 801020c:	b087      	sub	sp, #28
 801020e:	af00      	add	r7, sp, #0
 8010210:	6078      	str	r0, [r7, #4]
 8010212:	6039      	str	r1, [r7, #0]
	BaseType_t xReturn;
	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
 8010214:	687b      	ldr	r3, [r7, #4]
 8010216:	613b      	str	r3, [r7, #16]

		configASSERT( pxMutex );
 8010218:	693b      	ldr	r3, [r7, #16]
 801021a:	2b00      	cmp	r3, #0
 801021c:	d10b      	bne.n	8010236 <xQueueTakeMutexRecursive+0x2c>
	__asm volatile
 801021e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010222:	f383 8811 	msr	BASEPRI, r3
 8010226:	f3bf 8f6f 	isb	sy
 801022a:	f3bf 8f4f 	dsb	sy
 801022e:	60fb      	str	r3, [r7, #12]
}
 8010230:	bf00      	nop
 8010232:	bf00      	nop
 8010234:	e7fd      	b.n	8010232 <xQueueTakeMutexRecursive+0x28>
		/* Comments regarding mutual exclusion as per those within
		xQueueGiveMutexRecursive(). */

		traceTAKE_MUTEX_RECURSIVE( pxMutex );

		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
 8010236:	693b      	ldr	r3, [r7, #16]
 8010238:	689c      	ldr	r4, [r3, #8]
 801023a:	f001 fe03 	bl	8011e44 <xTaskGetCurrentTaskHandle>
 801023e:	4603      	mov	r3, r0
 8010240:	429c      	cmp	r4, r3
 8010242:	d107      	bne.n	8010254 <xQueueTakeMutexRecursive+0x4a>
		{
			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
 8010244:	693b      	ldr	r3, [r7, #16]
 8010246:	68db      	ldr	r3, [r3, #12]
 8010248:	1c5a      	adds	r2, r3, #1
 801024a:	693b      	ldr	r3, [r7, #16]
 801024c:	60da      	str	r2, [r3, #12]
			xReturn = pdPASS;
 801024e:	2301      	movs	r3, #1
 8010250:	617b      	str	r3, [r7, #20]
 8010252:	e00c      	b.n	801026e <xQueueTakeMutexRecursive+0x64>
		}
		else
		{
			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
 8010254:	6839      	ldr	r1, [r7, #0]
 8010256:	6938      	ldr	r0, [r7, #16]
 8010258:	f000 fa90 	bl	801077c <xQueueSemaphoreTake>
 801025c:	6178      	str	r0, [r7, #20]

			/* pdPASS will only be returned if the mutex was successfully
			obtained.  The calling task may have entered the Blocked state
			before reaching here. */
			if( xReturn != pdFAIL )
 801025e:	697b      	ldr	r3, [r7, #20]
 8010260:	2b00      	cmp	r3, #0
 8010262:	d004      	beq.n	801026e <xQueueTakeMutexRecursive+0x64>
			{
				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
 8010264:	693b      	ldr	r3, [r7, #16]
 8010266:	68db      	ldr	r3, [r3, #12]
 8010268:	1c5a      	adds	r2, r3, #1
 801026a:	693b      	ldr	r3, [r7, #16]
 801026c:	60da      	str	r2, [r3, #12]
			{
				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
			}
		}

		return xReturn;
 801026e:	697b      	ldr	r3, [r7, #20]
	}
 8010270:	4618      	mov	r0, r3
 8010272:	371c      	adds	r7, #28
 8010274:	46bd      	mov	sp, r7
 8010276:	bd90      	pop	{r4, r7, pc}

08010278 <xQueueGenericSend>:

#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
 8010278:	b580      	push	{r7, lr}
 801027a:	b08e      	sub	sp, #56	@ 0x38
 801027c:	af00      	add	r7, sp, #0
 801027e:	60f8      	str	r0, [r7, #12]
 8010280:	60b9      	str	r1, [r7, #8]
 8010282:	607a      	str	r2, [r7, #4]
 8010284:	603b      	str	r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
 8010286:	2300      	movs	r3, #0
 8010288:	637b      	str	r3, [r7, #52]	@ 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 801028a:	68fb      	ldr	r3, [r7, #12]
 801028c:	633b      	str	r3, [r7, #48]	@ 0x30

	configASSERT( pxQueue );
 801028e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010290:	2b00      	cmp	r3, #0
 8010292:	d10b      	bne.n	80102ac <xQueueGenericSend+0x34>
	__asm volatile
 8010294:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010298:	f383 8811 	msr	BASEPRI, r3
 801029c:	f3bf 8f6f 	isb	sy
 80102a0:	f3bf 8f4f 	dsb	sy
 80102a4:	62bb      	str	r3, [r7, #40]	@ 0x28
}
 80102a6:	bf00      	nop
 80102a8:	bf00      	nop
 80102aa:	e7fd      	b.n	80102a8 <xQueueGenericSend+0x30>
	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 80102ac:	68bb      	ldr	r3, [r7, #8]
 80102ae:	2b00      	cmp	r3, #0
 80102b0:	d103      	bne.n	80102ba <xQueueGenericSend+0x42>
 80102b2:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80102b4:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80102b6:	2b00      	cmp	r3, #0
 80102b8:	d101      	bne.n	80102be <xQueueGenericSend+0x46>
 80102ba:	2301      	movs	r3, #1
 80102bc:	e000      	b.n	80102c0 <xQueueGenericSend+0x48>
 80102be:	2300      	movs	r3, #0
 80102c0:	2b00      	cmp	r3, #0
 80102c2:	d10b      	bne.n	80102dc <xQueueGenericSend+0x64>
	__asm volatile
 80102c4:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80102c8:	f383 8811 	msr	BASEPRI, r3
 80102cc:	f3bf 8f6f 	isb	sy
 80102d0:	f3bf 8f4f 	dsb	sy
 80102d4:	627b      	str	r3, [r7, #36]	@ 0x24
}
 80102d6:	bf00      	nop
 80102d8:	bf00      	nop
 80102da:	e7fd      	b.n	80102d8 <xQueueGenericSend+0x60>
	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 80102dc:	683b      	ldr	r3, [r7, #0]
 80102de:	2b02      	cmp	r3, #2
 80102e0:	d103      	bne.n	80102ea <xQueueGenericSend+0x72>
 80102e2:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80102e4:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80102e6:	2b01      	cmp	r3, #1
 80102e8:	d101      	bne.n	80102ee <xQueueGenericSend+0x76>
 80102ea:	2301      	movs	r3, #1
 80102ec:	e000      	b.n	80102f0 <xQueueGenericSend+0x78>
 80102ee:	2300      	movs	r3, #0
 80102f0:	2b00      	cmp	r3, #0
 80102f2:	d10b      	bne.n	801030c <xQueueGenericSend+0x94>
	__asm volatile
 80102f4:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80102f8:	f383 8811 	msr	BASEPRI, r3
 80102fc:	f3bf 8f6f 	isb	sy
 8010300:	f3bf 8f4f 	dsb	sy
 8010304:	623b      	str	r3, [r7, #32]
}
 8010306:	bf00      	nop
 8010308:	bf00      	nop
 801030a:	e7fd      	b.n	8010308 <xQueueGenericSend+0x90>
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 801030c:	f001 fdaa 	bl	8011e64 <xTaskGetSchedulerState>
 8010310:	4603      	mov	r3, r0
 8010312:	2b00      	cmp	r3, #0
 8010314:	d102      	bne.n	801031c <xQueueGenericSend+0xa4>
 8010316:	687b      	ldr	r3, [r7, #4]
 8010318:	2b00      	cmp	r3, #0
 801031a:	d101      	bne.n	8010320 <xQueueGenericSend+0xa8>
 801031c:	2301      	movs	r3, #1
 801031e:	e000      	b.n	8010322 <xQueueGenericSend+0xaa>
 8010320:	2300      	movs	r3, #0
 8010322:	2b00      	cmp	r3, #0
 8010324:	d10b      	bne.n	801033e <xQueueGenericSend+0xc6>
	__asm volatile
 8010326:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801032a:	f383 8811 	msr	BASEPRI, r3
 801032e:	f3bf 8f6f 	isb	sy
 8010332:	f3bf 8f4f 	dsb	sy
 8010336:	61fb      	str	r3, [r7, #28]
}
 8010338:	bf00      	nop
 801033a:	bf00      	nop
 801033c:	e7fd      	b.n	801033a <xQueueGenericSend+0xc2>
	/*lint -save -e904 This function relaxes the coding standard somewhat to
	allow return statements within the function itself.  This is done in the
	interest of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 801033e:	f002 fe2b 	bl	8012f98 <vPortEnterCritical>
		{
			/* Is there room on the queue now?  The running task must be the
			highest priority task wanting to access the queue.  If the head item
			in the queue is to be overwritten then it does not matter if the
			queue is full. */
			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 8010342:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010344:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 8010346:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010348:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 801034a:	429a      	cmp	r2, r3
 801034c:	d302      	bcc.n	8010354 <xQueueGenericSend+0xdc>
 801034e:	683b      	ldr	r3, [r7, #0]
 8010350:	2b02      	cmp	r3, #2
 8010352:	d129      	bne.n	80103a8 <xQueueGenericSend+0x130>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 8010354:	683a      	ldr	r2, [r7, #0]
 8010356:	68b9      	ldr	r1, [r7, #8]
 8010358:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 801035a:	f000 fbb9 	bl	8010ad0 <prvCopyDataToQueue>
 801035e:	62f8      	str	r0, [r7, #44]	@ 0x2c

					/* If there was a task waiting for data to arrive on the
					queue then unblock it now. */
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8010360:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010362:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8010364:	2b00      	cmp	r3, #0
 8010366:	d010      	beq.n	801038a <xQueueGenericSend+0x112>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8010368:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801036a:	3324      	adds	r3, #36	@ 0x24
 801036c:	4618      	mov	r0, r3
 801036e:	f001 fb7b 	bl	8011a68 <xTaskRemoveFromEventList>
 8010372:	4603      	mov	r3, r0
 8010374:	2b00      	cmp	r3, #0
 8010376:	d013      	beq.n	80103a0 <xQueueGenericSend+0x128>
						{
							/* The unblocked task has a priority higher than
							our own so yield immediately.  Yes it is ok to do
							this from within the critical section - the kernel
							takes care of that. */
							queueYIELD_IF_USING_PREEMPTION();
 8010378:	4b3f      	ldr	r3, [pc, #252]	@ (8010478 <xQueueGenericSend+0x200>)
 801037a:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 801037e:	601a      	str	r2, [r3, #0]
 8010380:	f3bf 8f4f 	dsb	sy
 8010384:	f3bf 8f6f 	isb	sy
 8010388:	e00a      	b.n	80103a0 <xQueueGenericSend+0x128>
						else
						{
							mtCOVERAGE_TEST_MARKER();
						}
					}
					else if( xYieldRequired != pdFALSE )
 801038a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 801038c:	2b00      	cmp	r3, #0
 801038e:	d007      	beq.n	80103a0 <xQueueGenericSend+0x128>
					{
						/* This path is a special case that will only get
						executed if the task was holding multiple mutexes and
						the mutexes were given back in an order that is
						different to that in which they were taken. */
						queueYIELD_IF_USING_PREEMPTION();
 8010390:	4b39      	ldr	r3, [pc, #228]	@ (8010478 <xQueueGenericSend+0x200>)
 8010392:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8010396:	601a      	str	r2, [r3, #0]
 8010398:	f3bf 8f4f 	dsb	sy
 801039c:	f3bf 8f6f 	isb	sy
						mtCOVERAGE_TEST_MARKER();
					}
				}
				#endif /* configUSE_QUEUE_SETS */

				taskEXIT_CRITICAL();
 80103a0:	f002 fe2c 	bl	8012ffc <vPortExitCritical>
				return pdPASS;
 80103a4:	2301      	movs	r3, #1
 80103a6:	e063      	b.n	8010470 <xQueueGenericSend+0x1f8>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 80103a8:	687b      	ldr	r3, [r7, #4]
 80103aa:	2b00      	cmp	r3, #0
 80103ac:	d103      	bne.n	80103b6 <xQueueGenericSend+0x13e>
				{
					/* The queue was full and no block time is specified (or
					the block time has expired) so leave now. */
					taskEXIT_CRITICAL();
 80103ae:	f002 fe25 	bl	8012ffc <vPortExitCritical>

					/* Return to the original privilege level before exiting
					the function. */
					traceQUEUE_SEND_FAILED( pxQueue );
					return errQUEUE_FULL;
 80103b2:	2300      	movs	r3, #0
 80103b4:	e05c      	b.n	8010470 <xQueueGenericSend+0x1f8>
				}
				else if( xEntryTimeSet == pdFALSE )
 80103b6:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80103b8:	2b00      	cmp	r3, #0
 80103ba:	d106      	bne.n	80103ca <xQueueGenericSend+0x152>
				{
					/* The queue was full and a block time was specified so
					configure the timeout structure. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 80103bc:	f107 0314 	add.w	r3, r7, #20
 80103c0:	4618      	mov	r0, r3
 80103c2:	f001 fbdd 	bl	8011b80 <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 80103c6:	2301      	movs	r3, #1
 80103c8:	637b      	str	r3, [r7, #52]	@ 0x34
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 80103ca:	f002 fe17 	bl	8012ffc <vPortExitCritical>

		/* Interrupts and other tasks can send to and receive from the queue
		now the critical section has been exited. */

		vTaskSuspendAll();
 80103ce:	f001 f90f 	bl	80115f0 <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 80103d2:	f002 fde1 	bl	8012f98 <vPortEnterCritical>
 80103d6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80103d8:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 80103dc:	b25b      	sxtb	r3, r3
 80103de:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80103e2:	d103      	bne.n	80103ec <xQueueGenericSend+0x174>
 80103e4:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80103e6:	2200      	movs	r2, #0
 80103e8:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 80103ec:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80103ee:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 80103f2:	b25b      	sxtb	r3, r3
 80103f4:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80103f8:	d103      	bne.n	8010402 <xQueueGenericSend+0x18a>
 80103fa:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80103fc:	2200      	movs	r2, #0
 80103fe:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 8010402:	f002 fdfb 	bl	8012ffc <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 8010406:	1d3a      	adds	r2, r7, #4
 8010408:	f107 0314 	add.w	r3, r7, #20
 801040c:	4611      	mov	r1, r2
 801040e:	4618      	mov	r0, r3
 8010410:	f001 fbcc 	bl	8011bac <xTaskCheckForTimeOut>
 8010414:	4603      	mov	r3, r0
 8010416:	2b00      	cmp	r3, #0
 8010418:	d124      	bne.n	8010464 <xQueueGenericSend+0x1ec>
		{
			if( prvIsQueueFull( pxQueue ) != pdFALSE )
 801041a:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 801041c:	f000 fc50 	bl	8010cc0 <prvIsQueueFull>
 8010420:	4603      	mov	r3, r0
 8010422:	2b00      	cmp	r3, #0
 8010424:	d018      	beq.n	8010458 <xQueueGenericSend+0x1e0>
			{
				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
 8010426:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010428:	3310      	adds	r3, #16
 801042a:	687a      	ldr	r2, [r7, #4]
 801042c:	4611      	mov	r1, r2
 801042e:	4618      	mov	r0, r3
 8010430:	f001 fac8 	bl	80119c4 <vTaskPlaceOnEventList>
				/* Unlocking the queue means queue events can effect the
				event list.  It is possible that interrupts occurring now
				remove this task from the event list again - but as the
				scheduler is suspended the task will go onto the pending
				ready last instead of the actual ready list. */
				prvUnlockQueue( pxQueue );
 8010434:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8010436:	f000 fbdb 	bl	8010bf0 <prvUnlockQueue>
				/* Resuming the scheduler will move tasks from the pending
				ready list into the ready list - so it is feasible that this
				task is already in a ready list before it yields - in which
				case the yield will not cause a context switch unless there
				is also a higher priority task in the pending ready list. */
				if( xTaskResumeAll() == pdFALSE )
 801043a:	f001 f8e7 	bl	801160c <xTaskResumeAll>
 801043e:	4603      	mov	r3, r0
 8010440:	2b00      	cmp	r3, #0
 8010442:	f47f af7c 	bne.w	801033e <xQueueGenericSend+0xc6>
				{
					portYIELD_WITHIN_API();
 8010446:	4b0c      	ldr	r3, [pc, #48]	@ (8010478 <xQueueGenericSend+0x200>)
 8010448:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 801044c:	601a      	str	r2, [r3, #0]
 801044e:	f3bf 8f4f 	dsb	sy
 8010452:	f3bf 8f6f 	isb	sy
 8010456:	e772      	b.n	801033e <xQueueGenericSend+0xc6>
				}
			}
			else
			{
				/* Try again. */
				prvUnlockQueue( pxQueue );
 8010458:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 801045a:	f000 fbc9 	bl	8010bf0 <prvUnlockQueue>
				( void ) xTaskResumeAll();
 801045e:	f001 f8d5 	bl	801160c <xTaskResumeAll>
 8010462:	e76c      	b.n	801033e <xQueueGenericSend+0xc6>
			}
		}
		else
		{
			/* The timeout has expired. */
			prvUnlockQueue( pxQueue );
 8010464:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8010466:	f000 fbc3 	bl	8010bf0 <prvUnlockQueue>
			( void ) xTaskResumeAll();
 801046a:	f001 f8cf 	bl	801160c <xTaskResumeAll>

			traceQUEUE_SEND_FAILED( pxQueue );
			return errQUEUE_FULL;
 801046e:	2300      	movs	r3, #0
		}
	} /*lint -restore */
}
 8010470:	4618      	mov	r0, r3
 8010472:	3738      	adds	r7, #56	@ 0x38
 8010474:	46bd      	mov	sp, r7
 8010476:	bd80      	pop	{r7, pc}
 8010478:	e000ed04 	.word	0xe000ed04

0801047c <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
 801047c:	b580      	push	{r7, lr}
 801047e:	b090      	sub	sp, #64	@ 0x40
 8010480:	af00      	add	r7, sp, #0
 8010482:	60f8      	str	r0, [r7, #12]
 8010484:	60b9      	str	r1, [r7, #8]
 8010486:	607a      	str	r2, [r7, #4]
 8010488:	603b      	str	r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
 801048a:	68fb      	ldr	r3, [r7, #12]
 801048c:	63bb      	str	r3, [r7, #56]	@ 0x38

	configASSERT( pxQueue );
 801048e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8010490:	2b00      	cmp	r3, #0
 8010492:	d10b      	bne.n	80104ac <xQueueGenericSendFromISR+0x30>
	__asm volatile
 8010494:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010498:	f383 8811 	msr	BASEPRI, r3
 801049c:	f3bf 8f6f 	isb	sy
 80104a0:	f3bf 8f4f 	dsb	sy
 80104a4:	62bb      	str	r3, [r7, #40]	@ 0x28
}
 80104a6:	bf00      	nop
 80104a8:	bf00      	nop
 80104aa:	e7fd      	b.n	80104a8 <xQueueGenericSendFromISR+0x2c>
	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 80104ac:	68bb      	ldr	r3, [r7, #8]
 80104ae:	2b00      	cmp	r3, #0
 80104b0:	d103      	bne.n	80104ba <xQueueGenericSendFromISR+0x3e>
 80104b2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80104b4:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80104b6:	2b00      	cmp	r3, #0
 80104b8:	d101      	bne.n	80104be <xQueueGenericSendFromISR+0x42>
 80104ba:	2301      	movs	r3, #1
 80104bc:	e000      	b.n	80104c0 <xQueueGenericSendFromISR+0x44>
 80104be:	2300      	movs	r3, #0
 80104c0:	2b00      	cmp	r3, #0
 80104c2:	d10b      	bne.n	80104dc <xQueueGenericSendFromISR+0x60>
	__asm volatile
 80104c4:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80104c8:	f383 8811 	msr	BASEPRI, r3
 80104cc:	f3bf 8f6f 	isb	sy
 80104d0:	f3bf 8f4f 	dsb	sy
 80104d4:	627b      	str	r3, [r7, #36]	@ 0x24
}
 80104d6:	bf00      	nop
 80104d8:	bf00      	nop
 80104da:	e7fd      	b.n	80104d8 <xQueueGenericSendFromISR+0x5c>
	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 80104dc:	683b      	ldr	r3, [r7, #0]
 80104de:	2b02      	cmp	r3, #2
 80104e0:	d103      	bne.n	80104ea <xQueueGenericSendFromISR+0x6e>
 80104e2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80104e4:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80104e6:	2b01      	cmp	r3, #1
 80104e8:	d101      	bne.n	80104ee <xQueueGenericSendFromISR+0x72>
 80104ea:	2301      	movs	r3, #1
 80104ec:	e000      	b.n	80104f0 <xQueueGenericSendFromISR+0x74>
 80104ee:	2300      	movs	r3, #0
 80104f0:	2b00      	cmp	r3, #0
 80104f2:	d10b      	bne.n	801050c <xQueueGenericSendFromISR+0x90>
	__asm volatile
 80104f4:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80104f8:	f383 8811 	msr	BASEPRI, r3
 80104fc:	f3bf 8f6f 	isb	sy
 8010500:	f3bf 8f4f 	dsb	sy
 8010504:	623b      	str	r3, [r7, #32]
}
 8010506:	bf00      	nop
 8010508:	bf00      	nop
 801050a:	e7fd      	b.n	8010508 <xQueueGenericSendFromISR+0x8c>
	that have been assigned a priority at or (logically) below the maximum
	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
	safe API to ensure interrupt entry is as fast and as simple as possible.
	More information (albeit Cortex-M specific) is provided on the following
	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 801050c:	f002 fe24 	bl	8013158 <vPortValidateInterruptPriority>

portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;

	__asm volatile
 8010510:	f3ef 8211 	mrs	r2, BASEPRI
 8010514:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010518:	f383 8811 	msr	BASEPRI, r3
 801051c:	f3bf 8f6f 	isb	sy
 8010520:	f3bf 8f4f 	dsb	sy
 8010524:	61fa      	str	r2, [r7, #28]
 8010526:	61bb      	str	r3, [r7, #24]
		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
	);

	/* This return will not be reached but is necessary to prevent compiler
	warnings. */
	return ulOriginalBASEPRI;
 8010528:	69fb      	ldr	r3, [r7, #28]
	/* Similar to xQueueGenericSend, except without blocking if there is no room
	in the queue.  Also don't directly wake a task that was blocked on a queue
	read, instead return a flag to say whether a context switch is required or
	not (i.e. has a task with a higher priority than us been woken by this
	post). */
	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 801052a:	637b      	str	r3, [r7, #52]	@ 0x34
	{
		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 801052c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 801052e:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 8010530:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8010532:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8010534:	429a      	cmp	r2, r3
 8010536:	d302      	bcc.n	801053e <xQueueGenericSendFromISR+0xc2>
 8010538:	683b      	ldr	r3, [r7, #0]
 801053a:	2b02      	cmp	r3, #2
 801053c:	d12f      	bne.n	801059e <xQueueGenericSendFromISR+0x122>
		{
			const int8_t cTxLock = pxQueue->cTxLock;
 801053e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8010540:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8010544:	f887 3033 	strb.w	r3, [r7, #51]	@ 0x33
			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
 8010548:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 801054a:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 801054c:	62fb      	str	r3, [r7, #44]	@ 0x2c
			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
			in a task disinheriting a priority and prvCopyDataToQueue() can be
			called here even though the disinherit function does not check if
			the scheduler is suspended before accessing the ready lists. */
			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 801054e:	683a      	ldr	r2, [r7, #0]
 8010550:	68b9      	ldr	r1, [r7, #8]
 8010552:	6bb8      	ldr	r0, [r7, #56]	@ 0x38
 8010554:	f000 fabc 	bl	8010ad0 <prvCopyDataToQueue>

			/* The event list is not altered if the queue is locked.  This will
			be done when the queue is unlocked later. */
			if( cTxLock == queueUNLOCKED )
 8010558:	f997 3033 	ldrsb.w	r3, [r7, #51]	@ 0x33
 801055c:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8010560:	d112      	bne.n	8010588 <xQueueGenericSendFromISR+0x10c>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8010562:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8010564:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8010566:	2b00      	cmp	r3, #0
 8010568:	d016      	beq.n	8010598 <xQueueGenericSendFromISR+0x11c>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 801056a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 801056c:	3324      	adds	r3, #36	@ 0x24
 801056e:	4618      	mov	r0, r3
 8010570:	f001 fa7a 	bl	8011a68 <xTaskRemoveFromEventList>
 8010574:	4603      	mov	r3, r0
 8010576:	2b00      	cmp	r3, #0
 8010578:	d00e      	beq.n	8010598 <xQueueGenericSendFromISR+0x11c>
						{
							/* The task waiting has a higher priority so record that a
							context	switch is required. */
							if( pxHigherPriorityTaskWoken != NULL )
 801057a:	687b      	ldr	r3, [r7, #4]
 801057c:	2b00      	cmp	r3, #0
 801057e:	d00b      	beq.n	8010598 <xQueueGenericSendFromISR+0x11c>
							{
								*pxHigherPriorityTaskWoken = pdTRUE;
 8010580:	687b      	ldr	r3, [r7, #4]
 8010582:	2201      	movs	r2, #1
 8010584:	601a      	str	r2, [r3, #0]
 8010586:	e007      	b.n	8010598 <xQueueGenericSendFromISR+0x11c>
			}
			else
			{
				/* Increment the lock count so the task that unlocks the queue
				knows that data was posted while it was locked. */
				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
 8010588:	f897 3033 	ldrb.w	r3, [r7, #51]	@ 0x33
 801058c:	3301      	adds	r3, #1
 801058e:	b2db      	uxtb	r3, r3
 8010590:	b25a      	sxtb	r2, r3
 8010592:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8010594:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
			}

			xReturn = pdPASS;
 8010598:	2301      	movs	r3, #1
 801059a:	63fb      	str	r3, [r7, #60]	@ 0x3c
		{
 801059c:	e001      	b.n	80105a2 <xQueueGenericSendFromISR+0x126>
		}
		else
		{
			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
			xReturn = errQUEUE_FULL;
 801059e:	2300      	movs	r3, #0
 80105a0:	63fb      	str	r3, [r7, #60]	@ 0x3c
 80105a2:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80105a4:	617b      	str	r3, [r7, #20]
}
/*-----------------------------------------------------------*/

portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
	__asm volatile
 80105a6:	697b      	ldr	r3, [r7, #20]
 80105a8:	f383 8811 	msr	BASEPRI, r3
	(
		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
	);
}
 80105ac:	bf00      	nop
		}
	}
	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

	return xReturn;
 80105ae:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
}
 80105b0:	4618      	mov	r0, r3
 80105b2:	3740      	adds	r7, #64	@ 0x40
 80105b4:	46bd      	mov	sp, r7
 80105b6:	bd80      	pop	{r7, pc}

080105b8 <xQueueReceive>:
	return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
 80105b8:	b580      	push	{r7, lr}
 80105ba:	b08c      	sub	sp, #48	@ 0x30
 80105bc:	af00      	add	r7, sp, #0
 80105be:	60f8      	str	r0, [r7, #12]
 80105c0:	60b9      	str	r1, [r7, #8]
 80105c2:	607a      	str	r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
 80105c4:	2300      	movs	r3, #0
 80105c6:	62fb      	str	r3, [r7, #44]	@ 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 80105c8:	68fb      	ldr	r3, [r7, #12]
 80105ca:	62bb      	str	r3, [r7, #40]	@ 0x28

	/* Check the pointer is not NULL. */
	configASSERT( ( pxQueue ) );
 80105cc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80105ce:	2b00      	cmp	r3, #0
 80105d0:	d10b      	bne.n	80105ea <xQueueReceive+0x32>
	__asm volatile
 80105d2:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80105d6:	f383 8811 	msr	BASEPRI, r3
 80105da:	f3bf 8f6f 	isb	sy
 80105de:	f3bf 8f4f 	dsb	sy
 80105e2:	623b      	str	r3, [r7, #32]
}
 80105e4:	bf00      	nop
 80105e6:	bf00      	nop
 80105e8:	e7fd      	b.n	80105e6 <xQueueReceive+0x2e>

	/* The buffer into which data is received can only be NULL if the data size
	is zero (so no data is copied into the buffer. */
	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
 80105ea:	68bb      	ldr	r3, [r7, #8]
 80105ec:	2b00      	cmp	r3, #0
 80105ee:	d103      	bne.n	80105f8 <xQueueReceive+0x40>
 80105f0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80105f2:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80105f4:	2b00      	cmp	r3, #0
 80105f6:	d101      	bne.n	80105fc <xQueueReceive+0x44>
 80105f8:	2301      	movs	r3, #1
 80105fa:	e000      	b.n	80105fe <xQueueReceive+0x46>
 80105fc:	2300      	movs	r3, #0
 80105fe:	2b00      	cmp	r3, #0
 8010600:	d10b      	bne.n	801061a <xQueueReceive+0x62>
	__asm volatile
 8010602:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010606:	f383 8811 	msr	BASEPRI, r3
 801060a:	f3bf 8f6f 	isb	sy
 801060e:	f3bf 8f4f 	dsb	sy
 8010612:	61fb      	str	r3, [r7, #28]
}
 8010614:	bf00      	nop
 8010616:	bf00      	nop
 8010618:	e7fd      	b.n	8010616 <xQueueReceive+0x5e>

	/* Cannot block if the scheduler is suspended. */
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 801061a:	f001 fc23 	bl	8011e64 <xTaskGetSchedulerState>
 801061e:	4603      	mov	r3, r0
 8010620:	2b00      	cmp	r3, #0
 8010622:	d102      	bne.n	801062a <xQueueReceive+0x72>
 8010624:	687b      	ldr	r3, [r7, #4]
 8010626:	2b00      	cmp	r3, #0
 8010628:	d101      	bne.n	801062e <xQueueReceive+0x76>
 801062a:	2301      	movs	r3, #1
 801062c:	e000      	b.n	8010630 <xQueueReceive+0x78>
 801062e:	2300      	movs	r3, #0
 8010630:	2b00      	cmp	r3, #0
 8010632:	d10b      	bne.n	801064c <xQueueReceive+0x94>
	__asm volatile
 8010634:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010638:	f383 8811 	msr	BASEPRI, r3
 801063c:	f3bf 8f6f 	isb	sy
 8010640:	f3bf 8f4f 	dsb	sy
 8010644:	61bb      	str	r3, [r7, #24]
}
 8010646:	bf00      	nop
 8010648:	bf00      	nop
 801064a:	e7fd      	b.n	8010648 <xQueueReceive+0x90>
	/*lint -save -e904  This function relaxes the coding standard somewhat to
	allow return statements within the function itself.  This is done in the
	interest of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 801064c:	f002 fca4 	bl	8012f98 <vPortEnterCritical>
		{
			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 8010650:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8010652:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8010654:	627b      	str	r3, [r7, #36]	@ 0x24

			/* Is there data in the queue now?  To be running the calling task
			must be the highest priority task wanting to access the queue. */
			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8010656:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8010658:	2b00      	cmp	r3, #0
 801065a:	d01f      	beq.n	801069c <xQueueReceive+0xe4>
			{
				/* Data available, remove one item. */
				prvCopyDataFromQueue( pxQueue, pvBuffer );
 801065c:	68b9      	ldr	r1, [r7, #8]
 801065e:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8010660:	f000 faa0 	bl	8010ba4 <prvCopyDataFromQueue>
				traceQUEUE_RECEIVE( pxQueue );
				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
 8010664:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8010666:	1e5a      	subs	r2, r3, #1
 8010668:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 801066a:	639a      	str	r2, [r3, #56]	@ 0x38

				/* There is now space in the queue, were any tasks waiting to
				post to the queue?  If so, unblock the highest priority waiting
				task. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 801066c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 801066e:	691b      	ldr	r3, [r3, #16]
 8010670:	2b00      	cmp	r3, #0
 8010672:	d00f      	beq.n	8010694 <xQueueReceive+0xdc>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8010674:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8010676:	3310      	adds	r3, #16
 8010678:	4618      	mov	r0, r3
 801067a:	f001 f9f5 	bl	8011a68 <xTaskRemoveFromEventList>
 801067e:	4603      	mov	r3, r0
 8010680:	2b00      	cmp	r3, #0
 8010682:	d007      	beq.n	8010694 <xQueueReceive+0xdc>
					{
						queueYIELD_IF_USING_PREEMPTION();
 8010684:	4b3c      	ldr	r3, [pc, #240]	@ (8010778 <xQueueReceive+0x1c0>)
 8010686:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 801068a:	601a      	str	r2, [r3, #0]
 801068c:	f3bf 8f4f 	dsb	sy
 8010690:	f3bf 8f6f 	isb	sy
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				taskEXIT_CRITICAL();
 8010694:	f002 fcb2 	bl	8012ffc <vPortExitCritical>
				return pdPASS;
 8010698:	2301      	movs	r3, #1
 801069a:	e069      	b.n	8010770 <xQueueReceive+0x1b8>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 801069c:	687b      	ldr	r3, [r7, #4]
 801069e:	2b00      	cmp	r3, #0
 80106a0:	d103      	bne.n	80106aa <xQueueReceive+0xf2>
				{
					/* The queue was empty and no block time is specified (or
					the block time has expired) so leave now. */
					taskEXIT_CRITICAL();
 80106a2:	f002 fcab 	bl	8012ffc <vPortExitCritical>
					traceQUEUE_RECEIVE_FAILED( pxQueue );
					return errQUEUE_EMPTY;
 80106a6:	2300      	movs	r3, #0
 80106a8:	e062      	b.n	8010770 <xQueueReceive+0x1b8>
				}
				else if( xEntryTimeSet == pdFALSE )
 80106aa:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80106ac:	2b00      	cmp	r3, #0
 80106ae:	d106      	bne.n	80106be <xQueueReceive+0x106>
				{
					/* The queue was empty and a block time was specified so
					configure the timeout structure. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 80106b0:	f107 0310 	add.w	r3, r7, #16
 80106b4:	4618      	mov	r0, r3
 80106b6:	f001 fa63 	bl	8011b80 <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 80106ba:	2301      	movs	r3, #1
 80106bc:	62fb      	str	r3, [r7, #44]	@ 0x2c
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 80106be:	f002 fc9d 	bl	8012ffc <vPortExitCritical>

		/* Interrupts and other tasks can send to and receive from the queue
		now the critical section has been exited. */

		vTaskSuspendAll();
 80106c2:	f000 ff95 	bl	80115f0 <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 80106c6:	f002 fc67 	bl	8012f98 <vPortEnterCritical>
 80106ca:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80106cc:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 80106d0:	b25b      	sxtb	r3, r3
 80106d2:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80106d6:	d103      	bne.n	80106e0 <xQueueReceive+0x128>
 80106d8:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80106da:	2200      	movs	r2, #0
 80106dc:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 80106e0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80106e2:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 80106e6:	b25b      	sxtb	r3, r3
 80106e8:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80106ec:	d103      	bne.n	80106f6 <xQueueReceive+0x13e>
 80106ee:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80106f0:	2200      	movs	r2, #0
 80106f2:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 80106f6:	f002 fc81 	bl	8012ffc <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 80106fa:	1d3a      	adds	r2, r7, #4
 80106fc:	f107 0310 	add.w	r3, r7, #16
 8010700:	4611      	mov	r1, r2
 8010702:	4618      	mov	r0, r3
 8010704:	f001 fa52 	bl	8011bac <xTaskCheckForTimeOut>
 8010708:	4603      	mov	r3, r0
 801070a:	2b00      	cmp	r3, #0
 801070c:	d123      	bne.n	8010756 <xQueueReceive+0x19e>
		{
			/* The timeout has not expired.  If the queue is still empty place
			the task on the list of tasks waiting to receive from the queue. */
			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 801070e:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8010710:	f000 fac0 	bl	8010c94 <prvIsQueueEmpty>
 8010714:	4603      	mov	r3, r0
 8010716:	2b00      	cmp	r3, #0
 8010718:	d017      	beq.n	801074a <xQueueReceive+0x192>
			{
				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
 801071a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 801071c:	3324      	adds	r3, #36	@ 0x24
 801071e:	687a      	ldr	r2, [r7, #4]
 8010720:	4611      	mov	r1, r2
 8010722:	4618      	mov	r0, r3
 8010724:	f001 f94e 	bl	80119c4 <vTaskPlaceOnEventList>
				prvUnlockQueue( pxQueue );
 8010728:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 801072a:	f000 fa61 	bl	8010bf0 <prvUnlockQueue>
				if( xTaskResumeAll() == pdFALSE )
 801072e:	f000 ff6d 	bl	801160c <xTaskResumeAll>
 8010732:	4603      	mov	r3, r0
 8010734:	2b00      	cmp	r3, #0
 8010736:	d189      	bne.n	801064c <xQueueReceive+0x94>
				{
					portYIELD_WITHIN_API();
 8010738:	4b0f      	ldr	r3, [pc, #60]	@ (8010778 <xQueueReceive+0x1c0>)
 801073a:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 801073e:	601a      	str	r2, [r3, #0]
 8010740:	f3bf 8f4f 	dsb	sy
 8010744:	f3bf 8f6f 	isb	sy
 8010748:	e780      	b.n	801064c <xQueueReceive+0x94>
			}
			else
			{
				/* The queue contains data again.  Loop back to try and read the
				data. */
				prvUnlockQueue( pxQueue );
 801074a:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 801074c:	f000 fa50 	bl	8010bf0 <prvUnlockQueue>
				( void ) xTaskResumeAll();
 8010750:	f000 ff5c 	bl	801160c <xTaskResumeAll>
 8010754:	e77a      	b.n	801064c <xQueueReceive+0x94>
		}
		else
		{
			/* Timed out.  If there is no data in the queue exit, otherwise loop
			back and attempt to read the data. */
			prvUnlockQueue( pxQueue );
 8010756:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8010758:	f000 fa4a 	bl	8010bf0 <prvUnlockQueue>
			( void ) xTaskResumeAll();
 801075c:	f000 ff56 	bl	801160c <xTaskResumeAll>

			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 8010760:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8010762:	f000 fa97 	bl	8010c94 <prvIsQueueEmpty>
 8010766:	4603      	mov	r3, r0
 8010768:	2b00      	cmp	r3, #0
 801076a:	f43f af6f 	beq.w	801064c <xQueueReceive+0x94>
			{
				traceQUEUE_RECEIVE_FAILED( pxQueue );
				return errQUEUE_EMPTY;
 801076e:	2300      	movs	r3, #0
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	} /*lint -restore */
}
 8010770:	4618      	mov	r0, r3
 8010772:	3730      	adds	r7, #48	@ 0x30
 8010774:	46bd      	mov	sp, r7
 8010776:	bd80      	pop	{r7, pc}
 8010778:	e000ed04 	.word	0xe000ed04

0801077c <xQueueSemaphoreTake>:
/*-----------------------------------------------------------*/

BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
{
 801077c:	b580      	push	{r7, lr}
 801077e:	b08e      	sub	sp, #56	@ 0x38
 8010780:	af00      	add	r7, sp, #0
 8010782:	6078      	str	r0, [r7, #4]
 8010784:	6039      	str	r1, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE;
 8010786:	2300      	movs	r3, #0
 8010788:	637b      	str	r3, [r7, #52]	@ 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 801078a:	687b      	ldr	r3, [r7, #4]
 801078c:	62fb      	str	r3, [r7, #44]	@ 0x2c

#if( configUSE_MUTEXES == 1 )
	BaseType_t xInheritanceOccurred = pdFALSE;
 801078e:	2300      	movs	r3, #0
 8010790:	633b      	str	r3, [r7, #48]	@ 0x30
#endif

	/* Check the queue pointer is not NULL. */
	configASSERT( ( pxQueue ) );
 8010792:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010794:	2b00      	cmp	r3, #0
 8010796:	d10b      	bne.n	80107b0 <xQueueSemaphoreTake+0x34>
	__asm volatile
 8010798:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801079c:	f383 8811 	msr	BASEPRI, r3
 80107a0:	f3bf 8f6f 	isb	sy
 80107a4:	f3bf 8f4f 	dsb	sy
 80107a8:	623b      	str	r3, [r7, #32]
}
 80107aa:	bf00      	nop
 80107ac:	bf00      	nop
 80107ae:	e7fd      	b.n	80107ac <xQueueSemaphoreTake+0x30>

	/* Check this really is a semaphore, in which case the item size will be
	0. */
	configASSERT( pxQueue->uxItemSize == 0 );
 80107b0:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80107b2:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80107b4:	2b00      	cmp	r3, #0
 80107b6:	d00b      	beq.n	80107d0 <xQueueSemaphoreTake+0x54>
	__asm volatile
 80107b8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80107bc:	f383 8811 	msr	BASEPRI, r3
 80107c0:	f3bf 8f6f 	isb	sy
 80107c4:	f3bf 8f4f 	dsb	sy
 80107c8:	61fb      	str	r3, [r7, #28]
}
 80107ca:	bf00      	nop
 80107cc:	bf00      	nop
 80107ce:	e7fd      	b.n	80107cc <xQueueSemaphoreTake+0x50>

	/* Cannot block if the scheduler is suspended. */
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 80107d0:	f001 fb48 	bl	8011e64 <xTaskGetSchedulerState>
 80107d4:	4603      	mov	r3, r0
 80107d6:	2b00      	cmp	r3, #0
 80107d8:	d102      	bne.n	80107e0 <xQueueSemaphoreTake+0x64>
 80107da:	683b      	ldr	r3, [r7, #0]
 80107dc:	2b00      	cmp	r3, #0
 80107de:	d101      	bne.n	80107e4 <xQueueSemaphoreTake+0x68>
 80107e0:	2301      	movs	r3, #1
 80107e2:	e000      	b.n	80107e6 <xQueueSemaphoreTake+0x6a>
 80107e4:	2300      	movs	r3, #0
 80107e6:	2b00      	cmp	r3, #0
 80107e8:	d10b      	bne.n	8010802 <xQueueSemaphoreTake+0x86>
	__asm volatile
 80107ea:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80107ee:	f383 8811 	msr	BASEPRI, r3
 80107f2:	f3bf 8f6f 	isb	sy
 80107f6:	f3bf 8f4f 	dsb	sy
 80107fa:	61bb      	str	r3, [r7, #24]
}
 80107fc:	bf00      	nop
 80107fe:	bf00      	nop
 8010800:	e7fd      	b.n	80107fe <xQueueSemaphoreTake+0x82>
	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
	statements within the function itself.  This is done in the interest
	of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 8010802:	f002 fbc9 	bl	8012f98 <vPortEnterCritical>
		{
			/* Semaphores are queues with an item size of 0, and where the
			number of messages in the queue is the semaphore's count value. */
			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
 8010806:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010808:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 801080a:	62bb      	str	r3, [r7, #40]	@ 0x28

			/* Is there data in the queue now?  To be running the calling task
			must be the highest priority task wanting to access the queue. */
			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
 801080c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 801080e:	2b00      	cmp	r3, #0
 8010810:	d024      	beq.n	801085c <xQueueSemaphoreTake+0xe0>
			{
				traceQUEUE_RECEIVE( pxQueue );

				/* Semaphores are queues with a data size of zero and where the
				messages waiting is the semaphore's count.  Reduce the count. */
				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
 8010812:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8010814:	1e5a      	subs	r2, r3, #1
 8010816:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010818:	639a      	str	r2, [r3, #56]	@ 0x38

				#if ( configUSE_MUTEXES == 1 )
				{
					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 801081a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 801081c:	681b      	ldr	r3, [r3, #0]
 801081e:	2b00      	cmp	r3, #0
 8010820:	d104      	bne.n	801082c <xQueueSemaphoreTake+0xb0>
					{
						/* Record the information required to implement
						priority inheritance should it become necessary. */
						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
 8010822:	f001 fc99 	bl	8012158 <pvTaskIncrementMutexHeldCount>
 8010826:	4602      	mov	r2, r0
 8010828:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 801082a:	609a      	str	r2, [r3, #8]
				}
				#endif /* configUSE_MUTEXES */

				/* Check to see if other tasks are blocked waiting to give the
				semaphore, and if so, unblock the highest priority such task. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 801082c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 801082e:	691b      	ldr	r3, [r3, #16]
 8010830:	2b00      	cmp	r3, #0
 8010832:	d00f      	beq.n	8010854 <xQueueSemaphoreTake+0xd8>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8010834:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010836:	3310      	adds	r3, #16
 8010838:	4618      	mov	r0, r3
 801083a:	f001 f915 	bl	8011a68 <xTaskRemoveFromEventList>
 801083e:	4603      	mov	r3, r0
 8010840:	2b00      	cmp	r3, #0
 8010842:	d007      	beq.n	8010854 <xQueueSemaphoreTake+0xd8>
					{
						queueYIELD_IF_USING_PREEMPTION();
 8010844:	4b54      	ldr	r3, [pc, #336]	@ (8010998 <xQueueSemaphoreTake+0x21c>)
 8010846:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 801084a:	601a      	str	r2, [r3, #0]
 801084c:	f3bf 8f4f 	dsb	sy
 8010850:	f3bf 8f6f 	isb	sy
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				taskEXIT_CRITICAL();
 8010854:	f002 fbd2 	bl	8012ffc <vPortExitCritical>
				return pdPASS;
 8010858:	2301      	movs	r3, #1
 801085a:	e098      	b.n	801098e <xQueueSemaphoreTake+0x212>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 801085c:	683b      	ldr	r3, [r7, #0]
 801085e:	2b00      	cmp	r3, #0
 8010860:	d112      	bne.n	8010888 <xQueueSemaphoreTake+0x10c>
					/* For inheritance to have occurred there must have been an
					initial timeout, and an adjusted timeout cannot become 0, as
					if it were 0 the function would have exited. */
					#if( configUSE_MUTEXES == 1 )
					{
						configASSERT( xInheritanceOccurred == pdFALSE );
 8010862:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010864:	2b00      	cmp	r3, #0
 8010866:	d00b      	beq.n	8010880 <xQueueSemaphoreTake+0x104>
	__asm volatile
 8010868:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801086c:	f383 8811 	msr	BASEPRI, r3
 8010870:	f3bf 8f6f 	isb	sy
 8010874:	f3bf 8f4f 	dsb	sy
 8010878:	617b      	str	r3, [r7, #20]
}
 801087a:	bf00      	nop
 801087c:	bf00      	nop
 801087e:	e7fd      	b.n	801087c <xQueueSemaphoreTake+0x100>
					}
					#endif /* configUSE_MUTEXES */

					/* The semaphore count was 0 and no block time is specified
					(or the block time has expired) so exit now. */
					taskEXIT_CRITICAL();
 8010880:	f002 fbbc 	bl	8012ffc <vPortExitCritical>
					traceQUEUE_RECEIVE_FAILED( pxQueue );
					return errQUEUE_EMPTY;
 8010884:	2300      	movs	r3, #0
 8010886:	e082      	b.n	801098e <xQueueSemaphoreTake+0x212>
				}
				else if( xEntryTimeSet == pdFALSE )
 8010888:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 801088a:	2b00      	cmp	r3, #0
 801088c:	d106      	bne.n	801089c <xQueueSemaphoreTake+0x120>
				{
					/* The semaphore count was 0 and a block time was specified
					so configure the timeout structure ready to block. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 801088e:	f107 030c 	add.w	r3, r7, #12
 8010892:	4618      	mov	r0, r3
 8010894:	f001 f974 	bl	8011b80 <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 8010898:	2301      	movs	r3, #1
 801089a:	637b      	str	r3, [r7, #52]	@ 0x34
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 801089c:	f002 fbae 	bl	8012ffc <vPortExitCritical>

		/* Interrupts and other tasks can give to and take from the semaphore
		now the critical section has been exited. */

		vTaskSuspendAll();
 80108a0:	f000 fea6 	bl	80115f0 <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 80108a4:	f002 fb78 	bl	8012f98 <vPortEnterCritical>
 80108a8:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80108aa:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 80108ae:	b25b      	sxtb	r3, r3
 80108b0:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80108b4:	d103      	bne.n	80108be <xQueueSemaphoreTake+0x142>
 80108b6:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80108b8:	2200      	movs	r2, #0
 80108ba:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 80108be:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80108c0:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 80108c4:	b25b      	sxtb	r3, r3
 80108c6:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80108ca:	d103      	bne.n	80108d4 <xQueueSemaphoreTake+0x158>
 80108cc:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80108ce:	2200      	movs	r2, #0
 80108d0:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 80108d4:	f002 fb92 	bl	8012ffc <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 80108d8:	463a      	mov	r2, r7
 80108da:	f107 030c 	add.w	r3, r7, #12
 80108de:	4611      	mov	r1, r2
 80108e0:	4618      	mov	r0, r3
 80108e2:	f001 f963 	bl	8011bac <xTaskCheckForTimeOut>
 80108e6:	4603      	mov	r3, r0
 80108e8:	2b00      	cmp	r3, #0
 80108ea:	d132      	bne.n	8010952 <xQueueSemaphoreTake+0x1d6>
		{
			/* A block time is specified and not expired.  If the semaphore
			count is 0 then enter the Blocked state to wait for a semaphore to
			become available.  As semaphores are implemented with queues the
			queue being empty is equivalent to the semaphore count being 0. */
			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 80108ec:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 80108ee:	f000 f9d1 	bl	8010c94 <prvIsQueueEmpty>
 80108f2:	4603      	mov	r3, r0
 80108f4:	2b00      	cmp	r3, #0
 80108f6:	d026      	beq.n	8010946 <xQueueSemaphoreTake+0x1ca>
			{
				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );

				#if ( configUSE_MUTEXES == 1 )
				{
					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 80108f8:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80108fa:	681b      	ldr	r3, [r3, #0]
 80108fc:	2b00      	cmp	r3, #0
 80108fe:	d109      	bne.n	8010914 <xQueueSemaphoreTake+0x198>
					{
						taskENTER_CRITICAL();
 8010900:	f002 fb4a 	bl	8012f98 <vPortEnterCritical>
						{
							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
 8010904:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010906:	689b      	ldr	r3, [r3, #8]
 8010908:	4618      	mov	r0, r3
 801090a:	f001 fac9 	bl	8011ea0 <xTaskPriorityInherit>
 801090e:	6338      	str	r0, [r7, #48]	@ 0x30
						}
						taskEXIT_CRITICAL();
 8010910:	f002 fb74 	bl	8012ffc <vPortExitCritical>
						mtCOVERAGE_TEST_MARKER();
					}
				}
				#endif

				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
 8010914:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010916:	3324      	adds	r3, #36	@ 0x24
 8010918:	683a      	ldr	r2, [r7, #0]
 801091a:	4611      	mov	r1, r2
 801091c:	4618      	mov	r0, r3
 801091e:	f001 f851 	bl	80119c4 <vTaskPlaceOnEventList>
				prvUnlockQueue( pxQueue );
 8010922:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8010924:	f000 f964 	bl	8010bf0 <prvUnlockQueue>
				if( xTaskResumeAll() == pdFALSE )
 8010928:	f000 fe70 	bl	801160c <xTaskResumeAll>
 801092c:	4603      	mov	r3, r0
 801092e:	2b00      	cmp	r3, #0
 8010930:	f47f af67 	bne.w	8010802 <xQueueSemaphoreTake+0x86>
				{
					portYIELD_WITHIN_API();
 8010934:	4b18      	ldr	r3, [pc, #96]	@ (8010998 <xQueueSemaphoreTake+0x21c>)
 8010936:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 801093a:	601a      	str	r2, [r3, #0]
 801093c:	f3bf 8f4f 	dsb	sy
 8010940:	f3bf 8f6f 	isb	sy
 8010944:	e75d      	b.n	8010802 <xQueueSemaphoreTake+0x86>
			}
			else
			{
				/* There was no timeout and the semaphore count was not 0, so
				attempt to take the semaphore again. */
				prvUnlockQueue( pxQueue );
 8010946:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8010948:	f000 f952 	bl	8010bf0 <prvUnlockQueue>
				( void ) xTaskResumeAll();
 801094c:	f000 fe5e 	bl	801160c <xTaskResumeAll>
 8010950:	e757      	b.n	8010802 <xQueueSemaphoreTake+0x86>
			}
		}
		else
		{
			/* Timed out. */
			prvUnlockQueue( pxQueue );
 8010952:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8010954:	f000 f94c 	bl	8010bf0 <prvUnlockQueue>
			( void ) xTaskResumeAll();
 8010958:	f000 fe58 	bl	801160c <xTaskResumeAll>

			/* If the semaphore count is 0 exit now as the timeout has
			expired.  Otherwise return to attempt to take the semaphore that is
			known to be available.  As semaphores are implemented by queues the
			queue being empty is equivalent to the semaphore count being 0. */
			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 801095c:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 801095e:	f000 f999 	bl	8010c94 <prvIsQueueEmpty>
 8010962:	4603      	mov	r3, r0
 8010964:	2b00      	cmp	r3, #0
 8010966:	f43f af4c 	beq.w	8010802 <xQueueSemaphoreTake+0x86>
				#if ( configUSE_MUTEXES == 1 )
				{
					/* xInheritanceOccurred could only have be set if
					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
					test the mutex type again to check it is actually a mutex. */
					if( xInheritanceOccurred != pdFALSE )
 801096a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801096c:	2b00      	cmp	r3, #0
 801096e:	d00d      	beq.n	801098c <xQueueSemaphoreTake+0x210>
					{
						taskENTER_CRITICAL();
 8010970:	f002 fb12 	bl	8012f98 <vPortEnterCritical>
							/* This task blocking on the mutex caused another
							task to inherit this task's priority.  Now this task
							has timed out the priority should be disinherited
							again, but only as low as the next highest priority
							task that is waiting for the same mutex. */
							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
 8010974:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8010976:	f000 f893 	bl	8010aa0 <prvGetDisinheritPriorityAfterTimeout>
 801097a:	6278      	str	r0, [r7, #36]	@ 0x24
							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
 801097c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 801097e:	689b      	ldr	r3, [r3, #8]
 8010980:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 8010982:	4618      	mov	r0, r3
 8010984:	f001 fb64 	bl	8012050 <vTaskPriorityDisinheritAfterTimeout>
						}
						taskEXIT_CRITICAL();
 8010988:	f002 fb38 	bl	8012ffc <vPortExitCritical>
					}
				}
				#endif /* configUSE_MUTEXES */

				traceQUEUE_RECEIVE_FAILED( pxQueue );
				return errQUEUE_EMPTY;
 801098c:	2300      	movs	r3, #0
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	} /*lint -restore */
}
 801098e:	4618      	mov	r0, r3
 8010990:	3738      	adds	r7, #56	@ 0x38
 8010992:	46bd      	mov	sp, r7
 8010994:	bd80      	pop	{r7, pc}
 8010996:	bf00      	nop
 8010998:	e000ed04 	.word	0xe000ed04

0801099c <xQueueReceiveFromISR>:
	} /*lint -restore */
}
/*-----------------------------------------------------------*/

BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
{
 801099c:	b580      	push	{r7, lr}
 801099e:	b08e      	sub	sp, #56	@ 0x38
 80109a0:	af00      	add	r7, sp, #0
 80109a2:	60f8      	str	r0, [r7, #12]
 80109a4:	60b9      	str	r1, [r7, #8]
 80109a6:	607a      	str	r2, [r7, #4]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
 80109a8:	68fb      	ldr	r3, [r7, #12]
 80109aa:	633b      	str	r3, [r7, #48]	@ 0x30

	configASSERT( pxQueue );
 80109ac:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80109ae:	2b00      	cmp	r3, #0
 80109b0:	d10b      	bne.n	80109ca <xQueueReceiveFromISR+0x2e>
	__asm volatile
 80109b2:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80109b6:	f383 8811 	msr	BASEPRI, r3
 80109ba:	f3bf 8f6f 	isb	sy
 80109be:	f3bf 8f4f 	dsb	sy
 80109c2:	623b      	str	r3, [r7, #32]
}
 80109c4:	bf00      	nop
 80109c6:	bf00      	nop
 80109c8:	e7fd      	b.n	80109c6 <xQueueReceiveFromISR+0x2a>
	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 80109ca:	68bb      	ldr	r3, [r7, #8]
 80109cc:	2b00      	cmp	r3, #0
 80109ce:	d103      	bne.n	80109d8 <xQueueReceiveFromISR+0x3c>
 80109d0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80109d2:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80109d4:	2b00      	cmp	r3, #0
 80109d6:	d101      	bne.n	80109dc <xQueueReceiveFromISR+0x40>
 80109d8:	2301      	movs	r3, #1
 80109da:	e000      	b.n	80109de <xQueueReceiveFromISR+0x42>
 80109dc:	2300      	movs	r3, #0
 80109de:	2b00      	cmp	r3, #0
 80109e0:	d10b      	bne.n	80109fa <xQueueReceiveFromISR+0x5e>
	__asm volatile
 80109e2:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80109e6:	f383 8811 	msr	BASEPRI, r3
 80109ea:	f3bf 8f6f 	isb	sy
 80109ee:	f3bf 8f4f 	dsb	sy
 80109f2:	61fb      	str	r3, [r7, #28]
}
 80109f4:	bf00      	nop
 80109f6:	bf00      	nop
 80109f8:	e7fd      	b.n	80109f6 <xQueueReceiveFromISR+0x5a>
	that have been assigned a priority at or (logically) below the maximum
	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
	safe API to ensure interrupt entry is as fast and as simple as possible.
	More information (albeit Cortex-M specific) is provided on the following
	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 80109fa:	f002 fbad 	bl	8013158 <vPortValidateInterruptPriority>
	__asm volatile
 80109fe:	f3ef 8211 	mrs	r2, BASEPRI
 8010a02:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010a06:	f383 8811 	msr	BASEPRI, r3
 8010a0a:	f3bf 8f6f 	isb	sy
 8010a0e:	f3bf 8f4f 	dsb	sy
 8010a12:	61ba      	str	r2, [r7, #24]
 8010a14:	617b      	str	r3, [r7, #20]
	return ulOriginalBASEPRI;
 8010a16:	69bb      	ldr	r3, [r7, #24]

	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 8010a18:	62fb      	str	r3, [r7, #44]	@ 0x2c
	{
		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 8010a1a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010a1c:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8010a1e:	62bb      	str	r3, [r7, #40]	@ 0x28

		/* Cannot block in an ISR, so check there is data available. */
		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8010a20:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8010a22:	2b00      	cmp	r3, #0
 8010a24:	d02f      	beq.n	8010a86 <xQueueReceiveFromISR+0xea>
		{
			const int8_t cRxLock = pxQueue->cRxLock;
 8010a26:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010a28:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8010a2c:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27

			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );

			prvCopyDataFromQueue( pxQueue, pvBuffer );
 8010a30:	68b9      	ldr	r1, [r7, #8]
 8010a32:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8010a34:	f000 f8b6 	bl	8010ba4 <prvCopyDataFromQueue>
			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
 8010a38:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8010a3a:	1e5a      	subs	r2, r3, #1
 8010a3c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010a3e:	639a      	str	r2, [r3, #56]	@ 0x38

			/* If the queue is locked the event list will not be modified.
			Instead update the lock count so the task that unlocks the queue
			will know that an ISR has removed data while the queue was
			locked. */
			if( cRxLock == queueUNLOCKED )
 8010a40:	f997 3027 	ldrsb.w	r3, [r7, #39]	@ 0x27
 8010a44:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8010a48:	d112      	bne.n	8010a70 <xQueueReceiveFromISR+0xd4>
			{
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8010a4a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010a4c:	691b      	ldr	r3, [r3, #16]
 8010a4e:	2b00      	cmp	r3, #0
 8010a50:	d016      	beq.n	8010a80 <xQueueReceiveFromISR+0xe4>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8010a52:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010a54:	3310      	adds	r3, #16
 8010a56:	4618      	mov	r0, r3
 8010a58:	f001 f806 	bl	8011a68 <xTaskRemoveFromEventList>
 8010a5c:	4603      	mov	r3, r0
 8010a5e:	2b00      	cmp	r3, #0
 8010a60:	d00e      	beq.n	8010a80 <xQueueReceiveFromISR+0xe4>
					{
						/* The task waiting has a higher priority than us so
						force a context switch. */
						if( pxHigherPriorityTaskWoken != NULL )
 8010a62:	687b      	ldr	r3, [r7, #4]
 8010a64:	2b00      	cmp	r3, #0
 8010a66:	d00b      	beq.n	8010a80 <xQueueReceiveFromISR+0xe4>
						{
							*pxHigherPriorityTaskWoken = pdTRUE;
 8010a68:	687b      	ldr	r3, [r7, #4]
 8010a6a:	2201      	movs	r2, #1
 8010a6c:	601a      	str	r2, [r3, #0]
 8010a6e:	e007      	b.n	8010a80 <xQueueReceiveFromISR+0xe4>
			}
			else
			{
				/* Increment the lock count so the task that unlocks the queue
				knows that data was removed while it was locked. */
				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
 8010a70:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 8010a74:	3301      	adds	r3, #1
 8010a76:	b2db      	uxtb	r3, r3
 8010a78:	b25a      	sxtb	r2, r3
 8010a7a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010a7c:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
			}

			xReturn = pdPASS;
 8010a80:	2301      	movs	r3, #1
 8010a82:	637b      	str	r3, [r7, #52]	@ 0x34
 8010a84:	e001      	b.n	8010a8a <xQueueReceiveFromISR+0xee>
		}
		else
		{
			xReturn = pdFAIL;
 8010a86:	2300      	movs	r3, #0
 8010a88:	637b      	str	r3, [r7, #52]	@ 0x34
 8010a8a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010a8c:	613b      	str	r3, [r7, #16]
	__asm volatile
 8010a8e:	693b      	ldr	r3, [r7, #16]
 8010a90:	f383 8811 	msr	BASEPRI, r3
}
 8010a94:	bf00      	nop
			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
		}
	}
	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

	return xReturn;
 8010a96:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
}
 8010a98:	4618      	mov	r0, r3
 8010a9a:	3738      	adds	r7, #56	@ 0x38
 8010a9c:	46bd      	mov	sp, r7
 8010a9e:	bd80      	pop	{r7, pc}

08010aa0 <prvGetDisinheritPriorityAfterTimeout>:
/*-----------------------------------------------------------*/

#if( configUSE_MUTEXES == 1 )

	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
	{
 8010aa0:	b480      	push	{r7}
 8010aa2:	b085      	sub	sp, #20
 8010aa4:	af00      	add	r7, sp, #0
 8010aa6:	6078      	str	r0, [r7, #4]
		priority, but the waiting task times out, then the holder should
		disinherit the priority - but only down to the highest priority of any
		other tasks that are waiting for the same mutex.  For this purpose,
		return the priority of the highest priority task that is waiting for the
		mutex. */
		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
 8010aa8:	687b      	ldr	r3, [r7, #4]
 8010aaa:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8010aac:	2b00      	cmp	r3, #0
 8010aae:	d006      	beq.n	8010abe <prvGetDisinheritPriorityAfterTimeout+0x1e>
		{
			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
 8010ab0:	687b      	ldr	r3, [r7, #4]
 8010ab2:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8010ab4:	681b      	ldr	r3, [r3, #0]
 8010ab6:	f1c3 0338 	rsb	r3, r3, #56	@ 0x38
 8010aba:	60fb      	str	r3, [r7, #12]
 8010abc:	e001      	b.n	8010ac2 <prvGetDisinheritPriorityAfterTimeout+0x22>
		}
		else
		{
			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
 8010abe:	2300      	movs	r3, #0
 8010ac0:	60fb      	str	r3, [r7, #12]
		}

		return uxHighestPriorityOfWaitingTasks;
 8010ac2:	68fb      	ldr	r3, [r7, #12]
	}
 8010ac4:	4618      	mov	r0, r3
 8010ac6:	3714      	adds	r7, #20
 8010ac8:	46bd      	mov	sp, r7
 8010aca:	f85d 7b04 	ldr.w	r7, [sp], #4
 8010ace:	4770      	bx	lr

08010ad0 <prvCopyDataToQueue>:

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
 8010ad0:	b580      	push	{r7, lr}
 8010ad2:	b086      	sub	sp, #24
 8010ad4:	af00      	add	r7, sp, #0
 8010ad6:	60f8      	str	r0, [r7, #12]
 8010ad8:	60b9      	str	r1, [r7, #8]
 8010ada:	607a      	str	r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
 8010adc:	2300      	movs	r3, #0
 8010ade:	617b      	str	r3, [r7, #20]
UBaseType_t uxMessagesWaiting;

	/* This function is called from a critical section. */

	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 8010ae0:	68fb      	ldr	r3, [r7, #12]
 8010ae2:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8010ae4:	613b      	str	r3, [r7, #16]

	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
 8010ae6:	68fb      	ldr	r3, [r7, #12]
 8010ae8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8010aea:	2b00      	cmp	r3, #0
 8010aec:	d10d      	bne.n	8010b0a <prvCopyDataToQueue+0x3a>
	{
		#if ( configUSE_MUTEXES == 1 )
		{
			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 8010aee:	68fb      	ldr	r3, [r7, #12]
 8010af0:	681b      	ldr	r3, [r3, #0]
 8010af2:	2b00      	cmp	r3, #0
 8010af4:	d14d      	bne.n	8010b92 <prvCopyDataToQueue+0xc2>
			{
				/* The mutex is no longer being held. */
				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
 8010af6:	68fb      	ldr	r3, [r7, #12]
 8010af8:	689b      	ldr	r3, [r3, #8]
 8010afa:	4618      	mov	r0, r3
 8010afc:	f001 fa38 	bl	8011f70 <xTaskPriorityDisinherit>
 8010b00:	6178      	str	r0, [r7, #20]
				pxQueue->u.xSemaphore.xMutexHolder = NULL;
 8010b02:	68fb      	ldr	r3, [r7, #12]
 8010b04:	2200      	movs	r2, #0
 8010b06:	609a      	str	r2, [r3, #8]
 8010b08:	e043      	b.n	8010b92 <prvCopyDataToQueue+0xc2>
				mtCOVERAGE_TEST_MARKER();
			}
		}
		#endif /* configUSE_MUTEXES */
	}
	else if( xPosition == queueSEND_TO_BACK )
 8010b0a:	687b      	ldr	r3, [r7, #4]
 8010b0c:	2b00      	cmp	r3, #0
 8010b0e:	d119      	bne.n	8010b44 <prvCopyDataToQueue+0x74>
	{
		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 8010b10:	68fb      	ldr	r3, [r7, #12]
 8010b12:	6858      	ldr	r0, [r3, #4]
 8010b14:	68fb      	ldr	r3, [r7, #12]
 8010b16:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8010b18:	461a      	mov	r2, r3
 8010b1a:	68b9      	ldr	r1, [r7, #8]
 8010b1c:	f002 ff35 	bl	801398a <memcpy>
		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
 8010b20:	68fb      	ldr	r3, [r7, #12]
 8010b22:	685a      	ldr	r2, [r3, #4]
 8010b24:	68fb      	ldr	r3, [r7, #12]
 8010b26:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8010b28:	441a      	add	r2, r3
 8010b2a:	68fb      	ldr	r3, [r7, #12]
 8010b2c:	605a      	str	r2, [r3, #4]
		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 8010b2e:	68fb      	ldr	r3, [r7, #12]
 8010b30:	685a      	ldr	r2, [r3, #4]
 8010b32:	68fb      	ldr	r3, [r7, #12]
 8010b34:	689b      	ldr	r3, [r3, #8]
 8010b36:	429a      	cmp	r2, r3
 8010b38:	d32b      	bcc.n	8010b92 <prvCopyDataToQueue+0xc2>
		{
			pxQueue->pcWriteTo = pxQueue->pcHead;
 8010b3a:	68fb      	ldr	r3, [r7, #12]
 8010b3c:	681a      	ldr	r2, [r3, #0]
 8010b3e:	68fb      	ldr	r3, [r7, #12]
 8010b40:	605a      	str	r2, [r3, #4]
 8010b42:	e026      	b.n	8010b92 <prvCopyDataToQueue+0xc2>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	else
	{
		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
 8010b44:	68fb      	ldr	r3, [r7, #12]
 8010b46:	68d8      	ldr	r0, [r3, #12]
 8010b48:	68fb      	ldr	r3, [r7, #12]
 8010b4a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8010b4c:	461a      	mov	r2, r3
 8010b4e:	68b9      	ldr	r1, [r7, #8]
 8010b50:	f002 ff1b 	bl	801398a <memcpy>
		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
 8010b54:	68fb      	ldr	r3, [r7, #12]
 8010b56:	68da      	ldr	r2, [r3, #12]
 8010b58:	68fb      	ldr	r3, [r7, #12]
 8010b5a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8010b5c:	425b      	negs	r3, r3
 8010b5e:	441a      	add	r2, r3
 8010b60:	68fb      	ldr	r3, [r7, #12]
 8010b62:	60da      	str	r2, [r3, #12]
		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 8010b64:	68fb      	ldr	r3, [r7, #12]
 8010b66:	68da      	ldr	r2, [r3, #12]
 8010b68:	68fb      	ldr	r3, [r7, #12]
 8010b6a:	681b      	ldr	r3, [r3, #0]
 8010b6c:	429a      	cmp	r2, r3
 8010b6e:	d207      	bcs.n	8010b80 <prvCopyDataToQueue+0xb0>
		{
			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
 8010b70:	68fb      	ldr	r3, [r7, #12]
 8010b72:	689a      	ldr	r2, [r3, #8]
 8010b74:	68fb      	ldr	r3, [r7, #12]
 8010b76:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8010b78:	425b      	negs	r3, r3
 8010b7a:	441a      	add	r2, r3
 8010b7c:	68fb      	ldr	r3, [r7, #12]
 8010b7e:	60da      	str	r2, [r3, #12]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		if( xPosition == queueOVERWRITE )
 8010b80:	687b      	ldr	r3, [r7, #4]
 8010b82:	2b02      	cmp	r3, #2
 8010b84:	d105      	bne.n	8010b92 <prvCopyDataToQueue+0xc2>
		{
			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8010b86:	693b      	ldr	r3, [r7, #16]
 8010b88:	2b00      	cmp	r3, #0
 8010b8a:	d002      	beq.n	8010b92 <prvCopyDataToQueue+0xc2>
			{
				/* An item is not being added but overwritten, so subtract
				one from the recorded number of items in the queue so when
				one is added again below the number of recorded items remains
				correct. */
				--uxMessagesWaiting;
 8010b8c:	693b      	ldr	r3, [r7, #16]
 8010b8e:	3b01      	subs	r3, #1
 8010b90:	613b      	str	r3, [r7, #16]
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}

	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
 8010b92:	693b      	ldr	r3, [r7, #16]
 8010b94:	1c5a      	adds	r2, r3, #1
 8010b96:	68fb      	ldr	r3, [r7, #12]
 8010b98:	639a      	str	r2, [r3, #56]	@ 0x38

	return xReturn;
 8010b9a:	697b      	ldr	r3, [r7, #20]
}
 8010b9c:	4618      	mov	r0, r3
 8010b9e:	3718      	adds	r7, #24
 8010ba0:	46bd      	mov	sp, r7
 8010ba2:	bd80      	pop	{r7, pc}

08010ba4 <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/

static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
 8010ba4:	b580      	push	{r7, lr}
 8010ba6:	b082      	sub	sp, #8
 8010ba8:	af00      	add	r7, sp, #0
 8010baa:	6078      	str	r0, [r7, #4]
 8010bac:	6039      	str	r1, [r7, #0]
	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
 8010bae:	687b      	ldr	r3, [r7, #4]
 8010bb0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8010bb2:	2b00      	cmp	r3, #0
 8010bb4:	d018      	beq.n	8010be8 <prvCopyDataFromQueue+0x44>
	{
		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
 8010bb6:	687b      	ldr	r3, [r7, #4]
 8010bb8:	68da      	ldr	r2, [r3, #12]
 8010bba:	687b      	ldr	r3, [r7, #4]
 8010bbc:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8010bbe:	441a      	add	r2, r3
 8010bc0:	687b      	ldr	r3, [r7, #4]
 8010bc2:	60da      	str	r2, [r3, #12]
		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
 8010bc4:	687b      	ldr	r3, [r7, #4]
 8010bc6:	68da      	ldr	r2, [r3, #12]
 8010bc8:	687b      	ldr	r3, [r7, #4]
 8010bca:	689b      	ldr	r3, [r3, #8]
 8010bcc:	429a      	cmp	r2, r3
 8010bce:	d303      	bcc.n	8010bd8 <prvCopyDataFromQueue+0x34>
		{
			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
 8010bd0:	687b      	ldr	r3, [r7, #4]
 8010bd2:	681a      	ldr	r2, [r3, #0]
 8010bd4:	687b      	ldr	r3, [r7, #4]
 8010bd6:	60da      	str	r2, [r3, #12]
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 8010bd8:	687b      	ldr	r3, [r7, #4]
 8010bda:	68d9      	ldr	r1, [r3, #12]
 8010bdc:	687b      	ldr	r3, [r7, #4]
 8010bde:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8010be0:	461a      	mov	r2, r3
 8010be2:	6838      	ldr	r0, [r7, #0]
 8010be4:	f002 fed1 	bl	801398a <memcpy>
	}
}
 8010be8:	bf00      	nop
 8010bea:	3708      	adds	r7, #8
 8010bec:	46bd      	mov	sp, r7
 8010bee:	bd80      	pop	{r7, pc}

08010bf0 <prvUnlockQueue>:
/*-----------------------------------------------------------*/

static void prvUnlockQueue( Queue_t * const pxQueue )
{
 8010bf0:	b580      	push	{r7, lr}
 8010bf2:	b084      	sub	sp, #16
 8010bf4:	af00      	add	r7, sp, #0
 8010bf6:	6078      	str	r0, [r7, #4]

	/* The lock counts contains the number of extra data items placed or
	removed from the queue while the queue was locked.  When a queue is
	locked items can be added or removed, but the event lists cannot be
	updated. */
	taskENTER_CRITICAL();
 8010bf8:	f002 f9ce 	bl	8012f98 <vPortEnterCritical>
	{
		int8_t cTxLock = pxQueue->cTxLock;
 8010bfc:	687b      	ldr	r3, [r7, #4]
 8010bfe:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8010c02:	73fb      	strb	r3, [r7, #15]

		/* See if data was added to the queue while it was locked. */
		while( cTxLock > queueLOCKED_UNMODIFIED )
 8010c04:	e011      	b.n	8010c2a <prvUnlockQueue+0x3a>
			}
			#else /* configUSE_QUEUE_SETS */
			{
				/* Tasks that are removed from the event list will get added to
				the pending ready list as the scheduler is still suspended. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8010c06:	687b      	ldr	r3, [r7, #4]
 8010c08:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8010c0a:	2b00      	cmp	r3, #0
 8010c0c:	d012      	beq.n	8010c34 <prvUnlockQueue+0x44>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8010c0e:	687b      	ldr	r3, [r7, #4]
 8010c10:	3324      	adds	r3, #36	@ 0x24
 8010c12:	4618      	mov	r0, r3
 8010c14:	f000 ff28 	bl	8011a68 <xTaskRemoveFromEventList>
 8010c18:	4603      	mov	r3, r0
 8010c1a:	2b00      	cmp	r3, #0
 8010c1c:	d001      	beq.n	8010c22 <prvUnlockQueue+0x32>
					{
						/* The task waiting has a higher priority so record that
						a context switch is required. */
						vTaskMissedYield();
 8010c1e:	f001 f829 	bl	8011c74 <vTaskMissedYield>
					break;
				}
			}
			#endif /* configUSE_QUEUE_SETS */

			--cTxLock;
 8010c22:	7bfb      	ldrb	r3, [r7, #15]
 8010c24:	3b01      	subs	r3, #1
 8010c26:	b2db      	uxtb	r3, r3
 8010c28:	73fb      	strb	r3, [r7, #15]
		while( cTxLock > queueLOCKED_UNMODIFIED )
 8010c2a:	f997 300f 	ldrsb.w	r3, [r7, #15]
 8010c2e:	2b00      	cmp	r3, #0
 8010c30:	dce9      	bgt.n	8010c06 <prvUnlockQueue+0x16>
 8010c32:	e000      	b.n	8010c36 <prvUnlockQueue+0x46>
					break;
 8010c34:	bf00      	nop
		}

		pxQueue->cTxLock = queueUNLOCKED;
 8010c36:	687b      	ldr	r3, [r7, #4]
 8010c38:	22ff      	movs	r2, #255	@ 0xff
 8010c3a:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
	}
	taskEXIT_CRITICAL();
 8010c3e:	f002 f9dd 	bl	8012ffc <vPortExitCritical>

	/* Do the same for the Rx lock. */
	taskENTER_CRITICAL();
 8010c42:	f002 f9a9 	bl	8012f98 <vPortEnterCritical>
	{
		int8_t cRxLock = pxQueue->cRxLock;
 8010c46:	687b      	ldr	r3, [r7, #4]
 8010c48:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8010c4c:	73bb      	strb	r3, [r7, #14]

		while( cRxLock > queueLOCKED_UNMODIFIED )
 8010c4e:	e011      	b.n	8010c74 <prvUnlockQueue+0x84>
		{
			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8010c50:	687b      	ldr	r3, [r7, #4]
 8010c52:	691b      	ldr	r3, [r3, #16]
 8010c54:	2b00      	cmp	r3, #0
 8010c56:	d012      	beq.n	8010c7e <prvUnlockQueue+0x8e>
			{
				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8010c58:	687b      	ldr	r3, [r7, #4]
 8010c5a:	3310      	adds	r3, #16
 8010c5c:	4618      	mov	r0, r3
 8010c5e:	f000 ff03 	bl	8011a68 <xTaskRemoveFromEventList>
 8010c62:	4603      	mov	r3, r0
 8010c64:	2b00      	cmp	r3, #0
 8010c66:	d001      	beq.n	8010c6c <prvUnlockQueue+0x7c>
				{
					vTaskMissedYield();
 8010c68:	f001 f804 	bl	8011c74 <vTaskMissedYield>
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				--cRxLock;
 8010c6c:	7bbb      	ldrb	r3, [r7, #14]
 8010c6e:	3b01      	subs	r3, #1
 8010c70:	b2db      	uxtb	r3, r3
 8010c72:	73bb      	strb	r3, [r7, #14]
		while( cRxLock > queueLOCKED_UNMODIFIED )
 8010c74:	f997 300e 	ldrsb.w	r3, [r7, #14]
 8010c78:	2b00      	cmp	r3, #0
 8010c7a:	dce9      	bgt.n	8010c50 <prvUnlockQueue+0x60>
 8010c7c:	e000      	b.n	8010c80 <prvUnlockQueue+0x90>
			}
			else
			{
				break;
 8010c7e:	bf00      	nop
			}
		}

		pxQueue->cRxLock = queueUNLOCKED;
 8010c80:	687b      	ldr	r3, [r7, #4]
 8010c82:	22ff      	movs	r2, #255	@ 0xff
 8010c84:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
	}
	taskEXIT_CRITICAL();
 8010c88:	f002 f9b8 	bl	8012ffc <vPortExitCritical>
}
 8010c8c:	bf00      	nop
 8010c8e:	3710      	adds	r7, #16
 8010c90:	46bd      	mov	sp, r7
 8010c92:	bd80      	pop	{r7, pc}

08010c94 <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
 8010c94:	b580      	push	{r7, lr}
 8010c96:	b084      	sub	sp, #16
 8010c98:	af00      	add	r7, sp, #0
 8010c9a:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;

	taskENTER_CRITICAL();
 8010c9c:	f002 f97c 	bl	8012f98 <vPortEnterCritical>
	{
		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
 8010ca0:	687b      	ldr	r3, [r7, #4]
 8010ca2:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8010ca4:	2b00      	cmp	r3, #0
 8010ca6:	d102      	bne.n	8010cae <prvIsQueueEmpty+0x1a>
		{
			xReturn = pdTRUE;
 8010ca8:	2301      	movs	r3, #1
 8010caa:	60fb      	str	r3, [r7, #12]
 8010cac:	e001      	b.n	8010cb2 <prvIsQueueEmpty+0x1e>
		}
		else
		{
			xReturn = pdFALSE;
 8010cae:	2300      	movs	r3, #0
 8010cb0:	60fb      	str	r3, [r7, #12]
		}
	}
	taskEXIT_CRITICAL();
 8010cb2:	f002 f9a3 	bl	8012ffc <vPortExitCritical>

	return xReturn;
 8010cb6:	68fb      	ldr	r3, [r7, #12]
}
 8010cb8:	4618      	mov	r0, r3
 8010cba:	3710      	adds	r7, #16
 8010cbc:	46bd      	mov	sp, r7
 8010cbe:	bd80      	pop	{r7, pc}

08010cc0 <prvIsQueueFull>:
	return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
 8010cc0:	b580      	push	{r7, lr}
 8010cc2:	b084      	sub	sp, #16
 8010cc4:	af00      	add	r7, sp, #0
 8010cc6:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;

	taskENTER_CRITICAL();
 8010cc8:	f002 f966 	bl	8012f98 <vPortEnterCritical>
	{
		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
 8010ccc:	687b      	ldr	r3, [r7, #4]
 8010cce:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 8010cd0:	687b      	ldr	r3, [r7, #4]
 8010cd2:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8010cd4:	429a      	cmp	r2, r3
 8010cd6:	d102      	bne.n	8010cde <prvIsQueueFull+0x1e>
		{
			xReturn = pdTRUE;
 8010cd8:	2301      	movs	r3, #1
 8010cda:	60fb      	str	r3, [r7, #12]
 8010cdc:	e001      	b.n	8010ce2 <prvIsQueueFull+0x22>
		}
		else
		{
			xReturn = pdFALSE;
 8010cde:	2300      	movs	r3, #0
 8010ce0:	60fb      	str	r3, [r7, #12]
		}
	}
	taskEXIT_CRITICAL();
 8010ce2:	f002 f98b 	bl	8012ffc <vPortExitCritical>

	return xReturn;
 8010ce6:	68fb      	ldr	r3, [r7, #12]
}
 8010ce8:	4618      	mov	r0, r3
 8010cea:	3710      	adds	r7, #16
 8010cec:	46bd      	mov	sp, r7
 8010cee:	bd80      	pop	{r7, pc}

08010cf0 <vQueueAddToRegistry>:
/*-----------------------------------------------------------*/

#if ( configQUEUE_REGISTRY_SIZE > 0 )

	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
	{
 8010cf0:	b480      	push	{r7}
 8010cf2:	b085      	sub	sp, #20
 8010cf4:	af00      	add	r7, sp, #0
 8010cf6:	6078      	str	r0, [r7, #4]
 8010cf8:	6039      	str	r1, [r7, #0]
	UBaseType_t ux;

		/* See if there is an empty space in the registry.  A NULL name denotes
		a free slot. */
		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
 8010cfa:	2300      	movs	r3, #0
 8010cfc:	60fb      	str	r3, [r7, #12]
 8010cfe:	e014      	b.n	8010d2a <vQueueAddToRegistry+0x3a>
		{
			if( xQueueRegistry[ ux ].pcQueueName == NULL )
 8010d00:	4a0f      	ldr	r2, [pc, #60]	@ (8010d40 <vQueueAddToRegistry+0x50>)
 8010d02:	68fb      	ldr	r3, [r7, #12]
 8010d04:	f852 3033 	ldr.w	r3, [r2, r3, lsl #3]
 8010d08:	2b00      	cmp	r3, #0
 8010d0a:	d10b      	bne.n	8010d24 <vQueueAddToRegistry+0x34>
			{
				/* Store the information on this queue. */
				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
 8010d0c:	490c      	ldr	r1, [pc, #48]	@ (8010d40 <vQueueAddToRegistry+0x50>)
 8010d0e:	68fb      	ldr	r3, [r7, #12]
 8010d10:	683a      	ldr	r2, [r7, #0]
 8010d12:	f841 2033 	str.w	r2, [r1, r3, lsl #3]
				xQueueRegistry[ ux ].xHandle = xQueue;
 8010d16:	4a0a      	ldr	r2, [pc, #40]	@ (8010d40 <vQueueAddToRegistry+0x50>)
 8010d18:	68fb      	ldr	r3, [r7, #12]
 8010d1a:	00db      	lsls	r3, r3, #3
 8010d1c:	4413      	add	r3, r2
 8010d1e:	687a      	ldr	r2, [r7, #4]
 8010d20:	605a      	str	r2, [r3, #4]

				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
				break;
 8010d22:	e006      	b.n	8010d32 <vQueueAddToRegistry+0x42>
		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
 8010d24:	68fb      	ldr	r3, [r7, #12]
 8010d26:	3301      	adds	r3, #1
 8010d28:	60fb      	str	r3, [r7, #12]
 8010d2a:	68fb      	ldr	r3, [r7, #12]
 8010d2c:	2b07      	cmp	r3, #7
 8010d2e:	d9e7      	bls.n	8010d00 <vQueueAddToRegistry+0x10>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	}
 8010d30:	bf00      	nop
 8010d32:	bf00      	nop
 8010d34:	3714      	adds	r7, #20
 8010d36:	46bd      	mov	sp, r7
 8010d38:	f85d 7b04 	ldr.w	r7, [sp], #4
 8010d3c:	4770      	bx	lr
 8010d3e:	bf00      	nop
 8010d40:	240023b4 	.word	0x240023b4

08010d44 <vQueueWaitForMessageRestricted>:
/*-----------------------------------------------------------*/

#if ( configUSE_TIMERS == 1 )

	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
	{
 8010d44:	b580      	push	{r7, lr}
 8010d46:	b086      	sub	sp, #24
 8010d48:	af00      	add	r7, sp, #0
 8010d4a:	60f8      	str	r0, [r7, #12]
 8010d4c:	60b9      	str	r1, [r7, #8]
 8010d4e:	607a      	str	r2, [r7, #4]
	Queue_t * const pxQueue = xQueue;
 8010d50:	68fb      	ldr	r3, [r7, #12]
 8010d52:	617b      	str	r3, [r7, #20]
		will not actually cause the task to block, just place it on a blocked
		list.  It will not block until the scheduler is unlocked - at which
		time a yield will be performed.  If an item is added to the queue while
		the queue is locked, and the calling task blocks on the queue, then the
		calling task will be immediately unblocked when the queue is unlocked. */
		prvLockQueue( pxQueue );
 8010d54:	f002 f920 	bl	8012f98 <vPortEnterCritical>
 8010d58:	697b      	ldr	r3, [r7, #20]
 8010d5a:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8010d5e:	b25b      	sxtb	r3, r3
 8010d60:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8010d64:	d103      	bne.n	8010d6e <vQueueWaitForMessageRestricted+0x2a>
 8010d66:	697b      	ldr	r3, [r7, #20]
 8010d68:	2200      	movs	r2, #0
 8010d6a:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 8010d6e:	697b      	ldr	r3, [r7, #20]
 8010d70:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8010d74:	b25b      	sxtb	r3, r3
 8010d76:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8010d7a:	d103      	bne.n	8010d84 <vQueueWaitForMessageRestricted+0x40>
 8010d7c:	697b      	ldr	r3, [r7, #20]
 8010d7e:	2200      	movs	r2, #0
 8010d80:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 8010d84:	f002 f93a 	bl	8012ffc <vPortExitCritical>
		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
 8010d88:	697b      	ldr	r3, [r7, #20]
 8010d8a:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8010d8c:	2b00      	cmp	r3, #0
 8010d8e:	d106      	bne.n	8010d9e <vQueueWaitForMessageRestricted+0x5a>
		{
			/* There is nothing in the queue, block for the specified period. */
			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
 8010d90:	697b      	ldr	r3, [r7, #20]
 8010d92:	3324      	adds	r3, #36	@ 0x24
 8010d94:	687a      	ldr	r2, [r7, #4]
 8010d96:	68b9      	ldr	r1, [r7, #8]
 8010d98:	4618      	mov	r0, r3
 8010d9a:	f000 fe39 	bl	8011a10 <vTaskPlaceOnEventListRestricted>
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
		prvUnlockQueue( pxQueue );
 8010d9e:	6978      	ldr	r0, [r7, #20]
 8010da0:	f7ff ff26 	bl	8010bf0 <prvUnlockQueue>
	}
 8010da4:	bf00      	nop
 8010da6:	3718      	adds	r7, #24
 8010da8:	46bd      	mov	sp, r7
 8010daa:	bd80      	pop	{r7, pc}

08010dac <xStreamBufferSpacesAvailable>:
	return xReturn;
}
/*-----------------------------------------------------------*/

size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
{
 8010dac:	b480      	push	{r7}
 8010dae:	b087      	sub	sp, #28
 8010db0:	af00      	add	r7, sp, #0
 8010db2:	6078      	str	r0, [r7, #4]
const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 8010db4:	687b      	ldr	r3, [r7, #4]
 8010db6:	613b      	str	r3, [r7, #16]
size_t xSpace;

	configASSERT( pxStreamBuffer );
 8010db8:	693b      	ldr	r3, [r7, #16]
 8010dba:	2b00      	cmp	r3, #0
 8010dbc:	d10b      	bne.n	8010dd6 <xStreamBufferSpacesAvailable+0x2a>
	__asm volatile
 8010dbe:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010dc2:	f383 8811 	msr	BASEPRI, r3
 8010dc6:	f3bf 8f6f 	isb	sy
 8010dca:	f3bf 8f4f 	dsb	sy
 8010dce:	60fb      	str	r3, [r7, #12]
}
 8010dd0:	bf00      	nop
 8010dd2:	bf00      	nop
 8010dd4:	e7fd      	b.n	8010dd2 <xStreamBufferSpacesAvailable+0x26>

	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
 8010dd6:	693b      	ldr	r3, [r7, #16]
 8010dd8:	689a      	ldr	r2, [r3, #8]
 8010dda:	693b      	ldr	r3, [r7, #16]
 8010ddc:	681b      	ldr	r3, [r3, #0]
 8010dde:	4413      	add	r3, r2
 8010de0:	617b      	str	r3, [r7, #20]
	xSpace -= pxStreamBuffer->xHead;
 8010de2:	693b      	ldr	r3, [r7, #16]
 8010de4:	685b      	ldr	r3, [r3, #4]
 8010de6:	697a      	ldr	r2, [r7, #20]
 8010de8:	1ad3      	subs	r3, r2, r3
 8010dea:	617b      	str	r3, [r7, #20]
	xSpace -= ( size_t ) 1;
 8010dec:	697b      	ldr	r3, [r7, #20]
 8010dee:	3b01      	subs	r3, #1
 8010df0:	617b      	str	r3, [r7, #20]

	if( xSpace >= pxStreamBuffer->xLength )
 8010df2:	693b      	ldr	r3, [r7, #16]
 8010df4:	689b      	ldr	r3, [r3, #8]
 8010df6:	697a      	ldr	r2, [r7, #20]
 8010df8:	429a      	cmp	r2, r3
 8010dfa:	d304      	bcc.n	8010e06 <xStreamBufferSpacesAvailable+0x5a>
	{
		xSpace -= pxStreamBuffer->xLength;
 8010dfc:	693b      	ldr	r3, [r7, #16]
 8010dfe:	689b      	ldr	r3, [r3, #8]
 8010e00:	697a      	ldr	r2, [r7, #20]
 8010e02:	1ad3      	subs	r3, r2, r3
 8010e04:	617b      	str	r3, [r7, #20]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	return xSpace;
 8010e06:	697b      	ldr	r3, [r7, #20]
}
 8010e08:	4618      	mov	r0, r3
 8010e0a:	371c      	adds	r7, #28
 8010e0c:	46bd      	mov	sp, r7
 8010e0e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8010e12:	4770      	bx	lr

08010e14 <xStreamBufferSend>:

size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
						  const void *pvTxData,
						  size_t xDataLengthBytes,
						  TickType_t xTicksToWait )
{
 8010e14:	b580      	push	{r7, lr}
 8010e16:	b090      	sub	sp, #64	@ 0x40
 8010e18:	af02      	add	r7, sp, #8
 8010e1a:	60f8      	str	r0, [r7, #12]
 8010e1c:	60b9      	str	r1, [r7, #8]
 8010e1e:	607a      	str	r2, [r7, #4]
 8010e20:	603b      	str	r3, [r7, #0]
StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 8010e22:	68fb      	ldr	r3, [r7, #12]
 8010e24:	62fb      	str	r3, [r7, #44]	@ 0x2c
size_t xReturn, xSpace = 0;
 8010e26:	2300      	movs	r3, #0
 8010e28:	637b      	str	r3, [r7, #52]	@ 0x34
size_t xRequiredSpace = xDataLengthBytes;
 8010e2a:	687b      	ldr	r3, [r7, #4]
 8010e2c:	633b      	str	r3, [r7, #48]	@ 0x30
TimeOut_t xTimeOut;

	configASSERT( pvTxData );
 8010e2e:	68bb      	ldr	r3, [r7, #8]
 8010e30:	2b00      	cmp	r3, #0
 8010e32:	d10b      	bne.n	8010e4c <xStreamBufferSend+0x38>
	__asm volatile
 8010e34:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010e38:	f383 8811 	msr	BASEPRI, r3
 8010e3c:	f3bf 8f6f 	isb	sy
 8010e40:	f3bf 8f4f 	dsb	sy
 8010e44:	627b      	str	r3, [r7, #36]	@ 0x24
}
 8010e46:	bf00      	nop
 8010e48:	bf00      	nop
 8010e4a:	e7fd      	b.n	8010e48 <xStreamBufferSend+0x34>
	configASSERT( pxStreamBuffer );
 8010e4c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010e4e:	2b00      	cmp	r3, #0
 8010e50:	d10b      	bne.n	8010e6a <xStreamBufferSend+0x56>
	__asm volatile
 8010e52:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010e56:	f383 8811 	msr	BASEPRI, r3
 8010e5a:	f3bf 8f6f 	isb	sy
 8010e5e:	f3bf 8f4f 	dsb	sy
 8010e62:	623b      	str	r3, [r7, #32]
}
 8010e64:	bf00      	nop
 8010e66:	bf00      	nop
 8010e68:	e7fd      	b.n	8010e66 <xStreamBufferSend+0x52>

	/* This send function is used to write to both message buffers and stream
	buffers.  If this is a message buffer then the space needed must be
	increased by the amount of bytes needed to store the length of the
	message. */
	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
 8010e6a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010e6c:	7f1b      	ldrb	r3, [r3, #28]
 8010e6e:	f003 0301 	and.w	r3, r3, #1
 8010e72:	2b00      	cmp	r3, #0
 8010e74:	d012      	beq.n	8010e9c <xStreamBufferSend+0x88>
	{
		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
 8010e76:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010e78:	3304      	adds	r3, #4
 8010e7a:	633b      	str	r3, [r7, #48]	@ 0x30

		/* Overflow? */
		configASSERT( xRequiredSpace > xDataLengthBytes );
 8010e7c:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8010e7e:	687b      	ldr	r3, [r7, #4]
 8010e80:	429a      	cmp	r2, r3
 8010e82:	d80b      	bhi.n	8010e9c <xStreamBufferSend+0x88>
	__asm volatile
 8010e84:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010e88:	f383 8811 	msr	BASEPRI, r3
 8010e8c:	f3bf 8f6f 	isb	sy
 8010e90:	f3bf 8f4f 	dsb	sy
 8010e94:	61fb      	str	r3, [r7, #28]
}
 8010e96:	bf00      	nop
 8010e98:	bf00      	nop
 8010e9a:	e7fd      	b.n	8010e98 <xStreamBufferSend+0x84>
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	if( xTicksToWait != ( TickType_t ) 0 )
 8010e9c:	683b      	ldr	r3, [r7, #0]
 8010e9e:	2b00      	cmp	r3, #0
 8010ea0:	d03f      	beq.n	8010f22 <xStreamBufferSend+0x10e>
	{
		vTaskSetTimeOutState( &xTimeOut );
 8010ea2:	f107 0310 	add.w	r3, r7, #16
 8010ea6:	4618      	mov	r0, r3
 8010ea8:	f000 fe42 	bl	8011b30 <vTaskSetTimeOutState>

		do
		{
			/* Wait until the required number of bytes are free in the message
			buffer. */
			taskENTER_CRITICAL();
 8010eac:	f002 f874 	bl	8012f98 <vPortEnterCritical>
			{
				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
 8010eb0:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8010eb2:	f7ff ff7b 	bl	8010dac <xStreamBufferSpacesAvailable>
 8010eb6:	6378      	str	r0, [r7, #52]	@ 0x34

				if( xSpace < xRequiredSpace )
 8010eb8:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 8010eba:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010ebc:	429a      	cmp	r2, r3
 8010ebe:	d218      	bcs.n	8010ef2 <xStreamBufferSend+0xde>
				{
					/* Clear notification state as going to wait for space. */
					( void ) xTaskNotifyStateClear( NULL );
 8010ec0:	2000      	movs	r0, #0
 8010ec2:	f001 fb65 	bl	8012590 <xTaskNotifyStateClear>

					/* Should only be one writer. */
					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
 8010ec6:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010ec8:	695b      	ldr	r3, [r3, #20]
 8010eca:	2b00      	cmp	r3, #0
 8010ecc:	d00b      	beq.n	8010ee6 <xStreamBufferSend+0xd2>
	__asm volatile
 8010ece:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8010ed2:	f383 8811 	msr	BASEPRI, r3
 8010ed6:	f3bf 8f6f 	isb	sy
 8010eda:	f3bf 8f4f 	dsb	sy
 8010ede:	61bb      	str	r3, [r7, #24]
}
 8010ee0:	bf00      	nop
 8010ee2:	bf00      	nop
 8010ee4:	e7fd      	b.n	8010ee2 <xStreamBufferSend+0xce>
					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
 8010ee6:	f000 ffad 	bl	8011e44 <xTaskGetCurrentTaskHandle>
 8010eea:	4602      	mov	r2, r0
 8010eec:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010eee:	615a      	str	r2, [r3, #20]
 8010ef0:	e002      	b.n	8010ef8 <xStreamBufferSend+0xe4>
				}
				else
				{
					taskEXIT_CRITICAL();
 8010ef2:	f002 f883 	bl	8012ffc <vPortExitCritical>
					break;
 8010ef6:	e014      	b.n	8010f22 <xStreamBufferSend+0x10e>
				}
			}
			taskEXIT_CRITICAL();
 8010ef8:	f002 f880 	bl	8012ffc <vPortExitCritical>

			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
 8010efc:	683b      	ldr	r3, [r7, #0]
 8010efe:	2200      	movs	r2, #0
 8010f00:	2100      	movs	r1, #0
 8010f02:	2000      	movs	r0, #0
 8010f04:	f001 f93c 	bl	8012180 <xTaskNotifyWait>
			pxStreamBuffer->xTaskWaitingToSend = NULL;
 8010f08:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010f0a:	2200      	movs	r2, #0
 8010f0c:	615a      	str	r2, [r3, #20]

		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
 8010f0e:	463a      	mov	r2, r7
 8010f10:	f107 0310 	add.w	r3, r7, #16
 8010f14:	4611      	mov	r1, r2
 8010f16:	4618      	mov	r0, r3
 8010f18:	f000 fe48 	bl	8011bac <xTaskCheckForTimeOut>
 8010f1c:	4603      	mov	r3, r0
 8010f1e:	2b00      	cmp	r3, #0
 8010f20:	d0c4      	beq.n	8010eac <xStreamBufferSend+0x98>
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	if( xSpace == ( size_t ) 0 )
 8010f22:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8010f24:	2b00      	cmp	r3, #0
 8010f26:	d103      	bne.n	8010f30 <xStreamBufferSend+0x11c>
	{
		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
 8010f28:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8010f2a:	f7ff ff3f 	bl	8010dac <xStreamBufferSpacesAvailable>
 8010f2e:	6378      	str	r0, [r7, #52]	@ 0x34
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
 8010f30:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8010f32:	9300      	str	r3, [sp, #0]
 8010f34:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8010f36:	687a      	ldr	r2, [r7, #4]
 8010f38:	68b9      	ldr	r1, [r7, #8]
 8010f3a:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8010f3c:	f000 f823 	bl	8010f86 <prvWriteMessageToBuffer>
 8010f40:	62b8      	str	r0, [r7, #40]	@ 0x28

	if( xReturn > ( size_t ) 0 )
 8010f42:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8010f44:	2b00      	cmp	r3, #0
 8010f46:	d019      	beq.n	8010f7c <xStreamBufferSend+0x168>
	{
		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );

		/* Was a task waiting for the data? */
		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
 8010f48:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8010f4a:	f000 f8ce 	bl	80110ea <prvBytesInBuffer>
 8010f4e:	4602      	mov	r2, r0
 8010f50:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010f52:	68db      	ldr	r3, [r3, #12]
 8010f54:	429a      	cmp	r2, r3
 8010f56:	d311      	bcc.n	8010f7c <xStreamBufferSend+0x168>
		{
			sbSEND_COMPLETED( pxStreamBuffer );
 8010f58:	f000 fb4a 	bl	80115f0 <vTaskSuspendAll>
 8010f5c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010f5e:	691b      	ldr	r3, [r3, #16]
 8010f60:	2b00      	cmp	r3, #0
 8010f62:	d009      	beq.n	8010f78 <xStreamBufferSend+0x164>
 8010f64:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010f66:	6918      	ldr	r0, [r3, #16]
 8010f68:	2300      	movs	r3, #0
 8010f6a:	2200      	movs	r2, #0
 8010f6c:	2100      	movs	r1, #0
 8010f6e:	f001 f967 	bl	8012240 <xTaskGenericNotify>
 8010f72:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010f74:	2200      	movs	r2, #0
 8010f76:	611a      	str	r2, [r3, #16]
 8010f78:	f000 fb48 	bl	801160c <xTaskResumeAll>
	{
		mtCOVERAGE_TEST_MARKER();
		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
	}

	return xReturn;
 8010f7c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
}
 8010f7e:	4618      	mov	r0, r3
 8010f80:	3738      	adds	r7, #56	@ 0x38
 8010f82:	46bd      	mov	sp, r7
 8010f84:	bd80      	pop	{r7, pc}

08010f86 <prvWriteMessageToBuffer>:
static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
									   const void * pvTxData,
									   size_t xDataLengthBytes,
									   size_t xSpace,
									   size_t xRequiredSpace )
{
 8010f86:	b580      	push	{r7, lr}
 8010f88:	b086      	sub	sp, #24
 8010f8a:	af00      	add	r7, sp, #0
 8010f8c:	60f8      	str	r0, [r7, #12]
 8010f8e:	60b9      	str	r1, [r7, #8]
 8010f90:	607a      	str	r2, [r7, #4]
 8010f92:	603b      	str	r3, [r7, #0]
	BaseType_t xShouldWrite;
	size_t xReturn;

	if( xSpace == ( size_t ) 0 )
 8010f94:	683b      	ldr	r3, [r7, #0]
 8010f96:	2b00      	cmp	r3, #0
 8010f98:	d102      	bne.n	8010fa0 <prvWriteMessageToBuffer+0x1a>
	{
		/* Doesn't matter if this is a stream buffer or a message buffer, there
		is no space to write. */
		xShouldWrite = pdFALSE;
 8010f9a:	2300      	movs	r3, #0
 8010f9c:	617b      	str	r3, [r7, #20]
 8010f9e:	e01d      	b.n	8010fdc <prvWriteMessageToBuffer+0x56>
	}
	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
 8010fa0:	68fb      	ldr	r3, [r7, #12]
 8010fa2:	7f1b      	ldrb	r3, [r3, #28]
 8010fa4:	f003 0301 	and.w	r3, r3, #1
 8010fa8:	2b00      	cmp	r3, #0
 8010faa:	d108      	bne.n	8010fbe <prvWriteMessageToBuffer+0x38>
	{
		/* This is a stream buffer, as opposed to a message buffer, so writing a
		stream of bytes rather than discrete messages.  Write as many bytes as
		possible. */
		xShouldWrite = pdTRUE;
 8010fac:	2301      	movs	r3, #1
 8010fae:	617b      	str	r3, [r7, #20]
		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
 8010fb0:	687a      	ldr	r2, [r7, #4]
 8010fb2:	683b      	ldr	r3, [r7, #0]
 8010fb4:	4293      	cmp	r3, r2
 8010fb6:	bf28      	it	cs
 8010fb8:	4613      	movcs	r3, r2
 8010fba:	607b      	str	r3, [r7, #4]
 8010fbc:	e00e      	b.n	8010fdc <prvWriteMessageToBuffer+0x56>
	}
	else if( xSpace >= xRequiredSpace )
 8010fbe:	683a      	ldr	r2, [r7, #0]
 8010fc0:	6a3b      	ldr	r3, [r7, #32]
 8010fc2:	429a      	cmp	r2, r3
 8010fc4:	d308      	bcc.n	8010fd8 <prvWriteMessageToBuffer+0x52>
	{
		/* This is a message buffer, as opposed to a stream buffer, and there
		is enough space to write both the message length and the message itself
		into the buffer.  Start by writing the length of the data, the data
		itself will be written later in this function. */
		xShouldWrite = pdTRUE;
 8010fc6:	2301      	movs	r3, #1
 8010fc8:	617b      	str	r3, [r7, #20]
		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
 8010fca:	1d3b      	adds	r3, r7, #4
 8010fcc:	2204      	movs	r2, #4
 8010fce:	4619      	mov	r1, r3
 8010fd0:	68f8      	ldr	r0, [r7, #12]
 8010fd2:	f000 f815 	bl	8011000 <prvWriteBytesToBuffer>
 8010fd6:	e001      	b.n	8010fdc <prvWriteMessageToBuffer+0x56>
	}
	else
	{
		/* There is space available, but not enough space. */
		xShouldWrite = pdFALSE;
 8010fd8:	2300      	movs	r3, #0
 8010fda:	617b      	str	r3, [r7, #20]
	}

	if( xShouldWrite != pdFALSE )
 8010fdc:	697b      	ldr	r3, [r7, #20]
 8010fde:	2b00      	cmp	r3, #0
 8010fe0:	d007      	beq.n	8010ff2 <prvWriteMessageToBuffer+0x6c>
	{
		/* Writes the data itself. */
		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
 8010fe2:	687b      	ldr	r3, [r7, #4]
 8010fe4:	461a      	mov	r2, r3
 8010fe6:	68b9      	ldr	r1, [r7, #8]
 8010fe8:	68f8      	ldr	r0, [r7, #12]
 8010fea:	f000 f809 	bl	8011000 <prvWriteBytesToBuffer>
 8010fee:	6138      	str	r0, [r7, #16]
 8010ff0:	e001      	b.n	8010ff6 <prvWriteMessageToBuffer+0x70>
	}
	else
	{
		xReturn = 0;
 8010ff2:	2300      	movs	r3, #0
 8010ff4:	613b      	str	r3, [r7, #16]
	}

	return xReturn;
 8010ff6:	693b      	ldr	r3, [r7, #16]
}
 8010ff8:	4618      	mov	r0, r3
 8010ffa:	3718      	adds	r7, #24
 8010ffc:	46bd      	mov	sp, r7
 8010ffe:	bd80      	pop	{r7, pc}

08011000 <prvWriteBytesToBuffer>:
	return xReturn;
}
/*-----------------------------------------------------------*/

static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
{
 8011000:	b580      	push	{r7, lr}
 8011002:	b08a      	sub	sp, #40	@ 0x28
 8011004:	af00      	add	r7, sp, #0
 8011006:	60f8      	str	r0, [r7, #12]
 8011008:	60b9      	str	r1, [r7, #8]
 801100a:	607a      	str	r2, [r7, #4]
size_t xNextHead, xFirstLength;

	configASSERT( xCount > ( size_t ) 0 );
 801100c:	687b      	ldr	r3, [r7, #4]
 801100e:	2b00      	cmp	r3, #0
 8011010:	d10b      	bne.n	801102a <prvWriteBytesToBuffer+0x2a>
	__asm volatile
 8011012:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011016:	f383 8811 	msr	BASEPRI, r3
 801101a:	f3bf 8f6f 	isb	sy
 801101e:	f3bf 8f4f 	dsb	sy
 8011022:	61fb      	str	r3, [r7, #28]
}
 8011024:	bf00      	nop
 8011026:	bf00      	nop
 8011028:	e7fd      	b.n	8011026 <prvWriteBytesToBuffer+0x26>

	xNextHead = pxStreamBuffer->xHead;
 801102a:	68fb      	ldr	r3, [r7, #12]
 801102c:	685b      	ldr	r3, [r3, #4]
 801102e:	627b      	str	r3, [r7, #36]	@ 0x24

	/* Calculate the number of bytes that can be added in the first write -
	which may be less than the total number of bytes that need to be added if
	the buffer will wrap back to the beginning. */
	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
 8011030:	68fb      	ldr	r3, [r7, #12]
 8011032:	689a      	ldr	r2, [r3, #8]
 8011034:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8011036:	1ad3      	subs	r3, r2, r3
 8011038:	687a      	ldr	r2, [r7, #4]
 801103a:	4293      	cmp	r3, r2
 801103c:	bf28      	it	cs
 801103e:	4613      	movcs	r3, r2
 8011040:	623b      	str	r3, [r7, #32]

	/* Write as many bytes as can be written in the first write. */
	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
 8011042:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8011044:	6a3b      	ldr	r3, [r7, #32]
 8011046:	441a      	add	r2, r3
 8011048:	68fb      	ldr	r3, [r7, #12]
 801104a:	689b      	ldr	r3, [r3, #8]
 801104c:	429a      	cmp	r2, r3
 801104e:	d90b      	bls.n	8011068 <prvWriteBytesToBuffer+0x68>
	__asm volatile
 8011050:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011054:	f383 8811 	msr	BASEPRI, r3
 8011058:	f3bf 8f6f 	isb	sy
 801105c:	f3bf 8f4f 	dsb	sy
 8011060:	61bb      	str	r3, [r7, #24]
}
 8011062:	bf00      	nop
 8011064:	bf00      	nop
 8011066:	e7fd      	b.n	8011064 <prvWriteBytesToBuffer+0x64>
	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
 8011068:	68fb      	ldr	r3, [r7, #12]
 801106a:	699a      	ldr	r2, [r3, #24]
 801106c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 801106e:	4413      	add	r3, r2
 8011070:	6a3a      	ldr	r2, [r7, #32]
 8011072:	68b9      	ldr	r1, [r7, #8]
 8011074:	4618      	mov	r0, r3
 8011076:	f002 fc88 	bl	801398a <memcpy>

	/* If the number of bytes written was less than the number that could be
	written in the first write... */
	if( xCount > xFirstLength )
 801107a:	687a      	ldr	r2, [r7, #4]
 801107c:	6a3b      	ldr	r3, [r7, #32]
 801107e:	429a      	cmp	r2, r3
 8011080:	d91d      	bls.n	80110be <prvWriteBytesToBuffer+0xbe>
	{
		/* ...then write the remaining bytes to the start of the buffer. */
		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
 8011082:	687a      	ldr	r2, [r7, #4]
 8011084:	6a3b      	ldr	r3, [r7, #32]
 8011086:	1ad2      	subs	r2, r2, r3
 8011088:	68fb      	ldr	r3, [r7, #12]
 801108a:	689b      	ldr	r3, [r3, #8]
 801108c:	429a      	cmp	r2, r3
 801108e:	d90b      	bls.n	80110a8 <prvWriteBytesToBuffer+0xa8>
	__asm volatile
 8011090:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011094:	f383 8811 	msr	BASEPRI, r3
 8011098:	f3bf 8f6f 	isb	sy
 801109c:	f3bf 8f4f 	dsb	sy
 80110a0:	617b      	str	r3, [r7, #20]
}
 80110a2:	bf00      	nop
 80110a4:	bf00      	nop
 80110a6:	e7fd      	b.n	80110a4 <prvWriteBytesToBuffer+0xa4>
		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
 80110a8:	68fb      	ldr	r3, [r7, #12]
 80110aa:	6998      	ldr	r0, [r3, #24]
 80110ac:	68ba      	ldr	r2, [r7, #8]
 80110ae:	6a3b      	ldr	r3, [r7, #32]
 80110b0:	18d1      	adds	r1, r2, r3
 80110b2:	687a      	ldr	r2, [r7, #4]
 80110b4:	6a3b      	ldr	r3, [r7, #32]
 80110b6:	1ad3      	subs	r3, r2, r3
 80110b8:	461a      	mov	r2, r3
 80110ba:	f002 fc66 	bl	801398a <memcpy>
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	xNextHead += xCount;
 80110be:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 80110c0:	687b      	ldr	r3, [r7, #4]
 80110c2:	4413      	add	r3, r2
 80110c4:	627b      	str	r3, [r7, #36]	@ 0x24
	if( xNextHead >= pxStreamBuffer->xLength )
 80110c6:	68fb      	ldr	r3, [r7, #12]
 80110c8:	689b      	ldr	r3, [r3, #8]
 80110ca:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 80110cc:	429a      	cmp	r2, r3
 80110ce:	d304      	bcc.n	80110da <prvWriteBytesToBuffer+0xda>
	{
		xNextHead -= pxStreamBuffer->xLength;
 80110d0:	68fb      	ldr	r3, [r7, #12]
 80110d2:	689b      	ldr	r3, [r3, #8]
 80110d4:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 80110d6:	1ad3      	subs	r3, r2, r3
 80110d8:	627b      	str	r3, [r7, #36]	@ 0x24
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxStreamBuffer->xHead = xNextHead;
 80110da:	68fb      	ldr	r3, [r7, #12]
 80110dc:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 80110de:	605a      	str	r2, [r3, #4]

	return xCount;
 80110e0:	687b      	ldr	r3, [r7, #4]
}
 80110e2:	4618      	mov	r0, r3
 80110e4:	3728      	adds	r7, #40	@ 0x28
 80110e6:	46bd      	mov	sp, r7
 80110e8:	bd80      	pop	{r7, pc}

080110ea <prvBytesInBuffer>:
	return xCount;
}
/*-----------------------------------------------------------*/

static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
{
 80110ea:	b480      	push	{r7}
 80110ec:	b085      	sub	sp, #20
 80110ee:	af00      	add	r7, sp, #0
 80110f0:	6078      	str	r0, [r7, #4]
/* Returns the distance between xTail and xHead. */
size_t xCount;

	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
 80110f2:	687b      	ldr	r3, [r7, #4]
 80110f4:	689a      	ldr	r2, [r3, #8]
 80110f6:	687b      	ldr	r3, [r7, #4]
 80110f8:	685b      	ldr	r3, [r3, #4]
 80110fa:	4413      	add	r3, r2
 80110fc:	60fb      	str	r3, [r7, #12]
	xCount -= pxStreamBuffer->xTail;
 80110fe:	687b      	ldr	r3, [r7, #4]
 8011100:	681b      	ldr	r3, [r3, #0]
 8011102:	68fa      	ldr	r2, [r7, #12]
 8011104:	1ad3      	subs	r3, r2, r3
 8011106:	60fb      	str	r3, [r7, #12]
	if ( xCount >= pxStreamBuffer->xLength )
 8011108:	687b      	ldr	r3, [r7, #4]
 801110a:	689b      	ldr	r3, [r3, #8]
 801110c:	68fa      	ldr	r2, [r7, #12]
 801110e:	429a      	cmp	r2, r3
 8011110:	d304      	bcc.n	801111c <prvBytesInBuffer+0x32>
	{
		xCount -= pxStreamBuffer->xLength;
 8011112:	687b      	ldr	r3, [r7, #4]
 8011114:	689b      	ldr	r3, [r3, #8]
 8011116:	68fa      	ldr	r2, [r7, #12]
 8011118:	1ad3      	subs	r3, r2, r3
 801111a:	60fb      	str	r3, [r7, #12]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	return xCount;
 801111c:	68fb      	ldr	r3, [r7, #12]
}
 801111e:	4618      	mov	r0, r3
 8011120:	3714      	adds	r7, #20
 8011122:	46bd      	mov	sp, r7
 8011124:	f85d 7b04 	ldr.w	r7, [sp], #4
 8011128:	4770      	bx	lr

0801112a <xTaskCreateStatic>:
									const uint32_t ulStackDepth,
									void * const pvParameters,
									UBaseType_t uxPriority,
									StackType_t * const puxStackBuffer,
									StaticTask_t * const pxTaskBuffer )
	{
 801112a:	b580      	push	{r7, lr}
 801112c:	b08e      	sub	sp, #56	@ 0x38
 801112e:	af04      	add	r7, sp, #16
 8011130:	60f8      	str	r0, [r7, #12]
 8011132:	60b9      	str	r1, [r7, #8]
 8011134:	607a      	str	r2, [r7, #4]
 8011136:	603b      	str	r3, [r7, #0]
	TCB_t *pxNewTCB;
	TaskHandle_t xReturn;

		configASSERT( puxStackBuffer != NULL );
 8011138:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 801113a:	2b00      	cmp	r3, #0
 801113c:	d10b      	bne.n	8011156 <xTaskCreateStatic+0x2c>
	__asm volatile
 801113e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011142:	f383 8811 	msr	BASEPRI, r3
 8011146:	f3bf 8f6f 	isb	sy
 801114a:	f3bf 8f4f 	dsb	sy
 801114e:	623b      	str	r3, [r7, #32]
}
 8011150:	bf00      	nop
 8011152:	bf00      	nop
 8011154:	e7fd      	b.n	8011152 <xTaskCreateStatic+0x28>
		configASSERT( pxTaskBuffer != NULL );
 8011156:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8011158:	2b00      	cmp	r3, #0
 801115a:	d10b      	bne.n	8011174 <xTaskCreateStatic+0x4a>
	__asm volatile
 801115c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011160:	f383 8811 	msr	BASEPRI, r3
 8011164:	f3bf 8f6f 	isb	sy
 8011168:	f3bf 8f4f 	dsb	sy
 801116c:	61fb      	str	r3, [r7, #28]
}
 801116e:	bf00      	nop
 8011170:	bf00      	nop
 8011172:	e7fd      	b.n	8011170 <xTaskCreateStatic+0x46>
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticTask_t equals the size of the real task
			structure. */
			volatile size_t xSize = sizeof( StaticTask_t );
 8011174:	23a8      	movs	r3, #168	@ 0xa8
 8011176:	613b      	str	r3, [r7, #16]
			configASSERT( xSize == sizeof( TCB_t ) );
 8011178:	693b      	ldr	r3, [r7, #16]
 801117a:	2ba8      	cmp	r3, #168	@ 0xa8
 801117c:	d00b      	beq.n	8011196 <xTaskCreateStatic+0x6c>
	__asm volatile
 801117e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011182:	f383 8811 	msr	BASEPRI, r3
 8011186:	f3bf 8f6f 	isb	sy
 801118a:	f3bf 8f4f 	dsb	sy
 801118e:	61bb      	str	r3, [r7, #24]
}
 8011190:	bf00      	nop
 8011192:	bf00      	nop
 8011194:	e7fd      	b.n	8011192 <xTaskCreateStatic+0x68>
			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
 8011196:	693b      	ldr	r3, [r7, #16]
		}
		#endif /* configASSERT_DEFINED */


		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
 8011198:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 801119a:	2b00      	cmp	r3, #0
 801119c:	d01e      	beq.n	80111dc <xTaskCreateStatic+0xb2>
 801119e:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80111a0:	2b00      	cmp	r3, #0
 80111a2:	d01b      	beq.n	80111dc <xTaskCreateStatic+0xb2>
		{
			/* The memory used for the task's TCB and stack are passed into this
			function - use them. */
			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 80111a4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80111a6:	627b      	str	r3, [r7, #36]	@ 0x24
			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
 80111a8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80111aa:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 80111ac:	631a      	str	r2, [r3, #48]	@ 0x30

			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
			{
				/* Tasks can be created statically or dynamically, so note this
				task was created statically in case the task is later deleted. */
				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
 80111ae:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80111b0:	2202      	movs	r2, #2
 80111b2:	f883 20a5 	strb.w	r2, [r3, #165]	@ 0xa5
			}
			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
 80111b6:	2300      	movs	r3, #0
 80111b8:	9303      	str	r3, [sp, #12]
 80111ba:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80111bc:	9302      	str	r3, [sp, #8]
 80111be:	f107 0314 	add.w	r3, r7, #20
 80111c2:	9301      	str	r3, [sp, #4]
 80111c4:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80111c6:	9300      	str	r3, [sp, #0]
 80111c8:	683b      	ldr	r3, [r7, #0]
 80111ca:	687a      	ldr	r2, [r7, #4]
 80111cc:	68b9      	ldr	r1, [r7, #8]
 80111ce:	68f8      	ldr	r0, [r7, #12]
 80111d0:	f000 f850 	bl	8011274 <prvInitialiseNewTask>
			prvAddNewTaskToReadyList( pxNewTCB );
 80111d4:	6a78      	ldr	r0, [r7, #36]	@ 0x24
 80111d6:	f000 f8f5 	bl	80113c4 <prvAddNewTaskToReadyList>
 80111da:	e001      	b.n	80111e0 <xTaskCreateStatic+0xb6>
		}
		else
		{
			xReturn = NULL;
 80111dc:	2300      	movs	r3, #0
 80111de:	617b      	str	r3, [r7, #20]
		}

		return xReturn;
 80111e0:	697b      	ldr	r3, [r7, #20]
	}
 80111e2:	4618      	mov	r0, r3
 80111e4:	3728      	adds	r7, #40	@ 0x28
 80111e6:	46bd      	mov	sp, r7
 80111e8:	bd80      	pop	{r7, pc}

080111ea <xTaskCreate>:
							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
							const configSTACK_DEPTH_TYPE usStackDepth,
							void * const pvParameters,
							UBaseType_t uxPriority,
							TaskHandle_t * const pxCreatedTask )
	{
 80111ea:	b580      	push	{r7, lr}
 80111ec:	b08c      	sub	sp, #48	@ 0x30
 80111ee:	af04      	add	r7, sp, #16
 80111f0:	60f8      	str	r0, [r7, #12]
 80111f2:	60b9      	str	r1, [r7, #8]
 80111f4:	603b      	str	r3, [r7, #0]
 80111f6:	4613      	mov	r3, r2
 80111f8:	80fb      	strh	r3, [r7, #6]
		#else /* portSTACK_GROWTH */
		{
		StackType_t *pxStack;

			/* Allocate space for the stack used by the task being created. */
			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
 80111fa:	88fb      	ldrh	r3, [r7, #6]
 80111fc:	009b      	lsls	r3, r3, #2
 80111fe:	4618      	mov	r0, r3
 8011200:	f001 ffec 	bl	80131dc <pvPortMalloc>
 8011204:	6178      	str	r0, [r7, #20]

			if( pxStack != NULL )
 8011206:	697b      	ldr	r3, [r7, #20]
 8011208:	2b00      	cmp	r3, #0
 801120a:	d00e      	beq.n	801122a <xTaskCreate+0x40>
			{
				/* Allocate space for the TCB. */
				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
 801120c:	20a8      	movs	r0, #168	@ 0xa8
 801120e:	f001 ffe5 	bl	80131dc <pvPortMalloc>
 8011212:	61f8      	str	r0, [r7, #28]

				if( pxNewTCB != NULL )
 8011214:	69fb      	ldr	r3, [r7, #28]
 8011216:	2b00      	cmp	r3, #0
 8011218:	d003      	beq.n	8011222 <xTaskCreate+0x38>
				{
					/* Store the stack location in the TCB. */
					pxNewTCB->pxStack = pxStack;
 801121a:	69fb      	ldr	r3, [r7, #28]
 801121c:	697a      	ldr	r2, [r7, #20]
 801121e:	631a      	str	r2, [r3, #48]	@ 0x30
 8011220:	e005      	b.n	801122e <xTaskCreate+0x44>
				}
				else
				{
					/* The stack cannot be used as the TCB was not created.  Free
					it again. */
					vPortFree( pxStack );
 8011222:	6978      	ldr	r0, [r7, #20]
 8011224:	f002 f8a8 	bl	8013378 <vPortFree>
 8011228:	e001      	b.n	801122e <xTaskCreate+0x44>
				}
			}
			else
			{
				pxNewTCB = NULL;
 801122a:	2300      	movs	r3, #0
 801122c:	61fb      	str	r3, [r7, #28]
			}
		}
		#endif /* portSTACK_GROWTH */

		if( pxNewTCB != NULL )
 801122e:	69fb      	ldr	r3, [r7, #28]
 8011230:	2b00      	cmp	r3, #0
 8011232:	d017      	beq.n	8011264 <xTaskCreate+0x7a>
		{
			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
			{
				/* Tasks can be created statically or dynamically, so note this
				task was created dynamically in case it is later deleted. */
				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
 8011234:	69fb      	ldr	r3, [r7, #28]
 8011236:	2200      	movs	r2, #0
 8011238:	f883 20a5 	strb.w	r2, [r3, #165]	@ 0xa5
			}
			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
 801123c:	88fa      	ldrh	r2, [r7, #6]
 801123e:	2300      	movs	r3, #0
 8011240:	9303      	str	r3, [sp, #12]
 8011242:	69fb      	ldr	r3, [r7, #28]
 8011244:	9302      	str	r3, [sp, #8]
 8011246:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8011248:	9301      	str	r3, [sp, #4]
 801124a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 801124c:	9300      	str	r3, [sp, #0]
 801124e:	683b      	ldr	r3, [r7, #0]
 8011250:	68b9      	ldr	r1, [r7, #8]
 8011252:	68f8      	ldr	r0, [r7, #12]
 8011254:	f000 f80e 	bl	8011274 <prvInitialiseNewTask>
			prvAddNewTaskToReadyList( pxNewTCB );
 8011258:	69f8      	ldr	r0, [r7, #28]
 801125a:	f000 f8b3 	bl	80113c4 <prvAddNewTaskToReadyList>
			xReturn = pdPASS;
 801125e:	2301      	movs	r3, #1
 8011260:	61bb      	str	r3, [r7, #24]
 8011262:	e002      	b.n	801126a <xTaskCreate+0x80>
		}
		else
		{
			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
 8011264:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8011268:	61bb      	str	r3, [r7, #24]
		}

		return xReturn;
 801126a:	69bb      	ldr	r3, [r7, #24]
	}
 801126c:	4618      	mov	r0, r3
 801126e:	3720      	adds	r7, #32
 8011270:	46bd      	mov	sp, r7
 8011272:	bd80      	pop	{r7, pc}

08011274 <prvInitialiseNewTask>:
									void * const pvParameters,
									UBaseType_t uxPriority,
									TaskHandle_t * const pxCreatedTask,
									TCB_t *pxNewTCB,
									const MemoryRegion_t * const xRegions )
{
 8011274:	b580      	push	{r7, lr}
 8011276:	b088      	sub	sp, #32
 8011278:	af00      	add	r7, sp, #0
 801127a:	60f8      	str	r0, [r7, #12]
 801127c:	60b9      	str	r1, [r7, #8]
 801127e:	607a      	str	r2, [r7, #4]
 8011280:	603b      	str	r3, [r7, #0]

	/* Avoid dependency on memset() if it is not required. */
	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
	{
		/* Fill the stack with a known value to assist debugging. */
		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
 8011282:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8011284:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 8011286:	687b      	ldr	r3, [r7, #4]
 8011288:	009b      	lsls	r3, r3, #2
 801128a:	461a      	mov	r2, r3
 801128c:	21a5      	movs	r1, #165	@ 0xa5
 801128e:	f002 faaa 	bl	80137e6 <memset>
	grows from high memory to low (as per the 80x86) or vice versa.
	portSTACK_GROWTH is used to make the result positive or negative as required
	by the port. */
	#if( portSTACK_GROWTH < 0 )
	{
		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
 8011292:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8011294:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
 8011296:	6879      	ldr	r1, [r7, #4]
 8011298:	f06f 4340 	mvn.w	r3, #3221225472	@ 0xc0000000
 801129c:	440b      	add	r3, r1
 801129e:	009b      	lsls	r3, r3, #2
 80112a0:	4413      	add	r3, r2
 80112a2:	61bb      	str	r3, [r7, #24]
		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
 80112a4:	69bb      	ldr	r3, [r7, #24]
 80112a6:	f023 0307 	bic.w	r3, r3, #7
 80112aa:	61bb      	str	r3, [r7, #24]

		/* Check the alignment of the calculated top of stack is correct. */
		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
 80112ac:	69bb      	ldr	r3, [r7, #24]
 80112ae:	f003 0307 	and.w	r3, r3, #7
 80112b2:	2b00      	cmp	r3, #0
 80112b4:	d00b      	beq.n	80112ce <prvInitialiseNewTask+0x5a>
	__asm volatile
 80112b6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80112ba:	f383 8811 	msr	BASEPRI, r3
 80112be:	f3bf 8f6f 	isb	sy
 80112c2:	f3bf 8f4f 	dsb	sy
 80112c6:	617b      	str	r3, [r7, #20]
}
 80112c8:	bf00      	nop
 80112ca:	bf00      	nop
 80112cc:	e7fd      	b.n	80112ca <prvInitialiseNewTask+0x56>
		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
	}
	#endif /* portSTACK_GROWTH */

	/* Store the task name in the TCB. */
	if( pcName != NULL )
 80112ce:	68bb      	ldr	r3, [r7, #8]
 80112d0:	2b00      	cmp	r3, #0
 80112d2:	d01f      	beq.n	8011314 <prvInitialiseNewTask+0xa0>
	{
		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 80112d4:	2300      	movs	r3, #0
 80112d6:	61fb      	str	r3, [r7, #28]
 80112d8:	e012      	b.n	8011300 <prvInitialiseNewTask+0x8c>
		{
			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
 80112da:	68ba      	ldr	r2, [r7, #8]
 80112dc:	69fb      	ldr	r3, [r7, #28]
 80112de:	4413      	add	r3, r2
 80112e0:	7819      	ldrb	r1, [r3, #0]
 80112e2:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 80112e4:	69fb      	ldr	r3, [r7, #28]
 80112e6:	4413      	add	r3, r2
 80112e8:	3334      	adds	r3, #52	@ 0x34
 80112ea:	460a      	mov	r2, r1
 80112ec:	701a      	strb	r2, [r3, #0]

			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
			configMAX_TASK_NAME_LEN characters just in case the memory after the
			string is not accessible (extremely unlikely). */
			if( pcName[ x ] == ( char ) 0x00 )
 80112ee:	68ba      	ldr	r2, [r7, #8]
 80112f0:	69fb      	ldr	r3, [r7, #28]
 80112f2:	4413      	add	r3, r2
 80112f4:	781b      	ldrb	r3, [r3, #0]
 80112f6:	2b00      	cmp	r3, #0
 80112f8:	d006      	beq.n	8011308 <prvInitialiseNewTask+0x94>
		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 80112fa:	69fb      	ldr	r3, [r7, #28]
 80112fc:	3301      	adds	r3, #1
 80112fe:	61fb      	str	r3, [r7, #28]
 8011300:	69fb      	ldr	r3, [r7, #28]
 8011302:	2b0f      	cmp	r3, #15
 8011304:	d9e9      	bls.n	80112da <prvInitialiseNewTask+0x66>
 8011306:	e000      	b.n	801130a <prvInitialiseNewTask+0x96>
			{
				break;
 8011308:	bf00      	nop
			}
		}

		/* Ensure the name string is terminated in the case that the string length
		was greater or equal to configMAX_TASK_NAME_LEN. */
		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
 801130a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801130c:	2200      	movs	r2, #0
 801130e:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
 8011312:	e003      	b.n	801131c <prvInitialiseNewTask+0xa8>
	}
	else
	{
		/* The task has not been given a name, so just ensure there is a NULL
		terminator when it is read out. */
		pxNewTCB->pcTaskName[ 0 ] = 0x00;
 8011314:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8011316:	2200      	movs	r2, #0
 8011318:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
	}

	/* This is used as an array index so must ensure it's not too large.  First
	remove the privilege bit if one is present. */
	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
 801131c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 801131e:	2b37      	cmp	r3, #55	@ 0x37
 8011320:	d901      	bls.n	8011326 <prvInitialiseNewTask+0xb2>
	{
		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
 8011322:	2337      	movs	r3, #55	@ 0x37
 8011324:	62bb      	str	r3, [r7, #40]	@ 0x28
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxNewTCB->uxPriority = uxPriority;
 8011326:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8011328:	6aba      	ldr	r2, [r7, #40]	@ 0x28
 801132a:	62da      	str	r2, [r3, #44]	@ 0x2c
	#if ( configUSE_MUTEXES == 1 )
	{
		pxNewTCB->uxBasePriority = uxPriority;
 801132c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801132e:	6aba      	ldr	r2, [r7, #40]	@ 0x28
 8011330:	64da      	str	r2, [r3, #76]	@ 0x4c
		pxNewTCB->uxMutexesHeld = 0;
 8011332:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8011334:	2200      	movs	r2, #0
 8011336:	651a      	str	r2, [r3, #80]	@ 0x50
	}
	#endif /* configUSE_MUTEXES */

	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
 8011338:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801133a:	3304      	adds	r3, #4
 801133c:	4618      	mov	r0, r3
 801133e:	f7fe fd09 	bl	800fd54 <vListInitialiseItem>
	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
 8011342:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8011344:	3318      	adds	r3, #24
 8011346:	4618      	mov	r0, r3
 8011348:	f7fe fd04 	bl	800fd54 <vListInitialiseItem>

	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
	back to	the containing TCB from a generic item in a list. */
	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
 801134c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801134e:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8011350:	611a      	str	r2, [r3, #16]

	/* Event lists are always in priority order. */
	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8011352:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8011354:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 8011358:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801135a:	619a      	str	r2, [r3, #24]
	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
 801135c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801135e:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8011360:	625a      	str	r2, [r3, #36]	@ 0x24
	}
	#endif

	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
	{
		pxNewTCB->ulNotifiedValue = 0;
 8011362:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8011364:	2200      	movs	r2, #0
 8011366:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
 801136a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801136c:	2200      	movs	r2, #0
 801136e:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4
	#if ( configUSE_NEWLIB_REENTRANT == 1 )
	{
		/* Initialise this task's Newlib reent structure.
		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
		for additional information. */
		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
 8011372:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8011374:	3354      	adds	r3, #84	@ 0x54
 8011376:	224c      	movs	r2, #76	@ 0x4c
 8011378:	2100      	movs	r1, #0
 801137a:	4618      	mov	r0, r3
 801137c:	f002 fa33 	bl	80137e6 <memset>
 8011380:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8011382:	4a0d      	ldr	r2, [pc, #52]	@ (80113b8 <prvInitialiseNewTask+0x144>)
 8011384:	659a      	str	r2, [r3, #88]	@ 0x58
 8011386:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8011388:	4a0c      	ldr	r2, [pc, #48]	@ (80113bc <prvInitialiseNewTask+0x148>)
 801138a:	65da      	str	r2, [r3, #92]	@ 0x5c
 801138c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801138e:	4a0c      	ldr	r2, [pc, #48]	@ (80113c0 <prvInitialiseNewTask+0x14c>)
 8011390:	661a      	str	r2, [r3, #96]	@ 0x60
			}
			#endif /* portSTACK_GROWTH */
		}
		#else /* portHAS_STACK_OVERFLOW_CHECKING */
		{
			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
 8011392:	683a      	ldr	r2, [r7, #0]
 8011394:	68f9      	ldr	r1, [r7, #12]
 8011396:	69b8      	ldr	r0, [r7, #24]
 8011398:	f001 fcce 	bl	8012d38 <pxPortInitialiseStack>
 801139c:	4602      	mov	r2, r0
 801139e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80113a0:	601a      	str	r2, [r3, #0]
		}
		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
	}
	#endif /* portUSING_MPU_WRAPPERS */

	if( pxCreatedTask != NULL )
 80113a2:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80113a4:	2b00      	cmp	r3, #0
 80113a6:	d002      	beq.n	80113ae <prvInitialiseNewTask+0x13a>
	{
		/* Pass the handle out in an anonymous way.  The handle can be used to
		change the created task's priority, delete the created task, etc.*/
		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
 80113a8:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80113aa:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 80113ac:	601a      	str	r2, [r3, #0]
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 80113ae:	bf00      	nop
 80113b0:	3720      	adds	r7, #32
 80113b2:	46bd      	mov	sp, r7
 80113b4:	bd80      	pop	{r7, pc}
 80113b6:	bf00      	nop
 80113b8:	24012a48 	.word	0x24012a48
 80113bc:	24012ab0 	.word	0x24012ab0
 80113c0:	24012b18 	.word	0x24012b18

080113c4 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/

static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
 80113c4:	b580      	push	{r7, lr}
 80113c6:	b082      	sub	sp, #8
 80113c8:	af00      	add	r7, sp, #0
 80113ca:	6078      	str	r0, [r7, #4]
	/* Ensure interrupts don't access the task lists while the lists are being
	updated. */
	taskENTER_CRITICAL();
 80113cc:	f001 fde4 	bl	8012f98 <vPortEnterCritical>
	{
		uxCurrentNumberOfTasks++;
 80113d0:	4b2d      	ldr	r3, [pc, #180]	@ (8011488 <prvAddNewTaskToReadyList+0xc4>)
 80113d2:	681b      	ldr	r3, [r3, #0]
 80113d4:	3301      	adds	r3, #1
 80113d6:	4a2c      	ldr	r2, [pc, #176]	@ (8011488 <prvAddNewTaskToReadyList+0xc4>)
 80113d8:	6013      	str	r3, [r2, #0]
		if( pxCurrentTCB == NULL )
 80113da:	4b2c      	ldr	r3, [pc, #176]	@ (801148c <prvAddNewTaskToReadyList+0xc8>)
 80113dc:	681b      	ldr	r3, [r3, #0]
 80113de:	2b00      	cmp	r3, #0
 80113e0:	d109      	bne.n	80113f6 <prvAddNewTaskToReadyList+0x32>
		{
			/* There are no other tasks, or all the other tasks are in
			the suspended state - make this the current task. */
			pxCurrentTCB = pxNewTCB;
 80113e2:	4a2a      	ldr	r2, [pc, #168]	@ (801148c <prvAddNewTaskToReadyList+0xc8>)
 80113e4:	687b      	ldr	r3, [r7, #4]
 80113e6:	6013      	str	r3, [r2, #0]

			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
 80113e8:	4b27      	ldr	r3, [pc, #156]	@ (8011488 <prvAddNewTaskToReadyList+0xc4>)
 80113ea:	681b      	ldr	r3, [r3, #0]
 80113ec:	2b01      	cmp	r3, #1
 80113ee:	d110      	bne.n	8011412 <prvAddNewTaskToReadyList+0x4e>
			{
				/* This is the first task to be created so do the preliminary
				initialisation required.  We will not recover if this call
				fails, but we will report the failure. */
				prvInitialiseTaskLists();
 80113f0:	f000 fc64 	bl	8011cbc <prvInitialiseTaskLists>
 80113f4:	e00d      	b.n	8011412 <prvAddNewTaskToReadyList+0x4e>
		else
		{
			/* If the scheduler is not already running, make this task the
			current task if it is the highest priority task to be created
			so far. */
			if( xSchedulerRunning == pdFALSE )
 80113f6:	4b26      	ldr	r3, [pc, #152]	@ (8011490 <prvAddNewTaskToReadyList+0xcc>)
 80113f8:	681b      	ldr	r3, [r3, #0]
 80113fa:	2b00      	cmp	r3, #0
 80113fc:	d109      	bne.n	8011412 <prvAddNewTaskToReadyList+0x4e>
			{
				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
 80113fe:	4b23      	ldr	r3, [pc, #140]	@ (801148c <prvAddNewTaskToReadyList+0xc8>)
 8011400:	681b      	ldr	r3, [r3, #0]
 8011402:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011404:	687b      	ldr	r3, [r7, #4]
 8011406:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8011408:	429a      	cmp	r2, r3
 801140a:	d802      	bhi.n	8011412 <prvAddNewTaskToReadyList+0x4e>
				{
					pxCurrentTCB = pxNewTCB;
 801140c:	4a1f      	ldr	r2, [pc, #124]	@ (801148c <prvAddNewTaskToReadyList+0xc8>)
 801140e:	687b      	ldr	r3, [r7, #4]
 8011410:	6013      	str	r3, [r2, #0]
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}

		uxTaskNumber++;
 8011412:	4b20      	ldr	r3, [pc, #128]	@ (8011494 <prvAddNewTaskToReadyList+0xd0>)
 8011414:	681b      	ldr	r3, [r3, #0]
 8011416:	3301      	adds	r3, #1
 8011418:	4a1e      	ldr	r2, [pc, #120]	@ (8011494 <prvAddNewTaskToReadyList+0xd0>)
 801141a:	6013      	str	r3, [r2, #0]

		#if ( configUSE_TRACE_FACILITY == 1 )
		{
			/* Add a counter into the TCB for tracing only. */
			pxNewTCB->uxTCBNumber = uxTaskNumber;
 801141c:	4b1d      	ldr	r3, [pc, #116]	@ (8011494 <prvAddNewTaskToReadyList+0xd0>)
 801141e:	681a      	ldr	r2, [r3, #0]
 8011420:	687b      	ldr	r3, [r7, #4]
 8011422:	645a      	str	r2, [r3, #68]	@ 0x44
		}
		#endif /* configUSE_TRACE_FACILITY */
		traceTASK_CREATE( pxNewTCB );

		prvAddTaskToReadyList( pxNewTCB );
 8011424:	687b      	ldr	r3, [r7, #4]
 8011426:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011428:	4b1b      	ldr	r3, [pc, #108]	@ (8011498 <prvAddNewTaskToReadyList+0xd4>)
 801142a:	681b      	ldr	r3, [r3, #0]
 801142c:	429a      	cmp	r2, r3
 801142e:	d903      	bls.n	8011438 <prvAddNewTaskToReadyList+0x74>
 8011430:	687b      	ldr	r3, [r7, #4]
 8011432:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8011434:	4a18      	ldr	r2, [pc, #96]	@ (8011498 <prvAddNewTaskToReadyList+0xd4>)
 8011436:	6013      	str	r3, [r2, #0]
 8011438:	687b      	ldr	r3, [r7, #4]
 801143a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 801143c:	4613      	mov	r3, r2
 801143e:	009b      	lsls	r3, r3, #2
 8011440:	4413      	add	r3, r2
 8011442:	009b      	lsls	r3, r3, #2
 8011444:	4a15      	ldr	r2, [pc, #84]	@ (801149c <prvAddNewTaskToReadyList+0xd8>)
 8011446:	441a      	add	r2, r3
 8011448:	687b      	ldr	r3, [r7, #4]
 801144a:	3304      	adds	r3, #4
 801144c:	4619      	mov	r1, r3
 801144e:	4610      	mov	r0, r2
 8011450:	f7fe fc8d 	bl	800fd6e <vListInsertEnd>

		portSETUP_TCB( pxNewTCB );
	}
	taskEXIT_CRITICAL();
 8011454:	f001 fdd2 	bl	8012ffc <vPortExitCritical>

	if( xSchedulerRunning != pdFALSE )
 8011458:	4b0d      	ldr	r3, [pc, #52]	@ (8011490 <prvAddNewTaskToReadyList+0xcc>)
 801145a:	681b      	ldr	r3, [r3, #0]
 801145c:	2b00      	cmp	r3, #0
 801145e:	d00e      	beq.n	801147e <prvAddNewTaskToReadyList+0xba>
	{
		/* If the created task is of a higher priority than the current task
		then it should run now. */
		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
 8011460:	4b0a      	ldr	r3, [pc, #40]	@ (801148c <prvAddNewTaskToReadyList+0xc8>)
 8011462:	681b      	ldr	r3, [r3, #0]
 8011464:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011466:	687b      	ldr	r3, [r7, #4]
 8011468:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 801146a:	429a      	cmp	r2, r3
 801146c:	d207      	bcs.n	801147e <prvAddNewTaskToReadyList+0xba>
		{
			taskYIELD_IF_USING_PREEMPTION();
 801146e:	4b0c      	ldr	r3, [pc, #48]	@ (80114a0 <prvAddNewTaskToReadyList+0xdc>)
 8011470:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8011474:	601a      	str	r2, [r3, #0]
 8011476:	f3bf 8f4f 	dsb	sy
 801147a:	f3bf 8f6f 	isb	sy
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 801147e:	bf00      	nop
 8011480:	3708      	adds	r7, #8
 8011482:	46bd      	mov	sp, r7
 8011484:	bd80      	pop	{r7, pc}
 8011486:	bf00      	nop
 8011488:	240028c8 	.word	0x240028c8
 801148c:	240023f4 	.word	0x240023f4
 8011490:	240028d4 	.word	0x240028d4
 8011494:	240028e4 	.word	0x240028e4
 8011498:	240028d0 	.word	0x240028d0
 801149c:	240023f8 	.word	0x240023f8
 80114a0:	e000ed04 	.word	0xe000ed04

080114a4 <vTaskDelay>:
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelay == 1 )

	void vTaskDelay( const TickType_t xTicksToDelay )
	{
 80114a4:	b580      	push	{r7, lr}
 80114a6:	b084      	sub	sp, #16
 80114a8:	af00      	add	r7, sp, #0
 80114aa:	6078      	str	r0, [r7, #4]
	BaseType_t xAlreadyYielded = pdFALSE;
 80114ac:	2300      	movs	r3, #0
 80114ae:	60fb      	str	r3, [r7, #12]

		/* A delay time of zero just forces a reschedule. */
		if( xTicksToDelay > ( TickType_t ) 0U )
 80114b0:	687b      	ldr	r3, [r7, #4]
 80114b2:	2b00      	cmp	r3, #0
 80114b4:	d018      	beq.n	80114e8 <vTaskDelay+0x44>
		{
			configASSERT( uxSchedulerSuspended == 0 );
 80114b6:	4b14      	ldr	r3, [pc, #80]	@ (8011508 <vTaskDelay+0x64>)
 80114b8:	681b      	ldr	r3, [r3, #0]
 80114ba:	2b00      	cmp	r3, #0
 80114bc:	d00b      	beq.n	80114d6 <vTaskDelay+0x32>
	__asm volatile
 80114be:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80114c2:	f383 8811 	msr	BASEPRI, r3
 80114c6:	f3bf 8f6f 	isb	sy
 80114ca:	f3bf 8f4f 	dsb	sy
 80114ce:	60bb      	str	r3, [r7, #8]
}
 80114d0:	bf00      	nop
 80114d2:	bf00      	nop
 80114d4:	e7fd      	b.n	80114d2 <vTaskDelay+0x2e>
			vTaskSuspendAll();
 80114d6:	f000 f88b 	bl	80115f0 <vTaskSuspendAll>
				list or removed from the blocked list until the scheduler
				is resumed.

				This task cannot be in an event list as it is the currently
				executing task. */
				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
 80114da:	2100      	movs	r1, #0
 80114dc:	6878      	ldr	r0, [r7, #4]
 80114de:	f001 f87d 	bl	80125dc <prvAddCurrentTaskToDelayedList>
			}
			xAlreadyYielded = xTaskResumeAll();
 80114e2:	f000 f893 	bl	801160c <xTaskResumeAll>
 80114e6:	60f8      	str	r0, [r7, #12]
			mtCOVERAGE_TEST_MARKER();
		}

		/* Force a reschedule if xTaskResumeAll has not already done so, we may
		have put ourselves to sleep. */
		if( xAlreadyYielded == pdFALSE )
 80114e8:	68fb      	ldr	r3, [r7, #12]
 80114ea:	2b00      	cmp	r3, #0
 80114ec:	d107      	bne.n	80114fe <vTaskDelay+0x5a>
		{
			portYIELD_WITHIN_API();
 80114ee:	4b07      	ldr	r3, [pc, #28]	@ (801150c <vTaskDelay+0x68>)
 80114f0:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80114f4:	601a      	str	r2, [r3, #0]
 80114f6:	f3bf 8f4f 	dsb	sy
 80114fa:	f3bf 8f6f 	isb	sy
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
 80114fe:	bf00      	nop
 8011500:	3710      	adds	r7, #16
 8011502:	46bd      	mov	sp, r7
 8011504:	bd80      	pop	{r7, pc}
 8011506:	bf00      	nop
 8011508:	240028f0 	.word	0x240028f0
 801150c:	e000ed04 	.word	0xe000ed04

08011510 <vTaskStartScheduler>:

#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/

void vTaskStartScheduler( void )
{
 8011510:	b580      	push	{r7, lr}
 8011512:	b08a      	sub	sp, #40	@ 0x28
 8011514:	af04      	add	r7, sp, #16
BaseType_t xReturn;

	/* Add the idle task at the lowest priority. */
	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
	{
		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
 8011516:	2300      	movs	r3, #0
 8011518:	60bb      	str	r3, [r7, #8]
		StackType_t *pxIdleTaskStackBuffer = NULL;
 801151a:	2300      	movs	r3, #0
 801151c:	607b      	str	r3, [r7, #4]
		uint32_t ulIdleTaskStackSize;

		/* The Idle task is created using user provided RAM - obtain the
		address of the RAM then create the idle task. */
		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
 801151e:	463a      	mov	r2, r7
 8011520:	1d39      	adds	r1, r7, #4
 8011522:	f107 0308 	add.w	r3, r7, #8
 8011526:	4618      	mov	r0, r3
 8011528:	f7fe fbc0 	bl	800fcac <vApplicationGetIdleTaskMemory>
		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
 801152c:	6839      	ldr	r1, [r7, #0]
 801152e:	687b      	ldr	r3, [r7, #4]
 8011530:	68ba      	ldr	r2, [r7, #8]
 8011532:	9202      	str	r2, [sp, #8]
 8011534:	9301      	str	r3, [sp, #4]
 8011536:	2300      	movs	r3, #0
 8011538:	9300      	str	r3, [sp, #0]
 801153a:	2300      	movs	r3, #0
 801153c:	460a      	mov	r2, r1
 801153e:	4924      	ldr	r1, [pc, #144]	@ (80115d0 <vTaskStartScheduler+0xc0>)
 8011540:	4824      	ldr	r0, [pc, #144]	@ (80115d4 <vTaskStartScheduler+0xc4>)
 8011542:	f7ff fdf2 	bl	801112a <xTaskCreateStatic>
 8011546:	4603      	mov	r3, r0
 8011548:	4a23      	ldr	r2, [pc, #140]	@ (80115d8 <vTaskStartScheduler+0xc8>)
 801154a:	6013      	str	r3, [r2, #0]
												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
												pxIdleTaskStackBuffer,
												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */

		if( xIdleTaskHandle != NULL )
 801154c:	4b22      	ldr	r3, [pc, #136]	@ (80115d8 <vTaskStartScheduler+0xc8>)
 801154e:	681b      	ldr	r3, [r3, #0]
 8011550:	2b00      	cmp	r3, #0
 8011552:	d002      	beq.n	801155a <vTaskStartScheduler+0x4a>
		{
			xReturn = pdPASS;
 8011554:	2301      	movs	r3, #1
 8011556:	617b      	str	r3, [r7, #20]
 8011558:	e001      	b.n	801155e <vTaskStartScheduler+0x4e>
		}
		else
		{
			xReturn = pdFAIL;
 801155a:	2300      	movs	r3, #0
 801155c:	617b      	str	r3, [r7, #20]
	}
	#endif /* configSUPPORT_STATIC_ALLOCATION */

	#if ( configUSE_TIMERS == 1 )
	{
		if( xReturn == pdPASS )
 801155e:	697b      	ldr	r3, [r7, #20]
 8011560:	2b01      	cmp	r3, #1
 8011562:	d102      	bne.n	801156a <vTaskStartScheduler+0x5a>
		{
			xReturn = xTimerCreateTimerTask();
 8011564:	f001 f88e 	bl	8012684 <xTimerCreateTimerTask>
 8011568:	6178      	str	r0, [r7, #20]
			mtCOVERAGE_TEST_MARKER();
		}
	}
	#endif /* configUSE_TIMERS */

	if( xReturn == pdPASS )
 801156a:	697b      	ldr	r3, [r7, #20]
 801156c:	2b01      	cmp	r3, #1
 801156e:	d11b      	bne.n	80115a8 <vTaskStartScheduler+0x98>
	__asm volatile
 8011570:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011574:	f383 8811 	msr	BASEPRI, r3
 8011578:	f3bf 8f6f 	isb	sy
 801157c:	f3bf 8f4f 	dsb	sy
 8011580:	613b      	str	r3, [r7, #16]
}
 8011582:	bf00      	nop
		{
			/* Switch Newlib's _impure_ptr variable to point to the _reent
			structure specific to the task that will run first.
			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
			for additional information. */
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
 8011584:	4b15      	ldr	r3, [pc, #84]	@ (80115dc <vTaskStartScheduler+0xcc>)
 8011586:	681b      	ldr	r3, [r3, #0]
 8011588:	3354      	adds	r3, #84	@ 0x54
 801158a:	4a15      	ldr	r2, [pc, #84]	@ (80115e0 <vTaskStartScheduler+0xd0>)
 801158c:	6013      	str	r3, [r2, #0]
		}
		#endif /* configUSE_NEWLIB_REENTRANT */

		xNextTaskUnblockTime = portMAX_DELAY;
 801158e:	4b15      	ldr	r3, [pc, #84]	@ (80115e4 <vTaskStartScheduler+0xd4>)
 8011590:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8011594:	601a      	str	r2, [r3, #0]
		xSchedulerRunning = pdTRUE;
 8011596:	4b14      	ldr	r3, [pc, #80]	@ (80115e8 <vTaskStartScheduler+0xd8>)
 8011598:	2201      	movs	r2, #1
 801159a:	601a      	str	r2, [r3, #0]
		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
 801159c:	4b13      	ldr	r3, [pc, #76]	@ (80115ec <vTaskStartScheduler+0xdc>)
 801159e:	2200      	movs	r2, #0
 80115a0:	601a      	str	r2, [r3, #0]

		traceTASK_SWITCHED_IN();

		/* Setting up the timer tick is hardware specific and thus in the
		portable interface. */
		if( xPortStartScheduler() != pdFALSE )
 80115a2:	f001 fc55 	bl	8012e50 <xPortStartScheduler>
	}

	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
	meaning xIdleTaskHandle is not used anywhere else. */
	( void ) xIdleTaskHandle;
}
 80115a6:	e00f      	b.n	80115c8 <vTaskStartScheduler+0xb8>
		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
 80115a8:	697b      	ldr	r3, [r7, #20]
 80115aa:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80115ae:	d10b      	bne.n	80115c8 <vTaskStartScheduler+0xb8>
	__asm volatile
 80115b0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80115b4:	f383 8811 	msr	BASEPRI, r3
 80115b8:	f3bf 8f6f 	isb	sy
 80115bc:	f3bf 8f4f 	dsb	sy
 80115c0:	60fb      	str	r3, [r7, #12]
}
 80115c2:	bf00      	nop
 80115c4:	bf00      	nop
 80115c6:	e7fd      	b.n	80115c4 <vTaskStartScheduler+0xb4>
}
 80115c8:	bf00      	nop
 80115ca:	3718      	adds	r7, #24
 80115cc:	46bd      	mov	sp, r7
 80115ce:	bd80      	pop	{r7, pc}
 80115d0:	080145a8 	.word	0x080145a8
 80115d4:	08011c8d 	.word	0x08011c8d
 80115d8:	240028ec 	.word	0x240028ec
 80115dc:	240023f4 	.word	0x240023f4
 80115e0:	24000054 	.word	0x24000054
 80115e4:	240028e8 	.word	0x240028e8
 80115e8:	240028d4 	.word	0x240028d4
 80115ec:	240028cc 	.word	0x240028cc

080115f0 <vTaskSuspendAll>:
	vPortEndScheduler();
}
/*----------------------------------------------------------*/

void vTaskSuspendAll( void )
{
 80115f0:	b480      	push	{r7}
 80115f2:	af00      	add	r7, sp, #0
	do not otherwise exhibit real time behaviour. */
	portSOFTWARE_BARRIER();

	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
	is used to allow calls to vTaskSuspendAll() to nest. */
	++uxSchedulerSuspended;
 80115f4:	4b04      	ldr	r3, [pc, #16]	@ (8011608 <vTaskSuspendAll+0x18>)
 80115f6:	681b      	ldr	r3, [r3, #0]
 80115f8:	3301      	adds	r3, #1
 80115fa:	4a03      	ldr	r2, [pc, #12]	@ (8011608 <vTaskSuspendAll+0x18>)
 80115fc:	6013      	str	r3, [r2, #0]

	/* Enforces ordering for ports and optimised compilers that may otherwise place
	the above increment elsewhere. */
	portMEMORY_BARRIER();
}
 80115fe:	bf00      	nop
 8011600:	46bd      	mov	sp, r7
 8011602:	f85d 7b04 	ldr.w	r7, [sp], #4
 8011606:	4770      	bx	lr
 8011608:	240028f0 	.word	0x240028f0

0801160c <xTaskResumeAll>:

#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/

BaseType_t xTaskResumeAll( void )
{
 801160c:	b580      	push	{r7, lr}
 801160e:	b084      	sub	sp, #16
 8011610:	af00      	add	r7, sp, #0
TCB_t *pxTCB = NULL;
 8011612:	2300      	movs	r3, #0
 8011614:	60fb      	str	r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
 8011616:	2300      	movs	r3, #0
 8011618:	60bb      	str	r3, [r7, #8]

	/* If uxSchedulerSuspended is zero then this function does not match a
	previous call to vTaskSuspendAll(). */
	configASSERT( uxSchedulerSuspended );
 801161a:	4b42      	ldr	r3, [pc, #264]	@ (8011724 <xTaskResumeAll+0x118>)
 801161c:	681b      	ldr	r3, [r3, #0]
 801161e:	2b00      	cmp	r3, #0
 8011620:	d10b      	bne.n	801163a <xTaskResumeAll+0x2e>
	__asm volatile
 8011622:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011626:	f383 8811 	msr	BASEPRI, r3
 801162a:	f3bf 8f6f 	isb	sy
 801162e:	f3bf 8f4f 	dsb	sy
 8011632:	603b      	str	r3, [r7, #0]
}
 8011634:	bf00      	nop
 8011636:	bf00      	nop
 8011638:	e7fd      	b.n	8011636 <xTaskResumeAll+0x2a>
	/* It is possible that an ISR caused a task to be removed from an event
	list while the scheduler was suspended.  If this was the case then the
	removed task will have been added to the xPendingReadyList.  Once the
	scheduler has been resumed it is safe to move all the pending ready
	tasks from this list into their appropriate ready list. */
	taskENTER_CRITICAL();
 801163a:	f001 fcad 	bl	8012f98 <vPortEnterCritical>
	{
		--uxSchedulerSuspended;
 801163e:	4b39      	ldr	r3, [pc, #228]	@ (8011724 <xTaskResumeAll+0x118>)
 8011640:	681b      	ldr	r3, [r3, #0]
 8011642:	3b01      	subs	r3, #1
 8011644:	4a37      	ldr	r2, [pc, #220]	@ (8011724 <xTaskResumeAll+0x118>)
 8011646:	6013      	str	r3, [r2, #0]

		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8011648:	4b36      	ldr	r3, [pc, #216]	@ (8011724 <xTaskResumeAll+0x118>)
 801164a:	681b      	ldr	r3, [r3, #0]
 801164c:	2b00      	cmp	r3, #0
 801164e:	d162      	bne.n	8011716 <xTaskResumeAll+0x10a>
		{
			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
 8011650:	4b35      	ldr	r3, [pc, #212]	@ (8011728 <xTaskResumeAll+0x11c>)
 8011652:	681b      	ldr	r3, [r3, #0]
 8011654:	2b00      	cmp	r3, #0
 8011656:	d05e      	beq.n	8011716 <xTaskResumeAll+0x10a>
			{
				/* Move any readied tasks from the pending list into the
				appropriate ready list. */
				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 8011658:	e02f      	b.n	80116ba <xTaskResumeAll+0xae>
				{
					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 801165a:	4b34      	ldr	r3, [pc, #208]	@ (801172c <xTaskResumeAll+0x120>)
 801165c:	68db      	ldr	r3, [r3, #12]
 801165e:	68db      	ldr	r3, [r3, #12]
 8011660:	60fb      	str	r3, [r7, #12]
					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 8011662:	68fb      	ldr	r3, [r7, #12]
 8011664:	3318      	adds	r3, #24
 8011666:	4618      	mov	r0, r3
 8011668:	f7fe fbde 	bl	800fe28 <uxListRemove>
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 801166c:	68fb      	ldr	r3, [r7, #12]
 801166e:	3304      	adds	r3, #4
 8011670:	4618      	mov	r0, r3
 8011672:	f7fe fbd9 	bl	800fe28 <uxListRemove>
					prvAddTaskToReadyList( pxTCB );
 8011676:	68fb      	ldr	r3, [r7, #12]
 8011678:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 801167a:	4b2d      	ldr	r3, [pc, #180]	@ (8011730 <xTaskResumeAll+0x124>)
 801167c:	681b      	ldr	r3, [r3, #0]
 801167e:	429a      	cmp	r2, r3
 8011680:	d903      	bls.n	801168a <xTaskResumeAll+0x7e>
 8011682:	68fb      	ldr	r3, [r7, #12]
 8011684:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8011686:	4a2a      	ldr	r2, [pc, #168]	@ (8011730 <xTaskResumeAll+0x124>)
 8011688:	6013      	str	r3, [r2, #0]
 801168a:	68fb      	ldr	r3, [r7, #12]
 801168c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 801168e:	4613      	mov	r3, r2
 8011690:	009b      	lsls	r3, r3, #2
 8011692:	4413      	add	r3, r2
 8011694:	009b      	lsls	r3, r3, #2
 8011696:	4a27      	ldr	r2, [pc, #156]	@ (8011734 <xTaskResumeAll+0x128>)
 8011698:	441a      	add	r2, r3
 801169a:	68fb      	ldr	r3, [r7, #12]
 801169c:	3304      	adds	r3, #4
 801169e:	4619      	mov	r1, r3
 80116a0:	4610      	mov	r0, r2
 80116a2:	f7fe fb64 	bl	800fd6e <vListInsertEnd>

					/* If the moved task has a priority higher than the current
					task then a yield must be performed. */
					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 80116a6:	68fb      	ldr	r3, [r7, #12]
 80116a8:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80116aa:	4b23      	ldr	r3, [pc, #140]	@ (8011738 <xTaskResumeAll+0x12c>)
 80116ac:	681b      	ldr	r3, [r3, #0]
 80116ae:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80116b0:	429a      	cmp	r2, r3
 80116b2:	d302      	bcc.n	80116ba <xTaskResumeAll+0xae>
					{
						xYieldPending = pdTRUE;
 80116b4:	4b21      	ldr	r3, [pc, #132]	@ (801173c <xTaskResumeAll+0x130>)
 80116b6:	2201      	movs	r2, #1
 80116b8:	601a      	str	r2, [r3, #0]
				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 80116ba:	4b1c      	ldr	r3, [pc, #112]	@ (801172c <xTaskResumeAll+0x120>)
 80116bc:	681b      	ldr	r3, [r3, #0]
 80116be:	2b00      	cmp	r3, #0
 80116c0:	d1cb      	bne.n	801165a <xTaskResumeAll+0x4e>
					{
						mtCOVERAGE_TEST_MARKER();
					}
				}

				if( pxTCB != NULL )
 80116c2:	68fb      	ldr	r3, [r7, #12]
 80116c4:	2b00      	cmp	r3, #0
 80116c6:	d001      	beq.n	80116cc <xTaskResumeAll+0xc0>
					which may have prevented the next unblock time from being
					re-calculated, in which case re-calculate it now.  Mainly
					important for low power tickless implementations, where
					this can prevent an unnecessary exit from low power
					state. */
					prvResetNextTaskUnblockTime();
 80116c8:	f000 fb9c 	bl	8011e04 <prvResetNextTaskUnblockTime>
				/* If any ticks occurred while the scheduler was suspended then
				they should be processed now.  This ensures the tick count does
				not	slip, and that any delayed tasks are resumed at the correct
				time. */
				{
					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
 80116cc:	4b1c      	ldr	r3, [pc, #112]	@ (8011740 <xTaskResumeAll+0x134>)
 80116ce:	681b      	ldr	r3, [r3, #0]
 80116d0:	607b      	str	r3, [r7, #4]

					if( xPendedCounts > ( TickType_t ) 0U )
 80116d2:	687b      	ldr	r3, [r7, #4]
 80116d4:	2b00      	cmp	r3, #0
 80116d6:	d010      	beq.n	80116fa <xTaskResumeAll+0xee>
					{
						do
						{
							if( xTaskIncrementTick() != pdFALSE )
 80116d8:	f000 f846 	bl	8011768 <xTaskIncrementTick>
 80116dc:	4603      	mov	r3, r0
 80116de:	2b00      	cmp	r3, #0
 80116e0:	d002      	beq.n	80116e8 <xTaskResumeAll+0xdc>
							{
								xYieldPending = pdTRUE;
 80116e2:	4b16      	ldr	r3, [pc, #88]	@ (801173c <xTaskResumeAll+0x130>)
 80116e4:	2201      	movs	r2, #1
 80116e6:	601a      	str	r2, [r3, #0]
							}
							else
							{
								mtCOVERAGE_TEST_MARKER();
							}
							--xPendedCounts;
 80116e8:	687b      	ldr	r3, [r7, #4]
 80116ea:	3b01      	subs	r3, #1
 80116ec:	607b      	str	r3, [r7, #4]
						} while( xPendedCounts > ( TickType_t ) 0U );
 80116ee:	687b      	ldr	r3, [r7, #4]
 80116f0:	2b00      	cmp	r3, #0
 80116f2:	d1f1      	bne.n	80116d8 <xTaskResumeAll+0xcc>

						xPendedTicks = 0;
 80116f4:	4b12      	ldr	r3, [pc, #72]	@ (8011740 <xTaskResumeAll+0x134>)
 80116f6:	2200      	movs	r2, #0
 80116f8:	601a      	str	r2, [r3, #0]
					{
						mtCOVERAGE_TEST_MARKER();
					}
				}

				if( xYieldPending != pdFALSE )
 80116fa:	4b10      	ldr	r3, [pc, #64]	@ (801173c <xTaskResumeAll+0x130>)
 80116fc:	681b      	ldr	r3, [r3, #0]
 80116fe:	2b00      	cmp	r3, #0
 8011700:	d009      	beq.n	8011716 <xTaskResumeAll+0x10a>
				{
					#if( configUSE_PREEMPTION != 0 )
					{
						xAlreadyYielded = pdTRUE;
 8011702:	2301      	movs	r3, #1
 8011704:	60bb      	str	r3, [r7, #8]
					}
					#endif
					taskYIELD_IF_USING_PREEMPTION();
 8011706:	4b0f      	ldr	r3, [pc, #60]	@ (8011744 <xTaskResumeAll+0x138>)
 8011708:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 801170c:	601a      	str	r2, [r3, #0]
 801170e:	f3bf 8f4f 	dsb	sy
 8011712:	f3bf 8f6f 	isb	sy
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
	taskEXIT_CRITICAL();
 8011716:	f001 fc71 	bl	8012ffc <vPortExitCritical>

	return xAlreadyYielded;
 801171a:	68bb      	ldr	r3, [r7, #8]
}
 801171c:	4618      	mov	r0, r3
 801171e:	3710      	adds	r7, #16
 8011720:	46bd      	mov	sp, r7
 8011722:	bd80      	pop	{r7, pc}
 8011724:	240028f0 	.word	0x240028f0
 8011728:	240028c8 	.word	0x240028c8
 801172c:	24002888 	.word	0x24002888
 8011730:	240028d0 	.word	0x240028d0
 8011734:	240023f8 	.word	0x240023f8
 8011738:	240023f4 	.word	0x240023f4
 801173c:	240028dc 	.word	0x240028dc
 8011740:	240028d8 	.word	0x240028d8
 8011744:	e000ed04 	.word	0xe000ed04

08011748 <xTaskGetTickCount>:
/*-----------------------------------------------------------*/

TickType_t xTaskGetTickCount( void )
{
 8011748:	b480      	push	{r7}
 801174a:	b083      	sub	sp, #12
 801174c:	af00      	add	r7, sp, #0
TickType_t xTicks;

	/* Critical section required if running on a 16 bit processor. */
	portTICK_TYPE_ENTER_CRITICAL();
	{
		xTicks = xTickCount;
 801174e:	4b05      	ldr	r3, [pc, #20]	@ (8011764 <xTaskGetTickCount+0x1c>)
 8011750:	681b      	ldr	r3, [r3, #0]
 8011752:	607b      	str	r3, [r7, #4]
	}
	portTICK_TYPE_EXIT_CRITICAL();

	return xTicks;
 8011754:	687b      	ldr	r3, [r7, #4]
}
 8011756:	4618      	mov	r0, r3
 8011758:	370c      	adds	r7, #12
 801175a:	46bd      	mov	sp, r7
 801175c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8011760:	4770      	bx	lr
 8011762:	bf00      	nop
 8011764:	240028cc 	.word	0x240028cc

08011768 <xTaskIncrementTick>:

#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/

BaseType_t xTaskIncrementTick( void )
{
 8011768:	b580      	push	{r7, lr}
 801176a:	b086      	sub	sp, #24
 801176c:	af00      	add	r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
 801176e:	2300      	movs	r3, #0
 8011770:	617b      	str	r3, [r7, #20]

	/* Called by the portable layer each time a tick interrupt occurs.
	Increments the tick then checks to see if the new tick value will cause any
	tasks to be unblocked. */
	traceTASK_INCREMENT_TICK( xTickCount );
	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8011772:	4b4f      	ldr	r3, [pc, #316]	@ (80118b0 <xTaskIncrementTick+0x148>)
 8011774:	681b      	ldr	r3, [r3, #0]
 8011776:	2b00      	cmp	r3, #0
 8011778:	f040 8090 	bne.w	801189c <xTaskIncrementTick+0x134>
	{
		/* Minor optimisation.  The tick count cannot change in this
		block. */
		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
 801177c:	4b4d      	ldr	r3, [pc, #308]	@ (80118b4 <xTaskIncrementTick+0x14c>)
 801177e:	681b      	ldr	r3, [r3, #0]
 8011780:	3301      	adds	r3, #1
 8011782:	613b      	str	r3, [r7, #16]

		/* Increment the RTOS tick, switching the delayed and overflowed
		delayed lists if it wraps to 0. */
		xTickCount = xConstTickCount;
 8011784:	4a4b      	ldr	r2, [pc, #300]	@ (80118b4 <xTaskIncrementTick+0x14c>)
 8011786:	693b      	ldr	r3, [r7, #16]
 8011788:	6013      	str	r3, [r2, #0]

		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
 801178a:	693b      	ldr	r3, [r7, #16]
 801178c:	2b00      	cmp	r3, #0
 801178e:	d121      	bne.n	80117d4 <xTaskIncrementTick+0x6c>
		{
			taskSWITCH_DELAYED_LISTS();
 8011790:	4b49      	ldr	r3, [pc, #292]	@ (80118b8 <xTaskIncrementTick+0x150>)
 8011792:	681b      	ldr	r3, [r3, #0]
 8011794:	681b      	ldr	r3, [r3, #0]
 8011796:	2b00      	cmp	r3, #0
 8011798:	d00b      	beq.n	80117b2 <xTaskIncrementTick+0x4a>
	__asm volatile
 801179a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801179e:	f383 8811 	msr	BASEPRI, r3
 80117a2:	f3bf 8f6f 	isb	sy
 80117a6:	f3bf 8f4f 	dsb	sy
 80117aa:	603b      	str	r3, [r7, #0]
}
 80117ac:	bf00      	nop
 80117ae:	bf00      	nop
 80117b0:	e7fd      	b.n	80117ae <xTaskIncrementTick+0x46>
 80117b2:	4b41      	ldr	r3, [pc, #260]	@ (80118b8 <xTaskIncrementTick+0x150>)
 80117b4:	681b      	ldr	r3, [r3, #0]
 80117b6:	60fb      	str	r3, [r7, #12]
 80117b8:	4b40      	ldr	r3, [pc, #256]	@ (80118bc <xTaskIncrementTick+0x154>)
 80117ba:	681b      	ldr	r3, [r3, #0]
 80117bc:	4a3e      	ldr	r2, [pc, #248]	@ (80118b8 <xTaskIncrementTick+0x150>)
 80117be:	6013      	str	r3, [r2, #0]
 80117c0:	4a3e      	ldr	r2, [pc, #248]	@ (80118bc <xTaskIncrementTick+0x154>)
 80117c2:	68fb      	ldr	r3, [r7, #12]
 80117c4:	6013      	str	r3, [r2, #0]
 80117c6:	4b3e      	ldr	r3, [pc, #248]	@ (80118c0 <xTaskIncrementTick+0x158>)
 80117c8:	681b      	ldr	r3, [r3, #0]
 80117ca:	3301      	adds	r3, #1
 80117cc:	4a3c      	ldr	r2, [pc, #240]	@ (80118c0 <xTaskIncrementTick+0x158>)
 80117ce:	6013      	str	r3, [r2, #0]
 80117d0:	f000 fb18 	bl	8011e04 <prvResetNextTaskUnblockTime>

		/* See if this tick has made a timeout expire.  Tasks are stored in
		the	queue in the order of their wake time - meaning once one task
		has been found whose block time has not expired there is no need to
		look any further down the list. */
		if( xConstTickCount >= xNextTaskUnblockTime )
 80117d4:	4b3b      	ldr	r3, [pc, #236]	@ (80118c4 <xTaskIncrementTick+0x15c>)
 80117d6:	681b      	ldr	r3, [r3, #0]
 80117d8:	693a      	ldr	r2, [r7, #16]
 80117da:	429a      	cmp	r2, r3
 80117dc:	d349      	bcc.n	8011872 <xTaskIncrementTick+0x10a>
		{
			for( ;; )
			{
				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 80117de:	4b36      	ldr	r3, [pc, #216]	@ (80118b8 <xTaskIncrementTick+0x150>)
 80117e0:	681b      	ldr	r3, [r3, #0]
 80117e2:	681b      	ldr	r3, [r3, #0]
 80117e4:	2b00      	cmp	r3, #0
 80117e6:	d104      	bne.n	80117f2 <xTaskIncrementTick+0x8a>
					/* The delayed list is empty.  Set xNextTaskUnblockTime
					to the maximum possible value so it is extremely
					unlikely that the
					if( xTickCount >= xNextTaskUnblockTime ) test will pass
					next time through. */
					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80117e8:	4b36      	ldr	r3, [pc, #216]	@ (80118c4 <xTaskIncrementTick+0x15c>)
 80117ea:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 80117ee:	601a      	str	r2, [r3, #0]
					break;
 80117f0:	e03f      	b.n	8011872 <xTaskIncrementTick+0x10a>
				{
					/* The delayed list is not empty, get the value of the
					item at the head of the delayed list.  This is the time
					at which the task at the head of the delayed list must
					be removed from the Blocked state. */
					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80117f2:	4b31      	ldr	r3, [pc, #196]	@ (80118b8 <xTaskIncrementTick+0x150>)
 80117f4:	681b      	ldr	r3, [r3, #0]
 80117f6:	68db      	ldr	r3, [r3, #12]
 80117f8:	68db      	ldr	r3, [r3, #12]
 80117fa:	60bb      	str	r3, [r7, #8]
					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
 80117fc:	68bb      	ldr	r3, [r7, #8]
 80117fe:	685b      	ldr	r3, [r3, #4]
 8011800:	607b      	str	r3, [r7, #4]

					if( xConstTickCount < xItemValue )
 8011802:	693a      	ldr	r2, [r7, #16]
 8011804:	687b      	ldr	r3, [r7, #4]
 8011806:	429a      	cmp	r2, r3
 8011808:	d203      	bcs.n	8011812 <xTaskIncrementTick+0xaa>
						/* It is not time to unblock this item yet, but the
						item value is the time at which the task at the head
						of the blocked list must be removed from the Blocked
						state -	so record the item value in
						xNextTaskUnblockTime. */
						xNextTaskUnblockTime = xItemValue;
 801180a:	4a2e      	ldr	r2, [pc, #184]	@ (80118c4 <xTaskIncrementTick+0x15c>)
 801180c:	687b      	ldr	r3, [r7, #4]
 801180e:	6013      	str	r3, [r2, #0]
						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
 8011810:	e02f      	b.n	8011872 <xTaskIncrementTick+0x10a>
					{
						mtCOVERAGE_TEST_MARKER();
					}

					/* It is time to remove the item from the Blocked state. */
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8011812:	68bb      	ldr	r3, [r7, #8]
 8011814:	3304      	adds	r3, #4
 8011816:	4618      	mov	r0, r3
 8011818:	f7fe fb06 	bl	800fe28 <uxListRemove>

					/* Is the task waiting on an event also?  If so remove
					it from the event list. */
					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
 801181c:	68bb      	ldr	r3, [r7, #8]
 801181e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8011820:	2b00      	cmp	r3, #0
 8011822:	d004      	beq.n	801182e <xTaskIncrementTick+0xc6>
					{
						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 8011824:	68bb      	ldr	r3, [r7, #8]
 8011826:	3318      	adds	r3, #24
 8011828:	4618      	mov	r0, r3
 801182a:	f7fe fafd 	bl	800fe28 <uxListRemove>
						mtCOVERAGE_TEST_MARKER();
					}

					/* Place the unblocked task into the appropriate ready
					list. */
					prvAddTaskToReadyList( pxTCB );
 801182e:	68bb      	ldr	r3, [r7, #8]
 8011830:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011832:	4b25      	ldr	r3, [pc, #148]	@ (80118c8 <xTaskIncrementTick+0x160>)
 8011834:	681b      	ldr	r3, [r3, #0]
 8011836:	429a      	cmp	r2, r3
 8011838:	d903      	bls.n	8011842 <xTaskIncrementTick+0xda>
 801183a:	68bb      	ldr	r3, [r7, #8]
 801183c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 801183e:	4a22      	ldr	r2, [pc, #136]	@ (80118c8 <xTaskIncrementTick+0x160>)
 8011840:	6013      	str	r3, [r2, #0]
 8011842:	68bb      	ldr	r3, [r7, #8]
 8011844:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011846:	4613      	mov	r3, r2
 8011848:	009b      	lsls	r3, r3, #2
 801184a:	4413      	add	r3, r2
 801184c:	009b      	lsls	r3, r3, #2
 801184e:	4a1f      	ldr	r2, [pc, #124]	@ (80118cc <xTaskIncrementTick+0x164>)
 8011850:	441a      	add	r2, r3
 8011852:	68bb      	ldr	r3, [r7, #8]
 8011854:	3304      	adds	r3, #4
 8011856:	4619      	mov	r1, r3
 8011858:	4610      	mov	r0, r2
 801185a:	f7fe fa88 	bl	800fd6e <vListInsertEnd>
					{
						/* Preemption is on, but a context switch should
						only be performed if the unblocked task has a
						priority that is equal to or higher than the
						currently executing task. */
						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 801185e:	68bb      	ldr	r3, [r7, #8]
 8011860:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011862:	4b1b      	ldr	r3, [pc, #108]	@ (80118d0 <xTaskIncrementTick+0x168>)
 8011864:	681b      	ldr	r3, [r3, #0]
 8011866:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8011868:	429a      	cmp	r2, r3
 801186a:	d3b8      	bcc.n	80117de <xTaskIncrementTick+0x76>
						{
							xSwitchRequired = pdTRUE;
 801186c:	2301      	movs	r3, #1
 801186e:	617b      	str	r3, [r7, #20]
				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 8011870:	e7b5      	b.n	80117de <xTaskIncrementTick+0x76>
		/* Tasks of equal priority to the currently running task will share
		processing time (time slice) if preemption is on, and the application
		writer has not explicitly turned time slicing off. */
		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
		{
			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
 8011872:	4b17      	ldr	r3, [pc, #92]	@ (80118d0 <xTaskIncrementTick+0x168>)
 8011874:	681b      	ldr	r3, [r3, #0]
 8011876:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011878:	4914      	ldr	r1, [pc, #80]	@ (80118cc <xTaskIncrementTick+0x164>)
 801187a:	4613      	mov	r3, r2
 801187c:	009b      	lsls	r3, r3, #2
 801187e:	4413      	add	r3, r2
 8011880:	009b      	lsls	r3, r3, #2
 8011882:	440b      	add	r3, r1
 8011884:	681b      	ldr	r3, [r3, #0]
 8011886:	2b01      	cmp	r3, #1
 8011888:	d901      	bls.n	801188e <xTaskIncrementTick+0x126>
			{
				xSwitchRequired = pdTRUE;
 801188a:	2301      	movs	r3, #1
 801188c:	617b      	str	r3, [r7, #20]
		}
		#endif /* configUSE_TICK_HOOK */

		#if ( configUSE_PREEMPTION == 1 )
		{
			if( xYieldPending != pdFALSE )
 801188e:	4b11      	ldr	r3, [pc, #68]	@ (80118d4 <xTaskIncrementTick+0x16c>)
 8011890:	681b      	ldr	r3, [r3, #0]
 8011892:	2b00      	cmp	r3, #0
 8011894:	d007      	beq.n	80118a6 <xTaskIncrementTick+0x13e>
			{
				xSwitchRequired = pdTRUE;
 8011896:	2301      	movs	r3, #1
 8011898:	617b      	str	r3, [r7, #20]
 801189a:	e004      	b.n	80118a6 <xTaskIncrementTick+0x13e>
		}
		#endif /* configUSE_PREEMPTION */
	}
	else
	{
		++xPendedTicks;
 801189c:	4b0e      	ldr	r3, [pc, #56]	@ (80118d8 <xTaskIncrementTick+0x170>)
 801189e:	681b      	ldr	r3, [r3, #0]
 80118a0:	3301      	adds	r3, #1
 80118a2:	4a0d      	ldr	r2, [pc, #52]	@ (80118d8 <xTaskIncrementTick+0x170>)
 80118a4:	6013      	str	r3, [r2, #0]
			vApplicationTickHook();
		}
		#endif
	}

	return xSwitchRequired;
 80118a6:	697b      	ldr	r3, [r7, #20]
}
 80118a8:	4618      	mov	r0, r3
 80118aa:	3718      	adds	r7, #24
 80118ac:	46bd      	mov	sp, r7
 80118ae:	bd80      	pop	{r7, pc}
 80118b0:	240028f0 	.word	0x240028f0
 80118b4:	240028cc 	.word	0x240028cc
 80118b8:	24002880 	.word	0x24002880
 80118bc:	24002884 	.word	0x24002884
 80118c0:	240028e0 	.word	0x240028e0
 80118c4:	240028e8 	.word	0x240028e8
 80118c8:	240028d0 	.word	0x240028d0
 80118cc:	240023f8 	.word	0x240023f8
 80118d0:	240023f4 	.word	0x240023f4
 80118d4:	240028dc 	.word	0x240028dc
 80118d8:	240028d8 	.word	0x240028d8

080118dc <vTaskSwitchContext>:

#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/

void vTaskSwitchContext( void )
{
 80118dc:	b580      	push	{r7, lr}
 80118de:	b084      	sub	sp, #16
 80118e0:	af00      	add	r7, sp, #0
	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
 80118e2:	4b32      	ldr	r3, [pc, #200]	@ (80119ac <vTaskSwitchContext+0xd0>)
 80118e4:	681b      	ldr	r3, [r3, #0]
 80118e6:	2b00      	cmp	r3, #0
 80118e8:	d003      	beq.n	80118f2 <vTaskSwitchContext+0x16>
	{
		/* The scheduler is currently suspended - do not allow a context
		switch. */
		xYieldPending = pdTRUE;
 80118ea:	4b31      	ldr	r3, [pc, #196]	@ (80119b0 <vTaskSwitchContext+0xd4>)
 80118ec:	2201      	movs	r2, #1
 80118ee:	601a      	str	r2, [r3, #0]
			for additional information. */
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
		}
		#endif /* configUSE_NEWLIB_REENTRANT */
	}
}
 80118f0:	e058      	b.n	80119a4 <vTaskSwitchContext+0xc8>
		xYieldPending = pdFALSE;
 80118f2:	4b2f      	ldr	r3, [pc, #188]	@ (80119b0 <vTaskSwitchContext+0xd4>)
 80118f4:	2200      	movs	r2, #0
 80118f6:	601a      	str	r2, [r3, #0]
		taskCHECK_FOR_STACK_OVERFLOW();
 80118f8:	4b2e      	ldr	r3, [pc, #184]	@ (80119b4 <vTaskSwitchContext+0xd8>)
 80118fa:	681b      	ldr	r3, [r3, #0]
 80118fc:	681a      	ldr	r2, [r3, #0]
 80118fe:	4b2d      	ldr	r3, [pc, #180]	@ (80119b4 <vTaskSwitchContext+0xd8>)
 8011900:	681b      	ldr	r3, [r3, #0]
 8011902:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8011904:	429a      	cmp	r2, r3
 8011906:	d808      	bhi.n	801191a <vTaskSwitchContext+0x3e>
 8011908:	4b2a      	ldr	r3, [pc, #168]	@ (80119b4 <vTaskSwitchContext+0xd8>)
 801190a:	681a      	ldr	r2, [r3, #0]
 801190c:	4b29      	ldr	r3, [pc, #164]	@ (80119b4 <vTaskSwitchContext+0xd8>)
 801190e:	681b      	ldr	r3, [r3, #0]
 8011910:	3334      	adds	r3, #52	@ 0x34
 8011912:	4619      	mov	r1, r3
 8011914:	4610      	mov	r0, r2
 8011916:	f7ee feab 	bl	8000670 <vApplicationStackOverflowHook>
		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 801191a:	4b27      	ldr	r3, [pc, #156]	@ (80119b8 <vTaskSwitchContext+0xdc>)
 801191c:	681b      	ldr	r3, [r3, #0]
 801191e:	60fb      	str	r3, [r7, #12]
 8011920:	e011      	b.n	8011946 <vTaskSwitchContext+0x6a>
 8011922:	68fb      	ldr	r3, [r7, #12]
 8011924:	2b00      	cmp	r3, #0
 8011926:	d10b      	bne.n	8011940 <vTaskSwitchContext+0x64>
	__asm volatile
 8011928:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801192c:	f383 8811 	msr	BASEPRI, r3
 8011930:	f3bf 8f6f 	isb	sy
 8011934:	f3bf 8f4f 	dsb	sy
 8011938:	607b      	str	r3, [r7, #4]
}
 801193a:	bf00      	nop
 801193c:	bf00      	nop
 801193e:	e7fd      	b.n	801193c <vTaskSwitchContext+0x60>
 8011940:	68fb      	ldr	r3, [r7, #12]
 8011942:	3b01      	subs	r3, #1
 8011944:	60fb      	str	r3, [r7, #12]
 8011946:	491d      	ldr	r1, [pc, #116]	@ (80119bc <vTaskSwitchContext+0xe0>)
 8011948:	68fa      	ldr	r2, [r7, #12]
 801194a:	4613      	mov	r3, r2
 801194c:	009b      	lsls	r3, r3, #2
 801194e:	4413      	add	r3, r2
 8011950:	009b      	lsls	r3, r3, #2
 8011952:	440b      	add	r3, r1
 8011954:	681b      	ldr	r3, [r3, #0]
 8011956:	2b00      	cmp	r3, #0
 8011958:	d0e3      	beq.n	8011922 <vTaskSwitchContext+0x46>
 801195a:	68fa      	ldr	r2, [r7, #12]
 801195c:	4613      	mov	r3, r2
 801195e:	009b      	lsls	r3, r3, #2
 8011960:	4413      	add	r3, r2
 8011962:	009b      	lsls	r3, r3, #2
 8011964:	4a15      	ldr	r2, [pc, #84]	@ (80119bc <vTaskSwitchContext+0xe0>)
 8011966:	4413      	add	r3, r2
 8011968:	60bb      	str	r3, [r7, #8]
 801196a:	68bb      	ldr	r3, [r7, #8]
 801196c:	685b      	ldr	r3, [r3, #4]
 801196e:	685a      	ldr	r2, [r3, #4]
 8011970:	68bb      	ldr	r3, [r7, #8]
 8011972:	605a      	str	r2, [r3, #4]
 8011974:	68bb      	ldr	r3, [r7, #8]
 8011976:	685a      	ldr	r2, [r3, #4]
 8011978:	68bb      	ldr	r3, [r7, #8]
 801197a:	3308      	adds	r3, #8
 801197c:	429a      	cmp	r2, r3
 801197e:	d104      	bne.n	801198a <vTaskSwitchContext+0xae>
 8011980:	68bb      	ldr	r3, [r7, #8]
 8011982:	685b      	ldr	r3, [r3, #4]
 8011984:	685a      	ldr	r2, [r3, #4]
 8011986:	68bb      	ldr	r3, [r7, #8]
 8011988:	605a      	str	r2, [r3, #4]
 801198a:	68bb      	ldr	r3, [r7, #8]
 801198c:	685b      	ldr	r3, [r3, #4]
 801198e:	68db      	ldr	r3, [r3, #12]
 8011990:	4a08      	ldr	r2, [pc, #32]	@ (80119b4 <vTaskSwitchContext+0xd8>)
 8011992:	6013      	str	r3, [r2, #0]
 8011994:	4a08      	ldr	r2, [pc, #32]	@ (80119b8 <vTaskSwitchContext+0xdc>)
 8011996:	68fb      	ldr	r3, [r7, #12]
 8011998:	6013      	str	r3, [r2, #0]
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
 801199a:	4b06      	ldr	r3, [pc, #24]	@ (80119b4 <vTaskSwitchContext+0xd8>)
 801199c:	681b      	ldr	r3, [r3, #0]
 801199e:	3354      	adds	r3, #84	@ 0x54
 80119a0:	4a07      	ldr	r2, [pc, #28]	@ (80119c0 <vTaskSwitchContext+0xe4>)
 80119a2:	6013      	str	r3, [r2, #0]
}
 80119a4:	bf00      	nop
 80119a6:	3710      	adds	r7, #16
 80119a8:	46bd      	mov	sp, r7
 80119aa:	bd80      	pop	{r7, pc}
 80119ac:	240028f0 	.word	0x240028f0
 80119b0:	240028dc 	.word	0x240028dc
 80119b4:	240023f4 	.word	0x240023f4
 80119b8:	240028d0 	.word	0x240028d0
 80119bc:	240023f8 	.word	0x240023f8
 80119c0:	24000054 	.word	0x24000054

080119c4 <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/

void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
 80119c4:	b580      	push	{r7, lr}
 80119c6:	b084      	sub	sp, #16
 80119c8:	af00      	add	r7, sp, #0
 80119ca:	6078      	str	r0, [r7, #4]
 80119cc:	6039      	str	r1, [r7, #0]
	configASSERT( pxEventList );
 80119ce:	687b      	ldr	r3, [r7, #4]
 80119d0:	2b00      	cmp	r3, #0
 80119d2:	d10b      	bne.n	80119ec <vTaskPlaceOnEventList+0x28>
	__asm volatile
 80119d4:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80119d8:	f383 8811 	msr	BASEPRI, r3
 80119dc:	f3bf 8f6f 	isb	sy
 80119e0:	f3bf 8f4f 	dsb	sy
 80119e4:	60fb      	str	r3, [r7, #12]
}
 80119e6:	bf00      	nop
 80119e8:	bf00      	nop
 80119ea:	e7fd      	b.n	80119e8 <vTaskPlaceOnEventList+0x24>

	/* Place the event list item of the TCB in the appropriate event list.
	This is placed in the list in priority order so the highest priority task
	is the first to be woken by the event.  The queue that contains the event
	list is locked, preventing simultaneous access from interrupts. */
	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 80119ec:	4b07      	ldr	r3, [pc, #28]	@ (8011a0c <vTaskPlaceOnEventList+0x48>)
 80119ee:	681b      	ldr	r3, [r3, #0]
 80119f0:	3318      	adds	r3, #24
 80119f2:	4619      	mov	r1, r3
 80119f4:	6878      	ldr	r0, [r7, #4]
 80119f6:	f7fe f9de 	bl	800fdb6 <vListInsert>

	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
 80119fa:	2101      	movs	r1, #1
 80119fc:	6838      	ldr	r0, [r7, #0]
 80119fe:	f000 fded 	bl	80125dc <prvAddCurrentTaskToDelayedList>
}
 8011a02:	bf00      	nop
 8011a04:	3710      	adds	r7, #16
 8011a06:	46bd      	mov	sp, r7
 8011a08:	bd80      	pop	{r7, pc}
 8011a0a:	bf00      	nop
 8011a0c:	240023f4 	.word	0x240023f4

08011a10 <vTaskPlaceOnEventListRestricted>:
/*-----------------------------------------------------------*/

#if( configUSE_TIMERS == 1 )

	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
	{
 8011a10:	b580      	push	{r7, lr}
 8011a12:	b086      	sub	sp, #24
 8011a14:	af00      	add	r7, sp, #0
 8011a16:	60f8      	str	r0, [r7, #12]
 8011a18:	60b9      	str	r1, [r7, #8]
 8011a1a:	607a      	str	r2, [r7, #4]
		configASSERT( pxEventList );
 8011a1c:	68fb      	ldr	r3, [r7, #12]
 8011a1e:	2b00      	cmp	r3, #0
 8011a20:	d10b      	bne.n	8011a3a <vTaskPlaceOnEventListRestricted+0x2a>
	__asm volatile
 8011a22:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011a26:	f383 8811 	msr	BASEPRI, r3
 8011a2a:	f3bf 8f6f 	isb	sy
 8011a2e:	f3bf 8f4f 	dsb	sy
 8011a32:	617b      	str	r3, [r7, #20]
}
 8011a34:	bf00      	nop
 8011a36:	bf00      	nop
 8011a38:	e7fd      	b.n	8011a36 <vTaskPlaceOnEventListRestricted+0x26>

		/* Place the event list item of the TCB in the appropriate event list.
		In this case it is assume that this is the only task that is going to
		be waiting on this event list, so the faster vListInsertEnd() function
		can be used in place of vListInsert. */
		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 8011a3a:	4b0a      	ldr	r3, [pc, #40]	@ (8011a64 <vTaskPlaceOnEventListRestricted+0x54>)
 8011a3c:	681b      	ldr	r3, [r3, #0]
 8011a3e:	3318      	adds	r3, #24
 8011a40:	4619      	mov	r1, r3
 8011a42:	68f8      	ldr	r0, [r7, #12]
 8011a44:	f7fe f993 	bl	800fd6e <vListInsertEnd>

		/* If the task should block indefinitely then set the block time to a
		value that will be recognised as an indefinite delay inside the
		prvAddCurrentTaskToDelayedList() function. */
		if( xWaitIndefinitely != pdFALSE )
 8011a48:	687b      	ldr	r3, [r7, #4]
 8011a4a:	2b00      	cmp	r3, #0
 8011a4c:	d002      	beq.n	8011a54 <vTaskPlaceOnEventListRestricted+0x44>
		{
			xTicksToWait = portMAX_DELAY;
 8011a4e:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8011a52:	60bb      	str	r3, [r7, #8]
		}

		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
 8011a54:	6879      	ldr	r1, [r7, #4]
 8011a56:	68b8      	ldr	r0, [r7, #8]
 8011a58:	f000 fdc0 	bl	80125dc <prvAddCurrentTaskToDelayedList>
	}
 8011a5c:	bf00      	nop
 8011a5e:	3718      	adds	r7, #24
 8011a60:	46bd      	mov	sp, r7
 8011a62:	bd80      	pop	{r7, pc}
 8011a64:	240023f4 	.word	0x240023f4

08011a68 <xTaskRemoveFromEventList>:

#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/

BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
 8011a68:	b580      	push	{r7, lr}
 8011a6a:	b086      	sub	sp, #24
 8011a6c:	af00      	add	r7, sp, #0
 8011a6e:	6078      	str	r0, [r7, #4]
	get called - the lock count on the queue will get modified instead.  This
	means exclusive access to the event list is guaranteed here.

	This function assumes that a check has already been made to ensure that
	pxEventList is not empty. */
	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8011a70:	687b      	ldr	r3, [r7, #4]
 8011a72:	68db      	ldr	r3, [r3, #12]
 8011a74:	68db      	ldr	r3, [r3, #12]
 8011a76:	613b      	str	r3, [r7, #16]
	configASSERT( pxUnblockedTCB );
 8011a78:	693b      	ldr	r3, [r7, #16]
 8011a7a:	2b00      	cmp	r3, #0
 8011a7c:	d10b      	bne.n	8011a96 <xTaskRemoveFromEventList+0x2e>
	__asm volatile
 8011a7e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011a82:	f383 8811 	msr	BASEPRI, r3
 8011a86:	f3bf 8f6f 	isb	sy
 8011a8a:	f3bf 8f4f 	dsb	sy
 8011a8e:	60fb      	str	r3, [r7, #12]
}
 8011a90:	bf00      	nop
 8011a92:	bf00      	nop
 8011a94:	e7fd      	b.n	8011a92 <xTaskRemoveFromEventList+0x2a>
	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
 8011a96:	693b      	ldr	r3, [r7, #16]
 8011a98:	3318      	adds	r3, #24
 8011a9a:	4618      	mov	r0, r3
 8011a9c:	f7fe f9c4 	bl	800fe28 <uxListRemove>

	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8011aa0:	4b1d      	ldr	r3, [pc, #116]	@ (8011b18 <xTaskRemoveFromEventList+0xb0>)
 8011aa2:	681b      	ldr	r3, [r3, #0]
 8011aa4:	2b00      	cmp	r3, #0
 8011aa6:	d11d      	bne.n	8011ae4 <xTaskRemoveFromEventList+0x7c>
	{
		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
 8011aa8:	693b      	ldr	r3, [r7, #16]
 8011aaa:	3304      	adds	r3, #4
 8011aac:	4618      	mov	r0, r3
 8011aae:	f7fe f9bb 	bl	800fe28 <uxListRemove>
		prvAddTaskToReadyList( pxUnblockedTCB );
 8011ab2:	693b      	ldr	r3, [r7, #16]
 8011ab4:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011ab6:	4b19      	ldr	r3, [pc, #100]	@ (8011b1c <xTaskRemoveFromEventList+0xb4>)
 8011ab8:	681b      	ldr	r3, [r3, #0]
 8011aba:	429a      	cmp	r2, r3
 8011abc:	d903      	bls.n	8011ac6 <xTaskRemoveFromEventList+0x5e>
 8011abe:	693b      	ldr	r3, [r7, #16]
 8011ac0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8011ac2:	4a16      	ldr	r2, [pc, #88]	@ (8011b1c <xTaskRemoveFromEventList+0xb4>)
 8011ac4:	6013      	str	r3, [r2, #0]
 8011ac6:	693b      	ldr	r3, [r7, #16]
 8011ac8:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011aca:	4613      	mov	r3, r2
 8011acc:	009b      	lsls	r3, r3, #2
 8011ace:	4413      	add	r3, r2
 8011ad0:	009b      	lsls	r3, r3, #2
 8011ad2:	4a13      	ldr	r2, [pc, #76]	@ (8011b20 <xTaskRemoveFromEventList+0xb8>)
 8011ad4:	441a      	add	r2, r3
 8011ad6:	693b      	ldr	r3, [r7, #16]
 8011ad8:	3304      	adds	r3, #4
 8011ada:	4619      	mov	r1, r3
 8011adc:	4610      	mov	r0, r2
 8011ade:	f7fe f946 	bl	800fd6e <vListInsertEnd>
 8011ae2:	e005      	b.n	8011af0 <xTaskRemoveFromEventList+0x88>
	}
	else
	{
		/* The delayed and ready lists cannot be accessed, so hold this task
		pending until the scheduler is resumed. */
		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
 8011ae4:	693b      	ldr	r3, [r7, #16]
 8011ae6:	3318      	adds	r3, #24
 8011ae8:	4619      	mov	r1, r3
 8011aea:	480e      	ldr	r0, [pc, #56]	@ (8011b24 <xTaskRemoveFromEventList+0xbc>)
 8011aec:	f7fe f93f 	bl	800fd6e <vListInsertEnd>
	}

	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
 8011af0:	693b      	ldr	r3, [r7, #16]
 8011af2:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011af4:	4b0c      	ldr	r3, [pc, #48]	@ (8011b28 <xTaskRemoveFromEventList+0xc0>)
 8011af6:	681b      	ldr	r3, [r3, #0]
 8011af8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8011afa:	429a      	cmp	r2, r3
 8011afc:	d905      	bls.n	8011b0a <xTaskRemoveFromEventList+0xa2>
	{
		/* Return true if the task removed from the event list has a higher
		priority than the calling task.  This allows the calling task to know if
		it should force a context switch now. */
		xReturn = pdTRUE;
 8011afe:	2301      	movs	r3, #1
 8011b00:	617b      	str	r3, [r7, #20]

		/* Mark that a yield is pending in case the user is not using the
		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
		xYieldPending = pdTRUE;
 8011b02:	4b0a      	ldr	r3, [pc, #40]	@ (8011b2c <xTaskRemoveFromEventList+0xc4>)
 8011b04:	2201      	movs	r2, #1
 8011b06:	601a      	str	r2, [r3, #0]
 8011b08:	e001      	b.n	8011b0e <xTaskRemoveFromEventList+0xa6>
	}
	else
	{
		xReturn = pdFALSE;
 8011b0a:	2300      	movs	r3, #0
 8011b0c:	617b      	str	r3, [r7, #20]
	}

	return xReturn;
 8011b0e:	697b      	ldr	r3, [r7, #20]
}
 8011b10:	4618      	mov	r0, r3
 8011b12:	3718      	adds	r7, #24
 8011b14:	46bd      	mov	sp, r7
 8011b16:	bd80      	pop	{r7, pc}
 8011b18:	240028f0 	.word	0x240028f0
 8011b1c:	240028d0 	.word	0x240028d0
 8011b20:	240023f8 	.word	0x240023f8
 8011b24:	24002888 	.word	0x24002888
 8011b28:	240023f4 	.word	0x240023f4
 8011b2c:	240028dc 	.word	0x240028dc

08011b30 <vTaskSetTimeOutState>:
	}
}
/*-----------------------------------------------------------*/

void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
{
 8011b30:	b580      	push	{r7, lr}
 8011b32:	b084      	sub	sp, #16
 8011b34:	af00      	add	r7, sp, #0
 8011b36:	6078      	str	r0, [r7, #4]
	configASSERT( pxTimeOut );
 8011b38:	687b      	ldr	r3, [r7, #4]
 8011b3a:	2b00      	cmp	r3, #0
 8011b3c:	d10b      	bne.n	8011b56 <vTaskSetTimeOutState+0x26>
	__asm volatile
 8011b3e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011b42:	f383 8811 	msr	BASEPRI, r3
 8011b46:	f3bf 8f6f 	isb	sy
 8011b4a:	f3bf 8f4f 	dsb	sy
 8011b4e:	60fb      	str	r3, [r7, #12]
}
 8011b50:	bf00      	nop
 8011b52:	bf00      	nop
 8011b54:	e7fd      	b.n	8011b52 <vTaskSetTimeOutState+0x22>
	taskENTER_CRITICAL();
 8011b56:	f001 fa1f 	bl	8012f98 <vPortEnterCritical>
	{
		pxTimeOut->xOverflowCount = xNumOfOverflows;
 8011b5a:	4b07      	ldr	r3, [pc, #28]	@ (8011b78 <vTaskSetTimeOutState+0x48>)
 8011b5c:	681a      	ldr	r2, [r3, #0]
 8011b5e:	687b      	ldr	r3, [r7, #4]
 8011b60:	601a      	str	r2, [r3, #0]
		pxTimeOut->xTimeOnEntering = xTickCount;
 8011b62:	4b06      	ldr	r3, [pc, #24]	@ (8011b7c <vTaskSetTimeOutState+0x4c>)
 8011b64:	681a      	ldr	r2, [r3, #0]
 8011b66:	687b      	ldr	r3, [r7, #4]
 8011b68:	605a      	str	r2, [r3, #4]
	}
	taskEXIT_CRITICAL();
 8011b6a:	f001 fa47 	bl	8012ffc <vPortExitCritical>
}
 8011b6e:	bf00      	nop
 8011b70:	3710      	adds	r7, #16
 8011b72:	46bd      	mov	sp, r7
 8011b74:	bd80      	pop	{r7, pc}
 8011b76:	bf00      	nop
 8011b78:	240028e0 	.word	0x240028e0
 8011b7c:	240028cc 	.word	0x240028cc

08011b80 <vTaskInternalSetTimeOutState>:
/*-----------------------------------------------------------*/

void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
 8011b80:	b480      	push	{r7}
 8011b82:	b083      	sub	sp, #12
 8011b84:	af00      	add	r7, sp, #0
 8011b86:	6078      	str	r0, [r7, #4]
	/* For internal use only as it does not use a critical section. */
	pxTimeOut->xOverflowCount = xNumOfOverflows;
 8011b88:	4b06      	ldr	r3, [pc, #24]	@ (8011ba4 <vTaskInternalSetTimeOutState+0x24>)
 8011b8a:	681a      	ldr	r2, [r3, #0]
 8011b8c:	687b      	ldr	r3, [r7, #4]
 8011b8e:	601a      	str	r2, [r3, #0]
	pxTimeOut->xTimeOnEntering = xTickCount;
 8011b90:	4b05      	ldr	r3, [pc, #20]	@ (8011ba8 <vTaskInternalSetTimeOutState+0x28>)
 8011b92:	681a      	ldr	r2, [r3, #0]
 8011b94:	687b      	ldr	r3, [r7, #4]
 8011b96:	605a      	str	r2, [r3, #4]
}
 8011b98:	bf00      	nop
 8011b9a:	370c      	adds	r7, #12
 8011b9c:	46bd      	mov	sp, r7
 8011b9e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8011ba2:	4770      	bx	lr
 8011ba4:	240028e0 	.word	0x240028e0
 8011ba8:	240028cc 	.word	0x240028cc

08011bac <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/

BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
 8011bac:	b580      	push	{r7, lr}
 8011bae:	b088      	sub	sp, #32
 8011bb0:	af00      	add	r7, sp, #0
 8011bb2:	6078      	str	r0, [r7, #4]
 8011bb4:	6039      	str	r1, [r7, #0]
BaseType_t xReturn;

	configASSERT( pxTimeOut );
 8011bb6:	687b      	ldr	r3, [r7, #4]
 8011bb8:	2b00      	cmp	r3, #0
 8011bba:	d10b      	bne.n	8011bd4 <xTaskCheckForTimeOut+0x28>
	__asm volatile
 8011bbc:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011bc0:	f383 8811 	msr	BASEPRI, r3
 8011bc4:	f3bf 8f6f 	isb	sy
 8011bc8:	f3bf 8f4f 	dsb	sy
 8011bcc:	613b      	str	r3, [r7, #16]
}
 8011bce:	bf00      	nop
 8011bd0:	bf00      	nop
 8011bd2:	e7fd      	b.n	8011bd0 <xTaskCheckForTimeOut+0x24>
	configASSERT( pxTicksToWait );
 8011bd4:	683b      	ldr	r3, [r7, #0]
 8011bd6:	2b00      	cmp	r3, #0
 8011bd8:	d10b      	bne.n	8011bf2 <xTaskCheckForTimeOut+0x46>
	__asm volatile
 8011bda:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011bde:	f383 8811 	msr	BASEPRI, r3
 8011be2:	f3bf 8f6f 	isb	sy
 8011be6:	f3bf 8f4f 	dsb	sy
 8011bea:	60fb      	str	r3, [r7, #12]
}
 8011bec:	bf00      	nop
 8011bee:	bf00      	nop
 8011bf0:	e7fd      	b.n	8011bee <xTaskCheckForTimeOut+0x42>

	taskENTER_CRITICAL();
 8011bf2:	f001 f9d1 	bl	8012f98 <vPortEnterCritical>
	{
		/* Minor optimisation.  The tick count cannot change in this block. */
		const TickType_t xConstTickCount = xTickCount;
 8011bf6:	4b1d      	ldr	r3, [pc, #116]	@ (8011c6c <xTaskCheckForTimeOut+0xc0>)
 8011bf8:	681b      	ldr	r3, [r3, #0]
 8011bfa:	61bb      	str	r3, [r7, #24]
		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
 8011bfc:	687b      	ldr	r3, [r7, #4]
 8011bfe:	685b      	ldr	r3, [r3, #4]
 8011c00:	69ba      	ldr	r2, [r7, #24]
 8011c02:	1ad3      	subs	r3, r2, r3
 8011c04:	617b      	str	r3, [r7, #20]
			}
			else
		#endif

		#if ( INCLUDE_vTaskSuspend == 1 )
			if( *pxTicksToWait == portMAX_DELAY )
 8011c06:	683b      	ldr	r3, [r7, #0]
 8011c08:	681b      	ldr	r3, [r3, #0]
 8011c0a:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8011c0e:	d102      	bne.n	8011c16 <xTaskCheckForTimeOut+0x6a>
			{
				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
				specified is the maximum block time then the task should block
				indefinitely, and therefore never time out. */
				xReturn = pdFALSE;
 8011c10:	2300      	movs	r3, #0
 8011c12:	61fb      	str	r3, [r7, #28]
 8011c14:	e023      	b.n	8011c5e <xTaskCheckForTimeOut+0xb2>
			}
			else
		#endif

		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
 8011c16:	687b      	ldr	r3, [r7, #4]
 8011c18:	681a      	ldr	r2, [r3, #0]
 8011c1a:	4b15      	ldr	r3, [pc, #84]	@ (8011c70 <xTaskCheckForTimeOut+0xc4>)
 8011c1c:	681b      	ldr	r3, [r3, #0]
 8011c1e:	429a      	cmp	r2, r3
 8011c20:	d007      	beq.n	8011c32 <xTaskCheckForTimeOut+0x86>
 8011c22:	687b      	ldr	r3, [r7, #4]
 8011c24:	685b      	ldr	r3, [r3, #4]
 8011c26:	69ba      	ldr	r2, [r7, #24]
 8011c28:	429a      	cmp	r2, r3
 8011c2a:	d302      	bcc.n	8011c32 <xTaskCheckForTimeOut+0x86>
			/* The tick count is greater than the time at which
			vTaskSetTimeout() was called, but has also overflowed since
			vTaskSetTimeOut() was called.  It must have wrapped all the way
			around and gone past again. This passed since vTaskSetTimeout()
			was called. */
			xReturn = pdTRUE;
 8011c2c:	2301      	movs	r3, #1
 8011c2e:	61fb      	str	r3, [r7, #28]
 8011c30:	e015      	b.n	8011c5e <xTaskCheckForTimeOut+0xb2>
		}
		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
 8011c32:	683b      	ldr	r3, [r7, #0]
 8011c34:	681b      	ldr	r3, [r3, #0]
 8011c36:	697a      	ldr	r2, [r7, #20]
 8011c38:	429a      	cmp	r2, r3
 8011c3a:	d20b      	bcs.n	8011c54 <xTaskCheckForTimeOut+0xa8>
		{
			/* Not a genuine timeout. Adjust parameters for time remaining. */
			*pxTicksToWait -= xElapsedTime;
 8011c3c:	683b      	ldr	r3, [r7, #0]
 8011c3e:	681a      	ldr	r2, [r3, #0]
 8011c40:	697b      	ldr	r3, [r7, #20]
 8011c42:	1ad2      	subs	r2, r2, r3
 8011c44:	683b      	ldr	r3, [r7, #0]
 8011c46:	601a      	str	r2, [r3, #0]
			vTaskInternalSetTimeOutState( pxTimeOut );
 8011c48:	6878      	ldr	r0, [r7, #4]
 8011c4a:	f7ff ff99 	bl	8011b80 <vTaskInternalSetTimeOutState>
			xReturn = pdFALSE;
 8011c4e:	2300      	movs	r3, #0
 8011c50:	61fb      	str	r3, [r7, #28]
 8011c52:	e004      	b.n	8011c5e <xTaskCheckForTimeOut+0xb2>
		}
		else
		{
			*pxTicksToWait = 0;
 8011c54:	683b      	ldr	r3, [r7, #0]
 8011c56:	2200      	movs	r2, #0
 8011c58:	601a      	str	r2, [r3, #0]
			xReturn = pdTRUE;
 8011c5a:	2301      	movs	r3, #1
 8011c5c:	61fb      	str	r3, [r7, #28]
		}
	}
	taskEXIT_CRITICAL();
 8011c5e:	f001 f9cd 	bl	8012ffc <vPortExitCritical>

	return xReturn;
 8011c62:	69fb      	ldr	r3, [r7, #28]
}
 8011c64:	4618      	mov	r0, r3
 8011c66:	3720      	adds	r7, #32
 8011c68:	46bd      	mov	sp, r7
 8011c6a:	bd80      	pop	{r7, pc}
 8011c6c:	240028cc 	.word	0x240028cc
 8011c70:	240028e0 	.word	0x240028e0

08011c74 <vTaskMissedYield>:
/*-----------------------------------------------------------*/

void vTaskMissedYield( void )
{
 8011c74:	b480      	push	{r7}
 8011c76:	af00      	add	r7, sp, #0
	xYieldPending = pdTRUE;
 8011c78:	4b03      	ldr	r3, [pc, #12]	@ (8011c88 <vTaskMissedYield+0x14>)
 8011c7a:	2201      	movs	r2, #1
 8011c7c:	601a      	str	r2, [r3, #0]
}
 8011c7e:	bf00      	nop
 8011c80:	46bd      	mov	sp, r7
 8011c82:	f85d 7b04 	ldr.w	r7, [sp], #4
 8011c86:	4770      	bx	lr
 8011c88:	240028dc 	.word	0x240028dc

08011c8c <prvIdleTask>:
 *
 * void prvIdleTask( void *pvParameters );
 *
 */
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
 8011c8c:	b580      	push	{r7, lr}
 8011c8e:	b082      	sub	sp, #8
 8011c90:	af00      	add	r7, sp, #0
 8011c92:	6078      	str	r0, [r7, #4]

	for( ;; )
	{
		/* See if any tasks have deleted themselves - if so then the idle task
		is responsible for freeing the deleted task's TCB and stack. */
		prvCheckTasksWaitingTermination();
 8011c94:	f000 f852 	bl	8011d3c <prvCheckTasksWaitingTermination>

			A critical region is not required here as we are just reading from
			the list, and an occasional incorrect value will not matter.  If
			the ready list at the idle priority contains more than one task
			then a task other than the idle task is ready to execute. */
			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
 8011c98:	4b06      	ldr	r3, [pc, #24]	@ (8011cb4 <prvIdleTask+0x28>)
 8011c9a:	681b      	ldr	r3, [r3, #0]
 8011c9c:	2b01      	cmp	r3, #1
 8011c9e:	d9f9      	bls.n	8011c94 <prvIdleTask+0x8>
			{
				taskYIELD();
 8011ca0:	4b05      	ldr	r3, [pc, #20]	@ (8011cb8 <prvIdleTask+0x2c>)
 8011ca2:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8011ca6:	601a      	str	r2, [r3, #0]
 8011ca8:	f3bf 8f4f 	dsb	sy
 8011cac:	f3bf 8f6f 	isb	sy
		prvCheckTasksWaitingTermination();
 8011cb0:	e7f0      	b.n	8011c94 <prvIdleTask+0x8>
 8011cb2:	bf00      	nop
 8011cb4:	240023f8 	.word	0x240023f8
 8011cb8:	e000ed04 	.word	0xe000ed04

08011cbc <prvInitialiseTaskLists>:

#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/

static void prvInitialiseTaskLists( void )
{
 8011cbc:	b580      	push	{r7, lr}
 8011cbe:	b082      	sub	sp, #8
 8011cc0:	af00      	add	r7, sp, #0
UBaseType_t uxPriority;

	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
 8011cc2:	2300      	movs	r3, #0
 8011cc4:	607b      	str	r3, [r7, #4]
 8011cc6:	e00c      	b.n	8011ce2 <prvInitialiseTaskLists+0x26>
	{
		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
 8011cc8:	687a      	ldr	r2, [r7, #4]
 8011cca:	4613      	mov	r3, r2
 8011ccc:	009b      	lsls	r3, r3, #2
 8011cce:	4413      	add	r3, r2
 8011cd0:	009b      	lsls	r3, r3, #2
 8011cd2:	4a12      	ldr	r2, [pc, #72]	@ (8011d1c <prvInitialiseTaskLists+0x60>)
 8011cd4:	4413      	add	r3, r2
 8011cd6:	4618      	mov	r0, r3
 8011cd8:	f7fe f81c 	bl	800fd14 <vListInitialise>
	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
 8011cdc:	687b      	ldr	r3, [r7, #4]
 8011cde:	3301      	adds	r3, #1
 8011ce0:	607b      	str	r3, [r7, #4]
 8011ce2:	687b      	ldr	r3, [r7, #4]
 8011ce4:	2b37      	cmp	r3, #55	@ 0x37
 8011ce6:	d9ef      	bls.n	8011cc8 <prvInitialiseTaskLists+0xc>
	}

	vListInitialise( &xDelayedTaskList1 );
 8011ce8:	480d      	ldr	r0, [pc, #52]	@ (8011d20 <prvInitialiseTaskLists+0x64>)
 8011cea:	f7fe f813 	bl	800fd14 <vListInitialise>
	vListInitialise( &xDelayedTaskList2 );
 8011cee:	480d      	ldr	r0, [pc, #52]	@ (8011d24 <prvInitialiseTaskLists+0x68>)
 8011cf0:	f7fe f810 	bl	800fd14 <vListInitialise>
	vListInitialise( &xPendingReadyList );
 8011cf4:	480c      	ldr	r0, [pc, #48]	@ (8011d28 <prvInitialiseTaskLists+0x6c>)
 8011cf6:	f7fe f80d 	bl	800fd14 <vListInitialise>

	#if ( INCLUDE_vTaskDelete == 1 )
	{
		vListInitialise( &xTasksWaitingTermination );
 8011cfa:	480c      	ldr	r0, [pc, #48]	@ (8011d2c <prvInitialiseTaskLists+0x70>)
 8011cfc:	f7fe f80a 	bl	800fd14 <vListInitialise>
	}
	#endif /* INCLUDE_vTaskDelete */

	#if ( INCLUDE_vTaskSuspend == 1 )
	{
		vListInitialise( &xSuspendedTaskList );
 8011d00:	480b      	ldr	r0, [pc, #44]	@ (8011d30 <prvInitialiseTaskLists+0x74>)
 8011d02:	f7fe f807 	bl	800fd14 <vListInitialise>
	}
	#endif /* INCLUDE_vTaskSuspend */

	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
	using list2. */
	pxDelayedTaskList = &xDelayedTaskList1;
 8011d06:	4b0b      	ldr	r3, [pc, #44]	@ (8011d34 <prvInitialiseTaskLists+0x78>)
 8011d08:	4a05      	ldr	r2, [pc, #20]	@ (8011d20 <prvInitialiseTaskLists+0x64>)
 8011d0a:	601a      	str	r2, [r3, #0]
	pxOverflowDelayedTaskList = &xDelayedTaskList2;
 8011d0c:	4b0a      	ldr	r3, [pc, #40]	@ (8011d38 <prvInitialiseTaskLists+0x7c>)
 8011d0e:	4a05      	ldr	r2, [pc, #20]	@ (8011d24 <prvInitialiseTaskLists+0x68>)
 8011d10:	601a      	str	r2, [r3, #0]
}
 8011d12:	bf00      	nop
 8011d14:	3708      	adds	r7, #8
 8011d16:	46bd      	mov	sp, r7
 8011d18:	bd80      	pop	{r7, pc}
 8011d1a:	bf00      	nop
 8011d1c:	240023f8 	.word	0x240023f8
 8011d20:	24002858 	.word	0x24002858
 8011d24:	2400286c 	.word	0x2400286c
 8011d28:	24002888 	.word	0x24002888
 8011d2c:	2400289c 	.word	0x2400289c
 8011d30:	240028b4 	.word	0x240028b4
 8011d34:	24002880 	.word	0x24002880
 8011d38:	24002884 	.word	0x24002884

08011d3c <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/

static void prvCheckTasksWaitingTermination( void )
{
 8011d3c:	b580      	push	{r7, lr}
 8011d3e:	b082      	sub	sp, #8
 8011d40:	af00      	add	r7, sp, #0
	{
		TCB_t *pxTCB;

		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
		being called too often in the idle task. */
		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 8011d42:	e019      	b.n	8011d78 <prvCheckTasksWaitingTermination+0x3c>
		{
			taskENTER_CRITICAL();
 8011d44:	f001 f928 	bl	8012f98 <vPortEnterCritical>
			{
				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8011d48:	4b10      	ldr	r3, [pc, #64]	@ (8011d8c <prvCheckTasksWaitingTermination+0x50>)
 8011d4a:	68db      	ldr	r3, [r3, #12]
 8011d4c:	68db      	ldr	r3, [r3, #12]
 8011d4e:	607b      	str	r3, [r7, #4]
				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8011d50:	687b      	ldr	r3, [r7, #4]
 8011d52:	3304      	adds	r3, #4
 8011d54:	4618      	mov	r0, r3
 8011d56:	f7fe f867 	bl	800fe28 <uxListRemove>
				--uxCurrentNumberOfTasks;
 8011d5a:	4b0d      	ldr	r3, [pc, #52]	@ (8011d90 <prvCheckTasksWaitingTermination+0x54>)
 8011d5c:	681b      	ldr	r3, [r3, #0]
 8011d5e:	3b01      	subs	r3, #1
 8011d60:	4a0b      	ldr	r2, [pc, #44]	@ (8011d90 <prvCheckTasksWaitingTermination+0x54>)
 8011d62:	6013      	str	r3, [r2, #0]
				--uxDeletedTasksWaitingCleanUp;
 8011d64:	4b0b      	ldr	r3, [pc, #44]	@ (8011d94 <prvCheckTasksWaitingTermination+0x58>)
 8011d66:	681b      	ldr	r3, [r3, #0]
 8011d68:	3b01      	subs	r3, #1
 8011d6a:	4a0a      	ldr	r2, [pc, #40]	@ (8011d94 <prvCheckTasksWaitingTermination+0x58>)
 8011d6c:	6013      	str	r3, [r2, #0]
			}
			taskEXIT_CRITICAL();
 8011d6e:	f001 f945 	bl	8012ffc <vPortExitCritical>

			prvDeleteTCB( pxTCB );
 8011d72:	6878      	ldr	r0, [r7, #4]
 8011d74:	f000 f810 	bl	8011d98 <prvDeleteTCB>
		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 8011d78:	4b06      	ldr	r3, [pc, #24]	@ (8011d94 <prvCheckTasksWaitingTermination+0x58>)
 8011d7a:	681b      	ldr	r3, [r3, #0]
 8011d7c:	2b00      	cmp	r3, #0
 8011d7e:	d1e1      	bne.n	8011d44 <prvCheckTasksWaitingTermination+0x8>
		}
	}
	#endif /* INCLUDE_vTaskDelete */
}
 8011d80:	bf00      	nop
 8011d82:	bf00      	nop
 8011d84:	3708      	adds	r7, #8
 8011d86:	46bd      	mov	sp, r7
 8011d88:	bd80      	pop	{r7, pc}
 8011d8a:	bf00      	nop
 8011d8c:	2400289c 	.word	0x2400289c
 8011d90:	240028c8 	.word	0x240028c8
 8011d94:	240028b0 	.word	0x240028b0

08011d98 <prvDeleteTCB>:
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelete == 1 )

	static void prvDeleteTCB( TCB_t *pxTCB )
	{
 8011d98:	b580      	push	{r7, lr}
 8011d9a:	b084      	sub	sp, #16
 8011d9c:	af00      	add	r7, sp, #0
 8011d9e:	6078      	str	r0, [r7, #4]
		to the task to free any memory allocated at the application level.
		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
		for additional information. */
		#if ( configUSE_NEWLIB_REENTRANT == 1 )
		{
			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
 8011da0:	687b      	ldr	r3, [r7, #4]
 8011da2:	3354      	adds	r3, #84	@ 0x54
 8011da4:	4618      	mov	r0, r3
 8011da6:	f001 fd37 	bl	8013818 <_reclaim_reent>
		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
		{
			/* The task could have been allocated statically or dynamically, so
			check what was statically allocated before trying to free the
			memory. */
			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
 8011daa:	687b      	ldr	r3, [r7, #4]
 8011dac:	f893 30a5 	ldrb.w	r3, [r3, #165]	@ 0xa5
 8011db0:	2b00      	cmp	r3, #0
 8011db2:	d108      	bne.n	8011dc6 <prvDeleteTCB+0x2e>
			{
				/* Both the stack and TCB were allocated dynamically, so both
				must be freed. */
				vPortFree( pxTCB->pxStack );
 8011db4:	687b      	ldr	r3, [r7, #4]
 8011db6:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8011db8:	4618      	mov	r0, r3
 8011dba:	f001 fadd 	bl	8013378 <vPortFree>
				vPortFree( pxTCB );
 8011dbe:	6878      	ldr	r0, [r7, #4]
 8011dc0:	f001 fada 	bl	8013378 <vPortFree>
				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
				mtCOVERAGE_TEST_MARKER();
			}
		}
		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
	}
 8011dc4:	e019      	b.n	8011dfa <prvDeleteTCB+0x62>
			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
 8011dc6:	687b      	ldr	r3, [r7, #4]
 8011dc8:	f893 30a5 	ldrb.w	r3, [r3, #165]	@ 0xa5
 8011dcc:	2b01      	cmp	r3, #1
 8011dce:	d103      	bne.n	8011dd8 <prvDeleteTCB+0x40>
				vPortFree( pxTCB );
 8011dd0:	6878      	ldr	r0, [r7, #4]
 8011dd2:	f001 fad1 	bl	8013378 <vPortFree>
	}
 8011dd6:	e010      	b.n	8011dfa <prvDeleteTCB+0x62>
				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
 8011dd8:	687b      	ldr	r3, [r7, #4]
 8011dda:	f893 30a5 	ldrb.w	r3, [r3, #165]	@ 0xa5
 8011dde:	2b02      	cmp	r3, #2
 8011de0:	d00b      	beq.n	8011dfa <prvDeleteTCB+0x62>
	__asm volatile
 8011de2:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011de6:	f383 8811 	msr	BASEPRI, r3
 8011dea:	f3bf 8f6f 	isb	sy
 8011dee:	f3bf 8f4f 	dsb	sy
 8011df2:	60fb      	str	r3, [r7, #12]
}
 8011df4:	bf00      	nop
 8011df6:	bf00      	nop
 8011df8:	e7fd      	b.n	8011df6 <prvDeleteTCB+0x5e>
	}
 8011dfa:	bf00      	nop
 8011dfc:	3710      	adds	r7, #16
 8011dfe:	46bd      	mov	sp, r7
 8011e00:	bd80      	pop	{r7, pc}
	...

08011e04 <prvResetNextTaskUnblockTime>:

#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/

static void prvResetNextTaskUnblockTime( void )
{
 8011e04:	b480      	push	{r7}
 8011e06:	b083      	sub	sp, #12
 8011e08:	af00      	add	r7, sp, #0
TCB_t *pxTCB;

	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 8011e0a:	4b0c      	ldr	r3, [pc, #48]	@ (8011e3c <prvResetNextTaskUnblockTime+0x38>)
 8011e0c:	681b      	ldr	r3, [r3, #0]
 8011e0e:	681b      	ldr	r3, [r3, #0]
 8011e10:	2b00      	cmp	r3, #0
 8011e12:	d104      	bne.n	8011e1e <prvResetNextTaskUnblockTime+0x1a>
	{
		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
		the maximum possible value so it is	extremely unlikely that the
		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
		there is an item in the delayed list. */
		xNextTaskUnblockTime = portMAX_DELAY;
 8011e14:	4b0a      	ldr	r3, [pc, #40]	@ (8011e40 <prvResetNextTaskUnblockTime+0x3c>)
 8011e16:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8011e1a:	601a      	str	r2, [r3, #0]
		which the task at the head of the delayed list should be removed
		from the Blocked state. */
		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
	}
}
 8011e1c:	e008      	b.n	8011e30 <prvResetNextTaskUnblockTime+0x2c>
		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8011e1e:	4b07      	ldr	r3, [pc, #28]	@ (8011e3c <prvResetNextTaskUnblockTime+0x38>)
 8011e20:	681b      	ldr	r3, [r3, #0]
 8011e22:	68db      	ldr	r3, [r3, #12]
 8011e24:	68db      	ldr	r3, [r3, #12]
 8011e26:	607b      	str	r3, [r7, #4]
		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
 8011e28:	687b      	ldr	r3, [r7, #4]
 8011e2a:	685b      	ldr	r3, [r3, #4]
 8011e2c:	4a04      	ldr	r2, [pc, #16]	@ (8011e40 <prvResetNextTaskUnblockTime+0x3c>)
 8011e2e:	6013      	str	r3, [r2, #0]
}
 8011e30:	bf00      	nop
 8011e32:	370c      	adds	r7, #12
 8011e34:	46bd      	mov	sp, r7
 8011e36:	f85d 7b04 	ldr.w	r7, [sp], #4
 8011e3a:	4770      	bx	lr
 8011e3c:	24002880 	.word	0x24002880
 8011e40:	240028e8 	.word	0x240028e8

08011e44 <xTaskGetCurrentTaskHandle>:
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )

	TaskHandle_t xTaskGetCurrentTaskHandle( void )
	{
 8011e44:	b480      	push	{r7}
 8011e46:	b083      	sub	sp, #12
 8011e48:	af00      	add	r7, sp, #0
	TaskHandle_t xReturn;

		/* A critical section is not required as this is not called from
		an interrupt and the current TCB will always be the same for any
		individual execution thread. */
		xReturn = pxCurrentTCB;
 8011e4a:	4b05      	ldr	r3, [pc, #20]	@ (8011e60 <xTaskGetCurrentTaskHandle+0x1c>)
 8011e4c:	681b      	ldr	r3, [r3, #0]
 8011e4e:	607b      	str	r3, [r7, #4]

		return xReturn;
 8011e50:	687b      	ldr	r3, [r7, #4]
	}
 8011e52:	4618      	mov	r0, r3
 8011e54:	370c      	adds	r7, #12
 8011e56:	46bd      	mov	sp, r7
 8011e58:	f85d 7b04 	ldr.w	r7, [sp], #4
 8011e5c:	4770      	bx	lr
 8011e5e:	bf00      	nop
 8011e60:	240023f4 	.word	0x240023f4

08011e64 <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

	BaseType_t xTaskGetSchedulerState( void )
	{
 8011e64:	b480      	push	{r7}
 8011e66:	b083      	sub	sp, #12
 8011e68:	af00      	add	r7, sp, #0
	BaseType_t xReturn;

		if( xSchedulerRunning == pdFALSE )
 8011e6a:	4b0b      	ldr	r3, [pc, #44]	@ (8011e98 <xTaskGetSchedulerState+0x34>)
 8011e6c:	681b      	ldr	r3, [r3, #0]
 8011e6e:	2b00      	cmp	r3, #0
 8011e70:	d102      	bne.n	8011e78 <xTaskGetSchedulerState+0x14>
		{
			xReturn = taskSCHEDULER_NOT_STARTED;
 8011e72:	2301      	movs	r3, #1
 8011e74:	607b      	str	r3, [r7, #4]
 8011e76:	e008      	b.n	8011e8a <xTaskGetSchedulerState+0x26>
		}
		else
		{
			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8011e78:	4b08      	ldr	r3, [pc, #32]	@ (8011e9c <xTaskGetSchedulerState+0x38>)
 8011e7a:	681b      	ldr	r3, [r3, #0]
 8011e7c:	2b00      	cmp	r3, #0
 8011e7e:	d102      	bne.n	8011e86 <xTaskGetSchedulerState+0x22>
			{
				xReturn = taskSCHEDULER_RUNNING;
 8011e80:	2302      	movs	r3, #2
 8011e82:	607b      	str	r3, [r7, #4]
 8011e84:	e001      	b.n	8011e8a <xTaskGetSchedulerState+0x26>
			}
			else
			{
				xReturn = taskSCHEDULER_SUSPENDED;
 8011e86:	2300      	movs	r3, #0
 8011e88:	607b      	str	r3, [r7, #4]
			}
		}

		return xReturn;
 8011e8a:	687b      	ldr	r3, [r7, #4]
	}
 8011e8c:	4618      	mov	r0, r3
 8011e8e:	370c      	adds	r7, #12
 8011e90:	46bd      	mov	sp, r7
 8011e92:	f85d 7b04 	ldr.w	r7, [sp], #4
 8011e96:	4770      	bx	lr
 8011e98:	240028d4 	.word	0x240028d4
 8011e9c:	240028f0 	.word	0x240028f0

08011ea0 <xTaskPriorityInherit>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
	{
 8011ea0:	b580      	push	{r7, lr}
 8011ea2:	b084      	sub	sp, #16
 8011ea4:	af00      	add	r7, sp, #0
 8011ea6:	6078      	str	r0, [r7, #4]
	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
 8011ea8:	687b      	ldr	r3, [r7, #4]
 8011eaa:	60bb      	str	r3, [r7, #8]
	BaseType_t xReturn = pdFALSE;
 8011eac:	2300      	movs	r3, #0
 8011eae:	60fb      	str	r3, [r7, #12]

		/* If the mutex was given back by an interrupt while the queue was
		locked then the mutex holder might now be NULL.  _RB_ Is this still
		needed as interrupts can no longer use mutexes? */
		if( pxMutexHolder != NULL )
 8011eb0:	687b      	ldr	r3, [r7, #4]
 8011eb2:	2b00      	cmp	r3, #0
 8011eb4:	d051      	beq.n	8011f5a <xTaskPriorityInherit+0xba>
		{
			/* If the holder of the mutex has a priority below the priority of
			the task attempting to obtain the mutex then it will temporarily
			inherit the priority of the task attempting to obtain the mutex. */
			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
 8011eb6:	68bb      	ldr	r3, [r7, #8]
 8011eb8:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011eba:	4b2a      	ldr	r3, [pc, #168]	@ (8011f64 <xTaskPriorityInherit+0xc4>)
 8011ebc:	681b      	ldr	r3, [r3, #0]
 8011ebe:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8011ec0:	429a      	cmp	r2, r3
 8011ec2:	d241      	bcs.n	8011f48 <xTaskPriorityInherit+0xa8>
			{
				/* Adjust the mutex holder state to account for its new
				priority.  Only reset the event list item value if the value is
				not being used for anything else. */
				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
 8011ec4:	68bb      	ldr	r3, [r7, #8]
 8011ec6:	699b      	ldr	r3, [r3, #24]
 8011ec8:	2b00      	cmp	r3, #0
 8011eca:	db06      	blt.n	8011eda <xTaskPriorityInherit+0x3a>
				{
					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8011ecc:	4b25      	ldr	r3, [pc, #148]	@ (8011f64 <xTaskPriorityInherit+0xc4>)
 8011ece:	681b      	ldr	r3, [r3, #0]
 8011ed0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8011ed2:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 8011ed6:	68bb      	ldr	r3, [r7, #8]
 8011ed8:	619a      	str	r2, [r3, #24]
					mtCOVERAGE_TEST_MARKER();
				}

				/* If the task being modified is in the ready state it will need
				to be moved into a new list. */
				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
 8011eda:	68bb      	ldr	r3, [r7, #8]
 8011edc:	6959      	ldr	r1, [r3, #20]
 8011ede:	68bb      	ldr	r3, [r7, #8]
 8011ee0:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011ee2:	4613      	mov	r3, r2
 8011ee4:	009b      	lsls	r3, r3, #2
 8011ee6:	4413      	add	r3, r2
 8011ee8:	009b      	lsls	r3, r3, #2
 8011eea:	4a1f      	ldr	r2, [pc, #124]	@ (8011f68 <xTaskPriorityInherit+0xc8>)
 8011eec:	4413      	add	r3, r2
 8011eee:	4299      	cmp	r1, r3
 8011ef0:	d122      	bne.n	8011f38 <xTaskPriorityInherit+0x98>
				{
					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 8011ef2:	68bb      	ldr	r3, [r7, #8]
 8011ef4:	3304      	adds	r3, #4
 8011ef6:	4618      	mov	r0, r3
 8011ef8:	f7fd ff96 	bl	800fe28 <uxListRemove>
					{
						mtCOVERAGE_TEST_MARKER();
					}

					/* Inherit the priority before being moved into the new list. */
					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
 8011efc:	4b19      	ldr	r3, [pc, #100]	@ (8011f64 <xTaskPriorityInherit+0xc4>)
 8011efe:	681b      	ldr	r3, [r3, #0]
 8011f00:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011f02:	68bb      	ldr	r3, [r7, #8]
 8011f04:	62da      	str	r2, [r3, #44]	@ 0x2c
					prvAddTaskToReadyList( pxMutexHolderTCB );
 8011f06:	68bb      	ldr	r3, [r7, #8]
 8011f08:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011f0a:	4b18      	ldr	r3, [pc, #96]	@ (8011f6c <xTaskPriorityInherit+0xcc>)
 8011f0c:	681b      	ldr	r3, [r3, #0]
 8011f0e:	429a      	cmp	r2, r3
 8011f10:	d903      	bls.n	8011f1a <xTaskPriorityInherit+0x7a>
 8011f12:	68bb      	ldr	r3, [r7, #8]
 8011f14:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8011f16:	4a15      	ldr	r2, [pc, #84]	@ (8011f6c <xTaskPriorityInherit+0xcc>)
 8011f18:	6013      	str	r3, [r2, #0]
 8011f1a:	68bb      	ldr	r3, [r7, #8]
 8011f1c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011f1e:	4613      	mov	r3, r2
 8011f20:	009b      	lsls	r3, r3, #2
 8011f22:	4413      	add	r3, r2
 8011f24:	009b      	lsls	r3, r3, #2
 8011f26:	4a10      	ldr	r2, [pc, #64]	@ (8011f68 <xTaskPriorityInherit+0xc8>)
 8011f28:	441a      	add	r2, r3
 8011f2a:	68bb      	ldr	r3, [r7, #8]
 8011f2c:	3304      	adds	r3, #4
 8011f2e:	4619      	mov	r1, r3
 8011f30:	4610      	mov	r0, r2
 8011f32:	f7fd ff1c 	bl	800fd6e <vListInsertEnd>
 8011f36:	e004      	b.n	8011f42 <xTaskPriorityInherit+0xa2>
				}
				else
				{
					/* Just inherit the priority. */
					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
 8011f38:	4b0a      	ldr	r3, [pc, #40]	@ (8011f64 <xTaskPriorityInherit+0xc4>)
 8011f3a:	681b      	ldr	r3, [r3, #0]
 8011f3c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011f3e:	68bb      	ldr	r3, [r7, #8]
 8011f40:	62da      	str	r2, [r3, #44]	@ 0x2c
				}

				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );

				/* Inheritance occurred. */
				xReturn = pdTRUE;
 8011f42:	2301      	movs	r3, #1
 8011f44:	60fb      	str	r3, [r7, #12]
 8011f46:	e008      	b.n	8011f5a <xTaskPriorityInherit+0xba>
			}
			else
			{
				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
 8011f48:	68bb      	ldr	r3, [r7, #8]
 8011f4a:	6cda      	ldr	r2, [r3, #76]	@ 0x4c
 8011f4c:	4b05      	ldr	r3, [pc, #20]	@ (8011f64 <xTaskPriorityInherit+0xc4>)
 8011f4e:	681b      	ldr	r3, [r3, #0]
 8011f50:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8011f52:	429a      	cmp	r2, r3
 8011f54:	d201      	bcs.n	8011f5a <xTaskPriorityInherit+0xba>
					current priority of the mutex holder is not lower than the
					priority of the task attempting to take the mutex.
					Therefore the mutex holder must have already inherited a
					priority, but inheritance would have occurred if that had
					not been the case. */
					xReturn = pdTRUE;
 8011f56:	2301      	movs	r3, #1
 8011f58:	60fb      	str	r3, [r7, #12]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		return xReturn;
 8011f5a:	68fb      	ldr	r3, [r7, #12]
	}
 8011f5c:	4618      	mov	r0, r3
 8011f5e:	3710      	adds	r7, #16
 8011f60:	46bd      	mov	sp, r7
 8011f62:	bd80      	pop	{r7, pc}
 8011f64:	240023f4 	.word	0x240023f4
 8011f68:	240023f8 	.word	0x240023f8
 8011f6c:	240028d0 	.word	0x240028d0

08011f70 <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
	{
 8011f70:	b580      	push	{r7, lr}
 8011f72:	b086      	sub	sp, #24
 8011f74:	af00      	add	r7, sp, #0
 8011f76:	6078      	str	r0, [r7, #4]
	TCB_t * const pxTCB = pxMutexHolder;
 8011f78:	687b      	ldr	r3, [r7, #4]
 8011f7a:	613b      	str	r3, [r7, #16]
	BaseType_t xReturn = pdFALSE;
 8011f7c:	2300      	movs	r3, #0
 8011f7e:	617b      	str	r3, [r7, #20]

		if( pxMutexHolder != NULL )
 8011f80:	687b      	ldr	r3, [r7, #4]
 8011f82:	2b00      	cmp	r3, #0
 8011f84:	d058      	beq.n	8012038 <xTaskPriorityDisinherit+0xc8>
		{
			/* A task can only have an inherited priority if it holds the mutex.
			If the mutex is held by a task then it cannot be given from an
			interrupt, and if a mutex is given by the holding task then it must
			be the running state task. */
			configASSERT( pxTCB == pxCurrentTCB );
 8011f86:	4b2f      	ldr	r3, [pc, #188]	@ (8012044 <xTaskPriorityDisinherit+0xd4>)
 8011f88:	681b      	ldr	r3, [r3, #0]
 8011f8a:	693a      	ldr	r2, [r7, #16]
 8011f8c:	429a      	cmp	r2, r3
 8011f8e:	d00b      	beq.n	8011fa8 <xTaskPriorityDisinherit+0x38>
	__asm volatile
 8011f90:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011f94:	f383 8811 	msr	BASEPRI, r3
 8011f98:	f3bf 8f6f 	isb	sy
 8011f9c:	f3bf 8f4f 	dsb	sy
 8011fa0:	60fb      	str	r3, [r7, #12]
}
 8011fa2:	bf00      	nop
 8011fa4:	bf00      	nop
 8011fa6:	e7fd      	b.n	8011fa4 <xTaskPriorityDisinherit+0x34>
			configASSERT( pxTCB->uxMutexesHeld );
 8011fa8:	693b      	ldr	r3, [r7, #16]
 8011faa:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8011fac:	2b00      	cmp	r3, #0
 8011fae:	d10b      	bne.n	8011fc8 <xTaskPriorityDisinherit+0x58>
	__asm volatile
 8011fb0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8011fb4:	f383 8811 	msr	BASEPRI, r3
 8011fb8:	f3bf 8f6f 	isb	sy
 8011fbc:	f3bf 8f4f 	dsb	sy
 8011fc0:	60bb      	str	r3, [r7, #8]
}
 8011fc2:	bf00      	nop
 8011fc4:	bf00      	nop
 8011fc6:	e7fd      	b.n	8011fc4 <xTaskPriorityDisinherit+0x54>
			( pxTCB->uxMutexesHeld )--;
 8011fc8:	693b      	ldr	r3, [r7, #16]
 8011fca:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8011fcc:	1e5a      	subs	r2, r3, #1
 8011fce:	693b      	ldr	r3, [r7, #16]
 8011fd0:	651a      	str	r2, [r3, #80]	@ 0x50

			/* Has the holder of the mutex inherited the priority of another
			task? */
			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
 8011fd2:	693b      	ldr	r3, [r7, #16]
 8011fd4:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011fd6:	693b      	ldr	r3, [r7, #16]
 8011fd8:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8011fda:	429a      	cmp	r2, r3
 8011fdc:	d02c      	beq.n	8012038 <xTaskPriorityDisinherit+0xc8>
			{
				/* Only disinherit if no other mutexes are held. */
				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
 8011fde:	693b      	ldr	r3, [r7, #16]
 8011fe0:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8011fe2:	2b00      	cmp	r3, #0
 8011fe4:	d128      	bne.n	8012038 <xTaskPriorityDisinherit+0xc8>
					/* A task can only have an inherited priority if it holds
					the mutex.  If the mutex is held by a task then it cannot be
					given from an interrupt, and if a mutex is given by the
					holding task then it must be the running state task.  Remove
					the holding task from the ready/delayed list. */
					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 8011fe6:	693b      	ldr	r3, [r7, #16]
 8011fe8:	3304      	adds	r3, #4
 8011fea:	4618      	mov	r0, r3
 8011fec:	f7fd ff1c 	bl	800fe28 <uxListRemove>
					}

					/* Disinherit the priority before adding the task into the
					new	ready list. */
					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
					pxTCB->uxPriority = pxTCB->uxBasePriority;
 8011ff0:	693b      	ldr	r3, [r7, #16]
 8011ff2:	6cda      	ldr	r2, [r3, #76]	@ 0x4c
 8011ff4:	693b      	ldr	r3, [r7, #16]
 8011ff6:	62da      	str	r2, [r3, #44]	@ 0x2c

					/* Reset the event list item value.  It cannot be in use for
					any other purpose if this task is running, and it must be
					running to give back the mutex. */
					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8011ff8:	693b      	ldr	r3, [r7, #16]
 8011ffa:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8011ffc:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 8012000:	693b      	ldr	r3, [r7, #16]
 8012002:	619a      	str	r2, [r3, #24]
					prvAddTaskToReadyList( pxTCB );
 8012004:	693b      	ldr	r3, [r7, #16]
 8012006:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8012008:	4b0f      	ldr	r3, [pc, #60]	@ (8012048 <xTaskPriorityDisinherit+0xd8>)
 801200a:	681b      	ldr	r3, [r3, #0]
 801200c:	429a      	cmp	r2, r3
 801200e:	d903      	bls.n	8012018 <xTaskPriorityDisinherit+0xa8>
 8012010:	693b      	ldr	r3, [r7, #16]
 8012012:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8012014:	4a0c      	ldr	r2, [pc, #48]	@ (8012048 <xTaskPriorityDisinherit+0xd8>)
 8012016:	6013      	str	r3, [r2, #0]
 8012018:	693b      	ldr	r3, [r7, #16]
 801201a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 801201c:	4613      	mov	r3, r2
 801201e:	009b      	lsls	r3, r3, #2
 8012020:	4413      	add	r3, r2
 8012022:	009b      	lsls	r3, r3, #2
 8012024:	4a09      	ldr	r2, [pc, #36]	@ (801204c <xTaskPriorityDisinherit+0xdc>)
 8012026:	441a      	add	r2, r3
 8012028:	693b      	ldr	r3, [r7, #16]
 801202a:	3304      	adds	r3, #4
 801202c:	4619      	mov	r1, r3
 801202e:	4610      	mov	r0, r2
 8012030:	f7fd fe9d 	bl	800fd6e <vListInsertEnd>
					in an order different to that in which they were taken.
					If a context switch did not occur when the first mutex was
					returned, even if a task was waiting on it, then a context
					switch should occur when the last mutex is returned whether
					a task is waiting on it or not. */
					xReturn = pdTRUE;
 8012034:	2301      	movs	r3, #1
 8012036:	617b      	str	r3, [r7, #20]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		return xReturn;
 8012038:	697b      	ldr	r3, [r7, #20]
	}
 801203a:	4618      	mov	r0, r3
 801203c:	3718      	adds	r7, #24
 801203e:	46bd      	mov	sp, r7
 8012040:	bd80      	pop	{r7, pc}
 8012042:	bf00      	nop
 8012044:	240023f4 	.word	0x240023f4
 8012048:	240028d0 	.word	0x240028d0
 801204c:	240023f8 	.word	0x240023f8

08012050 <vTaskPriorityDisinheritAfterTimeout>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
	{
 8012050:	b580      	push	{r7, lr}
 8012052:	b088      	sub	sp, #32
 8012054:	af00      	add	r7, sp, #0
 8012056:	6078      	str	r0, [r7, #4]
 8012058:	6039      	str	r1, [r7, #0]
	TCB_t * const pxTCB = pxMutexHolder;
 801205a:	687b      	ldr	r3, [r7, #4]
 801205c:	61bb      	str	r3, [r7, #24]
	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
 801205e:	2301      	movs	r3, #1
 8012060:	617b      	str	r3, [r7, #20]

		if( pxMutexHolder != NULL )
 8012062:	687b      	ldr	r3, [r7, #4]
 8012064:	2b00      	cmp	r3, #0
 8012066:	d06c      	beq.n	8012142 <vTaskPriorityDisinheritAfterTimeout+0xf2>
		{
			/* If pxMutexHolder is not NULL then the holder must hold at least
			one mutex. */
			configASSERT( pxTCB->uxMutexesHeld );
 8012068:	69bb      	ldr	r3, [r7, #24]
 801206a:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 801206c:	2b00      	cmp	r3, #0
 801206e:	d10b      	bne.n	8012088 <vTaskPriorityDisinheritAfterTimeout+0x38>
	__asm volatile
 8012070:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012074:	f383 8811 	msr	BASEPRI, r3
 8012078:	f3bf 8f6f 	isb	sy
 801207c:	f3bf 8f4f 	dsb	sy
 8012080:	60fb      	str	r3, [r7, #12]
}
 8012082:	bf00      	nop
 8012084:	bf00      	nop
 8012086:	e7fd      	b.n	8012084 <vTaskPriorityDisinheritAfterTimeout+0x34>

			/* Determine the priority to which the priority of the task that
			holds the mutex should be set.  This will be the greater of the
			holding task's base priority and the priority of the highest
			priority task that is waiting to obtain the mutex. */
			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
 8012088:	69bb      	ldr	r3, [r7, #24]
 801208a:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 801208c:	683a      	ldr	r2, [r7, #0]
 801208e:	429a      	cmp	r2, r3
 8012090:	d902      	bls.n	8012098 <vTaskPriorityDisinheritAfterTimeout+0x48>
			{
				uxPriorityToUse = uxHighestPriorityWaitingTask;
 8012092:	683b      	ldr	r3, [r7, #0]
 8012094:	61fb      	str	r3, [r7, #28]
 8012096:	e002      	b.n	801209e <vTaskPriorityDisinheritAfterTimeout+0x4e>
			}
			else
			{
				uxPriorityToUse = pxTCB->uxBasePriority;
 8012098:	69bb      	ldr	r3, [r7, #24]
 801209a:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 801209c:	61fb      	str	r3, [r7, #28]
			}

			/* Does the priority need to change? */
			if( pxTCB->uxPriority != uxPriorityToUse )
 801209e:	69bb      	ldr	r3, [r7, #24]
 80120a0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80120a2:	69fa      	ldr	r2, [r7, #28]
 80120a4:	429a      	cmp	r2, r3
 80120a6:	d04c      	beq.n	8012142 <vTaskPriorityDisinheritAfterTimeout+0xf2>
			{
				/* Only disinherit if no other mutexes are held.  This is a
				simplification in the priority inheritance implementation.  If
				the task that holds the mutex is also holding other mutexes then
				the other mutexes may have caused the priority inheritance. */
				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
 80120a8:	69bb      	ldr	r3, [r7, #24]
 80120aa:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80120ac:	697a      	ldr	r2, [r7, #20]
 80120ae:	429a      	cmp	r2, r3
 80120b0:	d147      	bne.n	8012142 <vTaskPriorityDisinheritAfterTimeout+0xf2>
				{
					/* If a task has timed out because it already holds the
					mutex it was trying to obtain then it cannot of inherited
					its own priority. */
					configASSERT( pxTCB != pxCurrentTCB );
 80120b2:	4b26      	ldr	r3, [pc, #152]	@ (801214c <vTaskPriorityDisinheritAfterTimeout+0xfc>)
 80120b4:	681b      	ldr	r3, [r3, #0]
 80120b6:	69ba      	ldr	r2, [r7, #24]
 80120b8:	429a      	cmp	r2, r3
 80120ba:	d10b      	bne.n	80120d4 <vTaskPriorityDisinheritAfterTimeout+0x84>
	__asm volatile
 80120bc:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80120c0:	f383 8811 	msr	BASEPRI, r3
 80120c4:	f3bf 8f6f 	isb	sy
 80120c8:	f3bf 8f4f 	dsb	sy
 80120cc:	60bb      	str	r3, [r7, #8]
}
 80120ce:	bf00      	nop
 80120d0:	bf00      	nop
 80120d2:	e7fd      	b.n	80120d0 <vTaskPriorityDisinheritAfterTimeout+0x80>

					/* Disinherit the priority, remembering the previous
					priority to facilitate determining the subject task's
					state. */
					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
					uxPriorityUsedOnEntry = pxTCB->uxPriority;
 80120d4:	69bb      	ldr	r3, [r7, #24]
 80120d6:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80120d8:	613b      	str	r3, [r7, #16]
					pxTCB->uxPriority = uxPriorityToUse;
 80120da:	69bb      	ldr	r3, [r7, #24]
 80120dc:	69fa      	ldr	r2, [r7, #28]
 80120de:	62da      	str	r2, [r3, #44]	@ 0x2c

					/* Only reset the event list item value if the value is not
					being used for anything else. */
					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
 80120e0:	69bb      	ldr	r3, [r7, #24]
 80120e2:	699b      	ldr	r3, [r3, #24]
 80120e4:	2b00      	cmp	r3, #0
 80120e6:	db04      	blt.n	80120f2 <vTaskPriorityDisinheritAfterTimeout+0xa2>
					{
						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80120e8:	69fb      	ldr	r3, [r7, #28]
 80120ea:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 80120ee:	69bb      	ldr	r3, [r7, #24]
 80120f0:	619a      	str	r2, [r3, #24]
					then the task that holds the mutex could be in either the
					Ready, Blocked or Suspended states.  Only remove the task
					from its current state list if it is in the Ready state as
					the task's priority is going to change and there is one
					Ready list per priority. */
					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
 80120f2:	69bb      	ldr	r3, [r7, #24]
 80120f4:	6959      	ldr	r1, [r3, #20]
 80120f6:	693a      	ldr	r2, [r7, #16]
 80120f8:	4613      	mov	r3, r2
 80120fa:	009b      	lsls	r3, r3, #2
 80120fc:	4413      	add	r3, r2
 80120fe:	009b      	lsls	r3, r3, #2
 8012100:	4a13      	ldr	r2, [pc, #76]	@ (8012150 <vTaskPriorityDisinheritAfterTimeout+0x100>)
 8012102:	4413      	add	r3, r2
 8012104:	4299      	cmp	r1, r3
 8012106:	d11c      	bne.n	8012142 <vTaskPriorityDisinheritAfterTimeout+0xf2>
					{
						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 8012108:	69bb      	ldr	r3, [r7, #24]
 801210a:	3304      	adds	r3, #4
 801210c:	4618      	mov	r0, r3
 801210e:	f7fd fe8b 	bl	800fe28 <uxListRemove>
						else
						{
							mtCOVERAGE_TEST_MARKER();
						}

						prvAddTaskToReadyList( pxTCB );
 8012112:	69bb      	ldr	r3, [r7, #24]
 8012114:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8012116:	4b0f      	ldr	r3, [pc, #60]	@ (8012154 <vTaskPriorityDisinheritAfterTimeout+0x104>)
 8012118:	681b      	ldr	r3, [r3, #0]
 801211a:	429a      	cmp	r2, r3
 801211c:	d903      	bls.n	8012126 <vTaskPriorityDisinheritAfterTimeout+0xd6>
 801211e:	69bb      	ldr	r3, [r7, #24]
 8012120:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8012122:	4a0c      	ldr	r2, [pc, #48]	@ (8012154 <vTaskPriorityDisinheritAfterTimeout+0x104>)
 8012124:	6013      	str	r3, [r2, #0]
 8012126:	69bb      	ldr	r3, [r7, #24]
 8012128:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 801212a:	4613      	mov	r3, r2
 801212c:	009b      	lsls	r3, r3, #2
 801212e:	4413      	add	r3, r2
 8012130:	009b      	lsls	r3, r3, #2
 8012132:	4a07      	ldr	r2, [pc, #28]	@ (8012150 <vTaskPriorityDisinheritAfterTimeout+0x100>)
 8012134:	441a      	add	r2, r3
 8012136:	69bb      	ldr	r3, [r7, #24]
 8012138:	3304      	adds	r3, #4
 801213a:	4619      	mov	r1, r3
 801213c:	4610      	mov	r0, r2
 801213e:	f7fd fe16 	bl	800fd6e <vListInsertEnd>
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
 8012142:	bf00      	nop
 8012144:	3720      	adds	r7, #32
 8012146:	46bd      	mov	sp, r7
 8012148:	bd80      	pop	{r7, pc}
 801214a:	bf00      	nop
 801214c:	240023f4 	.word	0x240023f4
 8012150:	240023f8 	.word	0x240023f8
 8012154:	240028d0 	.word	0x240028d0

08012158 <pvTaskIncrementMutexHeldCount>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
	{
 8012158:	b480      	push	{r7}
 801215a:	af00      	add	r7, sp, #0
		/* If xSemaphoreCreateMutex() is called before any tasks have been created
		then pxCurrentTCB will be NULL. */
		if( pxCurrentTCB != NULL )
 801215c:	4b07      	ldr	r3, [pc, #28]	@ (801217c <pvTaskIncrementMutexHeldCount+0x24>)
 801215e:	681b      	ldr	r3, [r3, #0]
 8012160:	2b00      	cmp	r3, #0
 8012162:	d004      	beq.n	801216e <pvTaskIncrementMutexHeldCount+0x16>
		{
			( pxCurrentTCB->uxMutexesHeld )++;
 8012164:	4b05      	ldr	r3, [pc, #20]	@ (801217c <pvTaskIncrementMutexHeldCount+0x24>)
 8012166:	681b      	ldr	r3, [r3, #0]
 8012168:	6d1a      	ldr	r2, [r3, #80]	@ 0x50
 801216a:	3201      	adds	r2, #1
 801216c:	651a      	str	r2, [r3, #80]	@ 0x50
		}

		return pxCurrentTCB;
 801216e:	4b03      	ldr	r3, [pc, #12]	@ (801217c <pvTaskIncrementMutexHeldCount+0x24>)
 8012170:	681b      	ldr	r3, [r3, #0]
	}
 8012172:	4618      	mov	r0, r3
 8012174:	46bd      	mov	sp, r7
 8012176:	f85d 7b04 	ldr.w	r7, [sp], #4
 801217a:	4770      	bx	lr
 801217c:	240023f4 	.word	0x240023f4

08012180 <xTaskNotifyWait>:
/*-----------------------------------------------------------*/

#if( configUSE_TASK_NOTIFICATIONS == 1 )

	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
	{
 8012180:	b580      	push	{r7, lr}
 8012182:	b086      	sub	sp, #24
 8012184:	af00      	add	r7, sp, #0
 8012186:	60f8      	str	r0, [r7, #12]
 8012188:	60b9      	str	r1, [r7, #8]
 801218a:	607a      	str	r2, [r7, #4]
 801218c:	603b      	str	r3, [r7, #0]
	BaseType_t xReturn;

		taskENTER_CRITICAL();
 801218e:	f000 ff03 	bl	8012f98 <vPortEnterCritical>
		{
			/* Only block if a notification is not already pending. */
			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
 8012192:	4b29      	ldr	r3, [pc, #164]	@ (8012238 <xTaskNotifyWait+0xb8>)
 8012194:	681b      	ldr	r3, [r3, #0]
 8012196:	f893 30a4 	ldrb.w	r3, [r3, #164]	@ 0xa4
 801219a:	b2db      	uxtb	r3, r3
 801219c:	2b02      	cmp	r3, #2
 801219e:	d01c      	beq.n	80121da <xTaskNotifyWait+0x5a>
			{
				/* Clear bits in the task's notification value as bits may get
				set	by the notifying task or interrupt.  This can be used to
				clear the value to zero. */
				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
 80121a0:	4b25      	ldr	r3, [pc, #148]	@ (8012238 <xTaskNotifyWait+0xb8>)
 80121a2:	681b      	ldr	r3, [r3, #0]
 80121a4:	f8d3 10a0 	ldr.w	r1, [r3, #160]	@ 0xa0
 80121a8:	68fa      	ldr	r2, [r7, #12]
 80121aa:	43d2      	mvns	r2, r2
 80121ac:	400a      	ands	r2, r1
 80121ae:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0

				/* Mark this task as waiting for a notification. */
				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
 80121b2:	4b21      	ldr	r3, [pc, #132]	@ (8012238 <xTaskNotifyWait+0xb8>)
 80121b4:	681b      	ldr	r3, [r3, #0]
 80121b6:	2201      	movs	r2, #1
 80121b8:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4

				if( xTicksToWait > ( TickType_t ) 0 )
 80121bc:	683b      	ldr	r3, [r7, #0]
 80121be:	2b00      	cmp	r3, #0
 80121c0:	d00b      	beq.n	80121da <xTaskNotifyWait+0x5a>
				{
					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
 80121c2:	2101      	movs	r1, #1
 80121c4:	6838      	ldr	r0, [r7, #0]
 80121c6:	f000 fa09 	bl	80125dc <prvAddCurrentTaskToDelayedList>

					/* All ports are written to allow a yield in a critical
					section (some will yield immediately, others wait until the
					critical section exits) - but it is not something that
					application code should ever do. */
					portYIELD_WITHIN_API();
 80121ca:	4b1c      	ldr	r3, [pc, #112]	@ (801223c <xTaskNotifyWait+0xbc>)
 80121cc:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80121d0:	601a      	str	r2, [r3, #0]
 80121d2:	f3bf 8f4f 	dsb	sy
 80121d6:	f3bf 8f6f 	isb	sy
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
		taskEXIT_CRITICAL();
 80121da:	f000 ff0f 	bl	8012ffc <vPortExitCritical>

		taskENTER_CRITICAL();
 80121de:	f000 fedb 	bl	8012f98 <vPortEnterCritical>
		{
			traceTASK_NOTIFY_WAIT();

			if( pulNotificationValue != NULL )
 80121e2:	687b      	ldr	r3, [r7, #4]
 80121e4:	2b00      	cmp	r3, #0
 80121e6:	d005      	beq.n	80121f4 <xTaskNotifyWait+0x74>
			{
				/* Output the current notification value, which may or may not
				have changed. */
				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
 80121e8:	4b13      	ldr	r3, [pc, #76]	@ (8012238 <xTaskNotifyWait+0xb8>)
 80121ea:	681b      	ldr	r3, [r3, #0]
 80121ec:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
 80121f0:	687b      	ldr	r3, [r7, #4]
 80121f2:	601a      	str	r2, [r3, #0]

			/* If ucNotifyValue is set then either the task never entered the
			blocked state (because a notification was already pending) or the
			task unblocked because of a notification.  Otherwise the task
			unblocked because of a timeout. */
			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
 80121f4:	4b10      	ldr	r3, [pc, #64]	@ (8012238 <xTaskNotifyWait+0xb8>)
 80121f6:	681b      	ldr	r3, [r3, #0]
 80121f8:	f893 30a4 	ldrb.w	r3, [r3, #164]	@ 0xa4
 80121fc:	b2db      	uxtb	r3, r3
 80121fe:	2b02      	cmp	r3, #2
 8012200:	d002      	beq.n	8012208 <xTaskNotifyWait+0x88>
			{
				/* A notification was not received. */
				xReturn = pdFALSE;
 8012202:	2300      	movs	r3, #0
 8012204:	617b      	str	r3, [r7, #20]
 8012206:	e00a      	b.n	801221e <xTaskNotifyWait+0x9e>
			}
			else
			{
				/* A notification was already pending or a notification was
				received while the task was waiting. */
				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
 8012208:	4b0b      	ldr	r3, [pc, #44]	@ (8012238 <xTaskNotifyWait+0xb8>)
 801220a:	681b      	ldr	r3, [r3, #0]
 801220c:	f8d3 10a0 	ldr.w	r1, [r3, #160]	@ 0xa0
 8012210:	68ba      	ldr	r2, [r7, #8]
 8012212:	43d2      	mvns	r2, r2
 8012214:	400a      	ands	r2, r1
 8012216:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
				xReturn = pdTRUE;
 801221a:	2301      	movs	r3, #1
 801221c:	617b      	str	r3, [r7, #20]
			}

			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
 801221e:	4b06      	ldr	r3, [pc, #24]	@ (8012238 <xTaskNotifyWait+0xb8>)
 8012220:	681b      	ldr	r3, [r3, #0]
 8012222:	2200      	movs	r2, #0
 8012224:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4
		}
		taskEXIT_CRITICAL();
 8012228:	f000 fee8 	bl	8012ffc <vPortExitCritical>

		return xReturn;
 801222c:	697b      	ldr	r3, [r7, #20]
	}
 801222e:	4618      	mov	r0, r3
 8012230:	3718      	adds	r7, #24
 8012232:	46bd      	mov	sp, r7
 8012234:	bd80      	pop	{r7, pc}
 8012236:	bf00      	nop
 8012238:	240023f4 	.word	0x240023f4
 801223c:	e000ed04 	.word	0xe000ed04

08012240 <xTaskGenericNotify>:
/*-----------------------------------------------------------*/

#if( configUSE_TASK_NOTIFICATIONS == 1 )

	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
	{
 8012240:	b580      	push	{r7, lr}
 8012242:	b08a      	sub	sp, #40	@ 0x28
 8012244:	af00      	add	r7, sp, #0
 8012246:	60f8      	str	r0, [r7, #12]
 8012248:	60b9      	str	r1, [r7, #8]
 801224a:	603b      	str	r3, [r7, #0]
 801224c:	4613      	mov	r3, r2
 801224e:	71fb      	strb	r3, [r7, #7]
	TCB_t * pxTCB;
	BaseType_t xReturn = pdPASS;
 8012250:	2301      	movs	r3, #1
 8012252:	627b      	str	r3, [r7, #36]	@ 0x24
	uint8_t ucOriginalNotifyState;

		configASSERT( xTaskToNotify );
 8012254:	68fb      	ldr	r3, [r7, #12]
 8012256:	2b00      	cmp	r3, #0
 8012258:	d10b      	bne.n	8012272 <xTaskGenericNotify+0x32>
	__asm volatile
 801225a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801225e:	f383 8811 	msr	BASEPRI, r3
 8012262:	f3bf 8f6f 	isb	sy
 8012266:	f3bf 8f4f 	dsb	sy
 801226a:	61bb      	str	r3, [r7, #24]
}
 801226c:	bf00      	nop
 801226e:	bf00      	nop
 8012270:	e7fd      	b.n	801226e <xTaskGenericNotify+0x2e>
		pxTCB = xTaskToNotify;
 8012272:	68fb      	ldr	r3, [r7, #12]
 8012274:	623b      	str	r3, [r7, #32]

		taskENTER_CRITICAL();
 8012276:	f000 fe8f 	bl	8012f98 <vPortEnterCritical>
		{
			if( pulPreviousNotificationValue != NULL )
 801227a:	683b      	ldr	r3, [r7, #0]
 801227c:	2b00      	cmp	r3, #0
 801227e:	d004      	beq.n	801228a <xTaskGenericNotify+0x4a>
			{
				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
 8012280:	6a3b      	ldr	r3, [r7, #32]
 8012282:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
 8012286:	683b      	ldr	r3, [r7, #0]
 8012288:	601a      	str	r2, [r3, #0]
			}

			ucOriginalNotifyState = pxTCB->ucNotifyState;
 801228a:	6a3b      	ldr	r3, [r7, #32]
 801228c:	f893 30a4 	ldrb.w	r3, [r3, #164]	@ 0xa4
 8012290:	77fb      	strb	r3, [r7, #31]

			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
 8012292:	6a3b      	ldr	r3, [r7, #32]
 8012294:	2202      	movs	r2, #2
 8012296:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4

			switch( eAction )
 801229a:	79fb      	ldrb	r3, [r7, #7]
 801229c:	2b04      	cmp	r3, #4
 801229e:	d82e      	bhi.n	80122fe <xTaskGenericNotify+0xbe>
 80122a0:	a201      	add	r2, pc, #4	@ (adr r2, 80122a8 <xTaskGenericNotify+0x68>)
 80122a2:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80122a6:	bf00      	nop
 80122a8:	08012323 	.word	0x08012323
 80122ac:	080122bd 	.word	0x080122bd
 80122b0:	080122cf 	.word	0x080122cf
 80122b4:	080122df 	.word	0x080122df
 80122b8:	080122e9 	.word	0x080122e9
			{
				case eSetBits	:
					pxTCB->ulNotifiedValue |= ulValue;
 80122bc:	6a3b      	ldr	r3, [r7, #32]
 80122be:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
 80122c2:	68bb      	ldr	r3, [r7, #8]
 80122c4:	431a      	orrs	r2, r3
 80122c6:	6a3b      	ldr	r3, [r7, #32]
 80122c8:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 80122cc:	e02c      	b.n	8012328 <xTaskGenericNotify+0xe8>

				case eIncrement	:
					( pxTCB->ulNotifiedValue )++;
 80122ce:	6a3b      	ldr	r3, [r7, #32]
 80122d0:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 80122d4:	1c5a      	adds	r2, r3, #1
 80122d6:	6a3b      	ldr	r3, [r7, #32]
 80122d8:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 80122dc:	e024      	b.n	8012328 <xTaskGenericNotify+0xe8>

				case eSetValueWithOverwrite	:
					pxTCB->ulNotifiedValue = ulValue;
 80122de:	6a3b      	ldr	r3, [r7, #32]
 80122e0:	68ba      	ldr	r2, [r7, #8]
 80122e2:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 80122e6:	e01f      	b.n	8012328 <xTaskGenericNotify+0xe8>

				case eSetValueWithoutOverwrite :
					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
 80122e8:	7ffb      	ldrb	r3, [r7, #31]
 80122ea:	2b02      	cmp	r3, #2
 80122ec:	d004      	beq.n	80122f8 <xTaskGenericNotify+0xb8>
					{
						pxTCB->ulNotifiedValue = ulValue;
 80122ee:	6a3b      	ldr	r3, [r7, #32]
 80122f0:	68ba      	ldr	r2, [r7, #8]
 80122f2:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					else
					{
						/* The value could not be written to the task. */
						xReturn = pdFAIL;
					}
					break;
 80122f6:	e017      	b.n	8012328 <xTaskGenericNotify+0xe8>
						xReturn = pdFAIL;
 80122f8:	2300      	movs	r3, #0
 80122fa:	627b      	str	r3, [r7, #36]	@ 0x24
					break;
 80122fc:	e014      	b.n	8012328 <xTaskGenericNotify+0xe8>

				default:
					/* Should not get here if all enums are handled.
					Artificially force an assert by testing a value the
					compiler can't assume is const. */
					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
 80122fe:	6a3b      	ldr	r3, [r7, #32]
 8012300:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 8012304:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8012308:	d00d      	beq.n	8012326 <xTaskGenericNotify+0xe6>
	__asm volatile
 801230a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801230e:	f383 8811 	msr	BASEPRI, r3
 8012312:	f3bf 8f6f 	isb	sy
 8012316:	f3bf 8f4f 	dsb	sy
 801231a:	617b      	str	r3, [r7, #20]
}
 801231c:	bf00      	nop
 801231e:	bf00      	nop
 8012320:	e7fd      	b.n	801231e <xTaskGenericNotify+0xde>
					break;
 8012322:	bf00      	nop
 8012324:	e000      	b.n	8012328 <xTaskGenericNotify+0xe8>

					break;
 8012326:	bf00      	nop

			traceTASK_NOTIFY();

			/* If the task is in the blocked state specifically to wait for a
			notification then unblock it now. */
			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
 8012328:	7ffb      	ldrb	r3, [r7, #31]
 801232a:	2b01      	cmp	r3, #1
 801232c:	d13b      	bne.n	80123a6 <xTaskGenericNotify+0x166>
			{
				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 801232e:	6a3b      	ldr	r3, [r7, #32]
 8012330:	3304      	adds	r3, #4
 8012332:	4618      	mov	r0, r3
 8012334:	f7fd fd78 	bl	800fe28 <uxListRemove>
				prvAddTaskToReadyList( pxTCB );
 8012338:	6a3b      	ldr	r3, [r7, #32]
 801233a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 801233c:	4b1d      	ldr	r3, [pc, #116]	@ (80123b4 <xTaskGenericNotify+0x174>)
 801233e:	681b      	ldr	r3, [r3, #0]
 8012340:	429a      	cmp	r2, r3
 8012342:	d903      	bls.n	801234c <xTaskGenericNotify+0x10c>
 8012344:	6a3b      	ldr	r3, [r7, #32]
 8012346:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8012348:	4a1a      	ldr	r2, [pc, #104]	@ (80123b4 <xTaskGenericNotify+0x174>)
 801234a:	6013      	str	r3, [r2, #0]
 801234c:	6a3b      	ldr	r3, [r7, #32]
 801234e:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8012350:	4613      	mov	r3, r2
 8012352:	009b      	lsls	r3, r3, #2
 8012354:	4413      	add	r3, r2
 8012356:	009b      	lsls	r3, r3, #2
 8012358:	4a17      	ldr	r2, [pc, #92]	@ (80123b8 <xTaskGenericNotify+0x178>)
 801235a:	441a      	add	r2, r3
 801235c:	6a3b      	ldr	r3, [r7, #32]
 801235e:	3304      	adds	r3, #4
 8012360:	4619      	mov	r1, r3
 8012362:	4610      	mov	r0, r2
 8012364:	f7fd fd03 	bl	800fd6e <vListInsertEnd>

				/* The task should not have been on an event list. */
				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
 8012368:	6a3b      	ldr	r3, [r7, #32]
 801236a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 801236c:	2b00      	cmp	r3, #0
 801236e:	d00b      	beq.n	8012388 <xTaskGenericNotify+0x148>
	__asm volatile
 8012370:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012374:	f383 8811 	msr	BASEPRI, r3
 8012378:	f3bf 8f6f 	isb	sy
 801237c:	f3bf 8f4f 	dsb	sy
 8012380:	613b      	str	r3, [r7, #16]
}
 8012382:	bf00      	nop
 8012384:	bf00      	nop
 8012386:	e7fd      	b.n	8012384 <xTaskGenericNotify+0x144>
					earliest possible time. */
					prvResetNextTaskUnblockTime();
				}
				#endif

				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
 8012388:	6a3b      	ldr	r3, [r7, #32]
 801238a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 801238c:	4b0b      	ldr	r3, [pc, #44]	@ (80123bc <xTaskGenericNotify+0x17c>)
 801238e:	681b      	ldr	r3, [r3, #0]
 8012390:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8012392:	429a      	cmp	r2, r3
 8012394:	d907      	bls.n	80123a6 <xTaskGenericNotify+0x166>
				{
					/* The notified task has a priority above the currently
					executing task so a yield is required. */
					taskYIELD_IF_USING_PREEMPTION();
 8012396:	4b0a      	ldr	r3, [pc, #40]	@ (80123c0 <xTaskGenericNotify+0x180>)
 8012398:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 801239c:	601a      	str	r2, [r3, #0]
 801239e:	f3bf 8f4f 	dsb	sy
 80123a2:	f3bf 8f6f 	isb	sy
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
		taskEXIT_CRITICAL();
 80123a6:	f000 fe29 	bl	8012ffc <vPortExitCritical>

		return xReturn;
 80123aa:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
	}
 80123ac:	4618      	mov	r0, r3
 80123ae:	3728      	adds	r7, #40	@ 0x28
 80123b0:	46bd      	mov	sp, r7
 80123b2:	bd80      	pop	{r7, pc}
 80123b4:	240028d0 	.word	0x240028d0
 80123b8:	240023f8 	.word	0x240023f8
 80123bc:	240023f4 	.word	0x240023f4
 80123c0:	e000ed04 	.word	0xe000ed04

080123c4 <xTaskGenericNotifyFromISR>:
/*-----------------------------------------------------------*/

#if( configUSE_TASK_NOTIFICATIONS == 1 )

	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
	{
 80123c4:	b580      	push	{r7, lr}
 80123c6:	b08e      	sub	sp, #56	@ 0x38
 80123c8:	af00      	add	r7, sp, #0
 80123ca:	60f8      	str	r0, [r7, #12]
 80123cc:	60b9      	str	r1, [r7, #8]
 80123ce:	603b      	str	r3, [r7, #0]
 80123d0:	4613      	mov	r3, r2
 80123d2:	71fb      	strb	r3, [r7, #7]
	TCB_t * pxTCB;
	uint8_t ucOriginalNotifyState;
	BaseType_t xReturn = pdPASS;
 80123d4:	2301      	movs	r3, #1
 80123d6:	637b      	str	r3, [r7, #52]	@ 0x34
	UBaseType_t uxSavedInterruptStatus;

		configASSERT( xTaskToNotify );
 80123d8:	68fb      	ldr	r3, [r7, #12]
 80123da:	2b00      	cmp	r3, #0
 80123dc:	d10b      	bne.n	80123f6 <xTaskGenericNotifyFromISR+0x32>
	__asm volatile
 80123de:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80123e2:	f383 8811 	msr	BASEPRI, r3
 80123e6:	f3bf 8f6f 	isb	sy
 80123ea:	f3bf 8f4f 	dsb	sy
 80123ee:	627b      	str	r3, [r7, #36]	@ 0x24
}
 80123f0:	bf00      	nop
 80123f2:	bf00      	nop
 80123f4:	e7fd      	b.n	80123f2 <xTaskGenericNotifyFromISR+0x2e>
		below the maximum system call interrupt priority.  FreeRTOS maintains a
		separate interrupt safe API to ensure interrupt entry is as fast and as
		simple as possible.  More information (albeit Cortex-M specific) is
		provided on the following link:
		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 80123f6:	f000 feaf 	bl	8013158 <vPortValidateInterruptPriority>

		pxTCB = xTaskToNotify;
 80123fa:	68fb      	ldr	r3, [r7, #12]
 80123fc:	633b      	str	r3, [r7, #48]	@ 0x30
	__asm volatile
 80123fe:	f3ef 8211 	mrs	r2, BASEPRI
 8012402:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012406:	f383 8811 	msr	BASEPRI, r3
 801240a:	f3bf 8f6f 	isb	sy
 801240e:	f3bf 8f4f 	dsb	sy
 8012412:	623a      	str	r2, [r7, #32]
 8012414:	61fb      	str	r3, [r7, #28]
	return ulOriginalBASEPRI;
 8012416:	6a3b      	ldr	r3, [r7, #32]

		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 8012418:	62fb      	str	r3, [r7, #44]	@ 0x2c
		{
			if( pulPreviousNotificationValue != NULL )
 801241a:	683b      	ldr	r3, [r7, #0]
 801241c:	2b00      	cmp	r3, #0
 801241e:	d004      	beq.n	801242a <xTaskGenericNotifyFromISR+0x66>
			{
				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
 8012420:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012422:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
 8012426:	683b      	ldr	r3, [r7, #0]
 8012428:	601a      	str	r2, [r3, #0]
			}

			ucOriginalNotifyState = pxTCB->ucNotifyState;
 801242a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801242c:	f893 30a4 	ldrb.w	r3, [r3, #164]	@ 0xa4
 8012430:	f887 302b 	strb.w	r3, [r7, #43]	@ 0x2b
			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
 8012434:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012436:	2202      	movs	r2, #2
 8012438:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4

			switch( eAction )
 801243c:	79fb      	ldrb	r3, [r7, #7]
 801243e:	2b04      	cmp	r3, #4
 8012440:	d82e      	bhi.n	80124a0 <xTaskGenericNotifyFromISR+0xdc>
 8012442:	a201      	add	r2, pc, #4	@ (adr r2, 8012448 <xTaskGenericNotifyFromISR+0x84>)
 8012444:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8012448:	080124c5 	.word	0x080124c5
 801244c:	0801245d 	.word	0x0801245d
 8012450:	0801246f 	.word	0x0801246f
 8012454:	0801247f 	.word	0x0801247f
 8012458:	08012489 	.word	0x08012489
			{
				case eSetBits	:
					pxTCB->ulNotifiedValue |= ulValue;
 801245c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801245e:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
 8012462:	68bb      	ldr	r3, [r7, #8]
 8012464:	431a      	orrs	r2, r3
 8012466:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012468:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 801246c:	e02d      	b.n	80124ca <xTaskGenericNotifyFromISR+0x106>

				case eIncrement	:
					( pxTCB->ulNotifiedValue )++;
 801246e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012470:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 8012474:	1c5a      	adds	r2, r3, #1
 8012476:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012478:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 801247c:	e025      	b.n	80124ca <xTaskGenericNotifyFromISR+0x106>

				case eSetValueWithOverwrite	:
					pxTCB->ulNotifiedValue = ulValue;
 801247e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012480:	68ba      	ldr	r2, [r7, #8]
 8012482:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 8012486:	e020      	b.n	80124ca <xTaskGenericNotifyFromISR+0x106>

				case eSetValueWithoutOverwrite :
					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
 8012488:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
 801248c:	2b02      	cmp	r3, #2
 801248e:	d004      	beq.n	801249a <xTaskGenericNotifyFromISR+0xd6>
					{
						pxTCB->ulNotifiedValue = ulValue;
 8012490:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012492:	68ba      	ldr	r2, [r7, #8]
 8012494:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					else
					{
						/* The value could not be written to the task. */
						xReturn = pdFAIL;
					}
					break;
 8012498:	e017      	b.n	80124ca <xTaskGenericNotifyFromISR+0x106>
						xReturn = pdFAIL;
 801249a:	2300      	movs	r3, #0
 801249c:	637b      	str	r3, [r7, #52]	@ 0x34
					break;
 801249e:	e014      	b.n	80124ca <xTaskGenericNotifyFromISR+0x106>

				default:
					/* Should not get here if all enums are handled.
					Artificially force an assert by testing a value the
					compiler can't assume is const. */
					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
 80124a0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80124a2:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 80124a6:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80124aa:	d00d      	beq.n	80124c8 <xTaskGenericNotifyFromISR+0x104>
	__asm volatile
 80124ac:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80124b0:	f383 8811 	msr	BASEPRI, r3
 80124b4:	f3bf 8f6f 	isb	sy
 80124b8:	f3bf 8f4f 	dsb	sy
 80124bc:	61bb      	str	r3, [r7, #24]
}
 80124be:	bf00      	nop
 80124c0:	bf00      	nop
 80124c2:	e7fd      	b.n	80124c0 <xTaskGenericNotifyFromISR+0xfc>
					break;
 80124c4:	bf00      	nop
 80124c6:	e000      	b.n	80124ca <xTaskGenericNotifyFromISR+0x106>
					break;
 80124c8:	bf00      	nop

			traceTASK_NOTIFY_FROM_ISR();

			/* If the task is in the blocked state specifically to wait for a
			notification then unblock it now. */
			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
 80124ca:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
 80124ce:	2b01      	cmp	r3, #1
 80124d0:	d147      	bne.n	8012562 <xTaskGenericNotifyFromISR+0x19e>
			{
				/* The task should not have been on an event list. */
				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
 80124d2:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80124d4:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 80124d6:	2b00      	cmp	r3, #0
 80124d8:	d00b      	beq.n	80124f2 <xTaskGenericNotifyFromISR+0x12e>
	__asm volatile
 80124da:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80124de:	f383 8811 	msr	BASEPRI, r3
 80124e2:	f3bf 8f6f 	isb	sy
 80124e6:	f3bf 8f4f 	dsb	sy
 80124ea:	617b      	str	r3, [r7, #20]
}
 80124ec:	bf00      	nop
 80124ee:	bf00      	nop
 80124f0:	e7fd      	b.n	80124ee <xTaskGenericNotifyFromISR+0x12a>

				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 80124f2:	4b21      	ldr	r3, [pc, #132]	@ (8012578 <xTaskGenericNotifyFromISR+0x1b4>)
 80124f4:	681b      	ldr	r3, [r3, #0]
 80124f6:	2b00      	cmp	r3, #0
 80124f8:	d11d      	bne.n	8012536 <xTaskGenericNotifyFromISR+0x172>
				{
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 80124fa:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80124fc:	3304      	adds	r3, #4
 80124fe:	4618      	mov	r0, r3
 8012500:	f7fd fc92 	bl	800fe28 <uxListRemove>
					prvAddTaskToReadyList( pxTCB );
 8012504:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012506:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8012508:	4b1c      	ldr	r3, [pc, #112]	@ (801257c <xTaskGenericNotifyFromISR+0x1b8>)
 801250a:	681b      	ldr	r3, [r3, #0]
 801250c:	429a      	cmp	r2, r3
 801250e:	d903      	bls.n	8012518 <xTaskGenericNotifyFromISR+0x154>
 8012510:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012512:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8012514:	4a19      	ldr	r2, [pc, #100]	@ (801257c <xTaskGenericNotifyFromISR+0x1b8>)
 8012516:	6013      	str	r3, [r2, #0]
 8012518:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801251a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 801251c:	4613      	mov	r3, r2
 801251e:	009b      	lsls	r3, r3, #2
 8012520:	4413      	add	r3, r2
 8012522:	009b      	lsls	r3, r3, #2
 8012524:	4a16      	ldr	r2, [pc, #88]	@ (8012580 <xTaskGenericNotifyFromISR+0x1bc>)
 8012526:	441a      	add	r2, r3
 8012528:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801252a:	3304      	adds	r3, #4
 801252c:	4619      	mov	r1, r3
 801252e:	4610      	mov	r0, r2
 8012530:	f7fd fc1d 	bl	800fd6e <vListInsertEnd>
 8012534:	e005      	b.n	8012542 <xTaskGenericNotifyFromISR+0x17e>
				}
				else
				{
					/* The delayed and ready lists cannot be accessed, so hold
					this task pending until the scheduler is resumed. */
					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
 8012536:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012538:	3318      	adds	r3, #24
 801253a:	4619      	mov	r1, r3
 801253c:	4811      	ldr	r0, [pc, #68]	@ (8012584 <xTaskGenericNotifyFromISR+0x1c0>)
 801253e:	f7fd fc16 	bl	800fd6e <vListInsertEnd>
				}

				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
 8012542:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012544:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8012546:	4b10      	ldr	r3, [pc, #64]	@ (8012588 <xTaskGenericNotifyFromISR+0x1c4>)
 8012548:	681b      	ldr	r3, [r3, #0]
 801254a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 801254c:	429a      	cmp	r2, r3
 801254e:	d908      	bls.n	8012562 <xTaskGenericNotifyFromISR+0x19e>
				{
					/* The notified task has a priority above the currently
					executing task so a yield is required. */
					if( pxHigherPriorityTaskWoken != NULL )
 8012550:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 8012552:	2b00      	cmp	r3, #0
 8012554:	d002      	beq.n	801255c <xTaskGenericNotifyFromISR+0x198>
					{
						*pxHigherPriorityTaskWoken = pdTRUE;
 8012556:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 8012558:	2201      	movs	r2, #1
 801255a:	601a      	str	r2, [r3, #0]
					}

					/* Mark that a yield is pending in case the user is not
					using the "xHigherPriorityTaskWoken" parameter to an ISR
					safe FreeRTOS function. */
					xYieldPending = pdTRUE;
 801255c:	4b0b      	ldr	r3, [pc, #44]	@ (801258c <xTaskGenericNotifyFromISR+0x1c8>)
 801255e:	2201      	movs	r2, #1
 8012560:	601a      	str	r2, [r3, #0]
 8012562:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8012564:	613b      	str	r3, [r7, #16]
	__asm volatile
 8012566:	693b      	ldr	r3, [r7, #16]
 8012568:	f383 8811 	msr	BASEPRI, r3
}
 801256c:	bf00      	nop
				}
			}
		}
		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

		return xReturn;
 801256e:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
	}
 8012570:	4618      	mov	r0, r3
 8012572:	3738      	adds	r7, #56	@ 0x38
 8012574:	46bd      	mov	sp, r7
 8012576:	bd80      	pop	{r7, pc}
 8012578:	240028f0 	.word	0x240028f0
 801257c:	240028d0 	.word	0x240028d0
 8012580:	240023f8 	.word	0x240023f8
 8012584:	24002888 	.word	0x24002888
 8012588:	240023f4 	.word	0x240023f4
 801258c:	240028dc 	.word	0x240028dc

08012590 <xTaskNotifyStateClear>:
/*-----------------------------------------------------------*/

#if( configUSE_TASK_NOTIFICATIONS == 1 )

	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
	{
 8012590:	b580      	push	{r7, lr}
 8012592:	b084      	sub	sp, #16
 8012594:	af00      	add	r7, sp, #0
 8012596:	6078      	str	r0, [r7, #4]
	TCB_t *pxTCB;
	BaseType_t xReturn;

		/* If null is passed in here then it is the calling task that is having
		its notification state cleared. */
		pxTCB = prvGetTCBFromHandle( xTask );
 8012598:	687b      	ldr	r3, [r7, #4]
 801259a:	2b00      	cmp	r3, #0
 801259c:	d102      	bne.n	80125a4 <xTaskNotifyStateClear+0x14>
 801259e:	4b0e      	ldr	r3, [pc, #56]	@ (80125d8 <xTaskNotifyStateClear+0x48>)
 80125a0:	681b      	ldr	r3, [r3, #0]
 80125a2:	e000      	b.n	80125a6 <xTaskNotifyStateClear+0x16>
 80125a4:	687b      	ldr	r3, [r7, #4]
 80125a6:	60bb      	str	r3, [r7, #8]

		taskENTER_CRITICAL();
 80125a8:	f000 fcf6 	bl	8012f98 <vPortEnterCritical>
		{
			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
 80125ac:	68bb      	ldr	r3, [r7, #8]
 80125ae:	f893 30a4 	ldrb.w	r3, [r3, #164]	@ 0xa4
 80125b2:	b2db      	uxtb	r3, r3
 80125b4:	2b02      	cmp	r3, #2
 80125b6:	d106      	bne.n	80125c6 <xTaskNotifyStateClear+0x36>
			{
				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
 80125b8:	68bb      	ldr	r3, [r7, #8]
 80125ba:	2200      	movs	r2, #0
 80125bc:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4
				xReturn = pdPASS;
 80125c0:	2301      	movs	r3, #1
 80125c2:	60fb      	str	r3, [r7, #12]
 80125c4:	e001      	b.n	80125ca <xTaskNotifyStateClear+0x3a>
			}
			else
			{
				xReturn = pdFAIL;
 80125c6:	2300      	movs	r3, #0
 80125c8:	60fb      	str	r3, [r7, #12]
			}
		}
		taskEXIT_CRITICAL();
 80125ca:	f000 fd17 	bl	8012ffc <vPortExitCritical>

		return xReturn;
 80125ce:	68fb      	ldr	r3, [r7, #12]
	}
 80125d0:	4618      	mov	r0, r3
 80125d2:	3710      	adds	r7, #16
 80125d4:	46bd      	mov	sp, r7
 80125d6:	bd80      	pop	{r7, pc}
 80125d8:	240023f4 	.word	0x240023f4

080125dc <prvAddCurrentTaskToDelayedList>:

#endif
/*-----------------------------------------------------------*/

static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
 80125dc:	b580      	push	{r7, lr}
 80125de:	b084      	sub	sp, #16
 80125e0:	af00      	add	r7, sp, #0
 80125e2:	6078      	str	r0, [r7, #4]
 80125e4:	6039      	str	r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
 80125e6:	4b21      	ldr	r3, [pc, #132]	@ (801266c <prvAddCurrentTaskToDelayedList+0x90>)
 80125e8:	681b      	ldr	r3, [r3, #0]
 80125ea:	60fb      	str	r3, [r7, #12]
	}
	#endif

	/* Remove the task from the ready list before adding it to the blocked list
	as the same list item is used for both lists. */
	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 80125ec:	4b20      	ldr	r3, [pc, #128]	@ (8012670 <prvAddCurrentTaskToDelayedList+0x94>)
 80125ee:	681b      	ldr	r3, [r3, #0]
 80125f0:	3304      	adds	r3, #4
 80125f2:	4618      	mov	r0, r3
 80125f4:	f7fd fc18 	bl	800fe28 <uxListRemove>
		mtCOVERAGE_TEST_MARKER();
	}

	#if ( INCLUDE_vTaskSuspend == 1 )
	{
		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
 80125f8:	687b      	ldr	r3, [r7, #4]
 80125fa:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80125fe:	d10a      	bne.n	8012616 <prvAddCurrentTaskToDelayedList+0x3a>
 8012600:	683b      	ldr	r3, [r7, #0]
 8012602:	2b00      	cmp	r3, #0
 8012604:	d007      	beq.n	8012616 <prvAddCurrentTaskToDelayedList+0x3a>
		{
			/* Add the task to the suspended task list instead of a delayed task
			list to ensure it is not woken by a timing event.  It will block
			indefinitely. */
			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
 8012606:	4b1a      	ldr	r3, [pc, #104]	@ (8012670 <prvAddCurrentTaskToDelayedList+0x94>)
 8012608:	681b      	ldr	r3, [r3, #0]
 801260a:	3304      	adds	r3, #4
 801260c:	4619      	mov	r1, r3
 801260e:	4819      	ldr	r0, [pc, #100]	@ (8012674 <prvAddCurrentTaskToDelayedList+0x98>)
 8012610:	f7fd fbad 	bl	800fd6e <vListInsertEnd>

		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
		( void ) xCanBlockIndefinitely;
	}
	#endif /* INCLUDE_vTaskSuspend */
}
 8012614:	e026      	b.n	8012664 <prvAddCurrentTaskToDelayedList+0x88>
			xTimeToWake = xConstTickCount + xTicksToWait;
 8012616:	68fa      	ldr	r2, [r7, #12]
 8012618:	687b      	ldr	r3, [r7, #4]
 801261a:	4413      	add	r3, r2
 801261c:	60bb      	str	r3, [r7, #8]
			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
 801261e:	4b14      	ldr	r3, [pc, #80]	@ (8012670 <prvAddCurrentTaskToDelayedList+0x94>)
 8012620:	681b      	ldr	r3, [r3, #0]
 8012622:	68ba      	ldr	r2, [r7, #8]
 8012624:	605a      	str	r2, [r3, #4]
			if( xTimeToWake < xConstTickCount )
 8012626:	68ba      	ldr	r2, [r7, #8]
 8012628:	68fb      	ldr	r3, [r7, #12]
 801262a:	429a      	cmp	r2, r3
 801262c:	d209      	bcs.n	8012642 <prvAddCurrentTaskToDelayedList+0x66>
				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 801262e:	4b12      	ldr	r3, [pc, #72]	@ (8012678 <prvAddCurrentTaskToDelayedList+0x9c>)
 8012630:	681a      	ldr	r2, [r3, #0]
 8012632:	4b0f      	ldr	r3, [pc, #60]	@ (8012670 <prvAddCurrentTaskToDelayedList+0x94>)
 8012634:	681b      	ldr	r3, [r3, #0]
 8012636:	3304      	adds	r3, #4
 8012638:	4619      	mov	r1, r3
 801263a:	4610      	mov	r0, r2
 801263c:	f7fd fbbb 	bl	800fdb6 <vListInsert>
}
 8012640:	e010      	b.n	8012664 <prvAddCurrentTaskToDelayedList+0x88>
				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 8012642:	4b0e      	ldr	r3, [pc, #56]	@ (801267c <prvAddCurrentTaskToDelayedList+0xa0>)
 8012644:	681a      	ldr	r2, [r3, #0]
 8012646:	4b0a      	ldr	r3, [pc, #40]	@ (8012670 <prvAddCurrentTaskToDelayedList+0x94>)
 8012648:	681b      	ldr	r3, [r3, #0]
 801264a:	3304      	adds	r3, #4
 801264c:	4619      	mov	r1, r3
 801264e:	4610      	mov	r0, r2
 8012650:	f7fd fbb1 	bl	800fdb6 <vListInsert>
				if( xTimeToWake < xNextTaskUnblockTime )
 8012654:	4b0a      	ldr	r3, [pc, #40]	@ (8012680 <prvAddCurrentTaskToDelayedList+0xa4>)
 8012656:	681b      	ldr	r3, [r3, #0]
 8012658:	68ba      	ldr	r2, [r7, #8]
 801265a:	429a      	cmp	r2, r3
 801265c:	d202      	bcs.n	8012664 <prvAddCurrentTaskToDelayedList+0x88>
					xNextTaskUnblockTime = xTimeToWake;
 801265e:	4a08      	ldr	r2, [pc, #32]	@ (8012680 <prvAddCurrentTaskToDelayedList+0xa4>)
 8012660:	68bb      	ldr	r3, [r7, #8]
 8012662:	6013      	str	r3, [r2, #0]
}
 8012664:	bf00      	nop
 8012666:	3710      	adds	r7, #16
 8012668:	46bd      	mov	sp, r7
 801266a:	bd80      	pop	{r7, pc}
 801266c:	240028cc 	.word	0x240028cc
 8012670:	240023f4 	.word	0x240023f4
 8012674:	240028b4 	.word	0x240028b4
 8012678:	24002884 	.word	0x24002884
 801267c:	24002880 	.word	0x24002880
 8012680:	240028e8 	.word	0x240028e8

08012684 <xTimerCreateTimerTask>:
									TimerCallbackFunction_t pxCallbackFunction,
									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/

BaseType_t xTimerCreateTimerTask( void )
{
 8012684:	b580      	push	{r7, lr}
 8012686:	b08a      	sub	sp, #40	@ 0x28
 8012688:	af04      	add	r7, sp, #16
BaseType_t xReturn = pdFAIL;
 801268a:	2300      	movs	r3, #0
 801268c:	617b      	str	r3, [r7, #20]

	/* This function is called when the scheduler is started if
	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
	timer service task has been created/initialised.  If timers have already
	been created then the initialisation will already have been performed. */
	prvCheckForValidListAndQueue();
 801268e:	f000 fb13 	bl	8012cb8 <prvCheckForValidListAndQueue>

	if( xTimerQueue != NULL )
 8012692:	4b1d      	ldr	r3, [pc, #116]	@ (8012708 <xTimerCreateTimerTask+0x84>)
 8012694:	681b      	ldr	r3, [r3, #0]
 8012696:	2b00      	cmp	r3, #0
 8012698:	d021      	beq.n	80126de <xTimerCreateTimerTask+0x5a>
	{
		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
		{
			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
 801269a:	2300      	movs	r3, #0
 801269c:	60fb      	str	r3, [r7, #12]
			StackType_t *pxTimerTaskStackBuffer = NULL;
 801269e:	2300      	movs	r3, #0
 80126a0:	60bb      	str	r3, [r7, #8]
			uint32_t ulTimerTaskStackSize;

			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
 80126a2:	1d3a      	adds	r2, r7, #4
 80126a4:	f107 0108 	add.w	r1, r7, #8
 80126a8:	f107 030c 	add.w	r3, r7, #12
 80126ac:	4618      	mov	r0, r3
 80126ae:	f7fd fb17 	bl	800fce0 <vApplicationGetTimerTaskMemory>
			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
 80126b2:	6879      	ldr	r1, [r7, #4]
 80126b4:	68bb      	ldr	r3, [r7, #8]
 80126b6:	68fa      	ldr	r2, [r7, #12]
 80126b8:	9202      	str	r2, [sp, #8]
 80126ba:	9301      	str	r3, [sp, #4]
 80126bc:	2302      	movs	r3, #2
 80126be:	9300      	str	r3, [sp, #0]
 80126c0:	2300      	movs	r3, #0
 80126c2:	460a      	mov	r2, r1
 80126c4:	4911      	ldr	r1, [pc, #68]	@ (801270c <xTimerCreateTimerTask+0x88>)
 80126c6:	4812      	ldr	r0, [pc, #72]	@ (8012710 <xTimerCreateTimerTask+0x8c>)
 80126c8:	f7fe fd2f 	bl	801112a <xTaskCreateStatic>
 80126cc:	4603      	mov	r3, r0
 80126ce:	4a11      	ldr	r2, [pc, #68]	@ (8012714 <xTimerCreateTimerTask+0x90>)
 80126d0:	6013      	str	r3, [r2, #0]
													NULL,
													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
													pxTimerTaskStackBuffer,
													pxTimerTaskTCBBuffer );

			if( xTimerTaskHandle != NULL )
 80126d2:	4b10      	ldr	r3, [pc, #64]	@ (8012714 <xTimerCreateTimerTask+0x90>)
 80126d4:	681b      	ldr	r3, [r3, #0]
 80126d6:	2b00      	cmp	r3, #0
 80126d8:	d001      	beq.n	80126de <xTimerCreateTimerTask+0x5a>
			{
				xReturn = pdPASS;
 80126da:	2301      	movs	r3, #1
 80126dc:	617b      	str	r3, [r7, #20]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	configASSERT( xReturn );
 80126de:	697b      	ldr	r3, [r7, #20]
 80126e0:	2b00      	cmp	r3, #0
 80126e2:	d10b      	bne.n	80126fc <xTimerCreateTimerTask+0x78>
	__asm volatile
 80126e4:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80126e8:	f383 8811 	msr	BASEPRI, r3
 80126ec:	f3bf 8f6f 	isb	sy
 80126f0:	f3bf 8f4f 	dsb	sy
 80126f4:	613b      	str	r3, [r7, #16]
}
 80126f6:	bf00      	nop
 80126f8:	bf00      	nop
 80126fa:	e7fd      	b.n	80126f8 <xTimerCreateTimerTask+0x74>
	return xReturn;
 80126fc:	697b      	ldr	r3, [r7, #20]
}
 80126fe:	4618      	mov	r0, r3
 8012700:	3718      	adds	r7, #24
 8012702:	46bd      	mov	sp, r7
 8012704:	bd80      	pop	{r7, pc}
 8012706:	bf00      	nop
 8012708:	24002924 	.word	0x24002924
 801270c:	080145b0 	.word	0x080145b0
 8012710:	08012851 	.word	0x08012851
 8012714:	24002928 	.word	0x24002928

08012718 <xTimerGenericCommand>:
	}
}
/*-----------------------------------------------------------*/

BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
{
 8012718:	b580      	push	{r7, lr}
 801271a:	b08a      	sub	sp, #40	@ 0x28
 801271c:	af00      	add	r7, sp, #0
 801271e:	60f8      	str	r0, [r7, #12]
 8012720:	60b9      	str	r1, [r7, #8]
 8012722:	607a      	str	r2, [r7, #4]
 8012724:	603b      	str	r3, [r7, #0]
BaseType_t xReturn = pdFAIL;
 8012726:	2300      	movs	r3, #0
 8012728:	627b      	str	r3, [r7, #36]	@ 0x24
DaemonTaskMessage_t xMessage;

	configASSERT( xTimer );
 801272a:	68fb      	ldr	r3, [r7, #12]
 801272c:	2b00      	cmp	r3, #0
 801272e:	d10b      	bne.n	8012748 <xTimerGenericCommand+0x30>
	__asm volatile
 8012730:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012734:	f383 8811 	msr	BASEPRI, r3
 8012738:	f3bf 8f6f 	isb	sy
 801273c:	f3bf 8f4f 	dsb	sy
 8012740:	623b      	str	r3, [r7, #32]
}
 8012742:	bf00      	nop
 8012744:	bf00      	nop
 8012746:	e7fd      	b.n	8012744 <xTimerGenericCommand+0x2c>

	/* Send a message to the timer service task to perform a particular action
	on a particular timer definition. */
	if( xTimerQueue != NULL )
 8012748:	4b19      	ldr	r3, [pc, #100]	@ (80127b0 <xTimerGenericCommand+0x98>)
 801274a:	681b      	ldr	r3, [r3, #0]
 801274c:	2b00      	cmp	r3, #0
 801274e:	d02a      	beq.n	80127a6 <xTimerGenericCommand+0x8e>
	{
		/* Send a command to the timer service task to start the xTimer timer. */
		xMessage.xMessageID = xCommandID;
 8012750:	68bb      	ldr	r3, [r7, #8]
 8012752:	613b      	str	r3, [r7, #16]
		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
 8012754:	687b      	ldr	r3, [r7, #4]
 8012756:	617b      	str	r3, [r7, #20]
		xMessage.u.xTimerParameters.pxTimer = xTimer;
 8012758:	68fb      	ldr	r3, [r7, #12]
 801275a:	61bb      	str	r3, [r7, #24]

		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
 801275c:	68bb      	ldr	r3, [r7, #8]
 801275e:	2b05      	cmp	r3, #5
 8012760:	dc18      	bgt.n	8012794 <xTimerGenericCommand+0x7c>
		{
			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
 8012762:	f7ff fb7f 	bl	8011e64 <xTaskGetSchedulerState>
 8012766:	4603      	mov	r3, r0
 8012768:	2b02      	cmp	r3, #2
 801276a:	d109      	bne.n	8012780 <xTimerGenericCommand+0x68>
			{
				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
 801276c:	4b10      	ldr	r3, [pc, #64]	@ (80127b0 <xTimerGenericCommand+0x98>)
 801276e:	6818      	ldr	r0, [r3, #0]
 8012770:	f107 0110 	add.w	r1, r7, #16
 8012774:	2300      	movs	r3, #0
 8012776:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8012778:	f7fd fd7e 	bl	8010278 <xQueueGenericSend>
 801277c:	6278      	str	r0, [r7, #36]	@ 0x24
 801277e:	e012      	b.n	80127a6 <xTimerGenericCommand+0x8e>
			}
			else
			{
				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
 8012780:	4b0b      	ldr	r3, [pc, #44]	@ (80127b0 <xTimerGenericCommand+0x98>)
 8012782:	6818      	ldr	r0, [r3, #0]
 8012784:	f107 0110 	add.w	r1, r7, #16
 8012788:	2300      	movs	r3, #0
 801278a:	2200      	movs	r2, #0
 801278c:	f7fd fd74 	bl	8010278 <xQueueGenericSend>
 8012790:	6278      	str	r0, [r7, #36]	@ 0x24
 8012792:	e008      	b.n	80127a6 <xTimerGenericCommand+0x8e>
			}
		}
		else
		{
			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
 8012794:	4b06      	ldr	r3, [pc, #24]	@ (80127b0 <xTimerGenericCommand+0x98>)
 8012796:	6818      	ldr	r0, [r3, #0]
 8012798:	f107 0110 	add.w	r1, r7, #16
 801279c:	2300      	movs	r3, #0
 801279e:	683a      	ldr	r2, [r7, #0]
 80127a0:	f7fd fe6c 	bl	801047c <xQueueGenericSendFromISR>
 80127a4:	6278      	str	r0, [r7, #36]	@ 0x24
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	return xReturn;
 80127a6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
}
 80127a8:	4618      	mov	r0, r3
 80127aa:	3728      	adds	r7, #40	@ 0x28
 80127ac:	46bd      	mov	sp, r7
 80127ae:	bd80      	pop	{r7, pc}
 80127b0:	24002924 	.word	0x24002924

080127b4 <prvProcessExpiredTimer>:
	return pxTimer->pcTimerName;
}
/*-----------------------------------------------------------*/

static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
{
 80127b4:	b580      	push	{r7, lr}
 80127b6:	b088      	sub	sp, #32
 80127b8:	af02      	add	r7, sp, #8
 80127ba:	6078      	str	r0, [r7, #4]
 80127bc:	6039      	str	r1, [r7, #0]
BaseType_t xResult;
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80127be:	4b23      	ldr	r3, [pc, #140]	@ (801284c <prvProcessExpiredTimer+0x98>)
 80127c0:	681b      	ldr	r3, [r3, #0]
 80127c2:	68db      	ldr	r3, [r3, #12]
 80127c4:	68db      	ldr	r3, [r3, #12]
 80127c6:	617b      	str	r3, [r7, #20]

	/* Remove the timer from the list of active timers.  A check has already
	been performed to ensure the list is not empty. */
	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 80127c8:	697b      	ldr	r3, [r7, #20]
 80127ca:	3304      	adds	r3, #4
 80127cc:	4618      	mov	r0, r3
 80127ce:	f7fd fb2b 	bl	800fe28 <uxListRemove>
	traceTIMER_EXPIRED( pxTimer );

	/* If the timer is an auto-reload timer then calculate the next
	expiry time and re-insert the timer in the list of active timers. */
	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 80127d2:	697b      	ldr	r3, [r7, #20]
 80127d4:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 80127d8:	f003 0304 	and.w	r3, r3, #4
 80127dc:	2b00      	cmp	r3, #0
 80127de:	d023      	beq.n	8012828 <prvProcessExpiredTimer+0x74>
	{
		/* The timer is inserted into a list using a time relative to anything
		other than the current time.  It will therefore be inserted into the
		correct list relative to the time this task thinks it is now. */
		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
 80127e0:	697b      	ldr	r3, [r7, #20]
 80127e2:	699a      	ldr	r2, [r3, #24]
 80127e4:	687b      	ldr	r3, [r7, #4]
 80127e6:	18d1      	adds	r1, r2, r3
 80127e8:	687b      	ldr	r3, [r7, #4]
 80127ea:	683a      	ldr	r2, [r7, #0]
 80127ec:	6978      	ldr	r0, [r7, #20]
 80127ee:	f000 f8d5 	bl	801299c <prvInsertTimerInActiveList>
 80127f2:	4603      	mov	r3, r0
 80127f4:	2b00      	cmp	r3, #0
 80127f6:	d020      	beq.n	801283a <prvProcessExpiredTimer+0x86>
		{
			/* The timer expired before it was added to the active timer
			list.  Reload it now.  */
			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
 80127f8:	2300      	movs	r3, #0
 80127fa:	9300      	str	r3, [sp, #0]
 80127fc:	2300      	movs	r3, #0
 80127fe:	687a      	ldr	r2, [r7, #4]
 8012800:	2100      	movs	r1, #0
 8012802:	6978      	ldr	r0, [r7, #20]
 8012804:	f7ff ff88 	bl	8012718 <xTimerGenericCommand>
 8012808:	6138      	str	r0, [r7, #16]
			configASSERT( xResult );
 801280a:	693b      	ldr	r3, [r7, #16]
 801280c:	2b00      	cmp	r3, #0
 801280e:	d114      	bne.n	801283a <prvProcessExpiredTimer+0x86>
	__asm volatile
 8012810:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012814:	f383 8811 	msr	BASEPRI, r3
 8012818:	f3bf 8f6f 	isb	sy
 801281c:	f3bf 8f4f 	dsb	sy
 8012820:	60fb      	str	r3, [r7, #12]
}
 8012822:	bf00      	nop
 8012824:	bf00      	nop
 8012826:	e7fd      	b.n	8012824 <prvProcessExpiredTimer+0x70>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	else
	{
		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8012828:	697b      	ldr	r3, [r7, #20]
 801282a:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 801282e:	f023 0301 	bic.w	r3, r3, #1
 8012832:	b2da      	uxtb	r2, r3
 8012834:	697b      	ldr	r3, [r7, #20]
 8012836:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
		mtCOVERAGE_TEST_MARKER();
	}

	/* Call the timer callback. */
	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 801283a:	697b      	ldr	r3, [r7, #20]
 801283c:	6a1b      	ldr	r3, [r3, #32]
 801283e:	6978      	ldr	r0, [r7, #20]
 8012840:	4798      	blx	r3
}
 8012842:	bf00      	nop
 8012844:	3718      	adds	r7, #24
 8012846:	46bd      	mov	sp, r7
 8012848:	bd80      	pop	{r7, pc}
 801284a:	bf00      	nop
 801284c:	2400291c 	.word	0x2400291c

08012850 <prvTimerTask>:
/*-----------------------------------------------------------*/

static portTASK_FUNCTION( prvTimerTask, pvParameters )
{
 8012850:	b580      	push	{r7, lr}
 8012852:	b084      	sub	sp, #16
 8012854:	af00      	add	r7, sp, #0
 8012856:	6078      	str	r0, [r7, #4]

	for( ;; )
	{
		/* Query the timers list to see if it contains any timers, and if so,
		obtain the time at which the next timer will expire. */
		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
 8012858:	f107 0308 	add.w	r3, r7, #8
 801285c:	4618      	mov	r0, r3
 801285e:	f000 f859 	bl	8012914 <prvGetNextExpireTime>
 8012862:	60f8      	str	r0, [r7, #12]

		/* If a timer has expired, process it.  Otherwise, block this task
		until either a timer does expire, or a command is received. */
		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
 8012864:	68bb      	ldr	r3, [r7, #8]
 8012866:	4619      	mov	r1, r3
 8012868:	68f8      	ldr	r0, [r7, #12]
 801286a:	f000 f805 	bl	8012878 <prvProcessTimerOrBlockTask>

		/* Empty the command queue. */
		prvProcessReceivedCommands();
 801286e:	f000 f8d7 	bl	8012a20 <prvProcessReceivedCommands>
		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
 8012872:	bf00      	nop
 8012874:	e7f0      	b.n	8012858 <prvTimerTask+0x8>
	...

08012878 <prvProcessTimerOrBlockTask>:
	}
}
/*-----------------------------------------------------------*/

static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
{
 8012878:	b580      	push	{r7, lr}
 801287a:	b084      	sub	sp, #16
 801287c:	af00      	add	r7, sp, #0
 801287e:	6078      	str	r0, [r7, #4]
 8012880:	6039      	str	r1, [r7, #0]
TickType_t xTimeNow;
BaseType_t xTimerListsWereSwitched;

	vTaskSuspendAll();
 8012882:	f7fe feb5 	bl	80115f0 <vTaskSuspendAll>
		/* Obtain the time now to make an assessment as to whether the timer
		has expired or not.  If obtaining the time causes the lists to switch
		then don't process this timer as any timers that remained in the list
		when the lists were switched will have been processed within the
		prvSampleTimeNow() function. */
		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
 8012886:	f107 0308 	add.w	r3, r7, #8
 801288a:	4618      	mov	r0, r3
 801288c:	f000 f866 	bl	801295c <prvSampleTimeNow>
 8012890:	60f8      	str	r0, [r7, #12]
		if( xTimerListsWereSwitched == pdFALSE )
 8012892:	68bb      	ldr	r3, [r7, #8]
 8012894:	2b00      	cmp	r3, #0
 8012896:	d130      	bne.n	80128fa <prvProcessTimerOrBlockTask+0x82>
		{
			/* The tick count has not overflowed, has the timer expired? */
			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
 8012898:	683b      	ldr	r3, [r7, #0]
 801289a:	2b00      	cmp	r3, #0
 801289c:	d10a      	bne.n	80128b4 <prvProcessTimerOrBlockTask+0x3c>
 801289e:	687a      	ldr	r2, [r7, #4]
 80128a0:	68fb      	ldr	r3, [r7, #12]
 80128a2:	429a      	cmp	r2, r3
 80128a4:	d806      	bhi.n	80128b4 <prvProcessTimerOrBlockTask+0x3c>
			{
				( void ) xTaskResumeAll();
 80128a6:	f7fe feb1 	bl	801160c <xTaskResumeAll>
				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
 80128aa:	68f9      	ldr	r1, [r7, #12]
 80128ac:	6878      	ldr	r0, [r7, #4]
 80128ae:	f7ff ff81 	bl	80127b4 <prvProcessExpiredTimer>
		else
		{
			( void ) xTaskResumeAll();
		}
	}
}
 80128b2:	e024      	b.n	80128fe <prvProcessTimerOrBlockTask+0x86>
				if( xListWasEmpty != pdFALSE )
 80128b4:	683b      	ldr	r3, [r7, #0]
 80128b6:	2b00      	cmp	r3, #0
 80128b8:	d008      	beq.n	80128cc <prvProcessTimerOrBlockTask+0x54>
					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
 80128ba:	4b13      	ldr	r3, [pc, #76]	@ (8012908 <prvProcessTimerOrBlockTask+0x90>)
 80128bc:	681b      	ldr	r3, [r3, #0]
 80128be:	681b      	ldr	r3, [r3, #0]
 80128c0:	2b00      	cmp	r3, #0
 80128c2:	d101      	bne.n	80128c8 <prvProcessTimerOrBlockTask+0x50>
 80128c4:	2301      	movs	r3, #1
 80128c6:	e000      	b.n	80128ca <prvProcessTimerOrBlockTask+0x52>
 80128c8:	2300      	movs	r3, #0
 80128ca:	603b      	str	r3, [r7, #0]
				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
 80128cc:	4b0f      	ldr	r3, [pc, #60]	@ (801290c <prvProcessTimerOrBlockTask+0x94>)
 80128ce:	6818      	ldr	r0, [r3, #0]
 80128d0:	687a      	ldr	r2, [r7, #4]
 80128d2:	68fb      	ldr	r3, [r7, #12]
 80128d4:	1ad3      	subs	r3, r2, r3
 80128d6:	683a      	ldr	r2, [r7, #0]
 80128d8:	4619      	mov	r1, r3
 80128da:	f7fe fa33 	bl	8010d44 <vQueueWaitForMessageRestricted>
				if( xTaskResumeAll() == pdFALSE )
 80128de:	f7fe fe95 	bl	801160c <xTaskResumeAll>
 80128e2:	4603      	mov	r3, r0
 80128e4:	2b00      	cmp	r3, #0
 80128e6:	d10a      	bne.n	80128fe <prvProcessTimerOrBlockTask+0x86>
					portYIELD_WITHIN_API();
 80128e8:	4b09      	ldr	r3, [pc, #36]	@ (8012910 <prvProcessTimerOrBlockTask+0x98>)
 80128ea:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80128ee:	601a      	str	r2, [r3, #0]
 80128f0:	f3bf 8f4f 	dsb	sy
 80128f4:	f3bf 8f6f 	isb	sy
}
 80128f8:	e001      	b.n	80128fe <prvProcessTimerOrBlockTask+0x86>
			( void ) xTaskResumeAll();
 80128fa:	f7fe fe87 	bl	801160c <xTaskResumeAll>
}
 80128fe:	bf00      	nop
 8012900:	3710      	adds	r7, #16
 8012902:	46bd      	mov	sp, r7
 8012904:	bd80      	pop	{r7, pc}
 8012906:	bf00      	nop
 8012908:	24002920 	.word	0x24002920
 801290c:	24002924 	.word	0x24002924
 8012910:	e000ed04 	.word	0xe000ed04

08012914 <prvGetNextExpireTime>:
/*-----------------------------------------------------------*/

static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
{
 8012914:	b480      	push	{r7}
 8012916:	b085      	sub	sp, #20
 8012918:	af00      	add	r7, sp, #0
 801291a:	6078      	str	r0, [r7, #4]
	the timer with the nearest expiry time will expire.  If there are no
	active timers then just set the next expire time to 0.  That will cause
	this task to unblock when the tick count overflows, at which point the
	timer lists will be switched and the next expiry time can be
	re-assessed.  */
	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
 801291c:	4b0e      	ldr	r3, [pc, #56]	@ (8012958 <prvGetNextExpireTime+0x44>)
 801291e:	681b      	ldr	r3, [r3, #0]
 8012920:	681b      	ldr	r3, [r3, #0]
 8012922:	2b00      	cmp	r3, #0
 8012924:	d101      	bne.n	801292a <prvGetNextExpireTime+0x16>
 8012926:	2201      	movs	r2, #1
 8012928:	e000      	b.n	801292c <prvGetNextExpireTime+0x18>
 801292a:	2200      	movs	r2, #0
 801292c:	687b      	ldr	r3, [r7, #4]
 801292e:	601a      	str	r2, [r3, #0]
	if( *pxListWasEmpty == pdFALSE )
 8012930:	687b      	ldr	r3, [r7, #4]
 8012932:	681b      	ldr	r3, [r3, #0]
 8012934:	2b00      	cmp	r3, #0
 8012936:	d105      	bne.n	8012944 <prvGetNextExpireTime+0x30>
	{
		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 8012938:	4b07      	ldr	r3, [pc, #28]	@ (8012958 <prvGetNextExpireTime+0x44>)
 801293a:	681b      	ldr	r3, [r3, #0]
 801293c:	68db      	ldr	r3, [r3, #12]
 801293e:	681b      	ldr	r3, [r3, #0]
 8012940:	60fb      	str	r3, [r7, #12]
 8012942:	e001      	b.n	8012948 <prvGetNextExpireTime+0x34>
	}
	else
	{
		/* Ensure the task unblocks when the tick count rolls over. */
		xNextExpireTime = ( TickType_t ) 0U;
 8012944:	2300      	movs	r3, #0
 8012946:	60fb      	str	r3, [r7, #12]
	}

	return xNextExpireTime;
 8012948:	68fb      	ldr	r3, [r7, #12]
}
 801294a:	4618      	mov	r0, r3
 801294c:	3714      	adds	r7, #20
 801294e:	46bd      	mov	sp, r7
 8012950:	f85d 7b04 	ldr.w	r7, [sp], #4
 8012954:	4770      	bx	lr
 8012956:	bf00      	nop
 8012958:	2400291c 	.word	0x2400291c

0801295c <prvSampleTimeNow>:
/*-----------------------------------------------------------*/

static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
{
 801295c:	b580      	push	{r7, lr}
 801295e:	b084      	sub	sp, #16
 8012960:	af00      	add	r7, sp, #0
 8012962:	6078      	str	r0, [r7, #4]
TickType_t xTimeNow;
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */

	xTimeNow = xTaskGetTickCount();
 8012964:	f7fe fef0 	bl	8011748 <xTaskGetTickCount>
 8012968:	60f8      	str	r0, [r7, #12]

	if( xTimeNow < xLastTime )
 801296a:	4b0b      	ldr	r3, [pc, #44]	@ (8012998 <prvSampleTimeNow+0x3c>)
 801296c:	681b      	ldr	r3, [r3, #0]
 801296e:	68fa      	ldr	r2, [r7, #12]
 8012970:	429a      	cmp	r2, r3
 8012972:	d205      	bcs.n	8012980 <prvSampleTimeNow+0x24>
	{
		prvSwitchTimerLists();
 8012974:	f000 f93a 	bl	8012bec <prvSwitchTimerLists>
		*pxTimerListsWereSwitched = pdTRUE;
 8012978:	687b      	ldr	r3, [r7, #4]
 801297a:	2201      	movs	r2, #1
 801297c:	601a      	str	r2, [r3, #0]
 801297e:	e002      	b.n	8012986 <prvSampleTimeNow+0x2a>
	}
	else
	{
		*pxTimerListsWereSwitched = pdFALSE;
 8012980:	687b      	ldr	r3, [r7, #4]
 8012982:	2200      	movs	r2, #0
 8012984:	601a      	str	r2, [r3, #0]
	}

	xLastTime = xTimeNow;
 8012986:	4a04      	ldr	r2, [pc, #16]	@ (8012998 <prvSampleTimeNow+0x3c>)
 8012988:	68fb      	ldr	r3, [r7, #12]
 801298a:	6013      	str	r3, [r2, #0]

	return xTimeNow;
 801298c:	68fb      	ldr	r3, [r7, #12]
}
 801298e:	4618      	mov	r0, r3
 8012990:	3710      	adds	r7, #16
 8012992:	46bd      	mov	sp, r7
 8012994:	bd80      	pop	{r7, pc}
 8012996:	bf00      	nop
 8012998:	2400292c 	.word	0x2400292c

0801299c <prvInsertTimerInActiveList>:
/*-----------------------------------------------------------*/

static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
{
 801299c:	b580      	push	{r7, lr}
 801299e:	b086      	sub	sp, #24
 80129a0:	af00      	add	r7, sp, #0
 80129a2:	60f8      	str	r0, [r7, #12]
 80129a4:	60b9      	str	r1, [r7, #8]
 80129a6:	607a      	str	r2, [r7, #4]
 80129a8:	603b      	str	r3, [r7, #0]
BaseType_t xProcessTimerNow = pdFALSE;
 80129aa:	2300      	movs	r3, #0
 80129ac:	617b      	str	r3, [r7, #20]

	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
 80129ae:	68fb      	ldr	r3, [r7, #12]
 80129b0:	68ba      	ldr	r2, [r7, #8]
 80129b2:	605a      	str	r2, [r3, #4]
	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
 80129b4:	68fb      	ldr	r3, [r7, #12]
 80129b6:	68fa      	ldr	r2, [r7, #12]
 80129b8:	611a      	str	r2, [r3, #16]

	if( xNextExpiryTime <= xTimeNow )
 80129ba:	68ba      	ldr	r2, [r7, #8]
 80129bc:	687b      	ldr	r3, [r7, #4]
 80129be:	429a      	cmp	r2, r3
 80129c0:	d812      	bhi.n	80129e8 <prvInsertTimerInActiveList+0x4c>
	{
		/* Has the expiry time elapsed between the command to start/reset a
		timer was issued, and the time the command was processed? */
		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80129c2:	687a      	ldr	r2, [r7, #4]
 80129c4:	683b      	ldr	r3, [r7, #0]
 80129c6:	1ad2      	subs	r2, r2, r3
 80129c8:	68fb      	ldr	r3, [r7, #12]
 80129ca:	699b      	ldr	r3, [r3, #24]
 80129cc:	429a      	cmp	r2, r3
 80129ce:	d302      	bcc.n	80129d6 <prvInsertTimerInActiveList+0x3a>
		{
			/* The time between a command being issued and the command being
			processed actually exceeds the timers period.  */
			xProcessTimerNow = pdTRUE;
 80129d0:	2301      	movs	r3, #1
 80129d2:	617b      	str	r3, [r7, #20]
 80129d4:	e01b      	b.n	8012a0e <prvInsertTimerInActiveList+0x72>
		}
		else
		{
			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
 80129d6:	4b10      	ldr	r3, [pc, #64]	@ (8012a18 <prvInsertTimerInActiveList+0x7c>)
 80129d8:	681a      	ldr	r2, [r3, #0]
 80129da:	68fb      	ldr	r3, [r7, #12]
 80129dc:	3304      	adds	r3, #4
 80129de:	4619      	mov	r1, r3
 80129e0:	4610      	mov	r0, r2
 80129e2:	f7fd f9e8 	bl	800fdb6 <vListInsert>
 80129e6:	e012      	b.n	8012a0e <prvInsertTimerInActiveList+0x72>
		}
	}
	else
	{
		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
 80129e8:	687a      	ldr	r2, [r7, #4]
 80129ea:	683b      	ldr	r3, [r7, #0]
 80129ec:	429a      	cmp	r2, r3
 80129ee:	d206      	bcs.n	80129fe <prvInsertTimerInActiveList+0x62>
 80129f0:	68ba      	ldr	r2, [r7, #8]
 80129f2:	683b      	ldr	r3, [r7, #0]
 80129f4:	429a      	cmp	r2, r3
 80129f6:	d302      	bcc.n	80129fe <prvInsertTimerInActiveList+0x62>
		{
			/* If, since the command was issued, the tick count has overflowed
			but the expiry time has not, then the timer must have already passed
			its expiry time and should be processed immediately. */
			xProcessTimerNow = pdTRUE;
 80129f8:	2301      	movs	r3, #1
 80129fa:	617b      	str	r3, [r7, #20]
 80129fc:	e007      	b.n	8012a0e <prvInsertTimerInActiveList+0x72>
		}
		else
		{
			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
 80129fe:	4b07      	ldr	r3, [pc, #28]	@ (8012a1c <prvInsertTimerInActiveList+0x80>)
 8012a00:	681a      	ldr	r2, [r3, #0]
 8012a02:	68fb      	ldr	r3, [r7, #12]
 8012a04:	3304      	adds	r3, #4
 8012a06:	4619      	mov	r1, r3
 8012a08:	4610      	mov	r0, r2
 8012a0a:	f7fd f9d4 	bl	800fdb6 <vListInsert>
		}
	}

	return xProcessTimerNow;
 8012a0e:	697b      	ldr	r3, [r7, #20]
}
 8012a10:	4618      	mov	r0, r3
 8012a12:	3718      	adds	r7, #24
 8012a14:	46bd      	mov	sp, r7
 8012a16:	bd80      	pop	{r7, pc}
 8012a18:	24002920 	.word	0x24002920
 8012a1c:	2400291c 	.word	0x2400291c

08012a20 <prvProcessReceivedCommands>:
/*-----------------------------------------------------------*/

static void	prvProcessReceivedCommands( void )
{
 8012a20:	b580      	push	{r7, lr}
 8012a22:	b08e      	sub	sp, #56	@ 0x38
 8012a24:	af02      	add	r7, sp, #8
DaemonTaskMessage_t xMessage;
Timer_t *pxTimer;
BaseType_t xTimerListsWereSwitched, xResult;
TickType_t xTimeNow;

	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
 8012a26:	e0ce      	b.n	8012bc6 <prvProcessReceivedCommands+0x1a6>
	{
		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
		{
			/* Negative commands are pended function calls rather than timer
			commands. */
			if( xMessage.xMessageID < ( BaseType_t ) 0 )
 8012a28:	687b      	ldr	r3, [r7, #4]
 8012a2a:	2b00      	cmp	r3, #0
 8012a2c:	da19      	bge.n	8012a62 <prvProcessReceivedCommands+0x42>
			{
				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
 8012a2e:	1d3b      	adds	r3, r7, #4
 8012a30:	3304      	adds	r3, #4
 8012a32:	62fb      	str	r3, [r7, #44]	@ 0x2c

				/* The timer uses the xCallbackParameters member to request a
				callback be executed.  Check the callback is not NULL. */
				configASSERT( pxCallback );
 8012a34:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8012a36:	2b00      	cmp	r3, #0
 8012a38:	d10b      	bne.n	8012a52 <prvProcessReceivedCommands+0x32>
	__asm volatile
 8012a3a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012a3e:	f383 8811 	msr	BASEPRI, r3
 8012a42:	f3bf 8f6f 	isb	sy
 8012a46:	f3bf 8f4f 	dsb	sy
 8012a4a:	61fb      	str	r3, [r7, #28]
}
 8012a4c:	bf00      	nop
 8012a4e:	bf00      	nop
 8012a50:	e7fd      	b.n	8012a4e <prvProcessReceivedCommands+0x2e>

				/* Call the function. */
				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
 8012a52:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8012a54:	681b      	ldr	r3, [r3, #0]
 8012a56:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8012a58:	6850      	ldr	r0, [r2, #4]
 8012a5a:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8012a5c:	6892      	ldr	r2, [r2, #8]
 8012a5e:	4611      	mov	r1, r2
 8012a60:	4798      	blx	r3
		}
		#endif /* INCLUDE_xTimerPendFunctionCall */

		/* Commands that are positive are timer commands rather than pended
		function calls. */
		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
 8012a62:	687b      	ldr	r3, [r7, #4]
 8012a64:	2b00      	cmp	r3, #0
 8012a66:	f2c0 80ae 	blt.w	8012bc6 <prvProcessReceivedCommands+0x1a6>
		{
			/* The messages uses the xTimerParameters member to work on a
			software timer. */
			pxTimer = xMessage.u.xTimerParameters.pxTimer;
 8012a6a:	68fb      	ldr	r3, [r7, #12]
 8012a6c:	62bb      	str	r3, [r7, #40]	@ 0x28

			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
 8012a6e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012a70:	695b      	ldr	r3, [r3, #20]
 8012a72:	2b00      	cmp	r3, #0
 8012a74:	d004      	beq.n	8012a80 <prvProcessReceivedCommands+0x60>
			{
				/* The timer is in a list, remove it. */
				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 8012a76:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012a78:	3304      	adds	r3, #4
 8012a7a:	4618      	mov	r0, r3
 8012a7c:	f7fd f9d4 	bl	800fe28 <uxListRemove>
			it must be present in the function call.  prvSampleTimeNow() must be
			called after the message is received from xTimerQueue so there is no
			possibility of a higher priority task adding a message to the message
			queue with a time that is ahead of the timer daemon task (because it
			pre-empted the timer daemon task after the xTimeNow value was set). */
			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
 8012a80:	463b      	mov	r3, r7
 8012a82:	4618      	mov	r0, r3
 8012a84:	f7ff ff6a 	bl	801295c <prvSampleTimeNow>
 8012a88:	6278      	str	r0, [r7, #36]	@ 0x24

			switch( xMessage.xMessageID )
 8012a8a:	687b      	ldr	r3, [r7, #4]
 8012a8c:	2b09      	cmp	r3, #9
 8012a8e:	f200 8097 	bhi.w	8012bc0 <prvProcessReceivedCommands+0x1a0>
 8012a92:	a201      	add	r2, pc, #4	@ (adr r2, 8012a98 <prvProcessReceivedCommands+0x78>)
 8012a94:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8012a98:	08012ac1 	.word	0x08012ac1
 8012a9c:	08012ac1 	.word	0x08012ac1
 8012aa0:	08012ac1 	.word	0x08012ac1
 8012aa4:	08012b37 	.word	0x08012b37
 8012aa8:	08012b4b 	.word	0x08012b4b
 8012aac:	08012b97 	.word	0x08012b97
 8012ab0:	08012ac1 	.word	0x08012ac1
 8012ab4:	08012ac1 	.word	0x08012ac1
 8012ab8:	08012b37 	.word	0x08012b37
 8012abc:	08012b4b 	.word	0x08012b4b
				case tmrCOMMAND_START_FROM_ISR :
				case tmrCOMMAND_RESET :
				case tmrCOMMAND_RESET_FROM_ISR :
				case tmrCOMMAND_START_DONT_TRACE :
					/* Start or restart a timer. */
					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 8012ac0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012ac2:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8012ac6:	f043 0301 	orr.w	r3, r3, #1
 8012aca:	b2da      	uxtb	r2, r3
 8012acc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012ace:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
 8012ad2:	68ba      	ldr	r2, [r7, #8]
 8012ad4:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012ad6:	699b      	ldr	r3, [r3, #24]
 8012ad8:	18d1      	adds	r1, r2, r3
 8012ada:	68bb      	ldr	r3, [r7, #8]
 8012adc:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8012ade:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8012ae0:	f7ff ff5c 	bl	801299c <prvInsertTimerInActiveList>
 8012ae4:	4603      	mov	r3, r0
 8012ae6:	2b00      	cmp	r3, #0
 8012ae8:	d06c      	beq.n	8012bc4 <prvProcessReceivedCommands+0x1a4>
					{
						/* The timer expired before it was added to the active
						timer list.  Process it now. */
						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 8012aea:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012aec:	6a1b      	ldr	r3, [r3, #32]
 8012aee:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8012af0:	4798      	blx	r3
						traceTIMER_EXPIRED( pxTimer );

						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 8012af2:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012af4:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8012af8:	f003 0304 	and.w	r3, r3, #4
 8012afc:	2b00      	cmp	r3, #0
 8012afe:	d061      	beq.n	8012bc4 <prvProcessReceivedCommands+0x1a4>
						{
							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
 8012b00:	68ba      	ldr	r2, [r7, #8]
 8012b02:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012b04:	699b      	ldr	r3, [r3, #24]
 8012b06:	441a      	add	r2, r3
 8012b08:	2300      	movs	r3, #0
 8012b0a:	9300      	str	r3, [sp, #0]
 8012b0c:	2300      	movs	r3, #0
 8012b0e:	2100      	movs	r1, #0
 8012b10:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8012b12:	f7ff fe01 	bl	8012718 <xTimerGenericCommand>
 8012b16:	6238      	str	r0, [r7, #32]
							configASSERT( xResult );
 8012b18:	6a3b      	ldr	r3, [r7, #32]
 8012b1a:	2b00      	cmp	r3, #0
 8012b1c:	d152      	bne.n	8012bc4 <prvProcessReceivedCommands+0x1a4>
	__asm volatile
 8012b1e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012b22:	f383 8811 	msr	BASEPRI, r3
 8012b26:	f3bf 8f6f 	isb	sy
 8012b2a:	f3bf 8f4f 	dsb	sy
 8012b2e:	61bb      	str	r3, [r7, #24]
}
 8012b30:	bf00      	nop
 8012b32:	bf00      	nop
 8012b34:	e7fd      	b.n	8012b32 <prvProcessReceivedCommands+0x112>
					break;

				case tmrCOMMAND_STOP :
				case tmrCOMMAND_STOP_FROM_ISR :
					/* The timer has already been removed from the active list. */
					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8012b36:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012b38:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8012b3c:	f023 0301 	bic.w	r3, r3, #1
 8012b40:	b2da      	uxtb	r2, r3
 8012b42:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012b44:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					break;
 8012b48:	e03d      	b.n	8012bc6 <prvProcessReceivedCommands+0x1a6>

				case tmrCOMMAND_CHANGE_PERIOD :
				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 8012b4a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012b4c:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8012b50:	f043 0301 	orr.w	r3, r3, #1
 8012b54:	b2da      	uxtb	r2, r3
 8012b56:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012b58:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
 8012b5c:	68ba      	ldr	r2, [r7, #8]
 8012b5e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012b60:	619a      	str	r2, [r3, #24]
					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
 8012b62:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012b64:	699b      	ldr	r3, [r3, #24]
 8012b66:	2b00      	cmp	r3, #0
 8012b68:	d10b      	bne.n	8012b82 <prvProcessReceivedCommands+0x162>
	__asm volatile
 8012b6a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012b6e:	f383 8811 	msr	BASEPRI, r3
 8012b72:	f3bf 8f6f 	isb	sy
 8012b76:	f3bf 8f4f 	dsb	sy
 8012b7a:	617b      	str	r3, [r7, #20]
}
 8012b7c:	bf00      	nop
 8012b7e:	bf00      	nop
 8012b80:	e7fd      	b.n	8012b7e <prvProcessReceivedCommands+0x15e>
					be longer or shorter than the old one.  The command time is
					therefore set to the current time, and as the period cannot
					be zero the next expiry time can only be in the future,
					meaning (unlike for the xTimerStart() case above) there is
					no fail case that needs to be handled here. */
					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
 8012b82:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012b84:	699a      	ldr	r2, [r3, #24]
 8012b86:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8012b88:	18d1      	adds	r1, r2, r3
 8012b8a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8012b8c:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8012b8e:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8012b90:	f7ff ff04 	bl	801299c <prvInsertTimerInActiveList>
					break;
 8012b94:	e017      	b.n	8012bc6 <prvProcessReceivedCommands+0x1a6>
					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
					{
						/* The timer has already been removed from the active list,
						just free up the memory if the memory was dynamically
						allocated. */
						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
 8012b96:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012b98:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8012b9c:	f003 0302 	and.w	r3, r3, #2
 8012ba0:	2b00      	cmp	r3, #0
 8012ba2:	d103      	bne.n	8012bac <prvProcessReceivedCommands+0x18c>
						{
							vPortFree( pxTimer );
 8012ba4:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8012ba6:	f000 fbe7 	bl	8013378 <vPortFree>
						no need to free the memory - just mark the timer as
						"not active". */
						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
					}
					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
					break;
 8012baa:	e00c      	b.n	8012bc6 <prvProcessReceivedCommands+0x1a6>
							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8012bac:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012bae:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8012bb2:	f023 0301 	bic.w	r3, r3, #1
 8012bb6:	b2da      	uxtb	r2, r3
 8012bb8:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012bba:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					break;
 8012bbe:	e002      	b.n	8012bc6 <prvProcessReceivedCommands+0x1a6>

				default	:
					/* Don't expect to get here. */
					break;
 8012bc0:	bf00      	nop
 8012bc2:	e000      	b.n	8012bc6 <prvProcessReceivedCommands+0x1a6>
					break;
 8012bc4:	bf00      	nop
	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
 8012bc6:	4b08      	ldr	r3, [pc, #32]	@ (8012be8 <prvProcessReceivedCommands+0x1c8>)
 8012bc8:	681b      	ldr	r3, [r3, #0]
 8012bca:	1d39      	adds	r1, r7, #4
 8012bcc:	2200      	movs	r2, #0
 8012bce:	4618      	mov	r0, r3
 8012bd0:	f7fd fcf2 	bl	80105b8 <xQueueReceive>
 8012bd4:	4603      	mov	r3, r0
 8012bd6:	2b00      	cmp	r3, #0
 8012bd8:	f47f af26 	bne.w	8012a28 <prvProcessReceivedCommands+0x8>
			}
		}
	}
}
 8012bdc:	bf00      	nop
 8012bde:	bf00      	nop
 8012be0:	3730      	adds	r7, #48	@ 0x30
 8012be2:	46bd      	mov	sp, r7
 8012be4:	bd80      	pop	{r7, pc}
 8012be6:	bf00      	nop
 8012be8:	24002924 	.word	0x24002924

08012bec <prvSwitchTimerLists>:
/*-----------------------------------------------------------*/

static void prvSwitchTimerLists( void )
{
 8012bec:	b580      	push	{r7, lr}
 8012bee:	b088      	sub	sp, #32
 8012bf0:	af02      	add	r7, sp, #8

	/* The tick count has overflowed.  The timer lists must be switched.
	If there are any timers still referenced from the current timer list
	then they must have expired and should be processed before the lists
	are switched. */
	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
 8012bf2:	e049      	b.n	8012c88 <prvSwitchTimerLists+0x9c>
	{
		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 8012bf4:	4b2e      	ldr	r3, [pc, #184]	@ (8012cb0 <prvSwitchTimerLists+0xc4>)
 8012bf6:	681b      	ldr	r3, [r3, #0]
 8012bf8:	68db      	ldr	r3, [r3, #12]
 8012bfa:	681b      	ldr	r3, [r3, #0]
 8012bfc:	613b      	str	r3, [r7, #16]

		/* Remove the timer from the list. */
		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8012bfe:	4b2c      	ldr	r3, [pc, #176]	@ (8012cb0 <prvSwitchTimerLists+0xc4>)
 8012c00:	681b      	ldr	r3, [r3, #0]
 8012c02:	68db      	ldr	r3, [r3, #12]
 8012c04:	68db      	ldr	r3, [r3, #12]
 8012c06:	60fb      	str	r3, [r7, #12]
		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 8012c08:	68fb      	ldr	r3, [r7, #12]
 8012c0a:	3304      	adds	r3, #4
 8012c0c:	4618      	mov	r0, r3
 8012c0e:	f7fd f90b 	bl	800fe28 <uxListRemove>
		traceTIMER_EXPIRED( pxTimer );

		/* Execute its callback, then send a command to restart the timer if
		it is an auto-reload timer.  It cannot be restarted here as the lists
		have not yet been switched. */
		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 8012c12:	68fb      	ldr	r3, [r7, #12]
 8012c14:	6a1b      	ldr	r3, [r3, #32]
 8012c16:	68f8      	ldr	r0, [r7, #12]
 8012c18:	4798      	blx	r3

		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 8012c1a:	68fb      	ldr	r3, [r7, #12]
 8012c1c:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8012c20:	f003 0304 	and.w	r3, r3, #4
 8012c24:	2b00      	cmp	r3, #0
 8012c26:	d02f      	beq.n	8012c88 <prvSwitchTimerLists+0x9c>
			the timer going into the same timer list then it has already expired
			and the timer should be re-inserted into the current list so it is
			processed again within this loop.  Otherwise a command should be sent
			to restart the timer to ensure it is only inserted into a list after
			the lists have been swapped. */
			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
 8012c28:	68fb      	ldr	r3, [r7, #12]
 8012c2a:	699b      	ldr	r3, [r3, #24]
 8012c2c:	693a      	ldr	r2, [r7, #16]
 8012c2e:	4413      	add	r3, r2
 8012c30:	60bb      	str	r3, [r7, #8]
			if( xReloadTime > xNextExpireTime )
 8012c32:	68ba      	ldr	r2, [r7, #8]
 8012c34:	693b      	ldr	r3, [r7, #16]
 8012c36:	429a      	cmp	r2, r3
 8012c38:	d90e      	bls.n	8012c58 <prvSwitchTimerLists+0x6c>
			{
				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
 8012c3a:	68fb      	ldr	r3, [r7, #12]
 8012c3c:	68ba      	ldr	r2, [r7, #8]
 8012c3e:	605a      	str	r2, [r3, #4]
				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
 8012c40:	68fb      	ldr	r3, [r7, #12]
 8012c42:	68fa      	ldr	r2, [r7, #12]
 8012c44:	611a      	str	r2, [r3, #16]
				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
 8012c46:	4b1a      	ldr	r3, [pc, #104]	@ (8012cb0 <prvSwitchTimerLists+0xc4>)
 8012c48:	681a      	ldr	r2, [r3, #0]
 8012c4a:	68fb      	ldr	r3, [r7, #12]
 8012c4c:	3304      	adds	r3, #4
 8012c4e:	4619      	mov	r1, r3
 8012c50:	4610      	mov	r0, r2
 8012c52:	f7fd f8b0 	bl	800fdb6 <vListInsert>
 8012c56:	e017      	b.n	8012c88 <prvSwitchTimerLists+0x9c>
			}
			else
			{
				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
 8012c58:	2300      	movs	r3, #0
 8012c5a:	9300      	str	r3, [sp, #0]
 8012c5c:	2300      	movs	r3, #0
 8012c5e:	693a      	ldr	r2, [r7, #16]
 8012c60:	2100      	movs	r1, #0
 8012c62:	68f8      	ldr	r0, [r7, #12]
 8012c64:	f7ff fd58 	bl	8012718 <xTimerGenericCommand>
 8012c68:	6078      	str	r0, [r7, #4]
				configASSERT( xResult );
 8012c6a:	687b      	ldr	r3, [r7, #4]
 8012c6c:	2b00      	cmp	r3, #0
 8012c6e:	d10b      	bne.n	8012c88 <prvSwitchTimerLists+0x9c>
	__asm volatile
 8012c70:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012c74:	f383 8811 	msr	BASEPRI, r3
 8012c78:	f3bf 8f6f 	isb	sy
 8012c7c:	f3bf 8f4f 	dsb	sy
 8012c80:	603b      	str	r3, [r7, #0]
}
 8012c82:	bf00      	nop
 8012c84:	bf00      	nop
 8012c86:	e7fd      	b.n	8012c84 <prvSwitchTimerLists+0x98>
	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
 8012c88:	4b09      	ldr	r3, [pc, #36]	@ (8012cb0 <prvSwitchTimerLists+0xc4>)
 8012c8a:	681b      	ldr	r3, [r3, #0]
 8012c8c:	681b      	ldr	r3, [r3, #0]
 8012c8e:	2b00      	cmp	r3, #0
 8012c90:	d1b0      	bne.n	8012bf4 <prvSwitchTimerLists+0x8>
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}

	pxTemp = pxCurrentTimerList;
 8012c92:	4b07      	ldr	r3, [pc, #28]	@ (8012cb0 <prvSwitchTimerLists+0xc4>)
 8012c94:	681b      	ldr	r3, [r3, #0]
 8012c96:	617b      	str	r3, [r7, #20]
	pxCurrentTimerList = pxOverflowTimerList;
 8012c98:	4b06      	ldr	r3, [pc, #24]	@ (8012cb4 <prvSwitchTimerLists+0xc8>)
 8012c9a:	681b      	ldr	r3, [r3, #0]
 8012c9c:	4a04      	ldr	r2, [pc, #16]	@ (8012cb0 <prvSwitchTimerLists+0xc4>)
 8012c9e:	6013      	str	r3, [r2, #0]
	pxOverflowTimerList = pxTemp;
 8012ca0:	4a04      	ldr	r2, [pc, #16]	@ (8012cb4 <prvSwitchTimerLists+0xc8>)
 8012ca2:	697b      	ldr	r3, [r7, #20]
 8012ca4:	6013      	str	r3, [r2, #0]
}
 8012ca6:	bf00      	nop
 8012ca8:	3718      	adds	r7, #24
 8012caa:	46bd      	mov	sp, r7
 8012cac:	bd80      	pop	{r7, pc}
 8012cae:	bf00      	nop
 8012cb0:	2400291c 	.word	0x2400291c
 8012cb4:	24002920 	.word	0x24002920

08012cb8 <prvCheckForValidListAndQueue>:
/*-----------------------------------------------------------*/

static void prvCheckForValidListAndQueue( void )
{
 8012cb8:	b580      	push	{r7, lr}
 8012cba:	b082      	sub	sp, #8
 8012cbc:	af02      	add	r7, sp, #8
	/* Check that the list from which active timers are referenced, and the
	queue used to communicate with the timer service, have been
	initialised. */
	taskENTER_CRITICAL();
 8012cbe:	f000 f96b 	bl	8012f98 <vPortEnterCritical>
	{
		if( xTimerQueue == NULL )
 8012cc2:	4b15      	ldr	r3, [pc, #84]	@ (8012d18 <prvCheckForValidListAndQueue+0x60>)
 8012cc4:	681b      	ldr	r3, [r3, #0]
 8012cc6:	2b00      	cmp	r3, #0
 8012cc8:	d120      	bne.n	8012d0c <prvCheckForValidListAndQueue+0x54>
		{
			vListInitialise( &xActiveTimerList1 );
 8012cca:	4814      	ldr	r0, [pc, #80]	@ (8012d1c <prvCheckForValidListAndQueue+0x64>)
 8012ccc:	f7fd f822 	bl	800fd14 <vListInitialise>
			vListInitialise( &xActiveTimerList2 );
 8012cd0:	4813      	ldr	r0, [pc, #76]	@ (8012d20 <prvCheckForValidListAndQueue+0x68>)
 8012cd2:	f7fd f81f 	bl	800fd14 <vListInitialise>
			pxCurrentTimerList = &xActiveTimerList1;
 8012cd6:	4b13      	ldr	r3, [pc, #76]	@ (8012d24 <prvCheckForValidListAndQueue+0x6c>)
 8012cd8:	4a10      	ldr	r2, [pc, #64]	@ (8012d1c <prvCheckForValidListAndQueue+0x64>)
 8012cda:	601a      	str	r2, [r3, #0]
			pxOverflowTimerList = &xActiveTimerList2;
 8012cdc:	4b12      	ldr	r3, [pc, #72]	@ (8012d28 <prvCheckForValidListAndQueue+0x70>)
 8012cde:	4a10      	ldr	r2, [pc, #64]	@ (8012d20 <prvCheckForValidListAndQueue+0x68>)
 8012ce0:	601a      	str	r2, [r3, #0]
				/* The timer queue is allocated statically in case
				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */

				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
 8012ce2:	2300      	movs	r3, #0
 8012ce4:	9300      	str	r3, [sp, #0]
 8012ce6:	4b11      	ldr	r3, [pc, #68]	@ (8012d2c <prvCheckForValidListAndQueue+0x74>)
 8012ce8:	4a11      	ldr	r2, [pc, #68]	@ (8012d30 <prvCheckForValidListAndQueue+0x78>)
 8012cea:	2110      	movs	r1, #16
 8012cec:	200a      	movs	r0, #10
 8012cee:	f7fd f92f 	bl	800ff50 <xQueueGenericCreateStatic>
 8012cf2:	4603      	mov	r3, r0
 8012cf4:	4a08      	ldr	r2, [pc, #32]	@ (8012d18 <prvCheckForValidListAndQueue+0x60>)
 8012cf6:	6013      	str	r3, [r2, #0]
			}
			#endif

			#if ( configQUEUE_REGISTRY_SIZE > 0 )
			{
				if( xTimerQueue != NULL )
 8012cf8:	4b07      	ldr	r3, [pc, #28]	@ (8012d18 <prvCheckForValidListAndQueue+0x60>)
 8012cfa:	681b      	ldr	r3, [r3, #0]
 8012cfc:	2b00      	cmp	r3, #0
 8012cfe:	d005      	beq.n	8012d0c <prvCheckForValidListAndQueue+0x54>
				{
					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
 8012d00:	4b05      	ldr	r3, [pc, #20]	@ (8012d18 <prvCheckForValidListAndQueue+0x60>)
 8012d02:	681b      	ldr	r3, [r3, #0]
 8012d04:	490b      	ldr	r1, [pc, #44]	@ (8012d34 <prvCheckForValidListAndQueue+0x7c>)
 8012d06:	4618      	mov	r0, r3
 8012d08:	f7fd fff2 	bl	8010cf0 <vQueueAddToRegistry>
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
	taskEXIT_CRITICAL();
 8012d0c:	f000 f976 	bl	8012ffc <vPortExitCritical>
}
 8012d10:	bf00      	nop
 8012d12:	46bd      	mov	sp, r7
 8012d14:	bd80      	pop	{r7, pc}
 8012d16:	bf00      	nop
 8012d18:	24002924 	.word	0x24002924
 8012d1c:	240028f4 	.word	0x240028f4
 8012d20:	24002908 	.word	0x24002908
 8012d24:	2400291c 	.word	0x2400291c
 8012d28:	24002920 	.word	0x24002920
 8012d2c:	240029d0 	.word	0x240029d0
 8012d30:	24002930 	.word	0x24002930
 8012d34:	080145b8 	.word	0x080145b8

08012d38 <pxPortInitialiseStack>:

/*
 * See header file for description.
 */
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
 8012d38:	b480      	push	{r7}
 8012d3a:	b085      	sub	sp, #20
 8012d3c:	af00      	add	r7, sp, #0
 8012d3e:	60f8      	str	r0, [r7, #12]
 8012d40:	60b9      	str	r1, [r7, #8]
 8012d42:	607a      	str	r2, [r7, #4]
	/* Simulate the stack frame as it would be created by a context switch
	interrupt. */

	/* Offset added to account for the way the MCU uses the stack on entry/exit
	of interrupts, and to ensure alignment. */
	pxTopOfStack--;
 8012d44:	68fb      	ldr	r3, [r7, #12]
 8012d46:	3b04      	subs	r3, #4
 8012d48:	60fb      	str	r3, [r7, #12]

	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
 8012d4a:	68fb      	ldr	r3, [r7, #12]
 8012d4c:	f04f 7280 	mov.w	r2, #16777216	@ 0x1000000
 8012d50:	601a      	str	r2, [r3, #0]
	pxTopOfStack--;
 8012d52:	68fb      	ldr	r3, [r7, #12]
 8012d54:	3b04      	subs	r3, #4
 8012d56:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
 8012d58:	68bb      	ldr	r3, [r7, #8]
 8012d5a:	f023 0201 	bic.w	r2, r3, #1
 8012d5e:	68fb      	ldr	r3, [r7, #12]
 8012d60:	601a      	str	r2, [r3, #0]
	pxTopOfStack--;
 8012d62:	68fb      	ldr	r3, [r7, #12]
 8012d64:	3b04      	subs	r3, #4
 8012d66:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
 8012d68:	4a0c      	ldr	r2, [pc, #48]	@ (8012d9c <pxPortInitialiseStack+0x64>)
 8012d6a:	68fb      	ldr	r3, [r7, #12]
 8012d6c:	601a      	str	r2, [r3, #0]

	/* Save code space by skipping register initialisation. */
	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
 8012d6e:	68fb      	ldr	r3, [r7, #12]
 8012d70:	3b14      	subs	r3, #20
 8012d72:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
 8012d74:	687a      	ldr	r2, [r7, #4]
 8012d76:	68fb      	ldr	r3, [r7, #12]
 8012d78:	601a      	str	r2, [r3, #0]

	/* A save method is being used that requires each task to maintain its
	own exec return value. */
	pxTopOfStack--;
 8012d7a:	68fb      	ldr	r3, [r7, #12]
 8012d7c:	3b04      	subs	r3, #4
 8012d7e:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = portINITIAL_EXC_RETURN;
 8012d80:	68fb      	ldr	r3, [r7, #12]
 8012d82:	f06f 0202 	mvn.w	r2, #2
 8012d86:	601a      	str	r2, [r3, #0]

	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
 8012d88:	68fb      	ldr	r3, [r7, #12]
 8012d8a:	3b20      	subs	r3, #32
 8012d8c:	60fb      	str	r3, [r7, #12]

	return pxTopOfStack;
 8012d8e:	68fb      	ldr	r3, [r7, #12]
}
 8012d90:	4618      	mov	r0, r3
 8012d92:	3714      	adds	r7, #20
 8012d94:	46bd      	mov	sp, r7
 8012d96:	f85d 7b04 	ldr.w	r7, [sp], #4
 8012d9a:	4770      	bx	lr
 8012d9c:	08012da1 	.word	0x08012da1

08012da0 <prvTaskExitError>:
/*-----------------------------------------------------------*/

static void prvTaskExitError( void )
{
 8012da0:	b480      	push	{r7}
 8012da2:	b085      	sub	sp, #20
 8012da4:	af00      	add	r7, sp, #0
volatile uint32_t ulDummy = 0;
 8012da6:	2300      	movs	r3, #0
 8012da8:	607b      	str	r3, [r7, #4]
	its caller as there is nothing to return to.  If a task wants to exit it
	should instead call vTaskDelete( NULL ).

	Artificially force an assert() to be triggered if configASSERT() is
	defined, then stop here so application writers can catch the error. */
	configASSERT( uxCriticalNesting == ~0UL );
 8012daa:	4b13      	ldr	r3, [pc, #76]	@ (8012df8 <prvTaskExitError+0x58>)
 8012dac:	681b      	ldr	r3, [r3, #0]
 8012dae:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8012db2:	d00b      	beq.n	8012dcc <prvTaskExitError+0x2c>
	__asm volatile
 8012db4:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012db8:	f383 8811 	msr	BASEPRI, r3
 8012dbc:	f3bf 8f6f 	isb	sy
 8012dc0:	f3bf 8f4f 	dsb	sy
 8012dc4:	60fb      	str	r3, [r7, #12]
}
 8012dc6:	bf00      	nop
 8012dc8:	bf00      	nop
 8012dca:	e7fd      	b.n	8012dc8 <prvTaskExitError+0x28>
	__asm volatile
 8012dcc:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012dd0:	f383 8811 	msr	BASEPRI, r3
 8012dd4:	f3bf 8f6f 	isb	sy
 8012dd8:	f3bf 8f4f 	dsb	sy
 8012ddc:	60bb      	str	r3, [r7, #8]
}
 8012dde:	bf00      	nop
	portDISABLE_INTERRUPTS();
	while( ulDummy == 0 )
 8012de0:	bf00      	nop
 8012de2:	687b      	ldr	r3, [r7, #4]
 8012de4:	2b00      	cmp	r3, #0
 8012de6:	d0fc      	beq.n	8012de2 <prvTaskExitError+0x42>
		about code appearing after this function is called - making ulDummy
		volatile makes the compiler think the function could return and
		therefore not output an 'unreachable code' warning for code that appears
		after it. */
	}
}
 8012de8:	bf00      	nop
 8012dea:	bf00      	nop
 8012dec:	3714      	adds	r7, #20
 8012dee:	46bd      	mov	sp, r7
 8012df0:	f85d 7b04 	ldr.w	r7, [sp], #4
 8012df4:	4770      	bx	lr
 8012df6:	bf00      	nop
 8012df8:	24000044 	.word	0x24000044
 8012dfc:	00000000 	.word	0x00000000

08012e00 <SVC_Handler>:
/*-----------------------------------------------------------*/

void vPortSVCHandler( void )
{
	__asm volatile (
 8012e00:	4b07      	ldr	r3, [pc, #28]	@ (8012e20 <pxCurrentTCBConst2>)
 8012e02:	6819      	ldr	r1, [r3, #0]
 8012e04:	6808      	ldr	r0, [r1, #0]
 8012e06:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8012e0a:	f380 8809 	msr	PSP, r0
 8012e0e:	f3bf 8f6f 	isb	sy
 8012e12:	f04f 0000 	mov.w	r0, #0
 8012e16:	f380 8811 	msr	BASEPRI, r0
 8012e1a:	4770      	bx	lr
 8012e1c:	f3af 8000 	nop.w

08012e20 <pxCurrentTCBConst2>:
 8012e20:	240023f4 	.word	0x240023f4
					"	bx r14							\n"
					"									\n"
					"	.align 4						\n"
					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
				);
}
 8012e24:	bf00      	nop
 8012e26:	bf00      	nop

08012e28 <prvPortStartFirstTask>:
{
	/* Start the first task.  This also clears the bit that indicates the FPU is
	in use in case the FPU was used before the scheduler was started - which
	would otherwise result in the unnecessary leaving of space in the SVC stack
	for lazy saving of FPU registers. */
	__asm volatile(
 8012e28:	4808      	ldr	r0, [pc, #32]	@ (8012e4c <prvPortStartFirstTask+0x24>)
 8012e2a:	6800      	ldr	r0, [r0, #0]
 8012e2c:	6800      	ldr	r0, [r0, #0]
 8012e2e:	f380 8808 	msr	MSP, r0
 8012e32:	f04f 0000 	mov.w	r0, #0
 8012e36:	f380 8814 	msr	CONTROL, r0
 8012e3a:	b662      	cpsie	i
 8012e3c:	b661      	cpsie	f
 8012e3e:	f3bf 8f4f 	dsb	sy
 8012e42:	f3bf 8f6f 	isb	sy
 8012e46:	df00      	svc	0
 8012e48:	bf00      	nop
					" dsb					\n"
					" isb					\n"
					" svc 0					\n" /* System call to start first task. */
					" nop					\n"
				);
}
 8012e4a:	bf00      	nop
 8012e4c:	e000ed08 	.word	0xe000ed08

08012e50 <xPortStartScheduler>:

/*
 * See header file for description.
 */
BaseType_t xPortStartScheduler( void )
{
 8012e50:	b580      	push	{r7, lr}
 8012e52:	b086      	sub	sp, #24
 8012e54:	af00      	add	r7, sp, #0
	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );

	/* This port can be used on all revisions of the Cortex-M7 core other than
	the r0p1 parts.  r0p1 parts should use the port from the
	/source/portable/GCC/ARM_CM7/r0p1 directory. */
	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
 8012e56:	4b47      	ldr	r3, [pc, #284]	@ (8012f74 <xPortStartScheduler+0x124>)
 8012e58:	681b      	ldr	r3, [r3, #0]
 8012e5a:	4a47      	ldr	r2, [pc, #284]	@ (8012f78 <xPortStartScheduler+0x128>)
 8012e5c:	4293      	cmp	r3, r2
 8012e5e:	d10b      	bne.n	8012e78 <xPortStartScheduler+0x28>
	__asm volatile
 8012e60:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012e64:	f383 8811 	msr	BASEPRI, r3
 8012e68:	f3bf 8f6f 	isb	sy
 8012e6c:	f3bf 8f4f 	dsb	sy
 8012e70:	613b      	str	r3, [r7, #16]
}
 8012e72:	bf00      	nop
 8012e74:	bf00      	nop
 8012e76:	e7fd      	b.n	8012e74 <xPortStartScheduler+0x24>
	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
 8012e78:	4b3e      	ldr	r3, [pc, #248]	@ (8012f74 <xPortStartScheduler+0x124>)
 8012e7a:	681b      	ldr	r3, [r3, #0]
 8012e7c:	4a3f      	ldr	r2, [pc, #252]	@ (8012f7c <xPortStartScheduler+0x12c>)
 8012e7e:	4293      	cmp	r3, r2
 8012e80:	d10b      	bne.n	8012e9a <xPortStartScheduler+0x4a>
	__asm volatile
 8012e82:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012e86:	f383 8811 	msr	BASEPRI, r3
 8012e8a:	f3bf 8f6f 	isb	sy
 8012e8e:	f3bf 8f4f 	dsb	sy
 8012e92:	60fb      	str	r3, [r7, #12]
}
 8012e94:	bf00      	nop
 8012e96:	bf00      	nop
 8012e98:	e7fd      	b.n	8012e96 <xPortStartScheduler+0x46>

	#if( configASSERT_DEFINED == 1 )
	{
		volatile uint32_t ulOriginalPriority;
		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
 8012e9a:	4b39      	ldr	r3, [pc, #228]	@ (8012f80 <xPortStartScheduler+0x130>)
 8012e9c:	617b      	str	r3, [r7, #20]
		functions can be called.  ISR safe functions are those that end in
		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
		ensure interrupt entry is as fast and simple as possible.

		Save the interrupt priority value that is about to be clobbered. */
		ulOriginalPriority = *pucFirstUserPriorityRegister;
 8012e9e:	697b      	ldr	r3, [r7, #20]
 8012ea0:	781b      	ldrb	r3, [r3, #0]
 8012ea2:	b2db      	uxtb	r3, r3
 8012ea4:	607b      	str	r3, [r7, #4]

		/* Determine the number of priority bits available.  First write to all
		possible bits. */
		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
 8012ea6:	697b      	ldr	r3, [r7, #20]
 8012ea8:	22ff      	movs	r2, #255	@ 0xff
 8012eaa:	701a      	strb	r2, [r3, #0]

		/* Read the value back to see how many bits stuck. */
		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
 8012eac:	697b      	ldr	r3, [r7, #20]
 8012eae:	781b      	ldrb	r3, [r3, #0]
 8012eb0:	b2db      	uxtb	r3, r3
 8012eb2:	70fb      	strb	r3, [r7, #3]

		/* Use the same mask on the maximum system call priority. */
		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 8012eb4:	78fb      	ldrb	r3, [r7, #3]
 8012eb6:	b2db      	uxtb	r3, r3
 8012eb8:	f003 0350 	and.w	r3, r3, #80	@ 0x50
 8012ebc:	b2da      	uxtb	r2, r3
 8012ebe:	4b31      	ldr	r3, [pc, #196]	@ (8012f84 <xPortStartScheduler+0x134>)
 8012ec0:	701a      	strb	r2, [r3, #0]

		/* Calculate the maximum acceptable priority group value for the number
		of bits read back. */
		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
 8012ec2:	4b31      	ldr	r3, [pc, #196]	@ (8012f88 <xPortStartScheduler+0x138>)
 8012ec4:	2207      	movs	r2, #7
 8012ec6:	601a      	str	r2, [r3, #0]
		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
 8012ec8:	e009      	b.n	8012ede <xPortStartScheduler+0x8e>
		{
			ulMaxPRIGROUPValue--;
 8012eca:	4b2f      	ldr	r3, [pc, #188]	@ (8012f88 <xPortStartScheduler+0x138>)
 8012ecc:	681b      	ldr	r3, [r3, #0]
 8012ece:	3b01      	subs	r3, #1
 8012ed0:	4a2d      	ldr	r2, [pc, #180]	@ (8012f88 <xPortStartScheduler+0x138>)
 8012ed2:	6013      	str	r3, [r2, #0]
			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
 8012ed4:	78fb      	ldrb	r3, [r7, #3]
 8012ed6:	b2db      	uxtb	r3, r3
 8012ed8:	005b      	lsls	r3, r3, #1
 8012eda:	b2db      	uxtb	r3, r3
 8012edc:	70fb      	strb	r3, [r7, #3]
		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
 8012ede:	78fb      	ldrb	r3, [r7, #3]
 8012ee0:	b2db      	uxtb	r3, r3
 8012ee2:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8012ee6:	2b80      	cmp	r3, #128	@ 0x80
 8012ee8:	d0ef      	beq.n	8012eca <xPortStartScheduler+0x7a>
		#ifdef configPRIO_BITS
		{
			/* Check the FreeRTOS configuration that defines the number of
			priority bits matches the number of priority bits actually queried
			from the hardware. */
			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
 8012eea:	4b27      	ldr	r3, [pc, #156]	@ (8012f88 <xPortStartScheduler+0x138>)
 8012eec:	681b      	ldr	r3, [r3, #0]
 8012eee:	f1c3 0307 	rsb	r3, r3, #7
 8012ef2:	2b04      	cmp	r3, #4
 8012ef4:	d00b      	beq.n	8012f0e <xPortStartScheduler+0xbe>
	__asm volatile
 8012ef6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012efa:	f383 8811 	msr	BASEPRI, r3
 8012efe:	f3bf 8f6f 	isb	sy
 8012f02:	f3bf 8f4f 	dsb	sy
 8012f06:	60bb      	str	r3, [r7, #8]
}
 8012f08:	bf00      	nop
 8012f0a:	bf00      	nop
 8012f0c:	e7fd      	b.n	8012f0a <xPortStartScheduler+0xba>
		}
		#endif

		/* Shift the priority group value back to its position within the AIRCR
		register. */
		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
 8012f0e:	4b1e      	ldr	r3, [pc, #120]	@ (8012f88 <xPortStartScheduler+0x138>)
 8012f10:	681b      	ldr	r3, [r3, #0]
 8012f12:	021b      	lsls	r3, r3, #8
 8012f14:	4a1c      	ldr	r2, [pc, #112]	@ (8012f88 <xPortStartScheduler+0x138>)
 8012f16:	6013      	str	r3, [r2, #0]
		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
 8012f18:	4b1b      	ldr	r3, [pc, #108]	@ (8012f88 <xPortStartScheduler+0x138>)
 8012f1a:	681b      	ldr	r3, [r3, #0]
 8012f1c:	f403 63e0 	and.w	r3, r3, #1792	@ 0x700
 8012f20:	4a19      	ldr	r2, [pc, #100]	@ (8012f88 <xPortStartScheduler+0x138>)
 8012f22:	6013      	str	r3, [r2, #0]

		/* Restore the clobbered interrupt priority register to its original
		value. */
		*pucFirstUserPriorityRegister = ulOriginalPriority;
 8012f24:	687b      	ldr	r3, [r7, #4]
 8012f26:	b2da      	uxtb	r2, r3
 8012f28:	697b      	ldr	r3, [r7, #20]
 8012f2a:	701a      	strb	r2, [r3, #0]
	}
	#endif /* conifgASSERT_DEFINED */

	/* Make PendSV and SysTick the lowest priority interrupts. */
	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
 8012f2c:	4b17      	ldr	r3, [pc, #92]	@ (8012f8c <xPortStartScheduler+0x13c>)
 8012f2e:	681b      	ldr	r3, [r3, #0]
 8012f30:	4a16      	ldr	r2, [pc, #88]	@ (8012f8c <xPortStartScheduler+0x13c>)
 8012f32:	f443 0370 	orr.w	r3, r3, #15728640	@ 0xf00000
 8012f36:	6013      	str	r3, [r2, #0]
	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
 8012f38:	4b14      	ldr	r3, [pc, #80]	@ (8012f8c <xPortStartScheduler+0x13c>)
 8012f3a:	681b      	ldr	r3, [r3, #0]
 8012f3c:	4a13      	ldr	r2, [pc, #76]	@ (8012f8c <xPortStartScheduler+0x13c>)
 8012f3e:	f043 4370 	orr.w	r3, r3, #4026531840	@ 0xf0000000
 8012f42:	6013      	str	r3, [r2, #0]

	/* Start the timer that generates the tick ISR.  Interrupts are disabled
	here already. */
	vPortSetupTimerInterrupt();
 8012f44:	f000 f8da 	bl	80130fc <vPortSetupTimerInterrupt>

	/* Initialise the critical nesting count ready for the first task. */
	uxCriticalNesting = 0;
 8012f48:	4b11      	ldr	r3, [pc, #68]	@ (8012f90 <xPortStartScheduler+0x140>)
 8012f4a:	2200      	movs	r2, #0
 8012f4c:	601a      	str	r2, [r3, #0]

	/* Ensure the VFP is enabled - it should be anyway. */
	vPortEnableVFP();
 8012f4e:	f000 f8f9 	bl	8013144 <vPortEnableVFP>

	/* Lazy save always. */
	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
 8012f52:	4b10      	ldr	r3, [pc, #64]	@ (8012f94 <xPortStartScheduler+0x144>)
 8012f54:	681b      	ldr	r3, [r3, #0]
 8012f56:	4a0f      	ldr	r2, [pc, #60]	@ (8012f94 <xPortStartScheduler+0x144>)
 8012f58:	f043 4340 	orr.w	r3, r3, #3221225472	@ 0xc0000000
 8012f5c:	6013      	str	r3, [r2, #0]

	/* Start the first task. */
	prvPortStartFirstTask();
 8012f5e:	f7ff ff63 	bl	8012e28 <prvPortStartFirstTask>
	exit error function to prevent compiler warnings about a static function
	not being called in the case that the application writer overrides this
	functionality by defining configTASK_RETURN_ADDRESS.  Call
	vTaskSwitchContext() so link time optimisation does not remove the
	symbol. */
	vTaskSwitchContext();
 8012f62:	f7fe fcbb 	bl	80118dc <vTaskSwitchContext>
	prvTaskExitError();
 8012f66:	f7ff ff1b 	bl	8012da0 <prvTaskExitError>

	/* Should not get here! */
	return 0;
 8012f6a:	2300      	movs	r3, #0
}
 8012f6c:	4618      	mov	r0, r3
 8012f6e:	3718      	adds	r7, #24
 8012f70:	46bd      	mov	sp, r7
 8012f72:	bd80      	pop	{r7, pc}
 8012f74:	e000ed00 	.word	0xe000ed00
 8012f78:	410fc271 	.word	0x410fc271
 8012f7c:	410fc270 	.word	0x410fc270
 8012f80:	e000e400 	.word	0xe000e400
 8012f84:	24002a20 	.word	0x24002a20
 8012f88:	24002a24 	.word	0x24002a24
 8012f8c:	e000ed20 	.word	0xe000ed20
 8012f90:	24000044 	.word	0x24000044
 8012f94:	e000ef34 	.word	0xe000ef34

08012f98 <vPortEnterCritical>:
	configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/

void vPortEnterCritical( void )
{
 8012f98:	b480      	push	{r7}
 8012f9a:	b083      	sub	sp, #12
 8012f9c:	af00      	add	r7, sp, #0
	__asm volatile
 8012f9e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012fa2:	f383 8811 	msr	BASEPRI, r3
 8012fa6:	f3bf 8f6f 	isb	sy
 8012faa:	f3bf 8f4f 	dsb	sy
 8012fae:	607b      	str	r3, [r7, #4]
}
 8012fb0:	bf00      	nop
	portDISABLE_INTERRUPTS();
	uxCriticalNesting++;
 8012fb2:	4b10      	ldr	r3, [pc, #64]	@ (8012ff4 <vPortEnterCritical+0x5c>)
 8012fb4:	681b      	ldr	r3, [r3, #0]
 8012fb6:	3301      	adds	r3, #1
 8012fb8:	4a0e      	ldr	r2, [pc, #56]	@ (8012ff4 <vPortEnterCritical+0x5c>)
 8012fba:	6013      	str	r3, [r2, #0]
	/* This is not the interrupt safe version of the enter critical function so
	assert() if it is being called from an interrupt context.  Only API
	functions that end in "FromISR" can be used in an interrupt.  Only assert if
	the critical nesting count is 1 to protect against recursive calls if the
	assert function also uses a critical section. */
	if( uxCriticalNesting == 1 )
 8012fbc:	4b0d      	ldr	r3, [pc, #52]	@ (8012ff4 <vPortEnterCritical+0x5c>)
 8012fbe:	681b      	ldr	r3, [r3, #0]
 8012fc0:	2b01      	cmp	r3, #1
 8012fc2:	d110      	bne.n	8012fe6 <vPortEnterCritical+0x4e>
	{
		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
 8012fc4:	4b0c      	ldr	r3, [pc, #48]	@ (8012ff8 <vPortEnterCritical+0x60>)
 8012fc6:	681b      	ldr	r3, [r3, #0]
 8012fc8:	b2db      	uxtb	r3, r3
 8012fca:	2b00      	cmp	r3, #0
 8012fcc:	d00b      	beq.n	8012fe6 <vPortEnterCritical+0x4e>
	__asm volatile
 8012fce:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8012fd2:	f383 8811 	msr	BASEPRI, r3
 8012fd6:	f3bf 8f6f 	isb	sy
 8012fda:	f3bf 8f4f 	dsb	sy
 8012fde:	603b      	str	r3, [r7, #0]
}
 8012fe0:	bf00      	nop
 8012fe2:	bf00      	nop
 8012fe4:	e7fd      	b.n	8012fe2 <vPortEnterCritical+0x4a>
	}
}
 8012fe6:	bf00      	nop
 8012fe8:	370c      	adds	r7, #12
 8012fea:	46bd      	mov	sp, r7
 8012fec:	f85d 7b04 	ldr.w	r7, [sp], #4
 8012ff0:	4770      	bx	lr
 8012ff2:	bf00      	nop
 8012ff4:	24000044 	.word	0x24000044
 8012ff8:	e000ed04 	.word	0xe000ed04

08012ffc <vPortExitCritical>:
/*-----------------------------------------------------------*/

void vPortExitCritical( void )
{
 8012ffc:	b480      	push	{r7}
 8012ffe:	b083      	sub	sp, #12
 8013000:	af00      	add	r7, sp, #0
	configASSERT( uxCriticalNesting );
 8013002:	4b12      	ldr	r3, [pc, #72]	@ (801304c <vPortExitCritical+0x50>)
 8013004:	681b      	ldr	r3, [r3, #0]
 8013006:	2b00      	cmp	r3, #0
 8013008:	d10b      	bne.n	8013022 <vPortExitCritical+0x26>
	__asm volatile
 801300a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801300e:	f383 8811 	msr	BASEPRI, r3
 8013012:	f3bf 8f6f 	isb	sy
 8013016:	f3bf 8f4f 	dsb	sy
 801301a:	607b      	str	r3, [r7, #4]
}
 801301c:	bf00      	nop
 801301e:	bf00      	nop
 8013020:	e7fd      	b.n	801301e <vPortExitCritical+0x22>
	uxCriticalNesting--;
 8013022:	4b0a      	ldr	r3, [pc, #40]	@ (801304c <vPortExitCritical+0x50>)
 8013024:	681b      	ldr	r3, [r3, #0]
 8013026:	3b01      	subs	r3, #1
 8013028:	4a08      	ldr	r2, [pc, #32]	@ (801304c <vPortExitCritical+0x50>)
 801302a:	6013      	str	r3, [r2, #0]
	if( uxCriticalNesting == 0 )
 801302c:	4b07      	ldr	r3, [pc, #28]	@ (801304c <vPortExitCritical+0x50>)
 801302e:	681b      	ldr	r3, [r3, #0]
 8013030:	2b00      	cmp	r3, #0
 8013032:	d105      	bne.n	8013040 <vPortExitCritical+0x44>
 8013034:	2300      	movs	r3, #0
 8013036:	603b      	str	r3, [r7, #0]
	__asm volatile
 8013038:	683b      	ldr	r3, [r7, #0]
 801303a:	f383 8811 	msr	BASEPRI, r3
}
 801303e:	bf00      	nop
	{
		portENABLE_INTERRUPTS();
	}
}
 8013040:	bf00      	nop
 8013042:	370c      	adds	r7, #12
 8013044:	46bd      	mov	sp, r7
 8013046:	f85d 7b04 	ldr.w	r7, [sp], #4
 801304a:	4770      	bx	lr
 801304c:	24000044 	.word	0x24000044

08013050 <PendSV_Handler>:

void xPortPendSVHandler( void )
{
	/* This is a naked function. */

	__asm volatile
 8013050:	f3ef 8009 	mrs	r0, PSP
 8013054:	f3bf 8f6f 	isb	sy
 8013058:	4b15      	ldr	r3, [pc, #84]	@ (80130b0 <pxCurrentTCBConst>)
 801305a:	681a      	ldr	r2, [r3, #0]
 801305c:	f01e 0f10 	tst.w	lr, #16
 8013060:	bf08      	it	eq
 8013062:	ed20 8a10 	vstmdbeq	r0!, {s16-s31}
 8013066:	e920 4ff0 	stmdb	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 801306a:	6010      	str	r0, [r2, #0]
 801306c:	e92d 0009 	stmdb	sp!, {r0, r3}
 8013070:	f04f 0050 	mov.w	r0, #80	@ 0x50
 8013074:	f380 8811 	msr	BASEPRI, r0
 8013078:	f3bf 8f4f 	dsb	sy
 801307c:	f3bf 8f6f 	isb	sy
 8013080:	f7fe fc2c 	bl	80118dc <vTaskSwitchContext>
 8013084:	f04f 0000 	mov.w	r0, #0
 8013088:	f380 8811 	msr	BASEPRI, r0
 801308c:	bc09      	pop	{r0, r3}
 801308e:	6819      	ldr	r1, [r3, #0]
 8013090:	6808      	ldr	r0, [r1, #0]
 8013092:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8013096:	f01e 0f10 	tst.w	lr, #16
 801309a:	bf08      	it	eq
 801309c:	ecb0 8a10 	vldmiaeq	r0!, {s16-s31}
 80130a0:	f380 8809 	msr	PSP, r0
 80130a4:	f3bf 8f6f 	isb	sy
 80130a8:	4770      	bx	lr
 80130aa:	bf00      	nop
 80130ac:	f3af 8000 	nop.w

080130b0 <pxCurrentTCBConst>:
 80130b0:	240023f4 	.word	0x240023f4
	"										\n"
	"	.align 4							\n"
	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
	);
}
 80130b4:	bf00      	nop
 80130b6:	bf00      	nop

080130b8 <xPortSysTickHandler>:
/*-----------------------------------------------------------*/

void xPortSysTickHandler( void )
{
 80130b8:	b580      	push	{r7, lr}
 80130ba:	b082      	sub	sp, #8
 80130bc:	af00      	add	r7, sp, #0
	__asm volatile
 80130be:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80130c2:	f383 8811 	msr	BASEPRI, r3
 80130c6:	f3bf 8f6f 	isb	sy
 80130ca:	f3bf 8f4f 	dsb	sy
 80130ce:	607b      	str	r3, [r7, #4]
}
 80130d0:	bf00      	nop
	save and then restore the interrupt mask value as its value is already
	known. */
	portDISABLE_INTERRUPTS();
	{
		/* Increment the RTOS tick. */
		if( xTaskIncrementTick() != pdFALSE )
 80130d2:	f7fe fb49 	bl	8011768 <xTaskIncrementTick>
 80130d6:	4603      	mov	r3, r0
 80130d8:	2b00      	cmp	r3, #0
 80130da:	d003      	beq.n	80130e4 <xPortSysTickHandler+0x2c>
		{
			/* A context switch is required.  Context switching is performed in
			the PendSV interrupt.  Pend the PendSV interrupt. */
			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
 80130dc:	4b06      	ldr	r3, [pc, #24]	@ (80130f8 <xPortSysTickHandler+0x40>)
 80130de:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80130e2:	601a      	str	r2, [r3, #0]
 80130e4:	2300      	movs	r3, #0
 80130e6:	603b      	str	r3, [r7, #0]
	__asm volatile
 80130e8:	683b      	ldr	r3, [r7, #0]
 80130ea:	f383 8811 	msr	BASEPRI, r3
}
 80130ee:	bf00      	nop
		}
	}
	portENABLE_INTERRUPTS();
}
 80130f0:	bf00      	nop
 80130f2:	3708      	adds	r7, #8
 80130f4:	46bd      	mov	sp, r7
 80130f6:	bd80      	pop	{r7, pc}
 80130f8:	e000ed04 	.word	0xe000ed04

080130fc <vPortSetupTimerInterrupt>:
/*
 * Setup the systick timer to generate the tick interrupts at the required
 * frequency.
 */
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
 80130fc:	b480      	push	{r7}
 80130fe:	af00      	add	r7, sp, #0
		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
	}
	#endif /* configUSE_TICKLESS_IDLE */

	/* Stop and clear the SysTick. */
	portNVIC_SYSTICK_CTRL_REG = 0UL;
 8013100:	4b0b      	ldr	r3, [pc, #44]	@ (8013130 <vPortSetupTimerInterrupt+0x34>)
 8013102:	2200      	movs	r2, #0
 8013104:	601a      	str	r2, [r3, #0]
	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 8013106:	4b0b      	ldr	r3, [pc, #44]	@ (8013134 <vPortSetupTimerInterrupt+0x38>)
 8013108:	2200      	movs	r2, #0
 801310a:	601a      	str	r2, [r3, #0]

	/* Configure SysTick to interrupt at the requested rate. */
	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
 801310c:	4b0a      	ldr	r3, [pc, #40]	@ (8013138 <vPortSetupTimerInterrupt+0x3c>)
 801310e:	681b      	ldr	r3, [r3, #0]
 8013110:	4a0a      	ldr	r2, [pc, #40]	@ (801313c <vPortSetupTimerInterrupt+0x40>)
 8013112:	fba2 2303 	umull	r2, r3, r2, r3
 8013116:	099b      	lsrs	r3, r3, #6
 8013118:	4a09      	ldr	r2, [pc, #36]	@ (8013140 <vPortSetupTimerInterrupt+0x44>)
 801311a:	3b01      	subs	r3, #1
 801311c:	6013      	str	r3, [r2, #0]
	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
 801311e:	4b04      	ldr	r3, [pc, #16]	@ (8013130 <vPortSetupTimerInterrupt+0x34>)
 8013120:	2207      	movs	r2, #7
 8013122:	601a      	str	r2, [r3, #0]
}
 8013124:	bf00      	nop
 8013126:	46bd      	mov	sp, r7
 8013128:	f85d 7b04 	ldr.w	r7, [sp], #4
 801312c:	4770      	bx	lr
 801312e:	bf00      	nop
 8013130:	e000e010 	.word	0xe000e010
 8013134:	e000e018 	.word	0xe000e018
 8013138:	24000034 	.word	0x24000034
 801313c:	10624dd3 	.word	0x10624dd3
 8013140:	e000e014 	.word	0xe000e014

08013144 <vPortEnableVFP>:
/*-----------------------------------------------------------*/

/* This is a naked function. */
static void vPortEnableVFP( void )
{
	__asm volatile
 8013144:	f8df 000c 	ldr.w	r0, [pc, #12]	@ 8013154 <vPortEnableVFP+0x10>
 8013148:	6801      	ldr	r1, [r0, #0]
 801314a:	f441 0170 	orr.w	r1, r1, #15728640	@ 0xf00000
 801314e:	6001      	str	r1, [r0, #0]
 8013150:	4770      	bx	lr
		"								\n"
		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
		"	str r1, [r0]				\n"
		"	bx r14						"
	);
}
 8013152:	bf00      	nop
 8013154:	e000ed88 	.word	0xe000ed88

08013158 <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/

#if( configASSERT_DEFINED == 1 )

	void vPortValidateInterruptPriority( void )
	{
 8013158:	b480      	push	{r7}
 801315a:	b085      	sub	sp, #20
 801315c:	af00      	add	r7, sp, #0
	uint32_t ulCurrentInterrupt;
	uint8_t ucCurrentPriority;

		/* Obtain the number of the currently executing interrupt. */
		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
 801315e:	f3ef 8305 	mrs	r3, IPSR
 8013162:	60fb      	str	r3, [r7, #12]

		/* Is the interrupt number a user defined interrupt? */
		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
 8013164:	68fb      	ldr	r3, [r7, #12]
 8013166:	2b0f      	cmp	r3, #15
 8013168:	d915      	bls.n	8013196 <vPortValidateInterruptPriority+0x3e>
		{
			/* Look up the interrupt's priority. */
			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
 801316a:	4a18      	ldr	r2, [pc, #96]	@ (80131cc <vPortValidateInterruptPriority+0x74>)
 801316c:	68fb      	ldr	r3, [r7, #12]
 801316e:	4413      	add	r3, r2
 8013170:	781b      	ldrb	r3, [r3, #0]
 8013172:	72fb      	strb	r3, [r7, #11]
			interrupt entry is as fast and simple as possible.

			The following links provide detailed information:
			http://www.freertos.org/RTOS-Cortex-M3-M4.html
			http://www.freertos.org/FAQHelp.html */
			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
 8013174:	4b16      	ldr	r3, [pc, #88]	@ (80131d0 <vPortValidateInterruptPriority+0x78>)
 8013176:	781b      	ldrb	r3, [r3, #0]
 8013178:	7afa      	ldrb	r2, [r7, #11]
 801317a:	429a      	cmp	r2, r3
 801317c:	d20b      	bcs.n	8013196 <vPortValidateInterruptPriority+0x3e>
	__asm volatile
 801317e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8013182:	f383 8811 	msr	BASEPRI, r3
 8013186:	f3bf 8f6f 	isb	sy
 801318a:	f3bf 8f4f 	dsb	sy
 801318e:	607b      	str	r3, [r7, #4]
}
 8013190:	bf00      	nop
 8013192:	bf00      	nop
 8013194:	e7fd      	b.n	8013192 <vPortValidateInterruptPriority+0x3a>
		configuration then the correct setting can be achieved on all Cortex-M
		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
		scheduler.  Note however that some vendor specific peripheral libraries
		assume a non-zero priority group setting, in which cases using a value
		of zero will result in unpredictable behaviour. */
		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
 8013196:	4b0f      	ldr	r3, [pc, #60]	@ (80131d4 <vPortValidateInterruptPriority+0x7c>)
 8013198:	681b      	ldr	r3, [r3, #0]
 801319a:	f403 62e0 	and.w	r2, r3, #1792	@ 0x700
 801319e:	4b0e      	ldr	r3, [pc, #56]	@ (80131d8 <vPortValidateInterruptPriority+0x80>)
 80131a0:	681b      	ldr	r3, [r3, #0]
 80131a2:	429a      	cmp	r2, r3
 80131a4:	d90b      	bls.n	80131be <vPortValidateInterruptPriority+0x66>
	__asm volatile
 80131a6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80131aa:	f383 8811 	msr	BASEPRI, r3
 80131ae:	f3bf 8f6f 	isb	sy
 80131b2:	f3bf 8f4f 	dsb	sy
 80131b6:	603b      	str	r3, [r7, #0]
}
 80131b8:	bf00      	nop
 80131ba:	bf00      	nop
 80131bc:	e7fd      	b.n	80131ba <vPortValidateInterruptPriority+0x62>
	}
 80131be:	bf00      	nop
 80131c0:	3714      	adds	r7, #20
 80131c2:	46bd      	mov	sp, r7
 80131c4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80131c8:	4770      	bx	lr
 80131ca:	bf00      	nop
 80131cc:	e000e3f0 	.word	0xe000e3f0
 80131d0:	24002a20 	.word	0x24002a20
 80131d4:	e000ed0c 	.word	0xe000ed0c
 80131d8:	24002a24 	.word	0x24002a24

080131dc <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;

/*-----------------------------------------------------------*/

void *pvPortMalloc( size_t xWantedSize )
{
 80131dc:	b580      	push	{r7, lr}
 80131de:	b08a      	sub	sp, #40	@ 0x28
 80131e0:	af00      	add	r7, sp, #0
 80131e2:	6078      	str	r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
 80131e4:	2300      	movs	r3, #0
 80131e6:	61fb      	str	r3, [r7, #28]

	vTaskSuspendAll();
 80131e8:	f7fe fa02 	bl	80115f0 <vTaskSuspendAll>
	{
		/* If this is the first call to malloc then the heap will require
		initialisation to setup the list of free blocks. */
		if( pxEnd == NULL )
 80131ec:	4b5c      	ldr	r3, [pc, #368]	@ (8013360 <pvPortMalloc+0x184>)
 80131ee:	681b      	ldr	r3, [r3, #0]
 80131f0:	2b00      	cmp	r3, #0
 80131f2:	d101      	bne.n	80131f8 <pvPortMalloc+0x1c>
		{
			prvHeapInit();
 80131f4:	f000 f924 	bl	8013440 <prvHeapInit>

		/* Check the requested block size is not so large that the top bit is
		set.  The top bit of the block size member of the BlockLink_t structure
		is used to determine who owns the block - the application or the
		kernel, so it must be free. */
		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
 80131f8:	4b5a      	ldr	r3, [pc, #360]	@ (8013364 <pvPortMalloc+0x188>)
 80131fa:	681a      	ldr	r2, [r3, #0]
 80131fc:	687b      	ldr	r3, [r7, #4]
 80131fe:	4013      	ands	r3, r2
 8013200:	2b00      	cmp	r3, #0
 8013202:	f040 8095 	bne.w	8013330 <pvPortMalloc+0x154>
		{
			/* The wanted size is increased so it can contain a BlockLink_t
			structure in addition to the requested amount of bytes. */
			if( xWantedSize > 0 )
 8013206:	687b      	ldr	r3, [r7, #4]
 8013208:	2b00      	cmp	r3, #0
 801320a:	d01e      	beq.n	801324a <pvPortMalloc+0x6e>
			{
				xWantedSize += xHeapStructSize;
 801320c:	2208      	movs	r2, #8
 801320e:	687b      	ldr	r3, [r7, #4]
 8013210:	4413      	add	r3, r2
 8013212:	607b      	str	r3, [r7, #4]

				/* Ensure that blocks are always aligned to the required number
				of bytes. */
				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
 8013214:	687b      	ldr	r3, [r7, #4]
 8013216:	f003 0307 	and.w	r3, r3, #7
 801321a:	2b00      	cmp	r3, #0
 801321c:	d015      	beq.n	801324a <pvPortMalloc+0x6e>
				{
					/* Byte alignment required. */
					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
 801321e:	687b      	ldr	r3, [r7, #4]
 8013220:	f023 0307 	bic.w	r3, r3, #7
 8013224:	3308      	adds	r3, #8
 8013226:	607b      	str	r3, [r7, #4]
					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
 8013228:	687b      	ldr	r3, [r7, #4]
 801322a:	f003 0307 	and.w	r3, r3, #7
 801322e:	2b00      	cmp	r3, #0
 8013230:	d00b      	beq.n	801324a <pvPortMalloc+0x6e>
	__asm volatile
 8013232:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8013236:	f383 8811 	msr	BASEPRI, r3
 801323a:	f3bf 8f6f 	isb	sy
 801323e:	f3bf 8f4f 	dsb	sy
 8013242:	617b      	str	r3, [r7, #20]
}
 8013244:	bf00      	nop
 8013246:	bf00      	nop
 8013248:	e7fd      	b.n	8013246 <pvPortMalloc+0x6a>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}

			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
 801324a:	687b      	ldr	r3, [r7, #4]
 801324c:	2b00      	cmp	r3, #0
 801324e:	d06f      	beq.n	8013330 <pvPortMalloc+0x154>
 8013250:	4b45      	ldr	r3, [pc, #276]	@ (8013368 <pvPortMalloc+0x18c>)
 8013252:	681b      	ldr	r3, [r3, #0]
 8013254:	687a      	ldr	r2, [r7, #4]
 8013256:	429a      	cmp	r2, r3
 8013258:	d86a      	bhi.n	8013330 <pvPortMalloc+0x154>
			{
				/* Traverse the list from the start	(lowest address) block until
				one	of adequate size is found. */
				pxPreviousBlock = &xStart;
 801325a:	4b44      	ldr	r3, [pc, #272]	@ (801336c <pvPortMalloc+0x190>)
 801325c:	623b      	str	r3, [r7, #32]
				pxBlock = xStart.pxNextFreeBlock;
 801325e:	4b43      	ldr	r3, [pc, #268]	@ (801336c <pvPortMalloc+0x190>)
 8013260:	681b      	ldr	r3, [r3, #0]
 8013262:	627b      	str	r3, [r7, #36]	@ 0x24
				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
 8013264:	e004      	b.n	8013270 <pvPortMalloc+0x94>
				{
					pxPreviousBlock = pxBlock;
 8013266:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8013268:	623b      	str	r3, [r7, #32]
					pxBlock = pxBlock->pxNextFreeBlock;
 801326a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 801326c:	681b      	ldr	r3, [r3, #0]
 801326e:	627b      	str	r3, [r7, #36]	@ 0x24
				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
 8013270:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8013272:	685b      	ldr	r3, [r3, #4]
 8013274:	687a      	ldr	r2, [r7, #4]
 8013276:	429a      	cmp	r2, r3
 8013278:	d903      	bls.n	8013282 <pvPortMalloc+0xa6>
 801327a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 801327c:	681b      	ldr	r3, [r3, #0]
 801327e:	2b00      	cmp	r3, #0
 8013280:	d1f1      	bne.n	8013266 <pvPortMalloc+0x8a>
				}

				/* If the end marker was reached then a block of adequate size
				was	not found. */
				if( pxBlock != pxEnd )
 8013282:	4b37      	ldr	r3, [pc, #220]	@ (8013360 <pvPortMalloc+0x184>)
 8013284:	681b      	ldr	r3, [r3, #0]
 8013286:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8013288:	429a      	cmp	r2, r3
 801328a:	d051      	beq.n	8013330 <pvPortMalloc+0x154>
				{
					/* Return the memory space pointed to - jumping over the
					BlockLink_t structure at its start. */
					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
 801328c:	6a3b      	ldr	r3, [r7, #32]
 801328e:	681b      	ldr	r3, [r3, #0]
 8013290:	2208      	movs	r2, #8
 8013292:	4413      	add	r3, r2
 8013294:	61fb      	str	r3, [r7, #28]

					/* This block is being returned for use so must be taken out
					of the list of free blocks. */
					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
 8013296:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8013298:	681a      	ldr	r2, [r3, #0]
 801329a:	6a3b      	ldr	r3, [r7, #32]
 801329c:	601a      	str	r2, [r3, #0]

					/* If the block is larger than required it can be split into
					two. */
					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
 801329e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80132a0:	685a      	ldr	r2, [r3, #4]
 80132a2:	687b      	ldr	r3, [r7, #4]
 80132a4:	1ad2      	subs	r2, r2, r3
 80132a6:	2308      	movs	r3, #8
 80132a8:	005b      	lsls	r3, r3, #1
 80132aa:	429a      	cmp	r2, r3
 80132ac:	d920      	bls.n	80132f0 <pvPortMalloc+0x114>
					{
						/* This block is to be split into two.  Create a new
						block following the number of bytes requested. The void
						cast is used to prevent byte alignment warnings from the
						compiler. */
						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
 80132ae:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 80132b0:	687b      	ldr	r3, [r7, #4]
 80132b2:	4413      	add	r3, r2
 80132b4:	61bb      	str	r3, [r7, #24]
						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
 80132b6:	69bb      	ldr	r3, [r7, #24]
 80132b8:	f003 0307 	and.w	r3, r3, #7
 80132bc:	2b00      	cmp	r3, #0
 80132be:	d00b      	beq.n	80132d8 <pvPortMalloc+0xfc>
	__asm volatile
 80132c0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80132c4:	f383 8811 	msr	BASEPRI, r3
 80132c8:	f3bf 8f6f 	isb	sy
 80132cc:	f3bf 8f4f 	dsb	sy
 80132d0:	613b      	str	r3, [r7, #16]
}
 80132d2:	bf00      	nop
 80132d4:	bf00      	nop
 80132d6:	e7fd      	b.n	80132d4 <pvPortMalloc+0xf8>

						/* Calculate the sizes of two blocks split from the
						single block. */
						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
 80132d8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80132da:	685a      	ldr	r2, [r3, #4]
 80132dc:	687b      	ldr	r3, [r7, #4]
 80132de:	1ad2      	subs	r2, r2, r3
 80132e0:	69bb      	ldr	r3, [r7, #24]
 80132e2:	605a      	str	r2, [r3, #4]
						pxBlock->xBlockSize = xWantedSize;
 80132e4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80132e6:	687a      	ldr	r2, [r7, #4]
 80132e8:	605a      	str	r2, [r3, #4]

						/* Insert the new block into the list of free blocks. */
						prvInsertBlockIntoFreeList( pxNewBlockLink );
 80132ea:	69b8      	ldr	r0, [r7, #24]
 80132ec:	f000 f90a 	bl	8013504 <prvInsertBlockIntoFreeList>
					else
					{
						mtCOVERAGE_TEST_MARKER();
					}

					xFreeBytesRemaining -= pxBlock->xBlockSize;
 80132f0:	4b1d      	ldr	r3, [pc, #116]	@ (8013368 <pvPortMalloc+0x18c>)
 80132f2:	681a      	ldr	r2, [r3, #0]
 80132f4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80132f6:	685b      	ldr	r3, [r3, #4]
 80132f8:	1ad3      	subs	r3, r2, r3
 80132fa:	4a1b      	ldr	r2, [pc, #108]	@ (8013368 <pvPortMalloc+0x18c>)
 80132fc:	6013      	str	r3, [r2, #0]

					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
 80132fe:	4b1a      	ldr	r3, [pc, #104]	@ (8013368 <pvPortMalloc+0x18c>)
 8013300:	681a      	ldr	r2, [r3, #0]
 8013302:	4b1b      	ldr	r3, [pc, #108]	@ (8013370 <pvPortMalloc+0x194>)
 8013304:	681b      	ldr	r3, [r3, #0]
 8013306:	429a      	cmp	r2, r3
 8013308:	d203      	bcs.n	8013312 <pvPortMalloc+0x136>
					{
						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
 801330a:	4b17      	ldr	r3, [pc, #92]	@ (8013368 <pvPortMalloc+0x18c>)
 801330c:	681b      	ldr	r3, [r3, #0]
 801330e:	4a18      	ldr	r2, [pc, #96]	@ (8013370 <pvPortMalloc+0x194>)
 8013310:	6013      	str	r3, [r2, #0]
						mtCOVERAGE_TEST_MARKER();
					}

					/* The block is being returned - it is allocated and owned
					by the application and has no "next" block. */
					pxBlock->xBlockSize |= xBlockAllocatedBit;
 8013312:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8013314:	685a      	ldr	r2, [r3, #4]
 8013316:	4b13      	ldr	r3, [pc, #76]	@ (8013364 <pvPortMalloc+0x188>)
 8013318:	681b      	ldr	r3, [r3, #0]
 801331a:	431a      	orrs	r2, r3
 801331c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 801331e:	605a      	str	r2, [r3, #4]
					pxBlock->pxNextFreeBlock = NULL;
 8013320:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8013322:	2200      	movs	r2, #0
 8013324:	601a      	str	r2, [r3, #0]
					xNumberOfSuccessfulAllocations++;
 8013326:	4b13      	ldr	r3, [pc, #76]	@ (8013374 <pvPortMalloc+0x198>)
 8013328:	681b      	ldr	r3, [r3, #0]
 801332a:	3301      	adds	r3, #1
 801332c:	4a11      	ldr	r2, [pc, #68]	@ (8013374 <pvPortMalloc+0x198>)
 801332e:	6013      	str	r3, [r2, #0]
			mtCOVERAGE_TEST_MARKER();
		}

		traceMALLOC( pvReturn, xWantedSize );
	}
	( void ) xTaskResumeAll();
 8013330:	f7fe f96c 	bl	801160c <xTaskResumeAll>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	#endif

	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
 8013334:	69fb      	ldr	r3, [r7, #28]
 8013336:	f003 0307 	and.w	r3, r3, #7
 801333a:	2b00      	cmp	r3, #0
 801333c:	d00b      	beq.n	8013356 <pvPortMalloc+0x17a>
	__asm volatile
 801333e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8013342:	f383 8811 	msr	BASEPRI, r3
 8013346:	f3bf 8f6f 	isb	sy
 801334a:	f3bf 8f4f 	dsb	sy
 801334e:	60fb      	str	r3, [r7, #12]
}
 8013350:	bf00      	nop
 8013352:	bf00      	nop
 8013354:	e7fd      	b.n	8013352 <pvPortMalloc+0x176>
	return pvReturn;
 8013356:	69fb      	ldr	r3, [r7, #28]
}
 8013358:	4618      	mov	r0, r3
 801335a:	3728      	adds	r7, #40	@ 0x28
 801335c:	46bd      	mov	sp, r7
 801335e:	bd80      	pop	{r7, pc}
 8013360:	24012a30 	.word	0x24012a30
 8013364:	24012a44 	.word	0x24012a44
 8013368:	24012a34 	.word	0x24012a34
 801336c:	24012a28 	.word	0x24012a28
 8013370:	24012a38 	.word	0x24012a38
 8013374:	24012a3c 	.word	0x24012a3c

08013378 <vPortFree>:
/*-----------------------------------------------------------*/

void vPortFree( void *pv )
{
 8013378:	b580      	push	{r7, lr}
 801337a:	b086      	sub	sp, #24
 801337c:	af00      	add	r7, sp, #0
 801337e:	6078      	str	r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
 8013380:	687b      	ldr	r3, [r7, #4]
 8013382:	617b      	str	r3, [r7, #20]
BlockLink_t *pxLink;

	if( pv != NULL )
 8013384:	687b      	ldr	r3, [r7, #4]
 8013386:	2b00      	cmp	r3, #0
 8013388:	d04f      	beq.n	801342a <vPortFree+0xb2>
	{
		/* The memory being freed will have an BlockLink_t structure immediately
		before it. */
		puc -= xHeapStructSize;
 801338a:	2308      	movs	r3, #8
 801338c:	425b      	negs	r3, r3
 801338e:	697a      	ldr	r2, [r7, #20]
 8013390:	4413      	add	r3, r2
 8013392:	617b      	str	r3, [r7, #20]

		/* This casting is to keep the compiler from issuing warnings. */
		pxLink = ( void * ) puc;
 8013394:	697b      	ldr	r3, [r7, #20]
 8013396:	613b      	str	r3, [r7, #16]

		/* Check the block is actually allocated. */
		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
 8013398:	693b      	ldr	r3, [r7, #16]
 801339a:	685a      	ldr	r2, [r3, #4]
 801339c:	4b25      	ldr	r3, [pc, #148]	@ (8013434 <vPortFree+0xbc>)
 801339e:	681b      	ldr	r3, [r3, #0]
 80133a0:	4013      	ands	r3, r2
 80133a2:	2b00      	cmp	r3, #0
 80133a4:	d10b      	bne.n	80133be <vPortFree+0x46>
	__asm volatile
 80133a6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80133aa:	f383 8811 	msr	BASEPRI, r3
 80133ae:	f3bf 8f6f 	isb	sy
 80133b2:	f3bf 8f4f 	dsb	sy
 80133b6:	60fb      	str	r3, [r7, #12]
}
 80133b8:	bf00      	nop
 80133ba:	bf00      	nop
 80133bc:	e7fd      	b.n	80133ba <vPortFree+0x42>
		configASSERT( pxLink->pxNextFreeBlock == NULL );
 80133be:	693b      	ldr	r3, [r7, #16]
 80133c0:	681b      	ldr	r3, [r3, #0]
 80133c2:	2b00      	cmp	r3, #0
 80133c4:	d00b      	beq.n	80133de <vPortFree+0x66>
	__asm volatile
 80133c6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80133ca:	f383 8811 	msr	BASEPRI, r3
 80133ce:	f3bf 8f6f 	isb	sy
 80133d2:	f3bf 8f4f 	dsb	sy
 80133d6:	60bb      	str	r3, [r7, #8]
}
 80133d8:	bf00      	nop
 80133da:	bf00      	nop
 80133dc:	e7fd      	b.n	80133da <vPortFree+0x62>

		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
 80133de:	693b      	ldr	r3, [r7, #16]
 80133e0:	685a      	ldr	r2, [r3, #4]
 80133e2:	4b14      	ldr	r3, [pc, #80]	@ (8013434 <vPortFree+0xbc>)
 80133e4:	681b      	ldr	r3, [r3, #0]
 80133e6:	4013      	ands	r3, r2
 80133e8:	2b00      	cmp	r3, #0
 80133ea:	d01e      	beq.n	801342a <vPortFree+0xb2>
		{
			if( pxLink->pxNextFreeBlock == NULL )
 80133ec:	693b      	ldr	r3, [r7, #16]
 80133ee:	681b      	ldr	r3, [r3, #0]
 80133f0:	2b00      	cmp	r3, #0
 80133f2:	d11a      	bne.n	801342a <vPortFree+0xb2>
			{
				/* The block is being returned to the heap - it is no longer
				allocated. */
				pxLink->xBlockSize &= ~xBlockAllocatedBit;
 80133f4:	693b      	ldr	r3, [r7, #16]
 80133f6:	685a      	ldr	r2, [r3, #4]
 80133f8:	4b0e      	ldr	r3, [pc, #56]	@ (8013434 <vPortFree+0xbc>)
 80133fa:	681b      	ldr	r3, [r3, #0]
 80133fc:	43db      	mvns	r3, r3
 80133fe:	401a      	ands	r2, r3
 8013400:	693b      	ldr	r3, [r7, #16]
 8013402:	605a      	str	r2, [r3, #4]

				vTaskSuspendAll();
 8013404:	f7fe f8f4 	bl	80115f0 <vTaskSuspendAll>
				{
					/* Add this block to the list of free blocks. */
					xFreeBytesRemaining += pxLink->xBlockSize;
 8013408:	693b      	ldr	r3, [r7, #16]
 801340a:	685a      	ldr	r2, [r3, #4]
 801340c:	4b0a      	ldr	r3, [pc, #40]	@ (8013438 <vPortFree+0xc0>)
 801340e:	681b      	ldr	r3, [r3, #0]
 8013410:	4413      	add	r3, r2
 8013412:	4a09      	ldr	r2, [pc, #36]	@ (8013438 <vPortFree+0xc0>)
 8013414:	6013      	str	r3, [r2, #0]
					traceFREE( pv, pxLink->xBlockSize );
					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
 8013416:	6938      	ldr	r0, [r7, #16]
 8013418:	f000 f874 	bl	8013504 <prvInsertBlockIntoFreeList>
					xNumberOfSuccessfulFrees++;
 801341c:	4b07      	ldr	r3, [pc, #28]	@ (801343c <vPortFree+0xc4>)
 801341e:	681b      	ldr	r3, [r3, #0]
 8013420:	3301      	adds	r3, #1
 8013422:	4a06      	ldr	r2, [pc, #24]	@ (801343c <vPortFree+0xc4>)
 8013424:	6013      	str	r3, [r2, #0]
				}
				( void ) xTaskResumeAll();
 8013426:	f7fe f8f1 	bl	801160c <xTaskResumeAll>
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
}
 801342a:	bf00      	nop
 801342c:	3718      	adds	r7, #24
 801342e:	46bd      	mov	sp, r7
 8013430:	bd80      	pop	{r7, pc}
 8013432:	bf00      	nop
 8013434:	24012a44 	.word	0x24012a44
 8013438:	24012a34 	.word	0x24012a34
 801343c:	24012a40 	.word	0x24012a40

08013440 <prvHeapInit>:
	/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/

static void prvHeapInit( void )
{
 8013440:	b480      	push	{r7}
 8013442:	b085      	sub	sp, #20
 8013444:	af00      	add	r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
 8013446:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
 801344a:	60bb      	str	r3, [r7, #8]

	/* Ensure the heap starts on a correctly aligned boundary. */
	uxAddress = ( size_t ) ucHeap;
 801344c:	4b27      	ldr	r3, [pc, #156]	@ (80134ec <prvHeapInit+0xac>)
 801344e:	60fb      	str	r3, [r7, #12]

	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
 8013450:	68fb      	ldr	r3, [r7, #12]
 8013452:	f003 0307 	and.w	r3, r3, #7
 8013456:	2b00      	cmp	r3, #0
 8013458:	d00c      	beq.n	8013474 <prvHeapInit+0x34>
	{
		uxAddress += ( portBYTE_ALIGNMENT - 1 );
 801345a:	68fb      	ldr	r3, [r7, #12]
 801345c:	3307      	adds	r3, #7
 801345e:	60fb      	str	r3, [r7, #12]
		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
 8013460:	68fb      	ldr	r3, [r7, #12]
 8013462:	f023 0307 	bic.w	r3, r3, #7
 8013466:	60fb      	str	r3, [r7, #12]
		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
 8013468:	68ba      	ldr	r2, [r7, #8]
 801346a:	68fb      	ldr	r3, [r7, #12]
 801346c:	1ad3      	subs	r3, r2, r3
 801346e:	4a1f      	ldr	r2, [pc, #124]	@ (80134ec <prvHeapInit+0xac>)
 8013470:	4413      	add	r3, r2
 8013472:	60bb      	str	r3, [r7, #8]
	}

	pucAlignedHeap = ( uint8_t * ) uxAddress;
 8013474:	68fb      	ldr	r3, [r7, #12]
 8013476:	607b      	str	r3, [r7, #4]

	/* xStart is used to hold a pointer to the first item in the list of free
	blocks.  The void cast is used to prevent compiler warnings. */
	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
 8013478:	4a1d      	ldr	r2, [pc, #116]	@ (80134f0 <prvHeapInit+0xb0>)
 801347a:	687b      	ldr	r3, [r7, #4]
 801347c:	6013      	str	r3, [r2, #0]
	xStart.xBlockSize = ( size_t ) 0;
 801347e:	4b1c      	ldr	r3, [pc, #112]	@ (80134f0 <prvHeapInit+0xb0>)
 8013480:	2200      	movs	r2, #0
 8013482:	605a      	str	r2, [r3, #4]

	/* pxEnd is used to mark the end of the list of free blocks and is inserted
	at the end of the heap space. */
	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
 8013484:	687b      	ldr	r3, [r7, #4]
 8013486:	68ba      	ldr	r2, [r7, #8]
 8013488:	4413      	add	r3, r2
 801348a:	60fb      	str	r3, [r7, #12]
	uxAddress -= xHeapStructSize;
 801348c:	2208      	movs	r2, #8
 801348e:	68fb      	ldr	r3, [r7, #12]
 8013490:	1a9b      	subs	r3, r3, r2
 8013492:	60fb      	str	r3, [r7, #12]
	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
 8013494:	68fb      	ldr	r3, [r7, #12]
 8013496:	f023 0307 	bic.w	r3, r3, #7
 801349a:	60fb      	str	r3, [r7, #12]
	pxEnd = ( void * ) uxAddress;
 801349c:	68fb      	ldr	r3, [r7, #12]
 801349e:	4a15      	ldr	r2, [pc, #84]	@ (80134f4 <prvHeapInit+0xb4>)
 80134a0:	6013      	str	r3, [r2, #0]
	pxEnd->xBlockSize = 0;
 80134a2:	4b14      	ldr	r3, [pc, #80]	@ (80134f4 <prvHeapInit+0xb4>)
 80134a4:	681b      	ldr	r3, [r3, #0]
 80134a6:	2200      	movs	r2, #0
 80134a8:	605a      	str	r2, [r3, #4]
	pxEnd->pxNextFreeBlock = NULL;
 80134aa:	4b12      	ldr	r3, [pc, #72]	@ (80134f4 <prvHeapInit+0xb4>)
 80134ac:	681b      	ldr	r3, [r3, #0]
 80134ae:	2200      	movs	r2, #0
 80134b0:	601a      	str	r2, [r3, #0]

	/* To start with there is a single free block that is sized to take up the
	entire heap space, minus the space taken by pxEnd. */
	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
 80134b2:	687b      	ldr	r3, [r7, #4]
 80134b4:	603b      	str	r3, [r7, #0]
	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
 80134b6:	683b      	ldr	r3, [r7, #0]
 80134b8:	68fa      	ldr	r2, [r7, #12]
 80134ba:	1ad2      	subs	r2, r2, r3
 80134bc:	683b      	ldr	r3, [r7, #0]
 80134be:	605a      	str	r2, [r3, #4]
	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
 80134c0:	4b0c      	ldr	r3, [pc, #48]	@ (80134f4 <prvHeapInit+0xb4>)
 80134c2:	681a      	ldr	r2, [r3, #0]
 80134c4:	683b      	ldr	r3, [r7, #0]
 80134c6:	601a      	str	r2, [r3, #0]

	/* Only one block exists - and it covers the entire usable heap space. */
	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
 80134c8:	683b      	ldr	r3, [r7, #0]
 80134ca:	685b      	ldr	r3, [r3, #4]
 80134cc:	4a0a      	ldr	r2, [pc, #40]	@ (80134f8 <prvHeapInit+0xb8>)
 80134ce:	6013      	str	r3, [r2, #0]
	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
 80134d0:	683b      	ldr	r3, [r7, #0]
 80134d2:	685b      	ldr	r3, [r3, #4]
 80134d4:	4a09      	ldr	r2, [pc, #36]	@ (80134fc <prvHeapInit+0xbc>)
 80134d6:	6013      	str	r3, [r2, #0]

	/* Work out the position of the top bit in a size_t variable. */
	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
 80134d8:	4b09      	ldr	r3, [pc, #36]	@ (8013500 <prvHeapInit+0xc0>)
 80134da:	f04f 4200 	mov.w	r2, #2147483648	@ 0x80000000
 80134de:	601a      	str	r2, [r3, #0]
}
 80134e0:	bf00      	nop
 80134e2:	3714      	adds	r7, #20
 80134e4:	46bd      	mov	sp, r7
 80134e6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80134ea:	4770      	bx	lr
 80134ec:	24002a28 	.word	0x24002a28
 80134f0:	24012a28 	.word	0x24012a28
 80134f4:	24012a30 	.word	0x24012a30
 80134f8:	24012a38 	.word	0x24012a38
 80134fc:	24012a34 	.word	0x24012a34
 8013500:	24012a44 	.word	0x24012a44

08013504 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/

static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
 8013504:	b480      	push	{r7}
 8013506:	b085      	sub	sp, #20
 8013508:	af00      	add	r7, sp, #0
 801350a:	6078      	str	r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;

	/* Iterate through the list until a block is found that has a higher address
	than the block being inserted. */
	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
 801350c:	4b28      	ldr	r3, [pc, #160]	@ (80135b0 <prvInsertBlockIntoFreeList+0xac>)
 801350e:	60fb      	str	r3, [r7, #12]
 8013510:	e002      	b.n	8013518 <prvInsertBlockIntoFreeList+0x14>
 8013512:	68fb      	ldr	r3, [r7, #12]
 8013514:	681b      	ldr	r3, [r3, #0]
 8013516:	60fb      	str	r3, [r7, #12]
 8013518:	68fb      	ldr	r3, [r7, #12]
 801351a:	681b      	ldr	r3, [r3, #0]
 801351c:	687a      	ldr	r2, [r7, #4]
 801351e:	429a      	cmp	r2, r3
 8013520:	d8f7      	bhi.n	8013512 <prvInsertBlockIntoFreeList+0xe>
		/* Nothing to do here, just iterate to the right position. */
	}

	/* Do the block being inserted, and the block it is being inserted after
	make a contiguous block of memory? */
	puc = ( uint8_t * ) pxIterator;
 8013522:	68fb      	ldr	r3, [r7, #12]
 8013524:	60bb      	str	r3, [r7, #8]
	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
 8013526:	68fb      	ldr	r3, [r7, #12]
 8013528:	685b      	ldr	r3, [r3, #4]
 801352a:	68ba      	ldr	r2, [r7, #8]
 801352c:	4413      	add	r3, r2
 801352e:	687a      	ldr	r2, [r7, #4]
 8013530:	429a      	cmp	r2, r3
 8013532:	d108      	bne.n	8013546 <prvInsertBlockIntoFreeList+0x42>
	{
		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
 8013534:	68fb      	ldr	r3, [r7, #12]
 8013536:	685a      	ldr	r2, [r3, #4]
 8013538:	687b      	ldr	r3, [r7, #4]
 801353a:	685b      	ldr	r3, [r3, #4]
 801353c:	441a      	add	r2, r3
 801353e:	68fb      	ldr	r3, [r7, #12]
 8013540:	605a      	str	r2, [r3, #4]
		pxBlockToInsert = pxIterator;
 8013542:	68fb      	ldr	r3, [r7, #12]
 8013544:	607b      	str	r3, [r7, #4]
		mtCOVERAGE_TEST_MARKER();
	}

	/* Do the block being inserted, and the block it is being inserted before
	make a contiguous block of memory? */
	puc = ( uint8_t * ) pxBlockToInsert;
 8013546:	687b      	ldr	r3, [r7, #4]
 8013548:	60bb      	str	r3, [r7, #8]
	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
 801354a:	687b      	ldr	r3, [r7, #4]
 801354c:	685b      	ldr	r3, [r3, #4]
 801354e:	68ba      	ldr	r2, [r7, #8]
 8013550:	441a      	add	r2, r3
 8013552:	68fb      	ldr	r3, [r7, #12]
 8013554:	681b      	ldr	r3, [r3, #0]
 8013556:	429a      	cmp	r2, r3
 8013558:	d118      	bne.n	801358c <prvInsertBlockIntoFreeList+0x88>
	{
		if( pxIterator->pxNextFreeBlock != pxEnd )
 801355a:	68fb      	ldr	r3, [r7, #12]
 801355c:	681a      	ldr	r2, [r3, #0]
 801355e:	4b15      	ldr	r3, [pc, #84]	@ (80135b4 <prvInsertBlockIntoFreeList+0xb0>)
 8013560:	681b      	ldr	r3, [r3, #0]
 8013562:	429a      	cmp	r2, r3
 8013564:	d00d      	beq.n	8013582 <prvInsertBlockIntoFreeList+0x7e>
		{
			/* Form one big block from the two blocks. */
			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
 8013566:	687b      	ldr	r3, [r7, #4]
 8013568:	685a      	ldr	r2, [r3, #4]
 801356a:	68fb      	ldr	r3, [r7, #12]
 801356c:	681b      	ldr	r3, [r3, #0]
 801356e:	685b      	ldr	r3, [r3, #4]
 8013570:	441a      	add	r2, r3
 8013572:	687b      	ldr	r3, [r7, #4]
 8013574:	605a      	str	r2, [r3, #4]
			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
 8013576:	68fb      	ldr	r3, [r7, #12]
 8013578:	681b      	ldr	r3, [r3, #0]
 801357a:	681a      	ldr	r2, [r3, #0]
 801357c:	687b      	ldr	r3, [r7, #4]
 801357e:	601a      	str	r2, [r3, #0]
 8013580:	e008      	b.n	8013594 <prvInsertBlockIntoFreeList+0x90>
		}
		else
		{
			pxBlockToInsert->pxNextFreeBlock = pxEnd;
 8013582:	4b0c      	ldr	r3, [pc, #48]	@ (80135b4 <prvInsertBlockIntoFreeList+0xb0>)
 8013584:	681a      	ldr	r2, [r3, #0]
 8013586:	687b      	ldr	r3, [r7, #4]
 8013588:	601a      	str	r2, [r3, #0]
 801358a:	e003      	b.n	8013594 <prvInsertBlockIntoFreeList+0x90>
		}
	}
	else
	{
		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
 801358c:	68fb      	ldr	r3, [r7, #12]
 801358e:	681a      	ldr	r2, [r3, #0]
 8013590:	687b      	ldr	r3, [r7, #4]
 8013592:	601a      	str	r2, [r3, #0]

	/* If the block being inserted plugged a gab, so was merged with the block
	before and the block after, then it's pxNextFreeBlock pointer will have
	already been set, and should not be set here as that would make it point
	to itself. */
	if( pxIterator != pxBlockToInsert )
 8013594:	68fa      	ldr	r2, [r7, #12]
 8013596:	687b      	ldr	r3, [r7, #4]
 8013598:	429a      	cmp	r2, r3
 801359a:	d002      	beq.n	80135a2 <prvInsertBlockIntoFreeList+0x9e>
	{
		pxIterator->pxNextFreeBlock = pxBlockToInsert;
 801359c:	68fb      	ldr	r3, [r7, #12]
 801359e:	687a      	ldr	r2, [r7, #4]
 80135a0:	601a      	str	r2, [r3, #0]
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 80135a2:	bf00      	nop
 80135a4:	3714      	adds	r7, #20
 80135a6:	46bd      	mov	sp, r7
 80135a8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80135ac:	4770      	bx	lr
 80135ae:	bf00      	nop
 80135b0:	24012a28 	.word	0x24012a28
 80135b4:	24012a30 	.word	0x24012a30

080135b8 <std>:
 80135b8:	2300      	movs	r3, #0
 80135ba:	b510      	push	{r4, lr}
 80135bc:	4604      	mov	r4, r0
 80135be:	e9c0 3300 	strd	r3, r3, [r0]
 80135c2:	e9c0 3304 	strd	r3, r3, [r0, #16]
 80135c6:	6083      	str	r3, [r0, #8]
 80135c8:	8181      	strh	r1, [r0, #12]
 80135ca:	6643      	str	r3, [r0, #100]	@ 0x64
 80135cc:	81c2      	strh	r2, [r0, #14]
 80135ce:	6183      	str	r3, [r0, #24]
 80135d0:	4619      	mov	r1, r3
 80135d2:	2208      	movs	r2, #8
 80135d4:	305c      	adds	r0, #92	@ 0x5c
 80135d6:	f000 f906 	bl	80137e6 <memset>
 80135da:	4b0d      	ldr	r3, [pc, #52]	@ (8013610 <std+0x58>)
 80135dc:	6263      	str	r3, [r4, #36]	@ 0x24
 80135de:	4b0d      	ldr	r3, [pc, #52]	@ (8013614 <std+0x5c>)
 80135e0:	62a3      	str	r3, [r4, #40]	@ 0x28
 80135e2:	4b0d      	ldr	r3, [pc, #52]	@ (8013618 <std+0x60>)
 80135e4:	62e3      	str	r3, [r4, #44]	@ 0x2c
 80135e6:	4b0d      	ldr	r3, [pc, #52]	@ (801361c <std+0x64>)
 80135e8:	6323      	str	r3, [r4, #48]	@ 0x30
 80135ea:	4b0d      	ldr	r3, [pc, #52]	@ (8013620 <std+0x68>)
 80135ec:	6224      	str	r4, [r4, #32]
 80135ee:	429c      	cmp	r4, r3
 80135f0:	d006      	beq.n	8013600 <std+0x48>
 80135f2:	f103 0268 	add.w	r2, r3, #104	@ 0x68
 80135f6:	4294      	cmp	r4, r2
 80135f8:	d002      	beq.n	8013600 <std+0x48>
 80135fa:	33d0      	adds	r3, #208	@ 0xd0
 80135fc:	429c      	cmp	r4, r3
 80135fe:	d105      	bne.n	801360c <std+0x54>
 8013600:	f104 0058 	add.w	r0, r4, #88	@ 0x58
 8013604:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 8013608:	f000 b9bc 	b.w	8013984 <__retarget_lock_init_recursive>
 801360c:	bd10      	pop	{r4, pc}
 801360e:	bf00      	nop
 8013610:	08013761 	.word	0x08013761
 8013614:	08013783 	.word	0x08013783
 8013618:	080137bb 	.word	0x080137bb
 801361c:	080137df 	.word	0x080137df
 8013620:	24012a48 	.word	0x24012a48

08013624 <stdio_exit_handler>:
 8013624:	4a02      	ldr	r2, [pc, #8]	@ (8013630 <stdio_exit_handler+0xc>)
 8013626:	4903      	ldr	r1, [pc, #12]	@ (8013634 <stdio_exit_handler+0x10>)
 8013628:	4803      	ldr	r0, [pc, #12]	@ (8013638 <stdio_exit_handler+0x14>)
 801362a:	f000 b869 	b.w	8013700 <_fwalk_sglue>
 801362e:	bf00      	nop
 8013630:	24000048 	.word	0x24000048
 8013634:	08014241 	.word	0x08014241
 8013638:	24000058 	.word	0x24000058

0801363c <cleanup_stdio>:
 801363c:	6841      	ldr	r1, [r0, #4]
 801363e:	4b0c      	ldr	r3, [pc, #48]	@ (8013670 <cleanup_stdio+0x34>)
 8013640:	4299      	cmp	r1, r3
 8013642:	b510      	push	{r4, lr}
 8013644:	4604      	mov	r4, r0
 8013646:	d001      	beq.n	801364c <cleanup_stdio+0x10>
 8013648:	f000 fdfa 	bl	8014240 <_fflush_r>
 801364c:	68a1      	ldr	r1, [r4, #8]
 801364e:	4b09      	ldr	r3, [pc, #36]	@ (8013674 <cleanup_stdio+0x38>)
 8013650:	4299      	cmp	r1, r3
 8013652:	d002      	beq.n	801365a <cleanup_stdio+0x1e>
 8013654:	4620      	mov	r0, r4
 8013656:	f000 fdf3 	bl	8014240 <_fflush_r>
 801365a:	68e1      	ldr	r1, [r4, #12]
 801365c:	4b06      	ldr	r3, [pc, #24]	@ (8013678 <cleanup_stdio+0x3c>)
 801365e:	4299      	cmp	r1, r3
 8013660:	d004      	beq.n	801366c <cleanup_stdio+0x30>
 8013662:	4620      	mov	r0, r4
 8013664:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 8013668:	f000 bdea 	b.w	8014240 <_fflush_r>
 801366c:	bd10      	pop	{r4, pc}
 801366e:	bf00      	nop
 8013670:	24012a48 	.word	0x24012a48
 8013674:	24012ab0 	.word	0x24012ab0
 8013678:	24012b18 	.word	0x24012b18

0801367c <global_stdio_init.part.0>:
 801367c:	b510      	push	{r4, lr}
 801367e:	4b0b      	ldr	r3, [pc, #44]	@ (80136ac <global_stdio_init.part.0+0x30>)
 8013680:	4c0b      	ldr	r4, [pc, #44]	@ (80136b0 <global_stdio_init.part.0+0x34>)
 8013682:	4a0c      	ldr	r2, [pc, #48]	@ (80136b4 <global_stdio_init.part.0+0x38>)
 8013684:	601a      	str	r2, [r3, #0]
 8013686:	4620      	mov	r0, r4
 8013688:	2200      	movs	r2, #0
 801368a:	2104      	movs	r1, #4
 801368c:	f7ff ff94 	bl	80135b8 <std>
 8013690:	f104 0068 	add.w	r0, r4, #104	@ 0x68
 8013694:	2201      	movs	r2, #1
 8013696:	2109      	movs	r1, #9
 8013698:	f7ff ff8e 	bl	80135b8 <std>
 801369c:	f104 00d0 	add.w	r0, r4, #208	@ 0xd0
 80136a0:	2202      	movs	r2, #2
 80136a2:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 80136a6:	2112      	movs	r1, #18
 80136a8:	f7ff bf86 	b.w	80135b8 <std>
 80136ac:	24012b80 	.word	0x24012b80
 80136b0:	24012a48 	.word	0x24012a48
 80136b4:	08013625 	.word	0x08013625

080136b8 <__sfp_lock_acquire>:
 80136b8:	4801      	ldr	r0, [pc, #4]	@ (80136c0 <__sfp_lock_acquire+0x8>)
 80136ba:	f000 b964 	b.w	8013986 <__retarget_lock_acquire_recursive>
 80136be:	bf00      	nop
 80136c0:	24012b89 	.word	0x24012b89

080136c4 <__sfp_lock_release>:
 80136c4:	4801      	ldr	r0, [pc, #4]	@ (80136cc <__sfp_lock_release+0x8>)
 80136c6:	f000 b95f 	b.w	8013988 <__retarget_lock_release_recursive>
 80136ca:	bf00      	nop
 80136cc:	24012b89 	.word	0x24012b89

080136d0 <__sinit>:
 80136d0:	b510      	push	{r4, lr}
 80136d2:	4604      	mov	r4, r0
 80136d4:	f7ff fff0 	bl	80136b8 <__sfp_lock_acquire>
 80136d8:	6a23      	ldr	r3, [r4, #32]
 80136da:	b11b      	cbz	r3, 80136e4 <__sinit+0x14>
 80136dc:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 80136e0:	f7ff bff0 	b.w	80136c4 <__sfp_lock_release>
 80136e4:	4b04      	ldr	r3, [pc, #16]	@ (80136f8 <__sinit+0x28>)
 80136e6:	6223      	str	r3, [r4, #32]
 80136e8:	4b04      	ldr	r3, [pc, #16]	@ (80136fc <__sinit+0x2c>)
 80136ea:	681b      	ldr	r3, [r3, #0]
 80136ec:	2b00      	cmp	r3, #0
 80136ee:	d1f5      	bne.n	80136dc <__sinit+0xc>
 80136f0:	f7ff ffc4 	bl	801367c <global_stdio_init.part.0>
 80136f4:	e7f2      	b.n	80136dc <__sinit+0xc>
 80136f6:	bf00      	nop
 80136f8:	0801363d 	.word	0x0801363d
 80136fc:	24012b80 	.word	0x24012b80

08013700 <_fwalk_sglue>:
 8013700:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8013704:	4607      	mov	r7, r0
 8013706:	4688      	mov	r8, r1
 8013708:	4614      	mov	r4, r2
 801370a:	2600      	movs	r6, #0
 801370c:	e9d4 9501 	ldrd	r9, r5, [r4, #4]
 8013710:	f1b9 0901 	subs.w	r9, r9, #1
 8013714:	d505      	bpl.n	8013722 <_fwalk_sglue+0x22>
 8013716:	6824      	ldr	r4, [r4, #0]
 8013718:	2c00      	cmp	r4, #0
 801371a:	d1f7      	bne.n	801370c <_fwalk_sglue+0xc>
 801371c:	4630      	mov	r0, r6
 801371e:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 8013722:	89ab      	ldrh	r3, [r5, #12]
 8013724:	2b01      	cmp	r3, #1
 8013726:	d907      	bls.n	8013738 <_fwalk_sglue+0x38>
 8013728:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
 801372c:	3301      	adds	r3, #1
 801372e:	d003      	beq.n	8013738 <_fwalk_sglue+0x38>
 8013730:	4629      	mov	r1, r5
 8013732:	4638      	mov	r0, r7
 8013734:	47c0      	blx	r8
 8013736:	4306      	orrs	r6, r0
 8013738:	3568      	adds	r5, #104	@ 0x68
 801373a:	e7e9      	b.n	8013710 <_fwalk_sglue+0x10>

0801373c <iprintf>:
 801373c:	b40f      	push	{r0, r1, r2, r3}
 801373e:	b507      	push	{r0, r1, r2, lr}
 8013740:	4906      	ldr	r1, [pc, #24]	@ (801375c <iprintf+0x20>)
 8013742:	ab04      	add	r3, sp, #16
 8013744:	6808      	ldr	r0, [r1, #0]
 8013746:	f853 2b04 	ldr.w	r2, [r3], #4
 801374a:	6881      	ldr	r1, [r0, #8]
 801374c:	9301      	str	r3, [sp, #4]
 801374e:	f000 fa4d 	bl	8013bec <_vfiprintf_r>
 8013752:	b003      	add	sp, #12
 8013754:	f85d eb04 	ldr.w	lr, [sp], #4
 8013758:	b004      	add	sp, #16
 801375a:	4770      	bx	lr
 801375c:	24000054 	.word	0x24000054

08013760 <__sread>:
 8013760:	b510      	push	{r4, lr}
 8013762:	460c      	mov	r4, r1
 8013764:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8013768:	f000 f8be 	bl	80138e8 <_read_r>
 801376c:	2800      	cmp	r0, #0
 801376e:	bfab      	itete	ge
 8013770:	6d63      	ldrge	r3, [r4, #84]	@ 0x54
 8013772:	89a3      	ldrhlt	r3, [r4, #12]
 8013774:	181b      	addge	r3, r3, r0
 8013776:	f423 5380 	biclt.w	r3, r3, #4096	@ 0x1000
 801377a:	bfac      	ite	ge
 801377c:	6563      	strge	r3, [r4, #84]	@ 0x54
 801377e:	81a3      	strhlt	r3, [r4, #12]
 8013780:	bd10      	pop	{r4, pc}

08013782 <__swrite>:
 8013782:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8013786:	461f      	mov	r7, r3
 8013788:	898b      	ldrh	r3, [r1, #12]
 801378a:	05db      	lsls	r3, r3, #23
 801378c:	4605      	mov	r5, r0
 801378e:	460c      	mov	r4, r1
 8013790:	4616      	mov	r6, r2
 8013792:	d505      	bpl.n	80137a0 <__swrite+0x1e>
 8013794:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8013798:	2302      	movs	r3, #2
 801379a:	2200      	movs	r2, #0
 801379c:	f000 f892 	bl	80138c4 <_lseek_r>
 80137a0:	89a3      	ldrh	r3, [r4, #12]
 80137a2:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 80137a6:	f423 5380 	bic.w	r3, r3, #4096	@ 0x1000
 80137aa:	81a3      	strh	r3, [r4, #12]
 80137ac:	4632      	mov	r2, r6
 80137ae:	463b      	mov	r3, r7
 80137b0:	4628      	mov	r0, r5
 80137b2:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
 80137b6:	f000 b8a9 	b.w	801390c <_write_r>

080137ba <__sseek>:
 80137ba:	b510      	push	{r4, lr}
 80137bc:	460c      	mov	r4, r1
 80137be:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80137c2:	f000 f87f 	bl	80138c4 <_lseek_r>
 80137c6:	1c43      	adds	r3, r0, #1
 80137c8:	89a3      	ldrh	r3, [r4, #12]
 80137ca:	bf15      	itete	ne
 80137cc:	6560      	strne	r0, [r4, #84]	@ 0x54
 80137ce:	f423 5380 	biceq.w	r3, r3, #4096	@ 0x1000
 80137d2:	f443 5380 	orrne.w	r3, r3, #4096	@ 0x1000
 80137d6:	81a3      	strheq	r3, [r4, #12]
 80137d8:	bf18      	it	ne
 80137da:	81a3      	strhne	r3, [r4, #12]
 80137dc:	bd10      	pop	{r4, pc}

080137de <__sclose>:
 80137de:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80137e2:	f000 b809 	b.w	80137f8 <_close_r>

080137e6 <memset>:
 80137e6:	4402      	add	r2, r0
 80137e8:	4603      	mov	r3, r0
 80137ea:	4293      	cmp	r3, r2
 80137ec:	d100      	bne.n	80137f0 <memset+0xa>
 80137ee:	4770      	bx	lr
 80137f0:	f803 1b01 	strb.w	r1, [r3], #1
 80137f4:	e7f9      	b.n	80137ea <memset+0x4>
	...

080137f8 <_close_r>:
 80137f8:	b538      	push	{r3, r4, r5, lr}
 80137fa:	4d06      	ldr	r5, [pc, #24]	@ (8013814 <_close_r+0x1c>)
 80137fc:	2300      	movs	r3, #0
 80137fe:	4604      	mov	r4, r0
 8013800:	4608      	mov	r0, r1
 8013802:	602b      	str	r3, [r5, #0]
 8013804:	f7ee ffa3 	bl	800274e <_close>
 8013808:	1c43      	adds	r3, r0, #1
 801380a:	d102      	bne.n	8013812 <_close_r+0x1a>
 801380c:	682b      	ldr	r3, [r5, #0]
 801380e:	b103      	cbz	r3, 8013812 <_close_r+0x1a>
 8013810:	6023      	str	r3, [r4, #0]
 8013812:	bd38      	pop	{r3, r4, r5, pc}
 8013814:	24012b84 	.word	0x24012b84

08013818 <_reclaim_reent>:
 8013818:	4b29      	ldr	r3, [pc, #164]	@ (80138c0 <_reclaim_reent+0xa8>)
 801381a:	681b      	ldr	r3, [r3, #0]
 801381c:	4283      	cmp	r3, r0
 801381e:	b570      	push	{r4, r5, r6, lr}
 8013820:	4604      	mov	r4, r0
 8013822:	d04b      	beq.n	80138bc <_reclaim_reent+0xa4>
 8013824:	69c3      	ldr	r3, [r0, #28]
 8013826:	b1ab      	cbz	r3, 8013854 <_reclaim_reent+0x3c>
 8013828:	68db      	ldr	r3, [r3, #12]
 801382a:	b16b      	cbz	r3, 8013848 <_reclaim_reent+0x30>
 801382c:	2500      	movs	r5, #0
 801382e:	69e3      	ldr	r3, [r4, #28]
 8013830:	68db      	ldr	r3, [r3, #12]
 8013832:	5959      	ldr	r1, [r3, r5]
 8013834:	2900      	cmp	r1, #0
 8013836:	d13b      	bne.n	80138b0 <_reclaim_reent+0x98>
 8013838:	3504      	adds	r5, #4
 801383a:	2d80      	cmp	r5, #128	@ 0x80
 801383c:	d1f7      	bne.n	801382e <_reclaim_reent+0x16>
 801383e:	69e3      	ldr	r3, [r4, #28]
 8013840:	4620      	mov	r0, r4
 8013842:	68d9      	ldr	r1, [r3, #12]
 8013844:	f000 f8b0 	bl	80139a8 <_free_r>
 8013848:	69e3      	ldr	r3, [r4, #28]
 801384a:	6819      	ldr	r1, [r3, #0]
 801384c:	b111      	cbz	r1, 8013854 <_reclaim_reent+0x3c>
 801384e:	4620      	mov	r0, r4
 8013850:	f000 f8aa 	bl	80139a8 <_free_r>
 8013854:	6961      	ldr	r1, [r4, #20]
 8013856:	b111      	cbz	r1, 801385e <_reclaim_reent+0x46>
 8013858:	4620      	mov	r0, r4
 801385a:	f000 f8a5 	bl	80139a8 <_free_r>
 801385e:	69e1      	ldr	r1, [r4, #28]
 8013860:	b111      	cbz	r1, 8013868 <_reclaim_reent+0x50>
 8013862:	4620      	mov	r0, r4
 8013864:	f000 f8a0 	bl	80139a8 <_free_r>
 8013868:	6b21      	ldr	r1, [r4, #48]	@ 0x30
 801386a:	b111      	cbz	r1, 8013872 <_reclaim_reent+0x5a>
 801386c:	4620      	mov	r0, r4
 801386e:	f000 f89b 	bl	80139a8 <_free_r>
 8013872:	6b61      	ldr	r1, [r4, #52]	@ 0x34
 8013874:	b111      	cbz	r1, 801387c <_reclaim_reent+0x64>
 8013876:	4620      	mov	r0, r4
 8013878:	f000 f896 	bl	80139a8 <_free_r>
 801387c:	6ba1      	ldr	r1, [r4, #56]	@ 0x38
 801387e:	b111      	cbz	r1, 8013886 <_reclaim_reent+0x6e>
 8013880:	4620      	mov	r0, r4
 8013882:	f000 f891 	bl	80139a8 <_free_r>
 8013886:	6ca1      	ldr	r1, [r4, #72]	@ 0x48
 8013888:	b111      	cbz	r1, 8013890 <_reclaim_reent+0x78>
 801388a:	4620      	mov	r0, r4
 801388c:	f000 f88c 	bl	80139a8 <_free_r>
 8013890:	6c61      	ldr	r1, [r4, #68]	@ 0x44
 8013892:	b111      	cbz	r1, 801389a <_reclaim_reent+0x82>
 8013894:	4620      	mov	r0, r4
 8013896:	f000 f887 	bl	80139a8 <_free_r>
 801389a:	6ae1      	ldr	r1, [r4, #44]	@ 0x2c
 801389c:	b111      	cbz	r1, 80138a4 <_reclaim_reent+0x8c>
 801389e:	4620      	mov	r0, r4
 80138a0:	f000 f882 	bl	80139a8 <_free_r>
 80138a4:	6a23      	ldr	r3, [r4, #32]
 80138a6:	b14b      	cbz	r3, 80138bc <_reclaim_reent+0xa4>
 80138a8:	4620      	mov	r0, r4
 80138aa:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
 80138ae:	4718      	bx	r3
 80138b0:	680e      	ldr	r6, [r1, #0]
 80138b2:	4620      	mov	r0, r4
 80138b4:	f000 f878 	bl	80139a8 <_free_r>
 80138b8:	4631      	mov	r1, r6
 80138ba:	e7bb      	b.n	8013834 <_reclaim_reent+0x1c>
 80138bc:	bd70      	pop	{r4, r5, r6, pc}
 80138be:	bf00      	nop
 80138c0:	24000054 	.word	0x24000054

080138c4 <_lseek_r>:
 80138c4:	b538      	push	{r3, r4, r5, lr}
 80138c6:	4d07      	ldr	r5, [pc, #28]	@ (80138e4 <_lseek_r+0x20>)
 80138c8:	4604      	mov	r4, r0
 80138ca:	4608      	mov	r0, r1
 80138cc:	4611      	mov	r1, r2
 80138ce:	2200      	movs	r2, #0
 80138d0:	602a      	str	r2, [r5, #0]
 80138d2:	461a      	mov	r2, r3
 80138d4:	f7ee ff62 	bl	800279c <_lseek>
 80138d8:	1c43      	adds	r3, r0, #1
 80138da:	d102      	bne.n	80138e2 <_lseek_r+0x1e>
 80138dc:	682b      	ldr	r3, [r5, #0]
 80138de:	b103      	cbz	r3, 80138e2 <_lseek_r+0x1e>
 80138e0:	6023      	str	r3, [r4, #0]
 80138e2:	bd38      	pop	{r3, r4, r5, pc}
 80138e4:	24012b84 	.word	0x24012b84

080138e8 <_read_r>:
 80138e8:	b538      	push	{r3, r4, r5, lr}
 80138ea:	4d07      	ldr	r5, [pc, #28]	@ (8013908 <_read_r+0x20>)
 80138ec:	4604      	mov	r4, r0
 80138ee:	4608      	mov	r0, r1
 80138f0:	4611      	mov	r1, r2
 80138f2:	2200      	movs	r2, #0
 80138f4:	602a      	str	r2, [r5, #0]
 80138f6:	461a      	mov	r2, r3
 80138f8:	f7ee fef0 	bl	80026dc <_read>
 80138fc:	1c43      	adds	r3, r0, #1
 80138fe:	d102      	bne.n	8013906 <_read_r+0x1e>
 8013900:	682b      	ldr	r3, [r5, #0]
 8013902:	b103      	cbz	r3, 8013906 <_read_r+0x1e>
 8013904:	6023      	str	r3, [r4, #0]
 8013906:	bd38      	pop	{r3, r4, r5, pc}
 8013908:	24012b84 	.word	0x24012b84

0801390c <_write_r>:
 801390c:	b538      	push	{r3, r4, r5, lr}
 801390e:	4d07      	ldr	r5, [pc, #28]	@ (801392c <_write_r+0x20>)
 8013910:	4604      	mov	r4, r0
 8013912:	4608      	mov	r0, r1
 8013914:	4611      	mov	r1, r2
 8013916:	2200      	movs	r2, #0
 8013918:	602a      	str	r2, [r5, #0]
 801391a:	461a      	mov	r2, r3
 801391c:	f7ee fefb 	bl	8002716 <_write>
 8013920:	1c43      	adds	r3, r0, #1
 8013922:	d102      	bne.n	801392a <_write_r+0x1e>
 8013924:	682b      	ldr	r3, [r5, #0]
 8013926:	b103      	cbz	r3, 801392a <_write_r+0x1e>
 8013928:	6023      	str	r3, [r4, #0]
 801392a:	bd38      	pop	{r3, r4, r5, pc}
 801392c:	24012b84 	.word	0x24012b84

08013930 <__errno>:
 8013930:	4b01      	ldr	r3, [pc, #4]	@ (8013938 <__errno+0x8>)
 8013932:	6818      	ldr	r0, [r3, #0]
 8013934:	4770      	bx	lr
 8013936:	bf00      	nop
 8013938:	24000054 	.word	0x24000054

0801393c <__libc_init_array>:
 801393c:	b570      	push	{r4, r5, r6, lr}
 801393e:	4d0d      	ldr	r5, [pc, #52]	@ (8013974 <__libc_init_array+0x38>)
 8013940:	4c0d      	ldr	r4, [pc, #52]	@ (8013978 <__libc_init_array+0x3c>)
 8013942:	1b64      	subs	r4, r4, r5
 8013944:	10a4      	asrs	r4, r4, #2
 8013946:	2600      	movs	r6, #0
 8013948:	42a6      	cmp	r6, r4
 801394a:	d109      	bne.n	8013960 <__libc_init_array+0x24>
 801394c:	4d0b      	ldr	r5, [pc, #44]	@ (801397c <__libc_init_array+0x40>)
 801394e:	4c0c      	ldr	r4, [pc, #48]	@ (8013980 <__libc_init_array+0x44>)
 8013950:	f000 fdc6 	bl	80144e0 <_init>
 8013954:	1b64      	subs	r4, r4, r5
 8013956:	10a4      	asrs	r4, r4, #2
 8013958:	2600      	movs	r6, #0
 801395a:	42a6      	cmp	r6, r4
 801395c:	d105      	bne.n	801396a <__libc_init_array+0x2e>
 801395e:	bd70      	pop	{r4, r5, r6, pc}
 8013960:	f855 3b04 	ldr.w	r3, [r5], #4
 8013964:	4798      	blx	r3
 8013966:	3601      	adds	r6, #1
 8013968:	e7ee      	b.n	8013948 <__libc_init_array+0xc>
 801396a:	f855 3b04 	ldr.w	r3, [r5], #4
 801396e:	4798      	blx	r3
 8013970:	3601      	adds	r6, #1
 8013972:	e7f2      	b.n	801395a <__libc_init_array+0x1e>
 8013974:	08014660 	.word	0x08014660
 8013978:	08014660 	.word	0x08014660
 801397c:	08014660 	.word	0x08014660
 8013980:	08014664 	.word	0x08014664

08013984 <__retarget_lock_init_recursive>:
 8013984:	4770      	bx	lr

08013986 <__retarget_lock_acquire_recursive>:
 8013986:	4770      	bx	lr

08013988 <__retarget_lock_release_recursive>:
 8013988:	4770      	bx	lr

0801398a <memcpy>:
 801398a:	440a      	add	r2, r1
 801398c:	4291      	cmp	r1, r2
 801398e:	f100 33ff 	add.w	r3, r0, #4294967295	@ 0xffffffff
 8013992:	d100      	bne.n	8013996 <memcpy+0xc>
 8013994:	4770      	bx	lr
 8013996:	b510      	push	{r4, lr}
 8013998:	f811 4b01 	ldrb.w	r4, [r1], #1
 801399c:	f803 4f01 	strb.w	r4, [r3, #1]!
 80139a0:	4291      	cmp	r1, r2
 80139a2:	d1f9      	bne.n	8013998 <memcpy+0xe>
 80139a4:	bd10      	pop	{r4, pc}
	...

080139a8 <_free_r>:
 80139a8:	b538      	push	{r3, r4, r5, lr}
 80139aa:	4605      	mov	r5, r0
 80139ac:	2900      	cmp	r1, #0
 80139ae:	d041      	beq.n	8013a34 <_free_r+0x8c>
 80139b0:	f851 3c04 	ldr.w	r3, [r1, #-4]
 80139b4:	1f0c      	subs	r4, r1, #4
 80139b6:	2b00      	cmp	r3, #0
 80139b8:	bfb8      	it	lt
 80139ba:	18e4      	addlt	r4, r4, r3
 80139bc:	f000 f8e0 	bl	8013b80 <__malloc_lock>
 80139c0:	4a1d      	ldr	r2, [pc, #116]	@ (8013a38 <_free_r+0x90>)
 80139c2:	6813      	ldr	r3, [r2, #0]
 80139c4:	b933      	cbnz	r3, 80139d4 <_free_r+0x2c>
 80139c6:	6063      	str	r3, [r4, #4]
 80139c8:	6014      	str	r4, [r2, #0]
 80139ca:	4628      	mov	r0, r5
 80139cc:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 80139d0:	f000 b8dc 	b.w	8013b8c <__malloc_unlock>
 80139d4:	42a3      	cmp	r3, r4
 80139d6:	d908      	bls.n	80139ea <_free_r+0x42>
 80139d8:	6820      	ldr	r0, [r4, #0]
 80139da:	1821      	adds	r1, r4, r0
 80139dc:	428b      	cmp	r3, r1
 80139de:	bf01      	itttt	eq
 80139e0:	6819      	ldreq	r1, [r3, #0]
 80139e2:	685b      	ldreq	r3, [r3, #4]
 80139e4:	1809      	addeq	r1, r1, r0
 80139e6:	6021      	streq	r1, [r4, #0]
 80139e8:	e7ed      	b.n	80139c6 <_free_r+0x1e>
 80139ea:	461a      	mov	r2, r3
 80139ec:	685b      	ldr	r3, [r3, #4]
 80139ee:	b10b      	cbz	r3, 80139f4 <_free_r+0x4c>
 80139f0:	42a3      	cmp	r3, r4
 80139f2:	d9fa      	bls.n	80139ea <_free_r+0x42>
 80139f4:	6811      	ldr	r1, [r2, #0]
 80139f6:	1850      	adds	r0, r2, r1
 80139f8:	42a0      	cmp	r0, r4
 80139fa:	d10b      	bne.n	8013a14 <_free_r+0x6c>
 80139fc:	6820      	ldr	r0, [r4, #0]
 80139fe:	4401      	add	r1, r0
 8013a00:	1850      	adds	r0, r2, r1
 8013a02:	4283      	cmp	r3, r0
 8013a04:	6011      	str	r1, [r2, #0]
 8013a06:	d1e0      	bne.n	80139ca <_free_r+0x22>
 8013a08:	6818      	ldr	r0, [r3, #0]
 8013a0a:	685b      	ldr	r3, [r3, #4]
 8013a0c:	6053      	str	r3, [r2, #4]
 8013a0e:	4408      	add	r0, r1
 8013a10:	6010      	str	r0, [r2, #0]
 8013a12:	e7da      	b.n	80139ca <_free_r+0x22>
 8013a14:	d902      	bls.n	8013a1c <_free_r+0x74>
 8013a16:	230c      	movs	r3, #12
 8013a18:	602b      	str	r3, [r5, #0]
 8013a1a:	e7d6      	b.n	80139ca <_free_r+0x22>
 8013a1c:	6820      	ldr	r0, [r4, #0]
 8013a1e:	1821      	adds	r1, r4, r0
 8013a20:	428b      	cmp	r3, r1
 8013a22:	bf04      	itt	eq
 8013a24:	6819      	ldreq	r1, [r3, #0]
 8013a26:	685b      	ldreq	r3, [r3, #4]
 8013a28:	6063      	str	r3, [r4, #4]
 8013a2a:	bf04      	itt	eq
 8013a2c:	1809      	addeq	r1, r1, r0
 8013a2e:	6021      	streq	r1, [r4, #0]
 8013a30:	6054      	str	r4, [r2, #4]
 8013a32:	e7ca      	b.n	80139ca <_free_r+0x22>
 8013a34:	bd38      	pop	{r3, r4, r5, pc}
 8013a36:	bf00      	nop
 8013a38:	24012b90 	.word	0x24012b90

08013a3c <sbrk_aligned>:
 8013a3c:	b570      	push	{r4, r5, r6, lr}
 8013a3e:	4e0f      	ldr	r6, [pc, #60]	@ (8013a7c <sbrk_aligned+0x40>)
 8013a40:	460c      	mov	r4, r1
 8013a42:	6831      	ldr	r1, [r6, #0]
 8013a44:	4605      	mov	r5, r0
 8013a46:	b911      	cbnz	r1, 8013a4e <sbrk_aligned+0x12>
 8013a48:	f000 fcb6 	bl	80143b8 <_sbrk_r>
 8013a4c:	6030      	str	r0, [r6, #0]
 8013a4e:	4621      	mov	r1, r4
 8013a50:	4628      	mov	r0, r5
 8013a52:	f000 fcb1 	bl	80143b8 <_sbrk_r>
 8013a56:	1c43      	adds	r3, r0, #1
 8013a58:	d103      	bne.n	8013a62 <sbrk_aligned+0x26>
 8013a5a:	f04f 34ff 	mov.w	r4, #4294967295	@ 0xffffffff
 8013a5e:	4620      	mov	r0, r4
 8013a60:	bd70      	pop	{r4, r5, r6, pc}
 8013a62:	1cc4      	adds	r4, r0, #3
 8013a64:	f024 0403 	bic.w	r4, r4, #3
 8013a68:	42a0      	cmp	r0, r4
 8013a6a:	d0f8      	beq.n	8013a5e <sbrk_aligned+0x22>
 8013a6c:	1a21      	subs	r1, r4, r0
 8013a6e:	4628      	mov	r0, r5
 8013a70:	f000 fca2 	bl	80143b8 <_sbrk_r>
 8013a74:	3001      	adds	r0, #1
 8013a76:	d1f2      	bne.n	8013a5e <sbrk_aligned+0x22>
 8013a78:	e7ef      	b.n	8013a5a <sbrk_aligned+0x1e>
 8013a7a:	bf00      	nop
 8013a7c:	24012b8c 	.word	0x24012b8c

08013a80 <_malloc_r>:
 8013a80:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8013a84:	1ccd      	adds	r5, r1, #3
 8013a86:	f025 0503 	bic.w	r5, r5, #3
 8013a8a:	3508      	adds	r5, #8
 8013a8c:	2d0c      	cmp	r5, #12
 8013a8e:	bf38      	it	cc
 8013a90:	250c      	movcc	r5, #12
 8013a92:	2d00      	cmp	r5, #0
 8013a94:	4606      	mov	r6, r0
 8013a96:	db01      	blt.n	8013a9c <_malloc_r+0x1c>
 8013a98:	42a9      	cmp	r1, r5
 8013a9a:	d904      	bls.n	8013aa6 <_malloc_r+0x26>
 8013a9c:	230c      	movs	r3, #12
 8013a9e:	6033      	str	r3, [r6, #0]
 8013aa0:	2000      	movs	r0, #0
 8013aa2:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 8013aa6:	f8df 80d4 	ldr.w	r8, [pc, #212]	@ 8013b7c <_malloc_r+0xfc>
 8013aaa:	f000 f869 	bl	8013b80 <__malloc_lock>
 8013aae:	f8d8 3000 	ldr.w	r3, [r8]
 8013ab2:	461c      	mov	r4, r3
 8013ab4:	bb44      	cbnz	r4, 8013b08 <_malloc_r+0x88>
 8013ab6:	4629      	mov	r1, r5
 8013ab8:	4630      	mov	r0, r6
 8013aba:	f7ff ffbf 	bl	8013a3c <sbrk_aligned>
 8013abe:	1c43      	adds	r3, r0, #1
 8013ac0:	4604      	mov	r4, r0
 8013ac2:	d158      	bne.n	8013b76 <_malloc_r+0xf6>
 8013ac4:	f8d8 4000 	ldr.w	r4, [r8]
 8013ac8:	4627      	mov	r7, r4
 8013aca:	2f00      	cmp	r7, #0
 8013acc:	d143      	bne.n	8013b56 <_malloc_r+0xd6>
 8013ace:	2c00      	cmp	r4, #0
 8013ad0:	d04b      	beq.n	8013b6a <_malloc_r+0xea>
 8013ad2:	6823      	ldr	r3, [r4, #0]
 8013ad4:	4639      	mov	r1, r7
 8013ad6:	4630      	mov	r0, r6
 8013ad8:	eb04 0903 	add.w	r9, r4, r3
 8013adc:	f000 fc6c 	bl	80143b8 <_sbrk_r>
 8013ae0:	4581      	cmp	r9, r0
 8013ae2:	d142      	bne.n	8013b6a <_malloc_r+0xea>
 8013ae4:	6821      	ldr	r1, [r4, #0]
 8013ae6:	1a6d      	subs	r5, r5, r1
 8013ae8:	4629      	mov	r1, r5
 8013aea:	4630      	mov	r0, r6
 8013aec:	f7ff ffa6 	bl	8013a3c <sbrk_aligned>
 8013af0:	3001      	adds	r0, #1
 8013af2:	d03a      	beq.n	8013b6a <_malloc_r+0xea>
 8013af4:	6823      	ldr	r3, [r4, #0]
 8013af6:	442b      	add	r3, r5
 8013af8:	6023      	str	r3, [r4, #0]
 8013afa:	f8d8 3000 	ldr.w	r3, [r8]
 8013afe:	685a      	ldr	r2, [r3, #4]
 8013b00:	bb62      	cbnz	r2, 8013b5c <_malloc_r+0xdc>
 8013b02:	f8c8 7000 	str.w	r7, [r8]
 8013b06:	e00f      	b.n	8013b28 <_malloc_r+0xa8>
 8013b08:	6822      	ldr	r2, [r4, #0]
 8013b0a:	1b52      	subs	r2, r2, r5
 8013b0c:	d420      	bmi.n	8013b50 <_malloc_r+0xd0>
 8013b0e:	2a0b      	cmp	r2, #11
 8013b10:	d917      	bls.n	8013b42 <_malloc_r+0xc2>
 8013b12:	1961      	adds	r1, r4, r5
 8013b14:	42a3      	cmp	r3, r4
 8013b16:	6025      	str	r5, [r4, #0]
 8013b18:	bf18      	it	ne
 8013b1a:	6059      	strne	r1, [r3, #4]
 8013b1c:	6863      	ldr	r3, [r4, #4]
 8013b1e:	bf08      	it	eq
 8013b20:	f8c8 1000 	streq.w	r1, [r8]
 8013b24:	5162      	str	r2, [r4, r5]
 8013b26:	604b      	str	r3, [r1, #4]
 8013b28:	4630      	mov	r0, r6
 8013b2a:	f000 f82f 	bl	8013b8c <__malloc_unlock>
 8013b2e:	f104 000b 	add.w	r0, r4, #11
 8013b32:	1d23      	adds	r3, r4, #4
 8013b34:	f020 0007 	bic.w	r0, r0, #7
 8013b38:	1ac2      	subs	r2, r0, r3
 8013b3a:	bf1c      	itt	ne
 8013b3c:	1a1b      	subne	r3, r3, r0
 8013b3e:	50a3      	strne	r3, [r4, r2]
 8013b40:	e7af      	b.n	8013aa2 <_malloc_r+0x22>
 8013b42:	6862      	ldr	r2, [r4, #4]
 8013b44:	42a3      	cmp	r3, r4
 8013b46:	bf0c      	ite	eq
 8013b48:	f8c8 2000 	streq.w	r2, [r8]
 8013b4c:	605a      	strne	r2, [r3, #4]
 8013b4e:	e7eb      	b.n	8013b28 <_malloc_r+0xa8>
 8013b50:	4623      	mov	r3, r4
 8013b52:	6864      	ldr	r4, [r4, #4]
 8013b54:	e7ae      	b.n	8013ab4 <_malloc_r+0x34>
 8013b56:	463c      	mov	r4, r7
 8013b58:	687f      	ldr	r7, [r7, #4]
 8013b5a:	e7b6      	b.n	8013aca <_malloc_r+0x4a>
 8013b5c:	461a      	mov	r2, r3
 8013b5e:	685b      	ldr	r3, [r3, #4]
 8013b60:	42a3      	cmp	r3, r4
 8013b62:	d1fb      	bne.n	8013b5c <_malloc_r+0xdc>
 8013b64:	2300      	movs	r3, #0
 8013b66:	6053      	str	r3, [r2, #4]
 8013b68:	e7de      	b.n	8013b28 <_malloc_r+0xa8>
 8013b6a:	230c      	movs	r3, #12
 8013b6c:	6033      	str	r3, [r6, #0]
 8013b6e:	4630      	mov	r0, r6
 8013b70:	f000 f80c 	bl	8013b8c <__malloc_unlock>
 8013b74:	e794      	b.n	8013aa0 <_malloc_r+0x20>
 8013b76:	6005      	str	r5, [r0, #0]
 8013b78:	e7d6      	b.n	8013b28 <_malloc_r+0xa8>
 8013b7a:	bf00      	nop
 8013b7c:	24012b90 	.word	0x24012b90

08013b80 <__malloc_lock>:
 8013b80:	4801      	ldr	r0, [pc, #4]	@ (8013b88 <__malloc_lock+0x8>)
 8013b82:	f7ff bf00 	b.w	8013986 <__retarget_lock_acquire_recursive>
 8013b86:	bf00      	nop
 8013b88:	24012b88 	.word	0x24012b88

08013b8c <__malloc_unlock>:
 8013b8c:	4801      	ldr	r0, [pc, #4]	@ (8013b94 <__malloc_unlock+0x8>)
 8013b8e:	f7ff befb 	b.w	8013988 <__retarget_lock_release_recursive>
 8013b92:	bf00      	nop
 8013b94:	24012b88 	.word	0x24012b88

08013b98 <__sfputc_r>:
 8013b98:	6893      	ldr	r3, [r2, #8]
 8013b9a:	3b01      	subs	r3, #1
 8013b9c:	2b00      	cmp	r3, #0
 8013b9e:	b410      	push	{r4}
 8013ba0:	6093      	str	r3, [r2, #8]
 8013ba2:	da08      	bge.n	8013bb6 <__sfputc_r+0x1e>
 8013ba4:	6994      	ldr	r4, [r2, #24]
 8013ba6:	42a3      	cmp	r3, r4
 8013ba8:	db01      	blt.n	8013bae <__sfputc_r+0x16>
 8013baa:	290a      	cmp	r1, #10
 8013bac:	d103      	bne.n	8013bb6 <__sfputc_r+0x1e>
 8013bae:	f85d 4b04 	ldr.w	r4, [sp], #4
 8013bb2:	f000 bb6d 	b.w	8014290 <__swbuf_r>
 8013bb6:	6813      	ldr	r3, [r2, #0]
 8013bb8:	1c58      	adds	r0, r3, #1
 8013bba:	6010      	str	r0, [r2, #0]
 8013bbc:	7019      	strb	r1, [r3, #0]
 8013bbe:	4608      	mov	r0, r1
 8013bc0:	f85d 4b04 	ldr.w	r4, [sp], #4
 8013bc4:	4770      	bx	lr

08013bc6 <__sfputs_r>:
 8013bc6:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8013bc8:	4606      	mov	r6, r0
 8013bca:	460f      	mov	r7, r1
 8013bcc:	4614      	mov	r4, r2
 8013bce:	18d5      	adds	r5, r2, r3
 8013bd0:	42ac      	cmp	r4, r5
 8013bd2:	d101      	bne.n	8013bd8 <__sfputs_r+0x12>
 8013bd4:	2000      	movs	r0, #0
 8013bd6:	e007      	b.n	8013be8 <__sfputs_r+0x22>
 8013bd8:	f814 1b01 	ldrb.w	r1, [r4], #1
 8013bdc:	463a      	mov	r2, r7
 8013bde:	4630      	mov	r0, r6
 8013be0:	f7ff ffda 	bl	8013b98 <__sfputc_r>
 8013be4:	1c43      	adds	r3, r0, #1
 8013be6:	d1f3      	bne.n	8013bd0 <__sfputs_r+0xa>
 8013be8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	...

08013bec <_vfiprintf_r>:
 8013bec:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8013bf0:	460d      	mov	r5, r1
 8013bf2:	b09d      	sub	sp, #116	@ 0x74
 8013bf4:	4614      	mov	r4, r2
 8013bf6:	4698      	mov	r8, r3
 8013bf8:	4606      	mov	r6, r0
 8013bfa:	b118      	cbz	r0, 8013c04 <_vfiprintf_r+0x18>
 8013bfc:	6a03      	ldr	r3, [r0, #32]
 8013bfe:	b90b      	cbnz	r3, 8013c04 <_vfiprintf_r+0x18>
 8013c00:	f7ff fd66 	bl	80136d0 <__sinit>
 8013c04:	6e6b      	ldr	r3, [r5, #100]	@ 0x64
 8013c06:	07d9      	lsls	r1, r3, #31
 8013c08:	d405      	bmi.n	8013c16 <_vfiprintf_r+0x2a>
 8013c0a:	89ab      	ldrh	r3, [r5, #12]
 8013c0c:	059a      	lsls	r2, r3, #22
 8013c0e:	d402      	bmi.n	8013c16 <_vfiprintf_r+0x2a>
 8013c10:	6da8      	ldr	r0, [r5, #88]	@ 0x58
 8013c12:	f7ff feb8 	bl	8013986 <__retarget_lock_acquire_recursive>
 8013c16:	89ab      	ldrh	r3, [r5, #12]
 8013c18:	071b      	lsls	r3, r3, #28
 8013c1a:	d501      	bpl.n	8013c20 <_vfiprintf_r+0x34>
 8013c1c:	692b      	ldr	r3, [r5, #16]
 8013c1e:	b99b      	cbnz	r3, 8013c48 <_vfiprintf_r+0x5c>
 8013c20:	4629      	mov	r1, r5
 8013c22:	4630      	mov	r0, r6
 8013c24:	f000 fb72 	bl	801430c <__swsetup_r>
 8013c28:	b170      	cbz	r0, 8013c48 <_vfiprintf_r+0x5c>
 8013c2a:	6e6b      	ldr	r3, [r5, #100]	@ 0x64
 8013c2c:	07dc      	lsls	r4, r3, #31
 8013c2e:	d504      	bpl.n	8013c3a <_vfiprintf_r+0x4e>
 8013c30:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
 8013c34:	b01d      	add	sp, #116	@ 0x74
 8013c36:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8013c3a:	89ab      	ldrh	r3, [r5, #12]
 8013c3c:	0598      	lsls	r0, r3, #22
 8013c3e:	d4f7      	bmi.n	8013c30 <_vfiprintf_r+0x44>
 8013c40:	6da8      	ldr	r0, [r5, #88]	@ 0x58
 8013c42:	f7ff fea1 	bl	8013988 <__retarget_lock_release_recursive>
 8013c46:	e7f3      	b.n	8013c30 <_vfiprintf_r+0x44>
 8013c48:	2300      	movs	r3, #0
 8013c4a:	9309      	str	r3, [sp, #36]	@ 0x24
 8013c4c:	2320      	movs	r3, #32
 8013c4e:	f88d 3029 	strb.w	r3, [sp, #41]	@ 0x29
 8013c52:	f8cd 800c 	str.w	r8, [sp, #12]
 8013c56:	2330      	movs	r3, #48	@ 0x30
 8013c58:	f8df 81ac 	ldr.w	r8, [pc, #428]	@ 8013e08 <_vfiprintf_r+0x21c>
 8013c5c:	f88d 302a 	strb.w	r3, [sp, #42]	@ 0x2a
 8013c60:	f04f 0901 	mov.w	r9, #1
 8013c64:	4623      	mov	r3, r4
 8013c66:	469a      	mov	sl, r3
 8013c68:	f813 2b01 	ldrb.w	r2, [r3], #1
 8013c6c:	b10a      	cbz	r2, 8013c72 <_vfiprintf_r+0x86>
 8013c6e:	2a25      	cmp	r2, #37	@ 0x25
 8013c70:	d1f9      	bne.n	8013c66 <_vfiprintf_r+0x7a>
 8013c72:	ebba 0b04 	subs.w	fp, sl, r4
 8013c76:	d00b      	beq.n	8013c90 <_vfiprintf_r+0xa4>
 8013c78:	465b      	mov	r3, fp
 8013c7a:	4622      	mov	r2, r4
 8013c7c:	4629      	mov	r1, r5
 8013c7e:	4630      	mov	r0, r6
 8013c80:	f7ff ffa1 	bl	8013bc6 <__sfputs_r>
 8013c84:	3001      	adds	r0, #1
 8013c86:	f000 80a7 	beq.w	8013dd8 <_vfiprintf_r+0x1ec>
 8013c8a:	9a09      	ldr	r2, [sp, #36]	@ 0x24
 8013c8c:	445a      	add	r2, fp
 8013c8e:	9209      	str	r2, [sp, #36]	@ 0x24
 8013c90:	f89a 3000 	ldrb.w	r3, [sl]
 8013c94:	2b00      	cmp	r3, #0
 8013c96:	f000 809f 	beq.w	8013dd8 <_vfiprintf_r+0x1ec>
 8013c9a:	2300      	movs	r3, #0
 8013c9c:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8013ca0:	e9cd 2305 	strd	r2, r3, [sp, #20]
 8013ca4:	f10a 0a01 	add.w	sl, sl, #1
 8013ca8:	9304      	str	r3, [sp, #16]
 8013caa:	9307      	str	r3, [sp, #28]
 8013cac:	f88d 3053 	strb.w	r3, [sp, #83]	@ 0x53
 8013cb0:	931a      	str	r3, [sp, #104]	@ 0x68
 8013cb2:	4654      	mov	r4, sl
 8013cb4:	2205      	movs	r2, #5
 8013cb6:	f814 1b01 	ldrb.w	r1, [r4], #1
 8013cba:	4853      	ldr	r0, [pc, #332]	@ (8013e08 <_vfiprintf_r+0x21c>)
 8013cbc:	f7ec fb10 	bl	80002e0 <memchr>
 8013cc0:	9a04      	ldr	r2, [sp, #16]
 8013cc2:	b9d8      	cbnz	r0, 8013cfc <_vfiprintf_r+0x110>
 8013cc4:	06d1      	lsls	r1, r2, #27
 8013cc6:	bf44      	itt	mi
 8013cc8:	2320      	movmi	r3, #32
 8013cca:	f88d 3053 	strbmi.w	r3, [sp, #83]	@ 0x53
 8013cce:	0713      	lsls	r3, r2, #28
 8013cd0:	bf44      	itt	mi
 8013cd2:	232b      	movmi	r3, #43	@ 0x2b
 8013cd4:	f88d 3053 	strbmi.w	r3, [sp, #83]	@ 0x53
 8013cd8:	f89a 3000 	ldrb.w	r3, [sl]
 8013cdc:	2b2a      	cmp	r3, #42	@ 0x2a
 8013cde:	d015      	beq.n	8013d0c <_vfiprintf_r+0x120>
 8013ce0:	9a07      	ldr	r2, [sp, #28]
 8013ce2:	4654      	mov	r4, sl
 8013ce4:	2000      	movs	r0, #0
 8013ce6:	f04f 0c0a 	mov.w	ip, #10
 8013cea:	4621      	mov	r1, r4
 8013cec:	f811 3b01 	ldrb.w	r3, [r1], #1
 8013cf0:	3b30      	subs	r3, #48	@ 0x30
 8013cf2:	2b09      	cmp	r3, #9
 8013cf4:	d94b      	bls.n	8013d8e <_vfiprintf_r+0x1a2>
 8013cf6:	b1b0      	cbz	r0, 8013d26 <_vfiprintf_r+0x13a>
 8013cf8:	9207      	str	r2, [sp, #28]
 8013cfa:	e014      	b.n	8013d26 <_vfiprintf_r+0x13a>
 8013cfc:	eba0 0308 	sub.w	r3, r0, r8
 8013d00:	fa09 f303 	lsl.w	r3, r9, r3
 8013d04:	4313      	orrs	r3, r2
 8013d06:	9304      	str	r3, [sp, #16]
 8013d08:	46a2      	mov	sl, r4
 8013d0a:	e7d2      	b.n	8013cb2 <_vfiprintf_r+0xc6>
 8013d0c:	9b03      	ldr	r3, [sp, #12]
 8013d0e:	1d19      	adds	r1, r3, #4
 8013d10:	681b      	ldr	r3, [r3, #0]
 8013d12:	9103      	str	r1, [sp, #12]
 8013d14:	2b00      	cmp	r3, #0
 8013d16:	bfbb      	ittet	lt
 8013d18:	425b      	neglt	r3, r3
 8013d1a:	f042 0202 	orrlt.w	r2, r2, #2
 8013d1e:	9307      	strge	r3, [sp, #28]
 8013d20:	9307      	strlt	r3, [sp, #28]
 8013d22:	bfb8      	it	lt
 8013d24:	9204      	strlt	r2, [sp, #16]
 8013d26:	7823      	ldrb	r3, [r4, #0]
 8013d28:	2b2e      	cmp	r3, #46	@ 0x2e
 8013d2a:	d10a      	bne.n	8013d42 <_vfiprintf_r+0x156>
 8013d2c:	7863      	ldrb	r3, [r4, #1]
 8013d2e:	2b2a      	cmp	r3, #42	@ 0x2a
 8013d30:	d132      	bne.n	8013d98 <_vfiprintf_r+0x1ac>
 8013d32:	9b03      	ldr	r3, [sp, #12]
 8013d34:	1d1a      	adds	r2, r3, #4
 8013d36:	681b      	ldr	r3, [r3, #0]
 8013d38:	9203      	str	r2, [sp, #12]
 8013d3a:	ea43 73e3 	orr.w	r3, r3, r3, asr #31
 8013d3e:	3402      	adds	r4, #2
 8013d40:	9305      	str	r3, [sp, #20]
 8013d42:	f8df a0d4 	ldr.w	sl, [pc, #212]	@ 8013e18 <_vfiprintf_r+0x22c>
 8013d46:	7821      	ldrb	r1, [r4, #0]
 8013d48:	2203      	movs	r2, #3
 8013d4a:	4650      	mov	r0, sl
 8013d4c:	f7ec fac8 	bl	80002e0 <memchr>
 8013d50:	b138      	cbz	r0, 8013d62 <_vfiprintf_r+0x176>
 8013d52:	9b04      	ldr	r3, [sp, #16]
 8013d54:	eba0 000a 	sub.w	r0, r0, sl
 8013d58:	2240      	movs	r2, #64	@ 0x40
 8013d5a:	4082      	lsls	r2, r0
 8013d5c:	4313      	orrs	r3, r2
 8013d5e:	3401      	adds	r4, #1
 8013d60:	9304      	str	r3, [sp, #16]
 8013d62:	f814 1b01 	ldrb.w	r1, [r4], #1
 8013d66:	4829      	ldr	r0, [pc, #164]	@ (8013e0c <_vfiprintf_r+0x220>)
 8013d68:	f88d 1028 	strb.w	r1, [sp, #40]	@ 0x28
 8013d6c:	2206      	movs	r2, #6
 8013d6e:	f7ec fab7 	bl	80002e0 <memchr>
 8013d72:	2800      	cmp	r0, #0
 8013d74:	d03f      	beq.n	8013df6 <_vfiprintf_r+0x20a>
 8013d76:	4b26      	ldr	r3, [pc, #152]	@ (8013e10 <_vfiprintf_r+0x224>)
 8013d78:	bb1b      	cbnz	r3, 8013dc2 <_vfiprintf_r+0x1d6>
 8013d7a:	9b03      	ldr	r3, [sp, #12]
 8013d7c:	3307      	adds	r3, #7
 8013d7e:	f023 0307 	bic.w	r3, r3, #7
 8013d82:	3308      	adds	r3, #8
 8013d84:	9303      	str	r3, [sp, #12]
 8013d86:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 8013d88:	443b      	add	r3, r7
 8013d8a:	9309      	str	r3, [sp, #36]	@ 0x24
 8013d8c:	e76a      	b.n	8013c64 <_vfiprintf_r+0x78>
 8013d8e:	fb0c 3202 	mla	r2, ip, r2, r3
 8013d92:	460c      	mov	r4, r1
 8013d94:	2001      	movs	r0, #1
 8013d96:	e7a8      	b.n	8013cea <_vfiprintf_r+0xfe>
 8013d98:	2300      	movs	r3, #0
 8013d9a:	3401      	adds	r4, #1
 8013d9c:	9305      	str	r3, [sp, #20]
 8013d9e:	4619      	mov	r1, r3
 8013da0:	f04f 0c0a 	mov.w	ip, #10
 8013da4:	4620      	mov	r0, r4
 8013da6:	f810 2b01 	ldrb.w	r2, [r0], #1
 8013daa:	3a30      	subs	r2, #48	@ 0x30
 8013dac:	2a09      	cmp	r2, #9
 8013dae:	d903      	bls.n	8013db8 <_vfiprintf_r+0x1cc>
 8013db0:	2b00      	cmp	r3, #0
 8013db2:	d0c6      	beq.n	8013d42 <_vfiprintf_r+0x156>
 8013db4:	9105      	str	r1, [sp, #20]
 8013db6:	e7c4      	b.n	8013d42 <_vfiprintf_r+0x156>
 8013db8:	fb0c 2101 	mla	r1, ip, r1, r2
 8013dbc:	4604      	mov	r4, r0
 8013dbe:	2301      	movs	r3, #1
 8013dc0:	e7f0      	b.n	8013da4 <_vfiprintf_r+0x1b8>
 8013dc2:	ab03      	add	r3, sp, #12
 8013dc4:	9300      	str	r3, [sp, #0]
 8013dc6:	462a      	mov	r2, r5
 8013dc8:	4b12      	ldr	r3, [pc, #72]	@ (8013e14 <_vfiprintf_r+0x228>)
 8013dca:	a904      	add	r1, sp, #16
 8013dcc:	4630      	mov	r0, r6
 8013dce:	f3af 8000 	nop.w
 8013dd2:	4607      	mov	r7, r0
 8013dd4:	1c78      	adds	r0, r7, #1
 8013dd6:	d1d6      	bne.n	8013d86 <_vfiprintf_r+0x19a>
 8013dd8:	6e6b      	ldr	r3, [r5, #100]	@ 0x64
 8013dda:	07d9      	lsls	r1, r3, #31
 8013ddc:	d405      	bmi.n	8013dea <_vfiprintf_r+0x1fe>
 8013dde:	89ab      	ldrh	r3, [r5, #12]
 8013de0:	059a      	lsls	r2, r3, #22
 8013de2:	d402      	bmi.n	8013dea <_vfiprintf_r+0x1fe>
 8013de4:	6da8      	ldr	r0, [r5, #88]	@ 0x58
 8013de6:	f7ff fdcf 	bl	8013988 <__retarget_lock_release_recursive>
 8013dea:	89ab      	ldrh	r3, [r5, #12]
 8013dec:	065b      	lsls	r3, r3, #25
 8013dee:	f53f af1f 	bmi.w	8013c30 <_vfiprintf_r+0x44>
 8013df2:	9809      	ldr	r0, [sp, #36]	@ 0x24
 8013df4:	e71e      	b.n	8013c34 <_vfiprintf_r+0x48>
 8013df6:	ab03      	add	r3, sp, #12
 8013df8:	9300      	str	r3, [sp, #0]
 8013dfa:	462a      	mov	r2, r5
 8013dfc:	4b05      	ldr	r3, [pc, #20]	@ (8013e14 <_vfiprintf_r+0x228>)
 8013dfe:	a904      	add	r1, sp, #16
 8013e00:	4630      	mov	r0, r6
 8013e02:	f000 f879 	bl	8013ef8 <_printf_i>
 8013e06:	e7e4      	b.n	8013dd2 <_vfiprintf_r+0x1e6>
 8013e08:	08014624 	.word	0x08014624
 8013e0c:	0801462e 	.word	0x0801462e
 8013e10:	00000000 	.word	0x00000000
 8013e14:	08013bc7 	.word	0x08013bc7
 8013e18:	0801462a 	.word	0x0801462a

08013e1c <_printf_common>:
 8013e1c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8013e20:	4616      	mov	r6, r2
 8013e22:	4698      	mov	r8, r3
 8013e24:	688a      	ldr	r2, [r1, #8]
 8013e26:	690b      	ldr	r3, [r1, #16]
 8013e28:	f8dd 9020 	ldr.w	r9, [sp, #32]
 8013e2c:	4293      	cmp	r3, r2
 8013e2e:	bfb8      	it	lt
 8013e30:	4613      	movlt	r3, r2
 8013e32:	6033      	str	r3, [r6, #0]
 8013e34:	f891 2043 	ldrb.w	r2, [r1, #67]	@ 0x43
 8013e38:	4607      	mov	r7, r0
 8013e3a:	460c      	mov	r4, r1
 8013e3c:	b10a      	cbz	r2, 8013e42 <_printf_common+0x26>
 8013e3e:	3301      	adds	r3, #1
 8013e40:	6033      	str	r3, [r6, #0]
 8013e42:	6823      	ldr	r3, [r4, #0]
 8013e44:	0699      	lsls	r1, r3, #26
 8013e46:	bf42      	ittt	mi
 8013e48:	6833      	ldrmi	r3, [r6, #0]
 8013e4a:	3302      	addmi	r3, #2
 8013e4c:	6033      	strmi	r3, [r6, #0]
 8013e4e:	6825      	ldr	r5, [r4, #0]
 8013e50:	f015 0506 	ands.w	r5, r5, #6
 8013e54:	d106      	bne.n	8013e64 <_printf_common+0x48>
 8013e56:	f104 0a19 	add.w	sl, r4, #25
 8013e5a:	68e3      	ldr	r3, [r4, #12]
 8013e5c:	6832      	ldr	r2, [r6, #0]
 8013e5e:	1a9b      	subs	r3, r3, r2
 8013e60:	42ab      	cmp	r3, r5
 8013e62:	dc26      	bgt.n	8013eb2 <_printf_common+0x96>
 8013e64:	f894 3043 	ldrb.w	r3, [r4, #67]	@ 0x43
 8013e68:	6822      	ldr	r2, [r4, #0]
 8013e6a:	3b00      	subs	r3, #0
 8013e6c:	bf18      	it	ne
 8013e6e:	2301      	movne	r3, #1
 8013e70:	0692      	lsls	r2, r2, #26
 8013e72:	d42b      	bmi.n	8013ecc <_printf_common+0xb0>
 8013e74:	f104 0243 	add.w	r2, r4, #67	@ 0x43
 8013e78:	4641      	mov	r1, r8
 8013e7a:	4638      	mov	r0, r7
 8013e7c:	47c8      	blx	r9
 8013e7e:	3001      	adds	r0, #1
 8013e80:	d01e      	beq.n	8013ec0 <_printf_common+0xa4>
 8013e82:	6823      	ldr	r3, [r4, #0]
 8013e84:	6922      	ldr	r2, [r4, #16]
 8013e86:	f003 0306 	and.w	r3, r3, #6
 8013e8a:	2b04      	cmp	r3, #4
 8013e8c:	bf02      	ittt	eq
 8013e8e:	68e5      	ldreq	r5, [r4, #12]
 8013e90:	6833      	ldreq	r3, [r6, #0]
 8013e92:	1aed      	subeq	r5, r5, r3
 8013e94:	68a3      	ldr	r3, [r4, #8]
 8013e96:	bf0c      	ite	eq
 8013e98:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
 8013e9c:	2500      	movne	r5, #0
 8013e9e:	4293      	cmp	r3, r2
 8013ea0:	bfc4      	itt	gt
 8013ea2:	1a9b      	subgt	r3, r3, r2
 8013ea4:	18ed      	addgt	r5, r5, r3
 8013ea6:	2600      	movs	r6, #0
 8013ea8:	341a      	adds	r4, #26
 8013eaa:	42b5      	cmp	r5, r6
 8013eac:	d11a      	bne.n	8013ee4 <_printf_common+0xc8>
 8013eae:	2000      	movs	r0, #0
 8013eb0:	e008      	b.n	8013ec4 <_printf_common+0xa8>
 8013eb2:	2301      	movs	r3, #1
 8013eb4:	4652      	mov	r2, sl
 8013eb6:	4641      	mov	r1, r8
 8013eb8:	4638      	mov	r0, r7
 8013eba:	47c8      	blx	r9
 8013ebc:	3001      	adds	r0, #1
 8013ebe:	d103      	bne.n	8013ec8 <_printf_common+0xac>
 8013ec0:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
 8013ec4:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8013ec8:	3501      	adds	r5, #1
 8013eca:	e7c6      	b.n	8013e5a <_printf_common+0x3e>
 8013ecc:	18e1      	adds	r1, r4, r3
 8013ece:	1c5a      	adds	r2, r3, #1
 8013ed0:	2030      	movs	r0, #48	@ 0x30
 8013ed2:	f881 0043 	strb.w	r0, [r1, #67]	@ 0x43
 8013ed6:	4422      	add	r2, r4
 8013ed8:	f894 1045 	ldrb.w	r1, [r4, #69]	@ 0x45
 8013edc:	f882 1043 	strb.w	r1, [r2, #67]	@ 0x43
 8013ee0:	3302      	adds	r3, #2
 8013ee2:	e7c7      	b.n	8013e74 <_printf_common+0x58>
 8013ee4:	2301      	movs	r3, #1
 8013ee6:	4622      	mov	r2, r4
 8013ee8:	4641      	mov	r1, r8
 8013eea:	4638      	mov	r0, r7
 8013eec:	47c8      	blx	r9
 8013eee:	3001      	adds	r0, #1
 8013ef0:	d0e6      	beq.n	8013ec0 <_printf_common+0xa4>
 8013ef2:	3601      	adds	r6, #1
 8013ef4:	e7d9      	b.n	8013eaa <_printf_common+0x8e>
	...

08013ef8 <_printf_i>:
 8013ef8:	e92d 47ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
 8013efc:	7e0f      	ldrb	r7, [r1, #24]
 8013efe:	9e0c      	ldr	r6, [sp, #48]	@ 0x30
 8013f00:	2f78      	cmp	r7, #120	@ 0x78
 8013f02:	4691      	mov	r9, r2
 8013f04:	4680      	mov	r8, r0
 8013f06:	460c      	mov	r4, r1
 8013f08:	469a      	mov	sl, r3
 8013f0a:	f101 0243 	add.w	r2, r1, #67	@ 0x43
 8013f0e:	d807      	bhi.n	8013f20 <_printf_i+0x28>
 8013f10:	2f62      	cmp	r7, #98	@ 0x62
 8013f12:	d80a      	bhi.n	8013f2a <_printf_i+0x32>
 8013f14:	2f00      	cmp	r7, #0
 8013f16:	f000 80d2 	beq.w	80140be <_printf_i+0x1c6>
 8013f1a:	2f58      	cmp	r7, #88	@ 0x58
 8013f1c:	f000 80b9 	beq.w	8014092 <_printf_i+0x19a>
 8013f20:	f104 0642 	add.w	r6, r4, #66	@ 0x42
 8013f24:	f884 7042 	strb.w	r7, [r4, #66]	@ 0x42
 8013f28:	e03a      	b.n	8013fa0 <_printf_i+0xa8>
 8013f2a:	f1a7 0363 	sub.w	r3, r7, #99	@ 0x63
 8013f2e:	2b15      	cmp	r3, #21
 8013f30:	d8f6      	bhi.n	8013f20 <_printf_i+0x28>
 8013f32:	a101      	add	r1, pc, #4	@ (adr r1, 8013f38 <_printf_i+0x40>)
 8013f34:	f851 f023 	ldr.w	pc, [r1, r3, lsl #2]
 8013f38:	08013f91 	.word	0x08013f91
 8013f3c:	08013fa5 	.word	0x08013fa5
 8013f40:	08013f21 	.word	0x08013f21
 8013f44:	08013f21 	.word	0x08013f21
 8013f48:	08013f21 	.word	0x08013f21
 8013f4c:	08013f21 	.word	0x08013f21
 8013f50:	08013fa5 	.word	0x08013fa5
 8013f54:	08013f21 	.word	0x08013f21
 8013f58:	08013f21 	.word	0x08013f21
 8013f5c:	08013f21 	.word	0x08013f21
 8013f60:	08013f21 	.word	0x08013f21
 8013f64:	080140a5 	.word	0x080140a5
 8013f68:	08013fcf 	.word	0x08013fcf
 8013f6c:	0801405f 	.word	0x0801405f
 8013f70:	08013f21 	.word	0x08013f21
 8013f74:	08013f21 	.word	0x08013f21
 8013f78:	080140c7 	.word	0x080140c7
 8013f7c:	08013f21 	.word	0x08013f21
 8013f80:	08013fcf 	.word	0x08013fcf
 8013f84:	08013f21 	.word	0x08013f21
 8013f88:	08013f21 	.word	0x08013f21
 8013f8c:	08014067 	.word	0x08014067
 8013f90:	6833      	ldr	r3, [r6, #0]
 8013f92:	1d1a      	adds	r2, r3, #4
 8013f94:	681b      	ldr	r3, [r3, #0]
 8013f96:	6032      	str	r2, [r6, #0]
 8013f98:	f104 0642 	add.w	r6, r4, #66	@ 0x42
 8013f9c:	f884 3042 	strb.w	r3, [r4, #66]	@ 0x42
 8013fa0:	2301      	movs	r3, #1
 8013fa2:	e09d      	b.n	80140e0 <_printf_i+0x1e8>
 8013fa4:	6833      	ldr	r3, [r6, #0]
 8013fa6:	6820      	ldr	r0, [r4, #0]
 8013fa8:	1d19      	adds	r1, r3, #4
 8013faa:	6031      	str	r1, [r6, #0]
 8013fac:	0606      	lsls	r6, r0, #24
 8013fae:	d501      	bpl.n	8013fb4 <_printf_i+0xbc>
 8013fb0:	681d      	ldr	r5, [r3, #0]
 8013fb2:	e003      	b.n	8013fbc <_printf_i+0xc4>
 8013fb4:	0645      	lsls	r5, r0, #25
 8013fb6:	d5fb      	bpl.n	8013fb0 <_printf_i+0xb8>
 8013fb8:	f9b3 5000 	ldrsh.w	r5, [r3]
 8013fbc:	2d00      	cmp	r5, #0
 8013fbe:	da03      	bge.n	8013fc8 <_printf_i+0xd0>
 8013fc0:	232d      	movs	r3, #45	@ 0x2d
 8013fc2:	426d      	negs	r5, r5
 8013fc4:	f884 3043 	strb.w	r3, [r4, #67]	@ 0x43
 8013fc8:	4859      	ldr	r0, [pc, #356]	@ (8014130 <_printf_i+0x238>)
 8013fca:	230a      	movs	r3, #10
 8013fcc:	e011      	b.n	8013ff2 <_printf_i+0xfa>
 8013fce:	6821      	ldr	r1, [r4, #0]
 8013fd0:	6833      	ldr	r3, [r6, #0]
 8013fd2:	0608      	lsls	r0, r1, #24
 8013fd4:	f853 5b04 	ldr.w	r5, [r3], #4
 8013fd8:	d402      	bmi.n	8013fe0 <_printf_i+0xe8>
 8013fda:	0649      	lsls	r1, r1, #25
 8013fdc:	bf48      	it	mi
 8013fde:	b2ad      	uxthmi	r5, r5
 8013fe0:	2f6f      	cmp	r7, #111	@ 0x6f
 8013fe2:	4853      	ldr	r0, [pc, #332]	@ (8014130 <_printf_i+0x238>)
 8013fe4:	6033      	str	r3, [r6, #0]
 8013fe6:	bf14      	ite	ne
 8013fe8:	230a      	movne	r3, #10
 8013fea:	2308      	moveq	r3, #8
 8013fec:	2100      	movs	r1, #0
 8013fee:	f884 1043 	strb.w	r1, [r4, #67]	@ 0x43
 8013ff2:	6866      	ldr	r6, [r4, #4]
 8013ff4:	60a6      	str	r6, [r4, #8]
 8013ff6:	2e00      	cmp	r6, #0
 8013ff8:	bfa2      	ittt	ge
 8013ffa:	6821      	ldrge	r1, [r4, #0]
 8013ffc:	f021 0104 	bicge.w	r1, r1, #4
 8014000:	6021      	strge	r1, [r4, #0]
 8014002:	b90d      	cbnz	r5, 8014008 <_printf_i+0x110>
 8014004:	2e00      	cmp	r6, #0
 8014006:	d04b      	beq.n	80140a0 <_printf_i+0x1a8>
 8014008:	4616      	mov	r6, r2
 801400a:	fbb5 f1f3 	udiv	r1, r5, r3
 801400e:	fb03 5711 	mls	r7, r3, r1, r5
 8014012:	5dc7      	ldrb	r7, [r0, r7]
 8014014:	f806 7d01 	strb.w	r7, [r6, #-1]!
 8014018:	462f      	mov	r7, r5
 801401a:	42bb      	cmp	r3, r7
 801401c:	460d      	mov	r5, r1
 801401e:	d9f4      	bls.n	801400a <_printf_i+0x112>
 8014020:	2b08      	cmp	r3, #8
 8014022:	d10b      	bne.n	801403c <_printf_i+0x144>
 8014024:	6823      	ldr	r3, [r4, #0]
 8014026:	07df      	lsls	r7, r3, #31
 8014028:	d508      	bpl.n	801403c <_printf_i+0x144>
 801402a:	6923      	ldr	r3, [r4, #16]
 801402c:	6861      	ldr	r1, [r4, #4]
 801402e:	4299      	cmp	r1, r3
 8014030:	bfde      	ittt	le
 8014032:	2330      	movle	r3, #48	@ 0x30
 8014034:	f806 3c01 	strble.w	r3, [r6, #-1]
 8014038:	f106 36ff 	addle.w	r6, r6, #4294967295	@ 0xffffffff
 801403c:	1b92      	subs	r2, r2, r6
 801403e:	6122      	str	r2, [r4, #16]
 8014040:	f8cd a000 	str.w	sl, [sp]
 8014044:	464b      	mov	r3, r9
 8014046:	aa03      	add	r2, sp, #12
 8014048:	4621      	mov	r1, r4
 801404a:	4640      	mov	r0, r8
 801404c:	f7ff fee6 	bl	8013e1c <_printf_common>
 8014050:	3001      	adds	r0, #1
 8014052:	d14a      	bne.n	80140ea <_printf_i+0x1f2>
 8014054:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
 8014058:	b004      	add	sp, #16
 801405a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 801405e:	6823      	ldr	r3, [r4, #0]
 8014060:	f043 0320 	orr.w	r3, r3, #32
 8014064:	6023      	str	r3, [r4, #0]
 8014066:	4833      	ldr	r0, [pc, #204]	@ (8014134 <_printf_i+0x23c>)
 8014068:	2778      	movs	r7, #120	@ 0x78
 801406a:	f884 7045 	strb.w	r7, [r4, #69]	@ 0x45
 801406e:	6823      	ldr	r3, [r4, #0]
 8014070:	6831      	ldr	r1, [r6, #0]
 8014072:	061f      	lsls	r7, r3, #24
 8014074:	f851 5b04 	ldr.w	r5, [r1], #4
 8014078:	d402      	bmi.n	8014080 <_printf_i+0x188>
 801407a:	065f      	lsls	r7, r3, #25
 801407c:	bf48      	it	mi
 801407e:	b2ad      	uxthmi	r5, r5
 8014080:	6031      	str	r1, [r6, #0]
 8014082:	07d9      	lsls	r1, r3, #31
 8014084:	bf44      	itt	mi
 8014086:	f043 0320 	orrmi.w	r3, r3, #32
 801408a:	6023      	strmi	r3, [r4, #0]
 801408c:	b11d      	cbz	r5, 8014096 <_printf_i+0x19e>
 801408e:	2310      	movs	r3, #16
 8014090:	e7ac      	b.n	8013fec <_printf_i+0xf4>
 8014092:	4827      	ldr	r0, [pc, #156]	@ (8014130 <_printf_i+0x238>)
 8014094:	e7e9      	b.n	801406a <_printf_i+0x172>
 8014096:	6823      	ldr	r3, [r4, #0]
 8014098:	f023 0320 	bic.w	r3, r3, #32
 801409c:	6023      	str	r3, [r4, #0]
 801409e:	e7f6      	b.n	801408e <_printf_i+0x196>
 80140a0:	4616      	mov	r6, r2
 80140a2:	e7bd      	b.n	8014020 <_printf_i+0x128>
 80140a4:	6833      	ldr	r3, [r6, #0]
 80140a6:	6825      	ldr	r5, [r4, #0]
 80140a8:	6961      	ldr	r1, [r4, #20]
 80140aa:	1d18      	adds	r0, r3, #4
 80140ac:	6030      	str	r0, [r6, #0]
 80140ae:	062e      	lsls	r6, r5, #24
 80140b0:	681b      	ldr	r3, [r3, #0]
 80140b2:	d501      	bpl.n	80140b8 <_printf_i+0x1c0>
 80140b4:	6019      	str	r1, [r3, #0]
 80140b6:	e002      	b.n	80140be <_printf_i+0x1c6>
 80140b8:	0668      	lsls	r0, r5, #25
 80140ba:	d5fb      	bpl.n	80140b4 <_printf_i+0x1bc>
 80140bc:	8019      	strh	r1, [r3, #0]
 80140be:	2300      	movs	r3, #0
 80140c0:	6123      	str	r3, [r4, #16]
 80140c2:	4616      	mov	r6, r2
 80140c4:	e7bc      	b.n	8014040 <_printf_i+0x148>
 80140c6:	6833      	ldr	r3, [r6, #0]
 80140c8:	1d1a      	adds	r2, r3, #4
 80140ca:	6032      	str	r2, [r6, #0]
 80140cc:	681e      	ldr	r6, [r3, #0]
 80140ce:	6862      	ldr	r2, [r4, #4]
 80140d0:	2100      	movs	r1, #0
 80140d2:	4630      	mov	r0, r6
 80140d4:	f7ec f904 	bl	80002e0 <memchr>
 80140d8:	b108      	cbz	r0, 80140de <_printf_i+0x1e6>
 80140da:	1b80      	subs	r0, r0, r6
 80140dc:	6060      	str	r0, [r4, #4]
 80140de:	6863      	ldr	r3, [r4, #4]
 80140e0:	6123      	str	r3, [r4, #16]
 80140e2:	2300      	movs	r3, #0
 80140e4:	f884 3043 	strb.w	r3, [r4, #67]	@ 0x43
 80140e8:	e7aa      	b.n	8014040 <_printf_i+0x148>
 80140ea:	6923      	ldr	r3, [r4, #16]
 80140ec:	4632      	mov	r2, r6
 80140ee:	4649      	mov	r1, r9
 80140f0:	4640      	mov	r0, r8
 80140f2:	47d0      	blx	sl
 80140f4:	3001      	adds	r0, #1
 80140f6:	d0ad      	beq.n	8014054 <_printf_i+0x15c>
 80140f8:	6823      	ldr	r3, [r4, #0]
 80140fa:	079b      	lsls	r3, r3, #30
 80140fc:	d413      	bmi.n	8014126 <_printf_i+0x22e>
 80140fe:	68e0      	ldr	r0, [r4, #12]
 8014100:	9b03      	ldr	r3, [sp, #12]
 8014102:	4298      	cmp	r0, r3
 8014104:	bfb8      	it	lt
 8014106:	4618      	movlt	r0, r3
 8014108:	e7a6      	b.n	8014058 <_printf_i+0x160>
 801410a:	2301      	movs	r3, #1
 801410c:	4632      	mov	r2, r6
 801410e:	4649      	mov	r1, r9
 8014110:	4640      	mov	r0, r8
 8014112:	47d0      	blx	sl
 8014114:	3001      	adds	r0, #1
 8014116:	d09d      	beq.n	8014054 <_printf_i+0x15c>
 8014118:	3501      	adds	r5, #1
 801411a:	68e3      	ldr	r3, [r4, #12]
 801411c:	9903      	ldr	r1, [sp, #12]
 801411e:	1a5b      	subs	r3, r3, r1
 8014120:	42ab      	cmp	r3, r5
 8014122:	dcf2      	bgt.n	801410a <_printf_i+0x212>
 8014124:	e7eb      	b.n	80140fe <_printf_i+0x206>
 8014126:	2500      	movs	r5, #0
 8014128:	f104 0619 	add.w	r6, r4, #25
 801412c:	e7f5      	b.n	801411a <_printf_i+0x222>
 801412e:	bf00      	nop
 8014130:	08014635 	.word	0x08014635
 8014134:	08014646 	.word	0x08014646

08014138 <__sflush_r>:
 8014138:	f9b1 200c 	ldrsh.w	r2, [r1, #12]
 801413c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8014140:	0716      	lsls	r6, r2, #28
 8014142:	4605      	mov	r5, r0
 8014144:	460c      	mov	r4, r1
 8014146:	d454      	bmi.n	80141f2 <__sflush_r+0xba>
 8014148:	684b      	ldr	r3, [r1, #4]
 801414a:	2b00      	cmp	r3, #0
 801414c:	dc02      	bgt.n	8014154 <__sflush_r+0x1c>
 801414e:	6c0b      	ldr	r3, [r1, #64]	@ 0x40
 8014150:	2b00      	cmp	r3, #0
 8014152:	dd48      	ble.n	80141e6 <__sflush_r+0xae>
 8014154:	6ae6      	ldr	r6, [r4, #44]	@ 0x2c
 8014156:	2e00      	cmp	r6, #0
 8014158:	d045      	beq.n	80141e6 <__sflush_r+0xae>
 801415a:	2300      	movs	r3, #0
 801415c:	f412 5280 	ands.w	r2, r2, #4096	@ 0x1000
 8014160:	682f      	ldr	r7, [r5, #0]
 8014162:	6a21      	ldr	r1, [r4, #32]
 8014164:	602b      	str	r3, [r5, #0]
 8014166:	d030      	beq.n	80141ca <__sflush_r+0x92>
 8014168:	6d62      	ldr	r2, [r4, #84]	@ 0x54
 801416a:	89a3      	ldrh	r3, [r4, #12]
 801416c:	0759      	lsls	r1, r3, #29
 801416e:	d505      	bpl.n	801417c <__sflush_r+0x44>
 8014170:	6863      	ldr	r3, [r4, #4]
 8014172:	1ad2      	subs	r2, r2, r3
 8014174:	6b63      	ldr	r3, [r4, #52]	@ 0x34
 8014176:	b10b      	cbz	r3, 801417c <__sflush_r+0x44>
 8014178:	6c23      	ldr	r3, [r4, #64]	@ 0x40
 801417a:	1ad2      	subs	r2, r2, r3
 801417c:	2300      	movs	r3, #0
 801417e:	6ae6      	ldr	r6, [r4, #44]	@ 0x2c
 8014180:	6a21      	ldr	r1, [r4, #32]
 8014182:	4628      	mov	r0, r5
 8014184:	47b0      	blx	r6
 8014186:	1c43      	adds	r3, r0, #1
 8014188:	89a3      	ldrh	r3, [r4, #12]
 801418a:	d106      	bne.n	801419a <__sflush_r+0x62>
 801418c:	6829      	ldr	r1, [r5, #0]
 801418e:	291d      	cmp	r1, #29
 8014190:	d82b      	bhi.n	80141ea <__sflush_r+0xb2>
 8014192:	4a2a      	ldr	r2, [pc, #168]	@ (801423c <__sflush_r+0x104>)
 8014194:	410a      	asrs	r2, r1
 8014196:	07d6      	lsls	r6, r2, #31
 8014198:	d427      	bmi.n	80141ea <__sflush_r+0xb2>
 801419a:	2200      	movs	r2, #0
 801419c:	6062      	str	r2, [r4, #4]
 801419e:	04d9      	lsls	r1, r3, #19
 80141a0:	6922      	ldr	r2, [r4, #16]
 80141a2:	6022      	str	r2, [r4, #0]
 80141a4:	d504      	bpl.n	80141b0 <__sflush_r+0x78>
 80141a6:	1c42      	adds	r2, r0, #1
 80141a8:	d101      	bne.n	80141ae <__sflush_r+0x76>
 80141aa:	682b      	ldr	r3, [r5, #0]
 80141ac:	b903      	cbnz	r3, 80141b0 <__sflush_r+0x78>
 80141ae:	6560      	str	r0, [r4, #84]	@ 0x54
 80141b0:	6b61      	ldr	r1, [r4, #52]	@ 0x34
 80141b2:	602f      	str	r7, [r5, #0]
 80141b4:	b1b9      	cbz	r1, 80141e6 <__sflush_r+0xae>
 80141b6:	f104 0344 	add.w	r3, r4, #68	@ 0x44
 80141ba:	4299      	cmp	r1, r3
 80141bc:	d002      	beq.n	80141c4 <__sflush_r+0x8c>
 80141be:	4628      	mov	r0, r5
 80141c0:	f7ff fbf2 	bl	80139a8 <_free_r>
 80141c4:	2300      	movs	r3, #0
 80141c6:	6363      	str	r3, [r4, #52]	@ 0x34
 80141c8:	e00d      	b.n	80141e6 <__sflush_r+0xae>
 80141ca:	2301      	movs	r3, #1
 80141cc:	4628      	mov	r0, r5
 80141ce:	47b0      	blx	r6
 80141d0:	4602      	mov	r2, r0
 80141d2:	1c50      	adds	r0, r2, #1
 80141d4:	d1c9      	bne.n	801416a <__sflush_r+0x32>
 80141d6:	682b      	ldr	r3, [r5, #0]
 80141d8:	2b00      	cmp	r3, #0
 80141da:	d0c6      	beq.n	801416a <__sflush_r+0x32>
 80141dc:	2b1d      	cmp	r3, #29
 80141de:	d001      	beq.n	80141e4 <__sflush_r+0xac>
 80141e0:	2b16      	cmp	r3, #22
 80141e2:	d11e      	bne.n	8014222 <__sflush_r+0xea>
 80141e4:	602f      	str	r7, [r5, #0]
 80141e6:	2000      	movs	r0, #0
 80141e8:	e022      	b.n	8014230 <__sflush_r+0xf8>
 80141ea:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 80141ee:	b21b      	sxth	r3, r3
 80141f0:	e01b      	b.n	801422a <__sflush_r+0xf2>
 80141f2:	690f      	ldr	r7, [r1, #16]
 80141f4:	2f00      	cmp	r7, #0
 80141f6:	d0f6      	beq.n	80141e6 <__sflush_r+0xae>
 80141f8:	0793      	lsls	r3, r2, #30
 80141fa:	680e      	ldr	r6, [r1, #0]
 80141fc:	bf08      	it	eq
 80141fe:	694b      	ldreq	r3, [r1, #20]
 8014200:	600f      	str	r7, [r1, #0]
 8014202:	bf18      	it	ne
 8014204:	2300      	movne	r3, #0
 8014206:	eba6 0807 	sub.w	r8, r6, r7
 801420a:	608b      	str	r3, [r1, #8]
 801420c:	f1b8 0f00 	cmp.w	r8, #0
 8014210:	dde9      	ble.n	80141e6 <__sflush_r+0xae>
 8014212:	6a21      	ldr	r1, [r4, #32]
 8014214:	6aa6      	ldr	r6, [r4, #40]	@ 0x28
 8014216:	4643      	mov	r3, r8
 8014218:	463a      	mov	r2, r7
 801421a:	4628      	mov	r0, r5
 801421c:	47b0      	blx	r6
 801421e:	2800      	cmp	r0, #0
 8014220:	dc08      	bgt.n	8014234 <__sflush_r+0xfc>
 8014222:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8014226:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 801422a:	81a3      	strh	r3, [r4, #12]
 801422c:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
 8014230:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8014234:	4407      	add	r7, r0
 8014236:	eba8 0800 	sub.w	r8, r8, r0
 801423a:	e7e7      	b.n	801420c <__sflush_r+0xd4>
 801423c:	dfbffffe 	.word	0xdfbffffe

08014240 <_fflush_r>:
 8014240:	b538      	push	{r3, r4, r5, lr}
 8014242:	690b      	ldr	r3, [r1, #16]
 8014244:	4605      	mov	r5, r0
 8014246:	460c      	mov	r4, r1
 8014248:	b913      	cbnz	r3, 8014250 <_fflush_r+0x10>
 801424a:	2500      	movs	r5, #0
 801424c:	4628      	mov	r0, r5
 801424e:	bd38      	pop	{r3, r4, r5, pc}
 8014250:	b118      	cbz	r0, 801425a <_fflush_r+0x1a>
 8014252:	6a03      	ldr	r3, [r0, #32]
 8014254:	b90b      	cbnz	r3, 801425a <_fflush_r+0x1a>
 8014256:	f7ff fa3b 	bl	80136d0 <__sinit>
 801425a:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 801425e:	2b00      	cmp	r3, #0
 8014260:	d0f3      	beq.n	801424a <_fflush_r+0xa>
 8014262:	6e62      	ldr	r2, [r4, #100]	@ 0x64
 8014264:	07d0      	lsls	r0, r2, #31
 8014266:	d404      	bmi.n	8014272 <_fflush_r+0x32>
 8014268:	0599      	lsls	r1, r3, #22
 801426a:	d402      	bmi.n	8014272 <_fflush_r+0x32>
 801426c:	6da0      	ldr	r0, [r4, #88]	@ 0x58
 801426e:	f7ff fb8a 	bl	8013986 <__retarget_lock_acquire_recursive>
 8014272:	4628      	mov	r0, r5
 8014274:	4621      	mov	r1, r4
 8014276:	f7ff ff5f 	bl	8014138 <__sflush_r>
 801427a:	6e63      	ldr	r3, [r4, #100]	@ 0x64
 801427c:	07da      	lsls	r2, r3, #31
 801427e:	4605      	mov	r5, r0
 8014280:	d4e4      	bmi.n	801424c <_fflush_r+0xc>
 8014282:	89a3      	ldrh	r3, [r4, #12]
 8014284:	059b      	lsls	r3, r3, #22
 8014286:	d4e1      	bmi.n	801424c <_fflush_r+0xc>
 8014288:	6da0      	ldr	r0, [r4, #88]	@ 0x58
 801428a:	f7ff fb7d 	bl	8013988 <__retarget_lock_release_recursive>
 801428e:	e7dd      	b.n	801424c <_fflush_r+0xc>

08014290 <__swbuf_r>:
 8014290:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8014292:	460e      	mov	r6, r1
 8014294:	4614      	mov	r4, r2
 8014296:	4605      	mov	r5, r0
 8014298:	b118      	cbz	r0, 80142a2 <__swbuf_r+0x12>
 801429a:	6a03      	ldr	r3, [r0, #32]
 801429c:	b90b      	cbnz	r3, 80142a2 <__swbuf_r+0x12>
 801429e:	f7ff fa17 	bl	80136d0 <__sinit>
 80142a2:	69a3      	ldr	r3, [r4, #24]
 80142a4:	60a3      	str	r3, [r4, #8]
 80142a6:	89a3      	ldrh	r3, [r4, #12]
 80142a8:	071a      	lsls	r2, r3, #28
 80142aa:	d501      	bpl.n	80142b0 <__swbuf_r+0x20>
 80142ac:	6923      	ldr	r3, [r4, #16]
 80142ae:	b943      	cbnz	r3, 80142c2 <__swbuf_r+0x32>
 80142b0:	4621      	mov	r1, r4
 80142b2:	4628      	mov	r0, r5
 80142b4:	f000 f82a 	bl	801430c <__swsetup_r>
 80142b8:	b118      	cbz	r0, 80142c2 <__swbuf_r+0x32>
 80142ba:	f04f 37ff 	mov.w	r7, #4294967295	@ 0xffffffff
 80142be:	4638      	mov	r0, r7
 80142c0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 80142c2:	6823      	ldr	r3, [r4, #0]
 80142c4:	6922      	ldr	r2, [r4, #16]
 80142c6:	1a98      	subs	r0, r3, r2
 80142c8:	6963      	ldr	r3, [r4, #20]
 80142ca:	b2f6      	uxtb	r6, r6
 80142cc:	4283      	cmp	r3, r0
 80142ce:	4637      	mov	r7, r6
 80142d0:	dc05      	bgt.n	80142de <__swbuf_r+0x4e>
 80142d2:	4621      	mov	r1, r4
 80142d4:	4628      	mov	r0, r5
 80142d6:	f7ff ffb3 	bl	8014240 <_fflush_r>
 80142da:	2800      	cmp	r0, #0
 80142dc:	d1ed      	bne.n	80142ba <__swbuf_r+0x2a>
 80142de:	68a3      	ldr	r3, [r4, #8]
 80142e0:	3b01      	subs	r3, #1
 80142e2:	60a3      	str	r3, [r4, #8]
 80142e4:	6823      	ldr	r3, [r4, #0]
 80142e6:	1c5a      	adds	r2, r3, #1
 80142e8:	6022      	str	r2, [r4, #0]
 80142ea:	701e      	strb	r6, [r3, #0]
 80142ec:	6962      	ldr	r2, [r4, #20]
 80142ee:	1c43      	adds	r3, r0, #1
 80142f0:	429a      	cmp	r2, r3
 80142f2:	d004      	beq.n	80142fe <__swbuf_r+0x6e>
 80142f4:	89a3      	ldrh	r3, [r4, #12]
 80142f6:	07db      	lsls	r3, r3, #31
 80142f8:	d5e1      	bpl.n	80142be <__swbuf_r+0x2e>
 80142fa:	2e0a      	cmp	r6, #10
 80142fc:	d1df      	bne.n	80142be <__swbuf_r+0x2e>
 80142fe:	4621      	mov	r1, r4
 8014300:	4628      	mov	r0, r5
 8014302:	f7ff ff9d 	bl	8014240 <_fflush_r>
 8014306:	2800      	cmp	r0, #0
 8014308:	d0d9      	beq.n	80142be <__swbuf_r+0x2e>
 801430a:	e7d6      	b.n	80142ba <__swbuf_r+0x2a>

0801430c <__swsetup_r>:
 801430c:	b538      	push	{r3, r4, r5, lr}
 801430e:	4b29      	ldr	r3, [pc, #164]	@ (80143b4 <__swsetup_r+0xa8>)
 8014310:	4605      	mov	r5, r0
 8014312:	6818      	ldr	r0, [r3, #0]
 8014314:	460c      	mov	r4, r1
 8014316:	b118      	cbz	r0, 8014320 <__swsetup_r+0x14>
 8014318:	6a03      	ldr	r3, [r0, #32]
 801431a:	b90b      	cbnz	r3, 8014320 <__swsetup_r+0x14>
 801431c:	f7ff f9d8 	bl	80136d0 <__sinit>
 8014320:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8014324:	0719      	lsls	r1, r3, #28
 8014326:	d422      	bmi.n	801436e <__swsetup_r+0x62>
 8014328:	06da      	lsls	r2, r3, #27
 801432a:	d407      	bmi.n	801433c <__swsetup_r+0x30>
 801432c:	2209      	movs	r2, #9
 801432e:	602a      	str	r2, [r5, #0]
 8014330:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 8014334:	81a3      	strh	r3, [r4, #12]
 8014336:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
 801433a:	e033      	b.n	80143a4 <__swsetup_r+0x98>
 801433c:	0758      	lsls	r0, r3, #29
 801433e:	d512      	bpl.n	8014366 <__swsetup_r+0x5a>
 8014340:	6b61      	ldr	r1, [r4, #52]	@ 0x34
 8014342:	b141      	cbz	r1, 8014356 <__swsetup_r+0x4a>
 8014344:	f104 0344 	add.w	r3, r4, #68	@ 0x44
 8014348:	4299      	cmp	r1, r3
 801434a:	d002      	beq.n	8014352 <__swsetup_r+0x46>
 801434c:	4628      	mov	r0, r5
 801434e:	f7ff fb2b 	bl	80139a8 <_free_r>
 8014352:	2300      	movs	r3, #0
 8014354:	6363      	str	r3, [r4, #52]	@ 0x34
 8014356:	89a3      	ldrh	r3, [r4, #12]
 8014358:	f023 0324 	bic.w	r3, r3, #36	@ 0x24
 801435c:	81a3      	strh	r3, [r4, #12]
 801435e:	2300      	movs	r3, #0
 8014360:	6063      	str	r3, [r4, #4]
 8014362:	6923      	ldr	r3, [r4, #16]
 8014364:	6023      	str	r3, [r4, #0]
 8014366:	89a3      	ldrh	r3, [r4, #12]
 8014368:	f043 0308 	orr.w	r3, r3, #8
 801436c:	81a3      	strh	r3, [r4, #12]
 801436e:	6923      	ldr	r3, [r4, #16]
 8014370:	b94b      	cbnz	r3, 8014386 <__swsetup_r+0x7a>
 8014372:	89a3      	ldrh	r3, [r4, #12]
 8014374:	f403 7320 	and.w	r3, r3, #640	@ 0x280
 8014378:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 801437c:	d003      	beq.n	8014386 <__swsetup_r+0x7a>
 801437e:	4621      	mov	r1, r4
 8014380:	4628      	mov	r0, r5
 8014382:	f000 f84f 	bl	8014424 <__smakebuf_r>
 8014386:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 801438a:	f013 0201 	ands.w	r2, r3, #1
 801438e:	d00a      	beq.n	80143a6 <__swsetup_r+0x9a>
 8014390:	2200      	movs	r2, #0
 8014392:	60a2      	str	r2, [r4, #8]
 8014394:	6962      	ldr	r2, [r4, #20]
 8014396:	4252      	negs	r2, r2
 8014398:	61a2      	str	r2, [r4, #24]
 801439a:	6922      	ldr	r2, [r4, #16]
 801439c:	b942      	cbnz	r2, 80143b0 <__swsetup_r+0xa4>
 801439e:	f013 0080 	ands.w	r0, r3, #128	@ 0x80
 80143a2:	d1c5      	bne.n	8014330 <__swsetup_r+0x24>
 80143a4:	bd38      	pop	{r3, r4, r5, pc}
 80143a6:	0799      	lsls	r1, r3, #30
 80143a8:	bf58      	it	pl
 80143aa:	6962      	ldrpl	r2, [r4, #20]
 80143ac:	60a2      	str	r2, [r4, #8]
 80143ae:	e7f4      	b.n	801439a <__swsetup_r+0x8e>
 80143b0:	2000      	movs	r0, #0
 80143b2:	e7f7      	b.n	80143a4 <__swsetup_r+0x98>
 80143b4:	24000054 	.word	0x24000054

080143b8 <_sbrk_r>:
 80143b8:	b538      	push	{r3, r4, r5, lr}
 80143ba:	4d06      	ldr	r5, [pc, #24]	@ (80143d4 <_sbrk_r+0x1c>)
 80143bc:	2300      	movs	r3, #0
 80143be:	4604      	mov	r4, r0
 80143c0:	4608      	mov	r0, r1
 80143c2:	602b      	str	r3, [r5, #0]
 80143c4:	f7ee f9f8 	bl	80027b8 <_sbrk>
 80143c8:	1c43      	adds	r3, r0, #1
 80143ca:	d102      	bne.n	80143d2 <_sbrk_r+0x1a>
 80143cc:	682b      	ldr	r3, [r5, #0]
 80143ce:	b103      	cbz	r3, 80143d2 <_sbrk_r+0x1a>
 80143d0:	6023      	str	r3, [r4, #0]
 80143d2:	bd38      	pop	{r3, r4, r5, pc}
 80143d4:	24012b84 	.word	0x24012b84

080143d8 <__swhatbuf_r>:
 80143d8:	b570      	push	{r4, r5, r6, lr}
 80143da:	460c      	mov	r4, r1
 80143dc:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80143e0:	2900      	cmp	r1, #0
 80143e2:	b096      	sub	sp, #88	@ 0x58
 80143e4:	4615      	mov	r5, r2
 80143e6:	461e      	mov	r6, r3
 80143e8:	da0d      	bge.n	8014406 <__swhatbuf_r+0x2e>
 80143ea:	89a3      	ldrh	r3, [r4, #12]
 80143ec:	f013 0f80 	tst.w	r3, #128	@ 0x80
 80143f0:	f04f 0100 	mov.w	r1, #0
 80143f4:	bf14      	ite	ne
 80143f6:	2340      	movne	r3, #64	@ 0x40
 80143f8:	f44f 6380 	moveq.w	r3, #1024	@ 0x400
 80143fc:	2000      	movs	r0, #0
 80143fe:	6031      	str	r1, [r6, #0]
 8014400:	602b      	str	r3, [r5, #0]
 8014402:	b016      	add	sp, #88	@ 0x58
 8014404:	bd70      	pop	{r4, r5, r6, pc}
 8014406:	466a      	mov	r2, sp
 8014408:	f000 f848 	bl	801449c <_fstat_r>
 801440c:	2800      	cmp	r0, #0
 801440e:	dbec      	blt.n	80143ea <__swhatbuf_r+0x12>
 8014410:	9901      	ldr	r1, [sp, #4]
 8014412:	f401 4170 	and.w	r1, r1, #61440	@ 0xf000
 8014416:	f5a1 5300 	sub.w	r3, r1, #8192	@ 0x2000
 801441a:	4259      	negs	r1, r3
 801441c:	4159      	adcs	r1, r3
 801441e:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 8014422:	e7eb      	b.n	80143fc <__swhatbuf_r+0x24>

08014424 <__smakebuf_r>:
 8014424:	898b      	ldrh	r3, [r1, #12]
 8014426:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
 8014428:	079d      	lsls	r5, r3, #30
 801442a:	4606      	mov	r6, r0
 801442c:	460c      	mov	r4, r1
 801442e:	d507      	bpl.n	8014440 <__smakebuf_r+0x1c>
 8014430:	f104 0347 	add.w	r3, r4, #71	@ 0x47
 8014434:	6023      	str	r3, [r4, #0]
 8014436:	6123      	str	r3, [r4, #16]
 8014438:	2301      	movs	r3, #1
 801443a:	6163      	str	r3, [r4, #20]
 801443c:	b003      	add	sp, #12
 801443e:	bdf0      	pop	{r4, r5, r6, r7, pc}
 8014440:	ab01      	add	r3, sp, #4
 8014442:	466a      	mov	r2, sp
 8014444:	f7ff ffc8 	bl	80143d8 <__swhatbuf_r>
 8014448:	9f00      	ldr	r7, [sp, #0]
 801444a:	4605      	mov	r5, r0
 801444c:	4639      	mov	r1, r7
 801444e:	4630      	mov	r0, r6
 8014450:	f7ff fb16 	bl	8013a80 <_malloc_r>
 8014454:	b948      	cbnz	r0, 801446a <__smakebuf_r+0x46>
 8014456:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 801445a:	059a      	lsls	r2, r3, #22
 801445c:	d4ee      	bmi.n	801443c <__smakebuf_r+0x18>
 801445e:	f023 0303 	bic.w	r3, r3, #3
 8014462:	f043 0302 	orr.w	r3, r3, #2
 8014466:	81a3      	strh	r3, [r4, #12]
 8014468:	e7e2      	b.n	8014430 <__smakebuf_r+0xc>
 801446a:	89a3      	ldrh	r3, [r4, #12]
 801446c:	6020      	str	r0, [r4, #0]
 801446e:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 8014472:	81a3      	strh	r3, [r4, #12]
 8014474:	9b01      	ldr	r3, [sp, #4]
 8014476:	e9c4 0704 	strd	r0, r7, [r4, #16]
 801447a:	b15b      	cbz	r3, 8014494 <__smakebuf_r+0x70>
 801447c:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 8014480:	4630      	mov	r0, r6
 8014482:	f000 f81d 	bl	80144c0 <_isatty_r>
 8014486:	b128      	cbz	r0, 8014494 <__smakebuf_r+0x70>
 8014488:	89a3      	ldrh	r3, [r4, #12]
 801448a:	f023 0303 	bic.w	r3, r3, #3
 801448e:	f043 0301 	orr.w	r3, r3, #1
 8014492:	81a3      	strh	r3, [r4, #12]
 8014494:	89a3      	ldrh	r3, [r4, #12]
 8014496:	431d      	orrs	r5, r3
 8014498:	81a5      	strh	r5, [r4, #12]
 801449a:	e7cf      	b.n	801443c <__smakebuf_r+0x18>

0801449c <_fstat_r>:
 801449c:	b538      	push	{r3, r4, r5, lr}
 801449e:	4d07      	ldr	r5, [pc, #28]	@ (80144bc <_fstat_r+0x20>)
 80144a0:	2300      	movs	r3, #0
 80144a2:	4604      	mov	r4, r0
 80144a4:	4608      	mov	r0, r1
 80144a6:	4611      	mov	r1, r2
 80144a8:	602b      	str	r3, [r5, #0]
 80144aa:	f7ee f95c 	bl	8002766 <_fstat>
 80144ae:	1c43      	adds	r3, r0, #1
 80144b0:	d102      	bne.n	80144b8 <_fstat_r+0x1c>
 80144b2:	682b      	ldr	r3, [r5, #0]
 80144b4:	b103      	cbz	r3, 80144b8 <_fstat_r+0x1c>
 80144b6:	6023      	str	r3, [r4, #0]
 80144b8:	bd38      	pop	{r3, r4, r5, pc}
 80144ba:	bf00      	nop
 80144bc:	24012b84 	.word	0x24012b84

080144c0 <_isatty_r>:
 80144c0:	b538      	push	{r3, r4, r5, lr}
 80144c2:	4d06      	ldr	r5, [pc, #24]	@ (80144dc <_isatty_r+0x1c>)
 80144c4:	2300      	movs	r3, #0
 80144c6:	4604      	mov	r4, r0
 80144c8:	4608      	mov	r0, r1
 80144ca:	602b      	str	r3, [r5, #0]
 80144cc:	f7ee f95b 	bl	8002786 <_isatty>
 80144d0:	1c43      	adds	r3, r0, #1
 80144d2:	d102      	bne.n	80144da <_isatty_r+0x1a>
 80144d4:	682b      	ldr	r3, [r5, #0]
 80144d6:	b103      	cbz	r3, 80144da <_isatty_r+0x1a>
 80144d8:	6023      	str	r3, [r4, #0]
 80144da:	bd38      	pop	{r3, r4, r5, pc}
 80144dc:	24012b84 	.word	0x24012b84

080144e0 <_init>:
 80144e0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80144e2:	bf00      	nop
 80144e4:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80144e6:	bc08      	pop	{r3}
 80144e8:	469e      	mov	lr, r3
 80144ea:	4770      	bx	lr

080144ec <_fini>:
 80144ec:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80144ee:	bf00      	nop
 80144f0:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80144f2:	bc08      	pop	{r3}
 80144f4:	469e      	mov	lr, r3
 80144f6:	4770      	bx	lr