node-red-STM32/CM4/Debug/STM32H7-node-red-CM4.list

STM32H7-node-red-CM4.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000298  08100000  08100000  00001000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00000c30  08100298  08100298  00001298  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000010  08100ec8  08100ec8  00001ec8  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .init_array   00000004  08100ed8  08100ed8  00001ed8  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .fini_array   00000004  08100edc  08100edc  00001edc  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  5 .data         00000010  10000000  08100ee0  00002000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  6 .bss          00000020  10000010  08100ef0  00002010  2**2
                  ALLOC
  7 ._user_heap_stack 00000600  10000030  08100ef0  00002030  2**0
                  ALLOC
  8 .ARM.attributes 00000030  00000000  00000000  00002010  2**0
                  CONTENTS, READONLY
  9 .debug_info   00005854  00000000  00000000  00002040  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 10 .debug_abbrev 00000f2e  00000000  00000000  00007894  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 11 .debug_aranges 00000500  00000000  00000000  000087c8  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 12 .debug_rnglists 000003a5  00000000  00000000  00008cc8  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 13 .debug_macro  00036d4f  00000000  00000000  0000906d  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_line   00005e99  00000000  00000000  0003fdbc  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_str    0016d99a  00000000  00000000  00045c55  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .comment      00000043  00000000  00000000  001b35ef  2**0
                  CONTENTS, READONLY
 17 .debug_frame  00001270  00000000  00000000  001b3634  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_line_str 00000064  00000000  00000000  001b48a4  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

08100298 <__do_global_dtors_aux>:
 8100298:	b510      	push	{r4, lr}
 810029a:	4c05      	ldr	r4, [pc, #20]	@ (81002b0 <__do_global_dtors_aux+0x18>)
 810029c:	7823      	ldrb	r3, [r4, #0]
 810029e:	b933      	cbnz	r3, 81002ae <__do_global_dtors_aux+0x16>
 81002a0:	4b04      	ldr	r3, [pc, #16]	@ (81002b4 <__do_global_dtors_aux+0x1c>)
 81002a2:	b113      	cbz	r3, 81002aa <__do_global_dtors_aux+0x12>
 81002a4:	4804      	ldr	r0, [pc, #16]	@ (81002b8 <__do_global_dtors_aux+0x20>)
 81002a6:	f3af 8000 	nop.w
 81002aa:	2301      	movs	r3, #1
 81002ac:	7023      	strb	r3, [r4, #0]
 81002ae:	bd10      	pop	{r4, pc}
 81002b0:	10000010 	.word	0x10000010
 81002b4:	00000000 	.word	0x00000000
 81002b8:	08100eb0 	.word	0x08100eb0

081002bc <frame_dummy>:
 81002bc:	b508      	push	{r3, lr}
 81002be:	4b03      	ldr	r3, [pc, #12]	@ (81002cc <frame_dummy+0x10>)
 81002c0:	b11b      	cbz	r3, 81002ca <frame_dummy+0xe>
 81002c2:	4903      	ldr	r1, [pc, #12]	@ (81002d0 <frame_dummy+0x14>)
 81002c4:	4803      	ldr	r0, [pc, #12]	@ (81002d4 <frame_dummy+0x18>)
 81002c6:	f3af 8000 	nop.w
 81002ca:	bd08      	pop	{r3, pc}
 81002cc:	00000000 	.word	0x00000000
 81002d0:	10000014 	.word	0x10000014
 81002d4:	08100eb0 	.word	0x08100eb0

081002d8 <SystemInit>:
  *         configuration.
  * @param  None
  * @retval None
  */
void SystemInit (void)
{
 81002d8:	b480      	push	{r7}
 81002da:	af00      	add	r7, sp, #0
  /* FPU settings ------------------------------------------------------------*/
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
 81002dc:	4b09      	ldr	r3, [pc, #36]	@ (8100304 <SystemInit+0x2c>)
 81002de:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 81002e2:	4a08      	ldr	r2, [pc, #32]	@ (8100304 <SystemInit+0x2c>)
 81002e4:	f443 0370 	orr.w	r3, r3, #15728640	@ 0xf00000
 81002e8:	f8c2 3088 	str.w	r3, [r2, #136]	@ 0x88
  #endif

    /*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is
     detectable by the CPU after a WFI/WFE instruction.*/
 SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
 81002ec:	4b05      	ldr	r3, [pc, #20]	@ (8100304 <SystemInit+0x2c>)
 81002ee:	691b      	ldr	r3, [r3, #16]
 81002f0:	4a04      	ldr	r2, [pc, #16]	@ (8100304 <SystemInit+0x2c>)
 81002f2:	f043 0310 	orr.w	r3, r3, #16
 81002f6:	6113      	str	r3, [r2, #16]
#endif /* USER_VECT_TAB_ADDRESS */

#else
#error Please #define CORE_CM4 or CORE_CM7
#endif /* CORE_CM4 */
}
 81002f8:	bf00      	nop
 81002fa:	46bd      	mov	sp, r7
 81002fc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8100300:	4770      	bx	lr
 8100302:	bf00      	nop
 8100304:	e000ed00 	.word	0xe000ed00

08100308 <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 8100308:	b580      	push	{r7, lr}
 810030a:	b082      	sub	sp, #8
 810030c:	af00      	add	r7, sp, #0

/* USER CODE BEGIN Boot_Mode_Sequence_1 */
	/* ETH_CODE: fixed core synchronization
	 * Busy wait, since entering STOP mode breaks debug session.
	 */
	__HAL_RCC_HSEM_CLK_ENABLE();
 810030e:	4b26      	ldr	r3, [pc, #152]	@ (81003a8 <main+0xa0>)
 8100310:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8100314:	4a24      	ldr	r2, [pc, #144]	@ (81003a8 <main+0xa0>)
 8100316:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
 810031a:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 810031e:	4b22      	ldr	r3, [pc, #136]	@ (81003a8 <main+0xa0>)
 8100320:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8100324:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8100328:	607b      	str	r3, [r7, #4]
 810032a:	687b      	ldr	r3, [r7, #4]
	while((__HAL_HSEM_GET_FLAG(__HAL_HSEM_SEMID_TO_MASK(HSEM_ID_0))) == 0);
 810032c:	bf00      	nop
 810032e:	4b1f      	ldr	r3, [pc, #124]	@ (81003ac <main+0xa4>)
 8100330:	681b      	ldr	r3, [r3, #0]
 8100332:	091b      	lsrs	r3, r3, #4
 8100334:	f003 030f 	and.w	r3, r3, #15
 8100338:	2b07      	cmp	r3, #7
 810033a:	d10a      	bne.n	8100352 <main+0x4a>
 810033c:	4b1c      	ldr	r3, [pc, #112]	@ (81003b0 <main+0xa8>)
 810033e:	f8d3 3108 	ldr.w	r3, [r3, #264]	@ 0x108
 8100342:	f003 0301 	and.w	r3, r3, #1
 8100346:	2b00      	cmp	r3, #0
 8100348:	bf0c      	ite	eq
 810034a:	2301      	moveq	r3, #1
 810034c:	2300      	movne	r3, #0
 810034e:	b2db      	uxtb	r3, r3
 8100350:	e009      	b.n	8100366 <main+0x5e>
 8100352:	4b17      	ldr	r3, [pc, #92]	@ (81003b0 <main+0xa8>)
 8100354:	f8d3 3118 	ldr.w	r3, [r3, #280]	@ 0x118
 8100358:	f003 0301 	and.w	r3, r3, #1
 810035c:	2b00      	cmp	r3, #0
 810035e:	bf0c      	ite	eq
 8100360:	2301      	moveq	r3, #1
 8100362:	2300      	movne	r3, #0
 8100364:	b2db      	uxtb	r3, r3
 8100366:	2b00      	cmp	r3, #0
 8100368:	d1e1      	bne.n	810032e <main+0x26>
	__HAL_HSEM_CLEAR_FLAG(__HAL_HSEM_SEMID_TO_MASK(HSEM_ID_0));
 810036a:	4b10      	ldr	r3, [pc, #64]	@ (81003ac <main+0xa4>)
 810036c:	681b      	ldr	r3, [r3, #0]
 810036e:	091b      	lsrs	r3, r3, #4
 8100370:	f003 030f 	and.w	r3, r3, #15
 8100374:	2b07      	cmp	r3, #7
 8100376:	d108      	bne.n	810038a <main+0x82>
 8100378:	4b0d      	ldr	r3, [pc, #52]	@ (81003b0 <main+0xa8>)
 810037a:	f8d3 3104 	ldr.w	r3, [r3, #260]	@ 0x104
 810037e:	4a0c      	ldr	r2, [pc, #48]	@ (81003b0 <main+0xa8>)
 8100380:	f043 0301 	orr.w	r3, r3, #1
 8100384:	f8c2 3104 	str.w	r3, [r2, #260]	@ 0x104
 8100388:	e007      	b.n	810039a <main+0x92>
 810038a:	4b09      	ldr	r3, [pc, #36]	@ (81003b0 <main+0xa8>)
 810038c:	f8d3 3114 	ldr.w	r3, [r3, #276]	@ 0x114
 8100390:	4a07      	ldr	r2, [pc, #28]	@ (81003b0 <main+0xa8>)
 8100392:	f043 0301 	orr.w	r3, r3, #1
 8100396:	f8c2 3114 	str.w	r3, [r2, #276]	@ 0x114
/* USER CODE END Boot_Mode_Sequence_1 */
  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 810039a:	f000 f8af 	bl	81004fc <HAL_Init>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 810039e:	f000 f809 	bl	81003b4 <MX_GPIO_Init>

  /* USER CODE END 2 */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
 81003a2:	bf00      	nop
 81003a4:	e7fd      	b.n	81003a2 <main+0x9a>
 81003a6:	bf00      	nop
 81003a8:	58024400 	.word	0x58024400
 81003ac:	e000ed00 	.word	0xe000ed00
 81003b0:	58026400 	.word	0x58026400

081003b4 <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 81003b4:	b580      	push	{r7, lr}
 81003b6:	b086      	sub	sp, #24
 81003b8:	af00      	add	r7, sp, #0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 81003ba:	1d3b      	adds	r3, r7, #4
 81003bc:	2200      	movs	r2, #0
 81003be:	601a      	str	r2, [r3, #0]
 81003c0:	605a      	str	r2, [r3, #4]
 81003c2:	609a      	str	r2, [r3, #8]
 81003c4:	60da      	str	r2, [r3, #12]
 81003c6:	611a      	str	r2, [r3, #16]

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOE_CLK_ENABLE();
 81003c8:	4b10      	ldr	r3, [pc, #64]	@ (810040c <MX_GPIO_Init+0x58>)
 81003ca:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 81003ce:	4a0f      	ldr	r2, [pc, #60]	@ (810040c <MX_GPIO_Init+0x58>)
 81003d0:	f043 0310 	orr.w	r3, r3, #16
 81003d4:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 81003d8:	4b0c      	ldr	r3, [pc, #48]	@ (810040c <MX_GPIO_Init+0x58>)
 81003da:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 81003de:	f003 0310 	and.w	r3, r3, #16
 81003e2:	603b      	str	r3, [r7, #0]
 81003e4:	683b      	ldr	r3, [r7, #0]

  /*Configure GPIO pins : PE5 PE4 */
  GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_4;
 81003e6:	2330      	movs	r3, #48	@ 0x30
 81003e8:	607b      	str	r3, [r7, #4]
  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 81003ea:	2302      	movs	r3, #2
 81003ec:	60bb      	str	r3, [r7, #8]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 81003ee:	2300      	movs	r3, #0
 81003f0:	60fb      	str	r3, [r7, #12]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 81003f2:	2300      	movs	r3, #0
 81003f4:	613b      	str	r3, [r7, #16]
  GPIO_InitStruct.Alternate = GPIO_AF10_SAI4;
 81003f6:	230a      	movs	r3, #10
 81003f8:	617b      	str	r3, [r7, #20]
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 81003fa:	1d3b      	adds	r3, r7, #4
 81003fc:	4619      	mov	r1, r3
 81003fe:	4804      	ldr	r0, [pc, #16]	@ (8100410 <MX_GPIO_Init+0x5c>)
 8100400:	f000 fa08 	bl	8100814 <HAL_GPIO_Init>

}
 8100404:	bf00      	nop
 8100406:	3718      	adds	r7, #24
 8100408:	46bd      	mov	sp, r7
 810040a:	bd80      	pop	{r7, pc}
 810040c:	58024400 	.word	0x58024400
 8100410:	58021000 	.word	0x58021000

08100414 <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8100414:	b480      	push	{r7}
 8100416:	b083      	sub	sp, #12
 8100418:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 810041a:	4b0a      	ldr	r3, [pc, #40]	@ (8100444 <HAL_MspInit+0x30>)
 810041c:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 8100420:	4a08      	ldr	r2, [pc, #32]	@ (8100444 <HAL_MspInit+0x30>)
 8100422:	f043 0302 	orr.w	r3, r3, #2
 8100426:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
 810042a:	4b06      	ldr	r3, [pc, #24]	@ (8100444 <HAL_MspInit+0x30>)
 810042c:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 8100430:	f003 0302 	and.w	r3, r3, #2
 8100434:	607b      	str	r3, [r7, #4]
 8100436:	687b      	ldr	r3, [r7, #4]
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8100438:	bf00      	nop
 810043a:	370c      	adds	r7, #12
 810043c:	46bd      	mov	sp, r7
 810043e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8100442:	4770      	bx	lr
 8100444:	58024400 	.word	0x58024400

08100448 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 8100448:	b480      	push	{r7}
 810044a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  while (1)
 810044c:	bf00      	nop
 810044e:	e7fd      	b.n	810044c <NMI_Handler+0x4>

08100450 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8100450:	b480      	push	{r7}
 8100452:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 8100454:	bf00      	nop
 8100456:	e7fd      	b.n	8100454 <HardFault_Handler+0x4>

08100458 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 8100458:	b480      	push	{r7}
 810045a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 810045c:	bf00      	nop
 810045e:	e7fd      	b.n	810045c <MemManage_Handler+0x4>

08100460 <BusFault_Handler>:

/**
  * @brief This function handles Pre-fetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8100460:	b480      	push	{r7}
 8100462:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 8100464:	bf00      	nop
 8100466:	e7fd      	b.n	8100464 <BusFault_Handler+0x4>

08100468 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8100468:	b480      	push	{r7}
 810046a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 810046c:	bf00      	nop
 810046e:	e7fd      	b.n	810046c <UsageFault_Handler+0x4>

08100470 <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 8100470:	b480      	push	{r7}
 8100472:	af00      	add	r7, sp, #0

  /* USER CODE END SVCall_IRQn 0 */
  /* USER CODE BEGIN SVCall_IRQn 1 */

  /* USER CODE END SVCall_IRQn 1 */
}
 8100474:	bf00      	nop
 8100476:	46bd      	mov	sp, r7
 8100478:	f85d 7b04 	ldr.w	r7, [sp], #4
 810047c:	4770      	bx	lr

0810047e <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 810047e:	b480      	push	{r7}
 8100480:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 8100482:	bf00      	nop
 8100484:	46bd      	mov	sp, r7
 8100486:	f85d 7b04 	ldr.w	r7, [sp], #4
 810048a:	4770      	bx	lr

0810048c <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 810048c:	b480      	push	{r7}
 810048e:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 8100490:	bf00      	nop
 8100492:	46bd      	mov	sp, r7
 8100494:	f85d 7b04 	ldr.w	r7, [sp], #4
 8100498:	4770      	bx	lr

0810049a <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 810049a:	b580      	push	{r7, lr}
 810049c:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 810049e:	f000 f8c1 	bl	8100624 <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 81004a2:	bf00      	nop
 81004a4:	bd80      	pop	{r7, pc}
	...

081004a8 <Reset_Handler>:

    .section  .text.Reset_Handler
  .weak  Reset_Handler
  .type  Reset_Handler, %function
Reset_Handler:
  ldr   sp, =_estack      /* set stack pointer */
 81004a8:	f8df d034 	ldr.w	sp, [pc, #52]	@ 81004e0 <LoopFillZerobss+0xe>

/* Call the clock system initialization function.*/
  bl  SystemInit
 81004ac:	f7ff ff14 	bl	81002d8 <SystemInit>

/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 81004b0:	480c      	ldr	r0, [pc, #48]	@ (81004e4 <LoopFillZerobss+0x12>)
  ldr r1, =_edata
 81004b2:	490d      	ldr	r1, [pc, #52]	@ (81004e8 <LoopFillZerobss+0x16>)
  ldr r2, =_sidata
 81004b4:	4a0d      	ldr	r2, [pc, #52]	@ (81004ec <LoopFillZerobss+0x1a>)
  movs r3, #0
 81004b6:	2300      	movs	r3, #0
  b LoopCopyDataInit
 81004b8:	e002      	b.n	81004c0 <LoopCopyDataInit>

081004ba <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 81004ba:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 81004bc:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 81004be:	3304      	adds	r3, #4

081004c0 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 81004c0:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 81004c2:	428c      	cmp	r4, r1
  bcc CopyDataInit
 81004c4:	d3f9      	bcc.n	81004ba <CopyDataInit>
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 81004c6:	4a0a      	ldr	r2, [pc, #40]	@ (81004f0 <LoopFillZerobss+0x1e>)
  ldr r4, =_ebss
 81004c8:	4c0a      	ldr	r4, [pc, #40]	@ (81004f4 <LoopFillZerobss+0x22>)
  movs r3, #0
 81004ca:	2300      	movs	r3, #0
  b LoopFillZerobss
 81004cc:	e001      	b.n	81004d2 <LoopFillZerobss>

081004ce <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 81004ce:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 81004d0:	3204      	adds	r2, #4

081004d2 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 81004d2:	42a2      	cmp	r2, r4
  bcc FillZerobss
 81004d4:	d3fb      	bcc.n	81004ce <FillZerobss>

/* Call static constructors */
    bl __libc_init_array
 81004d6:	f000 fcc7 	bl	8100e68 <__libc_init_array>
/* Call the application's entry point.*/
  bl  main
 81004da:	f7ff ff15 	bl	8100308 <main>
  bx  lr
 81004de:	4770      	bx	lr
  ldr   sp, =_estack      /* set stack pointer */
 81004e0:	10020000 	.word	0x10020000
  ldr r0, =_sdata
 81004e4:	10000000 	.word	0x10000000
  ldr r1, =_edata
 81004e8:	10000010 	.word	0x10000010
  ldr r2, =_sidata
 81004ec:	08100ee0 	.word	0x08100ee0
  ldr r2, =_sbss
 81004f0:	10000010 	.word	0x10000010
  ldr r4, =_ebss
 81004f4:	10000030 	.word	0x10000030

081004f8 <ADC3_IRQHandler>:
 * @retval None
*/
    .section  .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b  Infinite_Loop
 81004f8:	e7fe      	b.n	81004f8 <ADC3_IRQHandler>
	...

081004fc <HAL_Init>:
  *         need to ensure that the SysTick time base is always set to 1 millisecond
  *         to have correct HAL operation.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 81004fc:	b580      	push	{r7, lr}
 81004fe:	b082      	sub	sp, #8
 8100500:	af00      	add	r7, sp, #0

uint32_t common_system_clock;

#if defined(DUAL_CORE) && defined(CORE_CM4)
   /* Configure Cortex-M4 Instruction cache through ART accelerator */
   __HAL_RCC_ART_CLK_ENABLE();                   /* Enable the Cortex-M4 ART Clock */
 8100502:	4b28      	ldr	r3, [pc, #160]	@ (81005a4 <HAL_Init+0xa8>)
 8100504:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 8100508:	4a26      	ldr	r2, [pc, #152]	@ (81005a4 <HAL_Init+0xa8>)
 810050a:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
 810050e:	f8c2 30d8 	str.w	r3, [r2, #216]	@ 0xd8
 8100512:	4b24      	ldr	r3, [pc, #144]	@ (81005a4 <HAL_Init+0xa8>)
 8100514:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 8100518:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
 810051c:	603b      	str	r3, [r7, #0]
 810051e:	683b      	ldr	r3, [r7, #0]
   __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL);  /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
 8100520:	4b21      	ldr	r3, [pc, #132]	@ (81005a8 <HAL_Init+0xac>)
 8100522:	681b      	ldr	r3, [r3, #0]
 8100524:	f423 237f 	bic.w	r3, r3, #1044480	@ 0xff000
 8100528:	f423 6370 	bic.w	r3, r3, #3840	@ 0xf00
 810052c:	4a1e      	ldr	r2, [pc, #120]	@ (81005a8 <HAL_Init+0xac>)
 810052e:	f443 4301 	orr.w	r3, r3, #33024	@ 0x8100
 8100532:	6013      	str	r3, [r2, #0]
   __HAL_ART_ENABLE();                           /* Enable the Cortex-M4 ART */
 8100534:	4b1c      	ldr	r3, [pc, #112]	@ (81005a8 <HAL_Init+0xac>)
 8100536:	681b      	ldr	r3, [r3, #0]
 8100538:	4a1b      	ldr	r2, [pc, #108]	@ (81005a8 <HAL_Init+0xac>)
 810053a:	f043 0301 	orr.w	r3, r3, #1
 810053e:	6013      	str	r3, [r2, #0]
#endif /* DUAL_CORE &&  CORE_CM4 */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8100540:	2003      	movs	r0, #3
 8100542:	f000 f935 	bl	81007b0 <HAL_NVIC_SetPriorityGrouping>

  /* Update the SystemCoreClock global variable */
#if defined(RCC_D1CFGR_D1CPRE)
  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
 8100546:	f000 fb15 	bl	8100b74 <HAL_RCC_GetSysClockFreq>
 810054a:	4602      	mov	r2, r0
 810054c:	4b15      	ldr	r3, [pc, #84]	@ (81005a4 <HAL_Init+0xa8>)
 810054e:	699b      	ldr	r3, [r3, #24]
 8100550:	0a1b      	lsrs	r3, r3, #8
 8100552:	f003 030f 	and.w	r3, r3, #15
 8100556:	4915      	ldr	r1, [pc, #84]	@ (81005ac <HAL_Init+0xb0>)
 8100558:	5ccb      	ldrb	r3, [r1, r3]
 810055a:	f003 031f 	and.w	r3, r3, #31
 810055e:	fa22 f303 	lsr.w	r3, r2, r3
 8100562:	607b      	str	r3, [r7, #4]
  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif

  /* Update the SystemD2Clock global variable */
#if defined(RCC_D1CFGR_HPRE)
  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 8100564:	4b0f      	ldr	r3, [pc, #60]	@ (81005a4 <HAL_Init+0xa8>)
 8100566:	699b      	ldr	r3, [r3, #24]
 8100568:	f003 030f 	and.w	r3, r3, #15
 810056c:	4a0f      	ldr	r2, [pc, #60]	@ (81005ac <HAL_Init+0xb0>)
 810056e:	5cd3      	ldrb	r3, [r2, r3]
 8100570:	f003 031f 	and.w	r3, r3, #31
 8100574:	687a      	ldr	r2, [r7, #4]
 8100576:	fa22 f303 	lsr.w	r3, r2, r3
 810057a:	4a0d      	ldr	r2, [pc, #52]	@ (81005b0 <HAL_Init+0xb4>)
 810057c:	6013      	str	r3, [r2, #0]
#else
  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif

#if defined(DUAL_CORE) && defined(CORE_CM4)
  SystemCoreClock = SystemD2Clock;
 810057e:	4b0c      	ldr	r3, [pc, #48]	@ (81005b0 <HAL_Init+0xb4>)
 8100580:	681b      	ldr	r3, [r3, #0]
 8100582:	4a0c      	ldr	r2, [pc, #48]	@ (81005b4 <HAL_Init+0xb8>)
 8100584:	6013      	str	r3, [r2, #0]
#else
  SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 8100586:	2000      	movs	r0, #0
 8100588:	f000 f816 	bl	81005b8 <HAL_InitTick>
 810058c:	4603      	mov	r3, r0
 810058e:	2b00      	cmp	r3, #0
 8100590:	d001      	beq.n	8100596 <HAL_Init+0x9a>
  {
    return HAL_ERROR;
 8100592:	2301      	movs	r3, #1
 8100594:	e002      	b.n	810059c <HAL_Init+0xa0>
  }

  /* Init the low level hardware */
  HAL_MspInit();
 8100596:	f7ff ff3d 	bl	8100414 <HAL_MspInit>

  /* Return function status */
  return HAL_OK;
 810059a:	2300      	movs	r3, #0
}
 810059c:	4618      	mov	r0, r3
 810059e:	3708      	adds	r7, #8
 81005a0:	46bd      	mov	sp, r7
 81005a2:	bd80      	pop	{r7, pc}
 81005a4:	58024400 	.word	0x58024400
 81005a8:	40024400 	.word	0x40024400
 81005ac:	08100ec8 	.word	0x08100ec8
 81005b0:	10000004 	.word	0x10000004
 81005b4:	10000000 	.word	0x10000000

081005b8 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority: Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 81005b8:	b580      	push	{r7, lr}
 81005ba:	b082      	sub	sp, #8
 81005bc:	af00      	add	r7, sp, #0
 81005be:	6078      	str	r0, [r7, #4]
  /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
  if((uint32_t)uwTickFreq == 0UL)
 81005c0:	4b15      	ldr	r3, [pc, #84]	@ (8100618 <HAL_InitTick+0x60>)
 81005c2:	781b      	ldrb	r3, [r3, #0]
 81005c4:	2b00      	cmp	r3, #0
 81005c6:	d101      	bne.n	81005cc <HAL_InitTick+0x14>
  {
    return HAL_ERROR;
 81005c8:	2301      	movs	r3, #1
 81005ca:	e021      	b.n	8100610 <HAL_InitTick+0x58>
  }

    /* Configure the SysTick to have interrupt in 1ms time basis*/
    if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
 81005cc:	4b13      	ldr	r3, [pc, #76]	@ (810061c <HAL_InitTick+0x64>)
 81005ce:	681a      	ldr	r2, [r3, #0]
 81005d0:	4b11      	ldr	r3, [pc, #68]	@ (8100618 <HAL_InitTick+0x60>)
 81005d2:	781b      	ldrb	r3, [r3, #0]
 81005d4:	4619      	mov	r1, r3
 81005d6:	f44f 737a 	mov.w	r3, #1000	@ 0x3e8
 81005da:	fbb3 f3f1 	udiv	r3, r3, r1
 81005de:	fbb2 f3f3 	udiv	r3, r2, r3
 81005e2:	4618      	mov	r0, r3
 81005e4:	f000 f909 	bl	81007fa <HAL_SYSTICK_Config>
 81005e8:	4603      	mov	r3, r0
 81005ea:	2b00      	cmp	r3, #0
 81005ec:	d001      	beq.n	81005f2 <HAL_InitTick+0x3a>
    {
      return HAL_ERROR;
 81005ee:	2301      	movs	r3, #1
 81005f0:	e00e      	b.n	8100610 <HAL_InitTick+0x58>
    }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 81005f2:	687b      	ldr	r3, [r7, #4]
 81005f4:	2b0f      	cmp	r3, #15
 81005f6:	d80a      	bhi.n	810060e <HAL_InitTick+0x56>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 81005f8:	2200      	movs	r2, #0
 81005fa:	6879      	ldr	r1, [r7, #4]
 81005fc:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
 8100600:	f000 f8e1 	bl	81007c6 <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 8100604:	4a06      	ldr	r2, [pc, #24]	@ (8100620 <HAL_InitTick+0x68>)
 8100606:	687b      	ldr	r3, [r7, #4]
 8100608:	6013      	str	r3, [r2, #0]
  {
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
 810060a:	2300      	movs	r3, #0
 810060c:	e000      	b.n	8100610 <HAL_InitTick+0x58>
    return HAL_ERROR;
 810060e:	2301      	movs	r3, #1
}
 8100610:	4618      	mov	r0, r3
 8100612:	3708      	adds	r7, #8
 8100614:	46bd      	mov	sp, r7
 8100616:	bd80      	pop	{r7, pc}
 8100618:	1000000c 	.word	0x1000000c
 810061c:	10000000 	.word	0x10000000
 8100620:	10000008 	.word	0x10000008

08100624 <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8100624:	b480      	push	{r7}
 8100626:	af00      	add	r7, sp, #0
  uwTick += (uint32_t)uwTickFreq;
 8100628:	4b06      	ldr	r3, [pc, #24]	@ (8100644 <HAL_IncTick+0x20>)
 810062a:	781b      	ldrb	r3, [r3, #0]
 810062c:	461a      	mov	r2, r3
 810062e:	4b06      	ldr	r3, [pc, #24]	@ (8100648 <HAL_IncTick+0x24>)
 8100630:	681b      	ldr	r3, [r3, #0]
 8100632:	4413      	add	r3, r2
 8100634:	4a04      	ldr	r2, [pc, #16]	@ (8100648 <HAL_IncTick+0x24>)
 8100636:	6013      	str	r3, [r2, #0]
}
 8100638:	bf00      	nop
 810063a:	46bd      	mov	sp, r7
 810063c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8100640:	4770      	bx	lr
 8100642:	bf00      	nop
 8100644:	1000000c 	.word	0x1000000c
 8100648:	1000002c 	.word	0x1000002c

0810064c <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 810064c:	b480      	push	{r7}
 810064e:	b085      	sub	sp, #20
 8100650:	af00      	add	r7, sp, #0
 8100652:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 8100654:	687b      	ldr	r3, [r7, #4]
 8100656:	f003 0307 	and.w	r3, r3, #7
 810065a:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 810065c:	4b0c      	ldr	r3, [pc, #48]	@ (8100690 <__NVIC_SetPriorityGrouping+0x44>)
 810065e:	68db      	ldr	r3, [r3, #12]
 8100660:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8100662:	68ba      	ldr	r2, [r7, #8]
 8100664:	f64f 03ff 	movw	r3, #63743	@ 0xf8ff
 8100668:	4013      	ands	r3, r2
 810066a:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 810066c:	68fb      	ldr	r3, [r7, #12]
 810066e:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 8100670:	68bb      	ldr	r3, [r7, #8]
 8100672:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 8100674:	f043 63bf 	orr.w	r3, r3, #100139008	@ 0x5f80000
 8100678:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 810067c:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 810067e:	4a04      	ldr	r2, [pc, #16]	@ (8100690 <__NVIC_SetPriorityGrouping+0x44>)
 8100680:	68bb      	ldr	r3, [r7, #8]
 8100682:	60d3      	str	r3, [r2, #12]
}
 8100684:	bf00      	nop
 8100686:	3714      	adds	r7, #20
 8100688:	46bd      	mov	sp, r7
 810068a:	f85d 7b04 	ldr.w	r7, [sp], #4
 810068e:	4770      	bx	lr
 8100690:	e000ed00 	.word	0xe000ed00

08100694 <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 8100694:	b480      	push	{r7}
 8100696:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8100698:	4b04      	ldr	r3, [pc, #16]	@ (81006ac <__NVIC_GetPriorityGrouping+0x18>)
 810069a:	68db      	ldr	r3, [r3, #12]
 810069c:	0a1b      	lsrs	r3, r3, #8
 810069e:	f003 0307 	and.w	r3, r3, #7
}
 81006a2:	4618      	mov	r0, r3
 81006a4:	46bd      	mov	sp, r7
 81006a6:	f85d 7b04 	ldr.w	r7, [sp], #4
 81006aa:	4770      	bx	lr
 81006ac:	e000ed00 	.word	0xe000ed00

081006b0 <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 81006b0:	b480      	push	{r7}
 81006b2:	b083      	sub	sp, #12
 81006b4:	af00      	add	r7, sp, #0
 81006b6:	4603      	mov	r3, r0
 81006b8:	6039      	str	r1, [r7, #0]
 81006ba:	80fb      	strh	r3, [r7, #6]
  if ((int32_t)(IRQn) >= 0)
 81006bc:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 81006c0:	2b00      	cmp	r3, #0
 81006c2:	db0a      	blt.n	81006da <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 81006c4:	683b      	ldr	r3, [r7, #0]
 81006c6:	b2da      	uxtb	r2, r3
 81006c8:	490c      	ldr	r1, [pc, #48]	@ (81006fc <__NVIC_SetPriority+0x4c>)
 81006ca:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 81006ce:	0112      	lsls	r2, r2, #4
 81006d0:	b2d2      	uxtb	r2, r2
 81006d2:	440b      	add	r3, r1
 81006d4:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 81006d8:	e00a      	b.n	81006f0 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 81006da:	683b      	ldr	r3, [r7, #0]
 81006dc:	b2da      	uxtb	r2, r3
 81006de:	4908      	ldr	r1, [pc, #32]	@ (8100700 <__NVIC_SetPriority+0x50>)
 81006e0:	88fb      	ldrh	r3, [r7, #6]
 81006e2:	f003 030f 	and.w	r3, r3, #15
 81006e6:	3b04      	subs	r3, #4
 81006e8:	0112      	lsls	r2, r2, #4
 81006ea:	b2d2      	uxtb	r2, r2
 81006ec:	440b      	add	r3, r1
 81006ee:	761a      	strb	r2, [r3, #24]
}
 81006f0:	bf00      	nop
 81006f2:	370c      	adds	r7, #12
 81006f4:	46bd      	mov	sp, r7
 81006f6:	f85d 7b04 	ldr.w	r7, [sp], #4
 81006fa:	4770      	bx	lr
 81006fc:	e000e100 	.word	0xe000e100
 8100700:	e000ed00 	.word	0xe000ed00

08100704 <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8100704:	b480      	push	{r7}
 8100706:	b089      	sub	sp, #36	@ 0x24
 8100708:	af00      	add	r7, sp, #0
 810070a:	60f8      	str	r0, [r7, #12]
 810070c:	60b9      	str	r1, [r7, #8]
 810070e:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 8100710:	68fb      	ldr	r3, [r7, #12]
 8100712:	f003 0307 	and.w	r3, r3, #7
 8100716:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8100718:	69fb      	ldr	r3, [r7, #28]
 810071a:	f1c3 0307 	rsb	r3, r3, #7
 810071e:	2b04      	cmp	r3, #4
 8100720:	bf28      	it	cs
 8100722:	2304      	movcs	r3, #4
 8100724:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8100726:	69fb      	ldr	r3, [r7, #28]
 8100728:	3304      	adds	r3, #4
 810072a:	2b06      	cmp	r3, #6
 810072c:	d902      	bls.n	8100734 <NVIC_EncodePriority+0x30>
 810072e:	69fb      	ldr	r3, [r7, #28]
 8100730:	3b03      	subs	r3, #3
 8100732:	e000      	b.n	8100736 <NVIC_EncodePriority+0x32>
 8100734:	2300      	movs	r3, #0
 8100736:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8100738:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 810073c:	69bb      	ldr	r3, [r7, #24]
 810073e:	fa02 f303 	lsl.w	r3, r2, r3
 8100742:	43da      	mvns	r2, r3
 8100744:	68bb      	ldr	r3, [r7, #8]
 8100746:	401a      	ands	r2, r3
 8100748:	697b      	ldr	r3, [r7, #20]
 810074a:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 810074c:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8100750:	697b      	ldr	r3, [r7, #20]
 8100752:	fa01 f303 	lsl.w	r3, r1, r3
 8100756:	43d9      	mvns	r1, r3
 8100758:	687b      	ldr	r3, [r7, #4]
 810075a:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 810075c:	4313      	orrs	r3, r2
         );
}
 810075e:	4618      	mov	r0, r3
 8100760:	3724      	adds	r7, #36	@ 0x24
 8100762:	46bd      	mov	sp, r7
 8100764:	f85d 7b04 	ldr.w	r7, [sp], #4
 8100768:	4770      	bx	lr
	...

0810076c <SysTick_Config>:
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
 810076c:	b580      	push	{r7, lr}
 810076e:	b082      	sub	sp, #8
 8100770:	af00      	add	r7, sp, #0
 8100772:	6078      	str	r0, [r7, #4]
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 8100774:	687b      	ldr	r3, [r7, #4]
 8100776:	3b01      	subs	r3, #1
 8100778:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
 810077c:	d301      	bcc.n	8100782 <SysTick_Config+0x16>
  {
    return (1UL);                                                   /* Reload value impossible */
 810077e:	2301      	movs	r3, #1
 8100780:	e00f      	b.n	81007a2 <SysTick_Config+0x36>
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 8100782:	4a0a      	ldr	r2, [pc, #40]	@ (81007ac <SysTick_Config+0x40>)
 8100784:	687b      	ldr	r3, [r7, #4]
 8100786:	3b01      	subs	r3, #1
 8100788:	6053      	str	r3, [r2, #4]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 810078a:	210f      	movs	r1, #15
 810078c:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
 8100790:	f7ff ff8e 	bl	81006b0 <__NVIC_SetPriority>
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 8100794:	4b05      	ldr	r3, [pc, #20]	@ (81007ac <SysTick_Config+0x40>)
 8100796:	2200      	movs	r2, #0
 8100798:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 810079a:	4b04      	ldr	r3, [pc, #16]	@ (81007ac <SysTick_Config+0x40>)
 810079c:	2207      	movs	r2, #7
 810079e:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 81007a0:	2300      	movs	r3, #0
}
 81007a2:	4618      	mov	r0, r3
 81007a4:	3708      	adds	r7, #8
 81007a6:	46bd      	mov	sp, r7
 81007a8:	bd80      	pop	{r7, pc}
 81007aa:	bf00      	nop
 81007ac:	e000e010 	.word	0xe000e010

081007b0 <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
  *         The pending IRQ priority will be managed only by the subpriority.
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 81007b0:	b580      	push	{r7, lr}
 81007b2:	b082      	sub	sp, #8
 81007b4:	af00      	add	r7, sp, #0
 81007b6:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));

  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 81007b8:	6878      	ldr	r0, [r7, #4]
 81007ba:	f7ff ff47 	bl	810064c <__NVIC_SetPriorityGrouping>
}
 81007be:	bf00      	nop
 81007c0:	3708      	adds	r7, #8
 81007c2:	46bd      	mov	sp, r7
 81007c4:	bd80      	pop	{r7, pc}

081007c6 <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
 81007c6:	b580      	push	{r7, lr}
 81007c8:	b086      	sub	sp, #24
 81007ca:	af00      	add	r7, sp, #0
 81007cc:	4603      	mov	r3, r0
 81007ce:	60b9      	str	r1, [r7, #8]
 81007d0:	607a      	str	r2, [r7, #4]
 81007d2:	81fb      	strh	r3, [r7, #14]

  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));

  prioritygroup = NVIC_GetPriorityGrouping();
 81007d4:	f7ff ff5e 	bl	8100694 <__NVIC_GetPriorityGrouping>
 81007d8:	6178      	str	r0, [r7, #20]

  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 81007da:	687a      	ldr	r2, [r7, #4]
 81007dc:	68b9      	ldr	r1, [r7, #8]
 81007de:	6978      	ldr	r0, [r7, #20]
 81007e0:	f7ff ff90 	bl	8100704 <NVIC_EncodePriority>
 81007e4:	4602      	mov	r2, r0
 81007e6:	f9b7 300e 	ldrsh.w	r3, [r7, #14]
 81007ea:	4611      	mov	r1, r2
 81007ec:	4618      	mov	r0, r3
 81007ee:	f7ff ff5f 	bl	81006b0 <__NVIC_SetPriority>
}
 81007f2:	bf00      	nop
 81007f4:	3718      	adds	r7, #24
 81007f6:	46bd      	mov	sp, r7
 81007f8:	bd80      	pop	{r7, pc}

081007fa <HAL_SYSTICK_Config>:
  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
  * @retval status   - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 81007fa:	b580      	push	{r7, lr}
 81007fc:	b082      	sub	sp, #8
 81007fe:	af00      	add	r7, sp, #0
 8100800:	6078      	str	r0, [r7, #4]
   return SysTick_Config(TicksNumb);
 8100802:	6878      	ldr	r0, [r7, #4]
 8100804:	f7ff ffb2 	bl	810076c <SysTick_Config>
 8100808:	4603      	mov	r3, r0
}
 810080a:	4618      	mov	r0, r3
 810080c:	3708      	adds	r7, #8
 810080e:	46bd      	mov	sp, r7
 8100810:	bd80      	pop	{r7, pc}
	...

08100814 <HAL_GPIO_Init>:
  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8100814:	b480      	push	{r7}
 8100816:	b089      	sub	sp, #36	@ 0x24
 8100818:	af00      	add	r7, sp, #0
 810081a:	6078      	str	r0, [r7, #4]
 810081c:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00U;
 810081e:	2300      	movs	r3, #0
 8100820:	61fb      	str	r3, [r7, #28]
  uint32_t iocurrent;
  uint32_t temp;
  EXTI_Core_TypeDef *EXTI_CurrentCPU;

#if defined(DUAL_CORE) && defined(CORE_CM4)
  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
 8100822:	4b89      	ldr	r3, [pc, #548]	@ (8100a48 <HAL_GPIO_Init+0x234>)
 8100824:	617b      	str	r3, [r7, #20]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0x00U)
 8100826:	e194      	b.n	8100b52 <HAL_GPIO_Init+0x33e>
  {
    /* Get current io position */
    iocurrent = (GPIO_Init->Pin) & (1UL << position);
 8100828:	683b      	ldr	r3, [r7, #0]
 810082a:	681a      	ldr	r2, [r3, #0]
 810082c:	2101      	movs	r1, #1
 810082e:	69fb      	ldr	r3, [r7, #28]
 8100830:	fa01 f303 	lsl.w	r3, r1, r3
 8100834:	4013      	ands	r3, r2
 8100836:	613b      	str	r3, [r7, #16]

    if (iocurrent != 0x00U)
 8100838:	693b      	ldr	r3, [r7, #16]
 810083a:	2b00      	cmp	r3, #0
 810083c:	f000 8186 	beq.w	8100b4c <HAL_GPIO_Init+0x338>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
 8100840:	683b      	ldr	r3, [r7, #0]
 8100842:	685b      	ldr	r3, [r3, #4]
 8100844:	f003 0303 	and.w	r3, r3, #3
 8100848:	2b01      	cmp	r3, #1
 810084a:	d005      	beq.n	8100858 <HAL_GPIO_Init+0x44>
 810084c:	683b      	ldr	r3, [r7, #0]
 810084e:	685b      	ldr	r3, [r3, #4]
 8100850:	f003 0303 	and.w	r3, r3, #3
 8100854:	2b02      	cmp	r3, #2
 8100856:	d130      	bne.n	81008ba <HAL_GPIO_Init+0xa6>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));

        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR;
 8100858:	687b      	ldr	r3, [r7, #4]
 810085a:	689b      	ldr	r3, [r3, #8]
 810085c:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
 810085e:	69fb      	ldr	r3, [r7, #28]
 8100860:	005b      	lsls	r3, r3, #1
 8100862:	2203      	movs	r2, #3
 8100864:	fa02 f303 	lsl.w	r3, r2, r3
 8100868:	43db      	mvns	r3, r3
 810086a:	69ba      	ldr	r2, [r7, #24]
 810086c:	4013      	ands	r3, r2
 810086e:	61bb      	str	r3, [r7, #24]
        temp |= (GPIO_Init->Speed << (position * 2U));
 8100870:	683b      	ldr	r3, [r7, #0]
 8100872:	68da      	ldr	r2, [r3, #12]
 8100874:	69fb      	ldr	r3, [r7, #28]
 8100876:	005b      	lsls	r3, r3, #1
 8100878:	fa02 f303 	lsl.w	r3, r2, r3
 810087c:	69ba      	ldr	r2, [r7, #24]
 810087e:	4313      	orrs	r3, r2
 8100880:	61bb      	str	r3, [r7, #24]
        GPIOx->OSPEEDR = temp;
 8100882:	687b      	ldr	r3, [r7, #4]
 8100884:	69ba      	ldr	r2, [r7, #24]
 8100886:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 8100888:	687b      	ldr	r3, [r7, #4]
 810088a:	685b      	ldr	r3, [r3, #4]
 810088c:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OTYPER_OT0 << position) ;
 810088e:	2201      	movs	r2, #1
 8100890:	69fb      	ldr	r3, [r7, #28]
 8100892:	fa02 f303 	lsl.w	r3, r2, r3
 8100896:	43db      	mvns	r3, r3
 8100898:	69ba      	ldr	r2, [r7, #24]
 810089a:	4013      	ands	r3, r2
 810089c:	61bb      	str	r3, [r7, #24]
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 810089e:	683b      	ldr	r3, [r7, #0]
 81008a0:	685b      	ldr	r3, [r3, #4]
 81008a2:	091b      	lsrs	r3, r3, #4
 81008a4:	f003 0201 	and.w	r2, r3, #1
 81008a8:	69fb      	ldr	r3, [r7, #28]
 81008aa:	fa02 f303 	lsl.w	r3, r2, r3
 81008ae:	69ba      	ldr	r2, [r7, #24]
 81008b0:	4313      	orrs	r3, r2
 81008b2:	61bb      	str	r3, [r7, #24]
        GPIOx->OTYPER = temp;
 81008b4:	687b      	ldr	r3, [r7, #4]
 81008b6:	69ba      	ldr	r2, [r7, #24]
 81008b8:	605a      	str	r2, [r3, #4]
      }

      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 81008ba:	683b      	ldr	r3, [r7, #0]
 81008bc:	685b      	ldr	r3, [r3, #4]
 81008be:	f003 0303 	and.w	r3, r3, #3
 81008c2:	2b03      	cmp	r3, #3
 81008c4:	d017      	beq.n	81008f6 <HAL_GPIO_Init+0xe2>
      {
       /* Check the Pull parameter */
       assert_param(IS_GPIO_PULL(GPIO_Init->Pull));

      /* Activate the Pull-up or Pull down resistor for the current IO */
      temp = GPIOx->PUPDR;
 81008c6:	687b      	ldr	r3, [r7, #4]
 81008c8:	68db      	ldr	r3, [r3, #12]
 81008ca:	61bb      	str	r3, [r7, #24]
      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
 81008cc:	69fb      	ldr	r3, [r7, #28]
 81008ce:	005b      	lsls	r3, r3, #1
 81008d0:	2203      	movs	r2, #3
 81008d2:	fa02 f303 	lsl.w	r3, r2, r3
 81008d6:	43db      	mvns	r3, r3
 81008d8:	69ba      	ldr	r2, [r7, #24]
 81008da:	4013      	ands	r3, r2
 81008dc:	61bb      	str	r3, [r7, #24]
      temp |= ((GPIO_Init->Pull) << (position * 2U));
 81008de:	683b      	ldr	r3, [r7, #0]
 81008e0:	689a      	ldr	r2, [r3, #8]
 81008e2:	69fb      	ldr	r3, [r7, #28]
 81008e4:	005b      	lsls	r3, r3, #1
 81008e6:	fa02 f303 	lsl.w	r3, r2, r3
 81008ea:	69ba      	ldr	r2, [r7, #24]
 81008ec:	4313      	orrs	r3, r2
 81008ee:	61bb      	str	r3, [r7, #24]
      GPIOx->PUPDR = temp;
 81008f0:	687b      	ldr	r3, [r7, #4]
 81008f2:	69ba      	ldr	r2, [r7, #24]
 81008f4:	60da      	str	r2, [r3, #12]
      }

      /* In case of Alternate function mode selection */
      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 81008f6:	683b      	ldr	r3, [r7, #0]
 81008f8:	685b      	ldr	r3, [r3, #4]
 81008fa:	f003 0303 	and.w	r3, r3, #3
 81008fe:	2b02      	cmp	r3, #2
 8100900:	d123      	bne.n	810094a <HAL_GPIO_Init+0x136>
        /* Check the Alternate function parameters */
        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));

        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3U];
 8100902:	69fb      	ldr	r3, [r7, #28]
 8100904:	08da      	lsrs	r2, r3, #3
 8100906:	687b      	ldr	r3, [r7, #4]
 8100908:	3208      	adds	r2, #8
 810090a:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 810090e:	61bb      	str	r3, [r7, #24]
        temp &= ~(0xFU << ((position & 0x07U) * 4U));
 8100910:	69fb      	ldr	r3, [r7, #28]
 8100912:	f003 0307 	and.w	r3, r3, #7
 8100916:	009b      	lsls	r3, r3, #2
 8100918:	220f      	movs	r2, #15
 810091a:	fa02 f303 	lsl.w	r3, r2, r3
 810091e:	43db      	mvns	r3, r3
 8100920:	69ba      	ldr	r2, [r7, #24]
 8100922:	4013      	ands	r3, r2
 8100924:	61bb      	str	r3, [r7, #24]
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
 8100926:	683b      	ldr	r3, [r7, #0]
 8100928:	691a      	ldr	r2, [r3, #16]
 810092a:	69fb      	ldr	r3, [r7, #28]
 810092c:	f003 0307 	and.w	r3, r3, #7
 8100930:	009b      	lsls	r3, r3, #2
 8100932:	fa02 f303 	lsl.w	r3, r2, r3
 8100936:	69ba      	ldr	r2, [r7, #24]
 8100938:	4313      	orrs	r3, r2
 810093a:	61bb      	str	r3, [r7, #24]
        GPIOx->AFR[position >> 3U] = temp;
 810093c:	69fb      	ldr	r3, [r7, #28]
 810093e:	08da      	lsrs	r2, r3, #3
 8100940:	687b      	ldr	r3, [r7, #4]
 8100942:	3208      	adds	r2, #8
 8100944:	69b9      	ldr	r1, [r7, #24]
 8100946:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 810094a:	687b      	ldr	r3, [r7, #4]
 810094c:	681b      	ldr	r3, [r3, #0]
 810094e:	61bb      	str	r3, [r7, #24]
      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
 8100950:	69fb      	ldr	r3, [r7, #28]
 8100952:	005b      	lsls	r3, r3, #1
 8100954:	2203      	movs	r2, #3
 8100956:	fa02 f303 	lsl.w	r3, r2, r3
 810095a:	43db      	mvns	r3, r3
 810095c:	69ba      	ldr	r2, [r7, #24]
 810095e:	4013      	ands	r3, r2
 8100960:	61bb      	str	r3, [r7, #24]
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
 8100962:	683b      	ldr	r3, [r7, #0]
 8100964:	685b      	ldr	r3, [r3, #4]
 8100966:	f003 0203 	and.w	r2, r3, #3
 810096a:	69fb      	ldr	r3, [r7, #28]
 810096c:	005b      	lsls	r3, r3, #1
 810096e:	fa02 f303 	lsl.w	r3, r2, r3
 8100972:	69ba      	ldr	r2, [r7, #24]
 8100974:	4313      	orrs	r3, r2
 8100976:	61bb      	str	r3, [r7, #24]
      GPIOx->MODER = temp;
 8100978:	687b      	ldr	r3, [r7, #4]
 810097a:	69ba      	ldr	r2, [r7, #24]
 810097c:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
 810097e:	683b      	ldr	r3, [r7, #0]
 8100980:	685b      	ldr	r3, [r3, #4]
 8100982:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 8100986:	2b00      	cmp	r3, #0
 8100988:	f000 80e0 	beq.w	8100b4c <HAL_GPIO_Init+0x338>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 810098c:	4b2f      	ldr	r3, [pc, #188]	@ (8100a4c <HAL_GPIO_Init+0x238>)
 810098e:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 8100992:	4a2e      	ldr	r2, [pc, #184]	@ (8100a4c <HAL_GPIO_Init+0x238>)
 8100994:	f043 0302 	orr.w	r3, r3, #2
 8100998:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
 810099c:	4b2b      	ldr	r3, [pc, #172]	@ (8100a4c <HAL_GPIO_Init+0x238>)
 810099e:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 81009a2:	f003 0302 	and.w	r3, r3, #2
 81009a6:	60fb      	str	r3, [r7, #12]
 81009a8:	68fb      	ldr	r3, [r7, #12]

        temp = SYSCFG->EXTICR[position >> 2U];
 81009aa:	4a29      	ldr	r2, [pc, #164]	@ (8100a50 <HAL_GPIO_Init+0x23c>)
 81009ac:	69fb      	ldr	r3, [r7, #28]
 81009ae:	089b      	lsrs	r3, r3, #2
 81009b0:	3302      	adds	r3, #2
 81009b2:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 81009b6:	61bb      	str	r3, [r7, #24]
        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
 81009b8:	69fb      	ldr	r3, [r7, #28]
 81009ba:	f003 0303 	and.w	r3, r3, #3
 81009be:	009b      	lsls	r3, r3, #2
 81009c0:	220f      	movs	r2, #15
 81009c2:	fa02 f303 	lsl.w	r3, r2, r3
 81009c6:	43db      	mvns	r3, r3
 81009c8:	69ba      	ldr	r2, [r7, #24]
 81009ca:	4013      	ands	r3, r2
 81009cc:	61bb      	str	r3, [r7, #24]
        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
 81009ce:	687b      	ldr	r3, [r7, #4]
 81009d0:	4a20      	ldr	r2, [pc, #128]	@ (8100a54 <HAL_GPIO_Init+0x240>)
 81009d2:	4293      	cmp	r3, r2
 81009d4:	d052      	beq.n	8100a7c <HAL_GPIO_Init+0x268>
 81009d6:	687b      	ldr	r3, [r7, #4]
 81009d8:	4a1f      	ldr	r2, [pc, #124]	@ (8100a58 <HAL_GPIO_Init+0x244>)
 81009da:	4293      	cmp	r3, r2
 81009dc:	d031      	beq.n	8100a42 <HAL_GPIO_Init+0x22e>
 81009de:	687b      	ldr	r3, [r7, #4]
 81009e0:	4a1e      	ldr	r2, [pc, #120]	@ (8100a5c <HAL_GPIO_Init+0x248>)
 81009e2:	4293      	cmp	r3, r2
 81009e4:	d02b      	beq.n	8100a3e <HAL_GPIO_Init+0x22a>
 81009e6:	687b      	ldr	r3, [r7, #4]
 81009e8:	4a1d      	ldr	r2, [pc, #116]	@ (8100a60 <HAL_GPIO_Init+0x24c>)
 81009ea:	4293      	cmp	r3, r2
 81009ec:	d025      	beq.n	8100a3a <HAL_GPIO_Init+0x226>
 81009ee:	687b      	ldr	r3, [r7, #4]
 81009f0:	4a1c      	ldr	r2, [pc, #112]	@ (8100a64 <HAL_GPIO_Init+0x250>)
 81009f2:	4293      	cmp	r3, r2
 81009f4:	d01f      	beq.n	8100a36 <HAL_GPIO_Init+0x222>
 81009f6:	687b      	ldr	r3, [r7, #4]
 81009f8:	4a1b      	ldr	r2, [pc, #108]	@ (8100a68 <HAL_GPIO_Init+0x254>)
 81009fa:	4293      	cmp	r3, r2
 81009fc:	d019      	beq.n	8100a32 <HAL_GPIO_Init+0x21e>
 81009fe:	687b      	ldr	r3, [r7, #4]
 8100a00:	4a1a      	ldr	r2, [pc, #104]	@ (8100a6c <HAL_GPIO_Init+0x258>)
 8100a02:	4293      	cmp	r3, r2
 8100a04:	d013      	beq.n	8100a2e <HAL_GPIO_Init+0x21a>
 8100a06:	687b      	ldr	r3, [r7, #4]
 8100a08:	4a19      	ldr	r2, [pc, #100]	@ (8100a70 <HAL_GPIO_Init+0x25c>)
 8100a0a:	4293      	cmp	r3, r2
 8100a0c:	d00d      	beq.n	8100a2a <HAL_GPIO_Init+0x216>
 8100a0e:	687b      	ldr	r3, [r7, #4]
 8100a10:	4a18      	ldr	r2, [pc, #96]	@ (8100a74 <HAL_GPIO_Init+0x260>)
 8100a12:	4293      	cmp	r3, r2
 8100a14:	d007      	beq.n	8100a26 <HAL_GPIO_Init+0x212>
 8100a16:	687b      	ldr	r3, [r7, #4]
 8100a18:	4a17      	ldr	r2, [pc, #92]	@ (8100a78 <HAL_GPIO_Init+0x264>)
 8100a1a:	4293      	cmp	r3, r2
 8100a1c:	d101      	bne.n	8100a22 <HAL_GPIO_Init+0x20e>
 8100a1e:	2309      	movs	r3, #9
 8100a20:	e02d      	b.n	8100a7e <HAL_GPIO_Init+0x26a>
 8100a22:	230a      	movs	r3, #10
 8100a24:	e02b      	b.n	8100a7e <HAL_GPIO_Init+0x26a>
 8100a26:	2308      	movs	r3, #8
 8100a28:	e029      	b.n	8100a7e <HAL_GPIO_Init+0x26a>
 8100a2a:	2307      	movs	r3, #7
 8100a2c:	e027      	b.n	8100a7e <HAL_GPIO_Init+0x26a>
 8100a2e:	2306      	movs	r3, #6
 8100a30:	e025      	b.n	8100a7e <HAL_GPIO_Init+0x26a>
 8100a32:	2305      	movs	r3, #5
 8100a34:	e023      	b.n	8100a7e <HAL_GPIO_Init+0x26a>
 8100a36:	2304      	movs	r3, #4
 8100a38:	e021      	b.n	8100a7e <HAL_GPIO_Init+0x26a>
 8100a3a:	2303      	movs	r3, #3
 8100a3c:	e01f      	b.n	8100a7e <HAL_GPIO_Init+0x26a>
 8100a3e:	2302      	movs	r3, #2
 8100a40:	e01d      	b.n	8100a7e <HAL_GPIO_Init+0x26a>
 8100a42:	2301      	movs	r3, #1
 8100a44:	e01b      	b.n	8100a7e <HAL_GPIO_Init+0x26a>
 8100a46:	bf00      	nop
 8100a48:	580000c0 	.word	0x580000c0
 8100a4c:	58024400 	.word	0x58024400
 8100a50:	58000400 	.word	0x58000400
 8100a54:	58020000 	.word	0x58020000
 8100a58:	58020400 	.word	0x58020400
 8100a5c:	58020800 	.word	0x58020800
 8100a60:	58020c00 	.word	0x58020c00
 8100a64:	58021000 	.word	0x58021000
 8100a68:	58021400 	.word	0x58021400
 8100a6c:	58021800 	.word	0x58021800
 8100a70:	58021c00 	.word	0x58021c00
 8100a74:	58022000 	.word	0x58022000
 8100a78:	58022400 	.word	0x58022400
 8100a7c:	2300      	movs	r3, #0
 8100a7e:	69fa      	ldr	r2, [r7, #28]
 8100a80:	f002 0203 	and.w	r2, r2, #3
 8100a84:	0092      	lsls	r2, r2, #2
 8100a86:	4093      	lsls	r3, r2
 8100a88:	69ba      	ldr	r2, [r7, #24]
 8100a8a:	4313      	orrs	r3, r2
 8100a8c:	61bb      	str	r3, [r7, #24]
        SYSCFG->EXTICR[position >> 2U] = temp;
 8100a8e:	4938      	ldr	r1, [pc, #224]	@ (8100b70 <HAL_GPIO_Init+0x35c>)
 8100a90:	69fb      	ldr	r3, [r7, #28]
 8100a92:	089b      	lsrs	r3, r3, #2
 8100a94:	3302      	adds	r3, #2
 8100a96:	69ba      	ldr	r2, [r7, #24]
 8100a98:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR1;
 8100a9c:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8100aa0:	681b      	ldr	r3, [r3, #0]
 8100aa2:	61bb      	str	r3, [r7, #24]
        temp &= ~(iocurrent);
 8100aa4:	693b      	ldr	r3, [r7, #16]
 8100aa6:	43db      	mvns	r3, r3
 8100aa8:	69ba      	ldr	r2, [r7, #24]
 8100aaa:	4013      	ands	r3, r2
 8100aac:	61bb      	str	r3, [r7, #24]
        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
 8100aae:	683b      	ldr	r3, [r7, #0]
 8100ab0:	685b      	ldr	r3, [r3, #4]
 8100ab2:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
 8100ab6:	2b00      	cmp	r3, #0
 8100ab8:	d003      	beq.n	8100ac2 <HAL_GPIO_Init+0x2ae>
        {
          temp |= iocurrent;
 8100aba:	69ba      	ldr	r2, [r7, #24]
 8100abc:	693b      	ldr	r3, [r7, #16]
 8100abe:	4313      	orrs	r3, r2
 8100ac0:	61bb      	str	r3, [r7, #24]
        }
        EXTI->RTSR1 = temp;
 8100ac2:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 8100ac6:	69bb      	ldr	r3, [r7, #24]
 8100ac8:	6013      	str	r3, [r2, #0]

        temp = EXTI->FTSR1;
 8100aca:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8100ace:	685b      	ldr	r3, [r3, #4]
 8100ad0:	61bb      	str	r3, [r7, #24]
        temp &= ~(iocurrent);
 8100ad2:	693b      	ldr	r3, [r7, #16]
 8100ad4:	43db      	mvns	r3, r3
 8100ad6:	69ba      	ldr	r2, [r7, #24]
 8100ad8:	4013      	ands	r3, r2
 8100ada:	61bb      	str	r3, [r7, #24]
        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
 8100adc:	683b      	ldr	r3, [r7, #0]
 8100ade:	685b      	ldr	r3, [r3, #4]
 8100ae0:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
 8100ae4:	2b00      	cmp	r3, #0
 8100ae6:	d003      	beq.n	8100af0 <HAL_GPIO_Init+0x2dc>
        {
          temp |= iocurrent;
 8100ae8:	69ba      	ldr	r2, [r7, #24]
 8100aea:	693b      	ldr	r3, [r7, #16]
 8100aec:	4313      	orrs	r3, r2
 8100aee:	61bb      	str	r3, [r7, #24]
        }
        EXTI->FTSR1 = temp;
 8100af0:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 8100af4:	69bb      	ldr	r3, [r7, #24]
 8100af6:	6053      	str	r3, [r2, #4]

        temp = EXTI_CurrentCPU->EMR1;
 8100af8:	697b      	ldr	r3, [r7, #20]
 8100afa:	685b      	ldr	r3, [r3, #4]
 8100afc:	61bb      	str	r3, [r7, #24]
        temp &= ~(iocurrent);
 8100afe:	693b      	ldr	r3, [r7, #16]
 8100b00:	43db      	mvns	r3, r3
 8100b02:	69ba      	ldr	r2, [r7, #24]
 8100b04:	4013      	ands	r3, r2
 8100b06:	61bb      	str	r3, [r7, #24]
        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
 8100b08:	683b      	ldr	r3, [r7, #0]
 8100b0a:	685b      	ldr	r3, [r3, #4]
 8100b0c:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8100b10:	2b00      	cmp	r3, #0
 8100b12:	d003      	beq.n	8100b1c <HAL_GPIO_Init+0x308>
        {
          temp |= iocurrent;
 8100b14:	69ba      	ldr	r2, [r7, #24]
 8100b16:	693b      	ldr	r3, [r7, #16]
 8100b18:	4313      	orrs	r3, r2
 8100b1a:	61bb      	str	r3, [r7, #24]
        }
        EXTI_CurrentCPU->EMR1 = temp;
 8100b1c:	697b      	ldr	r3, [r7, #20]
 8100b1e:	69ba      	ldr	r2, [r7, #24]
 8100b20:	605a      	str	r2, [r3, #4]

        /* Clear EXTI line configuration */
        temp = EXTI_CurrentCPU->IMR1;
 8100b22:	697b      	ldr	r3, [r7, #20]
 8100b24:	681b      	ldr	r3, [r3, #0]
 8100b26:	61bb      	str	r3, [r7, #24]
        temp &= ~(iocurrent);
 8100b28:	693b      	ldr	r3, [r7, #16]
 8100b2a:	43db      	mvns	r3, r3
 8100b2c:	69ba      	ldr	r2, [r7, #24]
 8100b2e:	4013      	ands	r3, r2
 8100b30:	61bb      	str	r3, [r7, #24]
        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
 8100b32:	683b      	ldr	r3, [r7, #0]
 8100b34:	685b      	ldr	r3, [r3, #4]
 8100b36:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 8100b3a:	2b00      	cmp	r3, #0
 8100b3c:	d003      	beq.n	8100b46 <HAL_GPIO_Init+0x332>
        {
          temp |= iocurrent;
 8100b3e:	69ba      	ldr	r2, [r7, #24]
 8100b40:	693b      	ldr	r3, [r7, #16]
 8100b42:	4313      	orrs	r3, r2
 8100b44:	61bb      	str	r3, [r7, #24]
        }
        EXTI_CurrentCPU->IMR1 = temp;
 8100b46:	697b      	ldr	r3, [r7, #20]
 8100b48:	69ba      	ldr	r2, [r7, #24]
 8100b4a:	601a      	str	r2, [r3, #0]
      }
    }

    position++;
 8100b4c:	69fb      	ldr	r3, [r7, #28]
 8100b4e:	3301      	adds	r3, #1
 8100b50:	61fb      	str	r3, [r7, #28]
  while (((GPIO_Init->Pin) >> position) != 0x00U)
 8100b52:	683b      	ldr	r3, [r7, #0]
 8100b54:	681a      	ldr	r2, [r3, #0]
 8100b56:	69fb      	ldr	r3, [r7, #28]
 8100b58:	fa22 f303 	lsr.w	r3, r2, r3
 8100b5c:	2b00      	cmp	r3, #0
 8100b5e:	f47f ae63 	bne.w	8100828 <HAL_GPIO_Init+0x14>
  }
}
 8100b62:	bf00      	nop
 8100b64:	bf00      	nop
 8100b66:	3724      	adds	r7, #36	@ 0x24
 8100b68:	46bd      	mov	sp, r7
 8100b6a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8100b6e:	4770      	bx	lr
 8100b70:	58000400 	.word	0x58000400

08100b74 <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8100b74:	b480      	push	{r7}
 8100b76:	b089      	sub	sp, #36	@ 0x24
 8100b78:	af00      	add	r7, sp, #0
  float_t fracn1, pllvco;
  uint32_t sysclockfreq;

  /* Get SYSCLK source -------------------------------------------------------*/

  switch (RCC->CFGR & RCC_CFGR_SWS)
 8100b7a:	4bb3      	ldr	r3, [pc, #716]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100b7c:	691b      	ldr	r3, [r3, #16]
 8100b7e:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 8100b82:	2b18      	cmp	r3, #24
 8100b84:	f200 8155 	bhi.w	8100e32 <HAL_RCC_GetSysClockFreq+0x2be>
 8100b88:	a201      	add	r2, pc, #4	@ (adr r2, 8100b90 <HAL_RCC_GetSysClockFreq+0x1c>)
 8100b8a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8100b8e:	bf00      	nop
 8100b90:	08100bf5 	.word	0x08100bf5
 8100b94:	08100e33 	.word	0x08100e33
 8100b98:	08100e33 	.word	0x08100e33
 8100b9c:	08100e33 	.word	0x08100e33
 8100ba0:	08100e33 	.word	0x08100e33
 8100ba4:	08100e33 	.word	0x08100e33
 8100ba8:	08100e33 	.word	0x08100e33
 8100bac:	08100e33 	.word	0x08100e33
 8100bb0:	08100c1b 	.word	0x08100c1b
 8100bb4:	08100e33 	.word	0x08100e33
 8100bb8:	08100e33 	.word	0x08100e33
 8100bbc:	08100e33 	.word	0x08100e33
 8100bc0:	08100e33 	.word	0x08100e33
 8100bc4:	08100e33 	.word	0x08100e33
 8100bc8:	08100e33 	.word	0x08100e33
 8100bcc:	08100e33 	.word	0x08100e33
 8100bd0:	08100c21 	.word	0x08100c21
 8100bd4:	08100e33 	.word	0x08100e33
 8100bd8:	08100e33 	.word	0x08100e33
 8100bdc:	08100e33 	.word	0x08100e33
 8100be0:	08100e33 	.word	0x08100e33
 8100be4:	08100e33 	.word	0x08100e33
 8100be8:	08100e33 	.word	0x08100e33
 8100bec:	08100e33 	.word	0x08100e33
 8100bf0:	08100c27 	.word	0x08100c27
  {
  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */

   if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 8100bf4:	4b94      	ldr	r3, [pc, #592]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100bf6:	681b      	ldr	r3, [r3, #0]
 8100bf8:	f003 0320 	and.w	r3, r3, #32
 8100bfc:	2b00      	cmp	r3, #0
 8100bfe:	d009      	beq.n	8100c14 <HAL_RCC_GetSysClockFreq+0xa0>
      {
        sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
 8100c00:	4b91      	ldr	r3, [pc, #580]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100c02:	681b      	ldr	r3, [r3, #0]
 8100c04:	08db      	lsrs	r3, r3, #3
 8100c06:	f003 0303 	and.w	r3, r3, #3
 8100c0a:	4a90      	ldr	r2, [pc, #576]	@ (8100e4c <HAL_RCC_GetSysClockFreq+0x2d8>)
 8100c0c:	fa22 f303 	lsr.w	r3, r2, r3
 8100c10:	61bb      	str	r3, [r7, #24]
      else
      {
        sysclockfreq = (uint32_t) HSI_VALUE;
      }

    break;
 8100c12:	e111      	b.n	8100e38 <HAL_RCC_GetSysClockFreq+0x2c4>
        sysclockfreq = (uint32_t) HSI_VALUE;
 8100c14:	4b8d      	ldr	r3, [pc, #564]	@ (8100e4c <HAL_RCC_GetSysClockFreq+0x2d8>)
 8100c16:	61bb      	str	r3, [r7, #24]
    break;
 8100c18:	e10e      	b.n	8100e38 <HAL_RCC_GetSysClockFreq+0x2c4>

  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
    sysclockfreq = CSI_VALUE;
 8100c1a:	4b8d      	ldr	r3, [pc, #564]	@ (8100e50 <HAL_RCC_GetSysClockFreq+0x2dc>)
 8100c1c:	61bb      	str	r3, [r7, #24]
    break;
 8100c1e:	e10b      	b.n	8100e38 <HAL_RCC_GetSysClockFreq+0x2c4>

  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
    sysclockfreq = HSE_VALUE;
 8100c20:	4b8c      	ldr	r3, [pc, #560]	@ (8100e54 <HAL_RCC_GetSysClockFreq+0x2e0>)
 8100c22:	61bb      	str	r3, [r7, #24]
    break;
 8100c24:	e108      	b.n	8100e38 <HAL_RCC_GetSysClockFreq+0x2c4>
  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */

    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
    SYSCLK = PLL_VCO / PLLR
    */
    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
 8100c26:	4b88      	ldr	r3, [pc, #544]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100c28:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8100c2a:	f003 0303 	and.w	r3, r3, #3
 8100c2e:	617b      	str	r3, [r7, #20]
    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
 8100c30:	4b85      	ldr	r3, [pc, #532]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100c32:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8100c34:	091b      	lsrs	r3, r3, #4
 8100c36:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
 8100c3a:	613b      	str	r3, [r7, #16]
    pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
 8100c3c:	4b82      	ldr	r3, [pc, #520]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100c3e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8100c40:	f003 0301 	and.w	r3, r3, #1
 8100c44:	60fb      	str	r3, [r7, #12]
    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
 8100c46:	4b80      	ldr	r3, [pc, #512]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100c48:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 8100c4a:	08db      	lsrs	r3, r3, #3
 8100c4c:	f3c3 030c 	ubfx	r3, r3, #0, #13
 8100c50:	68fa      	ldr	r2, [r7, #12]
 8100c52:	fb02 f303 	mul.w	r3, r2, r3
 8100c56:	ee07 3a90 	vmov	s15, r3
 8100c5a:	eef8 7a67 	vcvt.f32.u32	s15, s15
 8100c5e:	edc7 7a02 	vstr	s15, [r7, #8]

    if (pllm != 0U)
 8100c62:	693b      	ldr	r3, [r7, #16]
 8100c64:	2b00      	cmp	r3, #0
 8100c66:	f000 80e1 	beq.w	8100e2c <HAL_RCC_GetSysClockFreq+0x2b8>
 8100c6a:	697b      	ldr	r3, [r7, #20]
 8100c6c:	2b02      	cmp	r3, #2
 8100c6e:	f000 8083 	beq.w	8100d78 <HAL_RCC_GetSysClockFreq+0x204>
 8100c72:	697b      	ldr	r3, [r7, #20]
 8100c74:	2b02      	cmp	r3, #2
 8100c76:	f200 80a1 	bhi.w	8100dbc <HAL_RCC_GetSysClockFreq+0x248>
 8100c7a:	697b      	ldr	r3, [r7, #20]
 8100c7c:	2b00      	cmp	r3, #0
 8100c7e:	d003      	beq.n	8100c88 <HAL_RCC_GetSysClockFreq+0x114>
 8100c80:	697b      	ldr	r3, [r7, #20]
 8100c82:	2b01      	cmp	r3, #1
 8100c84:	d056      	beq.n	8100d34 <HAL_RCC_GetSysClockFreq+0x1c0>
 8100c86:	e099      	b.n	8100dbc <HAL_RCC_GetSysClockFreq+0x248>
    {
      switch (pllsource)
      {
      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */

       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 8100c88:	4b6f      	ldr	r3, [pc, #444]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100c8a:	681b      	ldr	r3, [r3, #0]
 8100c8c:	f003 0320 	and.w	r3, r3, #32
 8100c90:	2b00      	cmp	r3, #0
 8100c92:	d02d      	beq.n	8100cf0 <HAL_RCC_GetSysClockFreq+0x17c>
        {
          hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
 8100c94:	4b6c      	ldr	r3, [pc, #432]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100c96:	681b      	ldr	r3, [r3, #0]
 8100c98:	08db      	lsrs	r3, r3, #3
 8100c9a:	f003 0303 	and.w	r3, r3, #3
 8100c9e:	4a6b      	ldr	r2, [pc, #428]	@ (8100e4c <HAL_RCC_GetSysClockFreq+0x2d8>)
 8100ca0:	fa22 f303 	lsr.w	r3, r2, r3
 8100ca4:	607b      	str	r3, [r7, #4]
          pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
 8100ca6:	687b      	ldr	r3, [r7, #4]
 8100ca8:	ee07 3a90 	vmov	s15, r3
 8100cac:	eef8 6a67 	vcvt.f32.u32	s13, s15
 8100cb0:	693b      	ldr	r3, [r7, #16]
 8100cb2:	ee07 3a90 	vmov	s15, r3
 8100cb6:	eef8 7a67 	vcvt.f32.u32	s15, s15
 8100cba:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 8100cbe:	4b62      	ldr	r3, [pc, #392]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100cc0:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8100cc2:	f3c3 0308 	ubfx	r3, r3, #0, #9
 8100cc6:	ee07 3a90 	vmov	s15, r3
 8100cca:	eef8 6a67 	vcvt.f32.u32	s13, s15
 8100cce:	ed97 6a02 	vldr	s12, [r7, #8]
 8100cd2:	eddf 5a61 	vldr	s11, [pc, #388]	@ 8100e58 <HAL_RCC_GetSysClockFreq+0x2e4>
 8100cd6:	eec6 7a25 	vdiv.f32	s15, s12, s11
 8100cda:	ee76 7aa7 	vadd.f32	s15, s13, s15
 8100cde:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 8100ce2:	ee77 7aa6 	vadd.f32	s15, s15, s13
 8100ce6:	ee67 7a27 	vmul.f32	s15, s14, s15
 8100cea:	edc7 7a07 	vstr	s15, [r7, #28]
        }
        else
        {
          pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
        }
        break;
 8100cee:	e087      	b.n	8100e00 <HAL_RCC_GetSysClockFreq+0x28c>
          pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
 8100cf0:	693b      	ldr	r3, [r7, #16]
 8100cf2:	ee07 3a90 	vmov	s15, r3
 8100cf6:	eef8 7a67 	vcvt.f32.u32	s15, s15
 8100cfa:	eddf 6a58 	vldr	s13, [pc, #352]	@ 8100e5c <HAL_RCC_GetSysClockFreq+0x2e8>
 8100cfe:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 8100d02:	4b51      	ldr	r3, [pc, #324]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100d04:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8100d06:	f3c3 0308 	ubfx	r3, r3, #0, #9
 8100d0a:	ee07 3a90 	vmov	s15, r3
 8100d0e:	eef8 6a67 	vcvt.f32.u32	s13, s15
 8100d12:	ed97 6a02 	vldr	s12, [r7, #8]
 8100d16:	eddf 5a50 	vldr	s11, [pc, #320]	@ 8100e58 <HAL_RCC_GetSysClockFreq+0x2e4>
 8100d1a:	eec6 7a25 	vdiv.f32	s15, s12, s11
 8100d1e:	ee76 7aa7 	vadd.f32	s15, s13, s15
 8100d22:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 8100d26:	ee77 7aa6 	vadd.f32	s15, s15, s13
 8100d2a:	ee67 7a27 	vmul.f32	s15, s14, s15
 8100d2e:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 8100d32:	e065      	b.n	8100e00 <HAL_RCC_GetSysClockFreq+0x28c>

      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
 8100d34:	693b      	ldr	r3, [r7, #16]
 8100d36:	ee07 3a90 	vmov	s15, r3
 8100d3a:	eef8 7a67 	vcvt.f32.u32	s15, s15
 8100d3e:	eddf 6a48 	vldr	s13, [pc, #288]	@ 8100e60 <HAL_RCC_GetSysClockFreq+0x2ec>
 8100d42:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 8100d46:	4b40      	ldr	r3, [pc, #256]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100d48:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8100d4a:	f3c3 0308 	ubfx	r3, r3, #0, #9
 8100d4e:	ee07 3a90 	vmov	s15, r3
 8100d52:	eef8 6a67 	vcvt.f32.u32	s13, s15
 8100d56:	ed97 6a02 	vldr	s12, [r7, #8]
 8100d5a:	eddf 5a3f 	vldr	s11, [pc, #252]	@ 8100e58 <HAL_RCC_GetSysClockFreq+0x2e4>
 8100d5e:	eec6 7a25 	vdiv.f32	s15, s12, s11
 8100d62:	ee76 7aa7 	vadd.f32	s15, s13, s15
 8100d66:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 8100d6a:	ee77 7aa6 	vadd.f32	s15, s15, s13
 8100d6e:	ee67 7a27 	vmul.f32	s15, s14, s15
 8100d72:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 8100d76:	e043      	b.n	8100e00 <HAL_RCC_GetSysClockFreq+0x28c>

      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
        pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
 8100d78:	693b      	ldr	r3, [r7, #16]
 8100d7a:	ee07 3a90 	vmov	s15, r3
 8100d7e:	eef8 7a67 	vcvt.f32.u32	s15, s15
 8100d82:	eddf 6a38 	vldr	s13, [pc, #224]	@ 8100e64 <HAL_RCC_GetSysClockFreq+0x2f0>
 8100d86:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 8100d8a:	4b2f      	ldr	r3, [pc, #188]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100d8c:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8100d8e:	f3c3 0308 	ubfx	r3, r3, #0, #9
 8100d92:	ee07 3a90 	vmov	s15, r3
 8100d96:	eef8 6a67 	vcvt.f32.u32	s13, s15
 8100d9a:	ed97 6a02 	vldr	s12, [r7, #8]
 8100d9e:	eddf 5a2e 	vldr	s11, [pc, #184]	@ 8100e58 <HAL_RCC_GetSysClockFreq+0x2e4>
 8100da2:	eec6 7a25 	vdiv.f32	s15, s12, s11
 8100da6:	ee76 7aa7 	vadd.f32	s15, s13, s15
 8100daa:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 8100dae:	ee77 7aa6 	vadd.f32	s15, s15, s13
 8100db2:	ee67 7a27 	vmul.f32	s15, s14, s15
 8100db6:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 8100dba:	e021      	b.n	8100e00 <HAL_RCC_GetSysClockFreq+0x28c>

      default:
        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
 8100dbc:	693b      	ldr	r3, [r7, #16]
 8100dbe:	ee07 3a90 	vmov	s15, r3
 8100dc2:	eef8 7a67 	vcvt.f32.u32	s15, s15
 8100dc6:	eddf 6a26 	vldr	s13, [pc, #152]	@ 8100e60 <HAL_RCC_GetSysClockFreq+0x2ec>
 8100dca:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 8100dce:	4b1e      	ldr	r3, [pc, #120]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100dd0:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8100dd2:	f3c3 0308 	ubfx	r3, r3, #0, #9
 8100dd6:	ee07 3a90 	vmov	s15, r3
 8100dda:	eef8 6a67 	vcvt.f32.u32	s13, s15
 8100dde:	ed97 6a02 	vldr	s12, [r7, #8]
 8100de2:	eddf 5a1d 	vldr	s11, [pc, #116]	@ 8100e58 <HAL_RCC_GetSysClockFreq+0x2e4>
 8100de6:	eec6 7a25 	vdiv.f32	s15, s12, s11
 8100dea:	ee76 7aa7 	vadd.f32	s15, s13, s15
 8100dee:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 8100df2:	ee77 7aa6 	vadd.f32	s15, s15, s13
 8100df6:	ee67 7a27 	vmul.f32	s15, s14, s15
 8100dfa:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 8100dfe:	bf00      	nop
      }
      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
 8100e00:	4b11      	ldr	r3, [pc, #68]	@ (8100e48 <HAL_RCC_GetSysClockFreq+0x2d4>)
 8100e02:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8100e04:	0a5b      	lsrs	r3, r3, #9
 8100e06:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 8100e0a:	3301      	adds	r3, #1
 8100e0c:	603b      	str	r3, [r7, #0]
      sysclockfreq =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
 8100e0e:	683b      	ldr	r3, [r7, #0]
 8100e10:	ee07 3a90 	vmov	s15, r3
 8100e14:	eeb8 7a67 	vcvt.f32.u32	s14, s15
 8100e18:	edd7 6a07 	vldr	s13, [r7, #28]
 8100e1c:	eec6 7a87 	vdiv.f32	s15, s13, s14
 8100e20:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 8100e24:	ee17 3a90 	vmov	r3, s15
 8100e28:	61bb      	str	r3, [r7, #24]
    }
    else
    {
      sysclockfreq = 0U;
    }
    break;
 8100e2a:	e005      	b.n	8100e38 <HAL_RCC_GetSysClockFreq+0x2c4>
      sysclockfreq = 0U;
 8100e2c:	2300      	movs	r3, #0
 8100e2e:	61bb      	str	r3, [r7, #24]
    break;
 8100e30:	e002      	b.n	8100e38 <HAL_RCC_GetSysClockFreq+0x2c4>

  default:
    sysclockfreq = CSI_VALUE;
 8100e32:	4b07      	ldr	r3, [pc, #28]	@ (8100e50 <HAL_RCC_GetSysClockFreq+0x2dc>)
 8100e34:	61bb      	str	r3, [r7, #24]
    break;
 8100e36:	bf00      	nop
  }

  return sysclockfreq;
 8100e38:	69bb      	ldr	r3, [r7, #24]
}
 8100e3a:	4618      	mov	r0, r3
 8100e3c:	3724      	adds	r7, #36	@ 0x24
 8100e3e:	46bd      	mov	sp, r7
 8100e40:	f85d 7b04 	ldr.w	r7, [sp], #4
 8100e44:	4770      	bx	lr
 8100e46:	bf00      	nop
 8100e48:	58024400 	.word	0x58024400
 8100e4c:	03d09000 	.word	0x03d09000
 8100e50:	003d0900 	.word	0x003d0900
 8100e54:	017d7840 	.word	0x017d7840
 8100e58:	46000000 	.word	0x46000000
 8100e5c:	4c742400 	.word	0x4c742400
 8100e60:	4a742400 	.word	0x4a742400
 8100e64:	4bbebc20 	.word	0x4bbebc20

08100e68 <__libc_init_array>:
 8100e68:	b570      	push	{r4, r5, r6, lr}
 8100e6a:	4d0d      	ldr	r5, [pc, #52]	@ (8100ea0 <__libc_init_array+0x38>)
 8100e6c:	4c0d      	ldr	r4, [pc, #52]	@ (8100ea4 <__libc_init_array+0x3c>)
 8100e6e:	1b64      	subs	r4, r4, r5
 8100e70:	10a4      	asrs	r4, r4, #2
 8100e72:	2600      	movs	r6, #0
 8100e74:	42a6      	cmp	r6, r4
 8100e76:	d109      	bne.n	8100e8c <__libc_init_array+0x24>
 8100e78:	4d0b      	ldr	r5, [pc, #44]	@ (8100ea8 <__libc_init_array+0x40>)
 8100e7a:	4c0c      	ldr	r4, [pc, #48]	@ (8100eac <__libc_init_array+0x44>)
 8100e7c:	f000 f818 	bl	8100eb0 <_init>
 8100e80:	1b64      	subs	r4, r4, r5
 8100e82:	10a4      	asrs	r4, r4, #2
 8100e84:	2600      	movs	r6, #0
 8100e86:	42a6      	cmp	r6, r4
 8100e88:	d105      	bne.n	8100e96 <__libc_init_array+0x2e>
 8100e8a:	bd70      	pop	{r4, r5, r6, pc}
 8100e8c:	f855 3b04 	ldr.w	r3, [r5], #4
 8100e90:	4798      	blx	r3
 8100e92:	3601      	adds	r6, #1
 8100e94:	e7ee      	b.n	8100e74 <__libc_init_array+0xc>
 8100e96:	f855 3b04 	ldr.w	r3, [r5], #4
 8100e9a:	4798      	blx	r3
 8100e9c:	3601      	adds	r6, #1
 8100e9e:	e7f2      	b.n	8100e86 <__libc_init_array+0x1e>
 8100ea0:	08100ed8 	.word	0x08100ed8
 8100ea4:	08100ed8 	.word	0x08100ed8
 8100ea8:	08100ed8 	.word	0x08100ed8
 8100eac:	08100edc 	.word	0x08100edc

08100eb0 <_init>:
 8100eb0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8100eb2:	bf00      	nop
 8100eb4:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8100eb6:	bc08      	pop	{r3}
 8100eb8:	469e      	mov	lr, r3
 8100eba:	4770      	bx	lr

08100ebc <_fini>:
 8100ebc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8100ebe:	bf00      	nop
 8100ec0:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8100ec2:	bc08      	pop	{r3}
 8100ec4:	469e      	mov	lr, r3
 8100ec6:	4770      	bx	lr