node-red-STM32/OZE_Sensor/Debug/OZE_Sensor.list

OZE_Sensor.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000298  08000000  08000000  00001000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00018628  080002a0  080002a0  000012a0  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       000001d4  080188c8  080188c8  000198c8  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM          00000008  08018a9c  08018a9c  00019a9c  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  4 .init_array   00000004  08018aa4  08018aa4  00019aa4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .fini_array   00000004  08018aa8  08018aa8  00019aa8  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  6 .data         000000a4  24000000  08018aac  0001a000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .bss          00012d20  240000c0  08018b50  0001a0c0  2**5
                  ALLOC
  8 ._user_heap_stack 00000600  24012de0  08018b50  0001ade0  2**0
                  ALLOC
  9 .ARM.attributes 0000002e  00000000  00000000  0001a0a4  2**0
                  CONTENTS, READONLY
 10 .debug_info   000340b6  00000000  00000000  0001a0d2  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 11 .debug_abbrev 000062fd  00000000  00000000  0004e188  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 12 .debug_aranges 000024e0  00000000  00000000  00054488  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 13 .debug_macro  0003f37d  00000000  00000000  00056968  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_line   000307a6  00000000  00000000  00095ce5  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_str    00187dfb  00000000  00000000  000c648b  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .comment      00000043  00000000  00000000  0024e286  2**0
                  CONTENTS, READONLY
 17 .debug_rnglists 00001c67  00000000  00000000  0024e2c9  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_frame  0000a318  00000000  00000000  0024ff30  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .debug_line_str 00000066  00000000  00000000  0025a248  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

080002a0 <__do_global_dtors_aux>:
 80002a0:	b510      	push	{r4, lr}
 80002a2:	4c05      	ldr	r4, [pc, #20]	@ (80002b8 <__do_global_dtors_aux+0x18>)
 80002a4:	7823      	ldrb	r3, [r4, #0]
 80002a6:	b933      	cbnz	r3, 80002b6 <__do_global_dtors_aux+0x16>
 80002a8:	4b04      	ldr	r3, [pc, #16]	@ (80002bc <__do_global_dtors_aux+0x1c>)
 80002aa:	b113      	cbz	r3, 80002b2 <__do_global_dtors_aux+0x12>
 80002ac:	4804      	ldr	r0, [pc, #16]	@ (80002c0 <__do_global_dtors_aux+0x20>)
 80002ae:	f3af 8000 	nop.w
 80002b2:	2301      	movs	r3, #1
 80002b4:	7023      	strb	r3, [r4, #0]
 80002b6:	bd10      	pop	{r4, pc}
 80002b8:	240000c0 	.word	0x240000c0
 80002bc:	00000000 	.word	0x00000000
 80002c0:	080188b0 	.word	0x080188b0

080002c4 <frame_dummy>:
 80002c4:	b508      	push	{r3, lr}
 80002c6:	4b03      	ldr	r3, [pc, #12]	@ (80002d4 <frame_dummy+0x10>)
 80002c8:	b11b      	cbz	r3, 80002d2 <frame_dummy+0xe>
 80002ca:	4903      	ldr	r1, [pc, #12]	@ (80002d8 <frame_dummy+0x14>)
 80002cc:	4803      	ldr	r0, [pc, #12]	@ (80002dc <frame_dummy+0x18>)
 80002ce:	f3af 8000 	nop.w
 80002d2:	bd08      	pop	{r3, pc}
 80002d4:	00000000 	.word	0x00000000
 80002d8:	240000c4 	.word	0x240000c4
 80002dc:	080188b0 	.word	0x080188b0

080002e0 <memchr>:
 80002e0:	f001 01ff 	and.w	r1, r1, #255	@ 0xff
 80002e4:	2a10      	cmp	r2, #16
 80002e6:	db2b      	blt.n	8000340 <memchr+0x60>
 80002e8:	f010 0f07 	tst.w	r0, #7
 80002ec:	d008      	beq.n	8000300 <memchr+0x20>
 80002ee:	f810 3b01 	ldrb.w	r3, [r0], #1
 80002f2:	3a01      	subs	r2, #1
 80002f4:	428b      	cmp	r3, r1
 80002f6:	d02d      	beq.n	8000354 <memchr+0x74>
 80002f8:	f010 0f07 	tst.w	r0, #7
 80002fc:	b342      	cbz	r2, 8000350 <memchr+0x70>
 80002fe:	d1f6      	bne.n	80002ee <memchr+0xe>
 8000300:	b4f0      	push	{r4, r5, r6, r7}
 8000302:	ea41 2101 	orr.w	r1, r1, r1, lsl #8
 8000306:	ea41 4101 	orr.w	r1, r1, r1, lsl #16
 800030a:	f022 0407 	bic.w	r4, r2, #7
 800030e:	f07f 0700 	mvns.w	r7, #0
 8000312:	2300      	movs	r3, #0
 8000314:	e8f0 5602 	ldrd	r5, r6, [r0], #8
 8000318:	3c08      	subs	r4, #8
 800031a:	ea85 0501 	eor.w	r5, r5, r1
 800031e:	ea86 0601 	eor.w	r6, r6, r1
 8000322:	fa85 f547 	uadd8	r5, r5, r7
 8000326:	faa3 f587 	sel	r5, r3, r7
 800032a:	fa86 f647 	uadd8	r6, r6, r7
 800032e:	faa5 f687 	sel	r6, r5, r7
 8000332:	b98e      	cbnz	r6, 8000358 <memchr+0x78>
 8000334:	d1ee      	bne.n	8000314 <memchr+0x34>
 8000336:	bcf0      	pop	{r4, r5, r6, r7}
 8000338:	f001 01ff 	and.w	r1, r1, #255	@ 0xff
 800033c:	f002 0207 	and.w	r2, r2, #7
 8000340:	b132      	cbz	r2, 8000350 <memchr+0x70>
 8000342:	f810 3b01 	ldrb.w	r3, [r0], #1
 8000346:	3a01      	subs	r2, #1
 8000348:	ea83 0301 	eor.w	r3, r3, r1
 800034c:	b113      	cbz	r3, 8000354 <memchr+0x74>
 800034e:	d1f8      	bne.n	8000342 <memchr+0x62>
 8000350:	2000      	movs	r0, #0
 8000352:	4770      	bx	lr
 8000354:	3801      	subs	r0, #1
 8000356:	4770      	bx	lr
 8000358:	2d00      	cmp	r5, #0
 800035a:	bf06      	itte	eq
 800035c:	4635      	moveq	r5, r6
 800035e:	3803      	subeq	r0, #3
 8000360:	3807      	subne	r0, #7
 8000362:	f015 0f01 	tst.w	r5, #1
 8000366:	d107      	bne.n	8000378 <memchr+0x98>
 8000368:	3001      	adds	r0, #1
 800036a:	f415 7f80 	tst.w	r5, #256	@ 0x100
 800036e:	bf02      	ittt	eq
 8000370:	3001      	addeq	r0, #1
 8000372:	f415 3fc0 	tsteq.w	r5, #98304	@ 0x18000
 8000376:	3001      	addeq	r0, #1
 8000378:	bcf0      	pop	{r4, r5, r6, r7}
 800037a:	3801      	subs	r0, #1
 800037c:	4770      	bx	lr
 800037e:	bf00      	nop

08000380 <__aeabi_uldivmod>:
 8000380:	b953      	cbnz	r3, 8000398 <__aeabi_uldivmod+0x18>
 8000382:	b94a      	cbnz	r2, 8000398 <__aeabi_uldivmod+0x18>
 8000384:	2900      	cmp	r1, #0
 8000386:	bf08      	it	eq
 8000388:	2800      	cmpeq	r0, #0
 800038a:	bf1c      	itt	ne
 800038c:	f04f 31ff 	movne.w	r1, #4294967295	@ 0xffffffff
 8000390:	f04f 30ff 	movne.w	r0, #4294967295	@ 0xffffffff
 8000394:	f000 b96a 	b.w	800066c <__aeabi_idiv0>
 8000398:	f1ad 0c08 	sub.w	ip, sp, #8
 800039c:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 80003a0:	f000 f806 	bl	80003b0 <__udivmoddi4>
 80003a4:	f8dd e004 	ldr.w	lr, [sp, #4]
 80003a8:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 80003ac:	b004      	add	sp, #16
 80003ae:	4770      	bx	lr

080003b0 <__udivmoddi4>:
 80003b0:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 80003b4:	9d08      	ldr	r5, [sp, #32]
 80003b6:	460c      	mov	r4, r1
 80003b8:	2b00      	cmp	r3, #0
 80003ba:	d14e      	bne.n	800045a <__udivmoddi4+0xaa>
 80003bc:	4694      	mov	ip, r2
 80003be:	458c      	cmp	ip, r1
 80003c0:	4686      	mov	lr, r0
 80003c2:	fab2 f282 	clz	r2, r2
 80003c6:	d962      	bls.n	800048e <__udivmoddi4+0xde>
 80003c8:	b14a      	cbz	r2, 80003de <__udivmoddi4+0x2e>
 80003ca:	f1c2 0320 	rsb	r3, r2, #32
 80003ce:	4091      	lsls	r1, r2
 80003d0:	fa20 f303 	lsr.w	r3, r0, r3
 80003d4:	fa0c fc02 	lsl.w	ip, ip, r2
 80003d8:	4319      	orrs	r1, r3
 80003da:	fa00 fe02 	lsl.w	lr, r0, r2
 80003de:	ea4f 471c 	mov.w	r7, ip, lsr #16
 80003e2:	fa1f f68c 	uxth.w	r6, ip
 80003e6:	fbb1 f4f7 	udiv	r4, r1, r7
 80003ea:	ea4f 431e 	mov.w	r3, lr, lsr #16
 80003ee:	fb07 1114 	mls	r1, r7, r4, r1
 80003f2:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
 80003f6:	fb04 f106 	mul.w	r1, r4, r6
 80003fa:	4299      	cmp	r1, r3
 80003fc:	d90a      	bls.n	8000414 <__udivmoddi4+0x64>
 80003fe:	eb1c 0303 	adds.w	r3, ip, r3
 8000402:	f104 30ff 	add.w	r0, r4, #4294967295	@ 0xffffffff
 8000406:	f080 8112 	bcs.w	800062e <__udivmoddi4+0x27e>
 800040a:	4299      	cmp	r1, r3
 800040c:	f240 810f 	bls.w	800062e <__udivmoddi4+0x27e>
 8000410:	3c02      	subs	r4, #2
 8000412:	4463      	add	r3, ip
 8000414:	1a59      	subs	r1, r3, r1
 8000416:	fa1f f38e 	uxth.w	r3, lr
 800041a:	fbb1 f0f7 	udiv	r0, r1, r7
 800041e:	fb07 1110 	mls	r1, r7, r0, r1
 8000422:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
 8000426:	fb00 f606 	mul.w	r6, r0, r6
 800042a:	429e      	cmp	r6, r3
 800042c:	d90a      	bls.n	8000444 <__udivmoddi4+0x94>
 800042e:	eb1c 0303 	adds.w	r3, ip, r3
 8000432:	f100 31ff 	add.w	r1, r0, #4294967295	@ 0xffffffff
 8000436:	f080 80fc 	bcs.w	8000632 <__udivmoddi4+0x282>
 800043a:	429e      	cmp	r6, r3
 800043c:	f240 80f9 	bls.w	8000632 <__udivmoddi4+0x282>
 8000440:	4463      	add	r3, ip
 8000442:	3802      	subs	r0, #2
 8000444:	1b9b      	subs	r3, r3, r6
 8000446:	ea40 4004 	orr.w	r0, r0, r4, lsl #16
 800044a:	2100      	movs	r1, #0
 800044c:	b11d      	cbz	r5, 8000456 <__udivmoddi4+0xa6>
 800044e:	40d3      	lsrs	r3, r2
 8000450:	2200      	movs	r2, #0
 8000452:	e9c5 3200 	strd	r3, r2, [r5]
 8000456:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 800045a:	428b      	cmp	r3, r1
 800045c:	d905      	bls.n	800046a <__udivmoddi4+0xba>
 800045e:	b10d      	cbz	r5, 8000464 <__udivmoddi4+0xb4>
 8000460:	e9c5 0100 	strd	r0, r1, [r5]
 8000464:	2100      	movs	r1, #0
 8000466:	4608      	mov	r0, r1
 8000468:	e7f5      	b.n	8000456 <__udivmoddi4+0xa6>
 800046a:	fab3 f183 	clz	r1, r3
 800046e:	2900      	cmp	r1, #0
 8000470:	d146      	bne.n	8000500 <__udivmoddi4+0x150>
 8000472:	42a3      	cmp	r3, r4
 8000474:	d302      	bcc.n	800047c <__udivmoddi4+0xcc>
 8000476:	4290      	cmp	r0, r2
 8000478:	f0c0 80f0 	bcc.w	800065c <__udivmoddi4+0x2ac>
 800047c:	1a86      	subs	r6, r0, r2
 800047e:	eb64 0303 	sbc.w	r3, r4, r3
 8000482:	2001      	movs	r0, #1
 8000484:	2d00      	cmp	r5, #0
 8000486:	d0e6      	beq.n	8000456 <__udivmoddi4+0xa6>
 8000488:	e9c5 6300 	strd	r6, r3, [r5]
 800048c:	e7e3      	b.n	8000456 <__udivmoddi4+0xa6>
 800048e:	2a00      	cmp	r2, #0
 8000490:	f040 8090 	bne.w	80005b4 <__udivmoddi4+0x204>
 8000494:	eba1 040c 	sub.w	r4, r1, ip
 8000498:	ea4f 481c 	mov.w	r8, ip, lsr #16
 800049c:	fa1f f78c 	uxth.w	r7, ip
 80004a0:	2101      	movs	r1, #1
 80004a2:	fbb4 f6f8 	udiv	r6, r4, r8
 80004a6:	ea4f 431e 	mov.w	r3, lr, lsr #16
 80004aa:	fb08 4416 	mls	r4, r8, r6, r4
 80004ae:	ea43 4304 	orr.w	r3, r3, r4, lsl #16
 80004b2:	fb07 f006 	mul.w	r0, r7, r6
 80004b6:	4298      	cmp	r0, r3
 80004b8:	d908      	bls.n	80004cc <__udivmoddi4+0x11c>
 80004ba:	eb1c 0303 	adds.w	r3, ip, r3
 80004be:	f106 34ff 	add.w	r4, r6, #4294967295	@ 0xffffffff
 80004c2:	d202      	bcs.n	80004ca <__udivmoddi4+0x11a>
 80004c4:	4298      	cmp	r0, r3
 80004c6:	f200 80cd 	bhi.w	8000664 <__udivmoddi4+0x2b4>
 80004ca:	4626      	mov	r6, r4
 80004cc:	1a1c      	subs	r4, r3, r0
 80004ce:	fa1f f38e 	uxth.w	r3, lr
 80004d2:	fbb4 f0f8 	udiv	r0, r4, r8
 80004d6:	fb08 4410 	mls	r4, r8, r0, r4
 80004da:	ea43 4304 	orr.w	r3, r3, r4, lsl #16
 80004de:	fb00 f707 	mul.w	r7, r0, r7
 80004e2:	429f      	cmp	r7, r3
 80004e4:	d908      	bls.n	80004f8 <__udivmoddi4+0x148>
 80004e6:	eb1c 0303 	adds.w	r3, ip, r3
 80004ea:	f100 34ff 	add.w	r4, r0, #4294967295	@ 0xffffffff
 80004ee:	d202      	bcs.n	80004f6 <__udivmoddi4+0x146>
 80004f0:	429f      	cmp	r7, r3
 80004f2:	f200 80b0 	bhi.w	8000656 <__udivmoddi4+0x2a6>
 80004f6:	4620      	mov	r0, r4
 80004f8:	1bdb      	subs	r3, r3, r7
 80004fa:	ea40 4006 	orr.w	r0, r0, r6, lsl #16
 80004fe:	e7a5      	b.n	800044c <__udivmoddi4+0x9c>
 8000500:	f1c1 0620 	rsb	r6, r1, #32
 8000504:	408b      	lsls	r3, r1
 8000506:	fa22 f706 	lsr.w	r7, r2, r6
 800050a:	431f      	orrs	r7, r3
 800050c:	fa20 fc06 	lsr.w	ip, r0, r6
 8000510:	fa04 f301 	lsl.w	r3, r4, r1
 8000514:	ea43 030c 	orr.w	r3, r3, ip
 8000518:	40f4      	lsrs	r4, r6
 800051a:	fa00 f801 	lsl.w	r8, r0, r1
 800051e:	0c38      	lsrs	r0, r7, #16
 8000520:	ea4f 4913 	mov.w	r9, r3, lsr #16
 8000524:	fbb4 fef0 	udiv	lr, r4, r0
 8000528:	fa1f fc87 	uxth.w	ip, r7
 800052c:	fb00 441e 	mls	r4, r0, lr, r4
 8000530:	ea49 4404 	orr.w	r4, r9, r4, lsl #16
 8000534:	fb0e f90c 	mul.w	r9, lr, ip
 8000538:	45a1      	cmp	r9, r4
 800053a:	fa02 f201 	lsl.w	r2, r2, r1
 800053e:	d90a      	bls.n	8000556 <__udivmoddi4+0x1a6>
 8000540:	193c      	adds	r4, r7, r4
 8000542:	f10e 3aff 	add.w	sl, lr, #4294967295	@ 0xffffffff
 8000546:	f080 8084 	bcs.w	8000652 <__udivmoddi4+0x2a2>
 800054a:	45a1      	cmp	r9, r4
 800054c:	f240 8081 	bls.w	8000652 <__udivmoddi4+0x2a2>
 8000550:	f1ae 0e02 	sub.w	lr, lr, #2
 8000554:	443c      	add	r4, r7
 8000556:	eba4 0409 	sub.w	r4, r4, r9
 800055a:	fa1f f983 	uxth.w	r9, r3
 800055e:	fbb4 f3f0 	udiv	r3, r4, r0
 8000562:	fb00 4413 	mls	r4, r0, r3, r4
 8000566:	ea49 4404 	orr.w	r4, r9, r4, lsl #16
 800056a:	fb03 fc0c 	mul.w	ip, r3, ip
 800056e:	45a4      	cmp	ip, r4
 8000570:	d907      	bls.n	8000582 <__udivmoddi4+0x1d2>
 8000572:	193c      	adds	r4, r7, r4
 8000574:	f103 30ff 	add.w	r0, r3, #4294967295	@ 0xffffffff
 8000578:	d267      	bcs.n	800064a <__udivmoddi4+0x29a>
 800057a:	45a4      	cmp	ip, r4
 800057c:	d965      	bls.n	800064a <__udivmoddi4+0x29a>
 800057e:	3b02      	subs	r3, #2
 8000580:	443c      	add	r4, r7
 8000582:	ea43 400e 	orr.w	r0, r3, lr, lsl #16
 8000586:	fba0 9302 	umull	r9, r3, r0, r2
 800058a:	eba4 040c 	sub.w	r4, r4, ip
 800058e:	429c      	cmp	r4, r3
 8000590:	46ce      	mov	lr, r9
 8000592:	469c      	mov	ip, r3
 8000594:	d351      	bcc.n	800063a <__udivmoddi4+0x28a>
 8000596:	d04e      	beq.n	8000636 <__udivmoddi4+0x286>
 8000598:	b155      	cbz	r5, 80005b0 <__udivmoddi4+0x200>
 800059a:	ebb8 030e 	subs.w	r3, r8, lr
 800059e:	eb64 040c 	sbc.w	r4, r4, ip
 80005a2:	fa04 f606 	lsl.w	r6, r4, r6
 80005a6:	40cb      	lsrs	r3, r1
 80005a8:	431e      	orrs	r6, r3
 80005aa:	40cc      	lsrs	r4, r1
 80005ac:	e9c5 6400 	strd	r6, r4, [r5]
 80005b0:	2100      	movs	r1, #0
 80005b2:	e750      	b.n	8000456 <__udivmoddi4+0xa6>
 80005b4:	f1c2 0320 	rsb	r3, r2, #32
 80005b8:	fa20 f103 	lsr.w	r1, r0, r3
 80005bc:	fa0c fc02 	lsl.w	ip, ip, r2
 80005c0:	fa24 f303 	lsr.w	r3, r4, r3
 80005c4:	4094      	lsls	r4, r2
 80005c6:	430c      	orrs	r4, r1
 80005c8:	ea4f 481c 	mov.w	r8, ip, lsr #16
 80005cc:	fa00 fe02 	lsl.w	lr, r0, r2
 80005d0:	fa1f f78c 	uxth.w	r7, ip
 80005d4:	fbb3 f0f8 	udiv	r0, r3, r8
 80005d8:	fb08 3110 	mls	r1, r8, r0, r3
 80005dc:	0c23      	lsrs	r3, r4, #16
 80005de:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
 80005e2:	fb00 f107 	mul.w	r1, r0, r7
 80005e6:	4299      	cmp	r1, r3
 80005e8:	d908      	bls.n	80005fc <__udivmoddi4+0x24c>
 80005ea:	eb1c 0303 	adds.w	r3, ip, r3
 80005ee:	f100 36ff 	add.w	r6, r0, #4294967295	@ 0xffffffff
 80005f2:	d22c      	bcs.n	800064e <__udivmoddi4+0x29e>
 80005f4:	4299      	cmp	r1, r3
 80005f6:	d92a      	bls.n	800064e <__udivmoddi4+0x29e>
 80005f8:	3802      	subs	r0, #2
 80005fa:	4463      	add	r3, ip
 80005fc:	1a5b      	subs	r3, r3, r1
 80005fe:	b2a4      	uxth	r4, r4
 8000600:	fbb3 f1f8 	udiv	r1, r3, r8
 8000604:	fb08 3311 	mls	r3, r8, r1, r3
 8000608:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
 800060c:	fb01 f307 	mul.w	r3, r1, r7
 8000610:	42a3      	cmp	r3, r4
 8000612:	d908      	bls.n	8000626 <__udivmoddi4+0x276>
 8000614:	eb1c 0404 	adds.w	r4, ip, r4
 8000618:	f101 36ff 	add.w	r6, r1, #4294967295	@ 0xffffffff
 800061c:	d213      	bcs.n	8000646 <__udivmoddi4+0x296>
 800061e:	42a3      	cmp	r3, r4
 8000620:	d911      	bls.n	8000646 <__udivmoddi4+0x296>
 8000622:	3902      	subs	r1, #2
 8000624:	4464      	add	r4, ip
 8000626:	1ae4      	subs	r4, r4, r3
 8000628:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
 800062c:	e739      	b.n	80004a2 <__udivmoddi4+0xf2>
 800062e:	4604      	mov	r4, r0
 8000630:	e6f0      	b.n	8000414 <__udivmoddi4+0x64>
 8000632:	4608      	mov	r0, r1
 8000634:	e706      	b.n	8000444 <__udivmoddi4+0x94>
 8000636:	45c8      	cmp	r8, r9
 8000638:	d2ae      	bcs.n	8000598 <__udivmoddi4+0x1e8>
 800063a:	ebb9 0e02 	subs.w	lr, r9, r2
 800063e:	eb63 0c07 	sbc.w	ip, r3, r7
 8000642:	3801      	subs	r0, #1
 8000644:	e7a8      	b.n	8000598 <__udivmoddi4+0x1e8>
 8000646:	4631      	mov	r1, r6
 8000648:	e7ed      	b.n	8000626 <__udivmoddi4+0x276>
 800064a:	4603      	mov	r3, r0
 800064c:	e799      	b.n	8000582 <__udivmoddi4+0x1d2>
 800064e:	4630      	mov	r0, r6
 8000650:	e7d4      	b.n	80005fc <__udivmoddi4+0x24c>
 8000652:	46d6      	mov	lr, sl
 8000654:	e77f      	b.n	8000556 <__udivmoddi4+0x1a6>
 8000656:	4463      	add	r3, ip
 8000658:	3802      	subs	r0, #2
 800065a:	e74d      	b.n	80004f8 <__udivmoddi4+0x148>
 800065c:	4606      	mov	r6, r0
 800065e:	4623      	mov	r3, r4
 8000660:	4608      	mov	r0, r1
 8000662:	e70f      	b.n	8000484 <__udivmoddi4+0xd4>
 8000664:	3e02      	subs	r6, #2
 8000666:	4463      	add	r3, ip
 8000668:	e730      	b.n	80004cc <__udivmoddi4+0x11c>
 800066a:	bf00      	nop

0800066c <__aeabi_idiv0>:
 800066c:	4770      	bx	lr
 800066e:	bf00      	nop

08000670 <vApplicationStackOverflowHook>:
/* Hook prototypes */
void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName);

/* USER CODE BEGIN 4 */
void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
{
 8000670:	b480      	push	{r7}
 8000672:	b083      	sub	sp, #12
 8000674:	af00      	add	r7, sp, #0
 8000676:	6078      	str	r0, [r7, #4]
 8000678:	6039      	str	r1, [r7, #0]
   /* Run time stack overflow checking is performed if
   configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
   called if a stack overflow is detected. */
}
 800067a:	bf00      	nop
 800067c:	370c      	adds	r7, #12
 800067e:	46bd      	mov	sp, r7
 8000680:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000684:	4770      	bx	lr
	...

08000688 <__NVIC_SystemReset>:
/**
  \brief   System Reset
  \details Initiates a system reset request to reset the MCU.
 */
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
 8000688:	b480      	push	{r7}
 800068a:	af00      	add	r7, sp, #0
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
 800068c:	f3bf 8f4f 	dsb	sy
}
 8000690:	bf00      	nop
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
 8000692:	4b06      	ldr	r3, [pc, #24]	@ (80006ac <__NVIC_SystemReset+0x24>)
 8000694:	68db      	ldr	r3, [r3, #12]
 8000696:	f403 62e0 	and.w	r2, r3, #1792	@ 0x700
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
 800069a:	4904      	ldr	r1, [pc, #16]	@ (80006ac <__NVIC_SystemReset+0x24>)
 800069c:	4b04      	ldr	r3, [pc, #16]	@ (80006b0 <__NVIC_SystemReset+0x28>)
 800069e:	4313      	orrs	r3, r2
 80006a0:	60cb      	str	r3, [r1, #12]
  __ASM volatile ("dsb 0xF":::"memory");
 80006a2:	f3bf 8f4f 	dsb	sy
}
 80006a6:	bf00      	nop
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
 80006a8:	bf00      	nop
 80006aa:	e7fd      	b.n	80006a8 <__NVIC_SystemReset+0x20>
 80006ac:	e000ed00 	.word	0xe000ed00
 80006b0:	05fa0004 	.word	0x05fa0004

080006b4 <__io_putchar>:
/* USER CODE END PFP */

/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
int __io_putchar(int ch)
{
 80006b4:	b580      	push	{r7, lr}
 80006b6:	b082      	sub	sp, #8
 80006b8:	af00      	add	r7, sp, #0
 80006ba:	6078      	str	r0, [r7, #4]
#if UART_TASK_LOGS
  HAL_UART_Transmit(&huart8, (uint8_t *)&ch, 1, 0xFFFF); // Use UART8 as debug interface
 80006bc:	1d39      	adds	r1, r7, #4
 80006be:	f64f 73ff 	movw	r3, #65535	@ 0xffff
 80006c2:	2201      	movs	r2, #1
 80006c4:	4803      	ldr	r0, [pc, #12]	@ (80006d4 <__io_putchar+0x20>)
 80006c6:	f010 f97b 	bl	80109c0 <HAL_UART_Transmit>
//  ITM_SendChar(ch);	// Use SWV as debug interface
#endif
  return ch;
 80006ca:	687b      	ldr	r3, [r7, #4]
}
 80006cc:	4618      	mov	r0, r3
 80006ce:	3708      	adds	r7, #8
 80006d0:	46bd      	mov	sp, r7
 80006d2:	bd80      	pop	{r7, pc}
 80006d4:	2400057c 	.word	0x2400057c

080006d8 <HAL_GPIO_EXTI_Callback>:

void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
 80006d8:	b580      	push	{r7, lr}
 80006da:	b084      	sub	sp, #16
 80006dc:	af00      	add	r7, sp, #0
 80006de:	4603      	mov	r3, r0
 80006e0:	80fb      	strh	r3, [r7, #6]
	LimiterSwitchData limiterSwitchData = { 0 };
 80006e2:	2300      	movs	r3, #0
 80006e4:	60fb      	str	r3, [r7, #12]
	limiterSwitchData.gpioPin = GPIO_Pin;
 80006e6:	88fb      	ldrh	r3, [r7, #6]
 80006e8:	81bb      	strh	r3, [r7, #12]
	limiterSwitchData.pinState = HAL_GPIO_ReadPin(GPIOD, GPIO_Pin);
 80006ea:	88fb      	ldrh	r3, [r7, #6]
 80006ec:	4619      	mov	r1, r3
 80006ee:	4808      	ldr	r0, [pc, #32]	@ (8000710 <HAL_GPIO_EXTI_Callback+0x38>)
 80006f0:	f00a fa2c 	bl	800ab4c <HAL_GPIO_ReadPin>
 80006f4:	4603      	mov	r3, r0
 80006f6:	73bb      	strb	r3, [r7, #14]
	osMessageQueuePut(limiterSwitchDataQueue, &limiterSwitchData, 0, 0);
 80006f8:	4b06      	ldr	r3, [pc, #24]	@ (8000714 <HAL_GPIO_EXTI_Callback+0x3c>)
 80006fa:	6818      	ldr	r0, [r3, #0]
 80006fc:	f107 010c 	add.w	r1, r7, #12
 8000700:	2300      	movs	r3, #0
 8000702:	2200      	movs	r2, #0
 8000704:	f013 fb12 	bl	8013d2c <osMessageQueuePut>
}
 8000708:	bf00      	nop
 800070a:	3710      	adds	r7, #16
 800070c:	46bd      	mov	sp, r7
 800070e:	bd80      	pop	{r7, pc}
 8000710:	58020c00 	.word	0x58020c00
 8000714:	240007d4 	.word	0x240007d4

08000718 <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 8000718:	b580      	push	{r7, lr}
 800071a:	b084      	sub	sp, #16
 800071c:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN 1 */

  /* USER CODE END 1 */

  /* MPU Configuration--------------------------------------------------------*/
  MPU_Config();
 800071e:	f001 fadd 	bl	8001cdc <MPU_Config>
  \details Turns on I-Cache
  */
__STATIC_FORCEINLINE void SCB_EnableICache (void)
{
  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
 8000722:	4b5e      	ldr	r3, [pc, #376]	@ (800089c <main+0x184>)
 8000724:	695b      	ldr	r3, [r3, #20]
 8000726:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800072a:	2b00      	cmp	r3, #0
 800072c:	d11b      	bne.n	8000766 <main+0x4e>
  __ASM volatile ("dsb 0xF":::"memory");
 800072e:	f3bf 8f4f 	dsb	sy
}
 8000732:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 8000734:	f3bf 8f6f 	isb	sy
}
 8000738:	bf00      	nop

    __DSB();
    __ISB();
    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
 800073a:	4b58      	ldr	r3, [pc, #352]	@ (800089c <main+0x184>)
 800073c:	2200      	movs	r2, #0
 800073e:	f8c3 2250 	str.w	r2, [r3, #592]	@ 0x250
  __ASM volatile ("dsb 0xF":::"memory");
 8000742:	f3bf 8f4f 	dsb	sy
}
 8000746:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 8000748:	f3bf 8f6f 	isb	sy
}
 800074c:	bf00      	nop
    __DSB();
    __ISB();
    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
 800074e:	4b53      	ldr	r3, [pc, #332]	@ (800089c <main+0x184>)
 8000750:	695b      	ldr	r3, [r3, #20]
 8000752:	4a52      	ldr	r2, [pc, #328]	@ (800089c <main+0x184>)
 8000754:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 8000758:	6153      	str	r3, [r2, #20]
  __ASM volatile ("dsb 0xF":::"memory");
 800075a:	f3bf 8f4f 	dsb	sy
}
 800075e:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 8000760:	f3bf 8f6f 	isb	sy
}
 8000764:	e000      	b.n	8000768 <main+0x50>
    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
 8000766:	bf00      	nop
  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
    uint32_t ccsidr;
    uint32_t sets;
    uint32_t ways;

    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
 8000768:	4b4c      	ldr	r3, [pc, #304]	@ (800089c <main+0x184>)
 800076a:	695b      	ldr	r3, [r3, #20]
 800076c:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 8000770:	2b00      	cmp	r3, #0
 8000772:	d138      	bne.n	80007e6 <main+0xce>

    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
 8000774:	4b49      	ldr	r3, [pc, #292]	@ (800089c <main+0x184>)
 8000776:	2200      	movs	r2, #0
 8000778:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
  __ASM volatile ("dsb 0xF":::"memory");
 800077c:	f3bf 8f4f 	dsb	sy
}
 8000780:	bf00      	nop
    __DSB();

    ccsidr = SCB->CCSIDR;
 8000782:	4b46      	ldr	r3, [pc, #280]	@ (800089c <main+0x184>)
 8000784:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8000788:	60fb      	str	r3, [r7, #12]

                                            /* invalidate D-Cache */
    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
 800078a:	68fb      	ldr	r3, [r7, #12]
 800078c:	0b5b      	lsrs	r3, r3, #13
 800078e:	f3c3 030e 	ubfx	r3, r3, #0, #15
 8000792:	60bb      	str	r3, [r7, #8]
    do {
      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
 8000794:	68fb      	ldr	r3, [r7, #12]
 8000796:	08db      	lsrs	r3, r3, #3
 8000798:	f3c3 0309 	ubfx	r3, r3, #0, #10
 800079c:	607b      	str	r3, [r7, #4]
      do {
        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
 800079e:	68bb      	ldr	r3, [r7, #8]
 80007a0:	015a      	lsls	r2, r3, #5
 80007a2:	f643 73e0 	movw	r3, #16352	@ 0x3fe0
 80007a6:	4013      	ands	r3, r2
                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
 80007a8:	687a      	ldr	r2, [r7, #4]
 80007aa:	0792      	lsls	r2, r2, #30
        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
 80007ac:	493b      	ldr	r1, [pc, #236]	@ (800089c <main+0x184>)
 80007ae:	4313      	orrs	r3, r2
 80007b0:	f8c1 3260 	str.w	r3, [r1, #608]	@ 0x260
        #if defined ( __CC_ARM )
          __schedule_barrier();
        #endif
      } while (ways-- != 0U);
 80007b4:	687b      	ldr	r3, [r7, #4]
 80007b6:	1e5a      	subs	r2, r3, #1
 80007b8:	607a      	str	r2, [r7, #4]
 80007ba:	2b00      	cmp	r3, #0
 80007bc:	d1ef      	bne.n	800079e <main+0x86>
    } while(sets-- != 0U);
 80007be:	68bb      	ldr	r3, [r7, #8]
 80007c0:	1e5a      	subs	r2, r3, #1
 80007c2:	60ba      	str	r2, [r7, #8]
 80007c4:	2b00      	cmp	r3, #0
 80007c6:	d1e5      	bne.n	8000794 <main+0x7c>
  __ASM volatile ("dsb 0xF":::"memory");
 80007c8:	f3bf 8f4f 	dsb	sy
}
 80007cc:	bf00      	nop
    __DSB();

    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
 80007ce:	4b33      	ldr	r3, [pc, #204]	@ (800089c <main+0x184>)
 80007d0:	695b      	ldr	r3, [r3, #20]
 80007d2:	4a32      	ldr	r2, [pc, #200]	@ (800089c <main+0x184>)
 80007d4:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 80007d8:	6153      	str	r3, [r2, #20]
  __ASM volatile ("dsb 0xF":::"memory");
 80007da:	f3bf 8f4f 	dsb	sy
}
 80007de:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 80007e0:	f3bf 8f6f 	isb	sy
}
 80007e4:	e000      	b.n	80007e8 <main+0xd0>
    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
 80007e6:	bf00      	nop
  SCB_EnableDCache();

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 80007e8:	f004 fdd8 	bl	800539c <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 80007ec:	f000 f876 	bl	80008dc <SystemClock_Config>

/* Configure the peripherals common clocks */
  PeriphCommonClock_Config();
 80007f0:	f000 f8f0 	bl	80009d4 <PeriphCommonClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 80007f4:	f000 ff06 	bl	8001604 <MX_GPIO_Init>
  MX_DMA_Init();
 80007f8:	f000 fed4 	bl	80015a4 <MX_DMA_Init>
  MX_RNG_Init();
 80007fc:	f000 fbdc 	bl	8000fb8 <MX_RNG_Init>
  MX_USART1_UART_Init();
 8000800:	f000 fe80 	bl	8001504 <MX_USART1_UART_Init>
  MX_ADC1_Init();
 8000804:	f000 f916 	bl	8000a34 <MX_ADC1_Init>
  MX_UART8_Init();
 8000808:	f000 fe30 	bl	800146c <MX_UART8_Init>
  MX_CRC_Init();
 800080c:	f000 fb6e 	bl	8000eec <MX_CRC_Init>
  MX_ADC2_Init();
 8000810:	f000 f9fa 	bl	8000c08 <MX_ADC2_Init>
  MX_ADC3_Init();
 8000814:	f000 fa8c 	bl	8000d30 <MX_ADC3_Init>
  MX_TIM2_Init();
 8000818:	f000 fc80 	bl	800111c <MX_TIM2_Init>
  MX_TIM1_Init();
 800081c:	f000 fbe2 	bl	8000fe4 <MX_TIM1_Init>
  MX_TIM3_Init();
 8000820:	f000 fcfa 	bl	8001218 <MX_TIM3_Init>
  MX_DAC1_Init();
 8000824:	f000 fb8c 	bl	8000f40 <MX_DAC1_Init>
  MX_COMP1_Init();
 8000828:	f000 fb32 	bl	8000e90 <MX_COMP1_Init>
  MX_TIM4_Init();
 800082c:	f000 fda0 	bl	8001370 <MX_TIM4_Init>
  /* USER CODE BEGIN 2 */

  /* USER CODE END 2 */

  /* Init scheduler */
  osKernelInitialize();
 8000830:	f012 ff0c 	bl	801364c <osKernelInitialize>
  /* add semaphores, ... */
  /* USER CODE END RTOS_SEMAPHORES */

  /* Create the timer(s) */
  /* creation of debugLedTimer */
  debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes);
 8000834:	4b1a      	ldr	r3, [pc, #104]	@ (80008a0 <main+0x188>)
 8000836:	2200      	movs	r2, #0
 8000838:	2100      	movs	r1, #0
 800083a:	481a      	ldr	r0, [pc, #104]	@ (80008a4 <main+0x18c>)
 800083c:	f013 f814 	bl	8013868 <osTimerNew>
 8000840:	4603      	mov	r3, r0
 8000842:	4a19      	ldr	r2, [pc, #100]	@ (80008a8 <main+0x190>)
 8000844:	6013      	str	r3, [r2, #0]

  /* creation of fanTimer */
  fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes);
 8000846:	4b19      	ldr	r3, [pc, #100]	@ (80008ac <main+0x194>)
 8000848:	2200      	movs	r2, #0
 800084a:	2100      	movs	r1, #0
 800084c:	4818      	ldr	r0, [pc, #96]	@ (80008b0 <main+0x198>)
 800084e:	f013 f80b 	bl	8013868 <osTimerNew>
 8000852:	4603      	mov	r3, r0
 8000854:	4a17      	ldr	r2, [pc, #92]	@ (80008b4 <main+0x19c>)
 8000856:	6013      	str	r3, [r2, #0]

  /* creation of motorXTimer */
  motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes);
 8000858:	4b17      	ldr	r3, [pc, #92]	@ (80008b8 <main+0x1a0>)
 800085a:	2200      	movs	r2, #0
 800085c:	2101      	movs	r1, #1
 800085e:	4817      	ldr	r0, [pc, #92]	@ (80008bc <main+0x1a4>)
 8000860:	f013 f802 	bl	8013868 <osTimerNew>
 8000864:	4603      	mov	r3, r0
 8000866:	4a16      	ldr	r2, [pc, #88]	@ (80008c0 <main+0x1a8>)
 8000868:	6013      	str	r3, [r2, #0]

  /* creation of motorYTimer */
  motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes);
 800086a:	4b16      	ldr	r3, [pc, #88]	@ (80008c4 <main+0x1ac>)
 800086c:	2200      	movs	r2, #0
 800086e:	2101      	movs	r1, #1
 8000870:	4815      	ldr	r0, [pc, #84]	@ (80008c8 <main+0x1b0>)
 8000872:	f012 fff9 	bl	8013868 <osTimerNew>
 8000876:	4603      	mov	r3, r0
 8000878:	4a14      	ldr	r2, [pc, #80]	@ (80008cc <main+0x1b4>)
 800087a:	6013      	str	r3, [r2, #0]
  /* add queues, ... */
  /* USER CODE END RTOS_QUEUES */

  /* Create the thread(s) */
  /* creation of defaultTask */
  defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
 800087c:	4a14      	ldr	r2, [pc, #80]	@ (80008d0 <main+0x1b8>)
 800087e:	2100      	movs	r1, #0
 8000880:	4814      	ldr	r0, [pc, #80]	@ (80008d4 <main+0x1bc>)
 8000882:	f012 ff2d 	bl	80136e0 <osThreadNew>
 8000886:	4603      	mov	r3, r0
 8000888:	4a13      	ldr	r2, [pc, #76]	@ (80008d8 <main+0x1c0>)
 800088a:	6013      	str	r3, [r2, #0]

  /* USER CODE BEGIN RTOS_THREADS */
  /* add threads, ... */
//  Uart8TasksInit();
  UartTasksInit();
 800088c:	f003 fcdc 	bl	8004248 <UartTasksInit>
#ifdef USER_MOCKS
  MockMeasurmetsTaskInit();
#else
  MeasTasksInit();
 8000890:	f001 fada 	bl	8001e48 <MeasTasksInit>
  /* USER CODE BEGIN RTOS_EVENTS */
  /* add events, ... */
  /* USER CODE END RTOS_EVENTS */

  /* Start scheduler */
  osKernelStart();
 8000894:	f012 fefe 	bl	8013694 <osKernelStart>

  /* We should never get here as control is now taken by the scheduler */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
 8000898:	bf00      	nop
 800089a:	e7fd      	b.n	8000898 <main+0x180>
 800089c:	e000ed00 	.word	0xe000ed00
 80008a0:	080189e8 	.word	0x080189e8
 80008a4:	08001c31 	.word	0x08001c31
 80008a8:	240006a8 	.word	0x240006a8
 80008ac:	080189f8 	.word	0x080189f8
 80008b0:	08001c49 	.word	0x08001c49
 80008b4:	240006d8 	.word	0x240006d8
 80008b8:	08018a08 	.word	0x08018a08
 80008bc:	08001c65 	.word	0x08001c65
 80008c0:	24000708 	.word	0x24000708
 80008c4:	08018a18 	.word	0x08018a18
 80008c8:	08001ca1 	.word	0x08001ca1
 80008cc:	24000738 	.word	0x24000738
 80008d0:	080189c4 	.word	0x080189c4
 80008d4:	08001aa1 	.word	0x08001aa1
 80008d8:	240006a4 	.word	0x240006a4

080008dc <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 80008dc:	b580      	push	{r7, lr}
 80008de:	b09c      	sub	sp, #112	@ 0x70
 80008e0:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 80008e2:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 80008e6:	224c      	movs	r2, #76	@ 0x4c
 80008e8:	2100      	movs	r1, #0
 80008ea:	4618      	mov	r0, r3
 80008ec:	f017 f963 	bl	8017bb6 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 80008f0:	1d3b      	adds	r3, r7, #4
 80008f2:	2220      	movs	r2, #32
 80008f4:	2100      	movs	r1, #0
 80008f6:	4618      	mov	r0, r3
 80008f8:	f017 f95d 	bl	8017bb6 <memset>

  /** Supply configuration update enable
  */
  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
 80008fc:	2002      	movs	r0, #2
 80008fe:	f00a fa15 	bl	800ad2c <HAL_PWREx_ConfigSupply>

  /** Configure the main internal regulator output voltage
  */
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 8000902:	2300      	movs	r3, #0
 8000904:	603b      	str	r3, [r7, #0]
 8000906:	4b31      	ldr	r3, [pc, #196]	@ (80009cc <SystemClock_Config+0xf0>)
 8000908:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800090a:	4a30      	ldr	r2, [pc, #192]	@ (80009cc <SystemClock_Config+0xf0>)
 800090c:	f023 0301 	bic.w	r3, r3, #1
 8000910:	62d3      	str	r3, [r2, #44]	@ 0x2c
 8000912:	4b2e      	ldr	r3, [pc, #184]	@ (80009cc <SystemClock_Config+0xf0>)
 8000914:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8000916:	f003 0301 	and.w	r3, r3, #1
 800091a:	603b      	str	r3, [r7, #0]
 800091c:	4b2c      	ldr	r3, [pc, #176]	@ (80009d0 <SystemClock_Config+0xf4>)
 800091e:	699b      	ldr	r3, [r3, #24]
 8000920:	4a2b      	ldr	r2, [pc, #172]	@ (80009d0 <SystemClock_Config+0xf4>)
 8000922:	f443 4340 	orr.w	r3, r3, #49152	@ 0xc000
 8000926:	6193      	str	r3, [r2, #24]
 8000928:	4b29      	ldr	r3, [pc, #164]	@ (80009d0 <SystemClock_Config+0xf4>)
 800092a:	699b      	ldr	r3, [r3, #24]
 800092c:	f403 4340 	and.w	r3, r3, #49152	@ 0xc000
 8000930:	603b      	str	r3, [r7, #0]
 8000932:	683b      	ldr	r3, [r7, #0]

  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
 8000934:	bf00      	nop
 8000936:	4b26      	ldr	r3, [pc, #152]	@ (80009d0 <SystemClock_Config+0xf4>)
 8000938:	699b      	ldr	r3, [r3, #24]
 800093a:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 800093e:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 8000942:	d1f8      	bne.n	8000936 <SystemClock_Config+0x5a>

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
 8000944:	2321      	movs	r3, #33	@ 0x21
 8000946:	627b      	str	r3, [r7, #36]	@ 0x24
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 8000948:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
 800094c:	62bb      	str	r3, [r7, #40]	@ 0x28
  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
 800094e:	2301      	movs	r3, #1
 8000950:	63fb      	str	r3, [r7, #60]	@ 0x3c
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8000952:	2302      	movs	r3, #2
 8000954:	64bb      	str	r3, [r7, #72]	@ 0x48
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 8000956:	2302      	movs	r3, #2
 8000958:	64fb      	str	r3, [r7, #76]	@ 0x4c
  RCC_OscInitStruct.PLL.PLLM = 5;
 800095a:	2305      	movs	r3, #5
 800095c:	653b      	str	r3, [r7, #80]	@ 0x50
  RCC_OscInitStruct.PLL.PLLN = 160;
 800095e:	23a0      	movs	r3, #160	@ 0xa0
 8000960:	657b      	str	r3, [r7, #84]	@ 0x54
  RCC_OscInitStruct.PLL.PLLP = 2;
 8000962:	2302      	movs	r3, #2
 8000964:	65bb      	str	r3, [r7, #88]	@ 0x58
  RCC_OscInitStruct.PLL.PLLQ = 2;
 8000966:	2302      	movs	r3, #2
 8000968:	65fb      	str	r3, [r7, #92]	@ 0x5c
  RCC_OscInitStruct.PLL.PLLR = 2;
 800096a:	2302      	movs	r3, #2
 800096c:	663b      	str	r3, [r7, #96]	@ 0x60
  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
 800096e:	2308      	movs	r3, #8
 8000970:	667b      	str	r3, [r7, #100]	@ 0x64
  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
 8000972:	2300      	movs	r3, #0
 8000974:	66bb      	str	r3, [r7, #104]	@ 0x68
  RCC_OscInitStruct.PLL.PLLFRACN = 0;
 8000976:	2300      	movs	r3, #0
 8000978:	66fb      	str	r3, [r7, #108]	@ 0x6c
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 800097a:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800097e:	4618      	mov	r0, r3
 8000980:	f00a fa94 	bl	800aeac <HAL_RCC_OscConfig>
 8000984:	4603      	mov	r3, r0
 8000986:	2b00      	cmp	r3, #0
 8000988:	d001      	beq.n	800098e <SystemClock_Config+0xb2>
  {
    Error_Handler();
 800098a:	f001 fa57 	bl	8001e3c <Error_Handler>
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 800098e:	233f      	movs	r3, #63	@ 0x3f
 8000990:	607b      	str	r3, [r7, #4]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 8000992:	2303      	movs	r3, #3
 8000994:	60bb      	str	r3, [r7, #8]
  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
 8000996:	2300      	movs	r3, #0
 8000998:	60fb      	str	r3, [r7, #12]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
 800099a:	2308      	movs	r3, #8
 800099c:	613b      	str	r3, [r7, #16]
  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
 800099e:	2340      	movs	r3, #64	@ 0x40
 80009a0:	617b      	str	r3, [r7, #20]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
 80009a2:	2340      	movs	r3, #64	@ 0x40
 80009a4:	61bb      	str	r3, [r7, #24]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
 80009a6:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 80009aa:	61fb      	str	r3, [r7, #28]
  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
 80009ac:	2340      	movs	r3, #64	@ 0x40
 80009ae:	623b      	str	r3, [r7, #32]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 80009b0:	1d3b      	adds	r3, r7, #4
 80009b2:	2102      	movs	r1, #2
 80009b4:	4618      	mov	r0, r3
 80009b6:	f00a fed3 	bl	800b760 <HAL_RCC_ClockConfig>
 80009ba:	4603      	mov	r3, r0
 80009bc:	2b00      	cmp	r3, #0
 80009be:	d001      	beq.n	80009c4 <SystemClock_Config+0xe8>
  {
    Error_Handler();
 80009c0:	f001 fa3c 	bl	8001e3c <Error_Handler>
  }
}
 80009c4:	bf00      	nop
 80009c6:	3770      	adds	r7, #112	@ 0x70
 80009c8:	46bd      	mov	sp, r7
 80009ca:	bd80      	pop	{r7, pc}
 80009cc:	58000400 	.word	0x58000400
 80009d0:	58024800 	.word	0x58024800

080009d4 <PeriphCommonClock_Config>:
/**
  * @brief Peripherals Common Clock Configuration
  * @retval None
  */
void PeriphCommonClock_Config(void)
{
 80009d4:	b580      	push	{r7, lr}
 80009d6:	b0b0      	sub	sp, #192	@ 0xc0
 80009d8:	af00      	add	r7, sp, #0
  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 80009da:	463b      	mov	r3, r7
 80009dc:	22c0      	movs	r2, #192	@ 0xc0
 80009de:	2100      	movs	r1, #0
 80009e0:	4618      	mov	r0, r3
 80009e2:	f017 f8e8 	bl	8017bb6 <memset>

  /** Initializes the peripherals clock
  */
  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
 80009e6:	f44f 2200 	mov.w	r2, #524288	@ 0x80000
 80009ea:	f04f 0300 	mov.w	r3, #0
 80009ee:	e9c7 2300 	strd	r2, r3, [r7]
  PeriphClkInitStruct.PLL2.PLL2M = 5;
 80009f2:	2305      	movs	r3, #5
 80009f4:	60bb      	str	r3, [r7, #8]
  PeriphClkInitStruct.PLL2.PLL2N = 52;
 80009f6:	2334      	movs	r3, #52	@ 0x34
 80009f8:	60fb      	str	r3, [r7, #12]
  PeriphClkInitStruct.PLL2.PLL2P = 26;
 80009fa:	231a      	movs	r3, #26
 80009fc:	613b      	str	r3, [r7, #16]
  PeriphClkInitStruct.PLL2.PLL2Q = 2;
 80009fe:	2302      	movs	r3, #2
 8000a00:	617b      	str	r3, [r7, #20]
  PeriphClkInitStruct.PLL2.PLL2R = 2;
 8000a02:	2302      	movs	r3, #2
 8000a04:	61bb      	str	r3, [r7, #24]
  PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2;
 8000a06:	2380      	movs	r3, #128	@ 0x80
 8000a08:	61fb      	str	r3, [r7, #28]
  PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
 8000a0a:	2300      	movs	r3, #0
 8000a0c:	623b      	str	r3, [r7, #32]
  PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
 8000a0e:	2300      	movs	r3, #0
 8000a10:	627b      	str	r3, [r7, #36]	@ 0x24
  PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
 8000a12:	2300      	movs	r3, #0
 8000a14:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 8000a18:	463b      	mov	r3, r7
 8000a1a:	4618      	mov	r0, r3
 8000a1c:	f00b fa6e 	bl	800befc <HAL_RCCEx_PeriphCLKConfig>
 8000a20:	4603      	mov	r3, r0
 8000a22:	2b00      	cmp	r3, #0
 8000a24:	d001      	beq.n	8000a2a <PeriphCommonClock_Config+0x56>
  {
    Error_Handler();
 8000a26:	f001 fa09 	bl	8001e3c <Error_Handler>
  }
}
 8000a2a:	bf00      	nop
 8000a2c:	37c0      	adds	r7, #192	@ 0xc0
 8000a2e:	46bd      	mov	sp, r7
 8000a30:	bd80      	pop	{r7, pc}
	...

08000a34 <MX_ADC1_Init>:
  * @brief ADC1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_ADC1_Init(void)
{
 8000a34:	b580      	push	{r7, lr}
 8000a36:	b08a      	sub	sp, #40	@ 0x28
 8000a38:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN ADC1_Init 0 */

  /* USER CODE END ADC1_Init 0 */

  ADC_MultiModeTypeDef multimode = {0};
 8000a3a:	f107 031c 	add.w	r3, r7, #28
 8000a3e:	2200      	movs	r2, #0
 8000a40:	601a      	str	r2, [r3, #0]
 8000a42:	605a      	str	r2, [r3, #4]
 8000a44:	609a      	str	r2, [r3, #8]
  ADC_ChannelConfTypeDef sConfig = {0};
 8000a46:	463b      	mov	r3, r7
 8000a48:	2200      	movs	r2, #0
 8000a4a:	601a      	str	r2, [r3, #0]
 8000a4c:	605a      	str	r2, [r3, #4]
 8000a4e:	609a      	str	r2, [r3, #8]
 8000a50:	60da      	str	r2, [r3, #12]
 8000a52:	611a      	str	r2, [r3, #16]
 8000a54:	615a      	str	r2, [r3, #20]
 8000a56:	619a      	str	r2, [r3, #24]

  /* USER CODE END ADC1_Init 1 */

  /** Common config
  */
  hadc1.Instance = ADC1;
 8000a58:	4b62      	ldr	r3, [pc, #392]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000a5a:	4a63      	ldr	r2, [pc, #396]	@ (8000be8 <MX_ADC1_Init+0x1b4>)
 8000a5c:	601a      	str	r2, [r3, #0]
  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
 8000a5e:	4b61      	ldr	r3, [pc, #388]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000a60:	2200      	movs	r2, #0
 8000a62:	605a      	str	r2, [r3, #4]
  hadc1.Init.Resolution = ADC_RESOLUTION_16B;
 8000a64:	4b5f      	ldr	r3, [pc, #380]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000a66:	2200      	movs	r2, #0
 8000a68:	609a      	str	r2, [r3, #8]
  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
 8000a6a:	4b5e      	ldr	r3, [pc, #376]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000a6c:	2201      	movs	r2, #1
 8000a6e:	60da      	str	r2, [r3, #12]
  hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
 8000a70:	4b5c      	ldr	r3, [pc, #368]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000a72:	2208      	movs	r2, #8
 8000a74:	611a      	str	r2, [r3, #16]
  hadc1.Init.LowPowerAutoWait = DISABLE;
 8000a76:	4b5b      	ldr	r3, [pc, #364]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000a78:	2200      	movs	r2, #0
 8000a7a:	751a      	strb	r2, [r3, #20]
  hadc1.Init.ContinuousConvMode = ENABLE;
 8000a7c:	4b59      	ldr	r3, [pc, #356]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000a7e:	2201      	movs	r2, #1
 8000a80:	755a      	strb	r2, [r3, #21]
  hadc1.Init.NbrOfConversion = 7;
 8000a82:	4b58      	ldr	r3, [pc, #352]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000a84:	2207      	movs	r2, #7
 8000a86:	619a      	str	r2, [r3, #24]
  hadc1.Init.DiscontinuousConvMode = DISABLE;
 8000a88:	4b56      	ldr	r3, [pc, #344]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000a8a:	2200      	movs	r2, #0
 8000a8c:	771a      	strb	r2, [r3, #28]
  hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO;
 8000a8e:	4b55      	ldr	r3, [pc, #340]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000a90:	f44f 62ac 	mov.w	r2, #1376	@ 0x560
 8000a94:	625a      	str	r2, [r3, #36]	@ 0x24
  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
 8000a96:	4b53      	ldr	r3, [pc, #332]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000a98:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 8000a9c:	629a      	str	r2, [r3, #40]	@ 0x28
  hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT;
 8000a9e:	4b51      	ldr	r3, [pc, #324]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000aa0:	2201      	movs	r2, #1
 8000aa2:	62da      	str	r2, [r3, #44]	@ 0x2c
  hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
 8000aa4:	4b4f      	ldr	r3, [pc, #316]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000aa6:	2200      	movs	r2, #0
 8000aa8:	631a      	str	r2, [r3, #48]	@ 0x30
  hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
 8000aaa:	4b4e      	ldr	r3, [pc, #312]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000aac:	2200      	movs	r2, #0
 8000aae:	635a      	str	r2, [r3, #52]	@ 0x34
  hadc1.Init.OversamplingMode = DISABLE;
 8000ab0:	4b4c      	ldr	r3, [pc, #304]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000ab2:	2200      	movs	r2, #0
 8000ab4:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 8000ab8:	484a      	ldr	r0, [pc, #296]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000aba:	f004 ff1f 	bl	80058fc <HAL_ADC_Init>
 8000abe:	4603      	mov	r3, r0
 8000ac0:	2b00      	cmp	r3, #0
 8000ac2:	d001      	beq.n	8000ac8 <MX_ADC1_Init+0x94>
  {
    Error_Handler();
 8000ac4:	f001 f9ba 	bl	8001e3c <Error_Handler>
  }

  /** Configure the ADC multi-mode
  */
  multimode.Mode = ADC_MODE_INDEPENDENT;
 8000ac8:	2300      	movs	r3, #0
 8000aca:	61fb      	str	r3, [r7, #28]
  if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
 8000acc:	f107 031c 	add.w	r3, r7, #28
 8000ad0:	4619      	mov	r1, r3
 8000ad2:	4844      	ldr	r0, [pc, #272]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000ad4:	f006 f830 	bl	8006b38 <HAL_ADCEx_MultiModeConfigChannel>
 8000ad8:	4603      	mov	r3, r0
 8000ada:	2b00      	cmp	r3, #0
 8000adc:	d001      	beq.n	8000ae2 <MX_ADC1_Init+0xae>
  {
    Error_Handler();
 8000ade:	f001 f9ad 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_8;
 8000ae2:	4b42      	ldr	r3, [pc, #264]	@ (8000bec <MX_ADC1_Init+0x1b8>)
 8000ae4:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8000ae6:	2306      	movs	r3, #6
 8000ae8:	607b      	str	r3, [r7, #4]
  sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5;
 8000aea:	2306      	movs	r3, #6
 8000aec:	60bb      	str	r3, [r7, #8]
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
 8000aee:	f240 73ff 	movw	r3, #2047	@ 0x7ff
 8000af2:	60fb      	str	r3, [r7, #12]
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
 8000af4:	2304      	movs	r3, #4
 8000af6:	613b      	str	r3, [r7, #16]
  sConfig.Offset = 0;
 8000af8:	2300      	movs	r3, #0
 8000afa:	617b      	str	r3, [r7, #20]
  sConfig.OffsetSignedSaturation = DISABLE;
 8000afc:	2300      	movs	r3, #0
 8000afe:	767b      	strb	r3, [r7, #25]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8000b00:	463b      	mov	r3, r7
 8000b02:	4619      	mov	r1, r3
 8000b04:	4837      	ldr	r0, [pc, #220]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000b06:	f005 f973 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000b0a:	4603      	mov	r3, r0
 8000b0c:	2b00      	cmp	r3, #0
 8000b0e:	d001      	beq.n	8000b14 <MX_ADC1_Init+0xe0>
  {
    Error_Handler();
 8000b10:	f001 f994 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_7;
 8000b14:	4b36      	ldr	r3, [pc, #216]	@ (8000bf0 <MX_ADC1_Init+0x1bc>)
 8000b16:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_2;
 8000b18:	230c      	movs	r3, #12
 8000b1a:	607b      	str	r3, [r7, #4]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8000b1c:	463b      	mov	r3, r7
 8000b1e:	4619      	mov	r1, r3
 8000b20:	4830      	ldr	r0, [pc, #192]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000b22:	f005 f965 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000b26:	4603      	mov	r3, r0
 8000b28:	2b00      	cmp	r3, #0
 8000b2a:	d001      	beq.n	8000b30 <MX_ADC1_Init+0xfc>
  {
    Error_Handler();
 8000b2c:	f001 f986 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_9;
 8000b30:	4b30      	ldr	r3, [pc, #192]	@ (8000bf4 <MX_ADC1_Init+0x1c0>)
 8000b32:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_3;
 8000b34:	2312      	movs	r3, #18
 8000b36:	607b      	str	r3, [r7, #4]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8000b38:	463b      	mov	r3, r7
 8000b3a:	4619      	mov	r1, r3
 8000b3c:	4829      	ldr	r0, [pc, #164]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000b3e:	f005 f957 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000b42:	4603      	mov	r3, r0
 8000b44:	2b00      	cmp	r3, #0
 8000b46:	d001      	beq.n	8000b4c <MX_ADC1_Init+0x118>
  {
    Error_Handler();
 8000b48:	f001 f978 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_16;
 8000b4c:	4b2a      	ldr	r3, [pc, #168]	@ (8000bf8 <MX_ADC1_Init+0x1c4>)
 8000b4e:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_4;
 8000b50:	2318      	movs	r3, #24
 8000b52:	607b      	str	r3, [r7, #4]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8000b54:	463b      	mov	r3, r7
 8000b56:	4619      	mov	r1, r3
 8000b58:	4822      	ldr	r0, [pc, #136]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000b5a:	f005 f949 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000b5e:	4603      	mov	r3, r0
 8000b60:	2b00      	cmp	r3, #0
 8000b62:	d001      	beq.n	8000b68 <MX_ADC1_Init+0x134>
  {
    Error_Handler();
 8000b64:	f001 f96a 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_17;
 8000b68:	4b24      	ldr	r3, [pc, #144]	@ (8000bfc <MX_ADC1_Init+0x1c8>)
 8000b6a:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_5;
 8000b6c:	f44f 7380 	mov.w	r3, #256	@ 0x100
 8000b70:	607b      	str	r3, [r7, #4]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8000b72:	463b      	mov	r3, r7
 8000b74:	4619      	mov	r1, r3
 8000b76:	481b      	ldr	r0, [pc, #108]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000b78:	f005 f93a 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000b7c:	4603      	mov	r3, r0
 8000b7e:	2b00      	cmp	r3, #0
 8000b80:	d001      	beq.n	8000b86 <MX_ADC1_Init+0x152>
  {
    Error_Handler();
 8000b82:	f001 f95b 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_14;
 8000b86:	4b1e      	ldr	r3, [pc, #120]	@ (8000c00 <MX_ADC1_Init+0x1cc>)
 8000b88:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_6;
 8000b8a:	f44f 7383 	mov.w	r3, #262	@ 0x106
 8000b8e:	607b      	str	r3, [r7, #4]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8000b90:	463b      	mov	r3, r7
 8000b92:	4619      	mov	r1, r3
 8000b94:	4813      	ldr	r0, [pc, #76]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000b96:	f005 f92b 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000b9a:	4603      	mov	r3, r0
 8000b9c:	2b00      	cmp	r3, #0
 8000b9e:	d001      	beq.n	8000ba4 <MX_ADC1_Init+0x170>
  {
    Error_Handler();
 8000ba0:	f001 f94c 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_15;
 8000ba4:	4b17      	ldr	r3, [pc, #92]	@ (8000c04 <MX_ADC1_Init+0x1d0>)
 8000ba6:	603b      	str	r3, [r7, #0]
  sConfig.Rank = ADC_REGULAR_RANK_7;
 8000ba8:	f44f 7386 	mov.w	r3, #268	@ 0x10c
 8000bac:	607b      	str	r3, [r7, #4]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8000bae:	463b      	mov	r3, r7
 8000bb0:	4619      	mov	r1, r3
 8000bb2:	480c      	ldr	r0, [pc, #48]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000bb4:	f005 f91c 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000bb8:	4603      	mov	r3, r0
 8000bba:	2b00      	cmp	r3, #0
 8000bbc:	d001      	beq.n	8000bc2 <MX_ADC1_Init+0x18e>
  {
    Error_Handler();
 8000bbe:	f001 f93d 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE BEGIN ADC1_Init 2 */
  if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK)
 8000bc2:	f240 72ff 	movw	r2, #2047	@ 0x7ff
 8000bc6:	f04f 1101 	mov.w	r1, #65537	@ 0x10001
 8000bca:	4806      	ldr	r0, [pc, #24]	@ (8000be4 <MX_ADC1_Init+0x1b0>)
 8000bcc:	f005 ff50 	bl	8006a70 <HAL_ADCEx_Calibration_Start>
 8000bd0:	4603      	mov	r3, r0
 8000bd2:	2b00      	cmp	r3, #0
 8000bd4:	d001      	beq.n	8000bda <MX_ADC1_Init+0x1a6>
  {
	  Error_Handler();
 8000bd6:	f001 f931 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE END ADC1_Init 2 */

}
 8000bda:	bf00      	nop
 8000bdc:	3728      	adds	r7, #40	@ 0x28
 8000bde:	46bd      	mov	sp, r7
 8000be0:	bd80      	pop	{r7, pc}
 8000be2:	bf00      	nop
 8000be4:	24000140 	.word	0x24000140
 8000be8:	40022000 	.word	0x40022000
 8000bec:	21800100 	.word	0x21800100
 8000bf0:	1d500080 	.word	0x1d500080
 8000bf4:	25b00200 	.word	0x25b00200
 8000bf8:	43210000 	.word	0x43210000
 8000bfc:	47520000 	.word	0x47520000
 8000c00:	3ac04000 	.word	0x3ac04000
 8000c04:	3ef08000 	.word	0x3ef08000

08000c08 <MX_ADC2_Init>:
  * @brief ADC2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_ADC2_Init(void)
{
 8000c08:	b580      	push	{r7, lr}
 8000c0a:	b088      	sub	sp, #32
 8000c0c:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN ADC2_Init 0 */

  /* USER CODE END ADC2_Init 0 */

  ADC_ChannelConfTypeDef sConfig = {0};
 8000c0e:	1d3b      	adds	r3, r7, #4
 8000c10:	2200      	movs	r2, #0
 8000c12:	601a      	str	r2, [r3, #0]
 8000c14:	605a      	str	r2, [r3, #4]
 8000c16:	609a      	str	r2, [r3, #8]
 8000c18:	60da      	str	r2, [r3, #12]
 8000c1a:	611a      	str	r2, [r3, #16]
 8000c1c:	615a      	str	r2, [r3, #20]
 8000c1e:	619a      	str	r2, [r3, #24]

  /* USER CODE END ADC2_Init 1 */

  /** Common config
  */
  hadc2.Instance = ADC2;
 8000c20:	4b3e      	ldr	r3, [pc, #248]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c22:	4a3f      	ldr	r2, [pc, #252]	@ (8000d20 <MX_ADC2_Init+0x118>)
 8000c24:	601a      	str	r2, [r3, #0]
  hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
 8000c26:	4b3d      	ldr	r3, [pc, #244]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c28:	2200      	movs	r2, #0
 8000c2a:	605a      	str	r2, [r3, #4]
  hadc2.Init.Resolution = ADC_RESOLUTION_16B;
 8000c2c:	4b3b      	ldr	r3, [pc, #236]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c2e:	2200      	movs	r2, #0
 8000c30:	609a      	str	r2, [r3, #8]
  hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
 8000c32:	4b3a      	ldr	r3, [pc, #232]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c34:	2201      	movs	r2, #1
 8000c36:	60da      	str	r2, [r3, #12]
  hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
 8000c38:	4b38      	ldr	r3, [pc, #224]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c3a:	2208      	movs	r2, #8
 8000c3c:	611a      	str	r2, [r3, #16]
  hadc2.Init.LowPowerAutoWait = DISABLE;
 8000c3e:	4b37      	ldr	r3, [pc, #220]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c40:	2200      	movs	r2, #0
 8000c42:	751a      	strb	r2, [r3, #20]
  hadc2.Init.ContinuousConvMode = ENABLE;
 8000c44:	4b35      	ldr	r3, [pc, #212]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c46:	2201      	movs	r2, #1
 8000c48:	755a      	strb	r2, [r3, #21]
  hadc2.Init.NbrOfConversion = 3;
 8000c4a:	4b34      	ldr	r3, [pc, #208]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c4c:	2203      	movs	r2, #3
 8000c4e:	619a      	str	r2, [r3, #24]
  hadc2.Init.DiscontinuousConvMode = DISABLE;
 8000c50:	4b32      	ldr	r3, [pc, #200]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c52:	2200      	movs	r2, #0
 8000c54:	771a      	strb	r2, [r3, #28]
  hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO;
 8000c56:	4b31      	ldr	r3, [pc, #196]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c58:	f44f 62ac 	mov.w	r2, #1376	@ 0x560
 8000c5c:	625a      	str	r2, [r3, #36]	@ 0x24
  hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
 8000c5e:	4b2f      	ldr	r3, [pc, #188]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c60:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 8000c64:	629a      	str	r2, [r3, #40]	@ 0x28
  hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT;
 8000c66:	4b2d      	ldr	r3, [pc, #180]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c68:	2201      	movs	r2, #1
 8000c6a:	62da      	str	r2, [r3, #44]	@ 0x2c
  hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
 8000c6c:	4b2b      	ldr	r3, [pc, #172]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c6e:	2200      	movs	r2, #0
 8000c70:	631a      	str	r2, [r3, #48]	@ 0x30
  hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
 8000c72:	4b2a      	ldr	r3, [pc, #168]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c74:	2200      	movs	r2, #0
 8000c76:	635a      	str	r2, [r3, #52]	@ 0x34
  hadc2.Init.OversamplingMode = DISABLE;
 8000c78:	4b28      	ldr	r3, [pc, #160]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c7a:	2200      	movs	r2, #0
 8000c7c:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38
  if (HAL_ADC_Init(&hadc2) != HAL_OK)
 8000c80:	4826      	ldr	r0, [pc, #152]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000c82:	f004 fe3b 	bl	80058fc <HAL_ADC_Init>
 8000c86:	4603      	mov	r3, r0
 8000c88:	2b00      	cmp	r3, #0
 8000c8a:	d001      	beq.n	8000c90 <MX_ADC2_Init+0x88>
  {
    Error_Handler();
 8000c8c:	f001 f8d6 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_3;
 8000c90:	4b24      	ldr	r3, [pc, #144]	@ (8000d24 <MX_ADC2_Init+0x11c>)
 8000c92:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8000c94:	2306      	movs	r3, #6
 8000c96:	60bb      	str	r3, [r7, #8]
  sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5;
 8000c98:	2306      	movs	r3, #6
 8000c9a:	60fb      	str	r3, [r7, #12]
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
 8000c9c:	f240 73ff 	movw	r3, #2047	@ 0x7ff
 8000ca0:	613b      	str	r3, [r7, #16]
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
 8000ca2:	2304      	movs	r3, #4
 8000ca4:	617b      	str	r3, [r7, #20]
  sConfig.Offset = 0;
 8000ca6:	2300      	movs	r3, #0
 8000ca8:	61bb      	str	r3, [r7, #24]
  sConfig.OffsetSignedSaturation = DISABLE;
 8000caa:	2300      	movs	r3, #0
 8000cac:	777b      	strb	r3, [r7, #29]
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
 8000cae:	1d3b      	adds	r3, r7, #4
 8000cb0:	4619      	mov	r1, r3
 8000cb2:	481a      	ldr	r0, [pc, #104]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000cb4:	f005 f89c 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000cb8:	4603      	mov	r3, r0
 8000cba:	2b00      	cmp	r3, #0
 8000cbc:	d001      	beq.n	8000cc2 <MX_ADC2_Init+0xba>
  {
    Error_Handler();
 8000cbe:	f001 f8bd 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_4;
 8000cc2:	4b19      	ldr	r3, [pc, #100]	@ (8000d28 <MX_ADC2_Init+0x120>)
 8000cc4:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_2;
 8000cc6:	230c      	movs	r3, #12
 8000cc8:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
 8000cca:	1d3b      	adds	r3, r7, #4
 8000ccc:	4619      	mov	r1, r3
 8000cce:	4813      	ldr	r0, [pc, #76]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000cd0:	f005 f88e 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000cd4:	4603      	mov	r3, r0
 8000cd6:	2b00      	cmp	r3, #0
 8000cd8:	d001      	beq.n	8000cde <MX_ADC2_Init+0xd6>
  {
    Error_Handler();
 8000cda:	f001 f8af 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_5;
 8000cde:	4b13      	ldr	r3, [pc, #76]	@ (8000d2c <MX_ADC2_Init+0x124>)
 8000ce0:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_3;
 8000ce2:	2312      	movs	r3, #18
 8000ce4:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
 8000ce6:	1d3b      	adds	r3, r7, #4
 8000ce8:	4619      	mov	r1, r3
 8000cea:	480c      	ldr	r0, [pc, #48]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000cec:	f005 f880 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000cf0:	4603      	mov	r3, r0
 8000cf2:	2b00      	cmp	r3, #0
 8000cf4:	d001      	beq.n	8000cfa <MX_ADC2_Init+0xf2>
  {
    Error_Handler();
 8000cf6:	f001 f8a1 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE BEGIN ADC2_Init 2 */
  if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK)
 8000cfa:	f240 72ff 	movw	r2, #2047	@ 0x7ff
 8000cfe:	f04f 1101 	mov.w	r1, #65537	@ 0x10001
 8000d02:	4806      	ldr	r0, [pc, #24]	@ (8000d1c <MX_ADC2_Init+0x114>)
 8000d04:	f005 feb4 	bl	8006a70 <HAL_ADCEx_Calibration_Start>
 8000d08:	4603      	mov	r3, r0
 8000d0a:	2b00      	cmp	r3, #0
 8000d0c:	d001      	beq.n	8000d12 <MX_ADC2_Init+0x10a>
  {
	  Error_Handler();
 8000d0e:	f001 f895 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE END ADC2_Init 2 */

}
 8000d12:	bf00      	nop
 8000d14:	3720      	adds	r7, #32
 8000d16:	46bd      	mov	sp, r7
 8000d18:	bd80      	pop	{r7, pc}
 8000d1a:	bf00      	nop
 8000d1c:	240001a4 	.word	0x240001a4
 8000d20:	40022100 	.word	0x40022100
 8000d24:	0c900008 	.word	0x0c900008
 8000d28:	10c00010 	.word	0x10c00010
 8000d2c:	14f00020 	.word	0x14f00020

08000d30 <MX_ADC3_Init>:
  * @brief ADC3 Initialization Function
  * @param None
  * @retval None
  */
static void MX_ADC3_Init(void)
{
 8000d30:	b580      	push	{r7, lr}
 8000d32:	b088      	sub	sp, #32
 8000d34:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN ADC3_Init 0 */

  /* USER CODE END ADC3_Init 0 */

  ADC_ChannelConfTypeDef sConfig = {0};
 8000d36:	1d3b      	adds	r3, r7, #4
 8000d38:	2200      	movs	r2, #0
 8000d3a:	601a      	str	r2, [r3, #0]
 8000d3c:	605a      	str	r2, [r3, #4]
 8000d3e:	609a      	str	r2, [r3, #8]
 8000d40:	60da      	str	r2, [r3, #12]
 8000d42:	611a      	str	r2, [r3, #16]
 8000d44:	615a      	str	r2, [r3, #20]
 8000d46:	619a      	str	r2, [r3, #24]

  /* USER CODE END ADC3_Init 1 */

  /** Common config
  */
  hadc3.Instance = ADC3;
 8000d48:	4b4b      	ldr	r3, [pc, #300]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d4a:	4a4c      	ldr	r2, [pc, #304]	@ (8000e7c <MX_ADC3_Init+0x14c>)
 8000d4c:	601a      	str	r2, [r3, #0]
  hadc3.Init.Resolution = ADC_RESOLUTION_16B;
 8000d4e:	4b4a      	ldr	r3, [pc, #296]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d50:	2200      	movs	r2, #0
 8000d52:	609a      	str	r2, [r3, #8]
  hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE;
 8000d54:	4b48      	ldr	r3, [pc, #288]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d56:	2201      	movs	r2, #1
 8000d58:	60da      	str	r2, [r3, #12]
  hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV;
 8000d5a:	4b47      	ldr	r3, [pc, #284]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d5c:	2208      	movs	r2, #8
 8000d5e:	611a      	str	r2, [r3, #16]
  hadc3.Init.LowPowerAutoWait = DISABLE;
 8000d60:	4b45      	ldr	r3, [pc, #276]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d62:	2200      	movs	r2, #0
 8000d64:	751a      	strb	r2, [r3, #20]
  hadc3.Init.ContinuousConvMode = ENABLE;
 8000d66:	4b44      	ldr	r3, [pc, #272]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d68:	2201      	movs	r2, #1
 8000d6a:	755a      	strb	r2, [r3, #21]
  hadc3.Init.NbrOfConversion = 5;
 8000d6c:	4b42      	ldr	r3, [pc, #264]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d6e:	2205      	movs	r2, #5
 8000d70:	619a      	str	r2, [r3, #24]
  hadc3.Init.DiscontinuousConvMode = DISABLE;
 8000d72:	4b41      	ldr	r3, [pc, #260]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d74:	2200      	movs	r2, #0
 8000d76:	771a      	strb	r2, [r3, #28]
  hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO;
 8000d78:	4b3f      	ldr	r3, [pc, #252]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d7a:	f44f 62ac 	mov.w	r2, #1376	@ 0x560
 8000d7e:	625a      	str	r2, [r3, #36]	@ 0x24
  hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
 8000d80:	4b3d      	ldr	r3, [pc, #244]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d82:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 8000d86:	629a      	str	r2, [r3, #40]	@ 0x28
  hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT;
 8000d88:	4b3b      	ldr	r3, [pc, #236]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d8a:	2201      	movs	r2, #1
 8000d8c:	62da      	str	r2, [r3, #44]	@ 0x2c
  hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED;
 8000d8e:	4b3a      	ldr	r3, [pc, #232]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d90:	2200      	movs	r2, #0
 8000d92:	631a      	str	r2, [r3, #48]	@ 0x30
  hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
 8000d94:	4b38      	ldr	r3, [pc, #224]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d96:	2200      	movs	r2, #0
 8000d98:	635a      	str	r2, [r3, #52]	@ 0x34
  hadc3.Init.OversamplingMode = DISABLE;
 8000d9a:	4b37      	ldr	r3, [pc, #220]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000d9c:	2200      	movs	r2, #0
 8000d9e:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38
  if (HAL_ADC_Init(&hadc3) != HAL_OK)
 8000da2:	4835      	ldr	r0, [pc, #212]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000da4:	f004 fdaa 	bl	80058fc <HAL_ADC_Init>
 8000da8:	4603      	mov	r3, r0
 8000daa:	2b00      	cmp	r3, #0
 8000dac:	d001      	beq.n	8000db2 <MX_ADC3_Init+0x82>
  {
    Error_Handler();
 8000dae:	f001 f845 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_0;
 8000db2:	2301      	movs	r3, #1
 8000db4:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8000db6:	2306      	movs	r3, #6
 8000db8:	60bb      	str	r3, [r7, #8]
  sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5;
 8000dba:	2306      	movs	r3, #6
 8000dbc:	60fb      	str	r3, [r7, #12]
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
 8000dbe:	f240 73ff 	movw	r3, #2047	@ 0x7ff
 8000dc2:	613b      	str	r3, [r7, #16]
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
 8000dc4:	2304      	movs	r3, #4
 8000dc6:	617b      	str	r3, [r7, #20]
  sConfig.Offset = 0;
 8000dc8:	2300      	movs	r3, #0
 8000dca:	61bb      	str	r3, [r7, #24]
  sConfig.OffsetSignedSaturation = DISABLE;
 8000dcc:	2300      	movs	r3, #0
 8000dce:	777b      	strb	r3, [r7, #29]
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8000dd0:	1d3b      	adds	r3, r7, #4
 8000dd2:	4619      	mov	r1, r3
 8000dd4:	4828      	ldr	r0, [pc, #160]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000dd6:	f005 f80b 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000dda:	4603      	mov	r3, r0
 8000ddc:	2b00      	cmp	r3, #0
 8000dde:	d001      	beq.n	8000de4 <MX_ADC3_Init+0xb4>
  {
    Error_Handler();
 8000de0:	f001 f82c 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_1;
 8000de4:	4b26      	ldr	r3, [pc, #152]	@ (8000e80 <MX_ADC3_Init+0x150>)
 8000de6:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_2;
 8000de8:	230c      	movs	r3, #12
 8000dea:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8000dec:	1d3b      	adds	r3, r7, #4
 8000dee:	4619      	mov	r1, r3
 8000df0:	4821      	ldr	r0, [pc, #132]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000df2:	f004 fffd 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000df6:	4603      	mov	r3, r0
 8000df8:	2b00      	cmp	r3, #0
 8000dfa:	d001      	beq.n	8000e00 <MX_ADC3_Init+0xd0>
  {
    Error_Handler();
 8000dfc:	f001 f81e 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_10;
 8000e00:	4b20      	ldr	r3, [pc, #128]	@ (8000e84 <MX_ADC3_Init+0x154>)
 8000e02:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_3;
 8000e04:	2312      	movs	r3, #18
 8000e06:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8000e08:	1d3b      	adds	r3, r7, #4
 8000e0a:	4619      	mov	r1, r3
 8000e0c:	481a      	ldr	r0, [pc, #104]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000e0e:	f004 ffef 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000e12:	4603      	mov	r3, r0
 8000e14:	2b00      	cmp	r3, #0
 8000e16:	d001      	beq.n	8000e1c <MX_ADC3_Init+0xec>
  {
    Error_Handler();
 8000e18:	f001 f810 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_11;
 8000e1c:	4b1a      	ldr	r3, [pc, #104]	@ (8000e88 <MX_ADC3_Init+0x158>)
 8000e1e:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_4;
 8000e20:	2318      	movs	r3, #24
 8000e22:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8000e24:	1d3b      	adds	r3, r7, #4
 8000e26:	4619      	mov	r1, r3
 8000e28:	4813      	ldr	r0, [pc, #76]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000e2a:	f004 ffe1 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000e2e:	4603      	mov	r3, r0
 8000e30:	2b00      	cmp	r3, #0
 8000e32:	d001      	beq.n	8000e38 <MX_ADC3_Init+0x108>
  {
    Error_Handler();
 8000e34:	f001 f802 	bl	8001e3c <Error_Handler>
  }

  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_VREFINT;
 8000e38:	4b14      	ldr	r3, [pc, #80]	@ (8000e8c <MX_ADC3_Init+0x15c>)
 8000e3a:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_5;
 8000e3c:	f44f 7380 	mov.w	r3, #256	@ 0x100
 8000e40:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8000e42:	1d3b      	adds	r3, r7, #4
 8000e44:	4619      	mov	r1, r3
 8000e46:	480c      	ldr	r0, [pc, #48]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000e48:	f004 ffd2 	bl	8005df0 <HAL_ADC_ConfigChannel>
 8000e4c:	4603      	mov	r3, r0
 8000e4e:	2b00      	cmp	r3, #0
 8000e50:	d001      	beq.n	8000e56 <MX_ADC3_Init+0x126>
  {
    Error_Handler();
 8000e52:	f000 fff3 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE BEGIN ADC3_Init 2 */
  if (HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK)
 8000e56:	f240 72ff 	movw	r2, #2047	@ 0x7ff
 8000e5a:	f04f 1101 	mov.w	r1, #65537	@ 0x10001
 8000e5e:	4806      	ldr	r0, [pc, #24]	@ (8000e78 <MX_ADC3_Init+0x148>)
 8000e60:	f005 fe06 	bl	8006a70 <HAL_ADCEx_Calibration_Start>
 8000e64:	4603      	mov	r3, r0
 8000e66:	2b00      	cmp	r3, #0
 8000e68:	d001      	beq.n	8000e6e <MX_ADC3_Init+0x13e>
  {
	  Error_Handler();
 8000e6a:	f000 ffe7 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE END ADC3_Init 2 */

}
 8000e6e:	bf00      	nop
 8000e70:	3720      	adds	r7, #32
 8000e72:	46bd      	mov	sp, r7
 8000e74:	bd80      	pop	{r7, pc}
 8000e76:	bf00      	nop
 8000e78:	24000208 	.word	0x24000208
 8000e7c:	58026000 	.word	0x58026000
 8000e80:	04300002 	.word	0x04300002
 8000e84:	2a000400 	.word	0x2a000400
 8000e88:	2e300800 	.word	0x2e300800
 8000e8c:	cfb80000 	.word	0xcfb80000

08000e90 <MX_COMP1_Init>:
  * @brief COMP1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_COMP1_Init(void)
{
 8000e90:	b580      	push	{r7, lr}
 8000e92:	af00      	add	r7, sp, #0
  /* USER CODE END COMP1_Init 0 */

  /* USER CODE BEGIN COMP1_Init 1 */

  /* USER CODE END COMP1_Init 1 */
  hcomp1.Instance = COMP1;
 8000e94:	4b12      	ldr	r3, [pc, #72]	@ (8000ee0 <MX_COMP1_Init+0x50>)
 8000e96:	4a13      	ldr	r2, [pc, #76]	@ (8000ee4 <MX_COMP1_Init+0x54>)
 8000e98:	601a      	str	r2, [r3, #0]
  hcomp1.Init.InvertingInput = COMP_INPUT_MINUS_3_4VREFINT;
 8000e9a:	4b11      	ldr	r3, [pc, #68]	@ (8000ee0 <MX_COMP1_Init+0x50>)
 8000e9c:	4a12      	ldr	r2, [pc, #72]	@ (8000ee8 <MX_COMP1_Init+0x58>)
 8000e9e:	611a      	str	r2, [r3, #16]
  hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO2;
 8000ea0:	4b0f      	ldr	r3, [pc, #60]	@ (8000ee0 <MX_COMP1_Init+0x50>)
 8000ea2:	f44f 1280 	mov.w	r2, #1048576	@ 0x100000
 8000ea6:	60da      	str	r2, [r3, #12]
  hcomp1.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED;
 8000ea8:	4b0d      	ldr	r3, [pc, #52]	@ (8000ee0 <MX_COMP1_Init+0x50>)
 8000eaa:	2200      	movs	r2, #0
 8000eac:	619a      	str	r2, [r3, #24]
  hcomp1.Init.Hysteresis = COMP_HYSTERESIS_NONE;
 8000eae:	4b0c      	ldr	r3, [pc, #48]	@ (8000ee0 <MX_COMP1_Init+0x50>)
 8000eb0:	2200      	movs	r2, #0
 8000eb2:	615a      	str	r2, [r3, #20]
  hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE;
 8000eb4:	4b0a      	ldr	r3, [pc, #40]	@ (8000ee0 <MX_COMP1_Init+0x50>)
 8000eb6:	2200      	movs	r2, #0
 8000eb8:	61da      	str	r2, [r3, #28]
  hcomp1.Init.Mode = COMP_POWERMODE_HIGHSPEED;
 8000eba:	4b09      	ldr	r3, [pc, #36]	@ (8000ee0 <MX_COMP1_Init+0x50>)
 8000ebc:	2200      	movs	r2, #0
 8000ebe:	609a      	str	r2, [r3, #8]
  hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE;
 8000ec0:	4b07      	ldr	r3, [pc, #28]	@ (8000ee0 <MX_COMP1_Init+0x50>)
 8000ec2:	2200      	movs	r2, #0
 8000ec4:	605a      	str	r2, [r3, #4]
  hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_NONE;
 8000ec6:	4b06      	ldr	r3, [pc, #24]	@ (8000ee0 <MX_COMP1_Init+0x50>)
 8000ec8:	2200      	movs	r2, #0
 8000eca:	621a      	str	r2, [r3, #32]
  if (HAL_COMP_Init(&hcomp1) != HAL_OK)
 8000ecc:	4804      	ldr	r0, [pc, #16]	@ (8000ee0 <MX_COMP1_Init+0x50>)
 8000ece:	f005 ff11 	bl	8006cf4 <HAL_COMP_Init>
 8000ed2:	4603      	mov	r3, r0
 8000ed4:	2b00      	cmp	r3, #0
 8000ed6:	d001      	beq.n	8000edc <MX_COMP1_Init+0x4c>
  {
    Error_Handler();
 8000ed8:	f000 ffb0 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE BEGIN COMP1_Init 2 */

  /* USER CODE END COMP1_Init 2 */

}
 8000edc:	bf00      	nop
 8000ede:	bd80      	pop	{r7, pc}
 8000ee0:	240003d4 	.word	0x240003d4
 8000ee4:	5800380c 	.word	0x5800380c
 8000ee8:	00020006 	.word	0x00020006

08000eec <MX_CRC_Init>:
  * @brief CRC Initialization Function
  * @param None
  * @retval None
  */
static void MX_CRC_Init(void)
{
 8000eec:	b580      	push	{r7, lr}
 8000eee:	af00      	add	r7, sp, #0
  /* USER CODE END CRC_Init 0 */

  /* USER CODE BEGIN CRC_Init 1 */

  /* USER CODE END CRC_Init 1 */
  hcrc.Instance = CRC;
 8000ef0:	4b11      	ldr	r3, [pc, #68]	@ (8000f38 <MX_CRC_Init+0x4c>)
 8000ef2:	4a12      	ldr	r2, [pc, #72]	@ (8000f3c <MX_CRC_Init+0x50>)
 8000ef4:	601a      	str	r2, [r3, #0]
  hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE;
 8000ef6:	4b10      	ldr	r3, [pc, #64]	@ (8000f38 <MX_CRC_Init+0x4c>)
 8000ef8:	2201      	movs	r2, #1
 8000efa:	711a      	strb	r2, [r3, #4]
  hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE;
 8000efc:	4b0e      	ldr	r3, [pc, #56]	@ (8000f38 <MX_CRC_Init+0x4c>)
 8000efe:	2200      	movs	r2, #0
 8000f00:	715a      	strb	r2, [r3, #5]
  hcrc.Init.GeneratingPolynomial = 4129;
 8000f02:	4b0d      	ldr	r3, [pc, #52]	@ (8000f38 <MX_CRC_Init+0x4c>)
 8000f04:	f241 0221 	movw	r2, #4129	@ 0x1021
 8000f08:	609a      	str	r2, [r3, #8]
  hcrc.Init.CRCLength = CRC_POLYLENGTH_16B;
 8000f0a:	4b0b      	ldr	r3, [pc, #44]	@ (8000f38 <MX_CRC_Init+0x4c>)
 8000f0c:	2208      	movs	r2, #8
 8000f0e:	60da      	str	r2, [r3, #12]
  hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE;
 8000f10:	4b09      	ldr	r3, [pc, #36]	@ (8000f38 <MX_CRC_Init+0x4c>)
 8000f12:	2200      	movs	r2, #0
 8000f14:	615a      	str	r2, [r3, #20]
  hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE;
 8000f16:	4b08      	ldr	r3, [pc, #32]	@ (8000f38 <MX_CRC_Init+0x4c>)
 8000f18:	2200      	movs	r2, #0
 8000f1a:	619a      	str	r2, [r3, #24]
  hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
 8000f1c:	4b06      	ldr	r3, [pc, #24]	@ (8000f38 <MX_CRC_Init+0x4c>)
 8000f1e:	2201      	movs	r2, #1
 8000f20:	621a      	str	r2, [r3, #32]
  if (HAL_CRC_Init(&hcrc) != HAL_OK)
 8000f22:	4805      	ldr	r0, [pc, #20]	@ (8000f38 <MX_CRC_Init+0x4c>)
 8000f24:	f006 f9d0 	bl	80072c8 <HAL_CRC_Init>
 8000f28:	4603      	mov	r3, r0
 8000f2a:	2b00      	cmp	r3, #0
 8000f2c:	d001      	beq.n	8000f32 <MX_CRC_Init+0x46>
  {
    Error_Handler();
 8000f2e:	f000 ff85 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE BEGIN CRC_Init 2 */

  /* USER CODE END CRC_Init 2 */

}
 8000f32:	bf00      	nop
 8000f34:	bd80      	pop	{r7, pc}
 8000f36:	bf00      	nop
 8000f38:	24000400 	.word	0x24000400
 8000f3c:	58024c00 	.word	0x58024c00

08000f40 <MX_DAC1_Init>:
  * @brief DAC1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_DAC1_Init(void)
{
 8000f40:	b580      	push	{r7, lr}
 8000f42:	b08a      	sub	sp, #40	@ 0x28
 8000f44:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN DAC1_Init 0 */

  /* USER CODE END DAC1_Init 0 */

  DAC_ChannelConfTypeDef sConfig = {0};
 8000f46:	1d3b      	adds	r3, r7, #4
 8000f48:	2224      	movs	r2, #36	@ 0x24
 8000f4a:	2100      	movs	r1, #0
 8000f4c:	4618      	mov	r0, r3
 8000f4e:	f016 fe32 	bl	8017bb6 <memset>

  /* USER CODE END DAC1_Init 1 */

  /** DAC Initialization
  */
  hdac1.Instance = DAC1;
 8000f52:	4b17      	ldr	r3, [pc, #92]	@ (8000fb0 <MX_DAC1_Init+0x70>)
 8000f54:	4a17      	ldr	r2, [pc, #92]	@ (8000fb4 <MX_DAC1_Init+0x74>)
 8000f56:	601a      	str	r2, [r3, #0]
  if (HAL_DAC_Init(&hdac1) != HAL_OK)
 8000f58:	4815      	ldr	r0, [pc, #84]	@ (8000fb0 <MX_DAC1_Init+0x70>)
 8000f5a:	f006 fbbb 	bl	80076d4 <HAL_DAC_Init>
 8000f5e:	4603      	mov	r3, r0
 8000f60:	2b00      	cmp	r3, #0
 8000f62:	d001      	beq.n	8000f68 <MX_DAC1_Init+0x28>
  {
    Error_Handler();
 8000f64:	f000 ff6a 	bl	8001e3c <Error_Handler>
  }

  /** DAC channel OUT1 config
  */
  sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
 8000f68:	2300      	movs	r3, #0
 8000f6a:	607b      	str	r3, [r7, #4]
  sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
 8000f6c:	2300      	movs	r3, #0
 8000f6e:	60bb      	str	r3, [r7, #8]
  sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
 8000f70:	2300      	movs	r3, #0
 8000f72:	60fb      	str	r3, [r7, #12]
  sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE;
 8000f74:	2301      	movs	r3, #1
 8000f76:	613b      	str	r3, [r7, #16]
  sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
 8000f78:	2300      	movs	r3, #0
 8000f7a:	617b      	str	r3, [r7, #20]
  if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK)
 8000f7c:	1d3b      	adds	r3, r7, #4
 8000f7e:	2200      	movs	r2, #0
 8000f80:	4619      	mov	r1, r3
 8000f82:	480b      	ldr	r0, [pc, #44]	@ (8000fb0 <MX_DAC1_Init+0x70>)
 8000f84:	f006 fcaa 	bl	80078dc <HAL_DAC_ConfigChannel>
 8000f88:	4603      	mov	r3, r0
 8000f8a:	2b00      	cmp	r3, #0
 8000f8c:	d001      	beq.n	8000f92 <MX_DAC1_Init+0x52>
  {
    Error_Handler();
 8000f8e:	f000 ff55 	bl	8001e3c <Error_Handler>
  }

  /** DAC channel OUT2 config
  */
  if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK)
 8000f92:	1d3b      	adds	r3, r7, #4
 8000f94:	2210      	movs	r2, #16
 8000f96:	4619      	mov	r1, r3
 8000f98:	4805      	ldr	r0, [pc, #20]	@ (8000fb0 <MX_DAC1_Init+0x70>)
 8000f9a:	f006 fc9f 	bl	80078dc <HAL_DAC_ConfigChannel>
 8000f9e:	4603      	mov	r3, r0
 8000fa0:	2b00      	cmp	r3, #0
 8000fa2:	d001      	beq.n	8000fa8 <MX_DAC1_Init+0x68>
  {
    Error_Handler();
 8000fa4:	f000 ff4a 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE BEGIN DAC1_Init 2 */

  /* USER CODE END DAC1_Init 2 */

}
 8000fa8:	bf00      	nop
 8000faa:	3728      	adds	r7, #40	@ 0x28
 8000fac:	46bd      	mov	sp, r7
 8000fae:	bd80      	pop	{r7, pc}
 8000fb0:	24000424 	.word	0x24000424
 8000fb4:	40007400 	.word	0x40007400

08000fb8 <MX_RNG_Init>:
  * @brief RNG Initialization Function
  * @param None
  * @retval None
  */
static void MX_RNG_Init(void)
{
 8000fb8:	b580      	push	{r7, lr}
 8000fba:	af00      	add	r7, sp, #0
  /* USER CODE END RNG_Init 0 */

  /* USER CODE BEGIN RNG_Init 1 */

  /* USER CODE END RNG_Init 1 */
  hrng.Instance = RNG;
 8000fbc:	4b07      	ldr	r3, [pc, #28]	@ (8000fdc <MX_RNG_Init+0x24>)
 8000fbe:	4a08      	ldr	r2, [pc, #32]	@ (8000fe0 <MX_RNG_Init+0x28>)
 8000fc0:	601a      	str	r2, [r3, #0]
  hrng.Init.ClockErrorDetection = RNG_CED_ENABLE;
 8000fc2:	4b06      	ldr	r3, [pc, #24]	@ (8000fdc <MX_RNG_Init+0x24>)
 8000fc4:	2200      	movs	r2, #0
 8000fc6:	605a      	str	r2, [r3, #4]
  if (HAL_RNG_Init(&hrng) != HAL_OK)
 8000fc8:	4804      	ldr	r0, [pc, #16]	@ (8000fdc <MX_RNG_Init+0x24>)
 8000fca:	f00d fc79 	bl	800e8c0 <HAL_RNG_Init>
 8000fce:	4603      	mov	r3, r0
 8000fd0:	2b00      	cmp	r3, #0
 8000fd2:	d001      	beq.n	8000fd8 <MX_RNG_Init+0x20>
  {
    Error_Handler();
 8000fd4:	f000 ff32 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE BEGIN RNG_Init 2 */

  /* USER CODE END RNG_Init 2 */

}
 8000fd8:	bf00      	nop
 8000fda:	bd80      	pop	{r7, pc}
 8000fdc:	24000438 	.word	0x24000438
 8000fe0:	48021800 	.word	0x48021800

08000fe4 <MX_TIM1_Init>:
  * @brief TIM1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_TIM1_Init(void)
{
 8000fe4:	b5b0      	push	{r4, r5, r7, lr}
 8000fe6:	b096      	sub	sp, #88	@ 0x58
 8000fe8:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN TIM1_Init 0 */

  /* USER CODE END TIM1_Init 0 */

  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8000fea:	f107 034c 	add.w	r3, r7, #76	@ 0x4c
 8000fee:	2200      	movs	r2, #0
 8000ff0:	601a      	str	r2, [r3, #0]
 8000ff2:	605a      	str	r2, [r3, #4]
 8000ff4:	609a      	str	r2, [r3, #8]
  TIM_OC_InitTypeDef sConfigOC = {0};
 8000ff6:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8000ffa:	2200      	movs	r2, #0
 8000ffc:	601a      	str	r2, [r3, #0]
 8000ffe:	605a      	str	r2, [r3, #4]
 8001000:	609a      	str	r2, [r3, #8]
 8001002:	60da      	str	r2, [r3, #12]
 8001004:	611a      	str	r2, [r3, #16]
 8001006:	615a      	str	r2, [r3, #20]
 8001008:	619a      	str	r2, [r3, #24]
  TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
 800100a:	1d3b      	adds	r3, r7, #4
 800100c:	222c      	movs	r2, #44	@ 0x2c
 800100e:	2100      	movs	r1, #0
 8001010:	4618      	mov	r0, r3
 8001012:	f016 fdd0 	bl	8017bb6 <memset>

  /* USER CODE BEGIN TIM1_Init 1 */

  /* USER CODE END TIM1_Init 1 */
  htim1.Instance = TIM1;
 8001016:	4b3e      	ldr	r3, [pc, #248]	@ (8001110 <MX_TIM1_Init+0x12c>)
 8001018:	4a3e      	ldr	r2, [pc, #248]	@ (8001114 <MX_TIM1_Init+0x130>)
 800101a:	601a      	str	r2, [r3, #0]
  htim1.Init.Prescaler = 199;
 800101c:	4b3c      	ldr	r3, [pc, #240]	@ (8001110 <MX_TIM1_Init+0x12c>)
 800101e:	22c7      	movs	r2, #199	@ 0xc7
 8001020:	605a      	str	r2, [r3, #4]
  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
 8001022:	4b3b      	ldr	r3, [pc, #236]	@ (8001110 <MX_TIM1_Init+0x12c>)
 8001024:	2200      	movs	r2, #0
 8001026:	609a      	str	r2, [r3, #8]
  htim1.Init.Period = 999;
 8001028:	4b39      	ldr	r3, [pc, #228]	@ (8001110 <MX_TIM1_Init+0x12c>)
 800102a:	f240 32e7 	movw	r2, #999	@ 0x3e7
 800102e:	60da      	str	r2, [r3, #12]
  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
 8001030:	4b37      	ldr	r3, [pc, #220]	@ (8001110 <MX_TIM1_Init+0x12c>)
 8001032:	2200      	movs	r2, #0
 8001034:	611a      	str	r2, [r3, #16]
  htim1.Init.RepetitionCounter = 0;
 8001036:	4b36      	ldr	r3, [pc, #216]	@ (8001110 <MX_TIM1_Init+0x12c>)
 8001038:	2200      	movs	r2, #0
 800103a:	615a      	str	r2, [r3, #20]
  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
 800103c:	4b34      	ldr	r3, [pc, #208]	@ (8001110 <MX_TIM1_Init+0x12c>)
 800103e:	2280      	movs	r2, #128	@ 0x80
 8001040:	619a      	str	r2, [r3, #24]
  if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
 8001042:	4833      	ldr	r0, [pc, #204]	@ (8001110 <MX_TIM1_Init+0x12c>)
 8001044:	f00d fdde 	bl	800ec04 <HAL_TIM_PWM_Init>
 8001048:	4603      	mov	r3, r0
 800104a:	2b00      	cmp	r3, #0
 800104c:	d001      	beq.n	8001052 <MX_TIM1_Init+0x6e>
  {
    Error_Handler();
 800104e:	f000 fef5 	bl	8001e3c <Error_Handler>
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 8001052:	2300      	movs	r3, #0
 8001054:	64fb      	str	r3, [r7, #76]	@ 0x4c
  sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
 8001056:	2300      	movs	r3, #0
 8001058:	653b      	str	r3, [r7, #80]	@ 0x50
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 800105a:	2300      	movs	r3, #0
 800105c:	657b      	str	r3, [r7, #84]	@ 0x54
  if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
 800105e:	f107 034c 	add.w	r3, r7, #76	@ 0x4c
 8001062:	4619      	mov	r1, r3
 8001064:	482a      	ldr	r0, [pc, #168]	@ (8001110 <MX_TIM1_Init+0x12c>)
 8001066:	f00f fb31 	bl	80106cc <HAL_TIMEx_MasterConfigSynchronization>
 800106a:	4603      	mov	r3, r0
 800106c:	2b00      	cmp	r3, #0
 800106e:	d001      	beq.n	8001074 <MX_TIM1_Init+0x90>
  {
    Error_Handler();
 8001070:	f000 fee4 	bl	8001e3c <Error_Handler>
  }
  sConfigOC.OCMode = TIM_OCMODE_PWM1;
 8001074:	2360      	movs	r3, #96	@ 0x60
 8001076:	633b      	str	r3, [r7, #48]	@ 0x30
  sConfigOC.Pulse = 99;
 8001078:	2363      	movs	r3, #99	@ 0x63
 800107a:	637b      	str	r3, [r7, #52]	@ 0x34
  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
 800107c:	2300      	movs	r3, #0
 800107e:	63bb      	str	r3, [r7, #56]	@ 0x38
  sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
 8001080:	2300      	movs	r3, #0
 8001082:	63fb      	str	r3, [r7, #60]	@ 0x3c
  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
 8001084:	2300      	movs	r3, #0
 8001086:	643b      	str	r3, [r7, #64]	@ 0x40
  sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
 8001088:	2300      	movs	r3, #0
 800108a:	647b      	str	r3, [r7, #68]	@ 0x44
  sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
 800108c:	2300      	movs	r3, #0
 800108e:	64bb      	str	r3, [r7, #72]	@ 0x48
  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
 8001090:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8001094:	2204      	movs	r2, #4
 8001096:	4619      	mov	r1, r3
 8001098:	481d      	ldr	r0, [pc, #116]	@ (8001110 <MX_TIM1_Init+0x12c>)
 800109a:	f00e fb05 	bl	800f6a8 <HAL_TIM_PWM_ConfigChannel>
 800109e:	4603      	mov	r3, r0
 80010a0:	2b00      	cmp	r3, #0
 80010a2:	d001      	beq.n	80010a8 <MX_TIM1_Init+0xc4>
  {
    Error_Handler();
 80010a4:	f000 feca 	bl	8001e3c <Error_Handler>
  }
  sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
 80010a8:	2300      	movs	r3, #0
 80010aa:	607b      	str	r3, [r7, #4]
  sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
 80010ac:	2300      	movs	r3, #0
 80010ae:	60bb      	str	r3, [r7, #8]
  sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
 80010b0:	2300      	movs	r3, #0
 80010b2:	60fb      	str	r3, [r7, #12]
  sBreakDeadTimeConfig.DeadTime = 0;
 80010b4:	2300      	movs	r3, #0
 80010b6:	613b      	str	r3, [r7, #16]
  sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
 80010b8:	2300      	movs	r3, #0
 80010ba:	617b      	str	r3, [r7, #20]
  sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
 80010bc:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
 80010c0:	61bb      	str	r3, [r7, #24]
  sBreakDeadTimeConfig.BreakFilter = 0;
 80010c2:	2300      	movs	r3, #0
 80010c4:	61fb      	str	r3, [r7, #28]
  sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
 80010c6:	2300      	movs	r3, #0
 80010c8:	623b      	str	r3, [r7, #32]
  sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
 80010ca:	f04f 7300 	mov.w	r3, #33554432	@ 0x2000000
 80010ce:	627b      	str	r3, [r7, #36]	@ 0x24
  sBreakDeadTimeConfig.Break2Filter = 0;
 80010d0:	2300      	movs	r3, #0
 80010d2:	62bb      	str	r3, [r7, #40]	@ 0x28
  sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
 80010d4:	2300      	movs	r3, #0
 80010d6:	62fb      	str	r3, [r7, #44]	@ 0x2c
  if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
 80010d8:	1d3b      	adds	r3, r7, #4
 80010da:	4619      	mov	r1, r3
 80010dc:	480c      	ldr	r0, [pc, #48]	@ (8001110 <MX_TIM1_Init+0x12c>)
 80010de:	f00f fb83 	bl	80107e8 <HAL_TIMEx_ConfigBreakDeadTime>
 80010e2:	4603      	mov	r3, r0
 80010e4:	2b00      	cmp	r3, #0
 80010e6:	d001      	beq.n	80010ec <MX_TIM1_Init+0x108>
  {
    Error_Handler();
 80010e8:	f000 fea8 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE BEGIN TIM1_Init 2 */
  memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef));
 80010ec:	4b0a      	ldr	r3, [pc, #40]	@ (8001118 <MX_TIM1_Init+0x134>)
 80010ee:	461d      	mov	r5, r3
 80010f0:	f107 0430 	add.w	r4, r7, #48	@ 0x30
 80010f4:	cc0f      	ldmia	r4!, {r0, r1, r2, r3}
 80010f6:	c50f      	stmia	r5!, {r0, r1, r2, r3}
 80010f8:	e894 0007 	ldmia.w	r4, {r0, r1, r2}
 80010fc:	e885 0007 	stmia.w	r5, {r0, r1, r2}
  /* USER CODE END TIM1_Init 2 */
  HAL_TIM_MspPostInit(&htim1);
 8001100:	4803      	ldr	r0, [pc, #12]	@ (8001110 <MX_TIM1_Init+0x12c>)
 8001102:	f002 fd27 	bl	8003b54 <HAL_TIM_MspPostInit>

}
 8001106:	bf00      	nop
 8001108:	3758      	adds	r7, #88	@ 0x58
 800110a:	46bd      	mov	sp, r7
 800110c:	bdb0      	pop	{r4, r5, r7, pc}
 800110e:	bf00      	nop
 8001110:	2400044c 	.word	0x2400044c
 8001114:	40010000 	.word	0x40010000
 8001118:	24000768 	.word	0x24000768

0800111c <MX_TIM2_Init>:
  * @brief TIM2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_TIM2_Init(void)
{
 800111c:	b580      	push	{r7, lr}
 800111e:	b08c      	sub	sp, #48	@ 0x30
 8001120:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN TIM2_Init 0 */

  /* USER CODE END TIM2_Init 0 */

  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
 8001122:	f107 0320 	add.w	r3, r7, #32
 8001126:	2200      	movs	r2, #0
 8001128:	601a      	str	r2, [r3, #0]
 800112a:	605a      	str	r2, [r3, #4]
 800112c:	609a      	str	r2, [r3, #8]
 800112e:	60da      	str	r2, [r3, #12]
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8001130:	f107 0314 	add.w	r3, r7, #20
 8001134:	2200      	movs	r2, #0
 8001136:	601a      	str	r2, [r3, #0]
 8001138:	605a      	str	r2, [r3, #4]
 800113a:	609a      	str	r2, [r3, #8]
  TIM_IC_InitTypeDef sConfigIC = {0};
 800113c:	1d3b      	adds	r3, r7, #4
 800113e:	2200      	movs	r2, #0
 8001140:	601a      	str	r2, [r3, #0]
 8001142:	605a      	str	r2, [r3, #4]
 8001144:	609a      	str	r2, [r3, #8]
 8001146:	60da      	str	r2, [r3, #12]

  /* USER CODE BEGIN TIM2_Init 1 */

  /* USER CODE END TIM2_Init 1 */
  htim2.Instance = TIM2;
 8001148:	4b31      	ldr	r3, [pc, #196]	@ (8001210 <MX_TIM2_Init+0xf4>)
 800114a:	f04f 4280 	mov.w	r2, #1073741824	@ 0x40000000
 800114e:	601a      	str	r2, [r3, #0]
  htim2.Init.Prescaler = 0;
 8001150:	4b2f      	ldr	r3, [pc, #188]	@ (8001210 <MX_TIM2_Init+0xf4>)
 8001152:	2200      	movs	r2, #0
 8001154:	605a      	str	r2, [r3, #4]
  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
 8001156:	4b2e      	ldr	r3, [pc, #184]	@ (8001210 <MX_TIM2_Init+0xf4>)
 8001158:	2200      	movs	r2, #0
 800115a:	609a      	str	r2, [r3, #8]
  htim2.Init.Period = 9999999;
 800115c:	4b2c      	ldr	r3, [pc, #176]	@ (8001210 <MX_TIM2_Init+0xf4>)
 800115e:	4a2d      	ldr	r2, [pc, #180]	@ (8001214 <MX_TIM2_Init+0xf8>)
 8001160:	60da      	str	r2, [r3, #12]
  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2;
 8001162:	4b2b      	ldr	r3, [pc, #172]	@ (8001210 <MX_TIM2_Init+0xf4>)
 8001164:	f44f 7280 	mov.w	r2, #256	@ 0x100
 8001168:	611a      	str	r2, [r3, #16]
  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
 800116a:	4b29      	ldr	r3, [pc, #164]	@ (8001210 <MX_TIM2_Init+0xf4>)
 800116c:	2280      	movs	r2, #128	@ 0x80
 800116e:	619a      	str	r2, [r3, #24]
  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
 8001170:	4827      	ldr	r0, [pc, #156]	@ (8001210 <MX_TIM2_Init+0xf4>)
 8001172:	f00d fc07 	bl	800e984 <HAL_TIM_Base_Init>
 8001176:	4603      	mov	r3, r0
 8001178:	2b00      	cmp	r3, #0
 800117a:	d001      	beq.n	8001180 <MX_TIM2_Init+0x64>
  {
    Error_Handler();
 800117c:	f000 fe5e 	bl	8001e3c <Error_Handler>
  }
  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
 8001180:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
 8001184:	623b      	str	r3, [r7, #32]
  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
 8001186:	f107 0320 	add.w	r3, r7, #32
 800118a:	4619      	mov	r1, r3
 800118c:	4820      	ldr	r0, [pc, #128]	@ (8001210 <MX_TIM2_Init+0xf4>)
 800118e:	f00e fb9f 	bl	800f8d0 <HAL_TIM_ConfigClockSource>
 8001192:	4603      	mov	r3, r0
 8001194:	2b00      	cmp	r3, #0
 8001196:	d001      	beq.n	800119c <MX_TIM2_Init+0x80>
  {
    Error_Handler();
 8001198:	f000 fe50 	bl	8001e3c <Error_Handler>
  }
  if (HAL_TIM_IC_Init(&htim2) != HAL_OK)
 800119c:	481c      	ldr	r0, [pc, #112]	@ (8001210 <MX_TIM2_Init+0xf4>)
 800119e:	f00d ff2d 	bl	800effc <HAL_TIM_IC_Init>
 80011a2:	4603      	mov	r3, r0
 80011a4:	2b00      	cmp	r3, #0
 80011a6:	d001      	beq.n	80011ac <MX_TIM2_Init+0x90>
  {
    Error_Handler();
 80011a8:	f000 fe48 	bl	8001e3c <Error_Handler>
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
 80011ac:	2320      	movs	r3, #32
 80011ae:	617b      	str	r3, [r7, #20]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE;
 80011b0:	2380      	movs	r3, #128	@ 0x80
 80011b2:	61fb      	str	r3, [r7, #28]
  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
 80011b4:	f107 0314 	add.w	r3, r7, #20
 80011b8:	4619      	mov	r1, r3
 80011ba:	4815      	ldr	r0, [pc, #84]	@ (8001210 <MX_TIM2_Init+0xf4>)
 80011bc:	f00f fa86 	bl	80106cc <HAL_TIMEx_MasterConfigSynchronization>
 80011c0:	4603      	mov	r3, r0
 80011c2:	2b00      	cmp	r3, #0
 80011c4:	d001      	beq.n	80011ca <MX_TIM2_Init+0xae>
  {
    Error_Handler();
 80011c6:	f000 fe39 	bl	8001e3c <Error_Handler>
  }
  sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
 80011ca:	2300      	movs	r3, #0
 80011cc:	607b      	str	r3, [r7, #4]
  sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
 80011ce:	2301      	movs	r3, #1
 80011d0:	60bb      	str	r3, [r7, #8]
  sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
 80011d2:	2300      	movs	r3, #0
 80011d4:	60fb      	str	r3, [r7, #12]
  sConfigIC.ICFilter = 0;
 80011d6:	2300      	movs	r3, #0
 80011d8:	613b      	str	r3, [r7, #16]
  if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_3) != HAL_OK)
 80011da:	1d3b      	adds	r3, r7, #4
 80011dc:	2208      	movs	r2, #8
 80011de:	4619      	mov	r1, r3
 80011e0:	480b      	ldr	r0, [pc, #44]	@ (8001210 <MX_TIM2_Init+0xf4>)
 80011e2:	f00e f9c4 	bl	800f56e <HAL_TIM_IC_ConfigChannel>
 80011e6:	4603      	mov	r3, r0
 80011e8:	2b00      	cmp	r3, #0
 80011ea:	d001      	beq.n	80011f0 <MX_TIM2_Init+0xd4>
  {
    Error_Handler();
 80011ec:	f000 fe26 	bl	8001e3c <Error_Handler>
  }
  if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_4) != HAL_OK)
 80011f0:	1d3b      	adds	r3, r7, #4
 80011f2:	220c      	movs	r2, #12
 80011f4:	4619      	mov	r1, r3
 80011f6:	4806      	ldr	r0, [pc, #24]	@ (8001210 <MX_TIM2_Init+0xf4>)
 80011f8:	f00e f9b9 	bl	800f56e <HAL_TIM_IC_ConfigChannel>
 80011fc:	4603      	mov	r3, r0
 80011fe:	2b00      	cmp	r3, #0
 8001200:	d001      	beq.n	8001206 <MX_TIM2_Init+0xea>
  {
    Error_Handler();
 8001202:	f000 fe1b 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE BEGIN TIM2_Init 2 */

  /* USER CODE END TIM2_Init 2 */

}
 8001206:	bf00      	nop
 8001208:	3730      	adds	r7, #48	@ 0x30
 800120a:	46bd      	mov	sp, r7
 800120c:	bd80      	pop	{r7, pc}
 800120e:	bf00      	nop
 8001210:	24000498 	.word	0x24000498
 8001214:	0098967f 	.word	0x0098967f

08001218 <MX_TIM3_Init>:
  * @brief TIM3 Initialization Function
  * @param None
  * @retval None
  */
static void MX_TIM3_Init(void)
{
 8001218:	b5b0      	push	{r4, r5, r7, lr}
 800121a:	b08a      	sub	sp, #40	@ 0x28
 800121c:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN TIM3_Init 0 */

  /* USER CODE END TIM3_Init 0 */

  TIM_MasterConfigTypeDef sMasterConfig = {0};
 800121e:	f107 031c 	add.w	r3, r7, #28
 8001222:	2200      	movs	r2, #0
 8001224:	601a      	str	r2, [r3, #0]
 8001226:	605a      	str	r2, [r3, #4]
 8001228:	609a      	str	r2, [r3, #8]
  TIM_OC_InitTypeDef sConfigOC = {0};
 800122a:	463b      	mov	r3, r7
 800122c:	2200      	movs	r2, #0
 800122e:	601a      	str	r2, [r3, #0]
 8001230:	605a      	str	r2, [r3, #4]
 8001232:	609a      	str	r2, [r3, #8]
 8001234:	60da      	str	r2, [r3, #12]
 8001236:	611a      	str	r2, [r3, #16]
 8001238:	615a      	str	r2, [r3, #20]
 800123a:	619a      	str	r2, [r3, #24]

  /* USER CODE BEGIN TIM3_Init 1 */

  /* USER CODE END TIM3_Init 1 */
  htim3.Instance = TIM3;
 800123c:	4b48      	ldr	r3, [pc, #288]	@ (8001360 <MX_TIM3_Init+0x148>)
 800123e:	4a49      	ldr	r2, [pc, #292]	@ (8001364 <MX_TIM3_Init+0x14c>)
 8001240:	601a      	str	r2, [r3, #0]
  htim3.Init.Prescaler = 199;
 8001242:	4b47      	ldr	r3, [pc, #284]	@ (8001360 <MX_TIM3_Init+0x148>)
 8001244:	22c7      	movs	r2, #199	@ 0xc7
 8001246:	605a      	str	r2, [r3, #4]
  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
 8001248:	4b45      	ldr	r3, [pc, #276]	@ (8001360 <MX_TIM3_Init+0x148>)
 800124a:	2200      	movs	r2, #0
 800124c:	609a      	str	r2, [r3, #8]
  htim3.Init.Period = 999;
 800124e:	4b44      	ldr	r3, [pc, #272]	@ (8001360 <MX_TIM3_Init+0x148>)
 8001250:	f240 32e7 	movw	r2, #999	@ 0x3e7
 8001254:	60da      	str	r2, [r3, #12]
  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
 8001256:	4b42      	ldr	r3, [pc, #264]	@ (8001360 <MX_TIM3_Init+0x148>)
 8001258:	2200      	movs	r2, #0
 800125a:	611a      	str	r2, [r3, #16]
  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
 800125c:	4b40      	ldr	r3, [pc, #256]	@ (8001360 <MX_TIM3_Init+0x148>)
 800125e:	2280      	movs	r2, #128	@ 0x80
 8001260:	619a      	str	r2, [r3, #24]
  if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
 8001262:	483f      	ldr	r0, [pc, #252]	@ (8001360 <MX_TIM3_Init+0x148>)
 8001264:	f00d fcce 	bl	800ec04 <HAL_TIM_PWM_Init>
 8001268:	4603      	mov	r3, r0
 800126a:	2b00      	cmp	r3, #0
 800126c:	d001      	beq.n	8001272 <MX_TIM3_Init+0x5a>
  {
    Error_Handler();
 800126e:	f000 fde5 	bl	8001e3c <Error_Handler>
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 8001272:	2300      	movs	r3, #0
 8001274:	61fb      	str	r3, [r7, #28]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 8001276:	2300      	movs	r3, #0
 8001278:	627b      	str	r3, [r7, #36]	@ 0x24
  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
 800127a:	f107 031c 	add.w	r3, r7, #28
 800127e:	4619      	mov	r1, r3
 8001280:	4837      	ldr	r0, [pc, #220]	@ (8001360 <MX_TIM3_Init+0x148>)
 8001282:	f00f fa23 	bl	80106cc <HAL_TIMEx_MasterConfigSynchronization>
 8001286:	4603      	mov	r3, r0
 8001288:	2b00      	cmp	r3, #0
 800128a:	d001      	beq.n	8001290 <MX_TIM3_Init+0x78>
  {
    Error_Handler();
 800128c:	f000 fdd6 	bl	8001e3c <Error_Handler>
  }
  sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1;
 8001290:	4b35      	ldr	r3, [pc, #212]	@ (8001368 <MX_TIM3_Init+0x150>)
 8001292:	603b      	str	r3, [r7, #0]
  sConfigOC.Pulse = 500;
 8001294:	f44f 73fa 	mov.w	r3, #500	@ 0x1f4
 8001298:	607b      	str	r3, [r7, #4]
  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
 800129a:	2300      	movs	r3, #0
 800129c:	60bb      	str	r3, [r7, #8]
  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
 800129e:	2300      	movs	r3, #0
 80012a0:	613b      	str	r3, [r7, #16]
  if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
 80012a2:	463b      	mov	r3, r7
 80012a4:	2200      	movs	r2, #0
 80012a6:	4619      	mov	r1, r3
 80012a8:	482d      	ldr	r0, [pc, #180]	@ (8001360 <MX_TIM3_Init+0x148>)
 80012aa:	f00e f9fd 	bl	800f6a8 <HAL_TIM_PWM_ConfigChannel>
 80012ae:	4603      	mov	r3, r0
 80012b0:	2b00      	cmp	r3, #0
 80012b2:	d001      	beq.n	80012b8 <MX_TIM3_Init+0xa0>
  {
    Error_Handler();
 80012b4:	f000 fdc2 	bl	8001e3c <Error_Handler>
  }
  __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1);
 80012b8:	4b29      	ldr	r3, [pc, #164]	@ (8001360 <MX_TIM3_Init+0x148>)
 80012ba:	681b      	ldr	r3, [r3, #0]
 80012bc:	699a      	ldr	r2, [r3, #24]
 80012be:	4b28      	ldr	r3, [pc, #160]	@ (8001360 <MX_TIM3_Init+0x148>)
 80012c0:	681b      	ldr	r3, [r3, #0]
 80012c2:	f022 0208 	bic.w	r2, r2, #8
 80012c6:	619a      	str	r2, [r3, #24]
  sConfigOC.OCMode = TIM_OCMODE_PWM1;
 80012c8:	2360      	movs	r3, #96	@ 0x60
 80012ca:	603b      	str	r3, [r7, #0]
  if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
 80012cc:	463b      	mov	r3, r7
 80012ce:	2204      	movs	r2, #4
 80012d0:	4619      	mov	r1, r3
 80012d2:	4823      	ldr	r0, [pc, #140]	@ (8001360 <MX_TIM3_Init+0x148>)
 80012d4:	f00e f9e8 	bl	800f6a8 <HAL_TIM_PWM_ConfigChannel>
 80012d8:	4603      	mov	r3, r0
 80012da:	2b00      	cmp	r3, #0
 80012dc:	d001      	beq.n	80012e2 <MX_TIM3_Init+0xca>
  {
    Error_Handler();
 80012de:	f000 fdad 	bl	8001e3c <Error_Handler>
  }
  __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2);
 80012e2:	4b1f      	ldr	r3, [pc, #124]	@ (8001360 <MX_TIM3_Init+0x148>)
 80012e4:	681b      	ldr	r3, [r3, #0]
 80012e6:	699a      	ldr	r2, [r3, #24]
 80012e8:	4b1d      	ldr	r3, [pc, #116]	@ (8001360 <MX_TIM3_Init+0x148>)
 80012ea:	681b      	ldr	r3, [r3, #0]
 80012ec:	f422 6200 	bic.w	r2, r2, #2048	@ 0x800
 80012f0:	619a      	str	r2, [r3, #24]
  if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
 80012f2:	463b      	mov	r3, r7
 80012f4:	2208      	movs	r2, #8
 80012f6:	4619      	mov	r1, r3
 80012f8:	4819      	ldr	r0, [pc, #100]	@ (8001360 <MX_TIM3_Init+0x148>)
 80012fa:	f00e f9d5 	bl	800f6a8 <HAL_TIM_PWM_ConfigChannel>
 80012fe:	4603      	mov	r3, r0
 8001300:	2b00      	cmp	r3, #0
 8001302:	d001      	beq.n	8001308 <MX_TIM3_Init+0xf0>
  {
    Error_Handler();
 8001304:	f000 fd9a 	bl	8001e3c <Error_Handler>
  }
  __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3);
 8001308:	4b15      	ldr	r3, [pc, #84]	@ (8001360 <MX_TIM3_Init+0x148>)
 800130a:	681b      	ldr	r3, [r3, #0]
 800130c:	69da      	ldr	r2, [r3, #28]
 800130e:	4b14      	ldr	r3, [pc, #80]	@ (8001360 <MX_TIM3_Init+0x148>)
 8001310:	681b      	ldr	r3, [r3, #0]
 8001312:	f022 0208 	bic.w	r2, r2, #8
 8001316:	61da      	str	r2, [r3, #28]
  if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
 8001318:	463b      	mov	r3, r7
 800131a:	220c      	movs	r2, #12
 800131c:	4619      	mov	r1, r3
 800131e:	4810      	ldr	r0, [pc, #64]	@ (8001360 <MX_TIM3_Init+0x148>)
 8001320:	f00e f9c2 	bl	800f6a8 <HAL_TIM_PWM_ConfigChannel>
 8001324:	4603      	mov	r3, r0
 8001326:	2b00      	cmp	r3, #0
 8001328:	d001      	beq.n	800132e <MX_TIM3_Init+0x116>
  {
    Error_Handler();
 800132a:	f000 fd87 	bl	8001e3c <Error_Handler>
  }
  __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4);
 800132e:	4b0c      	ldr	r3, [pc, #48]	@ (8001360 <MX_TIM3_Init+0x148>)
 8001330:	681b      	ldr	r3, [r3, #0]
 8001332:	69da      	ldr	r2, [r3, #28]
 8001334:	4b0a      	ldr	r3, [pc, #40]	@ (8001360 <MX_TIM3_Init+0x148>)
 8001336:	681b      	ldr	r3, [r3, #0]
 8001338:	f422 6200 	bic.w	r2, r2, #2048	@ 0x800
 800133c:	61da      	str	r2, [r3, #28]
  /* USER CODE BEGIN TIM3_Init 2 */
  memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef));
 800133e:	4b0b      	ldr	r3, [pc, #44]	@ (800136c <MX_TIM3_Init+0x154>)
 8001340:	461d      	mov	r5, r3
 8001342:	463c      	mov	r4, r7
 8001344:	cc0f      	ldmia	r4!, {r0, r1, r2, r3}
 8001346:	c50f      	stmia	r5!, {r0, r1, r2, r3}
 8001348:	e894 0007 	ldmia.w	r4, {r0, r1, r2}
 800134c:	e885 0007 	stmia.w	r5, {r0, r1, r2}
  /* USER CODE END TIM3_Init 2 */
  HAL_TIM_MspPostInit(&htim3);
 8001350:	4803      	ldr	r0, [pc, #12]	@ (8001360 <MX_TIM3_Init+0x148>)
 8001352:	f002 fbff 	bl	8003b54 <HAL_TIM_MspPostInit>

}
 8001356:	bf00      	nop
 8001358:	3728      	adds	r7, #40	@ 0x28
 800135a:	46bd      	mov	sp, r7
 800135c:	bdb0      	pop	{r4, r5, r7, pc}
 800135e:	bf00      	nop
 8001360:	240004e4 	.word	0x240004e4
 8001364:	40000400 	.word	0x40000400
 8001368:	00010040 	.word	0x00010040
 800136c:	24000784 	.word	0x24000784

08001370 <MX_TIM4_Init>:
  * @brief TIM4 Initialization Function
  * @param None
  * @retval None
  */
static void MX_TIM4_Init(void)
{
 8001370:	b580      	push	{r7, lr}
 8001372:	b08c      	sub	sp, #48	@ 0x30
 8001374:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN TIM4_Init 0 */

  /* USER CODE END TIM4_Init 0 */

  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
 8001376:	f107 0320 	add.w	r3, r7, #32
 800137a:	2200      	movs	r2, #0
 800137c:	601a      	str	r2, [r3, #0]
 800137e:	605a      	str	r2, [r3, #4]
 8001380:	609a      	str	r2, [r3, #8]
 8001382:	60da      	str	r2, [r3, #12]
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8001384:	f107 0314 	add.w	r3, r7, #20
 8001388:	2200      	movs	r2, #0
 800138a:	601a      	str	r2, [r3, #0]
 800138c:	605a      	str	r2, [r3, #4]
 800138e:	609a      	str	r2, [r3, #8]
  TIM_IC_InitTypeDef sConfigIC = {0};
 8001390:	1d3b      	adds	r3, r7, #4
 8001392:	2200      	movs	r2, #0
 8001394:	601a      	str	r2, [r3, #0]
 8001396:	605a      	str	r2, [r3, #4]
 8001398:	609a      	str	r2, [r3, #8]
 800139a:	60da      	str	r2, [r3, #12]

  /* USER CODE BEGIN TIM4_Init 1 */

  /* USER CODE END TIM4_Init 1 */
  htim4.Instance = TIM4;
 800139c:	4b31      	ldr	r3, [pc, #196]	@ (8001464 <MX_TIM4_Init+0xf4>)
 800139e:	4a32      	ldr	r2, [pc, #200]	@ (8001468 <MX_TIM4_Init+0xf8>)
 80013a0:	601a      	str	r2, [r3, #0]
  htim4.Init.Prescaler = 19999;
 80013a2:	4b30      	ldr	r3, [pc, #192]	@ (8001464 <MX_TIM4_Init+0xf4>)
 80013a4:	f644 621f 	movw	r2, #19999	@ 0x4e1f
 80013a8:	605a      	str	r2, [r3, #4]
  htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
 80013aa:	4b2e      	ldr	r3, [pc, #184]	@ (8001464 <MX_TIM4_Init+0xf4>)
 80013ac:	2200      	movs	r2, #0
 80013ae:	609a      	str	r2, [r3, #8]
  htim4.Init.Period = 9999;
 80013b0:	4b2c      	ldr	r3, [pc, #176]	@ (8001464 <MX_TIM4_Init+0xf4>)
 80013b2:	f242 720f 	movw	r2, #9999	@ 0x270f
 80013b6:	60da      	str	r2, [r3, #12]
  htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
 80013b8:	4b2a      	ldr	r3, [pc, #168]	@ (8001464 <MX_TIM4_Init+0xf4>)
 80013ba:	2200      	movs	r2, #0
 80013bc:	611a      	str	r2, [r3, #16]
  htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
 80013be:	4b29      	ldr	r3, [pc, #164]	@ (8001464 <MX_TIM4_Init+0xf4>)
 80013c0:	2280      	movs	r2, #128	@ 0x80
 80013c2:	619a      	str	r2, [r3, #24]
  if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
 80013c4:	4827      	ldr	r0, [pc, #156]	@ (8001464 <MX_TIM4_Init+0xf4>)
 80013c6:	f00d fadd 	bl	800e984 <HAL_TIM_Base_Init>
 80013ca:	4603      	mov	r3, r0
 80013cc:	2b00      	cmp	r3, #0
 80013ce:	d001      	beq.n	80013d4 <MX_TIM4_Init+0x64>
  {
    Error_Handler();
 80013d0:	f000 fd34 	bl	8001e3c <Error_Handler>
  }
  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
 80013d4:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
 80013d8:	623b      	str	r3, [r7, #32]
  if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
 80013da:	f107 0320 	add.w	r3, r7, #32
 80013de:	4619      	mov	r1, r3
 80013e0:	4820      	ldr	r0, [pc, #128]	@ (8001464 <MX_TIM4_Init+0xf4>)
 80013e2:	f00e fa75 	bl	800f8d0 <HAL_TIM_ConfigClockSource>
 80013e6:	4603      	mov	r3, r0
 80013e8:	2b00      	cmp	r3, #0
 80013ea:	d001      	beq.n	80013f0 <MX_TIM4_Init+0x80>
  {
    Error_Handler();
 80013ec:	f000 fd26 	bl	8001e3c <Error_Handler>
  }
  if (HAL_TIM_IC_Init(&htim4) != HAL_OK)
 80013f0:	481c      	ldr	r0, [pc, #112]	@ (8001464 <MX_TIM4_Init+0xf4>)
 80013f2:	f00d fe03 	bl	800effc <HAL_TIM_IC_Init>
 80013f6:	4603      	mov	r3, r0
 80013f8:	2b00      	cmp	r3, #0
 80013fa:	d001      	beq.n	8001400 <MX_TIM4_Init+0x90>
  {
    Error_Handler();
 80013fc:	f000 fd1e 	bl	8001e3c <Error_Handler>
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 8001400:	2300      	movs	r3, #0
 8001402:	617b      	str	r3, [r7, #20]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 8001404:	2300      	movs	r3, #0
 8001406:	61fb      	str	r3, [r7, #28]
  if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
 8001408:	f107 0314 	add.w	r3, r7, #20
 800140c:	4619      	mov	r1, r3
 800140e:	4815      	ldr	r0, [pc, #84]	@ (8001464 <MX_TIM4_Init+0xf4>)
 8001410:	f00f f95c 	bl	80106cc <HAL_TIMEx_MasterConfigSynchronization>
 8001414:	4603      	mov	r3, r0
 8001416:	2b00      	cmp	r3, #0
 8001418:	d001      	beq.n	800141e <MX_TIM4_Init+0xae>
  {
    Error_Handler();
 800141a:	f000 fd0f 	bl	8001e3c <Error_Handler>
  }
  sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
 800141e:	2300      	movs	r3, #0
 8001420:	607b      	str	r3, [r7, #4]
  sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
 8001422:	2301      	movs	r3, #1
 8001424:	60bb      	str	r3, [r7, #8]
  sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
 8001426:	2300      	movs	r3, #0
 8001428:	60fb      	str	r3, [r7, #12]
  sConfigIC.ICFilter = 0;
 800142a:	2300      	movs	r3, #0
 800142c:	613b      	str	r3, [r7, #16]
  if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_3) != HAL_OK)
 800142e:	1d3b      	adds	r3, r7, #4
 8001430:	2208      	movs	r2, #8
 8001432:	4619      	mov	r1, r3
 8001434:	480b      	ldr	r0, [pc, #44]	@ (8001464 <MX_TIM4_Init+0xf4>)
 8001436:	f00e f89a 	bl	800f56e <HAL_TIM_IC_ConfigChannel>
 800143a:	4603      	mov	r3, r0
 800143c:	2b00      	cmp	r3, #0
 800143e:	d001      	beq.n	8001444 <MX_TIM4_Init+0xd4>
  {
    Error_Handler();
 8001440:	f000 fcfc 	bl	8001e3c <Error_Handler>
  }
  if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_4) != HAL_OK)
 8001444:	1d3b      	adds	r3, r7, #4
 8001446:	220c      	movs	r2, #12
 8001448:	4619      	mov	r1, r3
 800144a:	4806      	ldr	r0, [pc, #24]	@ (8001464 <MX_TIM4_Init+0xf4>)
 800144c:	f00e f88f 	bl	800f56e <HAL_TIM_IC_ConfigChannel>
 8001450:	4603      	mov	r3, r0
 8001452:	2b00      	cmp	r3, #0
 8001454:	d001      	beq.n	800145a <MX_TIM4_Init+0xea>
  {
    Error_Handler();
 8001456:	f000 fcf1 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE BEGIN TIM4_Init 2 */

  /* USER CODE END TIM4_Init 2 */

}
 800145a:	bf00      	nop
 800145c:	3730      	adds	r7, #48	@ 0x30
 800145e:	46bd      	mov	sp, r7
 8001460:	bd80      	pop	{r7, pc}
 8001462:	bf00      	nop
 8001464:	24000530 	.word	0x24000530
 8001468:	40000800 	.word	0x40000800

0800146c <MX_UART8_Init>:
  * @brief UART8 Initialization Function
  * @param None
  * @retval None
  */
static void MX_UART8_Init(void)
{
 800146c:	b580      	push	{r7, lr}
 800146e:	af00      	add	r7, sp, #0
  /* USER CODE END UART8_Init 0 */

  /* USER CODE BEGIN UART8_Init 1 */

  /* USER CODE END UART8_Init 1 */
  huart8.Instance = UART8;
 8001470:	4b22      	ldr	r3, [pc, #136]	@ (80014fc <MX_UART8_Init+0x90>)
 8001472:	4a23      	ldr	r2, [pc, #140]	@ (8001500 <MX_UART8_Init+0x94>)
 8001474:	601a      	str	r2, [r3, #0]
  huart8.Init.BaudRate = 115200;
 8001476:	4b21      	ldr	r3, [pc, #132]	@ (80014fc <MX_UART8_Init+0x90>)
 8001478:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
 800147c:	605a      	str	r2, [r3, #4]
  huart8.Init.WordLength = UART_WORDLENGTH_8B;
 800147e:	4b1f      	ldr	r3, [pc, #124]	@ (80014fc <MX_UART8_Init+0x90>)
 8001480:	2200      	movs	r2, #0
 8001482:	609a      	str	r2, [r3, #8]
  huart8.Init.StopBits = UART_STOPBITS_1;
 8001484:	4b1d      	ldr	r3, [pc, #116]	@ (80014fc <MX_UART8_Init+0x90>)
 8001486:	2200      	movs	r2, #0
 8001488:	60da      	str	r2, [r3, #12]
  huart8.Init.Parity = UART_PARITY_NONE;
 800148a:	4b1c      	ldr	r3, [pc, #112]	@ (80014fc <MX_UART8_Init+0x90>)
 800148c:	2200      	movs	r2, #0
 800148e:	611a      	str	r2, [r3, #16]
  huart8.Init.Mode = UART_MODE_TX_RX;
 8001490:	4b1a      	ldr	r3, [pc, #104]	@ (80014fc <MX_UART8_Init+0x90>)
 8001492:	220c      	movs	r2, #12
 8001494:	615a      	str	r2, [r3, #20]
  huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8001496:	4b19      	ldr	r3, [pc, #100]	@ (80014fc <MX_UART8_Init+0x90>)
 8001498:	2200      	movs	r2, #0
 800149a:	619a      	str	r2, [r3, #24]
  huart8.Init.OverSampling = UART_OVERSAMPLING_16;
 800149c:	4b17      	ldr	r3, [pc, #92]	@ (80014fc <MX_UART8_Init+0x90>)
 800149e:	2200      	movs	r2, #0
 80014a0:	61da      	str	r2, [r3, #28]
  huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 80014a2:	4b16      	ldr	r3, [pc, #88]	@ (80014fc <MX_UART8_Init+0x90>)
 80014a4:	2200      	movs	r2, #0
 80014a6:	621a      	str	r2, [r3, #32]
  huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1;
 80014a8:	4b14      	ldr	r3, [pc, #80]	@ (80014fc <MX_UART8_Init+0x90>)
 80014aa:	2200      	movs	r2, #0
 80014ac:	625a      	str	r2, [r3, #36]	@ 0x24
  huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 80014ae:	4b13      	ldr	r3, [pc, #76]	@ (80014fc <MX_UART8_Init+0x90>)
 80014b0:	2200      	movs	r2, #0
 80014b2:	629a      	str	r2, [r3, #40]	@ 0x28
  if (HAL_UART_Init(&huart8) != HAL_OK)
 80014b4:	4811      	ldr	r0, [pc, #68]	@ (80014fc <MX_UART8_Init+0x90>)
 80014b6:	f00f fa33 	bl	8010920 <HAL_UART_Init>
 80014ba:	4603      	mov	r3, r0
 80014bc:	2b00      	cmp	r3, #0
 80014be:	d001      	beq.n	80014c4 <MX_UART8_Init+0x58>
  {
    Error_Handler();
 80014c0:	f000 fcbc 	bl	8001e3c <Error_Handler>
  }
  if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
 80014c4:	2100      	movs	r1, #0
 80014c6:	480d      	ldr	r0, [pc, #52]	@ (80014fc <MX_UART8_Init+0x90>)
 80014c8:	f011 ff61 	bl	801338e <HAL_UARTEx_SetTxFifoThreshold>
 80014cc:	4603      	mov	r3, r0
 80014ce:	2b00      	cmp	r3, #0
 80014d0:	d001      	beq.n	80014d6 <MX_UART8_Init+0x6a>
  {
    Error_Handler();
 80014d2:	f000 fcb3 	bl	8001e3c <Error_Handler>
  }
  if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
 80014d6:	2100      	movs	r1, #0
 80014d8:	4808      	ldr	r0, [pc, #32]	@ (80014fc <MX_UART8_Init+0x90>)
 80014da:	f011 ff96 	bl	801340a <HAL_UARTEx_SetRxFifoThreshold>
 80014de:	4603      	mov	r3, r0
 80014e0:	2b00      	cmp	r3, #0
 80014e2:	d001      	beq.n	80014e8 <MX_UART8_Init+0x7c>
  {
    Error_Handler();
 80014e4:	f000 fcaa 	bl	8001e3c <Error_Handler>
  }
  if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK)
 80014e8:	4804      	ldr	r0, [pc, #16]	@ (80014fc <MX_UART8_Init+0x90>)
 80014ea:	f011 ff17 	bl	801331c <HAL_UARTEx_DisableFifoMode>
 80014ee:	4603      	mov	r3, r0
 80014f0:	2b00      	cmp	r3, #0
 80014f2:	d001      	beq.n	80014f8 <MX_UART8_Init+0x8c>
  {
    Error_Handler();
 80014f4:	f000 fca2 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE BEGIN UART8_Init 2 */

  /* USER CODE END UART8_Init 2 */

}
 80014f8:	bf00      	nop
 80014fa:	bd80      	pop	{r7, pc}
 80014fc:	2400057c 	.word	0x2400057c
 8001500:	40007c00 	.word	0x40007c00

08001504 <MX_USART1_UART_Init>:
  * @brief USART1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART1_UART_Init(void)
{
 8001504:	b580      	push	{r7, lr}
 8001506:	af00      	add	r7, sp, #0
  /* USER CODE END USART1_Init 0 */

  /* USER CODE BEGIN USART1_Init 1 */

  /* USER CODE END USART1_Init 1 */
  huart1.Instance = USART1;
 8001508:	4b24      	ldr	r3, [pc, #144]	@ (800159c <MX_USART1_UART_Init+0x98>)
 800150a:	4a25      	ldr	r2, [pc, #148]	@ (80015a0 <MX_USART1_UART_Init+0x9c>)
 800150c:	601a      	str	r2, [r3, #0]
  huart1.Init.BaudRate = 115200;
 800150e:	4b23      	ldr	r3, [pc, #140]	@ (800159c <MX_USART1_UART_Init+0x98>)
 8001510:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
 8001514:	605a      	str	r2, [r3, #4]
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 8001516:	4b21      	ldr	r3, [pc, #132]	@ (800159c <MX_USART1_UART_Init+0x98>)
 8001518:	2200      	movs	r2, #0
 800151a:	609a      	str	r2, [r3, #8]
  huart1.Init.StopBits = UART_STOPBITS_1;
 800151c:	4b1f      	ldr	r3, [pc, #124]	@ (800159c <MX_USART1_UART_Init+0x98>)
 800151e:	2200      	movs	r2, #0
 8001520:	60da      	str	r2, [r3, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 8001522:	4b1e      	ldr	r3, [pc, #120]	@ (800159c <MX_USART1_UART_Init+0x98>)
 8001524:	2200      	movs	r2, #0
 8001526:	611a      	str	r2, [r3, #16]
  huart1.Init.Mode = UART_MODE_TX_RX;
 8001528:	4b1c      	ldr	r3, [pc, #112]	@ (800159c <MX_USART1_UART_Init+0x98>)
 800152a:	220c      	movs	r2, #12
 800152c:	615a      	str	r2, [r3, #20]
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 800152e:	4b1b      	ldr	r3, [pc, #108]	@ (800159c <MX_USART1_UART_Init+0x98>)
 8001530:	2200      	movs	r2, #0
 8001532:	619a      	str	r2, [r3, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 8001534:	4b19      	ldr	r3, [pc, #100]	@ (800159c <MX_USART1_UART_Init+0x98>)
 8001536:	2200      	movs	r2, #0
 8001538:	61da      	str	r2, [r3, #28]
  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 800153a:	4b18      	ldr	r3, [pc, #96]	@ (800159c <MX_USART1_UART_Init+0x98>)
 800153c:	2200      	movs	r2, #0
 800153e:	621a      	str	r2, [r3, #32]
  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
 8001540:	4b16      	ldr	r3, [pc, #88]	@ (800159c <MX_USART1_UART_Init+0x98>)
 8001542:	2200      	movs	r2, #0
 8001544:	625a      	str	r2, [r3, #36]	@ 0x24
  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_TXINVERT_INIT;
 8001546:	4b15      	ldr	r3, [pc, #84]	@ (800159c <MX_USART1_UART_Init+0x98>)
 8001548:	2201      	movs	r2, #1
 800154a:	629a      	str	r2, [r3, #40]	@ 0x28
  huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE;
 800154c:	4b13      	ldr	r3, [pc, #76]	@ (800159c <MX_USART1_UART_Init+0x98>)
 800154e:	f44f 3200 	mov.w	r2, #131072	@ 0x20000
 8001552:	62da      	str	r2, [r3, #44]	@ 0x2c
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8001554:	4811      	ldr	r0, [pc, #68]	@ (800159c <MX_USART1_UART_Init+0x98>)
 8001556:	f00f f9e3 	bl	8010920 <HAL_UART_Init>
 800155a:	4603      	mov	r3, r0
 800155c:	2b00      	cmp	r3, #0
 800155e:	d001      	beq.n	8001564 <MX_USART1_UART_Init+0x60>
  {
    Error_Handler();
 8001560:	f000 fc6c 	bl	8001e3c <Error_Handler>
  }
  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
 8001564:	2100      	movs	r1, #0
 8001566:	480d      	ldr	r0, [pc, #52]	@ (800159c <MX_USART1_UART_Init+0x98>)
 8001568:	f011 ff11 	bl	801338e <HAL_UARTEx_SetTxFifoThreshold>
 800156c:	4603      	mov	r3, r0
 800156e:	2b00      	cmp	r3, #0
 8001570:	d001      	beq.n	8001576 <MX_USART1_UART_Init+0x72>
  {
    Error_Handler();
 8001572:	f000 fc63 	bl	8001e3c <Error_Handler>
  }
  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
 8001576:	2100      	movs	r1, #0
 8001578:	4808      	ldr	r0, [pc, #32]	@ (800159c <MX_USART1_UART_Init+0x98>)
 800157a:	f011 ff46 	bl	801340a <HAL_UARTEx_SetRxFifoThreshold>
 800157e:	4603      	mov	r3, r0
 8001580:	2b00      	cmp	r3, #0
 8001582:	d001      	beq.n	8001588 <MX_USART1_UART_Init+0x84>
  {
    Error_Handler();
 8001584:	f000 fc5a 	bl	8001e3c <Error_Handler>
  }
  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
 8001588:	4804      	ldr	r0, [pc, #16]	@ (800159c <MX_USART1_UART_Init+0x98>)
 800158a:	f011 fec7 	bl	801331c <HAL_UARTEx_DisableFifoMode>
 800158e:	4603      	mov	r3, r0
 8001590:	2b00      	cmp	r3, #0
 8001592:	d001      	beq.n	8001598 <MX_USART1_UART_Init+0x94>
  {
    Error_Handler();
 8001594:	f000 fc52 	bl	8001e3c <Error_Handler>
  }
  /* USER CODE BEGIN USART1_Init 2 */

  /* USER CODE END USART1_Init 2 */

}
 8001598:	bf00      	nop
 800159a:	bd80      	pop	{r7, pc}
 800159c:	24000610 	.word	0x24000610
 80015a0:	40011000 	.word	0x40011000

080015a4 <MX_DMA_Init>:

/**
  * Enable DMA controller clock
  */
static void MX_DMA_Init(void)
{
 80015a4:	b580      	push	{r7, lr}
 80015a6:	b082      	sub	sp, #8
 80015a8:	af00      	add	r7, sp, #0

  /* DMA controller clock enable */
  __HAL_RCC_DMA1_CLK_ENABLE();
 80015aa:	4b15      	ldr	r3, [pc, #84]	@ (8001600 <MX_DMA_Init+0x5c>)
 80015ac:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 80015b0:	4a13      	ldr	r2, [pc, #76]	@ (8001600 <MX_DMA_Init+0x5c>)
 80015b2:	f043 0301 	orr.w	r3, r3, #1
 80015b6:	f8c2 30d8 	str.w	r3, [r2, #216]	@ 0xd8
 80015ba:	4b11      	ldr	r3, [pc, #68]	@ (8001600 <MX_DMA_Init+0x5c>)
 80015bc:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 80015c0:	f003 0301 	and.w	r3, r3, #1
 80015c4:	607b      	str	r3, [r7, #4]
 80015c6:	687b      	ldr	r3, [r7, #4]

  /* DMA interrupt init */
  /* DMA1_Stream0_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
 80015c8:	2200      	movs	r2, #0
 80015ca:	2105      	movs	r1, #5
 80015cc:	200b      	movs	r0, #11
 80015ce:	f005 fddb 	bl	8007188 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
 80015d2:	200b      	movs	r0, #11
 80015d4:	f005 fdf2 	bl	80071bc <HAL_NVIC_EnableIRQ>
  /* DMA1_Stream1_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0);
 80015d8:	2200      	movs	r2, #0
 80015da:	2105      	movs	r1, #5
 80015dc:	200c      	movs	r0, #12
 80015de:	f005 fdd3 	bl	8007188 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
 80015e2:	200c      	movs	r0, #12
 80015e4:	f005 fdea 	bl	80071bc <HAL_NVIC_EnableIRQ>
  /* DMA1_Stream2_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0);
 80015e8:	2200      	movs	r2, #0
 80015ea:	2105      	movs	r1, #5
 80015ec:	200d      	movs	r0, #13
 80015ee:	f005 fdcb 	bl	8007188 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
 80015f2:	200d      	movs	r0, #13
 80015f4:	f005 fde2 	bl	80071bc <HAL_NVIC_EnableIRQ>

}
 80015f8:	bf00      	nop
 80015fa:	3708      	adds	r7, #8
 80015fc:	46bd      	mov	sp, r7
 80015fe:	bd80      	pop	{r7, pc}
 8001600:	58024400 	.word	0x58024400

08001604 <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 8001604:	b580      	push	{r7, lr}
 8001606:	b08c      	sub	sp, #48	@ 0x30
 8001608:	af00      	add	r7, sp, #0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 800160a:	f107 031c 	add.w	r3, r7, #28
 800160e:	2200      	movs	r2, #0
 8001610:	601a      	str	r2, [r3, #0]
 8001612:	605a      	str	r2, [r3, #4]
 8001614:	609a      	str	r2, [r3, #8]
 8001616:	60da      	str	r2, [r3, #12]
 8001618:	611a      	str	r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOH_CLK_ENABLE();
 800161a:	4b58      	ldr	r3, [pc, #352]	@ (800177c <MX_GPIO_Init+0x178>)
 800161c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001620:	4a56      	ldr	r2, [pc, #344]	@ (800177c <MX_GPIO_Init+0x178>)
 8001622:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 8001626:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 800162a:	4b54      	ldr	r3, [pc, #336]	@ (800177c <MX_GPIO_Init+0x178>)
 800162c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001630:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8001634:	61bb      	str	r3, [r7, #24]
 8001636:	69bb      	ldr	r3, [r7, #24]
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8001638:	4b50      	ldr	r3, [pc, #320]	@ (800177c <MX_GPIO_Init+0x178>)
 800163a:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800163e:	4a4f      	ldr	r2, [pc, #316]	@ (800177c <MX_GPIO_Init+0x178>)
 8001640:	f043 0304 	orr.w	r3, r3, #4
 8001644:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8001648:	4b4c      	ldr	r3, [pc, #304]	@ (800177c <MX_GPIO_Init+0x178>)
 800164a:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800164e:	f003 0304 	and.w	r3, r3, #4
 8001652:	617b      	str	r3, [r7, #20]
 8001654:	697b      	ldr	r3, [r7, #20]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8001656:	4b49      	ldr	r3, [pc, #292]	@ (800177c <MX_GPIO_Init+0x178>)
 8001658:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800165c:	4a47      	ldr	r2, [pc, #284]	@ (800177c <MX_GPIO_Init+0x178>)
 800165e:	f043 0301 	orr.w	r3, r3, #1
 8001662:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8001666:	4b45      	ldr	r3, [pc, #276]	@ (800177c <MX_GPIO_Init+0x178>)
 8001668:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800166c:	f003 0301 	and.w	r3, r3, #1
 8001670:	613b      	str	r3, [r7, #16]
 8001672:	693b      	ldr	r3, [r7, #16]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8001674:	4b41      	ldr	r3, [pc, #260]	@ (800177c <MX_GPIO_Init+0x178>)
 8001676:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800167a:	4a40      	ldr	r2, [pc, #256]	@ (800177c <MX_GPIO_Init+0x178>)
 800167c:	f043 0302 	orr.w	r3, r3, #2
 8001680:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8001684:	4b3d      	ldr	r3, [pc, #244]	@ (800177c <MX_GPIO_Init+0x178>)
 8001686:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800168a:	f003 0302 	and.w	r3, r3, #2
 800168e:	60fb      	str	r3, [r7, #12]
 8001690:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_GPIOE_CLK_ENABLE();
 8001692:	4b3a      	ldr	r3, [pc, #232]	@ (800177c <MX_GPIO_Init+0x178>)
 8001694:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8001698:	4a38      	ldr	r2, [pc, #224]	@ (800177c <MX_GPIO_Init+0x178>)
 800169a:	f043 0310 	orr.w	r3, r3, #16
 800169e:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80016a2:	4b36      	ldr	r3, [pc, #216]	@ (800177c <MX_GPIO_Init+0x178>)
 80016a4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80016a8:	f003 0310 	and.w	r3, r3, #16
 80016ac:	60bb      	str	r3, [r7, #8]
 80016ae:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_GPIOD_CLK_ENABLE();
 80016b0:	4b32      	ldr	r3, [pc, #200]	@ (800177c <MX_GPIO_Init+0x178>)
 80016b2:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80016b6:	4a31      	ldr	r2, [pc, #196]	@ (800177c <MX_GPIO_Init+0x178>)
 80016b8:	f043 0308 	orr.w	r3, r3, #8
 80016bc:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80016c0:	4b2e      	ldr	r3, [pc, #184]	@ (800177c <MX_GPIO_Init+0x178>)
 80016c2:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80016c6:	f003 0308 	and.w	r3, r3, #8
 80016ca:	607b      	str	r3, [r7, #4]
 80016cc:	687b      	ldr	r3, [r7, #4]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
 80016ce:	2200      	movs	r2, #0
 80016d0:	f24e 7180 	movw	r1, #59264	@ 0xe780
 80016d4:	482a      	ldr	r0, [pc, #168]	@ (8001780 <MX_GPIO_Init+0x17c>)
 80016d6:	f009 fa51 	bl	800ab7c <HAL_GPIO_WritePin>
                          |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15, GPIO_PIN_RESET);

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET);
 80016da:	2200      	movs	r2, #0
 80016dc:	21f0      	movs	r1, #240	@ 0xf0
 80016de:	4829      	ldr	r0, [pc, #164]	@ (8001784 <MX_GPIO_Init+0x180>)
 80016e0:	f009 fa4c 	bl	800ab7c <HAL_GPIO_WritePin>

  /*Configure GPIO pins : PE7 PE8 PE9 PE10
                           PE13 PE14 PE15 */
  GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
 80016e4:	f24e 7380 	movw	r3, #59264	@ 0xe780
 80016e8:	61fb      	str	r3, [r7, #28]
                          |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80016ea:	2301      	movs	r3, #1
 80016ec:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80016ee:	2300      	movs	r3, #0
 80016f0:	627b      	str	r3, [r7, #36]	@ 0x24
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80016f2:	2300      	movs	r3, #0
 80016f4:	62bb      	str	r3, [r7, #40]	@ 0x28
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 80016f6:	f107 031c 	add.w	r3, r7, #28
 80016fa:	4619      	mov	r1, r3
 80016fc:	4820      	ldr	r0, [pc, #128]	@ (8001780 <MX_GPIO_Init+0x17c>)
 80016fe:	f009 f875 	bl	800a7ec <HAL_GPIO_Init>

  /*Configure GPIO pins : PD8 PD9 PD10 PD11
                           PD12 PD13 */
  GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
 8001702:	f44f 537c 	mov.w	r3, #16128	@ 0x3f00
 8001706:	61fb      	str	r3, [r7, #28]
                          |GPIO_PIN_12|GPIO_PIN_13;
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
 8001708:	f44f 1344 	mov.w	r3, #3211264	@ 0x310000
 800170c:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 800170e:	2300      	movs	r3, #0
 8001710:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8001712:	f107 031c 	add.w	r3, r7, #28
 8001716:	4619      	mov	r1, r3
 8001718:	481a      	ldr	r0, [pc, #104]	@ (8001784 <MX_GPIO_Init+0x180>)
 800171a:	f009 f867 	bl	800a7ec <HAL_GPIO_Init>

  /*Configure GPIO pin : PD3 */
  GPIO_InitStruct.Pin = GPIO_PIN_3;
 800171e:	2308      	movs	r3, #8
 8001720:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8001722:	2300      	movs	r3, #0
 8001724:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001726:	2300      	movs	r3, #0
 8001728:	627b      	str	r3, [r7, #36]	@ 0x24
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 800172a:	f107 031c 	add.w	r3, r7, #28
 800172e:	4619      	mov	r1, r3
 8001730:	4814      	ldr	r0, [pc, #80]	@ (8001784 <MX_GPIO_Init+0x180>)
 8001732:	f009 f85b 	bl	800a7ec <HAL_GPIO_Init>

  /*Configure GPIO pins : PD4 PD5 PD6 PD7 */
  GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
 8001736:	23f0      	movs	r3, #240	@ 0xf0
 8001738:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 800173a:	2301      	movs	r3, #1
 800173c:	623b      	str	r3, [r7, #32]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 800173e:	2300      	movs	r3, #0
 8001740:	627b      	str	r3, [r7, #36]	@ 0x24
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8001742:	2300      	movs	r3, #0
 8001744:	62bb      	str	r3, [r7, #40]	@ 0x28
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8001746:	f107 031c 	add.w	r3, r7, #28
 800174a:	4619      	mov	r1, r3
 800174c:	480d      	ldr	r0, [pc, #52]	@ (8001784 <MX_GPIO_Init+0x180>)
 800174e:	f009 f84d 	bl	800a7ec <HAL_GPIO_Init>

  /* EXTI interrupt init*/
  HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0);
 8001752:	2200      	movs	r2, #0
 8001754:	2105      	movs	r1, #5
 8001756:	2017      	movs	r0, #23
 8001758:	f005 fd16 	bl	8007188 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
 800175c:	2017      	movs	r0, #23
 800175e:	f005 fd2d 	bl	80071bc <HAL_NVIC_EnableIRQ>

  HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0);
 8001762:	2200      	movs	r2, #0
 8001764:	2105      	movs	r1, #5
 8001766:	2028      	movs	r0, #40	@ 0x28
 8001768:	f005 fd0e 	bl	8007188 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
 800176c:	2028      	movs	r0, #40	@ 0x28
 800176e:	f005 fd25 	bl	80071bc <HAL_NVIC_EnableIRQ>

/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
 8001772:	bf00      	nop
 8001774:	3730      	adds	r7, #48	@ 0x30
 8001776:	46bd      	mov	sp, r7
 8001778:	bd80      	pop	{r7, pc}
 800177a:	bf00      	nop
 800177c:	58024400 	.word	0x58024400
 8001780:	58021000 	.word	0x58021000
 8001784:	58020c00 	.word	0x58020c00

08001788 <HAL_ADC_ConvCpltCallback>:

/* USER CODE BEGIN 4 */
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
{
 8001788:	b580      	push	{r7, lr}
 800178a:	b08e      	sub	sp, #56	@ 0x38
 800178c:	af00      	add	r7, sp, #0
 800178e:	6078      	str	r0, [r7, #4]
	if(hadc->Instance == ADC1)
 8001790:	687b      	ldr	r3, [r7, #4]
 8001792:	681b      	ldr	r3, [r3, #0]
 8001794:	4a67      	ldr	r2, [pc, #412]	@ (8001934 <HAL_ADC_ConvCpltCallback+0x1ac>)
 8001796:	4293      	cmp	r3, r2
 8001798:	d13f      	bne.n	800181a <HAL_ADC_ConvCpltCallback+0x92>
	{
		DbgLEDToggle(DBG_LED4);
 800179a:	2080      	movs	r0, #128	@ 0x80
 800179c:	f001 fad8 	bl	8002d50 <DbgLEDToggle>
		SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc1Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE);
 80017a0:	4b65      	ldr	r3, [pc, #404]	@ (8001938 <HAL_ADC_ConvCpltCallback+0x1b0>)
 80017a2:	f023 031f 	bic.w	r3, r3, #31
 80017a6:	637b      	str	r3, [r7, #52]	@ 0x34
 80017a8:	2320      	movs	r3, #32
 80017aa:	633b      	str	r3, [r7, #48]	@ 0x30
  \param[in]   dsize   size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
{
  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
    if ( dsize > 0 ) { 
 80017ac:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80017ae:	2b00      	cmp	r3, #0
 80017b0:	dd1d      	ble.n	80017ee <HAL_ADC_ConvCpltCallback+0x66>
       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
 80017b2:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80017b4:	f003 021f 	and.w	r2, r3, #31
 80017b8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80017ba:	4413      	add	r3, r2
 80017bc:	62fb      	str	r3, [r7, #44]	@ 0x2c
      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
 80017be:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80017c0:	62bb      	str	r3, [r7, #40]	@ 0x28
  __ASM volatile ("dsb 0xF":::"memory");
 80017c2:	f3bf 8f4f 	dsb	sy
}
 80017c6:	bf00      	nop
    
      __DSB();

      do {
        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
 80017c8:	4a5c      	ldr	r2, [pc, #368]	@ (800193c <HAL_ADC_ConvCpltCallback+0x1b4>)
 80017ca:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80017cc:	f8c2 325c 	str.w	r3, [r2, #604]	@ 0x25c
        op_addr += __SCB_DCACHE_LINE_SIZE;
 80017d0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80017d2:	3320      	adds	r3, #32
 80017d4:	62bb      	str	r3, [r7, #40]	@ 0x28
        op_size -= __SCB_DCACHE_LINE_SIZE;
 80017d6:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80017d8:	3b20      	subs	r3, #32
 80017da:	62fb      	str	r3, [r7, #44]	@ 0x2c
      } while ( op_size > 0 );
 80017dc:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80017de:	2b00      	cmp	r3, #0
 80017e0:	dcf2      	bgt.n	80017c8 <HAL_ADC_ConvCpltCallback+0x40>
  __ASM volatile ("dsb 0xF":::"memory");
 80017e2:	f3bf 8f4f 	dsb	sy
}
 80017e6:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 80017e8:	f3bf 8f6f 	isb	sy
}
 80017ec:	bf00      	nop

      __DSB();
      __ISB();
    }
  #endif
}
 80017ee:	bf00      	nop
		if(adc1MeasDataQueue != NULL)
 80017f0:	4b53      	ldr	r3, [pc, #332]	@ (8001940 <HAL_ADC_ConvCpltCallback+0x1b8>)
 80017f2:	681b      	ldr	r3, [r3, #0]
 80017f4:	2b00      	cmp	r3, #0
 80017f6:	d006      	beq.n	8001806 <HAL_ADC_ConvCpltCallback+0x7e>
		{
			osMessageQueuePut(adc1MeasDataQueue, &adc1Data, 0, 0);
 80017f8:	4b51      	ldr	r3, [pc, #324]	@ (8001940 <HAL_ADC_ConvCpltCallback+0x1b8>)
 80017fa:	6818      	ldr	r0, [r3, #0]
 80017fc:	2300      	movs	r3, #0
 80017fe:	2200      	movs	r2, #0
 8001800:	494d      	ldr	r1, [pc, #308]	@ (8001938 <HAL_ADC_ConvCpltCallback+0x1b0>)
 8001802:	f012 fa93 	bl	8013d2c <osMessageQueuePut>
		}
		if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK)
 8001806:	2207      	movs	r2, #7
 8001808:	494b      	ldr	r1, [pc, #300]	@ (8001938 <HAL_ADC_ConvCpltCallback+0x1b0>)
 800180a:	484e      	ldr	r0, [pc, #312]	@ (8001944 <HAL_ADC_ConvCpltCallback+0x1bc>)
 800180c:	f004 fa18 	bl	8005c40 <HAL_ADC_Start_DMA>
 8001810:	4603      	mov	r3, r0
 8001812:	2b00      	cmp	r3, #0
 8001814:	d001      	beq.n	800181a <HAL_ADC_ConvCpltCallback+0x92>
		{
		  Error_Handler();
 8001816:	f000 fb11 	bl	8001e3c <Error_Handler>
		}
	}
	if(hadc->Instance == ADC2)
 800181a:	687b      	ldr	r3, [r7, #4]
 800181c:	681b      	ldr	r3, [r3, #0]
 800181e:	4a4a      	ldr	r2, [pc, #296]	@ (8001948 <HAL_ADC_ConvCpltCallback+0x1c0>)
 8001820:	4293      	cmp	r3, r2
 8001822:	d13c      	bne.n	800189e <HAL_ADC_ConvCpltCallback+0x116>
	{
		SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc2Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE);
 8001824:	4b49      	ldr	r3, [pc, #292]	@ (800194c <HAL_ADC_ConvCpltCallback+0x1c4>)
 8001826:	f023 031f 	bic.w	r3, r3, #31
 800182a:	627b      	str	r3, [r7, #36]	@ 0x24
 800182c:	2320      	movs	r3, #32
 800182e:	623b      	str	r3, [r7, #32]
    if ( dsize > 0 ) { 
 8001830:	6a3b      	ldr	r3, [r7, #32]
 8001832:	2b00      	cmp	r3, #0
 8001834:	dd1d      	ble.n	8001872 <HAL_ADC_ConvCpltCallback+0xea>
       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
 8001836:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8001838:	f003 021f 	and.w	r2, r3, #31
 800183c:	6a3b      	ldr	r3, [r7, #32]
 800183e:	4413      	add	r3, r2
 8001840:	61fb      	str	r3, [r7, #28]
      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
 8001842:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8001844:	61bb      	str	r3, [r7, #24]
  __ASM volatile ("dsb 0xF":::"memory");
 8001846:	f3bf 8f4f 	dsb	sy
}
 800184a:	bf00      	nop
        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
 800184c:	4a3b      	ldr	r2, [pc, #236]	@ (800193c <HAL_ADC_ConvCpltCallback+0x1b4>)
 800184e:	69bb      	ldr	r3, [r7, #24]
 8001850:	f8c2 325c 	str.w	r3, [r2, #604]	@ 0x25c
        op_addr += __SCB_DCACHE_LINE_SIZE;
 8001854:	69bb      	ldr	r3, [r7, #24]
 8001856:	3320      	adds	r3, #32
 8001858:	61bb      	str	r3, [r7, #24]
        op_size -= __SCB_DCACHE_LINE_SIZE;
 800185a:	69fb      	ldr	r3, [r7, #28]
 800185c:	3b20      	subs	r3, #32
 800185e:	61fb      	str	r3, [r7, #28]
      } while ( op_size > 0 );
 8001860:	69fb      	ldr	r3, [r7, #28]
 8001862:	2b00      	cmp	r3, #0
 8001864:	dcf2      	bgt.n	800184c <HAL_ADC_ConvCpltCallback+0xc4>
  __ASM volatile ("dsb 0xF":::"memory");
 8001866:	f3bf 8f4f 	dsb	sy
}
 800186a:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 800186c:	f3bf 8f6f 	isb	sy
}
 8001870:	bf00      	nop
}
 8001872:	bf00      	nop
		if(adc2MeasDataQueue != NULL)
 8001874:	4b36      	ldr	r3, [pc, #216]	@ (8001950 <HAL_ADC_ConvCpltCallback+0x1c8>)
 8001876:	681b      	ldr	r3, [r3, #0]
 8001878:	2b00      	cmp	r3, #0
 800187a:	d006      	beq.n	800188a <HAL_ADC_ConvCpltCallback+0x102>
		{
			osMessageQueuePut(adc2MeasDataQueue, &adc2Data, 0, 0);
 800187c:	4b34      	ldr	r3, [pc, #208]	@ (8001950 <HAL_ADC_ConvCpltCallback+0x1c8>)
 800187e:	6818      	ldr	r0, [r3, #0]
 8001880:	2300      	movs	r3, #0
 8001882:	2200      	movs	r2, #0
 8001884:	4931      	ldr	r1, [pc, #196]	@ (800194c <HAL_ADC_ConvCpltCallback+0x1c4>)
 8001886:	f012 fa51 	bl	8013d2c <osMessageQueuePut>
		}
		if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK)
 800188a:	2203      	movs	r2, #3
 800188c:	492f      	ldr	r1, [pc, #188]	@ (800194c <HAL_ADC_ConvCpltCallback+0x1c4>)
 800188e:	4831      	ldr	r0, [pc, #196]	@ (8001954 <HAL_ADC_ConvCpltCallback+0x1cc>)
 8001890:	f004 f9d6 	bl	8005c40 <HAL_ADC_Start_DMA>
 8001894:	4603      	mov	r3, r0
 8001896:	2b00      	cmp	r3, #0
 8001898:	d001      	beq.n	800189e <HAL_ADC_ConvCpltCallback+0x116>
		{
		  Error_Handler();
 800189a:	f000 facf 	bl	8001e3c <Error_Handler>
		}
	}
	if(hadc->Instance == ADC3)
 800189e:	687b      	ldr	r3, [r7, #4]
 80018a0:	681b      	ldr	r3, [r3, #0]
 80018a2:	4a2d      	ldr	r2, [pc, #180]	@ (8001958 <HAL_ADC_ConvCpltCallback+0x1d0>)
 80018a4:	4293      	cmp	r3, r2
 80018a6:	d13c      	bne.n	8001922 <HAL_ADC_ConvCpltCallback+0x19a>
	{
		SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc3Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE);
 80018a8:	4b2c      	ldr	r3, [pc, #176]	@ (800195c <HAL_ADC_ConvCpltCallback+0x1d4>)
 80018aa:	f023 031f 	bic.w	r3, r3, #31
 80018ae:	617b      	str	r3, [r7, #20]
 80018b0:	2320      	movs	r3, #32
 80018b2:	613b      	str	r3, [r7, #16]
    if ( dsize > 0 ) { 
 80018b4:	693b      	ldr	r3, [r7, #16]
 80018b6:	2b00      	cmp	r3, #0
 80018b8:	dd1d      	ble.n	80018f6 <HAL_ADC_ConvCpltCallback+0x16e>
       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
 80018ba:	697b      	ldr	r3, [r7, #20]
 80018bc:	f003 021f 	and.w	r2, r3, #31
 80018c0:	693b      	ldr	r3, [r7, #16]
 80018c2:	4413      	add	r3, r2
 80018c4:	60fb      	str	r3, [r7, #12]
      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
 80018c6:	697b      	ldr	r3, [r7, #20]
 80018c8:	60bb      	str	r3, [r7, #8]
  __ASM volatile ("dsb 0xF":::"memory");
 80018ca:	f3bf 8f4f 	dsb	sy
}
 80018ce:	bf00      	nop
        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
 80018d0:	4a1a      	ldr	r2, [pc, #104]	@ (800193c <HAL_ADC_ConvCpltCallback+0x1b4>)
 80018d2:	68bb      	ldr	r3, [r7, #8]
 80018d4:	f8c2 325c 	str.w	r3, [r2, #604]	@ 0x25c
        op_addr += __SCB_DCACHE_LINE_SIZE;
 80018d8:	68bb      	ldr	r3, [r7, #8]
 80018da:	3320      	adds	r3, #32
 80018dc:	60bb      	str	r3, [r7, #8]
        op_size -= __SCB_DCACHE_LINE_SIZE;
 80018de:	68fb      	ldr	r3, [r7, #12]
 80018e0:	3b20      	subs	r3, #32
 80018e2:	60fb      	str	r3, [r7, #12]
      } while ( op_size > 0 );
 80018e4:	68fb      	ldr	r3, [r7, #12]
 80018e6:	2b00      	cmp	r3, #0
 80018e8:	dcf2      	bgt.n	80018d0 <HAL_ADC_ConvCpltCallback+0x148>
  __ASM volatile ("dsb 0xF":::"memory");
 80018ea:	f3bf 8f4f 	dsb	sy
}
 80018ee:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 80018f0:	f3bf 8f6f 	isb	sy
}
 80018f4:	bf00      	nop
}
 80018f6:	bf00      	nop
		if(adc3MeasDataQueue != NULL)
 80018f8:	4b19      	ldr	r3, [pc, #100]	@ (8001960 <HAL_ADC_ConvCpltCallback+0x1d8>)
 80018fa:	681b      	ldr	r3, [r3, #0]
 80018fc:	2b00      	cmp	r3, #0
 80018fe:	d006      	beq.n	800190e <HAL_ADC_ConvCpltCallback+0x186>
		{
			osMessageQueuePut(adc3MeasDataQueue, &adc3Data, 0, 0);
 8001900:	4b17      	ldr	r3, [pc, #92]	@ (8001960 <HAL_ADC_ConvCpltCallback+0x1d8>)
 8001902:	6818      	ldr	r0, [r3, #0]
 8001904:	2300      	movs	r3, #0
 8001906:	2200      	movs	r2, #0
 8001908:	4914      	ldr	r1, [pc, #80]	@ (800195c <HAL_ADC_ConvCpltCallback+0x1d4>)
 800190a:	f012 fa0f 	bl	8013d2c <osMessageQueuePut>
		}
		if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK)
 800190e:	2205      	movs	r2, #5
 8001910:	4912      	ldr	r1, [pc, #72]	@ (800195c <HAL_ADC_ConvCpltCallback+0x1d4>)
 8001912:	4814      	ldr	r0, [pc, #80]	@ (8001964 <HAL_ADC_ConvCpltCallback+0x1dc>)
 8001914:	f004 f994 	bl	8005c40 <HAL_ADC_Start_DMA>
 8001918:	4603      	mov	r3, r0
 800191a:	2b00      	cmp	r3, #0
 800191c:	d001      	beq.n	8001922 <HAL_ADC_ConvCpltCallback+0x19a>
		{
		  Error_Handler();
 800191e:	f000 fa8d 	bl	8001e3c <Error_Handler>
		}
	}osTimerStop (debugLedTimerHandle);
 8001922:	4b11      	ldr	r3, [pc, #68]	@ (8001968 <HAL_ADC_ConvCpltCallback+0x1e0>)
 8001924:	681b      	ldr	r3, [r3, #0]
 8001926:	4618      	mov	r0, r3
 8001928:	f012 f848 	bl	80139bc <osTimerStop>
}
 800192c:	bf00      	nop
 800192e:	3738      	adds	r7, #56	@ 0x38
 8001930:	46bd      	mov	sp, r7
 8001932:	bd80      	pop	{r7, pc}
 8001934:	40022000 	.word	0x40022000
 8001938:	240000e0 	.word	0x240000e0
 800193c:	e000ed00 	.word	0xe000ed00
 8001940:	240007c8 	.word	0x240007c8
 8001944:	24000140 	.word	0x24000140
 8001948:	40022100 	.word	0x40022100
 800194c:	24000100 	.word	0x24000100
 8001950:	240007cc 	.word	0x240007cc
 8001954:	240001a4 	.word	0x240001a4
 8001958:	58026000 	.word	0x58026000
 800195c:	24000120 	.word	0x24000120
 8001960:	240007d0 	.word	0x240007d0
 8001964:	24000208 	.word	0x24000208
 8001968:	240006a8 	.word	0x240006a8

0800196c <HAL_TIM_IC_CaptureCallback>:

void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
 800196c:	b580      	push	{r7, lr}
 800196e:	b084      	sub	sp, #16
 8001970:	af00      	add	r7, sp, #0
 8001972:	6078      	str	r0, [r7, #4]
	if (htim->Instance == TIM4)
 8001974:	687b      	ldr	r3, [r7, #4]
 8001976:	681b      	ldr	r3, [r3, #0]
 8001978:	4a42      	ldr	r2, [pc, #264]	@ (8001a84 <HAL_TIM_IC_CaptureCallback+0x118>)
 800197a:	4293      	cmp	r3, r2
 800197c:	d13c      	bne.n	80019f8 <HAL_TIM_IC_CaptureCallback+0x8c>
	{
		if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3)
 800197e:	687b      	ldr	r3, [r7, #4]
 8001980:	7f1b      	ldrb	r3, [r3, #28]
 8001982:	2b04      	cmp	r3, #4
 8001984:	d108      	bne.n	8001998 <HAL_TIM_IC_CaptureCallback+0x2c>
		{
			encoderXChannelA = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3);
 8001986:	2108      	movs	r1, #8
 8001988:	6878      	ldr	r0, [r7, #4]
 800198a:	f00e f899 	bl	800fac0 <HAL_TIM_ReadCapturedValue>
 800198e:	4603      	mov	r3, r0
 8001990:	461a      	mov	r2, r3
 8001992:	4b3d      	ldr	r3, [pc, #244]	@ (8001a88 <HAL_TIM_IC_CaptureCallback+0x11c>)
 8001994:	601a      	str	r2, [r3, #0]
 8001996:	e00b      	b.n	80019b0 <HAL_TIM_IC_CaptureCallback+0x44>
		} else if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4)
 8001998:	687b      	ldr	r3, [r7, #4]
 800199a:	7f1b      	ldrb	r3, [r3, #28]
 800199c:	2b08      	cmp	r3, #8
 800199e:	d107      	bne.n	80019b0 <HAL_TIM_IC_CaptureCallback+0x44>
		{
			encoderXChannelB = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4);
 80019a0:	210c      	movs	r1, #12
 80019a2:	6878      	ldr	r0, [r7, #4]
 80019a4:	f00e f88c 	bl	800fac0 <HAL_TIM_ReadCapturedValue>
 80019a8:	4603      	mov	r3, r0
 80019aa:	461a      	mov	r2, r3
 80019ac:	4b37      	ldr	r3, [pc, #220]	@ (8001a8c <HAL_TIM_IC_CaptureCallback+0x120>)
 80019ae:	601a      	str	r2, [r3, #0]
		}
		if((encoderXChannelA != 0) && (encoderXChannelB != 0))
 80019b0:	4b35      	ldr	r3, [pc, #212]	@ (8001a88 <HAL_TIM_IC_CaptureCallback+0x11c>)
 80019b2:	681b      	ldr	r3, [r3, #0]
 80019b4:	2b00      	cmp	r3, #0
 80019b6:	d060      	beq.n	8001a7a <HAL_TIM_IC_CaptureCallback+0x10e>
 80019b8:	4b34      	ldr	r3, [pc, #208]	@ (8001a8c <HAL_TIM_IC_CaptureCallback+0x120>)
 80019ba:	681b      	ldr	r3, [r3, #0]
 80019bc:	2b00      	cmp	r3, #0
 80019be:	d05c      	beq.n	8001a7a <HAL_TIM_IC_CaptureCallback+0x10e>
		{
			EncoderData encoderData = { 0 };
 80019c0:	2300      	movs	r3, #0
 80019c2:	81bb      	strh	r3, [r7, #12]
			encoderData.axe = encoderAxeX;
 80019c4:	2300      	movs	r3, #0
 80019c6:	733b      	strb	r3, [r7, #12]
			encoderData.direction = encoderXChannelA - encoderXChannelB < 0 ? encoderCW : encoderCCW;
 80019c8:	4b2f      	ldr	r3, [pc, #188]	@ (8001a88 <HAL_TIM_IC_CaptureCallback+0x11c>)
 80019ca:	681a      	ldr	r2, [r3, #0]
 80019cc:	4b2f      	ldr	r3, [pc, #188]	@ (8001a8c <HAL_TIM_IC_CaptureCallback+0x120>)
 80019ce:	681b      	ldr	r3, [r3, #0]
 80019d0:	1ad3      	subs	r3, r2, r3
 80019d2:	43db      	mvns	r3, r3
 80019d4:	0fdb      	lsrs	r3, r3, #31
 80019d6:	b2db      	uxtb	r3, r3
 80019d8:	737b      	strb	r3, [r7, #13]
			osMessageQueuePut(encoderXDataQueue, &encoderData, 0, 0);
 80019da:	4b2d      	ldr	r3, [pc, #180]	@ (8001a90 <HAL_TIM_IC_CaptureCallback+0x124>)
 80019dc:	6818      	ldr	r0, [r3, #0]
 80019de:	f107 010c 	add.w	r1, r7, #12
 80019e2:	2300      	movs	r3, #0
 80019e4:	2200      	movs	r2, #0
 80019e6:	f012 f9a1 	bl	8013d2c <osMessageQueuePut>
			encoderXChannelA = 0;
 80019ea:	4b27      	ldr	r3, [pc, #156]	@ (8001a88 <HAL_TIM_IC_CaptureCallback+0x11c>)
 80019ec:	2200      	movs	r2, #0
 80019ee:	601a      	str	r2, [r3, #0]
			encoderXChannelB = 0;
 80019f0:	4b26      	ldr	r3, [pc, #152]	@ (8001a8c <HAL_TIM_IC_CaptureCallback+0x120>)
 80019f2:	2200      	movs	r2, #0
 80019f4:	601a      	str	r2, [r3, #0]
			osMessageQueuePut(encoderYDataQueue, &encoderData, 0, 0);
			encoderYChannelA = 0;
			encoderYChannelB = 0;
		}
	}
}
 80019f6:	e040      	b.n	8001a7a <HAL_TIM_IC_CaptureCallback+0x10e>
	} else if (htim->Instance == TIM2)
 80019f8:	687b      	ldr	r3, [r7, #4]
 80019fa:	681b      	ldr	r3, [r3, #0]
 80019fc:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8001a00:	d13b      	bne.n	8001a7a <HAL_TIM_IC_CaptureCallback+0x10e>
		if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3)
 8001a02:	687b      	ldr	r3, [r7, #4]
 8001a04:	7f1b      	ldrb	r3, [r3, #28]
 8001a06:	2b04      	cmp	r3, #4
 8001a08:	d108      	bne.n	8001a1c <HAL_TIM_IC_CaptureCallback+0xb0>
			encoderYChannelA = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3);
 8001a0a:	2108      	movs	r1, #8
 8001a0c:	6878      	ldr	r0, [r7, #4]
 8001a0e:	f00e f857 	bl	800fac0 <HAL_TIM_ReadCapturedValue>
 8001a12:	4603      	mov	r3, r0
 8001a14:	461a      	mov	r2, r3
 8001a16:	4b1f      	ldr	r3, [pc, #124]	@ (8001a94 <HAL_TIM_IC_CaptureCallback+0x128>)
 8001a18:	601a      	str	r2, [r3, #0]
 8001a1a:	e00b      	b.n	8001a34 <HAL_TIM_IC_CaptureCallback+0xc8>
		} else if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4)
 8001a1c:	687b      	ldr	r3, [r7, #4]
 8001a1e:	7f1b      	ldrb	r3, [r3, #28]
 8001a20:	2b08      	cmp	r3, #8
 8001a22:	d107      	bne.n	8001a34 <HAL_TIM_IC_CaptureCallback+0xc8>
			encoderYChannelB = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4);
 8001a24:	210c      	movs	r1, #12
 8001a26:	6878      	ldr	r0, [r7, #4]
 8001a28:	f00e f84a 	bl	800fac0 <HAL_TIM_ReadCapturedValue>
 8001a2c:	4603      	mov	r3, r0
 8001a2e:	461a      	mov	r2, r3
 8001a30:	4b19      	ldr	r3, [pc, #100]	@ (8001a98 <HAL_TIM_IC_CaptureCallback+0x12c>)
 8001a32:	601a      	str	r2, [r3, #0]
		if((encoderYChannelA != 0) && (encoderYChannelB != 0))
 8001a34:	4b17      	ldr	r3, [pc, #92]	@ (8001a94 <HAL_TIM_IC_CaptureCallback+0x128>)
 8001a36:	681b      	ldr	r3, [r3, #0]
 8001a38:	2b00      	cmp	r3, #0
 8001a3a:	d01e      	beq.n	8001a7a <HAL_TIM_IC_CaptureCallback+0x10e>
 8001a3c:	4b16      	ldr	r3, [pc, #88]	@ (8001a98 <HAL_TIM_IC_CaptureCallback+0x12c>)
 8001a3e:	681b      	ldr	r3, [r3, #0]
 8001a40:	2b00      	cmp	r3, #0
 8001a42:	d01a      	beq.n	8001a7a <HAL_TIM_IC_CaptureCallback+0x10e>
			EncoderData encoderData = { 0 };
 8001a44:	2300      	movs	r3, #0
 8001a46:	813b      	strh	r3, [r7, #8]
			encoderData.axe = encoderAxeY;
 8001a48:	2301      	movs	r3, #1
 8001a4a:	723b      	strb	r3, [r7, #8]
			encoderData.direction = encoderYChannelA - encoderYChannelB < 0 ? encoderCW : encoderCCW;
 8001a4c:	4b11      	ldr	r3, [pc, #68]	@ (8001a94 <HAL_TIM_IC_CaptureCallback+0x128>)
 8001a4e:	681a      	ldr	r2, [r3, #0]
 8001a50:	4b11      	ldr	r3, [pc, #68]	@ (8001a98 <HAL_TIM_IC_CaptureCallback+0x12c>)
 8001a52:	681b      	ldr	r3, [r3, #0]
 8001a54:	1ad3      	subs	r3, r2, r3
 8001a56:	43db      	mvns	r3, r3
 8001a58:	0fdb      	lsrs	r3, r3, #31
 8001a5a:	b2db      	uxtb	r3, r3
 8001a5c:	727b      	strb	r3, [r7, #9]
			osMessageQueuePut(encoderYDataQueue, &encoderData, 0, 0);
 8001a5e:	4b0f      	ldr	r3, [pc, #60]	@ (8001a9c <HAL_TIM_IC_CaptureCallback+0x130>)
 8001a60:	6818      	ldr	r0, [r3, #0]
 8001a62:	f107 0108 	add.w	r1, r7, #8
 8001a66:	2300      	movs	r3, #0
 8001a68:	2200      	movs	r2, #0
 8001a6a:	f012 f95f 	bl	8013d2c <osMessageQueuePut>
			encoderYChannelA = 0;
 8001a6e:	4b09      	ldr	r3, [pc, #36]	@ (8001a94 <HAL_TIM_IC_CaptureCallback+0x128>)
 8001a70:	2200      	movs	r2, #0
 8001a72:	601a      	str	r2, [r3, #0]
			encoderYChannelB = 0;
 8001a74:	4b08      	ldr	r3, [pc, #32]	@ (8001a98 <HAL_TIM_IC_CaptureCallback+0x12c>)
 8001a76:	2200      	movs	r2, #0
 8001a78:	601a      	str	r2, [r3, #0]
}
 8001a7a:	bf00      	nop
 8001a7c:	3710      	adds	r7, #16
 8001a7e:	46bd      	mov	sp, r7
 8001a80:	bd80      	pop	{r7, pc}
 8001a82:	bf00      	nop
 8001a84:	40000800 	.word	0x40000800
 8001a88:	240007a0 	.word	0x240007a0
 8001a8c:	240007a4 	.word	0x240007a4
 8001a90:	240007d8 	.word	0x240007d8
 8001a94:	240007a8 	.word	0x240007a8
 8001a98:	240007ac 	.word	0x240007ac
 8001a9c:	240007dc 	.word	0x240007dc

08001aa0 <StartDefaultTask>:
  * @param  argument: Not used
  * @retval None
  */
/* USER CODE END Header_StartDefaultTask */
void StartDefaultTask(void *argument)
{
 8001aa0:	b580      	push	{r7, lr}
 8001aa2:	b082      	sub	sp, #8
 8001aa4:	af00      	add	r7, sp, #0
 8001aa6:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN 5 */
  SelectCurrentSensorGain(CurrentSensorL1, csGain3);
 8001aa8:	2102      	movs	r1, #2
 8001aaa:	2000      	movs	r0, #0
 8001aac:	f001 f96e 	bl	8002d8c <SelectCurrentSensorGain>
  SelectCurrentSensorGain(CurrentSensorL2, csGain3);
 8001ab0:	2102      	movs	r1, #2
 8001ab2:	2001      	movs	r0, #1
 8001ab4:	f001 f96a 	bl	8002d8c <SelectCurrentSensorGain>
  SelectCurrentSensorGain(CurrentSensorL3, csGain3);
 8001ab8:	2102      	movs	r1, #2
 8001aba:	2002      	movs	r0, #2
 8001abc:	f001 f966 	bl	8002d8c <SelectCurrentSensorGain>
  EnableCurrentSensors();
 8001ac0:	f001 f958 	bl	8002d74 <EnableCurrentSensors>
  osDelay(pdMS_TO_TICKS(1000));
 8001ac4:	f44f 707a 	mov.w	r0, #1000	@ 0x3e8
 8001ac8:	f011 fe9d 	bl	8013806 <osDelay>
  if(HAL_TIM_Base_Start(&htim2) != HAL_OK)
 8001acc:	484c      	ldr	r0, [pc, #304]	@ (8001c00 <StartDefaultTask+0x160>)
 8001ace:	f00c ffb1 	bl	800ea34 <HAL_TIM_Base_Start>
 8001ad2:	4603      	mov	r3, r0
 8001ad4:	2b00      	cmp	r3, #0
 8001ad6:	d001      	beq.n	8001adc <StartDefaultTask+0x3c>
  {
	  Error_Handler();
 8001ad8:	f000 f9b0 	bl	8001e3c <Error_Handler>
  }
  if(HAL_TIM_Base_Start_IT(&htim4) != HAL_OK)
 8001adc:	4849      	ldr	r0, [pc, #292]	@ (8001c04 <StartDefaultTask+0x164>)
 8001ade:	f00d f819 	bl	800eb14 <HAL_TIM_Base_Start_IT>
 8001ae2:	4603      	mov	r3, r0
 8001ae4:	2b00      	cmp	r3, #0
 8001ae6:	d001      	beq.n	8001aec <StartDefaultTask+0x4c>
  {
	  Error_Handler();
 8001ae8:	f000 f9a8 	bl	8001e3c <Error_Handler>
  }
  if(HAL_TIM_IC_Start_IT(&htim4, TIM_CHANNEL_3) != HAL_OK)
 8001aec:	2108      	movs	r1, #8
 8001aee:	4845      	ldr	r0, [pc, #276]	@ (8001c04 <StartDefaultTask+0x164>)
 8001af0:	f00d fae6 	bl	800f0c0 <HAL_TIM_IC_Start_IT>
 8001af4:	4603      	mov	r3, r0
 8001af6:	2b00      	cmp	r3, #0
 8001af8:	d001      	beq.n	8001afe <StartDefaultTask+0x5e>
  {
	  Error_Handler();
 8001afa:	f000 f99f 	bl	8001e3c <Error_Handler>
  }
  if(HAL_TIM_IC_Start_IT(&htim4, TIM_CHANNEL_4) != HAL_OK)
 8001afe:	210c      	movs	r1, #12
 8001b00:	4840      	ldr	r0, [pc, #256]	@ (8001c04 <StartDefaultTask+0x164>)
 8001b02:	f00d fadd 	bl	800f0c0 <HAL_TIM_IC_Start_IT>
 8001b06:	4603      	mov	r3, r0
 8001b08:	2b00      	cmp	r3, #0
 8001b0a:	d001      	beq.n	8001b10 <StartDefaultTask+0x70>
  {
	  Error_Handler();
 8001b0c:	f000 f996 	bl	8001e3c <Error_Handler>
  }
  if(HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_3) != HAL_OK)
 8001b10:	2108      	movs	r1, #8
 8001b12:	483b      	ldr	r0, [pc, #236]	@ (8001c00 <StartDefaultTask+0x160>)
 8001b14:	f00d fad4 	bl	800f0c0 <HAL_TIM_IC_Start_IT>
 8001b18:	4603      	mov	r3, r0
 8001b1a:	2b00      	cmp	r3, #0
 8001b1c:	d001      	beq.n	8001b22 <StartDefaultTask+0x82>
  {
	  Error_Handler();
 8001b1e:	f000 f98d 	bl	8001e3c <Error_Handler>
  }
  if(HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_4) != HAL_OK)
 8001b22:	210c      	movs	r1, #12
 8001b24:	4836      	ldr	r0, [pc, #216]	@ (8001c00 <StartDefaultTask+0x160>)
 8001b26:	f00d facb 	bl	800f0c0 <HAL_TIM_IC_Start_IT>
 8001b2a:	4603      	mov	r3, r0
 8001b2c:	2b00      	cmp	r3, #0
 8001b2e:	d001      	beq.n	8001b34 <StartDefaultTask+0x94>
  {
	  Error_Handler();
 8001b30:	f000 f984 	bl	8001e3c <Error_Handler>
  }
  if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK)
 8001b34:	2207      	movs	r2, #7
 8001b36:	4934      	ldr	r1, [pc, #208]	@ (8001c08 <StartDefaultTask+0x168>)
 8001b38:	4834      	ldr	r0, [pc, #208]	@ (8001c0c <StartDefaultTask+0x16c>)
 8001b3a:	f004 f881 	bl	8005c40 <HAL_ADC_Start_DMA>
 8001b3e:	4603      	mov	r3, r0
 8001b40:	2b00      	cmp	r3, #0
 8001b42:	d001      	beq.n	8001b48 <StartDefaultTask+0xa8>
  {
	  Error_Handler();
 8001b44:	f000 f97a 	bl	8001e3c <Error_Handler>
  }
  if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK)
 8001b48:	2203      	movs	r2, #3
 8001b4a:	4931      	ldr	r1, [pc, #196]	@ (8001c10 <StartDefaultTask+0x170>)
 8001b4c:	4831      	ldr	r0, [pc, #196]	@ (8001c14 <StartDefaultTask+0x174>)
 8001b4e:	f004 f877 	bl	8005c40 <HAL_ADC_Start_DMA>
 8001b52:	4603      	mov	r3, r0
 8001b54:	2b00      	cmp	r3, #0
 8001b56:	d001      	beq.n	8001b5c <StartDefaultTask+0xbc>
  {
	  Error_Handler();
 8001b58:	f000 f970 	bl	8001e3c <Error_Handler>
  }
  if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK)
 8001b5c:	2205      	movs	r2, #5
 8001b5e:	492e      	ldr	r1, [pc, #184]	@ (8001c18 <StartDefaultTask+0x178>)
 8001b60:	482e      	ldr	r0, [pc, #184]	@ (8001c1c <StartDefaultTask+0x17c>)
 8001b62:	f004 f86d 	bl	8005c40 <HAL_ADC_Start_DMA>
 8001b66:	4603      	mov	r3, r0
 8001b68:	2b00      	cmp	r3, #0
 8001b6a:	d001      	beq.n	8001b70 <StartDefaultTask+0xd0>
  {
	  Error_Handler();
 8001b6c:	f000 f966 	bl	8001e3c <Error_Handler>
  }
  HAL_COMP_Start(&hcomp1);
 8001b70:	482b      	ldr	r0, [pc, #172]	@ (8001c20 <StartDefaultTask+0x180>)
 8001b72:	f005 f9e9 	bl	8006f48 <HAL_COMP_Start>
  /* Infinite loop */
  for(;;)
  {
	 osDelay(pdMS_TO_TICKS(100));
 8001b76:	2064      	movs	r0, #100	@ 0x64
 8001b78:	f011 fe45 	bl	8013806 <osDelay>
	 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY &&
 8001b7c:	2100      	movs	r1, #0
 8001b7e:	4829      	ldr	r0, [pc, #164]	@ (8001c24 <StartDefaultTask+0x184>)
 8001b80:	f00e f800 	bl	800fb84 <HAL_TIM_GetChannelState>
 8001b84:	4603      	mov	r3, r0
 8001b86:	2b01      	cmp	r3, #1
 8001b88:	d118      	bne.n	8001bbc <StartDefaultTask+0x11c>
			 HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_2) == HAL_TIM_CHANNEL_STATE_READY)
 8001b8a:	2104      	movs	r1, #4
 8001b8c:	4825      	ldr	r0, [pc, #148]	@ (8001c24 <StartDefaultTask+0x184>)
 8001b8e:	f00d fff9 	bl	800fb84 <HAL_TIM_GetChannelState>
 8001b92:	4603      	mov	r3, r0
	 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY &&
 8001b94:	2b01      	cmp	r3, #1
 8001b96:	d111      	bne.n	8001bbc <StartDefaultTask+0x11c>
	 {
		if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK)
 8001b98:	4b23      	ldr	r3, [pc, #140]	@ (8001c28 <StartDefaultTask+0x188>)
 8001b9a:	681b      	ldr	r3, [r3, #0]
 8001b9c:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8001ba0:	4618      	mov	r0, r3
 8001ba2:	f011 ffc8 	bl	8013b36 <osMutexAcquire>
 8001ba6:	4603      	mov	r3, r0
 8001ba8:	2b00      	cmp	r3, #0
 8001baa:	d107      	bne.n	8001bbc <StartDefaultTask+0x11c>
		{
			sensorsInfo.motorXStatus = 0;
 8001bac:	4b1f      	ldr	r3, [pc, #124]	@ (8001c2c <StartDefaultTask+0x18c>)
 8001bae:	2200      	movs	r2, #0
 8001bb0:	751a      	strb	r2, [r3, #20]
			osMutexRelease(sensorsInfoMutex);
 8001bb2:	4b1d      	ldr	r3, [pc, #116]	@ (8001c28 <StartDefaultTask+0x188>)
 8001bb4:	681b      	ldr	r3, [r3, #0]
 8001bb6:	4618      	mov	r0, r3
 8001bb8:	f012 f808 	bl	8013bcc <osMutexRelease>
		}
	 }
	 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY &&
 8001bbc:	2108      	movs	r1, #8
 8001bbe:	4819      	ldr	r0, [pc, #100]	@ (8001c24 <StartDefaultTask+0x184>)
 8001bc0:	f00d ffe0 	bl	800fb84 <HAL_TIM_GetChannelState>
 8001bc4:	4603      	mov	r3, r0
 8001bc6:	2b01      	cmp	r3, #1
 8001bc8:	d1d5      	bne.n	8001b76 <StartDefaultTask+0xd6>
			 HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_4) == HAL_TIM_CHANNEL_STATE_READY)
 8001bca:	210c      	movs	r1, #12
 8001bcc:	4815      	ldr	r0, [pc, #84]	@ (8001c24 <StartDefaultTask+0x184>)
 8001bce:	f00d ffd9 	bl	800fb84 <HAL_TIM_GetChannelState>
 8001bd2:	4603      	mov	r3, r0
	 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY &&
 8001bd4:	2b01      	cmp	r3, #1
 8001bd6:	d1ce      	bne.n	8001b76 <StartDefaultTask+0xd6>
	 {
		if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK)
 8001bd8:	4b13      	ldr	r3, [pc, #76]	@ (8001c28 <StartDefaultTask+0x188>)
 8001bda:	681b      	ldr	r3, [r3, #0]
 8001bdc:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8001be0:	4618      	mov	r0, r3
 8001be2:	f011 ffa8 	bl	8013b36 <osMutexAcquire>
 8001be6:	4603      	mov	r3, r0
 8001be8:	2b00      	cmp	r3, #0
 8001bea:	d1c4      	bne.n	8001b76 <StartDefaultTask+0xd6>
		{
			sensorsInfo.motorYStatus = 0;
 8001bec:	4b0f      	ldr	r3, [pc, #60]	@ (8001c2c <StartDefaultTask+0x18c>)
 8001bee:	2200      	movs	r2, #0
 8001bf0:	755a      	strb	r2, [r3, #21]
			osMutexRelease(sensorsInfoMutex);
 8001bf2:	4b0d      	ldr	r3, [pc, #52]	@ (8001c28 <StartDefaultTask+0x188>)
 8001bf4:	681b      	ldr	r3, [r3, #0]
 8001bf6:	4618      	mov	r0, r3
 8001bf8:	f011 ffe8 	bl	8013bcc <osMutexRelease>
	 osDelay(pdMS_TO_TICKS(100));
 8001bfc:	e7bb      	b.n	8001b76 <StartDefaultTask+0xd6>
 8001bfe:	bf00      	nop
 8001c00:	24000498 	.word	0x24000498
 8001c04:	24000530 	.word	0x24000530
 8001c08:	240000e0 	.word	0x240000e0
 8001c0c:	24000140 	.word	0x24000140
 8001c10:	24000100 	.word	0x24000100
 8001c14:	240001a4 	.word	0x240001a4
 8001c18:	24000120 	.word	0x24000120
 8001c1c:	24000208 	.word	0x24000208
 8001c20:	240003d4 	.word	0x240003d4
 8001c24:	240004e4 	.word	0x240004e4
 8001c28:	240007e8 	.word	0x240007e8
 8001c2c:	2400082c 	.word	0x2400082c

08001c30 <debugLedTimerCallback>:
  /* USER CODE END 5 */
}

/* debugLedTimerCallback function */
void debugLedTimerCallback(void *argument)
{
 8001c30:	b580      	push	{r7, lr}
 8001c32:	b082      	sub	sp, #8
 8001c34:	af00      	add	r7, sp, #0
 8001c36:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN debugLedTimerCallback */
  DbgLEDOff (DBG_LED1);
 8001c38:	2010      	movs	r0, #16
 8001c3a:	f001 f877 	bl	8002d2c <DbgLEDOff>
  /* USER CODE END debugLedTimerCallback */
}
 8001c3e:	bf00      	nop
 8001c40:	3708      	adds	r7, #8
 8001c42:	46bd      	mov	sp, r7
 8001c44:	bd80      	pop	{r7, pc}
	...

08001c48 <fanTimerCallback>:

/* fanTimerCallback function */
void fanTimerCallback(void *argument)
{
 8001c48:	b580      	push	{r7, lr}
 8001c4a:	b082      	sub	sp, #8
 8001c4c:	af00      	add	r7, sp, #0
 8001c4e:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN fanTimerCallback */
	HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_2);
 8001c50:	2104      	movs	r1, #4
 8001c52:	4803      	ldr	r0, [pc, #12]	@ (8001c60 <fanTimerCallback+0x18>)
 8001c54:	f00d f93c 	bl	800eed0 <HAL_TIM_PWM_Stop>
  /* USER CODE END fanTimerCallback */
}
 8001c58:	bf00      	nop
 8001c5a:	3708      	adds	r7, #8
 8001c5c:	46bd      	mov	sp, r7
 8001c5e:	bd80      	pop	{r7, pc}
 8001c60:	2400044c 	.word	0x2400044c

08001c64 <motorXTimerCallback>:

/* motorXTimerCallback function */
void motorXTimerCallback(void *argument)
{
 8001c64:	b580      	push	{r7, lr}
 8001c66:	b084      	sub	sp, #16
 8001c68:	af02      	add	r7, sp, #8
 8001c6a:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN motorXTimerCallback */
	motorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0);
 8001c6c:	2300      	movs	r3, #0
 8001c6e:	9301      	str	r3, [sp, #4]
 8001c70:	2300      	movs	r3, #0
 8001c72:	9300      	str	r3, [sp, #0]
 8001c74:	2304      	movs	r3, #4
 8001c76:	2200      	movs	r2, #0
 8001c78:	4907      	ldr	r1, [pc, #28]	@ (8001c98 <motorXTimerCallback+0x34>)
 8001c7a:	4808      	ldr	r0, [pc, #32]	@ (8001c9c <motorXTimerCallback+0x38>)
 8001c7c:	f001 fa0b 	bl	8003096 <motorAction>
	HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1);
 8001c80:	2100      	movs	r1, #0
 8001c82:	4806      	ldr	r0, [pc, #24]	@ (8001c9c <motorXTimerCallback+0x38>)
 8001c84:	f00d f924 	bl	800eed0 <HAL_TIM_PWM_Stop>
	HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2);
 8001c88:	2104      	movs	r1, #4
 8001c8a:	4804      	ldr	r0, [pc, #16]	@ (8001c9c <motorXTimerCallback+0x38>)
 8001c8c:	f00d f920 	bl	800eed0 <HAL_TIM_PWM_Stop>
  /* USER CODE END motorXTimerCallback */
}
 8001c90:	bf00      	nop
 8001c92:	3708      	adds	r7, #8
 8001c94:	46bd      	mov	sp, r7
 8001c96:	bd80      	pop	{r7, pc}
 8001c98:	24000784 	.word	0x24000784
 8001c9c:	240004e4 	.word	0x240004e4

08001ca0 <motorYTimerCallback>:

/* motorYTimerCallback function */
void motorYTimerCallback(void *argument)
{
 8001ca0:	b580      	push	{r7, lr}
 8001ca2:	b084      	sub	sp, #16
 8001ca4:	af02      	add	r7, sp, #8
 8001ca6:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN motorYTimerCallback */
	motorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0);
 8001ca8:	2300      	movs	r3, #0
 8001caa:	9301      	str	r3, [sp, #4]
 8001cac:	2300      	movs	r3, #0
 8001cae:	9300      	str	r3, [sp, #0]
 8001cb0:	230c      	movs	r3, #12
 8001cb2:	2208      	movs	r2, #8
 8001cb4:	4907      	ldr	r1, [pc, #28]	@ (8001cd4 <motorYTimerCallback+0x34>)
 8001cb6:	4808      	ldr	r0, [pc, #32]	@ (8001cd8 <motorYTimerCallback+0x38>)
 8001cb8:	f001 f9ed 	bl	8003096 <motorAction>
	HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_3);
 8001cbc:	2108      	movs	r1, #8
 8001cbe:	4806      	ldr	r0, [pc, #24]	@ (8001cd8 <motorYTimerCallback+0x38>)
 8001cc0:	f00d f906 	bl	800eed0 <HAL_TIM_PWM_Stop>
	HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4);
 8001cc4:	210c      	movs	r1, #12
 8001cc6:	4804      	ldr	r0, [pc, #16]	@ (8001cd8 <motorYTimerCallback+0x38>)
 8001cc8:	f00d f902 	bl	800eed0 <HAL_TIM_PWM_Stop>
  /* USER CODE END motorYTimerCallback */
}
 8001ccc:	bf00      	nop
 8001cce:	3708      	adds	r7, #8
 8001cd0:	46bd      	mov	sp, r7
 8001cd2:	bd80      	pop	{r7, pc}
 8001cd4:	24000784 	.word	0x24000784
 8001cd8:	240004e4 	.word	0x240004e4

08001cdc <MPU_Config>:

 /* MPU Configuration */

void MPU_Config(void)
{
 8001cdc:	b580      	push	{r7, lr}
 8001cde:	b084      	sub	sp, #16
 8001ce0:	af00      	add	r7, sp, #0
  MPU_Region_InitTypeDef MPU_InitStruct = {0};
 8001ce2:	463b      	mov	r3, r7
 8001ce4:	2200      	movs	r2, #0
 8001ce6:	601a      	str	r2, [r3, #0]
 8001ce8:	605a      	str	r2, [r3, #4]
 8001cea:	609a      	str	r2, [r3, #8]
 8001cec:	60da      	str	r2, [r3, #12]

  /* Disables the MPU */
  HAL_MPU_Disable();
 8001cee:	f005 fa73 	bl	80071d8 <HAL_MPU_Disable>

  /** Initializes and configures the Region and the memory to be protected
  */
  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
 8001cf2:	2301      	movs	r3, #1
 8001cf4:	703b      	strb	r3, [r7, #0]
  MPU_InitStruct.Number = MPU_REGION_NUMBER0;
 8001cf6:	2300      	movs	r3, #0
 8001cf8:	707b      	strb	r3, [r7, #1]
  MPU_InitStruct.BaseAddress = 0x0;
 8001cfa:	2300      	movs	r3, #0
 8001cfc:	607b      	str	r3, [r7, #4]
  MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
 8001cfe:	231f      	movs	r3, #31
 8001d00:	723b      	strb	r3, [r7, #8]
  MPU_InitStruct.SubRegionDisable = 0x87;
 8001d02:	2387      	movs	r3, #135	@ 0x87
 8001d04:	727b      	strb	r3, [r7, #9]
  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
 8001d06:	2300      	movs	r3, #0
 8001d08:	72bb      	strb	r3, [r7, #10]
  MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
 8001d0a:	2300      	movs	r3, #0
 8001d0c:	72fb      	strb	r3, [r7, #11]
  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
 8001d0e:	2301      	movs	r3, #1
 8001d10:	733b      	strb	r3, [r7, #12]
  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
 8001d12:	2301      	movs	r3, #1
 8001d14:	737b      	strb	r3, [r7, #13]
  MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
 8001d16:	2300      	movs	r3, #0
 8001d18:	73bb      	strb	r3, [r7, #14]
  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
 8001d1a:	2300      	movs	r3, #0
 8001d1c:	73fb      	strb	r3, [r7, #15]

  HAL_MPU_ConfigRegion(&MPU_InitStruct);
 8001d1e:	463b      	mov	r3, r7
 8001d20:	4618      	mov	r0, r3
 8001d22:	f005 fa91 	bl	8007248 <HAL_MPU_ConfigRegion>

  /** Initializes and configures the Region and the memory to be protected
  */
  MPU_InitStruct.Number = MPU_REGION_NUMBER1;
 8001d26:	2301      	movs	r3, #1
 8001d28:	707b      	strb	r3, [r7, #1]
  MPU_InitStruct.BaseAddress = 0x24020000;
 8001d2a:	4b13      	ldr	r3, [pc, #76]	@ (8001d78 <MPU_Config+0x9c>)
 8001d2c:	607b      	str	r3, [r7, #4]
  MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
 8001d2e:	2310      	movs	r3, #16
 8001d30:	723b      	strb	r3, [r7, #8]
  MPU_InitStruct.SubRegionDisable = 0x0;
 8001d32:	2300      	movs	r3, #0
 8001d34:	727b      	strb	r3, [r7, #9]
  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
 8001d36:	2301      	movs	r3, #1
 8001d38:	72bb      	strb	r3, [r7, #10]
  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
 8001d3a:	2303      	movs	r3, #3
 8001d3c:	72fb      	strb	r3, [r7, #11]
  MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
 8001d3e:	2300      	movs	r3, #0
 8001d40:	737b      	strb	r3, [r7, #13]

  HAL_MPU_ConfigRegion(&MPU_InitStruct);
 8001d42:	463b      	mov	r3, r7
 8001d44:	4618      	mov	r0, r3
 8001d46:	f005 fa7f 	bl	8007248 <HAL_MPU_ConfigRegion>

  /** Initializes and configures the Region and the memory to be protected
  */
  MPU_InitStruct.Number = MPU_REGION_NUMBER2;
 8001d4a:	2302      	movs	r3, #2
 8001d4c:	707b      	strb	r3, [r7, #1]
  MPU_InitStruct.BaseAddress = 0x24040000;
 8001d4e:	4b0b      	ldr	r3, [pc, #44]	@ (8001d7c <MPU_Config+0xa0>)
 8001d50:	607b      	str	r3, [r7, #4]
  MPU_InitStruct.Size = MPU_REGION_SIZE_512B;
 8001d52:	2308      	movs	r3, #8
 8001d54:	723b      	strb	r3, [r7, #8]
  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
 8001d56:	2300      	movs	r3, #0
 8001d58:	72bb      	strb	r3, [r7, #10]
  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
 8001d5a:	2301      	movs	r3, #1
 8001d5c:	737b      	strb	r3, [r7, #13]
  MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
 8001d5e:	2301      	movs	r3, #1
 8001d60:	73fb      	strb	r3, [r7, #15]

  HAL_MPU_ConfigRegion(&MPU_InitStruct);
 8001d62:	463b      	mov	r3, r7
 8001d64:	4618      	mov	r0, r3
 8001d66:	f005 fa6f 	bl	8007248 <HAL_MPU_ConfigRegion>
  /* Enables the MPU */
  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
 8001d6a:	2004      	movs	r0, #4
 8001d6c:	f005 fa4c 	bl	8007208 <HAL_MPU_Enable>

}
 8001d70:	bf00      	nop
 8001d72:	3710      	adds	r7, #16
 8001d74:	46bd      	mov	sp, r7
 8001d76:	bd80      	pop	{r7, pc}
 8001d78:	24020000 	.word	0x24020000
 8001d7c:	24040000 	.word	0x24040000

08001d80 <HAL_TIM_PeriodElapsedCallback>:
  * a global variable "uwTick" used as application time base.
  * @param  htim : TIM handle
  * @retval None
  */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
 8001d80:	b580      	push	{r7, lr}
 8001d82:	b082      	sub	sp, #8
 8001d84:	af00      	add	r7, sp, #0
 8001d86:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN Callback 0 */

  /* USER CODE END Callback 0 */
  if (htim->Instance == TIM6) {
 8001d88:	687b      	ldr	r3, [r7, #4]
 8001d8a:	681b      	ldr	r3, [r3, #0]
 8001d8c:	4a25      	ldr	r2, [pc, #148]	@ (8001e24 <HAL_TIM_PeriodElapsedCallback+0xa4>)
 8001d8e:	4293      	cmp	r3, r2
 8001d90:	d102      	bne.n	8001d98 <HAL_TIM_PeriodElapsedCallback+0x18>
    HAL_IncTick();
 8001d92:	f003 fb3f 	bl	8005414 <HAL_IncTick>
		  encoderYChannelA += htim->Instance->ARR;
	  }
  }

  /* USER CODE END Callback 1 */
}
 8001d96:	e040      	b.n	8001e1a <HAL_TIM_PeriodElapsedCallback+0x9a>
  else if (htim->Instance == TIM4)
 8001d98:	687b      	ldr	r3, [r7, #4]
 8001d9a:	681b      	ldr	r3, [r3, #0]
 8001d9c:	4a22      	ldr	r2, [pc, #136]	@ (8001e28 <HAL_TIM_PeriodElapsedCallback+0xa8>)
 8001d9e:	4293      	cmp	r3, r2
 8001da0:	d11b      	bne.n	8001dda <HAL_TIM_PeriodElapsedCallback+0x5a>
	  if(encoderXChannelA > 0)
 8001da2:	4b22      	ldr	r3, [pc, #136]	@ (8001e2c <HAL_TIM_PeriodElapsedCallback+0xac>)
 8001da4:	681b      	ldr	r3, [r3, #0]
 8001da6:	2b00      	cmp	r3, #0
 8001da8:	dd09      	ble.n	8001dbe <HAL_TIM_PeriodElapsedCallback+0x3e>
		  encoderXChannelB += htim->Instance->ARR;
 8001daa:	687b      	ldr	r3, [r7, #4]
 8001dac:	681b      	ldr	r3, [r3, #0]
 8001dae:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8001db0:	4a1f      	ldr	r2, [pc, #124]	@ (8001e30 <HAL_TIM_PeriodElapsedCallback+0xb0>)
 8001db2:	6812      	ldr	r2, [r2, #0]
 8001db4:	4413      	add	r3, r2
 8001db6:	461a      	mov	r2, r3
 8001db8:	4b1d      	ldr	r3, [pc, #116]	@ (8001e30 <HAL_TIM_PeriodElapsedCallback+0xb0>)
 8001dba:	601a      	str	r2, [r3, #0]
}
 8001dbc:	e02d      	b.n	8001e1a <HAL_TIM_PeriodElapsedCallback+0x9a>
	  } else if(encoderXChannelB > 0)
 8001dbe:	4b1c      	ldr	r3, [pc, #112]	@ (8001e30 <HAL_TIM_PeriodElapsedCallback+0xb0>)
 8001dc0:	681b      	ldr	r3, [r3, #0]
 8001dc2:	2b00      	cmp	r3, #0
 8001dc4:	dd29      	ble.n	8001e1a <HAL_TIM_PeriodElapsedCallback+0x9a>
		  encoderXChannelA += htim->Instance->ARR;
 8001dc6:	687b      	ldr	r3, [r7, #4]
 8001dc8:	681b      	ldr	r3, [r3, #0]
 8001dca:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8001dcc:	4a17      	ldr	r2, [pc, #92]	@ (8001e2c <HAL_TIM_PeriodElapsedCallback+0xac>)
 8001dce:	6812      	ldr	r2, [r2, #0]
 8001dd0:	4413      	add	r3, r2
 8001dd2:	461a      	mov	r2, r3
 8001dd4:	4b15      	ldr	r3, [pc, #84]	@ (8001e2c <HAL_TIM_PeriodElapsedCallback+0xac>)
 8001dd6:	601a      	str	r2, [r3, #0]
}
 8001dd8:	e01f      	b.n	8001e1a <HAL_TIM_PeriodElapsedCallback+0x9a>
  else if (htim->Instance == TIM2)
 8001dda:	687b      	ldr	r3, [r7, #4]
 8001ddc:	681b      	ldr	r3, [r3, #0]
 8001dde:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8001de2:	d11a      	bne.n	8001e1a <HAL_TIM_PeriodElapsedCallback+0x9a>
	  if(encoderYChannelA > 0)
 8001de4:	4b13      	ldr	r3, [pc, #76]	@ (8001e34 <HAL_TIM_PeriodElapsedCallback+0xb4>)
 8001de6:	681b      	ldr	r3, [r3, #0]
 8001de8:	2b00      	cmp	r3, #0
 8001dea:	dd09      	ble.n	8001e00 <HAL_TIM_PeriodElapsedCallback+0x80>
		  encoderYChannelB += htim->Instance->ARR;
 8001dec:	687b      	ldr	r3, [r7, #4]
 8001dee:	681b      	ldr	r3, [r3, #0]
 8001df0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8001df2:	4a11      	ldr	r2, [pc, #68]	@ (8001e38 <HAL_TIM_PeriodElapsedCallback+0xb8>)
 8001df4:	6812      	ldr	r2, [r2, #0]
 8001df6:	4413      	add	r3, r2
 8001df8:	461a      	mov	r2, r3
 8001dfa:	4b0f      	ldr	r3, [pc, #60]	@ (8001e38 <HAL_TIM_PeriodElapsedCallback+0xb8>)
 8001dfc:	601a      	str	r2, [r3, #0]
}
 8001dfe:	e00c      	b.n	8001e1a <HAL_TIM_PeriodElapsedCallback+0x9a>
	  } else if(encoderYChannelB > 0)
 8001e00:	4b0d      	ldr	r3, [pc, #52]	@ (8001e38 <HAL_TIM_PeriodElapsedCallback+0xb8>)
 8001e02:	681b      	ldr	r3, [r3, #0]
 8001e04:	2b00      	cmp	r3, #0
 8001e06:	dd08      	ble.n	8001e1a <HAL_TIM_PeriodElapsedCallback+0x9a>
		  encoderYChannelA += htim->Instance->ARR;
 8001e08:	687b      	ldr	r3, [r7, #4]
 8001e0a:	681b      	ldr	r3, [r3, #0]
 8001e0c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8001e0e:	4a09      	ldr	r2, [pc, #36]	@ (8001e34 <HAL_TIM_PeriodElapsedCallback+0xb4>)
 8001e10:	6812      	ldr	r2, [r2, #0]
 8001e12:	4413      	add	r3, r2
 8001e14:	461a      	mov	r2, r3
 8001e16:	4b07      	ldr	r3, [pc, #28]	@ (8001e34 <HAL_TIM_PeriodElapsedCallback+0xb4>)
 8001e18:	601a      	str	r2, [r3, #0]
}
 8001e1a:	bf00      	nop
 8001e1c:	3708      	adds	r7, #8
 8001e1e:	46bd      	mov	sp, r7
 8001e20:	bd80      	pop	{r7, pc}
 8001e22:	bf00      	nop
 8001e24:	40001000 	.word	0x40001000
 8001e28:	40000800 	.word	0x40000800
 8001e2c:	240007a0 	.word	0x240007a0
 8001e30:	240007a4 	.word	0x240007a4
 8001e34:	240007a8 	.word	0x240007a8
 8001e38:	240007ac 	.word	0x240007ac

08001e3c <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8001e3c:	b580      	push	{r7, lr}
 8001e3e:	af00      	add	r7, sp, #0
  __ASM volatile ("cpsid i" : : : "memory");
 8001e40:	b672      	cpsid	i
}
 8001e42:	bf00      	nop
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  NVIC_SystemReset();
 8001e44:	f7fe fc20 	bl	8000688 <__NVIC_SystemReset>

08001e48 <MeasTasksInit>:
extern TIM_OC_InitTypeDef motorXYTimerConfigOC;
extern osTimerId_t motorXTimerHandle;
extern osTimerId_t motorYTimerHandle;


void MeasTasksInit (void) {
 8001e48:	b580      	push	{r7, lr}
 8001e4a:	b0b6      	sub	sp, #216	@ 0xd8
 8001e4c:	af00      	add	r7, sp, #0
    vRefmVMutex          = osMutexNew (NULL);
 8001e4e:	2000      	movs	r0, #0
 8001e50:	f011 fdeb 	bl	8013a2a <osMutexNew>
 8001e54:	4603      	mov	r3, r0
 8001e56:	4a69      	ldr	r2, [pc, #420]	@ (8001ffc <MeasTasksInit+0x1b4>)
 8001e58:	6013      	str	r3, [r2, #0]
    resMeasurementsMutex = osMutexNew (NULL);
 8001e5a:	2000      	movs	r0, #0
 8001e5c:	f011 fde5 	bl	8013a2a <osMutexNew>
 8001e60:	4603      	mov	r3, r0
 8001e62:	4a67      	ldr	r2, [pc, #412]	@ (8002000 <MeasTasksInit+0x1b8>)
 8001e64:	6013      	str	r3, [r2, #0]
    sensorsInfoMutex     = osMutexNew (NULL);
 8001e66:	2000      	movs	r0, #0
 8001e68:	f011 fddf 	bl	8013a2a <osMutexNew>
 8001e6c:	4603      	mov	r3, r0
 8001e6e:	4a65      	ldr	r2, [pc, #404]	@ (8002004 <MeasTasksInit+0x1bc>)
 8001e70:	6013      	str	r3, [r2, #0]
    ILxRefMutex          = osMutexNew (NULL);
 8001e72:	2000      	movs	r0, #0
 8001e74:	f011 fdd9 	bl	8013a2a <osMutexNew>
 8001e78:	4603      	mov	r3, r0
 8001e7a:	4a63      	ldr	r2, [pc, #396]	@ (8002008 <MeasTasksInit+0x1c0>)
 8001e7c:	6013      	str	r3, [r2, #0]
    adc1MeasDataQueue    = osMessageQueueNew (8, sizeof (ADC1_Data), NULL);
 8001e7e:	2200      	movs	r2, #0
 8001e80:	2120      	movs	r1, #32
 8001e82:	2008      	movs	r0, #8
 8001e84:	f011 fedf 	bl	8013c46 <osMessageQueueNew>
 8001e88:	4603      	mov	r3, r0
 8001e8a:	4a60      	ldr	r2, [pc, #384]	@ (800200c <MeasTasksInit+0x1c4>)
 8001e8c:	6013      	str	r3, [r2, #0]
    adc2MeasDataQueue    = osMessageQueueNew (8, sizeof (ADC2_Data), NULL);
 8001e8e:	2200      	movs	r2, #0
 8001e90:	2120      	movs	r1, #32
 8001e92:	2008      	movs	r0, #8
 8001e94:	f011 fed7 	bl	8013c46 <osMessageQueueNew>
 8001e98:	4603      	mov	r3, r0
 8001e9a:	4a5d      	ldr	r2, [pc, #372]	@ (8002010 <MeasTasksInit+0x1c8>)
 8001e9c:	6013      	str	r3, [r2, #0]
    adc3MeasDataQueue    = osMessageQueueNew (8, sizeof (ADC3_Data), NULL);
 8001e9e:	2200      	movs	r2, #0
 8001ea0:	2120      	movs	r1, #32
 8001ea2:	2008      	movs	r0, #8
 8001ea4:	f011 fecf 	bl	8013c46 <osMessageQueueNew>
 8001ea8:	4603      	mov	r3, r0
 8001eaa:	4a5a      	ldr	r2, [pc, #360]	@ (8002014 <MeasTasksInit+0x1cc>)
 8001eac:	6013      	str	r3, [r2, #0]

    osThreadAttr_t osThreadAttradc1MeasTask = { 0 };
 8001eae:	f107 03b4 	add.w	r3, r7, #180	@ 0xb4
 8001eb2:	2224      	movs	r2, #36	@ 0x24
 8001eb4:	2100      	movs	r1, #0
 8001eb6:	4618      	mov	r0, r3
 8001eb8:	f015 fe7d 	bl	8017bb6 <memset>
    osThreadAttr_t osThreadAttradc2MeasTask = { 0 };
 8001ebc:	f107 0390 	add.w	r3, r7, #144	@ 0x90
 8001ec0:	2224      	movs	r2, #36	@ 0x24
 8001ec2:	2100      	movs	r1, #0
 8001ec4:	4618      	mov	r0, r3
 8001ec6:	f015 fe76 	bl	8017bb6 <memset>
    osThreadAttr_t osThreadAttradc3MeasTask = { 0 };
 8001eca:	f107 036c 	add.w	r3, r7, #108	@ 0x6c
 8001ece:	2224      	movs	r2, #36	@ 0x24
 8001ed0:	2100      	movs	r1, #0
 8001ed2:	4618      	mov	r0, r3
 8001ed4:	f015 fe6f 	bl	8017bb6 <memset>

    osThreadAttradc1MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2;
 8001ed8:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 8001edc:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
    osThreadAttradc1MeasTask.priority   = (osPriority_t)osPriorityRealtime;
 8001ee0:	2330      	movs	r3, #48	@ 0x30
 8001ee2:	f8c7 30cc 	str.w	r3, [r7, #204]	@ 0xcc

    osThreadAttradc2MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2;
 8001ee6:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 8001eea:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
    osThreadAttradc2MeasTask.priority   = (osPriority_t)osPriorityRealtime;
 8001eee:	2330      	movs	r3, #48	@ 0x30
 8001ef0:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8

    osThreadAttradc3MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2;
 8001ef4:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 8001ef8:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
    osThreadAttradc3MeasTask.priority   = (osPriority_t)osPriorityNormal;
 8001efc:	2318      	movs	r3, #24
 8001efe:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84

    adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask);
 8001f02:	f107 03b4 	add.w	r3, r7, #180	@ 0xb4
 8001f06:	461a      	mov	r2, r3
 8001f08:	2100      	movs	r1, #0
 8001f0a:	4843      	ldr	r0, [pc, #268]	@ (8002018 <MeasTasksInit+0x1d0>)
 8001f0c:	f011 fbe8 	bl	80136e0 <osThreadNew>
 8001f10:	4603      	mov	r3, r0
 8001f12:	4a42      	ldr	r2, [pc, #264]	@ (800201c <MeasTasksInit+0x1d4>)
 8001f14:	6013      	str	r3, [r2, #0]
    adc2MeasTaskHandle = osThreadNew (ADC2MeasTask, NULL, &osThreadAttradc2MeasTask);
 8001f16:	f107 0390 	add.w	r3, r7, #144	@ 0x90
 8001f1a:	461a      	mov	r2, r3
 8001f1c:	2100      	movs	r1, #0
 8001f1e:	4840      	ldr	r0, [pc, #256]	@ (8002020 <MeasTasksInit+0x1d8>)
 8001f20:	f011 fbde 	bl	80136e0 <osThreadNew>
 8001f24:	4603      	mov	r3, r0
 8001f26:	4a3f      	ldr	r2, [pc, #252]	@ (8002024 <MeasTasksInit+0x1dc>)
 8001f28:	6013      	str	r3, [r2, #0]
    adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask);
 8001f2a:	f107 036c 	add.w	r3, r7, #108	@ 0x6c
 8001f2e:	461a      	mov	r2, r3
 8001f30:	2100      	movs	r1, #0
 8001f32:	483d      	ldr	r0, [pc, #244]	@ (8002028 <MeasTasksInit+0x1e0>)
 8001f34:	f011 fbd4 	bl	80136e0 <osThreadNew>
 8001f38:	4603      	mov	r3, r0
 8001f3a:	4a3c      	ldr	r2, [pc, #240]	@ (800202c <MeasTasksInit+0x1e4>)
 8001f3c:	6013      	str	r3, [r2, #0]

    limiterSwitchDataQueue = osMessageQueueNew (8, sizeof (LimiterSwitchData), NULL);
 8001f3e:	2200      	movs	r2, #0
 8001f40:	2104      	movs	r1, #4
 8001f42:	2008      	movs	r0, #8
 8001f44:	f011 fe7f 	bl	8013c46 <osMessageQueueNew>
 8001f48:	4603      	mov	r3, r0
 8001f4a:	4a39      	ldr	r2, [pc, #228]	@ (8002030 <MeasTasksInit+0x1e8>)
 8001f4c:	6013      	str	r3, [r2, #0]

    osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 };
 8001f4e:	f107 0348 	add.w	r3, r7, #72	@ 0x48
 8001f52:	2224      	movs	r2, #36	@ 0x24
 8001f54:	2100      	movs	r1, #0
 8001f56:	4618      	mov	r0, r3
 8001f58:	f015 fe2d 	bl	8017bb6 <memset>
    osThreadAttradc1LimiterSwitchTask.stack_size     = configMINIMAL_STACK_SIZE * 2;
 8001f5c:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 8001f60:	65fb      	str	r3, [r7, #92]	@ 0x5c
    osThreadAttradc1LimiterSwitchTask.priority       = (osPriority_t)osPriorityNormal;
 8001f62:	2318      	movs	r3, #24
 8001f64:	663b      	str	r3, [r7, #96]	@ 0x60
    limiterSwitchTaskHandle                          = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask);
 8001f66:	f107 0348 	add.w	r3, r7, #72	@ 0x48
 8001f6a:	461a      	mov	r2, r3
 8001f6c:	2100      	movs	r1, #0
 8001f6e:	4831      	ldr	r0, [pc, #196]	@ (8002034 <MeasTasksInit+0x1ec>)
 8001f70:	f011 fbb6 	bl	80136e0 <osThreadNew>
 8001f74:	4603      	mov	r3, r0
 8001f76:	4a30      	ldr	r2, [pc, #192]	@ (8002038 <MeasTasksInit+0x1f0>)
 8001f78:	6013      	str	r3, [r2, #0]

    encoderXDataQueue = osMessageQueueNew (8, sizeof (EncoderData), NULL);
 8001f7a:	2200      	movs	r2, #0
 8001f7c:	2102      	movs	r1, #2
 8001f7e:	2008      	movs	r0, #8
 8001f80:	f011 fe61 	bl	8013c46 <osMessageQueueNew>
 8001f84:	4603      	mov	r3, r0
 8001f86:	4a2d      	ldr	r2, [pc, #180]	@ (800203c <MeasTasksInit+0x1f4>)
 8001f88:	6013      	str	r3, [r2, #0]
    encoderYDataQueue = osMessageQueueNew (8, sizeof (EncoderData), NULL);
 8001f8a:	2200      	movs	r2, #0
 8001f8c:	2102      	movs	r1, #2
 8001f8e:	2008      	movs	r0, #8
 8001f90:	f011 fe59 	bl	8013c46 <osMessageQueueNew>
 8001f94:	4603      	mov	r3, r0
 8001f96:	4a2a      	ldr	r2, [pc, #168]	@ (8002040 <MeasTasksInit+0x1f8>)
 8001f98:	6013      	str	r3, [r2, #0]

    osThreadAttr_t osThreadAttrEncoderXTask = { 0 };
 8001f9a:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 8001f9e:	2224      	movs	r2, #36	@ 0x24
 8001fa0:	2100      	movs	r1, #0
 8001fa2:	4618      	mov	r0, r3
 8001fa4:	f015 fe07 	bl	8017bb6 <memset>
    osThreadAttrEncoderXTask.stack_size     = configMINIMAL_STACK_SIZE * 2;
 8001fa8:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 8001fac:	63bb      	str	r3, [r7, #56]	@ 0x38
    osThreadAttrEncoderXTask.priority       = (osPriority_t)osPriorityNormal;
 8001fae:	2318      	movs	r3, #24
 8001fb0:	63fb      	str	r3, [r7, #60]	@ 0x3c
    encoderXTaskHandle                      = osThreadNew (EncoderTask, encoderXDataQueue, &osThreadAttrEncoderXTask);
 8001fb2:	4b22      	ldr	r3, [pc, #136]	@ (800203c <MeasTasksInit+0x1f4>)
 8001fb4:	681b      	ldr	r3, [r3, #0]
 8001fb6:	f107 0224 	add.w	r2, r7, #36	@ 0x24
 8001fba:	4619      	mov	r1, r3
 8001fbc:	4821      	ldr	r0, [pc, #132]	@ (8002044 <MeasTasksInit+0x1fc>)
 8001fbe:	f011 fb8f 	bl	80136e0 <osThreadNew>
 8001fc2:	4603      	mov	r3, r0
 8001fc4:	4a20      	ldr	r2, [pc, #128]	@ (8002048 <MeasTasksInit+0x200>)
 8001fc6:	6013      	str	r3, [r2, #0]

    osThreadAttr_t osThreadAttrEncoderYTask = { 0 };
 8001fc8:	463b      	mov	r3, r7
 8001fca:	2224      	movs	r2, #36	@ 0x24
 8001fcc:	2100      	movs	r1, #0
 8001fce:	4618      	mov	r0, r3
 8001fd0:	f015 fdf1 	bl	8017bb6 <memset>
    osThreadAttrEncoderYTask.stack_size     = configMINIMAL_STACK_SIZE * 2;
 8001fd4:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 8001fd8:	617b      	str	r3, [r7, #20]
    osThreadAttrEncoderYTask.priority       = (osPriority_t)osPriorityNormal;
 8001fda:	2318      	movs	r3, #24
 8001fdc:	61bb      	str	r3, [r7, #24]
    encoderYTaskHandle                      = osThreadNew (EncoderTask, encoderYDataQueue, &osThreadAttrEncoderYTask);
 8001fde:	4b18      	ldr	r3, [pc, #96]	@ (8002040 <MeasTasksInit+0x1f8>)
 8001fe0:	681b      	ldr	r3, [r3, #0]
 8001fe2:	463a      	mov	r2, r7
 8001fe4:	4619      	mov	r1, r3
 8001fe6:	4817      	ldr	r0, [pc, #92]	@ (8002044 <MeasTasksInit+0x1fc>)
 8001fe8:	f011 fb7a 	bl	80136e0 <osThreadNew>
 8001fec:	4603      	mov	r3, r0
 8001fee:	4a17      	ldr	r2, [pc, #92]	@ (800204c <MeasTasksInit+0x204>)
 8001ff0:	6013      	str	r3, [r2, #0]
}
 8001ff2:	bf00      	nop
 8001ff4:	37d8      	adds	r7, #216	@ 0xd8
 8001ff6:	46bd      	mov	sp, r7
 8001ff8:	bd80      	pop	{r7, pc}
 8001ffa:	bf00      	nop
 8001ffc:	240007e0 	.word	0x240007e0
 8002000:	240007e4 	.word	0x240007e4
 8002004:	240007e8 	.word	0x240007e8
 8002008:	240007ec 	.word	0x240007ec
 800200c:	240007c8 	.word	0x240007c8
 8002010:	240007cc 	.word	0x240007cc
 8002014:	240007d0 	.word	0x240007d0
 8002018:	08002051 	.word	0x08002051
 800201c:	240007b0 	.word	0x240007b0
 8002020:	080023d9 	.word	0x080023d9
 8002024:	240007b4 	.word	0x240007b4
 8002028:	080026e1 	.word	0x080026e1
 800202c:	240007b8 	.word	0x240007b8
 8002030:	240007d4 	.word	0x240007d4
 8002034:	08002a5d 	.word	0x08002a5d
 8002038:	240007bc 	.word	0x240007bc
 800203c:	240007d8 	.word	0x240007d8
 8002040:	240007dc 	.word	0x240007dc
 8002044:	08002c4d 	.word	0x08002c4d
 8002048:	240007c0 	.word	0x240007c0
 800204c:	240007c4 	.word	0x240007c4

08002050 <ADC1MeasTask>:

void ADC1MeasTask (void* arg) {
 8002050:	b580      	push	{r7, lr}
 8002052:	b09a      	sub	sp, #104	@ 0x68
 8002054:	af00      	add	r7, sp, #0
 8002056:	6078      	str	r0, [r7, #4]
    float circBuffer[VOLTAGES_COUNT][CIRC_BUFF_LEN] = { 0 };
 8002058:	f107 032c 	add.w	r3, r7, #44	@ 0x2c
 800205c:	2228      	movs	r2, #40	@ 0x28
 800205e:	2100      	movs	r1, #0
 8002060:	4618      	mov	r0, r3
 8002062:	f015 fda8 	bl	8017bb6 <memset>
    float rms[VOLTAGES_COUNT]                       = { 0 };
 8002066:	f04f 0300 	mov.w	r3, #0
 800206a:	62bb      	str	r3, [r7, #40]	@ 0x28
    ;
    ADC1_Data adcData    = { 0 };
 800206c:	f107 0308 	add.w	r3, r7, #8
 8002070:	2220      	movs	r2, #32
 8002072:	2100      	movs	r1, #0
 8002074:	4618      	mov	r0, r3
 8002076:	f015 fd9e 	bl	8017bb6 <memset>
    uint32_t circBuffPos = 0;
 800207a:	2300      	movs	r3, #0
 800207c:	667b      	str	r3, [r7, #100]	@ 0x64
    float gainCorrection = 1.0;
 800207e:	f04f 537e 	mov.w	r3, #1065353216	@ 0x3f800000
 8002082:	663b      	str	r3, [r7, #96]	@ 0x60
    while (pdTRUE) {
        osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever);
 8002084:	4bc8      	ldr	r3, [pc, #800]	@ (80023a8 <ADC1MeasTask+0x358>)
 8002086:	6818      	ldr	r0, [r3, #0]
 8002088:	f107 0108 	add.w	r1, r7, #8
 800208c:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8002090:	2200      	movs	r2, #0
 8002092:	f011 feab 	bl	8013dec <osMessageQueueGet>
#ifdef GAIN_AUTO_CORRECTION
        if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) {
 8002096:	4bc5      	ldr	r3, [pc, #788]	@ (80023ac <ADC1MeasTask+0x35c>)
 8002098:	681b      	ldr	r3, [r3, #0]
 800209a:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 800209e:	4618      	mov	r0, r3
 80020a0:	f011 fd49 	bl	8013b36 <osMutexAcquire>
 80020a4:	4603      	mov	r3, r0
 80020a6:	2b00      	cmp	r3, #0
 80020a8:	d10c      	bne.n	80020c4 <ADC1MeasTask+0x74>
            gainCorrection = (float)vRefmV;
 80020aa:	4bc1      	ldr	r3, [pc, #772]	@ (80023b0 <ADC1MeasTask+0x360>)
 80020ac:	681b      	ldr	r3, [r3, #0]
 80020ae:	ee07 3a90 	vmov	s15, r3
 80020b2:	eef8 7a67 	vcvt.f32.u32	s15, s15
 80020b6:	edc7 7a18 	vstr	s15, [r7, #96]	@ 0x60
            osMutexRelease (vRefmVMutex);
 80020ba:	4bbc      	ldr	r3, [pc, #752]	@ (80023ac <ADC1MeasTask+0x35c>)
 80020bc:	681b      	ldr	r3, [r3, #0]
 80020be:	4618      	mov	r0, r3
 80020c0:	f011 fd84 	bl	8013bcc <osMutexRelease>
        }
        gainCorrection = gainCorrection / EXT_VREF_mV;
 80020c4:	ed97 7a18 	vldr	s14, [r7, #96]	@ 0x60
 80020c8:	eddf 6aba 	vldr	s13, [pc, #744]	@ 80023b4 <ADC1MeasTask+0x364>
 80020cc:	eec7 7a26 	vdiv.f32	s15, s14, s13
 80020d0:	edc7 7a18 	vstr	s15, [r7, #96]	@ 0x60
#endif
        for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) {
 80020d4:	2300      	movs	r3, #0
 80020d6:	f887 305f 	strb.w	r3, [r7, #95]	@ 0x5f
 80020da:	e0e7      	b.n	80022ac <ADC1MeasTask+0x25c>
            float val                  = adcData.adcDataBuffer[i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
 80020dc:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 80020e0:	005b      	lsls	r3, r3, #1
 80020e2:	3368      	adds	r3, #104	@ 0x68
 80020e4:	443b      	add	r3, r7
 80020e6:	f833 3c60 	ldrh.w	r3, [r3, #-96]
 80020ea:	ee07 3a90 	vmov	s15, r3
 80020ee:	eeb8 7be7 	vcvt.f64.s32	d7, s15
 80020f2:	eeb0 6b08 	vmov.f64	d6, #8	@ 0x40400000  3.0
 80020f6:	ee27 6b06 	vmul.f64	d6, d7, d6
 80020fa:	ed9f 5ba5 	vldr	d5, [pc, #660]	@ 8002390 <ADC1MeasTask+0x340>
 80020fe:	ee86 7b05 	vdiv.f64	d7, d6, d5
 8002102:	ed9f 6ba5 	vldr	d6, [pc, #660]	@ 8002398 <ADC1MeasTask+0x348>
 8002106:	ee27 6b06 	vmul.f64	d6, d7, d6
 800210a:	edd7 7a18 	vldr	s15, [r7, #96]	@ 0x60
 800210e:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 8002112:	ee26 6b07 	vmul.f64	d6, d6, d7
 8002116:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 800211a:	4aa7      	ldr	r2, [pc, #668]	@ (80023b8 <ADC1MeasTask+0x368>)
 800211c:	00db      	lsls	r3, r3, #3
 800211e:	4413      	add	r3, r2
 8002120:	edd3 7a00 	vldr	s15, [r3]
 8002124:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 8002128:	ee26 6b07 	vmul.f64	d6, d6, d7
 800212c:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 8002130:	4aa1      	ldr	r2, [pc, #644]	@ (80023b8 <ADC1MeasTask+0x368>)
 8002132:	00db      	lsls	r3, r3, #3
 8002134:	4413      	add	r3, r2
 8002136:	3304      	adds	r3, #4
 8002138:	edd3 7a00 	vldr	s15, [r3]
 800213c:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 8002140:	ee36 7b07 	vadd.f64	d7, d6, d7
 8002144:	eef7 7bc7 	vcvt.f32.f64	s15, d7
 8002148:	edc7 7a15 	vstr	s15, [r7, #84]	@ 0x54
            circBuffer[i][circBuffPos] = val;
 800214c:	f897 205f 	ldrb.w	r2, [r7, #95]	@ 0x5f
 8002150:	4613      	mov	r3, r2
 8002152:	009b      	lsls	r3, r3, #2
 8002154:	4413      	add	r3, r2
 8002156:	005b      	lsls	r3, r3, #1
 8002158:	6e7a      	ldr	r2, [r7, #100]	@ 0x64
 800215a:	4413      	add	r3, r2
 800215c:	009b      	lsls	r3, r3, #2
 800215e:	3368      	adds	r3, #104	@ 0x68
 8002160:	443b      	add	r3, r7
 8002162:	3b3c      	subs	r3, #60	@ 0x3c
 8002164:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
 8002166:	601a      	str	r2, [r3, #0]
            rms[i]                     = 0.0;
 8002168:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 800216c:	009b      	lsls	r3, r3, #2
 800216e:	3368      	adds	r3, #104	@ 0x68
 8002170:	443b      	add	r3, r7
 8002172:	3b40      	subs	r3, #64	@ 0x40
 8002174:	f04f 0200 	mov.w	r2, #0
 8002178:	601a      	str	r2, [r3, #0]
            for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) {
 800217a:	2300      	movs	r3, #0
 800217c:	f887 305e 	strb.w	r3, [r7, #94]	@ 0x5e
 8002180:	e025      	b.n	80021ce <ADC1MeasTask+0x17e>
                rms[i] += circBuffer[i][c];
 8002182:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 8002186:	009b      	lsls	r3, r3, #2
 8002188:	3368      	adds	r3, #104	@ 0x68
 800218a:	443b      	add	r3, r7
 800218c:	3b40      	subs	r3, #64	@ 0x40
 800218e:	ed93 7a00 	vldr	s14, [r3]
 8002192:	f897 205f 	ldrb.w	r2, [r7, #95]	@ 0x5f
 8002196:	f897 105e 	ldrb.w	r1, [r7, #94]	@ 0x5e
 800219a:	4613      	mov	r3, r2
 800219c:	009b      	lsls	r3, r3, #2
 800219e:	4413      	add	r3, r2
 80021a0:	005b      	lsls	r3, r3, #1
 80021a2:	440b      	add	r3, r1
 80021a4:	009b      	lsls	r3, r3, #2
 80021a6:	3368      	adds	r3, #104	@ 0x68
 80021a8:	443b      	add	r3, r7
 80021aa:	3b3c      	subs	r3, #60	@ 0x3c
 80021ac:	edd3 7a00 	vldr	s15, [r3]
 80021b0:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 80021b4:	ee77 7a27 	vadd.f32	s15, s14, s15
 80021b8:	009b      	lsls	r3, r3, #2
 80021ba:	3368      	adds	r3, #104	@ 0x68
 80021bc:	443b      	add	r3, r7
 80021be:	3b40      	subs	r3, #64	@ 0x40
 80021c0:	edc3 7a00 	vstr	s15, [r3]
            for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) {
 80021c4:	f897 305e 	ldrb.w	r3, [r7, #94]	@ 0x5e
 80021c8:	3301      	adds	r3, #1
 80021ca:	f887 305e 	strb.w	r3, [r7, #94]	@ 0x5e
 80021ce:	f897 305e 	ldrb.w	r3, [r7, #94]	@ 0x5e
 80021d2:	2b09      	cmp	r3, #9
 80021d4:	d9d5      	bls.n	8002182 <ADC1MeasTask+0x132>
            }
            rms[i] = rms[i] / CIRC_BUFF_LEN;
 80021d6:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 80021da:	009b      	lsls	r3, r3, #2
 80021dc:	3368      	adds	r3, #104	@ 0x68
 80021de:	443b      	add	r3, r7
 80021e0:	3b40      	subs	r3, #64	@ 0x40
 80021e2:	ed93 7a00 	vldr	s14, [r3]
 80021e6:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 80021ea:	eef2 6a04 	vmov.f32	s13, #36	@ 0x41200000  10.0
 80021ee:	eec7 7a26 	vdiv.f32	s15, s14, s13
 80021f2:	009b      	lsls	r3, r3, #2
 80021f4:	3368      	adds	r3, #104	@ 0x68
 80021f6:	443b      	add	r3, r7
 80021f8:	3b40      	subs	r3, #64	@ 0x40
 80021fa:	edc3 7a00 	vstr	s15, [r3]
            if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
 80021fe:	4b6f      	ldr	r3, [pc, #444]	@ (80023bc <ADC1MeasTask+0x36c>)
 8002200:	681b      	ldr	r3, [r3, #0]
 8002202:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8002206:	4618      	mov	r0, r3
 8002208:	f011 fc95 	bl	8013b36 <osMutexAcquire>
 800220c:	4603      	mov	r3, r0
 800220e:	2b00      	cmp	r3, #0
 8002210:	d147      	bne.n	80022a2 <ADC1MeasTask+0x252>
                if (fabs (resMeasurements.voltagePeak[i]) < fabs (val)) {
 8002212:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 8002216:	4a6a      	ldr	r2, [pc, #424]	@ (80023c0 <ADC1MeasTask+0x370>)
 8002218:	3302      	adds	r3, #2
 800221a:	009b      	lsls	r3, r3, #2
 800221c:	4413      	add	r3, r2
 800221e:	3304      	adds	r3, #4
 8002220:	edd3 7a00 	vldr	s15, [r3]
 8002224:	eeb0 7ae7 	vabs.f32	s14, s15
 8002228:	edd7 7a15 	vldr	s15, [r7, #84]	@ 0x54
 800222c:	eef0 7ae7 	vabs.f32	s15, s15
 8002230:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8002234:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8002238:	d508      	bpl.n	800224c <ADC1MeasTask+0x1fc>
                    resMeasurements.voltagePeak[i] = val;
 800223a:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 800223e:	4a60      	ldr	r2, [pc, #384]	@ (80023c0 <ADC1MeasTask+0x370>)
 8002240:	3302      	adds	r3, #2
 8002242:	009b      	lsls	r3, r3, #2
 8002244:	4413      	add	r3, r2
 8002246:	3304      	adds	r3, #4
 8002248:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
 800224a:	601a      	str	r2, [r3, #0]
                }
                resMeasurements.voltageRMS[i] = rms[i];
 800224c:	f897 205f 	ldrb.w	r2, [r7, #95]	@ 0x5f
 8002250:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 8002254:	0092      	lsls	r2, r2, #2
 8002256:	3268      	adds	r2, #104	@ 0x68
 8002258:	443a      	add	r2, r7
 800225a:	3a40      	subs	r2, #64	@ 0x40
 800225c:	6812      	ldr	r2, [r2, #0]
 800225e:	4958      	ldr	r1, [pc, #352]	@ (80023c0 <ADC1MeasTask+0x370>)
 8002260:	009b      	lsls	r3, r3, #2
 8002262:	440b      	add	r3, r1
 8002264:	601a      	str	r2, [r3, #0]
                resMeasurements.power[i]      = resMeasurements.voltageRMS[i] * resMeasurements.currentRMS[i];
 8002266:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 800226a:	4a55      	ldr	r2, [pc, #340]	@ (80023c0 <ADC1MeasTask+0x370>)
 800226c:	009b      	lsls	r3, r3, #2
 800226e:	4413      	add	r3, r2
 8002270:	ed93 7a00 	vldr	s14, [r3]
 8002274:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 8002278:	4a51      	ldr	r2, [pc, #324]	@ (80023c0 <ADC1MeasTask+0x370>)
 800227a:	3306      	adds	r3, #6
 800227c:	009b      	lsls	r3, r3, #2
 800227e:	4413      	add	r3, r2
 8002280:	edd3 7a00 	vldr	s15, [r3]
 8002284:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 8002288:	ee67 7a27 	vmul.f32	s15, s14, s15
 800228c:	4a4c      	ldr	r2, [pc, #304]	@ (80023c0 <ADC1MeasTask+0x370>)
 800228e:	330c      	adds	r3, #12
 8002290:	009b      	lsls	r3, r3, #2
 8002292:	4413      	add	r3, r2
 8002294:	edc3 7a00 	vstr	s15, [r3]
                osMutexRelease (resMeasurementsMutex);
 8002298:	4b48      	ldr	r3, [pc, #288]	@ (80023bc <ADC1MeasTask+0x36c>)
 800229a:	681b      	ldr	r3, [r3, #0]
 800229c:	4618      	mov	r0, r3
 800229e:	f011 fc95 	bl	8013bcc <osMutexRelease>
        for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) {
 80022a2:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 80022a6:	3301      	adds	r3, #1
 80022a8:	f887 305f 	strb.w	r3, [r7, #95]	@ 0x5f
 80022ac:	f897 305f 	ldrb.w	r3, [r7, #95]	@ 0x5f
 80022b0:	2b00      	cmp	r3, #0
 80022b2:	f43f af13 	beq.w	80020dc <ADC1MeasTask+0x8c>
            }
        }
        ++circBuffPos;
 80022b6:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 80022b8:	3301      	adds	r3, #1
 80022ba:	667b      	str	r3, [r7, #100]	@ 0x64
        circBuffPos = circBuffPos % CIRC_BUFF_LEN;
 80022bc:	6e7a      	ldr	r2, [r7, #100]	@ 0x64
 80022be:	4b41      	ldr	r3, [pc, #260]	@ (80023c4 <ADC1MeasTask+0x374>)
 80022c0:	fba3 1302 	umull	r1, r3, r3, r2
 80022c4:	08d9      	lsrs	r1, r3, #3
 80022c6:	460b      	mov	r3, r1
 80022c8:	009b      	lsls	r3, r3, #2
 80022ca:	440b      	add	r3, r1
 80022cc:	005b      	lsls	r3, r3, #1
 80022ce:	1ad3      	subs	r3, r2, r3
 80022d0:	667b      	str	r3, [r7, #100]	@ 0x64

        if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) {
 80022d2:	4b3d      	ldr	r3, [pc, #244]	@ (80023c8 <ADC1MeasTask+0x378>)
 80022d4:	681b      	ldr	r3, [r3, #0]
 80022d6:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80022da:	4618      	mov	r0, r3
 80022dc:	f011 fc2b 	bl	8013b36 <osMutexAcquire>
 80022e0:	4603      	mov	r3, r0
 80022e2:	2b00      	cmp	r3, #0
 80022e4:	d124      	bne.n	8002330 <ADC1MeasTask+0x2e0>
            uint8_t refIdx = 0;
 80022e6:	2300      	movs	r3, #0
 80022e8:	f887 305d 	strb.w	r3, [r7, #93]	@ 0x5d
            for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) {
 80022ec:	2303      	movs	r3, #3
 80022ee:	f887 305c 	strb.w	r3, [r7, #92]	@ 0x5c
 80022f2:	e014      	b.n	800231e <ADC1MeasTask+0x2ce>
                ILxRef[refIdx++] = adcData.adcDataBuffer[i];
 80022f4:	f897 205c 	ldrb.w	r2, [r7, #92]	@ 0x5c
 80022f8:	f897 305d 	ldrb.w	r3, [r7, #93]	@ 0x5d
 80022fc:	1c59      	adds	r1, r3, #1
 80022fe:	f887 105d 	strb.w	r1, [r7, #93]	@ 0x5d
 8002302:	4619      	mov	r1, r3
 8002304:	0053      	lsls	r3, r2, #1
 8002306:	3368      	adds	r3, #104	@ 0x68
 8002308:	443b      	add	r3, r7
 800230a:	f833 2c60 	ldrh.w	r2, [r3, #-96]
 800230e:	4b2f      	ldr	r3, [pc, #188]	@ (80023cc <ADC1MeasTask+0x37c>)
 8002310:	f823 2011 	strh.w	r2, [r3, r1, lsl #1]
            for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) {
 8002314:	f897 305c 	ldrb.w	r3, [r7, #92]	@ 0x5c
 8002318:	3301      	adds	r3, #1
 800231a:	f887 305c 	strb.w	r3, [r7, #92]	@ 0x5c
 800231e:	f897 305c 	ldrb.w	r3, [r7, #92]	@ 0x5c
 8002322:	2b05      	cmp	r3, #5
 8002324:	d9e6      	bls.n	80022f4 <ADC1MeasTask+0x2a4>
            }
            osMutexRelease (ILxRefMutex);
 8002326:	4b28      	ldr	r3, [pc, #160]	@ (80023c8 <ADC1MeasTask+0x378>)
 8002328:	681b      	ldr	r3, [r3, #0]
 800232a:	4618      	mov	r0, r3
 800232c:	f011 fc4e 	bl	8013bcc <osMutexRelease>
        }

        float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12;
 8002330:	8abb      	ldrh	r3, [r7, #20]
 8002332:	ee07 3a90 	vmov	s15, r3
 8002336:	eeb8 7be7 	vcvt.f64.s32	d7, s15
 800233a:	eeb0 6b08 	vmov.f64	d6, #8	@ 0x40400000  3.0
 800233e:	ee27 6b06 	vmul.f64	d6, d7, d6
 8002342:	ed9f 5b13 	vldr	d5, [pc, #76]	@ 8002390 <ADC1MeasTask+0x340>
 8002346:	ee86 7b05 	vdiv.f64	d7, d6, d5
 800234a:	ed9f 6b15 	vldr	d6, [pc, #84]	@ 80023a0 <ADC1MeasTask+0x350>
 800234e:	ee27 7b06 	vmul.f64	d7, d7, d6
 8002352:	eeb2 6b08 	vmov.f64	d6, #40	@ 0x41400000  12.0
 8002356:	ee37 7b06 	vadd.f64	d7, d7, d6
 800235a:	eef7 7bc7 	vcvt.f32.f64	s15, d7
 800235e:	edc7 7a16 	vstr	s15, [r7, #88]	@ 0x58
        if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
 8002362:	4b1b      	ldr	r3, [pc, #108]	@ (80023d0 <ADC1MeasTask+0x380>)
 8002364:	681b      	ldr	r3, [r3, #0]
 8002366:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 800236a:	4618      	mov	r0, r3
 800236c:	f011 fbe3 	bl	8013b36 <osMutexAcquire>
 8002370:	4603      	mov	r3, r0
 8002372:	2b00      	cmp	r3, #0
 8002374:	f47f ae86 	bne.w	8002084 <ADC1MeasTask+0x34>
            sensorsInfo.fanVoltage = fanFBVoltage;
 8002378:	4a16      	ldr	r2, [pc, #88]	@ (80023d4 <ADC1MeasTask+0x384>)
 800237a:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
 800237c:	6093      	str	r3, [r2, #8]
            osMutexRelease (sensorsInfoMutex);
 800237e:	4b14      	ldr	r3, [pc, #80]	@ (80023d0 <ADC1MeasTask+0x380>)
 8002380:	681b      	ldr	r3, [r3, #0]
 8002382:	4618      	mov	r0, r3
 8002384:	f011 fc22 	bl	8013bcc <osMutexRelease>
    while (pdTRUE) {
 8002388:	e67c      	b.n	8002084 <ADC1MeasTask+0x34>
 800238a:	bf00      	nop
 800238c:	f3af 8000 	nop.w
 8002390:	00000000 	.word	0x00000000
 8002394:	40efffe0 	.word	0x40efffe0
 8002398:	f5c28f5c 	.word	0xf5c28f5c
 800239c:	401e5c28 	.word	0x401e5c28
 80023a0:	66666666 	.word	0x66666666
 80023a4:	c0116666 	.word	0xc0116666
 80023a8:	240007c8 	.word	0x240007c8
 80023ac:	240007e0 	.word	0x240007e0
 80023b0:	24000030 	.word	0x24000030
 80023b4:	453b8000 	.word	0x453b8000
 80023b8:	24000000 	.word	0x24000000
 80023bc:	240007e4 	.word	0x240007e4
 80023c0:	240007f0 	.word	0x240007f0
 80023c4:	cccccccd 	.word	0xcccccccd
 80023c8:	240007ec 	.word	0x240007ec
 80023cc:	2400085c 	.word	0x2400085c
 80023d0:	240007e8 	.word	0x240007e8
 80023d4:	2400082c 	.word	0x2400082c

080023d8 <ADC2MeasTask>:
        }
    }
}

void ADC2MeasTask (void* arg) {
 80023d8:	b580      	push	{r7, lr}
 80023da:	b09c      	sub	sp, #112	@ 0x70
 80023dc:	af00      	add	r7, sp, #0
 80023de:	6078      	str	r0, [r7, #4]
    float circBuffer[CURRENTS_COUNT][CIRC_BUFF_LEN] = { 0 };
 80023e0:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 80023e4:	2228      	movs	r2, #40	@ 0x28
 80023e6:	2100      	movs	r1, #0
 80023e8:	4618      	mov	r0, r3
 80023ea:	f015 fbe4 	bl	8017bb6 <memset>
    float rms[CURRENTS_COUNT]                       = { 0 };
 80023ee:	f04f 0300 	mov.w	r3, #0
 80023f2:	633b      	str	r3, [r7, #48]	@ 0x30
    ADC2_Data adcData                               = { 0 };
 80023f4:	f107 0310 	add.w	r3, r7, #16
 80023f8:	2220      	movs	r2, #32
 80023fa:	2100      	movs	r1, #0
 80023fc:	4618      	mov	r0, r3
 80023fe:	f015 fbda 	bl	8017bb6 <memset>
    uint32_t circBuffPos                            = 0;
 8002402:	2300      	movs	r3, #0
 8002404:	66fb      	str	r3, [r7, #108]	@ 0x6c
    float gainCorrection                            = 1.0;
 8002406:	f04f 537e 	mov.w	r3, #1065353216	@ 0x3f800000
 800240a:	66bb      	str	r3, [r7, #104]	@ 0x68
    while (pdTRUE) {
        osMessageQueueGet (adc2MeasDataQueue, &adcData, 0, osWaitForever);
 800240c:	4baa      	ldr	r3, [pc, #680]	@ (80026b8 <ADC2MeasTask+0x2e0>)
 800240e:	6818      	ldr	r0, [r3, #0]
 8002410:	f107 0110 	add.w	r1, r7, #16
 8002414:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8002418:	2200      	movs	r2, #0
 800241a:	f011 fce7 	bl	8013dec <osMessageQueueGet>
        if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) {
 800241e:	4ba7      	ldr	r3, [pc, #668]	@ (80026bc <ADC2MeasTask+0x2e4>)
 8002420:	681b      	ldr	r3, [r3, #0]
 8002422:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8002426:	4618      	mov	r0, r3
 8002428:	f011 fb85 	bl	8013b36 <osMutexAcquire>
 800242c:	4603      	mov	r3, r0
 800242e:	2b00      	cmp	r3, #0
 8002430:	d10c      	bne.n	800244c <ADC2MeasTask+0x74>
            gainCorrection = (float)vRefmV;
 8002432:	4ba3      	ldr	r3, [pc, #652]	@ (80026c0 <ADC2MeasTask+0x2e8>)
 8002434:	681b      	ldr	r3, [r3, #0]
 8002436:	ee07 3a90 	vmov	s15, r3
 800243a:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800243e:	edc7 7a1a 	vstr	s15, [r7, #104]	@ 0x68
            osMutexRelease (vRefmVMutex);
 8002442:	4b9e      	ldr	r3, [pc, #632]	@ (80026bc <ADC2MeasTask+0x2e4>)
 8002444:	681b      	ldr	r3, [r3, #0]
 8002446:	4618      	mov	r0, r3
 8002448:	f011 fbc0 	bl	8013bcc <osMutexRelease>
        }
        gainCorrection            = gainCorrection / EXT_VREF_mV;
 800244c:	ed97 7a1a 	vldr	s14, [r7, #104]	@ 0x68
 8002450:	eddf 6a9c 	vldr	s13, [pc, #624]	@ 80026c4 <ADC2MeasTask+0x2ec>
 8002454:	eec7 7a26 	vdiv.f32	s15, s14, s13
 8002458:	edc7 7a1a 	vstr	s15, [r7, #104]	@ 0x68
        float ref[CURRENTS_COUNT] = { 0 };
 800245c:	f04f 0300 	mov.w	r3, #0
 8002460:	60fb      	str	r3, [r7, #12]
        if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) {
 8002462:	4b99      	ldr	r3, [pc, #612]	@ (80026c8 <ADC2MeasTask+0x2f0>)
 8002464:	681b      	ldr	r3, [r3, #0]
 8002466:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 800246a:	4618      	mov	r0, r3
 800246c:	f011 fb63 	bl	8013b36 <osMutexAcquire>
 8002470:	4603      	mov	r3, r0
 8002472:	2b00      	cmp	r3, #0
 8002474:	d122      	bne.n	80024bc <ADC2MeasTask+0xe4>
            for (uint8_t i = 0; i < CURRENTS_COUNT; i++) {
 8002476:	2300      	movs	r3, #0
 8002478:	f887 3067 	strb.w	r3, [r7, #103]	@ 0x67
 800247c:	e015      	b.n	80024aa <ADC2MeasTask+0xd2>
                ref[i] = (float)ILxRef[i];
 800247e:	f897 3067 	ldrb.w	r3, [r7, #103]	@ 0x67
 8002482:	4a92      	ldr	r2, [pc, #584]	@ (80026cc <ADC2MeasTask+0x2f4>)
 8002484:	f832 2013 	ldrh.w	r2, [r2, r3, lsl #1]
 8002488:	f897 3067 	ldrb.w	r3, [r7, #103]	@ 0x67
 800248c:	ee07 2a90 	vmov	s15, r2
 8002490:	eef8 7a67 	vcvt.f32.u32	s15, s15
 8002494:	009b      	lsls	r3, r3, #2
 8002496:	3370      	adds	r3, #112	@ 0x70
 8002498:	443b      	add	r3, r7
 800249a:	3b64      	subs	r3, #100	@ 0x64
 800249c:	edc3 7a00 	vstr	s15, [r3]
            for (uint8_t i = 0; i < CURRENTS_COUNT; i++) {
 80024a0:	f897 3067 	ldrb.w	r3, [r7, #103]	@ 0x67
 80024a4:	3301      	adds	r3, #1
 80024a6:	f887 3067 	strb.w	r3, [r7, #103]	@ 0x67
 80024aa:	f897 3067 	ldrb.w	r3, [r7, #103]	@ 0x67
 80024ae:	2b00      	cmp	r3, #0
 80024b0:	d0e5      	beq.n	800247e <ADC2MeasTask+0xa6>
            }
            osMutexRelease (ILxRefMutex);
 80024b2:	4b85      	ldr	r3, [pc, #532]	@ (80026c8 <ADC2MeasTask+0x2f0>)
 80024b4:	681b      	ldr	r3, [r3, #0]
 80024b6:	4618      	mov	r0, r3
 80024b8:	f011 fb88 	bl	8013bcc <osMutexRelease>
        }
        for (uint8_t i = 0; i < CURRENTS_COUNT; i++) {
 80024bc:	2300      	movs	r3, #0
 80024be:	f887 3066 	strb.w	r3, [r7, #102]	@ 0x66
 80024c2:	e0db      	b.n	800267c <ADC2MeasTask+0x2a4>
            float adcVal               = (float)adcData.adcDataBuffer[i];
 80024c4:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 80024c8:	005b      	lsls	r3, r3, #1
 80024ca:	3370      	adds	r3, #112	@ 0x70
 80024cc:	443b      	add	r3, r7
 80024ce:	f833 3c60 	ldrh.w	r3, [r3, #-96]
 80024d2:	ee07 3a90 	vmov	s15, r3
 80024d6:	eef8 7a67 	vcvt.f32.u32	s15, s15
 80024da:	edc7 7a18 	vstr	s15, [r7, #96]	@ 0x60
            float val                  = (adcVal - ref[i]) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset;
 80024de:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 80024e2:	009b      	lsls	r3, r3, #2
 80024e4:	3370      	adds	r3, #112	@ 0x70
 80024e6:	443b      	add	r3, r7
 80024e8:	3b64      	subs	r3, #100	@ 0x64
 80024ea:	edd3 7a00 	vldr	s15, [r3]
 80024ee:	ed97 7a18 	vldr	s14, [r7, #96]	@ 0x60
 80024f2:	ee77 7a67 	vsub.f32	s15, s14, s15
 80024f6:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 80024fa:	eeb0 6b08 	vmov.f64	d6, #8	@ 0x40400000  3.0
 80024fe:	ee27 6b06 	vmul.f64	d6, d7, d6
 8002502:	ed9f 5b69 	vldr	d5, [pc, #420]	@ 80026a8 <ADC2MeasTask+0x2d0>
 8002506:	ee86 7b05 	vdiv.f64	d7, d6, d5
 800250a:	ed9f 6b69 	vldr	d6, [pc, #420]	@ 80026b0 <ADC2MeasTask+0x2d8>
 800250e:	ee27 6b06 	vmul.f64	d6, d7, d6
 8002512:	edd7 7a1a 	vldr	s15, [r7, #104]	@ 0x68
 8002516:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 800251a:	ee26 6b07 	vmul.f64	d6, d6, d7
 800251e:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8002522:	4a6b      	ldr	r2, [pc, #428]	@ (80026d0 <ADC2MeasTask+0x2f8>)
 8002524:	00db      	lsls	r3, r3, #3
 8002526:	4413      	add	r3, r2
 8002528:	edd3 7a00 	vldr	s15, [r3]
 800252c:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 8002530:	ee26 6b07 	vmul.f64	d6, d6, d7
 8002534:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8002538:	4a65      	ldr	r2, [pc, #404]	@ (80026d0 <ADC2MeasTask+0x2f8>)
 800253a:	00db      	lsls	r3, r3, #3
 800253c:	4413      	add	r3, r2
 800253e:	3304      	adds	r3, #4
 8002540:	edd3 7a00 	vldr	s15, [r3]
 8002544:	eeb7 7ae7 	vcvt.f64.f32	d7, s15
 8002548:	ee36 7b07 	vadd.f64	d7, d6, d7
 800254c:	eef7 7bc7 	vcvt.f32.f64	s15, d7
 8002550:	edc7 7a17 	vstr	s15, [r7, #92]	@ 0x5c
            circBuffer[i][circBuffPos] = val;
 8002554:	f897 2066 	ldrb.w	r2, [r7, #102]	@ 0x66
 8002558:	4613      	mov	r3, r2
 800255a:	009b      	lsls	r3, r3, #2
 800255c:	4413      	add	r3, r2
 800255e:	005b      	lsls	r3, r3, #1
 8002560:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
 8002562:	4413      	add	r3, r2
 8002564:	009b      	lsls	r3, r3, #2
 8002566:	3370      	adds	r3, #112	@ 0x70
 8002568:	443b      	add	r3, r7
 800256a:	3b3c      	subs	r3, #60	@ 0x3c
 800256c:	6dfa      	ldr	r2, [r7, #92]	@ 0x5c
 800256e:	601a      	str	r2, [r3, #0]
            rms[i]                     = 0.0;
 8002570:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8002574:	009b      	lsls	r3, r3, #2
 8002576:	3370      	adds	r3, #112	@ 0x70
 8002578:	443b      	add	r3, r7
 800257a:	3b40      	subs	r3, #64	@ 0x40
 800257c:	f04f 0200 	mov.w	r2, #0
 8002580:	601a      	str	r2, [r3, #0]
            for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) {
 8002582:	2300      	movs	r3, #0
 8002584:	f887 3065 	strb.w	r3, [r7, #101]	@ 0x65
 8002588:	e025      	b.n	80025d6 <ADC2MeasTask+0x1fe>
                rms[i] += circBuffer[i][c];
 800258a:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 800258e:	009b      	lsls	r3, r3, #2
 8002590:	3370      	adds	r3, #112	@ 0x70
 8002592:	443b      	add	r3, r7
 8002594:	3b40      	subs	r3, #64	@ 0x40
 8002596:	ed93 7a00 	vldr	s14, [r3]
 800259a:	f897 2066 	ldrb.w	r2, [r7, #102]	@ 0x66
 800259e:	f897 1065 	ldrb.w	r1, [r7, #101]	@ 0x65
 80025a2:	4613      	mov	r3, r2
 80025a4:	009b      	lsls	r3, r3, #2
 80025a6:	4413      	add	r3, r2
 80025a8:	005b      	lsls	r3, r3, #1
 80025aa:	440b      	add	r3, r1
 80025ac:	009b      	lsls	r3, r3, #2
 80025ae:	3370      	adds	r3, #112	@ 0x70
 80025b0:	443b      	add	r3, r7
 80025b2:	3b3c      	subs	r3, #60	@ 0x3c
 80025b4:	edd3 7a00 	vldr	s15, [r3]
 80025b8:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 80025bc:	ee77 7a27 	vadd.f32	s15, s14, s15
 80025c0:	009b      	lsls	r3, r3, #2
 80025c2:	3370      	adds	r3, #112	@ 0x70
 80025c4:	443b      	add	r3, r7
 80025c6:	3b40      	subs	r3, #64	@ 0x40
 80025c8:	edc3 7a00 	vstr	s15, [r3]
            for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) {
 80025cc:	f897 3065 	ldrb.w	r3, [r7, #101]	@ 0x65
 80025d0:	3301      	adds	r3, #1
 80025d2:	f887 3065 	strb.w	r3, [r7, #101]	@ 0x65
 80025d6:	f897 3065 	ldrb.w	r3, [r7, #101]	@ 0x65
 80025da:	2b09      	cmp	r3, #9
 80025dc:	d9d5      	bls.n	800258a <ADC2MeasTask+0x1b2>
            }
            rms[i] = rms[i] / CIRC_BUFF_LEN;
 80025de:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 80025e2:	009b      	lsls	r3, r3, #2
 80025e4:	3370      	adds	r3, #112	@ 0x70
 80025e6:	443b      	add	r3, r7
 80025e8:	3b40      	subs	r3, #64	@ 0x40
 80025ea:	ed93 7a00 	vldr	s14, [r3]
 80025ee:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 80025f2:	eef2 6a04 	vmov.f32	s13, #36	@ 0x41200000  10.0
 80025f6:	eec7 7a26 	vdiv.f32	s15, s14, s13
 80025fa:	009b      	lsls	r3, r3, #2
 80025fc:	3370      	adds	r3, #112	@ 0x70
 80025fe:	443b      	add	r3, r7
 8002600:	3b40      	subs	r3, #64	@ 0x40
 8002602:	edc3 7a00 	vstr	s15, [r3]
            if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
 8002606:	4b33      	ldr	r3, [pc, #204]	@ (80026d4 <ADC2MeasTask+0x2fc>)
 8002608:	681b      	ldr	r3, [r3, #0]
 800260a:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 800260e:	4618      	mov	r0, r3
 8002610:	f011 fa91 	bl	8013b36 <osMutexAcquire>
 8002614:	4603      	mov	r3, r0
 8002616:	2b00      	cmp	r3, #0
 8002618:	d12b      	bne.n	8002672 <ADC2MeasTask+0x29a>
                if (resMeasurements.currentPeak[i] < val) {
 800261a:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 800261e:	4a2e      	ldr	r2, [pc, #184]	@ (80026d8 <ADC2MeasTask+0x300>)
 8002620:	3308      	adds	r3, #8
 8002622:	009b      	lsls	r3, r3, #2
 8002624:	4413      	add	r3, r2
 8002626:	3304      	adds	r3, #4
 8002628:	edd3 7a00 	vldr	s15, [r3]
 800262c:	ed97 7a17 	vldr	s14, [r7, #92]	@ 0x5c
 8002630:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8002634:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8002638:	dd08      	ble.n	800264c <ADC2MeasTask+0x274>
                    resMeasurements.currentPeak[i] = val;
 800263a:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 800263e:	4a26      	ldr	r2, [pc, #152]	@ (80026d8 <ADC2MeasTask+0x300>)
 8002640:	3308      	adds	r3, #8
 8002642:	009b      	lsls	r3, r3, #2
 8002644:	4413      	add	r3, r2
 8002646:	3304      	adds	r3, #4
 8002648:	6dfa      	ldr	r2, [r7, #92]	@ 0x5c
 800264a:	601a      	str	r2, [r3, #0]
                }
                resMeasurements.currentRMS[i] = rms[i];
 800264c:	f897 2066 	ldrb.w	r2, [r7, #102]	@ 0x66
 8002650:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8002654:	0092      	lsls	r2, r2, #2
 8002656:	3270      	adds	r2, #112	@ 0x70
 8002658:	443a      	add	r2, r7
 800265a:	3a40      	subs	r2, #64	@ 0x40
 800265c:	6812      	ldr	r2, [r2, #0]
 800265e:	491e      	ldr	r1, [pc, #120]	@ (80026d8 <ADC2MeasTask+0x300>)
 8002660:	3306      	adds	r3, #6
 8002662:	009b      	lsls	r3, r3, #2
 8002664:	440b      	add	r3, r1
 8002666:	601a      	str	r2, [r3, #0]
                osMutexRelease (resMeasurementsMutex);
 8002668:	4b1a      	ldr	r3, [pc, #104]	@ (80026d4 <ADC2MeasTask+0x2fc>)
 800266a:	681b      	ldr	r3, [r3, #0]
 800266c:	4618      	mov	r0, r3
 800266e:	f011 faad 	bl	8013bcc <osMutexRelease>
        for (uint8_t i = 0; i < CURRENTS_COUNT; i++) {
 8002672:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8002676:	3301      	adds	r3, #1
 8002678:	f887 3066 	strb.w	r3, [r7, #102]	@ 0x66
 800267c:	f897 3066 	ldrb.w	r3, [r7, #102]	@ 0x66
 8002680:	2b00      	cmp	r3, #0
 8002682:	f43f af1f 	beq.w	80024c4 <ADC2MeasTask+0xec>
            }
        }
        ++circBuffPos;
 8002686:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8002688:	3301      	adds	r3, #1
 800268a:	66fb      	str	r3, [r7, #108]	@ 0x6c
        circBuffPos = circBuffPos % CIRC_BUFF_LEN;
 800268c:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
 800268e:	4b13      	ldr	r3, [pc, #76]	@ (80026dc <ADC2MeasTask+0x304>)
 8002690:	fba3 1302 	umull	r1, r3, r3, r2
 8002694:	08d9      	lsrs	r1, r3, #3
 8002696:	460b      	mov	r3, r1
 8002698:	009b      	lsls	r3, r3, #2
 800269a:	440b      	add	r3, r1
 800269c:	005b      	lsls	r3, r3, #1
 800269e:	1ad3      	subs	r3, r2, r3
 80026a0:	66fb      	str	r3, [r7, #108]	@ 0x6c
    while (pdTRUE) {
 80026a2:	e6b3      	b.n	800240c <ADC2MeasTask+0x34>
 80026a4:	f3af 8000 	nop.w
 80026a8:	00000000 	.word	0x00000000
 80026ac:	40efffe0 	.word	0x40efffe0
 80026b0:	83e425af 	.word	0x83e425af
 80026b4:	401e4d9e 	.word	0x401e4d9e
 80026b8:	240007cc 	.word	0x240007cc
 80026bc:	240007e0 	.word	0x240007e0
 80026c0:	24000030 	.word	0x24000030
 80026c4:	453b8000 	.word	0x453b8000
 80026c8:	240007ec 	.word	0x240007ec
 80026cc:	2400085c 	.word	0x2400085c
 80026d0:	24000018 	.word	0x24000018
 80026d4:	240007e4 	.word	0x240007e4
 80026d8:	240007f0 	.word	0x240007f0
 80026dc:	cccccccd 	.word	0xcccccccd

080026e0 <ADC3MeasTask>:
    }
}

void ADC3MeasTask (void* arg) {
 80026e0:	b580      	push	{r7, lr}
 80026e2:	b0bc      	sub	sp, #240	@ 0xf0
 80026e4:	af00      	add	r7, sp, #0
 80026e6:	6078      	str	r0, [r7, #4]
    float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 };
 80026e8:	f107 03a4 	add.w	r3, r7, #164	@ 0xa4
 80026ec:	2228      	movs	r2, #40	@ 0x28
 80026ee:	2100      	movs	r1, #0
 80026f0:	4618      	mov	r0, r3
 80026f2:	f015 fa60 	bl	8017bb6 <memset>
    float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 };
 80026f6:	f107 037c 	add.w	r3, r7, #124	@ 0x7c
 80026fa:	2228      	movs	r2, #40	@ 0x28
 80026fc:	2100      	movs	r1, #0
 80026fe:	4618      	mov	r0, r3
 8002700:	f015 fa59 	bl	8017bb6 <memset>
    float pvT1CircBuffer[CIRC_BUFF_LEN]       = { 0 };
 8002704:	f107 0354 	add.w	r3, r7, #84	@ 0x54
 8002708:	2228      	movs	r2, #40	@ 0x28
 800270a:	2100      	movs	r1, #0
 800270c:	4618      	mov	r0, r3
 800270e:	f015 fa52 	bl	8017bb6 <memset>
    float pvT2CircBuffer[CIRC_BUFF_LEN]       = { 0 };
 8002712:	f107 032c 	add.w	r3, r7, #44	@ 0x2c
 8002716:	2228      	movs	r2, #40	@ 0x28
 8002718:	2100      	movs	r1, #0
 800271a:	4618      	mov	r0, r3
 800271c:	f015 fa4b 	bl	8017bb6 <memset>
    uint32_t circBuffPos                      = 0;
 8002720:	2300      	movs	r3, #0
 8002722:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
    ADC3_Data adcData                         = { 0 };
 8002726:	f107 030c 	add.w	r3, r7, #12
 800272a:	2220      	movs	r2, #32
 800272c:	2100      	movs	r1, #0
 800272e:	4618      	mov	r0, r3
 8002730:	f015 fa41 	bl	8017bb6 <memset>
    while (pdTRUE) {
        osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever);
 8002734:	4bc2      	ldr	r3, [pc, #776]	@ (8002a40 <ADC3MeasTask+0x360>)
 8002736:	6818      	ldr	r0, [r3, #0]
 8002738:	f107 010c 	add.w	r1, r7, #12
 800273c:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8002740:	2200      	movs	r2, #0
 8002742:	f011 fb53 	bl	8013dec <osMessageQueueGet>
        uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B);
 8002746:	4bbf      	ldr	r3, [pc, #764]	@ (8002a44 <ADC3MeasTask+0x364>)
 8002748:	881b      	ldrh	r3, [r3, #0]
 800274a:	461a      	mov	r2, r3
 800274c:	f640 43e4 	movw	r3, #3300	@ 0xce4
 8002750:	fb02 f303 	mul.w	r3, r2, r3
 8002754:	8aba      	ldrh	r2, [r7, #20]
 8002756:	fbb3 f3f2 	udiv	r3, r3, r2
 800275a:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
        if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) {
 800275e:	4bba      	ldr	r3, [pc, #744]	@ (8002a48 <ADC3MeasTask+0x368>)
 8002760:	681b      	ldr	r3, [r3, #0]
 8002762:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8002766:	4618      	mov	r0, r3
 8002768:	f011 f9e5 	bl	8013b36 <osMutexAcquire>
 800276c:	4603      	mov	r3, r0
 800276e:	2b00      	cmp	r3, #0
 8002770:	d108      	bne.n	8002784 <ADC3MeasTask+0xa4>
            vRefmV = vRef;
 8002772:	4ab6      	ldr	r2, [pc, #728]	@ (8002a4c <ADC3MeasTask+0x36c>)
 8002774:	f8d7 30d4 	ldr.w	r3, [r7, #212]	@ 0xd4
 8002778:	6013      	str	r3, [r2, #0]
            osMutexRelease (vRefmVMutex);
 800277a:	4bb3      	ldr	r3, [pc, #716]	@ (8002a48 <ADC3MeasTask+0x368>)
 800277c:	681b      	ldr	r3, [r3, #0]
 800277e:	4618      	mov	r0, r3
 8002780:	f011 fa24 	bl	8013bcc <osMutexRelease>
        }
        float motorXCurrentSense          = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333;
 8002784:	8a3b      	ldrh	r3, [r7, #16]
 8002786:	ee07 3a90 	vmov	s15, r3
 800278a:	eeb8 7be7 	vcvt.f64.s32	d7, s15
 800278e:	eeb0 6b08 	vmov.f64	d6, #8	@ 0x40400000  3.0
 8002792:	ee27 6b06 	vmul.f64	d6, d7, d6
 8002796:	ed9f 5ba2 	vldr	d5, [pc, #648]	@ 8002a20 <ADC3MeasTask+0x340>
 800279a:	ee86 7b05 	vdiv.f64	d7, d6, d5
 800279e:	eeb2 6b04 	vmov.f64	d6, #36	@ 0x41200000  10.0
 80027a2:	ee27 6b06 	vmul.f64	d6, d7, d6
 80027a6:	ed9f 5ba0 	vldr	d5, [pc, #640]	@ 8002a28 <ADC3MeasTask+0x348>
 80027aa:	ee86 7b05 	vdiv.f64	d7, d6, d5
 80027ae:	eef7 7bc7 	vcvt.f32.f64	s15, d7
 80027b2:	edc7 7a34 	vstr	s15, [r7, #208]	@ 0xd0
        float motorYCurrentSense          = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333;
 80027b6:	8a7b      	ldrh	r3, [r7, #18]
 80027b8:	ee07 3a90 	vmov	s15, r3
 80027bc:	eeb8 7be7 	vcvt.f64.s32	d7, s15
 80027c0:	eeb0 6b08 	vmov.f64	d6, #8	@ 0x40400000  3.0
 80027c4:	ee27 6b06 	vmul.f64	d6, d7, d6
 80027c8:	ed9f 5b95 	vldr	d5, [pc, #596]	@ 8002a20 <ADC3MeasTask+0x340>
 80027cc:	ee86 7b05 	vdiv.f64	d7, d6, d5
 80027d0:	eeb2 6b04 	vmov.f64	d6, #36	@ 0x41200000  10.0
 80027d4:	ee27 6b06 	vmul.f64	d6, d7, d6
 80027d8:	ed9f 5b93 	vldr	d5, [pc, #588]	@ 8002a28 <ADC3MeasTask+0x348>
 80027dc:	ee86 7b05 	vdiv.f64	d7, d6, d5
 80027e0:	eef7 7bc7 	vcvt.f32.f64	s15, d7
 80027e4:	edc7 7a33 	vstr	s15, [r7, #204]	@ 0xcc
        motorXSensCircBuffer[circBuffPos] = motorXCurrentSense;
 80027e8:	f8d7 30ec 	ldr.w	r3, [r7, #236]	@ 0xec
 80027ec:	009b      	lsls	r3, r3, #2
 80027ee:	33f0      	adds	r3, #240	@ 0xf0
 80027f0:	443b      	add	r3, r7
 80027f2:	3b4c      	subs	r3, #76	@ 0x4c
 80027f4:	f8d7 20d0 	ldr.w	r2, [r7, #208]	@ 0xd0
 80027f8:	601a      	str	r2, [r3, #0]
        motorYSensCircBuffer[circBuffPos] = motorYCurrentSense;
 80027fa:	f8d7 30ec 	ldr.w	r3, [r7, #236]	@ 0xec
 80027fe:	009b      	lsls	r3, r3, #2
 8002800:	33f0      	adds	r3, #240	@ 0xf0
 8002802:	443b      	add	r3, r7
 8002804:	3b74      	subs	r3, #116	@ 0x74
 8002806:	f8d7 20cc 	ldr.w	r2, [r7, #204]	@ 0xcc
 800280a:	601a      	str	r2, [r3, #0]
        pvT1CircBuffer[circBuffPos]       = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63;
 800280c:	89bb      	ldrh	r3, [r7, #12]
 800280e:	ee07 3a90 	vmov	s15, r3
 8002812:	eeb8 7be7 	vcvt.f64.s32	d7, s15
 8002816:	eeb0 6b08 	vmov.f64	d6, #8	@ 0x40400000  3.0
 800281a:	ee27 6b06 	vmul.f64	d6, d7, d6
 800281e:	ed9f 5b80 	vldr	d5, [pc, #512]	@ 8002a20 <ADC3MeasTask+0x340>
 8002822:	ee86 7b05 	vdiv.f64	d7, d6, d5
 8002826:	ed9f 6b82 	vldr	d6, [pc, #520]	@ 8002a30 <ADC3MeasTask+0x350>
 800282a:	ee27 7b06 	vmul.f64	d7, d7, d6
 800282e:	ed9f 6b82 	vldr	d6, [pc, #520]	@ 8002a38 <ADC3MeasTask+0x358>
 8002832:	ee37 7b46 	vsub.f64	d7, d7, d6
 8002836:	eef7 7bc7 	vcvt.f32.f64	s15, d7
 800283a:	f8d7 30ec 	ldr.w	r3, [r7, #236]	@ 0xec
 800283e:	009b      	lsls	r3, r3, #2
 8002840:	33f0      	adds	r3, #240	@ 0xf0
 8002842:	443b      	add	r3, r7
 8002844:	3b9c      	subs	r3, #156	@ 0x9c
 8002846:	edc3 7a00 	vstr	s15, [r3]
        pvT2CircBuffer[circBuffPos]       = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63;
 800284a:	89fb      	ldrh	r3, [r7, #14]
 800284c:	ee07 3a90 	vmov	s15, r3
 8002850:	eeb8 7be7 	vcvt.f64.s32	d7, s15
 8002854:	eeb0 6b08 	vmov.f64	d6, #8	@ 0x40400000  3.0
 8002858:	ee27 6b06 	vmul.f64	d6, d7, d6
 800285c:	ed9f 5b70 	vldr	d5, [pc, #448]	@ 8002a20 <ADC3MeasTask+0x340>
 8002860:	ee86 7b05 	vdiv.f64	d7, d6, d5
 8002864:	ed9f 6b72 	vldr	d6, [pc, #456]	@ 8002a30 <ADC3MeasTask+0x350>
 8002868:	ee27 7b06 	vmul.f64	d7, d7, d6
 800286c:	ed9f 6b72 	vldr	d6, [pc, #456]	@ 8002a38 <ADC3MeasTask+0x358>
 8002870:	ee37 7b46 	vsub.f64	d7, d7, d6
 8002874:	eef7 7bc7 	vcvt.f32.f64	s15, d7
 8002878:	f8d7 30ec 	ldr.w	r3, [r7, #236]	@ 0xec
 800287c:	009b      	lsls	r3, r3, #2
 800287e:	33f0      	adds	r3, #240	@ 0xf0
 8002880:	443b      	add	r3, r7
 8002882:	3bc4      	subs	r3, #196	@ 0xc4
 8002884:	edc3 7a00 	vstr	s15, [r3]
        float motorXAveCurrent            = 0;
 8002888:	f04f 0300 	mov.w	r3, #0
 800288c:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
        float motorYAveCurrent            = 0;
 8002890:	f04f 0300 	mov.w	r3, #0
 8002894:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
        float pvT1AveTemp                 = 0;
 8002898:	f04f 0300 	mov.w	r3, #0
 800289c:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
        float pvT2AveTemp                 = 0;
 80028a0:	f04f 0300 	mov.w	r3, #0
 80028a4:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
        for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) {
 80028a8:	2300      	movs	r3, #0
 80028aa:	f887 30db 	strb.w	r3, [r7, #219]	@ 0xdb
 80028ae:	e03c      	b.n	800292a <ADC3MeasTask+0x24a>
            motorXAveCurrent += motorXSensCircBuffer[i];
 80028b0:	f897 30db 	ldrb.w	r3, [r7, #219]	@ 0xdb
 80028b4:	009b      	lsls	r3, r3, #2
 80028b6:	33f0      	adds	r3, #240	@ 0xf0
 80028b8:	443b      	add	r3, r7
 80028ba:	3b4c      	subs	r3, #76	@ 0x4c
 80028bc:	edd3 7a00 	vldr	s15, [r3]
 80028c0:	ed97 7a3a 	vldr	s14, [r7, #232]	@ 0xe8
 80028c4:	ee77 7a27 	vadd.f32	s15, s14, s15
 80028c8:	edc7 7a3a 	vstr	s15, [r7, #232]	@ 0xe8
            motorYAveCurrent += motorYSensCircBuffer[i];
 80028cc:	f897 30db 	ldrb.w	r3, [r7, #219]	@ 0xdb
 80028d0:	009b      	lsls	r3, r3, #2
 80028d2:	33f0      	adds	r3, #240	@ 0xf0
 80028d4:	443b      	add	r3, r7
 80028d6:	3b74      	subs	r3, #116	@ 0x74
 80028d8:	edd3 7a00 	vldr	s15, [r3]
 80028dc:	ed97 7a39 	vldr	s14, [r7, #228]	@ 0xe4
 80028e0:	ee77 7a27 	vadd.f32	s15, s14, s15
 80028e4:	edc7 7a39 	vstr	s15, [r7, #228]	@ 0xe4
#ifdef PV_BOARD
            pvT1AveTemp += pvT1CircBuffer[i];
 80028e8:	f897 30db 	ldrb.w	r3, [r7, #219]	@ 0xdb
 80028ec:	009b      	lsls	r3, r3, #2
 80028ee:	33f0      	adds	r3, #240	@ 0xf0
 80028f0:	443b      	add	r3, r7
 80028f2:	3b9c      	subs	r3, #156	@ 0x9c
 80028f4:	edd3 7a00 	vldr	s15, [r3]
 80028f8:	ed97 7a38 	vldr	s14, [r7, #224]	@ 0xe0
 80028fc:	ee77 7a27 	vadd.f32	s15, s14, s15
 8002900:	edc7 7a38 	vstr	s15, [r7, #224]	@ 0xe0
            pvT2AveTemp += pvT2CircBuffer[i];
 8002904:	f897 30db 	ldrb.w	r3, [r7, #219]	@ 0xdb
 8002908:	009b      	lsls	r3, r3, #2
 800290a:	33f0      	adds	r3, #240	@ 0xf0
 800290c:	443b      	add	r3, r7
 800290e:	3bc4      	subs	r3, #196	@ 0xc4
 8002910:	edd3 7a00 	vldr	s15, [r3]
 8002914:	ed97 7a37 	vldr	s14, [r7, #220]	@ 0xdc
 8002918:	ee77 7a27 	vadd.f32	s15, s14, s15
 800291c:	edc7 7a37 	vstr	s15, [r7, #220]	@ 0xdc
        for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) {
 8002920:	f897 30db 	ldrb.w	r3, [r7, #219]	@ 0xdb
 8002924:	3301      	adds	r3, #1
 8002926:	f887 30db 	strb.w	r3, [r7, #219]	@ 0xdb
 800292a:	f897 30db 	ldrb.w	r3, [r7, #219]	@ 0xdb
 800292e:	2b09      	cmp	r3, #9
 8002930:	d9be      	bls.n	80028b0 <ADC3MeasTask+0x1d0>
#endif
        }
        motorXAveCurrent /= CIRC_BUFF_LEN;
 8002932:	ed97 7a3a 	vldr	s14, [r7, #232]	@ 0xe8
 8002936:	eef2 6a04 	vmov.f32	s13, #36	@ 0x41200000  10.0
 800293a:	eec7 7a26 	vdiv.f32	s15, s14, s13
 800293e:	edc7 7a3a 	vstr	s15, [r7, #232]	@ 0xe8
        motorYAveCurrent /= CIRC_BUFF_LEN;
 8002942:	ed97 7a39 	vldr	s14, [r7, #228]	@ 0xe4
 8002946:	eef2 6a04 	vmov.f32	s13, #36	@ 0x41200000  10.0
 800294a:	eec7 7a26 	vdiv.f32	s15, s14, s13
 800294e:	edc7 7a39 	vstr	s15, [r7, #228]	@ 0xe4
        pvT1AveTemp /= CIRC_BUFF_LEN;
 8002952:	ed97 7a38 	vldr	s14, [r7, #224]	@ 0xe0
 8002956:	eef2 6a04 	vmov.f32	s13, #36	@ 0x41200000  10.0
 800295a:	eec7 7a26 	vdiv.f32	s15, s14, s13
 800295e:	edc7 7a38 	vstr	s15, [r7, #224]	@ 0xe0
        pvT2AveTemp /= CIRC_BUFF_LEN;
 8002962:	ed97 7a37 	vldr	s14, [r7, #220]	@ 0xdc
 8002966:	eef2 6a04 	vmov.f32	s13, #36	@ 0x41200000  10.0
 800296a:	eec7 7a26 	vdiv.f32	s15, s14, s13
 800296e:	edc7 7a37 	vstr	s15, [r7, #220]	@ 0xdc
        if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
 8002972:	4b37      	ldr	r3, [pc, #220]	@ (8002a50 <ADC3MeasTask+0x370>)
 8002974:	681b      	ldr	r3, [r3, #0]
 8002976:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 800297a:	4618      	mov	r0, r3
 800297c:	f011 f8db 	bl	8013b36 <osMutexAcquire>
 8002980:	4603      	mov	r3, r0
 8002982:	2b00      	cmp	r3, #0
 8002984:	d138      	bne.n	80029f8 <ADC3MeasTask+0x318>
            if (sensorsInfo.motorXStatus == 1) {
 8002986:	4b33      	ldr	r3, [pc, #204]	@ (8002a54 <ADC3MeasTask+0x374>)
 8002988:	7d1b      	ldrb	r3, [r3, #20]
 800298a:	2b01      	cmp	r3, #1
 800298c:	d111      	bne.n	80029b2 <ADC3MeasTask+0x2d2>
                sensorsInfo.motorXAveCurrent = motorXAveCurrent;
 800298e:	4a31      	ldr	r2, [pc, #196]	@ (8002a54 <ADC3MeasTask+0x374>)
 8002990:	f8d7 30e8 	ldr.w	r3, [r7, #232]	@ 0xe8
 8002994:	6193      	str	r3, [r2, #24]
                if (sensorsInfo.motorXPeakCurrent < motorXCurrentSense) {
 8002996:	4b2f      	ldr	r3, [pc, #188]	@ (8002a54 <ADC3MeasTask+0x374>)
 8002998:	edd3 7a08 	vldr	s15, [r3, #32]
 800299c:	ed97 7a34 	vldr	s14, [r7, #208]	@ 0xd0
 80029a0:	eeb4 7ae7 	vcmpe.f32	s14, s15
 80029a4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 80029a8:	dd03      	ble.n	80029b2 <ADC3MeasTask+0x2d2>
                    sensorsInfo.motorXPeakCurrent = motorXCurrentSense;
 80029aa:	4a2a      	ldr	r2, [pc, #168]	@ (8002a54 <ADC3MeasTask+0x374>)
 80029ac:	f8d7 30d0 	ldr.w	r3, [r7, #208]	@ 0xd0
 80029b0:	6213      	str	r3, [r2, #32]
                }
            }
            if (sensorsInfo.motorYStatus == 1) {
 80029b2:	4b28      	ldr	r3, [pc, #160]	@ (8002a54 <ADC3MeasTask+0x374>)
 80029b4:	7d5b      	ldrb	r3, [r3, #21]
 80029b6:	2b01      	cmp	r3, #1
 80029b8:	d111      	bne.n	80029de <ADC3MeasTask+0x2fe>
                sensorsInfo.motorYAveCurrent = motorYAveCurrent;
 80029ba:	4a26      	ldr	r2, [pc, #152]	@ (8002a54 <ADC3MeasTask+0x374>)
 80029bc:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 80029c0:	61d3      	str	r3, [r2, #28]
                if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) {
 80029c2:	4b24      	ldr	r3, [pc, #144]	@ (8002a54 <ADC3MeasTask+0x374>)
 80029c4:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 80029c8:	ed97 7a33 	vldr	s14, [r7, #204]	@ 0xcc
 80029cc:	eeb4 7ae7 	vcmpe.f32	s14, s15
 80029d0:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 80029d4:	dd03      	ble.n	80029de <ADC3MeasTask+0x2fe>
                    sensorsInfo.motorYPeakCurrent = motorYCurrentSense;
 80029d6:	4a1f      	ldr	r2, [pc, #124]	@ (8002a54 <ADC3MeasTask+0x374>)
 80029d8:	f8d7 30cc 	ldr.w	r3, [r7, #204]	@ 0xcc
 80029dc:	6253      	str	r3, [r2, #36]	@ 0x24
                }
            }
            sensorsInfo.pvTemperature[0] = pvT1AveTemp;
 80029de:	4a1d      	ldr	r2, [pc, #116]	@ (8002a54 <ADC3MeasTask+0x374>)
 80029e0:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 80029e4:	6013      	str	r3, [r2, #0]
            sensorsInfo.pvTemperature[1] = pvT2AveTemp;
 80029e6:	4a1b      	ldr	r2, [pc, #108]	@ (8002a54 <ADC3MeasTask+0x374>)
 80029e8:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 80029ec:	6053      	str	r3, [r2, #4]
            osMutexRelease (sensorsInfoMutex);
 80029ee:	4b18      	ldr	r3, [pc, #96]	@ (8002a50 <ADC3MeasTask+0x370>)
 80029f0:	681b      	ldr	r3, [r3, #0]
 80029f2:	4618      	mov	r0, r3
 80029f4:	f011 f8ea 	bl	8013bcc <osMutexRelease>
        }
        ++circBuffPos;
 80029f8:	f8d7 30ec 	ldr.w	r3, [r7, #236]	@ 0xec
 80029fc:	3301      	adds	r3, #1
 80029fe:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
        circBuffPos = circBuffPos % CIRC_BUFF_LEN;
 8002a02:	f8d7 20ec 	ldr.w	r2, [r7, #236]	@ 0xec
 8002a06:	4b14      	ldr	r3, [pc, #80]	@ (8002a58 <ADC3MeasTask+0x378>)
 8002a08:	fba3 1302 	umull	r1, r3, r3, r2
 8002a0c:	08d9      	lsrs	r1, r3, #3
 8002a0e:	460b      	mov	r3, r1
 8002a10:	009b      	lsls	r3, r3, #2
 8002a12:	440b      	add	r3, r1
 8002a14:	005b      	lsls	r3, r3, #1
 8002a16:	1ad3      	subs	r3, r2, r3
 8002a18:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
    while (pdTRUE) {
 8002a1c:	e68a      	b.n	8002734 <ADC3MeasTask+0x54>
 8002a1e:	bf00      	nop
 8002a20:	00000000 	.word	0x00000000
 8002a24:	40efffe0 	.word	0x40efffe0
 8002a28:	3ad18d26 	.word	0x3ad18d26
 8002a2c:	4020aaaa 	.word	0x4020aaaa
 8002a30:	aaa38226 	.word	0xaaa38226
 8002a34:	4046aaaa 	.word	0x4046aaaa
 8002a38:	00000000 	.word	0x00000000
 8002a3c:	404f8000 	.word	0x404f8000
 8002a40:	240007d0 	.word	0x240007d0
 8002a44:	1ff1e860 	.word	0x1ff1e860
 8002a48:	240007e0 	.word	0x240007e0
 8002a4c:	24000030 	.word	0x24000030
 8002a50:	240007e8 	.word	0x240007e8
 8002a54:	2400082c 	.word	0x2400082c
 8002a58:	cccccccd 	.word	0xcccccccd

08002a5c <LimiterSwitchTask>:
    }
}

void LimiterSwitchTask (void* arg) {
 8002a5c:	b580      	push	{r7, lr}
 8002a5e:	b08a      	sub	sp, #40	@ 0x28
 8002a60:	af06      	add	r7, sp, #24
 8002a62:	6078      	str	r0, [r7, #4]
    LimiterSwitchData limiterSwitchData = { 0 };
 8002a64:	2300      	movs	r3, #0
 8002a66:	60bb      	str	r3, [r7, #8]
    limiterSwitchData.gpioPin           = GPIO_PIN_8;
 8002a68:	f44f 7380 	mov.w	r3, #256	@ 0x100
 8002a6c:	813b      	strh	r3, [r7, #8]
    for (uint8_t i = 0; i < 6; i++) {
 8002a6e:	2300      	movs	r3, #0
 8002a70:	73fb      	strb	r3, [r7, #15]
 8002a72:	e015      	b.n	8002aa0 <LimiterSwitchTask+0x44>
        limiterSwitchData.pinState = HAL_GPIO_ReadPin (GPIOD, limiterSwitchData.gpioPin);
 8002a74:	893b      	ldrh	r3, [r7, #8]
 8002a76:	4619      	mov	r1, r3
 8002a78:	486c      	ldr	r0, [pc, #432]	@ (8002c2c <LimiterSwitchTask+0x1d0>)
 8002a7a:	f008 f867 	bl	800ab4c <HAL_GPIO_ReadPin>
 8002a7e:	4603      	mov	r3, r0
 8002a80:	72bb      	strb	r3, [r7, #10]
        osMessageQueuePut (limiterSwitchDataQueue, &limiterSwitchData, 0, 0);
 8002a82:	4b6b      	ldr	r3, [pc, #428]	@ (8002c30 <LimiterSwitchTask+0x1d4>)
 8002a84:	6818      	ldr	r0, [r3, #0]
 8002a86:	f107 0108 	add.w	r1, r7, #8
 8002a8a:	2300      	movs	r3, #0
 8002a8c:	2200      	movs	r2, #0
 8002a8e:	f011 f94d 	bl	8013d2c <osMessageQueuePut>
        limiterSwitchData.gpioPin = limiterSwitchData.gpioPin << 1;
 8002a92:	893b      	ldrh	r3, [r7, #8]
 8002a94:	005b      	lsls	r3, r3, #1
 8002a96:	b29b      	uxth	r3, r3
 8002a98:	813b      	strh	r3, [r7, #8]
    for (uint8_t i = 0; i < 6; i++) {
 8002a9a:	7bfb      	ldrb	r3, [r7, #15]
 8002a9c:	3301      	adds	r3, #1
 8002a9e:	73fb      	strb	r3, [r7, #15]
 8002aa0:	7bfb      	ldrb	r3, [r7, #15]
 8002aa2:	2b05      	cmp	r3, #5
 8002aa4:	d9e6      	bls.n	8002a74 <LimiterSwitchTask+0x18>
    }
    while (pdTRUE) {
        osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever);
 8002aa6:	4b62      	ldr	r3, [pc, #392]	@ (8002c30 <LimiterSwitchTask+0x1d4>)
 8002aa8:	6818      	ldr	r0, [r3, #0]
 8002aaa:	f107 0108 	add.w	r1, r7, #8
 8002aae:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8002ab2:	2200      	movs	r2, #0
 8002ab4:	f011 f99a 	bl	8013dec <osMessageQueueGet>
        if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
 8002ab8:	4b5e      	ldr	r3, [pc, #376]	@ (8002c34 <LimiterSwitchTask+0x1d8>)
 8002aba:	681b      	ldr	r3, [r3, #0]
 8002abc:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8002ac0:	4618      	mov	r0, r3
 8002ac2:	f011 f838 	bl	8013b36 <osMutexAcquire>
 8002ac6:	4603      	mov	r3, r0
 8002ac8:	2b00      	cmp	r3, #0
 8002aca:	d1ec      	bne.n	8002aa6 <LimiterSwitchTask+0x4a>
            switch (limiterSwitchData.gpioPin) {
 8002acc:	893b      	ldrh	r3, [r7, #8]
 8002ace:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 8002ad2:	d052      	beq.n	8002b7a <LimiterSwitchTask+0x11e>
 8002ad4:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 8002ad8:	dc5a      	bgt.n	8002b90 <LimiterSwitchTask+0x134>
 8002ada:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 8002ade:	d041      	beq.n	8002b64 <LimiterSwitchTask+0x108>
 8002ae0:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 8002ae4:	dc54      	bgt.n	8002b90 <LimiterSwitchTask+0x134>
 8002ae6:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 8002aea:	d030      	beq.n	8002b4e <LimiterSwitchTask+0xf2>
 8002aec:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 8002af0:	dc4e      	bgt.n	8002b90 <LimiterSwitchTask+0x134>
 8002af2:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 8002af6:	d01f      	beq.n	8002b38 <LimiterSwitchTask+0xdc>
 8002af8:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 8002afc:	dc48      	bgt.n	8002b90 <LimiterSwitchTask+0x134>
 8002afe:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 8002b02:	d003      	beq.n	8002b0c <LimiterSwitchTask+0xb0>
 8002b04:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 8002b08:	d00b      	beq.n	8002b22 <LimiterSwitchTask+0xc6>
            case GPIO_PIN_9: sensorsInfo.limitYSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break;
            case GPIO_PIN_10: sensorsInfo.limitXSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break;
            case GPIO_PIN_11: sensorsInfo.limitYSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break;
            case GPIO_PIN_12: sensorsInfo.limitXSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break;
            case GPIO_PIN_13: sensorsInfo.limitXSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break;
            default: break;
 8002b0a:	e041      	b.n	8002b90 <LimiterSwitchTask+0x134>
            case GPIO_PIN_8: sensorsInfo.limitYSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break;
 8002b0c:	7abb      	ldrb	r3, [r7, #10]
 8002b0e:	2b01      	cmp	r3, #1
 8002b10:	bf14      	ite	ne
 8002b12:	2301      	movne	r3, #1
 8002b14:	2300      	moveq	r3, #0
 8002b16:	b2db      	uxtb	r3, r3
 8002b18:	461a      	mov	r2, r3
 8002b1a:	4b47      	ldr	r3, [pc, #284]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002b1c:	f883 202d 	strb.w	r2, [r3, #45]	@ 0x2d
 8002b20:	e037      	b.n	8002b92 <LimiterSwitchTask+0x136>
            case GPIO_PIN_9: sensorsInfo.limitYSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break;
 8002b22:	7abb      	ldrb	r3, [r7, #10]
 8002b24:	2b01      	cmp	r3, #1
 8002b26:	bf14      	ite	ne
 8002b28:	2301      	movne	r3, #1
 8002b2a:	2300      	moveq	r3, #0
 8002b2c:	b2db      	uxtb	r3, r3
 8002b2e:	461a      	mov	r2, r3
 8002b30:	4b41      	ldr	r3, [pc, #260]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002b32:	f883 202c 	strb.w	r2, [r3, #44]	@ 0x2c
 8002b36:	e02c      	b.n	8002b92 <LimiterSwitchTask+0x136>
            case GPIO_PIN_10: sensorsInfo.limitXSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break;
 8002b38:	7abb      	ldrb	r3, [r7, #10]
 8002b3a:	2b01      	cmp	r3, #1
 8002b3c:	bf14      	ite	ne
 8002b3e:	2301      	movne	r3, #1
 8002b40:	2300      	moveq	r3, #0
 8002b42:	b2db      	uxtb	r3, r3
 8002b44:	461a      	mov	r2, r3
 8002b46:	4b3c      	ldr	r3, [pc, #240]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002b48:	f883 202a 	strb.w	r2, [r3, #42]	@ 0x2a
 8002b4c:	e021      	b.n	8002b92 <LimiterSwitchTask+0x136>
            case GPIO_PIN_11: sensorsInfo.limitYSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break;
 8002b4e:	7abb      	ldrb	r3, [r7, #10]
 8002b50:	2b01      	cmp	r3, #1
 8002b52:	bf14      	ite	ne
 8002b54:	2301      	movne	r3, #1
 8002b56:	2300      	moveq	r3, #0
 8002b58:	b2db      	uxtb	r3, r3
 8002b5a:	461a      	mov	r2, r3
 8002b5c:	4b36      	ldr	r3, [pc, #216]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002b5e:	f883 202b 	strb.w	r2, [r3, #43]	@ 0x2b
 8002b62:	e016      	b.n	8002b92 <LimiterSwitchTask+0x136>
            case GPIO_PIN_12: sensorsInfo.limitXSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break;
 8002b64:	7abb      	ldrb	r3, [r7, #10]
 8002b66:	2b01      	cmp	r3, #1
 8002b68:	bf14      	ite	ne
 8002b6a:	2301      	movne	r3, #1
 8002b6c:	2300      	moveq	r3, #0
 8002b6e:	b2db      	uxtb	r3, r3
 8002b70:	461a      	mov	r2, r3
 8002b72:	4b31      	ldr	r3, [pc, #196]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002b74:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
 8002b78:	e00b      	b.n	8002b92 <LimiterSwitchTask+0x136>
            case GPIO_PIN_13: sensorsInfo.limitXSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break;
 8002b7a:	7abb      	ldrb	r3, [r7, #10]
 8002b7c:	2b01      	cmp	r3, #1
 8002b7e:	bf14      	ite	ne
 8002b80:	2301      	movne	r3, #1
 8002b82:	2300      	moveq	r3, #0
 8002b84:	b2db      	uxtb	r3, r3
 8002b86:	461a      	mov	r2, r3
 8002b88:	4b2b      	ldr	r3, [pc, #172]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002b8a:	f883 2029 	strb.w	r2, [r3, #41]	@ 0x29
 8002b8e:	e000      	b.n	8002b92 <LimiterSwitchTask+0x136>
            default: break;
 8002b90:	bf00      	nop
            }
            if ((sensorsInfo.limitXSwitchDown == 1) || (sensorsInfo.limitXSwitchUp == 1)) {
 8002b92:	4b29      	ldr	r3, [pc, #164]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002b94:	f893 3029 	ldrb.w	r3, [r3, #41]	@ 0x29
 8002b98:	2b01      	cmp	r3, #1
 8002b9a:	d004      	beq.n	8002ba6 <LimiterSwitchTask+0x14a>
 8002b9c:	4b26      	ldr	r3, [pc, #152]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002b9e:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8002ba2:	2b01      	cmp	r3, #1
 8002ba4:	d118      	bne.n	8002bd8 <LimiterSwitchTask+0x17c>
                sensorsInfo.motorXStatus = motorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown);
 8002ba6:	4b25      	ldr	r3, [pc, #148]	@ (8002c3c <LimiterSwitchTask+0x1e0>)
 8002ba8:	681b      	ldr	r3, [r3, #0]
 8002baa:	4a23      	ldr	r2, [pc, #140]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002bac:	f892 2028 	ldrb.w	r2, [r2, #40]	@ 0x28
 8002bb0:	4921      	ldr	r1, [pc, #132]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002bb2:	f891 1029 	ldrb.w	r1, [r1, #41]	@ 0x29
 8002bb6:	9104      	str	r1, [sp, #16]
 8002bb8:	9203      	str	r2, [sp, #12]
 8002bba:	2200      	movs	r2, #0
 8002bbc:	9202      	str	r2, [sp, #8]
 8002bbe:	2200      	movs	r2, #0
 8002bc0:	9201      	str	r2, [sp, #4]
 8002bc2:	9300      	str	r3, [sp, #0]
 8002bc4:	2304      	movs	r3, #4
 8002bc6:	2200      	movs	r2, #0
 8002bc8:	491d      	ldr	r1, [pc, #116]	@ (8002c40 <LimiterSwitchTask+0x1e4>)
 8002bca:	481e      	ldr	r0, [pc, #120]	@ (8002c44 <LimiterSwitchTask+0x1e8>)
 8002bcc:	f000 f92a 	bl	8002e24 <motorControl>
 8002bd0:	4603      	mov	r3, r0
 8002bd2:	461a      	mov	r2, r3
 8002bd4:	4b18      	ldr	r3, [pc, #96]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002bd6:	751a      	strb	r2, [r3, #20]
            }
            if ((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) {
 8002bd8:	4b17      	ldr	r3, [pc, #92]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002bda:	f893 302c 	ldrb.w	r3, [r3, #44]	@ 0x2c
 8002bde:	2b01      	cmp	r3, #1
 8002be0:	d004      	beq.n	8002bec <LimiterSwitchTask+0x190>
 8002be2:	4b15      	ldr	r3, [pc, #84]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002be4:	f893 302b 	ldrb.w	r3, [r3, #43]	@ 0x2b
 8002be8:	2b01      	cmp	r3, #1
 8002bea:	d118      	bne.n	8002c1e <LimiterSwitchTask+0x1c2>
                sensorsInfo.motorYStatus = motorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown);
 8002bec:	4b16      	ldr	r3, [pc, #88]	@ (8002c48 <LimiterSwitchTask+0x1ec>)
 8002bee:	681b      	ldr	r3, [r3, #0]
 8002bf0:	4a11      	ldr	r2, [pc, #68]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002bf2:	f892 202b 	ldrb.w	r2, [r2, #43]	@ 0x2b
 8002bf6:	4910      	ldr	r1, [pc, #64]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002bf8:	f891 102c 	ldrb.w	r1, [r1, #44]	@ 0x2c
 8002bfc:	9104      	str	r1, [sp, #16]
 8002bfe:	9203      	str	r2, [sp, #12]
 8002c00:	2200      	movs	r2, #0
 8002c02:	9202      	str	r2, [sp, #8]
 8002c04:	2200      	movs	r2, #0
 8002c06:	9201      	str	r2, [sp, #4]
 8002c08:	9300      	str	r3, [sp, #0]
 8002c0a:	230c      	movs	r3, #12
 8002c0c:	2208      	movs	r2, #8
 8002c0e:	490c      	ldr	r1, [pc, #48]	@ (8002c40 <LimiterSwitchTask+0x1e4>)
 8002c10:	480c      	ldr	r0, [pc, #48]	@ (8002c44 <LimiterSwitchTask+0x1e8>)
 8002c12:	f000 f907 	bl	8002e24 <motorControl>
 8002c16:	4603      	mov	r3, r0
 8002c18:	461a      	mov	r2, r3
 8002c1a:	4b07      	ldr	r3, [pc, #28]	@ (8002c38 <LimiterSwitchTask+0x1dc>)
 8002c1c:	755a      	strb	r2, [r3, #21]
            }
            osMutexRelease (sensorsInfoMutex);
 8002c1e:	4b05      	ldr	r3, [pc, #20]	@ (8002c34 <LimiterSwitchTask+0x1d8>)
 8002c20:	681b      	ldr	r3, [r3, #0]
 8002c22:	4618      	mov	r0, r3
 8002c24:	f010 ffd2 	bl	8013bcc <osMutexRelease>
        osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever);
 8002c28:	e73d      	b.n	8002aa6 <LimiterSwitchTask+0x4a>
 8002c2a:	bf00      	nop
 8002c2c:	58020c00 	.word	0x58020c00
 8002c30:	240007d4 	.word	0x240007d4
 8002c34:	240007e8 	.word	0x240007e8
 8002c38:	2400082c 	.word	0x2400082c
 8002c3c:	24000708 	.word	0x24000708
 8002c40:	24000784 	.word	0x24000784
 8002c44:	240004e4 	.word	0x240004e4
 8002c48:	24000738 	.word	0x24000738

08002c4c <EncoderTask>:
        }
    }
}

void EncoderTask (void* arg) {
 8002c4c:	b580      	push	{r7, lr}
 8002c4e:	b084      	sub	sp, #16
 8002c50:	af00      	add	r7, sp, #0
 8002c52:	6078      	str	r0, [r7, #4]
    EncoderData encoderData         = { 0 };
 8002c54:	2300      	movs	r3, #0
 8002c56:	813b      	strh	r3, [r7, #8]
    osMessageQueueId_t encoderQueue = (osMessageQueueId_t)arg;
 8002c58:	687b      	ldr	r3, [r7, #4]
 8002c5a:	60fb      	str	r3, [r7, #12]
    while (pdTRUE) {
        osMessageQueueGet (encoderQueue, &encoderData, 0, osWaitForever);
 8002c5c:	f107 0108 	add.w	r1, r7, #8
 8002c60:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8002c64:	2200      	movs	r2, #0
 8002c66:	68f8      	ldr	r0, [r7, #12]
 8002c68:	f011 f8c0 	bl	8013dec <osMessageQueueGet>
        if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
 8002c6c:	4b24      	ldr	r3, [pc, #144]	@ (8002d00 <EncoderTask+0xb4>)
 8002c6e:	681b      	ldr	r3, [r3, #0]
 8002c70:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8002c74:	4618      	mov	r0, r3
 8002c76:	f010 ff5e 	bl	8013b36 <osMutexAcquire>
 8002c7a:	4603      	mov	r3, r0
 8002c7c:	2b00      	cmp	r3, #0
 8002c7e:	d1ed      	bne.n	8002c5c <EncoderTask+0x10>
            if (encoderData.axe == encoderAxeX) {
 8002c80:	7a3b      	ldrb	r3, [r7, #8]
 8002c82:	2b00      	cmp	r3, #0
 8002c84:	d11b      	bne.n	8002cbe <EncoderTask+0x72>
                if (encoderData.direction == encoderCW) {
 8002c86:	7a7b      	ldrb	r3, [r7, #9]
 8002c88:	2b00      	cmp	r3, #0
 8002c8a:	d10a      	bne.n	8002ca2 <EncoderTask+0x56>
                    sensorsInfo.pvEncoderX += 360.0 / ENCODER_X_IMP_PER_TURN;
 8002c8c:	4b1d      	ldr	r3, [pc, #116]	@ (8002d04 <EncoderTask+0xb8>)
 8002c8e:	edd3 7a03 	vldr	s15, [r3, #12]
 8002c92:	eeb3 7a02 	vmov.f32	s14, #50	@ 0x41900000  18.0
 8002c96:	ee77 7a87 	vadd.f32	s15, s15, s14
 8002c9a:	4b1a      	ldr	r3, [pc, #104]	@ (8002d04 <EncoderTask+0xb8>)
 8002c9c:	edc3 7a03 	vstr	s15, [r3, #12]
 8002ca0:	e009      	b.n	8002cb6 <EncoderTask+0x6a>
                } else {
                    sensorsInfo.pvEncoderX -= 360.0 / ENCODER_X_IMP_PER_TURN;
 8002ca2:	4b18      	ldr	r3, [pc, #96]	@ (8002d04 <EncoderTask+0xb8>)
 8002ca4:	edd3 7a03 	vldr	s15, [r3, #12]
 8002ca8:	eeb3 7a02 	vmov.f32	s14, #50	@ 0x41900000  18.0
 8002cac:	ee77 7ac7 	vsub.f32	s15, s15, s14
 8002cb0:	4b14      	ldr	r3, [pc, #80]	@ (8002d04 <EncoderTask+0xb8>)
 8002cb2:	edc3 7a03 	vstr	s15, [r3, #12]
                }
                DbgLEDToggle(DBG_LED2);
 8002cb6:	2020      	movs	r0, #32
 8002cb8:	f000 f84a 	bl	8002d50 <DbgLEDToggle>
 8002cbc:	e01a      	b.n	8002cf4 <EncoderTask+0xa8>
            } else {
                if (encoderData.direction == encoderCW) {
 8002cbe:	7a7b      	ldrb	r3, [r7, #9]
 8002cc0:	2b00      	cmp	r3, #0
 8002cc2:	d10a      	bne.n	8002cda <EncoderTask+0x8e>
                    sensorsInfo.pvEncoderY += 360.0 / ENCODER_Y_IMP_PER_TURN;
 8002cc4:	4b0f      	ldr	r3, [pc, #60]	@ (8002d04 <EncoderTask+0xb8>)
 8002cc6:	edd3 7a04 	vldr	s15, [r3, #16]
 8002cca:	eeb3 7a02 	vmov.f32	s14, #50	@ 0x41900000  18.0
 8002cce:	ee77 7a87 	vadd.f32	s15, s15, s14
 8002cd2:	4b0c      	ldr	r3, [pc, #48]	@ (8002d04 <EncoderTask+0xb8>)
 8002cd4:	edc3 7a04 	vstr	s15, [r3, #16]
 8002cd8:	e009      	b.n	8002cee <EncoderTask+0xa2>
                } else {
                    sensorsInfo.pvEncoderY -= 360.0 / ENCODER_Y_IMP_PER_TURN;
 8002cda:	4b0a      	ldr	r3, [pc, #40]	@ (8002d04 <EncoderTask+0xb8>)
 8002cdc:	edd3 7a04 	vldr	s15, [r3, #16]
 8002ce0:	eeb3 7a02 	vmov.f32	s14, #50	@ 0x41900000  18.0
 8002ce4:	ee77 7ac7 	vsub.f32	s15, s15, s14
 8002ce8:	4b06      	ldr	r3, [pc, #24]	@ (8002d04 <EncoderTask+0xb8>)
 8002cea:	edc3 7a04 	vstr	s15, [r3, #16]
                }
                DbgLEDToggle(DBG_LED3);
 8002cee:	2040      	movs	r0, #64	@ 0x40
 8002cf0:	f000 f82e 	bl	8002d50 <DbgLEDToggle>
            }
            osMutexRelease (sensorsInfoMutex);
 8002cf4:	4b02      	ldr	r3, [pc, #8]	@ (8002d00 <EncoderTask+0xb4>)
 8002cf6:	681b      	ldr	r3, [r3, #0]
 8002cf8:	4618      	mov	r0, r3
 8002cfa:	f010 ff67 	bl	8013bcc <osMutexRelease>
        osMessageQueueGet (encoderQueue, &encoderData, 0, osWaitForever);
 8002cfe:	e7ad      	b.n	8002c5c <EncoderTask+0x10>
 8002d00:	240007e8 	.word	0x240007e8
 8002d04:	2400082c 	.word	0x2400082c

08002d08 <DbgLEDOn>:

#include <stdlib.h>

#include "peripherial.h"

void DbgLEDOn (uint8_t ledNumber) {
 8002d08:	b580      	push	{r7, lr}
 8002d0a:	b082      	sub	sp, #8
 8002d0c:	af00      	add	r7, sp, #0
 8002d0e:	4603      	mov	r3, r0
 8002d10:	71fb      	strb	r3, [r7, #7]
    HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_SET);
 8002d12:	79fb      	ldrb	r3, [r7, #7]
 8002d14:	b29b      	uxth	r3, r3
 8002d16:	2201      	movs	r2, #1
 8002d18:	4619      	mov	r1, r3
 8002d1a:	4803      	ldr	r0, [pc, #12]	@ (8002d28 <DbgLEDOn+0x20>)
 8002d1c:	f007 ff2e 	bl	800ab7c <HAL_GPIO_WritePin>
}
 8002d20:	bf00      	nop
 8002d22:	3708      	adds	r7, #8
 8002d24:	46bd      	mov	sp, r7
 8002d26:	bd80      	pop	{r7, pc}
 8002d28:	58020c00 	.word	0x58020c00

08002d2c <DbgLEDOff>:

void DbgLEDOff (uint8_t ledNumber) {
 8002d2c:	b580      	push	{r7, lr}
 8002d2e:	b082      	sub	sp, #8
 8002d30:	af00      	add	r7, sp, #0
 8002d32:	4603      	mov	r3, r0
 8002d34:	71fb      	strb	r3, [r7, #7]
    HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_RESET);
 8002d36:	79fb      	ldrb	r3, [r7, #7]
 8002d38:	b29b      	uxth	r3, r3
 8002d3a:	2200      	movs	r2, #0
 8002d3c:	4619      	mov	r1, r3
 8002d3e:	4803      	ldr	r0, [pc, #12]	@ (8002d4c <DbgLEDOff+0x20>)
 8002d40:	f007 ff1c 	bl	800ab7c <HAL_GPIO_WritePin>
}
 8002d44:	bf00      	nop
 8002d46:	3708      	adds	r7, #8
 8002d48:	46bd      	mov	sp, r7
 8002d4a:	bd80      	pop	{r7, pc}
 8002d4c:	58020c00 	.word	0x58020c00

08002d50 <DbgLEDToggle>:

void DbgLEDToggle (uint8_t ledNumber) {
 8002d50:	b580      	push	{r7, lr}
 8002d52:	b082      	sub	sp, #8
 8002d54:	af00      	add	r7, sp, #0
 8002d56:	4603      	mov	r3, r0
 8002d58:	71fb      	strb	r3, [r7, #7]
    HAL_GPIO_TogglePin (GPIOD, ledNumber);
 8002d5a:	79fb      	ldrb	r3, [r7, #7]
 8002d5c:	b29b      	uxth	r3, r3
 8002d5e:	4619      	mov	r1, r3
 8002d60:	4803      	ldr	r0, [pc, #12]	@ (8002d70 <DbgLEDToggle+0x20>)
 8002d62:	f007 ff24 	bl	800abae <HAL_GPIO_TogglePin>
}
 8002d66:	bf00      	nop
 8002d68:	3708      	adds	r7, #8
 8002d6a:	46bd      	mov	sp, r7
 8002d6c:	bd80      	pop	{r7, pc}
 8002d6e:	bf00      	nop
 8002d70:	58020c00 	.word	0x58020c00

08002d74 <EnableCurrentSensors>:

void EnableCurrentSensors (void) {
 8002d74:	b580      	push	{r7, lr}
 8002d76:	af00      	add	r7, sp, #0
    HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_SET);
 8002d78:	2201      	movs	r2, #1
 8002d7a:	f44f 4100 	mov.w	r1, #32768	@ 0x8000
 8002d7e:	4802      	ldr	r0, [pc, #8]	@ (8002d88 <EnableCurrentSensors+0x14>)
 8002d80:	f007 fefc 	bl	800ab7c <HAL_GPIO_WritePin>
}
 8002d84:	bf00      	nop
 8002d86:	bd80      	pop	{r7, pc}
 8002d88:	58021000 	.word	0x58021000

08002d8c <SelectCurrentSensorGain>:

void DisableCurrentSensors (void) {
    HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_RESET);
}

void SelectCurrentSensorGain (CurrentSensor sensor, CurrentSensorGain gain) {
 8002d8c:	b580      	push	{r7, lr}
 8002d8e:	b084      	sub	sp, #16
 8002d90:	af00      	add	r7, sp, #0
 8002d92:	4603      	mov	r3, r0
 8002d94:	460a      	mov	r2, r1
 8002d96:	71fb      	strb	r3, [r7, #7]
 8002d98:	4613      	mov	r3, r2
 8002d9a:	71bb      	strb	r3, [r7, #6]
    uint8_t gpioOffset = 0;
 8002d9c:	2300      	movs	r3, #0
 8002d9e:	73fb      	strb	r3, [r7, #15]
    switch (sensor) {
 8002da0:	79fb      	ldrb	r3, [r7, #7]
 8002da2:	2b02      	cmp	r3, #2
 8002da4:	d00c      	beq.n	8002dc0 <SelectCurrentSensorGain+0x34>
 8002da6:	2b02      	cmp	r3, #2
 8002da8:	dc0d      	bgt.n	8002dc6 <SelectCurrentSensorGain+0x3a>
 8002daa:	2b00      	cmp	r3, #0
 8002dac:	d002      	beq.n	8002db4 <SelectCurrentSensorGain+0x28>
 8002dae:	2b01      	cmp	r3, #1
 8002db0:	d003      	beq.n	8002dba <SelectCurrentSensorGain+0x2e>
    case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break;
    case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break;
    case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break;
    default: break;
 8002db2:	e008      	b.n	8002dc6 <SelectCurrentSensorGain+0x3a>
    case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break;
 8002db4:	2307      	movs	r3, #7
 8002db6:	73fb      	strb	r3, [r7, #15]
 8002db8:	e006      	b.n	8002dc8 <SelectCurrentSensorGain+0x3c>
    case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break;
 8002dba:	2309      	movs	r3, #9
 8002dbc:	73fb      	strb	r3, [r7, #15]
 8002dbe:	e003      	b.n	8002dc8 <SelectCurrentSensorGain+0x3c>
    case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break;
 8002dc0:	230d      	movs	r3, #13
 8002dc2:	73fb      	strb	r3, [r7, #15]
 8002dc4:	e000      	b.n	8002dc8 <SelectCurrentSensorGain+0x3c>
    default: break;
 8002dc6:	bf00      	nop
    }
    if (gpioOffset > 0) {
 8002dc8:	7bfb      	ldrb	r3, [r7, #15]
 8002dca:	2b00      	cmp	r3, #0
 8002dcc:	d023      	beq.n	8002e16 <SelectCurrentSensorGain+0x8a>
        uint16_t gain0Gpio = 1 << gpioOffset;
 8002dce:	7bfb      	ldrb	r3, [r7, #15]
 8002dd0:	2201      	movs	r2, #1
 8002dd2:	fa02 f303 	lsl.w	r3, r2, r3
 8002dd6:	81bb      	strh	r3, [r7, #12]
        uint16_t gain1Gpio = 1 << (gpioOffset + 1);
 8002dd8:	7bfb      	ldrb	r3, [r7, #15]
 8002dda:	3301      	adds	r3, #1
 8002ddc:	2201      	movs	r2, #1
 8002dde:	fa02 f303 	lsl.w	r3, r2, r3
 8002de2:	817b      	strh	r3, [r7, #10]
        uint16_t gpioState = ((uint16_t)gain) & 0x0001;
 8002de4:	79bb      	ldrb	r3, [r7, #6]
 8002de6:	b29b      	uxth	r3, r3
 8002de8:	f003 0301 	and.w	r3, r3, #1
 8002dec:	813b      	strh	r3, [r7, #8]
        HAL_GPIO_WritePin (GPIOE, gain0Gpio, gpioState);
 8002dee:	893b      	ldrh	r3, [r7, #8]
 8002df0:	b2da      	uxtb	r2, r3
 8002df2:	89bb      	ldrh	r3, [r7, #12]
 8002df4:	4619      	mov	r1, r3
 8002df6:	480a      	ldr	r0, [pc, #40]	@ (8002e20 <SelectCurrentSensorGain+0x94>)
 8002df8:	f007 fec0 	bl	800ab7c <HAL_GPIO_WritePin>
        gpioState = (((uint16_t)gain) >> 1) & 0x0001;
 8002dfc:	79bb      	ldrb	r3, [r7, #6]
 8002dfe:	085b      	lsrs	r3, r3, #1
 8002e00:	b2db      	uxtb	r3, r3
 8002e02:	f003 0301 	and.w	r3, r3, #1
 8002e06:	813b      	strh	r3, [r7, #8]
        HAL_GPIO_WritePin (GPIOE, gain1Gpio, gpioState);
 8002e08:	893b      	ldrh	r3, [r7, #8]
 8002e0a:	b2da      	uxtb	r2, r3
 8002e0c:	897b      	ldrh	r3, [r7, #10]
 8002e0e:	4619      	mov	r1, r3
 8002e10:	4803      	ldr	r0, [pc, #12]	@ (8002e20 <SelectCurrentSensorGain+0x94>)
 8002e12:	f007 feb3 	bl	800ab7c <HAL_GPIO_WritePin>
    }
}
 8002e16:	bf00      	nop
 8002e18:	3710      	adds	r7, #16
 8002e1a:	46bd      	mov	sp, r7
 8002e1c:	bd80      	pop	{r7, pc}
 8002e1e:	bf00      	nop
 8002e20:	58021000 	.word	0x58021000

08002e24 <motorControl>:

uint8_t
motorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) {
 8002e24:	b580      	push	{r7, lr}
 8002e26:	b088      	sub	sp, #32
 8002e28:	af02      	add	r7, sp, #8
 8002e2a:	60f8      	str	r0, [r7, #12]
 8002e2c:	60b9      	str	r1, [r7, #8]
 8002e2e:	4611      	mov	r1, r2
 8002e30:	461a      	mov	r2, r3
 8002e32:	460b      	mov	r3, r1
 8002e34:	71fb      	strb	r3, [r7, #7]
 8002e36:	4613      	mov	r3, r2
 8002e38:	71bb      	strb	r3, [r7, #6]
    uint32_t motorStatus            = 0;
 8002e3a:	2300      	movs	r3, #0
 8002e3c:	617b      	str	r3, [r7, #20]
    MotorDriverState setMotorYState = HiZ;
 8002e3e:	2300      	movs	r3, #0
 8002e40:	74fb      	strb	r3, [r7, #19]

    HAL_TIM_PWM_Stop (htim, channel1);
 8002e42:	79fb      	ldrb	r3, [r7, #7]
 8002e44:	4619      	mov	r1, r3
 8002e46:	68f8      	ldr	r0, [r7, #12]
 8002e48:	f00c f842 	bl	800eed0 <HAL_TIM_PWM_Stop>
    HAL_TIM_PWM_Stop (htim, channel2);
 8002e4c:	79bb      	ldrb	r3, [r7, #6]
 8002e4e:	4619      	mov	r1, r3
 8002e50:	68f8      	ldr	r0, [r7, #12]
 8002e52:	f00c f83d 	bl	800eed0 <HAL_TIM_PWM_Stop>
    if (motorTimerPeriod > 0) {
 8002e56:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8002e58:	2b00      	cmp	r3, #0
 8002e5a:	f340 808c 	ble.w	8002f76 <motorControl+0x152>
        if (motorPWMPulse > 0) {
 8002e5e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8002e60:	2b00      	cmp	r3, #0
 8002e62:	dd2c      	ble.n	8002ebe <motorControl+0x9a>
            // Forward
            if (switchLimiterUpStat == 0) {
 8002e64:	f897 302c 	ldrb.w	r3, [r7, #44]	@ 0x2c
 8002e68:	2b00      	cmp	r3, #0
 8002e6a:	d11d      	bne.n	8002ea8 <motorControl+0x84>
                setMotorYState = Forward;
 8002e6c:	2301      	movs	r3, #1
 8002e6e:	74fb      	strb	r3, [r7, #19]
                motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10);
 8002e70:	79f9      	ldrb	r1, [r7, #7]
 8002e72:	79b8      	ldrb	r0, [r7, #6]
 8002e74:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8002e76:	ea83 72e3 	eor.w	r2, r3, r3, asr #31
 8002e7a:	eba2 72e3 	sub.w	r2, r2, r3, asr #31
 8002e7e:	4613      	mov	r3, r2
 8002e80:	009b      	lsls	r3, r3, #2
 8002e82:	4413      	add	r3, r2
 8002e84:	005b      	lsls	r3, r3, #1
 8002e86:	9301      	str	r3, [sp, #4]
 8002e88:	7cfb      	ldrb	r3, [r7, #19]
 8002e8a:	9300      	str	r3, [sp, #0]
 8002e8c:	4603      	mov	r3, r0
 8002e8e:	460a      	mov	r2, r1
 8002e90:	68b9      	ldr	r1, [r7, #8]
 8002e92:	68f8      	ldr	r0, [r7, #12]
 8002e94:	f000 f8ff 	bl	8003096 <motorAction>
                HAL_TIM_PWM_Start (htim, channel1);
 8002e98:	79fb      	ldrb	r3, [r7, #7]
 8002e9a:	4619      	mov	r1, r3
 8002e9c:	68f8      	ldr	r0, [r7, #12]
 8002e9e:	f00b ff09 	bl	800ecb4 <HAL_TIM_PWM_Start>
                motorStatus = 1;
 8002ea2:	2301      	movs	r3, #1
 8002ea4:	617b      	str	r3, [r7, #20]
 8002ea6:	e004      	b.n	8002eb2 <motorControl+0x8e>
            } else {
                HAL_TIM_PWM_Stop (htim, channel1);
 8002ea8:	79fb      	ldrb	r3, [r7, #7]
 8002eaa:	4619      	mov	r1, r3
 8002eac:	68f8      	ldr	r0, [r7, #12]
 8002eae:	f00c f80f 	bl	800eed0 <HAL_TIM_PWM_Stop>
            }
            HAL_TIM_PWM_Stop (htim, channel2);
 8002eb2:	79bb      	ldrb	r3, [r7, #6]
 8002eb4:	4619      	mov	r1, r3
 8002eb6:	68f8      	ldr	r0, [r7, #12]
 8002eb8:	f00c f80a 	bl	800eed0 <HAL_TIM_PWM_Stop>
 8002ebc:	e051      	b.n	8002f62 <motorControl+0x13e>
        } else if (motorPWMPulse < 0) {
 8002ebe:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8002ec0:	2b00      	cmp	r3, #0
 8002ec2:	da2c      	bge.n	8002f1e <motorControl+0xfa>
            // Reverse
            if (switchLimiterDownStat == 0) {
 8002ec4:	f897 3030 	ldrb.w	r3, [r7, #48]	@ 0x30
 8002ec8:	2b00      	cmp	r3, #0
 8002eca:	d11d      	bne.n	8002f08 <motorControl+0xe4>
                setMotorYState = Reverse;
 8002ecc:	2302      	movs	r3, #2
 8002ece:	74fb      	strb	r3, [r7, #19]
                motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10);
 8002ed0:	79f9      	ldrb	r1, [r7, #7]
 8002ed2:	79b8      	ldrb	r0, [r7, #6]
 8002ed4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8002ed6:	ea83 72e3 	eor.w	r2, r3, r3, asr #31
 8002eda:	eba2 72e3 	sub.w	r2, r2, r3, asr #31
 8002ede:	4613      	mov	r3, r2
 8002ee0:	009b      	lsls	r3, r3, #2
 8002ee2:	4413      	add	r3, r2
 8002ee4:	005b      	lsls	r3, r3, #1
 8002ee6:	9301      	str	r3, [sp, #4]
 8002ee8:	7cfb      	ldrb	r3, [r7, #19]
 8002eea:	9300      	str	r3, [sp, #0]
 8002eec:	4603      	mov	r3, r0
 8002eee:	460a      	mov	r2, r1
 8002ef0:	68b9      	ldr	r1, [r7, #8]
 8002ef2:	68f8      	ldr	r0, [r7, #12]
 8002ef4:	f000 f8cf 	bl	8003096 <motorAction>
                HAL_TIM_PWM_Start (htim, channel2);
 8002ef8:	79bb      	ldrb	r3, [r7, #6]
 8002efa:	4619      	mov	r1, r3
 8002efc:	68f8      	ldr	r0, [r7, #12]
 8002efe:	f00b fed9 	bl	800ecb4 <HAL_TIM_PWM_Start>
                motorStatus = 1;
 8002f02:	2301      	movs	r3, #1
 8002f04:	617b      	str	r3, [r7, #20]
 8002f06:	e004      	b.n	8002f12 <motorControl+0xee>
            } else {
                HAL_TIM_PWM_Stop (htim, channel2);
 8002f08:	79bb      	ldrb	r3, [r7, #6]
 8002f0a:	4619      	mov	r1, r3
 8002f0c:	68f8      	ldr	r0, [r7, #12]
 8002f0e:	f00b ffdf 	bl	800eed0 <HAL_TIM_PWM_Stop>
            }
            HAL_TIM_PWM_Stop (htim, channel1);
 8002f12:	79fb      	ldrb	r3, [r7, #7]
 8002f14:	4619      	mov	r1, r3
 8002f16:	68f8      	ldr	r0, [r7, #12]
 8002f18:	f00b ffda 	bl	800eed0 <HAL_TIM_PWM_Stop>
 8002f1c:	e021      	b.n	8002f62 <motorControl+0x13e>
        } else {
            // Brake
            setMotorYState = Brake;
 8002f1e:	2303      	movs	r3, #3
 8002f20:	74fb      	strb	r3, [r7, #19]
            motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10);
 8002f22:	79f9      	ldrb	r1, [r7, #7]
 8002f24:	79b8      	ldrb	r0, [r7, #6]
 8002f26:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8002f28:	ea83 72e3 	eor.w	r2, r3, r3, asr #31
 8002f2c:	eba2 72e3 	sub.w	r2, r2, r3, asr #31
 8002f30:	4613      	mov	r3, r2
 8002f32:	009b      	lsls	r3, r3, #2
 8002f34:	4413      	add	r3, r2
 8002f36:	005b      	lsls	r3, r3, #1
 8002f38:	9301      	str	r3, [sp, #4]
 8002f3a:	7cfb      	ldrb	r3, [r7, #19]
 8002f3c:	9300      	str	r3, [sp, #0]
 8002f3e:	4603      	mov	r3, r0
 8002f40:	460a      	mov	r2, r1
 8002f42:	68b9      	ldr	r1, [r7, #8]
 8002f44:	68f8      	ldr	r0, [r7, #12]
 8002f46:	f000 f8a6 	bl	8003096 <motorAction>
            HAL_TIM_PWM_Start (htim, channel1);
 8002f4a:	79fb      	ldrb	r3, [r7, #7]
 8002f4c:	4619      	mov	r1, r3
 8002f4e:	68f8      	ldr	r0, [r7, #12]
 8002f50:	f00b feb0 	bl	800ecb4 <HAL_TIM_PWM_Start>
            HAL_TIM_PWM_Start (htim, channel2);
 8002f54:	79bb      	ldrb	r3, [r7, #6]
 8002f56:	4619      	mov	r1, r3
 8002f58:	68f8      	ldr	r0, [r7, #12]
 8002f5a:	f00b feab 	bl	800ecb4 <HAL_TIM_PWM_Start>
            motorStatus = 0;
 8002f5e:	2300      	movs	r3, #0
 8002f60:	617b      	str	r3, [r7, #20]
        }
        osTimerStart (motorTimerHandle, motorTimerPeriod * 1000);
 8002f62:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8002f64:	f44f 727a 	mov.w	r2, #1000	@ 0x3e8
 8002f68:	fb02 f303 	mul.w	r3, r2, r3
 8002f6c:	4619      	mov	r1, r3
 8002f6e:	6a38      	ldr	r0, [r7, #32]
 8002f70:	f010 fcf6 	bl	8013960 <osTimerStart>
 8002f74:	e089      	b.n	800308a <motorControl+0x266>
    } else if ((motorTimerPeriod == 0) && (motorPWMPulse == 0)) {
 8002f76:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8002f78:	2b00      	cmp	r3, #0
 8002f7a:	d126      	bne.n	8002fca <motorControl+0x1a6>
 8002f7c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8002f7e:	2b00      	cmp	r3, #0
 8002f80:	d123      	bne.n	8002fca <motorControl+0x1a6>
        motorAction (htim, motorTimerConfigOC, channel1, channel2, HiZ, abs (motorPWMPulse) * 10);
 8002f82:	79f9      	ldrb	r1, [r7, #7]
 8002f84:	79b8      	ldrb	r0, [r7, #6]
 8002f86:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8002f88:	ea83 72e3 	eor.w	r2, r3, r3, asr #31
 8002f8c:	eba2 72e3 	sub.w	r2, r2, r3, asr #31
 8002f90:	4613      	mov	r3, r2
 8002f92:	009b      	lsls	r3, r3, #2
 8002f94:	4413      	add	r3, r2
 8002f96:	005b      	lsls	r3, r3, #1
 8002f98:	9301      	str	r3, [sp, #4]
 8002f9a:	2300      	movs	r3, #0
 8002f9c:	9300      	str	r3, [sp, #0]
 8002f9e:	4603      	mov	r3, r0
 8002fa0:	460a      	mov	r2, r1
 8002fa2:	68b9      	ldr	r1, [r7, #8]
 8002fa4:	68f8      	ldr	r0, [r7, #12]
 8002fa6:	f000 f876 	bl	8003096 <motorAction>
        HAL_TIM_PWM_Stop (htim, channel1);
 8002faa:	79fb      	ldrb	r3, [r7, #7]
 8002fac:	4619      	mov	r1, r3
 8002fae:	68f8      	ldr	r0, [r7, #12]
 8002fb0:	f00b ff8e 	bl	800eed0 <HAL_TIM_PWM_Stop>
        HAL_TIM_PWM_Stop (htim, channel2);
 8002fb4:	79bb      	ldrb	r3, [r7, #6]
 8002fb6:	4619      	mov	r1, r3
 8002fb8:	68f8      	ldr	r0, [r7, #12]
 8002fba:	f00b ff89 	bl	800eed0 <HAL_TIM_PWM_Stop>
        osTimerStop (motorTimerHandle);
 8002fbe:	6a38      	ldr	r0, [r7, #32]
 8002fc0:	f010 fcfc 	bl	80139bc <osTimerStop>
        motorStatus = 0;
 8002fc4:	2300      	movs	r3, #0
 8002fc6:	617b      	str	r3, [r7, #20]
 8002fc8:	e05f      	b.n	800308a <motorControl+0x266>
    } else if (motorTimerPeriod == -1) {
 8002fca:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8002fcc:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8002fd0:	d15b      	bne.n	800308a <motorControl+0x266>
        if (motorPWMPulse > 0) {
 8002fd2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8002fd4:	2b00      	cmp	r3, #0
 8002fd6:	dd2c      	ble.n	8003032 <motorControl+0x20e>
            // Forward
            if (switchLimiterUpStat == 0) {
 8002fd8:	f897 302c 	ldrb.w	r3, [r7, #44]	@ 0x2c
 8002fdc:	2b00      	cmp	r3, #0
 8002fde:	d11d      	bne.n	800301c <motorControl+0x1f8>
                setMotorYState = Forward;
 8002fe0:	2301      	movs	r3, #1
 8002fe2:	74fb      	strb	r3, [r7, #19]
                motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10);
 8002fe4:	79f9      	ldrb	r1, [r7, #7]
 8002fe6:	79b8      	ldrb	r0, [r7, #6]
 8002fe8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8002fea:	ea83 72e3 	eor.w	r2, r3, r3, asr #31
 8002fee:	eba2 72e3 	sub.w	r2, r2, r3, asr #31
 8002ff2:	4613      	mov	r3, r2
 8002ff4:	009b      	lsls	r3, r3, #2
 8002ff6:	4413      	add	r3, r2
 8002ff8:	005b      	lsls	r3, r3, #1
 8002ffa:	9301      	str	r3, [sp, #4]
 8002ffc:	7cfb      	ldrb	r3, [r7, #19]
 8002ffe:	9300      	str	r3, [sp, #0]
 8003000:	4603      	mov	r3, r0
 8003002:	460a      	mov	r2, r1
 8003004:	68b9      	ldr	r1, [r7, #8]
 8003006:	68f8      	ldr	r0, [r7, #12]
 8003008:	f000 f845 	bl	8003096 <motorAction>
                HAL_TIM_PWM_Start (htim, channel1);
 800300c:	79fb      	ldrb	r3, [r7, #7]
 800300e:	4619      	mov	r1, r3
 8003010:	68f8      	ldr	r0, [r7, #12]
 8003012:	f00b fe4f 	bl	800ecb4 <HAL_TIM_PWM_Start>
                motorStatus = 1;
 8003016:	2301      	movs	r3, #1
 8003018:	617b      	str	r3, [r7, #20]
 800301a:	e004      	b.n	8003026 <motorControl+0x202>
            } else {
                HAL_TIM_PWM_Stop (htim, channel1);
 800301c:	79fb      	ldrb	r3, [r7, #7]
 800301e:	4619      	mov	r1, r3
 8003020:	68f8      	ldr	r0, [r7, #12]
 8003022:	f00b ff55 	bl	800eed0 <HAL_TIM_PWM_Stop>
            }
            HAL_TIM_PWM_Stop (htim, channel2);
 8003026:	79bb      	ldrb	r3, [r7, #6]
 8003028:	4619      	mov	r1, r3
 800302a:	68f8      	ldr	r0, [r7, #12]
 800302c:	f00b ff50 	bl	800eed0 <HAL_TIM_PWM_Stop>
 8003030:	e02b      	b.n	800308a <motorControl+0x266>
        } else {
            // Reverse
            if (switchLimiterDownStat == 0) {
 8003032:	f897 3030 	ldrb.w	r3, [r7, #48]	@ 0x30
 8003036:	2b00      	cmp	r3, #0
 8003038:	d11d      	bne.n	8003076 <motorControl+0x252>
                setMotorYState = Reverse;
 800303a:	2302      	movs	r3, #2
 800303c:	74fb      	strb	r3, [r7, #19]
                motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10);
 800303e:	79f9      	ldrb	r1, [r7, #7]
 8003040:	79b8      	ldrb	r0, [r7, #6]
 8003042:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8003044:	ea83 72e3 	eor.w	r2, r3, r3, asr #31
 8003048:	eba2 72e3 	sub.w	r2, r2, r3, asr #31
 800304c:	4613      	mov	r3, r2
 800304e:	009b      	lsls	r3, r3, #2
 8003050:	4413      	add	r3, r2
 8003052:	005b      	lsls	r3, r3, #1
 8003054:	9301      	str	r3, [sp, #4]
 8003056:	7cfb      	ldrb	r3, [r7, #19]
 8003058:	9300      	str	r3, [sp, #0]
 800305a:	4603      	mov	r3, r0
 800305c:	460a      	mov	r2, r1
 800305e:	68b9      	ldr	r1, [r7, #8]
 8003060:	68f8      	ldr	r0, [r7, #12]
 8003062:	f000 f818 	bl	8003096 <motorAction>
                HAL_TIM_PWM_Start (htim, channel2);
 8003066:	79bb      	ldrb	r3, [r7, #6]
 8003068:	4619      	mov	r1, r3
 800306a:	68f8      	ldr	r0, [r7, #12]
 800306c:	f00b fe22 	bl	800ecb4 <HAL_TIM_PWM_Start>
                motorStatus = 1;
 8003070:	2301      	movs	r3, #1
 8003072:	617b      	str	r3, [r7, #20]
 8003074:	e004      	b.n	8003080 <motorControl+0x25c>
            } else {
                HAL_TIM_PWM_Stop (htim, channel2);
 8003076:	79bb      	ldrb	r3, [r7, #6]
 8003078:	4619      	mov	r1, r3
 800307a:	68f8      	ldr	r0, [r7, #12]
 800307c:	f00b ff28 	bl	800eed0 <HAL_TIM_PWM_Stop>
            }
            HAL_TIM_PWM_Stop (htim, channel1);
 8003080:	79fb      	ldrb	r3, [r7, #7]
 8003082:	4619      	mov	r1, r3
 8003084:	68f8      	ldr	r0, [r7, #12]
 8003086:	f00b ff23 	bl	800eed0 <HAL_TIM_PWM_Stop>
        }
    }
    return motorStatus;
 800308a:	697b      	ldr	r3, [r7, #20]
 800308c:	b2db      	uxtb	r3, r3
}
 800308e:	4618      	mov	r0, r3
 8003090:	3718      	adds	r7, #24
 8003092:	46bd      	mov	sp, r7
 8003094:	bd80      	pop	{r7, pc}

08003096 <motorAction>:

void motorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) {
 8003096:	b580      	push	{r7, lr}
 8003098:	b084      	sub	sp, #16
 800309a:	af00      	add	r7, sp, #0
 800309c:	60f8      	str	r0, [r7, #12]
 800309e:	60b9      	str	r1, [r7, #8]
 80030a0:	607a      	str	r2, [r7, #4]
 80030a2:	603b      	str	r3, [r7, #0]
    timerConf->Pulse = pulse;
 80030a4:	68bb      	ldr	r3, [r7, #8]
 80030a6:	69fa      	ldr	r2, [r7, #28]
 80030a8:	605a      	str	r2, [r3, #4]
    switch (setState) {
 80030aa:	7e3b      	ldrb	r3, [r7, #24]
 80030ac:	2b02      	cmp	r3, #2
 80030ae:	dc02      	bgt.n	80030b6 <motorAction+0x20>
 80030b0:	2b00      	cmp	r3, #0
 80030b2:	da03      	bge.n	80030bc <motorAction+0x26>
 80030b4:	e038      	b.n	8003128 <motorAction+0x92>
 80030b6:	2b03      	cmp	r3, #3
 80030b8:	d01b      	beq.n	80030f2 <motorAction+0x5c>
 80030ba:	e035      	b.n	8003128 <motorAction+0x92>
    case Forward:
    case Reverse:
    case HiZ:
        timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
 80030bc:	68bb      	ldr	r3, [r7, #8]
 80030be:	2200      	movs	r2, #0
 80030c0:	609a      	str	r2, [r3, #8]
        if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
 80030c2:	687a      	ldr	r2, [r7, #4]
 80030c4:	68b9      	ldr	r1, [r7, #8]
 80030c6:	68f8      	ldr	r0, [r7, #12]
 80030c8:	f00c faee 	bl	800f6a8 <HAL_TIM_PWM_ConfigChannel>
 80030cc:	4603      	mov	r3, r0
 80030ce:	2b00      	cmp	r3, #0
 80030d0:	d001      	beq.n	80030d6 <motorAction+0x40>
            Error_Handler ();
 80030d2:	f7fe feb3 	bl	8001e3c <Error_Handler>
        }
        timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
 80030d6:	68bb      	ldr	r3, [r7, #8]
 80030d8:	2200      	movs	r2, #0
 80030da:	609a      	str	r2, [r3, #8]
        if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
 80030dc:	683a      	ldr	r2, [r7, #0]
 80030de:	68b9      	ldr	r1, [r7, #8]
 80030e0:	68f8      	ldr	r0, [r7, #12]
 80030e2:	f00c fae1 	bl	800f6a8 <HAL_TIM_PWM_ConfigChannel>
 80030e6:	4603      	mov	r3, r0
 80030e8:	2b00      	cmp	r3, #0
 80030ea:	d038      	beq.n	800315e <motorAction+0xc8>
            Error_Handler ();
 80030ec:	f7fe fea6 	bl	8001e3c <Error_Handler>
        }
        break;
 80030f0:	e035      	b.n	800315e <motorAction+0xc8>
    case Brake:
        timerConf->OCPolarity = TIM_OCPOLARITY_LOW;
 80030f2:	68bb      	ldr	r3, [r7, #8]
 80030f4:	2202      	movs	r2, #2
 80030f6:	609a      	str	r2, [r3, #8]
        if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
 80030f8:	687a      	ldr	r2, [r7, #4]
 80030fa:	68b9      	ldr	r1, [r7, #8]
 80030fc:	68f8      	ldr	r0, [r7, #12]
 80030fe:	f00c fad3 	bl	800f6a8 <HAL_TIM_PWM_ConfigChannel>
 8003102:	4603      	mov	r3, r0
 8003104:	2b00      	cmp	r3, #0
 8003106:	d001      	beq.n	800310c <motorAction+0x76>
            Error_Handler ();
 8003108:	f7fe fe98 	bl	8001e3c <Error_Handler>
        }
        timerConf->OCPolarity = TIM_OCPOLARITY_LOW;
 800310c:	68bb      	ldr	r3, [r7, #8]
 800310e:	2202      	movs	r2, #2
 8003110:	609a      	str	r2, [r3, #8]
        if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
 8003112:	683a      	ldr	r2, [r7, #0]
 8003114:	68b9      	ldr	r1, [r7, #8]
 8003116:	68f8      	ldr	r0, [r7, #12]
 8003118:	f00c fac6 	bl	800f6a8 <HAL_TIM_PWM_ConfigChannel>
 800311c:	4603      	mov	r3, r0
 800311e:	2b00      	cmp	r3, #0
 8003120:	d01f      	beq.n	8003162 <motorAction+0xcc>
            Error_Handler ();
 8003122:	f7fe fe8b 	bl	8001e3c <Error_Handler>
        }
        break;
 8003126:	e01c      	b.n	8003162 <motorAction+0xcc>
    default:
        timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
 8003128:	68bb      	ldr	r3, [r7, #8]
 800312a:	2200      	movs	r2, #0
 800312c:	609a      	str	r2, [r3, #8]
        if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
 800312e:	687a      	ldr	r2, [r7, #4]
 8003130:	68b9      	ldr	r1, [r7, #8]
 8003132:	68f8      	ldr	r0, [r7, #12]
 8003134:	f00c fab8 	bl	800f6a8 <HAL_TIM_PWM_ConfigChannel>
 8003138:	4603      	mov	r3, r0
 800313a:	2b00      	cmp	r3, #0
 800313c:	d001      	beq.n	8003142 <motorAction+0xac>
            Error_Handler ();
 800313e:	f7fe fe7d 	bl	8001e3c <Error_Handler>
        }
        timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
 8003142:	68bb      	ldr	r3, [r7, #8]
 8003144:	2200      	movs	r2, #0
 8003146:	609a      	str	r2, [r3, #8]
        if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
 8003148:	683a      	ldr	r2, [r7, #0]
 800314a:	68b9      	ldr	r1, [r7, #8]
 800314c:	68f8      	ldr	r0, [r7, #12]
 800314e:	f00c faab 	bl	800f6a8 <HAL_TIM_PWM_ConfigChannel>
 8003152:	4603      	mov	r3, r0
 8003154:	2b00      	cmp	r3, #0
 8003156:	d006      	beq.n	8003166 <motorAction+0xd0>
            Error_Handler ();
 8003158:	f7fe fe70 	bl	8001e3c <Error_Handler>
        }
        break;
 800315c:	e003      	b.n	8003166 <motorAction+0xd0>
        break;
 800315e:	bf00      	nop
 8003160:	e002      	b.n	8003168 <motorAction+0xd2>
        break;
 8003162:	bf00      	nop
 8003164:	e000      	b.n	8003168 <motorAction+0xd2>
        break;
 8003166:	bf00      	nop
    }
}
 8003168:	bf00      	nop
 800316a:	3710      	adds	r7, #16
 800316c:	46bd      	mov	sp, r7
 800316e:	bd80      	pop	{r7, pc}

08003170 <WriteDataToBuffer>:
        buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF);
    }
    *buffPos = newBuffPos;
}

void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) {
 8003170:	b480      	push	{r7}
 8003172:	b089      	sub	sp, #36	@ 0x24
 8003174:	af00      	add	r7, sp, #0
 8003176:	60f8      	str	r0, [r7, #12]
 8003178:	60b9      	str	r1, [r7, #8]
 800317a:	607a      	str	r2, [r7, #4]
 800317c:	70fb      	strb	r3, [r7, #3]
    uint32_t* uDataPtr = data;
 800317e:	687b      	ldr	r3, [r7, #4]
 8003180:	61bb      	str	r3, [r7, #24]
    uint32_t uData     = *uDataPtr;
 8003182:	69bb      	ldr	r3, [r7, #24]
 8003184:	681b      	ldr	r3, [r3, #0]
 8003186:	617b      	str	r3, [r7, #20]
    uint8_t i          = 0;
 8003188:	2300      	movs	r3, #0
 800318a:	77fb      	strb	r3, [r7, #31]
    uint8_t newBuffPos = *buffPos;
 800318c:	68bb      	ldr	r3, [r7, #8]
 800318e:	881b      	ldrh	r3, [r3, #0]
 8003190:	77bb      	strb	r3, [r7, #30]
    for (i = 0; i < dataSize; i++) {
 8003192:	2300      	movs	r3, #0
 8003194:	77fb      	strb	r3, [r7, #31]
 8003196:	e00e      	b.n	80031b6 <WriteDataToBuffer+0x46>
        buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF);
 8003198:	7ffb      	ldrb	r3, [r7, #31]
 800319a:	00db      	lsls	r3, r3, #3
 800319c:	697a      	ldr	r2, [r7, #20]
 800319e:	40da      	lsrs	r2, r3
 80031a0:	7fbb      	ldrb	r3, [r7, #30]
 80031a2:	1c59      	adds	r1, r3, #1
 80031a4:	77b9      	strb	r1, [r7, #30]
 80031a6:	4619      	mov	r1, r3
 80031a8:	68fb      	ldr	r3, [r7, #12]
 80031aa:	440b      	add	r3, r1
 80031ac:	b2d2      	uxtb	r2, r2
 80031ae:	701a      	strb	r2, [r3, #0]
    for (i = 0; i < dataSize; i++) {
 80031b0:	7ffb      	ldrb	r3, [r7, #31]
 80031b2:	3301      	adds	r3, #1
 80031b4:	77fb      	strb	r3, [r7, #31]
 80031b6:	7ffa      	ldrb	r2, [r7, #31]
 80031b8:	78fb      	ldrb	r3, [r7, #3]
 80031ba:	429a      	cmp	r2, r3
 80031bc:	d3ec      	bcc.n	8003198 <WriteDataToBuffer+0x28>
    }
    *buffPos = newBuffPos;
 80031be:	7fbb      	ldrb	r3, [r7, #30]
 80031c0:	b29a      	uxth	r2, r3
 80031c2:	68bb      	ldr	r3, [r7, #8]
 80031c4:	801a      	strh	r2, [r3, #0]
}
 80031c6:	bf00      	nop
 80031c8:	3724      	adds	r7, #36	@ 0x24
 80031ca:	46bd      	mov	sp, r7
 80031cc:	f85d 7b04 	ldr.w	r7, [sp], #4
 80031d0:	4770      	bx	lr

080031d2 <ReadWordFromBufer>:
	*data = CONVERT_BYTES_TO_SHORT_WORD(&buff[*buffPos]);
	*buffPos += sizeof(uint16_t);
}

void ReadWordFromBufer(uint8_t* buff, uint16_t* buffPos, uint32_t* data)
{
 80031d2:	b480      	push	{r7}
 80031d4:	b085      	sub	sp, #20
 80031d6:	af00      	add	r7, sp, #0
 80031d8:	60f8      	str	r0, [r7, #12]
 80031da:	60b9      	str	r1, [r7, #8]
 80031dc:	607a      	str	r2, [r7, #4]
	*data = CONVERT_BYTES_TO_WORD(&buff[*buffPos]);
 80031de:	68bb      	ldr	r3, [r7, #8]
 80031e0:	881b      	ldrh	r3, [r3, #0]
 80031e2:	3303      	adds	r3, #3
 80031e4:	68fa      	ldr	r2, [r7, #12]
 80031e6:	4413      	add	r3, r2
 80031e8:	781b      	ldrb	r3, [r3, #0]
 80031ea:	061a      	lsls	r2, r3, #24
 80031ec:	68bb      	ldr	r3, [r7, #8]
 80031ee:	881b      	ldrh	r3, [r3, #0]
 80031f0:	3302      	adds	r3, #2
 80031f2:	68f9      	ldr	r1, [r7, #12]
 80031f4:	440b      	add	r3, r1
 80031f6:	781b      	ldrb	r3, [r3, #0]
 80031f8:	041b      	lsls	r3, r3, #16
 80031fa:	431a      	orrs	r2, r3
 80031fc:	68bb      	ldr	r3, [r7, #8]
 80031fe:	881b      	ldrh	r3, [r3, #0]
 8003200:	3301      	adds	r3, #1
 8003202:	68f9      	ldr	r1, [r7, #12]
 8003204:	440b      	add	r3, r1
 8003206:	781b      	ldrb	r3, [r3, #0]
 8003208:	021b      	lsls	r3, r3, #8
 800320a:	4313      	orrs	r3, r2
 800320c:	68ba      	ldr	r2, [r7, #8]
 800320e:	8812      	ldrh	r2, [r2, #0]
 8003210:	4611      	mov	r1, r2
 8003212:	68fa      	ldr	r2, [r7, #12]
 8003214:	440a      	add	r2, r1
 8003216:	7812      	ldrb	r2, [r2, #0]
 8003218:	4313      	orrs	r3, r2
 800321a:	461a      	mov	r2, r3
 800321c:	687b      	ldr	r3, [r7, #4]
 800321e:	601a      	str	r2, [r3, #0]
	*buffPos += sizeof(uint32_t);
 8003220:	68bb      	ldr	r3, [r7, #8]
 8003222:	881b      	ldrh	r3, [r3, #0]
 8003224:	3304      	adds	r3, #4
 8003226:	b29a      	uxth	r2, r3
 8003228:	68bb      	ldr	r3, [r7, #8]
 800322a:	801a      	strh	r2, [r3, #0]
}
 800322c:	bf00      	nop
 800322e:	3714      	adds	r7, #20
 8003230:	46bd      	mov	sp, r7
 8003232:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003236:	4770      	bx	lr

08003238 <PrepareRespFrame>:
    txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc);

    return txBufferPos;
}

uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) {
 8003238:	b580      	push	{r7, lr}
 800323a:	b084      	sub	sp, #16
 800323c:	af00      	add	r7, sp, #0
 800323e:	6078      	str	r0, [r7, #4]
 8003240:	4608      	mov	r0, r1
 8003242:	4611      	mov	r1, r2
 8003244:	461a      	mov	r2, r3
 8003246:	4603      	mov	r3, r0
 8003248:	807b      	strh	r3, [r7, #2]
 800324a:	460b      	mov	r3, r1
 800324c:	707b      	strb	r3, [r7, #1]
 800324e:	4613      	mov	r3, r2
 8003250:	703b      	strb	r3, [r7, #0]
    uint16_t crc         = 0;
 8003252:	2300      	movs	r3, #0
 8003254:	81bb      	strh	r3, [r7, #12]
    uint16_t txBufferPos = 0;
 8003256:	2300      	movs	r3, #0
 8003258:	81fb      	strh	r3, [r7, #14]
    uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response
 800325a:	787b      	ldrb	r3, [r7, #1]
 800325c:	b21a      	sxth	r2, r3
 800325e:	4b43      	ldr	r3, [pc, #268]	@ (800336c <PrepareRespFrame+0x134>)
 8003260:	4313      	orrs	r3, r2
 8003262:	b21b      	sxth	r3, r3
 8003264:	817b      	strh	r3, [r7, #10]

    memset (txBuffer, 0x00, dataLength);
 8003266:	8bbb      	ldrh	r3, [r7, #28]
 8003268:	461a      	mov	r2, r3
 800326a:	2100      	movs	r1, #0
 800326c:	6878      	ldr	r0, [r7, #4]
 800326e:	f014 fca2 	bl	8017bb6 <memset>
    txBuffer[txBufferPos++] = FRAME_INDICATOR;
 8003272:	89fb      	ldrh	r3, [r7, #14]
 8003274:	1c5a      	adds	r2, r3, #1
 8003276:	81fa      	strh	r2, [r7, #14]
 8003278:	461a      	mov	r2, r3
 800327a:	687b      	ldr	r3, [r7, #4]
 800327c:	4413      	add	r3, r2
 800327e:	22aa      	movs	r2, #170	@ 0xaa
 8003280:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId);
 8003282:	89fb      	ldrh	r3, [r7, #14]
 8003284:	1c5a      	adds	r2, r3, #1
 8003286:	81fa      	strh	r2, [r7, #14]
 8003288:	461a      	mov	r2, r3
 800328a:	687b      	ldr	r3, [r7, #4]
 800328c:	4413      	add	r3, r2
 800328e:	887a      	ldrh	r2, [r7, #2]
 8003290:	b2d2      	uxtb	r2, r2
 8003292:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId);
 8003294:	887b      	ldrh	r3, [r7, #2]
 8003296:	0a1b      	lsrs	r3, r3, #8
 8003298:	b29a      	uxth	r2, r3
 800329a:	89fb      	ldrh	r3, [r7, #14]
 800329c:	1c59      	adds	r1, r3, #1
 800329e:	81f9      	strh	r1, [r7, #14]
 80032a0:	4619      	mov	r1, r3
 80032a2:	687b      	ldr	r3, [r7, #4]
 80032a4:	440b      	add	r3, r1
 80032a6:	b2d2      	uxtb	r2, r2
 80032a8:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd);
 80032aa:	89fb      	ldrh	r3, [r7, #14]
 80032ac:	1c5a      	adds	r2, r3, #1
 80032ae:	81fa      	strh	r2, [r7, #14]
 80032b0:	461a      	mov	r2, r3
 80032b2:	687b      	ldr	r3, [r7, #4]
 80032b4:	4413      	add	r3, r2
 80032b6:	897a      	ldrh	r2, [r7, #10]
 80032b8:	b2d2      	uxtb	r2, r2
 80032ba:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd);
 80032bc:	897b      	ldrh	r3, [r7, #10]
 80032be:	0a1b      	lsrs	r3, r3, #8
 80032c0:	b29a      	uxth	r2, r3
 80032c2:	89fb      	ldrh	r3, [r7, #14]
 80032c4:	1c59      	adds	r1, r3, #1
 80032c6:	81f9      	strh	r1, [r7, #14]
 80032c8:	4619      	mov	r1, r3
 80032ca:	687b      	ldr	r3, [r7, #4]
 80032cc:	440b      	add	r3, r1
 80032ce:	b2d2      	uxtb	r2, r2
 80032d0:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength);
 80032d2:	89fb      	ldrh	r3, [r7, #14]
 80032d4:	1c5a      	adds	r2, r3, #1
 80032d6:	81fa      	strh	r2, [r7, #14]
 80032d8:	461a      	mov	r2, r3
 80032da:	687b      	ldr	r3, [r7, #4]
 80032dc:	4413      	add	r3, r2
 80032de:	8bba      	ldrh	r2, [r7, #28]
 80032e0:	b2d2      	uxtb	r2, r2
 80032e2:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength);
 80032e4:	8bbb      	ldrh	r3, [r7, #28]
 80032e6:	0a1b      	lsrs	r3, r3, #8
 80032e8:	b29a      	uxth	r2, r3
 80032ea:	89fb      	ldrh	r3, [r7, #14]
 80032ec:	1c59      	adds	r1, r3, #1
 80032ee:	81f9      	strh	r1, [r7, #14]
 80032f0:	4619      	mov	r1, r3
 80032f2:	687b      	ldr	r3, [r7, #4]
 80032f4:	440b      	add	r3, r1
 80032f6:	b2d2      	uxtb	r2, r2
 80032f8:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = (uint8_t)respStatus;
 80032fa:	89fb      	ldrh	r3, [r7, #14]
 80032fc:	1c5a      	adds	r2, r3, #1
 80032fe:	81fa      	strh	r2, [r7, #14]
 8003300:	461a      	mov	r2, r3
 8003302:	687b      	ldr	r3, [r7, #4]
 8003304:	4413      	add	r3, r2
 8003306:	783a      	ldrb	r2, [r7, #0]
 8003308:	701a      	strb	r2, [r3, #0]
    if (dataLength > 0) {
 800330a:	8bbb      	ldrh	r3, [r7, #28]
 800330c:	2b00      	cmp	r3, #0
 800330e:	d00b      	beq.n	8003328 <PrepareRespFrame+0xf0>
        memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength);
 8003310:	89fb      	ldrh	r3, [r7, #14]
 8003312:	687a      	ldr	r2, [r7, #4]
 8003314:	4413      	add	r3, r2
 8003316:	8bba      	ldrh	r2, [r7, #28]
 8003318:	69b9      	ldr	r1, [r7, #24]
 800331a:	4618      	mov	r0, r3
 800331c:	f014 fd1d 	bl	8017d5a <memcpy>
        txBufferPos += dataLength;
 8003320:	89fa      	ldrh	r2, [r7, #14]
 8003322:	8bbb      	ldrh	r3, [r7, #28]
 8003324:	4413      	add	r3, r2
 8003326:	81fb      	strh	r3, [r7, #14]
    }
    crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos);
 8003328:	89fb      	ldrh	r3, [r7, #14]
 800332a:	461a      	mov	r2, r3
 800332c:	6879      	ldr	r1, [r7, #4]
 800332e:	4810      	ldr	r0, [pc, #64]	@ (8003370 <PrepareRespFrame+0x138>)
 8003330:	f004 f82e 	bl	8007390 <HAL_CRC_Calculate>
 8003334:	4603      	mov	r3, r0
 8003336:	81bb      	strh	r3, [r7, #12]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc);
 8003338:	89fb      	ldrh	r3, [r7, #14]
 800333a:	1c5a      	adds	r2, r3, #1
 800333c:	81fa      	strh	r2, [r7, #14]
 800333e:	461a      	mov	r2, r3
 8003340:	687b      	ldr	r3, [r7, #4]
 8003342:	4413      	add	r3, r2
 8003344:	89ba      	ldrh	r2, [r7, #12]
 8003346:	b2d2      	uxtb	r2, r2
 8003348:	701a      	strb	r2, [r3, #0]
    txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc);
 800334a:	89bb      	ldrh	r3, [r7, #12]
 800334c:	0a1b      	lsrs	r3, r3, #8
 800334e:	b29a      	uxth	r2, r3
 8003350:	89fb      	ldrh	r3, [r7, #14]
 8003352:	1c59      	adds	r1, r3, #1
 8003354:	81f9      	strh	r1, [r7, #14]
 8003356:	4619      	mov	r1, r3
 8003358:	687b      	ldr	r3, [r7, #4]
 800335a:	440b      	add	r3, r1
 800335c:	b2d2      	uxtb	r2, r2
 800335e:	701a      	strb	r2, [r3, #0]

    return txBufferPos;
 8003360:	89fb      	ldrh	r3, [r7, #14]
}
 8003362:	4618      	mov	r0, r3
 8003364:	3710      	adds	r7, #16
 8003366:	46bd      	mov	sp, r7
 8003368:	bd80      	pop	{r7, pc}
 800336a:	bf00      	nop
 800336c:	ffff8000 	.word	0xffff8000
 8003370:	24000400 	.word	0x24000400

08003374 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
                                        /**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8003374:	b580      	push	{r7, lr}
 8003376:	b086      	sub	sp, #24
 8003378:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */
  PWREx_AVDTypeDef sConfigAVD = {0};
 800337a:	f107 0310 	add.w	r3, r7, #16
 800337e:	2200      	movs	r2, #0
 8003380:	601a      	str	r2, [r3, #0]
 8003382:	605a      	str	r2, [r3, #4]
  PWR_PVDTypeDef sConfigPVD = {0};
 8003384:	f107 0308 	add.w	r3, r7, #8
 8003388:	2200      	movs	r2, #0
 800338a:	601a      	str	r2, [r3, #0]
 800338c:	605a      	str	r2, [r3, #4]

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 800338e:	4b26      	ldr	r3, [pc, #152]	@ (8003428 <HAL_MspInit+0xb4>)
 8003390:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 8003394:	4a24      	ldr	r2, [pc, #144]	@ (8003428 <HAL_MspInit+0xb4>)
 8003396:	f043 0302 	orr.w	r3, r3, #2
 800339a:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
 800339e:	4b22      	ldr	r3, [pc, #136]	@ (8003428 <HAL_MspInit+0xb4>)
 80033a0:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 80033a4:	f003 0302 	and.w	r3, r3, #2
 80033a8:	607b      	str	r3, [r7, #4]
 80033aa:	687b      	ldr	r3, [r7, #4]

  /* System interrupt init*/
  /* PendSV_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
 80033ac:	2200      	movs	r2, #0
 80033ae:	210f      	movs	r1, #15
 80033b0:	f06f 0001 	mvn.w	r0, #1
 80033b4:	f003 fee8 	bl	8007188 <HAL_NVIC_SetPriority>

  /* Peripheral interrupt init */
  /* RCC_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(RCC_IRQn, 5, 0);
 80033b8:	2200      	movs	r2, #0
 80033ba:	2105      	movs	r1, #5
 80033bc:	2005      	movs	r0, #5
 80033be:	f003 fee3 	bl	8007188 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(RCC_IRQn);
 80033c2:	2005      	movs	r0, #5
 80033c4:	f003 fefa 	bl	80071bc <HAL_NVIC_EnableIRQ>

  /** AVD Configuration
  */
  sConfigAVD.AVDLevel = PWR_AVDLEVEL_3;
 80033c8:	f44f 23c0 	mov.w	r3, #393216	@ 0x60000
 80033cc:	613b      	str	r3, [r7, #16]
  sConfigAVD.Mode = PWR_AVD_MODE_NORMAL;
 80033ce:	2300      	movs	r3, #0
 80033d0:	617b      	str	r3, [r7, #20]
  HAL_PWREx_ConfigAVD(&sConfigAVD);
 80033d2:	f107 0310 	add.w	r3, r7, #16
 80033d6:	4618      	mov	r0, r3
 80033d8:	f007 fce2 	bl	800ada0 <HAL_PWREx_ConfigAVD>

  /** Enable the AVD Output
  */
  HAL_PWREx_EnableAVD();
 80033dc:	f007 fd56 	bl	800ae8c <HAL_PWREx_EnableAVD>

  /** PVD Configuration
  */
  sConfigPVD.PVDLevel = PWR_PVDLEVEL_6;
 80033e0:	23c0      	movs	r3, #192	@ 0xc0
 80033e2:	60bb      	str	r3, [r7, #8]
  sConfigPVD.Mode = PWR_PVD_MODE_NORMAL;
 80033e4:	2300      	movs	r3, #0
 80033e6:	60fb      	str	r3, [r7, #12]
  HAL_PWR_ConfigPVD(&sConfigPVD);
 80033e8:	f107 0308 	add.w	r3, r7, #8
 80033ec:	4618      	mov	r0, r3
 80033ee:	f007 fc13 	bl	800ac18 <HAL_PWR_ConfigPVD>

  /** Enable the PVD Output
  */
  HAL_PWR_EnablePVD();
 80033f2:	f007 fc8b 	bl	800ad0c <HAL_PWR_EnablePVD>

  /** Enable the VREF clock
  */
  __HAL_RCC_VREF_CLK_ENABLE();
 80033f6:	4b0c      	ldr	r3, [pc, #48]	@ (8003428 <HAL_MspInit+0xb4>)
 80033f8:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 80033fc:	4a0a      	ldr	r2, [pc, #40]	@ (8003428 <HAL_MspInit+0xb4>)
 80033fe:	f443 4300 	orr.w	r3, r3, #32768	@ 0x8000
 8003402:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
 8003406:	4b08      	ldr	r3, [pc, #32]	@ (8003428 <HAL_MspInit+0xb4>)
 8003408:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 800340c:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 8003410:	603b      	str	r3, [r7, #0]
 8003412:	683b      	ldr	r3, [r7, #0]

  /** Disable the Internal Voltage Reference buffer
  */
  HAL_SYSCFG_DisableVREFBUF();
 8003414:	f002 f83e 	bl	8005494 <HAL_SYSCFG_DisableVREFBUF>

  /** Configure the internal voltage reference buffer high impedance mode
  */
  HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE);
 8003418:	2002      	movs	r0, #2
 800341a:	f002 f827 	bl	800546c <HAL_SYSCFG_VREFBUF_HighImpedanceConfig>

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 800341e:	bf00      	nop
 8003420:	3718      	adds	r7, #24
 8003422:	46bd      	mov	sp, r7
 8003424:	bd80      	pop	{r7, pc}
 8003426:	bf00      	nop
 8003428:	58024400 	.word	0x58024400

0800342c <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
 800342c:	b580      	push	{r7, lr}
 800342e:	b092      	sub	sp, #72	@ 0x48
 8003430:	af00      	add	r7, sp, #0
 8003432:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8003434:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8003438:	2200      	movs	r2, #0
 800343a:	601a      	str	r2, [r3, #0]
 800343c:	605a      	str	r2, [r3, #4]
 800343e:	609a      	str	r2, [r3, #8]
 8003440:	60da      	str	r2, [r3, #12]
 8003442:	611a      	str	r2, [r3, #16]
  if(hadc->Instance==ADC1)
 8003444:	687b      	ldr	r3, [r7, #4]
 8003446:	681b      	ldr	r3, [r3, #0]
 8003448:	4a9d      	ldr	r2, [pc, #628]	@ (80036c0 <HAL_ADC_MspInit+0x294>)
 800344a:	4293      	cmp	r3, r2
 800344c:	f040 8099 	bne.w	8003582 <HAL_ADC_MspInit+0x156>
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */
    /* Peripheral clock enable */
    HAL_RCC_ADC12_CLK_ENABLED++;
 8003450:	4b9c      	ldr	r3, [pc, #624]	@ (80036c4 <HAL_ADC_MspInit+0x298>)
 8003452:	681b      	ldr	r3, [r3, #0]
 8003454:	3301      	adds	r3, #1
 8003456:	4a9b      	ldr	r2, [pc, #620]	@ (80036c4 <HAL_ADC_MspInit+0x298>)
 8003458:	6013      	str	r3, [r2, #0]
    if(HAL_RCC_ADC12_CLK_ENABLED==1){
 800345a:	4b9a      	ldr	r3, [pc, #616]	@ (80036c4 <HAL_ADC_MspInit+0x298>)
 800345c:	681b      	ldr	r3, [r3, #0]
 800345e:	2b01      	cmp	r3, #1
 8003460:	d10e      	bne.n	8003480 <HAL_ADC_MspInit+0x54>
      __HAL_RCC_ADC12_CLK_ENABLE();
 8003462:	4b99      	ldr	r3, [pc, #612]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 8003464:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 8003468:	4a97      	ldr	r2, [pc, #604]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 800346a:	f043 0320 	orr.w	r3, r3, #32
 800346e:	f8c2 30d8 	str.w	r3, [r2, #216]	@ 0xd8
 8003472:	4b95      	ldr	r3, [pc, #596]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 8003474:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 8003478:	f003 0320 	and.w	r3, r3, #32
 800347c:	633b      	str	r3, [r7, #48]	@ 0x30
 800347e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
    }

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8003480:	4b91      	ldr	r3, [pc, #580]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 8003482:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003486:	4a90      	ldr	r2, [pc, #576]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 8003488:	f043 0301 	orr.w	r3, r3, #1
 800348c:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8003490:	4b8d      	ldr	r3, [pc, #564]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 8003492:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003496:	f003 0301 	and.w	r3, r3, #1
 800349a:	62fb      	str	r3, [r7, #44]	@ 0x2c
 800349c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
    __HAL_RCC_GPIOC_CLK_ENABLE();
 800349e:	4b8a      	ldr	r3, [pc, #552]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80034a0:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80034a4:	4a88      	ldr	r2, [pc, #544]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80034a6:	f043 0304 	orr.w	r3, r3, #4
 80034aa:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80034ae:	4b86      	ldr	r3, [pc, #536]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80034b0:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80034b4:	f003 0304 	and.w	r3, r3, #4
 80034b8:	62bb      	str	r3, [r7, #40]	@ 0x28
 80034ba:	6abb      	ldr	r3, [r7, #40]	@ 0x28
    __HAL_RCC_GPIOB_CLK_ENABLE();
 80034bc:	4b82      	ldr	r3, [pc, #520]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80034be:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80034c2:	4a81      	ldr	r2, [pc, #516]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80034c4:	f043 0302 	orr.w	r3, r3, #2
 80034c8:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80034cc:	4b7e      	ldr	r3, [pc, #504]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80034ce:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80034d2:	f003 0302 	and.w	r3, r3, #2
 80034d6:	627b      	str	r3, [r7, #36]	@ 0x24
 80034d8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
    PA3     ------> ADC1_INP15
    PA7     ------> ADC1_INP7
    PC5     ------> ADC1_INP8
    PB0     ------> ADC1_INP9
    */
    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
 80034da:	238f      	movs	r3, #143	@ 0x8f
 80034dc:	637b      	str	r3, [r7, #52]	@ 0x34
                          |GPIO_PIN_7;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 80034de:	2303      	movs	r3, #3
 80034e0:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80034e2:	2300      	movs	r3, #0
 80034e4:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80034e6:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 80034ea:	4619      	mov	r1, r3
 80034ec:	4877      	ldr	r0, [pc, #476]	@ (80036cc <HAL_ADC_MspInit+0x2a0>)
 80034ee:	f007 f97d 	bl	800a7ec <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = GPIO_PIN_5;
 80034f2:	2320      	movs	r3, #32
 80034f4:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 80034f6:	2303      	movs	r3, #3
 80034f8:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80034fa:	2300      	movs	r3, #0
 80034fc:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 80034fe:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8003502:	4619      	mov	r1, r3
 8003504:	4872      	ldr	r0, [pc, #456]	@ (80036d0 <HAL_ADC_MspInit+0x2a4>)
 8003506:	f007 f971 	bl	800a7ec <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = GPIO_PIN_0;
 800350a:	2301      	movs	r3, #1
 800350c:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 800350e:	2303      	movs	r3, #3
 8003510:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003512:	2300      	movs	r3, #0
 8003514:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8003516:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 800351a:	4619      	mov	r1, r3
 800351c:	486d      	ldr	r0, [pc, #436]	@ (80036d4 <HAL_ADC_MspInit+0x2a8>)
 800351e:	f007 f965 	bl	800a7ec <HAL_GPIO_Init>

    /* ADC1 DMA Init */
    /* ADC1 Init */
    hdma_adc1.Instance = DMA1_Stream0;
 8003522:	4b6d      	ldr	r3, [pc, #436]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 8003524:	4a6d      	ldr	r2, [pc, #436]	@ (80036dc <HAL_ADC_MspInit+0x2b0>)
 8003526:	601a      	str	r2, [r3, #0]
    hdma_adc1.Init.Request = DMA_REQUEST_ADC1;
 8003528:	4b6b      	ldr	r3, [pc, #428]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 800352a:	2209      	movs	r2, #9
 800352c:	605a      	str	r2, [r3, #4]
    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
 800352e:	4b6a      	ldr	r3, [pc, #424]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 8003530:	2200      	movs	r2, #0
 8003532:	609a      	str	r2, [r3, #8]
    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
 8003534:	4b68      	ldr	r3, [pc, #416]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 8003536:	2200      	movs	r2, #0
 8003538:	60da      	str	r2, [r3, #12]
    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
 800353a:	4b67      	ldr	r3, [pc, #412]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 800353c:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 8003540:	611a      	str	r2, [r3, #16]
    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
 8003542:	4b65      	ldr	r3, [pc, #404]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 8003544:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 8003548:	615a      	str	r2, [r3, #20]
    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
 800354a:	4b63      	ldr	r3, [pc, #396]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 800354c:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
 8003550:	619a      	str	r2, [r3, #24]
    hdma_adc1.Init.Mode = DMA_NORMAL;
 8003552:	4b61      	ldr	r3, [pc, #388]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 8003554:	2200      	movs	r2, #0
 8003556:	61da      	str	r2, [r3, #28]
    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
 8003558:	4b5f      	ldr	r3, [pc, #380]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 800355a:	2200      	movs	r2, #0
 800355c:	621a      	str	r2, [r3, #32]
    hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
 800355e:	4b5e      	ldr	r3, [pc, #376]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 8003560:	2200      	movs	r2, #0
 8003562:	625a      	str	r2, [r3, #36]	@ 0x24
    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
 8003564:	485c      	ldr	r0, [pc, #368]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 8003566:	f004 fb05 	bl	8007b74 <HAL_DMA_Init>
 800356a:	4603      	mov	r3, r0
 800356c:	2b00      	cmp	r3, #0
 800356e:	d001      	beq.n	8003574 <HAL_ADC_MspInit+0x148>
    {
      Error_Handler();
 8003570:	f7fe fc64 	bl	8001e3c <Error_Handler>
    }

    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
 8003574:	687b      	ldr	r3, [r7, #4]
 8003576:	4a58      	ldr	r2, [pc, #352]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 8003578:	64da      	str	r2, [r3, #76]	@ 0x4c
 800357a:	4a57      	ldr	r2, [pc, #348]	@ (80036d8 <HAL_ADC_MspInit+0x2ac>)
 800357c:	687b      	ldr	r3, [r7, #4]
 800357e:	6393      	str	r3, [r2, #56]	@ 0x38
  /* USER CODE BEGIN ADC3_MspInit 1 */

  /* USER CODE END ADC3_MspInit 1 */
  }

}
 8003580:	e11e      	b.n	80037c0 <HAL_ADC_MspInit+0x394>
  else if(hadc->Instance==ADC2)
 8003582:	687b      	ldr	r3, [r7, #4]
 8003584:	681b      	ldr	r3, [r3, #0]
 8003586:	4a56      	ldr	r2, [pc, #344]	@ (80036e0 <HAL_ADC_MspInit+0x2b4>)
 8003588:	4293      	cmp	r3, r2
 800358a:	f040 80af 	bne.w	80036ec <HAL_ADC_MspInit+0x2c0>
    HAL_RCC_ADC12_CLK_ENABLED++;
 800358e:	4b4d      	ldr	r3, [pc, #308]	@ (80036c4 <HAL_ADC_MspInit+0x298>)
 8003590:	681b      	ldr	r3, [r3, #0]
 8003592:	3301      	adds	r3, #1
 8003594:	4a4b      	ldr	r2, [pc, #300]	@ (80036c4 <HAL_ADC_MspInit+0x298>)
 8003596:	6013      	str	r3, [r2, #0]
    if(HAL_RCC_ADC12_CLK_ENABLED==1){
 8003598:	4b4a      	ldr	r3, [pc, #296]	@ (80036c4 <HAL_ADC_MspInit+0x298>)
 800359a:	681b      	ldr	r3, [r3, #0]
 800359c:	2b01      	cmp	r3, #1
 800359e:	d10e      	bne.n	80035be <HAL_ADC_MspInit+0x192>
      __HAL_RCC_ADC12_CLK_ENABLE();
 80035a0:	4b49      	ldr	r3, [pc, #292]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80035a2:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 80035a6:	4a48      	ldr	r2, [pc, #288]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80035a8:	f043 0320 	orr.w	r3, r3, #32
 80035ac:	f8c2 30d8 	str.w	r3, [r2, #216]	@ 0xd8
 80035b0:	4b45      	ldr	r3, [pc, #276]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80035b2:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
 80035b6:	f003 0320 	and.w	r3, r3, #32
 80035ba:	623b      	str	r3, [r7, #32]
 80035bc:	6a3b      	ldr	r3, [r7, #32]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 80035be:	4b42      	ldr	r3, [pc, #264]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80035c0:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80035c4:	4a40      	ldr	r2, [pc, #256]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80035c6:	f043 0301 	orr.w	r3, r3, #1
 80035ca:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80035ce:	4b3e      	ldr	r3, [pc, #248]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80035d0:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80035d4:	f003 0301 	and.w	r3, r3, #1
 80035d8:	61fb      	str	r3, [r7, #28]
 80035da:	69fb      	ldr	r3, [r7, #28]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 80035dc:	4b3a      	ldr	r3, [pc, #232]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80035de:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80035e2:	4a39      	ldr	r2, [pc, #228]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80035e4:	f043 0304 	orr.w	r3, r3, #4
 80035e8:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80035ec:	4b36      	ldr	r3, [pc, #216]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80035ee:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80035f2:	f003 0304 	and.w	r3, r3, #4
 80035f6:	61bb      	str	r3, [r7, #24]
 80035f8:	69bb      	ldr	r3, [r7, #24]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 80035fa:	4b33      	ldr	r3, [pc, #204]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 80035fc:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003600:	4a31      	ldr	r2, [pc, #196]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 8003602:	f043 0302 	orr.w	r3, r3, #2
 8003606:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 800360a:	4b2f      	ldr	r3, [pc, #188]	@ (80036c8 <HAL_ADC_MspInit+0x29c>)
 800360c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003610:	f003 0302 	and.w	r3, r3, #2
 8003614:	617b      	str	r3, [r7, #20]
 8003616:	697b      	ldr	r3, [r7, #20]
    GPIO_InitStruct.Pin = GPIO_PIN_6;
 8003618:	2340      	movs	r3, #64	@ 0x40
 800361a:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 800361c:	2303      	movs	r3, #3
 800361e:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003620:	2300      	movs	r3, #0
 8003622:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8003624:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8003628:	4619      	mov	r1, r3
 800362a:	4828      	ldr	r0, [pc, #160]	@ (80036cc <HAL_ADC_MspInit+0x2a0>)
 800362c:	f007 f8de 	bl	800a7ec <HAL_GPIO_Init>
    GPIO_InitStruct.Pin = GPIO_PIN_4;
 8003630:	2310      	movs	r3, #16
 8003632:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8003634:	2303      	movs	r3, #3
 8003636:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003638:	2300      	movs	r3, #0
 800363a:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 800363c:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8003640:	4619      	mov	r1, r3
 8003642:	4823      	ldr	r0, [pc, #140]	@ (80036d0 <HAL_ADC_MspInit+0x2a4>)
 8003644:	f007 f8d2 	bl	800a7ec <HAL_GPIO_Init>
    GPIO_InitStruct.Pin = GPIO_PIN_1;
 8003648:	2302      	movs	r3, #2
 800364a:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 800364c:	2303      	movs	r3, #3
 800364e:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003650:	2300      	movs	r3, #0
 8003652:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8003654:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8003658:	4619      	mov	r1, r3
 800365a:	481e      	ldr	r0, [pc, #120]	@ (80036d4 <HAL_ADC_MspInit+0x2a8>)
 800365c:	f007 f8c6 	bl	800a7ec <HAL_GPIO_Init>
    hdma_adc2.Instance = DMA1_Stream1;
 8003660:	4b20      	ldr	r3, [pc, #128]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 8003662:	4a21      	ldr	r2, [pc, #132]	@ (80036e8 <HAL_ADC_MspInit+0x2bc>)
 8003664:	601a      	str	r2, [r3, #0]
    hdma_adc2.Init.Request = DMA_REQUEST_ADC2;
 8003666:	4b1f      	ldr	r3, [pc, #124]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 8003668:	220a      	movs	r2, #10
 800366a:	605a      	str	r2, [r3, #4]
    hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY;
 800366c:	4b1d      	ldr	r3, [pc, #116]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 800366e:	2200      	movs	r2, #0
 8003670:	609a      	str	r2, [r3, #8]
    hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE;
 8003672:	4b1c      	ldr	r3, [pc, #112]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 8003674:	2200      	movs	r2, #0
 8003676:	60da      	str	r2, [r3, #12]
    hdma_adc2.Init.MemInc = DMA_MINC_ENABLE;
 8003678:	4b1a      	ldr	r3, [pc, #104]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 800367a:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 800367e:	611a      	str	r2, [r3, #16]
    hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
 8003680:	4b18      	ldr	r3, [pc, #96]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 8003682:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 8003686:	615a      	str	r2, [r3, #20]
    hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
 8003688:	4b16      	ldr	r3, [pc, #88]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 800368a:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
 800368e:	619a      	str	r2, [r3, #24]
    hdma_adc2.Init.Mode = DMA_NORMAL;
 8003690:	4b14      	ldr	r3, [pc, #80]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 8003692:	2200      	movs	r2, #0
 8003694:	61da      	str	r2, [r3, #28]
    hdma_adc2.Init.Priority = DMA_PRIORITY_LOW;
 8003696:	4b13      	ldr	r3, [pc, #76]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 8003698:	2200      	movs	r2, #0
 800369a:	621a      	str	r2, [r3, #32]
    hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
 800369c:	4b11      	ldr	r3, [pc, #68]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 800369e:	2200      	movs	r2, #0
 80036a0:	625a      	str	r2, [r3, #36]	@ 0x24
    if (HAL_DMA_Init(&hdma_adc2) != HAL_OK)
 80036a2:	4810      	ldr	r0, [pc, #64]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 80036a4:	f004 fa66 	bl	8007b74 <HAL_DMA_Init>
 80036a8:	4603      	mov	r3, r0
 80036aa:	2b00      	cmp	r3, #0
 80036ac:	d001      	beq.n	80036b2 <HAL_ADC_MspInit+0x286>
      Error_Handler();
 80036ae:	f7fe fbc5 	bl	8001e3c <Error_Handler>
    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2);
 80036b2:	687b      	ldr	r3, [r7, #4]
 80036b4:	4a0b      	ldr	r2, [pc, #44]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 80036b6:	64da      	str	r2, [r3, #76]	@ 0x4c
 80036b8:	4a0a      	ldr	r2, [pc, #40]	@ (80036e4 <HAL_ADC_MspInit+0x2b8>)
 80036ba:	687b      	ldr	r3, [r7, #4]
 80036bc:	6393      	str	r3, [r2, #56]	@ 0x38
}
 80036be:	e07f      	b.n	80037c0 <HAL_ADC_MspInit+0x394>
 80036c0:	40022000 	.word	0x40022000
 80036c4:	24000860 	.word	0x24000860
 80036c8:	58024400 	.word	0x58024400
 80036cc:	58020000 	.word	0x58020000
 80036d0:	58020800 	.word	0x58020800
 80036d4:	58020400 	.word	0x58020400
 80036d8:	2400026c 	.word	0x2400026c
 80036dc:	40020010 	.word	0x40020010
 80036e0:	40022100 	.word	0x40022100
 80036e4:	240002e4 	.word	0x240002e4
 80036e8:	40020028 	.word	0x40020028
  else if(hadc->Instance==ADC3)
 80036ec:	687b      	ldr	r3, [r7, #4]
 80036ee:	681b      	ldr	r3, [r3, #0]
 80036f0:	4a35      	ldr	r2, [pc, #212]	@ (80037c8 <HAL_ADC_MspInit+0x39c>)
 80036f2:	4293      	cmp	r3, r2
 80036f4:	d164      	bne.n	80037c0 <HAL_ADC_MspInit+0x394>
    __HAL_RCC_ADC3_CLK_ENABLE();
 80036f6:	4b35      	ldr	r3, [pc, #212]	@ (80037cc <HAL_ADC_MspInit+0x3a0>)
 80036f8:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80036fc:	4a33      	ldr	r2, [pc, #204]	@ (80037cc <HAL_ADC_MspInit+0x3a0>)
 80036fe:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8003702:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8003706:	4b31      	ldr	r3, [pc, #196]	@ (80037cc <HAL_ADC_MspInit+0x3a0>)
 8003708:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800370c:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 8003710:	613b      	str	r3, [r7, #16]
 8003712:	693b      	ldr	r3, [r7, #16]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 8003714:	4b2d      	ldr	r3, [pc, #180]	@ (80037cc <HAL_ADC_MspInit+0x3a0>)
 8003716:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800371a:	4a2c      	ldr	r2, [pc, #176]	@ (80037cc <HAL_ADC_MspInit+0x3a0>)
 800371c:	f043 0304 	orr.w	r3, r3, #4
 8003720:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8003724:	4b29      	ldr	r3, [pc, #164]	@ (80037cc <HAL_ADC_MspInit+0x3a0>)
 8003726:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 800372a:	f003 0304 	and.w	r3, r3, #4
 800372e:	60fb      	str	r3, [r7, #12]
 8003730:	68fb      	ldr	r3, [r7, #12]
    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
 8003732:	2303      	movs	r3, #3
 8003734:	637b      	str	r3, [r7, #52]	@ 0x34
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8003736:	2303      	movs	r3, #3
 8003738:	63bb      	str	r3, [r7, #56]	@ 0x38
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 800373a:	2300      	movs	r3, #0
 800373c:	63fb      	str	r3, [r7, #60]	@ 0x3c
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 800373e:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8003742:	4619      	mov	r1, r3
 8003744:	4822      	ldr	r0, [pc, #136]	@ (80037d0 <HAL_ADC_MspInit+0x3a4>)
 8003746:	f007 f851 	bl	800a7ec <HAL_GPIO_Init>
    HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN);
 800374a:	f04f 6180 	mov.w	r1, #67108864	@ 0x4000000
 800374e:	f04f 6080 	mov.w	r0, #67108864	@ 0x4000000
 8003752:	f001 feaf 	bl	80054b4 <HAL_SYSCFG_AnalogSwitchConfig>
    HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN);
 8003756:	f04f 6100 	mov.w	r1, #134217728	@ 0x8000000
 800375a:	f04f 6000 	mov.w	r0, #134217728	@ 0x8000000
 800375e:	f001 fea9 	bl	80054b4 <HAL_SYSCFG_AnalogSwitchConfig>
    hdma_adc3.Instance = DMA1_Stream2;
 8003762:	4b1c      	ldr	r3, [pc, #112]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 8003764:	4a1c      	ldr	r2, [pc, #112]	@ (80037d8 <HAL_ADC_MspInit+0x3ac>)
 8003766:	601a      	str	r2, [r3, #0]
    hdma_adc3.Init.Request = DMA_REQUEST_ADC3;
 8003768:	4b1a      	ldr	r3, [pc, #104]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 800376a:	2273      	movs	r2, #115	@ 0x73
 800376c:	605a      	str	r2, [r3, #4]
    hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY;
 800376e:	4b19      	ldr	r3, [pc, #100]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 8003770:	2200      	movs	r2, #0
 8003772:	609a      	str	r2, [r3, #8]
    hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE;
 8003774:	4b17      	ldr	r3, [pc, #92]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 8003776:	2200      	movs	r2, #0
 8003778:	60da      	str	r2, [r3, #12]
    hdma_adc3.Init.MemInc = DMA_MINC_ENABLE;
 800377a:	4b16      	ldr	r3, [pc, #88]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 800377c:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 8003780:	611a      	str	r2, [r3, #16]
    hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
 8003782:	4b14      	ldr	r3, [pc, #80]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 8003784:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 8003788:	615a      	str	r2, [r3, #20]
    hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
 800378a:	4b12      	ldr	r3, [pc, #72]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 800378c:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
 8003790:	619a      	str	r2, [r3, #24]
    hdma_adc3.Init.Mode = DMA_NORMAL;
 8003792:	4b10      	ldr	r3, [pc, #64]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 8003794:	2200      	movs	r2, #0
 8003796:	61da      	str	r2, [r3, #28]
    hdma_adc3.Init.Priority = DMA_PRIORITY_LOW;
 8003798:	4b0e      	ldr	r3, [pc, #56]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 800379a:	2200      	movs	r2, #0
 800379c:	621a      	str	r2, [r3, #32]
    hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
 800379e:	4b0d      	ldr	r3, [pc, #52]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 80037a0:	2200      	movs	r2, #0
 80037a2:	625a      	str	r2, [r3, #36]	@ 0x24
    if (HAL_DMA_Init(&hdma_adc3) != HAL_OK)
 80037a4:	480b      	ldr	r0, [pc, #44]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 80037a6:	f004 f9e5 	bl	8007b74 <HAL_DMA_Init>
 80037aa:	4603      	mov	r3, r0
 80037ac:	2b00      	cmp	r3, #0
 80037ae:	d001      	beq.n	80037b4 <HAL_ADC_MspInit+0x388>
      Error_Handler();
 80037b0:	f7fe fb44 	bl	8001e3c <Error_Handler>
    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3);
 80037b4:	687b      	ldr	r3, [r7, #4]
 80037b6:	4a07      	ldr	r2, [pc, #28]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 80037b8:	64da      	str	r2, [r3, #76]	@ 0x4c
 80037ba:	4a06      	ldr	r2, [pc, #24]	@ (80037d4 <HAL_ADC_MspInit+0x3a8>)
 80037bc:	687b      	ldr	r3, [r7, #4]
 80037be:	6393      	str	r3, [r2, #56]	@ 0x38
}
 80037c0:	bf00      	nop
 80037c2:	3748      	adds	r7, #72	@ 0x48
 80037c4:	46bd      	mov	sp, r7
 80037c6:	bd80      	pop	{r7, pc}
 80037c8:	58026000 	.word	0x58026000
 80037cc:	58024400 	.word	0x58024400
 80037d0:	58020800 	.word	0x58020800
 80037d4:	2400035c 	.word	0x2400035c
 80037d8:	40020040 	.word	0x40020040

080037dc <HAL_COMP_MspInit>:
* This function configures the hardware resources used in this example
* @param hcomp: COMP handle pointer
* @retval None
*/
void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp)
{
 80037dc:	b580      	push	{r7, lr}
 80037de:	b08a      	sub	sp, #40	@ 0x28
 80037e0:	af00      	add	r7, sp, #0
 80037e2:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80037e4:	f107 0314 	add.w	r3, r7, #20
 80037e8:	2200      	movs	r2, #0
 80037ea:	601a      	str	r2, [r3, #0]
 80037ec:	605a      	str	r2, [r3, #4]
 80037ee:	609a      	str	r2, [r3, #8]
 80037f0:	60da      	str	r2, [r3, #12]
 80037f2:	611a      	str	r2, [r3, #16]
  if(hcomp->Instance==COMP1)
 80037f4:	687b      	ldr	r3, [r7, #4]
 80037f6:	681b      	ldr	r3, [r3, #0]
 80037f8:	4a18      	ldr	r2, [pc, #96]	@ (800385c <HAL_COMP_MspInit+0x80>)
 80037fa:	4293      	cmp	r3, r2
 80037fc:	d129      	bne.n	8003852 <HAL_COMP_MspInit+0x76>
  {
  /* USER CODE BEGIN COMP1_MspInit 0 */

  /* USER CODE END COMP1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_COMP12_CLK_ENABLE();
 80037fe:	4b18      	ldr	r3, [pc, #96]	@ (8003860 <HAL_COMP_MspInit+0x84>)
 8003800:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 8003804:	4a16      	ldr	r2, [pc, #88]	@ (8003860 <HAL_COMP_MspInit+0x84>)
 8003806:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
 800380a:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
 800380e:	4b14      	ldr	r3, [pc, #80]	@ (8003860 <HAL_COMP_MspInit+0x84>)
 8003810:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 8003814:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
 8003818:	613b      	str	r3, [r7, #16]
 800381a:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOB_CLK_ENABLE();
 800381c:	4b10      	ldr	r3, [pc, #64]	@ (8003860 <HAL_COMP_MspInit+0x84>)
 800381e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003822:	4a0f      	ldr	r2, [pc, #60]	@ (8003860 <HAL_COMP_MspInit+0x84>)
 8003824:	f043 0302 	orr.w	r3, r3, #2
 8003828:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 800382c:	4b0c      	ldr	r3, [pc, #48]	@ (8003860 <HAL_COMP_MspInit+0x84>)
 800382e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003832:	f003 0302 	and.w	r3, r3, #2
 8003836:	60fb      	str	r3, [r7, #12]
 8003838:	68fb      	ldr	r3, [r7, #12]
    /**COMP1 GPIO Configuration
    PB2     ------> COMP1_INP
    */
    GPIO_InitStruct.Pin = GPIO_PIN_2;
 800383a:	2304      	movs	r3, #4
 800383c:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 800383e:	2303      	movs	r3, #3
 8003840:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003842:	2300      	movs	r3, #0
 8003844:	61fb      	str	r3, [r7, #28]
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8003846:	f107 0314 	add.w	r3, r7, #20
 800384a:	4619      	mov	r1, r3
 800384c:	4805      	ldr	r0, [pc, #20]	@ (8003864 <HAL_COMP_MspInit+0x88>)
 800384e:	f006 ffcd 	bl	800a7ec <HAL_GPIO_Init>
  /* USER CODE BEGIN COMP1_MspInit 1 */

  /* USER CODE END COMP1_MspInit 1 */
  }

}
 8003852:	bf00      	nop
 8003854:	3728      	adds	r7, #40	@ 0x28
 8003856:	46bd      	mov	sp, r7
 8003858:	bd80      	pop	{r7, pc}
 800385a:	bf00      	nop
 800385c:	5800380c 	.word	0x5800380c
 8003860:	58024400 	.word	0x58024400
 8003864:	58020400 	.word	0x58020400

08003868 <HAL_CRC_MspInit>:
* This function configures the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
{
 8003868:	b480      	push	{r7}
 800386a:	b085      	sub	sp, #20
 800386c:	af00      	add	r7, sp, #0
 800386e:	6078      	str	r0, [r7, #4]
  if(hcrc->Instance==CRC)
 8003870:	687b      	ldr	r3, [r7, #4]
 8003872:	681b      	ldr	r3, [r3, #0]
 8003874:	4a0b      	ldr	r2, [pc, #44]	@ (80038a4 <HAL_CRC_MspInit+0x3c>)
 8003876:	4293      	cmp	r3, r2
 8003878:	d10e      	bne.n	8003898 <HAL_CRC_MspInit+0x30>
  {
  /* USER CODE BEGIN CRC_MspInit 0 */

  /* USER CODE END CRC_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_CRC_CLK_ENABLE();
 800387a:	4b0b      	ldr	r3, [pc, #44]	@ (80038a8 <HAL_CRC_MspInit+0x40>)
 800387c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003880:	4a09      	ldr	r2, [pc, #36]	@ (80038a8 <HAL_CRC_MspInit+0x40>)
 8003882:	f443 2300 	orr.w	r3, r3, #524288	@ 0x80000
 8003886:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 800388a:	4b07      	ldr	r3, [pc, #28]	@ (80038a8 <HAL_CRC_MspInit+0x40>)
 800388c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003890:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
 8003894:	60fb      	str	r3, [r7, #12]
 8003896:	68fb      	ldr	r3, [r7, #12]
  /* USER CODE BEGIN CRC_MspInit 1 */

  /* USER CODE END CRC_MspInit 1 */
  }

}
 8003898:	bf00      	nop
 800389a:	3714      	adds	r7, #20
 800389c:	46bd      	mov	sp, r7
 800389e:	f85d 7b04 	ldr.w	r7, [sp], #4
 80038a2:	4770      	bx	lr
 80038a4:	58024c00 	.word	0x58024c00
 80038a8:	58024400 	.word	0x58024400

080038ac <HAL_DAC_MspInit>:
* This function configures the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
 80038ac:	b580      	push	{r7, lr}
 80038ae:	b08a      	sub	sp, #40	@ 0x28
 80038b0:	af00      	add	r7, sp, #0
 80038b2:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80038b4:	f107 0314 	add.w	r3, r7, #20
 80038b8:	2200      	movs	r2, #0
 80038ba:	601a      	str	r2, [r3, #0]
 80038bc:	605a      	str	r2, [r3, #4]
 80038be:	609a      	str	r2, [r3, #8]
 80038c0:	60da      	str	r2, [r3, #12]
 80038c2:	611a      	str	r2, [r3, #16]
  if(hdac->Instance==DAC1)
 80038c4:	687b      	ldr	r3, [r7, #4]
 80038c6:	681b      	ldr	r3, [r3, #0]
 80038c8:	4a1c      	ldr	r2, [pc, #112]	@ (800393c <HAL_DAC_MspInit+0x90>)
 80038ca:	4293      	cmp	r3, r2
 80038cc:	d131      	bne.n	8003932 <HAL_DAC_MspInit+0x86>
  {
  /* USER CODE BEGIN DAC1_MspInit 0 */

  /* USER CODE END DAC1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_DAC12_CLK_ENABLE();
 80038ce:	4b1c      	ldr	r3, [pc, #112]	@ (8003940 <HAL_DAC_MspInit+0x94>)
 80038d0:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 80038d4:	4a1a      	ldr	r2, [pc, #104]	@ (8003940 <HAL_DAC_MspInit+0x94>)
 80038d6:	f043 5300 	orr.w	r3, r3, #536870912	@ 0x20000000
 80038da:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
 80038de:	4b18      	ldr	r3, [pc, #96]	@ (8003940 <HAL_DAC_MspInit+0x94>)
 80038e0:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 80038e4:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 80038e8:	613b      	str	r3, [r7, #16]
 80038ea:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOA_CLK_ENABLE();
 80038ec:	4b14      	ldr	r3, [pc, #80]	@ (8003940 <HAL_DAC_MspInit+0x94>)
 80038ee:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 80038f2:	4a13      	ldr	r2, [pc, #76]	@ (8003940 <HAL_DAC_MspInit+0x94>)
 80038f4:	f043 0301 	orr.w	r3, r3, #1
 80038f8:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 80038fc:	4b10      	ldr	r3, [pc, #64]	@ (8003940 <HAL_DAC_MspInit+0x94>)
 80038fe:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003902:	f003 0301 	and.w	r3, r3, #1
 8003906:	60fb      	str	r3, [r7, #12]
 8003908:	68fb      	ldr	r3, [r7, #12]
    /**DAC1 GPIO Configuration
    PA4     ------> DAC1_OUT1
    PA5     ------> DAC1_OUT2
    */
    GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
 800390a:	2330      	movs	r3, #48	@ 0x30
 800390c:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 800390e:	2303      	movs	r3, #3
 8003910:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003912:	2300      	movs	r3, #0
 8003914:	61fb      	str	r3, [r7, #28]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8003916:	f107 0314 	add.w	r3, r7, #20
 800391a:	4619      	mov	r1, r3
 800391c:	4809      	ldr	r0, [pc, #36]	@ (8003944 <HAL_DAC_MspInit+0x98>)
 800391e:	f006 ff65 	bl	800a7ec <HAL_GPIO_Init>

    /* DAC1 interrupt Init */
    HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0);
 8003922:	2200      	movs	r2, #0
 8003924:	2105      	movs	r1, #5
 8003926:	2036      	movs	r0, #54	@ 0x36
 8003928:	f003 fc2e 	bl	8007188 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
 800392c:	2036      	movs	r0, #54	@ 0x36
 800392e:	f003 fc45 	bl	80071bc <HAL_NVIC_EnableIRQ>
  /* USER CODE BEGIN DAC1_MspInit 1 */

  /* USER CODE END DAC1_MspInit 1 */
  }

}
 8003932:	bf00      	nop
 8003934:	3728      	adds	r7, #40	@ 0x28
 8003936:	46bd      	mov	sp, r7
 8003938:	bd80      	pop	{r7, pc}
 800393a:	bf00      	nop
 800393c:	40007400 	.word	0x40007400
 8003940:	58024400 	.word	0x58024400
 8003944:	58020000 	.word	0x58020000

08003948 <HAL_RNG_MspInit>:
* This function configures the hardware resources used in this example
* @param hrng: RNG handle pointer
* @retval None
*/
void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng)
{
 8003948:	b580      	push	{r7, lr}
 800394a:	b0b4      	sub	sp, #208	@ 0xd0
 800394c:	af00      	add	r7, sp, #0
 800394e:	6078      	str	r0, [r7, #4]
  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 8003950:	f107 0310 	add.w	r3, r7, #16
 8003954:	22c0      	movs	r2, #192	@ 0xc0
 8003956:	2100      	movs	r1, #0
 8003958:	4618      	mov	r0, r3
 800395a:	f014 f92c 	bl	8017bb6 <memset>
  if(hrng->Instance==RNG)
 800395e:	687b      	ldr	r3, [r7, #4]
 8003960:	681b      	ldr	r3, [r3, #0]
 8003962:	4a14      	ldr	r2, [pc, #80]	@ (80039b4 <HAL_RNG_MspInit+0x6c>)
 8003964:	4293      	cmp	r3, r2
 8003966:	d121      	bne.n	80039ac <HAL_RNG_MspInit+0x64>

  /* USER CODE END RNG_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
 8003968:	f44f 3200 	mov.w	r2, #131072	@ 0x20000
 800396c:	f04f 0300 	mov.w	r3, #0
 8003970:	e9c7 2304 	strd	r2, r3, [r7, #16]
    PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
 8003974:	2300      	movs	r3, #0
 8003976:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 800397a:	f107 0310 	add.w	r3, r7, #16
 800397e:	4618      	mov	r0, r3
 8003980:	f008 fabc 	bl	800befc <HAL_RCCEx_PeriphCLKConfig>
 8003984:	4603      	mov	r3, r0
 8003986:	2b00      	cmp	r3, #0
 8003988:	d001      	beq.n	800398e <HAL_RNG_MspInit+0x46>
    {
      Error_Handler();
 800398a:	f7fe fa57 	bl	8001e3c <Error_Handler>
    }

    /* Peripheral clock enable */
    __HAL_RCC_RNG_CLK_ENABLE();
 800398e:	4b0a      	ldr	r3, [pc, #40]	@ (80039b8 <HAL_RNG_MspInit+0x70>)
 8003990:	f8d3 30dc 	ldr.w	r3, [r3, #220]	@ 0xdc
 8003994:	4a08      	ldr	r2, [pc, #32]	@ (80039b8 <HAL_RNG_MspInit+0x70>)
 8003996:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 800399a:	f8c2 30dc 	str.w	r3, [r2, #220]	@ 0xdc
 800399e:	4b06      	ldr	r3, [pc, #24]	@ (80039b8 <HAL_RNG_MspInit+0x70>)
 80039a0:	f8d3 30dc 	ldr.w	r3, [r3, #220]	@ 0xdc
 80039a4:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 80039a8:	60fb      	str	r3, [r7, #12]
 80039aa:	68fb      	ldr	r3, [r7, #12]
  /* USER CODE BEGIN RNG_MspInit 1 */

  /* USER CODE END RNG_MspInit 1 */
  }

}
 80039ac:	bf00      	nop
 80039ae:	37d0      	adds	r7, #208	@ 0xd0
 80039b0:	46bd      	mov	sp, r7
 80039b2:	bd80      	pop	{r7, pc}
 80039b4:	48021800 	.word	0x48021800
 80039b8:	58024400 	.word	0x58024400

080039bc <HAL_TIM_PWM_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_pwm: TIM_PWM handle pointer
* @retval None
*/
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
{
 80039bc:	b480      	push	{r7}
 80039be:	b085      	sub	sp, #20
 80039c0:	af00      	add	r7, sp, #0
 80039c2:	6078      	str	r0, [r7, #4]
  if(htim_pwm->Instance==TIM1)
 80039c4:	687b      	ldr	r3, [r7, #4]
 80039c6:	681b      	ldr	r3, [r3, #0]
 80039c8:	4a16      	ldr	r2, [pc, #88]	@ (8003a24 <HAL_TIM_PWM_MspInit+0x68>)
 80039ca:	4293      	cmp	r3, r2
 80039cc:	d10f      	bne.n	80039ee <HAL_TIM_PWM_MspInit+0x32>
  {
  /* USER CODE BEGIN TIM1_MspInit 0 */

  /* USER CODE END TIM1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_TIM1_CLK_ENABLE();
 80039ce:	4b16      	ldr	r3, [pc, #88]	@ (8003a28 <HAL_TIM_PWM_MspInit+0x6c>)
 80039d0:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
 80039d4:	4a14      	ldr	r2, [pc, #80]	@ (8003a28 <HAL_TIM_PWM_MspInit+0x6c>)
 80039d6:	f043 0301 	orr.w	r3, r3, #1
 80039da:	f8c2 30f0 	str.w	r3, [r2, #240]	@ 0xf0
 80039de:	4b12      	ldr	r3, [pc, #72]	@ (8003a28 <HAL_TIM_PWM_MspInit+0x6c>)
 80039e0:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
 80039e4:	f003 0301 	and.w	r3, r3, #1
 80039e8:	60fb      	str	r3, [r7, #12]
 80039ea:	68fb      	ldr	r3, [r7, #12]
  /* USER CODE BEGIN TIM3_MspInit 1 */

  /* USER CODE END TIM3_MspInit 1 */
  }

}
 80039ec:	e013      	b.n	8003a16 <HAL_TIM_PWM_MspInit+0x5a>
  else if(htim_pwm->Instance==TIM3)
 80039ee:	687b      	ldr	r3, [r7, #4]
 80039f0:	681b      	ldr	r3, [r3, #0]
 80039f2:	4a0e      	ldr	r2, [pc, #56]	@ (8003a2c <HAL_TIM_PWM_MspInit+0x70>)
 80039f4:	4293      	cmp	r3, r2
 80039f6:	d10e      	bne.n	8003a16 <HAL_TIM_PWM_MspInit+0x5a>
    __HAL_RCC_TIM3_CLK_ENABLE();
 80039f8:	4b0b      	ldr	r3, [pc, #44]	@ (8003a28 <HAL_TIM_PWM_MspInit+0x6c>)
 80039fa:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 80039fe:	4a0a      	ldr	r2, [pc, #40]	@ (8003a28 <HAL_TIM_PWM_MspInit+0x6c>)
 8003a00:	f043 0302 	orr.w	r3, r3, #2
 8003a04:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
 8003a08:	4b07      	ldr	r3, [pc, #28]	@ (8003a28 <HAL_TIM_PWM_MspInit+0x6c>)
 8003a0a:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 8003a0e:	f003 0302 	and.w	r3, r3, #2
 8003a12:	60bb      	str	r3, [r7, #8]
 8003a14:	68bb      	ldr	r3, [r7, #8]
}
 8003a16:	bf00      	nop
 8003a18:	3714      	adds	r7, #20
 8003a1a:	46bd      	mov	sp, r7
 8003a1c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003a20:	4770      	bx	lr
 8003a22:	bf00      	nop
 8003a24:	40010000 	.word	0x40010000
 8003a28:	58024400 	.word	0x58024400
 8003a2c:	40000400 	.word	0x40000400

08003a30 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
 8003a30:	b580      	push	{r7, lr}
 8003a32:	b08c      	sub	sp, #48	@ 0x30
 8003a34:	af00      	add	r7, sp, #0
 8003a36:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8003a38:	f107 031c 	add.w	r3, r7, #28
 8003a3c:	2200      	movs	r2, #0
 8003a3e:	601a      	str	r2, [r3, #0]
 8003a40:	605a      	str	r2, [r3, #4]
 8003a42:	609a      	str	r2, [r3, #8]
 8003a44:	60da      	str	r2, [r3, #12]
 8003a46:	611a      	str	r2, [r3, #16]
  if(htim_base->Instance==TIM2)
 8003a48:	687b      	ldr	r3, [r7, #4]
 8003a4a:	681b      	ldr	r3, [r3, #0]
 8003a4c:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8003a50:	d137      	bne.n	8003ac2 <HAL_TIM_Base_MspInit+0x92>
  {
  /* USER CODE BEGIN TIM2_MspInit 0 */

  /* USER CODE END TIM2_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_TIM2_CLK_ENABLE();
 8003a52:	4b3c      	ldr	r3, [pc, #240]	@ (8003b44 <HAL_TIM_Base_MspInit+0x114>)
 8003a54:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 8003a58:	4a3a      	ldr	r2, [pc, #232]	@ (8003b44 <HAL_TIM_Base_MspInit+0x114>)
 8003a5a:	f043 0301 	orr.w	r3, r3, #1
 8003a5e:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
 8003a62:	4b38      	ldr	r3, [pc, #224]	@ (8003b44 <HAL_TIM_Base_MspInit+0x114>)
 8003a64:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 8003a68:	f003 0301 	and.w	r3, r3, #1
 8003a6c:	61bb      	str	r3, [r7, #24]
 8003a6e:	69bb      	ldr	r3, [r7, #24]

    __HAL_RCC_GPIOB_CLK_ENABLE();
 8003a70:	4b34      	ldr	r3, [pc, #208]	@ (8003b44 <HAL_TIM_Base_MspInit+0x114>)
 8003a72:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003a76:	4a33      	ldr	r2, [pc, #204]	@ (8003b44 <HAL_TIM_Base_MspInit+0x114>)
 8003a78:	f043 0302 	orr.w	r3, r3, #2
 8003a7c:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8003a80:	4b30      	ldr	r3, [pc, #192]	@ (8003b44 <HAL_TIM_Base_MspInit+0x114>)
 8003a82:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003a86:	f003 0302 	and.w	r3, r3, #2
 8003a8a:	617b      	str	r3, [r7, #20]
 8003a8c:	697b      	ldr	r3, [r7, #20]
    /**TIM2 GPIO Configuration
    PB10     ------> TIM2_CH3
    PB11     ------> TIM2_CH4
    */
    GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
 8003a8e:	f44f 6340 	mov.w	r3, #3072	@ 0xc00
 8003a92:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8003a94:	2302      	movs	r3, #2
 8003a96:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003a98:	2300      	movs	r3, #0
 8003a9a:	627b      	str	r3, [r7, #36]	@ 0x24
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8003a9c:	2300      	movs	r3, #0
 8003a9e:	62bb      	str	r3, [r7, #40]	@ 0x28
    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
 8003aa0:	2301      	movs	r3, #1
 8003aa2:	62fb      	str	r3, [r7, #44]	@ 0x2c
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8003aa4:	f107 031c 	add.w	r3, r7, #28
 8003aa8:	4619      	mov	r1, r3
 8003aaa:	4827      	ldr	r0, [pc, #156]	@ (8003b48 <HAL_TIM_Base_MspInit+0x118>)
 8003aac:	f006 fe9e 	bl	800a7ec <HAL_GPIO_Init>

    /* TIM2 interrupt Init */
    HAL_NVIC_SetPriority(TIM2_IRQn, 5, 0);
 8003ab0:	2200      	movs	r2, #0
 8003ab2:	2105      	movs	r1, #5
 8003ab4:	201c      	movs	r0, #28
 8003ab6:	f003 fb67 	bl	8007188 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(TIM2_IRQn);
 8003aba:	201c      	movs	r0, #28
 8003abc:	f003 fb7e 	bl	80071bc <HAL_NVIC_EnableIRQ>
  /* USER CODE BEGIN TIM4_MspInit 1 */

  /* USER CODE END TIM4_MspInit 1 */
  }

}
 8003ac0:	e03b      	b.n	8003b3a <HAL_TIM_Base_MspInit+0x10a>
  else if(htim_base->Instance==TIM4)
 8003ac2:	687b      	ldr	r3, [r7, #4]
 8003ac4:	681b      	ldr	r3, [r3, #0]
 8003ac6:	4a21      	ldr	r2, [pc, #132]	@ (8003b4c <HAL_TIM_Base_MspInit+0x11c>)
 8003ac8:	4293      	cmp	r3, r2
 8003aca:	d136      	bne.n	8003b3a <HAL_TIM_Base_MspInit+0x10a>
    __HAL_RCC_TIM4_CLK_ENABLE();
 8003acc:	4b1d      	ldr	r3, [pc, #116]	@ (8003b44 <HAL_TIM_Base_MspInit+0x114>)
 8003ace:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 8003ad2:	4a1c      	ldr	r2, [pc, #112]	@ (8003b44 <HAL_TIM_Base_MspInit+0x114>)
 8003ad4:	f043 0304 	orr.w	r3, r3, #4
 8003ad8:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
 8003adc:	4b19      	ldr	r3, [pc, #100]	@ (8003b44 <HAL_TIM_Base_MspInit+0x114>)
 8003ade:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 8003ae2:	f003 0304 	and.w	r3, r3, #4
 8003ae6:	613b      	str	r3, [r7, #16]
 8003ae8:	693b      	ldr	r3, [r7, #16]
    __HAL_RCC_GPIOD_CLK_ENABLE();
 8003aea:	4b16      	ldr	r3, [pc, #88]	@ (8003b44 <HAL_TIM_Base_MspInit+0x114>)
 8003aec:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003af0:	4a14      	ldr	r2, [pc, #80]	@ (8003b44 <HAL_TIM_Base_MspInit+0x114>)
 8003af2:	f043 0308 	orr.w	r3, r3, #8
 8003af6:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8003afa:	4b12      	ldr	r3, [pc, #72]	@ (8003b44 <HAL_TIM_Base_MspInit+0x114>)
 8003afc:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003b00:	f003 0308 	and.w	r3, r3, #8
 8003b04:	60fb      	str	r3, [r7, #12]
 8003b06:	68fb      	ldr	r3, [r7, #12]
    GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
 8003b08:	f44f 4340 	mov.w	r3, #49152	@ 0xc000
 8003b0c:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8003b0e:	2302      	movs	r3, #2
 8003b10:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003b12:	2300      	movs	r3, #0
 8003b14:	627b      	str	r3, [r7, #36]	@ 0x24
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8003b16:	2300      	movs	r3, #0
 8003b18:	62bb      	str	r3, [r7, #40]	@ 0x28
    GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
 8003b1a:	2302      	movs	r3, #2
 8003b1c:	62fb      	str	r3, [r7, #44]	@ 0x2c
    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8003b1e:	f107 031c 	add.w	r3, r7, #28
 8003b22:	4619      	mov	r1, r3
 8003b24:	480a      	ldr	r0, [pc, #40]	@ (8003b50 <HAL_TIM_Base_MspInit+0x120>)
 8003b26:	f006 fe61 	bl	800a7ec <HAL_GPIO_Init>
    HAL_NVIC_SetPriority(TIM4_IRQn, 5, 0);
 8003b2a:	2200      	movs	r2, #0
 8003b2c:	2105      	movs	r1, #5
 8003b2e:	201e      	movs	r0, #30
 8003b30:	f003 fb2a 	bl	8007188 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(TIM4_IRQn);
 8003b34:	201e      	movs	r0, #30
 8003b36:	f003 fb41 	bl	80071bc <HAL_NVIC_EnableIRQ>
}
 8003b3a:	bf00      	nop
 8003b3c:	3730      	adds	r7, #48	@ 0x30
 8003b3e:	46bd      	mov	sp, r7
 8003b40:	bd80      	pop	{r7, pc}
 8003b42:	bf00      	nop
 8003b44:	58024400 	.word	0x58024400
 8003b48:	58020400 	.word	0x58020400
 8003b4c:	40000800 	.word	0x40000800
 8003b50:	58020c00 	.word	0x58020c00

08003b54 <HAL_TIM_MspPostInit>:

void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
 8003b54:	b580      	push	{r7, lr}
 8003b56:	b08a      	sub	sp, #40	@ 0x28
 8003b58:	af00      	add	r7, sp, #0
 8003b5a:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8003b5c:	f107 0314 	add.w	r3, r7, #20
 8003b60:	2200      	movs	r2, #0
 8003b62:	601a      	str	r2, [r3, #0]
 8003b64:	605a      	str	r2, [r3, #4]
 8003b66:	609a      	str	r2, [r3, #8]
 8003b68:	60da      	str	r2, [r3, #12]
 8003b6a:	611a      	str	r2, [r3, #16]
  if(htim->Instance==TIM1)
 8003b6c:	687b      	ldr	r3, [r7, #4]
 8003b6e:	681b      	ldr	r3, [r3, #0]
 8003b70:	4a26      	ldr	r2, [pc, #152]	@ (8003c0c <HAL_TIM_MspPostInit+0xb8>)
 8003b72:	4293      	cmp	r3, r2
 8003b74:	d120      	bne.n	8003bb8 <HAL_TIM_MspPostInit+0x64>
  {
  /* USER CODE BEGIN TIM1_MspPostInit 0 */

  /* USER CODE END TIM1_MspPostInit 0 */
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8003b76:	4b26      	ldr	r3, [pc, #152]	@ (8003c10 <HAL_TIM_MspPostInit+0xbc>)
 8003b78:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003b7c:	4a24      	ldr	r2, [pc, #144]	@ (8003c10 <HAL_TIM_MspPostInit+0xbc>)
 8003b7e:	f043 0301 	orr.w	r3, r3, #1
 8003b82:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8003b86:	4b22      	ldr	r3, [pc, #136]	@ (8003c10 <HAL_TIM_MspPostInit+0xbc>)
 8003b88:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003b8c:	f003 0301 	and.w	r3, r3, #1
 8003b90:	613b      	str	r3, [r7, #16]
 8003b92:	693b      	ldr	r3, [r7, #16]
    /**TIM1 GPIO Configuration
    PA9     ------> TIM1_CH2
    */
    GPIO_InitStruct.Pin = GPIO_PIN_9;
 8003b94:	f44f 7300 	mov.w	r3, #512	@ 0x200
 8003b98:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8003b9a:	2302      	movs	r3, #2
 8003b9c:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003b9e:	2300      	movs	r3, #0
 8003ba0:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8003ba2:	2300      	movs	r3, #0
 8003ba4:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
 8003ba6:	2301      	movs	r3, #1
 8003ba8:	627b      	str	r3, [r7, #36]	@ 0x24
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8003baa:	f107 0314 	add.w	r3, r7, #20
 8003bae:	4619      	mov	r1, r3
 8003bb0:	4818      	ldr	r0, [pc, #96]	@ (8003c14 <HAL_TIM_MspPostInit+0xc0>)
 8003bb2:	f006 fe1b 	bl	800a7ec <HAL_GPIO_Init>
  /* USER CODE BEGIN TIM3_MspPostInit 1 */

  /* USER CODE END TIM3_MspPostInit 1 */
  }

}
 8003bb6:	e024      	b.n	8003c02 <HAL_TIM_MspPostInit+0xae>
  else if(htim->Instance==TIM3)
 8003bb8:	687b      	ldr	r3, [r7, #4]
 8003bba:	681b      	ldr	r3, [r3, #0]
 8003bbc:	4a16      	ldr	r2, [pc, #88]	@ (8003c18 <HAL_TIM_MspPostInit+0xc4>)
 8003bbe:	4293      	cmp	r3, r2
 8003bc0:	d11f      	bne.n	8003c02 <HAL_TIM_MspPostInit+0xae>
    __HAL_RCC_GPIOC_CLK_ENABLE();
 8003bc2:	4b13      	ldr	r3, [pc, #76]	@ (8003c10 <HAL_TIM_MspPostInit+0xbc>)
 8003bc4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003bc8:	4a11      	ldr	r2, [pc, #68]	@ (8003c10 <HAL_TIM_MspPostInit+0xbc>)
 8003bca:	f043 0304 	orr.w	r3, r3, #4
 8003bce:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8003bd2:	4b0f      	ldr	r3, [pc, #60]	@ (8003c10 <HAL_TIM_MspPostInit+0xbc>)
 8003bd4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003bd8:	f003 0304 	and.w	r3, r3, #4
 8003bdc:	60fb      	str	r3, [r7, #12]
 8003bde:	68fb      	ldr	r3, [r7, #12]
    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9;
 8003be0:	f44f 7370 	mov.w	r3, #960	@ 0x3c0
 8003be4:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8003be6:	2302      	movs	r3, #2
 8003be8:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003bea:	2300      	movs	r3, #0
 8003bec:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
 8003bee:	2301      	movs	r3, #1
 8003bf0:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
 8003bf2:	2302      	movs	r3, #2
 8003bf4:	627b      	str	r3, [r7, #36]	@ 0x24
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8003bf6:	f107 0314 	add.w	r3, r7, #20
 8003bfa:	4619      	mov	r1, r3
 8003bfc:	4807      	ldr	r0, [pc, #28]	@ (8003c1c <HAL_TIM_MspPostInit+0xc8>)
 8003bfe:	f006 fdf5 	bl	800a7ec <HAL_GPIO_Init>
}
 8003c02:	bf00      	nop
 8003c04:	3728      	adds	r7, #40	@ 0x28
 8003c06:	46bd      	mov	sp, r7
 8003c08:	bd80      	pop	{r7, pc}
 8003c0a:	bf00      	nop
 8003c0c:	40010000 	.word	0x40010000
 8003c10:	58024400 	.word	0x58024400
 8003c14:	58020000 	.word	0x58020000
 8003c18:	40000400 	.word	0x40000400
 8003c1c:	58020800 	.word	0x58020800

08003c20 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8003c20:	b580      	push	{r7, lr}
 8003c22:	b0bc      	sub	sp, #240	@ 0xf0
 8003c24:	af00      	add	r7, sp, #0
 8003c26:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8003c28:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
 8003c2c:	2200      	movs	r2, #0
 8003c2e:	601a      	str	r2, [r3, #0]
 8003c30:	605a      	str	r2, [r3, #4]
 8003c32:	609a      	str	r2, [r3, #8]
 8003c34:	60da      	str	r2, [r3, #12]
 8003c36:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 8003c38:	f107 0318 	add.w	r3, r7, #24
 8003c3c:	22c0      	movs	r2, #192	@ 0xc0
 8003c3e:	2100      	movs	r1, #0
 8003c40:	4618      	mov	r0, r3
 8003c42:	f013 ffb8 	bl	8017bb6 <memset>
  if(huart->Instance==UART8)
 8003c46:	687b      	ldr	r3, [r7, #4]
 8003c48:	681b      	ldr	r3, [r3, #0]
 8003c4a:	4a55      	ldr	r2, [pc, #340]	@ (8003da0 <HAL_UART_MspInit+0x180>)
 8003c4c:	4293      	cmp	r3, r2
 8003c4e:	d14e      	bne.n	8003cee <HAL_UART_MspInit+0xce>

  /* USER CODE END UART8_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8;
 8003c50:	f04f 0202 	mov.w	r2, #2
 8003c54:	f04f 0300 	mov.w	r3, #0
 8003c58:	e9c7 2306 	strd	r2, r3, [r7, #24]
    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
 8003c5c:	2300      	movs	r3, #0
 8003c5e:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 8003c62:	f107 0318 	add.w	r3, r7, #24
 8003c66:	4618      	mov	r0, r3
 8003c68:	f008 f948 	bl	800befc <HAL_RCCEx_PeriphCLKConfig>
 8003c6c:	4603      	mov	r3, r0
 8003c6e:	2b00      	cmp	r3, #0
 8003c70:	d001      	beq.n	8003c76 <HAL_UART_MspInit+0x56>
    {
      Error_Handler();
 8003c72:	f7fe f8e3 	bl	8001e3c <Error_Handler>
    }

    /* Peripheral clock enable */
    __HAL_RCC_UART8_CLK_ENABLE();
 8003c76:	4b4b      	ldr	r3, [pc, #300]	@ (8003da4 <HAL_UART_MspInit+0x184>)
 8003c78:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 8003c7c:	4a49      	ldr	r2, [pc, #292]	@ (8003da4 <HAL_UART_MspInit+0x184>)
 8003c7e:	f043 4300 	orr.w	r3, r3, #2147483648	@ 0x80000000
 8003c82:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
 8003c86:	4b47      	ldr	r3, [pc, #284]	@ (8003da4 <HAL_UART_MspInit+0x184>)
 8003c88:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 8003c8c:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
 8003c90:	617b      	str	r3, [r7, #20]
 8003c92:	697b      	ldr	r3, [r7, #20]

    __HAL_RCC_GPIOE_CLK_ENABLE();
 8003c94:	4b43      	ldr	r3, [pc, #268]	@ (8003da4 <HAL_UART_MspInit+0x184>)
 8003c96:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003c9a:	4a42      	ldr	r2, [pc, #264]	@ (8003da4 <HAL_UART_MspInit+0x184>)
 8003c9c:	f043 0310 	orr.w	r3, r3, #16
 8003ca0:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8003ca4:	4b3f      	ldr	r3, [pc, #252]	@ (8003da4 <HAL_UART_MspInit+0x184>)
 8003ca6:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003caa:	f003 0310 	and.w	r3, r3, #16
 8003cae:	613b      	str	r3, [r7, #16]
 8003cb0:	693b      	ldr	r3, [r7, #16]
    /**UART8 GPIO Configuration
    PE0     ------> UART8_RX
    PE1     ------> UART8_TX
    */
    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
 8003cb2:	2303      	movs	r3, #3
 8003cb4:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8003cb8:	2302      	movs	r3, #2
 8003cba:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003cbe:	2300      	movs	r3, #0
 8003cc0:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8003cc4:	2300      	movs	r3, #0
 8003cc6:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
    GPIO_InitStruct.Alternate = GPIO_AF8_UART8;
 8003cca:	2308      	movs	r3, #8
 8003ccc:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 8003cd0:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
 8003cd4:	4619      	mov	r1, r3
 8003cd6:	4834      	ldr	r0, [pc, #208]	@ (8003da8 <HAL_UART_MspInit+0x188>)
 8003cd8:	f006 fd88 	bl	800a7ec <HAL_GPIO_Init>

    /* UART8 interrupt Init */
    HAL_NVIC_SetPriority(UART8_IRQn, 5, 0);
 8003cdc:	2200      	movs	r2, #0
 8003cde:	2105      	movs	r1, #5
 8003ce0:	2053      	movs	r0, #83	@ 0x53
 8003ce2:	f003 fa51 	bl	8007188 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(UART8_IRQn);
 8003ce6:	2053      	movs	r0, #83	@ 0x53
 8003ce8:	f003 fa68 	bl	80071bc <HAL_NVIC_EnableIRQ>
  /* USER CODE BEGIN USART1_MspInit 1 */

  /* USER CODE END USART1_MspInit 1 */
  }

}
 8003cec:	e053      	b.n	8003d96 <HAL_UART_MspInit+0x176>
  else if(huart->Instance==USART1)
 8003cee:	687b      	ldr	r3, [r7, #4]
 8003cf0:	681b      	ldr	r3, [r3, #0]
 8003cf2:	4a2e      	ldr	r2, [pc, #184]	@ (8003dac <HAL_UART_MspInit+0x18c>)
 8003cf4:	4293      	cmp	r3, r2
 8003cf6:	d14e      	bne.n	8003d96 <HAL_UART_MspInit+0x176>
    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
 8003cf8:	f04f 0201 	mov.w	r2, #1
 8003cfc:	f04f 0300 	mov.w	r3, #0
 8003d00:	e9c7 2306 	strd	r2, r3, [r7, #24]
    PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
 8003d04:	2300      	movs	r3, #0
 8003d06:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 8003d0a:	f107 0318 	add.w	r3, r7, #24
 8003d0e:	4618      	mov	r0, r3
 8003d10:	f008 f8f4 	bl	800befc <HAL_RCCEx_PeriphCLKConfig>
 8003d14:	4603      	mov	r3, r0
 8003d16:	2b00      	cmp	r3, #0
 8003d18:	d001      	beq.n	8003d1e <HAL_UART_MspInit+0xfe>
      Error_Handler();
 8003d1a:	f7fe f88f 	bl	8001e3c <Error_Handler>
    __HAL_RCC_USART1_CLK_ENABLE();
 8003d1e:	4b21      	ldr	r3, [pc, #132]	@ (8003da4 <HAL_UART_MspInit+0x184>)
 8003d20:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
 8003d24:	4a1f      	ldr	r2, [pc, #124]	@ (8003da4 <HAL_UART_MspInit+0x184>)
 8003d26:	f043 0310 	orr.w	r3, r3, #16
 8003d2a:	f8c2 30f0 	str.w	r3, [r2, #240]	@ 0xf0
 8003d2e:	4b1d      	ldr	r3, [pc, #116]	@ (8003da4 <HAL_UART_MspInit+0x184>)
 8003d30:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
 8003d34:	f003 0310 	and.w	r3, r3, #16
 8003d38:	60fb      	str	r3, [r7, #12]
 8003d3a:	68fb      	ldr	r3, [r7, #12]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8003d3c:	4b19      	ldr	r3, [pc, #100]	@ (8003da4 <HAL_UART_MspInit+0x184>)
 8003d3e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003d42:	4a18      	ldr	r2, [pc, #96]	@ (8003da4 <HAL_UART_MspInit+0x184>)
 8003d44:	f043 0302 	orr.w	r3, r3, #2
 8003d48:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
 8003d4c:	4b15      	ldr	r3, [pc, #84]	@ (8003da4 <HAL_UART_MspInit+0x184>)
 8003d4e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
 8003d52:	f003 0302 	and.w	r3, r3, #2
 8003d56:	60bb      	str	r3, [r7, #8]
 8003d58:	68bb      	ldr	r3, [r7, #8]
    GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
 8003d5a:	f44f 4340 	mov.w	r3, #49152	@ 0xc000
 8003d5e:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8003d62:	2302      	movs	r3, #2
 8003d64:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003d68:	2300      	movs	r3, #0
 8003d6a:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8003d6e:	2300      	movs	r3, #0
 8003d70:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
    GPIO_InitStruct.Alternate = GPIO_AF4_USART1;
 8003d74:	2304      	movs	r3, #4
 8003d76:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8003d7a:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
 8003d7e:	4619      	mov	r1, r3
 8003d80:	480b      	ldr	r0, [pc, #44]	@ (8003db0 <HAL_UART_MspInit+0x190>)
 8003d82:	f006 fd33 	bl	800a7ec <HAL_GPIO_Init>
    HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
 8003d86:	2200      	movs	r2, #0
 8003d88:	2105      	movs	r1, #5
 8003d8a:	2025      	movs	r0, #37	@ 0x25
 8003d8c:	f003 f9fc 	bl	8007188 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(USART1_IRQn);
 8003d90:	2025      	movs	r0, #37	@ 0x25
 8003d92:	f003 fa13 	bl	80071bc <HAL_NVIC_EnableIRQ>
}
 8003d96:	bf00      	nop
 8003d98:	37f0      	adds	r7, #240	@ 0xf0
 8003d9a:	46bd      	mov	sp, r7
 8003d9c:	bd80      	pop	{r7, pc}
 8003d9e:	bf00      	nop
 8003da0:	40007c00 	.word	0x40007c00
 8003da4:	58024400 	.word	0x58024400
 8003da8:	58021000 	.word	0x58021000
 8003dac:	40011000 	.word	0x40011000
 8003db0:	58020400 	.word	0x58020400

08003db4 <HAL_InitTick>:
  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
  * @param  TickPriority: Tick interrupt priority.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8003db4:	b580      	push	{r7, lr}
 8003db6:	b090      	sub	sp, #64	@ 0x40
 8003db8:	af00      	add	r7, sp, #0
 8003dba:	6078      	str	r0, [r7, #4]
  uint32_t              uwTimclock, uwAPB1Prescaler;

  uint32_t              uwPrescalerValue;
  uint32_t              pFLatency;
/*Configure the TIM6 IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8003dbc:	687b      	ldr	r3, [r7, #4]
 8003dbe:	2b0f      	cmp	r3, #15
 8003dc0:	d827      	bhi.n	8003e12 <HAL_InitTick+0x5e>
  {
  HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
 8003dc2:	2200      	movs	r2, #0
 8003dc4:	6879      	ldr	r1, [r7, #4]
 8003dc6:	2036      	movs	r0, #54	@ 0x36
 8003dc8:	f003 f9de 	bl	8007188 <HAL_NVIC_SetPriority>

  /* Enable the TIM6 global Interrupt */
  HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
 8003dcc:	2036      	movs	r0, #54	@ 0x36
 8003dce:	f003 f9f5 	bl	80071bc <HAL_NVIC_EnableIRQ>
    uwTickPrio = TickPriority;
 8003dd2:	4a29      	ldr	r2, [pc, #164]	@ (8003e78 <HAL_InitTick+0xc4>)
 8003dd4:	687b      	ldr	r3, [r7, #4]
 8003dd6:	6013      	str	r3, [r2, #0]
  {
    return HAL_ERROR;
  }

  /* Enable TIM6 clock */
  __HAL_RCC_TIM6_CLK_ENABLE();
 8003dd8:	4b28      	ldr	r3, [pc, #160]	@ (8003e7c <HAL_InitTick+0xc8>)
 8003dda:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 8003dde:	4a27      	ldr	r2, [pc, #156]	@ (8003e7c <HAL_InitTick+0xc8>)
 8003de0:	f043 0310 	orr.w	r3, r3, #16
 8003de4:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
 8003de8:	4b24      	ldr	r3, [pc, #144]	@ (8003e7c <HAL_InitTick+0xc8>)
 8003dea:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
 8003dee:	f003 0310 	and.w	r3, r3, #16
 8003df2:	60fb      	str	r3, [r7, #12]
 8003df4:	68fb      	ldr	r3, [r7, #12]

  /* Get clock configuration */
  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
 8003df6:	f107 0210 	add.w	r2, r7, #16
 8003dfa:	f107 0314 	add.w	r3, r7, #20
 8003dfe:	4611      	mov	r1, r2
 8003e00:	4618      	mov	r0, r3
 8003e02:	f008 f839 	bl	800be78 <HAL_RCC_GetClockConfig>

  /* Get APB1 prescaler */
  uwAPB1Prescaler = clkconfig.APB1CLKDivider;
 8003e06:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8003e08:	63bb      	str	r3, [r7, #56]	@ 0x38
  /* Compute TIM6 clock */
  if (uwAPB1Prescaler == RCC_HCLK_DIV1)
 8003e0a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8003e0c:	2b00      	cmp	r3, #0
 8003e0e:	d106      	bne.n	8003e1e <HAL_InitTick+0x6a>
 8003e10:	e001      	b.n	8003e16 <HAL_InitTick+0x62>
    return HAL_ERROR;
 8003e12:	2301      	movs	r3, #1
 8003e14:	e02b      	b.n	8003e6e <HAL_InitTick+0xba>
  {
    uwTimclock = HAL_RCC_GetPCLK1Freq();
 8003e16:	f008 f803 	bl	800be20 <HAL_RCC_GetPCLK1Freq>
 8003e1a:	63f8      	str	r0, [r7, #60]	@ 0x3c
 8003e1c:	e004      	b.n	8003e28 <HAL_InitTick+0x74>
  }
  else
  {
    uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
 8003e1e:	f007 ffff 	bl	800be20 <HAL_RCC_GetPCLK1Freq>
 8003e22:	4603      	mov	r3, r0
 8003e24:	005b      	lsls	r3, r3, #1
 8003e26:	63fb      	str	r3, [r7, #60]	@ 0x3c
  }

  /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
 8003e28:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8003e2a:	4a15      	ldr	r2, [pc, #84]	@ (8003e80 <HAL_InitTick+0xcc>)
 8003e2c:	fba2 2303 	umull	r2, r3, r2, r3
 8003e30:	0c9b      	lsrs	r3, r3, #18
 8003e32:	3b01      	subs	r3, #1
 8003e34:	637b      	str	r3, [r7, #52]	@ 0x34

  /* Initialize TIM6 */
  htim6.Instance = TIM6;
 8003e36:	4b13      	ldr	r3, [pc, #76]	@ (8003e84 <HAL_InitTick+0xd0>)
 8003e38:	4a13      	ldr	r2, [pc, #76]	@ (8003e88 <HAL_InitTick+0xd4>)
 8003e3a:	601a      	str	r2, [r3, #0]
  + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
  + ClockDivision = 0
  + Counter direction = Up
  */
  htim6.Init.Period = (1000000U / 1000U) - 1U;
 8003e3c:	4b11      	ldr	r3, [pc, #68]	@ (8003e84 <HAL_InitTick+0xd0>)
 8003e3e:	f240 32e7 	movw	r2, #999	@ 0x3e7
 8003e42:	60da      	str	r2, [r3, #12]
  htim6.Init.Prescaler = uwPrescalerValue;
 8003e44:	4a0f      	ldr	r2, [pc, #60]	@ (8003e84 <HAL_InitTick+0xd0>)
 8003e46:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8003e48:	6053      	str	r3, [r2, #4]
  htim6.Init.ClockDivision = 0;
 8003e4a:	4b0e      	ldr	r3, [pc, #56]	@ (8003e84 <HAL_InitTick+0xd0>)
 8003e4c:	2200      	movs	r2, #0
 8003e4e:	611a      	str	r2, [r3, #16]
  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
 8003e50:	4b0c      	ldr	r3, [pc, #48]	@ (8003e84 <HAL_InitTick+0xd0>)
 8003e52:	2200      	movs	r2, #0
 8003e54:	609a      	str	r2, [r3, #8]

  if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
 8003e56:	480b      	ldr	r0, [pc, #44]	@ (8003e84 <HAL_InitTick+0xd0>)
 8003e58:	f00a fd94 	bl	800e984 <HAL_TIM_Base_Init>
 8003e5c:	4603      	mov	r3, r0
 8003e5e:	2b00      	cmp	r3, #0
 8003e60:	d104      	bne.n	8003e6c <HAL_InitTick+0xb8>
  {
    /* Start the TIM time Base generation in interrupt mode */
    return HAL_TIM_Base_Start_IT(&htim6);
 8003e62:	4808      	ldr	r0, [pc, #32]	@ (8003e84 <HAL_InitTick+0xd0>)
 8003e64:	f00a fe56 	bl	800eb14 <HAL_TIM_Base_Start_IT>
 8003e68:	4603      	mov	r3, r0
 8003e6a:	e000      	b.n	8003e6e <HAL_InitTick+0xba>
  }

  /* Return function status */
  return HAL_ERROR;
 8003e6c:	2301      	movs	r3, #1
}
 8003e6e:	4618      	mov	r0, r3
 8003e70:	3740      	adds	r7, #64	@ 0x40
 8003e72:	46bd      	mov	sp, r7
 8003e74:	bd80      	pop	{r7, pc}
 8003e76:	bf00      	nop
 8003e78:	2400003c 	.word	0x2400003c
 8003e7c:	58024400 	.word	0x58024400
 8003e80:	431bde83 	.word	0x431bde83
 8003e84:	24000864 	.word	0x24000864
 8003e88:	40001000 	.word	0x40001000

08003e8c <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 8003e8c:	b480      	push	{r7}
 8003e8e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
   while (1)
 8003e90:	bf00      	nop
 8003e92:	e7fd      	b.n	8003e90 <NMI_Handler+0x4>

08003e94 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8003e94:	b480      	push	{r7}
 8003e96:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 8003e98:	bf00      	nop
 8003e9a:	e7fd      	b.n	8003e98 <HardFault_Handler+0x4>

08003e9c <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 8003e9c:	b480      	push	{r7}
 8003e9e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 8003ea0:	bf00      	nop
 8003ea2:	e7fd      	b.n	8003ea0 <MemManage_Handler+0x4>

08003ea4 <BusFault_Handler>:

/**
  * @brief This function handles Pre-fetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8003ea4:	b480      	push	{r7}
 8003ea6:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 8003ea8:	bf00      	nop
 8003eaa:	e7fd      	b.n	8003ea8 <BusFault_Handler+0x4>

08003eac <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8003eac:	b480      	push	{r7}
 8003eae:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 8003eb0:	bf00      	nop
 8003eb2:	e7fd      	b.n	8003eb0 <UsageFault_Handler+0x4>

08003eb4 <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 8003eb4:	b480      	push	{r7}
 8003eb6:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 8003eb8:	bf00      	nop
 8003eba:	46bd      	mov	sp, r7
 8003ebc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003ec0:	4770      	bx	lr

08003ec2 <RCC_IRQHandler>:

/**
  * @brief This function handles RCC global interrupt.
  */
void RCC_IRQHandler(void)
{
 8003ec2:	b480      	push	{r7}
 8003ec4:	af00      	add	r7, sp, #0

  /* USER CODE END RCC_IRQn 0 */
  /* USER CODE BEGIN RCC_IRQn 1 */

  /* USER CODE END RCC_IRQn 1 */
}
 8003ec6:	bf00      	nop
 8003ec8:	46bd      	mov	sp, r7
 8003eca:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003ece:	4770      	bx	lr

08003ed0 <DMA1_Stream0_IRQHandler>:

/**
  * @brief This function handles DMA1 stream0 global interrupt.
  */
void DMA1_Stream0_IRQHandler(void)
{
 8003ed0:	b580      	push	{r7, lr}
 8003ed2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */

  /* USER CODE END DMA1_Stream0_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc1);
 8003ed4:	4802      	ldr	r0, [pc, #8]	@ (8003ee0 <DMA1_Stream0_IRQHandler+0x10>)
 8003ed6:	f005 f977 	bl	80091c8 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */

  /* USER CODE END DMA1_Stream0_IRQn 1 */
}
 8003eda:	bf00      	nop
 8003edc:	bd80      	pop	{r7, pc}
 8003ede:	bf00      	nop
 8003ee0:	2400026c 	.word	0x2400026c

08003ee4 <DMA1_Stream1_IRQHandler>:

/**
  * @brief This function handles DMA1 stream1 global interrupt.
  */
void DMA1_Stream1_IRQHandler(void)
{
 8003ee4:	b580      	push	{r7, lr}
 8003ee6:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */

  /* USER CODE END DMA1_Stream1_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc2);
 8003ee8:	4802      	ldr	r0, [pc, #8]	@ (8003ef4 <DMA1_Stream1_IRQHandler+0x10>)
 8003eea:	f005 f96d 	bl	80091c8 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */

  /* USER CODE END DMA1_Stream1_IRQn 1 */
}
 8003eee:	bf00      	nop
 8003ef0:	bd80      	pop	{r7, pc}
 8003ef2:	bf00      	nop
 8003ef4:	240002e4 	.word	0x240002e4

08003ef8 <DMA1_Stream2_IRQHandler>:

/**
  * @brief This function handles DMA1 stream2 global interrupt.
  */
void DMA1_Stream2_IRQHandler(void)
{
 8003ef8:	b580      	push	{r7, lr}
 8003efa:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */

  /* USER CODE END DMA1_Stream2_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc3);
 8003efc:	4802      	ldr	r0, [pc, #8]	@ (8003f08 <DMA1_Stream2_IRQHandler+0x10>)
 8003efe:	f005 f963 	bl	80091c8 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */

  /* USER CODE END DMA1_Stream2_IRQn 1 */
}
 8003f02:	bf00      	nop
 8003f04:	bd80      	pop	{r7, pc}
 8003f06:	bf00      	nop
 8003f08:	2400035c 	.word	0x2400035c

08003f0c <EXTI9_5_IRQHandler>:

/**
  * @brief This function handles EXTI line[9:5] interrupts.
  */
void EXTI9_5_IRQHandler(void)
{
 8003f0c:	b580      	push	{r7, lr}
 8003f0e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN EXTI9_5_IRQn 0 */

  /* USER CODE END EXTI9_5_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
 8003f10:	f44f 7080 	mov.w	r0, #256	@ 0x100
 8003f14:	f006 fe65 	bl	800abe2 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
 8003f18:	f44f 7000 	mov.w	r0, #512	@ 0x200
 8003f1c:	f006 fe61 	bl	800abe2 <HAL_GPIO_EXTI_IRQHandler>
  /* USER CODE BEGIN EXTI9_5_IRQn 1 */

  /* USER CODE END EXTI9_5_IRQn 1 */
}
 8003f20:	bf00      	nop
 8003f22:	bd80      	pop	{r7, pc}

08003f24 <TIM2_IRQHandler>:

/**
  * @brief This function handles TIM2 global interrupt.
  */
void TIM2_IRQHandler(void)
{
 8003f24:	b580      	push	{r7, lr}
 8003f26:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM2_IRQn 0 */

  /* USER CODE END TIM2_IRQn 0 */
  HAL_TIM_IRQHandler(&htim2);
 8003f28:	4802      	ldr	r0, [pc, #8]	@ (8003f34 <TIM2_IRQHandler+0x10>)
 8003f2a:	f00b fa19 	bl	800f360 <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM2_IRQn 1 */

  /* USER CODE END TIM2_IRQn 1 */
}
 8003f2e:	bf00      	nop
 8003f30:	bd80      	pop	{r7, pc}
 8003f32:	bf00      	nop
 8003f34:	24000498 	.word	0x24000498

08003f38 <TIM4_IRQHandler>:

/**
  * @brief This function handles TIM4 global interrupt.
  */
void TIM4_IRQHandler(void)
{
 8003f38:	b580      	push	{r7, lr}
 8003f3a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM4_IRQn 0 */

  /* USER CODE END TIM4_IRQn 0 */
  HAL_TIM_IRQHandler(&htim4);
 8003f3c:	4802      	ldr	r0, [pc, #8]	@ (8003f48 <TIM4_IRQHandler+0x10>)
 8003f3e:	f00b fa0f 	bl	800f360 <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM4_IRQn 1 */

  /* USER CODE END TIM4_IRQn 1 */
}
 8003f42:	bf00      	nop
 8003f44:	bd80      	pop	{r7, pc}
 8003f46:	bf00      	nop
 8003f48:	24000530 	.word	0x24000530

08003f4c <USART1_IRQHandler>:

/**
  * @brief This function handles USART1 global interrupt.
  */
void USART1_IRQHandler(void)
{
 8003f4c:	b580      	push	{r7, lr}
 8003f4e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN USART1_IRQn 0 */

  /* USER CODE END USART1_IRQn 0 */
  HAL_UART_IRQHandler(&huart1);
 8003f50:	4802      	ldr	r0, [pc, #8]	@ (8003f5c <USART1_IRQHandler+0x10>)
 8003f52:	f00c fe57 	bl	8010c04 <HAL_UART_IRQHandler>
  /* USER CODE BEGIN USART1_IRQn 1 */

  /* USER CODE END USART1_IRQn 1 */
}
 8003f56:	bf00      	nop
 8003f58:	bd80      	pop	{r7, pc}
 8003f5a:	bf00      	nop
 8003f5c:	24000610 	.word	0x24000610

08003f60 <EXTI15_10_IRQHandler>:

/**
  * @brief This function handles EXTI line[15:10] interrupts.
  */
void EXTI15_10_IRQHandler(void)
{
 8003f60:	b580      	push	{r7, lr}
 8003f62:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN EXTI15_10_IRQn 0 */

  /* USER CODE END EXTI15_10_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
 8003f64:	f44f 6080 	mov.w	r0, #1024	@ 0x400
 8003f68:	f006 fe3b 	bl	800abe2 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
 8003f6c:	f44f 6000 	mov.w	r0, #2048	@ 0x800
 8003f70:	f006 fe37 	bl	800abe2 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
 8003f74:	f44f 5080 	mov.w	r0, #4096	@ 0x1000
 8003f78:	f006 fe33 	bl	800abe2 <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
 8003f7c:	f44f 5000 	mov.w	r0, #8192	@ 0x2000
 8003f80:	f006 fe2f 	bl	800abe2 <HAL_GPIO_EXTI_IRQHandler>
  /* USER CODE BEGIN EXTI15_10_IRQn 1 */

  /* USER CODE END EXTI15_10_IRQn 1 */
}
 8003f84:	bf00      	nop
 8003f86:	bd80      	pop	{r7, pc}

08003f88 <TIM6_DAC_IRQHandler>:

/**
  * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts.
  */
void TIM6_DAC_IRQHandler(void)
{
 8003f88:	b580      	push	{r7, lr}
 8003f8a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */

  /* USER CODE END TIM6_DAC_IRQn 0 */
  if (hdac1.State != HAL_DAC_STATE_RESET) {
 8003f8c:	4b06      	ldr	r3, [pc, #24]	@ (8003fa8 <TIM6_DAC_IRQHandler+0x20>)
 8003f8e:	791b      	ldrb	r3, [r3, #4]
 8003f90:	b2db      	uxtb	r3, r3
 8003f92:	2b00      	cmp	r3, #0
 8003f94:	d002      	beq.n	8003f9c <TIM6_DAC_IRQHandler+0x14>
    HAL_DAC_IRQHandler(&hdac1);
 8003f96:	4804      	ldr	r0, [pc, #16]	@ (8003fa8 <TIM6_DAC_IRQHandler+0x20>)
 8003f98:	f003 fc15 	bl	80077c6 <HAL_DAC_IRQHandler>
  }
  HAL_TIM_IRQHandler(&htim6);
 8003f9c:	4803      	ldr	r0, [pc, #12]	@ (8003fac <TIM6_DAC_IRQHandler+0x24>)
 8003f9e:	f00b f9df 	bl	800f360 <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */

  /* USER CODE END TIM6_DAC_IRQn 1 */
}
 8003fa2:	bf00      	nop
 8003fa4:	bd80      	pop	{r7, pc}
 8003fa6:	bf00      	nop
 8003fa8:	24000424 	.word	0x24000424
 8003fac:	24000864 	.word	0x24000864

08003fb0 <UART8_IRQHandler>:

/**
  * @brief This function handles UART8 global interrupt.
  */
void UART8_IRQHandler(void)
{
 8003fb0:	b580      	push	{r7, lr}
 8003fb2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UART8_IRQn 0 */

  /* USER CODE END UART8_IRQn 0 */
  HAL_UART_IRQHandler(&huart8);
 8003fb4:	4802      	ldr	r0, [pc, #8]	@ (8003fc0 <UART8_IRQHandler+0x10>)
 8003fb6:	f00c fe25 	bl	8010c04 <HAL_UART_IRQHandler>
  /* USER CODE BEGIN UART8_IRQn 1 */

  /* USER CODE END UART8_IRQn 1 */
}
 8003fba:	bf00      	nop
 8003fbc:	bd80      	pop	{r7, pc}
 8003fbe:	bf00      	nop
 8003fc0:	2400057c 	.word	0x2400057c

08003fc4 <_read>:
  _kill(status, -1);
  while (1) {}    /* Make sure we hang here */
}

__attribute__((weak)) int _read(int file, char *ptr, int len)
{
 8003fc4:	b580      	push	{r7, lr}
 8003fc6:	b086      	sub	sp, #24
 8003fc8:	af00      	add	r7, sp, #0
 8003fca:	60f8      	str	r0, [r7, #12]
 8003fcc:	60b9      	str	r1, [r7, #8]
 8003fce:	607a      	str	r2, [r7, #4]
  (void)file;
  int DataIdx;

  for (DataIdx = 0; DataIdx < len; DataIdx++)
 8003fd0:	2300      	movs	r3, #0
 8003fd2:	617b      	str	r3, [r7, #20]
 8003fd4:	e00a      	b.n	8003fec <_read+0x28>
  {
    *ptr++ = __io_getchar();
 8003fd6:	f3af 8000 	nop.w
 8003fda:	4601      	mov	r1, r0
 8003fdc:	68bb      	ldr	r3, [r7, #8]
 8003fde:	1c5a      	adds	r2, r3, #1
 8003fe0:	60ba      	str	r2, [r7, #8]
 8003fe2:	b2ca      	uxtb	r2, r1
 8003fe4:	701a      	strb	r2, [r3, #0]
  for (DataIdx = 0; DataIdx < len; DataIdx++)
 8003fe6:	697b      	ldr	r3, [r7, #20]
 8003fe8:	3301      	adds	r3, #1
 8003fea:	617b      	str	r3, [r7, #20]
 8003fec:	697a      	ldr	r2, [r7, #20]
 8003fee:	687b      	ldr	r3, [r7, #4]
 8003ff0:	429a      	cmp	r2, r3
 8003ff2:	dbf0      	blt.n	8003fd6 <_read+0x12>
  }

  return len;
 8003ff4:	687b      	ldr	r3, [r7, #4]
}
 8003ff6:	4618      	mov	r0, r3
 8003ff8:	3718      	adds	r7, #24
 8003ffa:	46bd      	mov	sp, r7
 8003ffc:	bd80      	pop	{r7, pc}

08003ffe <_write>:

__attribute__((weak)) int _write(int file, char *ptr, int len)
{
 8003ffe:	b580      	push	{r7, lr}
 8004000:	b086      	sub	sp, #24
 8004002:	af00      	add	r7, sp, #0
 8004004:	60f8      	str	r0, [r7, #12]
 8004006:	60b9      	str	r1, [r7, #8]
 8004008:	607a      	str	r2, [r7, #4]
  (void)file;
  int DataIdx;

  for (DataIdx = 0; DataIdx < len; DataIdx++)
 800400a:	2300      	movs	r3, #0
 800400c:	617b      	str	r3, [r7, #20]
 800400e:	e009      	b.n	8004024 <_write+0x26>
  {
    __io_putchar(*ptr++);
 8004010:	68bb      	ldr	r3, [r7, #8]
 8004012:	1c5a      	adds	r2, r3, #1
 8004014:	60ba      	str	r2, [r7, #8]
 8004016:	781b      	ldrb	r3, [r3, #0]
 8004018:	4618      	mov	r0, r3
 800401a:	f7fc fb4b 	bl	80006b4 <__io_putchar>
  for (DataIdx = 0; DataIdx < len; DataIdx++)
 800401e:	697b      	ldr	r3, [r7, #20]
 8004020:	3301      	adds	r3, #1
 8004022:	617b      	str	r3, [r7, #20]
 8004024:	697a      	ldr	r2, [r7, #20]
 8004026:	687b      	ldr	r3, [r7, #4]
 8004028:	429a      	cmp	r2, r3
 800402a:	dbf1      	blt.n	8004010 <_write+0x12>
  }
  return len;
 800402c:	687b      	ldr	r3, [r7, #4]
}
 800402e:	4618      	mov	r0, r3
 8004030:	3718      	adds	r7, #24
 8004032:	46bd      	mov	sp, r7
 8004034:	bd80      	pop	{r7, pc}

08004036 <_close>:

int _close(int file)
{
 8004036:	b480      	push	{r7}
 8004038:	b083      	sub	sp, #12
 800403a:	af00      	add	r7, sp, #0
 800403c:	6078      	str	r0, [r7, #4]
  (void)file;
  return -1;
 800403e:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
}
 8004042:	4618      	mov	r0, r3
 8004044:	370c      	adds	r7, #12
 8004046:	46bd      	mov	sp, r7
 8004048:	f85d 7b04 	ldr.w	r7, [sp], #4
 800404c:	4770      	bx	lr

0800404e <_fstat>:


int _fstat(int file, struct stat *st)
{
 800404e:	b480      	push	{r7}
 8004050:	b083      	sub	sp, #12
 8004052:	af00      	add	r7, sp, #0
 8004054:	6078      	str	r0, [r7, #4]
 8004056:	6039      	str	r1, [r7, #0]
  (void)file;
  st->st_mode = S_IFCHR;
 8004058:	683b      	ldr	r3, [r7, #0]
 800405a:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
 800405e:	605a      	str	r2, [r3, #4]
  return 0;
 8004060:	2300      	movs	r3, #0
}
 8004062:	4618      	mov	r0, r3
 8004064:	370c      	adds	r7, #12
 8004066:	46bd      	mov	sp, r7
 8004068:	f85d 7b04 	ldr.w	r7, [sp], #4
 800406c:	4770      	bx	lr

0800406e <_isatty>:

int _isatty(int file)
{
 800406e:	b480      	push	{r7}
 8004070:	b083      	sub	sp, #12
 8004072:	af00      	add	r7, sp, #0
 8004074:	6078      	str	r0, [r7, #4]
  (void)file;
  return 1;
 8004076:	2301      	movs	r3, #1
}
 8004078:	4618      	mov	r0, r3
 800407a:	370c      	adds	r7, #12
 800407c:	46bd      	mov	sp, r7
 800407e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004082:	4770      	bx	lr

08004084 <_lseek>:

int _lseek(int file, int ptr, int dir)
{
 8004084:	b480      	push	{r7}
 8004086:	b085      	sub	sp, #20
 8004088:	af00      	add	r7, sp, #0
 800408a:	60f8      	str	r0, [r7, #12]
 800408c:	60b9      	str	r1, [r7, #8]
 800408e:	607a      	str	r2, [r7, #4]
  (void)file;
  (void)ptr;
  (void)dir;
  return 0;
 8004090:	2300      	movs	r3, #0
}
 8004092:	4618      	mov	r0, r3
 8004094:	3714      	adds	r7, #20
 8004096:	46bd      	mov	sp, r7
 8004098:	f85d 7b04 	ldr.w	r7, [sp], #4
 800409c:	4770      	bx	lr
	...

080040a0 <_sbrk>:
 *
 * @param incr Memory size
 * @return Pointer to allocated memory
 */
void *_sbrk(ptrdiff_t incr)
{
 80040a0:	b580      	push	{r7, lr}
 80040a2:	b086      	sub	sp, #24
 80040a4:	af00      	add	r7, sp, #0
 80040a6:	6078      	str	r0, [r7, #4]
  extern uint8_t _end; /* Symbol defined in the linker script */
  extern uint8_t _estack; /* Symbol defined in the linker script */
  extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
  const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
 80040a8:	4a14      	ldr	r2, [pc, #80]	@ (80040fc <_sbrk+0x5c>)
 80040aa:	4b15      	ldr	r3, [pc, #84]	@ (8004100 <_sbrk+0x60>)
 80040ac:	1ad3      	subs	r3, r2, r3
 80040ae:	617b      	str	r3, [r7, #20]
  const uint8_t *max_heap = (uint8_t *)stack_limit;
 80040b0:	697b      	ldr	r3, [r7, #20]
 80040b2:	613b      	str	r3, [r7, #16]
  uint8_t *prev_heap_end;

  /* Initialize heap end at first call */
  if (NULL == __sbrk_heap_end)
 80040b4:	4b13      	ldr	r3, [pc, #76]	@ (8004104 <_sbrk+0x64>)
 80040b6:	681b      	ldr	r3, [r3, #0]
 80040b8:	2b00      	cmp	r3, #0
 80040ba:	d102      	bne.n	80040c2 <_sbrk+0x22>
  {
    __sbrk_heap_end = &_end;
 80040bc:	4b11      	ldr	r3, [pc, #68]	@ (8004104 <_sbrk+0x64>)
 80040be:	4a12      	ldr	r2, [pc, #72]	@ (8004108 <_sbrk+0x68>)
 80040c0:	601a      	str	r2, [r3, #0]
  }

  /* Protect heap from growing into the reserved MSP stack */
  if (__sbrk_heap_end + incr > max_heap)
 80040c2:	4b10      	ldr	r3, [pc, #64]	@ (8004104 <_sbrk+0x64>)
 80040c4:	681a      	ldr	r2, [r3, #0]
 80040c6:	687b      	ldr	r3, [r7, #4]
 80040c8:	4413      	add	r3, r2
 80040ca:	693a      	ldr	r2, [r7, #16]
 80040cc:	429a      	cmp	r2, r3
 80040ce:	d207      	bcs.n	80040e0 <_sbrk+0x40>
  {
    errno = ENOMEM;
 80040d0:	f013 fe16 	bl	8017d00 <__errno>
 80040d4:	4603      	mov	r3, r0
 80040d6:	220c      	movs	r2, #12
 80040d8:	601a      	str	r2, [r3, #0]
    return (void *)-1;
 80040da:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 80040de:	e009      	b.n	80040f4 <_sbrk+0x54>
  }

  prev_heap_end = __sbrk_heap_end;
 80040e0:	4b08      	ldr	r3, [pc, #32]	@ (8004104 <_sbrk+0x64>)
 80040e2:	681b      	ldr	r3, [r3, #0]
 80040e4:	60fb      	str	r3, [r7, #12]
  __sbrk_heap_end += incr;
 80040e6:	4b07      	ldr	r3, [pc, #28]	@ (8004104 <_sbrk+0x64>)
 80040e8:	681a      	ldr	r2, [r3, #0]
 80040ea:	687b      	ldr	r3, [r7, #4]
 80040ec:	4413      	add	r3, r2
 80040ee:	4a05      	ldr	r2, [pc, #20]	@ (8004104 <_sbrk+0x64>)
 80040f0:	6013      	str	r3, [r2, #0]

  return (void *)prev_heap_end;
 80040f2:	68fb      	ldr	r3, [r7, #12]
}
 80040f4:	4618      	mov	r0, r3
 80040f6:	3718      	adds	r7, #24
 80040f8:	46bd      	mov	sp, r7
 80040fa:	bd80      	pop	{r7, pc}
 80040fc:	24060000 	.word	0x24060000
 8004100:	00000400 	.word	0x00000400
 8004104:	240008b0 	.word	0x240008b0
 8004108:	24012de0 	.word	0x24012de0

0800410c <SystemInit>:
  *         configuration.
  * @param  None
  * @retval None
  */
void SystemInit (void)
{
 800410c:	b480      	push	{r7}
 800410e:	af00      	add	r7, sp, #0
 __IO uint32_t tmpreg;
#endif /* DATA_IN_D2_SRAM */

  /* FPU settings ------------------------------------------------------------*/
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
 8004110:	4b37      	ldr	r3, [pc, #220]	@ (80041f0 <SystemInit+0xe4>)
 8004112:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8004116:	4a36      	ldr	r2, [pc, #216]	@ (80041f0 <SystemInit+0xe4>)
 8004118:	f443 0370 	orr.w	r3, r3, #15728640	@ 0xf00000
 800411c:	f8c2 3088 	str.w	r3, [r2, #136]	@ 0x88
  #endif
  /* Reset the RCC clock configuration to the default reset state ------------*/

   /* Increasing the CPU frequency */
  if(FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
 8004120:	4b34      	ldr	r3, [pc, #208]	@ (80041f4 <SystemInit+0xe8>)
 8004122:	681b      	ldr	r3, [r3, #0]
 8004124:	f003 030f 	and.w	r3, r3, #15
 8004128:	2b06      	cmp	r3, #6
 800412a:	d807      	bhi.n	800413c <SystemInit+0x30>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
 800412c:	4b31      	ldr	r3, [pc, #196]	@ (80041f4 <SystemInit+0xe8>)
 800412e:	681b      	ldr	r3, [r3, #0]
 8004130:	f023 030f 	bic.w	r3, r3, #15
 8004134:	4a2f      	ldr	r2, [pc, #188]	@ (80041f4 <SystemInit+0xe8>)
 8004136:	f043 0307 	orr.w	r3, r3, #7
 800413a:	6013      	str	r3, [r2, #0]
  }

  /* Set HSION bit */
  RCC->CR |= RCC_CR_HSION;
 800413c:	4b2e      	ldr	r3, [pc, #184]	@ (80041f8 <SystemInit+0xec>)
 800413e:	681b      	ldr	r3, [r3, #0]
 8004140:	4a2d      	ldr	r2, [pc, #180]	@ (80041f8 <SystemInit+0xec>)
 8004142:	f043 0301 	orr.w	r3, r3, #1
 8004146:	6013      	str	r3, [r2, #0]

  /* Reset CFGR register */
  RCC->CFGR = 0x00000000;
 8004148:	4b2b      	ldr	r3, [pc, #172]	@ (80041f8 <SystemInit+0xec>)
 800414a:	2200      	movs	r2, #0
 800414c:	611a      	str	r2, [r3, #16]

  /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
  RCC->CR &= 0xEAF6ED7FU;
 800414e:	4b2a      	ldr	r3, [pc, #168]	@ (80041f8 <SystemInit+0xec>)
 8004150:	681a      	ldr	r2, [r3, #0]
 8004152:	4929      	ldr	r1, [pc, #164]	@ (80041f8 <SystemInit+0xec>)
 8004154:	4b29      	ldr	r3, [pc, #164]	@ (80041fc <SystemInit+0xf0>)
 8004156:	4013      	ands	r3, r2
 8004158:	600b      	str	r3, [r1, #0]

   /* Decreasing the number of wait states because of lower CPU frequency */
  if(FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
 800415a:	4b26      	ldr	r3, [pc, #152]	@ (80041f4 <SystemInit+0xe8>)
 800415c:	681b      	ldr	r3, [r3, #0]
 800415e:	f003 0308 	and.w	r3, r3, #8
 8004162:	2b00      	cmp	r3, #0
 8004164:	d007      	beq.n	8004176 <SystemInit+0x6a>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
 8004166:	4b23      	ldr	r3, [pc, #140]	@ (80041f4 <SystemInit+0xe8>)
 8004168:	681b      	ldr	r3, [r3, #0]
 800416a:	f023 030f 	bic.w	r3, r3, #15
 800416e:	4a21      	ldr	r2, [pc, #132]	@ (80041f4 <SystemInit+0xe8>)
 8004170:	f043 0307 	orr.w	r3, r3, #7
 8004174:	6013      	str	r3, [r2, #0]
  }

#if defined(D3_SRAM_BASE)
  /* Reset D1CFGR register */
  RCC->D1CFGR = 0x00000000;
 8004176:	4b20      	ldr	r3, [pc, #128]	@ (80041f8 <SystemInit+0xec>)
 8004178:	2200      	movs	r2, #0
 800417a:	619a      	str	r2, [r3, #24]

  /* Reset D2CFGR register */
  RCC->D2CFGR = 0x00000000;
 800417c:	4b1e      	ldr	r3, [pc, #120]	@ (80041f8 <SystemInit+0xec>)
 800417e:	2200      	movs	r2, #0
 8004180:	61da      	str	r2, [r3, #28]

  /* Reset D3CFGR register */
  RCC->D3CFGR = 0x00000000;
 8004182:	4b1d      	ldr	r3, [pc, #116]	@ (80041f8 <SystemInit+0xec>)
 8004184:	2200      	movs	r2, #0
 8004186:	621a      	str	r2, [r3, #32]

  /* Reset SRDCFGR register */
  RCC->SRDCFGR = 0x00000000;
#endif
  /* Reset PLLCKSELR register */
  RCC->PLLCKSELR = 0x02020200;
 8004188:	4b1b      	ldr	r3, [pc, #108]	@ (80041f8 <SystemInit+0xec>)
 800418a:	4a1d      	ldr	r2, [pc, #116]	@ (8004200 <SystemInit+0xf4>)
 800418c:	629a      	str	r2, [r3, #40]	@ 0x28

  /* Reset PLLCFGR register */
  RCC->PLLCFGR = 0x01FF0000;
 800418e:	4b1a      	ldr	r3, [pc, #104]	@ (80041f8 <SystemInit+0xec>)
 8004190:	4a1c      	ldr	r2, [pc, #112]	@ (8004204 <SystemInit+0xf8>)
 8004192:	62da      	str	r2, [r3, #44]	@ 0x2c
  /* Reset PLL1DIVR register */
  RCC->PLL1DIVR = 0x01010280;
 8004194:	4b18      	ldr	r3, [pc, #96]	@ (80041f8 <SystemInit+0xec>)
 8004196:	4a1c      	ldr	r2, [pc, #112]	@ (8004208 <SystemInit+0xfc>)
 8004198:	631a      	str	r2, [r3, #48]	@ 0x30
  /* Reset PLL1FRACR register */
  RCC->PLL1FRACR = 0x00000000;
 800419a:	4b17      	ldr	r3, [pc, #92]	@ (80041f8 <SystemInit+0xec>)
 800419c:	2200      	movs	r2, #0
 800419e:	635a      	str	r2, [r3, #52]	@ 0x34

  /* Reset PLL2DIVR register */
  RCC->PLL2DIVR = 0x01010280;
 80041a0:	4b15      	ldr	r3, [pc, #84]	@ (80041f8 <SystemInit+0xec>)
 80041a2:	4a19      	ldr	r2, [pc, #100]	@ (8004208 <SystemInit+0xfc>)
 80041a4:	639a      	str	r2, [r3, #56]	@ 0x38

  /* Reset PLL2FRACR register */

  RCC->PLL2FRACR = 0x00000000;
 80041a6:	4b14      	ldr	r3, [pc, #80]	@ (80041f8 <SystemInit+0xec>)
 80041a8:	2200      	movs	r2, #0
 80041aa:	63da      	str	r2, [r3, #60]	@ 0x3c
  /* Reset PLL3DIVR register */
  RCC->PLL3DIVR = 0x01010280;
 80041ac:	4b12      	ldr	r3, [pc, #72]	@ (80041f8 <SystemInit+0xec>)
 80041ae:	4a16      	ldr	r2, [pc, #88]	@ (8004208 <SystemInit+0xfc>)
 80041b0:	641a      	str	r2, [r3, #64]	@ 0x40

  /* Reset PLL3FRACR register */
  RCC->PLL3FRACR = 0x00000000;
 80041b2:	4b11      	ldr	r3, [pc, #68]	@ (80041f8 <SystemInit+0xec>)
 80041b4:	2200      	movs	r2, #0
 80041b6:	645a      	str	r2, [r3, #68]	@ 0x44

  /* Reset HSEBYP bit */
  RCC->CR &= 0xFFFBFFFFU;
 80041b8:	4b0f      	ldr	r3, [pc, #60]	@ (80041f8 <SystemInit+0xec>)
 80041ba:	681b      	ldr	r3, [r3, #0]
 80041bc:	4a0e      	ldr	r2, [pc, #56]	@ (80041f8 <SystemInit+0xec>)
 80041be:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
 80041c2:	6013      	str	r3, [r2, #0]

  /* Disable all interrupts */
  RCC->CIER = 0x00000000;
 80041c4:	4b0c      	ldr	r3, [pc, #48]	@ (80041f8 <SystemInit+0xec>)
 80041c6:	2200      	movs	r2, #0
 80041c8:	661a      	str	r2, [r3, #96]	@ 0x60

#if (STM32H7_DEV_ID == 0x450UL)
  /* dual core CM7 or single core line */
  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
 80041ca:	4b10      	ldr	r3, [pc, #64]	@ (800420c <SystemInit+0x100>)
 80041cc:	681a      	ldr	r2, [r3, #0]
 80041ce:	4b10      	ldr	r3, [pc, #64]	@ (8004210 <SystemInit+0x104>)
 80041d0:	4013      	ands	r3, r2
 80041d2:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 80041d6:	d202      	bcs.n	80041de <SystemInit+0xd2>
  {
    /* if stm32h7 revY*/
    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
    *((__IO uint32_t*)0x51008108) = 0x000000001U;
 80041d8:	4b0e      	ldr	r3, [pc, #56]	@ (8004214 <SystemInit+0x108>)
 80041da:	2201      	movs	r2, #1
 80041dc:	601a      	str	r2, [r3, #0]
  /*
   * Disable the FMC bank1 (enabled after reset).
   * This, prevents CPU speculation access on this bank which blocks the use of FMC during
   * 24us. During this time the others FMC master (such as LTDC) cannot use it!
   */
  FMC_Bank1_R->BTCR[0] = 0x000030D2;
 80041de:	4b0e      	ldr	r3, [pc, #56]	@ (8004218 <SystemInit+0x10c>)
 80041e0:	f243 02d2 	movw	r2, #12498	@ 0x30d2
 80041e4:	601a      	str	r2, [r3, #0]
#if defined(USER_VECT_TAB_ADDRESS)
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */

#endif /*DUAL_CORE && CORE_CM4*/
}
 80041e6:	bf00      	nop
 80041e8:	46bd      	mov	sp, r7
 80041ea:	f85d 7b04 	ldr.w	r7, [sp], #4
 80041ee:	4770      	bx	lr
 80041f0:	e000ed00 	.word	0xe000ed00
 80041f4:	52002000 	.word	0x52002000
 80041f8:	58024400 	.word	0x58024400
 80041fc:	eaf6ed7f 	.word	0xeaf6ed7f
 8004200:	02020200 	.word	0x02020200
 8004204:	01ff0000 	.word	0x01ff0000
 8004208:	01010280 	.word	0x01010280
 800420c:	5c001000 	.word	0x5c001000
 8004210:	ffff0000 	.word	0xffff0000
 8004214:	51008108 	.word	0x51008108
 8004218:	52004000 	.word	0x52004000

0800421c <__NVIC_SystemReset>:
{
 800421c:	b480      	push	{r7}
 800421e:	af00      	add	r7, sp, #0
  __ASM volatile ("dsb 0xF":::"memory");
 8004220:	f3bf 8f4f 	dsb	sy
}
 8004224:	bf00      	nop
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
 8004226:	4b06      	ldr	r3, [pc, #24]	@ (8004240 <__NVIC_SystemReset+0x24>)
 8004228:	68db      	ldr	r3, [r3, #12]
 800422a:	f403 62e0 	and.w	r2, r3, #1792	@ 0x700
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
 800422e:	4904      	ldr	r1, [pc, #16]	@ (8004240 <__NVIC_SystemReset+0x24>)
 8004230:	4b04      	ldr	r3, [pc, #16]	@ (8004244 <__NVIC_SystemReset+0x28>)
 8004232:	4313      	orrs	r3, r2
 8004234:	60cb      	str	r3, [r1, #12]
  __ASM volatile ("dsb 0xF":::"memory");
 8004236:	f3bf 8f4f 	dsb	sy
}
 800423a:	bf00      	nop
    __NOP();
 800423c:	bf00      	nop
 800423e:	e7fd      	b.n	800423c <__NVIC_SystemReset+0x20>
 8004240:	e000ed00 	.word	0xe000ed00
 8004244:	05fa0004 	.word	0x05fa0004

08004248 <UartTasksInit>:

uint32_t slaveLastSeen[SLAVES_COUNT] = { 0 };

extern RNG_HandleTypeDef hrng;

void UartTasksInit (void) {
 8004248:	b580      	push	{r7, lr}
 800424a:	af00      	add	r7, sp, #0
    uart1TaskData.uartRxBuffer           = uart1RxBuffer;
 800424c:	4b13      	ldr	r3, [pc, #76]	@ (800429c <UartTasksInit+0x54>)
 800424e:	4a14      	ldr	r2, [pc, #80]	@ (80042a0 <UartTasksInit+0x58>)
 8004250:	601a      	str	r2, [r3, #0]
    uart1TaskData.uartRxBufferLen        = UART1_RX_BUFF_SIZE;
 8004252:	4b12      	ldr	r3, [pc, #72]	@ (800429c <UartTasksInit+0x54>)
 8004254:	f44f 7280 	mov.w	r2, #256	@ 0x100
 8004258:	809a      	strh	r2, [r3, #4]
    uart1TaskData.uartTxBuffer           = uart1TxBuffer;
 800425a:	4b10      	ldr	r3, [pc, #64]	@ (800429c <UartTasksInit+0x54>)
 800425c:	4a11      	ldr	r2, [pc, #68]	@ (80042a4 <UartTasksInit+0x5c>)
 800425e:	609a      	str	r2, [r3, #8]
    uart1TaskData.uartRxBufferLen        = UART1_TX_BUFF_SIZE;
 8004260:	4b0e      	ldr	r3, [pc, #56]	@ (800429c <UartTasksInit+0x54>)
 8004262:	f44f 7280 	mov.w	r2, #256	@ 0x100
 8004266:	809a      	strh	r2, [r3, #4]
    uart1TaskData.frameData              = uart1TaskFrameData;
 8004268:	4b0c      	ldr	r3, [pc, #48]	@ (800429c <UartTasksInit+0x54>)
 800426a:	4a0f      	ldr	r2, [pc, #60]	@ (80042a8 <UartTasksInit+0x60>)
 800426c:	611a      	str	r2, [r3, #16]
    uart1TaskData.frameDataLen           = UART1_RX_BUFF_SIZE;
 800426e:	4b0b      	ldr	r3, [pc, #44]	@ (800429c <UartTasksInit+0x54>)
 8004270:	f44f 7280 	mov.w	r2, #256	@ 0x100
 8004274:	829a      	strh	r2, [r3, #20]
    uart1TaskData.huart                  = &huart1;
 8004276:	4b09      	ldr	r3, [pc, #36]	@ (800429c <UartTasksInit+0x54>)
 8004278:	4a0c      	ldr	r2, [pc, #48]	@ (80042ac <UartTasksInit+0x64>)
 800427a:	631a      	str	r2, [r3, #48]	@ 0x30
    uart1TaskData.uartNumber             = 1;
 800427c:	4b07      	ldr	r3, [pc, #28]	@ (800429c <UartTasksInit+0x54>)
 800427e:	2201      	movs	r2, #1
 8004280:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
    uart1TaskData.processDataCb          = Uart1ReceivedDataProcessCallback;
 8004284:	4b05      	ldr	r3, [pc, #20]	@ (800429c <UartTasksInit+0x54>)
 8004286:	4a0a      	ldr	r2, [pc, #40]	@ (80042b0 <UartTasksInit+0x68>)
 8004288:	629a      	str	r2, [r3, #40]	@ 0x28
    uart1TaskData.processRxDataMsgBuffer = NULL;
 800428a:	4b04      	ldr	r3, [pc, #16]	@ (800429c <UartTasksInit+0x54>)
 800428c:	2200      	movs	r2, #0
 800428e:	625a      	str	r2, [r3, #36]	@ 0x24

    UartTaskCreate (&uart1TaskData);
 8004290:	4802      	ldr	r0, [pc, #8]	@ (800429c <UartTasksInit+0x54>)
 8004292:	f000 f80f 	bl	80042b4 <UartTaskCreate>
}
 8004296:	bf00      	nop
 8004298:	bd80      	pop	{r7, pc}
 800429a:	bf00      	nop
 800429c:	24000bb4 	.word	0x24000bb4
 80042a0:	240008b4 	.word	0x240008b4
 80042a4:	240009b4 	.word	0x240009b4
 80042a8:	24000ab4 	.word	0x24000ab4
 80042ac:	24000610 	.word	0x24000610
 80042b0:	080049b9 	.word	0x080049b9

080042b4 <UartTaskCreate>:

void UartTaskCreate (UartTaskData* uartTaskData) {
 80042b4:	b580      	push	{r7, lr}
 80042b6:	b08c      	sub	sp, #48	@ 0x30
 80042b8:	af00      	add	r7, sp, #0
 80042ba:	6078      	str	r0, [r7, #4]
    osThreadAttr_t osThreadAttrRxUart   = { 0 };
 80042bc:	f107 030c 	add.w	r3, r7, #12
 80042c0:	2224      	movs	r2, #36	@ 0x24
 80042c2:	2100      	movs	r1, #0
 80042c4:	4618      	mov	r0, r3
 80042c6:	f013 fc76 	bl	8017bb6 <memset>
    osThreadAttrRxUart.stack_size       = configMINIMAL_STACK_SIZE * 2;
 80042ca:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 80042ce:	623b      	str	r3, [r7, #32]
    osThreadAttrRxUart.priority         = (osPriority_t)osPriorityHigh;
 80042d0:	2328      	movs	r3, #40	@ 0x28
 80042d2:	627b      	str	r3, [r7, #36]	@ 0x24
    uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart);
 80042d4:	f107 030c 	add.w	r3, r7, #12
 80042d8:	461a      	mov	r2, r3
 80042da:	6879      	ldr	r1, [r7, #4]
 80042dc:	4804      	ldr	r0, [pc, #16]	@ (80042f0 <UartTaskCreate+0x3c>)
 80042de:	f00f f9ff 	bl	80136e0 <osThreadNew>
 80042e2:	4602      	mov	r2, r0
 80042e4:	687b      	ldr	r3, [r7, #4]
 80042e6:	619a      	str	r2, [r3, #24]
}
 80042e8:	bf00      	nop
 80042ea:	3730      	adds	r7, #48	@ 0x30
 80042ec:	46bd      	mov	sp, r7
 80042ee:	bd80      	pop	{r7, pc}
 80042f0:	08004409 	.word	0x08004409

080042f4 <HAL_UART_RxCpltCallback>:
    uart8TaskData.huart                 = &huart8;
    uart8TaskData.uartNumber            = 8;
    uart8TaskData.uartRecieveTaskHandle = osThreadNew (UartRxTask, &uart8TaskData, &osThreadAttrRxUart);
}

void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) {
 80042f4:	b480      	push	{r7}
 80042f6:	b083      	sub	sp, #12
 80042f8:	af00      	add	r7, sp, #0
 80042fa:	6078      	str	r0, [r7, #4]
}
 80042fc:	bf00      	nop
 80042fe:	370c      	adds	r7, #12
 8004300:	46bd      	mov	sp, r7
 8004302:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004306:	4770      	bx	lr

08004308 <HAL_UARTEx_RxEventCallback>:

void HAL_UARTEx_RxEventCallback (UART_HandleTypeDef* huart, uint16_t Size) {
 8004308:	b580      	push	{r7, lr}
 800430a:	b082      	sub	sp, #8
 800430c:	af00      	add	r7, sp, #0
 800430e:	6078      	str	r0, [r7, #4]
 8004310:	460b      	mov	r3, r1
 8004312:	807b      	strh	r3, [r7, #2]
    if (huart->Instance == USART1) {
 8004314:	687b      	ldr	r3, [r7, #4]
 8004316:	681b      	ldr	r3, [r3, #0]
 8004318:	4a0c      	ldr	r2, [pc, #48]	@ (800434c <HAL_UARTEx_RxEventCallback+0x44>)
 800431a:	4293      	cmp	r3, r2
 800431c:	d106      	bne.n	800432c <HAL_UARTEx_RxEventCallback+0x24>
        HandleUartRxCallback (&uart1TaskData, huart, Size);
 800431e:	887b      	ldrh	r3, [r7, #2]
 8004320:	461a      	mov	r2, r3
 8004322:	6879      	ldr	r1, [r7, #4]
 8004324:	480a      	ldr	r0, [pc, #40]	@ (8004350 <HAL_UARTEx_RxEventCallback+0x48>)
 8004326:	f000 f823 	bl	8004370 <HandleUartRxCallback>
    } else if (huart->Instance == UART8) {
        HandleUartRxCallback (&uart8TaskData, huart, Size);
    }
}
 800432a:	e00a      	b.n	8004342 <HAL_UARTEx_RxEventCallback+0x3a>
    } else if (huart->Instance == UART8) {
 800432c:	687b      	ldr	r3, [r7, #4]
 800432e:	681b      	ldr	r3, [r3, #0]
 8004330:	4a08      	ldr	r2, [pc, #32]	@ (8004354 <HAL_UARTEx_RxEventCallback+0x4c>)
 8004332:	4293      	cmp	r3, r2
 8004334:	d105      	bne.n	8004342 <HAL_UARTEx_RxEventCallback+0x3a>
        HandleUartRxCallback (&uart8TaskData, huart, Size);
 8004336:	887b      	ldrh	r3, [r7, #2]
 8004338:	461a      	mov	r2, r3
 800433a:	6879      	ldr	r1, [r7, #4]
 800433c:	4806      	ldr	r0, [pc, #24]	@ (8004358 <HAL_UARTEx_RxEventCallback+0x50>)
 800433e:	f000 f817 	bl	8004370 <HandleUartRxCallback>
}
 8004342:	bf00      	nop
 8004344:	3708      	adds	r7, #8
 8004346:	46bd      	mov	sp, r7
 8004348:	bd80      	pop	{r7, pc}
 800434a:	bf00      	nop
 800434c:	40011000 	.word	0x40011000
 8004350:	24000bb4 	.word	0x24000bb4
 8004354:	40007c00 	.word	0x40007c00
 8004358:	24000bec 	.word	0x24000bec

0800435c <HAL_UART_TxCpltCallback>:

void HAL_UART_TxCpltCallback (UART_HandleTypeDef* huart) {
 800435c:	b480      	push	{r7}
 800435e:	b083      	sub	sp, #12
 8004360:	af00      	add	r7, sp, #0
 8004362:	6078      	str	r0, [r7, #4]
    if (huart->Instance == UART8) {
    }
}
 8004364:	bf00      	nop
 8004366:	370c      	adds	r7, #12
 8004368:	46bd      	mov	sp, r7
 800436a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800436e:	4770      	bx	lr

08004370 <HandleUartRxCallback>:

void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) {
 8004370:	b580      	push	{r7, lr}
 8004372:	b088      	sub	sp, #32
 8004374:	af02      	add	r7, sp, #8
 8004376:	60f8      	str	r0, [r7, #12]
 8004378:	60b9      	str	r1, [r7, #8]
 800437a:	4613      	mov	r3, r2
 800437c:	80fb      	strh	r3, [r7, #6]
    BaseType_t pxHigherPriorityTaskWoken = pdFALSE;
 800437e:	2300      	movs	r3, #0
 8004380:	617b      	str	r3, [r7, #20]
    osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
 8004382:	68fb      	ldr	r3, [r7, #12]
 8004384:	6a1b      	ldr	r3, [r3, #32]
 8004386:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 800438a:	4618      	mov	r0, r3
 800438c:	f00f fbd3 	bl	8013b36 <osMutexAcquire>
    memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size);
 8004390:	68fb      	ldr	r3, [r7, #12]
 8004392:	691b      	ldr	r3, [r3, #16]
 8004394:	68fa      	ldr	r2, [r7, #12]
 8004396:	8ad2      	ldrh	r2, [r2, #22]
 8004398:	1898      	adds	r0, r3, r2
 800439a:	68fb      	ldr	r3, [r7, #12]
 800439c:	681b      	ldr	r3, [r3, #0]
 800439e:	88fa      	ldrh	r2, [r7, #6]
 80043a0:	4619      	mov	r1, r3
 80043a2:	f013 fcda 	bl	8017d5a <memcpy>
    uartTaskData->frameBytesCount += Size;
 80043a6:	68fb      	ldr	r3, [r7, #12]
 80043a8:	8ada      	ldrh	r2, [r3, #22]
 80043aa:	88fb      	ldrh	r3, [r7, #6]
 80043ac:	4413      	add	r3, r2
 80043ae:	b29a      	uxth	r2, r3
 80043b0:	68fb      	ldr	r3, [r7, #12]
 80043b2:	82da      	strh	r2, [r3, #22]
    osMutexRelease (uartTaskData->rxDataBufferMutex);
 80043b4:	68fb      	ldr	r3, [r7, #12]
 80043b6:	6a1b      	ldr	r3, [r3, #32]
 80043b8:	4618      	mov	r0, r3
 80043ba:	f00f fc07 	bl	8013bcc <osMutexRelease>
    xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken);
 80043be:	68fb      	ldr	r3, [r7, #12]
 80043c0:	6998      	ldr	r0, [r3, #24]
 80043c2:	88f9      	ldrh	r1, [r7, #6]
 80043c4:	f107 0314 	add.w	r3, r7, #20
 80043c8:	9300      	str	r3, [sp, #0]
 80043ca:	2300      	movs	r3, #0
 80043cc:	2203      	movs	r2, #3
 80043ce:	f012 f8f7 	bl	80165c0 <xTaskGenericNotifyFromISR>
    HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
 80043d2:	68fb      	ldr	r3, [r7, #12]
 80043d4:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 80043d6:	68fb      	ldr	r3, [r7, #12]
 80043d8:	6819      	ldr	r1, [r3, #0]
 80043da:	68fb      	ldr	r3, [r7, #12]
 80043dc:	889b      	ldrh	r3, [r3, #4]
 80043de:	461a      	mov	r2, r3
 80043e0:	f00f f851 	bl	8013486 <HAL_UARTEx_ReceiveToIdle_IT>
    portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken);
 80043e4:	697b      	ldr	r3, [r7, #20]
 80043e6:	2b00      	cmp	r3, #0
 80043e8:	d007      	beq.n	80043fa <HandleUartRxCallback+0x8a>
 80043ea:	4b06      	ldr	r3, [pc, #24]	@ (8004404 <HandleUartRxCallback+0x94>)
 80043ec:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80043f0:	601a      	str	r2, [r3, #0]
 80043f2:	f3bf 8f4f 	dsb	sy
 80043f6:	f3bf 8f6f 	isb	sy
}
 80043fa:	bf00      	nop
 80043fc:	3718      	adds	r7, #24
 80043fe:	46bd      	mov	sp, r7
 8004400:	bd80      	pop	{r7, pc}
 8004402:	bf00      	nop
 8004404:	e000ed04 	.word	0xe000ed04

08004408 <UartRxTask>:

void UartRxTask (void* argument) {
 8004408:	b580      	push	{r7, lr}
 800440a:	b0d2      	sub	sp, #328	@ 0x148
 800440c:	af02      	add	r7, sp, #8
 800440e:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8004412:	f5a3 739e 	sub.w	r3, r3, #316	@ 0x13c
 8004416:	6018      	str	r0, [r3, #0]
    UartTaskData* uartTaskData             = (UartTaskData*)argument;
 8004418:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 800441c:	f5a3 739e 	sub.w	r3, r3, #316	@ 0x13c
 8004420:	681b      	ldr	r3, [r3, #0]
 8004422:	f8c7 312c 	str.w	r3, [r7, #300]	@ 0x12c
    SerialProtocolFrameData spFrameData    = { 0 };
 8004426:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 800442a:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 800442e:	4618      	mov	r0, r3
 8004430:	f44f 7386 	mov.w	r3, #268	@ 0x10c
 8004434:	461a      	mov	r2, r3
 8004436:	2100      	movs	r1, #0
 8004438:	f013 fbbd 	bl	8017bb6 <memset>
    uint32_t bytesRec                      = 0;
 800443c:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8004440:	f5a3 739a 	sub.w	r3, r3, #308	@ 0x134
 8004444:	2200      	movs	r2, #0
 8004446:	601a      	str	r2, [r3, #0]
    uint32_t crc                           = 0;
 8004448:	2300      	movs	r3, #0
 800444a:	f8c7 3128 	str.w	r3, [r7, #296]	@ 0x128
    uint16_t frameCommandRaw               = 0x0000;
 800444e:	2300      	movs	r3, #0
 8004450:	f8a7 3126 	strh.w	r3, [r7, #294]	@ 0x126
    uint16_t frameBytesCount               = 0;
 8004454:	2300      	movs	r3, #0
 8004456:	f8a7 3124 	strh.w	r3, [r7, #292]	@ 0x124
    uint16_t frameCrc                      = 0;
 800445a:	2300      	movs	r3, #0
 800445c:	f8a7 3122 	strh.w	r3, [r7, #290]	@ 0x122
    uint16_t frameTotalLength              = 0;
 8004460:	2300      	movs	r3, #0
 8004462:	f8a7 313e 	strh.w	r3, [r7, #318]	@ 0x13e
    uint16_t dataToSend                    = 0;
 8004466:	2300      	movs	r3, #0
 8004468:	f8a7 313c 	strh.w	r3, [r7, #316]	@ 0x13c
    portBASE_TYPE crcPass                  = pdFAIL;
 800446c:	2300      	movs	r3, #0
 800446e:	f8c7 3138 	str.w	r3, [r7, #312]	@ 0x138
    portBASE_TYPE proceed                  = pdFALSE;
 8004472:	2300      	movs	r3, #0
 8004474:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
    portBASE_TYPE frameTimeout             = pdFAIL;
 8004478:	2300      	movs	r3, #0
 800447a:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
    enum SerialReceiverStates receverState = srWaitForHeader;
 800447e:	2300      	movs	r3, #0
 8004480:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133

    uartTaskData->rxDataBufferMutex = osMutexNew (NULL);
 8004484:	2000      	movs	r0, #0
 8004486:	f00f fad0 	bl	8013a2a <osMutexNew>
 800448a:	4602      	mov	r2, r0
 800448c:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004490:	621a      	str	r2, [r3, #32]
    HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
 8004492:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004496:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 8004498:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800449c:	6819      	ldr	r1, [r3, #0]
 800449e:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80044a2:	889b      	ldrh	r3, [r3, #4]
 80044a4:	461a      	mov	r2, r3
 80044a6:	f00e ffee 	bl	8013486 <HAL_UARTEx_ReceiveToIdle_IT>
    while (pdTRUE) {
        frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
 80044aa:	f107 020c 	add.w	r2, r7, #12
 80044ae:	f44f 63fa 	mov.w	r3, #2000	@ 0x7d0
 80044b2:	2100      	movs	r1, #0
 80044b4:	2000      	movs	r0, #0
 80044b6:	f011 ff61 	bl	801637c <xTaskNotifyWait>
 80044ba:	4603      	mov	r3, r0
 80044bc:	2b00      	cmp	r3, #0
 80044be:	bf0c      	ite	eq
 80044c0:	2301      	moveq	r3, #1
 80044c2:	2300      	movne	r3, #0
 80044c4:	b2db      	uxtb	r3, r3
 80044c6:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c

        osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
 80044ca:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80044ce:	6a1b      	ldr	r3, [r3, #32]
 80044d0:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80044d4:	4618      	mov	r0, r3
 80044d6:	f00f fb2e 	bl	8013b36 <osMutexAcquire>
        frameBytesCount = uartTaskData->frameBytesCount;
 80044da:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80044de:	8adb      	ldrh	r3, [r3, #22]
 80044e0:	f8a7 3124 	strh.w	r3, [r7, #292]	@ 0x124
        osMutexRelease (uartTaskData->rxDataBufferMutex);
 80044e4:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80044e8:	6a1b      	ldr	r3, [r3, #32]
 80044ea:	4618      	mov	r0, r3
 80044ec:	f00f fb6e 	bl	8013bcc <osMutexRelease>
        if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) {
 80044f0:	f8d7 311c 	ldr.w	r3, [r7, #284]	@ 0x11c
 80044f4:	2b01      	cmp	r3, #1
 80044f6:	d10a      	bne.n	800450e <UartRxTask+0x106>
 80044f8:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 80044fc:	2b00      	cmp	r3, #0
 80044fe:	d006      	beq.n	800450e <UartRxTask+0x106>
            receverState = srFail;
 8004500:	2304      	movs	r3, #4
 8004502:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
            proceed      = pdTRUE;
 8004506:	2301      	movs	r3, #1
 8004508:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
 800450c:	e029      	b.n	8004562 <UartRxTask+0x15a>
        } else {
            if (frameTimeout == pdFALSE) {
 800450e:	f8d7 311c 	ldr.w	r3, [r7, #284]	@ 0x11c
 8004512:	2b00      	cmp	r3, #0
 8004514:	d111      	bne.n	800453a <UartRxTask+0x132>
                proceed = pdTRUE;
 8004516:	2301      	movs	r3, #1
 8004518:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
                printf ("Uart%d: RX bytes received: %ld\n", uartTaskData->uartNumber, bytesRec);
 800451c:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004520:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8004524:	4619      	mov	r1, r3
 8004526:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 800452a:	f5a3 739a 	sub.w	r3, r3, #308	@ 0x134
 800452e:	681b      	ldr	r3, [r3, #0]
 8004530:	461a      	mov	r2, r3
 8004532:	48c1      	ldr	r0, [pc, #772]	@ (8004838 <UartRxTask+0x430>)
 8004534:	f013 faea 	bl	8017b0c <iprintf>
 8004538:	e22f      	b.n	800499a <UartRxTask+0x592>
            } else {
                if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) {
 800453a:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800453e:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8004540:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 8004544:	2b20      	cmp	r3, #32
 8004546:	f040 8228 	bne.w	800499a <UartRxTask+0x592>
                    HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
 800454a:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800454e:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 8004550:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004554:	6819      	ldr	r1, [r3, #0]
 8004556:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800455a:	889b      	ldrh	r3, [r3, #4]
 800455c:	461a      	mov	r2, r3
 800455e:	f00e ff92 	bl	8013486 <HAL_UARTEx_ReceiveToIdle_IT>
                }
            }
        }

        while (proceed) {
 8004562:	e21a      	b.n	800499a <UartRxTask+0x592>
            switch (receverState) {
 8004564:	f897 3133 	ldrb.w	r3, [r7, #307]	@ 0x133
 8004568:	2b04      	cmp	r3, #4
 800456a:	f200 81f1 	bhi.w	8004950 <UartRxTask+0x548>
 800456e:	a201      	add	r2, pc, #4	@ (adr r2, 8004574 <UartRxTask+0x16c>)
 8004570:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8004574:	08004589 	.word	0x08004589
 8004578:	080046eb 	.word	0x080046eb
 800457c:	080046cf 	.word	0x080046cf
 8004580:	0800478b 	.word	0x0800478b
 8004584:	08004845 	.word	0x08004845
            case srWaitForHeader:
                osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
 8004588:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800458c:	6a1b      	ldr	r3, [r3, #32]
 800458e:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8004592:	4618      	mov	r0, r3
 8004594:	f00f facf 	bl	8013b36 <osMutexAcquire>
                if (uartTaskData->frameData[0] == FRAME_INDICATOR) {
 8004598:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800459c:	691b      	ldr	r3, [r3, #16]
 800459e:	781b      	ldrb	r3, [r3, #0]
 80045a0:	2baa      	cmp	r3, #170	@ 0xaa
 80045a2:	f040 8082 	bne.w	80046aa <UartRxTask+0x2a2>
                    if (frameBytesCount > FRAME_ID_LENGTH) {
 80045a6:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 80045aa:	2b02      	cmp	r3, #2
 80045ac:	d914      	bls.n	80045d8 <UartRxTask+0x1d0>
                        spFrameData.frameHeader.frameId =
                        CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_ID_LENGTH - FRAME_COMMAND_LENGTH]));
 80045ae:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80045b2:	691b      	ldr	r3, [r3, #16]
 80045b4:	3302      	adds	r3, #2
 80045b6:	781b      	ldrb	r3, [r3, #0]
 80045b8:	021b      	lsls	r3, r3, #8
 80045ba:	b21a      	sxth	r2, r3
 80045bc:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80045c0:	691b      	ldr	r3, [r3, #16]
 80045c2:	3301      	adds	r3, #1
 80045c4:	781b      	ldrb	r3, [r3, #0]
 80045c6:	b21b      	sxth	r3, r3
 80045c8:	4313      	orrs	r3, r2
 80045ca:	b21b      	sxth	r3, r3
 80045cc:	b29a      	uxth	r2, r3
                        spFrameData.frameHeader.frameId =
 80045ce:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 80045d2:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 80045d6:	801a      	strh	r2, [r3, #0]
                    }
                    if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) {
 80045d8:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 80045dc:	2b04      	cmp	r3, #4
 80045de:	d923      	bls.n	8004628 <UartRxTask+0x220>
                        frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH]));
 80045e0:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80045e4:	691b      	ldr	r3, [r3, #16]
 80045e6:	3304      	adds	r3, #4
 80045e8:	781b      	ldrb	r3, [r3, #0]
 80045ea:	021b      	lsls	r3, r3, #8
 80045ec:	b21a      	sxth	r2, r3
 80045ee:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80045f2:	691b      	ldr	r3, [r3, #16]
 80045f4:	3303      	adds	r3, #3
 80045f6:	781b      	ldrb	r3, [r3, #0]
 80045f8:	b21b      	sxth	r3, r3
 80045fa:	4313      	orrs	r3, r2
 80045fc:	b21b      	sxth	r3, r3
 80045fe:	f8a7 3126 	strh.w	r3, [r7, #294]	@ 0x126
                        spFrameData.frameHeader.frameCommand    = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF);
 8004602:	f8b7 3126 	ldrh.w	r3, [r7, #294]	@ 0x126
 8004606:	b2da      	uxtb	r2, r3
 8004608:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 800460c:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8004610:	709a      	strb	r2, [r3, #2]
                        spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE;
 8004612:	f9b7 3126 	ldrsh.w	r3, [r7, #294]	@ 0x126
 8004616:	13db      	asrs	r3, r3, #15
 8004618:	b21b      	sxth	r3, r3
 800461a:	f003 0201 	and.w	r2, r3, #1
 800461e:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8004622:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8004626:	609a      	str	r2, [r3, #8]
                    }
                    if ((frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH) && ((spFrameData.frameHeader.frameCommand & 0x8000) != 0)) {
 8004628:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 800462c:	2b05      	cmp	r3, #5
 800462e:	d913      	bls.n	8004658 <UartRxTask+0x250>
 8004630:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8004634:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8004638:	789b      	ldrb	r3, [r3, #2]
 800463a:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 800463e:	2b00      	cmp	r3, #0
 8004640:	d00a      	beq.n	8004658 <UartRxTask+0x250>
                        spFrameData.frameHeader.respStatus = (SerialProtocolRespStatus)(uartTaskData->frameData[FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH]);
 8004642:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004646:	691b      	ldr	r3, [r3, #16]
 8004648:	3305      	adds	r3, #5
 800464a:	781b      	ldrb	r3, [r3, #0]
 800464c:	b25a      	sxtb	r2, r3
 800464e:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8004652:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8004656:	70da      	strb	r2, [r3, #3]
                    }
                    if (frameBytesCount >= FRAME_HEADER_LENGTH) {
 8004658:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 800465c:	2b07      	cmp	r3, #7
 800465e:	d920      	bls.n	80046a2 <UartRxTask+0x29a>
                        spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH]));
 8004660:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004664:	691b      	ldr	r3, [r3, #16]
 8004666:	3306      	adds	r3, #6
 8004668:	781b      	ldrb	r3, [r3, #0]
 800466a:	021b      	lsls	r3, r3, #8
 800466c:	b21a      	sxth	r2, r3
 800466e:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004672:	691b      	ldr	r3, [r3, #16]
 8004674:	3305      	adds	r3, #5
 8004676:	781b      	ldrb	r3, [r3, #0]
 8004678:	b21b      	sxth	r3, r3
 800467a:	4313      	orrs	r3, r2
 800467c:	b21b      	sxth	r3, r3
 800467e:	b29a      	uxth	r2, r3
 8004680:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8004684:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8004688:	809a      	strh	r2, [r3, #4]
                        frameTotalLength                        = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH;
 800468a:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 800468e:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8004692:	889b      	ldrh	r3, [r3, #4]
 8004694:	330a      	adds	r3, #10
 8004696:	f8a7 313e 	strh.w	r3, [r7, #318]	@ 0x13e
                        receverState                            = srRecieveData;
 800469a:	2302      	movs	r3, #2
 800469c:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
 80046a0:	e00e      	b.n	80046c0 <UartRxTask+0x2b8>
                    } else {
                        proceed = pdFALSE;
 80046a2:	2300      	movs	r3, #0
 80046a4:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
 80046a8:	e00a      	b.n	80046c0 <UartRxTask+0x2b8>
                    }
                } else {
                    if (frameBytesCount > 0) {
 80046aa:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 80046ae:	2b00      	cmp	r3, #0
 80046b0:	d003      	beq.n	80046ba <UartRxTask+0x2b2>
                        receverState = srFail;
 80046b2:	2304      	movs	r3, #4
 80046b4:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
 80046b8:	e002      	b.n	80046c0 <UartRxTask+0x2b8>
                    } else {
                        proceed = pdFALSE;
 80046ba:	2300      	movs	r3, #0
 80046bc:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
                    }
                }
                osMutexRelease (uartTaskData->rxDataBufferMutex);
 80046c0:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80046c4:	6a1b      	ldr	r3, [r3, #32]
 80046c6:	4618      	mov	r0, r3
 80046c8:	f00f fa80 	bl	8013bcc <osMutexRelease>
                break;
 80046cc:	e165      	b.n	800499a <UartRxTask+0x592>
            case srRecieveData:
                if (frameBytesCount >= frameTotalLength) {
 80046ce:	f8b7 2124 	ldrh.w	r2, [r7, #292]	@ 0x124
 80046d2:	f8b7 313e 	ldrh.w	r3, [r7, #318]	@ 0x13e
 80046d6:	429a      	cmp	r2, r3
 80046d8:	d303      	bcc.n	80046e2 <UartRxTask+0x2da>
                    receverState = srCheckCrc;
 80046da:	2301      	movs	r3, #1
 80046dc:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                } else {
                    proceed = pdFALSE;
                }
                break;
 80046e0:	e15b      	b.n	800499a <UartRxTask+0x592>
                    proceed = pdFALSE;
 80046e2:	2300      	movs	r3, #0
 80046e4:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
                break;
 80046e8:	e157      	b.n	800499a <UartRxTask+0x592>
            case srCheckCrc:
                osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
 80046ea:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80046ee:	6a1b      	ldr	r3, [r3, #32]
 80046f0:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80046f4:	4618      	mov	r0, r3
 80046f6:	f00f fa1e 	bl	8013b36 <osMutexAcquire>
                frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH]));
 80046fa:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80046fe:	691a      	ldr	r2, [r3, #16]
 8004700:	f8b7 313e 	ldrh.w	r3, [r7, #318]	@ 0x13e
 8004704:	3b01      	subs	r3, #1
 8004706:	4413      	add	r3, r2
 8004708:	781b      	ldrb	r3, [r3, #0]
 800470a:	021b      	lsls	r3, r3, #8
 800470c:	b21a      	sxth	r2, r3
 800470e:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004712:	6919      	ldr	r1, [r3, #16]
 8004714:	f8b7 313e 	ldrh.w	r3, [r7, #318]	@ 0x13e
 8004718:	3b02      	subs	r3, #2
 800471a:	440b      	add	r3, r1
 800471c:	781b      	ldrb	r3, [r3, #0]
 800471e:	b21b      	sxth	r3, r3
 8004720:	4313      	orrs	r3, r2
 8004722:	b21b      	sxth	r3, r3
 8004724:	f8a7 3122 	strh.w	r3, [r7, #290]	@ 0x122
                crc      = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH);
 8004728:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800472c:	6919      	ldr	r1, [r3, #16]
 800472e:	f8b7 313e 	ldrh.w	r3, [r7, #318]	@ 0x13e
 8004732:	3b02      	subs	r3, #2
 8004734:	461a      	mov	r2, r3
 8004736:	4841      	ldr	r0, [pc, #260]	@ (800483c <UartRxTask+0x434>)
 8004738:	f002 fe2a 	bl	8007390 <HAL_CRC_Calculate>
 800473c:	f8c7 0128 	str.w	r0, [r7, #296]	@ 0x128
                osMutexRelease (uartTaskData->rxDataBufferMutex);
 8004740:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004744:	6a1b      	ldr	r3, [r3, #32]
 8004746:	4618      	mov	r0, r3
 8004748:	f00f fa40 	bl	8013bcc <osMutexRelease>
                crcPass = frameCrc == crc;
 800474c:	f8b7 3122 	ldrh.w	r3, [r7, #290]	@ 0x122
 8004750:	f8d7 2128 	ldr.w	r2, [r7, #296]	@ 0x128
 8004754:	429a      	cmp	r2, r3
 8004756:	bf0c      	ite	eq
 8004758:	2301      	moveq	r3, #1
 800475a:	2300      	movne	r3, #0
 800475c:	b2db      	uxtb	r3, r3
 800475e:	f8c7 3138 	str.w	r3, [r7, #312]	@ 0x138
                if (crcPass) {
 8004762:	f8d7 3138 	ldr.w	r3, [r7, #312]	@ 0x138
 8004766:	2b00      	cmp	r3, #0
 8004768:	d00b      	beq.n	8004782 <UartRxTask+0x37a>
                    printf ("Uart%d: Frame CRC PASS\n", uartTaskData->uartNumber);
 800476a:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800476e:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8004772:	4619      	mov	r1, r3
 8004774:	4832      	ldr	r0, [pc, #200]	@ (8004840 <UartRxTask+0x438>)
 8004776:	f013 f9c9 	bl	8017b0c <iprintf>
                    receverState = srExecuteCmd;
 800477a:	2303      	movs	r3, #3
 800477c:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                } else {
                    receverState = srFail;
                }
                break;
 8004780:	e10b      	b.n	800499a <UartRxTask+0x592>
                    receverState = srFail;
 8004782:	2304      	movs	r3, #4
 8004784:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                break;
 8004788:	e107      	b.n	800499a <UartRxTask+0x592>
            case srExecuteCmd:
                if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) {
 800478a:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800478e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8004790:	2b00      	cmp	r3, #0
 8004792:	d104      	bne.n	800479e <UartRxTask+0x396>
 8004794:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004798:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800479a:	2b00      	cmp	r3, #0
 800479c:	d01e      	beq.n	80047dc <UartRxTask+0x3d4>
                    osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
 800479e:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80047a2:	6a1b      	ldr	r3, [r3, #32]
 80047a4:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80047a8:	4618      	mov	r0, r3
 80047aa:	f00f f9c4 	bl	8013b36 <osMutexAcquire>
                    memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength);
 80047ae:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80047b2:	691b      	ldr	r3, [r3, #16]
 80047b4:	f103 0108 	add.w	r1, r3, #8
 80047b8:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 80047bc:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 80047c0:	889b      	ldrh	r3, [r3, #4]
 80047c2:	461a      	mov	r2, r3
 80047c4:	f107 0310 	add.w	r3, r7, #16
 80047c8:	330c      	adds	r3, #12
 80047ca:	4618      	mov	r0, r3
 80047cc:	f013 fac5 	bl	8017d5a <memcpy>
                    osMutexRelease (uartTaskData->rxDataBufferMutex);
 80047d0:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80047d4:	6a1b      	ldr	r3, [r3, #32]
 80047d6:	4618      	mov	r0, r3
 80047d8:	f00f f9f8 	bl	8013bcc <osMutexRelease>
                }

                if (uartTaskData->processRxDataMsgBuffer != NULL) {
 80047dc:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80047e0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80047e2:	2b00      	cmp	r3, #0
 80047e4:	d015      	beq.n	8004812 <UartRxTask+0x40a>
                    if (xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE) {
 80047e6:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80047ea:	6a58      	ldr	r0, [r3, #36]	@ 0x24
 80047ec:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 80047f0:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 80047f4:	889b      	ldrh	r3, [r3, #4]
 80047f6:	f103 020c 	add.w	r2, r3, #12
 80047fa:	f107 0110 	add.w	r1, r7, #16
 80047fe:	23c8      	movs	r3, #200	@ 0xc8
 8004800:	f010 fc06 	bl	8015010 <xStreamBufferSend>
 8004804:	4603      	mov	r3, r0
 8004806:	2b00      	cmp	r3, #0
 8004808:	d103      	bne.n	8004812 <UartRxTask+0x40a>
                        receverState = srFail;
 800480a:	2304      	movs	r3, #4
 800480c:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                        break;
 8004810:	e0c3      	b.n	800499a <UartRxTask+0x592>
                    }
                }
                if (uartTaskData->processDataCb != NULL) {
 8004812:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004816:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8004818:	2b00      	cmp	r3, #0
 800481a:	d008      	beq.n	800482e <UartRxTask+0x426>
                    uartTaskData->processDataCb (uartTaskData, &spFrameData);
 800481c:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004820:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8004822:	f107 0210 	add.w	r2, r7, #16
 8004826:	4611      	mov	r1, r2
 8004828:	f8d7 012c 	ldr.w	r0, [r7, #300]	@ 0x12c
 800482c:	4798      	blx	r3
                }
                receverState = srFinish;
 800482e:	2305      	movs	r3, #5
 8004830:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                break;
 8004834:	e0b1      	b.n	800499a <UartRxTask+0x592>
 8004836:	bf00      	nop
 8004838:	0801891c 	.word	0x0801891c
 800483c:	24000400 	.word	0x24000400
 8004840:	0801893c 	.word	0x0801893c
            case srFail:
                dataToSend = 0;
 8004844:	2300      	movs	r3, #0
 8004846:	f8a7 313c 	strh.w	r3, [r7, #316]	@ 0x13c
                if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) {
 800484a:	f8d7 311c 	ldr.w	r3, [r7, #284]	@ 0x11c
 800484e:	2b01      	cmp	r3, #1
 8004850:	d124      	bne.n	800489c <UartRxTask+0x494>
 8004852:	f8b7 3124 	ldrh.w	r3, [r7, #292]	@ 0x124
 8004856:	2b02      	cmp	r3, #2
 8004858:	d920      	bls.n	800489c <UartRxTask+0x494>
                    dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0);
 800485a:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800485e:	6898      	ldr	r0, [r3, #8]
 8004860:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8004864:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8004868:	8819      	ldrh	r1, [r3, #0]
 800486a:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 800486e:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 8004872:	789a      	ldrb	r2, [r3, #2]
 8004874:	2300      	movs	r3, #0
 8004876:	9301      	str	r3, [sp, #4]
 8004878:	2300      	movs	r3, #0
 800487a:	9300      	str	r3, [sp, #0]
 800487c:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8004880:	f7fe fcda 	bl	8003238 <PrepareRespFrame>
 8004884:	4603      	mov	r3, r0
 8004886:	f8a7 313c 	strh.w	r3, [r7, #316]	@ 0x13c
                    printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber);
 800488a:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800488e:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8004892:	4619      	mov	r1, r3
 8004894:	4844      	ldr	r0, [pc, #272]	@ (80049a8 <UartRxTask+0x5a0>)
 8004896:	f013 f939 	bl	8017b0c <iprintf>
 800489a:	e03c      	b.n	8004916 <UartRxTask+0x50e>
                } else if (!crcPass) {
 800489c:	f8d7 3138 	ldr.w	r3, [r7, #312]	@ 0x138
 80048a0:	2b00      	cmp	r3, #0
 80048a2:	d120      	bne.n	80048e6 <UartRxTask+0x4de>
                    dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0);
 80048a4:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80048a8:	6898      	ldr	r0, [r3, #8]
 80048aa:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 80048ae:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 80048b2:	8819      	ldrh	r1, [r3, #0]
 80048b4:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 80048b8:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 80048bc:	789a      	ldrb	r2, [r3, #2]
 80048be:	2300      	movs	r3, #0
 80048c0:	9301      	str	r3, [sp, #4]
 80048c2:	2300      	movs	r3, #0
 80048c4:	9300      	str	r3, [sp, #0]
 80048c6:	f06f 0301 	mvn.w	r3, #1
 80048ca:	f7fe fcb5 	bl	8003238 <PrepareRespFrame>
 80048ce:	4603      	mov	r3, r0
 80048d0:	f8a7 313c 	strh.w	r3, [r7, #316]	@ 0x13c
                    printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber);
 80048d4:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80048d8:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 80048dc:	4619      	mov	r1, r3
 80048de:	4833      	ldr	r0, [pc, #204]	@ (80049ac <UartRxTask+0x5a4>)
 80048e0:	f013 f914 	bl	8017b0c <iprintf>
 80048e4:	e017      	b.n	8004916 <UartRxTask+0x50e>
                } else {
                    dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0);
 80048e6:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 80048ea:	6898      	ldr	r0, [r3, #8]
 80048ec:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 80048f0:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 80048f4:	8819      	ldrh	r1, [r3, #0]
 80048f6:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 80048fa:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 80048fe:	789a      	ldrb	r2, [r3, #2]
 8004900:	2300      	movs	r3, #0
 8004902:	9301      	str	r3, [sp, #4]
 8004904:	2300      	movs	r3, #0
 8004906:	9300      	str	r3, [sp, #0]
 8004908:	f06f 0303 	mvn.w	r3, #3
 800490c:	f7fe fc94 	bl	8003238 <PrepareRespFrame>
 8004910:	4603      	mov	r3, r0
 8004912:	f8a7 313c 	strh.w	r3, [r7, #316]	@ 0x13c
                }
                if (dataToSend > 0) {
 8004916:	f8b7 313c 	ldrh.w	r3, [r7, #316]	@ 0x13c
 800491a:	2b00      	cmp	r3, #0
 800491c:	d00a      	beq.n	8004934 <UartRxTask+0x52c>
                    HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend);
 800491e:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004922:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 8004924:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004928:	689b      	ldr	r3, [r3, #8]
 800492a:	f8b7 213c 	ldrh.w	r2, [r7, #316]	@ 0x13c
 800492e:	4619      	mov	r1, r3
 8004930:	f00c f8d4 	bl	8010adc <HAL_UART_Transmit_IT>
                }
                printf ("Uart%d: TX bytes sent: %d\n", dataToSend, uartTaskData->uartNumber);
 8004934:	f8b7 113c 	ldrh.w	r1, [r7, #316]	@ 0x13c
 8004938:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800493c:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8004940:	461a      	mov	r2, r3
 8004942:	481b      	ldr	r0, [pc, #108]	@ (80049b0 <UartRxTask+0x5a8>)
 8004944:	f013 f8e2 	bl	8017b0c <iprintf>
                receverState = srFinish;
 8004948:	2305      	movs	r3, #5
 800494a:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                break;
 800494e:	e024      	b.n	800499a <UartRxTask+0x592>
            case srFinish:
            default:
                osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
 8004950:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004954:	6a1b      	ldr	r3, [r3, #32]
 8004956:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 800495a:	4618      	mov	r0, r3
 800495c:	f00f f8eb 	bl	8013b36 <osMutexAcquire>
                uartTaskData->frameBytesCount = 0;
 8004960:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 8004964:	2200      	movs	r2, #0
 8004966:	82da      	strh	r2, [r3, #22]
                osMutexRelease (uartTaskData->rxDataBufferMutex);
 8004968:	f8d7 312c 	ldr.w	r3, [r7, #300]	@ 0x12c
 800496c:	6a1b      	ldr	r3, [r3, #32]
 800496e:	4618      	mov	r0, r3
 8004970:	f00f f92c 	bl	8013bcc <osMutexRelease>
                spFrameData.frameHeader.frameCommand = spUnknown;
 8004974:	f507 73a0 	add.w	r3, r7, #320	@ 0x140
 8004978:	f5a3 7398 	sub.w	r3, r3, #304	@ 0x130
 800497c:	2210      	movs	r2, #16
 800497e:	709a      	strb	r2, [r3, #2]
                frameTotalLength                     = 0;
 8004980:	2300      	movs	r3, #0
 8004982:	f8a7 313e 	strh.w	r3, [r7, #318]	@ 0x13e
                outputDataBufferPos                  = 0;
 8004986:	4b0b      	ldr	r3, [pc, #44]	@ (80049b4 <UartRxTask+0x5ac>)
 8004988:	2200      	movs	r2, #0
 800498a:	801a      	strh	r2, [r3, #0]
                receverState                         = srWaitForHeader;
 800498c:	2300      	movs	r3, #0
 800498e:	f887 3133 	strb.w	r3, [r7, #307]	@ 0x133
                proceed                              = pdFALSE;
 8004992:	2300      	movs	r3, #0
 8004994:	f8c7 3134 	str.w	r3, [r7, #308]	@ 0x134
                break;
 8004998:	bf00      	nop
        while (proceed) {
 800499a:	f8d7 3134 	ldr.w	r3, [r7, #308]	@ 0x134
 800499e:	2b00      	cmp	r3, #0
 80049a0:	f47f ade0 	bne.w	8004564 <UartRxTask+0x15c>
        frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
 80049a4:	e581      	b.n	80044aa <UartRxTask+0xa2>
 80049a6:	bf00      	nop
 80049a8:	08018954 	.word	0x08018954
 80049ac:	08018978 	.word	0x08018978
 80049b0:	08018990 	.word	0x08018990
 80049b4:	24000ca4 	.word	0x24000ca4

080049b8 <Uart1ReceivedDataProcessCallback>:

void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) {
    Uart1ReceivedDataProcessCallback (arg, spFrameData);
}

void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) {
 80049b8:	b590      	push	{r4, r7, lr}
 80049ba:	b0a3      	sub	sp, #140	@ 0x8c
 80049bc:	af06      	add	r7, sp, #24
 80049be:	6078      	str	r0, [r7, #4]
 80049c0:	6039      	str	r1, [r7, #0]
    UartTaskData* uartTaskData          = (UartTaskData*)arg;
 80049c2:	687b      	ldr	r3, [r7, #4]
 80049c4:	64fb      	str	r3, [r7, #76]	@ 0x4c
    uint16_t dataToSend                 = 0;
 80049c6:	2300      	movs	r3, #0
 80049c8:	f8a7 304a 	strh.w	r3, [r7, #74]	@ 0x4a
    outputDataBufferPos                 = 0;
 80049cc:	4ba4      	ldr	r3, [pc, #656]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 80049ce:	2200      	movs	r2, #0
 80049d0:	801a      	strh	r2, [r3, #0]
    uint16_t inputDataBufferPos         = 0;
 80049d2:	2300      	movs	r3, #0
 80049d4:	86bb      	strh	r3, [r7, #52]	@ 0x34
    SerialProtocolRespStatus respStatus = spUnknownCommand;
 80049d6:	23fd      	movs	r3, #253	@ 0xfd
 80049d8:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
    switch (spFrameData->frameHeader.frameCommand) {
 80049dc:	683b      	ldr	r3, [r7, #0]
 80049de:	789b      	ldrb	r3, [r3, #2]
 80049e0:	2b0f      	cmp	r3, #15
 80049e2:	f200 8479 	bhi.w	80052d8 <Uart1ReceivedDataProcessCallback+0x920>
 80049e6:	a201      	add	r2, pc, #4	@ (adr r2, 80049ec <Uart1ReceivedDataProcessCallback+0x34>)
 80049e8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80049ec:	08004a2d 	.word	0x08004a2d
 80049f0:	08004b1b 	.word	0x08004b1b
 80049f4:	08004cc5 	.word	0x08004cc5
 80049f8:	08004d81 	.word	0x08004d81
 80049fc:	08004e23 	.word	0x08004e23
 8004a00:	08004f41 	.word	0x08004f41
 8004a04:	08004fc9 	.word	0x08004fc9
 8004a08:	08004ec5 	.word	0x08004ec5
 8004a0c:	0800501f 	.word	0x0800501f
 8004a10:	08005091 	.word	0x08005091
 8004a14:	080050dd 	.word	0x080050dd
 8004a18:	08005129 	.word	0x08005129
 8004a1c:	0800518b 	.word	0x0800518b
 8004a20:	080051ef 	.word	0x080051ef
 8004a24:	08005251 	.word	0x08005251
 8004a28:	080052b5 	.word	0x080052b5
    case spGetElectricalMeasurments:
        if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
 8004a2c:	4b8d      	ldr	r3, [pc, #564]	@ (8004c64 <Uart1ReceivedDataProcessCallback+0x2ac>)
 8004a2e:	681b      	ldr	r3, [r3, #0]
 8004a30:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8004a34:	4618      	mov	r0, r3
 8004a36:	f00f f87e 	bl	8013b36 <osMutexAcquire>
 8004a3a:	4603      	mov	r3, r0
 8004a3c:	2b00      	cmp	r3, #0
 8004a3e:	d168      	bne.n	8004b12 <Uart1ReceivedDataProcessCallback+0x15a>
            for (int i = 0; i < 3; i++) {
 8004a40:	2300      	movs	r3, #0
 8004a42:	66bb      	str	r3, [r7, #104]	@ 0x68
 8004a44:	e00b      	b.n	8004a5e <Uart1ReceivedDataProcessCallback+0xa6>
                WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float));
 8004a46:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 8004a48:	009b      	lsls	r3, r3, #2
 8004a4a:	4a87      	ldr	r2, [pc, #540]	@ (8004c68 <Uart1ReceivedDataProcessCallback+0x2b0>)
 8004a4c:	441a      	add	r2, r3
 8004a4e:	2304      	movs	r3, #4
 8004a50:	4983      	ldr	r1, [pc, #524]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004a52:	4886      	ldr	r0, [pc, #536]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004a54:	f7fe fb8c 	bl	8003170 <WriteDataToBuffer>
            for (int i = 0; i < 3; i++) {
 8004a58:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 8004a5a:	3301      	adds	r3, #1
 8004a5c:	66bb      	str	r3, [r7, #104]	@ 0x68
 8004a5e:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 8004a60:	2b02      	cmp	r3, #2
 8004a62:	ddf0      	ble.n	8004a46 <Uart1ReceivedDataProcessCallback+0x8e>
            }
            for (int i = 0; i < 3; i++) {
 8004a64:	2300      	movs	r3, #0
 8004a66:	667b      	str	r3, [r7, #100]	@ 0x64
 8004a68:	e00d      	b.n	8004a86 <Uart1ReceivedDataProcessCallback+0xce>
                WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof (float));
 8004a6a:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 8004a6c:	3302      	adds	r3, #2
 8004a6e:	009b      	lsls	r3, r3, #2
 8004a70:	4a7d      	ldr	r2, [pc, #500]	@ (8004c68 <Uart1ReceivedDataProcessCallback+0x2b0>)
 8004a72:	4413      	add	r3, r2
 8004a74:	1d1a      	adds	r2, r3, #4
 8004a76:	2304      	movs	r3, #4
 8004a78:	4979      	ldr	r1, [pc, #484]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004a7a:	487c      	ldr	r0, [pc, #496]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004a7c:	f7fe fb78 	bl	8003170 <WriteDataToBuffer>
            for (int i = 0; i < 3; i++) {
 8004a80:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 8004a82:	3301      	adds	r3, #1
 8004a84:	667b      	str	r3, [r7, #100]	@ 0x64
 8004a86:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 8004a88:	2b02      	cmp	r3, #2
 8004a8a:	ddee      	ble.n	8004a6a <Uart1ReceivedDataProcessCallback+0xb2>
            }
            for (int i = 0; i < 3; i++) {
 8004a8c:	2300      	movs	r3, #0
 8004a8e:	663b      	str	r3, [r7, #96]	@ 0x60
 8004a90:	e00c      	b.n	8004aac <Uart1ReceivedDataProcessCallback+0xf4>
                WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof (float));
 8004a92:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 8004a94:	3306      	adds	r3, #6
 8004a96:	009b      	lsls	r3, r3, #2
 8004a98:	4a73      	ldr	r2, [pc, #460]	@ (8004c68 <Uart1ReceivedDataProcessCallback+0x2b0>)
 8004a9a:	441a      	add	r2, r3
 8004a9c:	2304      	movs	r3, #4
 8004a9e:	4970      	ldr	r1, [pc, #448]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004aa0:	4872      	ldr	r0, [pc, #456]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004aa2:	f7fe fb65 	bl	8003170 <WriteDataToBuffer>
            for (int i = 0; i < 3; i++) {
 8004aa6:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 8004aa8:	3301      	adds	r3, #1
 8004aaa:	663b      	str	r3, [r7, #96]	@ 0x60
 8004aac:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 8004aae:	2b02      	cmp	r3, #2
 8004ab0:	ddef      	ble.n	8004a92 <Uart1ReceivedDataProcessCallback+0xda>
            }
            for (int i = 0; i < 3; i++) {
 8004ab2:	2300      	movs	r3, #0
 8004ab4:	65fb      	str	r3, [r7, #92]	@ 0x5c
 8004ab6:	e00d      	b.n	8004ad4 <Uart1ReceivedDataProcessCallback+0x11c>
                WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof (float));
 8004ab8:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 8004aba:	3308      	adds	r3, #8
 8004abc:	009b      	lsls	r3, r3, #2
 8004abe:	4a6a      	ldr	r2, [pc, #424]	@ (8004c68 <Uart1ReceivedDataProcessCallback+0x2b0>)
 8004ac0:	4413      	add	r3, r2
 8004ac2:	1d1a      	adds	r2, r3, #4
 8004ac4:	2304      	movs	r3, #4
 8004ac6:	4966      	ldr	r1, [pc, #408]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004ac8:	4868      	ldr	r0, [pc, #416]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004aca:	f7fe fb51 	bl	8003170 <WriteDataToBuffer>
            for (int i = 0; i < 3; i++) {
 8004ace:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 8004ad0:	3301      	adds	r3, #1
 8004ad2:	65fb      	str	r3, [r7, #92]	@ 0x5c
 8004ad4:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 8004ad6:	2b02      	cmp	r3, #2
 8004ad8:	ddee      	ble.n	8004ab8 <Uart1ReceivedDataProcessCallback+0x100>
            }
            for (int i = 0; i < 3; i++) {
 8004ada:	2300      	movs	r3, #0
 8004adc:	65bb      	str	r3, [r7, #88]	@ 0x58
 8004ade:	e00c      	b.n	8004afa <Uart1ReceivedDataProcessCallback+0x142>
                WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof (float));
 8004ae0:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
 8004ae2:	330c      	adds	r3, #12
 8004ae4:	009b      	lsls	r3, r3, #2
 8004ae6:	4a60      	ldr	r2, [pc, #384]	@ (8004c68 <Uart1ReceivedDataProcessCallback+0x2b0>)
 8004ae8:	441a      	add	r2, r3
 8004aea:	2304      	movs	r3, #4
 8004aec:	495c      	ldr	r1, [pc, #368]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004aee:	485f      	ldr	r0, [pc, #380]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004af0:	f7fe fb3e 	bl	8003170 <WriteDataToBuffer>
            for (int i = 0; i < 3; i++) {
 8004af4:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
 8004af6:	3301      	adds	r3, #1
 8004af8:	65bb      	str	r3, [r7, #88]	@ 0x58
 8004afa:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
 8004afc:	2b02      	cmp	r3, #2
 8004afe:	ddef      	ble.n	8004ae0 <Uart1ReceivedDataProcessCallback+0x128>
            }
            osMutexRelease (resMeasurementsMutex);
 8004b00:	4b58      	ldr	r3, [pc, #352]	@ (8004c64 <Uart1ReceivedDataProcessCallback+0x2ac>)
 8004b02:	681b      	ldr	r3, [r3, #0]
 8004b04:	4618      	mov	r0, r3
 8004b06:	f00f f861 	bl	8013bcc <osMutexRelease>
            respStatus = spOK;
 8004b0a:	2300      	movs	r3, #0
 8004b0c:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        } else {
            respStatus = spInternalError;
        }
        break;
 8004b10:	e3e6      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
            respStatus = spInternalError;
 8004b12:	23fc      	movs	r3, #252	@ 0xfc
 8004b14:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 8004b18:	e3e2      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
    case spGetSensorMeasurments:
        if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
 8004b1a:	4b55      	ldr	r3, [pc, #340]	@ (8004c70 <Uart1ReceivedDataProcessCallback+0x2b8>)
 8004b1c:	681b      	ldr	r3, [r3, #0]
 8004b1e:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8004b22:	4618      	mov	r0, r3
 8004b24:	f00f f807 	bl	8013b36 <osMutexAcquire>
 8004b28:	4603      	mov	r3, r0
 8004b2a:	2b00      	cmp	r3, #0
 8004b2c:	f040 8094 	bne.w	8004c58 <Uart1ReceivedDataProcessCallback+0x2a0>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof (float));
 8004b30:	2304      	movs	r3, #4
 8004b32:	4a50      	ldr	r2, [pc, #320]	@ (8004c74 <Uart1ReceivedDataProcessCallback+0x2bc>)
 8004b34:	494a      	ldr	r1, [pc, #296]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004b36:	484d      	ldr	r0, [pc, #308]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004b38:	f7fe fb1a 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof (float));
 8004b3c:	2304      	movs	r3, #4
 8004b3e:	4a4e      	ldr	r2, [pc, #312]	@ (8004c78 <Uart1ReceivedDataProcessCallback+0x2c0>)
 8004b40:	4947      	ldr	r1, [pc, #284]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004b42:	484a      	ldr	r0, [pc, #296]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004b44:	f7fe fb14 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof (float));
 8004b48:	2304      	movs	r3, #4
 8004b4a:	4a4c      	ldr	r2, [pc, #304]	@ (8004c7c <Uart1ReceivedDataProcessCallback+0x2c4>)
 8004b4c:	4944      	ldr	r1, [pc, #272]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004b4e:	4847      	ldr	r0, [pc, #284]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004b50:	f7fe fb0e 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderX, sizeof (float));
 8004b54:	2304      	movs	r3, #4
 8004b56:	4a4a      	ldr	r2, [pc, #296]	@ (8004c80 <Uart1ReceivedDataProcessCallback+0x2c8>)
 8004b58:	4941      	ldr	r1, [pc, #260]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004b5a:	4844      	ldr	r0, [pc, #272]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004b5c:	f7fe fb08 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderY, sizeof (float));
 8004b60:	2304      	movs	r3, #4
 8004b62:	4a48      	ldr	r2, [pc, #288]	@ (8004c84 <Uart1ReceivedDataProcessCallback+0x2cc>)
 8004b64:	493e      	ldr	r1, [pc, #248]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004b66:	4841      	ldr	r0, [pc, #260]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004b68:	f7fe fb02 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof (uint8_t));
 8004b6c:	2301      	movs	r3, #1
 8004b6e:	4a46      	ldr	r2, [pc, #280]	@ (8004c88 <Uart1ReceivedDataProcessCallback+0x2d0>)
 8004b70:	493b      	ldr	r1, [pc, #236]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004b72:	483e      	ldr	r0, [pc, #248]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004b74:	f7fe fafc 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof (uint8_t));
 8004b78:	2301      	movs	r3, #1
 8004b7a:	4a44      	ldr	r2, [pc, #272]	@ (8004c8c <Uart1ReceivedDataProcessCallback+0x2d4>)
 8004b7c:	4938      	ldr	r1, [pc, #224]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004b7e:	483b      	ldr	r0, [pc, #236]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004b80:	f7fe faf6 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof (float));
 8004b84:	2304      	movs	r3, #4
 8004b86:	4a42      	ldr	r2, [pc, #264]	@ (8004c90 <Uart1ReceivedDataProcessCallback+0x2d8>)
 8004b88:	4935      	ldr	r1, [pc, #212]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004b8a:	4838      	ldr	r0, [pc, #224]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004b8c:	f7fe faf0 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof (float));
 8004b90:	2304      	movs	r3, #4
 8004b92:	4a40      	ldr	r2, [pc, #256]	@ (8004c94 <Uart1ReceivedDataProcessCallback+0x2dc>)
 8004b94:	4932      	ldr	r1, [pc, #200]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004b96:	4835      	ldr	r0, [pc, #212]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004b98:	f7fe faea 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof (float));
 8004b9c:	2304      	movs	r3, #4
 8004b9e:	4a3e      	ldr	r2, [pc, #248]	@ (8004c98 <Uart1ReceivedDataProcessCallback+0x2e0>)
 8004ba0:	492f      	ldr	r1, [pc, #188]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004ba2:	4832      	ldr	r0, [pc, #200]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004ba4:	f7fe fae4 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof (float));
 8004ba8:	2304      	movs	r3, #4
 8004baa:	4a3c      	ldr	r2, [pc, #240]	@ (8004c9c <Uart1ReceivedDataProcessCallback+0x2e4>)
 8004bac:	492c      	ldr	r1, [pc, #176]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004bae:	482f      	ldr	r0, [pc, #188]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004bb0:	f7fe fade 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchUp, sizeof (uint8_t));
 8004bb4:	2301      	movs	r3, #1
 8004bb6:	4a3a      	ldr	r2, [pc, #232]	@ (8004ca0 <Uart1ReceivedDataProcessCallback+0x2e8>)
 8004bb8:	4929      	ldr	r1, [pc, #164]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004bba:	482c      	ldr	r0, [pc, #176]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004bbc:	f7fe fad8 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchDown, sizeof (uint8_t));
 8004bc0:	2301      	movs	r3, #1
 8004bc2:	4a38      	ldr	r2, [pc, #224]	@ (8004ca4 <Uart1ReceivedDataProcessCallback+0x2ec>)
 8004bc4:	4926      	ldr	r1, [pc, #152]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004bc6:	4829      	ldr	r0, [pc, #164]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004bc8:	f7fe fad2 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchCenter, sizeof (uint8_t));
 8004bcc:	2301      	movs	r3, #1
 8004bce:	4a36      	ldr	r2, [pc, #216]	@ (8004ca8 <Uart1ReceivedDataProcessCallback+0x2f0>)
 8004bd0:	4923      	ldr	r1, [pc, #140]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004bd2:	4826      	ldr	r0, [pc, #152]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004bd4:	f7fe facc 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchUp, sizeof (uint8_t));
 8004bd8:	2301      	movs	r3, #1
 8004bda:	4a34      	ldr	r2, [pc, #208]	@ (8004cac <Uart1ReceivedDataProcessCallback+0x2f4>)
 8004bdc:	4920      	ldr	r1, [pc, #128]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004bde:	4823      	ldr	r0, [pc, #140]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004be0:	f7fe fac6 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchDown, sizeof (uint8_t));
 8004be4:	2301      	movs	r3, #1
 8004be6:	4a32      	ldr	r2, [pc, #200]	@ (8004cb0 <Uart1ReceivedDataProcessCallback+0x2f8>)
 8004be8:	491d      	ldr	r1, [pc, #116]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004bea:	4820      	ldr	r0, [pc, #128]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004bec:	f7fe fac0 	bl	8003170 <WriteDataToBuffer>
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchCenter, sizeof (uint8_t));
 8004bf0:	2301      	movs	r3, #1
 8004bf2:	4a30      	ldr	r2, [pc, #192]	@ (8004cb4 <Uart1ReceivedDataProcessCallback+0x2fc>)
 8004bf4:	491a      	ldr	r1, [pc, #104]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004bf6:	481d      	ldr	r0, [pc, #116]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004bf8:	f7fe faba 	bl	8003170 <WriteDataToBuffer>
            uint8_t comparatorOutput        = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0;
 8004bfc:	482e      	ldr	r0, [pc, #184]	@ (8004cb8 <Uart1ReceivedDataProcessCallback+0x300>)
 8004bfe:	f002 f9ed 	bl	8006fdc <HAL_COMP_GetOutputLevel>
 8004c02:	4603      	mov	r3, r0
 8004c04:	2b01      	cmp	r3, #1
 8004c06:	bf0c      	ite	eq
 8004c08:	2301      	moveq	r3, #1
 8004c0a:	2300      	movne	r3, #0
 8004c0c:	b2db      	uxtb	r3, r3
 8004c0e:	f887 3037 	strb.w	r3, [r7, #55]	@ 0x37
            sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01;
 8004c12:	f897 3037 	ldrb.w	r3, [r7, #55]	@ 0x37
 8004c16:	005c      	lsls	r4, r3, #1
 8004c18:	2108      	movs	r1, #8
 8004c1a:	4828      	ldr	r0, [pc, #160]	@ (8004cbc <Uart1ReceivedDataProcessCallback+0x304>)
 8004c1c:	f005 ff96 	bl	800ab4c <HAL_GPIO_ReadPin>
 8004c20:	4603      	mov	r3, r0
 8004c22:	4323      	orrs	r3, r4
 8004c24:	f003 0301 	and.w	r3, r3, #1
 8004c28:	2b00      	cmp	r3, #0
 8004c2a:	bf0c      	ite	eq
 8004c2c:	2301      	moveq	r3, #1
 8004c2e:	2300      	movne	r3, #0
 8004c30:	b2db      	uxtb	r3, r3
 8004c32:	461a      	mov	r2, r3
 8004c34:	4b0f      	ldr	r3, [pc, #60]	@ (8004c74 <Uart1ReceivedDataProcessCallback+0x2bc>)
 8004c36:	f883 202e 	strb.w	r2, [r3, #46]	@ 0x2e
            WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t));
 8004c3a:	2301      	movs	r3, #1
 8004c3c:	4a20      	ldr	r2, [pc, #128]	@ (8004cc0 <Uart1ReceivedDataProcessCallback+0x308>)
 8004c3e:	4908      	ldr	r1, [pc, #32]	@ (8004c60 <Uart1ReceivedDataProcessCallback+0x2a8>)
 8004c40:	480a      	ldr	r0, [pc, #40]	@ (8004c6c <Uart1ReceivedDataProcessCallback+0x2b4>)
 8004c42:	f7fe fa95 	bl	8003170 <WriteDataToBuffer>
            osMutexRelease (sensorsInfoMutex);
 8004c46:	4b0a      	ldr	r3, [pc, #40]	@ (8004c70 <Uart1ReceivedDataProcessCallback+0x2b8>)
 8004c48:	681b      	ldr	r3, [r3, #0]
 8004c4a:	4618      	mov	r0, r3
 8004c4c:	f00e ffbe 	bl	8013bcc <osMutexRelease>
            respStatus = spOK;
 8004c50:	2300      	movs	r3, #0
 8004c52:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        } else {
            respStatus = spInternalError;
        }
        break;
 8004c56:	e343      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
            respStatus = spInternalError;
 8004c58:	23fc      	movs	r3, #252	@ 0xfc
 8004c5a:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 8004c5e:	e33f      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
 8004c60:	24000ca4 	.word	0x24000ca4
 8004c64:	240007e4 	.word	0x240007e4
 8004c68:	240007f0 	.word	0x240007f0
 8004c6c:	24000c24 	.word	0x24000c24
 8004c70:	240007e8 	.word	0x240007e8
 8004c74:	2400082c 	.word	0x2400082c
 8004c78:	24000830 	.word	0x24000830
 8004c7c:	24000834 	.word	0x24000834
 8004c80:	24000838 	.word	0x24000838
 8004c84:	2400083c 	.word	0x2400083c
 8004c88:	24000840 	.word	0x24000840
 8004c8c:	24000841 	.word	0x24000841
 8004c90:	24000844 	.word	0x24000844
 8004c94:	24000848 	.word	0x24000848
 8004c98:	2400084c 	.word	0x2400084c
 8004c9c:	24000850 	.word	0x24000850
 8004ca0:	24000854 	.word	0x24000854
 8004ca4:	24000855 	.word	0x24000855
 8004ca8:	24000856 	.word	0x24000856
 8004cac:	24000857 	.word	0x24000857
 8004cb0:	24000858 	.word	0x24000858
 8004cb4:	24000859 	.word	0x24000859
 8004cb8:	240003d4 	.word	0x240003d4
 8004cbc:	58020c00 	.word	0x58020c00
 8004cc0:	2400085a 	.word	0x2400085a
    case spSetFanSpeed:
        osTimerStop (fanTimerHandle);
 8004cc4:	4bb4      	ldr	r3, [pc, #720]	@ (8004f98 <Uart1ReceivedDataProcessCallback+0x5e0>)
 8004cc6:	681b      	ldr	r3, [r3, #0]
 8004cc8:	4618      	mov	r0, r3
 8004cca:	f00e fe77 	bl	80139bc <osTimerStop>
        int32_t fanTimerPeriod = 0;
 8004cce:	2300      	movs	r3, #0
 8004cd0:	633b      	str	r3, [r7, #48]	@ 0x30
        uint32_t pulse         = 0;
 8004cd2:	2300      	movs	r3, #0
 8004cd4:	62fb      	str	r3, [r7, #44]	@ 0x2c
        ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse);
 8004cd6:	683b      	ldr	r3, [r7, #0]
 8004cd8:	330c      	adds	r3, #12
 8004cda:	f107 022c 	add.w	r2, r7, #44	@ 0x2c
 8004cde:	f107 0134 	add.w	r1, r7, #52	@ 0x34
 8004ce2:	4618      	mov	r0, r3
 8004ce4:	f7fe fa75 	bl	80031d2 <ReadWordFromBufer>
        ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&fanTimerPeriod);
 8004ce8:	683b      	ldr	r3, [r7, #0]
 8004cea:	330c      	adds	r3, #12
 8004cec:	f107 0230 	add.w	r2, r7, #48	@ 0x30
 8004cf0:	f107 0134 	add.w	r1, r7, #52	@ 0x34
 8004cf4:	4618      	mov	r0, r3
 8004cf6:	f7fe fa6c 	bl	80031d2 <ReadWordFromBufer>
        fanTimerConfigOC.Pulse = pulse * 10;
 8004cfa:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8004cfc:	4613      	mov	r3, r2
 8004cfe:	009b      	lsls	r3, r3, #2
 8004d00:	4413      	add	r3, r2
 8004d02:	005b      	lsls	r3, r3, #1
 8004d04:	461a      	mov	r2, r3
 8004d06:	4ba5      	ldr	r3, [pc, #660]	@ (8004f9c <Uart1ReceivedDataProcessCallback+0x5e4>)
 8004d08:	605a      	str	r2, [r3, #4]
        if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) {
 8004d0a:	2204      	movs	r2, #4
 8004d0c:	49a3      	ldr	r1, [pc, #652]	@ (8004f9c <Uart1ReceivedDataProcessCallback+0x5e4>)
 8004d0e:	48a4      	ldr	r0, [pc, #656]	@ (8004fa0 <Uart1ReceivedDataProcessCallback+0x5e8>)
 8004d10:	f00a fcca 	bl	800f6a8 <HAL_TIM_PWM_ConfigChannel>
 8004d14:	4603      	mov	r3, r0
 8004d16:	2b00      	cmp	r3, #0
 8004d18:	d001      	beq.n	8004d1e <Uart1ReceivedDataProcessCallback+0x366>
            Error_Handler ();
 8004d1a:	f7fd f88f 	bl	8001e3c <Error_Handler>
        }
        if (fanTimerPeriod > 0) {
 8004d1e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8004d20:	2b00      	cmp	r3, #0
 8004d22:	dd0f      	ble.n	8004d44 <Uart1ReceivedDataProcessCallback+0x38c>
            osTimerStart (fanTimerHandle, fanTimerPeriod * 1000);
 8004d24:	4b9c      	ldr	r3, [pc, #624]	@ (8004f98 <Uart1ReceivedDataProcessCallback+0x5e0>)
 8004d26:	681a      	ldr	r2, [r3, #0]
 8004d28:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8004d2a:	f44f 717a 	mov.w	r1, #1000	@ 0x3e8
 8004d2e:	fb01 f303 	mul.w	r3, r1, r3
 8004d32:	4619      	mov	r1, r3
 8004d34:	4610      	mov	r0, r2
 8004d36:	f00e fe13 	bl	8013960 <osTimerStart>
            HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2);
 8004d3a:	2104      	movs	r1, #4
 8004d3c:	4898      	ldr	r0, [pc, #608]	@ (8004fa0 <Uart1ReceivedDataProcessCallback+0x5e8>)
 8004d3e:	f009 ffb9 	bl	800ecb4 <HAL_TIM_PWM_Start>
 8004d42:	e019      	b.n	8004d78 <Uart1ReceivedDataProcessCallback+0x3c0>
        } else if (fanTimerPeriod == 0) {
 8004d44:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8004d46:	2b00      	cmp	r3, #0
 8004d48:	d109      	bne.n	8004d5e <Uart1ReceivedDataProcessCallback+0x3a6>
            osTimerStop (fanTimerHandle);
 8004d4a:	4b93      	ldr	r3, [pc, #588]	@ (8004f98 <Uart1ReceivedDataProcessCallback+0x5e0>)
 8004d4c:	681b      	ldr	r3, [r3, #0]
 8004d4e:	4618      	mov	r0, r3
 8004d50:	f00e fe34 	bl	80139bc <osTimerStop>
            HAL_TIM_PWM_Stop (&htim1, TIM_CHANNEL_2);
 8004d54:	2104      	movs	r1, #4
 8004d56:	4892      	ldr	r0, [pc, #584]	@ (8004fa0 <Uart1ReceivedDataProcessCallback+0x5e8>)
 8004d58:	f00a f8ba 	bl	800eed0 <HAL_TIM_PWM_Stop>
 8004d5c:	e00c      	b.n	8004d78 <Uart1ReceivedDataProcessCallback+0x3c0>
        } else if (fanTimerPeriod == -1) {
 8004d5e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8004d60:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8004d64:	d108      	bne.n	8004d78 <Uart1ReceivedDataProcessCallback+0x3c0>
            osTimerStop (fanTimerHandle);
 8004d66:	4b8c      	ldr	r3, [pc, #560]	@ (8004f98 <Uart1ReceivedDataProcessCallback+0x5e0>)
 8004d68:	681b      	ldr	r3, [r3, #0]
 8004d6a:	4618      	mov	r0, r3
 8004d6c:	f00e fe26 	bl	80139bc <osTimerStop>
            HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2);
 8004d70:	2104      	movs	r1, #4
 8004d72:	488b      	ldr	r0, [pc, #556]	@ (8004fa0 <Uart1ReceivedDataProcessCallback+0x5e8>)
 8004d74:	f009 ff9e 	bl	800ecb4 <HAL_TIM_PWM_Start>
        }
        respStatus = spOK;
 8004d78:	2300      	movs	r3, #0
 8004d7a:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 8004d7e:	e2af      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
    case spSetMotorXOn:
        int32_t motorXPWMPulse    = 0;
 8004d80:	2300      	movs	r3, #0
 8004d82:	62bb      	str	r3, [r7, #40]	@ 0x28
        int32_t motorXTimerPeriod = 0;
 8004d84:	2300      	movs	r3, #0
 8004d86:	627b      	str	r3, [r7, #36]	@ 0x24
        uint32_t motorXStatus     = 0;
 8004d88:	2300      	movs	r3, #0
 8004d8a:	63bb      	str	r3, [r7, #56]	@ 0x38
        ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse);
 8004d8c:	683b      	ldr	r3, [r7, #0]
 8004d8e:	330c      	adds	r3, #12
 8004d90:	f107 0228 	add.w	r2, r7, #40	@ 0x28
 8004d94:	f107 0134 	add.w	r1, r7, #52	@ 0x34
 8004d98:	4618      	mov	r0, r3
 8004d9a:	f7fe fa1a 	bl	80031d2 <ReadWordFromBufer>
        ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod);
 8004d9e:	683b      	ldr	r3, [r7, #0]
 8004da0:	330c      	adds	r3, #12
 8004da2:	f107 0224 	add.w	r2, r7, #36	@ 0x24
 8004da6:	f107 0134 	add.w	r1, r7, #52	@ 0x34
 8004daa:	4618      	mov	r0, r3
 8004dac:	f7fe fa11 	bl	80031d2 <ReadWordFromBufer>
        if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
 8004db0:	4b7c      	ldr	r3, [pc, #496]	@ (8004fa4 <Uart1ReceivedDataProcessCallback+0x5ec>)
 8004db2:	681b      	ldr	r3, [r3, #0]
 8004db4:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8004db8:	4618      	mov	r0, r3
 8004dba:	f00e febc 	bl	8013b36 <osMutexAcquire>
 8004dbe:	4603      	mov	r3, r0
 8004dc0:	2b00      	cmp	r3, #0
 8004dc2:	d12a      	bne.n	8004e1a <Uart1ReceivedDataProcessCallback+0x462>
            motorXStatus =
            motorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, motorXPWMPulse, motorXTimerPeriod, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown);
 8004dc4:	4b78      	ldr	r3, [pc, #480]	@ (8004fa8 <Uart1ReceivedDataProcessCallback+0x5f0>)
 8004dc6:	681b      	ldr	r3, [r3, #0]
 8004dc8:	6aba      	ldr	r2, [r7, #40]	@ 0x28
 8004dca:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 8004dcc:	4877      	ldr	r0, [pc, #476]	@ (8004fac <Uart1ReceivedDataProcessCallback+0x5f4>)
 8004dce:	f890 0028 	ldrb.w	r0, [r0, #40]	@ 0x28
 8004dd2:	4c76      	ldr	r4, [pc, #472]	@ (8004fac <Uart1ReceivedDataProcessCallback+0x5f4>)
 8004dd4:	f894 4029 	ldrb.w	r4, [r4, #41]	@ 0x29
 8004dd8:	9404      	str	r4, [sp, #16]
 8004dda:	9003      	str	r0, [sp, #12]
 8004ddc:	9102      	str	r1, [sp, #8]
 8004dde:	9201      	str	r2, [sp, #4]
 8004de0:	9300      	str	r3, [sp, #0]
 8004de2:	2304      	movs	r3, #4
 8004de4:	2200      	movs	r2, #0
 8004de6:	4972      	ldr	r1, [pc, #456]	@ (8004fb0 <Uart1ReceivedDataProcessCallback+0x5f8>)
 8004de8:	4872      	ldr	r0, [pc, #456]	@ (8004fb4 <Uart1ReceivedDataProcessCallback+0x5fc>)
 8004dea:	f7fe f81b 	bl	8002e24 <motorControl>
 8004dee:	4603      	mov	r3, r0
            motorXStatus =
 8004df0:	63bb      	str	r3, [r7, #56]	@ 0x38
            sensorsInfo.motorXStatus = motorXStatus;
 8004df2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8004df4:	b2da      	uxtb	r2, r3
 8004df6:	4b6d      	ldr	r3, [pc, #436]	@ (8004fac <Uart1ReceivedDataProcessCallback+0x5f4>)
 8004df8:	751a      	strb	r2, [r3, #20]
            if (motorXStatus == 1) {
 8004dfa:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8004dfc:	2b01      	cmp	r3, #1
 8004dfe:	d103      	bne.n	8004e08 <Uart1ReceivedDataProcessCallback+0x450>
                sensorsInfo.motorXPeakCurrent = 0.0;
 8004e00:	4b6a      	ldr	r3, [pc, #424]	@ (8004fac <Uart1ReceivedDataProcessCallback+0x5f4>)
 8004e02:	f04f 0200 	mov.w	r2, #0
 8004e06:	621a      	str	r2, [r3, #32]
            }
            osMutexRelease (sensorsInfoMutex);
 8004e08:	4b66      	ldr	r3, [pc, #408]	@ (8004fa4 <Uart1ReceivedDataProcessCallback+0x5ec>)
 8004e0a:	681b      	ldr	r3, [r3, #0]
 8004e0c:	4618      	mov	r0, r3
 8004e0e:	f00e fedd 	bl	8013bcc <osMutexRelease>
            respStatus = spOK;
 8004e12:	2300      	movs	r3, #0
 8004e14:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        } else {
            respStatus = spInternalError;
        }
        break;
 8004e18:	e262      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
            respStatus = spInternalError;
 8004e1a:	23fc      	movs	r3, #252	@ 0xfc
 8004e1c:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 8004e20:	e25e      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
    case spSetMotorYOn:
        int32_t motorYPWMPulse    = 0;
 8004e22:	2300      	movs	r3, #0
 8004e24:	623b      	str	r3, [r7, #32]
        int32_t motorYTimerPeriod = 0;
 8004e26:	2300      	movs	r3, #0
 8004e28:	61fb      	str	r3, [r7, #28]
        uint32_t motorYStatus     = 0;
 8004e2a:	2300      	movs	r3, #0
 8004e2c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse);
 8004e2e:	683b      	ldr	r3, [r7, #0]
 8004e30:	330c      	adds	r3, #12
 8004e32:	f107 0220 	add.w	r2, r7, #32
 8004e36:	f107 0134 	add.w	r1, r7, #52	@ 0x34
 8004e3a:	4618      	mov	r0, r3
 8004e3c:	f7fe f9c9 	bl	80031d2 <ReadWordFromBufer>
        ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod);
 8004e40:	683b      	ldr	r3, [r7, #0]
 8004e42:	330c      	adds	r3, #12
 8004e44:	f107 021c 	add.w	r2, r7, #28
 8004e48:	f107 0134 	add.w	r1, r7, #52	@ 0x34
 8004e4c:	4618      	mov	r0, r3
 8004e4e:	f7fe f9c0 	bl	80031d2 <ReadWordFromBufer>
        if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
 8004e52:	4b54      	ldr	r3, [pc, #336]	@ (8004fa4 <Uart1ReceivedDataProcessCallback+0x5ec>)
 8004e54:	681b      	ldr	r3, [r3, #0]
 8004e56:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8004e5a:	4618      	mov	r0, r3
 8004e5c:	f00e fe6b 	bl	8013b36 <osMutexAcquire>
 8004e60:	4603      	mov	r3, r0
 8004e62:	2b00      	cmp	r3, #0
 8004e64:	d12a      	bne.n	8004ebc <Uart1ReceivedDataProcessCallback+0x504>
            motorYStatus =
            motorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, motorYPWMPulse, motorYTimerPeriod, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown);
 8004e66:	4b54      	ldr	r3, [pc, #336]	@ (8004fb8 <Uart1ReceivedDataProcessCallback+0x600>)
 8004e68:	681b      	ldr	r3, [r3, #0]
 8004e6a:	6a3a      	ldr	r2, [r7, #32]
 8004e6c:	69f9      	ldr	r1, [r7, #28]
 8004e6e:	484f      	ldr	r0, [pc, #316]	@ (8004fac <Uart1ReceivedDataProcessCallback+0x5f4>)
 8004e70:	f890 002b 	ldrb.w	r0, [r0, #43]	@ 0x2b
 8004e74:	4c4d      	ldr	r4, [pc, #308]	@ (8004fac <Uart1ReceivedDataProcessCallback+0x5f4>)
 8004e76:	f894 402c 	ldrb.w	r4, [r4, #44]	@ 0x2c
 8004e7a:	9404      	str	r4, [sp, #16]
 8004e7c:	9003      	str	r0, [sp, #12]
 8004e7e:	9102      	str	r1, [sp, #8]
 8004e80:	9201      	str	r2, [sp, #4]
 8004e82:	9300      	str	r3, [sp, #0]
 8004e84:	230c      	movs	r3, #12
 8004e86:	2208      	movs	r2, #8
 8004e88:	4949      	ldr	r1, [pc, #292]	@ (8004fb0 <Uart1ReceivedDataProcessCallback+0x5f8>)
 8004e8a:	484a      	ldr	r0, [pc, #296]	@ (8004fb4 <Uart1ReceivedDataProcessCallback+0x5fc>)
 8004e8c:	f7fd ffca 	bl	8002e24 <motorControl>
 8004e90:	4603      	mov	r3, r0
            motorYStatus =
 8004e92:	63fb      	str	r3, [r7, #60]	@ 0x3c
            sensorsInfo.motorYStatus = motorYStatus;
 8004e94:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8004e96:	b2da      	uxtb	r2, r3
 8004e98:	4b44      	ldr	r3, [pc, #272]	@ (8004fac <Uart1ReceivedDataProcessCallback+0x5f4>)
 8004e9a:	755a      	strb	r2, [r3, #21]
            if (motorYStatus == 1) {
 8004e9c:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8004e9e:	2b01      	cmp	r3, #1
 8004ea0:	d103      	bne.n	8004eaa <Uart1ReceivedDataProcessCallback+0x4f2>
                sensorsInfo.motorYPeakCurrent = 0.0;
 8004ea2:	4b42      	ldr	r3, [pc, #264]	@ (8004fac <Uart1ReceivedDataProcessCallback+0x5f4>)
 8004ea4:	f04f 0200 	mov.w	r2, #0
 8004ea8:	625a      	str	r2, [r3, #36]	@ 0x24
            }
            osMutexRelease (sensorsInfoMutex);
 8004eaa:	4b3e      	ldr	r3, [pc, #248]	@ (8004fa4 <Uart1ReceivedDataProcessCallback+0x5ec>)
 8004eac:	681b      	ldr	r3, [r3, #0]
 8004eae:	4618      	mov	r0, r3
 8004eb0:	f00e fe8c 	bl	8013bcc <osMutexRelease>
            respStatus = spOK;
 8004eb4:	2300      	movs	r3, #0
 8004eb6:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        } else {
            respStatus = spInternalError;
        }
        break;
 8004eba:	e211      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
            respStatus = spInternalError;
 8004ebc:	23fc      	movs	r3, #252	@ 0xfc
 8004ebe:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 8004ec2:	e20d      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
    case spSetDiodeOn:
        osTimerStop (debugLedTimerHandle);
 8004ec4:	4b3d      	ldr	r3, [pc, #244]	@ (8004fbc <Uart1ReceivedDataProcessCallback+0x604>)
 8004ec6:	681b      	ldr	r3, [r3, #0]
 8004ec8:	4618      	mov	r0, r3
 8004eca:	f00e fd77 	bl	80139bc <osTimerStop>
        int32_t dbgLedTimerPeriod = 0;
 8004ece:	2300      	movs	r3, #0
 8004ed0:	61bb      	str	r3, [r7, #24]
        ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod);
 8004ed2:	683b      	ldr	r3, [r7, #0]
 8004ed4:	330c      	adds	r3, #12
 8004ed6:	f107 0218 	add.w	r2, r7, #24
 8004eda:	f107 0134 	add.w	r1, r7, #52	@ 0x34
 8004ede:	4618      	mov	r0, r3
 8004ee0:	f7fe f977 	bl	80031d2 <ReadWordFromBufer>
        if (dbgLedTimerPeriod > 0) {
 8004ee4:	69bb      	ldr	r3, [r7, #24]
 8004ee6:	2b00      	cmp	r3, #0
 8004ee8:	dd0e      	ble.n	8004f08 <Uart1ReceivedDataProcessCallback+0x550>
            osTimerStart (debugLedTimerHandle, dbgLedTimerPeriod * 1000);
 8004eea:	4b34      	ldr	r3, [pc, #208]	@ (8004fbc <Uart1ReceivedDataProcessCallback+0x604>)
 8004eec:	681a      	ldr	r2, [r3, #0]
 8004eee:	69bb      	ldr	r3, [r7, #24]
 8004ef0:	f44f 717a 	mov.w	r1, #1000	@ 0x3e8
 8004ef4:	fb01 f303 	mul.w	r3, r1, r3
 8004ef8:	4619      	mov	r1, r3
 8004efa:	4610      	mov	r0, r2
 8004efc:	f00e fd30 	bl	8013960 <osTimerStart>
            DbgLEDOn (DBG_LED1);
 8004f00:	2010      	movs	r0, #16
 8004f02:	f7fd ff01 	bl	8002d08 <DbgLEDOn>
 8004f06:	e017      	b.n	8004f38 <Uart1ReceivedDataProcessCallback+0x580>
        } else if (dbgLedTimerPeriod == 0) {
 8004f08:	69bb      	ldr	r3, [r7, #24]
 8004f0a:	2b00      	cmp	r3, #0
 8004f0c:	d108      	bne.n	8004f20 <Uart1ReceivedDataProcessCallback+0x568>
            osTimerStop (debugLedTimerHandle);
 8004f0e:	4b2b      	ldr	r3, [pc, #172]	@ (8004fbc <Uart1ReceivedDataProcessCallback+0x604>)
 8004f10:	681b      	ldr	r3, [r3, #0]
 8004f12:	4618      	mov	r0, r3
 8004f14:	f00e fd52 	bl	80139bc <osTimerStop>
            DbgLEDOff (DBG_LED1);
 8004f18:	2010      	movs	r0, #16
 8004f1a:	f7fd ff07 	bl	8002d2c <DbgLEDOff>
 8004f1e:	e00b      	b.n	8004f38 <Uart1ReceivedDataProcessCallback+0x580>
        } else if (dbgLedTimerPeriod == -1) {
 8004f20:	69bb      	ldr	r3, [r7, #24]
 8004f22:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8004f26:	d107      	bne.n	8004f38 <Uart1ReceivedDataProcessCallback+0x580>
            osTimerStop (debugLedTimerHandle);
 8004f28:	4b24      	ldr	r3, [pc, #144]	@ (8004fbc <Uart1ReceivedDataProcessCallback+0x604>)
 8004f2a:	681b      	ldr	r3, [r3, #0]
 8004f2c:	4618      	mov	r0, r3
 8004f2e:	f00e fd45 	bl	80139bc <osTimerStop>
            DbgLEDOn (DBG_LED1);
 8004f32:	2010      	movs	r0, #16
 8004f34:	f7fd fee8 	bl	8002d08 <DbgLEDOn>
        }
        respStatus = spOK;
 8004f38:	2300      	movs	r3, #0
 8004f3a:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 8004f3e:	e1cf      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
    case spSetmotorXMaxCurrent:
        float motorXMaxCurrent = 0;
 8004f40:	f04f 0300 	mov.w	r3, #0
 8004f44:	617b      	str	r3, [r7, #20]
        ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent);
 8004f46:	683b      	ldr	r3, [r7, #0]
 8004f48:	330c      	adds	r3, #12
 8004f4a:	f107 0214 	add.w	r2, r7, #20
 8004f4e:	f107 0134 	add.w	r1, r7, #52	@ 0x34
 8004f52:	4618      	mov	r0, r3
 8004f54:	f7fe f93d 	bl	80031d2 <ReadWordFromBufer>
        uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001));
 8004f58:	edd7 7a05 	vldr	s15, [r7, #20]
 8004f5c:	ed9f 7a19 	vldr	s14, [pc, #100]	@ 8004fc4 <Uart1ReceivedDataProcessCallback+0x60c>
 8004f60:	ee67 7a87 	vmul.f32	s15, s15, s14
 8004f64:	eeb7 6ae7 	vcvt.f64.f32	d6, s15
 8004f68:	eeb0 5b08 	vmov.f64	d5, #8	@ 0x40400000  3.0
 8004f6c:	ee86 7b05 	vdiv.f64	d7, d6, d5
 8004f70:	eefc 7bc7 	vcvt.u32.f64	s15, d7
 8004f74:	ee17 3a90 	vmov	r3, s15
 8004f78:	643b      	str	r3, [r7, #64]	@ 0x40
        HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1);
 8004f7a:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 8004f7c:	2200      	movs	r2, #0
 8004f7e:	2100      	movs	r1, #0
 8004f80:	480f      	ldr	r0, [pc, #60]	@ (8004fc0 <Uart1ReceivedDataProcessCallback+0x608>)
 8004f82:	f002 fc76 	bl	8007872 <HAL_DAC_SetValue>
        HAL_DAC_Start (&hdac1, DAC_CHANNEL_1);
 8004f86:	2100      	movs	r1, #0
 8004f88:	480d      	ldr	r0, [pc, #52]	@ (8004fc0 <Uart1ReceivedDataProcessCallback+0x608>)
 8004f8a:	f002 fbc5 	bl	8007718 <HAL_DAC_Start>
        respStatus = spOK;
 8004f8e:	2300      	movs	r3, #0
 8004f90:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 8004f94:	e1a4      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
 8004f96:	bf00      	nop
 8004f98:	240006d8 	.word	0x240006d8
 8004f9c:	24000768 	.word	0x24000768
 8004fa0:	2400044c 	.word	0x2400044c
 8004fa4:	240007e8 	.word	0x240007e8
 8004fa8:	24000708 	.word	0x24000708
 8004fac:	2400082c 	.word	0x2400082c
 8004fb0:	24000784 	.word	0x24000784
 8004fb4:	240004e4 	.word	0x240004e4
 8004fb8:	24000738 	.word	0x24000738
 8004fbc:	240006a8 	.word	0x240006a8
 8004fc0:	24000424 	.word	0x24000424
 8004fc4:	457ff000 	.word	0x457ff000
    case spSetmotorYMaxCurrent:
        float motorYMaxCurrent = 0;
 8004fc8:	f04f 0300 	mov.w	r3, #0
 8004fcc:	613b      	str	r3, [r7, #16]
        ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent);
 8004fce:	683b      	ldr	r3, [r7, #0]
 8004fd0:	330c      	adds	r3, #12
 8004fd2:	f107 0210 	add.w	r2, r7, #16
 8004fd6:	f107 0134 	add.w	r1, r7, #52	@ 0x34
 8004fda:	4618      	mov	r0, r3
 8004fdc:	f7fe f8f9 	bl	80031d2 <ReadWordFromBufer>
        uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001));
 8004fe0:	edd7 7a04 	vldr	s15, [r7, #16]
 8004fe4:	ed1f 7a09 	vldr	s14, [pc, #-36]	@ 8004fc4 <Uart1ReceivedDataProcessCallback+0x60c>
 8004fe8:	ee67 7a87 	vmul.f32	s15, s15, s14
 8004fec:	eeb7 6ae7 	vcvt.f64.f32	d6, s15
 8004ff0:	eeb0 5b08 	vmov.f64	d5, #8	@ 0x40400000  3.0
 8004ff4:	ee86 7b05 	vdiv.f64	d7, d6, d5
 8004ff8:	eefc 7bc7 	vcvt.u32.f64	s15, d7
 8004ffc:	ee17 3a90 	vmov	r3, s15
 8005000:	647b      	str	r3, [r7, #68]	@ 0x44
        HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2);
 8005002:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 8005004:	2200      	movs	r2, #0
 8005006:	2110      	movs	r1, #16
 8005008:	48ac      	ldr	r0, [pc, #688]	@ (80052bc <Uart1ReceivedDataProcessCallback+0x904>)
 800500a:	f002 fc32 	bl	8007872 <HAL_DAC_SetValue>
        HAL_DAC_Start (&hdac1, DAC_CHANNEL_2);
 800500e:	2110      	movs	r1, #16
 8005010:	48aa      	ldr	r0, [pc, #680]	@ (80052bc <Uart1ReceivedDataProcessCallback+0x904>)
 8005012:	f002 fb81 	bl	8007718 <HAL_DAC_Start>
        respStatus = spOK;
 8005016:	2300      	movs	r3, #0
 8005018:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 800501c:	e160      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
    case spClearPeakMeasurments:
        if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
 800501e:	4ba8      	ldr	r3, [pc, #672]	@ (80052c0 <Uart1ReceivedDataProcessCallback+0x908>)
 8005020:	681b      	ldr	r3, [r3, #0]
 8005022:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8005026:	4618      	mov	r0, r3
 8005028:	f00e fd85 	bl	8013b36 <osMutexAcquire>
 800502c:	4603      	mov	r3, r0
 800502e:	2b00      	cmp	r3, #0
 8005030:	d12a      	bne.n	8005088 <Uart1ReceivedDataProcessCallback+0x6d0>
            for (int i = 0; i < 3; i++) {
 8005032:	2300      	movs	r3, #0
 8005034:	657b      	str	r3, [r7, #84]	@ 0x54
 8005036:	e01b      	b.n	8005070 <Uart1ReceivedDataProcessCallback+0x6b8>
                resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i];
 8005038:	4aa2      	ldr	r2, [pc, #648]	@ (80052c4 <Uart1ReceivedDataProcessCallback+0x90c>)
 800503a:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 800503c:	009b      	lsls	r3, r3, #2
 800503e:	4413      	add	r3, r2
 8005040:	681a      	ldr	r2, [r3, #0]
 8005042:	49a0      	ldr	r1, [pc, #640]	@ (80052c4 <Uart1ReceivedDataProcessCallback+0x90c>)
 8005044:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 8005046:	3302      	adds	r3, #2
 8005048:	009b      	lsls	r3, r3, #2
 800504a:	440b      	add	r3, r1
 800504c:	3304      	adds	r3, #4
 800504e:	601a      	str	r2, [r3, #0]
                resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i];
 8005050:	4a9c      	ldr	r2, [pc, #624]	@ (80052c4 <Uart1ReceivedDataProcessCallback+0x90c>)
 8005052:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 8005054:	3306      	adds	r3, #6
 8005056:	009b      	lsls	r3, r3, #2
 8005058:	4413      	add	r3, r2
 800505a:	681a      	ldr	r2, [r3, #0]
 800505c:	4999      	ldr	r1, [pc, #612]	@ (80052c4 <Uart1ReceivedDataProcessCallback+0x90c>)
 800505e:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 8005060:	3308      	adds	r3, #8
 8005062:	009b      	lsls	r3, r3, #2
 8005064:	440b      	add	r3, r1
 8005066:	3304      	adds	r3, #4
 8005068:	601a      	str	r2, [r3, #0]
            for (int i = 0; i < 3; i++) {
 800506a:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 800506c:	3301      	adds	r3, #1
 800506e:	657b      	str	r3, [r7, #84]	@ 0x54
 8005070:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 8005072:	2b02      	cmp	r3, #2
 8005074:	dde0      	ble.n	8005038 <Uart1ReceivedDataProcessCallback+0x680>
            }
            osMutexRelease (resMeasurementsMutex);
 8005076:	4b92      	ldr	r3, [pc, #584]	@ (80052c0 <Uart1ReceivedDataProcessCallback+0x908>)
 8005078:	681b      	ldr	r3, [r3, #0]
 800507a:	4618      	mov	r0, r3
 800507c:	f00e fda6 	bl	8013bcc <osMutexRelease>
            respStatus = spOK;
 8005080:	2300      	movs	r3, #0
 8005082:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        } else {
            respStatus = spInternalError;
        }
        break;
 8005086:	e12b      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
            respStatus = spInternalError;
 8005088:	23fc      	movs	r3, #252	@ 0xfc
 800508a:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 800508e:	e127      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
    case spSetEncoderXValue:
        float enocoderXValue = 0;
 8005090:	f04f 0300 	mov.w	r3, #0
 8005094:	60fb      	str	r3, [r7, #12]
        ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderXValue);
 8005096:	683b      	ldr	r3, [r7, #0]
 8005098:	330c      	adds	r3, #12
 800509a:	f107 020c 	add.w	r2, r7, #12
 800509e:	f107 0134 	add.w	r1, r7, #52	@ 0x34
 80050a2:	4618      	mov	r0, r3
 80050a4:	f7fe f895 	bl	80031d2 <ReadWordFromBufer>
        if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
 80050a8:	4b87      	ldr	r3, [pc, #540]	@ (80052c8 <Uart1ReceivedDataProcessCallback+0x910>)
 80050aa:	681b      	ldr	r3, [r3, #0]
 80050ac:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80050b0:	4618      	mov	r0, r3
 80050b2:	f00e fd40 	bl	8013b36 <osMutexAcquire>
 80050b6:	4603      	mov	r3, r0
 80050b8:	2b00      	cmp	r3, #0
 80050ba:	d10b      	bne.n	80050d4 <Uart1ReceivedDataProcessCallback+0x71c>
            sensorsInfo.pvEncoderX = enocoderXValue;
 80050bc:	68fb      	ldr	r3, [r7, #12]
 80050be:	4a83      	ldr	r2, [pc, #524]	@ (80052cc <Uart1ReceivedDataProcessCallback+0x914>)
 80050c0:	60d3      	str	r3, [r2, #12]
            osMutexRelease (sensorsInfoMutex);
 80050c2:	4b81      	ldr	r3, [pc, #516]	@ (80052c8 <Uart1ReceivedDataProcessCallback+0x910>)
 80050c4:	681b      	ldr	r3, [r3, #0]
 80050c6:	4618      	mov	r0, r3
 80050c8:	f00e fd80 	bl	8013bcc <osMutexRelease>
            respStatus = spOK;
 80050cc:	2300      	movs	r3, #0
 80050ce:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        } else {
            respStatus = spInternalError;
        }
        break;
 80050d2:	e105      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
            respStatus = spInternalError;
 80050d4:	23fc      	movs	r3, #252	@ 0xfc
 80050d6:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 80050da:	e101      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
    case spSetEncoderYValue:
        float enocoderYValue = 0;
 80050dc:	f04f 0300 	mov.w	r3, #0
 80050e0:	60bb      	str	r3, [r7, #8]
        ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderYValue);
 80050e2:	683b      	ldr	r3, [r7, #0]
 80050e4:	330c      	adds	r3, #12
 80050e6:	f107 0208 	add.w	r2, r7, #8
 80050ea:	f107 0134 	add.w	r1, r7, #52	@ 0x34
 80050ee:	4618      	mov	r0, r3
 80050f0:	f7fe f86f 	bl	80031d2 <ReadWordFromBufer>
        if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
 80050f4:	4b74      	ldr	r3, [pc, #464]	@ (80052c8 <Uart1ReceivedDataProcessCallback+0x910>)
 80050f6:	681b      	ldr	r3, [r3, #0]
 80050f8:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80050fc:	4618      	mov	r0, r3
 80050fe:	f00e fd1a 	bl	8013b36 <osMutexAcquire>
 8005102:	4603      	mov	r3, r0
 8005104:	2b00      	cmp	r3, #0
 8005106:	d10b      	bne.n	8005120 <Uart1ReceivedDataProcessCallback+0x768>
            sensorsInfo.pvEncoderY = enocoderYValue;
 8005108:	68bb      	ldr	r3, [r7, #8]
 800510a:	4a70      	ldr	r2, [pc, #448]	@ (80052cc <Uart1ReceivedDataProcessCallback+0x914>)
 800510c:	6113      	str	r3, [r2, #16]
            osMutexRelease (sensorsInfoMutex);
 800510e:	4b6e      	ldr	r3, [pc, #440]	@ (80052c8 <Uart1ReceivedDataProcessCallback+0x910>)
 8005110:	681b      	ldr	r3, [r3, #0]
 8005112:	4618      	mov	r0, r3
 8005114:	f00e fd5a 	bl	8013bcc <osMutexRelease>
            respStatus = spOK;
 8005118:	2300      	movs	r3, #0
 800511a:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        } else {
            respStatus = spInternalError;
        }
        break;
 800511e:	e0df      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
            respStatus = spInternalError;
 8005120:	23fc      	movs	r3, #252	@ 0xfc
 8005122:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 8005126:	e0db      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
    case spSetVoltageMeasGains:
        if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
 8005128:	4b65      	ldr	r3, [pc, #404]	@ (80052c0 <Uart1ReceivedDataProcessCallback+0x908>)
 800512a:	681b      	ldr	r3, [r3, #0]
 800512c:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8005130:	4618      	mov	r0, r3
 8005132:	f00e fd00 	bl	8013b36 <osMutexAcquire>
 8005136:	4603      	mov	r3, r0
 8005138:	2b00      	cmp	r3, #0
 800513a:	d122      	bne.n	8005182 <Uart1ReceivedDataProcessCallback+0x7ca>
            for (uint8_t i = 0; i < 3; i++) {
 800513c:	2300      	movs	r3, #0
 800513e:	f887 3053 	strb.w	r3, [r7, #83]	@ 0x53
 8005142:	e011      	b.n	8005168 <Uart1ReceivedDataProcessCallback+0x7b0>
                ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].gain);
 8005144:	683b      	ldr	r3, [r7, #0]
 8005146:	f103 000c 	add.w	r0, r3, #12
 800514a:	f897 3053 	ldrb.w	r3, [r7, #83]	@ 0x53
 800514e:	00db      	lsls	r3, r3, #3
 8005150:	4a5f      	ldr	r2, [pc, #380]	@ (80052d0 <Uart1ReceivedDataProcessCallback+0x918>)
 8005152:	441a      	add	r2, r3
 8005154:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8005158:	4619      	mov	r1, r3
 800515a:	f7fe f83a 	bl	80031d2 <ReadWordFromBufer>
            for (uint8_t i = 0; i < 3; i++) {
 800515e:	f897 3053 	ldrb.w	r3, [r7, #83]	@ 0x53
 8005162:	3301      	adds	r3, #1
 8005164:	f887 3053 	strb.w	r3, [r7, #83]	@ 0x53
 8005168:	f897 3053 	ldrb.w	r3, [r7, #83]	@ 0x53
 800516c:	2b02      	cmp	r3, #2
 800516e:	d9e9      	bls.n	8005144 <Uart1ReceivedDataProcessCallback+0x78c>
            }
            osMutexRelease (resMeasurementsMutex);
 8005170:	4b53      	ldr	r3, [pc, #332]	@ (80052c0 <Uart1ReceivedDataProcessCallback+0x908>)
 8005172:	681b      	ldr	r3, [r3, #0]
 8005174:	4618      	mov	r0, r3
 8005176:	f00e fd29 	bl	8013bcc <osMutexRelease>
            respStatus = spOK;
 800517a:	2300      	movs	r3, #0
 800517c:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        } else {
            respStatus = spInternalError;
        }
        break;
 8005180:	e0ae      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
            respStatus = spInternalError;
 8005182:	23fc      	movs	r3, #252	@ 0xfc
 8005184:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 8005188:	e0aa      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
    case spSetVoltageMeasOffsets:
        if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
 800518a:	4b4d      	ldr	r3, [pc, #308]	@ (80052c0 <Uart1ReceivedDataProcessCallback+0x908>)
 800518c:	681b      	ldr	r3, [r3, #0]
 800518e:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8005192:	4618      	mov	r0, r3
 8005194:	f00e fccf 	bl	8013b36 <osMutexAcquire>
 8005198:	4603      	mov	r3, r0
 800519a:	2b00      	cmp	r3, #0
 800519c:	d123      	bne.n	80051e6 <Uart1ReceivedDataProcessCallback+0x82e>
            for (uint8_t i = 0; i < 3; i++) {
 800519e:	2300      	movs	r3, #0
 80051a0:	f887 3052 	strb.w	r3, [r7, #82]	@ 0x52
 80051a4:	e012      	b.n	80051cc <Uart1ReceivedDataProcessCallback+0x814>
                ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].offset);
 80051a6:	683b      	ldr	r3, [r7, #0]
 80051a8:	f103 000c 	add.w	r0, r3, #12
 80051ac:	f897 3052 	ldrb.w	r3, [r7, #82]	@ 0x52
 80051b0:	00db      	lsls	r3, r3, #3
 80051b2:	4a47      	ldr	r2, [pc, #284]	@ (80052d0 <Uart1ReceivedDataProcessCallback+0x918>)
 80051b4:	4413      	add	r3, r2
 80051b6:	1d1a      	adds	r2, r3, #4
 80051b8:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 80051bc:	4619      	mov	r1, r3
 80051be:	f7fe f808 	bl	80031d2 <ReadWordFromBufer>
            for (uint8_t i = 0; i < 3; i++) {
 80051c2:	f897 3052 	ldrb.w	r3, [r7, #82]	@ 0x52
 80051c6:	3301      	adds	r3, #1
 80051c8:	f887 3052 	strb.w	r3, [r7, #82]	@ 0x52
 80051cc:	f897 3052 	ldrb.w	r3, [r7, #82]	@ 0x52
 80051d0:	2b02      	cmp	r3, #2
 80051d2:	d9e8      	bls.n	80051a6 <Uart1ReceivedDataProcessCallback+0x7ee>
            }
            osMutexRelease (resMeasurementsMutex);
 80051d4:	4b3a      	ldr	r3, [pc, #232]	@ (80052c0 <Uart1ReceivedDataProcessCallback+0x908>)
 80051d6:	681b      	ldr	r3, [r3, #0]
 80051d8:	4618      	mov	r0, r3
 80051da:	f00e fcf7 	bl	8013bcc <osMutexRelease>
            respStatus = spOK;
 80051de:	2300      	movs	r3, #0
 80051e0:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        } else {
            respStatus = spInternalError;
        }
        break;
 80051e4:	e07c      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
            respStatus = spInternalError;
 80051e6:	23fc      	movs	r3, #252	@ 0xfc
 80051e8:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 80051ec:	e078      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
    case spSetCurrentMeasGains:
        if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
 80051ee:	4b34      	ldr	r3, [pc, #208]	@ (80052c0 <Uart1ReceivedDataProcessCallback+0x908>)
 80051f0:	681b      	ldr	r3, [r3, #0]
 80051f2:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 80051f6:	4618      	mov	r0, r3
 80051f8:	f00e fc9d 	bl	8013b36 <osMutexAcquire>
 80051fc:	4603      	mov	r3, r0
 80051fe:	2b00      	cmp	r3, #0
 8005200:	d122      	bne.n	8005248 <Uart1ReceivedDataProcessCallback+0x890>
            for (uint8_t i = 0; i < 3; i++) {
 8005202:	2300      	movs	r3, #0
 8005204:	f887 3051 	strb.w	r3, [r7, #81]	@ 0x51
 8005208:	e011      	b.n	800522e <Uart1ReceivedDataProcessCallback+0x876>
                ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].gain);
 800520a:	683b      	ldr	r3, [r7, #0]
 800520c:	f103 000c 	add.w	r0, r3, #12
 8005210:	f897 3051 	ldrb.w	r3, [r7, #81]	@ 0x51
 8005214:	00db      	lsls	r3, r3, #3
 8005216:	4a2f      	ldr	r2, [pc, #188]	@ (80052d4 <Uart1ReceivedDataProcessCallback+0x91c>)
 8005218:	441a      	add	r2, r3
 800521a:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 800521e:	4619      	mov	r1, r3
 8005220:	f7fd ffd7 	bl	80031d2 <ReadWordFromBufer>
            for (uint8_t i = 0; i < 3; i++) {
 8005224:	f897 3051 	ldrb.w	r3, [r7, #81]	@ 0x51
 8005228:	3301      	adds	r3, #1
 800522a:	f887 3051 	strb.w	r3, [r7, #81]	@ 0x51
 800522e:	f897 3051 	ldrb.w	r3, [r7, #81]	@ 0x51
 8005232:	2b02      	cmp	r3, #2
 8005234:	d9e9      	bls.n	800520a <Uart1ReceivedDataProcessCallback+0x852>
            }
            osMutexRelease (resMeasurementsMutex);
 8005236:	4b22      	ldr	r3, [pc, #136]	@ (80052c0 <Uart1ReceivedDataProcessCallback+0x908>)
 8005238:	681b      	ldr	r3, [r3, #0]
 800523a:	4618      	mov	r0, r3
 800523c:	f00e fcc6 	bl	8013bcc <osMutexRelease>
            respStatus = spOK;
 8005240:	2300      	movs	r3, #0
 8005242:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        } else {
            respStatus = spInternalError;
        }
        break;
 8005246:	e04b      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
            respStatus = spInternalError;
 8005248:	23fc      	movs	r3, #252	@ 0xfc
 800524a:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 800524e:	e047      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
    case spSetCurrentMeasOffsets:
        if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
 8005250:	4b1b      	ldr	r3, [pc, #108]	@ (80052c0 <Uart1ReceivedDataProcessCallback+0x908>)
 8005252:	681b      	ldr	r3, [r3, #0]
 8005254:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8005258:	4618      	mov	r0, r3
 800525a:	f00e fc6c 	bl	8013b36 <osMutexAcquire>
 800525e:	4603      	mov	r3, r0
 8005260:	2b00      	cmp	r3, #0
 8005262:	d123      	bne.n	80052ac <Uart1ReceivedDataProcessCallback+0x8f4>
            for (uint8_t i = 0; i < 3; i++) {
 8005264:	2300      	movs	r3, #0
 8005266:	f887 3050 	strb.w	r3, [r7, #80]	@ 0x50
 800526a:	e012      	b.n	8005292 <Uart1ReceivedDataProcessCallback+0x8da>
                ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].offset);
 800526c:	683b      	ldr	r3, [r7, #0]
 800526e:	f103 000c 	add.w	r0, r3, #12
 8005272:	f897 3050 	ldrb.w	r3, [r7, #80]	@ 0x50
 8005276:	00db      	lsls	r3, r3, #3
 8005278:	4a16      	ldr	r2, [pc, #88]	@ (80052d4 <Uart1ReceivedDataProcessCallback+0x91c>)
 800527a:	4413      	add	r3, r2
 800527c:	1d1a      	adds	r2, r3, #4
 800527e:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 8005282:	4619      	mov	r1, r3
 8005284:	f7fd ffa5 	bl	80031d2 <ReadWordFromBufer>
            for (uint8_t i = 0; i < 3; i++) {
 8005288:	f897 3050 	ldrb.w	r3, [r7, #80]	@ 0x50
 800528c:	3301      	adds	r3, #1
 800528e:	f887 3050 	strb.w	r3, [r7, #80]	@ 0x50
 8005292:	f897 3050 	ldrb.w	r3, [r7, #80]	@ 0x50
 8005296:	2b02      	cmp	r3, #2
 8005298:	d9e8      	bls.n	800526c <Uart1ReceivedDataProcessCallback+0x8b4>
            }
            osMutexRelease (resMeasurementsMutex);
 800529a:	4b09      	ldr	r3, [pc, #36]	@ (80052c0 <Uart1ReceivedDataProcessCallback+0x908>)
 800529c:	681b      	ldr	r3, [r3, #0]
 800529e:	4618      	mov	r0, r3
 80052a0:	f00e fc94 	bl	8013bcc <osMutexRelease>
            respStatus = spOK;
 80052a4:	2300      	movs	r3, #0
 80052a6:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        } else {
            respStatus = spInternalError;
        }
        break;
 80052aa:	e019      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
            respStatus = spInternalError;
 80052ac:	23fc      	movs	r3, #252	@ 0xfc
 80052ae:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
        break;
 80052b2:	e015      	b.n	80052e0 <Uart1ReceivedDataProcessCallback+0x928>
  __ASM volatile ("cpsid i" : : : "memory");
 80052b4:	b672      	cpsid	i
}
 80052b6:	bf00      	nop
    case spResetSystem:
    	__disable_irq();
    	NVIC_SystemReset();
 80052b8:	f7fe ffb0 	bl	800421c <__NVIC_SystemReset>
 80052bc:	24000424 	.word	0x24000424
 80052c0:	240007e4 	.word	0x240007e4
 80052c4:	240007f0 	.word	0x240007f0
 80052c8:	240007e8 	.word	0x240007e8
 80052cc:	2400082c 	.word	0x2400082c
 80052d0:	24000000 	.word	0x24000000
 80052d4:	24000018 	.word	0x24000018
    	break;
    default: respStatus = spUnknownCommand; break;
 80052d8:	23fd      	movs	r3, #253	@ 0xfd
 80052da:	f887 306f 	strb.w	r3, [r7, #111]	@ 0x6f
 80052de:	bf00      	nop
    }
    dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
 80052e0:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 80052e2:	6898      	ldr	r0, [r3, #8]
 80052e4:	683b      	ldr	r3, [r7, #0]
 80052e6:	8819      	ldrh	r1, [r3, #0]
 80052e8:	683b      	ldr	r3, [r7, #0]
 80052ea:	789a      	ldrb	r2, [r3, #2]
 80052ec:	4b13      	ldr	r3, [pc, #76]	@ (800533c <Uart1ReceivedDataProcessCallback+0x984>)
 80052ee:	881b      	ldrh	r3, [r3, #0]
 80052f0:	f997 406f 	ldrsb.w	r4, [r7, #111]	@ 0x6f
 80052f4:	9301      	str	r3, [sp, #4]
 80052f6:	4b12      	ldr	r3, [pc, #72]	@ (8005340 <Uart1ReceivedDataProcessCallback+0x988>)
 80052f8:	9300      	str	r3, [sp, #0]
 80052fa:	4623      	mov	r3, r4
 80052fc:	f7fd ff9c 	bl	8003238 <PrepareRespFrame>
 8005300:	4603      	mov	r3, r0
 8005302:	f8a7 304a 	strh.w	r3, [r7, #74]	@ 0x4a
    if (dataToSend > 0) {
 8005306:	f8b7 304a 	ldrh.w	r3, [r7, #74]	@ 0x4a
 800530a:	2b00      	cmp	r3, #0
 800530c:	d008      	beq.n	8005320 <Uart1ReceivedDataProcessCallback+0x968>
        HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend);
 800530e:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8005310:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 8005312:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8005314:	689b      	ldr	r3, [r3, #8]
 8005316:	f8b7 204a 	ldrh.w	r2, [r7, #74]	@ 0x4a
 800531a:	4619      	mov	r1, r3
 800531c:	f00b fbde 	bl	8010adc <HAL_UART_Transmit_IT>
    }
    printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend);
 8005320:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8005322:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8005326:	4619      	mov	r1, r3
 8005328:	f8b7 304a 	ldrh.w	r3, [r7, #74]	@ 0x4a
 800532c:	461a      	mov	r2, r3
 800532e:	4805      	ldr	r0, [pc, #20]	@ (8005344 <Uart1ReceivedDataProcessCallback+0x98c>)
 8005330:	f012 fbec 	bl	8017b0c <iprintf>
}
 8005334:	bf00      	nop
 8005336:	3774      	adds	r7, #116	@ 0x74
 8005338:	46bd      	mov	sp, r7
 800533a:	bd90      	pop	{r4, r7, pc}
 800533c:	24000ca4 	.word	0x24000ca4
 8005340:	24000c24 	.word	0x24000c24
 8005344:	08018990 	.word	0x08018990

08005348 <Reset_Handler>:

    .section  .text.Reset_Handler
  .weak  Reset_Handler
  .type  Reset_Handler, %function
Reset_Handler:
  ldr   sp, =_estack      /* set stack pointer */
 8005348:	f8df d034 	ldr.w	sp, [pc, #52]	@ 8005380 <LoopFillZerobss+0xe>

/* Call the clock system initialization function.*/
  bl  SystemInit
 800534c:	f7fe fede 	bl	800410c <SystemInit>

/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 8005350:	480c      	ldr	r0, [pc, #48]	@ (8005384 <LoopFillZerobss+0x12>)
  ldr r1, =_edata
 8005352:	490d      	ldr	r1, [pc, #52]	@ (8005388 <LoopFillZerobss+0x16>)
  ldr r2, =_sidata
 8005354:	4a0d      	ldr	r2, [pc, #52]	@ (800538c <LoopFillZerobss+0x1a>)
  movs r3, #0
 8005356:	2300      	movs	r3, #0
  b LoopCopyDataInit
 8005358:	e002      	b.n	8005360 <LoopCopyDataInit>

0800535a <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 800535a:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 800535c:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 800535e:	3304      	adds	r3, #4

08005360 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 8005360:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 8005362:	428c      	cmp	r4, r1
  bcc CopyDataInit
 8005364:	d3f9      	bcc.n	800535a <CopyDataInit>
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 8005366:	4a0a      	ldr	r2, [pc, #40]	@ (8005390 <LoopFillZerobss+0x1e>)
  ldr r4, =_ebss
 8005368:	4c0a      	ldr	r4, [pc, #40]	@ (8005394 <LoopFillZerobss+0x22>)
  movs r3, #0
 800536a:	2300      	movs	r3, #0
  b LoopFillZerobss
 800536c:	e001      	b.n	8005372 <LoopFillZerobss>

0800536e <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 800536e:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 8005370:	3204      	adds	r2, #4

08005372 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 8005372:	42a2      	cmp	r2, r4
  bcc FillZerobss
 8005374:	d3fb      	bcc.n	800536e <FillZerobss>

/* Call static constructors */
    bl __libc_init_array
 8005376:	f012 fcc9 	bl	8017d0c <__libc_init_array>
/* Call the application's entry point.*/
  bl  main
 800537a:	f7fb f9cd 	bl	8000718 <main>
  bx  lr
 800537e:	4770      	bx	lr
  ldr   sp, =_estack      /* set stack pointer */
 8005380:	24060000 	.word	0x24060000
  ldr r0, =_sdata
 8005384:	24000000 	.word	0x24000000
  ldr r1, =_edata
 8005388:	240000a4 	.word	0x240000a4
  ldr r2, =_sidata
 800538c:	08018aac 	.word	0x08018aac
  ldr r2, =_sbss
 8005390:	240000c0 	.word	0x240000c0
  ldr r4, =_ebss
 8005394:	24012de0 	.word	0x24012de0

08005398 <ADC3_IRQHandler>:
 * @retval None
*/
    .section  .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b  Infinite_Loop
 8005398:	e7fe      	b.n	8005398 <ADC3_IRQHandler>
	...

0800539c <HAL_Init>:
  *         need to ensure that the SysTick time base is always set to 1 millisecond
  *         to have correct HAL operation.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 800539c:	b580      	push	{r7, lr}
 800539e:	b082      	sub	sp, #8
 80053a0:	af00      	add	r7, sp, #0
   __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL);  /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
   __HAL_ART_ENABLE();                           /* Enable the Cortex-M4 ART */
#endif /* DUAL_CORE &&  CORE_CM4 */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 80053a2:	2003      	movs	r0, #3
 80053a4:	f001 fee5 	bl	8007172 <HAL_NVIC_SetPriorityGrouping>

  /* Update the SystemCoreClock global variable */
#if defined(RCC_D1CFGR_D1CPRE)
  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
 80053a8:	f006 fb90 	bl	800bacc <HAL_RCC_GetSysClockFreq>
 80053ac:	4602      	mov	r2, r0
 80053ae:	4b15      	ldr	r3, [pc, #84]	@ (8005404 <HAL_Init+0x68>)
 80053b0:	699b      	ldr	r3, [r3, #24]
 80053b2:	0a1b      	lsrs	r3, r3, #8
 80053b4:	f003 030f 	and.w	r3, r3, #15
 80053b8:	4913      	ldr	r1, [pc, #76]	@ (8005408 <HAL_Init+0x6c>)
 80053ba:	5ccb      	ldrb	r3, [r1, r3]
 80053bc:	f003 031f 	and.w	r3, r3, #31
 80053c0:	fa22 f303 	lsr.w	r3, r2, r3
 80053c4:	607b      	str	r3, [r7, #4]
  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif

  /* Update the SystemD2Clock global variable */
#if defined(RCC_D1CFGR_HPRE)
  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 80053c6:	4b0f      	ldr	r3, [pc, #60]	@ (8005404 <HAL_Init+0x68>)
 80053c8:	699b      	ldr	r3, [r3, #24]
 80053ca:	f003 030f 	and.w	r3, r3, #15
 80053ce:	4a0e      	ldr	r2, [pc, #56]	@ (8005408 <HAL_Init+0x6c>)
 80053d0:	5cd3      	ldrb	r3, [r2, r3]
 80053d2:	f003 031f 	and.w	r3, r3, #31
 80053d6:	687a      	ldr	r2, [r7, #4]
 80053d8:	fa22 f303 	lsr.w	r3, r2, r3
 80053dc:	4a0b      	ldr	r2, [pc, #44]	@ (800540c <HAL_Init+0x70>)
 80053de:	6013      	str	r3, [r2, #0]
#endif

#if defined(DUAL_CORE) && defined(CORE_CM4)
  SystemCoreClock = SystemD2Clock;
#else
  SystemCoreClock = common_system_clock;
 80053e0:	4a0b      	ldr	r2, [pc, #44]	@ (8005410 <HAL_Init+0x74>)
 80053e2:	687b      	ldr	r3, [r7, #4]
 80053e4:	6013      	str	r3, [r2, #0]
#endif /* DUAL_CORE && CORE_CM4 */

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 80053e6:	2005      	movs	r0, #5
 80053e8:	f7fe fce4 	bl	8003db4 <HAL_InitTick>
 80053ec:	4603      	mov	r3, r0
 80053ee:	2b00      	cmp	r3, #0
 80053f0:	d001      	beq.n	80053f6 <HAL_Init+0x5a>
  {
    return HAL_ERROR;
 80053f2:	2301      	movs	r3, #1
 80053f4:	e002      	b.n	80053fc <HAL_Init+0x60>
  }

  /* Init the low level hardware */
  HAL_MspInit();
 80053f6:	f7fd ffbd 	bl	8003374 <HAL_MspInit>

  /* Return function status */
  return HAL_OK;
 80053fa:	2300      	movs	r3, #0
}
 80053fc:	4618      	mov	r0, r3
 80053fe:	3708      	adds	r7, #8
 8005400:	46bd      	mov	sp, r7
 8005402:	bd80      	pop	{r7, pc}
 8005404:	58024400 	.word	0x58024400
 8005408:	08018a28 	.word	0x08018a28
 800540c:	24000038 	.word	0x24000038
 8005410:	24000034 	.word	0x24000034

08005414 <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8005414:	b480      	push	{r7}
 8005416:	af00      	add	r7, sp, #0
  uwTick += (uint32_t)uwTickFreq;
 8005418:	4b06      	ldr	r3, [pc, #24]	@ (8005434 <HAL_IncTick+0x20>)
 800541a:	781b      	ldrb	r3, [r3, #0]
 800541c:	461a      	mov	r2, r3
 800541e:	4b06      	ldr	r3, [pc, #24]	@ (8005438 <HAL_IncTick+0x24>)
 8005420:	681b      	ldr	r3, [r3, #0]
 8005422:	4413      	add	r3, r2
 8005424:	4a04      	ldr	r2, [pc, #16]	@ (8005438 <HAL_IncTick+0x24>)
 8005426:	6013      	str	r3, [r2, #0]
}
 8005428:	bf00      	nop
 800542a:	46bd      	mov	sp, r7
 800542c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005430:	4770      	bx	lr
 8005432:	bf00      	nop
 8005434:	24000040 	.word	0x24000040
 8005438:	24000ca8 	.word	0x24000ca8

0800543c <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 800543c:	b480      	push	{r7}
 800543e:	af00      	add	r7, sp, #0
  return uwTick;
 8005440:	4b03      	ldr	r3, [pc, #12]	@ (8005450 <HAL_GetTick+0x14>)
 8005442:	681b      	ldr	r3, [r3, #0]
}
 8005444:	4618      	mov	r0, r3
 8005446:	46bd      	mov	sp, r7
 8005448:	f85d 7b04 	ldr.w	r7, [sp], #4
 800544c:	4770      	bx	lr
 800544e:	bf00      	nop
 8005450:	24000ca8 	.word	0x24000ca8

08005454 <HAL_GetREVID>:
/**
  * @brief  Returns the device revision identifier.
  * @retval Device revision identifier
  */
uint32_t HAL_GetREVID(void)
{
 8005454:	b480      	push	{r7}
 8005456:	af00      	add	r7, sp, #0
   return((DBGMCU->IDCODE) >> 16);
 8005458:	4b03      	ldr	r3, [pc, #12]	@ (8005468 <HAL_GetREVID+0x14>)
 800545a:	681b      	ldr	r3, [r3, #0]
 800545c:	0c1b      	lsrs	r3, r3, #16
}
 800545e:	4618      	mov	r0, r3
 8005460:	46bd      	mov	sp, r7
 8005462:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005466:	4770      	bx	lr
 8005468:	5c001000 	.word	0x5c001000

0800546c <HAL_SYSCFG_VREFBUF_HighImpedanceConfig>:
  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
  * @retval None
  */
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
{
 800546c:	b480      	push	{r7}
 800546e:	b083      	sub	sp, #12
 8005470:	af00      	add	r7, sp, #0
 8005472:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));

  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
 8005474:	4b06      	ldr	r3, [pc, #24]	@ (8005490 <HAL_SYSCFG_VREFBUF_HighImpedanceConfig+0x24>)
 8005476:	681b      	ldr	r3, [r3, #0]
 8005478:	f023 0202 	bic.w	r2, r3, #2
 800547c:	4904      	ldr	r1, [pc, #16]	@ (8005490 <HAL_SYSCFG_VREFBUF_HighImpedanceConfig+0x24>)
 800547e:	687b      	ldr	r3, [r7, #4]
 8005480:	4313      	orrs	r3, r2
 8005482:	600b      	str	r3, [r1, #0]
}
 8005484:	bf00      	nop
 8005486:	370c      	adds	r7, #12
 8005488:	46bd      	mov	sp, r7
 800548a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800548e:	4770      	bx	lr
 8005490:	58003c00 	.word	0x58003c00

08005494 <HAL_SYSCFG_DisableVREFBUF>:
  * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
  *
  * @retval None
  */
void HAL_SYSCFG_DisableVREFBUF(void)
{
 8005494:	b480      	push	{r7}
 8005496:	af00      	add	r7, sp, #0
  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
 8005498:	4b05      	ldr	r3, [pc, #20]	@ (80054b0 <HAL_SYSCFG_DisableVREFBUF+0x1c>)
 800549a:	681b      	ldr	r3, [r3, #0]
 800549c:	4a04      	ldr	r2, [pc, #16]	@ (80054b0 <HAL_SYSCFG_DisableVREFBUF+0x1c>)
 800549e:	f023 0301 	bic.w	r3, r3, #1
 80054a2:	6013      	str	r3, [r2, #0]
}
 80054a4:	bf00      	nop
 80054a6:	46bd      	mov	sp, r7
 80054a8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80054ac:	4770      	bx	lr
 80054ae:	bf00      	nop
 80054b0:	58003c00 	.word	0x58003c00

080054b4 <HAL_SYSCFG_AnalogSwitchConfig>:
  *   @arg SYSCFG_SWITCH_PC3_CLOSE
  * @retval None
  */

void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
{
 80054b4:	b480      	push	{r7}
 80054b6:	b083      	sub	sp, #12
 80054b8:	af00      	add	r7, sp, #0
 80054ba:	6078      	str	r0, [r7, #4]
 80054bc:	6039      	str	r1, [r7, #0]
  /* Check the parameter */
  assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
  assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));

  MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
 80054be:	4b07      	ldr	r3, [pc, #28]	@ (80054dc <HAL_SYSCFG_AnalogSwitchConfig+0x28>)
 80054c0:	685a      	ldr	r2, [r3, #4]
 80054c2:	687b      	ldr	r3, [r7, #4]
 80054c4:	43db      	mvns	r3, r3
 80054c6:	401a      	ands	r2, r3
 80054c8:	4904      	ldr	r1, [pc, #16]	@ (80054dc <HAL_SYSCFG_AnalogSwitchConfig+0x28>)
 80054ca:	683b      	ldr	r3, [r7, #0]
 80054cc:	4313      	orrs	r3, r2
 80054ce:	604b      	str	r3, [r1, #4]
}
 80054d0:	bf00      	nop
 80054d2:	370c      	adds	r7, #12
 80054d4:	46bd      	mov	sp, r7
 80054d6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80054da:	4770      	bx	lr
 80054dc:	58000400 	.word	0x58000400

080054e0 <LL_ADC_SetCommonClock>:
  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
  * @retval None
  */
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
 80054e0:	b480      	push	{r7}
 80054e2:	b083      	sub	sp, #12
 80054e4:	af00      	add	r7, sp, #0
 80054e6:	6078      	str	r0, [r7, #4]
 80054e8:	6039      	str	r1, [r7, #0]
  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
 80054ea:	687b      	ldr	r3, [r7, #4]
 80054ec:	689b      	ldr	r3, [r3, #8]
 80054ee:	f423 127c 	bic.w	r2, r3, #4128768	@ 0x3f0000
 80054f2:	683b      	ldr	r3, [r7, #0]
 80054f4:	431a      	orrs	r2, r3
 80054f6:	687b      	ldr	r3, [r7, #4]
 80054f8:	609a      	str	r2, [r3, #8]
}
 80054fa:	bf00      	nop
 80054fc:	370c      	adds	r7, #12
 80054fe:	46bd      	mov	sp, r7
 8005500:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005504:	4770      	bx	lr

08005506 <LL_ADC_SetCommonPathInternalCh>:
  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
  * @retval None
  */
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
 8005506:	b480      	push	{r7}
 8005508:	b083      	sub	sp, #12
 800550a:	af00      	add	r7, sp, #0
 800550c:	6078      	str	r0, [r7, #4]
 800550e:	6039      	str	r1, [r7, #0]
  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
 8005510:	687b      	ldr	r3, [r7, #4]
 8005512:	689b      	ldr	r3, [r3, #8]
 8005514:	f023 72e0 	bic.w	r2, r3, #29360128	@ 0x1c00000
 8005518:	683b      	ldr	r3, [r7, #0]
 800551a:	431a      	orrs	r2, r3
 800551c:	687b      	ldr	r3, [r7, #4]
 800551e:	609a      	str	r2, [r3, #8]
}
 8005520:	bf00      	nop
 8005522:	370c      	adds	r7, #12
 8005524:	46bd      	mov	sp, r7
 8005526:	f85d 7b04 	ldr.w	r7, [sp], #4
 800552a:	4770      	bx	lr

0800552c <LL_ADC_GetCommonPathInternalCh>:
  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
  */
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
{
 800552c:	b480      	push	{r7}
 800552e:	b083      	sub	sp, #12
 8005530:	af00      	add	r7, sp, #0
 8005532:	6078      	str	r0, [r7, #4]
  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
 8005534:	687b      	ldr	r3, [r7, #4]
 8005536:	689b      	ldr	r3, [r3, #8]
 8005538:	f003 73e0 	and.w	r3, r3, #29360128	@ 0x1c00000
}
 800553c:	4618      	mov	r0, r3
 800553e:	370c      	adds	r7, #12
 8005540:	46bd      	mov	sp, r7
 8005542:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005546:	4770      	bx	lr

08005548 <LL_ADC_SetOffset>:
  *             Other channels are slow channels (conversion rate: refer to reference manual).
  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
  * @retval None
  */
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
 8005548:	b480      	push	{r7}
 800554a:	b087      	sub	sp, #28
 800554c:	af00      	add	r7, sp, #0
 800554e:	60f8      	str	r0, [r7, #12]
 8005550:	60b9      	str	r1, [r7, #8]
 8005552:	607a      	str	r2, [r7, #4]
 8005554:	603b      	str	r3, [r7, #0]
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
 8005556:	68fb      	ldr	r3, [r7, #12]
 8005558:	3360      	adds	r3, #96	@ 0x60
 800555a:	461a      	mov	r2, r3
 800555c:	68bb      	ldr	r3, [r7, #8]
 800555e:	009b      	lsls	r3, r3, #2
 8005560:	4413      	add	r3, r2
 8005562:	617b      	str	r3, [r7, #20]
               ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
  }
  else
#endif /* ADC_VER_V5_V90 */
  {
    MODIFY_REG(*preg,
 8005564:	697b      	ldr	r3, [r7, #20]
 8005566:	681b      	ldr	r3, [r3, #0]
 8005568:	f003 4200 	and.w	r2, r3, #2147483648	@ 0x80000000
 800556c:	687b      	ldr	r3, [r7, #4]
 800556e:	f003 41f8 	and.w	r1, r3, #2080374784	@ 0x7c000000
 8005572:	683b      	ldr	r3, [r7, #0]
 8005574:	430b      	orrs	r3, r1
 8005576:	431a      	orrs	r2, r3
 8005578:	697b      	ldr	r3, [r7, #20]
 800557a:	601a      	str	r2, [r3, #0]
               ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
               (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
  }
}
 800557c:	bf00      	nop
 800557e:	371c      	adds	r7, #28
 8005580:	46bd      	mov	sp, r7
 8005582:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005586:	4770      	bx	lr

08005588 <LL_ADC_SetDataRightShift>:
  *         @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
  *         @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
  * @retval Returned None
  */
__STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
{
 8005588:	b480      	push	{r7}
 800558a:	b085      	sub	sp, #20
 800558c:	af00      	add	r7, sp, #0
 800558e:	60f8      	str	r0, [r7, #12]
 8005590:	60b9      	str	r1, [r7, #8]
 8005592:	607a      	str	r2, [r7, #4]
  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
 8005594:	68fb      	ldr	r3, [r7, #12]
 8005596:	691b      	ldr	r3, [r3, #16]
 8005598:	f423 42f0 	bic.w	r2, r3, #30720	@ 0x7800
 800559c:	68bb      	ldr	r3, [r7, #8]
 800559e:	f003 031f 	and.w	r3, r3, #31
 80055a2:	6879      	ldr	r1, [r7, #4]
 80055a4:	fa01 f303 	lsl.w	r3, r1, r3
 80055a8:	431a      	orrs	r2, r3
 80055aa:	68fb      	ldr	r3, [r7, #12]
 80055ac:	611a      	str	r2, [r3, #16]
}
 80055ae:	bf00      	nop
 80055b0:	3714      	adds	r7, #20
 80055b2:	46bd      	mov	sp, r7
 80055b4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80055b8:	4770      	bx	lr

080055ba <LL_ADC_SetOffsetSignedSaturation>:
  *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
  *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
  * @retval Returned None
  */
__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
{
 80055ba:	b480      	push	{r7}
 80055bc:	b087      	sub	sp, #28
 80055be:	af00      	add	r7, sp, #0
 80055c0:	60f8      	str	r0, [r7, #12]
 80055c2:	60b9      	str	r1, [r7, #8]
 80055c4:	607a      	str	r2, [r7, #4]
    /* Function not available on this instance */
  }
  else
#endif  /* ADC_VER_V5_V90 */
  {
    __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
 80055c6:	68fb      	ldr	r3, [r7, #12]
 80055c8:	3360      	adds	r3, #96	@ 0x60
 80055ca:	461a      	mov	r2, r3
 80055cc:	68bb      	ldr	r3, [r7, #8]
 80055ce:	009b      	lsls	r3, r3, #2
 80055d0:	4413      	add	r3, r2
 80055d2:	617b      	str	r3, [r7, #20]
    MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
 80055d4:	697b      	ldr	r3, [r7, #20]
 80055d6:	681b      	ldr	r3, [r3, #0]
 80055d8:	f023 4200 	bic.w	r2, r3, #2147483648	@ 0x80000000
 80055dc:	687b      	ldr	r3, [r7, #4]
 80055de:	431a      	orrs	r2, r3
 80055e0:	697b      	ldr	r3, [r7, #20]
 80055e2:	601a      	str	r2, [r3, #0]
  }
}
 80055e4:	bf00      	nop
 80055e6:	371c      	adds	r7, #28
 80055e8:	46bd      	mov	sp, r7
 80055ea:	f85d 7b04 	ldr.w	r7, [sp], #4
 80055ee:	4770      	bx	lr

080055f0 <LL_ADC_REG_IsTriggerSourceSWStart>:
  * @param  ADCx ADC instance
  * @retval Value "0" if trigger source external trigger
  *         Value "1" if trigger source SW start.
  */
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
 80055f0:	b480      	push	{r7}
 80055f2:	b083      	sub	sp, #12
 80055f4:	af00      	add	r7, sp, #0
 80055f6:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
 80055f8:	687b      	ldr	r3, [r7, #4]
 80055fa:	68db      	ldr	r3, [r3, #12]
 80055fc:	f403 6340 	and.w	r3, r3, #3072	@ 0xc00
 8005600:	2b00      	cmp	r3, #0
 8005602:	d101      	bne.n	8005608 <LL_ADC_REG_IsTriggerSourceSWStart+0x18>
 8005604:	2301      	movs	r3, #1
 8005606:	e000      	b.n	800560a <LL_ADC_REG_IsTriggerSourceSWStart+0x1a>
 8005608:	2300      	movs	r3, #0
}
 800560a:	4618      	mov	r0, r3
 800560c:	370c      	adds	r7, #12
 800560e:	46bd      	mov	sp, r7
 8005610:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005614:	4770      	bx	lr

08005616 <LL_ADC_REG_SetSequencerRanks>:
  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
  *             Other channels are slow channels (conversion rate: refer to reference manual).
  * @retval None
  */
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
 8005616:	b480      	push	{r7}
 8005618:	b087      	sub	sp, #28
 800561a:	af00      	add	r7, sp, #0
 800561c:	60f8      	str	r0, [r7, #12]
 800561e:	60b9      	str	r1, [r7, #8]
 8005620:	607a      	str	r2, [r7, #4]
  /* Set bits with content of parameter "Channel" with bits position          */
  /* in register and register position depending on parameter "Rank".         */
  /* Parameters "Rank" and "Channel" are used with masks because containing   */
  /* other bits reserved for other purpose.                                   */
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
 8005622:	68fb      	ldr	r3, [r7, #12]
 8005624:	3330      	adds	r3, #48	@ 0x30
 8005626:	461a      	mov	r2, r3
 8005628:	68bb      	ldr	r3, [r7, #8]
 800562a:	0a1b      	lsrs	r3, r3, #8
 800562c:	009b      	lsls	r3, r3, #2
 800562e:	f003 030c 	and.w	r3, r3, #12
 8005632:	4413      	add	r3, r2
 8005634:	617b      	str	r3, [r7, #20]

  MODIFY_REG(*preg,
 8005636:	697b      	ldr	r3, [r7, #20]
 8005638:	681a      	ldr	r2, [r3, #0]
 800563a:	68bb      	ldr	r3, [r7, #8]
 800563c:	f003 031f 	and.w	r3, r3, #31
 8005640:	211f      	movs	r1, #31
 8005642:	fa01 f303 	lsl.w	r3, r1, r3
 8005646:	43db      	mvns	r3, r3
 8005648:	401a      	ands	r2, r3
 800564a:	687b      	ldr	r3, [r7, #4]
 800564c:	0e9b      	lsrs	r3, r3, #26
 800564e:	f003 011f 	and.w	r1, r3, #31
 8005652:	68bb      	ldr	r3, [r7, #8]
 8005654:	f003 031f 	and.w	r3, r3, #31
 8005658:	fa01 f303 	lsl.w	r3, r1, r3
 800565c:	431a      	orrs	r2, r3
 800565e:	697b      	ldr	r3, [r7, #20]
 8005660:	601a      	str	r2, [r3, #0]
             ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
 8005662:	bf00      	nop
 8005664:	371c      	adds	r7, #28
 8005666:	46bd      	mov	sp, r7
 8005668:	f85d 7b04 	ldr.w	r7, [sp], #4
 800566c:	4770      	bx	lr

0800566e <LL_ADC_REG_SetDataTransferMode>:
  * @param  ADCx ADC instance
  * @param  DataTransferMode Select Data Management configuration
  * @retval None
  */
__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
{
 800566e:	b480      	push	{r7}
 8005670:	b083      	sub	sp, #12
 8005672:	af00      	add	r7, sp, #0
 8005674:	6078      	str	r0, [r7, #4]
 8005676:	6039      	str	r1, [r7, #0]
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);
 8005678:	687b      	ldr	r3, [r7, #4]
 800567a:	68db      	ldr	r3, [r3, #12]
 800567c:	f023 0203 	bic.w	r2, r3, #3
 8005680:	683b      	ldr	r3, [r7, #0]
 8005682:	431a      	orrs	r2, r3
 8005684:	687b      	ldr	r3, [r7, #4]
 8005686:	60da      	str	r2, [r3, #12]
}
 8005688:	bf00      	nop
 800568a:	370c      	adds	r7, #12
 800568c:	46bd      	mov	sp, r7
 800568e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005692:	4770      	bx	lr

08005694 <LL_ADC_SetChannelSamplingTime>:
  *         @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
  *         @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
  * @retval None
  */
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
 8005694:	b480      	push	{r7}
 8005696:	b087      	sub	sp, #28
 8005698:	af00      	add	r7, sp, #0
 800569a:	60f8      	str	r0, [r7, #12]
 800569c:	60b9      	str	r1, [r7, #8]
 800569e:	607a      	str	r2, [r7, #4]
  /* Set bits with content of parameter "SamplingTime" with bits position     */
  /* in register and register position depending on parameter "Channel".      */
  /* Parameter "Channel" is used with masks because containing                */
  /* other bits reserved for other purpose.                                   */
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
 80056a0:	68fb      	ldr	r3, [r7, #12]
 80056a2:	3314      	adds	r3, #20
 80056a4:	461a      	mov	r2, r3
 80056a6:	68bb      	ldr	r3, [r7, #8]
 80056a8:	0e5b      	lsrs	r3, r3, #25
 80056aa:	009b      	lsls	r3, r3, #2
 80056ac:	f003 0304 	and.w	r3, r3, #4
 80056b0:	4413      	add	r3, r2
 80056b2:	617b      	str	r3, [r7, #20]

  MODIFY_REG(*preg,
 80056b4:	697b      	ldr	r3, [r7, #20]
 80056b6:	681a      	ldr	r2, [r3, #0]
 80056b8:	68bb      	ldr	r3, [r7, #8]
 80056ba:	0d1b      	lsrs	r3, r3, #20
 80056bc:	f003 031f 	and.w	r3, r3, #31
 80056c0:	2107      	movs	r1, #7
 80056c2:	fa01 f303 	lsl.w	r3, r1, r3
 80056c6:	43db      	mvns	r3, r3
 80056c8:	401a      	ands	r2, r3
 80056ca:	68bb      	ldr	r3, [r7, #8]
 80056cc:	0d1b      	lsrs	r3, r3, #20
 80056ce:	f003 031f 	and.w	r3, r3, #31
 80056d2:	6879      	ldr	r1, [r7, #4]
 80056d4:	fa01 f303 	lsl.w	r3, r1, r3
 80056d8:	431a      	orrs	r2, r3
 80056da:	697b      	ldr	r3, [r7, #20]
 80056dc:	601a      	str	r2, [r3, #0]
             ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
             SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
}
 80056de:	bf00      	nop
 80056e0:	371c      	adds	r7, #28
 80056e2:	46bd      	mov	sp, r7
 80056e4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80056e8:	4770      	bx	lr
	...

080056ec <LL_ADC_SetChannelSingleDiff>:
  *         @arg @ref LL_ADC_SINGLE_ENDED
  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
  * @retval None
  */
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
 80056ec:	b480      	push	{r7}
 80056ee:	b085      	sub	sp, #20
 80056f0:	af00      	add	r7, sp, #0
 80056f2:	60f8      	str	r0, [r7, #12]
 80056f4:	60b9      	str	r1, [r7, #8]
 80056f6:	607a      	str	r2, [r7, #4]
  }
#else  /* ADC_VER_V5_V90 */
  /* Bits of channels in single or differential mode are set only for         */
  /* differential mode (for single mode, mask of bits allowed to be set is    */
  /* shifted out of range of bits of channels in single or differential mode. */
  MODIFY_REG(ADCx->DIFSEL,
 80056f8:	68fb      	ldr	r3, [r7, #12]
 80056fa:	f8d3 20c0 	ldr.w	r2, [r3, #192]	@ 0xc0
 80056fe:	68bb      	ldr	r3, [r7, #8]
 8005700:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8005704:	43db      	mvns	r3, r3
 8005706:	401a      	ands	r2, r3
 8005708:	687b      	ldr	r3, [r7, #4]
 800570a:	f003 0318 	and.w	r3, r3, #24
 800570e:	4908      	ldr	r1, [pc, #32]	@ (8005730 <LL_ADC_SetChannelSingleDiff+0x44>)
 8005710:	40d9      	lsrs	r1, r3
 8005712:	68bb      	ldr	r3, [r7, #8]
 8005714:	400b      	ands	r3, r1
 8005716:	f3c3 0313 	ubfx	r3, r3, #0, #20
 800571a:	431a      	orrs	r2, r3
 800571c:	68fb      	ldr	r3, [r7, #12]
 800571e:	f8c3 20c0 	str.w	r2, [r3, #192]	@ 0xc0
             Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
             (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
#endif /* ADC_VER_V5_V90 */
}
 8005722:	bf00      	nop
 8005724:	3714      	adds	r7, #20
 8005726:	46bd      	mov	sp, r7
 8005728:	f85d 7b04 	ldr.w	r7, [sp], #4
 800572c:	4770      	bx	lr
 800572e:	bf00      	nop
 8005730:	000fffff 	.word	0x000fffff

08005734 <LL_ADC_GetMultimode>:
  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
  */
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
{
 8005734:	b480      	push	{r7}
 8005736:	b083      	sub	sp, #12
 8005738:	af00      	add	r7, sp, #0
 800573a:	6078      	str	r0, [r7, #4]
  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
 800573c:	687b      	ldr	r3, [r7, #4]
 800573e:	689b      	ldr	r3, [r3, #8]
 8005740:	f003 031f 	and.w	r3, r3, #31
}
 8005744:	4618      	mov	r0, r3
 8005746:	370c      	adds	r7, #12
 8005748:	46bd      	mov	sp, r7
 800574a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800574e:	4770      	bx	lr

08005750 <LL_ADC_DisableDeepPowerDown>:
  * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
  * @param  ADCx ADC instance
  * @retval None
  */
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
{
 8005750:	b480      	push	{r7}
 8005752:	b083      	sub	sp, #12
 8005754:	af00      	add	r7, sp, #0
 8005756:	6078      	str	r0, [r7, #4]
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
 8005758:	687b      	ldr	r3, [r7, #4]
 800575a:	689a      	ldr	r2, [r3, #8]
 800575c:	4b04      	ldr	r3, [pc, #16]	@ (8005770 <LL_ADC_DisableDeepPowerDown+0x20>)
 800575e:	4013      	ands	r3, r2
 8005760:	687a      	ldr	r2, [r7, #4]
 8005762:	6093      	str	r3, [r2, #8]
}
 8005764:	bf00      	nop
 8005766:	370c      	adds	r7, #12
 8005768:	46bd      	mov	sp, r7
 800576a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800576e:	4770      	bx	lr
 8005770:	5fffffc0 	.word	0x5fffffc0

08005774 <LL_ADC_IsDeepPowerDownEnabled>:
  * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
  * @param  ADCx ADC instance
  * @retval 0: deep power down is disabled, 1: deep power down is enabled.
  */
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
{
 8005774:	b480      	push	{r7}
 8005776:	b083      	sub	sp, #12
 8005778:	af00      	add	r7, sp, #0
 800577a:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
 800577c:	687b      	ldr	r3, [r7, #4]
 800577e:	689b      	ldr	r3, [r3, #8]
 8005780:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 8005784:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 8005788:	d101      	bne.n	800578e <LL_ADC_IsDeepPowerDownEnabled+0x1a>
 800578a:	2301      	movs	r3, #1
 800578c:	e000      	b.n	8005790 <LL_ADC_IsDeepPowerDownEnabled+0x1c>
 800578e:	2300      	movs	r3, #0
}
 8005790:	4618      	mov	r0, r3
 8005792:	370c      	adds	r7, #12
 8005794:	46bd      	mov	sp, r7
 8005796:	f85d 7b04 	ldr.w	r7, [sp], #4
 800579a:	4770      	bx	lr

0800579c <LL_ADC_EnableInternalRegulator>:
  * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
  * @param  ADCx ADC instance
  * @retval None
  */
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
 800579c:	b480      	push	{r7}
 800579e:	b083      	sub	sp, #12
 80057a0:	af00      	add	r7, sp, #0
 80057a2:	6078      	str	r0, [r7, #4]
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
 80057a4:	687b      	ldr	r3, [r7, #4]
 80057a6:	689a      	ldr	r2, [r3, #8]
 80057a8:	4b05      	ldr	r3, [pc, #20]	@ (80057c0 <LL_ADC_EnableInternalRegulator+0x24>)
 80057aa:	4013      	ands	r3, r2
 80057ac:	f043 5280 	orr.w	r2, r3, #268435456	@ 0x10000000
 80057b0:	687b      	ldr	r3, [r7, #4]
 80057b2:	609a      	str	r2, [r3, #8]
             ADC_CR_BITS_PROPERTY_RS,
             ADC_CR_ADVREGEN);
}
 80057b4:	bf00      	nop
 80057b6:	370c      	adds	r7, #12
 80057b8:	46bd      	mov	sp, r7
 80057ba:	f85d 7b04 	ldr.w	r7, [sp], #4
 80057be:	4770      	bx	lr
 80057c0:	6fffffc0 	.word	0x6fffffc0

080057c4 <LL_ADC_IsInternalRegulatorEnabled>:
  * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
  * @param  ADCx ADC instance
  * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
  */
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
{
 80057c4:	b480      	push	{r7}
 80057c6:	b083      	sub	sp, #12
 80057c8:	af00      	add	r7, sp, #0
 80057ca:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
 80057cc:	687b      	ldr	r3, [r7, #4]
 80057ce:	689b      	ldr	r3, [r3, #8]
 80057d0:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 80057d4:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 80057d8:	d101      	bne.n	80057de <LL_ADC_IsInternalRegulatorEnabled+0x1a>
 80057da:	2301      	movs	r3, #1
 80057dc:	e000      	b.n	80057e0 <LL_ADC_IsInternalRegulatorEnabled+0x1c>
 80057de:	2300      	movs	r3, #0
}
 80057e0:	4618      	mov	r0, r3
 80057e2:	370c      	adds	r7, #12
 80057e4:	46bd      	mov	sp, r7
 80057e6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80057ea:	4770      	bx	lr

080057ec <LL_ADC_Enable>:
  * @rmtoll CR       ADEN           LL_ADC_Enable
  * @param  ADCx ADC instance
  * @retval None
  */
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
{
 80057ec:	b480      	push	{r7}
 80057ee:	b083      	sub	sp, #12
 80057f0:	af00      	add	r7, sp, #0
 80057f2:	6078      	str	r0, [r7, #4]
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
 80057f4:	687b      	ldr	r3, [r7, #4]
 80057f6:	689a      	ldr	r2, [r3, #8]
 80057f8:	4b05      	ldr	r3, [pc, #20]	@ (8005810 <LL_ADC_Enable+0x24>)
 80057fa:	4013      	ands	r3, r2
 80057fc:	f043 0201 	orr.w	r2, r3, #1
 8005800:	687b      	ldr	r3, [r7, #4]
 8005802:	609a      	str	r2, [r3, #8]
             ADC_CR_BITS_PROPERTY_RS,
             ADC_CR_ADEN);
}
 8005804:	bf00      	nop
 8005806:	370c      	adds	r7, #12
 8005808:	46bd      	mov	sp, r7
 800580a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800580e:	4770      	bx	lr
 8005810:	7fffffc0 	.word	0x7fffffc0

08005814 <LL_ADC_Disable>:
  * @rmtoll CR       ADDIS          LL_ADC_Disable
  * @param  ADCx ADC instance
  * @retval None
  */
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
{
 8005814:	b480      	push	{r7}
 8005816:	b083      	sub	sp, #12
 8005818:	af00      	add	r7, sp, #0
 800581a:	6078      	str	r0, [r7, #4]
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
 800581c:	687b      	ldr	r3, [r7, #4]
 800581e:	689a      	ldr	r2, [r3, #8]
 8005820:	4b05      	ldr	r3, [pc, #20]	@ (8005838 <LL_ADC_Disable+0x24>)
 8005822:	4013      	ands	r3, r2
 8005824:	f043 0202 	orr.w	r2, r3, #2
 8005828:	687b      	ldr	r3, [r7, #4]
 800582a:	609a      	str	r2, [r3, #8]
             ADC_CR_BITS_PROPERTY_RS,
             ADC_CR_ADDIS);
}
 800582c:	bf00      	nop
 800582e:	370c      	adds	r7, #12
 8005830:	46bd      	mov	sp, r7
 8005832:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005836:	4770      	bx	lr
 8005838:	7fffffc0 	.word	0x7fffffc0

0800583c <LL_ADC_IsEnabled>:
  * @rmtoll CR       ADEN           LL_ADC_IsEnabled
  * @param  ADCx ADC instance
  * @retval 0: ADC is disabled, 1: ADC is enabled.
  */
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
{
 800583c:	b480      	push	{r7}
 800583e:	b083      	sub	sp, #12
 8005840:	af00      	add	r7, sp, #0
 8005842:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
 8005844:	687b      	ldr	r3, [r7, #4]
 8005846:	689b      	ldr	r3, [r3, #8]
 8005848:	f003 0301 	and.w	r3, r3, #1
 800584c:	2b01      	cmp	r3, #1
 800584e:	d101      	bne.n	8005854 <LL_ADC_IsEnabled+0x18>
 8005850:	2301      	movs	r3, #1
 8005852:	e000      	b.n	8005856 <LL_ADC_IsEnabled+0x1a>
 8005854:	2300      	movs	r3, #0
}
 8005856:	4618      	mov	r0, r3
 8005858:	370c      	adds	r7, #12
 800585a:	46bd      	mov	sp, r7
 800585c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005860:	4770      	bx	lr

08005862 <LL_ADC_IsDisableOngoing>:
  * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
  * @param  ADCx ADC instance
  * @retval 0: no ADC disable command on going.
  */
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
{
 8005862:	b480      	push	{r7}
 8005864:	b083      	sub	sp, #12
 8005866:	af00      	add	r7, sp, #0
 8005868:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
 800586a:	687b      	ldr	r3, [r7, #4]
 800586c:	689b      	ldr	r3, [r3, #8]
 800586e:	f003 0302 	and.w	r3, r3, #2
 8005872:	2b02      	cmp	r3, #2
 8005874:	d101      	bne.n	800587a <LL_ADC_IsDisableOngoing+0x18>
 8005876:	2301      	movs	r3, #1
 8005878:	e000      	b.n	800587c <LL_ADC_IsDisableOngoing+0x1a>
 800587a:	2300      	movs	r3, #0
}
 800587c:	4618      	mov	r0, r3
 800587e:	370c      	adds	r7, #12
 8005880:	46bd      	mov	sp, r7
 8005882:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005886:	4770      	bx	lr

08005888 <LL_ADC_REG_StartConversion>:
  * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
  * @param  ADCx ADC instance
  * @retval None
  */
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
{
 8005888:	b480      	push	{r7}
 800588a:	b083      	sub	sp, #12
 800588c:	af00      	add	r7, sp, #0
 800588e:	6078      	str	r0, [r7, #4]
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
 8005890:	687b      	ldr	r3, [r7, #4]
 8005892:	689a      	ldr	r2, [r3, #8]
 8005894:	4b05      	ldr	r3, [pc, #20]	@ (80058ac <LL_ADC_REG_StartConversion+0x24>)
 8005896:	4013      	ands	r3, r2
 8005898:	f043 0204 	orr.w	r2, r3, #4
 800589c:	687b      	ldr	r3, [r7, #4]
 800589e:	609a      	str	r2, [r3, #8]
             ADC_CR_BITS_PROPERTY_RS,
             ADC_CR_ADSTART);
}
 80058a0:	bf00      	nop
 80058a2:	370c      	adds	r7, #12
 80058a4:	46bd      	mov	sp, r7
 80058a6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80058aa:	4770      	bx	lr
 80058ac:	7fffffc0 	.word	0x7fffffc0

080058b0 <LL_ADC_REG_IsConversionOngoing>:
  * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
  * @param  ADCx ADC instance
  * @retval 0: no conversion is on going on ADC group regular.
  */
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
{
 80058b0:	b480      	push	{r7}
 80058b2:	b083      	sub	sp, #12
 80058b4:	af00      	add	r7, sp, #0
 80058b6:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
 80058b8:	687b      	ldr	r3, [r7, #4]
 80058ba:	689b      	ldr	r3, [r3, #8]
 80058bc:	f003 0304 	and.w	r3, r3, #4
 80058c0:	2b04      	cmp	r3, #4
 80058c2:	d101      	bne.n	80058c8 <LL_ADC_REG_IsConversionOngoing+0x18>
 80058c4:	2301      	movs	r3, #1
 80058c6:	e000      	b.n	80058ca <LL_ADC_REG_IsConversionOngoing+0x1a>
 80058c8:	2300      	movs	r3, #0
}
 80058ca:	4618      	mov	r0, r3
 80058cc:	370c      	adds	r7, #12
 80058ce:	46bd      	mov	sp, r7
 80058d0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80058d4:	4770      	bx	lr

080058d6 <LL_ADC_INJ_IsConversionOngoing>:
  * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
  * @param  ADCx ADC instance
  * @retval 0: no conversion is on going on ADC group injected.
  */
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
{
 80058d6:	b480      	push	{r7}
 80058d8:	b083      	sub	sp, #12
 80058da:	af00      	add	r7, sp, #0
 80058dc:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
 80058de:	687b      	ldr	r3, [r7, #4]
 80058e0:	689b      	ldr	r3, [r3, #8]
 80058e2:	f003 0308 	and.w	r3, r3, #8
 80058e6:	2b08      	cmp	r3, #8
 80058e8:	d101      	bne.n	80058ee <LL_ADC_INJ_IsConversionOngoing+0x18>
 80058ea:	2301      	movs	r3, #1
 80058ec:	e000      	b.n	80058f0 <LL_ADC_INJ_IsConversionOngoing+0x1a>
 80058ee:	2300      	movs	r3, #0
}
 80058f0:	4618      	mov	r0, r3
 80058f2:	370c      	adds	r7, #12
 80058f4:	46bd      	mov	sp, r7
 80058f6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80058fa:	4770      	bx	lr

080058fc <HAL_ADC_Init>:
  *         without  disabling the other ADCs.
  * @param hadc ADC handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
 80058fc:	b590      	push	{r4, r7, lr}
 80058fe:	b089      	sub	sp, #36	@ 0x24
 8005900:	af00      	add	r7, sp, #0
 8005902:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8005904:	2300      	movs	r3, #0
 8005906:	77fb      	strb	r3, [r7, #31]
  uint32_t tmpCFGR;
  uint32_t tmp_adc_reg_is_conversion_on_going;
  __IO uint32_t wait_loop_index = 0UL;
 8005908:	2300      	movs	r3, #0
 800590a:	60bb      	str	r3, [r7, #8]
  uint32_t tmp_adc_is_conversion_on_going_regular;
  uint32_t tmp_adc_is_conversion_on_going_injected;

  /* Check ADC handle */
  if (hadc == NULL)
 800590c:	687b      	ldr	r3, [r7, #4]
 800590e:	2b00      	cmp	r3, #0
 8005910:	d101      	bne.n	8005916 <HAL_ADC_Init+0x1a>
  {
    return HAL_ERROR;
 8005912:	2301      	movs	r3, #1
 8005914:	e18f      	b.n	8005c36 <HAL_ADC_Init+0x33a>
  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
  assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));

  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
 8005916:	687b      	ldr	r3, [r7, #4]
 8005918:	68db      	ldr	r3, [r3, #12]
 800591a:	2b00      	cmp	r3, #0
  /* DISCEN and CONT bits cannot be set at the same time */
  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));

  /* Actions performed only if ADC is coming from state reset:                */
  /* - Initialization of ADC MSP                                              */
  if (hadc->State == HAL_ADC_STATE_RESET)
 800591c:	687b      	ldr	r3, [r7, #4]
 800591e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8005920:	2b00      	cmp	r3, #0
 8005922:	d109      	bne.n	8005938 <HAL_ADC_Init+0x3c>

    /* Init the low level hardware */
    hadc->MspInitCallback(hadc);
#else
    /* Init the low level hardware */
    HAL_ADC_MspInit(hadc);
 8005924:	6878      	ldr	r0, [r7, #4]
 8005926:	f7fd fd81 	bl	800342c <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */

    /* Set ADC error code to none */
    ADC_CLEAR_ERRORCODE(hadc);
 800592a:	687b      	ldr	r3, [r7, #4]
 800592c:	2200      	movs	r2, #0
 800592e:	659a      	str	r2, [r3, #88]	@ 0x58

    /* Initialize Lock */
    hadc->Lock = HAL_UNLOCKED;
 8005930:	687b      	ldr	r3, [r7, #4]
 8005932:	2200      	movs	r2, #0
 8005934:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50
  }

  /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
  if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
 8005938:	687b      	ldr	r3, [r7, #4]
 800593a:	681b      	ldr	r3, [r3, #0]
 800593c:	4618      	mov	r0, r3
 800593e:	f7ff ff19 	bl	8005774 <LL_ADC_IsDeepPowerDownEnabled>
 8005942:	4603      	mov	r3, r0
 8005944:	2b00      	cmp	r3, #0
 8005946:	d004      	beq.n	8005952 <HAL_ADC_Init+0x56>
  {
    /* Disable ADC deep power down mode */
    LL_ADC_DisableDeepPowerDown(hadc->Instance);
 8005948:	687b      	ldr	r3, [r7, #4]
 800594a:	681b      	ldr	r3, [r3, #0]
 800594c:	4618      	mov	r0, r3
 800594e:	f7ff feff 	bl	8005750 <LL_ADC_DisableDeepPowerDown>
    /* System was in deep power down mode, calibration must
     be relaunched or a previously saved calibration factor
     re-applied once the ADC voltage regulator is enabled */
  }

  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
 8005952:	687b      	ldr	r3, [r7, #4]
 8005954:	681b      	ldr	r3, [r3, #0]
 8005956:	4618      	mov	r0, r3
 8005958:	f7ff ff34 	bl	80057c4 <LL_ADC_IsInternalRegulatorEnabled>
 800595c:	4603      	mov	r3, r0
 800595e:	2b00      	cmp	r3, #0
 8005960:	d114      	bne.n	800598c <HAL_ADC_Init+0x90>
  {
    /* Enable ADC internal voltage regulator */
    LL_ADC_EnableInternalRegulator(hadc->Instance);
 8005962:	687b      	ldr	r3, [r7, #4]
 8005964:	681b      	ldr	r3, [r3, #0]
 8005966:	4618      	mov	r0, r3
 8005968:	f7ff ff18 	bl	800579c <LL_ADC_EnableInternalRegulator>

    /* Note: Variable divided by 2 to compensate partially              */
    /*       CPU processing cycles, scaling in us split to not          */
    /*       exceed 32 bits register capacity and handle low frequency. */
    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
 800596c:	4b87      	ldr	r3, [pc, #540]	@ (8005b8c <HAL_ADC_Init+0x290>)
 800596e:	681b      	ldr	r3, [r3, #0]
 8005970:	099b      	lsrs	r3, r3, #6
 8005972:	4a87      	ldr	r2, [pc, #540]	@ (8005b90 <HAL_ADC_Init+0x294>)
 8005974:	fba2 2303 	umull	r2, r3, r2, r3
 8005978:	099b      	lsrs	r3, r3, #6
 800597a:	3301      	adds	r3, #1
 800597c:	60bb      	str	r3, [r7, #8]
    while (wait_loop_index != 0UL)
 800597e:	e002      	b.n	8005986 <HAL_ADC_Init+0x8a>
    {
      wait_loop_index--;
 8005980:	68bb      	ldr	r3, [r7, #8]
 8005982:	3b01      	subs	r3, #1
 8005984:	60bb      	str	r3, [r7, #8]
    while (wait_loop_index != 0UL)
 8005986:	68bb      	ldr	r3, [r7, #8]
 8005988:	2b00      	cmp	r3, #0
 800598a:	d1f9      	bne.n	8005980 <HAL_ADC_Init+0x84>
  }

  /* Verification that ADC voltage regulator is correctly enabled, whether    */
  /* or not ADC is coming from state reset (if any potential problem of       */
  /* clocking, voltage regulator would not be enabled).                       */
  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
 800598c:	687b      	ldr	r3, [r7, #4]
 800598e:	681b      	ldr	r3, [r3, #0]
 8005990:	4618      	mov	r0, r3
 8005992:	f7ff ff17 	bl	80057c4 <LL_ADC_IsInternalRegulatorEnabled>
 8005996:	4603      	mov	r3, r0
 8005998:	2b00      	cmp	r3, #0
 800599a:	d10d      	bne.n	80059b8 <HAL_ADC_Init+0xbc>
  {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 800599c:	687b      	ldr	r3, [r7, #4]
 800599e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80059a0:	f043 0210 	orr.w	r2, r3, #16
 80059a4:	687b      	ldr	r3, [r7, #4]
 80059a6:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Set ADC error code to ADC peripheral internal error */
    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80059a8:	687b      	ldr	r3, [r7, #4]
 80059aa:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80059ac:	f043 0201 	orr.w	r2, r3, #1
 80059b0:	687b      	ldr	r3, [r7, #4]
 80059b2:	659a      	str	r2, [r3, #88]	@ 0x58

    tmp_hal_status = HAL_ERROR;
 80059b4:	2301      	movs	r3, #1
 80059b6:	77fb      	strb	r3, [r7, #31]

  /* Configuration of ADC parameters if previous preliminary actions are      */
  /* correctly completed and if there is no conversion on going on regular    */
  /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
  /* called to update a parameter on the fly).                                */
  tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
 80059b8:	687b      	ldr	r3, [r7, #4]
 80059ba:	681b      	ldr	r3, [r3, #0]
 80059bc:	4618      	mov	r0, r3
 80059be:	f7ff ff77 	bl	80058b0 <LL_ADC_REG_IsConversionOngoing>
 80059c2:	6178      	str	r0, [r7, #20]

  if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
 80059c4:	687b      	ldr	r3, [r7, #4]
 80059c6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80059c8:	f003 0310 	and.w	r3, r3, #16
 80059cc:	2b00      	cmp	r3, #0
 80059ce:	f040 8129 	bne.w	8005c24 <HAL_ADC_Init+0x328>
      && (tmp_adc_reg_is_conversion_on_going == 0UL)
 80059d2:	697b      	ldr	r3, [r7, #20]
 80059d4:	2b00      	cmp	r3, #0
 80059d6:	f040 8125 	bne.w	8005c24 <HAL_ADC_Init+0x328>
     )
  {
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 80059da:	687b      	ldr	r3, [r7, #4]
 80059dc:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80059de:	f423 7381 	bic.w	r3, r3, #258	@ 0x102
 80059e2:	f043 0202 	orr.w	r2, r3, #2
 80059e6:	687b      	ldr	r3, [r7, #4]
 80059e8:	655a      	str	r2, [r3, #84]	@ 0x54
    /* Configuration of common ADC parameters                                 */

    /* Parameters update conditioned to ADC state:                            */
    /* Parameters that can be updated only when ADC is disabled:              */
    /*  - clock configuration                                                 */
    if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
 80059ea:	687b      	ldr	r3, [r7, #4]
 80059ec:	681b      	ldr	r3, [r3, #0]
 80059ee:	4618      	mov	r0, r3
 80059f0:	f7ff ff24 	bl	800583c <LL_ADC_IsEnabled>
 80059f4:	4603      	mov	r3, r0
 80059f6:	2b00      	cmp	r3, #0
 80059f8:	d136      	bne.n	8005a68 <HAL_ADC_Init+0x16c>
    {
      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
 80059fa:	687b      	ldr	r3, [r7, #4]
 80059fc:	681b      	ldr	r3, [r3, #0]
 80059fe:	4a65      	ldr	r2, [pc, #404]	@ (8005b94 <HAL_ADC_Init+0x298>)
 8005a00:	4293      	cmp	r3, r2
 8005a02:	d004      	beq.n	8005a0e <HAL_ADC_Init+0x112>
 8005a04:	687b      	ldr	r3, [r7, #4]
 8005a06:	681b      	ldr	r3, [r3, #0]
 8005a08:	4a63      	ldr	r2, [pc, #396]	@ (8005b98 <HAL_ADC_Init+0x29c>)
 8005a0a:	4293      	cmp	r3, r2
 8005a0c:	d10e      	bne.n	8005a2c <HAL_ADC_Init+0x130>
 8005a0e:	4861      	ldr	r0, [pc, #388]	@ (8005b94 <HAL_ADC_Init+0x298>)
 8005a10:	f7ff ff14 	bl	800583c <LL_ADC_IsEnabled>
 8005a14:	4604      	mov	r4, r0
 8005a16:	4860      	ldr	r0, [pc, #384]	@ (8005b98 <HAL_ADC_Init+0x29c>)
 8005a18:	f7ff ff10 	bl	800583c <LL_ADC_IsEnabled>
 8005a1c:	4603      	mov	r3, r0
 8005a1e:	4323      	orrs	r3, r4
 8005a20:	2b00      	cmp	r3, #0
 8005a22:	bf0c      	ite	eq
 8005a24:	2301      	moveq	r3, #1
 8005a26:	2300      	movne	r3, #0
 8005a28:	b2db      	uxtb	r3, r3
 8005a2a:	e008      	b.n	8005a3e <HAL_ADC_Init+0x142>
 8005a2c:	485b      	ldr	r0, [pc, #364]	@ (8005b9c <HAL_ADC_Init+0x2a0>)
 8005a2e:	f7ff ff05 	bl	800583c <LL_ADC_IsEnabled>
 8005a32:	4603      	mov	r3, r0
 8005a34:	2b00      	cmp	r3, #0
 8005a36:	bf0c      	ite	eq
 8005a38:	2301      	moveq	r3, #1
 8005a3a:	2300      	movne	r3, #0
 8005a3c:	b2db      	uxtb	r3, r3
 8005a3e:	2b00      	cmp	r3, #0
 8005a40:	d012      	beq.n	8005a68 <HAL_ADC_Init+0x16c>
        /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
        /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
        /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
        /*     (set into HAL_ADC_ConfigChannel() or                             */
        /*     HAL_ADCEx_InjectedConfigChannel() )                              */
        LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
 8005a42:	687b      	ldr	r3, [r7, #4]
 8005a44:	681b      	ldr	r3, [r3, #0]
 8005a46:	4a53      	ldr	r2, [pc, #332]	@ (8005b94 <HAL_ADC_Init+0x298>)
 8005a48:	4293      	cmp	r3, r2
 8005a4a:	d004      	beq.n	8005a56 <HAL_ADC_Init+0x15a>
 8005a4c:	687b      	ldr	r3, [r7, #4]
 8005a4e:	681b      	ldr	r3, [r3, #0]
 8005a50:	4a51      	ldr	r2, [pc, #324]	@ (8005b98 <HAL_ADC_Init+0x29c>)
 8005a52:	4293      	cmp	r3, r2
 8005a54:	d101      	bne.n	8005a5a <HAL_ADC_Init+0x15e>
 8005a56:	4a52      	ldr	r2, [pc, #328]	@ (8005ba0 <HAL_ADC_Init+0x2a4>)
 8005a58:	e000      	b.n	8005a5c <HAL_ADC_Init+0x160>
 8005a5a:	4a52      	ldr	r2, [pc, #328]	@ (8005ba4 <HAL_ADC_Init+0x2a8>)
 8005a5c:	687b      	ldr	r3, [r7, #4]
 8005a5e:	685b      	ldr	r3, [r3, #4]
 8005a60:	4619      	mov	r1, r3
 8005a62:	4610      	mov	r0, r2
 8005a64:	f7ff fd3c 	bl	80054e0 <LL_ADC_SetCommonClock>
                  ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
    }

#else

    if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
 8005a68:	f7ff fcf4 	bl	8005454 <HAL_GetREVID>
 8005a6c:	4603      	mov	r3, r0
 8005a6e:	f241 0203 	movw	r2, #4099	@ 0x1003
 8005a72:	4293      	cmp	r3, r2
 8005a74:	d914      	bls.n	8005aa0 <HAL_ADC_Init+0x1a4>
 8005a76:	687b      	ldr	r3, [r7, #4]
 8005a78:	689b      	ldr	r3, [r3, #8]
 8005a7a:	2b10      	cmp	r3, #16
 8005a7c:	d110      	bne.n	8005aa0 <HAL_ADC_Init+0x1a4>
    {
      /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */
      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
 8005a7e:	687b      	ldr	r3, [r7, #4]
 8005a80:	7d5b      	ldrb	r3, [r3, #21]
 8005a82:	035a      	lsls	r2, r3, #13
                  hadc->Init.Overrun                                                    |
 8005a84:	687b      	ldr	r3, [r7, #4]
 8005a86:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
 8005a88:	431a      	orrs	r2, r3
                  hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)                |
 8005a8a:	687b      	ldr	r3, [r7, #4]
 8005a8c:	689b      	ldr	r3, [r3, #8]
                  hadc->Init.Overrun                                                    |
 8005a8e:	431a      	orrs	r2, r3
                  ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
 8005a90:	687b      	ldr	r3, [r7, #4]
 8005a92:	7f1b      	ldrb	r3, [r3, #28]
 8005a94:	041b      	lsls	r3, r3, #16
                  hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)                |
 8005a96:	4313      	orrs	r3, r2
      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
 8005a98:	f043 030c 	orr.w	r3, r3, #12
 8005a9c:	61bb      	str	r3, [r7, #24]
 8005a9e:	e00d      	b.n	8005abc <HAL_ADC_Init+0x1c0>
    }
    else
    {

      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
 8005aa0:	687b      	ldr	r3, [r7, #4]
 8005aa2:	7d5b      	ldrb	r3, [r3, #21]
 8005aa4:	035a      	lsls	r2, r3, #13
                  hadc->Init.Overrun                                                    |
 8005aa6:	687b      	ldr	r3, [r7, #4]
 8005aa8:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
 8005aaa:	431a      	orrs	r2, r3
                  hadc->Init.Resolution                                                 |
 8005aac:	687b      	ldr	r3, [r7, #4]
 8005aae:	689b      	ldr	r3, [r3, #8]
                  hadc->Init.Overrun                                                    |
 8005ab0:	431a      	orrs	r2, r3
                  ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
 8005ab2:	687b      	ldr	r3, [r7, #4]
 8005ab4:	7f1b      	ldrb	r3, [r3, #28]
 8005ab6:	041b      	lsls	r3, r3, #16
      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
 8005ab8:	4313      	orrs	r3, r2
 8005aba:	61bb      	str	r3, [r7, #24]
    }

#endif /* ADC_VER_V5_3 */

    if (hadc->Init.DiscontinuousConvMode == ENABLE)
 8005abc:	687b      	ldr	r3, [r7, #4]
 8005abe:	7f1b      	ldrb	r3, [r3, #28]
 8005ac0:	2b01      	cmp	r3, #1
 8005ac2:	d106      	bne.n	8005ad2 <HAL_ADC_Init+0x1d6>
    {
      tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
 8005ac4:	687b      	ldr	r3, [r7, #4]
 8005ac6:	6a1b      	ldr	r3, [r3, #32]
 8005ac8:	3b01      	subs	r3, #1
 8005aca:	045b      	lsls	r3, r3, #17
 8005acc:	69ba      	ldr	r2, [r7, #24]
 8005ace:	4313      	orrs	r3, r2
 8005ad0:	61bb      	str	r3, [r7, #24]
    /* Enable external trigger if trigger selection is different of software  */
    /* start.                                                                 */
    /* Note: This configuration keeps the hardware feature of parameter       */
    /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
    /*       software start.                                                  */
    if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
 8005ad2:	687b      	ldr	r3, [r7, #4]
 8005ad4:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8005ad6:	2b00      	cmp	r3, #0
 8005ad8:	d009      	beq.n	8005aee <HAL_ADC_Init+0x1f2>
    {
      tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
 8005ada:	687b      	ldr	r3, [r7, #4]
 8005adc:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8005ade:	f403 7278 	and.w	r2, r3, #992	@ 0x3e0
                  | hadc->Init.ExternalTrigConvEdge
 8005ae2:	687b      	ldr	r3, [r7, #4]
 8005ae4:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8005ae6:	4313      	orrs	r3, r2
      tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
 8005ae8:	69ba      	ldr	r2, [r7, #24]
 8005aea:	4313      	orrs	r3, r2
 8005aec:	61bb      	str	r3, [r7, #24]
      /* Update Configuration Register CFGR */
      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
    }
#else
    /* Update Configuration Register CFGR */
    MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
 8005aee:	687b      	ldr	r3, [r7, #4]
 8005af0:	681b      	ldr	r3, [r3, #0]
 8005af2:	68da      	ldr	r2, [r3, #12]
 8005af4:	4b2c      	ldr	r3, [pc, #176]	@ (8005ba8 <HAL_ADC_Init+0x2ac>)
 8005af6:	4013      	ands	r3, r2
 8005af8:	687a      	ldr	r2, [r7, #4]
 8005afa:	6812      	ldr	r2, [r2, #0]
 8005afc:	69b9      	ldr	r1, [r7, #24]
 8005afe:	430b      	orrs	r3, r1
 8005b00:	60d3      	str	r3, [r2, #12]
    /* Parameters that can be updated when ADC is disabled or enabled without */
    /* conversion on going on regular and injected groups:                    */
    /*  - Conversion data management      Init.ConversionDataManagement       */
    /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
    /*  - Oversampling parameters         Init.Oversampling                   */
    tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
 8005b02:	687b      	ldr	r3, [r7, #4]
 8005b04:	681b      	ldr	r3, [r3, #0]
 8005b06:	4618      	mov	r0, r3
 8005b08:	f7ff fed2 	bl	80058b0 <LL_ADC_REG_IsConversionOngoing>
 8005b0c:	6138      	str	r0, [r7, #16]
    tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
 8005b0e:	687b      	ldr	r3, [r7, #4]
 8005b10:	681b      	ldr	r3, [r3, #0]
 8005b12:	4618      	mov	r0, r3
 8005b14:	f7ff fedf 	bl	80058d6 <LL_ADC_INJ_IsConversionOngoing>
 8005b18:	60f8      	str	r0, [r7, #12]
    if ((tmp_adc_is_conversion_on_going_regular == 0UL)
 8005b1a:	693b      	ldr	r3, [r7, #16]
 8005b1c:	2b00      	cmp	r3, #0
 8005b1e:	d15f      	bne.n	8005be0 <HAL_ADC_Init+0x2e4>
        && (tmp_adc_is_conversion_on_going_injected == 0UL)
 8005b20:	68fb      	ldr	r3, [r7, #12]
 8005b22:	2b00      	cmp	r3, #0
 8005b24:	d15c      	bne.n	8005be0 <HAL_ADC_Init+0x2e4>
                    ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
                    ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
      }
#else
      tmpCFGR = (
                  ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
 8005b26:	687b      	ldr	r3, [r7, #4]
 8005b28:	7d1b      	ldrb	r3, [r3, #20]
 8005b2a:	039a      	lsls	r2, r3, #14
                  ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
 8005b2c:	687b      	ldr	r3, [r7, #4]
 8005b2e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
      tmpCFGR = (
 8005b30:	4313      	orrs	r3, r2
 8005b32:	61bb      	str	r3, [r7, #24]
#endif

      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
 8005b34:	687b      	ldr	r3, [r7, #4]
 8005b36:	681b      	ldr	r3, [r3, #0]
 8005b38:	68da      	ldr	r2, [r3, #12]
 8005b3a:	4b1c      	ldr	r3, [pc, #112]	@ (8005bac <HAL_ADC_Init+0x2b0>)
 8005b3c:	4013      	ands	r3, r2
 8005b3e:	687a      	ldr	r2, [r7, #4]
 8005b40:	6812      	ldr	r2, [r2, #0]
 8005b42:	69b9      	ldr	r1, [r7, #24]
 8005b44:	430b      	orrs	r3, r1
 8005b46:	60d3      	str	r3, [r2, #12]

      if (hadc->Init.OversamplingMode == ENABLE)
 8005b48:	687b      	ldr	r3, [r7, #4]
 8005b4a:	f893 3038 	ldrb.w	r3, [r3, #56]	@ 0x38
 8005b4e:	2b01      	cmp	r3, #1
 8005b50:	d130      	bne.n	8005bb4 <HAL_ADC_Init+0x2b8>
#endif
        assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
        assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
        assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));

        if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
 8005b52:	687b      	ldr	r3, [r7, #4]
 8005b54:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8005b56:	2b00      	cmp	r3, #0
        /*  - Oversampling Ratio                                               */
        /*  - Right bit shift                                                  */
        /*  - Left bit shift                                                   */
        /*  - Triggered mode                                                   */
        /*  - Oversampling mode (continued/resumed)                            */
        MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
 8005b58:	687b      	ldr	r3, [r7, #4]
 8005b5a:	681b      	ldr	r3, [r3, #0]
 8005b5c:	691a      	ldr	r2, [r3, #16]
 8005b5e:	4b14      	ldr	r3, [pc, #80]	@ (8005bb0 <HAL_ADC_Init+0x2b4>)
 8005b60:	4013      	ands	r3, r2
 8005b62:	687a      	ldr	r2, [r7, #4]
 8005b64:	6bd2      	ldr	r2, [r2, #60]	@ 0x3c
 8005b66:	3a01      	subs	r2, #1
 8005b68:	0411      	lsls	r1, r2, #16
 8005b6a:	687a      	ldr	r2, [r7, #4]
 8005b6c:	6c12      	ldr	r2, [r2, #64]	@ 0x40
 8005b6e:	4311      	orrs	r1, r2
 8005b70:	687a      	ldr	r2, [r7, #4]
 8005b72:	6c52      	ldr	r2, [r2, #68]	@ 0x44
 8005b74:	4311      	orrs	r1, r2
 8005b76:	687a      	ldr	r2, [r7, #4]
 8005b78:	6c92      	ldr	r2, [r2, #72]	@ 0x48
 8005b7a:	430a      	orrs	r2, r1
 8005b7c:	431a      	orrs	r2, r3
 8005b7e:	687b      	ldr	r3, [r7, #4]
 8005b80:	681b      	ldr	r3, [r3, #0]
 8005b82:	f042 0201 	orr.w	r2, r2, #1
 8005b86:	611a      	str	r2, [r3, #16]
 8005b88:	e01c      	b.n	8005bc4 <HAL_ADC_Init+0x2c8>
 8005b8a:	bf00      	nop
 8005b8c:	24000034 	.word	0x24000034
 8005b90:	053e2d63 	.word	0x053e2d63
 8005b94:	40022000 	.word	0x40022000
 8005b98:	40022100 	.word	0x40022100
 8005b9c:	58026000 	.word	0x58026000
 8005ba0:	40022300 	.word	0x40022300
 8005ba4:	58026300 	.word	0x58026300
 8005ba8:	fff0c003 	.word	0xfff0c003
 8005bac:	ffffbffc 	.word	0xffffbffc
 8005bb0:	fc00f81e 	.word	0xfc00f81e

      }
      else
      {
        /* Disable ADC oversampling scope on ADC group regular */
        CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
 8005bb4:	687b      	ldr	r3, [r7, #4]
 8005bb6:	681b      	ldr	r3, [r3, #0]
 8005bb8:	691a      	ldr	r2, [r3, #16]
 8005bba:	687b      	ldr	r3, [r7, #4]
 8005bbc:	681b      	ldr	r3, [r3, #0]
 8005bbe:	f022 0201 	bic.w	r2, r2, #1
 8005bc2:	611a      	str	r2, [r3, #16]
      }

      /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
      MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
 8005bc4:	687b      	ldr	r3, [r7, #4]
 8005bc6:	681b      	ldr	r3, [r3, #0]
 8005bc8:	691b      	ldr	r3, [r3, #16]
 8005bca:	f023 4170 	bic.w	r1, r3, #4026531840	@ 0xf0000000
 8005bce:	687b      	ldr	r3, [r7, #4]
 8005bd0:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 8005bd2:	687b      	ldr	r3, [r7, #4]
 8005bd4:	681b      	ldr	r3, [r3, #0]
 8005bd6:	430a      	orrs	r2, r1
 8005bd8:	611a      	str	r2, [r3, #16]
        /* Configure the BOOST Mode */
        ADC_ConfigureBoostMode(hadc);
      }
#else
      /* Configure the BOOST Mode */
      ADC_ConfigureBoostMode(hadc);
 8005bda:	6878      	ldr	r0, [r7, #4]
 8005bdc:	f000 fde2 	bl	80067a4 <ADC_ConfigureBoostMode>
    /*   Note: Scan mode is not present by hardware on this device, but       */
    /*   emulated by software for alignment over all STM32 devices.           */
    /* - if scan mode is enabled, regular channels sequence length is set to  */
    /*   parameter "NbrOfConversion".                                         */

    if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
 8005be0:	687b      	ldr	r3, [r7, #4]
 8005be2:	68db      	ldr	r3, [r3, #12]
 8005be4:	2b01      	cmp	r3, #1
 8005be6:	d10c      	bne.n	8005c02 <HAL_ADC_Init+0x306>
    {
      /* Set number of ranks in regular group sequencer */
      MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
 8005be8:	687b      	ldr	r3, [r7, #4]
 8005bea:	681b      	ldr	r3, [r3, #0]
 8005bec:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8005bee:	f023 010f 	bic.w	r1, r3, #15
 8005bf2:	687b      	ldr	r3, [r7, #4]
 8005bf4:	699b      	ldr	r3, [r3, #24]
 8005bf6:	1e5a      	subs	r2, r3, #1
 8005bf8:	687b      	ldr	r3, [r7, #4]
 8005bfa:	681b      	ldr	r3, [r3, #0]
 8005bfc:	430a      	orrs	r2, r1
 8005bfe:	631a      	str	r2, [r3, #48]	@ 0x30
 8005c00:	e007      	b.n	8005c12 <HAL_ADC_Init+0x316>
    }
    else
    {
      CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
 8005c02:	687b      	ldr	r3, [r7, #4]
 8005c04:	681b      	ldr	r3, [r3, #0]
 8005c06:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
 8005c08:	687b      	ldr	r3, [r7, #4]
 8005c0a:	681b      	ldr	r3, [r3, #0]
 8005c0c:	f022 020f 	bic.w	r2, r2, #15
 8005c10:	631a      	str	r2, [r3, #48]	@ 0x30
    }

    /* Initialize the ADC state */
    /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
 8005c12:	687b      	ldr	r3, [r7, #4]
 8005c14:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8005c16:	f023 0303 	bic.w	r3, r3, #3
 8005c1a:	f043 0201 	orr.w	r2, r3, #1
 8005c1e:	687b      	ldr	r3, [r7, #4]
 8005c20:	655a      	str	r2, [r3, #84]	@ 0x54
 8005c22:	e007      	b.n	8005c34 <HAL_ADC_Init+0x338>
  }
  else
  {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8005c24:	687b      	ldr	r3, [r7, #4]
 8005c26:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8005c28:	f043 0210 	orr.w	r2, r3, #16
 8005c2c:	687b      	ldr	r3, [r7, #4]
 8005c2e:	655a      	str	r2, [r3, #84]	@ 0x54

    tmp_hal_status = HAL_ERROR;
 8005c30:	2301      	movs	r3, #1
 8005c32:	77fb      	strb	r3, [r7, #31]
  }

  /* Return function status */
  return tmp_hal_status;
 8005c34:	7ffb      	ldrb	r3, [r7, #31]
}
 8005c36:	4618      	mov	r0, r3
 8005c38:	3724      	adds	r7, #36	@ 0x24
 8005c3a:	46bd      	mov	sp, r7
 8005c3c:	bd90      	pop	{r4, r7, pc}
 8005c3e:	bf00      	nop

08005c40 <HAL_ADC_Start_DMA>:
  * @param pData Destination Buffer address.
  * @param Length Number of data to be transferred from ADC peripheral to memory
  * @retval HAL status.
  */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
{
 8005c40:	b580      	push	{r7, lr}
 8005c42:	b086      	sub	sp, #24
 8005c44:	af00      	add	r7, sp, #0
 8005c46:	60f8      	str	r0, [r7, #12]
 8005c48:	60b9      	str	r1, [r7, #8]
 8005c4a:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status;
  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
 8005c4c:	68fb      	ldr	r3, [r7, #12]
 8005c4e:	681b      	ldr	r3, [r3, #0]
 8005c50:	4a55      	ldr	r2, [pc, #340]	@ (8005da8 <HAL_ADC_Start_DMA+0x168>)
 8005c52:	4293      	cmp	r3, r2
 8005c54:	d004      	beq.n	8005c60 <HAL_ADC_Start_DMA+0x20>
 8005c56:	68fb      	ldr	r3, [r7, #12]
 8005c58:	681b      	ldr	r3, [r3, #0]
 8005c5a:	4a54      	ldr	r2, [pc, #336]	@ (8005dac <HAL_ADC_Start_DMA+0x16c>)
 8005c5c:	4293      	cmp	r3, r2
 8005c5e:	d101      	bne.n	8005c64 <HAL_ADC_Start_DMA+0x24>
 8005c60:	4b53      	ldr	r3, [pc, #332]	@ (8005db0 <HAL_ADC_Start_DMA+0x170>)
 8005c62:	e000      	b.n	8005c66 <HAL_ADC_Start_DMA+0x26>
 8005c64:	4b53      	ldr	r3, [pc, #332]	@ (8005db4 <HAL_ADC_Start_DMA+0x174>)
 8005c66:	4618      	mov	r0, r3
 8005c68:	f7ff fd64 	bl	8005734 <LL_ADC_GetMultimode>
 8005c6c:	6138      	str	r0, [r7, #16]

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Perform ADC enable and conversion start if no conversion is on going */
  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
 8005c6e:	68fb      	ldr	r3, [r7, #12]
 8005c70:	681b      	ldr	r3, [r3, #0]
 8005c72:	4618      	mov	r0, r3
 8005c74:	f7ff fe1c 	bl	80058b0 <LL_ADC_REG_IsConversionOngoing>
 8005c78:	4603      	mov	r3, r0
 8005c7a:	2b00      	cmp	r3, #0
 8005c7c:	f040 808c 	bne.w	8005d98 <HAL_ADC_Start_DMA+0x158>
  {
    /* Process locked */
    __HAL_LOCK(hadc);
 8005c80:	68fb      	ldr	r3, [r7, #12]
 8005c82:	f893 3050 	ldrb.w	r3, [r3, #80]	@ 0x50
 8005c86:	2b01      	cmp	r3, #1
 8005c88:	d101      	bne.n	8005c8e <HAL_ADC_Start_DMA+0x4e>
 8005c8a:	2302      	movs	r3, #2
 8005c8c:	e087      	b.n	8005d9e <HAL_ADC_Start_DMA+0x15e>
 8005c8e:	68fb      	ldr	r3, [r7, #12]
 8005c90:	2201      	movs	r2, #1
 8005c92:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

    /* Ensure that multimode regular conversions are not enabled.   */
    /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
    if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
 8005c96:	693b      	ldr	r3, [r7, #16]
 8005c98:	2b00      	cmp	r3, #0
 8005c9a:	d005      	beq.n	8005ca8 <HAL_ADC_Start_DMA+0x68>
        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
 8005c9c:	693b      	ldr	r3, [r7, #16]
 8005c9e:	2b05      	cmp	r3, #5
 8005ca0:	d002      	beq.n	8005ca8 <HAL_ADC_Start_DMA+0x68>
        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
 8005ca2:	693b      	ldr	r3, [r7, #16]
 8005ca4:	2b09      	cmp	r3, #9
 8005ca6:	d170      	bne.n	8005d8a <HAL_ADC_Start_DMA+0x14a>
       )
    {
      /* Enable the ADC peripheral */
      tmp_hal_status = ADC_Enable(hadc);
 8005ca8:	68f8      	ldr	r0, [r7, #12]
 8005caa:	f000 fbfd 	bl	80064a8 <ADC_Enable>
 8005cae:	4603      	mov	r3, r0
 8005cb0:	75fb      	strb	r3, [r7, #23]

      /* Start conversion if ADC is effectively enabled */
      if (tmp_hal_status == HAL_OK)
 8005cb2:	7dfb      	ldrb	r3, [r7, #23]
 8005cb4:	2b00      	cmp	r3, #0
 8005cb6:	d163      	bne.n	8005d80 <HAL_ADC_Start_DMA+0x140>
      {
        /* Set ADC state                                                        */
        /* - Clear state bitfield related to regular group conversion results   */
        /* - Set state bitfield related to regular operation                    */
        ADC_STATE_CLR_SET(hadc->State,
 8005cb8:	68fb      	ldr	r3, [r7, #12]
 8005cba:	6d5a      	ldr	r2, [r3, #84]	@ 0x54
 8005cbc:	4b3e      	ldr	r3, [pc, #248]	@ (8005db8 <HAL_ADC_Start_DMA+0x178>)
 8005cbe:	4013      	ands	r3, r2
 8005cc0:	f443 7280 	orr.w	r2, r3, #256	@ 0x100
 8005cc4:	68fb      	ldr	r3, [r7, #12]
 8005cc6:	655a      	str	r2, [r3, #84]	@ 0x54
                          HAL_ADC_STATE_REG_BUSY);

        /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
          - if ADC instance is master or if multimode feature is not available
          - if multimode setting is disabled (ADC instance slave in independent mode) */
        if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
 8005cc8:	68fb      	ldr	r3, [r7, #12]
 8005cca:	681b      	ldr	r3, [r3, #0]
 8005ccc:	4a37      	ldr	r2, [pc, #220]	@ (8005dac <HAL_ADC_Start_DMA+0x16c>)
 8005cce:	4293      	cmp	r3, r2
 8005cd0:	d002      	beq.n	8005cd8 <HAL_ADC_Start_DMA+0x98>
 8005cd2:	68fb      	ldr	r3, [r7, #12]
 8005cd4:	681b      	ldr	r3, [r3, #0]
 8005cd6:	e000      	b.n	8005cda <HAL_ADC_Start_DMA+0x9a>
 8005cd8:	4b33      	ldr	r3, [pc, #204]	@ (8005da8 <HAL_ADC_Start_DMA+0x168>)
 8005cda:	68fa      	ldr	r2, [r7, #12]
 8005cdc:	6812      	ldr	r2, [r2, #0]
 8005cde:	4293      	cmp	r3, r2
 8005ce0:	d002      	beq.n	8005ce8 <HAL_ADC_Start_DMA+0xa8>
            || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
 8005ce2:	693b      	ldr	r3, [r7, #16]
 8005ce4:	2b00      	cmp	r3, #0
 8005ce6:	d105      	bne.n	8005cf4 <HAL_ADC_Start_DMA+0xb4>
           )
        {
          CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
 8005ce8:	68fb      	ldr	r3, [r7, #12]
 8005cea:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8005cec:	f423 1280 	bic.w	r2, r3, #1048576	@ 0x100000
 8005cf0:	68fb      	ldr	r3, [r7, #12]
 8005cf2:	655a      	str	r2, [r3, #84]	@ 0x54
        }

        /* Check if a conversion is on going on ADC group injected */
        if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
 8005cf4:	68fb      	ldr	r3, [r7, #12]
 8005cf6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8005cf8:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
 8005cfc:	2b00      	cmp	r3, #0
 8005cfe:	d006      	beq.n	8005d0e <HAL_ADC_Start_DMA+0xce>
        {
          /* Reset ADC error code fields related to regular conversions only */
          CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
 8005d00:	68fb      	ldr	r3, [r7, #12]
 8005d02:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8005d04:	f023 0206 	bic.w	r2, r3, #6
 8005d08:	68fb      	ldr	r3, [r7, #12]
 8005d0a:	659a      	str	r2, [r3, #88]	@ 0x58
 8005d0c:	e002      	b.n	8005d14 <HAL_ADC_Start_DMA+0xd4>
        }
        else
        {
          /* Reset all ADC error code fields */
          ADC_CLEAR_ERRORCODE(hadc);
 8005d0e:	68fb      	ldr	r3, [r7, #12]
 8005d10:	2200      	movs	r2, #0
 8005d12:	659a      	str	r2, [r3, #88]	@ 0x58
        }

        /* Set the DMA transfer complete callback */
        hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
 8005d14:	68fb      	ldr	r3, [r7, #12]
 8005d16:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8005d18:	4a28      	ldr	r2, [pc, #160]	@ (8005dbc <HAL_ADC_Start_DMA+0x17c>)
 8005d1a:	63da      	str	r2, [r3, #60]	@ 0x3c

        /* Set the DMA half transfer complete callback */
        hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
 8005d1c:	68fb      	ldr	r3, [r7, #12]
 8005d1e:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8005d20:	4a27      	ldr	r2, [pc, #156]	@ (8005dc0 <HAL_ADC_Start_DMA+0x180>)
 8005d22:	641a      	str	r2, [r3, #64]	@ 0x40

        /* Set the DMA error callback */
        hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
 8005d24:	68fb      	ldr	r3, [r7, #12]
 8005d26:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8005d28:	4a26      	ldr	r2, [pc, #152]	@ (8005dc4 <HAL_ADC_Start_DMA+0x184>)
 8005d2a:	64da      	str	r2, [r3, #76]	@ 0x4c
        /* ADC start (in case of SW start):                                   */

        /* Clear regular group conversion flag and overrun flag               */
        /* (To ensure of no unknown state from potential previous ADC         */
        /* operations)                                                        */
        __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
 8005d2c:	68fb      	ldr	r3, [r7, #12]
 8005d2e:	681b      	ldr	r3, [r3, #0]
 8005d30:	221c      	movs	r2, #28
 8005d32:	601a      	str	r2, [r3, #0]

        /* Process unlocked */
        /* Unlock before starting ADC conversions: in case of potential         */
        /* interruption, to let the process to ADC IRQ Handler.                 */
        __HAL_UNLOCK(hadc);
 8005d34:	68fb      	ldr	r3, [r7, #12]
 8005d36:	2200      	movs	r2, #0
 8005d38:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

        /* With DMA, overrun event is always considered as an error even if
           hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
           ADC_IT_OVR is enabled. */
        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
 8005d3c:	68fb      	ldr	r3, [r7, #12]
 8005d3e:	681b      	ldr	r3, [r3, #0]
 8005d40:	685a      	ldr	r2, [r3, #4]
 8005d42:	68fb      	ldr	r3, [r7, #12]
 8005d44:	681b      	ldr	r3, [r3, #0]
 8005d46:	f042 0210 	orr.w	r2, r2, #16
 8005d4a:	605a      	str	r2, [r3, #4]
        {
          LL_ADC_REG_SetDataTransferMode(hadc->Instance, ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
        }

#else
        LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement);
 8005d4c:	68fb      	ldr	r3, [r7, #12]
 8005d4e:	681a      	ldr	r2, [r3, #0]
 8005d50:	68fb      	ldr	r3, [r7, #12]
 8005d52:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8005d54:	4619      	mov	r1, r3
 8005d56:	4610      	mov	r0, r2
 8005d58:	f7ff fc89 	bl	800566e <LL_ADC_REG_SetDataTransferMode>
#endif


        /* Start the DMA channel */
        tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
 8005d5c:	68fb      	ldr	r3, [r7, #12]
 8005d5e:	6cd8      	ldr	r0, [r3, #76]	@ 0x4c
 8005d60:	68fb      	ldr	r3, [r7, #12]
 8005d62:	681b      	ldr	r3, [r3, #0]
 8005d64:	3340      	adds	r3, #64	@ 0x40
 8005d66:	4619      	mov	r1, r3
 8005d68:	68ba      	ldr	r2, [r7, #8]
 8005d6a:	687b      	ldr	r3, [r7, #4]
 8005d6c:	f002 fa5e 	bl	800822c <HAL_DMA_Start_IT>
 8005d70:	4603      	mov	r3, r0
 8005d72:	75fb      	strb	r3, [r7, #23]
        /* Enable conversion of regular group.                                  */
        /* If software start has been selected, conversion starts immediately.  */
        /* If external trigger has been selected, conversion will start at next */
        /* trigger event.                                                       */
        /* Start ADC group regular conversion */
        LL_ADC_REG_StartConversion(hadc->Instance);
 8005d74:	68fb      	ldr	r3, [r7, #12]
 8005d76:	681b      	ldr	r3, [r3, #0]
 8005d78:	4618      	mov	r0, r3
 8005d7a:	f7ff fd85 	bl	8005888 <LL_ADC_REG_StartConversion>
      if (tmp_hal_status == HAL_OK)
 8005d7e:	e00d      	b.n	8005d9c <HAL_ADC_Start_DMA+0x15c>
      }
      else
      {
        /* Process unlocked */
        __HAL_UNLOCK(hadc);
 8005d80:	68fb      	ldr	r3, [r7, #12]
 8005d82:	2200      	movs	r2, #0
 8005d84:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50
      if (tmp_hal_status == HAL_OK)
 8005d88:	e008      	b.n	8005d9c <HAL_ADC_Start_DMA+0x15c>
      }

    }
    else
    {
      tmp_hal_status = HAL_ERROR;
 8005d8a:	2301      	movs	r3, #1
 8005d8c:	75fb      	strb	r3, [r7, #23]
      /* Process unlocked */
      __HAL_UNLOCK(hadc);
 8005d8e:	68fb      	ldr	r3, [r7, #12]
 8005d90:	2200      	movs	r2, #0
 8005d92:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50
 8005d96:	e001      	b.n	8005d9c <HAL_ADC_Start_DMA+0x15c>
    }
  }
  else
  {
    tmp_hal_status = HAL_BUSY;
 8005d98:	2302      	movs	r3, #2
 8005d9a:	75fb      	strb	r3, [r7, #23]
  }

  /* Return function status */
  return tmp_hal_status;
 8005d9c:	7dfb      	ldrb	r3, [r7, #23]
}
 8005d9e:	4618      	mov	r0, r3
 8005da0:	3718      	adds	r7, #24
 8005da2:	46bd      	mov	sp, r7
 8005da4:	bd80      	pop	{r7, pc}
 8005da6:	bf00      	nop
 8005da8:	40022000 	.word	0x40022000
 8005dac:	40022100 	.word	0x40022100
 8005db0:	40022300 	.word	0x40022300
 8005db4:	58026300 	.word	0x58026300
 8005db8:	fffff0fe 	.word	0xfffff0fe
 8005dbc:	0800667b 	.word	0x0800667b
 8005dc0:	08006753 	.word	0x08006753
 8005dc4:	0800676f 	.word	0x0800676f

08005dc8 <HAL_ADC_ConvHalfCpltCallback>:
  * @brief  Conversion DMA half-transfer callback in non-blocking mode.
  * @param hadc ADC handle
  * @retval None
  */
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
{
 8005dc8:	b480      	push	{r7}
 8005dca:	b083      	sub	sp, #12
 8005dcc:	af00      	add	r7, sp, #0
 8005dce:	6078      	str	r0, [r7, #4]
  UNUSED(hadc);

  /* NOTE : This function should not be modified. When the callback is needed,
            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
  */
}
 8005dd0:	bf00      	nop
 8005dd2:	370c      	adds	r7, #12
 8005dd4:	46bd      	mov	sp, r7
 8005dd6:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005dda:	4770      	bx	lr

08005ddc <HAL_ADC_ErrorCallback>:
  *           (this function is also clearing overrun flag)
  * @param hadc ADC handle
  * @retval None
  */
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
 8005ddc:	b480      	push	{r7}
 8005dde:	b083      	sub	sp, #12
 8005de0:	af00      	add	r7, sp, #0
 8005de2:	6078      	str	r0, [r7, #4]
  UNUSED(hadc);

  /* NOTE : This function should not be modified. When the callback is needed,
            function HAL_ADC_ErrorCallback must be implemented in the user file.
  */
}
 8005de4:	bf00      	nop
 8005de6:	370c      	adds	r7, #12
 8005de8:	46bd      	mov	sp, r7
 8005dea:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005dee:	4770      	bx	lr

08005df0 <HAL_ADC_ConfigChannel>:
  * @param hadc ADC handle
  * @param sConfig Structure of ADC channel assigned to ADC group regular.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
{
 8005df0:	b590      	push	{r4, r7, lr}
 8005df2:	b0a1      	sub	sp, #132	@ 0x84
 8005df4:	af00      	add	r7, sp, #0
 8005df6:	6078      	str	r0, [r7, #4]
 8005df8:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8005dfa:	2300      	movs	r3, #0
 8005dfc:	f887 307f 	strb.w	r3, [r7, #127]	@ 0x7f
  uint32_t tmpOffsetShifted;
  uint32_t tmp_config_internal_channel;
  __IO uint32_t wait_loop_index = 0;
 8005e00:	2300      	movs	r3, #0
 8005e02:	60bb      	str	r3, [r7, #8]
  /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
     ignored (considered as reset) */
  assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));

  /* Verification of channel number */
  if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
 8005e04:	683b      	ldr	r3, [r7, #0]
 8005e06:	68db      	ldr	r3, [r3, #12]
 8005e08:	4a65      	ldr	r2, [pc, #404]	@ (8005fa0 <HAL_ADC_ConfigChannel+0x1b0>)
 8005e0a:	4293      	cmp	r3, r2
    }
#endif
  }

  /* Process locked */
  __HAL_LOCK(hadc);
 8005e0c:	687b      	ldr	r3, [r7, #4]
 8005e0e:	f893 3050 	ldrb.w	r3, [r3, #80]	@ 0x50
 8005e12:	2b01      	cmp	r3, #1
 8005e14:	d101      	bne.n	8005e1a <HAL_ADC_ConfigChannel+0x2a>
 8005e16:	2302      	movs	r3, #2
 8005e18:	e32e      	b.n	8006478 <HAL_ADC_ConfigChannel+0x688>
 8005e1a:	687b      	ldr	r3, [r7, #4]
 8005e1c:	2201      	movs	r2, #1
 8005e1e:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50
  /* Parameters update conditioned to ADC state:                              */
  /* Parameters that can be updated when ADC is disabled or enabled without   */
  /* conversion on going on regular group:                                    */
  /*  - Channel number                                                        */
  /*  - Channel rank                                                          */
  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
 8005e22:	687b      	ldr	r3, [r7, #4]
 8005e24:	681b      	ldr	r3, [r3, #0]
 8005e26:	4618      	mov	r0, r3
 8005e28:	f7ff fd42 	bl	80058b0 <LL_ADC_REG_IsConversionOngoing>
 8005e2c:	4603      	mov	r3, r0
 8005e2e:	2b00      	cmp	r3, #0
 8005e30:	f040 8313 	bne.w	800645a <HAL_ADC_ConfigChannel+0x66a>
  {
    if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)))
 8005e34:	683b      	ldr	r3, [r7, #0]
 8005e36:	681b      	ldr	r3, [r3, #0]
 8005e38:	2b00      	cmp	r3, #0
 8005e3a:	db2c      	blt.n	8005e96 <HAL_ADC_ConfigChannel+0xa6>
        /* ADC channels preselection */
        hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
      }
#else
      /* ADC channels preselection */
      hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
 8005e3c:	683b      	ldr	r3, [r7, #0]
 8005e3e:	681b      	ldr	r3, [r3, #0]
 8005e40:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8005e44:	2b00      	cmp	r3, #0
 8005e46:	d108      	bne.n	8005e5a <HAL_ADC_ConfigChannel+0x6a>
 8005e48:	683b      	ldr	r3, [r7, #0]
 8005e4a:	681b      	ldr	r3, [r3, #0]
 8005e4c:	0e9b      	lsrs	r3, r3, #26
 8005e4e:	f003 031f 	and.w	r3, r3, #31
 8005e52:	2201      	movs	r2, #1
 8005e54:	fa02 f303 	lsl.w	r3, r2, r3
 8005e58:	e016      	b.n	8005e88 <HAL_ADC_ConfigChannel+0x98>
 8005e5a:	683b      	ldr	r3, [r7, #0]
 8005e5c:	681b      	ldr	r3, [r3, #0]
 8005e5e:	667b      	str	r3, [r7, #100]	@ 0x64
  uint32_t result;

#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 8005e60:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 8005e62:	fa93 f3a3 	rbit	r3, r3
 8005e66:	663b      	str	r3, [r7, #96]	@ 0x60
    result |= value & 1U;
    s--;
  }
  result <<= s;                        /* shift when v's highest bits are zero */
#endif
  return result;
 8005e68:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 8005e6a:	66bb      	str	r3, [r7, #104]	@ 0x68
     optimisations using the logic "value was passed to __builtin_clz, so it
     is non-zero".
     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
     single CLZ instruction.
   */
  if (value == 0U)
 8005e6c:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 8005e6e:	2b00      	cmp	r3, #0
 8005e70:	d101      	bne.n	8005e76 <HAL_ADC_ConfigChannel+0x86>
  {
    return 32U;
 8005e72:	2320      	movs	r3, #32
 8005e74:	e003      	b.n	8005e7e <HAL_ADC_ConfigChannel+0x8e>
  }
  return __builtin_clz(value);
 8005e76:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 8005e78:	fab3 f383 	clz	r3, r3
 8005e7c:	b2db      	uxtb	r3, r3
 8005e7e:	f003 031f 	and.w	r3, r3, #31
 8005e82:	2201      	movs	r2, #1
 8005e84:	fa02 f303 	lsl.w	r3, r2, r3
 8005e88:	687a      	ldr	r2, [r7, #4]
 8005e8a:	6812      	ldr	r2, [r2, #0]
 8005e8c:	69d1      	ldr	r1, [r2, #28]
 8005e8e:	687a      	ldr	r2, [r7, #4]
 8005e90:	6812      	ldr	r2, [r2, #0]
 8005e92:	430b      	orrs	r3, r1
 8005e94:	61d3      	str	r3, [r2, #28]
#endif /* ADC_VER_V5_V90 */
    }

    /* Set ADC group regular sequence: channel on the selected scan sequence rank */
    LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
 8005e96:	687b      	ldr	r3, [r7, #4]
 8005e98:	6818      	ldr	r0, [r3, #0]
 8005e9a:	683b      	ldr	r3, [r7, #0]
 8005e9c:	6859      	ldr	r1, [r3, #4]
 8005e9e:	683b      	ldr	r3, [r7, #0]
 8005ea0:	681b      	ldr	r3, [r3, #0]
 8005ea2:	461a      	mov	r2, r3
 8005ea4:	f7ff fbb7 	bl	8005616 <LL_ADC_REG_SetSequencerRanks>
    /* Parameters update conditioned to ADC state:                              */
    /* Parameters that can be updated when ADC is disabled or enabled without   */
    /* conversion on going on regular group:                                    */
    /*  - Channel sampling time                                                 */
    /*  - Channel offset                                                        */
    tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
 8005ea8:	687b      	ldr	r3, [r7, #4]
 8005eaa:	681b      	ldr	r3, [r3, #0]
 8005eac:	4618      	mov	r0, r3
 8005eae:	f7ff fcff 	bl	80058b0 <LL_ADC_REG_IsConversionOngoing>
 8005eb2:	67b8      	str	r0, [r7, #120]	@ 0x78
    tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
 8005eb4:	687b      	ldr	r3, [r7, #4]
 8005eb6:	681b      	ldr	r3, [r3, #0]
 8005eb8:	4618      	mov	r0, r3
 8005eba:	f7ff fd0c 	bl	80058d6 <LL_ADC_INJ_IsConversionOngoing>
 8005ebe:	6778      	str	r0, [r7, #116]	@ 0x74
    if ((tmp_adc_is_conversion_on_going_regular == 0UL)
 8005ec0:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
 8005ec2:	2b00      	cmp	r3, #0
 8005ec4:	f040 80b8 	bne.w	8006038 <HAL_ADC_ConfigChannel+0x248>
        && (tmp_adc_is_conversion_on_going_injected == 0UL)
 8005ec8:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
 8005eca:	2b00      	cmp	r3, #0
 8005ecc:	f040 80b4 	bne.w	8006038 <HAL_ADC_ConfigChannel+0x248>
       )
    {
      /* Set sampling time of the selected ADC channel */
      LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
 8005ed0:	687b      	ldr	r3, [r7, #4]
 8005ed2:	6818      	ldr	r0, [r3, #0]
 8005ed4:	683b      	ldr	r3, [r7, #0]
 8005ed6:	6819      	ldr	r1, [r3, #0]
 8005ed8:	683b      	ldr	r3, [r7, #0]
 8005eda:	689b      	ldr	r3, [r3, #8]
 8005edc:	461a      	mov	r2, r3
 8005ede:	f7ff fbd9 	bl	8005694 <LL_ADC_SetChannelSamplingTime>
        tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
      }
      else
#endif /* ADC_VER_V5_V90 */
      {
        tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
 8005ee2:	4b30      	ldr	r3, [pc, #192]	@ (8005fa4 <HAL_ADC_ConfigChannel+0x1b4>)
 8005ee4:	681b      	ldr	r3, [r3, #0]
 8005ee6:	f003 4370 	and.w	r3, r3, #4026531840	@ 0xf0000000
 8005eea:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 8005eee:	d10b      	bne.n	8005f08 <HAL_ADC_ConfigChannel+0x118>
 8005ef0:	683b      	ldr	r3, [r7, #0]
 8005ef2:	695a      	ldr	r2, [r3, #20]
 8005ef4:	687b      	ldr	r3, [r7, #4]
 8005ef6:	681b      	ldr	r3, [r3, #0]
 8005ef8:	68db      	ldr	r3, [r3, #12]
 8005efa:	089b      	lsrs	r3, r3, #2
 8005efc:	f003 0307 	and.w	r3, r3, #7
 8005f00:	005b      	lsls	r3, r3, #1
 8005f02:	fa02 f303 	lsl.w	r3, r2, r3
 8005f06:	e01d      	b.n	8005f44 <HAL_ADC_ConfigChannel+0x154>
 8005f08:	687b      	ldr	r3, [r7, #4]
 8005f0a:	681b      	ldr	r3, [r3, #0]
 8005f0c:	68db      	ldr	r3, [r3, #12]
 8005f0e:	f003 0310 	and.w	r3, r3, #16
 8005f12:	2b00      	cmp	r3, #0
 8005f14:	d10b      	bne.n	8005f2e <HAL_ADC_ConfigChannel+0x13e>
 8005f16:	683b      	ldr	r3, [r7, #0]
 8005f18:	695a      	ldr	r2, [r3, #20]
 8005f1a:	687b      	ldr	r3, [r7, #4]
 8005f1c:	681b      	ldr	r3, [r3, #0]
 8005f1e:	68db      	ldr	r3, [r3, #12]
 8005f20:	089b      	lsrs	r3, r3, #2
 8005f22:	f003 0307 	and.w	r3, r3, #7
 8005f26:	005b      	lsls	r3, r3, #1
 8005f28:	fa02 f303 	lsl.w	r3, r2, r3
 8005f2c:	e00a      	b.n	8005f44 <HAL_ADC_ConfigChannel+0x154>
 8005f2e:	683b      	ldr	r3, [r7, #0]
 8005f30:	695a      	ldr	r2, [r3, #20]
 8005f32:	687b      	ldr	r3, [r7, #4]
 8005f34:	681b      	ldr	r3, [r3, #0]
 8005f36:	68db      	ldr	r3, [r3, #12]
 8005f38:	089b      	lsrs	r3, r3, #2
 8005f3a:	f003 0304 	and.w	r3, r3, #4
 8005f3e:	005b      	lsls	r3, r3, #1
 8005f40:	fa02 f303 	lsl.w	r3, r2, r3
 8005f44:	673b      	str	r3, [r7, #112]	@ 0x70
      }
      
      if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
 8005f46:	683b      	ldr	r3, [r7, #0]
 8005f48:	691b      	ldr	r3, [r3, #16]
 8005f4a:	2b04      	cmp	r3, #4
 8005f4c:	d02c      	beq.n	8005fa8 <HAL_ADC_ConfigChannel+0x1b8>
      {
        /* Set ADC selected offset number */
        LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
 8005f4e:	687b      	ldr	r3, [r7, #4]
 8005f50:	6818      	ldr	r0, [r3, #0]
 8005f52:	683b      	ldr	r3, [r7, #0]
 8005f54:	6919      	ldr	r1, [r3, #16]
 8005f56:	683b      	ldr	r3, [r7, #0]
 8005f58:	681a      	ldr	r2, [r3, #0]
 8005f5a:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
 8005f5c:	f7ff faf4 	bl	8005548 <LL_ADC_SetOffset>
        else
#endif /* ADC_VER_V5_V90 */
        {
          assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation));
          /* Set ADC selected offset signed saturation */
          LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
 8005f60:	687b      	ldr	r3, [r7, #4]
 8005f62:	6818      	ldr	r0, [r3, #0]
 8005f64:	683b      	ldr	r3, [r7, #0]
 8005f66:	6919      	ldr	r1, [r3, #16]
 8005f68:	683b      	ldr	r3, [r7, #0]
 8005f6a:	7e5b      	ldrb	r3, [r3, #25]
 8005f6c:	2b01      	cmp	r3, #1
 8005f6e:	d102      	bne.n	8005f76 <HAL_ADC_ConfigChannel+0x186>
 8005f70:	f04f 4300 	mov.w	r3, #2147483648	@ 0x80000000
 8005f74:	e000      	b.n	8005f78 <HAL_ADC_ConfigChannel+0x188>
 8005f76:	2300      	movs	r3, #0
 8005f78:	461a      	mov	r2, r3
 8005f7a:	f7ff fb1e 	bl	80055ba <LL_ADC_SetOffsetSignedSaturation>

          assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift));
          /* Set ADC selected offset right shift */
          LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
 8005f7e:	687b      	ldr	r3, [r7, #4]
 8005f80:	6818      	ldr	r0, [r3, #0]
 8005f82:	683b      	ldr	r3, [r7, #0]
 8005f84:	6919      	ldr	r1, [r3, #16]
 8005f86:	683b      	ldr	r3, [r7, #0]
 8005f88:	7e1b      	ldrb	r3, [r3, #24]
 8005f8a:	2b01      	cmp	r3, #1
 8005f8c:	d102      	bne.n	8005f94 <HAL_ADC_ConfigChannel+0x1a4>
 8005f8e:	f44f 6300 	mov.w	r3, #2048	@ 0x800
 8005f92:	e000      	b.n	8005f96 <HAL_ADC_ConfigChannel+0x1a6>
 8005f94:	2300      	movs	r3, #0
 8005f96:	461a      	mov	r2, r3
 8005f98:	f7ff faf6 	bl	8005588 <LL_ADC_SetDataRightShift>
 8005f9c:	e04c      	b.n	8006038 <HAL_ADC_ConfigChannel+0x248>
 8005f9e:	bf00      	nop
 8005fa0:	47ff0000 	.word	0x47ff0000
 8005fa4:	5c001000 	.word	0x5c001000
          }
        }
        else
#endif /* ADC_VER_V5_V90 */
        {
          if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
 8005fa8:	687b      	ldr	r3, [r7, #4]
 8005faa:	681b      	ldr	r3, [r3, #0]
 8005fac:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8005fae:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 8005fb2:	683b      	ldr	r3, [r7, #0]
 8005fb4:	681b      	ldr	r3, [r3, #0]
 8005fb6:	069b      	lsls	r3, r3, #26
 8005fb8:	429a      	cmp	r2, r3
 8005fba:	d107      	bne.n	8005fcc <HAL_ADC_ConfigChannel+0x1dc>
          {
            CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
 8005fbc:	687b      	ldr	r3, [r7, #4]
 8005fbe:	681b      	ldr	r3, [r3, #0]
 8005fc0:	6e1a      	ldr	r2, [r3, #96]	@ 0x60
 8005fc2:	687b      	ldr	r3, [r7, #4]
 8005fc4:	681b      	ldr	r3, [r3, #0]
 8005fc6:	f022 4200 	bic.w	r2, r2, #2147483648	@ 0x80000000
 8005fca:	661a      	str	r2, [r3, #96]	@ 0x60
          }
          if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
 8005fcc:	687b      	ldr	r3, [r7, #4]
 8005fce:	681b      	ldr	r3, [r3, #0]
 8005fd0:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8005fd2:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 8005fd6:	683b      	ldr	r3, [r7, #0]
 8005fd8:	681b      	ldr	r3, [r3, #0]
 8005fda:	069b      	lsls	r3, r3, #26
 8005fdc:	429a      	cmp	r2, r3
 8005fde:	d107      	bne.n	8005ff0 <HAL_ADC_ConfigChannel+0x200>
          {
            CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
 8005fe0:	687b      	ldr	r3, [r7, #4]
 8005fe2:	681b      	ldr	r3, [r3, #0]
 8005fe4:	6e5a      	ldr	r2, [r3, #100]	@ 0x64
 8005fe6:	687b      	ldr	r3, [r7, #4]
 8005fe8:	681b      	ldr	r3, [r3, #0]
 8005fea:	f022 4200 	bic.w	r2, r2, #2147483648	@ 0x80000000
 8005fee:	665a      	str	r2, [r3, #100]	@ 0x64
          }
          if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
 8005ff0:	687b      	ldr	r3, [r7, #4]
 8005ff2:	681b      	ldr	r3, [r3, #0]
 8005ff4:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 8005ff6:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 8005ffa:	683b      	ldr	r3, [r7, #0]
 8005ffc:	681b      	ldr	r3, [r3, #0]
 8005ffe:	069b      	lsls	r3, r3, #26
 8006000:	429a      	cmp	r2, r3
 8006002:	d107      	bne.n	8006014 <HAL_ADC_ConfigChannel+0x224>
          {
            CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
 8006004:	687b      	ldr	r3, [r7, #4]
 8006006:	681b      	ldr	r3, [r3, #0]
 8006008:	6e9a      	ldr	r2, [r3, #104]	@ 0x68
 800600a:	687b      	ldr	r3, [r7, #4]
 800600c:	681b      	ldr	r3, [r3, #0]
 800600e:	f022 4200 	bic.w	r2, r2, #2147483648	@ 0x80000000
 8006012:	669a      	str	r2, [r3, #104]	@ 0x68
          }
          if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
 8006014:	687b      	ldr	r3, [r7, #4]
 8006016:	681b      	ldr	r3, [r3, #0]
 8006018:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800601a:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 800601e:	683b      	ldr	r3, [r7, #0]
 8006020:	681b      	ldr	r3, [r3, #0]
 8006022:	069b      	lsls	r3, r3, #26
 8006024:	429a      	cmp	r2, r3
 8006026:	d107      	bne.n	8006038 <HAL_ADC_ConfigChannel+0x248>
          {
            CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
 8006028:	687b      	ldr	r3, [r7, #4]
 800602a:	681b      	ldr	r3, [r3, #0]
 800602c:	6eda      	ldr	r2, [r3, #108]	@ 0x6c
 800602e:	687b      	ldr	r3, [r7, #4]
 8006030:	681b      	ldr	r3, [r3, #0]
 8006032:	f022 4200 	bic.w	r2, r2, #2147483648	@ 0x80000000
 8006036:	66da      	str	r2, [r3, #108]	@ 0x6c

    /* Parameters update conditioned to ADC state:                              */
    /* Parameters that can be updated only when ADC is disabled:                */
    /*  - Single or differential mode                                           */
    /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
    if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
 8006038:	687b      	ldr	r3, [r7, #4]
 800603a:	681b      	ldr	r3, [r3, #0]
 800603c:	4618      	mov	r0, r3
 800603e:	f7ff fbfd 	bl	800583c <LL_ADC_IsEnabled>
 8006042:	4603      	mov	r3, r0
 8006044:	2b00      	cmp	r3, #0
 8006046:	f040 8211 	bne.w	800646c <HAL_ADC_ConfigChannel+0x67c>
    {
      /* Set mode single-ended or differential input of the selected ADC channel */
      LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
 800604a:	687b      	ldr	r3, [r7, #4]
 800604c:	6818      	ldr	r0, [r3, #0]
 800604e:	683b      	ldr	r3, [r7, #0]
 8006050:	6819      	ldr	r1, [r3, #0]
 8006052:	683b      	ldr	r3, [r7, #0]
 8006054:	68db      	ldr	r3, [r3, #12]
 8006056:	461a      	mov	r2, r3
 8006058:	f7ff fb48 	bl	80056ec <LL_ADC_SetChannelSingleDiff>

      /* Configuration of differential mode */
      if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
 800605c:	683b      	ldr	r3, [r7, #0]
 800605e:	68db      	ldr	r3, [r3, #12]
 8006060:	4aa1      	ldr	r2, [pc, #644]	@ (80062e8 <HAL_ADC_ConfigChannel+0x4f8>)
 8006062:	4293      	cmp	r3, r2
 8006064:	f040 812e 	bne.w	80062c4 <HAL_ADC_ConfigChannel+0x4d4>
      {
        /* Set sampling time of the selected ADC channel */
        /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
        LL_ADC_SetChannelSamplingTime(hadc->Instance,
 8006068:	687b      	ldr	r3, [r7, #4]
 800606a:	6818      	ldr	r0, [r3, #0]
                                      (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
 800606c:	683b      	ldr	r3, [r7, #0]
 800606e:	681b      	ldr	r3, [r3, #0]
 8006070:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8006074:	2b00      	cmp	r3, #0
 8006076:	d10b      	bne.n	8006090 <HAL_ADC_ConfigChannel+0x2a0>
 8006078:	683b      	ldr	r3, [r7, #0]
 800607a:	681b      	ldr	r3, [r3, #0]
 800607c:	0e9b      	lsrs	r3, r3, #26
 800607e:	3301      	adds	r3, #1
 8006080:	f003 031f 	and.w	r3, r3, #31
 8006084:	2b09      	cmp	r3, #9
 8006086:	bf94      	ite	ls
 8006088:	2301      	movls	r3, #1
 800608a:	2300      	movhi	r3, #0
 800608c:	b2db      	uxtb	r3, r3
 800608e:	e019      	b.n	80060c4 <HAL_ADC_ConfigChannel+0x2d4>
 8006090:	683b      	ldr	r3, [r7, #0]
 8006092:	681b      	ldr	r3, [r3, #0]
 8006094:	65bb      	str	r3, [r7, #88]	@ 0x58
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 8006096:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
 8006098:	fa93 f3a3 	rbit	r3, r3
 800609c:	657b      	str	r3, [r7, #84]	@ 0x54
  return result;
 800609e:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 80060a0:	65fb      	str	r3, [r7, #92]	@ 0x5c
  if (value == 0U)
 80060a2:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 80060a4:	2b00      	cmp	r3, #0
 80060a6:	d101      	bne.n	80060ac <HAL_ADC_ConfigChannel+0x2bc>
    return 32U;
 80060a8:	2320      	movs	r3, #32
 80060aa:	e003      	b.n	80060b4 <HAL_ADC_ConfigChannel+0x2c4>
  return __builtin_clz(value);
 80060ac:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 80060ae:	fab3 f383 	clz	r3, r3
 80060b2:	b2db      	uxtb	r3, r3
 80060b4:	3301      	adds	r3, #1
 80060b6:	f003 031f 	and.w	r3, r3, #31
 80060ba:	2b09      	cmp	r3, #9
 80060bc:	bf94      	ite	ls
 80060be:	2301      	movls	r3, #1
 80060c0:	2300      	movhi	r3, #0
 80060c2:	b2db      	uxtb	r3, r3
        LL_ADC_SetChannelSamplingTime(hadc->Instance,
 80060c4:	2b00      	cmp	r3, #0
 80060c6:	d079      	beq.n	80061bc <HAL_ADC_ConfigChannel+0x3cc>
                                      (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
 80060c8:	683b      	ldr	r3, [r7, #0]
 80060ca:	681b      	ldr	r3, [r3, #0]
 80060cc:	f3c3 0313 	ubfx	r3, r3, #0, #20
 80060d0:	2b00      	cmp	r3, #0
 80060d2:	d107      	bne.n	80060e4 <HAL_ADC_ConfigChannel+0x2f4>
 80060d4:	683b      	ldr	r3, [r7, #0]
 80060d6:	681b      	ldr	r3, [r3, #0]
 80060d8:	0e9b      	lsrs	r3, r3, #26
 80060da:	3301      	adds	r3, #1
 80060dc:	069b      	lsls	r3, r3, #26
 80060de:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 80060e2:	e015      	b.n	8006110 <HAL_ADC_ConfigChannel+0x320>
 80060e4:	683b      	ldr	r3, [r7, #0]
 80060e6:	681b      	ldr	r3, [r3, #0]
 80060e8:	64fb      	str	r3, [r7, #76]	@ 0x4c
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 80060ea:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 80060ec:	fa93 f3a3 	rbit	r3, r3
 80060f0:	64bb      	str	r3, [r7, #72]	@ 0x48
  return result;
 80060f2:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 80060f4:	653b      	str	r3, [r7, #80]	@ 0x50
  if (value == 0U)
 80060f6:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 80060f8:	2b00      	cmp	r3, #0
 80060fa:	d101      	bne.n	8006100 <HAL_ADC_ConfigChannel+0x310>
    return 32U;
 80060fc:	2320      	movs	r3, #32
 80060fe:	e003      	b.n	8006108 <HAL_ADC_ConfigChannel+0x318>
  return __builtin_clz(value);
 8006100:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 8006102:	fab3 f383 	clz	r3, r3
 8006106:	b2db      	uxtb	r3, r3
 8006108:	3301      	adds	r3, #1
 800610a:	069b      	lsls	r3, r3, #26
 800610c:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 8006110:	683b      	ldr	r3, [r7, #0]
 8006112:	681b      	ldr	r3, [r3, #0]
 8006114:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8006118:	2b00      	cmp	r3, #0
 800611a:	d109      	bne.n	8006130 <HAL_ADC_ConfigChannel+0x340>
 800611c:	683b      	ldr	r3, [r7, #0]
 800611e:	681b      	ldr	r3, [r3, #0]
 8006120:	0e9b      	lsrs	r3, r3, #26
 8006122:	3301      	adds	r3, #1
 8006124:	f003 031f 	and.w	r3, r3, #31
 8006128:	2101      	movs	r1, #1
 800612a:	fa01 f303 	lsl.w	r3, r1, r3
 800612e:	e017      	b.n	8006160 <HAL_ADC_ConfigChannel+0x370>
 8006130:	683b      	ldr	r3, [r7, #0]
 8006132:	681b      	ldr	r3, [r3, #0]
 8006134:	643b      	str	r3, [r7, #64]	@ 0x40
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 8006136:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 8006138:	fa93 f3a3 	rbit	r3, r3
 800613c:	63fb      	str	r3, [r7, #60]	@ 0x3c
  return result;
 800613e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8006140:	647b      	str	r3, [r7, #68]	@ 0x44
  if (value == 0U)
 8006142:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 8006144:	2b00      	cmp	r3, #0
 8006146:	d101      	bne.n	800614c <HAL_ADC_ConfigChannel+0x35c>
    return 32U;
 8006148:	2320      	movs	r3, #32
 800614a:	e003      	b.n	8006154 <HAL_ADC_ConfigChannel+0x364>
  return __builtin_clz(value);
 800614c:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 800614e:	fab3 f383 	clz	r3, r3
 8006152:	b2db      	uxtb	r3, r3
 8006154:	3301      	adds	r3, #1
 8006156:	f003 031f 	and.w	r3, r3, #31
 800615a:	2101      	movs	r1, #1
 800615c:	fa01 f303 	lsl.w	r3, r1, r3
 8006160:	ea42 0103 	orr.w	r1, r2, r3
 8006164:	683b      	ldr	r3, [r7, #0]
 8006166:	681b      	ldr	r3, [r3, #0]
 8006168:	f3c3 0313 	ubfx	r3, r3, #0, #20
 800616c:	2b00      	cmp	r3, #0
 800616e:	d10a      	bne.n	8006186 <HAL_ADC_ConfigChannel+0x396>
 8006170:	683b      	ldr	r3, [r7, #0]
 8006172:	681b      	ldr	r3, [r3, #0]
 8006174:	0e9b      	lsrs	r3, r3, #26
 8006176:	3301      	adds	r3, #1
 8006178:	f003 021f 	and.w	r2, r3, #31
 800617c:	4613      	mov	r3, r2
 800617e:	005b      	lsls	r3, r3, #1
 8006180:	4413      	add	r3, r2
 8006182:	051b      	lsls	r3, r3, #20
 8006184:	e018      	b.n	80061b8 <HAL_ADC_ConfigChannel+0x3c8>
 8006186:	683b      	ldr	r3, [r7, #0]
 8006188:	681b      	ldr	r3, [r3, #0]
 800618a:	637b      	str	r3, [r7, #52]	@ 0x34
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 800618c:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800618e:	fa93 f3a3 	rbit	r3, r3
 8006192:	633b      	str	r3, [r7, #48]	@ 0x30
  return result;
 8006194:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8006196:	63bb      	str	r3, [r7, #56]	@ 0x38
  if (value == 0U)
 8006198:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800619a:	2b00      	cmp	r3, #0
 800619c:	d101      	bne.n	80061a2 <HAL_ADC_ConfigChannel+0x3b2>
    return 32U;
 800619e:	2320      	movs	r3, #32
 80061a0:	e003      	b.n	80061aa <HAL_ADC_ConfigChannel+0x3ba>
  return __builtin_clz(value);
 80061a2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80061a4:	fab3 f383 	clz	r3, r3
 80061a8:	b2db      	uxtb	r3, r3
 80061aa:	3301      	adds	r3, #1
 80061ac:	f003 021f 	and.w	r2, r3, #31
 80061b0:	4613      	mov	r3, r2
 80061b2:	005b      	lsls	r3, r3, #1
 80061b4:	4413      	add	r3, r2
 80061b6:	051b      	lsls	r3, r3, #20
        LL_ADC_SetChannelSamplingTime(hadc->Instance,
 80061b8:	430b      	orrs	r3, r1
 80061ba:	e07e      	b.n	80062ba <HAL_ADC_ConfigChannel+0x4ca>
                                      (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
 80061bc:	683b      	ldr	r3, [r7, #0]
 80061be:	681b      	ldr	r3, [r3, #0]
 80061c0:	f3c3 0313 	ubfx	r3, r3, #0, #20
 80061c4:	2b00      	cmp	r3, #0
 80061c6:	d107      	bne.n	80061d8 <HAL_ADC_ConfigChannel+0x3e8>
 80061c8:	683b      	ldr	r3, [r7, #0]
 80061ca:	681b      	ldr	r3, [r3, #0]
 80061cc:	0e9b      	lsrs	r3, r3, #26
 80061ce:	3301      	adds	r3, #1
 80061d0:	069b      	lsls	r3, r3, #26
 80061d2:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 80061d6:	e015      	b.n	8006204 <HAL_ADC_ConfigChannel+0x414>
 80061d8:	683b      	ldr	r3, [r7, #0]
 80061da:	681b      	ldr	r3, [r3, #0]
 80061dc:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 80061de:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80061e0:	fa93 f3a3 	rbit	r3, r3
 80061e4:	627b      	str	r3, [r7, #36]	@ 0x24
  return result;
 80061e6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80061e8:	62fb      	str	r3, [r7, #44]	@ 0x2c
  if (value == 0U)
 80061ea:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80061ec:	2b00      	cmp	r3, #0
 80061ee:	d101      	bne.n	80061f4 <HAL_ADC_ConfigChannel+0x404>
    return 32U;
 80061f0:	2320      	movs	r3, #32
 80061f2:	e003      	b.n	80061fc <HAL_ADC_ConfigChannel+0x40c>
  return __builtin_clz(value);
 80061f4:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80061f6:	fab3 f383 	clz	r3, r3
 80061fa:	b2db      	uxtb	r3, r3
 80061fc:	3301      	adds	r3, #1
 80061fe:	069b      	lsls	r3, r3, #26
 8006200:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
 8006204:	683b      	ldr	r3, [r7, #0]
 8006206:	681b      	ldr	r3, [r3, #0]
 8006208:	f3c3 0313 	ubfx	r3, r3, #0, #20
 800620c:	2b00      	cmp	r3, #0
 800620e:	d109      	bne.n	8006224 <HAL_ADC_ConfigChannel+0x434>
 8006210:	683b      	ldr	r3, [r7, #0]
 8006212:	681b      	ldr	r3, [r3, #0]
 8006214:	0e9b      	lsrs	r3, r3, #26
 8006216:	3301      	adds	r3, #1
 8006218:	f003 031f 	and.w	r3, r3, #31
 800621c:	2101      	movs	r1, #1
 800621e:	fa01 f303 	lsl.w	r3, r1, r3
 8006222:	e017      	b.n	8006254 <HAL_ADC_ConfigChannel+0x464>
 8006224:	683b      	ldr	r3, [r7, #0]
 8006226:	681b      	ldr	r3, [r3, #0]
 8006228:	61fb      	str	r3, [r7, #28]
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 800622a:	69fb      	ldr	r3, [r7, #28]
 800622c:	fa93 f3a3 	rbit	r3, r3
 8006230:	61bb      	str	r3, [r7, #24]
  return result;
 8006232:	69bb      	ldr	r3, [r7, #24]
 8006234:	623b      	str	r3, [r7, #32]
  if (value == 0U)
 8006236:	6a3b      	ldr	r3, [r7, #32]
 8006238:	2b00      	cmp	r3, #0
 800623a:	d101      	bne.n	8006240 <HAL_ADC_ConfigChannel+0x450>
    return 32U;
 800623c:	2320      	movs	r3, #32
 800623e:	e003      	b.n	8006248 <HAL_ADC_ConfigChannel+0x458>
  return __builtin_clz(value);
 8006240:	6a3b      	ldr	r3, [r7, #32]
 8006242:	fab3 f383 	clz	r3, r3
 8006246:	b2db      	uxtb	r3, r3
 8006248:	3301      	adds	r3, #1
 800624a:	f003 031f 	and.w	r3, r3, #31
 800624e:	2101      	movs	r1, #1
 8006250:	fa01 f303 	lsl.w	r3, r1, r3
 8006254:	ea42 0103 	orr.w	r1, r2, r3
 8006258:	683b      	ldr	r3, [r7, #0]
 800625a:	681b      	ldr	r3, [r3, #0]
 800625c:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8006260:	2b00      	cmp	r3, #0
 8006262:	d10d      	bne.n	8006280 <HAL_ADC_ConfigChannel+0x490>
 8006264:	683b      	ldr	r3, [r7, #0]
 8006266:	681b      	ldr	r3, [r3, #0]
 8006268:	0e9b      	lsrs	r3, r3, #26
 800626a:	3301      	adds	r3, #1
 800626c:	f003 021f 	and.w	r2, r3, #31
 8006270:	4613      	mov	r3, r2
 8006272:	005b      	lsls	r3, r3, #1
 8006274:	4413      	add	r3, r2
 8006276:	3b1e      	subs	r3, #30
 8006278:	051b      	lsls	r3, r3, #20
 800627a:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
 800627e:	e01b      	b.n	80062b8 <HAL_ADC_ConfigChannel+0x4c8>
 8006280:	683b      	ldr	r3, [r7, #0]
 8006282:	681b      	ldr	r3, [r3, #0]
 8006284:	613b      	str	r3, [r7, #16]
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 8006286:	693b      	ldr	r3, [r7, #16]
 8006288:	fa93 f3a3 	rbit	r3, r3
 800628c:	60fb      	str	r3, [r7, #12]
  return result;
 800628e:	68fb      	ldr	r3, [r7, #12]
 8006290:	617b      	str	r3, [r7, #20]
  if (value == 0U)
 8006292:	697b      	ldr	r3, [r7, #20]
 8006294:	2b00      	cmp	r3, #0
 8006296:	d101      	bne.n	800629c <HAL_ADC_ConfigChannel+0x4ac>
    return 32U;
 8006298:	2320      	movs	r3, #32
 800629a:	e003      	b.n	80062a4 <HAL_ADC_ConfigChannel+0x4b4>
  return __builtin_clz(value);
 800629c:	697b      	ldr	r3, [r7, #20]
 800629e:	fab3 f383 	clz	r3, r3
 80062a2:	b2db      	uxtb	r3, r3
 80062a4:	3301      	adds	r3, #1
 80062a6:	f003 021f 	and.w	r2, r3, #31
 80062aa:	4613      	mov	r3, r2
 80062ac:	005b      	lsls	r3, r3, #1
 80062ae:	4413      	add	r3, r2
 80062b0:	3b1e      	subs	r3, #30
 80062b2:	051b      	lsls	r3, r3, #20
 80062b4:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
        LL_ADC_SetChannelSamplingTime(hadc->Instance,
 80062b8:	430b      	orrs	r3, r1
 80062ba:	683a      	ldr	r2, [r7, #0]
 80062bc:	6892      	ldr	r2, [r2, #8]
 80062be:	4619      	mov	r1, r3
 80062c0:	f7ff f9e8 	bl	8005694 <LL_ADC_SetChannelSamplingTime>
      /* If internal channel selected, enable dedicated internal buffers and    */
      /* paths.                                                                 */
      /* Note: these internal measurement paths can be disabled using           */
      /* HAL_ADC_DeInit().                                                      */

      if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
 80062c4:	683b      	ldr	r3, [r7, #0]
 80062c6:	681b      	ldr	r3, [r3, #0]
 80062c8:	2b00      	cmp	r3, #0
 80062ca:	f280 80cf 	bge.w	800646c <HAL_ADC_ConfigChannel+0x67c>
      {
        /* Configuration of common ADC parameters                                 */

        tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
 80062ce:	687b      	ldr	r3, [r7, #4]
 80062d0:	681b      	ldr	r3, [r3, #0]
 80062d2:	4a06      	ldr	r2, [pc, #24]	@ (80062ec <HAL_ADC_ConfigChannel+0x4fc>)
 80062d4:	4293      	cmp	r3, r2
 80062d6:	d004      	beq.n	80062e2 <HAL_ADC_ConfigChannel+0x4f2>
 80062d8:	687b      	ldr	r3, [r7, #4]
 80062da:	681b      	ldr	r3, [r3, #0]
 80062dc:	4a04      	ldr	r2, [pc, #16]	@ (80062f0 <HAL_ADC_ConfigChannel+0x500>)
 80062de:	4293      	cmp	r3, r2
 80062e0:	d10a      	bne.n	80062f8 <HAL_ADC_ConfigChannel+0x508>
 80062e2:	4b04      	ldr	r3, [pc, #16]	@ (80062f4 <HAL_ADC_ConfigChannel+0x504>)
 80062e4:	e009      	b.n	80062fa <HAL_ADC_ConfigChannel+0x50a>
 80062e6:	bf00      	nop
 80062e8:	47ff0000 	.word	0x47ff0000
 80062ec:	40022000 	.word	0x40022000
 80062f0:	40022100 	.word	0x40022100
 80062f4:	40022300 	.word	0x40022300
 80062f8:	4b61      	ldr	r3, [pc, #388]	@ (8006480 <HAL_ADC_ConfigChannel+0x690>)
 80062fa:	4618      	mov	r0, r3
 80062fc:	f7ff f916 	bl	800552c <LL_ADC_GetCommonPathInternalCh>
 8006300:	66f8      	str	r0, [r7, #108]	@ 0x6c

        /* Software is allowed to change common parameters only when all ADCs   */
        /* of the common group are disabled.                                    */
        if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
 8006302:	687b      	ldr	r3, [r7, #4]
 8006304:	681b      	ldr	r3, [r3, #0]
 8006306:	4a5f      	ldr	r2, [pc, #380]	@ (8006484 <HAL_ADC_ConfigChannel+0x694>)
 8006308:	4293      	cmp	r3, r2
 800630a:	d004      	beq.n	8006316 <HAL_ADC_ConfigChannel+0x526>
 800630c:	687b      	ldr	r3, [r7, #4]
 800630e:	681b      	ldr	r3, [r3, #0]
 8006310:	4a5d      	ldr	r2, [pc, #372]	@ (8006488 <HAL_ADC_ConfigChannel+0x698>)
 8006312:	4293      	cmp	r3, r2
 8006314:	d10e      	bne.n	8006334 <HAL_ADC_ConfigChannel+0x544>
 8006316:	485b      	ldr	r0, [pc, #364]	@ (8006484 <HAL_ADC_ConfigChannel+0x694>)
 8006318:	f7ff fa90 	bl	800583c <LL_ADC_IsEnabled>
 800631c:	4604      	mov	r4, r0
 800631e:	485a      	ldr	r0, [pc, #360]	@ (8006488 <HAL_ADC_ConfigChannel+0x698>)
 8006320:	f7ff fa8c 	bl	800583c <LL_ADC_IsEnabled>
 8006324:	4603      	mov	r3, r0
 8006326:	4323      	orrs	r3, r4
 8006328:	2b00      	cmp	r3, #0
 800632a:	bf0c      	ite	eq
 800632c:	2301      	moveq	r3, #1
 800632e:	2300      	movne	r3, #0
 8006330:	b2db      	uxtb	r3, r3
 8006332:	e008      	b.n	8006346 <HAL_ADC_ConfigChannel+0x556>
 8006334:	4855      	ldr	r0, [pc, #340]	@ (800648c <HAL_ADC_ConfigChannel+0x69c>)
 8006336:	f7ff fa81 	bl	800583c <LL_ADC_IsEnabled>
 800633a:	4603      	mov	r3, r0
 800633c:	2b00      	cmp	r3, #0
 800633e:	bf0c      	ite	eq
 8006340:	2301      	moveq	r3, #1
 8006342:	2300      	movne	r3, #0
 8006344:	b2db      	uxtb	r3, r3
 8006346:	2b00      	cmp	r3, #0
 8006348:	d07d      	beq.n	8006446 <HAL_ADC_ConfigChannel+0x656>
        {
          /* If the requested internal measurement path has already been enabled, */
          /* bypass the configuration processing.                                 */
          if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
 800634a:	683b      	ldr	r3, [r7, #0]
 800634c:	681b      	ldr	r3, [r3, #0]
 800634e:	4a50      	ldr	r2, [pc, #320]	@ (8006490 <HAL_ADC_ConfigChannel+0x6a0>)
 8006350:	4293      	cmp	r3, r2
 8006352:	d130      	bne.n	80063b6 <HAL_ADC_ConfigChannel+0x5c6>
 8006354:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8006356:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 800635a:	2b00      	cmp	r3, #0
 800635c:	d12b      	bne.n	80063b6 <HAL_ADC_ConfigChannel+0x5c6>
          {
            if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
 800635e:	687b      	ldr	r3, [r7, #4]
 8006360:	681b      	ldr	r3, [r3, #0]
 8006362:	4a4a      	ldr	r2, [pc, #296]	@ (800648c <HAL_ADC_ConfigChannel+0x69c>)
 8006364:	4293      	cmp	r3, r2
 8006366:	f040 8081 	bne.w	800646c <HAL_ADC_ConfigChannel+0x67c>
            {
              LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
 800636a:	687b      	ldr	r3, [r7, #4]
 800636c:	681b      	ldr	r3, [r3, #0]
 800636e:	4a45      	ldr	r2, [pc, #276]	@ (8006484 <HAL_ADC_ConfigChannel+0x694>)
 8006370:	4293      	cmp	r3, r2
 8006372:	d004      	beq.n	800637e <HAL_ADC_ConfigChannel+0x58e>
 8006374:	687b      	ldr	r3, [r7, #4]
 8006376:	681b      	ldr	r3, [r3, #0]
 8006378:	4a43      	ldr	r2, [pc, #268]	@ (8006488 <HAL_ADC_ConfigChannel+0x698>)
 800637a:	4293      	cmp	r3, r2
 800637c:	d101      	bne.n	8006382 <HAL_ADC_ConfigChannel+0x592>
 800637e:	4a45      	ldr	r2, [pc, #276]	@ (8006494 <HAL_ADC_ConfigChannel+0x6a4>)
 8006380:	e000      	b.n	8006384 <HAL_ADC_ConfigChannel+0x594>
 8006382:	4a3f      	ldr	r2, [pc, #252]	@ (8006480 <HAL_ADC_ConfigChannel+0x690>)
 8006384:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8006386:	f443 0300 	orr.w	r3, r3, #8388608	@ 0x800000
 800638a:	4619      	mov	r1, r3
 800638c:	4610      	mov	r0, r2
 800638e:	f7ff f8ba 	bl	8005506 <LL_ADC_SetCommonPathInternalCh>
              /* Delay for temperature sensor stabilization time */
              /* Wait loop initialization and execution */
              /* Note: Variable divided by 2 to compensate partially              */
              /*       CPU processing cycles, scaling in us split to not          */
              /*       exceed 32 bits register capacity and handle low frequency. */
              wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
 8006392:	4b41      	ldr	r3, [pc, #260]	@ (8006498 <HAL_ADC_ConfigChannel+0x6a8>)
 8006394:	681b      	ldr	r3, [r3, #0]
 8006396:	099b      	lsrs	r3, r3, #6
 8006398:	4a40      	ldr	r2, [pc, #256]	@ (800649c <HAL_ADC_ConfigChannel+0x6ac>)
 800639a:	fba2 2303 	umull	r2, r3, r2, r3
 800639e:	099b      	lsrs	r3, r3, #6
 80063a0:	3301      	adds	r3, #1
 80063a2:	005b      	lsls	r3, r3, #1
 80063a4:	60bb      	str	r3, [r7, #8]
              while (wait_loop_index != 0UL)
 80063a6:	e002      	b.n	80063ae <HAL_ADC_ConfigChannel+0x5be>
              {
                wait_loop_index--;
 80063a8:	68bb      	ldr	r3, [r7, #8]
 80063aa:	3b01      	subs	r3, #1
 80063ac:	60bb      	str	r3, [r7, #8]
              while (wait_loop_index != 0UL)
 80063ae:	68bb      	ldr	r3, [r7, #8]
 80063b0:	2b00      	cmp	r3, #0
 80063b2:	d1f9      	bne.n	80063a8 <HAL_ADC_ConfigChannel+0x5b8>
            if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
 80063b4:	e05a      	b.n	800646c <HAL_ADC_ConfigChannel+0x67c>
              }
            }
          }
          else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
 80063b6:	683b      	ldr	r3, [r7, #0]
 80063b8:	681b      	ldr	r3, [r3, #0]
 80063ba:	4a39      	ldr	r2, [pc, #228]	@ (80064a0 <HAL_ADC_ConfigChannel+0x6b0>)
 80063bc:	4293      	cmp	r3, r2
 80063be:	d11e      	bne.n	80063fe <HAL_ADC_ConfigChannel+0x60e>
 80063c0:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 80063c2:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 80063c6:	2b00      	cmp	r3, #0
 80063c8:	d119      	bne.n	80063fe <HAL_ADC_ConfigChannel+0x60e>
          {
            if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
 80063ca:	687b      	ldr	r3, [r7, #4]
 80063cc:	681b      	ldr	r3, [r3, #0]
 80063ce:	4a2f      	ldr	r2, [pc, #188]	@ (800648c <HAL_ADC_ConfigChannel+0x69c>)
 80063d0:	4293      	cmp	r3, r2
 80063d2:	d14b      	bne.n	800646c <HAL_ADC_ConfigChannel+0x67c>
            {
              LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
 80063d4:	687b      	ldr	r3, [r7, #4]
 80063d6:	681b      	ldr	r3, [r3, #0]
 80063d8:	4a2a      	ldr	r2, [pc, #168]	@ (8006484 <HAL_ADC_ConfigChannel+0x694>)
 80063da:	4293      	cmp	r3, r2
 80063dc:	d004      	beq.n	80063e8 <HAL_ADC_ConfigChannel+0x5f8>
 80063de:	687b      	ldr	r3, [r7, #4]
 80063e0:	681b      	ldr	r3, [r3, #0]
 80063e2:	4a29      	ldr	r2, [pc, #164]	@ (8006488 <HAL_ADC_ConfigChannel+0x698>)
 80063e4:	4293      	cmp	r3, r2
 80063e6:	d101      	bne.n	80063ec <HAL_ADC_ConfigChannel+0x5fc>
 80063e8:	4a2a      	ldr	r2, [pc, #168]	@ (8006494 <HAL_ADC_ConfigChannel+0x6a4>)
 80063ea:	e000      	b.n	80063ee <HAL_ADC_ConfigChannel+0x5fe>
 80063ec:	4a24      	ldr	r2, [pc, #144]	@ (8006480 <HAL_ADC_ConfigChannel+0x690>)
 80063ee:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 80063f0:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 80063f4:	4619      	mov	r1, r3
 80063f6:	4610      	mov	r0, r2
 80063f8:	f7ff f885 	bl	8005506 <LL_ADC_SetCommonPathInternalCh>
            if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
 80063fc:	e036      	b.n	800646c <HAL_ADC_ConfigChannel+0x67c>
            }
          }
          else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
 80063fe:	683b      	ldr	r3, [r7, #0]
 8006400:	681b      	ldr	r3, [r3, #0]
 8006402:	4a28      	ldr	r2, [pc, #160]	@ (80064a4 <HAL_ADC_ConfigChannel+0x6b4>)
 8006404:	4293      	cmp	r3, r2
 8006406:	d131      	bne.n	800646c <HAL_ADC_ConfigChannel+0x67c>
 8006408:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 800640a:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
 800640e:	2b00      	cmp	r3, #0
 8006410:	d12c      	bne.n	800646c <HAL_ADC_ConfigChannel+0x67c>
          {
            if (ADC_VREFINT_INSTANCE(hadc))
 8006412:	687b      	ldr	r3, [r7, #4]
 8006414:	681b      	ldr	r3, [r3, #0]
 8006416:	4a1d      	ldr	r2, [pc, #116]	@ (800648c <HAL_ADC_ConfigChannel+0x69c>)
 8006418:	4293      	cmp	r3, r2
 800641a:	d127      	bne.n	800646c <HAL_ADC_ConfigChannel+0x67c>
            {
              LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
 800641c:	687b      	ldr	r3, [r7, #4]
 800641e:	681b      	ldr	r3, [r3, #0]
 8006420:	4a18      	ldr	r2, [pc, #96]	@ (8006484 <HAL_ADC_ConfigChannel+0x694>)
 8006422:	4293      	cmp	r3, r2
 8006424:	d004      	beq.n	8006430 <HAL_ADC_ConfigChannel+0x640>
 8006426:	687b      	ldr	r3, [r7, #4]
 8006428:	681b      	ldr	r3, [r3, #0]
 800642a:	4a17      	ldr	r2, [pc, #92]	@ (8006488 <HAL_ADC_ConfigChannel+0x698>)
 800642c:	4293      	cmp	r3, r2
 800642e:	d101      	bne.n	8006434 <HAL_ADC_ConfigChannel+0x644>
 8006430:	4a18      	ldr	r2, [pc, #96]	@ (8006494 <HAL_ADC_ConfigChannel+0x6a4>)
 8006432:	e000      	b.n	8006436 <HAL_ADC_ConfigChannel+0x646>
 8006434:	4a12      	ldr	r2, [pc, #72]	@ (8006480 <HAL_ADC_ConfigChannel+0x690>)
 8006436:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8006438:	f443 0380 	orr.w	r3, r3, #4194304	@ 0x400000
 800643c:	4619      	mov	r1, r3
 800643e:	4610      	mov	r0, r2
 8006440:	f7ff f861 	bl	8005506 <LL_ADC_SetCommonPathInternalCh>
 8006444:	e012      	b.n	800646c <HAL_ADC_ConfigChannel+0x67c>
        /* enabled and other ADC of the common group are enabled, internal      */
        /* measurement paths cannot be enabled.                                 */
        else
        {
          /* Update ADC state machine to error */
          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 8006446:	687b      	ldr	r3, [r7, #4]
 8006448:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800644a:	f043 0220 	orr.w	r2, r3, #32
 800644e:	687b      	ldr	r3, [r7, #4]
 8006450:	655a      	str	r2, [r3, #84]	@ 0x54

          tmp_hal_status = HAL_ERROR;
 8006452:	2301      	movs	r3, #1
 8006454:	f887 307f 	strb.w	r3, [r7, #127]	@ 0x7f
 8006458:	e008      	b.n	800646c <HAL_ADC_ConfigChannel+0x67c>
  /* channel could be done on neither of the channel configuration structure  */
  /* parameters.                                                              */
  else
  {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 800645a:	687b      	ldr	r3, [r7, #4]
 800645c:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800645e:	f043 0220 	orr.w	r2, r3, #32
 8006462:	687b      	ldr	r3, [r7, #4]
 8006464:	655a      	str	r2, [r3, #84]	@ 0x54

    tmp_hal_status = HAL_ERROR;
 8006466:	2301      	movs	r3, #1
 8006468:	f887 307f 	strb.w	r3, [r7, #127]	@ 0x7f
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 800646c:	687b      	ldr	r3, [r7, #4]
 800646e:	2200      	movs	r2, #0
 8006470:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

  /* Return function status */
  return tmp_hal_status;
 8006474:	f897 307f 	ldrb.w	r3, [r7, #127]	@ 0x7f
}
 8006478:	4618      	mov	r0, r3
 800647a:	3784      	adds	r7, #132	@ 0x84
 800647c:	46bd      	mov	sp, r7
 800647e:	bd90      	pop	{r4, r7, pc}
 8006480:	58026300 	.word	0x58026300
 8006484:	40022000 	.word	0x40022000
 8006488:	40022100 	.word	0x40022100
 800648c:	58026000 	.word	0x58026000
 8006490:	cb840000 	.word	0xcb840000
 8006494:	40022300 	.word	0x40022300
 8006498:	24000034 	.word	0x24000034
 800649c:	053e2d63 	.word	0x053e2d63
 80064a0:	c7520000 	.word	0xc7520000
 80064a4:	cfb80000 	.word	0xcfb80000

080064a8 <ADC_Enable>:
  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
  * @param hadc ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
 80064a8:	b580      	push	{r7, lr}
 80064aa:	b084      	sub	sp, #16
 80064ac:	af00      	add	r7, sp, #0
 80064ae:	6078      	str	r0, [r7, #4]

  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
  /* enabling phase not yet completed: flag ADC ready not yet set).           */
  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
  /* causes: ADC clock not running, ...).                                     */
  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
 80064b0:	687b      	ldr	r3, [r7, #4]
 80064b2:	681b      	ldr	r3, [r3, #0]
 80064b4:	4618      	mov	r0, r3
 80064b6:	f7ff f9c1 	bl	800583c <LL_ADC_IsEnabled>
 80064ba:	4603      	mov	r3, r0
 80064bc:	2b00      	cmp	r3, #0
 80064be:	d16e      	bne.n	800659e <ADC_Enable+0xf6>
  {
    /* Check if conditions to enable the ADC are fulfilled */
    if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
 80064c0:	687b      	ldr	r3, [r7, #4]
 80064c2:	681b      	ldr	r3, [r3, #0]
 80064c4:	689a      	ldr	r2, [r3, #8]
 80064c6:	4b38      	ldr	r3, [pc, #224]	@ (80065a8 <ADC_Enable+0x100>)
 80064c8:	4013      	ands	r3, r2
 80064ca:	2b00      	cmp	r3, #0
 80064cc:	d00d      	beq.n	80064ea <ADC_Enable+0x42>
    {
      /* Update ADC state machine to error */
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 80064ce:	687b      	ldr	r3, [r7, #4]
 80064d0:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80064d2:	f043 0210 	orr.w	r2, r3, #16
 80064d6:	687b      	ldr	r3, [r7, #4]
 80064d8:	655a      	str	r2, [r3, #84]	@ 0x54

      /* Set ADC error code to ADC peripheral internal error */
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80064da:	687b      	ldr	r3, [r7, #4]
 80064dc:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80064de:	f043 0201 	orr.w	r2, r3, #1
 80064e2:	687b      	ldr	r3, [r7, #4]
 80064e4:	659a      	str	r2, [r3, #88]	@ 0x58

      return HAL_ERROR;
 80064e6:	2301      	movs	r3, #1
 80064e8:	e05a      	b.n	80065a0 <ADC_Enable+0xf8>
    }

    /* Enable the ADC peripheral */
    LL_ADC_Enable(hadc->Instance);
 80064ea:	687b      	ldr	r3, [r7, #4]
 80064ec:	681b      	ldr	r3, [r3, #0]
 80064ee:	4618      	mov	r0, r3
 80064f0:	f7ff f97c 	bl	80057ec <LL_ADC_Enable>

    /* Wait for ADC effectively enabled */
    tickstart = HAL_GetTick();
 80064f4:	f7fe ffa2 	bl	800543c <HAL_GetTick>
 80064f8:	60f8      	str	r0, [r7, #12]

    /* Poll for ADC ready flag raised except case of multimode enabled
       and ADC slave selected. */
    uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
 80064fa:	687b      	ldr	r3, [r7, #4]
 80064fc:	681b      	ldr	r3, [r3, #0]
 80064fe:	4a2b      	ldr	r2, [pc, #172]	@ (80065ac <ADC_Enable+0x104>)
 8006500:	4293      	cmp	r3, r2
 8006502:	d004      	beq.n	800650e <ADC_Enable+0x66>
 8006504:	687b      	ldr	r3, [r7, #4]
 8006506:	681b      	ldr	r3, [r3, #0]
 8006508:	4a29      	ldr	r2, [pc, #164]	@ (80065b0 <ADC_Enable+0x108>)
 800650a:	4293      	cmp	r3, r2
 800650c:	d101      	bne.n	8006512 <ADC_Enable+0x6a>
 800650e:	4b29      	ldr	r3, [pc, #164]	@ (80065b4 <ADC_Enable+0x10c>)
 8006510:	e000      	b.n	8006514 <ADC_Enable+0x6c>
 8006512:	4b29      	ldr	r3, [pc, #164]	@ (80065b8 <ADC_Enable+0x110>)
 8006514:	4618      	mov	r0, r3
 8006516:	f7ff f90d 	bl	8005734 <LL_ADC_GetMultimode>
 800651a:	60b8      	str	r0, [r7, #8]
    if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
 800651c:	687b      	ldr	r3, [r7, #4]
 800651e:	681b      	ldr	r3, [r3, #0]
 8006520:	4a23      	ldr	r2, [pc, #140]	@ (80065b0 <ADC_Enable+0x108>)
 8006522:	4293      	cmp	r3, r2
 8006524:	d002      	beq.n	800652c <ADC_Enable+0x84>
 8006526:	687b      	ldr	r3, [r7, #4]
 8006528:	681b      	ldr	r3, [r3, #0]
 800652a:	e000      	b.n	800652e <ADC_Enable+0x86>
 800652c:	4b1f      	ldr	r3, [pc, #124]	@ (80065ac <ADC_Enable+0x104>)
 800652e:	687a      	ldr	r2, [r7, #4]
 8006530:	6812      	ldr	r2, [r2, #0]
 8006532:	4293      	cmp	r3, r2
 8006534:	d02c      	beq.n	8006590 <ADC_Enable+0xe8>
        || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
 8006536:	68bb      	ldr	r3, [r7, #8]
 8006538:	2b00      	cmp	r3, #0
 800653a:	d130      	bne.n	800659e <ADC_Enable+0xf6>
       )
    {
      while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
 800653c:	e028      	b.n	8006590 <ADC_Enable+0xe8>
            The workaround is to continue setting ADEN until ADRDY is becomes 1.
            Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
            4 ADC clock cycle duration */
        /* Note: Test of ADC enabled required due to hardware constraint to     */
        /*       not enable ADC if already enabled.                             */
        if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
 800653e:	687b      	ldr	r3, [r7, #4]
 8006540:	681b      	ldr	r3, [r3, #0]
 8006542:	4618      	mov	r0, r3
 8006544:	f7ff f97a 	bl	800583c <LL_ADC_IsEnabled>
 8006548:	4603      	mov	r3, r0
 800654a:	2b00      	cmp	r3, #0
 800654c:	d104      	bne.n	8006558 <ADC_Enable+0xb0>
        {
          LL_ADC_Enable(hadc->Instance);
 800654e:	687b      	ldr	r3, [r7, #4]
 8006550:	681b      	ldr	r3, [r3, #0]
 8006552:	4618      	mov	r0, r3
 8006554:	f7ff f94a 	bl	80057ec <LL_ADC_Enable>
        }

        if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
 8006558:	f7fe ff70 	bl	800543c <HAL_GetTick>
 800655c:	4602      	mov	r2, r0
 800655e:	68fb      	ldr	r3, [r7, #12]
 8006560:	1ad3      	subs	r3, r2, r3
 8006562:	2b02      	cmp	r3, #2
 8006564:	d914      	bls.n	8006590 <ADC_Enable+0xe8>
        {
          /* New check to avoid false timeout detection in case of preemption */
          if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
 8006566:	687b      	ldr	r3, [r7, #4]
 8006568:	681b      	ldr	r3, [r3, #0]
 800656a:	681b      	ldr	r3, [r3, #0]
 800656c:	f003 0301 	and.w	r3, r3, #1
 8006570:	2b01      	cmp	r3, #1
 8006572:	d00d      	beq.n	8006590 <ADC_Enable+0xe8>
          {
            /* Update ADC state machine to error */
            SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8006574:	687b      	ldr	r3, [r7, #4]
 8006576:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006578:	f043 0210 	orr.w	r2, r3, #16
 800657c:	687b      	ldr	r3, [r7, #4]
 800657e:	655a      	str	r2, [r3, #84]	@ 0x54

            /* Set ADC error code to ADC peripheral internal error */
            SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8006580:	687b      	ldr	r3, [r7, #4]
 8006582:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8006584:	f043 0201 	orr.w	r2, r3, #1
 8006588:	687b      	ldr	r3, [r7, #4]
 800658a:	659a      	str	r2, [r3, #88]	@ 0x58

            return HAL_ERROR;
 800658c:	2301      	movs	r3, #1
 800658e:	e007      	b.n	80065a0 <ADC_Enable+0xf8>
      while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
 8006590:	687b      	ldr	r3, [r7, #4]
 8006592:	681b      	ldr	r3, [r3, #0]
 8006594:	681b      	ldr	r3, [r3, #0]
 8006596:	f003 0301 	and.w	r3, r3, #1
 800659a:	2b01      	cmp	r3, #1
 800659c:	d1cf      	bne.n	800653e <ADC_Enable+0x96>
      }
    }
  }

  /* Return HAL status */
  return HAL_OK;
 800659e:	2300      	movs	r3, #0
}
 80065a0:	4618      	mov	r0, r3
 80065a2:	3710      	adds	r7, #16
 80065a4:	46bd      	mov	sp, r7
 80065a6:	bd80      	pop	{r7, pc}
 80065a8:	8000003f 	.word	0x8000003f
 80065ac:	40022000 	.word	0x40022000
 80065b0:	40022100 	.word	0x40022100
 80065b4:	40022300 	.word	0x40022300
 80065b8:	58026300 	.word	0x58026300

080065bc <ADC_Disable>:
  *         stopped.
  * @param hadc ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
{
 80065bc:	b580      	push	{r7, lr}
 80065be:	b084      	sub	sp, #16
 80065c0:	af00      	add	r7, sp, #0
 80065c2:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
 80065c4:	687b      	ldr	r3, [r7, #4]
 80065c6:	681b      	ldr	r3, [r3, #0]
 80065c8:	4618      	mov	r0, r3
 80065ca:	f7ff f94a 	bl	8005862 <LL_ADC_IsDisableOngoing>
 80065ce:	60f8      	str	r0, [r7, #12]

  /* Verification if ADC is not already disabled:                             */
  /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
  /*       disabled.                                                          */
  if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
 80065d0:	687b      	ldr	r3, [r7, #4]
 80065d2:	681b      	ldr	r3, [r3, #0]
 80065d4:	4618      	mov	r0, r3
 80065d6:	f7ff f931 	bl	800583c <LL_ADC_IsEnabled>
 80065da:	4603      	mov	r3, r0
 80065dc:	2b00      	cmp	r3, #0
 80065de:	d047      	beq.n	8006670 <ADC_Disable+0xb4>
      && (tmp_adc_is_disable_on_going == 0UL)
 80065e0:	68fb      	ldr	r3, [r7, #12]
 80065e2:	2b00      	cmp	r3, #0
 80065e4:	d144      	bne.n	8006670 <ADC_Disable+0xb4>
     )
  {
    /* Check if conditions to disable the ADC are fulfilled */
    if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
 80065e6:	687b      	ldr	r3, [r7, #4]
 80065e8:	681b      	ldr	r3, [r3, #0]
 80065ea:	689b      	ldr	r3, [r3, #8]
 80065ec:	f003 030d 	and.w	r3, r3, #13
 80065f0:	2b01      	cmp	r3, #1
 80065f2:	d10c      	bne.n	800660e <ADC_Disable+0x52>
    {
      /* Disable the ADC peripheral */
      LL_ADC_Disable(hadc->Instance);
 80065f4:	687b      	ldr	r3, [r7, #4]
 80065f6:	681b      	ldr	r3, [r3, #0]
 80065f8:	4618      	mov	r0, r3
 80065fa:	f7ff f90b 	bl	8005814 <LL_ADC_Disable>
      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
 80065fe:	687b      	ldr	r3, [r7, #4]
 8006600:	681b      	ldr	r3, [r3, #0]
 8006602:	2203      	movs	r2, #3
 8006604:	601a      	str	r2, [r3, #0]
      return HAL_ERROR;
    }

    /* Wait for ADC effectively disabled */
    /* Get tick count */
    tickstart = HAL_GetTick();
 8006606:	f7fe ff19 	bl	800543c <HAL_GetTick>
 800660a:	60b8      	str	r0, [r7, #8]

    while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
 800660c:	e029      	b.n	8006662 <ADC_Disable+0xa6>
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 800660e:	687b      	ldr	r3, [r7, #4]
 8006610:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006612:	f043 0210 	orr.w	r2, r3, #16
 8006616:	687b      	ldr	r3, [r7, #4]
 8006618:	655a      	str	r2, [r3, #84]	@ 0x54
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 800661a:	687b      	ldr	r3, [r7, #4]
 800661c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800661e:	f043 0201 	orr.w	r2, r3, #1
 8006622:	687b      	ldr	r3, [r7, #4]
 8006624:	659a      	str	r2, [r3, #88]	@ 0x58
      return HAL_ERROR;
 8006626:	2301      	movs	r3, #1
 8006628:	e023      	b.n	8006672 <ADC_Disable+0xb6>
    {
      if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
 800662a:	f7fe ff07 	bl	800543c <HAL_GetTick>
 800662e:	4602      	mov	r2, r0
 8006630:	68bb      	ldr	r3, [r7, #8]
 8006632:	1ad3      	subs	r3, r2, r3
 8006634:	2b02      	cmp	r3, #2
 8006636:	d914      	bls.n	8006662 <ADC_Disable+0xa6>
      {
        /* New check to avoid false timeout detection in case of preemption */
        if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
 8006638:	687b      	ldr	r3, [r7, #4]
 800663a:	681b      	ldr	r3, [r3, #0]
 800663c:	689b      	ldr	r3, [r3, #8]
 800663e:	f003 0301 	and.w	r3, r3, #1
 8006642:	2b00      	cmp	r3, #0
 8006644:	d00d      	beq.n	8006662 <ADC_Disable+0xa6>
        {
          /* Update ADC state machine to error */
          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8006646:	687b      	ldr	r3, [r7, #4]
 8006648:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800664a:	f043 0210 	orr.w	r2, r3, #16
 800664e:	687b      	ldr	r3, [r7, #4]
 8006650:	655a      	str	r2, [r3, #84]	@ 0x54

          /* Set ADC error code to ADC peripheral internal error */
          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8006652:	687b      	ldr	r3, [r7, #4]
 8006654:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8006656:	f043 0201 	orr.w	r2, r3, #1
 800665a:	687b      	ldr	r3, [r7, #4]
 800665c:	659a      	str	r2, [r3, #88]	@ 0x58

          return HAL_ERROR;
 800665e:	2301      	movs	r3, #1
 8006660:	e007      	b.n	8006672 <ADC_Disable+0xb6>
    while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
 8006662:	687b      	ldr	r3, [r7, #4]
 8006664:	681b      	ldr	r3, [r3, #0]
 8006666:	689b      	ldr	r3, [r3, #8]
 8006668:	f003 0301 	and.w	r3, r3, #1
 800666c:	2b00      	cmp	r3, #0
 800666e:	d1dc      	bne.n	800662a <ADC_Disable+0x6e>
      }
    }
  }

  /* Return HAL status */
  return HAL_OK;
 8006670:	2300      	movs	r3, #0
}
 8006672:	4618      	mov	r0, r3
 8006674:	3710      	adds	r7, #16
 8006676:	46bd      	mov	sp, r7
 8006678:	bd80      	pop	{r7, pc}

0800667a <ADC_DMAConvCplt>:
  * @brief  DMA transfer complete callback.
  * @param hdma pointer to DMA handle.
  * @retval None
  */
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
 800667a:	b580      	push	{r7, lr}
 800667c:	b084      	sub	sp, #16
 800667e:	af00      	add	r7, sp, #0
 8006680:	6078      	str	r0, [r7, #4]
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 8006682:	687b      	ldr	r3, [r7, #4]
 8006684:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8006686:	60fb      	str	r3, [r7, #12]

  /* Update state machine on conversion status if not in error state */
  if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
 8006688:	68fb      	ldr	r3, [r7, #12]
 800668a:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800668c:	f003 0350 	and.w	r3, r3, #80	@ 0x50
 8006690:	2b00      	cmp	r3, #0
 8006692:	d14b      	bne.n	800672c <ADC_DMAConvCplt+0xb2>
  {
    /* Set ADC state */
    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
 8006694:	68fb      	ldr	r3, [r7, #12]
 8006696:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006698:	f443 7200 	orr.w	r2, r3, #512	@ 0x200
 800669c:	68fb      	ldr	r3, [r7, #12]
 800669e:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Determine whether any further conversion upcoming on group regular     */
    /* by external trigger, continuous mode or scan sequence on going         */
    /* to disable interruption.                                               */
    /* Is it the end of the regular sequence ? */
    if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
 80066a0:	68fb      	ldr	r3, [r7, #12]
 80066a2:	681b      	ldr	r3, [r3, #0]
 80066a4:	681b      	ldr	r3, [r3, #0]
 80066a6:	f003 0308 	and.w	r3, r3, #8
 80066aa:	2b00      	cmp	r3, #0
 80066ac:	d021      	beq.n	80066f2 <ADC_DMAConvCplt+0x78>
    {
      /* Are conversions software-triggered ? */
      if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
 80066ae:	68fb      	ldr	r3, [r7, #12]
 80066b0:	681b      	ldr	r3, [r3, #0]
 80066b2:	4618      	mov	r0, r3
 80066b4:	f7fe ff9c 	bl	80055f0 <LL_ADC_REG_IsTriggerSourceSWStart>
 80066b8:	4603      	mov	r3, r0
 80066ba:	2b00      	cmp	r3, #0
 80066bc:	d032      	beq.n	8006724 <ADC_DMAConvCplt+0xaa>
      {
        /* Is CONT bit set ? */
        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
 80066be:	68fb      	ldr	r3, [r7, #12]
 80066c0:	681b      	ldr	r3, [r3, #0]
 80066c2:	68db      	ldr	r3, [r3, #12]
 80066c4:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 80066c8:	2b00      	cmp	r3, #0
 80066ca:	d12b      	bne.n	8006724 <ADC_DMAConvCplt+0xaa>
        {
          /* CONT bit is not set, no more conversions expected */
          CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
 80066cc:	68fb      	ldr	r3, [r7, #12]
 80066ce:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80066d0:	f423 7280 	bic.w	r2, r3, #256	@ 0x100
 80066d4:	68fb      	ldr	r3, [r7, #12]
 80066d6:	655a      	str	r2, [r3, #84]	@ 0x54
          if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
 80066d8:	68fb      	ldr	r3, [r7, #12]
 80066da:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80066dc:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
 80066e0:	2b00      	cmp	r3, #0
 80066e2:	d11f      	bne.n	8006724 <ADC_DMAConvCplt+0xaa>
          {
            SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 80066e4:	68fb      	ldr	r3, [r7, #12]
 80066e6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80066e8:	f043 0201 	orr.w	r2, r3, #1
 80066ec:	68fb      	ldr	r3, [r7, #12]
 80066ee:	655a      	str	r2, [r3, #84]	@ 0x54
 80066f0:	e018      	b.n	8006724 <ADC_DMAConvCplt+0xaa>
    }
    else
    {
      /* DMA End of Transfer interrupt was triggered but conversions sequence
         is not over. If DMACFG is set to 0, conversions are stopped. */
      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL)
 80066f2:	68fb      	ldr	r3, [r7, #12]
 80066f4:	681b      	ldr	r3, [r3, #0]
 80066f6:	68db      	ldr	r3, [r3, #12]
 80066f8:	f003 0303 	and.w	r3, r3, #3
 80066fc:	2b00      	cmp	r3, #0
 80066fe:	d111      	bne.n	8006724 <ADC_DMAConvCplt+0xaa>
      {
        /* DMACFG bit is not set, conversions are stopped. */
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
 8006700:	68fb      	ldr	r3, [r7, #12]
 8006702:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006704:	f423 7280 	bic.w	r2, r3, #256	@ 0x100
 8006708:	68fb      	ldr	r3, [r7, #12]
 800670a:	655a      	str	r2, [r3, #84]	@ 0x54
        if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
 800670c:	68fb      	ldr	r3, [r7, #12]
 800670e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006710:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
 8006714:	2b00      	cmp	r3, #0
 8006716:	d105      	bne.n	8006724 <ADC_DMAConvCplt+0xaa>
        {
          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 8006718:	68fb      	ldr	r3, [r7, #12]
 800671a:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800671c:	f043 0201 	orr.w	r2, r3, #1
 8006720:	68fb      	ldr	r3, [r7, #12]
 8006722:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
    hadc->ConvCpltCallback(hadc);
#else
    HAL_ADC_ConvCpltCallback(hadc);
 8006724:	68f8      	ldr	r0, [r7, #12]
 8006726:	f7fb f82f 	bl	8001788 <HAL_ADC_ConvCpltCallback>
    {
      /* Call ADC DMA error callback */
      hadc->DMA_Handle->XferErrorCallback(hdma);
    }
  }
}
 800672a:	e00e      	b.n	800674a <ADC_DMAConvCplt+0xd0>
    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
 800672c:	68fb      	ldr	r3, [r7, #12]
 800672e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006730:	f003 0310 	and.w	r3, r3, #16
 8006734:	2b00      	cmp	r3, #0
 8006736:	d003      	beq.n	8006740 <ADC_DMAConvCplt+0xc6>
      HAL_ADC_ErrorCallback(hadc);
 8006738:	68f8      	ldr	r0, [r7, #12]
 800673a:	f7ff fb4f 	bl	8005ddc <HAL_ADC_ErrorCallback>
}
 800673e:	e004      	b.n	800674a <ADC_DMAConvCplt+0xd0>
      hadc->DMA_Handle->XferErrorCallback(hdma);
 8006740:	68fb      	ldr	r3, [r7, #12]
 8006742:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8006744:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8006746:	6878      	ldr	r0, [r7, #4]
 8006748:	4798      	blx	r3
}
 800674a:	bf00      	nop
 800674c:	3710      	adds	r7, #16
 800674e:	46bd      	mov	sp, r7
 8006750:	bd80      	pop	{r7, pc}

08006752 <ADC_DMAHalfConvCplt>:
  * @brief  DMA half transfer complete callback.
  * @param hdma pointer to DMA handle.
  * @retval None
  */
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
 8006752:	b580      	push	{r7, lr}
 8006754:	b084      	sub	sp, #16
 8006756:	af00      	add	r7, sp, #0
 8006758:	6078      	str	r0, [r7, #4]
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 800675a:	687b      	ldr	r3, [r7, #4]
 800675c:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800675e:	60fb      	str	r3, [r7, #12]

  /* Half conversion callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  hadc->ConvHalfCpltCallback(hadc);
#else
  HAL_ADC_ConvHalfCpltCallback(hadc);
 8006760:	68f8      	ldr	r0, [r7, #12]
 8006762:	f7ff fb31 	bl	8005dc8 <HAL_ADC_ConvHalfCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
 8006766:	bf00      	nop
 8006768:	3710      	adds	r7, #16
 800676a:	46bd      	mov	sp, r7
 800676c:	bd80      	pop	{r7, pc}

0800676e <ADC_DMAError>:
  * @brief  DMA error callback.
  * @param hdma pointer to DMA handle.
  * @retval None
  */
void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
 800676e:	b580      	push	{r7, lr}
 8006770:	b084      	sub	sp, #16
 8006772:	af00      	add	r7, sp, #0
 8006774:	6078      	str	r0, [r7, #4]
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 8006776:	687b      	ldr	r3, [r7, #4]
 8006778:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800677a:	60fb      	str	r3, [r7, #12]

  /* Set ADC state */
  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
 800677c:	68fb      	ldr	r3, [r7, #12]
 800677e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006780:	f043 0240 	orr.w	r2, r3, #64	@ 0x40
 8006784:	68fb      	ldr	r3, [r7, #12]
 8006786:	655a      	str	r2, [r3, #84]	@ 0x54

  /* Set ADC error code to DMA error */
  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
 8006788:	68fb      	ldr	r3, [r7, #12]
 800678a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800678c:	f043 0204 	orr.w	r2, r3, #4
 8006790:	68fb      	ldr	r3, [r7, #12]
 8006792:	659a      	str	r2, [r3, #88]	@ 0x58

  /* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  hadc->ErrorCallback(hadc);
#else
  HAL_ADC_ErrorCallback(hadc);
 8006794:	68f8      	ldr	r0, [r7, #12]
 8006796:	f7ff fb21 	bl	8005ddc <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
 800679a:	bf00      	nop
 800679c:	3710      	adds	r7, #16
 800679e:	46bd      	mov	sp, r7
 80067a0:	bd80      	pop	{r7, pc}
	...

080067a4 <ADC_ConfigureBoostMode>:
  *         stopped.
  * @param  hadc ADC handle
  * @retval None.
  */
void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc)
{
 80067a4:	b580      	push	{r7, lr}
 80067a6:	b084      	sub	sp, #16
 80067a8:	af00      	add	r7, sp, #0
 80067aa:	6078      	str	r0, [r7, #4]
  uint32_t freq;
  if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
 80067ac:	687b      	ldr	r3, [r7, #4]
 80067ae:	681b      	ldr	r3, [r3, #0]
 80067b0:	4a7a      	ldr	r2, [pc, #488]	@ (800699c <ADC_ConfigureBoostMode+0x1f8>)
 80067b2:	4293      	cmp	r3, r2
 80067b4:	d004      	beq.n	80067c0 <ADC_ConfigureBoostMode+0x1c>
 80067b6:	687b      	ldr	r3, [r7, #4]
 80067b8:	681b      	ldr	r3, [r3, #0]
 80067ba:	4a79      	ldr	r2, [pc, #484]	@ (80069a0 <ADC_ConfigureBoostMode+0x1fc>)
 80067bc:	4293      	cmp	r3, r2
 80067be:	d109      	bne.n	80067d4 <ADC_ConfigureBoostMode+0x30>
 80067c0:	4b78      	ldr	r3, [pc, #480]	@ (80069a4 <ADC_ConfigureBoostMode+0x200>)
 80067c2:	689b      	ldr	r3, [r3, #8]
 80067c4:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 80067c8:	2b00      	cmp	r3, #0
 80067ca:	bf14      	ite	ne
 80067cc:	2301      	movne	r3, #1
 80067ce:	2300      	moveq	r3, #0
 80067d0:	b2db      	uxtb	r3, r3
 80067d2:	e008      	b.n	80067e6 <ADC_ConfigureBoostMode+0x42>
 80067d4:	4b74      	ldr	r3, [pc, #464]	@ (80069a8 <ADC_ConfigureBoostMode+0x204>)
 80067d6:	689b      	ldr	r3, [r3, #8]
 80067d8:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 80067dc:	2b00      	cmp	r3, #0
 80067de:	bf14      	ite	ne
 80067e0:	2301      	movne	r3, #1
 80067e2:	2300      	moveq	r3, #0
 80067e4:	b2db      	uxtb	r3, r3
 80067e6:	2b00      	cmp	r3, #0
 80067e8:	d01c      	beq.n	8006824 <ADC_ConfigureBoostMode+0x80>
  {
    freq = HAL_RCC_GetHCLKFreq();
 80067ea:	f005 fae9 	bl	800bdc0 <HAL_RCC_GetHCLKFreq>
 80067ee:	60f8      	str	r0, [r7, #12]
    switch (hadc->Init.ClockPrescaler)
 80067f0:	687b      	ldr	r3, [r7, #4]
 80067f2:	685b      	ldr	r3, [r3, #4]
 80067f4:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
 80067f8:	d010      	beq.n	800681c <ADC_ConfigureBoostMode+0x78>
 80067fa:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
 80067fe:	d873      	bhi.n	80068e8 <ADC_ConfigureBoostMode+0x144>
 8006800:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 8006804:	d002      	beq.n	800680c <ADC_ConfigureBoostMode+0x68>
 8006806:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800680a:	d16d      	bne.n	80068e8 <ADC_ConfigureBoostMode+0x144>
    {
      case ADC_CLOCK_SYNC_PCLK_DIV1:
      case ADC_CLOCK_SYNC_PCLK_DIV2:
        freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos);
 800680c:	687b      	ldr	r3, [r7, #4]
 800680e:	685b      	ldr	r3, [r3, #4]
 8006810:	0c1b      	lsrs	r3, r3, #16
 8006812:	68fa      	ldr	r2, [r7, #12]
 8006814:	fbb2 f3f3 	udiv	r3, r2, r3
 8006818:	60fb      	str	r3, [r7, #12]
        break;
 800681a:	e068      	b.n	80068ee <ADC_ConfigureBoostMode+0x14a>
      case ADC_CLOCK_SYNC_PCLK_DIV4:
        freq /= 4UL;
 800681c:	68fb      	ldr	r3, [r7, #12]
 800681e:	089b      	lsrs	r3, r3, #2
 8006820:	60fb      	str	r3, [r7, #12]
        break;
 8006822:	e064      	b.n	80068ee <ADC_ConfigureBoostMode+0x14a>
        break;
    }
  }
  else
  {
    freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
 8006824:	f44f 2000 	mov.w	r0, #524288	@ 0x80000
 8006828:	f04f 0100 	mov.w	r1, #0
 800682c:	f006 fd54 	bl	800d2d8 <HAL_RCCEx_GetPeriphCLKFreq>
 8006830:	60f8      	str	r0, [r7, #12]
    switch (hadc->Init.ClockPrescaler)
 8006832:	687b      	ldr	r3, [r7, #4]
 8006834:	685b      	ldr	r3, [r3, #4]
 8006836:	f5b3 1f30 	cmp.w	r3, #2883584	@ 0x2c0000
 800683a:	d051      	beq.n	80068e0 <ADC_ConfigureBoostMode+0x13c>
 800683c:	f5b3 1f30 	cmp.w	r3, #2883584	@ 0x2c0000
 8006840:	d854      	bhi.n	80068ec <ADC_ConfigureBoostMode+0x148>
 8006842:	f5b3 1f20 	cmp.w	r3, #2621440	@ 0x280000
 8006846:	d047      	beq.n	80068d8 <ADC_ConfigureBoostMode+0x134>
 8006848:	f5b3 1f20 	cmp.w	r3, #2621440	@ 0x280000
 800684c:	d84e      	bhi.n	80068ec <ADC_ConfigureBoostMode+0x148>
 800684e:	f5b3 1f10 	cmp.w	r3, #2359296	@ 0x240000
 8006852:	d03d      	beq.n	80068d0 <ADC_ConfigureBoostMode+0x12c>
 8006854:	f5b3 1f10 	cmp.w	r3, #2359296	@ 0x240000
 8006858:	d848      	bhi.n	80068ec <ADC_ConfigureBoostMode+0x148>
 800685a:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 800685e:	d033      	beq.n	80068c8 <ADC_ConfigureBoostMode+0x124>
 8006860:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 8006864:	d842      	bhi.n	80068ec <ADC_ConfigureBoostMode+0x148>
 8006866:	f5b3 1fe0 	cmp.w	r3, #1835008	@ 0x1c0000
 800686a:	d029      	beq.n	80068c0 <ADC_ConfigureBoostMode+0x11c>
 800686c:	f5b3 1fe0 	cmp.w	r3, #1835008	@ 0x1c0000
 8006870:	d83c      	bhi.n	80068ec <ADC_ConfigureBoostMode+0x148>
 8006872:	f5b3 1fc0 	cmp.w	r3, #1572864	@ 0x180000
 8006876:	d01a      	beq.n	80068ae <ADC_ConfigureBoostMode+0x10a>
 8006878:	f5b3 1fc0 	cmp.w	r3, #1572864	@ 0x180000
 800687c:	d836      	bhi.n	80068ec <ADC_ConfigureBoostMode+0x148>
 800687e:	f5b3 1fa0 	cmp.w	r3, #1310720	@ 0x140000
 8006882:	d014      	beq.n	80068ae <ADC_ConfigureBoostMode+0x10a>
 8006884:	f5b3 1fa0 	cmp.w	r3, #1310720	@ 0x140000
 8006888:	d830      	bhi.n	80068ec <ADC_ConfigureBoostMode+0x148>
 800688a:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 800688e:	d00e      	beq.n	80068ae <ADC_ConfigureBoostMode+0x10a>
 8006890:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 8006894:	d82a      	bhi.n	80068ec <ADC_ConfigureBoostMode+0x148>
 8006896:	f5b3 2f40 	cmp.w	r3, #786432	@ 0xc0000
 800689a:	d008      	beq.n	80068ae <ADC_ConfigureBoostMode+0x10a>
 800689c:	f5b3 2f40 	cmp.w	r3, #786432	@ 0xc0000
 80068a0:	d824      	bhi.n	80068ec <ADC_ConfigureBoostMode+0x148>
 80068a2:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
 80068a6:	d002      	beq.n	80068ae <ADC_ConfigureBoostMode+0x10a>
 80068a8:	f5b3 2f00 	cmp.w	r3, #524288	@ 0x80000
 80068ac:	d11e      	bne.n	80068ec <ADC_ConfigureBoostMode+0x148>
      case ADC_CLOCK_ASYNC_DIV4:
      case ADC_CLOCK_ASYNC_DIV6:
      case ADC_CLOCK_ASYNC_DIV8:
      case ADC_CLOCK_ASYNC_DIV10:
      case ADC_CLOCK_ASYNC_DIV12:
        freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL);
 80068ae:	687b      	ldr	r3, [r7, #4]
 80068b0:	685b      	ldr	r3, [r3, #4]
 80068b2:	0c9b      	lsrs	r3, r3, #18
 80068b4:	005b      	lsls	r3, r3, #1
 80068b6:	68fa      	ldr	r2, [r7, #12]
 80068b8:	fbb2 f3f3 	udiv	r3, r2, r3
 80068bc:	60fb      	str	r3, [r7, #12]
        break;
 80068be:	e016      	b.n	80068ee <ADC_ConfigureBoostMode+0x14a>
      case ADC_CLOCK_ASYNC_DIV16:
        freq /= 16UL;
 80068c0:	68fb      	ldr	r3, [r7, #12]
 80068c2:	091b      	lsrs	r3, r3, #4
 80068c4:	60fb      	str	r3, [r7, #12]
        break;
 80068c6:	e012      	b.n	80068ee <ADC_ConfigureBoostMode+0x14a>
      case ADC_CLOCK_ASYNC_DIV32:
        freq /= 32UL;
 80068c8:	68fb      	ldr	r3, [r7, #12]
 80068ca:	095b      	lsrs	r3, r3, #5
 80068cc:	60fb      	str	r3, [r7, #12]
        break;
 80068ce:	e00e      	b.n	80068ee <ADC_ConfigureBoostMode+0x14a>
      case ADC_CLOCK_ASYNC_DIV64:
        freq /= 64UL;
 80068d0:	68fb      	ldr	r3, [r7, #12]
 80068d2:	099b      	lsrs	r3, r3, #6
 80068d4:	60fb      	str	r3, [r7, #12]
        break;
 80068d6:	e00a      	b.n	80068ee <ADC_ConfigureBoostMode+0x14a>
      case ADC_CLOCK_ASYNC_DIV128:
        freq /= 128UL;
 80068d8:	68fb      	ldr	r3, [r7, #12]
 80068da:	09db      	lsrs	r3, r3, #7
 80068dc:	60fb      	str	r3, [r7, #12]
        break;
 80068de:	e006      	b.n	80068ee <ADC_ConfigureBoostMode+0x14a>
      case ADC_CLOCK_ASYNC_DIV256:
        freq /= 256UL;
 80068e0:	68fb      	ldr	r3, [r7, #12]
 80068e2:	0a1b      	lsrs	r3, r3, #8
 80068e4:	60fb      	str	r3, [r7, #12]
        break;
 80068e6:	e002      	b.n	80068ee <ADC_ConfigureBoostMode+0x14a>
        break;
 80068e8:	bf00      	nop
 80068ea:	e000      	b.n	80068ee <ADC_ConfigureBoostMode+0x14a>
      default:
        break;
 80068ec:	bf00      	nop
  else /* if(freq > 25000000UL) */
  {
    MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
  }
#else
  if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
 80068ee:	f7fe fdb1 	bl	8005454 <HAL_GetREVID>
 80068f2:	4603      	mov	r3, r0
 80068f4:	f241 0203 	movw	r2, #4099	@ 0x1003
 80068f8:	4293      	cmp	r3, r2
 80068fa:	d815      	bhi.n	8006928 <ADC_ConfigureBoostMode+0x184>
  {
    if (freq > 20000000UL)
 80068fc:	68fb      	ldr	r3, [r7, #12]
 80068fe:	4a2b      	ldr	r2, [pc, #172]	@ (80069ac <ADC_ConfigureBoostMode+0x208>)
 8006900:	4293      	cmp	r3, r2
 8006902:	d908      	bls.n	8006916 <ADC_ConfigureBoostMode+0x172>
    {
      SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
 8006904:	687b      	ldr	r3, [r7, #4]
 8006906:	681b      	ldr	r3, [r3, #0]
 8006908:	689a      	ldr	r2, [r3, #8]
 800690a:	687b      	ldr	r3, [r7, #4]
 800690c:	681b      	ldr	r3, [r3, #0]
 800690e:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
 8006912:	609a      	str	r2, [r3, #8]
    {
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
    }
  }
#endif /* ADC_VER_V5_3 */
}
 8006914:	e03e      	b.n	8006994 <ADC_ConfigureBoostMode+0x1f0>
      CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
 8006916:	687b      	ldr	r3, [r7, #4]
 8006918:	681b      	ldr	r3, [r3, #0]
 800691a:	689a      	ldr	r2, [r3, #8]
 800691c:	687b      	ldr	r3, [r7, #4]
 800691e:	681b      	ldr	r3, [r3, #0]
 8006920:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
 8006924:	609a      	str	r2, [r3, #8]
}
 8006926:	e035      	b.n	8006994 <ADC_ConfigureBoostMode+0x1f0>
    freq /= 2U; /* divider by 2 for Rev.V */
 8006928:	68fb      	ldr	r3, [r7, #12]
 800692a:	085b      	lsrs	r3, r3, #1
 800692c:	60fb      	str	r3, [r7, #12]
    if (freq <= 6250000UL)
 800692e:	68fb      	ldr	r3, [r7, #12]
 8006930:	4a1f      	ldr	r2, [pc, #124]	@ (80069b0 <ADC_ConfigureBoostMode+0x20c>)
 8006932:	4293      	cmp	r3, r2
 8006934:	d808      	bhi.n	8006948 <ADC_ConfigureBoostMode+0x1a4>
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
 8006936:	687b      	ldr	r3, [r7, #4]
 8006938:	681b      	ldr	r3, [r3, #0]
 800693a:	689a      	ldr	r2, [r3, #8]
 800693c:	687b      	ldr	r3, [r7, #4]
 800693e:	681b      	ldr	r3, [r3, #0]
 8006940:	f422 7240 	bic.w	r2, r2, #768	@ 0x300
 8006944:	609a      	str	r2, [r3, #8]
}
 8006946:	e025      	b.n	8006994 <ADC_ConfigureBoostMode+0x1f0>
    else if (freq <= 12500000UL)
 8006948:	68fb      	ldr	r3, [r7, #12]
 800694a:	4a1a      	ldr	r2, [pc, #104]	@ (80069b4 <ADC_ConfigureBoostMode+0x210>)
 800694c:	4293      	cmp	r3, r2
 800694e:	d80a      	bhi.n	8006966 <ADC_ConfigureBoostMode+0x1c2>
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
 8006950:	687b      	ldr	r3, [r7, #4]
 8006952:	681b      	ldr	r3, [r3, #0]
 8006954:	689b      	ldr	r3, [r3, #8]
 8006956:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
 800695a:	687b      	ldr	r3, [r7, #4]
 800695c:	681b      	ldr	r3, [r3, #0]
 800695e:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
 8006962:	609a      	str	r2, [r3, #8]
}
 8006964:	e016      	b.n	8006994 <ADC_ConfigureBoostMode+0x1f0>
    else if (freq <= 25000000UL)
 8006966:	68fb      	ldr	r3, [r7, #12]
 8006968:	4a13      	ldr	r2, [pc, #76]	@ (80069b8 <ADC_ConfigureBoostMode+0x214>)
 800696a:	4293      	cmp	r3, r2
 800696c:	d80a      	bhi.n	8006984 <ADC_ConfigureBoostMode+0x1e0>
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
 800696e:	687b      	ldr	r3, [r7, #4]
 8006970:	681b      	ldr	r3, [r3, #0]
 8006972:	689b      	ldr	r3, [r3, #8]
 8006974:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
 8006978:	687b      	ldr	r3, [r7, #4]
 800697a:	681b      	ldr	r3, [r3, #0]
 800697c:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
 8006980:	609a      	str	r2, [r3, #8]
}
 8006982:	e007      	b.n	8006994 <ADC_ConfigureBoostMode+0x1f0>
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
 8006984:	687b      	ldr	r3, [r7, #4]
 8006986:	681b      	ldr	r3, [r3, #0]
 8006988:	689a      	ldr	r2, [r3, #8]
 800698a:	687b      	ldr	r3, [r7, #4]
 800698c:	681b      	ldr	r3, [r3, #0]
 800698e:	f442 7240 	orr.w	r2, r2, #768	@ 0x300
 8006992:	609a      	str	r2, [r3, #8]
}
 8006994:	bf00      	nop
 8006996:	3710      	adds	r7, #16
 8006998:	46bd      	mov	sp, r7
 800699a:	bd80      	pop	{r7, pc}
 800699c:	40022000 	.word	0x40022000
 80069a0:	40022100 	.word	0x40022100
 80069a4:	40022300 	.word	0x40022300
 80069a8:	58026300 	.word	0x58026300
 80069ac:	01312d00 	.word	0x01312d00
 80069b0:	005f5e10 	.word	0x005f5e10
 80069b4:	00bebc20 	.word	0x00bebc20
 80069b8:	017d7840 	.word	0x017d7840

080069bc <LL_ADC_IsEnabled>:
{
 80069bc:	b480      	push	{r7}
 80069be:	b083      	sub	sp, #12
 80069c0:	af00      	add	r7, sp, #0
 80069c2:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
 80069c4:	687b      	ldr	r3, [r7, #4]
 80069c6:	689b      	ldr	r3, [r3, #8]
 80069c8:	f003 0301 	and.w	r3, r3, #1
 80069cc:	2b01      	cmp	r3, #1
 80069ce:	d101      	bne.n	80069d4 <LL_ADC_IsEnabled+0x18>
 80069d0:	2301      	movs	r3, #1
 80069d2:	e000      	b.n	80069d6 <LL_ADC_IsEnabled+0x1a>
 80069d4:	2300      	movs	r3, #0
}
 80069d6:	4618      	mov	r0, r3
 80069d8:	370c      	adds	r7, #12
 80069da:	46bd      	mov	sp, r7
 80069dc:	f85d 7b04 	ldr.w	r7, [sp], #4
 80069e0:	4770      	bx	lr
	...

080069e4 <LL_ADC_StartCalibration>:
{
 80069e4:	b480      	push	{r7}
 80069e6:	b085      	sub	sp, #20
 80069e8:	af00      	add	r7, sp, #0
 80069ea:	60f8      	str	r0, [r7, #12]
 80069ec:	60b9      	str	r1, [r7, #8]
 80069ee:	607a      	str	r2, [r7, #4]
  MODIFY_REG(ADCx->CR,
 80069f0:	68fb      	ldr	r3, [r7, #12]
 80069f2:	689a      	ldr	r2, [r3, #8]
 80069f4:	4b09      	ldr	r3, [pc, #36]	@ (8006a1c <LL_ADC_StartCalibration+0x38>)
 80069f6:	4013      	ands	r3, r2
 80069f8:	68ba      	ldr	r2, [r7, #8]
 80069fa:	f402 3180 	and.w	r1, r2, #65536	@ 0x10000
 80069fe:	687a      	ldr	r2, [r7, #4]
 8006a00:	f002 4280 	and.w	r2, r2, #1073741824	@ 0x40000000
 8006a04:	430a      	orrs	r2, r1
 8006a06:	4313      	orrs	r3, r2
 8006a08:	f043 4200 	orr.w	r2, r3, #2147483648	@ 0x80000000
 8006a0c:	68fb      	ldr	r3, [r7, #12]
 8006a0e:	609a      	str	r2, [r3, #8]
}
 8006a10:	bf00      	nop
 8006a12:	3714      	adds	r7, #20
 8006a14:	46bd      	mov	sp, r7
 8006a16:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006a1a:	4770      	bx	lr
 8006a1c:	3ffeffc0 	.word	0x3ffeffc0

08006a20 <LL_ADC_IsCalibrationOnGoing>:
{
 8006a20:	b480      	push	{r7}
 8006a22:	b083      	sub	sp, #12
 8006a24:	af00      	add	r7, sp, #0
 8006a26:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
 8006a28:	687b      	ldr	r3, [r7, #4]
 8006a2a:	689b      	ldr	r3, [r3, #8]
 8006a2c:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
 8006a30:	f1b3 4f00 	cmp.w	r3, #2147483648	@ 0x80000000
 8006a34:	d101      	bne.n	8006a3a <LL_ADC_IsCalibrationOnGoing+0x1a>
 8006a36:	2301      	movs	r3, #1
 8006a38:	e000      	b.n	8006a3c <LL_ADC_IsCalibrationOnGoing+0x1c>
 8006a3a:	2300      	movs	r3, #0
}
 8006a3c:	4618      	mov	r0, r3
 8006a3e:	370c      	adds	r7, #12
 8006a40:	46bd      	mov	sp, r7
 8006a42:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006a46:	4770      	bx	lr

08006a48 <LL_ADC_REG_IsConversionOngoing>:
{
 8006a48:	b480      	push	{r7}
 8006a4a:	b083      	sub	sp, #12
 8006a4c:	af00      	add	r7, sp, #0
 8006a4e:	6078      	str	r0, [r7, #4]
  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
 8006a50:	687b      	ldr	r3, [r7, #4]
 8006a52:	689b      	ldr	r3, [r3, #8]
 8006a54:	f003 0304 	and.w	r3, r3, #4
 8006a58:	2b04      	cmp	r3, #4
 8006a5a:	d101      	bne.n	8006a60 <LL_ADC_REG_IsConversionOngoing+0x18>
 8006a5c:	2301      	movs	r3, #1
 8006a5e:	e000      	b.n	8006a62 <LL_ADC_REG_IsConversionOngoing+0x1a>
 8006a60:	2300      	movs	r3, #0
}
 8006a62:	4618      	mov	r0, r3
 8006a64:	370c      	adds	r7, #12
 8006a66:	46bd      	mov	sp, r7
 8006a68:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006a6c:	4770      	bx	lr
	...

08006a70 <HAL_ADCEx_Calibration_Start>:
  *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
  *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
{
 8006a70:	b580      	push	{r7, lr}
 8006a72:	b086      	sub	sp, #24
 8006a74:	af00      	add	r7, sp, #0
 8006a76:	60f8      	str	r0, [r7, #12]
 8006a78:	60b9      	str	r1, [r7, #8]
 8006a7a:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status;
  __IO uint32_t wait_loop_index = 0UL;
 8006a7c:	2300      	movs	r3, #0
 8006a7e:	613b      	str	r3, [r7, #16]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));

  /* Process locked */
  __HAL_LOCK(hadc);
 8006a80:	68fb      	ldr	r3, [r7, #12]
 8006a82:	f893 3050 	ldrb.w	r3, [r3, #80]	@ 0x50
 8006a86:	2b01      	cmp	r3, #1
 8006a88:	d101      	bne.n	8006a8e <HAL_ADCEx_Calibration_Start+0x1e>
 8006a8a:	2302      	movs	r3, #2
 8006a8c:	e04c      	b.n	8006b28 <HAL_ADCEx_Calibration_Start+0xb8>
 8006a8e:	68fb      	ldr	r3, [r7, #12]
 8006a90:	2201      	movs	r2, #1
 8006a92:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

  /* Calibration prerequisite: ADC must be disabled. */

  /* Disable the ADC (if not already disabled) */
  tmp_hal_status = ADC_Disable(hadc);
 8006a96:	68f8      	ldr	r0, [r7, #12]
 8006a98:	f7ff fd90 	bl	80065bc <ADC_Disable>
 8006a9c:	4603      	mov	r3, r0
 8006a9e:	75fb      	strb	r3, [r7, #23]

  /* Check if ADC is effectively disabled */
  if (tmp_hal_status == HAL_OK)
 8006aa0:	7dfb      	ldrb	r3, [r7, #23]
 8006aa2:	2b00      	cmp	r3, #0
 8006aa4:	d135      	bne.n	8006b12 <HAL_ADCEx_Calibration_Start+0xa2>
  {
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 8006aa6:	68fb      	ldr	r3, [r7, #12]
 8006aa8:	6d5a      	ldr	r2, [r3, #84]	@ 0x54
 8006aaa:	4b21      	ldr	r3, [pc, #132]	@ (8006b30 <HAL_ADCEx_Calibration_Start+0xc0>)
 8006aac:	4013      	ands	r3, r2
 8006aae:	f043 0202 	orr.w	r2, r3, #2
 8006ab2:	68fb      	ldr	r3, [r7, #12]
 8006ab4:	655a      	str	r2, [r3, #84]	@ 0x54
                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
                      HAL_ADC_STATE_BUSY_INTERNAL);

    /* Start ADC calibration in mode single-ended or differential */
    LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff);
 8006ab6:	68fb      	ldr	r3, [r7, #12]
 8006ab8:	681b      	ldr	r3, [r3, #0]
 8006aba:	687a      	ldr	r2, [r7, #4]
 8006abc:	68b9      	ldr	r1, [r7, #8]
 8006abe:	4618      	mov	r0, r3
 8006ac0:	f7ff ff90 	bl	80069e4 <LL_ADC_StartCalibration>

    /* Wait for calibration completion */
    while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
 8006ac4:	e014      	b.n	8006af0 <HAL_ADCEx_Calibration_Start+0x80>
    {
      wait_loop_index++;
 8006ac6:	693b      	ldr	r3, [r7, #16]
 8006ac8:	3301      	adds	r3, #1
 8006aca:	613b      	str	r3, [r7, #16]
      if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
 8006acc:	693b      	ldr	r3, [r7, #16]
 8006ace:	4a19      	ldr	r2, [pc, #100]	@ (8006b34 <HAL_ADCEx_Calibration_Start+0xc4>)
 8006ad0:	4293      	cmp	r3, r2
 8006ad2:	d30d      	bcc.n	8006af0 <HAL_ADCEx_Calibration_Start+0x80>
      {
        /* Update ADC state machine to error */
        ADC_STATE_CLR_SET(hadc->State,
 8006ad4:	68fb      	ldr	r3, [r7, #12]
 8006ad6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006ad8:	f023 0312 	bic.w	r3, r3, #18
 8006adc:	f043 0210 	orr.w	r2, r3, #16
 8006ae0:	68fb      	ldr	r3, [r7, #12]
 8006ae2:	655a      	str	r2, [r3, #84]	@ 0x54
                          HAL_ADC_STATE_BUSY_INTERNAL,
                          HAL_ADC_STATE_ERROR_INTERNAL);

        /* Process unlocked */
        __HAL_UNLOCK(hadc);
 8006ae4:	68fb      	ldr	r3, [r7, #12]
 8006ae6:	2200      	movs	r2, #0
 8006ae8:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

        return HAL_ERROR;
 8006aec:	2301      	movs	r3, #1
 8006aee:	e01b      	b.n	8006b28 <HAL_ADCEx_Calibration_Start+0xb8>
    while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
 8006af0:	68fb      	ldr	r3, [r7, #12]
 8006af2:	681b      	ldr	r3, [r3, #0]
 8006af4:	4618      	mov	r0, r3
 8006af6:	f7ff ff93 	bl	8006a20 <LL_ADC_IsCalibrationOnGoing>
 8006afa:	4603      	mov	r3, r0
 8006afc:	2b00      	cmp	r3, #0
 8006afe:	d1e2      	bne.n	8006ac6 <HAL_ADCEx_Calibration_Start+0x56>
      }
    }

    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 8006b00:	68fb      	ldr	r3, [r7, #12]
 8006b02:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006b04:	f023 0303 	bic.w	r3, r3, #3
 8006b08:	f043 0201 	orr.w	r2, r3, #1
 8006b0c:	68fb      	ldr	r3, [r7, #12]
 8006b0e:	655a      	str	r2, [r3, #84]	@ 0x54
 8006b10:	e005      	b.n	8006b1e <HAL_ADCEx_Calibration_Start+0xae>
                      HAL_ADC_STATE_BUSY_INTERNAL,
                      HAL_ADC_STATE_READY);
  }
  else
  {
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8006b12:	68fb      	ldr	r3, [r7, #12]
 8006b14:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006b16:	f043 0210 	orr.w	r2, r3, #16
 8006b1a:	68fb      	ldr	r3, [r7, #12]
 8006b1c:	655a      	str	r2, [r3, #84]	@ 0x54
    /* Note: No need to update variable "tmp_hal_status" here: already set    */
    /*       to state "HAL_ERROR" by function disabling the ADC.              */
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 8006b1e:	68fb      	ldr	r3, [r7, #12]
 8006b20:	2200      	movs	r2, #0
 8006b22:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

  /* Return function status */
  return tmp_hal_status;
 8006b26:	7dfb      	ldrb	r3, [r7, #23]
}
 8006b28:	4618      	mov	r0, r3
 8006b2a:	3718      	adds	r7, #24
 8006b2c:	46bd      	mov	sp, r7
 8006b2e:	bd80      	pop	{r7, pc}
 8006b30:	ffffeefd 	.word	0xffffeefd
 8006b34:	25c3f800 	.word	0x25c3f800

08006b38 <HAL_ADCEx_MultiModeConfigChannel>:
  * @param hadc Master ADC handle
  * @param multimode Structure of ADC multimode configuration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
{
 8006b38:	b590      	push	{r4, r7, lr}
 8006b3a:	b09f      	sub	sp, #124	@ 0x7c
 8006b3c:	af00      	add	r7, sp, #0
 8006b3e:	6078      	str	r0, [r7, #4]
 8006b40:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8006b42:	2300      	movs	r3, #0
 8006b44:	f887 3077 	strb.w	r3, [r7, #119]	@ 0x77
    assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData));
    assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
  }

  /* Process locked */
  __HAL_LOCK(hadc);
 8006b48:	687b      	ldr	r3, [r7, #4]
 8006b4a:	f893 3050 	ldrb.w	r3, [r3, #80]	@ 0x50
 8006b4e:	2b01      	cmp	r3, #1
 8006b50:	d101      	bne.n	8006b56 <HAL_ADCEx_MultiModeConfigChannel+0x1e>
 8006b52:	2302      	movs	r3, #2
 8006b54:	e0be      	b.n	8006cd4 <HAL_ADCEx_MultiModeConfigChannel+0x19c>
 8006b56:	687b      	ldr	r3, [r7, #4]
 8006b58:	2201      	movs	r2, #1
 8006b5a:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

  tmphadcSlave.State = HAL_ADC_STATE_RESET;
 8006b5e:	2300      	movs	r3, #0
 8006b60:	65fb      	str	r3, [r7, #92]	@ 0x5c
  tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
 8006b62:	2300      	movs	r3, #0
 8006b64:	663b      	str	r3, [r7, #96]	@ 0x60

  ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
 8006b66:	687b      	ldr	r3, [r7, #4]
 8006b68:	681b      	ldr	r3, [r3, #0]
 8006b6a:	4a5c      	ldr	r2, [pc, #368]	@ (8006cdc <HAL_ADCEx_MultiModeConfigChannel+0x1a4>)
 8006b6c:	4293      	cmp	r3, r2
 8006b6e:	d102      	bne.n	8006b76 <HAL_ADCEx_MultiModeConfigChannel+0x3e>
 8006b70:	4b5b      	ldr	r3, [pc, #364]	@ (8006ce0 <HAL_ADCEx_MultiModeConfigChannel+0x1a8>)
 8006b72:	60bb      	str	r3, [r7, #8]
 8006b74:	e001      	b.n	8006b7a <HAL_ADCEx_MultiModeConfigChannel+0x42>
 8006b76:	2300      	movs	r3, #0
 8006b78:	60bb      	str	r3, [r7, #8]

  if (tmphadcSlave.Instance == NULL)
 8006b7a:	68bb      	ldr	r3, [r7, #8]
 8006b7c:	2b00      	cmp	r3, #0
 8006b7e:	d10b      	bne.n	8006b98 <HAL_ADCEx_MultiModeConfigChannel+0x60>
  {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 8006b80:	687b      	ldr	r3, [r7, #4]
 8006b82:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006b84:	f043 0220 	orr.w	r2, r3, #32
 8006b88:	687b      	ldr	r3, [r7, #4]
 8006b8a:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Process unlocked */
    __HAL_UNLOCK(hadc);
 8006b8c:	687b      	ldr	r3, [r7, #4]
 8006b8e:	2200      	movs	r2, #0
 8006b90:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

    return HAL_ERROR;
 8006b94:	2301      	movs	r3, #1
 8006b96:	e09d      	b.n	8006cd4 <HAL_ADCEx_MultiModeConfigChannel+0x19c>

  /* Parameters update conditioned to ADC state:                              */
  /* Parameters that can be updated when ADC is disabled or enabled without   */
  /* conversion on going on regular group:                                    */
  /*  - Multimode DATA Format configuration                                   */
  tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
 8006b98:	68bb      	ldr	r3, [r7, #8]
 8006b9a:	4618      	mov	r0, r3
 8006b9c:	f7ff ff54 	bl	8006a48 <LL_ADC_REG_IsConversionOngoing>
 8006ba0:	6738      	str	r0, [r7, #112]	@ 0x70
  if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
 8006ba2:	687b      	ldr	r3, [r7, #4]
 8006ba4:	681b      	ldr	r3, [r3, #0]
 8006ba6:	4618      	mov	r0, r3
 8006ba8:	f7ff ff4e 	bl	8006a48 <LL_ADC_REG_IsConversionOngoing>
 8006bac:	4603      	mov	r3, r0
 8006bae:	2b00      	cmp	r3, #0
 8006bb0:	d17f      	bne.n	8006cb2 <HAL_ADCEx_MultiModeConfigChannel+0x17a>
      && (tmphadcSlave_conversion_on_going == 0UL))
 8006bb2:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
 8006bb4:	2b00      	cmp	r3, #0
 8006bb6:	d17c      	bne.n	8006cb2 <HAL_ADCEx_MultiModeConfigChannel+0x17a>
  {
    /* Pointer to the common control register */
    tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
 8006bb8:	687b      	ldr	r3, [r7, #4]
 8006bba:	681b      	ldr	r3, [r3, #0]
 8006bbc:	4a47      	ldr	r2, [pc, #284]	@ (8006cdc <HAL_ADCEx_MultiModeConfigChannel+0x1a4>)
 8006bbe:	4293      	cmp	r3, r2
 8006bc0:	d004      	beq.n	8006bcc <HAL_ADCEx_MultiModeConfigChannel+0x94>
 8006bc2:	687b      	ldr	r3, [r7, #4]
 8006bc4:	681b      	ldr	r3, [r3, #0]
 8006bc6:	4a46      	ldr	r2, [pc, #280]	@ (8006ce0 <HAL_ADCEx_MultiModeConfigChannel+0x1a8>)
 8006bc8:	4293      	cmp	r3, r2
 8006bca:	d101      	bne.n	8006bd0 <HAL_ADCEx_MultiModeConfigChannel+0x98>
 8006bcc:	4b45      	ldr	r3, [pc, #276]	@ (8006ce4 <HAL_ADCEx_MultiModeConfigChannel+0x1ac>)
 8006bce:	e000      	b.n	8006bd2 <HAL_ADCEx_MultiModeConfigChannel+0x9a>
 8006bd0:	4b45      	ldr	r3, [pc, #276]	@ (8006ce8 <HAL_ADCEx_MultiModeConfigChannel+0x1b0>)
 8006bd2:	66fb      	str	r3, [r7, #108]	@ 0x6c

    /* If multimode is selected, configure all multimode parameters.          */
    /* Otherwise, reset multimode parameters (can be used in case of          */
    /* transition from multimode to independent mode).                        */
    if (multimode->Mode != ADC_MODE_INDEPENDENT)
 8006bd4:	683b      	ldr	r3, [r7, #0]
 8006bd6:	681b      	ldr	r3, [r3, #0]
 8006bd8:	2b00      	cmp	r3, #0
 8006bda:	d039      	beq.n	8006c50 <HAL_ADCEx_MultiModeConfigChannel+0x118>
    {
      MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
 8006bdc:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8006bde:	689b      	ldr	r3, [r3, #8]
 8006be0:	f423 4240 	bic.w	r2, r3, #49152	@ 0xc000
 8006be4:	683b      	ldr	r3, [r7, #0]
 8006be6:	685b      	ldr	r3, [r3, #4]
 8006be8:	431a      	orrs	r2, r3
 8006bea:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8006bec:	609a      	str	r2, [r3, #8]
      /*      from 1 to 8 clock cycles for 12 bits                              */
      /*      from 1 to 6 clock cycles for 10 and 8 bits                        */
      /*    If a higher delay is selected, it will be clipped to maximum delay  */
      /*    range                                                               */

      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
 8006bee:	687b      	ldr	r3, [r7, #4]
 8006bf0:	681b      	ldr	r3, [r3, #0]
 8006bf2:	4a3a      	ldr	r2, [pc, #232]	@ (8006cdc <HAL_ADCEx_MultiModeConfigChannel+0x1a4>)
 8006bf4:	4293      	cmp	r3, r2
 8006bf6:	d004      	beq.n	8006c02 <HAL_ADCEx_MultiModeConfigChannel+0xca>
 8006bf8:	687b      	ldr	r3, [r7, #4]
 8006bfa:	681b      	ldr	r3, [r3, #0]
 8006bfc:	4a38      	ldr	r2, [pc, #224]	@ (8006ce0 <HAL_ADCEx_MultiModeConfigChannel+0x1a8>)
 8006bfe:	4293      	cmp	r3, r2
 8006c00:	d10e      	bne.n	8006c20 <HAL_ADCEx_MultiModeConfigChannel+0xe8>
 8006c02:	4836      	ldr	r0, [pc, #216]	@ (8006cdc <HAL_ADCEx_MultiModeConfigChannel+0x1a4>)
 8006c04:	f7ff feda 	bl	80069bc <LL_ADC_IsEnabled>
 8006c08:	4604      	mov	r4, r0
 8006c0a:	4835      	ldr	r0, [pc, #212]	@ (8006ce0 <HAL_ADCEx_MultiModeConfigChannel+0x1a8>)
 8006c0c:	f7ff fed6 	bl	80069bc <LL_ADC_IsEnabled>
 8006c10:	4603      	mov	r3, r0
 8006c12:	4323      	orrs	r3, r4
 8006c14:	2b00      	cmp	r3, #0
 8006c16:	bf0c      	ite	eq
 8006c18:	2301      	moveq	r3, #1
 8006c1a:	2300      	movne	r3, #0
 8006c1c:	b2db      	uxtb	r3, r3
 8006c1e:	e008      	b.n	8006c32 <HAL_ADCEx_MultiModeConfigChannel+0xfa>
 8006c20:	4832      	ldr	r0, [pc, #200]	@ (8006cec <HAL_ADCEx_MultiModeConfigChannel+0x1b4>)
 8006c22:	f7ff fecb 	bl	80069bc <LL_ADC_IsEnabled>
 8006c26:	4603      	mov	r3, r0
 8006c28:	2b00      	cmp	r3, #0
 8006c2a:	bf0c      	ite	eq
 8006c2c:	2301      	moveq	r3, #1
 8006c2e:	2300      	movne	r3, #0
 8006c30:	b2db      	uxtb	r3, r3
 8006c32:	2b00      	cmp	r3, #0
 8006c34:	d047      	beq.n	8006cc6 <HAL_ADCEx_MultiModeConfigChannel+0x18e>
      {
        MODIFY_REG(tmpADC_Common->CCR,
 8006c36:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8006c38:	689a      	ldr	r2, [r3, #8]
 8006c3a:	4b2d      	ldr	r3, [pc, #180]	@ (8006cf0 <HAL_ADCEx_MultiModeConfigChannel+0x1b8>)
 8006c3c:	4013      	ands	r3, r2
 8006c3e:	683a      	ldr	r2, [r7, #0]
 8006c40:	6811      	ldr	r1, [r2, #0]
 8006c42:	683a      	ldr	r2, [r7, #0]
 8006c44:	6892      	ldr	r2, [r2, #8]
 8006c46:	430a      	orrs	r2, r1
 8006c48:	431a      	orrs	r2, r3
 8006c4a:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8006c4c:	609a      	str	r2, [r3, #8]
    if (multimode->Mode != ADC_MODE_INDEPENDENT)
 8006c4e:	e03a      	b.n	8006cc6 <HAL_ADCEx_MultiModeConfigChannel+0x18e>
                  );
      }
    }
    else /* ADC_MODE_INDEPENDENT */
    {
      CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
 8006c50:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8006c52:	689b      	ldr	r3, [r3, #8]
 8006c54:	f423 4240 	bic.w	r2, r3, #49152	@ 0xc000
 8006c58:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8006c5a:	609a      	str	r2, [r3, #8]

      /* Parameters that can be updated only when ADC is disabled:                */
      /*  - Multimode mode selection                                              */
      /*  - Multimode delay                                                       */
      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
 8006c5c:	687b      	ldr	r3, [r7, #4]
 8006c5e:	681b      	ldr	r3, [r3, #0]
 8006c60:	4a1e      	ldr	r2, [pc, #120]	@ (8006cdc <HAL_ADCEx_MultiModeConfigChannel+0x1a4>)
 8006c62:	4293      	cmp	r3, r2
 8006c64:	d004      	beq.n	8006c70 <HAL_ADCEx_MultiModeConfigChannel+0x138>
 8006c66:	687b      	ldr	r3, [r7, #4]
 8006c68:	681b      	ldr	r3, [r3, #0]
 8006c6a:	4a1d      	ldr	r2, [pc, #116]	@ (8006ce0 <HAL_ADCEx_MultiModeConfigChannel+0x1a8>)
 8006c6c:	4293      	cmp	r3, r2
 8006c6e:	d10e      	bne.n	8006c8e <HAL_ADCEx_MultiModeConfigChannel+0x156>
 8006c70:	481a      	ldr	r0, [pc, #104]	@ (8006cdc <HAL_ADCEx_MultiModeConfigChannel+0x1a4>)
 8006c72:	f7ff fea3 	bl	80069bc <LL_ADC_IsEnabled>
 8006c76:	4604      	mov	r4, r0
 8006c78:	4819      	ldr	r0, [pc, #100]	@ (8006ce0 <HAL_ADCEx_MultiModeConfigChannel+0x1a8>)
 8006c7a:	f7ff fe9f 	bl	80069bc <LL_ADC_IsEnabled>
 8006c7e:	4603      	mov	r3, r0
 8006c80:	4323      	orrs	r3, r4
 8006c82:	2b00      	cmp	r3, #0
 8006c84:	bf0c      	ite	eq
 8006c86:	2301      	moveq	r3, #1
 8006c88:	2300      	movne	r3, #0
 8006c8a:	b2db      	uxtb	r3, r3
 8006c8c:	e008      	b.n	8006ca0 <HAL_ADCEx_MultiModeConfigChannel+0x168>
 8006c8e:	4817      	ldr	r0, [pc, #92]	@ (8006cec <HAL_ADCEx_MultiModeConfigChannel+0x1b4>)
 8006c90:	f7ff fe94 	bl	80069bc <LL_ADC_IsEnabled>
 8006c94:	4603      	mov	r3, r0
 8006c96:	2b00      	cmp	r3, #0
 8006c98:	bf0c      	ite	eq
 8006c9a:	2301      	moveq	r3, #1
 8006c9c:	2300      	movne	r3, #0
 8006c9e:	b2db      	uxtb	r3, r3
 8006ca0:	2b00      	cmp	r3, #0
 8006ca2:	d010      	beq.n	8006cc6 <HAL_ADCEx_MultiModeConfigChannel+0x18e>
      {
        CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
 8006ca4:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8006ca6:	689a      	ldr	r2, [r3, #8]
 8006ca8:	4b11      	ldr	r3, [pc, #68]	@ (8006cf0 <HAL_ADCEx_MultiModeConfigChannel+0x1b8>)
 8006caa:	4013      	ands	r3, r2
 8006cac:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
 8006cae:	6093      	str	r3, [r2, #8]
    if (multimode->Mode != ADC_MODE_INDEPENDENT)
 8006cb0:	e009      	b.n	8006cc6 <HAL_ADCEx_MultiModeConfigChannel+0x18e>
  /* If one of the ADC sharing the same common group is enabled, no update    */
  /* could be done on neither of the multimode structure parameters.          */
  else
  {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 8006cb2:	687b      	ldr	r3, [r7, #4]
 8006cb4:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8006cb6:	f043 0220 	orr.w	r2, r3, #32
 8006cba:	687b      	ldr	r3, [r7, #4]
 8006cbc:	655a      	str	r2, [r3, #84]	@ 0x54

    tmp_hal_status = HAL_ERROR;
 8006cbe:	2301      	movs	r3, #1
 8006cc0:	f887 3077 	strb.w	r3, [r7, #119]	@ 0x77
 8006cc4:	e000      	b.n	8006cc8 <HAL_ADCEx_MultiModeConfigChannel+0x190>
    if (multimode->Mode != ADC_MODE_INDEPENDENT)
 8006cc6:	bf00      	nop
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 8006cc8:	687b      	ldr	r3, [r7, #4]
 8006cca:	2200      	movs	r2, #0
 8006ccc:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50

  /* Return function status */
  return tmp_hal_status;
 8006cd0:	f897 3077 	ldrb.w	r3, [r7, #119]	@ 0x77
}
 8006cd4:	4618      	mov	r0, r3
 8006cd6:	377c      	adds	r7, #124	@ 0x7c
 8006cd8:	46bd      	mov	sp, r7
 8006cda:	bd90      	pop	{r4, r7, pc}
 8006cdc:	40022000 	.word	0x40022000
 8006ce0:	40022100 	.word	0x40022100
 8006ce4:	40022300 	.word	0x40022300
 8006ce8:	58026300 	.word	0x58026300
 8006cec:	58026000 	.word	0x58026000
 8006cf0:	fffff0e0 	.word	0xfffff0e0

08006cf4 <HAL_COMP_Init>:
  *         To unlock the configuration, perform a system reset.
  * @param  hcomp COMP handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
 8006cf4:	b580      	push	{r7, lr}
 8006cf6:	b088      	sub	sp, #32
 8006cf8:	af00      	add	r7, sp, #0
 8006cfa:	6078      	str	r0, [r7, #4]
  uint32_t tmp_csr ;
  uint32_t exti_line ;
  uint32_t comp_voltage_scaler_initialized; /* Value "0" is comparator voltage scaler is not initialized */
  __IO uint32_t wait_loop_index = 0UL;
 8006cfc:	2300      	movs	r3, #0
 8006cfe:	60fb      	str	r3, [r7, #12]

  HAL_StatusTypeDef status = HAL_OK;
 8006d00:	2300      	movs	r3, #0
 8006d02:	77fb      	strb	r3, [r7, #31]
  
  /* Check the COMP handle allocation and lock status */
  if(hcomp == NULL)
 8006d04:	687b      	ldr	r3, [r7, #4]
 8006d06:	2b00      	cmp	r3, #0
 8006d08:	d102      	bne.n	8006d10 <HAL_COMP_Init+0x1c>
  {
    status = HAL_ERROR;
 8006d0a:	2301      	movs	r3, #1
 8006d0c:	77fb      	strb	r3, [r7, #31]
 8006d0e:	e10e      	b.n	8006f2e <HAL_COMP_Init+0x23a>
  }
  else if(__HAL_COMP_IS_LOCKED(hcomp))
 8006d10:	687b      	ldr	r3, [r7, #4]
 8006d12:	681b      	ldr	r3, [r3, #0]
 8006d14:	681b      	ldr	r3, [r3, #0]
 8006d16:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
 8006d1a:	f1b3 4f00 	cmp.w	r3, #2147483648	@ 0x80000000
 8006d1e:	d102      	bne.n	8006d26 <HAL_COMP_Init+0x32>
  {
    status = HAL_ERROR;
 8006d20:	2301      	movs	r3, #1
 8006d22:	77fb      	strb	r3, [r7, #31]
 8006d24:	e103      	b.n	8006f2e <HAL_COMP_Init+0x23a>
    assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
    assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); 
    assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
    assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));

    if(hcomp->State == HAL_COMP_STATE_RESET)
 8006d26:	687b      	ldr	r3, [r7, #4]
 8006d28:	f893 3025 	ldrb.w	r3, [r3, #37]	@ 0x25
 8006d2c:	b2db      	uxtb	r3, r3
 8006d2e:	2b00      	cmp	r3, #0
 8006d30:	d109      	bne.n	8006d46 <HAL_COMP_Init+0x52>
    {
      /* Allocate lock resource and initialize it */
      hcomp->Lock = HAL_UNLOCKED;
 8006d32:	687b      	ldr	r3, [r7, #4]
 8006d34:	2200      	movs	r2, #0
 8006d36:	f883 2024 	strb.w	r2, [r3, #36]	@ 0x24
	  
	  /* Set COMP error code to none */
      COMP_CLEAR_ERRORCODE(hcomp);
 8006d3a:	687b      	ldr	r3, [r7, #4]
 8006d3c:	2200      	movs	r2, #0
 8006d3e:	629a      	str	r2, [r3, #40]	@ 0x28
      
      /* Init the low level hardware */
      hcomp->MspInitCallback(hcomp);
#else
	 /* Init the low level hardware */
      HAL_COMP_MspInit(hcomp);
 8006d40:	6878      	ldr	r0, [r7, #4]
 8006d42:	f7fc fd4b 	bl	80037dc <HAL_COMP_MspInit>
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
    }
    /* Memorize voltage scaler state before initialization */
    comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN);
 8006d46:	687b      	ldr	r3, [r7, #4]
 8006d48:	681b      	ldr	r3, [r3, #0]
 8006d4a:	681b      	ldr	r3, [r3, #0]
 8006d4c:	f003 0304 	and.w	r3, r3, #4
 8006d50:	61bb      	str	r3, [r7, #24]
    /*     Set BLANKING bits according to hcomp->Init.BlankingSrce value       */
    /*     Set HYST bits according to hcomp->Init.Hysteresis value             */
    /*     Set POLARITY bit according to hcomp->Init.OutputPol value           */
    /*     Set POWERMODE bits according to hcomp->Init.Mode value              */
   
    tmp_csr = (hcomp->Init.InvertingInput    |  \
 8006d52:	687b      	ldr	r3, [r7, #4]
 8006d54:	691a      	ldr	r2, [r3, #16]
              hcomp->Init.NonInvertingInput  |  \
 8006d56:	687b      	ldr	r3, [r7, #4]
 8006d58:	68db      	ldr	r3, [r3, #12]
    tmp_csr = (hcomp->Init.InvertingInput    |  \
 8006d5a:	431a      	orrs	r2, r3
              hcomp->Init.BlankingSrce       |  \
 8006d5c:	687b      	ldr	r3, [r7, #4]
 8006d5e:	69db      	ldr	r3, [r3, #28]
              hcomp->Init.NonInvertingInput  |  \
 8006d60:	431a      	orrs	r2, r3
              hcomp->Init.Hysteresis         |  \
 8006d62:	687b      	ldr	r3, [r7, #4]
 8006d64:	695b      	ldr	r3, [r3, #20]
              hcomp->Init.BlankingSrce       |  \
 8006d66:	431a      	orrs	r2, r3
              hcomp->Init.OutputPol          |  \
 8006d68:	687b      	ldr	r3, [r7, #4]
 8006d6a:	699b      	ldr	r3, [r3, #24]
              hcomp->Init.Hysteresis         |  \
 8006d6c:	431a      	orrs	r2, r3
              hcomp->Init.Mode                );
 8006d6e:	687b      	ldr	r3, [r7, #4]
 8006d70:	689b      	ldr	r3, [r3, #8]
    tmp_csr = (hcomp->Init.InvertingInput    |  \
 8006d72:	4313      	orrs	r3, r2
 8006d74:	617b      	str	r3, [r7, #20]
               COMP_CFGRx_INP2SEL  | COMP_CFGRx_WINMODE  | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST    |
               COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN    | COMP_CFGRx_SCALEN,
               tmp_csr
              );
#else
    MODIFY_REG(hcomp->Instance->CFGR,
 8006d76:	687b      	ldr	r3, [r7, #4]
 8006d78:	681b      	ldr	r3, [r3, #0]
 8006d7a:	681a      	ldr	r2, [r3, #0]
 8006d7c:	4b6e      	ldr	r3, [pc, #440]	@ (8006f38 <HAL_COMP_Init+0x244>)
 8006d7e:	4013      	ands	r3, r2
 8006d80:	687a      	ldr	r2, [r7, #4]
 8006d82:	6812      	ldr	r2, [r2, #0]
 8006d84:	6979      	ldr	r1, [r7, #20]
 8006d86:	430b      	orrs	r3, r1
 8006d88:	6013      	str	r3, [r2, #0]
#endif
    /* Set window mode */
    /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP     */
    /*       instances. Therefore, this function can update another COMP      */
    /*       instance that the one currently selected.                        */
    if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
 8006d8a:	687b      	ldr	r3, [r7, #4]
 8006d8c:	685b      	ldr	r3, [r3, #4]
 8006d8e:	2b10      	cmp	r3, #16
 8006d90:	d108      	bne.n	8006da4 <HAL_COMP_Init+0xb0>
    {
      SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE);
 8006d92:	687b      	ldr	r3, [r7, #4]
 8006d94:	681b      	ldr	r3, [r3, #0]
 8006d96:	681a      	ldr	r2, [r3, #0]
 8006d98:	687b      	ldr	r3, [r7, #4]
 8006d9a:	681b      	ldr	r3, [r3, #0]
 8006d9c:	f042 0210 	orr.w	r2, r2, #16
 8006da0:	601a      	str	r2, [r3, #0]
 8006da2:	e007      	b.n	8006db4 <HAL_COMP_Init+0xc0>
    }
    else
    {
      CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE);
 8006da4:	687b      	ldr	r3, [r7, #4]
 8006da6:	681b      	ldr	r3, [r3, #0]
 8006da8:	681a      	ldr	r2, [r3, #0]
 8006daa:	687b      	ldr	r3, [r7, #4]
 8006dac:	681b      	ldr	r3, [r3, #0]
 8006dae:	f022 0210 	bic.w	r2, r2, #16
 8006db2:	601a      	str	r2, [r3, #0]
    }
    /* Delay for COMP scaler bridge voltage stabilization */
    /* Apply the delay if voltage scaler bridge is enabled for the first time */
    if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0UL) &&
 8006db4:	687b      	ldr	r3, [r7, #4]
 8006db6:	681b      	ldr	r3, [r3, #0]
 8006db8:	681b      	ldr	r3, [r3, #0]
 8006dba:	f003 0304 	and.w	r3, r3, #4
 8006dbe:	2b00      	cmp	r3, #0
 8006dc0:	d016      	beq.n	8006df0 <HAL_COMP_Init+0xfc>
 8006dc2:	69bb      	ldr	r3, [r7, #24]
 8006dc4:	2b00      	cmp	r3, #0
 8006dc6:	d013      	beq.n	8006df0 <HAL_COMP_Init+0xfc>
    {
      /* Wait loop initialization and execution */
      /* Note: Variable divided by 2 to compensate partially                  */
      /*       CPU processing cycles.*/

     wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
 8006dc8:	4b5c      	ldr	r3, [pc, #368]	@ (8006f3c <HAL_COMP_Init+0x248>)
 8006dca:	681b      	ldr	r3, [r3, #0]
 8006dcc:	099b      	lsrs	r3, r3, #6
 8006dce:	4a5c      	ldr	r2, [pc, #368]	@ (8006f40 <HAL_COMP_Init+0x24c>)
 8006dd0:	fba2 2303 	umull	r2, r3, r2, r3
 8006dd4:	099b      	lsrs	r3, r3, #6
 8006dd6:	1c5a      	adds	r2, r3, #1
 8006dd8:	4613      	mov	r3, r2
 8006dda:	009b      	lsls	r3, r3, #2
 8006ddc:	4413      	add	r3, r2
 8006dde:	009b      	lsls	r3, r3, #2
 8006de0:	60fb      	str	r3, [r7, #12]

     while(wait_loop_index != 0UL)
 8006de2:	e002      	b.n	8006dea <HAL_COMP_Init+0xf6>
     {
       wait_loop_index --;
 8006de4:	68fb      	ldr	r3, [r7, #12]
 8006de6:	3b01      	subs	r3, #1
 8006de8:	60fb      	str	r3, [r7, #12]
     while(wait_loop_index != 0UL)
 8006dea:	68fb      	ldr	r3, [r7, #12]
 8006dec:	2b00      	cmp	r3, #0
 8006dee:	d1f9      	bne.n	8006de4 <HAL_COMP_Init+0xf0>
     }
    }

    /* Get the EXTI line corresponding to the selected COMP instance */
    exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
 8006df0:	687b      	ldr	r3, [r7, #4]
 8006df2:	681b      	ldr	r3, [r3, #0]
 8006df4:	4a53      	ldr	r2, [pc, #332]	@ (8006f44 <HAL_COMP_Init+0x250>)
 8006df6:	4293      	cmp	r3, r2
 8006df8:	d102      	bne.n	8006e00 <HAL_COMP_Init+0x10c>
 8006dfa:	f44f 1380 	mov.w	r3, #1048576	@ 0x100000
 8006dfe:	e001      	b.n	8006e04 <HAL_COMP_Init+0x110>
 8006e00:	f44f 1300 	mov.w	r3, #2097152	@ 0x200000
 8006e04:	613b      	str	r3, [r7, #16]
    
    /* Manage EXTI settings */
    if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) 
 8006e06:	687b      	ldr	r3, [r7, #4]
 8006e08:	6a1b      	ldr	r3, [r3, #32]
 8006e0a:	f003 0303 	and.w	r3, r3, #3
 8006e0e:	2b00      	cmp	r3, #0
 8006e10:	d06d      	beq.n	8006eee <HAL_COMP_Init+0x1fa>
    {
      /* Configure EXTI rising edge */
      if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
 8006e12:	687b      	ldr	r3, [r7, #4]
 8006e14:	6a1b      	ldr	r3, [r3, #32]
 8006e16:	f003 0310 	and.w	r3, r3, #16
 8006e1a:	2b00      	cmp	r3, #0
 8006e1c:	d008      	beq.n	8006e30 <HAL_COMP_Init+0x13c>
      {
        SET_BIT(EXTI->RTSR1, exti_line);
 8006e1e:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8006e22:	681a      	ldr	r2, [r3, #0]
 8006e24:	f04f 41b0 	mov.w	r1, #1476395008	@ 0x58000000
 8006e28:	693b      	ldr	r3, [r7, #16]
 8006e2a:	4313      	orrs	r3, r2
 8006e2c:	600b      	str	r3, [r1, #0]
 8006e2e:	e008      	b.n	8006e42 <HAL_COMP_Init+0x14e>
      }
      else
      {
        CLEAR_BIT(EXTI->RTSR1, exti_line);
 8006e30:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8006e34:	681a      	ldr	r2, [r3, #0]
 8006e36:	693b      	ldr	r3, [r7, #16]
 8006e38:	43db      	mvns	r3, r3
 8006e3a:	f04f 41b0 	mov.w	r1, #1476395008	@ 0x58000000
 8006e3e:	4013      	ands	r3, r2
 8006e40:	600b      	str	r3, [r1, #0]
      }
      
      /* Configure EXTI falling edge */
      if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
 8006e42:	687b      	ldr	r3, [r7, #4]
 8006e44:	6a1b      	ldr	r3, [r3, #32]
 8006e46:	f003 0320 	and.w	r3, r3, #32
 8006e4a:	2b00      	cmp	r3, #0
 8006e4c:	d008      	beq.n	8006e60 <HAL_COMP_Init+0x16c>
      {
        SET_BIT(EXTI->FTSR1, exti_line);
 8006e4e:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8006e52:	685a      	ldr	r2, [r3, #4]
 8006e54:	f04f 41b0 	mov.w	r1, #1476395008	@ 0x58000000
 8006e58:	693b      	ldr	r3, [r7, #16]
 8006e5a:	4313      	orrs	r3, r2
 8006e5c:	604b      	str	r3, [r1, #4]
 8006e5e:	e008      	b.n	8006e72 <HAL_COMP_Init+0x17e>
      }
      else
      {
        CLEAR_BIT(EXTI->FTSR1, exti_line);
 8006e60:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8006e64:	685a      	ldr	r2, [r3, #4]
 8006e66:	693b      	ldr	r3, [r7, #16]
 8006e68:	43db      	mvns	r3, r3
 8006e6a:	f04f 41b0 	mov.w	r1, #1476395008	@ 0x58000000
 8006e6e:	4013      	ands	r3, r2
 8006e70:	604b      	str	r3, [r1, #4]
      }
     
#if !defined (CORE_CM4)
      /* Clear COMP EXTI pending bit (if any) */
      WRITE_REG(EXTI->PR1, exti_line);
 8006e72:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 8006e76:	693b      	ldr	r3, [r7, #16]
 8006e78:	f8c2 3088 	str.w	r3, [r2, #136]	@ 0x88

      /* Configure EXTI event mode */
      if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
 8006e7c:	687b      	ldr	r3, [r7, #4]
 8006e7e:	6a1b      	ldr	r3, [r3, #32]
 8006e80:	f003 0302 	and.w	r3, r3, #2
 8006e84:	2b00      	cmp	r3, #0
 8006e86:	d00a      	beq.n	8006e9e <HAL_COMP_Init+0x1aa>
      {
        SET_BIT(EXTI->EMR1, exti_line);
 8006e88:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8006e8c:	f8d3 2084 	ldr.w	r2, [r3, #132]	@ 0x84
 8006e90:	f04f 41b0 	mov.w	r1, #1476395008	@ 0x58000000
 8006e94:	693b      	ldr	r3, [r7, #16]
 8006e96:	4313      	orrs	r3, r2
 8006e98:	f8c1 3084 	str.w	r3, [r1, #132]	@ 0x84
 8006e9c:	e00a      	b.n	8006eb4 <HAL_COMP_Init+0x1c0>
      }
      else
      {
        CLEAR_BIT(EXTI->EMR1, exti_line);
 8006e9e:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8006ea2:	f8d3 2084 	ldr.w	r2, [r3, #132]	@ 0x84
 8006ea6:	693b      	ldr	r3, [r7, #16]
 8006ea8:	43db      	mvns	r3, r3
 8006eaa:	f04f 41b0 	mov.w	r1, #1476395008	@ 0x58000000
 8006eae:	4013      	ands	r3, r2
 8006eb0:	f8c1 3084 	str.w	r3, [r1, #132]	@ 0x84
      }
      
       /* Configure EXTI interrupt mode */
      if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
 8006eb4:	687b      	ldr	r3, [r7, #4]
 8006eb6:	6a1b      	ldr	r3, [r3, #32]
 8006eb8:	f003 0301 	and.w	r3, r3, #1
 8006ebc:	2b00      	cmp	r3, #0
 8006ebe:	d00a      	beq.n	8006ed6 <HAL_COMP_Init+0x1e2>
      {
        SET_BIT(EXTI->IMR1, exti_line);
 8006ec0:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8006ec4:	f8d3 2080 	ldr.w	r2, [r3, #128]	@ 0x80
 8006ec8:	f04f 41b0 	mov.w	r1, #1476395008	@ 0x58000000
 8006ecc:	693b      	ldr	r3, [r7, #16]
 8006ece:	4313      	orrs	r3, r2
 8006ed0:	f8c1 3080 	str.w	r3, [r1, #128]	@ 0x80
 8006ed4:	e021      	b.n	8006f1a <HAL_COMP_Init+0x226>
      }
      else
      {
        CLEAR_BIT(EXTI->IMR1, exti_line);
 8006ed6:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8006eda:	f8d3 2080 	ldr.w	r2, [r3, #128]	@ 0x80
 8006ede:	693b      	ldr	r3, [r7, #16]
 8006ee0:	43db      	mvns	r3, r3
 8006ee2:	f04f 41b0 	mov.w	r1, #1476395008	@ 0x58000000
 8006ee6:	4013      	ands	r3, r2
 8006ee8:	f8c1 3080 	str.w	r3, [r1, #128]	@ 0x80
 8006eec:	e015      	b.n	8006f1a <HAL_COMP_Init+0x226>
      }
    }
    else
    {
      /* Disable EXTI event mode */
      CLEAR_BIT(EXTI->EMR1, exti_line);
 8006eee:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8006ef2:	f8d3 2084 	ldr.w	r2, [r3, #132]	@ 0x84
 8006ef6:	693b      	ldr	r3, [r7, #16]
 8006ef8:	43db      	mvns	r3, r3
 8006efa:	f04f 41b0 	mov.w	r1, #1476395008	@ 0x58000000
 8006efe:	4013      	ands	r3, r2
 8006f00:	f8c1 3084 	str.w	r3, [r1, #132]	@ 0x84
      
      /* Disable EXTI interrupt mode */
      CLEAR_BIT(EXTI->IMR1, exti_line);
 8006f04:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 8006f08:	f8d3 2080 	ldr.w	r2, [r3, #128]	@ 0x80
 8006f0c:	693b      	ldr	r3, [r7, #16]
 8006f0e:	43db      	mvns	r3, r3
 8006f10:	f04f 41b0 	mov.w	r1, #1476395008	@ 0x58000000
 8006f14:	4013      	ands	r3, r2
 8006f16:	f8c1 3080 	str.w	r3, [r1, #128]	@ 0x80
    }
#endif
    /* Set HAL COMP handle state */
    /* Note: Transition from state reset to state ready,                      */
    /*       otherwise (coming from state ready or busy) no state update.     */
    if (hcomp->State == HAL_COMP_STATE_RESET)
 8006f1a:	687b      	ldr	r3, [r7, #4]
 8006f1c:	f893 3025 	ldrb.w	r3, [r3, #37]	@ 0x25
 8006f20:	b2db      	uxtb	r3, r3
 8006f22:	2b00      	cmp	r3, #0
 8006f24:	d103      	bne.n	8006f2e <HAL_COMP_Init+0x23a>
    {
     
      hcomp->State = HAL_COMP_STATE_READY;
 8006f26:	687b      	ldr	r3, [r7, #4]
 8006f28:	2201      	movs	r2, #1
 8006f2a:	f883 2025 	strb.w	r2, [r3, #37]	@ 0x25
    }
   
  }
  
  return status;
 8006f2e:	7ffb      	ldrb	r3, [r7, #31]
}
 8006f30:	4618      	mov	r0, r3
 8006f32:	3720      	adds	r7, #32
 8006f34:	46bd      	mov	sp, r7
 8006f36:	bd80      	pop	{r7, pc}
 8006f38:	f0e8cce1 	.word	0xf0e8cce1
 8006f3c:	24000034 	.word	0x24000034
 8006f40:	053e2d63 	.word	0x053e2d63
 8006f44:	5800380c 	.word	0x5800380c

08006f48 <HAL_COMP_Start>:
  * @brief  Start the comparator. 
  * @param  hcomp COMP handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
{ 
 8006f48:	b480      	push	{r7}
 8006f4a:	b085      	sub	sp, #20
 8006f4c:	af00      	add	r7, sp, #0
 8006f4e:	6078      	str	r0, [r7, #4]
  __IO uint32_t wait_loop_index = 0UL;
 8006f50:	2300      	movs	r3, #0
 8006f52:	60bb      	str	r3, [r7, #8]

  HAL_StatusTypeDef status = HAL_OK;
 8006f54:	2300      	movs	r3, #0
 8006f56:	73fb      	strb	r3, [r7, #15]
  
  /* Check the COMP handle allocation and lock status */
  if(hcomp == NULL)
 8006f58:	687b      	ldr	r3, [r7, #4]
 8006f5a:	2b00      	cmp	r3, #0
 8006f5c:	d102      	bne.n	8006f64 <HAL_COMP_Start+0x1c>
  {
    status = HAL_ERROR;
 8006f5e:	2301      	movs	r3, #1
 8006f60:	73fb      	strb	r3, [r7, #15]
 8006f62:	e030      	b.n	8006fc6 <HAL_COMP_Start+0x7e>
  }
  else if(__HAL_COMP_IS_LOCKED(hcomp))
 8006f64:	687b      	ldr	r3, [r7, #4]
 8006f66:	681b      	ldr	r3, [r3, #0]
 8006f68:	681b      	ldr	r3, [r3, #0]
 8006f6a:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
 8006f6e:	f1b3 4f00 	cmp.w	r3, #2147483648	@ 0x80000000
 8006f72:	d102      	bne.n	8006f7a <HAL_COMP_Start+0x32>
  {
    status = HAL_ERROR;
 8006f74:	2301      	movs	r3, #1
 8006f76:	73fb      	strb	r3, [r7, #15]
 8006f78:	e025      	b.n	8006fc6 <HAL_COMP_Start+0x7e>
  else
  {
    /* Check the parameter */
    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));

    if(hcomp->State == HAL_COMP_STATE_READY)
 8006f7a:	687b      	ldr	r3, [r7, #4]
 8006f7c:	f893 3025 	ldrb.w	r3, [r3, #37]	@ 0x25
 8006f80:	b2db      	uxtb	r3, r3
 8006f82:	2b01      	cmp	r3, #1
 8006f84:	d11d      	bne.n	8006fc2 <HAL_COMP_Start+0x7a>
    {
      /* Enable the selected comparator */
      SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
 8006f86:	687b      	ldr	r3, [r7, #4]
 8006f88:	681b      	ldr	r3, [r3, #0]
 8006f8a:	681a      	ldr	r2, [r3, #0]
 8006f8c:	687b      	ldr	r3, [r7, #4]
 8006f8e:	681b      	ldr	r3, [r3, #0]
 8006f90:	f042 0201 	orr.w	r2, r2, #1
 8006f94:	601a      	str	r2, [r3, #0]

      /* Set HAL COMP handle state */
      hcomp->State = HAL_COMP_STATE_BUSY;
 8006f96:	687b      	ldr	r3, [r7, #4]
 8006f98:	2202      	movs	r2, #2
 8006f9a:	f883 2025 	strb.w	r2, [r3, #37]	@ 0x25
     /* Delay for COMP startup time */
     /* Wait loop initialization and execution */
     /* Note: Variable divided by 2 to compensate partially    */
     /*       CPU processing cycles.                           */
    
     wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
 8006f9e:	4b0d      	ldr	r3, [pc, #52]	@ (8006fd4 <HAL_COMP_Start+0x8c>)
 8006fa0:	681b      	ldr	r3, [r3, #0]
 8006fa2:	099b      	lsrs	r3, r3, #6
 8006fa4:	4a0c      	ldr	r2, [pc, #48]	@ (8006fd8 <HAL_COMP_Start+0x90>)
 8006fa6:	fba2 2303 	umull	r2, r3, r2, r3
 8006faa:	099b      	lsrs	r3, r3, #6
 8006fac:	3301      	adds	r3, #1
 8006fae:	00db      	lsls	r3, r3, #3
 8006fb0:	60bb      	str	r3, [r7, #8]
     while(wait_loop_index != 0UL)
 8006fb2:	e002      	b.n	8006fba <HAL_COMP_Start+0x72>
     {
       wait_loop_index--;
 8006fb4:	68bb      	ldr	r3, [r7, #8]
 8006fb6:	3b01      	subs	r3, #1
 8006fb8:	60bb      	str	r3, [r7, #8]
     while(wait_loop_index != 0UL)
 8006fba:	68bb      	ldr	r3, [r7, #8]
 8006fbc:	2b00      	cmp	r3, #0
 8006fbe:	d1f9      	bne.n	8006fb4 <HAL_COMP_Start+0x6c>
 8006fc0:	e001      	b.n	8006fc6 <HAL_COMP_Start+0x7e>
     }      
    }
    else
    {
      status = HAL_ERROR;
 8006fc2:	2301      	movs	r3, #1
 8006fc4:	73fb      	strb	r3, [r7, #15]
    }
  }

  return status;
 8006fc6:	7bfb      	ldrb	r3, [r7, #15]
}
 8006fc8:	4618      	mov	r0, r3
 8006fca:	3714      	adds	r7, #20
 8006fcc:	46bd      	mov	sp, r7
 8006fce:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006fd2:	4770      	bx	lr
 8006fd4:	24000034 	.word	0x24000034
 8006fd8:	053e2d63 	.word	0x053e2d63

08006fdc <HAL_COMP_GetOutputLevel>:
  *         @arg @ref COMP_OUTPUT_LEVEL_LOW
  *         @arg @ref COMP_OUTPUT_LEVEL_HIGH
  *       
  */
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
{
 8006fdc:	b480      	push	{r7}
 8006fde:	b083      	sub	sp, #12
 8006fe0:	af00      	add	r7, sp, #0
 8006fe2:	6078      	str	r0, [r7, #4]
  /* Check the parameter */
  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
 
  if (hcomp->Instance == COMP1)
 8006fe4:	687b      	ldr	r3, [r7, #4]
 8006fe6:	681b      	ldr	r3, [r3, #0]
 8006fe8:	4a09      	ldr	r2, [pc, #36]	@ (8007010 <HAL_COMP_GetOutputLevel+0x34>)
 8006fea:	4293      	cmp	r3, r2
 8006fec:	d104      	bne.n	8006ff8 <HAL_COMP_GetOutputLevel+0x1c>
  {
    return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL));                 
 8006fee:	4b09      	ldr	r3, [pc, #36]	@ (8007014 <HAL_COMP_GetOutputLevel+0x38>)
 8006ff0:	681b      	ldr	r3, [r3, #0]
 8006ff2:	f003 0301 	and.w	r3, r3, #1
 8006ff6:	e004      	b.n	8007002 <HAL_COMP_GetOutputLevel+0x26>
  }
  else
  {
    return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1UL);
 8006ff8:	4b06      	ldr	r3, [pc, #24]	@ (8007014 <HAL_COMP_GetOutputLevel+0x38>)
 8006ffa:	681b      	ldr	r3, [r3, #0]
 8006ffc:	085b      	lsrs	r3, r3, #1
 8006ffe:	f003 0301 	and.w	r3, r3, #1
  }
}
 8007002:	4618      	mov	r0, r3
 8007004:	370c      	adds	r7, #12
 8007006:	46bd      	mov	sp, r7
 8007008:	f85d 7b04 	ldr.w	r7, [sp], #4
 800700c:	4770      	bx	lr
 800700e:	bf00      	nop
 8007010:	5800380c 	.word	0x5800380c
 8007014:	58003800 	.word	0x58003800

08007018 <__NVIC_SetPriorityGrouping>:
{
 8007018:	b480      	push	{r7}
 800701a:	b085      	sub	sp, #20
 800701c:	af00      	add	r7, sp, #0
 800701e:	6078      	str	r0, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 8007020:	687b      	ldr	r3, [r7, #4]
 8007022:	f003 0307 	and.w	r3, r3, #7
 8007026:	60fb      	str	r3, [r7, #12]
  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8007028:	4b0b      	ldr	r3, [pc, #44]	@ (8007058 <__NVIC_SetPriorityGrouping+0x40>)
 800702a:	68db      	ldr	r3, [r3, #12]
 800702c:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 800702e:	68ba      	ldr	r2, [r7, #8]
 8007030:	f64f 03ff 	movw	r3, #63743	@ 0xf8ff
 8007034:	4013      	ands	r3, r2
 8007036:	60bb      	str	r3, [r7, #8]
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 8007038:	68fb      	ldr	r3, [r7, #12]
 800703a:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 800703c:	68bb      	ldr	r3, [r7, #8]
 800703e:	431a      	orrs	r2, r3
  reg_value  =  (reg_value                                   |
 8007040:	4b06      	ldr	r3, [pc, #24]	@ (800705c <__NVIC_SetPriorityGrouping+0x44>)
 8007042:	4313      	orrs	r3, r2
 8007044:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 8007046:	4a04      	ldr	r2, [pc, #16]	@ (8007058 <__NVIC_SetPriorityGrouping+0x40>)
 8007048:	68bb      	ldr	r3, [r7, #8]
 800704a:	60d3      	str	r3, [r2, #12]
}
 800704c:	bf00      	nop
 800704e:	3714      	adds	r7, #20
 8007050:	46bd      	mov	sp, r7
 8007052:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007056:	4770      	bx	lr
 8007058:	e000ed00 	.word	0xe000ed00
 800705c:	05fa0000 	.word	0x05fa0000

08007060 <__NVIC_GetPriorityGrouping>:
{
 8007060:	b480      	push	{r7}
 8007062:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8007064:	4b04      	ldr	r3, [pc, #16]	@ (8007078 <__NVIC_GetPriorityGrouping+0x18>)
 8007066:	68db      	ldr	r3, [r3, #12]
 8007068:	0a1b      	lsrs	r3, r3, #8
 800706a:	f003 0307 	and.w	r3, r3, #7
}
 800706e:	4618      	mov	r0, r3
 8007070:	46bd      	mov	sp, r7
 8007072:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007076:	4770      	bx	lr
 8007078:	e000ed00 	.word	0xe000ed00

0800707c <__NVIC_EnableIRQ>:
{
 800707c:	b480      	push	{r7}
 800707e:	b083      	sub	sp, #12
 8007080:	af00      	add	r7, sp, #0
 8007082:	4603      	mov	r3, r0
 8007084:	80fb      	strh	r3, [r7, #6]
  if ((int32_t)(IRQn) >= 0)
 8007086:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 800708a:	2b00      	cmp	r3, #0
 800708c:	db0b      	blt.n	80070a6 <__NVIC_EnableIRQ+0x2a>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 800708e:	88fb      	ldrh	r3, [r7, #6]
 8007090:	f003 021f 	and.w	r2, r3, #31
 8007094:	4907      	ldr	r1, [pc, #28]	@ (80070b4 <__NVIC_EnableIRQ+0x38>)
 8007096:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 800709a:	095b      	lsrs	r3, r3, #5
 800709c:	2001      	movs	r0, #1
 800709e:	fa00 f202 	lsl.w	r2, r0, r2
 80070a2:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
}
 80070a6:	bf00      	nop
 80070a8:	370c      	adds	r7, #12
 80070aa:	46bd      	mov	sp, r7
 80070ac:	f85d 7b04 	ldr.w	r7, [sp], #4
 80070b0:	4770      	bx	lr
 80070b2:	bf00      	nop
 80070b4:	e000e100 	.word	0xe000e100

080070b8 <__NVIC_SetPriority>:
{
 80070b8:	b480      	push	{r7}
 80070ba:	b083      	sub	sp, #12
 80070bc:	af00      	add	r7, sp, #0
 80070be:	4603      	mov	r3, r0
 80070c0:	6039      	str	r1, [r7, #0]
 80070c2:	80fb      	strh	r3, [r7, #6]
  if ((int32_t)(IRQn) >= 0)
 80070c4:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 80070c8:	2b00      	cmp	r3, #0
 80070ca:	db0a      	blt.n	80070e2 <__NVIC_SetPriority+0x2a>
    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80070cc:	683b      	ldr	r3, [r7, #0]
 80070ce:	b2da      	uxtb	r2, r3
 80070d0:	490c      	ldr	r1, [pc, #48]	@ (8007104 <__NVIC_SetPriority+0x4c>)
 80070d2:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 80070d6:	0112      	lsls	r2, r2, #4
 80070d8:	b2d2      	uxtb	r2, r2
 80070da:	440b      	add	r3, r1
 80070dc:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
}
 80070e0:	e00a      	b.n	80070f8 <__NVIC_SetPriority+0x40>
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80070e2:	683b      	ldr	r3, [r7, #0]
 80070e4:	b2da      	uxtb	r2, r3
 80070e6:	4908      	ldr	r1, [pc, #32]	@ (8007108 <__NVIC_SetPriority+0x50>)
 80070e8:	88fb      	ldrh	r3, [r7, #6]
 80070ea:	f003 030f 	and.w	r3, r3, #15
 80070ee:	3b04      	subs	r3, #4
 80070f0:	0112      	lsls	r2, r2, #4
 80070f2:	b2d2      	uxtb	r2, r2
 80070f4:	440b      	add	r3, r1
 80070f6:	761a      	strb	r2, [r3, #24]
}
 80070f8:	bf00      	nop
 80070fa:	370c      	adds	r7, #12
 80070fc:	46bd      	mov	sp, r7
 80070fe:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007102:	4770      	bx	lr
 8007104:	e000e100 	.word	0xe000e100
 8007108:	e000ed00 	.word	0xe000ed00

0800710c <NVIC_EncodePriority>:
{
 800710c:	b480      	push	{r7}
 800710e:	b089      	sub	sp, #36	@ 0x24
 8007110:	af00      	add	r7, sp, #0
 8007112:	60f8      	str	r0, [r7, #12]
 8007114:	60b9      	str	r1, [r7, #8]
 8007116:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 8007118:	68fb      	ldr	r3, [r7, #12]
 800711a:	f003 0307 	and.w	r3, r3, #7
 800711e:	61fb      	str	r3, [r7, #28]
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8007120:	69fb      	ldr	r3, [r7, #28]
 8007122:	f1c3 0307 	rsb	r3, r3, #7
 8007126:	2b04      	cmp	r3, #4
 8007128:	bf28      	it	cs
 800712a:	2304      	movcs	r3, #4
 800712c:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 800712e:	69fb      	ldr	r3, [r7, #28]
 8007130:	3304      	adds	r3, #4
 8007132:	2b06      	cmp	r3, #6
 8007134:	d902      	bls.n	800713c <NVIC_EncodePriority+0x30>
 8007136:	69fb      	ldr	r3, [r7, #28]
 8007138:	3b03      	subs	r3, #3
 800713a:	e000      	b.n	800713e <NVIC_EncodePriority+0x32>
 800713c:	2300      	movs	r3, #0
 800713e:	617b      	str	r3, [r7, #20]
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8007140:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8007144:	69bb      	ldr	r3, [r7, #24]
 8007146:	fa02 f303 	lsl.w	r3, r2, r3
 800714a:	43da      	mvns	r2, r3
 800714c:	68bb      	ldr	r3, [r7, #8]
 800714e:	401a      	ands	r2, r3
 8007150:	697b      	ldr	r3, [r7, #20]
 8007152:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8007154:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
 8007158:	697b      	ldr	r3, [r7, #20]
 800715a:	fa01 f303 	lsl.w	r3, r1, r3
 800715e:	43d9      	mvns	r1, r3
 8007160:	687b      	ldr	r3, [r7, #4]
 8007162:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8007164:	4313      	orrs	r3, r2
}
 8007166:	4618      	mov	r0, r3
 8007168:	3724      	adds	r7, #36	@ 0x24
 800716a:	46bd      	mov	sp, r7
 800716c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007170:	4770      	bx	lr

08007172 <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
  *         The pending IRQ priority will be managed only by the subpriority.
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8007172:	b580      	push	{r7, lr}
 8007174:	b082      	sub	sp, #8
 8007176:	af00      	add	r7, sp, #0
 8007178:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));

  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 800717a:	6878      	ldr	r0, [r7, #4]
 800717c:	f7ff ff4c 	bl	8007018 <__NVIC_SetPriorityGrouping>
}
 8007180:	bf00      	nop
 8007182:	3708      	adds	r7, #8
 8007184:	46bd      	mov	sp, r7
 8007186:	bd80      	pop	{r7, pc}

08007188 <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8007188:	b580      	push	{r7, lr}
 800718a:	b086      	sub	sp, #24
 800718c:	af00      	add	r7, sp, #0
 800718e:	4603      	mov	r3, r0
 8007190:	60b9      	str	r1, [r7, #8]
 8007192:	607a      	str	r2, [r7, #4]
 8007194:	81fb      	strh	r3, [r7, #14]

  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));

  prioritygroup = NVIC_GetPriorityGrouping();
 8007196:	f7ff ff63 	bl	8007060 <__NVIC_GetPriorityGrouping>
 800719a:	6178      	str	r0, [r7, #20]

  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 800719c:	687a      	ldr	r2, [r7, #4]
 800719e:	68b9      	ldr	r1, [r7, #8]
 80071a0:	6978      	ldr	r0, [r7, #20]
 80071a2:	f7ff ffb3 	bl	800710c <NVIC_EncodePriority>
 80071a6:	4602      	mov	r2, r0
 80071a8:	f9b7 300e 	ldrsh.w	r3, [r7, #14]
 80071ac:	4611      	mov	r1, r2
 80071ae:	4618      	mov	r0, r3
 80071b0:	f7ff ff82 	bl	80070b8 <__NVIC_SetPriority>
}
 80071b4:	bf00      	nop
 80071b6:	3718      	adds	r7, #24
 80071b8:	46bd      	mov	sp, r7
 80071ba:	bd80      	pop	{r7, pc}

080071bc <HAL_NVIC_EnableIRQ>:
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
  * @retval None
  */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
 80071bc:	b580      	push	{r7, lr}
 80071be:	b082      	sub	sp, #8
 80071c0:	af00      	add	r7, sp, #0
 80071c2:	4603      	mov	r3, r0
 80071c4:	80fb      	strh	r3, [r7, #6]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));

  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
 80071c6:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 80071ca:	4618      	mov	r0, r3
 80071cc:	f7ff ff56 	bl	800707c <__NVIC_EnableIRQ>
}
 80071d0:	bf00      	nop
 80071d2:	3708      	adds	r7, #8
 80071d4:	46bd      	mov	sp, r7
 80071d6:	bd80      	pop	{r7, pc}

080071d8 <HAL_MPU_Disable>:
/**
  * @brief  Disables the MPU
  * @retval None
  */
void HAL_MPU_Disable(void)
{
 80071d8:	b480      	push	{r7}
 80071da:	af00      	add	r7, sp, #0
  __ASM volatile ("dmb 0xF":::"memory");
 80071dc:	f3bf 8f5f 	dmb	sy
}
 80071e0:	bf00      	nop
  /* Make sure outstanding transfers are done */
  __DMB();

  /* Disable fault exceptions */
  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 80071e2:	4b07      	ldr	r3, [pc, #28]	@ (8007200 <HAL_MPU_Disable+0x28>)
 80071e4:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80071e6:	4a06      	ldr	r2, [pc, #24]	@ (8007200 <HAL_MPU_Disable+0x28>)
 80071e8:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 80071ec:	6253      	str	r3, [r2, #36]	@ 0x24

  /* Disable the MPU and clear the control register*/
  MPU->CTRL = 0;
 80071ee:	4b05      	ldr	r3, [pc, #20]	@ (8007204 <HAL_MPU_Disable+0x2c>)
 80071f0:	2200      	movs	r2, #0
 80071f2:	605a      	str	r2, [r3, #4]
}
 80071f4:	bf00      	nop
 80071f6:	46bd      	mov	sp, r7
 80071f8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80071fc:	4770      	bx	lr
 80071fe:	bf00      	nop
 8007200:	e000ed00 	.word	0xe000ed00
 8007204:	e000ed90 	.word	0xe000ed90

08007208 <HAL_MPU_Enable>:
  *            @arg MPU_PRIVILEGED_DEFAULT
  *            @arg MPU_HFNMI_PRIVDEF
  * @retval None
  */
void HAL_MPU_Enable(uint32_t MPU_Control)
{
 8007208:	b480      	push	{r7}
 800720a:	b083      	sub	sp, #12
 800720c:	af00      	add	r7, sp, #0
 800720e:	6078      	str	r0, [r7, #4]
  /* Enable the MPU */
  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 8007210:	4a0b      	ldr	r2, [pc, #44]	@ (8007240 <HAL_MPU_Enable+0x38>)
 8007212:	687b      	ldr	r3, [r7, #4]
 8007214:	f043 0301 	orr.w	r3, r3, #1
 8007218:	6053      	str	r3, [r2, #4]

  /* Enable fault exceptions */
  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 800721a:	4b0a      	ldr	r3, [pc, #40]	@ (8007244 <HAL_MPU_Enable+0x3c>)
 800721c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800721e:	4a09      	ldr	r2, [pc, #36]	@ (8007244 <HAL_MPU_Enable+0x3c>)
 8007220:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 8007224:	6253      	str	r3, [r2, #36]	@ 0x24
  __ASM volatile ("dsb 0xF":::"memory");
 8007226:	f3bf 8f4f 	dsb	sy
}
 800722a:	bf00      	nop
  __ASM volatile ("isb 0xF":::"memory");
 800722c:	f3bf 8f6f 	isb	sy
}
 8007230:	bf00      	nop

  /* Ensure MPU setting take effects */
  __DSB();
  __ISB();
}
 8007232:	bf00      	nop
 8007234:	370c      	adds	r7, #12
 8007236:	46bd      	mov	sp, r7
 8007238:	f85d 7b04 	ldr.w	r7, [sp], #4
 800723c:	4770      	bx	lr
 800723e:	bf00      	nop
 8007240:	e000ed90 	.word	0xe000ed90
 8007244:	e000ed00 	.word	0xe000ed00

08007248 <HAL_MPU_ConfigRegion>:
  * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
  *                the initialization and configuration information.
  * @retval None
  */
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
{
 8007248:	b480      	push	{r7}
 800724a:	b083      	sub	sp, #12
 800724c:	af00      	add	r7, sp, #0
 800724e:	6078      	str	r0, [r7, #4]
  assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
  assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
  assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));

  /* Set the Region number */
  MPU->RNR = MPU_Init->Number;
 8007250:	687b      	ldr	r3, [r7, #4]
 8007252:	785a      	ldrb	r2, [r3, #1]
 8007254:	4b1b      	ldr	r3, [pc, #108]	@ (80072c4 <HAL_MPU_ConfigRegion+0x7c>)
 8007256:	609a      	str	r2, [r3, #8]

  /* Disable the Region */
  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
 8007258:	4b1a      	ldr	r3, [pc, #104]	@ (80072c4 <HAL_MPU_ConfigRegion+0x7c>)
 800725a:	691b      	ldr	r3, [r3, #16]
 800725c:	4a19      	ldr	r2, [pc, #100]	@ (80072c4 <HAL_MPU_ConfigRegion+0x7c>)
 800725e:	f023 0301 	bic.w	r3, r3, #1
 8007262:	6113      	str	r3, [r2, #16]

  /* Apply configuration */
  MPU->RBAR = MPU_Init->BaseAddress;
 8007264:	4a17      	ldr	r2, [pc, #92]	@ (80072c4 <HAL_MPU_ConfigRegion+0x7c>)
 8007266:	687b      	ldr	r3, [r7, #4]
 8007268:	685b      	ldr	r3, [r3, #4]
 800726a:	60d3      	str	r3, [r2, #12]
  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 800726c:	687b      	ldr	r3, [r7, #4]
 800726e:	7b1b      	ldrb	r3, [r3, #12]
 8007270:	071a      	lsls	r2, r3, #28
              ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
 8007272:	687b      	ldr	r3, [r7, #4]
 8007274:	7adb      	ldrb	r3, [r3, #11]
 8007276:	061b      	lsls	r3, r3, #24
  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 8007278:	431a      	orrs	r2, r3
              ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
 800727a:	687b      	ldr	r3, [r7, #4]
 800727c:	7a9b      	ldrb	r3, [r3, #10]
 800727e:	04db      	lsls	r3, r3, #19
              ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
 8007280:	431a      	orrs	r2, r3
              ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
 8007282:	687b      	ldr	r3, [r7, #4]
 8007284:	7b5b      	ldrb	r3, [r3, #13]
 8007286:	049b      	lsls	r3, r3, #18
              ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
 8007288:	431a      	orrs	r2, r3
              ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
 800728a:	687b      	ldr	r3, [r7, #4]
 800728c:	7b9b      	ldrb	r3, [r3, #14]
 800728e:	045b      	lsls	r3, r3, #17
              ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
 8007290:	431a      	orrs	r2, r3
              ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
 8007292:	687b      	ldr	r3, [r7, #4]
 8007294:	7bdb      	ldrb	r3, [r3, #15]
 8007296:	041b      	lsls	r3, r3, #16
              ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
 8007298:	431a      	orrs	r2, r3
              ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
 800729a:	687b      	ldr	r3, [r7, #4]
 800729c:	7a5b      	ldrb	r3, [r3, #9]
 800729e:	021b      	lsls	r3, r3, #8
              ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
 80072a0:	431a      	orrs	r2, r3
              ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
 80072a2:	687b      	ldr	r3, [r7, #4]
 80072a4:	7a1b      	ldrb	r3, [r3, #8]
 80072a6:	005b      	lsls	r3, r3, #1
              ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
 80072a8:	4313      	orrs	r3, r2
              ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
 80072aa:	687a      	ldr	r2, [r7, #4]
 80072ac:	7812      	ldrb	r2, [r2, #0]
 80072ae:	4611      	mov	r1, r2
  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 80072b0:	4a04      	ldr	r2, [pc, #16]	@ (80072c4 <HAL_MPU_ConfigRegion+0x7c>)
              ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
 80072b2:	430b      	orrs	r3, r1
  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 80072b4:	6113      	str	r3, [r2, #16]
}
 80072b6:	bf00      	nop
 80072b8:	370c      	adds	r7, #12
 80072ba:	46bd      	mov	sp, r7
 80072bc:	f85d 7b04 	ldr.w	r7, [sp], #4
 80072c0:	4770      	bx	lr
 80072c2:	bf00      	nop
 80072c4:	e000ed90 	.word	0xe000ed90

080072c8 <HAL_CRC_Init>:
  *         parameters in the CRC_InitTypeDef and create the associated handle.
  * @param  hcrc CRC handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
 80072c8:	b580      	push	{r7, lr}
 80072ca:	b082      	sub	sp, #8
 80072cc:	af00      	add	r7, sp, #0
 80072ce:	6078      	str	r0, [r7, #4]
  /* Check the CRC handle allocation */
  if (hcrc == NULL)
 80072d0:	687b      	ldr	r3, [r7, #4]
 80072d2:	2b00      	cmp	r3, #0
 80072d4:	d101      	bne.n	80072da <HAL_CRC_Init+0x12>
  {
    return HAL_ERROR;
 80072d6:	2301      	movs	r3, #1
 80072d8:	e054      	b.n	8007384 <HAL_CRC_Init+0xbc>
  }

  /* Check the parameters */
  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));

  if (hcrc->State == HAL_CRC_STATE_RESET)
 80072da:	687b      	ldr	r3, [r7, #4]
 80072dc:	7f5b      	ldrb	r3, [r3, #29]
 80072de:	b2db      	uxtb	r3, r3
 80072e0:	2b00      	cmp	r3, #0
 80072e2:	d105      	bne.n	80072f0 <HAL_CRC_Init+0x28>
  {
    /* Allocate lock resource and initialize it */
    hcrc->Lock = HAL_UNLOCKED;
 80072e4:	687b      	ldr	r3, [r7, #4]
 80072e6:	2200      	movs	r2, #0
 80072e8:	771a      	strb	r2, [r3, #28]
    /* Init the low level hardware */
    HAL_CRC_MspInit(hcrc);
 80072ea:	6878      	ldr	r0, [r7, #4]
 80072ec:	f7fc fabc 	bl	8003868 <HAL_CRC_MspInit>
  }

  hcrc->State = HAL_CRC_STATE_BUSY;
 80072f0:	687b      	ldr	r3, [r7, #4]
 80072f2:	2202      	movs	r2, #2
 80072f4:	775a      	strb	r2, [r3, #29]

  /* check whether or not non-default generating polynomial has been
   * picked up by user */
  assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
  if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
 80072f6:	687b      	ldr	r3, [r7, #4]
 80072f8:	791b      	ldrb	r3, [r3, #4]
 80072fa:	2b00      	cmp	r3, #0
 80072fc:	d10c      	bne.n	8007318 <HAL_CRC_Init+0x50>
  {
    /* initialize peripheral with default generating polynomial */
    WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
 80072fe:	687b      	ldr	r3, [r7, #4]
 8007300:	681b      	ldr	r3, [r3, #0]
 8007302:	4a22      	ldr	r2, [pc, #136]	@ (800738c <HAL_CRC_Init+0xc4>)
 8007304:	615a      	str	r2, [r3, #20]
    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
 8007306:	687b      	ldr	r3, [r7, #4]
 8007308:	681b      	ldr	r3, [r3, #0]
 800730a:	689a      	ldr	r2, [r3, #8]
 800730c:	687b      	ldr	r3, [r7, #4]
 800730e:	681b      	ldr	r3, [r3, #0]
 8007310:	f022 0218 	bic.w	r2, r2, #24
 8007314:	609a      	str	r2, [r3, #8]
 8007316:	e00c      	b.n	8007332 <HAL_CRC_Init+0x6a>
  }
  else
  {
    /* initialize CRC peripheral with generating polynomial defined by user */
    if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
 8007318:	687b      	ldr	r3, [r7, #4]
 800731a:	6899      	ldr	r1, [r3, #8]
 800731c:	687b      	ldr	r3, [r7, #4]
 800731e:	68db      	ldr	r3, [r3, #12]
 8007320:	461a      	mov	r2, r3
 8007322:	6878      	ldr	r0, [r7, #4]
 8007324:	f000 f948 	bl	80075b8 <HAL_CRCEx_Polynomial_Set>
 8007328:	4603      	mov	r3, r0
 800732a:	2b00      	cmp	r3, #0
 800732c:	d001      	beq.n	8007332 <HAL_CRC_Init+0x6a>
    {
      return HAL_ERROR;
 800732e:	2301      	movs	r3, #1
 8007330:	e028      	b.n	8007384 <HAL_CRC_Init+0xbc>
  }

  /* check whether or not non-default CRC initial value has been
   * picked up by user */
  assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
  if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
 8007332:	687b      	ldr	r3, [r7, #4]
 8007334:	795b      	ldrb	r3, [r3, #5]
 8007336:	2b00      	cmp	r3, #0
 8007338:	d105      	bne.n	8007346 <HAL_CRC_Init+0x7e>
  {
    WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
 800733a:	687b      	ldr	r3, [r7, #4]
 800733c:	681b      	ldr	r3, [r3, #0]
 800733e:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8007342:	611a      	str	r2, [r3, #16]
 8007344:	e004      	b.n	8007350 <HAL_CRC_Init+0x88>
  }
  else
  {
    WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
 8007346:	687b      	ldr	r3, [r7, #4]
 8007348:	681b      	ldr	r3, [r3, #0]
 800734a:	687a      	ldr	r2, [r7, #4]
 800734c:	6912      	ldr	r2, [r2, #16]
 800734e:	611a      	str	r2, [r3, #16]
  }


  /* set input data inversion mode */
  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
 8007350:	687b      	ldr	r3, [r7, #4]
 8007352:	681b      	ldr	r3, [r3, #0]
 8007354:	689b      	ldr	r3, [r3, #8]
 8007356:	f023 0160 	bic.w	r1, r3, #96	@ 0x60
 800735a:	687b      	ldr	r3, [r7, #4]
 800735c:	695a      	ldr	r2, [r3, #20]
 800735e:	687b      	ldr	r3, [r7, #4]
 8007360:	681b      	ldr	r3, [r3, #0]
 8007362:	430a      	orrs	r2, r1
 8007364:	609a      	str	r2, [r3, #8]

  /* set output data inversion mode */
  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
 8007366:	687b      	ldr	r3, [r7, #4]
 8007368:	681b      	ldr	r3, [r3, #0]
 800736a:	689b      	ldr	r3, [r3, #8]
 800736c:	f023 0180 	bic.w	r1, r3, #128	@ 0x80
 8007370:	687b      	ldr	r3, [r7, #4]
 8007372:	699a      	ldr	r2, [r3, #24]
 8007374:	687b      	ldr	r3, [r7, #4]
 8007376:	681b      	ldr	r3, [r3, #0]
 8007378:	430a      	orrs	r2, r1
 800737a:	609a      	str	r2, [r3, #8]
  /* makes sure the input data format (bytes, halfwords or words stream)
   * is properly specified by user */
  assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));

  /* Change CRC peripheral state */
  hcrc->State = HAL_CRC_STATE_READY;
 800737c:	687b      	ldr	r3, [r7, #4]
 800737e:	2201      	movs	r2, #1
 8007380:	775a      	strb	r2, [r3, #29]

  /* Return function status */
  return HAL_OK;
 8007382:	2300      	movs	r3, #0
}
 8007384:	4618      	mov	r0, r3
 8007386:	3708      	adds	r7, #8
 8007388:	46bd      	mov	sp, r7
 800738a:	bd80      	pop	{r7, pc}
 800738c:	04c11db7 	.word	0x04c11db7

08007390 <HAL_CRC_Calculate>:
  *        and the API will internally adjust its input data processing based on the
  *        handle field hcrc->InputDataFormat.
  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
  */
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
 8007390:	b580      	push	{r7, lr}
 8007392:	b086      	sub	sp, #24
 8007394:	af00      	add	r7, sp, #0
 8007396:	60f8      	str	r0, [r7, #12]
 8007398:	60b9      	str	r1, [r7, #8]
 800739a:	607a      	str	r2, [r7, #4]
  uint32_t index;      /* CRC input data buffer index */
  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
 800739c:	2300      	movs	r3, #0
 800739e:	613b      	str	r3, [r7, #16]

  /* Change CRC peripheral state */
  hcrc->State = HAL_CRC_STATE_BUSY;
 80073a0:	68fb      	ldr	r3, [r7, #12]
 80073a2:	2202      	movs	r2, #2
 80073a4:	775a      	strb	r2, [r3, #29]

  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
  *  written in hcrc->Instance->DR) */
  __HAL_CRC_DR_RESET(hcrc);
 80073a6:	68fb      	ldr	r3, [r7, #12]
 80073a8:	681b      	ldr	r3, [r3, #0]
 80073aa:	689a      	ldr	r2, [r3, #8]
 80073ac:	68fb      	ldr	r3, [r7, #12]
 80073ae:	681b      	ldr	r3, [r3, #0]
 80073b0:	f042 0201 	orr.w	r2, r2, #1
 80073b4:	609a      	str	r2, [r3, #8]

  switch (hcrc->InputDataFormat)
 80073b6:	68fb      	ldr	r3, [r7, #12]
 80073b8:	6a1b      	ldr	r3, [r3, #32]
 80073ba:	2b03      	cmp	r3, #3
 80073bc:	d006      	beq.n	80073cc <HAL_CRC_Calculate+0x3c>
 80073be:	2b03      	cmp	r3, #3
 80073c0:	d829      	bhi.n	8007416 <HAL_CRC_Calculate+0x86>
 80073c2:	2b01      	cmp	r3, #1
 80073c4:	d019      	beq.n	80073fa <HAL_CRC_Calculate+0x6a>
 80073c6:	2b02      	cmp	r3, #2
 80073c8:	d01e      	beq.n	8007408 <HAL_CRC_Calculate+0x78>
      /* Specific 16-bit input data handling  */
      temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
      break;

    default:
      break;
 80073ca:	e024      	b.n	8007416 <HAL_CRC_Calculate+0x86>
      for (index = 0U; index < BufferLength; index++)
 80073cc:	2300      	movs	r3, #0
 80073ce:	617b      	str	r3, [r7, #20]
 80073d0:	e00a      	b.n	80073e8 <HAL_CRC_Calculate+0x58>
        hcrc->Instance->DR = pBuffer[index];
 80073d2:	697b      	ldr	r3, [r7, #20]
 80073d4:	009b      	lsls	r3, r3, #2
 80073d6:	68ba      	ldr	r2, [r7, #8]
 80073d8:	441a      	add	r2, r3
 80073da:	68fb      	ldr	r3, [r7, #12]
 80073dc:	681b      	ldr	r3, [r3, #0]
 80073de:	6812      	ldr	r2, [r2, #0]
 80073e0:	601a      	str	r2, [r3, #0]
      for (index = 0U; index < BufferLength; index++)
 80073e2:	697b      	ldr	r3, [r7, #20]
 80073e4:	3301      	adds	r3, #1
 80073e6:	617b      	str	r3, [r7, #20]
 80073e8:	697a      	ldr	r2, [r7, #20]
 80073ea:	687b      	ldr	r3, [r7, #4]
 80073ec:	429a      	cmp	r2, r3
 80073ee:	d3f0      	bcc.n	80073d2 <HAL_CRC_Calculate+0x42>
      temp = hcrc->Instance->DR;
 80073f0:	68fb      	ldr	r3, [r7, #12]
 80073f2:	681b      	ldr	r3, [r3, #0]
 80073f4:	681b      	ldr	r3, [r3, #0]
 80073f6:	613b      	str	r3, [r7, #16]
      break;
 80073f8:	e00e      	b.n	8007418 <HAL_CRC_Calculate+0x88>
      temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
 80073fa:	687a      	ldr	r2, [r7, #4]
 80073fc:	68b9      	ldr	r1, [r7, #8]
 80073fe:	68f8      	ldr	r0, [r7, #12]
 8007400:	f000 f812 	bl	8007428 <CRC_Handle_8>
 8007404:	6138      	str	r0, [r7, #16]
      break;
 8007406:	e007      	b.n	8007418 <HAL_CRC_Calculate+0x88>
      temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
 8007408:	687a      	ldr	r2, [r7, #4]
 800740a:	68b9      	ldr	r1, [r7, #8]
 800740c:	68f8      	ldr	r0, [r7, #12]
 800740e:	f000 f899 	bl	8007544 <CRC_Handle_16>
 8007412:	6138      	str	r0, [r7, #16]
      break;
 8007414:	e000      	b.n	8007418 <HAL_CRC_Calculate+0x88>
      break;
 8007416:	bf00      	nop
  }

  /* Change CRC peripheral state */
  hcrc->State = HAL_CRC_STATE_READY;
 8007418:	68fb      	ldr	r3, [r7, #12]
 800741a:	2201      	movs	r2, #1
 800741c:	775a      	strb	r2, [r3, #29]

  /* Return the CRC computed value */
  return temp;
 800741e:	693b      	ldr	r3, [r7, #16]
}
 8007420:	4618      	mov	r0, r3
 8007422:	3718      	adds	r7, #24
 8007424:	46bd      	mov	sp, r7
 8007426:	bd80      	pop	{r7, pc}

08007428 <CRC_Handle_8>:
  * @param  pBuffer pointer to the input data buffer
  * @param  BufferLength input data buffer length
  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
  */
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
{
 8007428:	b480      	push	{r7}
 800742a:	b089      	sub	sp, #36	@ 0x24
 800742c:	af00      	add	r7, sp, #0
 800742e:	60f8      	str	r0, [r7, #12]
 8007430:	60b9      	str	r1, [r7, #8]
 8007432:	607a      	str	r2, [r7, #4]
  __IO uint16_t *pReg;

  /* Processing time optimization: 4 bytes are entered in a row with a single word write,
   * last bytes must be carefully fed to the CRC calculator to ensure a correct type
   * handling by the peripheral */
  for (i = 0U; i < (BufferLength / 4U); i++)
 8007434:	2300      	movs	r3, #0
 8007436:	61fb      	str	r3, [r7, #28]
 8007438:	e023      	b.n	8007482 <CRC_Handle_8+0x5a>
  {
    hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
 800743a:	69fb      	ldr	r3, [r7, #28]
 800743c:	009b      	lsls	r3, r3, #2
 800743e:	68ba      	ldr	r2, [r7, #8]
 8007440:	4413      	add	r3, r2
 8007442:	781b      	ldrb	r3, [r3, #0]
 8007444:	061a      	lsls	r2, r3, #24
                         ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
 8007446:	69fb      	ldr	r3, [r7, #28]
 8007448:	009b      	lsls	r3, r3, #2
 800744a:	3301      	adds	r3, #1
 800744c:	68b9      	ldr	r1, [r7, #8]
 800744e:	440b      	add	r3, r1
 8007450:	781b      	ldrb	r3, [r3, #0]
 8007452:	041b      	lsls	r3, r3, #16
    hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
 8007454:	431a      	orrs	r2, r3
                         ((uint32_t)pBuffer[(4U * i) + 2U] << 8U)  | \
 8007456:	69fb      	ldr	r3, [r7, #28]
 8007458:	009b      	lsls	r3, r3, #2
 800745a:	3302      	adds	r3, #2
 800745c:	68b9      	ldr	r1, [r7, #8]
 800745e:	440b      	add	r3, r1
 8007460:	781b      	ldrb	r3, [r3, #0]
 8007462:	021b      	lsls	r3, r3, #8
                         ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
 8007464:	431a      	orrs	r2, r3
                         (uint32_t)pBuffer[(4U * i) + 3U];
 8007466:	69fb      	ldr	r3, [r7, #28]
 8007468:	009b      	lsls	r3, r3, #2
 800746a:	3303      	adds	r3, #3
 800746c:	68b9      	ldr	r1, [r7, #8]
 800746e:	440b      	add	r3, r1
 8007470:	781b      	ldrb	r3, [r3, #0]
 8007472:	4619      	mov	r1, r3
    hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
 8007474:	68fb      	ldr	r3, [r7, #12]
 8007476:	681b      	ldr	r3, [r3, #0]
                         ((uint32_t)pBuffer[(4U * i) + 2U] << 8U)  | \
 8007478:	430a      	orrs	r2, r1
    hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
 800747a:	601a      	str	r2, [r3, #0]
  for (i = 0U; i < (BufferLength / 4U); i++)
 800747c:	69fb      	ldr	r3, [r7, #28]
 800747e:	3301      	adds	r3, #1
 8007480:	61fb      	str	r3, [r7, #28]
 8007482:	687b      	ldr	r3, [r7, #4]
 8007484:	089b      	lsrs	r3, r3, #2
 8007486:	69fa      	ldr	r2, [r7, #28]
 8007488:	429a      	cmp	r2, r3
 800748a:	d3d6      	bcc.n	800743a <CRC_Handle_8+0x12>
  }
  /* last bytes specific handling */
  if ((BufferLength % 4U) != 0U)
 800748c:	687b      	ldr	r3, [r7, #4]
 800748e:	f003 0303 	and.w	r3, r3, #3
 8007492:	2b00      	cmp	r3, #0
 8007494:	d04d      	beq.n	8007532 <CRC_Handle_8+0x10a>
  {
    if ((BufferLength % 4U) == 1U)
 8007496:	687b      	ldr	r3, [r7, #4]
 8007498:	f003 0303 	and.w	r3, r3, #3
 800749c:	2b01      	cmp	r3, #1
 800749e:	d107      	bne.n	80074b0 <CRC_Handle_8+0x88>
    {
      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i];         /* Derogation MisraC2012 R.11.5 */
 80074a0:	69fb      	ldr	r3, [r7, #28]
 80074a2:	009b      	lsls	r3, r3, #2
 80074a4:	68ba      	ldr	r2, [r7, #8]
 80074a6:	4413      	add	r3, r2
 80074a8:	68fa      	ldr	r2, [r7, #12]
 80074aa:	6812      	ldr	r2, [r2, #0]
 80074ac:	781b      	ldrb	r3, [r3, #0]
 80074ae:	7013      	strb	r3, [r2, #0]
    }
    if ((BufferLength % 4U) == 2U)
 80074b0:	687b      	ldr	r3, [r7, #4]
 80074b2:	f003 0303 	and.w	r3, r3, #3
 80074b6:	2b02      	cmp	r3, #2
 80074b8:	d116      	bne.n	80074e8 <CRC_Handle_8+0xc0>
    {
      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
 80074ba:	69fb      	ldr	r3, [r7, #28]
 80074bc:	009b      	lsls	r3, r3, #2
 80074be:	68ba      	ldr	r2, [r7, #8]
 80074c0:	4413      	add	r3, r2
 80074c2:	781b      	ldrb	r3, [r3, #0]
 80074c4:	021b      	lsls	r3, r3, #8
 80074c6:	b21a      	sxth	r2, r3
 80074c8:	69fb      	ldr	r3, [r7, #28]
 80074ca:	009b      	lsls	r3, r3, #2
 80074cc:	3301      	adds	r3, #1
 80074ce:	68b9      	ldr	r1, [r7, #8]
 80074d0:	440b      	add	r3, r1
 80074d2:	781b      	ldrb	r3, [r3, #0]
 80074d4:	b21b      	sxth	r3, r3
 80074d6:	4313      	orrs	r3, r2
 80074d8:	b21b      	sxth	r3, r3
 80074da:	837b      	strh	r3, [r7, #26]
      pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
 80074dc:	68fb      	ldr	r3, [r7, #12]
 80074de:	681b      	ldr	r3, [r3, #0]
 80074e0:	617b      	str	r3, [r7, #20]
      *pReg = data;
 80074e2:	697b      	ldr	r3, [r7, #20]
 80074e4:	8b7a      	ldrh	r2, [r7, #26]
 80074e6:	801a      	strh	r2, [r3, #0]
    }
    if ((BufferLength % 4U) == 3U)
 80074e8:	687b      	ldr	r3, [r7, #4]
 80074ea:	f003 0303 	and.w	r3, r3, #3
 80074ee:	2b03      	cmp	r3, #3
 80074f0:	d11f      	bne.n	8007532 <CRC_Handle_8+0x10a>
    {
      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
 80074f2:	69fb      	ldr	r3, [r7, #28]
 80074f4:	009b      	lsls	r3, r3, #2
 80074f6:	68ba      	ldr	r2, [r7, #8]
 80074f8:	4413      	add	r3, r2
 80074fa:	781b      	ldrb	r3, [r3, #0]
 80074fc:	021b      	lsls	r3, r3, #8
 80074fe:	b21a      	sxth	r2, r3
 8007500:	69fb      	ldr	r3, [r7, #28]
 8007502:	009b      	lsls	r3, r3, #2
 8007504:	3301      	adds	r3, #1
 8007506:	68b9      	ldr	r1, [r7, #8]
 8007508:	440b      	add	r3, r1
 800750a:	781b      	ldrb	r3, [r3, #0]
 800750c:	b21b      	sxth	r3, r3
 800750e:	4313      	orrs	r3, r2
 8007510:	b21b      	sxth	r3, r3
 8007512:	837b      	strh	r3, [r7, #26]
      pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
 8007514:	68fb      	ldr	r3, [r7, #12]
 8007516:	681b      	ldr	r3, [r3, #0]
 8007518:	617b      	str	r3, [r7, #20]
      *pReg = data;
 800751a:	697b      	ldr	r3, [r7, #20]
 800751c:	8b7a      	ldrh	r2, [r7, #26]
 800751e:	801a      	strh	r2, [r3, #0]

      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U];  /* Derogation MisraC2012 R.11.5 */
 8007520:	69fb      	ldr	r3, [r7, #28]
 8007522:	009b      	lsls	r3, r3, #2
 8007524:	3302      	adds	r3, #2
 8007526:	68ba      	ldr	r2, [r7, #8]
 8007528:	4413      	add	r3, r2
 800752a:	68fa      	ldr	r2, [r7, #12]
 800752c:	6812      	ldr	r2, [r2, #0]
 800752e:	781b      	ldrb	r3, [r3, #0]
 8007530:	7013      	strb	r3, [r2, #0]
    }
  }

  /* Return the CRC computed value */
  return hcrc->Instance->DR;
 8007532:	68fb      	ldr	r3, [r7, #12]
 8007534:	681b      	ldr	r3, [r3, #0]
 8007536:	681b      	ldr	r3, [r3, #0]
}
 8007538:	4618      	mov	r0, r3
 800753a:	3724      	adds	r7, #36	@ 0x24
 800753c:	46bd      	mov	sp, r7
 800753e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007542:	4770      	bx	lr

08007544 <CRC_Handle_16>:
  * @param  pBuffer pointer to the input data buffer
  * @param  BufferLength input data buffer length
  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
  */
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{
 8007544:	b480      	push	{r7}
 8007546:	b087      	sub	sp, #28
 8007548:	af00      	add	r7, sp, #0
 800754a:	60f8      	str	r0, [r7, #12]
 800754c:	60b9      	str	r1, [r7, #8]
 800754e:	607a      	str	r2, [r7, #4]
  __IO uint16_t *pReg;

  /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
   * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
   * a correct type handling by the peripheral */
  for (i = 0U; i < (BufferLength / 2U); i++)
 8007550:	2300      	movs	r3, #0
 8007552:	617b      	str	r3, [r7, #20]
 8007554:	e013      	b.n	800757e <CRC_Handle_16+0x3a>
  {
    hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
 8007556:	697b      	ldr	r3, [r7, #20]
 8007558:	009b      	lsls	r3, r3, #2
 800755a:	68ba      	ldr	r2, [r7, #8]
 800755c:	4413      	add	r3, r2
 800755e:	881b      	ldrh	r3, [r3, #0]
 8007560:	041a      	lsls	r2, r3, #16
 8007562:	697b      	ldr	r3, [r7, #20]
 8007564:	009b      	lsls	r3, r3, #2
 8007566:	3302      	adds	r3, #2
 8007568:	68b9      	ldr	r1, [r7, #8]
 800756a:	440b      	add	r3, r1
 800756c:	881b      	ldrh	r3, [r3, #0]
 800756e:	4619      	mov	r1, r3
 8007570:	68fb      	ldr	r3, [r7, #12]
 8007572:	681b      	ldr	r3, [r3, #0]
 8007574:	430a      	orrs	r2, r1
 8007576:	601a      	str	r2, [r3, #0]
  for (i = 0U; i < (BufferLength / 2U); i++)
 8007578:	697b      	ldr	r3, [r7, #20]
 800757a:	3301      	adds	r3, #1
 800757c:	617b      	str	r3, [r7, #20]
 800757e:	687b      	ldr	r3, [r7, #4]
 8007580:	085b      	lsrs	r3, r3, #1
 8007582:	697a      	ldr	r2, [r7, #20]
 8007584:	429a      	cmp	r2, r3
 8007586:	d3e6      	bcc.n	8007556 <CRC_Handle_16+0x12>
  }
  if ((BufferLength % 2U) != 0U)
 8007588:	687b      	ldr	r3, [r7, #4]
 800758a:	f003 0301 	and.w	r3, r3, #1
 800758e:	2b00      	cmp	r3, #0
 8007590:	d009      	beq.n	80075a6 <CRC_Handle_16+0x62>
  {
    pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                 /* Derogation MisraC2012 R.11.5 */
 8007592:	68fb      	ldr	r3, [r7, #12]
 8007594:	681b      	ldr	r3, [r3, #0]
 8007596:	613b      	str	r3, [r7, #16]
    *pReg = pBuffer[2U * i];
 8007598:	697b      	ldr	r3, [r7, #20]
 800759a:	009b      	lsls	r3, r3, #2
 800759c:	68ba      	ldr	r2, [r7, #8]
 800759e:	4413      	add	r3, r2
 80075a0:	881a      	ldrh	r2, [r3, #0]
 80075a2:	693b      	ldr	r3, [r7, #16]
 80075a4:	801a      	strh	r2, [r3, #0]
  }

  /* Return the CRC computed value */
  return hcrc->Instance->DR;
 80075a6:	68fb      	ldr	r3, [r7, #12]
 80075a8:	681b      	ldr	r3, [r3, #0]
 80075aa:	681b      	ldr	r3, [r3, #0]
}
 80075ac:	4618      	mov	r0, r3
 80075ae:	371c      	adds	r7, #28
 80075b0:	46bd      	mov	sp, r7
 80075b2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80075b6:	4770      	bx	lr

080075b8 <HAL_CRCEx_Polynomial_Set>:
  *          @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
  *          @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
 80075b8:	b480      	push	{r7}
 80075ba:	b087      	sub	sp, #28
 80075bc:	af00      	add	r7, sp, #0
 80075be:	60f8      	str	r0, [r7, #12]
 80075c0:	60b9      	str	r1, [r7, #8]
 80075c2:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 80075c4:	2300      	movs	r3, #0
 80075c6:	75fb      	strb	r3, [r7, #23]
  uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
 80075c8:	231f      	movs	r3, #31
 80075ca:	613b      	str	r3, [r7, #16]

  /* Check the parameters */
  assert_param(IS_CRC_POL_LENGTH(PolyLength));

  /* Ensure that the generating polynomial is odd */
  if ((Pol & (uint32_t)(0x1U)) ==  0U)
 80075cc:	68bb      	ldr	r3, [r7, #8]
 80075ce:	f003 0301 	and.w	r3, r3, #1
 80075d2:	2b00      	cmp	r3, #0
 80075d4:	d102      	bne.n	80075dc <HAL_CRCEx_Polynomial_Set+0x24>
  {
    status =  HAL_ERROR;
 80075d6:	2301      	movs	r3, #1
 80075d8:	75fb      	strb	r3, [r7, #23]
 80075da:	e063      	b.n	80076a4 <HAL_CRCEx_Polynomial_Set+0xec>
     * definition. HAL_ERROR is reported if Pol degree is
     * larger than that indicated by PolyLength.
     * Look for MSB position: msb will contain the degree of
     *  the second to the largest polynomial member. E.g., for
     *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
    while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
 80075dc:	bf00      	nop
 80075de:	693b      	ldr	r3, [r7, #16]
 80075e0:	1e5a      	subs	r2, r3, #1
 80075e2:	613a      	str	r2, [r7, #16]
 80075e4:	2b00      	cmp	r3, #0
 80075e6:	d009      	beq.n	80075fc <HAL_CRCEx_Polynomial_Set+0x44>
 80075e8:	693b      	ldr	r3, [r7, #16]
 80075ea:	f003 031f 	and.w	r3, r3, #31
 80075ee:	68ba      	ldr	r2, [r7, #8]
 80075f0:	fa22 f303 	lsr.w	r3, r2, r3
 80075f4:	f003 0301 	and.w	r3, r3, #1
 80075f8:	2b00      	cmp	r3, #0
 80075fa:	d0f0      	beq.n	80075de <HAL_CRCEx_Polynomial_Set+0x26>
    {
    }

    switch (PolyLength)
 80075fc:	687b      	ldr	r3, [r7, #4]
 80075fe:	2b18      	cmp	r3, #24
 8007600:	d846      	bhi.n	8007690 <HAL_CRCEx_Polynomial_Set+0xd8>
 8007602:	a201      	add	r2, pc, #4	@ (adr r2, 8007608 <HAL_CRCEx_Polynomial_Set+0x50>)
 8007604:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8007608:	08007697 	.word	0x08007697
 800760c:	08007691 	.word	0x08007691
 8007610:	08007691 	.word	0x08007691
 8007614:	08007691 	.word	0x08007691
 8007618:	08007691 	.word	0x08007691
 800761c:	08007691 	.word	0x08007691
 8007620:	08007691 	.word	0x08007691
 8007624:	08007691 	.word	0x08007691
 8007628:	08007685 	.word	0x08007685
 800762c:	08007691 	.word	0x08007691
 8007630:	08007691 	.word	0x08007691
 8007634:	08007691 	.word	0x08007691
 8007638:	08007691 	.word	0x08007691
 800763c:	08007691 	.word	0x08007691
 8007640:	08007691 	.word	0x08007691
 8007644:	08007691 	.word	0x08007691
 8007648:	08007679 	.word	0x08007679
 800764c:	08007691 	.word	0x08007691
 8007650:	08007691 	.word	0x08007691
 8007654:	08007691 	.word	0x08007691
 8007658:	08007691 	.word	0x08007691
 800765c:	08007691 	.word	0x08007691
 8007660:	08007691 	.word	0x08007691
 8007664:	08007691 	.word	0x08007691
 8007668:	0800766d 	.word	0x0800766d
    {

      case CRC_POLYLENGTH_7B:
        if (msb >= HAL_CRC_LENGTH_7B)
 800766c:	693b      	ldr	r3, [r7, #16]
 800766e:	2b06      	cmp	r3, #6
 8007670:	d913      	bls.n	800769a <HAL_CRCEx_Polynomial_Set+0xe2>
        {
          status =   HAL_ERROR;
 8007672:	2301      	movs	r3, #1
 8007674:	75fb      	strb	r3, [r7, #23]
        }
        break;
 8007676:	e010      	b.n	800769a <HAL_CRCEx_Polynomial_Set+0xe2>
      case CRC_POLYLENGTH_8B:
        if (msb >= HAL_CRC_LENGTH_8B)
 8007678:	693b      	ldr	r3, [r7, #16]
 800767a:	2b07      	cmp	r3, #7
 800767c:	d90f      	bls.n	800769e <HAL_CRCEx_Polynomial_Set+0xe6>
        {
          status =   HAL_ERROR;
 800767e:	2301      	movs	r3, #1
 8007680:	75fb      	strb	r3, [r7, #23]
        }
        break;
 8007682:	e00c      	b.n	800769e <HAL_CRCEx_Polynomial_Set+0xe6>
      case CRC_POLYLENGTH_16B:
        if (msb >= HAL_CRC_LENGTH_16B)
 8007684:	693b      	ldr	r3, [r7, #16]
 8007686:	2b0f      	cmp	r3, #15
 8007688:	d90b      	bls.n	80076a2 <HAL_CRCEx_Polynomial_Set+0xea>
        {
          status =   HAL_ERROR;
 800768a:	2301      	movs	r3, #1
 800768c:	75fb      	strb	r3, [r7, #23]
        }
        break;
 800768e:	e008      	b.n	80076a2 <HAL_CRCEx_Polynomial_Set+0xea>

      case CRC_POLYLENGTH_32B:
        /* no polynomial definition vs. polynomial length issue possible */
        break;
      default:
        status =  HAL_ERROR;
 8007690:	2301      	movs	r3, #1
 8007692:	75fb      	strb	r3, [r7, #23]
        break;
 8007694:	e006      	b.n	80076a4 <HAL_CRCEx_Polynomial_Set+0xec>
        break;
 8007696:	bf00      	nop
 8007698:	e004      	b.n	80076a4 <HAL_CRCEx_Polynomial_Set+0xec>
        break;
 800769a:	bf00      	nop
 800769c:	e002      	b.n	80076a4 <HAL_CRCEx_Polynomial_Set+0xec>
        break;
 800769e:	bf00      	nop
 80076a0:	e000      	b.n	80076a4 <HAL_CRCEx_Polynomial_Set+0xec>
        break;
 80076a2:	bf00      	nop
    }
  }
  if (status == HAL_OK)
 80076a4:	7dfb      	ldrb	r3, [r7, #23]
 80076a6:	2b00      	cmp	r3, #0
 80076a8:	d10d      	bne.n	80076c6 <HAL_CRCEx_Polynomial_Set+0x10e>
  {
    /* set generating polynomial */
    WRITE_REG(hcrc->Instance->POL, Pol);
 80076aa:	68fb      	ldr	r3, [r7, #12]
 80076ac:	681b      	ldr	r3, [r3, #0]
 80076ae:	68ba      	ldr	r2, [r7, #8]
 80076b0:	615a      	str	r2, [r3, #20]

    /* set generating polynomial size */
    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
 80076b2:	68fb      	ldr	r3, [r7, #12]
 80076b4:	681b      	ldr	r3, [r3, #0]
 80076b6:	689b      	ldr	r3, [r3, #8]
 80076b8:	f023 0118 	bic.w	r1, r3, #24
 80076bc:	68fb      	ldr	r3, [r7, #12]
 80076be:	681b      	ldr	r3, [r3, #0]
 80076c0:	687a      	ldr	r2, [r7, #4]
 80076c2:	430a      	orrs	r2, r1
 80076c4:	609a      	str	r2, [r3, #8]
  }
  /* Return function status */
  return status;
 80076c6:	7dfb      	ldrb	r3, [r7, #23]
}
 80076c8:	4618      	mov	r0, r3
 80076ca:	371c      	adds	r7, #28
 80076cc:	46bd      	mov	sp, r7
 80076ce:	f85d 7b04 	ldr.w	r7, [sp], #4
 80076d2:	4770      	bx	lr

080076d4 <HAL_DAC_Init>:
  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
  *         the configuration information for the specified DAC.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
{
 80076d4:	b580      	push	{r7, lr}
 80076d6:	b082      	sub	sp, #8
 80076d8:	af00      	add	r7, sp, #0
 80076da:	6078      	str	r0, [r7, #4]
  /* Check the DAC peripheral handle */
  if (hdac == NULL)
 80076dc:	687b      	ldr	r3, [r7, #4]
 80076de:	2b00      	cmp	r3, #0
 80076e0:	d101      	bne.n	80076e6 <HAL_DAC_Init+0x12>
  {
    return HAL_ERROR;
 80076e2:	2301      	movs	r3, #1
 80076e4:	e014      	b.n	8007710 <HAL_DAC_Init+0x3c>
  }
  /* Check the parameters */
  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));

  if (hdac->State == HAL_DAC_STATE_RESET)
 80076e6:	687b      	ldr	r3, [r7, #4]
 80076e8:	791b      	ldrb	r3, [r3, #4]
 80076ea:	b2db      	uxtb	r3, r3
 80076ec:	2b00      	cmp	r3, #0
 80076ee:	d105      	bne.n	80076fc <HAL_DAC_Init+0x28>
      hdac->MspInitCallback             = HAL_DAC_MspInit;
    }
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */

    /* Allocate lock resource and initialize it */
    hdac->Lock = HAL_UNLOCKED;
 80076f0:	687b      	ldr	r3, [r7, #4]
 80076f2:	2200      	movs	r2, #0
 80076f4:	715a      	strb	r2, [r3, #5]
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
    /* Init the low level hardware */
    hdac->MspInitCallback(hdac);
#else
    /* Init the low level hardware */
    HAL_DAC_MspInit(hdac);
 80076f6:	6878      	ldr	r0, [r7, #4]
 80076f8:	f7fc f8d8 	bl	80038ac <HAL_DAC_MspInit>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
  }

  /* Initialize the DAC state*/
  hdac->State = HAL_DAC_STATE_BUSY;
 80076fc:	687b      	ldr	r3, [r7, #4]
 80076fe:	2202      	movs	r2, #2
 8007700:	711a      	strb	r2, [r3, #4]

  /* Set DAC error code to none */
  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
 8007702:	687b      	ldr	r3, [r7, #4]
 8007704:	2200      	movs	r2, #0
 8007706:	611a      	str	r2, [r3, #16]

  /* Initialize the DAC state*/
  hdac->State = HAL_DAC_STATE_READY;
 8007708:	687b      	ldr	r3, [r7, #4]
 800770a:	2201      	movs	r2, #1
 800770c:	711a      	strb	r2, [r3, #4]

  /* Return function status */
  return HAL_OK;
 800770e:	2300      	movs	r3, #0
}
 8007710:	4618      	mov	r0, r3
 8007712:	3708      	adds	r7, #8
 8007714:	46bd      	mov	sp, r7
 8007716:	bd80      	pop	{r7, pc}

08007718 <HAL_DAC_Start>:
  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
 8007718:	b480      	push	{r7}
 800771a:	b083      	sub	sp, #12
 800771c:	af00      	add	r7, sp, #0
 800771e:	6078      	str	r0, [r7, #4]
 8007720:	6039      	str	r1, [r7, #0]
  /* Check the DAC peripheral handle */
  if (hdac == NULL)
 8007722:	687b      	ldr	r3, [r7, #4]
 8007724:	2b00      	cmp	r3, #0
 8007726:	d101      	bne.n	800772c <HAL_DAC_Start+0x14>
  {
    return HAL_ERROR;
 8007728:	2301      	movs	r3, #1
 800772a:	e046      	b.n	80077ba <HAL_DAC_Start+0xa2>

  /* Check the parameters */
  assert_param(IS_DAC_CHANNEL(Channel));

  /* Process locked */
  __HAL_LOCK(hdac);
 800772c:	687b      	ldr	r3, [r7, #4]
 800772e:	795b      	ldrb	r3, [r3, #5]
 8007730:	2b01      	cmp	r3, #1
 8007732:	d101      	bne.n	8007738 <HAL_DAC_Start+0x20>
 8007734:	2302      	movs	r3, #2
 8007736:	e040      	b.n	80077ba <HAL_DAC_Start+0xa2>
 8007738:	687b      	ldr	r3, [r7, #4]
 800773a:	2201      	movs	r2, #1
 800773c:	715a      	strb	r2, [r3, #5]

  /* Change DAC state */
  hdac->State = HAL_DAC_STATE_BUSY;
 800773e:	687b      	ldr	r3, [r7, #4]
 8007740:	2202      	movs	r2, #2
 8007742:	711a      	strb	r2, [r3, #4]

  /* Enable the Peripheral */
  __HAL_DAC_ENABLE(hdac, Channel);
 8007744:	687b      	ldr	r3, [r7, #4]
 8007746:	681b      	ldr	r3, [r3, #0]
 8007748:	6819      	ldr	r1, [r3, #0]
 800774a:	683b      	ldr	r3, [r7, #0]
 800774c:	f003 0310 	and.w	r3, r3, #16
 8007750:	2201      	movs	r2, #1
 8007752:	409a      	lsls	r2, r3
 8007754:	687b      	ldr	r3, [r7, #4]
 8007756:	681b      	ldr	r3, [r3, #0]
 8007758:	430a      	orrs	r2, r1
 800775a:	601a      	str	r2, [r3, #0]

  if (Channel == DAC_CHANNEL_1)
 800775c:	683b      	ldr	r3, [r7, #0]
 800775e:	2b00      	cmp	r3, #0
 8007760:	d10f      	bne.n	8007782 <HAL_DAC_Start+0x6a>
  {
    /* Check if software trigger enabled */
    if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
 8007762:	687b      	ldr	r3, [r7, #4]
 8007764:	681b      	ldr	r3, [r3, #0]
 8007766:	681b      	ldr	r3, [r3, #0]
 8007768:	f003 033e 	and.w	r3, r3, #62	@ 0x3e
 800776c:	2b02      	cmp	r3, #2
 800776e:	d11d      	bne.n	80077ac <HAL_DAC_Start+0x94>
    {
      /* Enable the selected DAC software conversion */
      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
 8007770:	687b      	ldr	r3, [r7, #4]
 8007772:	681b      	ldr	r3, [r3, #0]
 8007774:	685a      	ldr	r2, [r3, #4]
 8007776:	687b      	ldr	r3, [r7, #4]
 8007778:	681b      	ldr	r3, [r3, #0]
 800777a:	f042 0201 	orr.w	r2, r2, #1
 800777e:	605a      	str	r2, [r3, #4]
 8007780:	e014      	b.n	80077ac <HAL_DAC_Start+0x94>
  }

  else
  {
    /* Check if software trigger enabled */
    if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
 8007782:	687b      	ldr	r3, [r7, #4]
 8007784:	681b      	ldr	r3, [r3, #0]
 8007786:	681b      	ldr	r3, [r3, #0]
 8007788:	f403 1278 	and.w	r2, r3, #4063232	@ 0x3e0000
 800778c:	683b      	ldr	r3, [r7, #0]
 800778e:	f003 0310 	and.w	r3, r3, #16
 8007792:	2102      	movs	r1, #2
 8007794:	fa01 f303 	lsl.w	r3, r1, r3
 8007798:	429a      	cmp	r2, r3
 800779a:	d107      	bne.n	80077ac <HAL_DAC_Start+0x94>
    {
      /* Enable the selected DAC software conversion*/
      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
 800779c:	687b      	ldr	r3, [r7, #4]
 800779e:	681b      	ldr	r3, [r3, #0]
 80077a0:	685a      	ldr	r2, [r3, #4]
 80077a2:	687b      	ldr	r3, [r7, #4]
 80077a4:	681b      	ldr	r3, [r3, #0]
 80077a6:	f042 0202 	orr.w	r2, r2, #2
 80077aa:	605a      	str	r2, [r3, #4]
    }
  }


  /* Change DAC state */
  hdac->State = HAL_DAC_STATE_READY;
 80077ac:	687b      	ldr	r3, [r7, #4]
 80077ae:	2201      	movs	r2, #1
 80077b0:	711a      	strb	r2, [r3, #4]

  /* Process unlocked */
  __HAL_UNLOCK(hdac);
 80077b2:	687b      	ldr	r3, [r7, #4]
 80077b4:	2200      	movs	r2, #0
 80077b6:	715a      	strb	r2, [r3, #5]

  /* Return function status */
  return HAL_OK;
 80077b8:	2300      	movs	r3, #0
}
 80077ba:	4618      	mov	r0, r3
 80077bc:	370c      	adds	r7, #12
 80077be:	46bd      	mov	sp, r7
 80077c0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80077c4:	4770      	bx	lr

080077c6 <HAL_DAC_IRQHandler>:
  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
  *         the configuration information for the specified DAC.
  * @retval None
  */
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
{
 80077c6:	b580      	push	{r7, lr}
 80077c8:	b084      	sub	sp, #16
 80077ca:	af00      	add	r7, sp, #0
 80077cc:	6078      	str	r0, [r7, #4]
  uint32_t itsource = hdac->Instance->CR;
 80077ce:	687b      	ldr	r3, [r7, #4]
 80077d0:	681b      	ldr	r3, [r3, #0]
 80077d2:	681b      	ldr	r3, [r3, #0]
 80077d4:	60fb      	str	r3, [r7, #12]
  uint32_t itflag   = hdac->Instance->SR;
 80077d6:	687b      	ldr	r3, [r7, #4]
 80077d8:	681b      	ldr	r3, [r3, #0]
 80077da:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 80077dc:	60bb      	str	r3, [r7, #8]

  if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
 80077de:	68fb      	ldr	r3, [r7, #12]
 80077e0:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 80077e4:	2b00      	cmp	r3, #0
 80077e6:	d01d      	beq.n	8007824 <HAL_DAC_IRQHandler+0x5e>
  {
    /* Check underrun flag of DAC channel 1 */
    if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
 80077e8:	68bb      	ldr	r3, [r7, #8]
 80077ea:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 80077ee:	2b00      	cmp	r3, #0
 80077f0:	d018      	beq.n	8007824 <HAL_DAC_IRQHandler+0x5e>
    {
      /* Change DAC state to error state */
      hdac->State = HAL_DAC_STATE_ERROR;
 80077f2:	687b      	ldr	r3, [r7, #4]
 80077f4:	2204      	movs	r2, #4
 80077f6:	711a      	strb	r2, [r3, #4]

      /* Set DAC error code to channel1 DMA underrun error */
      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
 80077f8:	687b      	ldr	r3, [r7, #4]
 80077fa:	691b      	ldr	r3, [r3, #16]
 80077fc:	f043 0201 	orr.w	r2, r3, #1
 8007800:	687b      	ldr	r3, [r7, #4]
 8007802:	611a      	str	r2, [r3, #16]

      /* Clear the underrun flag */
      __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
 8007804:	687b      	ldr	r3, [r7, #4]
 8007806:	681b      	ldr	r3, [r3, #0]
 8007808:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
 800780c:	635a      	str	r2, [r3, #52]	@ 0x34

      /* Disable the selected DAC channel1 DMA request */
      __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
 800780e:	687b      	ldr	r3, [r7, #4]
 8007810:	681b      	ldr	r3, [r3, #0]
 8007812:	681a      	ldr	r2, [r3, #0]
 8007814:	687b      	ldr	r3, [r7, #4]
 8007816:	681b      	ldr	r3, [r3, #0]
 8007818:	f422 5280 	bic.w	r2, r2, #4096	@ 0x1000
 800781c:	601a      	str	r2, [r3, #0]

      /* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
      hdac->DMAUnderrunCallbackCh1(hdac);
#else
      HAL_DAC_DMAUnderrunCallbackCh1(hdac);
 800781e:	6878      	ldr	r0, [r7, #4]
 8007820:	f000 f851 	bl	80078c6 <HAL_DAC_DMAUnderrunCallbackCh1>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
    }
  }


  if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
 8007824:	68fb      	ldr	r3, [r7, #12]
 8007826:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800782a:	2b00      	cmp	r3, #0
 800782c:	d01d      	beq.n	800786a <HAL_DAC_IRQHandler+0xa4>
  {
    /* Check underrun flag of DAC channel 2 */
    if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
 800782e:	68bb      	ldr	r3, [r7, #8]
 8007830:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 8007834:	2b00      	cmp	r3, #0
 8007836:	d018      	beq.n	800786a <HAL_DAC_IRQHandler+0xa4>
    {
      /* Change DAC state to error state */
      hdac->State = HAL_DAC_STATE_ERROR;
 8007838:	687b      	ldr	r3, [r7, #4]
 800783a:	2204      	movs	r2, #4
 800783c:	711a      	strb	r2, [r3, #4]

      /* Set DAC error code to channel2 DMA underrun error */
      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
 800783e:	687b      	ldr	r3, [r7, #4]
 8007840:	691b      	ldr	r3, [r3, #16]
 8007842:	f043 0202 	orr.w	r2, r3, #2
 8007846:	687b      	ldr	r3, [r7, #4]
 8007848:	611a      	str	r2, [r3, #16]

      /* Clear the underrun flag */
      __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
 800784a:	687b      	ldr	r3, [r7, #4]
 800784c:	681b      	ldr	r3, [r3, #0]
 800784e:	f04f 5200 	mov.w	r2, #536870912	@ 0x20000000
 8007852:	635a      	str	r2, [r3, #52]	@ 0x34

      /* Disable the selected DAC channel2 DMA request */
      __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
 8007854:	687b      	ldr	r3, [r7, #4]
 8007856:	681b      	ldr	r3, [r3, #0]
 8007858:	681a      	ldr	r2, [r3, #0]
 800785a:	687b      	ldr	r3, [r7, #4]
 800785c:	681b      	ldr	r3, [r3, #0]
 800785e:	f022 5280 	bic.w	r2, r2, #268435456	@ 0x10000000
 8007862:	601a      	str	r2, [r3, #0]

      /* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
      hdac->DMAUnderrunCallbackCh2(hdac);
#else
      HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
 8007864:	6878      	ldr	r0, [r7, #4]
 8007866:	f000 f97b 	bl	8007b60 <HAL_DACEx_DMAUnderrunCallbackCh2>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
    }
  }

}
 800786a:	bf00      	nop
 800786c:	3710      	adds	r7, #16
 800786e:	46bd      	mov	sp, r7
 8007870:	bd80      	pop	{r7, pc}

08007872 <HAL_DAC_SetValue>:
  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
  * @param  Data Data to be loaded in the selected data holding register.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
 8007872:	b480      	push	{r7}
 8007874:	b087      	sub	sp, #28
 8007876:	af00      	add	r7, sp, #0
 8007878:	60f8      	str	r0, [r7, #12]
 800787a:	60b9      	str	r1, [r7, #8]
 800787c:	607a      	str	r2, [r7, #4]
 800787e:	603b      	str	r3, [r7, #0]
  __IO uint32_t tmp = 0UL;
 8007880:	2300      	movs	r3, #0
 8007882:	617b      	str	r3, [r7, #20]

  /* Check the DAC peripheral handle */
  if (hdac == NULL)
 8007884:	68fb      	ldr	r3, [r7, #12]
 8007886:	2b00      	cmp	r3, #0
 8007888:	d101      	bne.n	800788e <HAL_DAC_SetValue+0x1c>
  {
    return HAL_ERROR;
 800788a:	2301      	movs	r3, #1
 800788c:	e015      	b.n	80078ba <HAL_DAC_SetValue+0x48>
  /* Check the parameters */
  assert_param(IS_DAC_CHANNEL(Channel));
  assert_param(IS_DAC_ALIGN(Alignment));
  assert_param(IS_DAC_DATA(Data));

  tmp = (uint32_t)hdac->Instance;
 800788e:	68fb      	ldr	r3, [r7, #12]
 8007890:	681b      	ldr	r3, [r3, #0]
 8007892:	617b      	str	r3, [r7, #20]
  if (Channel == DAC_CHANNEL_1)
 8007894:	68bb      	ldr	r3, [r7, #8]
 8007896:	2b00      	cmp	r3, #0
 8007898:	d105      	bne.n	80078a6 <HAL_DAC_SetValue+0x34>
  {
    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
 800789a:	697a      	ldr	r2, [r7, #20]
 800789c:	687b      	ldr	r3, [r7, #4]
 800789e:	4413      	add	r3, r2
 80078a0:	3308      	adds	r3, #8
 80078a2:	617b      	str	r3, [r7, #20]
 80078a4:	e004      	b.n	80078b0 <HAL_DAC_SetValue+0x3e>
  }

  else
  {
    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
 80078a6:	697a      	ldr	r2, [r7, #20]
 80078a8:	687b      	ldr	r3, [r7, #4]
 80078aa:	4413      	add	r3, r2
 80078ac:	3314      	adds	r3, #20
 80078ae:	617b      	str	r3, [r7, #20]
  }


  /* Set the DAC channel selected data holding register */
  *(__IO uint32_t *) tmp = Data;
 80078b0:	697b      	ldr	r3, [r7, #20]
 80078b2:	461a      	mov	r2, r3
 80078b4:	683b      	ldr	r3, [r7, #0]
 80078b6:	6013      	str	r3, [r2, #0]

  /* Return function status */
  return HAL_OK;
 80078b8:	2300      	movs	r3, #0
}
 80078ba:	4618      	mov	r0, r3
 80078bc:	371c      	adds	r7, #28
 80078be:	46bd      	mov	sp, r7
 80078c0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80078c4:	4770      	bx	lr

080078c6 <HAL_DAC_DMAUnderrunCallbackCh1>:
  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
  *         the configuration information for the specified DAC.
  * @retval None
  */
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
{
 80078c6:	b480      	push	{r7}
 80078c8:	b083      	sub	sp, #12
 80078ca:	af00      	add	r7, sp, #0
 80078cc:	6078      	str	r0, [r7, #4]
  UNUSED(hdac);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
   */
}
 80078ce:	bf00      	nop
 80078d0:	370c      	adds	r7, #12
 80078d2:	46bd      	mov	sp, r7
 80078d4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80078d8:	4770      	bx	lr
	...

080078dc <HAL_DAC_ConfigChannel>:
  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
                                        const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
 80078dc:	b580      	push	{r7, lr}
 80078de:	b08a      	sub	sp, #40	@ 0x28
 80078e0:	af00      	add	r7, sp, #0
 80078e2:	60f8      	str	r0, [r7, #12]
 80078e4:	60b9      	str	r1, [r7, #8]
 80078e6:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 80078e8:	2300      	movs	r3, #0
 80078ea:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
  uint32_t tmpreg2;
  uint32_t tickstart;
  uint32_t connectOnChip;

  /* Check the DAC peripheral handle and channel configuration struct */
  if ((hdac == NULL) || (sConfig == NULL))
 80078ee:	68fb      	ldr	r3, [r7, #12]
 80078f0:	2b00      	cmp	r3, #0
 80078f2:	d002      	beq.n	80078fa <HAL_DAC_ConfigChannel+0x1e>
 80078f4:	68bb      	ldr	r3, [r7, #8]
 80078f6:	2b00      	cmp	r3, #0
 80078f8:	d101      	bne.n	80078fe <HAL_DAC_ConfigChannel+0x22>
  {
    return HAL_ERROR;
 80078fa:	2301      	movs	r3, #1
 80078fc:	e12a      	b.n	8007b54 <HAL_DAC_ConfigChannel+0x278>
    assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
  }
  assert_param(IS_DAC_CHANNEL(Channel));

  /* Process locked */
  __HAL_LOCK(hdac);
 80078fe:	68fb      	ldr	r3, [r7, #12]
 8007900:	795b      	ldrb	r3, [r3, #5]
 8007902:	2b01      	cmp	r3, #1
 8007904:	d101      	bne.n	800790a <HAL_DAC_ConfigChannel+0x2e>
 8007906:	2302      	movs	r3, #2
 8007908:	e124      	b.n	8007b54 <HAL_DAC_ConfigChannel+0x278>
 800790a:	68fb      	ldr	r3, [r7, #12]
 800790c:	2201      	movs	r2, #1
 800790e:	715a      	strb	r2, [r3, #5]

  /* Change DAC state */
  hdac->State = HAL_DAC_STATE_BUSY;
 8007910:	68fb      	ldr	r3, [r7, #12]
 8007912:	2202      	movs	r2, #2
 8007914:	711a      	strb	r2, [r3, #4]

  /* Sample and hold configuration */
  if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
 8007916:	68bb      	ldr	r3, [r7, #8]
 8007918:	681b      	ldr	r3, [r3, #0]
 800791a:	2b04      	cmp	r3, #4
 800791c:	d17a      	bne.n	8007a14 <HAL_DAC_ConfigChannel+0x138>
  {
    /* Get timeout */
    tickstart = HAL_GetTick();
 800791e:	f7fd fd8d 	bl	800543c <HAL_GetTick>
 8007922:	61f8      	str	r0, [r7, #28]

    if (Channel == DAC_CHANNEL_1)
 8007924:	687b      	ldr	r3, [r7, #4]
 8007926:	2b00      	cmp	r3, #0
 8007928:	d13d      	bne.n	80079a6 <HAL_DAC_ConfigChannel+0xca>
    {
      /* SHSR1 can be written when BWST1 is cleared */
      while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
 800792a:	e018      	b.n	800795e <HAL_DAC_ConfigChannel+0x82>
      {
        /* Check for the Timeout */
        if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
 800792c:	f7fd fd86 	bl	800543c <HAL_GetTick>
 8007930:	4602      	mov	r2, r0
 8007932:	69fb      	ldr	r3, [r7, #28]
 8007934:	1ad3      	subs	r3, r2, r3
 8007936:	2b01      	cmp	r3, #1
 8007938:	d911      	bls.n	800795e <HAL_DAC_ConfigChannel+0x82>
        {
          /* New check to avoid false timeout detection in case of preemption */
          if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
 800793a:	68fb      	ldr	r3, [r7, #12]
 800793c:	681b      	ldr	r3, [r3, #0]
 800793e:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 8007940:	4b86      	ldr	r3, [pc, #536]	@ (8007b5c <HAL_DAC_ConfigChannel+0x280>)
 8007942:	4013      	ands	r3, r2
 8007944:	2b00      	cmp	r3, #0
 8007946:	d00a      	beq.n	800795e <HAL_DAC_ConfigChannel+0x82>
          {
            /* Update error code */
            SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
 8007948:	68fb      	ldr	r3, [r7, #12]
 800794a:	691b      	ldr	r3, [r3, #16]
 800794c:	f043 0208 	orr.w	r2, r3, #8
 8007950:	68fb      	ldr	r3, [r7, #12]
 8007952:	611a      	str	r2, [r3, #16]

            /* Change the DMA state */
            hdac->State = HAL_DAC_STATE_TIMEOUT;
 8007954:	68fb      	ldr	r3, [r7, #12]
 8007956:	2203      	movs	r2, #3
 8007958:	711a      	strb	r2, [r3, #4]

            return HAL_TIMEOUT;
 800795a:	2303      	movs	r3, #3
 800795c:	e0fa      	b.n	8007b54 <HAL_DAC_ConfigChannel+0x278>
      while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
 800795e:	68fb      	ldr	r3, [r7, #12]
 8007960:	681b      	ldr	r3, [r3, #0]
 8007962:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 8007964:	4b7d      	ldr	r3, [pc, #500]	@ (8007b5c <HAL_DAC_ConfigChannel+0x280>)
 8007966:	4013      	ands	r3, r2
 8007968:	2b00      	cmp	r3, #0
 800796a:	d1df      	bne.n	800792c <HAL_DAC_ConfigChannel+0x50>
          }
        }
      }
      hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
 800796c:	68fb      	ldr	r3, [r7, #12]
 800796e:	681b      	ldr	r3, [r3, #0]
 8007970:	68ba      	ldr	r2, [r7, #8]
 8007972:	6992      	ldr	r2, [r2, #24]
 8007974:	641a      	str	r2, [r3, #64]	@ 0x40
 8007976:	e020      	b.n	80079ba <HAL_DAC_ConfigChannel+0xde>
    {
      /* SHSR2 can be written when BWST2 is cleared */
      while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
      {
        /* Check for the Timeout */
        if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
 8007978:	f7fd fd60 	bl	800543c <HAL_GetTick>
 800797c:	4602      	mov	r2, r0
 800797e:	69fb      	ldr	r3, [r7, #28]
 8007980:	1ad3      	subs	r3, r2, r3
 8007982:	2b01      	cmp	r3, #1
 8007984:	d90f      	bls.n	80079a6 <HAL_DAC_ConfigChannel+0xca>
        {
          /* New check to avoid false timeout detection in case of preemption */
          if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
 8007986:	68fb      	ldr	r3, [r7, #12]
 8007988:	681b      	ldr	r3, [r3, #0]
 800798a:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 800798c:	2b00      	cmp	r3, #0
 800798e:	da0a      	bge.n	80079a6 <HAL_DAC_ConfigChannel+0xca>
          {
            /* Update error code */
            SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
 8007990:	68fb      	ldr	r3, [r7, #12]
 8007992:	691b      	ldr	r3, [r3, #16]
 8007994:	f043 0208 	orr.w	r2, r3, #8
 8007998:	68fb      	ldr	r3, [r7, #12]
 800799a:	611a      	str	r2, [r3, #16]

            /* Change the DMA state */
            hdac->State = HAL_DAC_STATE_TIMEOUT;
 800799c:	68fb      	ldr	r3, [r7, #12]
 800799e:	2203      	movs	r2, #3
 80079a0:	711a      	strb	r2, [r3, #4]

            return HAL_TIMEOUT;
 80079a2:	2303      	movs	r3, #3
 80079a4:	e0d6      	b.n	8007b54 <HAL_DAC_ConfigChannel+0x278>
      while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
 80079a6:	68fb      	ldr	r3, [r7, #12]
 80079a8:	681b      	ldr	r3, [r3, #0]
 80079aa:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 80079ac:	2b00      	cmp	r3, #0
 80079ae:	dbe3      	blt.n	8007978 <HAL_DAC_ConfigChannel+0x9c>
          }
        }
      }
      hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
 80079b0:	68fb      	ldr	r3, [r7, #12]
 80079b2:	681b      	ldr	r3, [r3, #0]
 80079b4:	68ba      	ldr	r2, [r7, #8]
 80079b6:	6992      	ldr	r2, [r2, #24]
 80079b8:	645a      	str	r2, [r3, #68]	@ 0x44
    }


    /* HoldTime */
    MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
 80079ba:	68fb      	ldr	r3, [r7, #12]
 80079bc:	681b      	ldr	r3, [r3, #0]
 80079be:	6c9a      	ldr	r2, [r3, #72]	@ 0x48
 80079c0:	687b      	ldr	r3, [r7, #4]
 80079c2:	f003 0310 	and.w	r3, r3, #16
 80079c6:	f240 31ff 	movw	r1, #1023	@ 0x3ff
 80079ca:	fa01 f303 	lsl.w	r3, r1, r3
 80079ce:	43db      	mvns	r3, r3
 80079d0:	ea02 0103 	and.w	r1, r2, r3
 80079d4:	68bb      	ldr	r3, [r7, #8]
 80079d6:	69da      	ldr	r2, [r3, #28]
 80079d8:	687b      	ldr	r3, [r7, #4]
 80079da:	f003 0310 	and.w	r3, r3, #16
 80079de:	409a      	lsls	r2, r3
 80079e0:	68fb      	ldr	r3, [r7, #12]
 80079e2:	681b      	ldr	r3, [r3, #0]
 80079e4:	430a      	orrs	r2, r1
 80079e6:	649a      	str	r2, [r3, #72]	@ 0x48
               (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
    /* RefreshTime */
    MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
 80079e8:	68fb      	ldr	r3, [r7, #12]
 80079ea:	681b      	ldr	r3, [r3, #0]
 80079ec:	6cda      	ldr	r2, [r3, #76]	@ 0x4c
 80079ee:	687b      	ldr	r3, [r7, #4]
 80079f0:	f003 0310 	and.w	r3, r3, #16
 80079f4:	21ff      	movs	r1, #255	@ 0xff
 80079f6:	fa01 f303 	lsl.w	r3, r1, r3
 80079fa:	43db      	mvns	r3, r3
 80079fc:	ea02 0103 	and.w	r1, r2, r3
 8007a00:	68bb      	ldr	r3, [r7, #8]
 8007a02:	6a1a      	ldr	r2, [r3, #32]
 8007a04:	687b      	ldr	r3, [r7, #4]
 8007a06:	f003 0310 	and.w	r3, r3, #16
 8007a0a:	409a      	lsls	r2, r3
 8007a0c:	68fb      	ldr	r3, [r7, #12]
 8007a0e:	681b      	ldr	r3, [r3, #0]
 8007a10:	430a      	orrs	r2, r1
 8007a12:	64da      	str	r2, [r3, #76]	@ 0x4c
               (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
  }

  if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
 8007a14:	68bb      	ldr	r3, [r7, #8]
 8007a16:	691b      	ldr	r3, [r3, #16]
 8007a18:	2b01      	cmp	r3, #1
 8007a1a:	d11d      	bne.n	8007a58 <HAL_DAC_ConfigChannel+0x17c>
    /* USER TRIMMING */
  {
    /* Get the DAC CCR value */
    tmpreg1 = hdac->Instance->CCR;
 8007a1c:	68fb      	ldr	r3, [r7, #12]
 8007a1e:	681b      	ldr	r3, [r3, #0]
 8007a20:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8007a22:	61bb      	str	r3, [r7, #24]
    /* Clear trimming value */
    tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
 8007a24:	687b      	ldr	r3, [r7, #4]
 8007a26:	f003 0310 	and.w	r3, r3, #16
 8007a2a:	221f      	movs	r2, #31
 8007a2c:	fa02 f303 	lsl.w	r3, r2, r3
 8007a30:	43db      	mvns	r3, r3
 8007a32:	69ba      	ldr	r2, [r7, #24]
 8007a34:	4013      	ands	r3, r2
 8007a36:	61bb      	str	r3, [r7, #24]
    /* Configure for the selected trimming offset */
    tmpreg2 = sConfig->DAC_TrimmingValue;
 8007a38:	68bb      	ldr	r3, [r7, #8]
 8007a3a:	695b      	ldr	r3, [r3, #20]
 8007a3c:	617b      	str	r3, [r7, #20]
    /* Calculate CCR register value depending on DAC_Channel */
    tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
 8007a3e:	687b      	ldr	r3, [r7, #4]
 8007a40:	f003 0310 	and.w	r3, r3, #16
 8007a44:	697a      	ldr	r2, [r7, #20]
 8007a46:	fa02 f303 	lsl.w	r3, r2, r3
 8007a4a:	69ba      	ldr	r2, [r7, #24]
 8007a4c:	4313      	orrs	r3, r2
 8007a4e:	61bb      	str	r3, [r7, #24]
    /* Write to DAC CCR */
    hdac->Instance->CCR = tmpreg1;
 8007a50:	68fb      	ldr	r3, [r7, #12]
 8007a52:	681b      	ldr	r3, [r3, #0]
 8007a54:	69ba      	ldr	r2, [r7, #24]
 8007a56:	639a      	str	r2, [r3, #56]	@ 0x38
  }
  /* else factory trimming is used (factory setting are available at reset)*/
  /* SW Nothing has nothing to do */

  /* Get the DAC MCR value */
  tmpreg1 = hdac->Instance->MCR;
 8007a58:	68fb      	ldr	r3, [r7, #12]
 8007a5a:	681b      	ldr	r3, [r3, #0]
 8007a5c:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8007a5e:	61bb      	str	r3, [r7, #24]
  /* Clear DAC_MCR_MODEx bits */
  tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
 8007a60:	687b      	ldr	r3, [r7, #4]
 8007a62:	f003 0310 	and.w	r3, r3, #16
 8007a66:	2207      	movs	r2, #7
 8007a68:	fa02 f303 	lsl.w	r3, r2, r3
 8007a6c:	43db      	mvns	r3, r3
 8007a6e:	69ba      	ldr	r2, [r7, #24]
 8007a70:	4013      	ands	r3, r2
 8007a72:	61bb      	str	r3, [r7, #24]
  /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */


  if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
 8007a74:	68bb      	ldr	r3, [r7, #8]
 8007a76:	68db      	ldr	r3, [r3, #12]
 8007a78:	2b01      	cmp	r3, #1
 8007a7a:	d102      	bne.n	8007a82 <HAL_DAC_ConfigChannel+0x1a6>
  {
    connectOnChip = 0x00000000UL;
 8007a7c:	2300      	movs	r3, #0
 8007a7e:	627b      	str	r3, [r7, #36]	@ 0x24
 8007a80:	e00f      	b.n	8007aa2 <HAL_DAC_ConfigChannel+0x1c6>
  }
  else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
 8007a82:	68bb      	ldr	r3, [r7, #8]
 8007a84:	68db      	ldr	r3, [r3, #12]
 8007a86:	2b02      	cmp	r3, #2
 8007a88:	d102      	bne.n	8007a90 <HAL_DAC_ConfigChannel+0x1b4>
  {
    connectOnChip = DAC_MCR_MODE1_0;
 8007a8a:	2301      	movs	r3, #1
 8007a8c:	627b      	str	r3, [r7, #36]	@ 0x24
 8007a8e:	e008      	b.n	8007aa2 <HAL_DAC_ConfigChannel+0x1c6>
  }
  else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
  {
    if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
 8007a90:	68bb      	ldr	r3, [r7, #8]
 8007a92:	689b      	ldr	r3, [r3, #8]
 8007a94:	2b00      	cmp	r3, #0
 8007a96:	d102      	bne.n	8007a9e <HAL_DAC_ConfigChannel+0x1c2>
    {
      connectOnChip = DAC_MCR_MODE1_0;
 8007a98:	2301      	movs	r3, #1
 8007a9a:	627b      	str	r3, [r7, #36]	@ 0x24
 8007a9c:	e001      	b.n	8007aa2 <HAL_DAC_ConfigChannel+0x1c6>
    }
    else
    {
      connectOnChip = 0x00000000UL;
 8007a9e:	2300      	movs	r3, #0
 8007aa0:	627b      	str	r3, [r7, #36]	@ 0x24
    }
  }
  tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
 8007aa2:	68bb      	ldr	r3, [r7, #8]
 8007aa4:	681a      	ldr	r2, [r3, #0]
 8007aa6:	68bb      	ldr	r3, [r7, #8]
 8007aa8:	689b      	ldr	r3, [r3, #8]
 8007aaa:	4313      	orrs	r3, r2
 8007aac:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8007aae:	4313      	orrs	r3, r2
 8007ab0:	617b      	str	r3, [r7, #20]
  /* Calculate MCR register value depending on DAC_Channel */
  tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
 8007ab2:	687b      	ldr	r3, [r7, #4]
 8007ab4:	f003 0310 	and.w	r3, r3, #16
 8007ab8:	697a      	ldr	r2, [r7, #20]
 8007aba:	fa02 f303 	lsl.w	r3, r2, r3
 8007abe:	69ba      	ldr	r2, [r7, #24]
 8007ac0:	4313      	orrs	r3, r2
 8007ac2:	61bb      	str	r3, [r7, #24]
  /* Write to DAC MCR */
  hdac->Instance->MCR = tmpreg1;
 8007ac4:	68fb      	ldr	r3, [r7, #12]
 8007ac6:	681b      	ldr	r3, [r3, #0]
 8007ac8:	69ba      	ldr	r2, [r7, #24]
 8007aca:	63da      	str	r2, [r3, #60]	@ 0x3c

  /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
  CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
 8007acc:	68fb      	ldr	r3, [r7, #12]
 8007ace:	681b      	ldr	r3, [r3, #0]
 8007ad0:	6819      	ldr	r1, [r3, #0]
 8007ad2:	687b      	ldr	r3, [r7, #4]
 8007ad4:	f003 0310 	and.w	r3, r3, #16
 8007ad8:	f44f 4280 	mov.w	r2, #16384	@ 0x4000
 8007adc:	fa02 f303 	lsl.w	r3, r2, r3
 8007ae0:	43da      	mvns	r2, r3
 8007ae2:	68fb      	ldr	r3, [r7, #12]
 8007ae4:	681b      	ldr	r3, [r3, #0]
 8007ae6:	400a      	ands	r2, r1
 8007ae8:	601a      	str	r2, [r3, #0]

  /* Get the DAC CR value */
  tmpreg1 = hdac->Instance->CR;
 8007aea:	68fb      	ldr	r3, [r7, #12]
 8007aec:	681b      	ldr	r3, [r3, #0]
 8007aee:	681b      	ldr	r3, [r3, #0]
 8007af0:	61bb      	str	r3, [r7, #24]
  /* Clear TENx, TSELx, WAVEx and MAMPx bits */
  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
 8007af2:	687b      	ldr	r3, [r7, #4]
 8007af4:	f003 0310 	and.w	r3, r3, #16
 8007af8:	f640 72fe 	movw	r2, #4094	@ 0xffe
 8007afc:	fa02 f303 	lsl.w	r3, r2, r3
 8007b00:	43db      	mvns	r3, r3
 8007b02:	69ba      	ldr	r2, [r7, #24]
 8007b04:	4013      	ands	r3, r2
 8007b06:	61bb      	str	r3, [r7, #24]
  /* Configure for the selected DAC channel: trigger */
  /* Set TSELx and TENx bits according to DAC_Trigger value */
  tmpreg2 = sConfig->DAC_Trigger;
 8007b08:	68bb      	ldr	r3, [r7, #8]
 8007b0a:	685b      	ldr	r3, [r3, #4]
 8007b0c:	617b      	str	r3, [r7, #20]
  /* Calculate CR register value depending on DAC_Channel */
  tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
 8007b0e:	687b      	ldr	r3, [r7, #4]
 8007b10:	f003 0310 	and.w	r3, r3, #16
 8007b14:	697a      	ldr	r2, [r7, #20]
 8007b16:	fa02 f303 	lsl.w	r3, r2, r3
 8007b1a:	69ba      	ldr	r2, [r7, #24]
 8007b1c:	4313      	orrs	r3, r2
 8007b1e:	61bb      	str	r3, [r7, #24]
  /* Write to DAC CR */
  hdac->Instance->CR = tmpreg1;
 8007b20:	68fb      	ldr	r3, [r7, #12]
 8007b22:	681b      	ldr	r3, [r3, #0]
 8007b24:	69ba      	ldr	r2, [r7, #24]
 8007b26:	601a      	str	r2, [r3, #0]
  /* Disable wave generation */
  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
 8007b28:	68fb      	ldr	r3, [r7, #12]
 8007b2a:	681b      	ldr	r3, [r3, #0]
 8007b2c:	6819      	ldr	r1, [r3, #0]
 8007b2e:	687b      	ldr	r3, [r7, #4]
 8007b30:	f003 0310 	and.w	r3, r3, #16
 8007b34:	22c0      	movs	r2, #192	@ 0xc0
 8007b36:	fa02 f303 	lsl.w	r3, r2, r3
 8007b3a:	43da      	mvns	r2, r3
 8007b3c:	68fb      	ldr	r3, [r7, #12]
 8007b3e:	681b      	ldr	r3, [r3, #0]
 8007b40:	400a      	ands	r2, r1
 8007b42:	601a      	str	r2, [r3, #0]

  /* Change DAC state */
  hdac->State = HAL_DAC_STATE_READY;
 8007b44:	68fb      	ldr	r3, [r7, #12]
 8007b46:	2201      	movs	r2, #1
 8007b48:	711a      	strb	r2, [r3, #4]

  /* Process unlocked */
  __HAL_UNLOCK(hdac);
 8007b4a:	68fb      	ldr	r3, [r7, #12]
 8007b4c:	2200      	movs	r2, #0
 8007b4e:	715a      	strb	r2, [r3, #5]

  /* Return function status */
  return status;
 8007b50:	f897 3023 	ldrb.w	r3, [r7, #35]	@ 0x23
}
 8007b54:	4618      	mov	r0, r3
 8007b56:	3728      	adds	r7, #40	@ 0x28
 8007b58:	46bd      	mov	sp, r7
 8007b5a:	bd80      	pop	{r7, pc}
 8007b5c:	20008000 	.word	0x20008000

08007b60 <HAL_DACEx_DMAUnderrunCallbackCh2>:
  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
  *         the configuration information for the specified DAC.
  * @retval None
  */
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
{
 8007b60:	b480      	push	{r7}
 8007b62:	b083      	sub	sp, #12
 8007b64:	af00      	add	r7, sp, #0
 8007b66:	6078      	str	r0, [r7, #4]
  UNUSED(hdac);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
   */
}
 8007b68:	bf00      	nop
 8007b6a:	370c      	adds	r7, #12
 8007b6c:	46bd      	mov	sp, r7
 8007b6e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8007b72:	4770      	bx	lr

08007b74 <HAL_DMA_Init>:
  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Stream.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 8007b74:	b580      	push	{r7, lr}
 8007b76:	b086      	sub	sp, #24
 8007b78:	af00      	add	r7, sp, #0
 8007b7a:	6078      	str	r0, [r7, #4]
  uint32_t registerValue;
  uint32_t tickstart = HAL_GetTick();
 8007b7c:	f7fd fc5e 	bl	800543c <HAL_GetTick>
 8007b80:	6138      	str	r0, [r7, #16]
  DMA_Base_Registers *regs_dma;
  BDMA_Base_Registers *regs_bdma;

  /* Check the DMA peripheral handle */
  if(hdma == NULL)
 8007b82:	687b      	ldr	r3, [r7, #4]
 8007b84:	2b00      	cmp	r3, #0
 8007b86:	d101      	bne.n	8007b8c <HAL_DMA_Init+0x18>
  {
    return HAL_ERROR;
 8007b88:	2301      	movs	r3, #1
 8007b8a:	e316      	b.n	80081ba <HAL_DMA_Init+0x646>
  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));

  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 8007b8c:	687b      	ldr	r3, [r7, #4]
 8007b8e:	681b      	ldr	r3, [r3, #0]
 8007b90:	4a66      	ldr	r2, [pc, #408]	@ (8007d2c <HAL_DMA_Init+0x1b8>)
 8007b92:	4293      	cmp	r3, r2
 8007b94:	d04a      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007b96:	687b      	ldr	r3, [r7, #4]
 8007b98:	681b      	ldr	r3, [r3, #0]
 8007b9a:	4a65      	ldr	r2, [pc, #404]	@ (8007d30 <HAL_DMA_Init+0x1bc>)
 8007b9c:	4293      	cmp	r3, r2
 8007b9e:	d045      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007ba0:	687b      	ldr	r3, [r7, #4]
 8007ba2:	681b      	ldr	r3, [r3, #0]
 8007ba4:	4a63      	ldr	r2, [pc, #396]	@ (8007d34 <HAL_DMA_Init+0x1c0>)
 8007ba6:	4293      	cmp	r3, r2
 8007ba8:	d040      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007baa:	687b      	ldr	r3, [r7, #4]
 8007bac:	681b      	ldr	r3, [r3, #0]
 8007bae:	4a62      	ldr	r2, [pc, #392]	@ (8007d38 <HAL_DMA_Init+0x1c4>)
 8007bb0:	4293      	cmp	r3, r2
 8007bb2:	d03b      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007bb4:	687b      	ldr	r3, [r7, #4]
 8007bb6:	681b      	ldr	r3, [r3, #0]
 8007bb8:	4a60      	ldr	r2, [pc, #384]	@ (8007d3c <HAL_DMA_Init+0x1c8>)
 8007bba:	4293      	cmp	r3, r2
 8007bbc:	d036      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007bbe:	687b      	ldr	r3, [r7, #4]
 8007bc0:	681b      	ldr	r3, [r3, #0]
 8007bc2:	4a5f      	ldr	r2, [pc, #380]	@ (8007d40 <HAL_DMA_Init+0x1cc>)
 8007bc4:	4293      	cmp	r3, r2
 8007bc6:	d031      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007bc8:	687b      	ldr	r3, [r7, #4]
 8007bca:	681b      	ldr	r3, [r3, #0]
 8007bcc:	4a5d      	ldr	r2, [pc, #372]	@ (8007d44 <HAL_DMA_Init+0x1d0>)
 8007bce:	4293      	cmp	r3, r2
 8007bd0:	d02c      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007bd2:	687b      	ldr	r3, [r7, #4]
 8007bd4:	681b      	ldr	r3, [r3, #0]
 8007bd6:	4a5c      	ldr	r2, [pc, #368]	@ (8007d48 <HAL_DMA_Init+0x1d4>)
 8007bd8:	4293      	cmp	r3, r2
 8007bda:	d027      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007bdc:	687b      	ldr	r3, [r7, #4]
 8007bde:	681b      	ldr	r3, [r3, #0]
 8007be0:	4a5a      	ldr	r2, [pc, #360]	@ (8007d4c <HAL_DMA_Init+0x1d8>)
 8007be2:	4293      	cmp	r3, r2
 8007be4:	d022      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007be6:	687b      	ldr	r3, [r7, #4]
 8007be8:	681b      	ldr	r3, [r3, #0]
 8007bea:	4a59      	ldr	r2, [pc, #356]	@ (8007d50 <HAL_DMA_Init+0x1dc>)
 8007bec:	4293      	cmp	r3, r2
 8007bee:	d01d      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007bf0:	687b      	ldr	r3, [r7, #4]
 8007bf2:	681b      	ldr	r3, [r3, #0]
 8007bf4:	4a57      	ldr	r2, [pc, #348]	@ (8007d54 <HAL_DMA_Init+0x1e0>)
 8007bf6:	4293      	cmp	r3, r2
 8007bf8:	d018      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007bfa:	687b      	ldr	r3, [r7, #4]
 8007bfc:	681b      	ldr	r3, [r3, #0]
 8007bfe:	4a56      	ldr	r2, [pc, #344]	@ (8007d58 <HAL_DMA_Init+0x1e4>)
 8007c00:	4293      	cmp	r3, r2
 8007c02:	d013      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007c04:	687b      	ldr	r3, [r7, #4]
 8007c06:	681b      	ldr	r3, [r3, #0]
 8007c08:	4a54      	ldr	r2, [pc, #336]	@ (8007d5c <HAL_DMA_Init+0x1e8>)
 8007c0a:	4293      	cmp	r3, r2
 8007c0c:	d00e      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007c0e:	687b      	ldr	r3, [r7, #4]
 8007c10:	681b      	ldr	r3, [r3, #0]
 8007c12:	4a53      	ldr	r2, [pc, #332]	@ (8007d60 <HAL_DMA_Init+0x1ec>)
 8007c14:	4293      	cmp	r3, r2
 8007c16:	d009      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007c18:	687b      	ldr	r3, [r7, #4]
 8007c1a:	681b      	ldr	r3, [r3, #0]
 8007c1c:	4a51      	ldr	r2, [pc, #324]	@ (8007d64 <HAL_DMA_Init+0x1f0>)
 8007c1e:	4293      	cmp	r3, r2
 8007c20:	d004      	beq.n	8007c2c <HAL_DMA_Init+0xb8>
 8007c22:	687b      	ldr	r3, [r7, #4]
 8007c24:	681b      	ldr	r3, [r3, #0]
 8007c26:	4a50      	ldr	r2, [pc, #320]	@ (8007d68 <HAL_DMA_Init+0x1f4>)
 8007c28:	4293      	cmp	r3, r2
 8007c2a:	d101      	bne.n	8007c30 <HAL_DMA_Init+0xbc>
 8007c2c:	2301      	movs	r3, #1
 8007c2e:	e000      	b.n	8007c32 <HAL_DMA_Init+0xbe>
 8007c30:	2300      	movs	r3, #0
 8007c32:	2b00      	cmp	r3, #0
 8007c34:	f000 813b 	beq.w	8007eae <HAL_DMA_Init+0x33a>
      assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
      assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
    }

    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 8007c38:	687b      	ldr	r3, [r7, #4]
 8007c3a:	2202      	movs	r2, #2
 8007c3c:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

    /* Allocate lock resource */
    __HAL_UNLOCK(hdma);
 8007c40:	687b      	ldr	r3, [r7, #4]
 8007c42:	2200      	movs	r2, #0
 8007c44:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);
 8007c48:	687b      	ldr	r3, [r7, #4]
 8007c4a:	681b      	ldr	r3, [r3, #0]
 8007c4c:	4a37      	ldr	r2, [pc, #220]	@ (8007d2c <HAL_DMA_Init+0x1b8>)
 8007c4e:	4293      	cmp	r3, r2
 8007c50:	d04a      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007c52:	687b      	ldr	r3, [r7, #4]
 8007c54:	681b      	ldr	r3, [r3, #0]
 8007c56:	4a36      	ldr	r2, [pc, #216]	@ (8007d30 <HAL_DMA_Init+0x1bc>)
 8007c58:	4293      	cmp	r3, r2
 8007c5a:	d045      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007c5c:	687b      	ldr	r3, [r7, #4]
 8007c5e:	681b      	ldr	r3, [r3, #0]
 8007c60:	4a34      	ldr	r2, [pc, #208]	@ (8007d34 <HAL_DMA_Init+0x1c0>)
 8007c62:	4293      	cmp	r3, r2
 8007c64:	d040      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007c66:	687b      	ldr	r3, [r7, #4]
 8007c68:	681b      	ldr	r3, [r3, #0]
 8007c6a:	4a33      	ldr	r2, [pc, #204]	@ (8007d38 <HAL_DMA_Init+0x1c4>)
 8007c6c:	4293      	cmp	r3, r2
 8007c6e:	d03b      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007c70:	687b      	ldr	r3, [r7, #4]
 8007c72:	681b      	ldr	r3, [r3, #0]
 8007c74:	4a31      	ldr	r2, [pc, #196]	@ (8007d3c <HAL_DMA_Init+0x1c8>)
 8007c76:	4293      	cmp	r3, r2
 8007c78:	d036      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007c7a:	687b      	ldr	r3, [r7, #4]
 8007c7c:	681b      	ldr	r3, [r3, #0]
 8007c7e:	4a30      	ldr	r2, [pc, #192]	@ (8007d40 <HAL_DMA_Init+0x1cc>)
 8007c80:	4293      	cmp	r3, r2
 8007c82:	d031      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007c84:	687b      	ldr	r3, [r7, #4]
 8007c86:	681b      	ldr	r3, [r3, #0]
 8007c88:	4a2e      	ldr	r2, [pc, #184]	@ (8007d44 <HAL_DMA_Init+0x1d0>)
 8007c8a:	4293      	cmp	r3, r2
 8007c8c:	d02c      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007c8e:	687b      	ldr	r3, [r7, #4]
 8007c90:	681b      	ldr	r3, [r3, #0]
 8007c92:	4a2d      	ldr	r2, [pc, #180]	@ (8007d48 <HAL_DMA_Init+0x1d4>)
 8007c94:	4293      	cmp	r3, r2
 8007c96:	d027      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007c98:	687b      	ldr	r3, [r7, #4]
 8007c9a:	681b      	ldr	r3, [r3, #0]
 8007c9c:	4a2b      	ldr	r2, [pc, #172]	@ (8007d4c <HAL_DMA_Init+0x1d8>)
 8007c9e:	4293      	cmp	r3, r2
 8007ca0:	d022      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007ca2:	687b      	ldr	r3, [r7, #4]
 8007ca4:	681b      	ldr	r3, [r3, #0]
 8007ca6:	4a2a      	ldr	r2, [pc, #168]	@ (8007d50 <HAL_DMA_Init+0x1dc>)
 8007ca8:	4293      	cmp	r3, r2
 8007caa:	d01d      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007cac:	687b      	ldr	r3, [r7, #4]
 8007cae:	681b      	ldr	r3, [r3, #0]
 8007cb0:	4a28      	ldr	r2, [pc, #160]	@ (8007d54 <HAL_DMA_Init+0x1e0>)
 8007cb2:	4293      	cmp	r3, r2
 8007cb4:	d018      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007cb6:	687b      	ldr	r3, [r7, #4]
 8007cb8:	681b      	ldr	r3, [r3, #0]
 8007cba:	4a27      	ldr	r2, [pc, #156]	@ (8007d58 <HAL_DMA_Init+0x1e4>)
 8007cbc:	4293      	cmp	r3, r2
 8007cbe:	d013      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007cc0:	687b      	ldr	r3, [r7, #4]
 8007cc2:	681b      	ldr	r3, [r3, #0]
 8007cc4:	4a25      	ldr	r2, [pc, #148]	@ (8007d5c <HAL_DMA_Init+0x1e8>)
 8007cc6:	4293      	cmp	r3, r2
 8007cc8:	d00e      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007cca:	687b      	ldr	r3, [r7, #4]
 8007ccc:	681b      	ldr	r3, [r3, #0]
 8007cce:	4a24      	ldr	r2, [pc, #144]	@ (8007d60 <HAL_DMA_Init+0x1ec>)
 8007cd0:	4293      	cmp	r3, r2
 8007cd2:	d009      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007cd4:	687b      	ldr	r3, [r7, #4]
 8007cd6:	681b      	ldr	r3, [r3, #0]
 8007cd8:	4a22      	ldr	r2, [pc, #136]	@ (8007d64 <HAL_DMA_Init+0x1f0>)
 8007cda:	4293      	cmp	r3, r2
 8007cdc:	d004      	beq.n	8007ce8 <HAL_DMA_Init+0x174>
 8007cde:	687b      	ldr	r3, [r7, #4]
 8007ce0:	681b      	ldr	r3, [r3, #0]
 8007ce2:	4a21      	ldr	r2, [pc, #132]	@ (8007d68 <HAL_DMA_Init+0x1f4>)
 8007ce4:	4293      	cmp	r3, r2
 8007ce6:	d108      	bne.n	8007cfa <HAL_DMA_Init+0x186>
 8007ce8:	687b      	ldr	r3, [r7, #4]
 8007cea:	681b      	ldr	r3, [r3, #0]
 8007cec:	681a      	ldr	r2, [r3, #0]
 8007cee:	687b      	ldr	r3, [r7, #4]
 8007cf0:	681b      	ldr	r3, [r3, #0]
 8007cf2:	f022 0201 	bic.w	r2, r2, #1
 8007cf6:	601a      	str	r2, [r3, #0]
 8007cf8:	e007      	b.n	8007d0a <HAL_DMA_Init+0x196>
 8007cfa:	687b      	ldr	r3, [r7, #4]
 8007cfc:	681b      	ldr	r3, [r3, #0]
 8007cfe:	681a      	ldr	r2, [r3, #0]
 8007d00:	687b      	ldr	r3, [r7, #4]
 8007d02:	681b      	ldr	r3, [r3, #0]
 8007d04:	f022 0201 	bic.w	r2, r2, #1
 8007d08:	601a      	str	r2, [r3, #0]

    /* Check if the DMA Stream is effectively disabled */
    while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
 8007d0a:	e02f      	b.n	8007d6c <HAL_DMA_Init+0x1f8>
    {
      /* Check for the Timeout */
      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
 8007d0c:	f7fd fb96 	bl	800543c <HAL_GetTick>
 8007d10:	4602      	mov	r2, r0
 8007d12:	693b      	ldr	r3, [r7, #16]
 8007d14:	1ad3      	subs	r3, r2, r3
 8007d16:	2b05      	cmp	r3, #5
 8007d18:	d928      	bls.n	8007d6c <HAL_DMA_Init+0x1f8>
      {
        /* Update error code */
        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
 8007d1a:	687b      	ldr	r3, [r7, #4]
 8007d1c:	2220      	movs	r2, #32
 8007d1e:	655a      	str	r2, [r3, #84]	@ 0x54

        /* Change the DMA state */
        hdma->State = HAL_DMA_STATE_ERROR;
 8007d20:	687b      	ldr	r3, [r7, #4]
 8007d22:	2203      	movs	r2, #3
 8007d24:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

        return HAL_ERROR;
 8007d28:	2301      	movs	r3, #1
 8007d2a:	e246      	b.n	80081ba <HAL_DMA_Init+0x646>
 8007d2c:	40020010 	.word	0x40020010
 8007d30:	40020028 	.word	0x40020028
 8007d34:	40020040 	.word	0x40020040
 8007d38:	40020058 	.word	0x40020058
 8007d3c:	40020070 	.word	0x40020070
 8007d40:	40020088 	.word	0x40020088
 8007d44:	400200a0 	.word	0x400200a0
 8007d48:	400200b8 	.word	0x400200b8
 8007d4c:	40020410 	.word	0x40020410
 8007d50:	40020428 	.word	0x40020428
 8007d54:	40020440 	.word	0x40020440
 8007d58:	40020458 	.word	0x40020458
 8007d5c:	40020470 	.word	0x40020470
 8007d60:	40020488 	.word	0x40020488
 8007d64:	400204a0 	.word	0x400204a0
 8007d68:	400204b8 	.word	0x400204b8
    while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
 8007d6c:	687b      	ldr	r3, [r7, #4]
 8007d6e:	681b      	ldr	r3, [r3, #0]
 8007d70:	681b      	ldr	r3, [r3, #0]
 8007d72:	f003 0301 	and.w	r3, r3, #1
 8007d76:	2b00      	cmp	r3, #0
 8007d78:	d1c8      	bne.n	8007d0c <HAL_DMA_Init+0x198>
      }
    }

    /* Get the CR register value */
    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->CR;
 8007d7a:	687b      	ldr	r3, [r7, #4]
 8007d7c:	681b      	ldr	r3, [r3, #0]
 8007d7e:	681b      	ldr	r3, [r3, #0]
 8007d80:	617b      	str	r3, [r7, #20]

    /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
    registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
 8007d82:	697a      	ldr	r2, [r7, #20]
 8007d84:	4b83      	ldr	r3, [pc, #524]	@ (8007f94 <HAL_DMA_Init+0x420>)
 8007d86:	4013      	ands	r3, r2
 8007d88:	617b      	str	r3, [r7, #20]
                        DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
                        DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
                        DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));

    /* Prepare the DMA Stream configuration */
    registerValue |=  hdma->Init.Direction           |
 8007d8a:	687b      	ldr	r3, [r7, #4]
 8007d8c:	689a      	ldr	r2, [r3, #8]
            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8007d8e:	687b      	ldr	r3, [r7, #4]
 8007d90:	68db      	ldr	r3, [r3, #12]
    registerValue |=  hdma->Init.Direction           |
 8007d92:	431a      	orrs	r2, r3
            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8007d94:	687b      	ldr	r3, [r7, #4]
 8007d96:	691b      	ldr	r3, [r3, #16]
 8007d98:	431a      	orrs	r2, r3
            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8007d9a:	687b      	ldr	r3, [r7, #4]
 8007d9c:	695b      	ldr	r3, [r3, #20]
            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8007d9e:	431a      	orrs	r2, r3
            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8007da0:	687b      	ldr	r3, [r7, #4]
 8007da2:	699b      	ldr	r3, [r3, #24]
 8007da4:	431a      	orrs	r2, r3
            hdma->Init.Mode                | hdma->Init.Priority;
 8007da6:	687b      	ldr	r3, [r7, #4]
 8007da8:	69db      	ldr	r3, [r3, #28]
            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8007daa:	431a      	orrs	r2, r3
            hdma->Init.Mode                | hdma->Init.Priority;
 8007dac:	687b      	ldr	r3, [r7, #4]
 8007dae:	6a1b      	ldr	r3, [r3, #32]
 8007db0:	4313      	orrs	r3, r2
    registerValue |=  hdma->Init.Direction           |
 8007db2:	697a      	ldr	r2, [r7, #20]
 8007db4:	4313      	orrs	r3, r2
 8007db6:	617b      	str	r3, [r7, #20]

    /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
 8007db8:	687b      	ldr	r3, [r7, #4]
 8007dba:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8007dbc:	2b04      	cmp	r3, #4
 8007dbe:	d107      	bne.n	8007dd0 <HAL_DMA_Init+0x25c>
    {
      /* Get memory burst and peripheral burst */
      registerValue |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
 8007dc0:	687b      	ldr	r3, [r7, #4]
 8007dc2:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8007dc4:	687b      	ldr	r3, [r7, #4]
 8007dc6:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8007dc8:	4313      	orrs	r3, r2
 8007dca:	697a      	ldr	r2, [r7, #20]
 8007dcc:	4313      	orrs	r3, r2
 8007dce:	617b      	str	r3, [r7, #20]
    }

    /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
                                    lock when transferring data to/from USART/UART */
#if (STM32H7_DEV_ID == 0x450UL)
    if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
 8007dd0:	4b71      	ldr	r3, [pc, #452]	@ (8007f98 <HAL_DMA_Init+0x424>)
 8007dd2:	681a      	ldr	r2, [r3, #0]
 8007dd4:	4b71      	ldr	r3, [pc, #452]	@ (8007f9c <HAL_DMA_Init+0x428>)
 8007dd6:	4013      	ands	r3, r2
 8007dd8:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 8007ddc:	d328      	bcc.n	8007e30 <HAL_DMA_Init+0x2bc>
    {
#endif /* STM32H7_DEV_ID == 0x450UL */
      if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
 8007dde:	687b      	ldr	r3, [r7, #4]
 8007de0:	685b      	ldr	r3, [r3, #4]
 8007de2:	2b28      	cmp	r3, #40	@ 0x28
 8007de4:	d903      	bls.n	8007dee <HAL_DMA_Init+0x27a>
 8007de6:	687b      	ldr	r3, [r7, #4]
 8007de8:	685b      	ldr	r3, [r3, #4]
 8007dea:	2b2e      	cmp	r3, #46	@ 0x2e
 8007dec:	d917      	bls.n	8007e1e <HAL_DMA_Init+0x2aa>
 8007dee:	687b      	ldr	r3, [r7, #4]
 8007df0:	685b      	ldr	r3, [r3, #4]
 8007df2:	2b3e      	cmp	r3, #62	@ 0x3e
 8007df4:	d903      	bls.n	8007dfe <HAL_DMA_Init+0x28a>
 8007df6:	687b      	ldr	r3, [r7, #4]
 8007df8:	685b      	ldr	r3, [r3, #4]
 8007dfa:	2b42      	cmp	r3, #66	@ 0x42
 8007dfc:	d90f      	bls.n	8007e1e <HAL_DMA_Init+0x2aa>
 8007dfe:	687b      	ldr	r3, [r7, #4]
 8007e00:	685b      	ldr	r3, [r3, #4]
 8007e02:	2b46      	cmp	r3, #70	@ 0x46
 8007e04:	d903      	bls.n	8007e0e <HAL_DMA_Init+0x29a>
 8007e06:	687b      	ldr	r3, [r7, #4]
 8007e08:	685b      	ldr	r3, [r3, #4]
 8007e0a:	2b48      	cmp	r3, #72	@ 0x48
 8007e0c:	d907      	bls.n	8007e1e <HAL_DMA_Init+0x2aa>
 8007e0e:	687b      	ldr	r3, [r7, #4]
 8007e10:	685b      	ldr	r3, [r3, #4]
 8007e12:	2b4e      	cmp	r3, #78	@ 0x4e
 8007e14:	d905      	bls.n	8007e22 <HAL_DMA_Init+0x2ae>
 8007e16:	687b      	ldr	r3, [r7, #4]
 8007e18:	685b      	ldr	r3, [r3, #4]
 8007e1a:	2b52      	cmp	r3, #82	@ 0x52
 8007e1c:	d801      	bhi.n	8007e22 <HAL_DMA_Init+0x2ae>
 8007e1e:	2301      	movs	r3, #1
 8007e20:	e000      	b.n	8007e24 <HAL_DMA_Init+0x2b0>
 8007e22:	2300      	movs	r3, #0
 8007e24:	2b00      	cmp	r3, #0
 8007e26:	d003      	beq.n	8007e30 <HAL_DMA_Init+0x2bc>
      {
        registerValue |= DMA_SxCR_TRBUFF;
 8007e28:	697b      	ldr	r3, [r7, #20]
 8007e2a:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 8007e2e:	617b      	str	r3, [r7, #20]
#if (STM32H7_DEV_ID == 0x450UL)
    }
#endif /* STM32H7_DEV_ID == 0x450UL */

    /* Write to DMA Stream CR register */
    ((DMA_Stream_TypeDef   *)hdma->Instance)->CR = registerValue;
 8007e30:	687b      	ldr	r3, [r7, #4]
 8007e32:	681b      	ldr	r3, [r3, #0]
 8007e34:	697a      	ldr	r2, [r7, #20]
 8007e36:	601a      	str	r2, [r3, #0]

    /* Get the FCR register value */
    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR;
 8007e38:	687b      	ldr	r3, [r7, #4]
 8007e3a:	681b      	ldr	r3, [r3, #0]
 8007e3c:	695b      	ldr	r3, [r3, #20]
 8007e3e:	617b      	str	r3, [r7, #20]

    /* Clear Direct mode and FIFO threshold bits */
    registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
 8007e40:	697b      	ldr	r3, [r7, #20]
 8007e42:	f023 0307 	bic.w	r3, r3, #7
 8007e46:	617b      	str	r3, [r7, #20]

    /* Prepare the DMA Stream FIFO configuration */
    registerValue |= hdma->Init.FIFOMode;
 8007e48:	687b      	ldr	r3, [r7, #4]
 8007e4a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8007e4c:	697a      	ldr	r2, [r7, #20]
 8007e4e:	4313      	orrs	r3, r2
 8007e50:	617b      	str	r3, [r7, #20]

    /* the FIFO threshold is not used when the FIFO mode is disabled */
    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
 8007e52:	687b      	ldr	r3, [r7, #4]
 8007e54:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8007e56:	2b04      	cmp	r3, #4
 8007e58:	d117      	bne.n	8007e8a <HAL_DMA_Init+0x316>
    {
      /* Get the FIFO threshold */
      registerValue |= hdma->Init.FIFOThreshold;
 8007e5a:	687b      	ldr	r3, [r7, #4]
 8007e5c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8007e5e:	697a      	ldr	r2, [r7, #20]
 8007e60:	4313      	orrs	r3, r2
 8007e62:	617b      	str	r3, [r7, #20]

      /* Check compatibility between FIFO threshold level and size of the memory burst */
      /* for INCR4, INCR8, INCR16 */
      if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)
 8007e64:	687b      	ldr	r3, [r7, #4]
 8007e66:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8007e68:	2b00      	cmp	r3, #0
 8007e6a:	d00e      	beq.n	8007e8a <HAL_DMA_Init+0x316>
      {
        if (DMA_CheckFifoParam(hdma) != HAL_OK)
 8007e6c:	6878      	ldr	r0, [r7, #4]
 8007e6e:	f002 fb33 	bl	800a4d8 <DMA_CheckFifoParam>
 8007e72:	4603      	mov	r3, r0
 8007e74:	2b00      	cmp	r3, #0
 8007e76:	d008      	beq.n	8007e8a <HAL_DMA_Init+0x316>
        {
          /* Update error code */
          hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
 8007e78:	687b      	ldr	r3, [r7, #4]
 8007e7a:	2240      	movs	r2, #64	@ 0x40
 8007e7c:	655a      	str	r2, [r3, #84]	@ 0x54

          /* Change the DMA state */
          hdma->State = HAL_DMA_STATE_READY;
 8007e7e:	687b      	ldr	r3, [r7, #4]
 8007e80:	2201      	movs	r2, #1
 8007e82:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

          return HAL_ERROR;
 8007e86:	2301      	movs	r3, #1
 8007e88:	e197      	b.n	80081ba <HAL_DMA_Init+0x646>
        }
      }
    }

    /* Write to DMA Stream FCR */
    ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR = registerValue;
 8007e8a:	687b      	ldr	r3, [r7, #4]
 8007e8c:	681b      	ldr	r3, [r3, #0]
 8007e8e:	697a      	ldr	r2, [r7, #20]
 8007e90:	615a      	str	r2, [r3, #20]

    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
       DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
    regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
 8007e92:	6878      	ldr	r0, [r7, #4]
 8007e94:	f002 fa6e 	bl	800a374 <DMA_CalcBaseAndBitshift>
 8007e98:	4603      	mov	r3, r0
 8007e9a:	60bb      	str	r3, [r7, #8]

    /* Clear all interrupt flags */
    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
 8007e9c:	687b      	ldr	r3, [r7, #4]
 8007e9e:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8007ea0:	f003 031f 	and.w	r3, r3, #31
 8007ea4:	223f      	movs	r2, #63	@ 0x3f
 8007ea6:	409a      	lsls	r2, r3
 8007ea8:	68bb      	ldr	r3, [r7, #8]
 8007eaa:	609a      	str	r2, [r3, #8]
 8007eac:	e0cd      	b.n	800804a <HAL_DMA_Init+0x4d6>
  }
  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
 8007eae:	687b      	ldr	r3, [r7, #4]
 8007eb0:	681b      	ldr	r3, [r3, #0]
 8007eb2:	4a3b      	ldr	r2, [pc, #236]	@ (8007fa0 <HAL_DMA_Init+0x42c>)
 8007eb4:	4293      	cmp	r3, r2
 8007eb6:	d022      	beq.n	8007efe <HAL_DMA_Init+0x38a>
 8007eb8:	687b      	ldr	r3, [r7, #4]
 8007eba:	681b      	ldr	r3, [r3, #0]
 8007ebc:	4a39      	ldr	r2, [pc, #228]	@ (8007fa4 <HAL_DMA_Init+0x430>)
 8007ebe:	4293      	cmp	r3, r2
 8007ec0:	d01d      	beq.n	8007efe <HAL_DMA_Init+0x38a>
 8007ec2:	687b      	ldr	r3, [r7, #4]
 8007ec4:	681b      	ldr	r3, [r3, #0]
 8007ec6:	4a38      	ldr	r2, [pc, #224]	@ (8007fa8 <HAL_DMA_Init+0x434>)
 8007ec8:	4293      	cmp	r3, r2
 8007eca:	d018      	beq.n	8007efe <HAL_DMA_Init+0x38a>
 8007ecc:	687b      	ldr	r3, [r7, #4]
 8007ece:	681b      	ldr	r3, [r3, #0]
 8007ed0:	4a36      	ldr	r2, [pc, #216]	@ (8007fac <HAL_DMA_Init+0x438>)
 8007ed2:	4293      	cmp	r3, r2
 8007ed4:	d013      	beq.n	8007efe <HAL_DMA_Init+0x38a>
 8007ed6:	687b      	ldr	r3, [r7, #4]
 8007ed8:	681b      	ldr	r3, [r3, #0]
 8007eda:	4a35      	ldr	r2, [pc, #212]	@ (8007fb0 <HAL_DMA_Init+0x43c>)
 8007edc:	4293      	cmp	r3, r2
 8007ede:	d00e      	beq.n	8007efe <HAL_DMA_Init+0x38a>
 8007ee0:	687b      	ldr	r3, [r7, #4]
 8007ee2:	681b      	ldr	r3, [r3, #0]
 8007ee4:	4a33      	ldr	r2, [pc, #204]	@ (8007fb4 <HAL_DMA_Init+0x440>)
 8007ee6:	4293      	cmp	r3, r2
 8007ee8:	d009      	beq.n	8007efe <HAL_DMA_Init+0x38a>
 8007eea:	687b      	ldr	r3, [r7, #4]
 8007eec:	681b      	ldr	r3, [r3, #0]
 8007eee:	4a32      	ldr	r2, [pc, #200]	@ (8007fb8 <HAL_DMA_Init+0x444>)
 8007ef0:	4293      	cmp	r3, r2
 8007ef2:	d004      	beq.n	8007efe <HAL_DMA_Init+0x38a>
 8007ef4:	687b      	ldr	r3, [r7, #4]
 8007ef6:	681b      	ldr	r3, [r3, #0]
 8007ef8:	4a30      	ldr	r2, [pc, #192]	@ (8007fbc <HAL_DMA_Init+0x448>)
 8007efa:	4293      	cmp	r3, r2
 8007efc:	d101      	bne.n	8007f02 <HAL_DMA_Init+0x38e>
 8007efe:	2301      	movs	r3, #1
 8007f00:	e000      	b.n	8007f04 <HAL_DMA_Init+0x390>
 8007f02:	2300      	movs	r3, #0
 8007f04:	2b00      	cmp	r3, #0
 8007f06:	f000 8097 	beq.w	8008038 <HAL_DMA_Init+0x4c4>
  {
    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
 8007f0a:	687b      	ldr	r3, [r7, #4]
 8007f0c:	681b      	ldr	r3, [r3, #0]
 8007f0e:	4a24      	ldr	r2, [pc, #144]	@ (8007fa0 <HAL_DMA_Init+0x42c>)
 8007f10:	4293      	cmp	r3, r2
 8007f12:	d021      	beq.n	8007f58 <HAL_DMA_Init+0x3e4>
 8007f14:	687b      	ldr	r3, [r7, #4]
 8007f16:	681b      	ldr	r3, [r3, #0]
 8007f18:	4a22      	ldr	r2, [pc, #136]	@ (8007fa4 <HAL_DMA_Init+0x430>)
 8007f1a:	4293      	cmp	r3, r2
 8007f1c:	d01c      	beq.n	8007f58 <HAL_DMA_Init+0x3e4>
 8007f1e:	687b      	ldr	r3, [r7, #4]
 8007f20:	681b      	ldr	r3, [r3, #0]
 8007f22:	4a21      	ldr	r2, [pc, #132]	@ (8007fa8 <HAL_DMA_Init+0x434>)
 8007f24:	4293      	cmp	r3, r2
 8007f26:	d017      	beq.n	8007f58 <HAL_DMA_Init+0x3e4>
 8007f28:	687b      	ldr	r3, [r7, #4]
 8007f2a:	681b      	ldr	r3, [r3, #0]
 8007f2c:	4a1f      	ldr	r2, [pc, #124]	@ (8007fac <HAL_DMA_Init+0x438>)
 8007f2e:	4293      	cmp	r3, r2
 8007f30:	d012      	beq.n	8007f58 <HAL_DMA_Init+0x3e4>
 8007f32:	687b      	ldr	r3, [r7, #4]
 8007f34:	681b      	ldr	r3, [r3, #0]
 8007f36:	4a1e      	ldr	r2, [pc, #120]	@ (8007fb0 <HAL_DMA_Init+0x43c>)
 8007f38:	4293      	cmp	r3, r2
 8007f3a:	d00d      	beq.n	8007f58 <HAL_DMA_Init+0x3e4>
 8007f3c:	687b      	ldr	r3, [r7, #4]
 8007f3e:	681b      	ldr	r3, [r3, #0]
 8007f40:	4a1c      	ldr	r2, [pc, #112]	@ (8007fb4 <HAL_DMA_Init+0x440>)
 8007f42:	4293      	cmp	r3, r2
 8007f44:	d008      	beq.n	8007f58 <HAL_DMA_Init+0x3e4>
 8007f46:	687b      	ldr	r3, [r7, #4]
 8007f48:	681b      	ldr	r3, [r3, #0]
 8007f4a:	4a1b      	ldr	r2, [pc, #108]	@ (8007fb8 <HAL_DMA_Init+0x444>)
 8007f4c:	4293      	cmp	r3, r2
 8007f4e:	d003      	beq.n	8007f58 <HAL_DMA_Init+0x3e4>
 8007f50:	687b      	ldr	r3, [r7, #4]
 8007f52:	681b      	ldr	r3, [r3, #0]
 8007f54:	4a19      	ldr	r2, [pc, #100]	@ (8007fbc <HAL_DMA_Init+0x448>)
 8007f56:	4293      	cmp	r3, r2
      /* Check the request parameter */
      assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
    }

    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 8007f58:	687b      	ldr	r3, [r7, #4]
 8007f5a:	2202      	movs	r2, #2
 8007f5c:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

    /* Allocate lock resource */
    __HAL_UNLOCK(hdma);
 8007f60:	687b      	ldr	r3, [r7, #4]
 8007f62:	2200      	movs	r2, #0
 8007f64:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

    /* Get the CR register value */
    registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
 8007f68:	687b      	ldr	r3, [r7, #4]
 8007f6a:	681b      	ldr	r3, [r3, #0]
 8007f6c:	681b      	ldr	r3, [r3, #0]
 8007f6e:	617b      	str	r3, [r7, #20]

    /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */
    registerValue &= ((uint32_t)~(BDMA_CCR_PL    | BDMA_CCR_MSIZE   | BDMA_CCR_PSIZE  | \
 8007f70:	697a      	ldr	r2, [r7, #20]
 8007f72:	4b13      	ldr	r3, [pc, #76]	@ (8007fc0 <HAL_DMA_Init+0x44c>)
 8007f74:	4013      	ands	r3, r2
 8007f76:	617b      	str	r3, [r7, #20]
                                  BDMA_CCR_MINC  | BDMA_CCR_PINC    | BDMA_CCR_CIRC   | \
                                  BDMA_CCR_DIR   | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM    | \
                                  BDMA_CCR_CT));

    /* Prepare the DMA Channel configuration */
    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
 8007f78:	687b      	ldr	r3, [r7, #4]
 8007f7a:	689b      	ldr	r3, [r3, #8]
 8007f7c:	2b40      	cmp	r3, #64	@ 0x40
 8007f7e:	d021      	beq.n	8007fc4 <HAL_DMA_Init+0x450>
 8007f80:	687b      	ldr	r3, [r7, #4]
 8007f82:	689b      	ldr	r3, [r3, #8]
 8007f84:	2b80      	cmp	r3, #128	@ 0x80
 8007f86:	d102      	bne.n	8007f8e <HAL_DMA_Init+0x41a>
 8007f88:	f44f 4380 	mov.w	r3, #16384	@ 0x4000
 8007f8c:	e01b      	b.n	8007fc6 <HAL_DMA_Init+0x452>
 8007f8e:	2300      	movs	r3, #0
 8007f90:	e019      	b.n	8007fc6 <HAL_DMA_Init+0x452>
 8007f92:	bf00      	nop
 8007f94:	fe10803f 	.word	0xfe10803f
 8007f98:	5c001000 	.word	0x5c001000
 8007f9c:	ffff0000 	.word	0xffff0000
 8007fa0:	58025408 	.word	0x58025408
 8007fa4:	5802541c 	.word	0x5802541c
 8007fa8:	58025430 	.word	0x58025430
 8007fac:	58025444 	.word	0x58025444
 8007fb0:	58025458 	.word	0x58025458
 8007fb4:	5802546c 	.word	0x5802546c
 8007fb8:	58025480 	.word	0x58025480
 8007fbc:	58025494 	.word	0x58025494
 8007fc0:	fffe000f 	.word	0xfffe000f
 8007fc4:	2310      	movs	r3, #16
                      DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
 8007fc6:	687a      	ldr	r2, [r7, #4]
 8007fc8:	68d2      	ldr	r2, [r2, #12]
 8007fca:	08d2      	lsrs	r2, r2, #3
    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
 8007fcc:	431a      	orrs	r2, r3
                      DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
 8007fce:	687b      	ldr	r3, [r7, #4]
 8007fd0:	691b      	ldr	r3, [r3, #16]
 8007fd2:	08db      	lsrs	r3, r3, #3
                      DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
 8007fd4:	431a      	orrs	r2, r3
                      DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
 8007fd6:	687b      	ldr	r3, [r7, #4]
 8007fd8:	695b      	ldr	r3, [r3, #20]
 8007fda:	08db      	lsrs	r3, r3, #3
                      DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
 8007fdc:	431a      	orrs	r2, r3
                      DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
 8007fde:	687b      	ldr	r3, [r7, #4]
 8007fe0:	699b      	ldr	r3, [r3, #24]
 8007fe2:	08db      	lsrs	r3, r3, #3
                      DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
 8007fe4:	431a      	orrs	r2, r3
                      DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
 8007fe6:	687b      	ldr	r3, [r7, #4]
 8007fe8:	69db      	ldr	r3, [r3, #28]
 8007fea:	08db      	lsrs	r3, r3, #3
                      DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
 8007fec:	431a      	orrs	r2, r3
                      DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);
 8007fee:	687b      	ldr	r3, [r7, #4]
 8007ff0:	6a1b      	ldr	r3, [r3, #32]
 8007ff2:	091b      	lsrs	r3, r3, #4
                      DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
 8007ff4:	4313      	orrs	r3, r2
    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
 8007ff6:	697a      	ldr	r2, [r7, #20]
 8007ff8:	4313      	orrs	r3, r2
 8007ffa:	617b      	str	r3, [r7, #20]

    /* Write to DMA Channel CR register */
    ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;
 8007ffc:	687b      	ldr	r3, [r7, #4]
 8007ffe:	681b      	ldr	r3, [r3, #0]
 8008000:	697a      	ldr	r2, [r7, #20]
 8008002:	601a      	str	r2, [r3, #0]

    /* calculation of the channel index */
    hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
 8008004:	687b      	ldr	r3, [r7, #4]
 8008006:	681b      	ldr	r3, [r3, #0]
 8008008:	461a      	mov	r2, r3
 800800a:	4b6e      	ldr	r3, [pc, #440]	@ (80081c4 <HAL_DMA_Init+0x650>)
 800800c:	4413      	add	r3, r2
 800800e:	4a6e      	ldr	r2, [pc, #440]	@ (80081c8 <HAL_DMA_Init+0x654>)
 8008010:	fba2 2303 	umull	r2, r3, r2, r3
 8008014:	091b      	lsrs	r3, r3, #4
 8008016:	009a      	lsls	r2, r3, #2
 8008018:	687b      	ldr	r3, [r7, #4]
 800801a:	65da      	str	r2, [r3, #92]	@ 0x5c

    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
    DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
    regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
 800801c:	6878      	ldr	r0, [r7, #4]
 800801e:	f002 f9a9 	bl	800a374 <DMA_CalcBaseAndBitshift>
 8008022:	4603      	mov	r3, r0
 8008024:	60fb      	str	r3, [r7, #12]

    /* Clear all interrupt flags */
    regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
 8008026:	687b      	ldr	r3, [r7, #4]
 8008028:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800802a:	f003 031f 	and.w	r3, r3, #31
 800802e:	2201      	movs	r2, #1
 8008030:	409a      	lsls	r2, r3
 8008032:	68fb      	ldr	r3, [r7, #12]
 8008034:	605a      	str	r2, [r3, #4]
 8008036:	e008      	b.n	800804a <HAL_DMA_Init+0x4d6>
  }
  else
  {
    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
 8008038:	687b      	ldr	r3, [r7, #4]
 800803a:	2240      	movs	r2, #64	@ 0x40
 800803c:	655a      	str	r2, [r3, #84]	@ 0x54
    hdma->State     = HAL_DMA_STATE_ERROR;
 800803e:	687b      	ldr	r3, [r7, #4]
 8008040:	2203      	movs	r2, #3
 8008042:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

    return HAL_ERROR;
 8008046:	2301      	movs	r3, #1
 8008048:	e0b7      	b.n	80081ba <HAL_DMA_Init+0x646>
  }

  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
 800804a:	687b      	ldr	r3, [r7, #4]
 800804c:	681b      	ldr	r3, [r3, #0]
 800804e:	4a5f      	ldr	r2, [pc, #380]	@ (80081cc <HAL_DMA_Init+0x658>)
 8008050:	4293      	cmp	r3, r2
 8008052:	d072      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 8008054:	687b      	ldr	r3, [r7, #4]
 8008056:	681b      	ldr	r3, [r3, #0]
 8008058:	4a5d      	ldr	r2, [pc, #372]	@ (80081d0 <HAL_DMA_Init+0x65c>)
 800805a:	4293      	cmp	r3, r2
 800805c:	d06d      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 800805e:	687b      	ldr	r3, [r7, #4]
 8008060:	681b      	ldr	r3, [r3, #0]
 8008062:	4a5c      	ldr	r2, [pc, #368]	@ (80081d4 <HAL_DMA_Init+0x660>)
 8008064:	4293      	cmp	r3, r2
 8008066:	d068      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 8008068:	687b      	ldr	r3, [r7, #4]
 800806a:	681b      	ldr	r3, [r3, #0]
 800806c:	4a5a      	ldr	r2, [pc, #360]	@ (80081d8 <HAL_DMA_Init+0x664>)
 800806e:	4293      	cmp	r3, r2
 8008070:	d063      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 8008072:	687b      	ldr	r3, [r7, #4]
 8008074:	681b      	ldr	r3, [r3, #0]
 8008076:	4a59      	ldr	r2, [pc, #356]	@ (80081dc <HAL_DMA_Init+0x668>)
 8008078:	4293      	cmp	r3, r2
 800807a:	d05e      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 800807c:	687b      	ldr	r3, [r7, #4]
 800807e:	681b      	ldr	r3, [r3, #0]
 8008080:	4a57      	ldr	r2, [pc, #348]	@ (80081e0 <HAL_DMA_Init+0x66c>)
 8008082:	4293      	cmp	r3, r2
 8008084:	d059      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 8008086:	687b      	ldr	r3, [r7, #4]
 8008088:	681b      	ldr	r3, [r3, #0]
 800808a:	4a56      	ldr	r2, [pc, #344]	@ (80081e4 <HAL_DMA_Init+0x670>)
 800808c:	4293      	cmp	r3, r2
 800808e:	d054      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 8008090:	687b      	ldr	r3, [r7, #4]
 8008092:	681b      	ldr	r3, [r3, #0]
 8008094:	4a54      	ldr	r2, [pc, #336]	@ (80081e8 <HAL_DMA_Init+0x674>)
 8008096:	4293      	cmp	r3, r2
 8008098:	d04f      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 800809a:	687b      	ldr	r3, [r7, #4]
 800809c:	681b      	ldr	r3, [r3, #0]
 800809e:	4a53      	ldr	r2, [pc, #332]	@ (80081ec <HAL_DMA_Init+0x678>)
 80080a0:	4293      	cmp	r3, r2
 80080a2:	d04a      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 80080a4:	687b      	ldr	r3, [r7, #4]
 80080a6:	681b      	ldr	r3, [r3, #0]
 80080a8:	4a51      	ldr	r2, [pc, #324]	@ (80081f0 <HAL_DMA_Init+0x67c>)
 80080aa:	4293      	cmp	r3, r2
 80080ac:	d045      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 80080ae:	687b      	ldr	r3, [r7, #4]
 80080b0:	681b      	ldr	r3, [r3, #0]
 80080b2:	4a50      	ldr	r2, [pc, #320]	@ (80081f4 <HAL_DMA_Init+0x680>)
 80080b4:	4293      	cmp	r3, r2
 80080b6:	d040      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 80080b8:	687b      	ldr	r3, [r7, #4]
 80080ba:	681b      	ldr	r3, [r3, #0]
 80080bc:	4a4e      	ldr	r2, [pc, #312]	@ (80081f8 <HAL_DMA_Init+0x684>)
 80080be:	4293      	cmp	r3, r2
 80080c0:	d03b      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 80080c2:	687b      	ldr	r3, [r7, #4]
 80080c4:	681b      	ldr	r3, [r3, #0]
 80080c6:	4a4d      	ldr	r2, [pc, #308]	@ (80081fc <HAL_DMA_Init+0x688>)
 80080c8:	4293      	cmp	r3, r2
 80080ca:	d036      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 80080cc:	687b      	ldr	r3, [r7, #4]
 80080ce:	681b      	ldr	r3, [r3, #0]
 80080d0:	4a4b      	ldr	r2, [pc, #300]	@ (8008200 <HAL_DMA_Init+0x68c>)
 80080d2:	4293      	cmp	r3, r2
 80080d4:	d031      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 80080d6:	687b      	ldr	r3, [r7, #4]
 80080d8:	681b      	ldr	r3, [r3, #0]
 80080da:	4a4a      	ldr	r2, [pc, #296]	@ (8008204 <HAL_DMA_Init+0x690>)
 80080dc:	4293      	cmp	r3, r2
 80080de:	d02c      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 80080e0:	687b      	ldr	r3, [r7, #4]
 80080e2:	681b      	ldr	r3, [r3, #0]
 80080e4:	4a48      	ldr	r2, [pc, #288]	@ (8008208 <HAL_DMA_Init+0x694>)
 80080e6:	4293      	cmp	r3, r2
 80080e8:	d027      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 80080ea:	687b      	ldr	r3, [r7, #4]
 80080ec:	681b      	ldr	r3, [r3, #0]
 80080ee:	4a47      	ldr	r2, [pc, #284]	@ (800820c <HAL_DMA_Init+0x698>)
 80080f0:	4293      	cmp	r3, r2
 80080f2:	d022      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 80080f4:	687b      	ldr	r3, [r7, #4]
 80080f6:	681b      	ldr	r3, [r3, #0]
 80080f8:	4a45      	ldr	r2, [pc, #276]	@ (8008210 <HAL_DMA_Init+0x69c>)
 80080fa:	4293      	cmp	r3, r2
 80080fc:	d01d      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 80080fe:	687b      	ldr	r3, [r7, #4]
 8008100:	681b      	ldr	r3, [r3, #0]
 8008102:	4a44      	ldr	r2, [pc, #272]	@ (8008214 <HAL_DMA_Init+0x6a0>)
 8008104:	4293      	cmp	r3, r2
 8008106:	d018      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 8008108:	687b      	ldr	r3, [r7, #4]
 800810a:	681b      	ldr	r3, [r3, #0]
 800810c:	4a42      	ldr	r2, [pc, #264]	@ (8008218 <HAL_DMA_Init+0x6a4>)
 800810e:	4293      	cmp	r3, r2
 8008110:	d013      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 8008112:	687b      	ldr	r3, [r7, #4]
 8008114:	681b      	ldr	r3, [r3, #0]
 8008116:	4a41      	ldr	r2, [pc, #260]	@ (800821c <HAL_DMA_Init+0x6a8>)
 8008118:	4293      	cmp	r3, r2
 800811a:	d00e      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 800811c:	687b      	ldr	r3, [r7, #4]
 800811e:	681b      	ldr	r3, [r3, #0]
 8008120:	4a3f      	ldr	r2, [pc, #252]	@ (8008220 <HAL_DMA_Init+0x6ac>)
 8008122:	4293      	cmp	r3, r2
 8008124:	d009      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 8008126:	687b      	ldr	r3, [r7, #4]
 8008128:	681b      	ldr	r3, [r3, #0]
 800812a:	4a3e      	ldr	r2, [pc, #248]	@ (8008224 <HAL_DMA_Init+0x6b0>)
 800812c:	4293      	cmp	r3, r2
 800812e:	d004      	beq.n	800813a <HAL_DMA_Init+0x5c6>
 8008130:	687b      	ldr	r3, [r7, #4]
 8008132:	681b      	ldr	r3, [r3, #0]
 8008134:	4a3c      	ldr	r2, [pc, #240]	@ (8008228 <HAL_DMA_Init+0x6b4>)
 8008136:	4293      	cmp	r3, r2
 8008138:	d101      	bne.n	800813e <HAL_DMA_Init+0x5ca>
 800813a:	2301      	movs	r3, #1
 800813c:	e000      	b.n	8008140 <HAL_DMA_Init+0x5cc>
 800813e:	2300      	movs	r3, #0
 8008140:	2b00      	cmp	r3, #0
 8008142:	d032      	beq.n	80081aa <HAL_DMA_Init+0x636>
  {
    /* Initialize parameters for DMAMUX channel :
    DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
    */
    DMA_CalcDMAMUXChannelBaseAndMask(hdma);
 8008144:	6878      	ldr	r0, [r7, #4]
 8008146:	f002 fa43 	bl	800a5d0 <DMA_CalcDMAMUXChannelBaseAndMask>

    if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
 800814a:	687b      	ldr	r3, [r7, #4]
 800814c:	689b      	ldr	r3, [r3, #8]
 800814e:	2b80      	cmp	r3, #128	@ 0x80
 8008150:	d102      	bne.n	8008158 <HAL_DMA_Init+0x5e4>
    {
      /* if memory to memory force the request to 0*/
      hdma->Init.Request = DMA_REQUEST_MEM2MEM;
 8008152:	687b      	ldr	r3, [r7, #4]
 8008154:	2200      	movs	r2, #0
 8008156:	605a      	str	r2, [r3, #4]
    }

    /* Set peripheral request  to DMAMUX channel */
    hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
 8008158:	687b      	ldr	r3, [r7, #4]
 800815a:	685a      	ldr	r2, [r3, #4]
 800815c:	687b      	ldr	r3, [r7, #4]
 800815e:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8008160:	b2d2      	uxtb	r2, r2
 8008162:	601a      	str	r2, [r3, #0]

    /* Clear the DMAMUX synchro overrun flag */
    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 8008164:	687b      	ldr	r3, [r7, #4]
 8008166:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8008168:	687a      	ldr	r2, [r7, #4]
 800816a:	6e92      	ldr	r2, [r2, #104]	@ 0x68
 800816c:	605a      	str	r2, [r3, #4]

    /* Initialize parameters for DMAMUX request generator :
    if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
    */
    if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
 800816e:	687b      	ldr	r3, [r7, #4]
 8008170:	685b      	ldr	r3, [r3, #4]
 8008172:	2b00      	cmp	r3, #0
 8008174:	d010      	beq.n	8008198 <HAL_DMA_Init+0x624>
 8008176:	687b      	ldr	r3, [r7, #4]
 8008178:	685b      	ldr	r3, [r3, #4]
 800817a:	2b08      	cmp	r3, #8
 800817c:	d80c      	bhi.n	8008198 <HAL_DMA_Init+0x624>
    {
      /* Initialize parameters for DMAMUX request generator :
      DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
      DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
 800817e:	6878      	ldr	r0, [r7, #4]
 8008180:	f002 fac0 	bl	800a704 <DMA_CalcDMAMUXRequestGenBaseAndMask>

      /* Reset the DMAMUX request generator register */
      hdma->DMAmuxRequestGen->RGCR = 0U;
 8008184:	687b      	ldr	r3, [r7, #4]
 8008186:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8008188:	2200      	movs	r2, #0
 800818a:	601a      	str	r2, [r3, #0]

      /* Clear the DMAMUX request generator overrun flag */
      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 800818c:	687b      	ldr	r3, [r7, #4]
 800818e:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8008190:	687a      	ldr	r2, [r7, #4]
 8008192:	6f52      	ldr	r2, [r2, #116]	@ 0x74
 8008194:	605a      	str	r2, [r3, #4]
 8008196:	e008      	b.n	80081aa <HAL_DMA_Init+0x636>
    }
    else
    {
      hdma->DMAmuxRequestGen = 0U;
 8008198:	687b      	ldr	r3, [r7, #4]
 800819a:	2200      	movs	r2, #0
 800819c:	66da      	str	r2, [r3, #108]	@ 0x6c
      hdma->DMAmuxRequestGenStatus = 0U;
 800819e:	687b      	ldr	r3, [r7, #4]
 80081a0:	2200      	movs	r2, #0
 80081a2:	671a      	str	r2, [r3, #112]	@ 0x70
      hdma->DMAmuxRequestGenStatusMask = 0U;
 80081a4:	687b      	ldr	r3, [r7, #4]
 80081a6:	2200      	movs	r2, #0
 80081a8:	675a      	str	r2, [r3, #116]	@ 0x74
    }
  }

  /* Initialize the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 80081aa:	687b      	ldr	r3, [r7, #4]
 80081ac:	2200      	movs	r2, #0
 80081ae:	655a      	str	r2, [r3, #84]	@ 0x54

  /* Initialize the DMA state */
  hdma->State = HAL_DMA_STATE_READY;
 80081b0:	687b      	ldr	r3, [r7, #4]
 80081b2:	2201      	movs	r2, #1
 80081b4:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

  return HAL_OK;
 80081b8:	2300      	movs	r3, #0
}
 80081ba:	4618      	mov	r0, r3
 80081bc:	3718      	adds	r7, #24
 80081be:	46bd      	mov	sp, r7
 80081c0:	bd80      	pop	{r7, pc}
 80081c2:	bf00      	nop
 80081c4:	a7fdabf8 	.word	0xa7fdabf8
 80081c8:	cccccccd 	.word	0xcccccccd
 80081cc:	40020010 	.word	0x40020010
 80081d0:	40020028 	.word	0x40020028
 80081d4:	40020040 	.word	0x40020040
 80081d8:	40020058 	.word	0x40020058
 80081dc:	40020070 	.word	0x40020070
 80081e0:	40020088 	.word	0x40020088
 80081e4:	400200a0 	.word	0x400200a0
 80081e8:	400200b8 	.word	0x400200b8
 80081ec:	40020410 	.word	0x40020410
 80081f0:	40020428 	.word	0x40020428
 80081f4:	40020440 	.word	0x40020440
 80081f8:	40020458 	.word	0x40020458
 80081fc:	40020470 	.word	0x40020470
 8008200:	40020488 	.word	0x40020488
 8008204:	400204a0 	.word	0x400204a0
 8008208:	400204b8 	.word	0x400204b8
 800820c:	58025408 	.word	0x58025408
 8008210:	5802541c 	.word	0x5802541c
 8008214:	58025430 	.word	0x58025430
 8008218:	58025444 	.word	0x58025444
 800821c:	58025458 	.word	0x58025458
 8008220:	5802546c 	.word	0x5802546c
 8008224:	58025480 	.word	0x58025480
 8008228:	58025494 	.word	0x58025494

0800822c <HAL_DMA_Start_IT>:
  * @param  DstAddress: The destination memory Buffer address
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 800822c:	b580      	push	{r7, lr}
 800822e:	b086      	sub	sp, #24
 8008230:	af00      	add	r7, sp, #0
 8008232:	60f8      	str	r0, [r7, #12]
 8008234:	60b9      	str	r1, [r7, #8]
 8008236:	607a      	str	r2, [r7, #4]
 8008238:	603b      	str	r3, [r7, #0]
  HAL_StatusTypeDef status = HAL_OK;
 800823a:	2300      	movs	r3, #0
 800823c:	75fb      	strb	r3, [r7, #23]

  /* Check the parameters */
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));

  /* Check the DMA peripheral handle */
  if(hdma == NULL)
 800823e:	68fb      	ldr	r3, [r7, #12]
 8008240:	2b00      	cmp	r3, #0
 8008242:	d101      	bne.n	8008248 <HAL_DMA_Start_IT+0x1c>
  {
    return HAL_ERROR;
 8008244:	2301      	movs	r3, #1
 8008246:	e226      	b.n	8008696 <HAL_DMA_Start_IT+0x46a>
  }

  /* Process locked */
  __HAL_LOCK(hdma);
 8008248:	68fb      	ldr	r3, [r7, #12]
 800824a:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 800824e:	2b01      	cmp	r3, #1
 8008250:	d101      	bne.n	8008256 <HAL_DMA_Start_IT+0x2a>
 8008252:	2302      	movs	r3, #2
 8008254:	e21f      	b.n	8008696 <HAL_DMA_Start_IT+0x46a>
 8008256:	68fb      	ldr	r3, [r7, #12]
 8008258:	2201      	movs	r2, #1
 800825a:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

  if(HAL_DMA_STATE_READY == hdma->State)
 800825e:	68fb      	ldr	r3, [r7, #12]
 8008260:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
 8008264:	b2db      	uxtb	r3, r3
 8008266:	2b01      	cmp	r3, #1
 8008268:	f040 820a 	bne.w	8008680 <HAL_DMA_Start_IT+0x454>
  {
    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 800826c:	68fb      	ldr	r3, [r7, #12]
 800826e:	2202      	movs	r2, #2
 8008270:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

    /* Initialize the error code */
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8008274:	68fb      	ldr	r3, [r7, #12]
 8008276:	2200      	movs	r2, #0
 8008278:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);
 800827a:	68fb      	ldr	r3, [r7, #12]
 800827c:	681b      	ldr	r3, [r3, #0]
 800827e:	4a68      	ldr	r2, [pc, #416]	@ (8008420 <HAL_DMA_Start_IT+0x1f4>)
 8008280:	4293      	cmp	r3, r2
 8008282:	d04a      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 8008284:	68fb      	ldr	r3, [r7, #12]
 8008286:	681b      	ldr	r3, [r3, #0]
 8008288:	4a66      	ldr	r2, [pc, #408]	@ (8008424 <HAL_DMA_Start_IT+0x1f8>)
 800828a:	4293      	cmp	r3, r2
 800828c:	d045      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 800828e:	68fb      	ldr	r3, [r7, #12]
 8008290:	681b      	ldr	r3, [r3, #0]
 8008292:	4a65      	ldr	r2, [pc, #404]	@ (8008428 <HAL_DMA_Start_IT+0x1fc>)
 8008294:	4293      	cmp	r3, r2
 8008296:	d040      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 8008298:	68fb      	ldr	r3, [r7, #12]
 800829a:	681b      	ldr	r3, [r3, #0]
 800829c:	4a63      	ldr	r2, [pc, #396]	@ (800842c <HAL_DMA_Start_IT+0x200>)
 800829e:	4293      	cmp	r3, r2
 80082a0:	d03b      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 80082a2:	68fb      	ldr	r3, [r7, #12]
 80082a4:	681b      	ldr	r3, [r3, #0]
 80082a6:	4a62      	ldr	r2, [pc, #392]	@ (8008430 <HAL_DMA_Start_IT+0x204>)
 80082a8:	4293      	cmp	r3, r2
 80082aa:	d036      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 80082ac:	68fb      	ldr	r3, [r7, #12]
 80082ae:	681b      	ldr	r3, [r3, #0]
 80082b0:	4a60      	ldr	r2, [pc, #384]	@ (8008434 <HAL_DMA_Start_IT+0x208>)
 80082b2:	4293      	cmp	r3, r2
 80082b4:	d031      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 80082b6:	68fb      	ldr	r3, [r7, #12]
 80082b8:	681b      	ldr	r3, [r3, #0]
 80082ba:	4a5f      	ldr	r2, [pc, #380]	@ (8008438 <HAL_DMA_Start_IT+0x20c>)
 80082bc:	4293      	cmp	r3, r2
 80082be:	d02c      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 80082c0:	68fb      	ldr	r3, [r7, #12]
 80082c2:	681b      	ldr	r3, [r3, #0]
 80082c4:	4a5d      	ldr	r2, [pc, #372]	@ (800843c <HAL_DMA_Start_IT+0x210>)
 80082c6:	4293      	cmp	r3, r2
 80082c8:	d027      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 80082ca:	68fb      	ldr	r3, [r7, #12]
 80082cc:	681b      	ldr	r3, [r3, #0]
 80082ce:	4a5c      	ldr	r2, [pc, #368]	@ (8008440 <HAL_DMA_Start_IT+0x214>)
 80082d0:	4293      	cmp	r3, r2
 80082d2:	d022      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 80082d4:	68fb      	ldr	r3, [r7, #12]
 80082d6:	681b      	ldr	r3, [r3, #0]
 80082d8:	4a5a      	ldr	r2, [pc, #360]	@ (8008444 <HAL_DMA_Start_IT+0x218>)
 80082da:	4293      	cmp	r3, r2
 80082dc:	d01d      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 80082de:	68fb      	ldr	r3, [r7, #12]
 80082e0:	681b      	ldr	r3, [r3, #0]
 80082e2:	4a59      	ldr	r2, [pc, #356]	@ (8008448 <HAL_DMA_Start_IT+0x21c>)
 80082e4:	4293      	cmp	r3, r2
 80082e6:	d018      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 80082e8:	68fb      	ldr	r3, [r7, #12]
 80082ea:	681b      	ldr	r3, [r3, #0]
 80082ec:	4a57      	ldr	r2, [pc, #348]	@ (800844c <HAL_DMA_Start_IT+0x220>)
 80082ee:	4293      	cmp	r3, r2
 80082f0:	d013      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 80082f2:	68fb      	ldr	r3, [r7, #12]
 80082f4:	681b      	ldr	r3, [r3, #0]
 80082f6:	4a56      	ldr	r2, [pc, #344]	@ (8008450 <HAL_DMA_Start_IT+0x224>)
 80082f8:	4293      	cmp	r3, r2
 80082fa:	d00e      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 80082fc:	68fb      	ldr	r3, [r7, #12]
 80082fe:	681b      	ldr	r3, [r3, #0]
 8008300:	4a54      	ldr	r2, [pc, #336]	@ (8008454 <HAL_DMA_Start_IT+0x228>)
 8008302:	4293      	cmp	r3, r2
 8008304:	d009      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 8008306:	68fb      	ldr	r3, [r7, #12]
 8008308:	681b      	ldr	r3, [r3, #0]
 800830a:	4a53      	ldr	r2, [pc, #332]	@ (8008458 <HAL_DMA_Start_IT+0x22c>)
 800830c:	4293      	cmp	r3, r2
 800830e:	d004      	beq.n	800831a <HAL_DMA_Start_IT+0xee>
 8008310:	68fb      	ldr	r3, [r7, #12]
 8008312:	681b      	ldr	r3, [r3, #0]
 8008314:	4a51      	ldr	r2, [pc, #324]	@ (800845c <HAL_DMA_Start_IT+0x230>)
 8008316:	4293      	cmp	r3, r2
 8008318:	d108      	bne.n	800832c <HAL_DMA_Start_IT+0x100>
 800831a:	68fb      	ldr	r3, [r7, #12]
 800831c:	681b      	ldr	r3, [r3, #0]
 800831e:	681a      	ldr	r2, [r3, #0]
 8008320:	68fb      	ldr	r3, [r7, #12]
 8008322:	681b      	ldr	r3, [r3, #0]
 8008324:	f022 0201 	bic.w	r2, r2, #1
 8008328:	601a      	str	r2, [r3, #0]
 800832a:	e007      	b.n	800833c <HAL_DMA_Start_IT+0x110>
 800832c:	68fb      	ldr	r3, [r7, #12]
 800832e:	681b      	ldr	r3, [r3, #0]
 8008330:	681a      	ldr	r2, [r3, #0]
 8008332:	68fb      	ldr	r3, [r7, #12]
 8008334:	681b      	ldr	r3, [r3, #0]
 8008336:	f022 0201 	bic.w	r2, r2, #1
 800833a:	601a      	str	r2, [r3, #0]

    /* Configure the source, destination address and the data length */
    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
 800833c:	683b      	ldr	r3, [r7, #0]
 800833e:	687a      	ldr	r2, [r7, #4]
 8008340:	68b9      	ldr	r1, [r7, #8]
 8008342:	68f8      	ldr	r0, [r7, #12]
 8008344:	f001 fe6a 	bl	800a01c <DMA_SetConfig>

    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 8008348:	68fb      	ldr	r3, [r7, #12]
 800834a:	681b      	ldr	r3, [r3, #0]
 800834c:	4a34      	ldr	r2, [pc, #208]	@ (8008420 <HAL_DMA_Start_IT+0x1f4>)
 800834e:	4293      	cmp	r3, r2
 8008350:	d04a      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 8008352:	68fb      	ldr	r3, [r7, #12]
 8008354:	681b      	ldr	r3, [r3, #0]
 8008356:	4a33      	ldr	r2, [pc, #204]	@ (8008424 <HAL_DMA_Start_IT+0x1f8>)
 8008358:	4293      	cmp	r3, r2
 800835a:	d045      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 800835c:	68fb      	ldr	r3, [r7, #12]
 800835e:	681b      	ldr	r3, [r3, #0]
 8008360:	4a31      	ldr	r2, [pc, #196]	@ (8008428 <HAL_DMA_Start_IT+0x1fc>)
 8008362:	4293      	cmp	r3, r2
 8008364:	d040      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 8008366:	68fb      	ldr	r3, [r7, #12]
 8008368:	681b      	ldr	r3, [r3, #0]
 800836a:	4a30      	ldr	r2, [pc, #192]	@ (800842c <HAL_DMA_Start_IT+0x200>)
 800836c:	4293      	cmp	r3, r2
 800836e:	d03b      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 8008370:	68fb      	ldr	r3, [r7, #12]
 8008372:	681b      	ldr	r3, [r3, #0]
 8008374:	4a2e      	ldr	r2, [pc, #184]	@ (8008430 <HAL_DMA_Start_IT+0x204>)
 8008376:	4293      	cmp	r3, r2
 8008378:	d036      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 800837a:	68fb      	ldr	r3, [r7, #12]
 800837c:	681b      	ldr	r3, [r3, #0]
 800837e:	4a2d      	ldr	r2, [pc, #180]	@ (8008434 <HAL_DMA_Start_IT+0x208>)
 8008380:	4293      	cmp	r3, r2
 8008382:	d031      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 8008384:	68fb      	ldr	r3, [r7, #12]
 8008386:	681b      	ldr	r3, [r3, #0]
 8008388:	4a2b      	ldr	r2, [pc, #172]	@ (8008438 <HAL_DMA_Start_IT+0x20c>)
 800838a:	4293      	cmp	r3, r2
 800838c:	d02c      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 800838e:	68fb      	ldr	r3, [r7, #12]
 8008390:	681b      	ldr	r3, [r3, #0]
 8008392:	4a2a      	ldr	r2, [pc, #168]	@ (800843c <HAL_DMA_Start_IT+0x210>)
 8008394:	4293      	cmp	r3, r2
 8008396:	d027      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 8008398:	68fb      	ldr	r3, [r7, #12]
 800839a:	681b      	ldr	r3, [r3, #0]
 800839c:	4a28      	ldr	r2, [pc, #160]	@ (8008440 <HAL_DMA_Start_IT+0x214>)
 800839e:	4293      	cmp	r3, r2
 80083a0:	d022      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 80083a2:	68fb      	ldr	r3, [r7, #12]
 80083a4:	681b      	ldr	r3, [r3, #0]
 80083a6:	4a27      	ldr	r2, [pc, #156]	@ (8008444 <HAL_DMA_Start_IT+0x218>)
 80083a8:	4293      	cmp	r3, r2
 80083aa:	d01d      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 80083ac:	68fb      	ldr	r3, [r7, #12]
 80083ae:	681b      	ldr	r3, [r3, #0]
 80083b0:	4a25      	ldr	r2, [pc, #148]	@ (8008448 <HAL_DMA_Start_IT+0x21c>)
 80083b2:	4293      	cmp	r3, r2
 80083b4:	d018      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 80083b6:	68fb      	ldr	r3, [r7, #12]
 80083b8:	681b      	ldr	r3, [r3, #0]
 80083ba:	4a24      	ldr	r2, [pc, #144]	@ (800844c <HAL_DMA_Start_IT+0x220>)
 80083bc:	4293      	cmp	r3, r2
 80083be:	d013      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 80083c0:	68fb      	ldr	r3, [r7, #12]
 80083c2:	681b      	ldr	r3, [r3, #0]
 80083c4:	4a22      	ldr	r2, [pc, #136]	@ (8008450 <HAL_DMA_Start_IT+0x224>)
 80083c6:	4293      	cmp	r3, r2
 80083c8:	d00e      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 80083ca:	68fb      	ldr	r3, [r7, #12]
 80083cc:	681b      	ldr	r3, [r3, #0]
 80083ce:	4a21      	ldr	r2, [pc, #132]	@ (8008454 <HAL_DMA_Start_IT+0x228>)
 80083d0:	4293      	cmp	r3, r2
 80083d2:	d009      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 80083d4:	68fb      	ldr	r3, [r7, #12]
 80083d6:	681b      	ldr	r3, [r3, #0]
 80083d8:	4a1f      	ldr	r2, [pc, #124]	@ (8008458 <HAL_DMA_Start_IT+0x22c>)
 80083da:	4293      	cmp	r3, r2
 80083dc:	d004      	beq.n	80083e8 <HAL_DMA_Start_IT+0x1bc>
 80083de:	68fb      	ldr	r3, [r7, #12]
 80083e0:	681b      	ldr	r3, [r3, #0]
 80083e2:	4a1e      	ldr	r2, [pc, #120]	@ (800845c <HAL_DMA_Start_IT+0x230>)
 80083e4:	4293      	cmp	r3, r2
 80083e6:	d101      	bne.n	80083ec <HAL_DMA_Start_IT+0x1c0>
 80083e8:	2301      	movs	r3, #1
 80083ea:	e000      	b.n	80083ee <HAL_DMA_Start_IT+0x1c2>
 80083ec:	2300      	movs	r3, #0
 80083ee:	2b00      	cmp	r3, #0
 80083f0:	d036      	beq.n	8008460 <HAL_DMA_Start_IT+0x234>
    {
      /* Enable Common interrupts*/
      MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
 80083f2:	68fb      	ldr	r3, [r7, #12]
 80083f4:	681b      	ldr	r3, [r3, #0]
 80083f6:	681b      	ldr	r3, [r3, #0]
 80083f8:	f023 021e 	bic.w	r2, r3, #30
 80083fc:	68fb      	ldr	r3, [r7, #12]
 80083fe:	681b      	ldr	r3, [r3, #0]
 8008400:	f042 0216 	orr.w	r2, r2, #22
 8008404:	601a      	str	r2, [r3, #0]

      if(hdma->XferHalfCpltCallback != NULL)
 8008406:	68fb      	ldr	r3, [r7, #12]
 8008408:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800840a:	2b00      	cmp	r3, #0
 800840c:	d03e      	beq.n	800848c <HAL_DMA_Start_IT+0x260>
      {
        /* Enable Half Transfer IT if corresponding Callback is set */
        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
 800840e:	68fb      	ldr	r3, [r7, #12]
 8008410:	681b      	ldr	r3, [r3, #0]
 8008412:	681a      	ldr	r2, [r3, #0]
 8008414:	68fb      	ldr	r3, [r7, #12]
 8008416:	681b      	ldr	r3, [r3, #0]
 8008418:	f042 0208 	orr.w	r2, r2, #8
 800841c:	601a      	str	r2, [r3, #0]
 800841e:	e035      	b.n	800848c <HAL_DMA_Start_IT+0x260>
 8008420:	40020010 	.word	0x40020010
 8008424:	40020028 	.word	0x40020028
 8008428:	40020040 	.word	0x40020040
 800842c:	40020058 	.word	0x40020058
 8008430:	40020070 	.word	0x40020070
 8008434:	40020088 	.word	0x40020088
 8008438:	400200a0 	.word	0x400200a0
 800843c:	400200b8 	.word	0x400200b8
 8008440:	40020410 	.word	0x40020410
 8008444:	40020428 	.word	0x40020428
 8008448:	40020440 	.word	0x40020440
 800844c:	40020458 	.word	0x40020458
 8008450:	40020470 	.word	0x40020470
 8008454:	40020488 	.word	0x40020488
 8008458:	400204a0 	.word	0x400204a0
 800845c:	400204b8 	.word	0x400204b8
      }
    }
    else /* BDMA channel */
    {
      /* Enable Common interrupts */
      MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
 8008460:	68fb      	ldr	r3, [r7, #12]
 8008462:	681b      	ldr	r3, [r3, #0]
 8008464:	681b      	ldr	r3, [r3, #0]
 8008466:	f023 020e 	bic.w	r2, r3, #14
 800846a:	68fb      	ldr	r3, [r7, #12]
 800846c:	681b      	ldr	r3, [r3, #0]
 800846e:	f042 020a 	orr.w	r2, r2, #10
 8008472:	601a      	str	r2, [r3, #0]

      if(hdma->XferHalfCpltCallback != NULL)
 8008474:	68fb      	ldr	r3, [r7, #12]
 8008476:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8008478:	2b00      	cmp	r3, #0
 800847a:	d007      	beq.n	800848c <HAL_DMA_Start_IT+0x260>
      {
        /*Enable Half Transfer IT if corresponding Callback is set */
        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
 800847c:	68fb      	ldr	r3, [r7, #12]
 800847e:	681b      	ldr	r3, [r3, #0]
 8008480:	681a      	ldr	r2, [r3, #0]
 8008482:	68fb      	ldr	r3, [r7, #12]
 8008484:	681b      	ldr	r3, [r3, #0]
 8008486:	f042 0204 	orr.w	r2, r2, #4
 800848a:	601a      	str	r2, [r3, #0]
      }
    }

    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
 800848c:	68fb      	ldr	r3, [r7, #12]
 800848e:	681b      	ldr	r3, [r3, #0]
 8008490:	4a83      	ldr	r2, [pc, #524]	@ (80086a0 <HAL_DMA_Start_IT+0x474>)
 8008492:	4293      	cmp	r3, r2
 8008494:	d072      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 8008496:	68fb      	ldr	r3, [r7, #12]
 8008498:	681b      	ldr	r3, [r3, #0]
 800849a:	4a82      	ldr	r2, [pc, #520]	@ (80086a4 <HAL_DMA_Start_IT+0x478>)
 800849c:	4293      	cmp	r3, r2
 800849e:	d06d      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 80084a0:	68fb      	ldr	r3, [r7, #12]
 80084a2:	681b      	ldr	r3, [r3, #0]
 80084a4:	4a80      	ldr	r2, [pc, #512]	@ (80086a8 <HAL_DMA_Start_IT+0x47c>)
 80084a6:	4293      	cmp	r3, r2
 80084a8:	d068      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 80084aa:	68fb      	ldr	r3, [r7, #12]
 80084ac:	681b      	ldr	r3, [r3, #0]
 80084ae:	4a7f      	ldr	r2, [pc, #508]	@ (80086ac <HAL_DMA_Start_IT+0x480>)
 80084b0:	4293      	cmp	r3, r2
 80084b2:	d063      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 80084b4:	68fb      	ldr	r3, [r7, #12]
 80084b6:	681b      	ldr	r3, [r3, #0]
 80084b8:	4a7d      	ldr	r2, [pc, #500]	@ (80086b0 <HAL_DMA_Start_IT+0x484>)
 80084ba:	4293      	cmp	r3, r2
 80084bc:	d05e      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 80084be:	68fb      	ldr	r3, [r7, #12]
 80084c0:	681b      	ldr	r3, [r3, #0]
 80084c2:	4a7c      	ldr	r2, [pc, #496]	@ (80086b4 <HAL_DMA_Start_IT+0x488>)
 80084c4:	4293      	cmp	r3, r2
 80084c6:	d059      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 80084c8:	68fb      	ldr	r3, [r7, #12]
 80084ca:	681b      	ldr	r3, [r3, #0]
 80084cc:	4a7a      	ldr	r2, [pc, #488]	@ (80086b8 <HAL_DMA_Start_IT+0x48c>)
 80084ce:	4293      	cmp	r3, r2
 80084d0:	d054      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 80084d2:	68fb      	ldr	r3, [r7, #12]
 80084d4:	681b      	ldr	r3, [r3, #0]
 80084d6:	4a79      	ldr	r2, [pc, #484]	@ (80086bc <HAL_DMA_Start_IT+0x490>)
 80084d8:	4293      	cmp	r3, r2
 80084da:	d04f      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 80084dc:	68fb      	ldr	r3, [r7, #12]
 80084de:	681b      	ldr	r3, [r3, #0]
 80084e0:	4a77      	ldr	r2, [pc, #476]	@ (80086c0 <HAL_DMA_Start_IT+0x494>)
 80084e2:	4293      	cmp	r3, r2
 80084e4:	d04a      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 80084e6:	68fb      	ldr	r3, [r7, #12]
 80084e8:	681b      	ldr	r3, [r3, #0]
 80084ea:	4a76      	ldr	r2, [pc, #472]	@ (80086c4 <HAL_DMA_Start_IT+0x498>)
 80084ec:	4293      	cmp	r3, r2
 80084ee:	d045      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 80084f0:	68fb      	ldr	r3, [r7, #12]
 80084f2:	681b      	ldr	r3, [r3, #0]
 80084f4:	4a74      	ldr	r2, [pc, #464]	@ (80086c8 <HAL_DMA_Start_IT+0x49c>)
 80084f6:	4293      	cmp	r3, r2
 80084f8:	d040      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 80084fa:	68fb      	ldr	r3, [r7, #12]
 80084fc:	681b      	ldr	r3, [r3, #0]
 80084fe:	4a73      	ldr	r2, [pc, #460]	@ (80086cc <HAL_DMA_Start_IT+0x4a0>)
 8008500:	4293      	cmp	r3, r2
 8008502:	d03b      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 8008504:	68fb      	ldr	r3, [r7, #12]
 8008506:	681b      	ldr	r3, [r3, #0]
 8008508:	4a71      	ldr	r2, [pc, #452]	@ (80086d0 <HAL_DMA_Start_IT+0x4a4>)
 800850a:	4293      	cmp	r3, r2
 800850c:	d036      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 800850e:	68fb      	ldr	r3, [r7, #12]
 8008510:	681b      	ldr	r3, [r3, #0]
 8008512:	4a70      	ldr	r2, [pc, #448]	@ (80086d4 <HAL_DMA_Start_IT+0x4a8>)
 8008514:	4293      	cmp	r3, r2
 8008516:	d031      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 8008518:	68fb      	ldr	r3, [r7, #12]
 800851a:	681b      	ldr	r3, [r3, #0]
 800851c:	4a6e      	ldr	r2, [pc, #440]	@ (80086d8 <HAL_DMA_Start_IT+0x4ac>)
 800851e:	4293      	cmp	r3, r2
 8008520:	d02c      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 8008522:	68fb      	ldr	r3, [r7, #12]
 8008524:	681b      	ldr	r3, [r3, #0]
 8008526:	4a6d      	ldr	r2, [pc, #436]	@ (80086dc <HAL_DMA_Start_IT+0x4b0>)
 8008528:	4293      	cmp	r3, r2
 800852a:	d027      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 800852c:	68fb      	ldr	r3, [r7, #12]
 800852e:	681b      	ldr	r3, [r3, #0]
 8008530:	4a6b      	ldr	r2, [pc, #428]	@ (80086e0 <HAL_DMA_Start_IT+0x4b4>)
 8008532:	4293      	cmp	r3, r2
 8008534:	d022      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 8008536:	68fb      	ldr	r3, [r7, #12]
 8008538:	681b      	ldr	r3, [r3, #0]
 800853a:	4a6a      	ldr	r2, [pc, #424]	@ (80086e4 <HAL_DMA_Start_IT+0x4b8>)
 800853c:	4293      	cmp	r3, r2
 800853e:	d01d      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 8008540:	68fb      	ldr	r3, [r7, #12]
 8008542:	681b      	ldr	r3, [r3, #0]
 8008544:	4a68      	ldr	r2, [pc, #416]	@ (80086e8 <HAL_DMA_Start_IT+0x4bc>)
 8008546:	4293      	cmp	r3, r2
 8008548:	d018      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 800854a:	68fb      	ldr	r3, [r7, #12]
 800854c:	681b      	ldr	r3, [r3, #0]
 800854e:	4a67      	ldr	r2, [pc, #412]	@ (80086ec <HAL_DMA_Start_IT+0x4c0>)
 8008550:	4293      	cmp	r3, r2
 8008552:	d013      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 8008554:	68fb      	ldr	r3, [r7, #12]
 8008556:	681b      	ldr	r3, [r3, #0]
 8008558:	4a65      	ldr	r2, [pc, #404]	@ (80086f0 <HAL_DMA_Start_IT+0x4c4>)
 800855a:	4293      	cmp	r3, r2
 800855c:	d00e      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 800855e:	68fb      	ldr	r3, [r7, #12]
 8008560:	681b      	ldr	r3, [r3, #0]
 8008562:	4a64      	ldr	r2, [pc, #400]	@ (80086f4 <HAL_DMA_Start_IT+0x4c8>)
 8008564:	4293      	cmp	r3, r2
 8008566:	d009      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 8008568:	68fb      	ldr	r3, [r7, #12]
 800856a:	681b      	ldr	r3, [r3, #0]
 800856c:	4a62      	ldr	r2, [pc, #392]	@ (80086f8 <HAL_DMA_Start_IT+0x4cc>)
 800856e:	4293      	cmp	r3, r2
 8008570:	d004      	beq.n	800857c <HAL_DMA_Start_IT+0x350>
 8008572:	68fb      	ldr	r3, [r7, #12]
 8008574:	681b      	ldr	r3, [r3, #0]
 8008576:	4a61      	ldr	r2, [pc, #388]	@ (80086fc <HAL_DMA_Start_IT+0x4d0>)
 8008578:	4293      	cmp	r3, r2
 800857a:	d101      	bne.n	8008580 <HAL_DMA_Start_IT+0x354>
 800857c:	2301      	movs	r3, #1
 800857e:	e000      	b.n	8008582 <HAL_DMA_Start_IT+0x356>
 8008580:	2300      	movs	r3, #0
 8008582:	2b00      	cmp	r3, #0
 8008584:	d01a      	beq.n	80085bc <HAL_DMA_Start_IT+0x390>
    {
      /* Check if DMAMUX Synchronization is enabled */
      if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
 8008586:	68fb      	ldr	r3, [r7, #12]
 8008588:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 800858a:	681b      	ldr	r3, [r3, #0]
 800858c:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 8008590:	2b00      	cmp	r3, #0
 8008592:	d007      	beq.n	80085a4 <HAL_DMA_Start_IT+0x378>
      {
        /* Enable DMAMUX sync overrun IT*/
        hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
 8008594:	68fb      	ldr	r3, [r7, #12]
 8008596:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8008598:	681a      	ldr	r2, [r3, #0]
 800859a:	68fb      	ldr	r3, [r7, #12]
 800859c:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 800859e:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
 80085a2:	601a      	str	r2, [r3, #0]
      }

      if(hdma->DMAmuxRequestGen != 0U)
 80085a4:	68fb      	ldr	r3, [r7, #12]
 80085a6:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 80085a8:	2b00      	cmp	r3, #0
 80085aa:	d007      	beq.n	80085bc <HAL_DMA_Start_IT+0x390>
      {
        /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
        /* enable the request gen overrun IT */
        hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
 80085ac:	68fb      	ldr	r3, [r7, #12]
 80085ae:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 80085b0:	681a      	ldr	r2, [r3, #0]
 80085b2:	68fb      	ldr	r3, [r7, #12]
 80085b4:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 80085b6:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
 80085ba:	601a      	str	r2, [r3, #0]
      }
    }

    /* Enable the Peripheral */
    __HAL_DMA_ENABLE(hdma);
 80085bc:	68fb      	ldr	r3, [r7, #12]
 80085be:	681b      	ldr	r3, [r3, #0]
 80085c0:	4a37      	ldr	r2, [pc, #220]	@ (80086a0 <HAL_DMA_Start_IT+0x474>)
 80085c2:	4293      	cmp	r3, r2
 80085c4:	d04a      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 80085c6:	68fb      	ldr	r3, [r7, #12]
 80085c8:	681b      	ldr	r3, [r3, #0]
 80085ca:	4a36      	ldr	r2, [pc, #216]	@ (80086a4 <HAL_DMA_Start_IT+0x478>)
 80085cc:	4293      	cmp	r3, r2
 80085ce:	d045      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 80085d0:	68fb      	ldr	r3, [r7, #12]
 80085d2:	681b      	ldr	r3, [r3, #0]
 80085d4:	4a34      	ldr	r2, [pc, #208]	@ (80086a8 <HAL_DMA_Start_IT+0x47c>)
 80085d6:	4293      	cmp	r3, r2
 80085d8:	d040      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 80085da:	68fb      	ldr	r3, [r7, #12]
 80085dc:	681b      	ldr	r3, [r3, #0]
 80085de:	4a33      	ldr	r2, [pc, #204]	@ (80086ac <HAL_DMA_Start_IT+0x480>)
 80085e0:	4293      	cmp	r3, r2
 80085e2:	d03b      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 80085e4:	68fb      	ldr	r3, [r7, #12]
 80085e6:	681b      	ldr	r3, [r3, #0]
 80085e8:	4a31      	ldr	r2, [pc, #196]	@ (80086b0 <HAL_DMA_Start_IT+0x484>)
 80085ea:	4293      	cmp	r3, r2
 80085ec:	d036      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 80085ee:	68fb      	ldr	r3, [r7, #12]
 80085f0:	681b      	ldr	r3, [r3, #0]
 80085f2:	4a30      	ldr	r2, [pc, #192]	@ (80086b4 <HAL_DMA_Start_IT+0x488>)
 80085f4:	4293      	cmp	r3, r2
 80085f6:	d031      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 80085f8:	68fb      	ldr	r3, [r7, #12]
 80085fa:	681b      	ldr	r3, [r3, #0]
 80085fc:	4a2e      	ldr	r2, [pc, #184]	@ (80086b8 <HAL_DMA_Start_IT+0x48c>)
 80085fe:	4293      	cmp	r3, r2
 8008600:	d02c      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 8008602:	68fb      	ldr	r3, [r7, #12]
 8008604:	681b      	ldr	r3, [r3, #0]
 8008606:	4a2d      	ldr	r2, [pc, #180]	@ (80086bc <HAL_DMA_Start_IT+0x490>)
 8008608:	4293      	cmp	r3, r2
 800860a:	d027      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 800860c:	68fb      	ldr	r3, [r7, #12]
 800860e:	681b      	ldr	r3, [r3, #0]
 8008610:	4a2b      	ldr	r2, [pc, #172]	@ (80086c0 <HAL_DMA_Start_IT+0x494>)
 8008612:	4293      	cmp	r3, r2
 8008614:	d022      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 8008616:	68fb      	ldr	r3, [r7, #12]
 8008618:	681b      	ldr	r3, [r3, #0]
 800861a:	4a2a      	ldr	r2, [pc, #168]	@ (80086c4 <HAL_DMA_Start_IT+0x498>)
 800861c:	4293      	cmp	r3, r2
 800861e:	d01d      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 8008620:	68fb      	ldr	r3, [r7, #12]
 8008622:	681b      	ldr	r3, [r3, #0]
 8008624:	4a28      	ldr	r2, [pc, #160]	@ (80086c8 <HAL_DMA_Start_IT+0x49c>)
 8008626:	4293      	cmp	r3, r2
 8008628:	d018      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 800862a:	68fb      	ldr	r3, [r7, #12]
 800862c:	681b      	ldr	r3, [r3, #0]
 800862e:	4a27      	ldr	r2, [pc, #156]	@ (80086cc <HAL_DMA_Start_IT+0x4a0>)
 8008630:	4293      	cmp	r3, r2
 8008632:	d013      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 8008634:	68fb      	ldr	r3, [r7, #12]
 8008636:	681b      	ldr	r3, [r3, #0]
 8008638:	4a25      	ldr	r2, [pc, #148]	@ (80086d0 <HAL_DMA_Start_IT+0x4a4>)
 800863a:	4293      	cmp	r3, r2
 800863c:	d00e      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 800863e:	68fb      	ldr	r3, [r7, #12]
 8008640:	681b      	ldr	r3, [r3, #0]
 8008642:	4a24      	ldr	r2, [pc, #144]	@ (80086d4 <HAL_DMA_Start_IT+0x4a8>)
 8008644:	4293      	cmp	r3, r2
 8008646:	d009      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 8008648:	68fb      	ldr	r3, [r7, #12]
 800864a:	681b      	ldr	r3, [r3, #0]
 800864c:	4a22      	ldr	r2, [pc, #136]	@ (80086d8 <HAL_DMA_Start_IT+0x4ac>)
 800864e:	4293      	cmp	r3, r2
 8008650:	d004      	beq.n	800865c <HAL_DMA_Start_IT+0x430>
 8008652:	68fb      	ldr	r3, [r7, #12]
 8008654:	681b      	ldr	r3, [r3, #0]
 8008656:	4a21      	ldr	r2, [pc, #132]	@ (80086dc <HAL_DMA_Start_IT+0x4b0>)
 8008658:	4293      	cmp	r3, r2
 800865a:	d108      	bne.n	800866e <HAL_DMA_Start_IT+0x442>
 800865c:	68fb      	ldr	r3, [r7, #12]
 800865e:	681b      	ldr	r3, [r3, #0]
 8008660:	681a      	ldr	r2, [r3, #0]
 8008662:	68fb      	ldr	r3, [r7, #12]
 8008664:	681b      	ldr	r3, [r3, #0]
 8008666:	f042 0201 	orr.w	r2, r2, #1
 800866a:	601a      	str	r2, [r3, #0]
 800866c:	e012      	b.n	8008694 <HAL_DMA_Start_IT+0x468>
 800866e:	68fb      	ldr	r3, [r7, #12]
 8008670:	681b      	ldr	r3, [r3, #0]
 8008672:	681a      	ldr	r2, [r3, #0]
 8008674:	68fb      	ldr	r3, [r7, #12]
 8008676:	681b      	ldr	r3, [r3, #0]
 8008678:	f042 0201 	orr.w	r2, r2, #1
 800867c:	601a      	str	r2, [r3, #0]
 800867e:	e009      	b.n	8008694 <HAL_DMA_Start_IT+0x468>
  }
  else
  {
    /* Set the error code to busy */
    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
 8008680:	68fb      	ldr	r3, [r7, #12]
 8008682:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 8008686:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Process unlocked */
    __HAL_UNLOCK(hdma);
 8008688:	68fb      	ldr	r3, [r7, #12]
 800868a:	2200      	movs	r2, #0
 800868c:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

    /* Return error status */
    status = HAL_ERROR;
 8008690:	2301      	movs	r3, #1
 8008692:	75fb      	strb	r3, [r7, #23]
  }

  return status;
 8008694:	7dfb      	ldrb	r3, [r7, #23]
}
 8008696:	4618      	mov	r0, r3
 8008698:	3718      	adds	r7, #24
 800869a:	46bd      	mov	sp, r7
 800869c:	bd80      	pop	{r7, pc}
 800869e:	bf00      	nop
 80086a0:	40020010 	.word	0x40020010
 80086a4:	40020028 	.word	0x40020028
 80086a8:	40020040 	.word	0x40020040
 80086ac:	40020058 	.word	0x40020058
 80086b0:	40020070 	.word	0x40020070
 80086b4:	40020088 	.word	0x40020088
 80086b8:	400200a0 	.word	0x400200a0
 80086bc:	400200b8 	.word	0x400200b8
 80086c0:	40020410 	.word	0x40020410
 80086c4:	40020428 	.word	0x40020428
 80086c8:	40020440 	.word	0x40020440
 80086cc:	40020458 	.word	0x40020458
 80086d0:	40020470 	.word	0x40020470
 80086d4:	40020488 	.word	0x40020488
 80086d8:	400204a0 	.word	0x400204a0
 80086dc:	400204b8 	.word	0x400204b8
 80086e0:	58025408 	.word	0x58025408
 80086e4:	5802541c 	.word	0x5802541c
 80086e8:	58025430 	.word	0x58025430
 80086ec:	58025444 	.word	0x58025444
 80086f0:	58025458 	.word	0x58025458
 80086f4:	5802546c 	.word	0x5802546c
 80086f8:	58025480 	.word	0x58025480
 80086fc:	58025494 	.word	0x58025494

08008700 <HAL_DMA_Abort>:
  *        and the Stream will be effectively disabled only after the transfer of
  *        this single data is finished.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
 8008700:	b580      	push	{r7, lr}
 8008702:	b086      	sub	sp, #24
 8008704:	af00      	add	r7, sp, #0
 8008706:	6078      	str	r0, [r7, #4]
  /* calculate DMA base and stream number */
  DMA_Base_Registers *regs_dma;
  BDMA_Base_Registers *regs_bdma;
  const __IO uint32_t *enableRegister;

  uint32_t tickstart = HAL_GetTick();
 8008708:	f7fc fe98 	bl	800543c <HAL_GetTick>
 800870c:	6138      	str	r0, [r7, #16]

 /* Check the DMA peripheral handle */
  if(hdma == NULL)
 800870e:	687b      	ldr	r3, [r7, #4]
 8008710:	2b00      	cmp	r3, #0
 8008712:	d101      	bne.n	8008718 <HAL_DMA_Abort+0x18>
  {
    return HAL_ERROR;
 8008714:	2301      	movs	r3, #1
 8008716:	e2dc      	b.n	8008cd2 <HAL_DMA_Abort+0x5d2>
  }

  /* Check the DMA peripheral state */
  if(hdma->State != HAL_DMA_STATE_BUSY)
 8008718:	687b      	ldr	r3, [r7, #4]
 800871a:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
 800871e:	b2db      	uxtb	r3, r3
 8008720:	2b02      	cmp	r3, #2
 8008722:	d008      	beq.n	8008736 <HAL_DMA_Abort+0x36>
  {
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 8008724:	687b      	ldr	r3, [r7, #4]
 8008726:	2280      	movs	r2, #128	@ 0x80
 8008728:	655a      	str	r2, [r3, #84]	@ 0x54

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 800872a:	687b      	ldr	r3, [r7, #4]
 800872c:	2200      	movs	r2, #0
 800872e:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

    return HAL_ERROR;
 8008732:	2301      	movs	r3, #1
 8008734:	e2cd      	b.n	8008cd2 <HAL_DMA_Abort+0x5d2>
  }
  else
  {
    /* Disable all the transfer interrupts */
    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 8008736:	687b      	ldr	r3, [r7, #4]
 8008738:	681b      	ldr	r3, [r3, #0]
 800873a:	4a76      	ldr	r2, [pc, #472]	@ (8008914 <HAL_DMA_Abort+0x214>)
 800873c:	4293      	cmp	r3, r2
 800873e:	d04a      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 8008740:	687b      	ldr	r3, [r7, #4]
 8008742:	681b      	ldr	r3, [r3, #0]
 8008744:	4a74      	ldr	r2, [pc, #464]	@ (8008918 <HAL_DMA_Abort+0x218>)
 8008746:	4293      	cmp	r3, r2
 8008748:	d045      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 800874a:	687b      	ldr	r3, [r7, #4]
 800874c:	681b      	ldr	r3, [r3, #0]
 800874e:	4a73      	ldr	r2, [pc, #460]	@ (800891c <HAL_DMA_Abort+0x21c>)
 8008750:	4293      	cmp	r3, r2
 8008752:	d040      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 8008754:	687b      	ldr	r3, [r7, #4]
 8008756:	681b      	ldr	r3, [r3, #0]
 8008758:	4a71      	ldr	r2, [pc, #452]	@ (8008920 <HAL_DMA_Abort+0x220>)
 800875a:	4293      	cmp	r3, r2
 800875c:	d03b      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 800875e:	687b      	ldr	r3, [r7, #4]
 8008760:	681b      	ldr	r3, [r3, #0]
 8008762:	4a70      	ldr	r2, [pc, #448]	@ (8008924 <HAL_DMA_Abort+0x224>)
 8008764:	4293      	cmp	r3, r2
 8008766:	d036      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 8008768:	687b      	ldr	r3, [r7, #4]
 800876a:	681b      	ldr	r3, [r3, #0]
 800876c:	4a6e      	ldr	r2, [pc, #440]	@ (8008928 <HAL_DMA_Abort+0x228>)
 800876e:	4293      	cmp	r3, r2
 8008770:	d031      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 8008772:	687b      	ldr	r3, [r7, #4]
 8008774:	681b      	ldr	r3, [r3, #0]
 8008776:	4a6d      	ldr	r2, [pc, #436]	@ (800892c <HAL_DMA_Abort+0x22c>)
 8008778:	4293      	cmp	r3, r2
 800877a:	d02c      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 800877c:	687b      	ldr	r3, [r7, #4]
 800877e:	681b      	ldr	r3, [r3, #0]
 8008780:	4a6b      	ldr	r2, [pc, #428]	@ (8008930 <HAL_DMA_Abort+0x230>)
 8008782:	4293      	cmp	r3, r2
 8008784:	d027      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 8008786:	687b      	ldr	r3, [r7, #4]
 8008788:	681b      	ldr	r3, [r3, #0]
 800878a:	4a6a      	ldr	r2, [pc, #424]	@ (8008934 <HAL_DMA_Abort+0x234>)
 800878c:	4293      	cmp	r3, r2
 800878e:	d022      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 8008790:	687b      	ldr	r3, [r7, #4]
 8008792:	681b      	ldr	r3, [r3, #0]
 8008794:	4a68      	ldr	r2, [pc, #416]	@ (8008938 <HAL_DMA_Abort+0x238>)
 8008796:	4293      	cmp	r3, r2
 8008798:	d01d      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 800879a:	687b      	ldr	r3, [r7, #4]
 800879c:	681b      	ldr	r3, [r3, #0]
 800879e:	4a67      	ldr	r2, [pc, #412]	@ (800893c <HAL_DMA_Abort+0x23c>)
 80087a0:	4293      	cmp	r3, r2
 80087a2:	d018      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 80087a4:	687b      	ldr	r3, [r7, #4]
 80087a6:	681b      	ldr	r3, [r3, #0]
 80087a8:	4a65      	ldr	r2, [pc, #404]	@ (8008940 <HAL_DMA_Abort+0x240>)
 80087aa:	4293      	cmp	r3, r2
 80087ac:	d013      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 80087ae:	687b      	ldr	r3, [r7, #4]
 80087b0:	681b      	ldr	r3, [r3, #0]
 80087b2:	4a64      	ldr	r2, [pc, #400]	@ (8008944 <HAL_DMA_Abort+0x244>)
 80087b4:	4293      	cmp	r3, r2
 80087b6:	d00e      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 80087b8:	687b      	ldr	r3, [r7, #4]
 80087ba:	681b      	ldr	r3, [r3, #0]
 80087bc:	4a62      	ldr	r2, [pc, #392]	@ (8008948 <HAL_DMA_Abort+0x248>)
 80087be:	4293      	cmp	r3, r2
 80087c0:	d009      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 80087c2:	687b      	ldr	r3, [r7, #4]
 80087c4:	681b      	ldr	r3, [r3, #0]
 80087c6:	4a61      	ldr	r2, [pc, #388]	@ (800894c <HAL_DMA_Abort+0x24c>)
 80087c8:	4293      	cmp	r3, r2
 80087ca:	d004      	beq.n	80087d6 <HAL_DMA_Abort+0xd6>
 80087cc:	687b      	ldr	r3, [r7, #4]
 80087ce:	681b      	ldr	r3, [r3, #0]
 80087d0:	4a5f      	ldr	r2, [pc, #380]	@ (8008950 <HAL_DMA_Abort+0x250>)
 80087d2:	4293      	cmp	r3, r2
 80087d4:	d101      	bne.n	80087da <HAL_DMA_Abort+0xda>
 80087d6:	2301      	movs	r3, #1
 80087d8:	e000      	b.n	80087dc <HAL_DMA_Abort+0xdc>
 80087da:	2300      	movs	r3, #0
 80087dc:	2b00      	cmp	r3, #0
 80087de:	d013      	beq.n	8008808 <HAL_DMA_Abort+0x108>
    {
       /* Disable DMA All Interrupts  */
      ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
 80087e0:	687b      	ldr	r3, [r7, #4]
 80087e2:	681b      	ldr	r3, [r3, #0]
 80087e4:	681a      	ldr	r2, [r3, #0]
 80087e6:	687b      	ldr	r3, [r7, #4]
 80087e8:	681b      	ldr	r3, [r3, #0]
 80087ea:	f022 021e 	bic.w	r2, r2, #30
 80087ee:	601a      	str	r2, [r3, #0]
      ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
 80087f0:	687b      	ldr	r3, [r7, #4]
 80087f2:	681b      	ldr	r3, [r3, #0]
 80087f4:	695a      	ldr	r2, [r3, #20]
 80087f6:	687b      	ldr	r3, [r7, #4]
 80087f8:	681b      	ldr	r3, [r3, #0]
 80087fa:	f022 0280 	bic.w	r2, r2, #128	@ 0x80
 80087fe:	615a      	str	r2, [r3, #20]

      enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef   *)hdma->Instance)->CR));
 8008800:	687b      	ldr	r3, [r7, #4]
 8008802:	681b      	ldr	r3, [r3, #0]
 8008804:	617b      	str	r3, [r7, #20]
 8008806:	e00a      	b.n	800881e <HAL_DMA_Abort+0x11e>
    }
    else /* BDMA channel */
    {
      /* Disable DMA All Interrupts */
      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
 8008808:	687b      	ldr	r3, [r7, #4]
 800880a:	681b      	ldr	r3, [r3, #0]
 800880c:	681a      	ldr	r2, [r3, #0]
 800880e:	687b      	ldr	r3, [r7, #4]
 8008810:	681b      	ldr	r3, [r3, #0]
 8008812:	f022 020e 	bic.w	r2, r2, #14
 8008816:	601a      	str	r2, [r3, #0]

      enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR));
 8008818:	687b      	ldr	r3, [r7, #4]
 800881a:	681b      	ldr	r3, [r3, #0]
 800881c:	617b      	str	r3, [r7, #20]
    }

    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
 800881e:	687b      	ldr	r3, [r7, #4]
 8008820:	681b      	ldr	r3, [r3, #0]
 8008822:	4a3c      	ldr	r2, [pc, #240]	@ (8008914 <HAL_DMA_Abort+0x214>)
 8008824:	4293      	cmp	r3, r2
 8008826:	d072      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 8008828:	687b      	ldr	r3, [r7, #4]
 800882a:	681b      	ldr	r3, [r3, #0]
 800882c:	4a3a      	ldr	r2, [pc, #232]	@ (8008918 <HAL_DMA_Abort+0x218>)
 800882e:	4293      	cmp	r3, r2
 8008830:	d06d      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 8008832:	687b      	ldr	r3, [r7, #4]
 8008834:	681b      	ldr	r3, [r3, #0]
 8008836:	4a39      	ldr	r2, [pc, #228]	@ (800891c <HAL_DMA_Abort+0x21c>)
 8008838:	4293      	cmp	r3, r2
 800883a:	d068      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 800883c:	687b      	ldr	r3, [r7, #4]
 800883e:	681b      	ldr	r3, [r3, #0]
 8008840:	4a37      	ldr	r2, [pc, #220]	@ (8008920 <HAL_DMA_Abort+0x220>)
 8008842:	4293      	cmp	r3, r2
 8008844:	d063      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 8008846:	687b      	ldr	r3, [r7, #4]
 8008848:	681b      	ldr	r3, [r3, #0]
 800884a:	4a36      	ldr	r2, [pc, #216]	@ (8008924 <HAL_DMA_Abort+0x224>)
 800884c:	4293      	cmp	r3, r2
 800884e:	d05e      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 8008850:	687b      	ldr	r3, [r7, #4]
 8008852:	681b      	ldr	r3, [r3, #0]
 8008854:	4a34      	ldr	r2, [pc, #208]	@ (8008928 <HAL_DMA_Abort+0x228>)
 8008856:	4293      	cmp	r3, r2
 8008858:	d059      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 800885a:	687b      	ldr	r3, [r7, #4]
 800885c:	681b      	ldr	r3, [r3, #0]
 800885e:	4a33      	ldr	r2, [pc, #204]	@ (800892c <HAL_DMA_Abort+0x22c>)
 8008860:	4293      	cmp	r3, r2
 8008862:	d054      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 8008864:	687b      	ldr	r3, [r7, #4]
 8008866:	681b      	ldr	r3, [r3, #0]
 8008868:	4a31      	ldr	r2, [pc, #196]	@ (8008930 <HAL_DMA_Abort+0x230>)
 800886a:	4293      	cmp	r3, r2
 800886c:	d04f      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 800886e:	687b      	ldr	r3, [r7, #4]
 8008870:	681b      	ldr	r3, [r3, #0]
 8008872:	4a30      	ldr	r2, [pc, #192]	@ (8008934 <HAL_DMA_Abort+0x234>)
 8008874:	4293      	cmp	r3, r2
 8008876:	d04a      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 8008878:	687b      	ldr	r3, [r7, #4]
 800887a:	681b      	ldr	r3, [r3, #0]
 800887c:	4a2e      	ldr	r2, [pc, #184]	@ (8008938 <HAL_DMA_Abort+0x238>)
 800887e:	4293      	cmp	r3, r2
 8008880:	d045      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 8008882:	687b      	ldr	r3, [r7, #4]
 8008884:	681b      	ldr	r3, [r3, #0]
 8008886:	4a2d      	ldr	r2, [pc, #180]	@ (800893c <HAL_DMA_Abort+0x23c>)
 8008888:	4293      	cmp	r3, r2
 800888a:	d040      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 800888c:	687b      	ldr	r3, [r7, #4]
 800888e:	681b      	ldr	r3, [r3, #0]
 8008890:	4a2b      	ldr	r2, [pc, #172]	@ (8008940 <HAL_DMA_Abort+0x240>)
 8008892:	4293      	cmp	r3, r2
 8008894:	d03b      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 8008896:	687b      	ldr	r3, [r7, #4]
 8008898:	681b      	ldr	r3, [r3, #0]
 800889a:	4a2a      	ldr	r2, [pc, #168]	@ (8008944 <HAL_DMA_Abort+0x244>)
 800889c:	4293      	cmp	r3, r2
 800889e:	d036      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 80088a0:	687b      	ldr	r3, [r7, #4]
 80088a2:	681b      	ldr	r3, [r3, #0]
 80088a4:	4a28      	ldr	r2, [pc, #160]	@ (8008948 <HAL_DMA_Abort+0x248>)
 80088a6:	4293      	cmp	r3, r2
 80088a8:	d031      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 80088aa:	687b      	ldr	r3, [r7, #4]
 80088ac:	681b      	ldr	r3, [r3, #0]
 80088ae:	4a27      	ldr	r2, [pc, #156]	@ (800894c <HAL_DMA_Abort+0x24c>)
 80088b0:	4293      	cmp	r3, r2
 80088b2:	d02c      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 80088b4:	687b      	ldr	r3, [r7, #4]
 80088b6:	681b      	ldr	r3, [r3, #0]
 80088b8:	4a25      	ldr	r2, [pc, #148]	@ (8008950 <HAL_DMA_Abort+0x250>)
 80088ba:	4293      	cmp	r3, r2
 80088bc:	d027      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 80088be:	687b      	ldr	r3, [r7, #4]
 80088c0:	681b      	ldr	r3, [r3, #0]
 80088c2:	4a24      	ldr	r2, [pc, #144]	@ (8008954 <HAL_DMA_Abort+0x254>)
 80088c4:	4293      	cmp	r3, r2
 80088c6:	d022      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 80088c8:	687b      	ldr	r3, [r7, #4]
 80088ca:	681b      	ldr	r3, [r3, #0]
 80088cc:	4a22      	ldr	r2, [pc, #136]	@ (8008958 <HAL_DMA_Abort+0x258>)
 80088ce:	4293      	cmp	r3, r2
 80088d0:	d01d      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 80088d2:	687b      	ldr	r3, [r7, #4]
 80088d4:	681b      	ldr	r3, [r3, #0]
 80088d6:	4a21      	ldr	r2, [pc, #132]	@ (800895c <HAL_DMA_Abort+0x25c>)
 80088d8:	4293      	cmp	r3, r2
 80088da:	d018      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 80088dc:	687b      	ldr	r3, [r7, #4]
 80088de:	681b      	ldr	r3, [r3, #0]
 80088e0:	4a1f      	ldr	r2, [pc, #124]	@ (8008960 <HAL_DMA_Abort+0x260>)
 80088e2:	4293      	cmp	r3, r2
 80088e4:	d013      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 80088e6:	687b      	ldr	r3, [r7, #4]
 80088e8:	681b      	ldr	r3, [r3, #0]
 80088ea:	4a1e      	ldr	r2, [pc, #120]	@ (8008964 <HAL_DMA_Abort+0x264>)
 80088ec:	4293      	cmp	r3, r2
 80088ee:	d00e      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 80088f0:	687b      	ldr	r3, [r7, #4]
 80088f2:	681b      	ldr	r3, [r3, #0]
 80088f4:	4a1c      	ldr	r2, [pc, #112]	@ (8008968 <HAL_DMA_Abort+0x268>)
 80088f6:	4293      	cmp	r3, r2
 80088f8:	d009      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 80088fa:	687b      	ldr	r3, [r7, #4]
 80088fc:	681b      	ldr	r3, [r3, #0]
 80088fe:	4a1b      	ldr	r2, [pc, #108]	@ (800896c <HAL_DMA_Abort+0x26c>)
 8008900:	4293      	cmp	r3, r2
 8008902:	d004      	beq.n	800890e <HAL_DMA_Abort+0x20e>
 8008904:	687b      	ldr	r3, [r7, #4]
 8008906:	681b      	ldr	r3, [r3, #0]
 8008908:	4a19      	ldr	r2, [pc, #100]	@ (8008970 <HAL_DMA_Abort+0x270>)
 800890a:	4293      	cmp	r3, r2
 800890c:	d132      	bne.n	8008974 <HAL_DMA_Abort+0x274>
 800890e:	2301      	movs	r3, #1
 8008910:	e031      	b.n	8008976 <HAL_DMA_Abort+0x276>
 8008912:	bf00      	nop
 8008914:	40020010 	.word	0x40020010
 8008918:	40020028 	.word	0x40020028
 800891c:	40020040 	.word	0x40020040
 8008920:	40020058 	.word	0x40020058
 8008924:	40020070 	.word	0x40020070
 8008928:	40020088 	.word	0x40020088
 800892c:	400200a0 	.word	0x400200a0
 8008930:	400200b8 	.word	0x400200b8
 8008934:	40020410 	.word	0x40020410
 8008938:	40020428 	.word	0x40020428
 800893c:	40020440 	.word	0x40020440
 8008940:	40020458 	.word	0x40020458
 8008944:	40020470 	.word	0x40020470
 8008948:	40020488 	.word	0x40020488
 800894c:	400204a0 	.word	0x400204a0
 8008950:	400204b8 	.word	0x400204b8
 8008954:	58025408 	.word	0x58025408
 8008958:	5802541c 	.word	0x5802541c
 800895c:	58025430 	.word	0x58025430
 8008960:	58025444 	.word	0x58025444
 8008964:	58025458 	.word	0x58025458
 8008968:	5802546c 	.word	0x5802546c
 800896c:	58025480 	.word	0x58025480
 8008970:	58025494 	.word	0x58025494
 8008974:	2300      	movs	r3, #0
 8008976:	2b00      	cmp	r3, #0
 8008978:	d007      	beq.n	800898a <HAL_DMA_Abort+0x28a>
    {
      /* disable the DMAMUX sync overrun IT */
      hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
 800897a:	687b      	ldr	r3, [r7, #4]
 800897c:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 800897e:	681a      	ldr	r2, [r3, #0]
 8008980:	687b      	ldr	r3, [r7, #4]
 8008982:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8008984:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
 8008988:	601a      	str	r2, [r3, #0]
    }

    /* Disable the stream */
    __HAL_DMA_DISABLE(hdma);
 800898a:	687b      	ldr	r3, [r7, #4]
 800898c:	681b      	ldr	r3, [r3, #0]
 800898e:	4a6d      	ldr	r2, [pc, #436]	@ (8008b44 <HAL_DMA_Abort+0x444>)
 8008990:	4293      	cmp	r3, r2
 8008992:	d04a      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 8008994:	687b      	ldr	r3, [r7, #4]
 8008996:	681b      	ldr	r3, [r3, #0]
 8008998:	4a6b      	ldr	r2, [pc, #428]	@ (8008b48 <HAL_DMA_Abort+0x448>)
 800899a:	4293      	cmp	r3, r2
 800899c:	d045      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 800899e:	687b      	ldr	r3, [r7, #4]
 80089a0:	681b      	ldr	r3, [r3, #0]
 80089a2:	4a6a      	ldr	r2, [pc, #424]	@ (8008b4c <HAL_DMA_Abort+0x44c>)
 80089a4:	4293      	cmp	r3, r2
 80089a6:	d040      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 80089a8:	687b      	ldr	r3, [r7, #4]
 80089aa:	681b      	ldr	r3, [r3, #0]
 80089ac:	4a68      	ldr	r2, [pc, #416]	@ (8008b50 <HAL_DMA_Abort+0x450>)
 80089ae:	4293      	cmp	r3, r2
 80089b0:	d03b      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 80089b2:	687b      	ldr	r3, [r7, #4]
 80089b4:	681b      	ldr	r3, [r3, #0]
 80089b6:	4a67      	ldr	r2, [pc, #412]	@ (8008b54 <HAL_DMA_Abort+0x454>)
 80089b8:	4293      	cmp	r3, r2
 80089ba:	d036      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 80089bc:	687b      	ldr	r3, [r7, #4]
 80089be:	681b      	ldr	r3, [r3, #0]
 80089c0:	4a65      	ldr	r2, [pc, #404]	@ (8008b58 <HAL_DMA_Abort+0x458>)
 80089c2:	4293      	cmp	r3, r2
 80089c4:	d031      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 80089c6:	687b      	ldr	r3, [r7, #4]
 80089c8:	681b      	ldr	r3, [r3, #0]
 80089ca:	4a64      	ldr	r2, [pc, #400]	@ (8008b5c <HAL_DMA_Abort+0x45c>)
 80089cc:	4293      	cmp	r3, r2
 80089ce:	d02c      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 80089d0:	687b      	ldr	r3, [r7, #4]
 80089d2:	681b      	ldr	r3, [r3, #0]
 80089d4:	4a62      	ldr	r2, [pc, #392]	@ (8008b60 <HAL_DMA_Abort+0x460>)
 80089d6:	4293      	cmp	r3, r2
 80089d8:	d027      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 80089da:	687b      	ldr	r3, [r7, #4]
 80089dc:	681b      	ldr	r3, [r3, #0]
 80089de:	4a61      	ldr	r2, [pc, #388]	@ (8008b64 <HAL_DMA_Abort+0x464>)
 80089e0:	4293      	cmp	r3, r2
 80089e2:	d022      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 80089e4:	687b      	ldr	r3, [r7, #4]
 80089e6:	681b      	ldr	r3, [r3, #0]
 80089e8:	4a5f      	ldr	r2, [pc, #380]	@ (8008b68 <HAL_DMA_Abort+0x468>)
 80089ea:	4293      	cmp	r3, r2
 80089ec:	d01d      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 80089ee:	687b      	ldr	r3, [r7, #4]
 80089f0:	681b      	ldr	r3, [r3, #0]
 80089f2:	4a5e      	ldr	r2, [pc, #376]	@ (8008b6c <HAL_DMA_Abort+0x46c>)
 80089f4:	4293      	cmp	r3, r2
 80089f6:	d018      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 80089f8:	687b      	ldr	r3, [r7, #4]
 80089fa:	681b      	ldr	r3, [r3, #0]
 80089fc:	4a5c      	ldr	r2, [pc, #368]	@ (8008b70 <HAL_DMA_Abort+0x470>)
 80089fe:	4293      	cmp	r3, r2
 8008a00:	d013      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 8008a02:	687b      	ldr	r3, [r7, #4]
 8008a04:	681b      	ldr	r3, [r3, #0]
 8008a06:	4a5b      	ldr	r2, [pc, #364]	@ (8008b74 <HAL_DMA_Abort+0x474>)
 8008a08:	4293      	cmp	r3, r2
 8008a0a:	d00e      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 8008a0c:	687b      	ldr	r3, [r7, #4]
 8008a0e:	681b      	ldr	r3, [r3, #0]
 8008a10:	4a59      	ldr	r2, [pc, #356]	@ (8008b78 <HAL_DMA_Abort+0x478>)
 8008a12:	4293      	cmp	r3, r2
 8008a14:	d009      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 8008a16:	687b      	ldr	r3, [r7, #4]
 8008a18:	681b      	ldr	r3, [r3, #0]
 8008a1a:	4a58      	ldr	r2, [pc, #352]	@ (8008b7c <HAL_DMA_Abort+0x47c>)
 8008a1c:	4293      	cmp	r3, r2
 8008a1e:	d004      	beq.n	8008a2a <HAL_DMA_Abort+0x32a>
 8008a20:	687b      	ldr	r3, [r7, #4]
 8008a22:	681b      	ldr	r3, [r3, #0]
 8008a24:	4a56      	ldr	r2, [pc, #344]	@ (8008b80 <HAL_DMA_Abort+0x480>)
 8008a26:	4293      	cmp	r3, r2
 8008a28:	d108      	bne.n	8008a3c <HAL_DMA_Abort+0x33c>
 8008a2a:	687b      	ldr	r3, [r7, #4]
 8008a2c:	681b      	ldr	r3, [r3, #0]
 8008a2e:	681a      	ldr	r2, [r3, #0]
 8008a30:	687b      	ldr	r3, [r7, #4]
 8008a32:	681b      	ldr	r3, [r3, #0]
 8008a34:	f022 0201 	bic.w	r2, r2, #1
 8008a38:	601a      	str	r2, [r3, #0]
 8008a3a:	e007      	b.n	8008a4c <HAL_DMA_Abort+0x34c>
 8008a3c:	687b      	ldr	r3, [r7, #4]
 8008a3e:	681b      	ldr	r3, [r3, #0]
 8008a40:	681a      	ldr	r2, [r3, #0]
 8008a42:	687b      	ldr	r3, [r7, #4]
 8008a44:	681b      	ldr	r3, [r3, #0]
 8008a46:	f022 0201 	bic.w	r2, r2, #1
 8008a4a:	601a      	str	r2, [r3, #0]

    /* Check if the DMA Stream is effectively disabled */
    while(((*enableRegister) & DMA_SxCR_EN) != 0U)
 8008a4c:	e013      	b.n	8008a76 <HAL_DMA_Abort+0x376>
    {
      /* Check for the Timeout */
      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
 8008a4e:	f7fc fcf5 	bl	800543c <HAL_GetTick>
 8008a52:	4602      	mov	r2, r0
 8008a54:	693b      	ldr	r3, [r7, #16]
 8008a56:	1ad3      	subs	r3, r2, r3
 8008a58:	2b05      	cmp	r3, #5
 8008a5a:	d90c      	bls.n	8008a76 <HAL_DMA_Abort+0x376>
      {
        /* Update error code */
        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
 8008a5c:	687b      	ldr	r3, [r7, #4]
 8008a5e:	2220      	movs	r2, #32
 8008a60:	655a      	str	r2, [r3, #84]	@ 0x54

        /* Change the DMA state */
        hdma->State = HAL_DMA_STATE_ERROR;
 8008a62:	687b      	ldr	r3, [r7, #4]
 8008a64:	2203      	movs	r2, #3
 8008a66:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

        /* Process Unlocked */
        __HAL_UNLOCK(hdma);
 8008a6a:	687b      	ldr	r3, [r7, #4]
 8008a6c:	2200      	movs	r2, #0
 8008a6e:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

        return HAL_ERROR;
 8008a72:	2301      	movs	r3, #1
 8008a74:	e12d      	b.n	8008cd2 <HAL_DMA_Abort+0x5d2>
    while(((*enableRegister) & DMA_SxCR_EN) != 0U)
 8008a76:	697b      	ldr	r3, [r7, #20]
 8008a78:	681b      	ldr	r3, [r3, #0]
 8008a7a:	f003 0301 	and.w	r3, r3, #1
 8008a7e:	2b00      	cmp	r3, #0
 8008a80:	d1e5      	bne.n	8008a4e <HAL_DMA_Abort+0x34e>
      }
    }

    /* Clear all interrupt flags at correct offset within the register */
    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 8008a82:	687b      	ldr	r3, [r7, #4]
 8008a84:	681b      	ldr	r3, [r3, #0]
 8008a86:	4a2f      	ldr	r2, [pc, #188]	@ (8008b44 <HAL_DMA_Abort+0x444>)
 8008a88:	4293      	cmp	r3, r2
 8008a8a:	d04a      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008a8c:	687b      	ldr	r3, [r7, #4]
 8008a8e:	681b      	ldr	r3, [r3, #0]
 8008a90:	4a2d      	ldr	r2, [pc, #180]	@ (8008b48 <HAL_DMA_Abort+0x448>)
 8008a92:	4293      	cmp	r3, r2
 8008a94:	d045      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008a96:	687b      	ldr	r3, [r7, #4]
 8008a98:	681b      	ldr	r3, [r3, #0]
 8008a9a:	4a2c      	ldr	r2, [pc, #176]	@ (8008b4c <HAL_DMA_Abort+0x44c>)
 8008a9c:	4293      	cmp	r3, r2
 8008a9e:	d040      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008aa0:	687b      	ldr	r3, [r7, #4]
 8008aa2:	681b      	ldr	r3, [r3, #0]
 8008aa4:	4a2a      	ldr	r2, [pc, #168]	@ (8008b50 <HAL_DMA_Abort+0x450>)
 8008aa6:	4293      	cmp	r3, r2
 8008aa8:	d03b      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008aaa:	687b      	ldr	r3, [r7, #4]
 8008aac:	681b      	ldr	r3, [r3, #0]
 8008aae:	4a29      	ldr	r2, [pc, #164]	@ (8008b54 <HAL_DMA_Abort+0x454>)
 8008ab0:	4293      	cmp	r3, r2
 8008ab2:	d036      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008ab4:	687b      	ldr	r3, [r7, #4]
 8008ab6:	681b      	ldr	r3, [r3, #0]
 8008ab8:	4a27      	ldr	r2, [pc, #156]	@ (8008b58 <HAL_DMA_Abort+0x458>)
 8008aba:	4293      	cmp	r3, r2
 8008abc:	d031      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008abe:	687b      	ldr	r3, [r7, #4]
 8008ac0:	681b      	ldr	r3, [r3, #0]
 8008ac2:	4a26      	ldr	r2, [pc, #152]	@ (8008b5c <HAL_DMA_Abort+0x45c>)
 8008ac4:	4293      	cmp	r3, r2
 8008ac6:	d02c      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008ac8:	687b      	ldr	r3, [r7, #4]
 8008aca:	681b      	ldr	r3, [r3, #0]
 8008acc:	4a24      	ldr	r2, [pc, #144]	@ (8008b60 <HAL_DMA_Abort+0x460>)
 8008ace:	4293      	cmp	r3, r2
 8008ad0:	d027      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008ad2:	687b      	ldr	r3, [r7, #4]
 8008ad4:	681b      	ldr	r3, [r3, #0]
 8008ad6:	4a23      	ldr	r2, [pc, #140]	@ (8008b64 <HAL_DMA_Abort+0x464>)
 8008ad8:	4293      	cmp	r3, r2
 8008ada:	d022      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008adc:	687b      	ldr	r3, [r7, #4]
 8008ade:	681b      	ldr	r3, [r3, #0]
 8008ae0:	4a21      	ldr	r2, [pc, #132]	@ (8008b68 <HAL_DMA_Abort+0x468>)
 8008ae2:	4293      	cmp	r3, r2
 8008ae4:	d01d      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008ae6:	687b      	ldr	r3, [r7, #4]
 8008ae8:	681b      	ldr	r3, [r3, #0]
 8008aea:	4a20      	ldr	r2, [pc, #128]	@ (8008b6c <HAL_DMA_Abort+0x46c>)
 8008aec:	4293      	cmp	r3, r2
 8008aee:	d018      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008af0:	687b      	ldr	r3, [r7, #4]
 8008af2:	681b      	ldr	r3, [r3, #0]
 8008af4:	4a1e      	ldr	r2, [pc, #120]	@ (8008b70 <HAL_DMA_Abort+0x470>)
 8008af6:	4293      	cmp	r3, r2
 8008af8:	d013      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008afa:	687b      	ldr	r3, [r7, #4]
 8008afc:	681b      	ldr	r3, [r3, #0]
 8008afe:	4a1d      	ldr	r2, [pc, #116]	@ (8008b74 <HAL_DMA_Abort+0x474>)
 8008b00:	4293      	cmp	r3, r2
 8008b02:	d00e      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008b04:	687b      	ldr	r3, [r7, #4]
 8008b06:	681b      	ldr	r3, [r3, #0]
 8008b08:	4a1b      	ldr	r2, [pc, #108]	@ (8008b78 <HAL_DMA_Abort+0x478>)
 8008b0a:	4293      	cmp	r3, r2
 8008b0c:	d009      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008b0e:	687b      	ldr	r3, [r7, #4]
 8008b10:	681b      	ldr	r3, [r3, #0]
 8008b12:	4a1a      	ldr	r2, [pc, #104]	@ (8008b7c <HAL_DMA_Abort+0x47c>)
 8008b14:	4293      	cmp	r3, r2
 8008b16:	d004      	beq.n	8008b22 <HAL_DMA_Abort+0x422>
 8008b18:	687b      	ldr	r3, [r7, #4]
 8008b1a:	681b      	ldr	r3, [r3, #0]
 8008b1c:	4a18      	ldr	r2, [pc, #96]	@ (8008b80 <HAL_DMA_Abort+0x480>)
 8008b1e:	4293      	cmp	r3, r2
 8008b20:	d101      	bne.n	8008b26 <HAL_DMA_Abort+0x426>
 8008b22:	2301      	movs	r3, #1
 8008b24:	e000      	b.n	8008b28 <HAL_DMA_Abort+0x428>
 8008b26:	2300      	movs	r3, #0
 8008b28:	2b00      	cmp	r3, #0
 8008b2a:	d02b      	beq.n	8008b84 <HAL_DMA_Abort+0x484>
    {
      regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
 8008b2c:	687b      	ldr	r3, [r7, #4]
 8008b2e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8008b30:	60bb      	str	r3, [r7, #8]
      regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
 8008b32:	687b      	ldr	r3, [r7, #4]
 8008b34:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8008b36:	f003 031f 	and.w	r3, r3, #31
 8008b3a:	223f      	movs	r2, #63	@ 0x3f
 8008b3c:	409a      	lsls	r2, r3
 8008b3e:	68bb      	ldr	r3, [r7, #8]
 8008b40:	609a      	str	r2, [r3, #8]
 8008b42:	e02a      	b.n	8008b9a <HAL_DMA_Abort+0x49a>
 8008b44:	40020010 	.word	0x40020010
 8008b48:	40020028 	.word	0x40020028
 8008b4c:	40020040 	.word	0x40020040
 8008b50:	40020058 	.word	0x40020058
 8008b54:	40020070 	.word	0x40020070
 8008b58:	40020088 	.word	0x40020088
 8008b5c:	400200a0 	.word	0x400200a0
 8008b60:	400200b8 	.word	0x400200b8
 8008b64:	40020410 	.word	0x40020410
 8008b68:	40020428 	.word	0x40020428
 8008b6c:	40020440 	.word	0x40020440
 8008b70:	40020458 	.word	0x40020458
 8008b74:	40020470 	.word	0x40020470
 8008b78:	40020488 	.word	0x40020488
 8008b7c:	400204a0 	.word	0x400204a0
 8008b80:	400204b8 	.word	0x400204b8
    }
    else /* BDMA channel */
    {
      regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
 8008b84:	687b      	ldr	r3, [r7, #4]
 8008b86:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8008b88:	60fb      	str	r3, [r7, #12]
      regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
 8008b8a:	687b      	ldr	r3, [r7, #4]
 8008b8c:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8008b8e:	f003 031f 	and.w	r3, r3, #31
 8008b92:	2201      	movs	r2, #1
 8008b94:	409a      	lsls	r2, r3
 8008b96:	68fb      	ldr	r3, [r7, #12]
 8008b98:	605a      	str	r2, [r3, #4]
    }

    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
 8008b9a:	687b      	ldr	r3, [r7, #4]
 8008b9c:	681b      	ldr	r3, [r3, #0]
 8008b9e:	4a4f      	ldr	r2, [pc, #316]	@ (8008cdc <HAL_DMA_Abort+0x5dc>)
 8008ba0:	4293      	cmp	r3, r2
 8008ba2:	d072      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008ba4:	687b      	ldr	r3, [r7, #4]
 8008ba6:	681b      	ldr	r3, [r3, #0]
 8008ba8:	4a4d      	ldr	r2, [pc, #308]	@ (8008ce0 <HAL_DMA_Abort+0x5e0>)
 8008baa:	4293      	cmp	r3, r2
 8008bac:	d06d      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008bae:	687b      	ldr	r3, [r7, #4]
 8008bb0:	681b      	ldr	r3, [r3, #0]
 8008bb2:	4a4c      	ldr	r2, [pc, #304]	@ (8008ce4 <HAL_DMA_Abort+0x5e4>)
 8008bb4:	4293      	cmp	r3, r2
 8008bb6:	d068      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008bb8:	687b      	ldr	r3, [r7, #4]
 8008bba:	681b      	ldr	r3, [r3, #0]
 8008bbc:	4a4a      	ldr	r2, [pc, #296]	@ (8008ce8 <HAL_DMA_Abort+0x5e8>)
 8008bbe:	4293      	cmp	r3, r2
 8008bc0:	d063      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008bc2:	687b      	ldr	r3, [r7, #4]
 8008bc4:	681b      	ldr	r3, [r3, #0]
 8008bc6:	4a49      	ldr	r2, [pc, #292]	@ (8008cec <HAL_DMA_Abort+0x5ec>)
 8008bc8:	4293      	cmp	r3, r2
 8008bca:	d05e      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008bcc:	687b      	ldr	r3, [r7, #4]
 8008bce:	681b      	ldr	r3, [r3, #0]
 8008bd0:	4a47      	ldr	r2, [pc, #284]	@ (8008cf0 <HAL_DMA_Abort+0x5f0>)
 8008bd2:	4293      	cmp	r3, r2
 8008bd4:	d059      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008bd6:	687b      	ldr	r3, [r7, #4]
 8008bd8:	681b      	ldr	r3, [r3, #0]
 8008bda:	4a46      	ldr	r2, [pc, #280]	@ (8008cf4 <HAL_DMA_Abort+0x5f4>)
 8008bdc:	4293      	cmp	r3, r2
 8008bde:	d054      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008be0:	687b      	ldr	r3, [r7, #4]
 8008be2:	681b      	ldr	r3, [r3, #0]
 8008be4:	4a44      	ldr	r2, [pc, #272]	@ (8008cf8 <HAL_DMA_Abort+0x5f8>)
 8008be6:	4293      	cmp	r3, r2
 8008be8:	d04f      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008bea:	687b      	ldr	r3, [r7, #4]
 8008bec:	681b      	ldr	r3, [r3, #0]
 8008bee:	4a43      	ldr	r2, [pc, #268]	@ (8008cfc <HAL_DMA_Abort+0x5fc>)
 8008bf0:	4293      	cmp	r3, r2
 8008bf2:	d04a      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008bf4:	687b      	ldr	r3, [r7, #4]
 8008bf6:	681b      	ldr	r3, [r3, #0]
 8008bf8:	4a41      	ldr	r2, [pc, #260]	@ (8008d00 <HAL_DMA_Abort+0x600>)
 8008bfa:	4293      	cmp	r3, r2
 8008bfc:	d045      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008bfe:	687b      	ldr	r3, [r7, #4]
 8008c00:	681b      	ldr	r3, [r3, #0]
 8008c02:	4a40      	ldr	r2, [pc, #256]	@ (8008d04 <HAL_DMA_Abort+0x604>)
 8008c04:	4293      	cmp	r3, r2
 8008c06:	d040      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c08:	687b      	ldr	r3, [r7, #4]
 8008c0a:	681b      	ldr	r3, [r3, #0]
 8008c0c:	4a3e      	ldr	r2, [pc, #248]	@ (8008d08 <HAL_DMA_Abort+0x608>)
 8008c0e:	4293      	cmp	r3, r2
 8008c10:	d03b      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c12:	687b      	ldr	r3, [r7, #4]
 8008c14:	681b      	ldr	r3, [r3, #0]
 8008c16:	4a3d      	ldr	r2, [pc, #244]	@ (8008d0c <HAL_DMA_Abort+0x60c>)
 8008c18:	4293      	cmp	r3, r2
 8008c1a:	d036      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c1c:	687b      	ldr	r3, [r7, #4]
 8008c1e:	681b      	ldr	r3, [r3, #0]
 8008c20:	4a3b      	ldr	r2, [pc, #236]	@ (8008d10 <HAL_DMA_Abort+0x610>)
 8008c22:	4293      	cmp	r3, r2
 8008c24:	d031      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c26:	687b      	ldr	r3, [r7, #4]
 8008c28:	681b      	ldr	r3, [r3, #0]
 8008c2a:	4a3a      	ldr	r2, [pc, #232]	@ (8008d14 <HAL_DMA_Abort+0x614>)
 8008c2c:	4293      	cmp	r3, r2
 8008c2e:	d02c      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c30:	687b      	ldr	r3, [r7, #4]
 8008c32:	681b      	ldr	r3, [r3, #0]
 8008c34:	4a38      	ldr	r2, [pc, #224]	@ (8008d18 <HAL_DMA_Abort+0x618>)
 8008c36:	4293      	cmp	r3, r2
 8008c38:	d027      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c3a:	687b      	ldr	r3, [r7, #4]
 8008c3c:	681b      	ldr	r3, [r3, #0]
 8008c3e:	4a37      	ldr	r2, [pc, #220]	@ (8008d1c <HAL_DMA_Abort+0x61c>)
 8008c40:	4293      	cmp	r3, r2
 8008c42:	d022      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c44:	687b      	ldr	r3, [r7, #4]
 8008c46:	681b      	ldr	r3, [r3, #0]
 8008c48:	4a35      	ldr	r2, [pc, #212]	@ (8008d20 <HAL_DMA_Abort+0x620>)
 8008c4a:	4293      	cmp	r3, r2
 8008c4c:	d01d      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c4e:	687b      	ldr	r3, [r7, #4]
 8008c50:	681b      	ldr	r3, [r3, #0]
 8008c52:	4a34      	ldr	r2, [pc, #208]	@ (8008d24 <HAL_DMA_Abort+0x624>)
 8008c54:	4293      	cmp	r3, r2
 8008c56:	d018      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c58:	687b      	ldr	r3, [r7, #4]
 8008c5a:	681b      	ldr	r3, [r3, #0]
 8008c5c:	4a32      	ldr	r2, [pc, #200]	@ (8008d28 <HAL_DMA_Abort+0x628>)
 8008c5e:	4293      	cmp	r3, r2
 8008c60:	d013      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c62:	687b      	ldr	r3, [r7, #4]
 8008c64:	681b      	ldr	r3, [r3, #0]
 8008c66:	4a31      	ldr	r2, [pc, #196]	@ (8008d2c <HAL_DMA_Abort+0x62c>)
 8008c68:	4293      	cmp	r3, r2
 8008c6a:	d00e      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c6c:	687b      	ldr	r3, [r7, #4]
 8008c6e:	681b      	ldr	r3, [r3, #0]
 8008c70:	4a2f      	ldr	r2, [pc, #188]	@ (8008d30 <HAL_DMA_Abort+0x630>)
 8008c72:	4293      	cmp	r3, r2
 8008c74:	d009      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c76:	687b      	ldr	r3, [r7, #4]
 8008c78:	681b      	ldr	r3, [r3, #0]
 8008c7a:	4a2e      	ldr	r2, [pc, #184]	@ (8008d34 <HAL_DMA_Abort+0x634>)
 8008c7c:	4293      	cmp	r3, r2
 8008c7e:	d004      	beq.n	8008c8a <HAL_DMA_Abort+0x58a>
 8008c80:	687b      	ldr	r3, [r7, #4]
 8008c82:	681b      	ldr	r3, [r3, #0]
 8008c84:	4a2c      	ldr	r2, [pc, #176]	@ (8008d38 <HAL_DMA_Abort+0x638>)
 8008c86:	4293      	cmp	r3, r2
 8008c88:	d101      	bne.n	8008c8e <HAL_DMA_Abort+0x58e>
 8008c8a:	2301      	movs	r3, #1
 8008c8c:	e000      	b.n	8008c90 <HAL_DMA_Abort+0x590>
 8008c8e:	2300      	movs	r3, #0
 8008c90:	2b00      	cmp	r3, #0
 8008c92:	d015      	beq.n	8008cc0 <HAL_DMA_Abort+0x5c0>
    {
      /* Clear the DMAMUX synchro overrun flag */
      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 8008c94:	687b      	ldr	r3, [r7, #4]
 8008c96:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8008c98:	687a      	ldr	r2, [r7, #4]
 8008c9a:	6e92      	ldr	r2, [r2, #104]	@ 0x68
 8008c9c:	605a      	str	r2, [r3, #4]

      if(hdma->DMAmuxRequestGen != 0U)
 8008c9e:	687b      	ldr	r3, [r7, #4]
 8008ca0:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8008ca2:	2b00      	cmp	r3, #0
 8008ca4:	d00c      	beq.n	8008cc0 <HAL_DMA_Abort+0x5c0>
      {
        /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */
        /* disable the request gen overrun IT */
        hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
 8008ca6:	687b      	ldr	r3, [r7, #4]
 8008ca8:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8008caa:	681a      	ldr	r2, [r3, #0]
 8008cac:	687b      	ldr	r3, [r7, #4]
 8008cae:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8008cb0:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
 8008cb4:	601a      	str	r2, [r3, #0]

        /* Clear the DMAMUX request generator overrun flag */
        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 8008cb6:	687b      	ldr	r3, [r7, #4]
 8008cb8:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8008cba:	687a      	ldr	r2, [r7, #4]
 8008cbc:	6f52      	ldr	r2, [r2, #116]	@ 0x74
 8008cbe:	605a      	str	r2, [r3, #4]
      }
    }

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;
 8008cc0:	687b      	ldr	r3, [r7, #4]
 8008cc2:	2201      	movs	r2, #1
 8008cc4:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8008cc8:	687b      	ldr	r3, [r7, #4]
 8008cca:	2200      	movs	r2, #0
 8008ccc:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
  }

  return HAL_OK;
 8008cd0:	2300      	movs	r3, #0
}
 8008cd2:	4618      	mov	r0, r3
 8008cd4:	3718      	adds	r7, #24
 8008cd6:	46bd      	mov	sp, r7
 8008cd8:	bd80      	pop	{r7, pc}
 8008cda:	bf00      	nop
 8008cdc:	40020010 	.word	0x40020010
 8008ce0:	40020028 	.word	0x40020028
 8008ce4:	40020040 	.word	0x40020040
 8008ce8:	40020058 	.word	0x40020058
 8008cec:	40020070 	.word	0x40020070
 8008cf0:	40020088 	.word	0x40020088
 8008cf4:	400200a0 	.word	0x400200a0
 8008cf8:	400200b8 	.word	0x400200b8
 8008cfc:	40020410 	.word	0x40020410
 8008d00:	40020428 	.word	0x40020428
 8008d04:	40020440 	.word	0x40020440
 8008d08:	40020458 	.word	0x40020458
 8008d0c:	40020470 	.word	0x40020470
 8008d10:	40020488 	.word	0x40020488
 8008d14:	400204a0 	.word	0x400204a0
 8008d18:	400204b8 	.word	0x400204b8
 8008d1c:	58025408 	.word	0x58025408
 8008d20:	5802541c 	.word	0x5802541c
 8008d24:	58025430 	.word	0x58025430
 8008d28:	58025444 	.word	0x58025444
 8008d2c:	58025458 	.word	0x58025458
 8008d30:	5802546c 	.word	0x5802546c
 8008d34:	58025480 	.word	0x58025480
 8008d38:	58025494 	.word	0x58025494

08008d3c <HAL_DMA_Abort_IT>:
  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
  *                 the configuration information for the specified DMA Stream.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
 8008d3c:	b580      	push	{r7, lr}
 8008d3e:	b084      	sub	sp, #16
 8008d40:	af00      	add	r7, sp, #0
 8008d42:	6078      	str	r0, [r7, #4]
  BDMA_Base_Registers *regs_bdma;

  /* Check the DMA peripheral handle */
  if(hdma == NULL)
 8008d44:	687b      	ldr	r3, [r7, #4]
 8008d46:	2b00      	cmp	r3, #0
 8008d48:	d101      	bne.n	8008d4e <HAL_DMA_Abort_IT+0x12>
  {
    return HAL_ERROR;
 8008d4a:	2301      	movs	r3, #1
 8008d4c:	e237      	b.n	80091be <HAL_DMA_Abort_IT+0x482>
  }

  if(hdma->State != HAL_DMA_STATE_BUSY)
 8008d4e:	687b      	ldr	r3, [r7, #4]
 8008d50:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
 8008d54:	b2db      	uxtb	r3, r3
 8008d56:	2b02      	cmp	r3, #2
 8008d58:	d004      	beq.n	8008d64 <HAL_DMA_Abort_IT+0x28>
  {
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 8008d5a:	687b      	ldr	r3, [r7, #4]
 8008d5c:	2280      	movs	r2, #128	@ 0x80
 8008d5e:	655a      	str	r2, [r3, #84]	@ 0x54
    return HAL_ERROR;
 8008d60:	2301      	movs	r3, #1
 8008d62:	e22c      	b.n	80091be <HAL_DMA_Abort_IT+0x482>
  }
  else
  {
    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 8008d64:	687b      	ldr	r3, [r7, #4]
 8008d66:	681b      	ldr	r3, [r3, #0]
 8008d68:	4a5c      	ldr	r2, [pc, #368]	@ (8008edc <HAL_DMA_Abort_IT+0x1a0>)
 8008d6a:	4293      	cmp	r3, r2
 8008d6c:	d04a      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008d6e:	687b      	ldr	r3, [r7, #4]
 8008d70:	681b      	ldr	r3, [r3, #0]
 8008d72:	4a5b      	ldr	r2, [pc, #364]	@ (8008ee0 <HAL_DMA_Abort_IT+0x1a4>)
 8008d74:	4293      	cmp	r3, r2
 8008d76:	d045      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008d78:	687b      	ldr	r3, [r7, #4]
 8008d7a:	681b      	ldr	r3, [r3, #0]
 8008d7c:	4a59      	ldr	r2, [pc, #356]	@ (8008ee4 <HAL_DMA_Abort_IT+0x1a8>)
 8008d7e:	4293      	cmp	r3, r2
 8008d80:	d040      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008d82:	687b      	ldr	r3, [r7, #4]
 8008d84:	681b      	ldr	r3, [r3, #0]
 8008d86:	4a58      	ldr	r2, [pc, #352]	@ (8008ee8 <HAL_DMA_Abort_IT+0x1ac>)
 8008d88:	4293      	cmp	r3, r2
 8008d8a:	d03b      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008d8c:	687b      	ldr	r3, [r7, #4]
 8008d8e:	681b      	ldr	r3, [r3, #0]
 8008d90:	4a56      	ldr	r2, [pc, #344]	@ (8008eec <HAL_DMA_Abort_IT+0x1b0>)
 8008d92:	4293      	cmp	r3, r2
 8008d94:	d036      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008d96:	687b      	ldr	r3, [r7, #4]
 8008d98:	681b      	ldr	r3, [r3, #0]
 8008d9a:	4a55      	ldr	r2, [pc, #340]	@ (8008ef0 <HAL_DMA_Abort_IT+0x1b4>)
 8008d9c:	4293      	cmp	r3, r2
 8008d9e:	d031      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008da0:	687b      	ldr	r3, [r7, #4]
 8008da2:	681b      	ldr	r3, [r3, #0]
 8008da4:	4a53      	ldr	r2, [pc, #332]	@ (8008ef4 <HAL_DMA_Abort_IT+0x1b8>)
 8008da6:	4293      	cmp	r3, r2
 8008da8:	d02c      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008daa:	687b      	ldr	r3, [r7, #4]
 8008dac:	681b      	ldr	r3, [r3, #0]
 8008dae:	4a52      	ldr	r2, [pc, #328]	@ (8008ef8 <HAL_DMA_Abort_IT+0x1bc>)
 8008db0:	4293      	cmp	r3, r2
 8008db2:	d027      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008db4:	687b      	ldr	r3, [r7, #4]
 8008db6:	681b      	ldr	r3, [r3, #0]
 8008db8:	4a50      	ldr	r2, [pc, #320]	@ (8008efc <HAL_DMA_Abort_IT+0x1c0>)
 8008dba:	4293      	cmp	r3, r2
 8008dbc:	d022      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008dbe:	687b      	ldr	r3, [r7, #4]
 8008dc0:	681b      	ldr	r3, [r3, #0]
 8008dc2:	4a4f      	ldr	r2, [pc, #316]	@ (8008f00 <HAL_DMA_Abort_IT+0x1c4>)
 8008dc4:	4293      	cmp	r3, r2
 8008dc6:	d01d      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008dc8:	687b      	ldr	r3, [r7, #4]
 8008dca:	681b      	ldr	r3, [r3, #0]
 8008dcc:	4a4d      	ldr	r2, [pc, #308]	@ (8008f04 <HAL_DMA_Abort_IT+0x1c8>)
 8008dce:	4293      	cmp	r3, r2
 8008dd0:	d018      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008dd2:	687b      	ldr	r3, [r7, #4]
 8008dd4:	681b      	ldr	r3, [r3, #0]
 8008dd6:	4a4c      	ldr	r2, [pc, #304]	@ (8008f08 <HAL_DMA_Abort_IT+0x1cc>)
 8008dd8:	4293      	cmp	r3, r2
 8008dda:	d013      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008ddc:	687b      	ldr	r3, [r7, #4]
 8008dde:	681b      	ldr	r3, [r3, #0]
 8008de0:	4a4a      	ldr	r2, [pc, #296]	@ (8008f0c <HAL_DMA_Abort_IT+0x1d0>)
 8008de2:	4293      	cmp	r3, r2
 8008de4:	d00e      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008de6:	687b      	ldr	r3, [r7, #4]
 8008de8:	681b      	ldr	r3, [r3, #0]
 8008dea:	4a49      	ldr	r2, [pc, #292]	@ (8008f10 <HAL_DMA_Abort_IT+0x1d4>)
 8008dec:	4293      	cmp	r3, r2
 8008dee:	d009      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008df0:	687b      	ldr	r3, [r7, #4]
 8008df2:	681b      	ldr	r3, [r3, #0]
 8008df4:	4a47      	ldr	r2, [pc, #284]	@ (8008f14 <HAL_DMA_Abort_IT+0x1d8>)
 8008df6:	4293      	cmp	r3, r2
 8008df8:	d004      	beq.n	8008e04 <HAL_DMA_Abort_IT+0xc8>
 8008dfa:	687b      	ldr	r3, [r7, #4]
 8008dfc:	681b      	ldr	r3, [r3, #0]
 8008dfe:	4a46      	ldr	r2, [pc, #280]	@ (8008f18 <HAL_DMA_Abort_IT+0x1dc>)
 8008e00:	4293      	cmp	r3, r2
 8008e02:	d101      	bne.n	8008e08 <HAL_DMA_Abort_IT+0xcc>
 8008e04:	2301      	movs	r3, #1
 8008e06:	e000      	b.n	8008e0a <HAL_DMA_Abort_IT+0xce>
 8008e08:	2300      	movs	r3, #0
 8008e0a:	2b00      	cmp	r3, #0
 8008e0c:	f000 8086 	beq.w	8008f1c <HAL_DMA_Abort_IT+0x1e0>
    {
      /* Set Abort State  */
      hdma->State = HAL_DMA_STATE_ABORT;
 8008e10:	687b      	ldr	r3, [r7, #4]
 8008e12:	2204      	movs	r2, #4
 8008e14:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

      /* Disable the stream */
      __HAL_DMA_DISABLE(hdma);
 8008e18:	687b      	ldr	r3, [r7, #4]
 8008e1a:	681b      	ldr	r3, [r3, #0]
 8008e1c:	4a2f      	ldr	r2, [pc, #188]	@ (8008edc <HAL_DMA_Abort_IT+0x1a0>)
 8008e1e:	4293      	cmp	r3, r2
 8008e20:	d04a      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e22:	687b      	ldr	r3, [r7, #4]
 8008e24:	681b      	ldr	r3, [r3, #0]
 8008e26:	4a2e      	ldr	r2, [pc, #184]	@ (8008ee0 <HAL_DMA_Abort_IT+0x1a4>)
 8008e28:	4293      	cmp	r3, r2
 8008e2a:	d045      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e2c:	687b      	ldr	r3, [r7, #4]
 8008e2e:	681b      	ldr	r3, [r3, #0]
 8008e30:	4a2c      	ldr	r2, [pc, #176]	@ (8008ee4 <HAL_DMA_Abort_IT+0x1a8>)
 8008e32:	4293      	cmp	r3, r2
 8008e34:	d040      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e36:	687b      	ldr	r3, [r7, #4]
 8008e38:	681b      	ldr	r3, [r3, #0]
 8008e3a:	4a2b      	ldr	r2, [pc, #172]	@ (8008ee8 <HAL_DMA_Abort_IT+0x1ac>)
 8008e3c:	4293      	cmp	r3, r2
 8008e3e:	d03b      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e40:	687b      	ldr	r3, [r7, #4]
 8008e42:	681b      	ldr	r3, [r3, #0]
 8008e44:	4a29      	ldr	r2, [pc, #164]	@ (8008eec <HAL_DMA_Abort_IT+0x1b0>)
 8008e46:	4293      	cmp	r3, r2
 8008e48:	d036      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e4a:	687b      	ldr	r3, [r7, #4]
 8008e4c:	681b      	ldr	r3, [r3, #0]
 8008e4e:	4a28      	ldr	r2, [pc, #160]	@ (8008ef0 <HAL_DMA_Abort_IT+0x1b4>)
 8008e50:	4293      	cmp	r3, r2
 8008e52:	d031      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e54:	687b      	ldr	r3, [r7, #4]
 8008e56:	681b      	ldr	r3, [r3, #0]
 8008e58:	4a26      	ldr	r2, [pc, #152]	@ (8008ef4 <HAL_DMA_Abort_IT+0x1b8>)
 8008e5a:	4293      	cmp	r3, r2
 8008e5c:	d02c      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e5e:	687b      	ldr	r3, [r7, #4]
 8008e60:	681b      	ldr	r3, [r3, #0]
 8008e62:	4a25      	ldr	r2, [pc, #148]	@ (8008ef8 <HAL_DMA_Abort_IT+0x1bc>)
 8008e64:	4293      	cmp	r3, r2
 8008e66:	d027      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e68:	687b      	ldr	r3, [r7, #4]
 8008e6a:	681b      	ldr	r3, [r3, #0]
 8008e6c:	4a23      	ldr	r2, [pc, #140]	@ (8008efc <HAL_DMA_Abort_IT+0x1c0>)
 8008e6e:	4293      	cmp	r3, r2
 8008e70:	d022      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e72:	687b      	ldr	r3, [r7, #4]
 8008e74:	681b      	ldr	r3, [r3, #0]
 8008e76:	4a22      	ldr	r2, [pc, #136]	@ (8008f00 <HAL_DMA_Abort_IT+0x1c4>)
 8008e78:	4293      	cmp	r3, r2
 8008e7a:	d01d      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e7c:	687b      	ldr	r3, [r7, #4]
 8008e7e:	681b      	ldr	r3, [r3, #0]
 8008e80:	4a20      	ldr	r2, [pc, #128]	@ (8008f04 <HAL_DMA_Abort_IT+0x1c8>)
 8008e82:	4293      	cmp	r3, r2
 8008e84:	d018      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e86:	687b      	ldr	r3, [r7, #4]
 8008e88:	681b      	ldr	r3, [r3, #0]
 8008e8a:	4a1f      	ldr	r2, [pc, #124]	@ (8008f08 <HAL_DMA_Abort_IT+0x1cc>)
 8008e8c:	4293      	cmp	r3, r2
 8008e8e:	d013      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e90:	687b      	ldr	r3, [r7, #4]
 8008e92:	681b      	ldr	r3, [r3, #0]
 8008e94:	4a1d      	ldr	r2, [pc, #116]	@ (8008f0c <HAL_DMA_Abort_IT+0x1d0>)
 8008e96:	4293      	cmp	r3, r2
 8008e98:	d00e      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008e9a:	687b      	ldr	r3, [r7, #4]
 8008e9c:	681b      	ldr	r3, [r3, #0]
 8008e9e:	4a1c      	ldr	r2, [pc, #112]	@ (8008f10 <HAL_DMA_Abort_IT+0x1d4>)
 8008ea0:	4293      	cmp	r3, r2
 8008ea2:	d009      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008ea4:	687b      	ldr	r3, [r7, #4]
 8008ea6:	681b      	ldr	r3, [r3, #0]
 8008ea8:	4a1a      	ldr	r2, [pc, #104]	@ (8008f14 <HAL_DMA_Abort_IT+0x1d8>)
 8008eaa:	4293      	cmp	r3, r2
 8008eac:	d004      	beq.n	8008eb8 <HAL_DMA_Abort_IT+0x17c>
 8008eae:	687b      	ldr	r3, [r7, #4]
 8008eb0:	681b      	ldr	r3, [r3, #0]
 8008eb2:	4a19      	ldr	r2, [pc, #100]	@ (8008f18 <HAL_DMA_Abort_IT+0x1dc>)
 8008eb4:	4293      	cmp	r3, r2
 8008eb6:	d108      	bne.n	8008eca <HAL_DMA_Abort_IT+0x18e>
 8008eb8:	687b      	ldr	r3, [r7, #4]
 8008eba:	681b      	ldr	r3, [r3, #0]
 8008ebc:	681a      	ldr	r2, [r3, #0]
 8008ebe:	687b      	ldr	r3, [r7, #4]
 8008ec0:	681b      	ldr	r3, [r3, #0]
 8008ec2:	f022 0201 	bic.w	r2, r2, #1
 8008ec6:	601a      	str	r2, [r3, #0]
 8008ec8:	e178      	b.n	80091bc <HAL_DMA_Abort_IT+0x480>
 8008eca:	687b      	ldr	r3, [r7, #4]
 8008ecc:	681b      	ldr	r3, [r3, #0]
 8008ece:	681a      	ldr	r2, [r3, #0]
 8008ed0:	687b      	ldr	r3, [r7, #4]
 8008ed2:	681b      	ldr	r3, [r3, #0]
 8008ed4:	f022 0201 	bic.w	r2, r2, #1
 8008ed8:	601a      	str	r2, [r3, #0]
 8008eda:	e16f      	b.n	80091bc <HAL_DMA_Abort_IT+0x480>
 8008edc:	40020010 	.word	0x40020010
 8008ee0:	40020028 	.word	0x40020028
 8008ee4:	40020040 	.word	0x40020040
 8008ee8:	40020058 	.word	0x40020058
 8008eec:	40020070 	.word	0x40020070
 8008ef0:	40020088 	.word	0x40020088
 8008ef4:	400200a0 	.word	0x400200a0
 8008ef8:	400200b8 	.word	0x400200b8
 8008efc:	40020410 	.word	0x40020410
 8008f00:	40020428 	.word	0x40020428
 8008f04:	40020440 	.word	0x40020440
 8008f08:	40020458 	.word	0x40020458
 8008f0c:	40020470 	.word	0x40020470
 8008f10:	40020488 	.word	0x40020488
 8008f14:	400204a0 	.word	0x400204a0
 8008f18:	400204b8 	.word	0x400204b8
    }
    else /* BDMA channel */
    {
      /* Disable DMA All Interrupts  */
      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
 8008f1c:	687b      	ldr	r3, [r7, #4]
 8008f1e:	681b      	ldr	r3, [r3, #0]
 8008f20:	681a      	ldr	r2, [r3, #0]
 8008f22:	687b      	ldr	r3, [r7, #4]
 8008f24:	681b      	ldr	r3, [r3, #0]
 8008f26:	f022 020e 	bic.w	r2, r2, #14
 8008f2a:	601a      	str	r2, [r3, #0]

      /* Disable the channel */
      __HAL_DMA_DISABLE(hdma);
 8008f2c:	687b      	ldr	r3, [r7, #4]
 8008f2e:	681b      	ldr	r3, [r3, #0]
 8008f30:	4a6c      	ldr	r2, [pc, #432]	@ (80090e4 <HAL_DMA_Abort_IT+0x3a8>)
 8008f32:	4293      	cmp	r3, r2
 8008f34:	d04a      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008f36:	687b      	ldr	r3, [r7, #4]
 8008f38:	681b      	ldr	r3, [r3, #0]
 8008f3a:	4a6b      	ldr	r2, [pc, #428]	@ (80090e8 <HAL_DMA_Abort_IT+0x3ac>)
 8008f3c:	4293      	cmp	r3, r2
 8008f3e:	d045      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008f40:	687b      	ldr	r3, [r7, #4]
 8008f42:	681b      	ldr	r3, [r3, #0]
 8008f44:	4a69      	ldr	r2, [pc, #420]	@ (80090ec <HAL_DMA_Abort_IT+0x3b0>)
 8008f46:	4293      	cmp	r3, r2
 8008f48:	d040      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008f4a:	687b      	ldr	r3, [r7, #4]
 8008f4c:	681b      	ldr	r3, [r3, #0]
 8008f4e:	4a68      	ldr	r2, [pc, #416]	@ (80090f0 <HAL_DMA_Abort_IT+0x3b4>)
 8008f50:	4293      	cmp	r3, r2
 8008f52:	d03b      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008f54:	687b      	ldr	r3, [r7, #4]
 8008f56:	681b      	ldr	r3, [r3, #0]
 8008f58:	4a66      	ldr	r2, [pc, #408]	@ (80090f4 <HAL_DMA_Abort_IT+0x3b8>)
 8008f5a:	4293      	cmp	r3, r2
 8008f5c:	d036      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008f5e:	687b      	ldr	r3, [r7, #4]
 8008f60:	681b      	ldr	r3, [r3, #0]
 8008f62:	4a65      	ldr	r2, [pc, #404]	@ (80090f8 <HAL_DMA_Abort_IT+0x3bc>)
 8008f64:	4293      	cmp	r3, r2
 8008f66:	d031      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008f68:	687b      	ldr	r3, [r7, #4]
 8008f6a:	681b      	ldr	r3, [r3, #0]
 8008f6c:	4a63      	ldr	r2, [pc, #396]	@ (80090fc <HAL_DMA_Abort_IT+0x3c0>)
 8008f6e:	4293      	cmp	r3, r2
 8008f70:	d02c      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008f72:	687b      	ldr	r3, [r7, #4]
 8008f74:	681b      	ldr	r3, [r3, #0]
 8008f76:	4a62      	ldr	r2, [pc, #392]	@ (8009100 <HAL_DMA_Abort_IT+0x3c4>)
 8008f78:	4293      	cmp	r3, r2
 8008f7a:	d027      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008f7c:	687b      	ldr	r3, [r7, #4]
 8008f7e:	681b      	ldr	r3, [r3, #0]
 8008f80:	4a60      	ldr	r2, [pc, #384]	@ (8009104 <HAL_DMA_Abort_IT+0x3c8>)
 8008f82:	4293      	cmp	r3, r2
 8008f84:	d022      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008f86:	687b      	ldr	r3, [r7, #4]
 8008f88:	681b      	ldr	r3, [r3, #0]
 8008f8a:	4a5f      	ldr	r2, [pc, #380]	@ (8009108 <HAL_DMA_Abort_IT+0x3cc>)
 8008f8c:	4293      	cmp	r3, r2
 8008f8e:	d01d      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008f90:	687b      	ldr	r3, [r7, #4]
 8008f92:	681b      	ldr	r3, [r3, #0]
 8008f94:	4a5d      	ldr	r2, [pc, #372]	@ (800910c <HAL_DMA_Abort_IT+0x3d0>)
 8008f96:	4293      	cmp	r3, r2
 8008f98:	d018      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008f9a:	687b      	ldr	r3, [r7, #4]
 8008f9c:	681b      	ldr	r3, [r3, #0]
 8008f9e:	4a5c      	ldr	r2, [pc, #368]	@ (8009110 <HAL_DMA_Abort_IT+0x3d4>)
 8008fa0:	4293      	cmp	r3, r2
 8008fa2:	d013      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008fa4:	687b      	ldr	r3, [r7, #4]
 8008fa6:	681b      	ldr	r3, [r3, #0]
 8008fa8:	4a5a      	ldr	r2, [pc, #360]	@ (8009114 <HAL_DMA_Abort_IT+0x3d8>)
 8008faa:	4293      	cmp	r3, r2
 8008fac:	d00e      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008fae:	687b      	ldr	r3, [r7, #4]
 8008fb0:	681b      	ldr	r3, [r3, #0]
 8008fb2:	4a59      	ldr	r2, [pc, #356]	@ (8009118 <HAL_DMA_Abort_IT+0x3dc>)
 8008fb4:	4293      	cmp	r3, r2
 8008fb6:	d009      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008fb8:	687b      	ldr	r3, [r7, #4]
 8008fba:	681b      	ldr	r3, [r3, #0]
 8008fbc:	4a57      	ldr	r2, [pc, #348]	@ (800911c <HAL_DMA_Abort_IT+0x3e0>)
 8008fbe:	4293      	cmp	r3, r2
 8008fc0:	d004      	beq.n	8008fcc <HAL_DMA_Abort_IT+0x290>
 8008fc2:	687b      	ldr	r3, [r7, #4]
 8008fc4:	681b      	ldr	r3, [r3, #0]
 8008fc6:	4a56      	ldr	r2, [pc, #344]	@ (8009120 <HAL_DMA_Abort_IT+0x3e4>)
 8008fc8:	4293      	cmp	r3, r2
 8008fca:	d108      	bne.n	8008fde <HAL_DMA_Abort_IT+0x2a2>
 8008fcc:	687b      	ldr	r3, [r7, #4]
 8008fce:	681b      	ldr	r3, [r3, #0]
 8008fd0:	681a      	ldr	r2, [r3, #0]
 8008fd2:	687b      	ldr	r3, [r7, #4]
 8008fd4:	681b      	ldr	r3, [r3, #0]
 8008fd6:	f022 0201 	bic.w	r2, r2, #1
 8008fda:	601a      	str	r2, [r3, #0]
 8008fdc:	e007      	b.n	8008fee <HAL_DMA_Abort_IT+0x2b2>
 8008fde:	687b      	ldr	r3, [r7, #4]
 8008fe0:	681b      	ldr	r3, [r3, #0]
 8008fe2:	681a      	ldr	r2, [r3, #0]
 8008fe4:	687b      	ldr	r3, [r7, #4]
 8008fe6:	681b      	ldr	r3, [r3, #0]
 8008fe8:	f022 0201 	bic.w	r2, r2, #1
 8008fec:	601a      	str	r2, [r3, #0]

      if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
 8008fee:	687b      	ldr	r3, [r7, #4]
 8008ff0:	681b      	ldr	r3, [r3, #0]
 8008ff2:	4a3c      	ldr	r2, [pc, #240]	@ (80090e4 <HAL_DMA_Abort_IT+0x3a8>)
 8008ff4:	4293      	cmp	r3, r2
 8008ff6:	d072      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 8008ff8:	687b      	ldr	r3, [r7, #4]
 8008ffa:	681b      	ldr	r3, [r3, #0]
 8008ffc:	4a3a      	ldr	r2, [pc, #232]	@ (80090e8 <HAL_DMA_Abort_IT+0x3ac>)
 8008ffe:	4293      	cmp	r3, r2
 8009000:	d06d      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 8009002:	687b      	ldr	r3, [r7, #4]
 8009004:	681b      	ldr	r3, [r3, #0]
 8009006:	4a39      	ldr	r2, [pc, #228]	@ (80090ec <HAL_DMA_Abort_IT+0x3b0>)
 8009008:	4293      	cmp	r3, r2
 800900a:	d068      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 800900c:	687b      	ldr	r3, [r7, #4]
 800900e:	681b      	ldr	r3, [r3, #0]
 8009010:	4a37      	ldr	r2, [pc, #220]	@ (80090f0 <HAL_DMA_Abort_IT+0x3b4>)
 8009012:	4293      	cmp	r3, r2
 8009014:	d063      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 8009016:	687b      	ldr	r3, [r7, #4]
 8009018:	681b      	ldr	r3, [r3, #0]
 800901a:	4a36      	ldr	r2, [pc, #216]	@ (80090f4 <HAL_DMA_Abort_IT+0x3b8>)
 800901c:	4293      	cmp	r3, r2
 800901e:	d05e      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 8009020:	687b      	ldr	r3, [r7, #4]
 8009022:	681b      	ldr	r3, [r3, #0]
 8009024:	4a34      	ldr	r2, [pc, #208]	@ (80090f8 <HAL_DMA_Abort_IT+0x3bc>)
 8009026:	4293      	cmp	r3, r2
 8009028:	d059      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 800902a:	687b      	ldr	r3, [r7, #4]
 800902c:	681b      	ldr	r3, [r3, #0]
 800902e:	4a33      	ldr	r2, [pc, #204]	@ (80090fc <HAL_DMA_Abort_IT+0x3c0>)
 8009030:	4293      	cmp	r3, r2
 8009032:	d054      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 8009034:	687b      	ldr	r3, [r7, #4]
 8009036:	681b      	ldr	r3, [r3, #0]
 8009038:	4a31      	ldr	r2, [pc, #196]	@ (8009100 <HAL_DMA_Abort_IT+0x3c4>)
 800903a:	4293      	cmp	r3, r2
 800903c:	d04f      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 800903e:	687b      	ldr	r3, [r7, #4]
 8009040:	681b      	ldr	r3, [r3, #0]
 8009042:	4a30      	ldr	r2, [pc, #192]	@ (8009104 <HAL_DMA_Abort_IT+0x3c8>)
 8009044:	4293      	cmp	r3, r2
 8009046:	d04a      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 8009048:	687b      	ldr	r3, [r7, #4]
 800904a:	681b      	ldr	r3, [r3, #0]
 800904c:	4a2e      	ldr	r2, [pc, #184]	@ (8009108 <HAL_DMA_Abort_IT+0x3cc>)
 800904e:	4293      	cmp	r3, r2
 8009050:	d045      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 8009052:	687b      	ldr	r3, [r7, #4]
 8009054:	681b      	ldr	r3, [r3, #0]
 8009056:	4a2d      	ldr	r2, [pc, #180]	@ (800910c <HAL_DMA_Abort_IT+0x3d0>)
 8009058:	4293      	cmp	r3, r2
 800905a:	d040      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 800905c:	687b      	ldr	r3, [r7, #4]
 800905e:	681b      	ldr	r3, [r3, #0]
 8009060:	4a2b      	ldr	r2, [pc, #172]	@ (8009110 <HAL_DMA_Abort_IT+0x3d4>)
 8009062:	4293      	cmp	r3, r2
 8009064:	d03b      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 8009066:	687b      	ldr	r3, [r7, #4]
 8009068:	681b      	ldr	r3, [r3, #0]
 800906a:	4a2a      	ldr	r2, [pc, #168]	@ (8009114 <HAL_DMA_Abort_IT+0x3d8>)
 800906c:	4293      	cmp	r3, r2
 800906e:	d036      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 8009070:	687b      	ldr	r3, [r7, #4]
 8009072:	681b      	ldr	r3, [r3, #0]
 8009074:	4a28      	ldr	r2, [pc, #160]	@ (8009118 <HAL_DMA_Abort_IT+0x3dc>)
 8009076:	4293      	cmp	r3, r2
 8009078:	d031      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 800907a:	687b      	ldr	r3, [r7, #4]
 800907c:	681b      	ldr	r3, [r3, #0]
 800907e:	4a27      	ldr	r2, [pc, #156]	@ (800911c <HAL_DMA_Abort_IT+0x3e0>)
 8009080:	4293      	cmp	r3, r2
 8009082:	d02c      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 8009084:	687b      	ldr	r3, [r7, #4]
 8009086:	681b      	ldr	r3, [r3, #0]
 8009088:	4a25      	ldr	r2, [pc, #148]	@ (8009120 <HAL_DMA_Abort_IT+0x3e4>)
 800908a:	4293      	cmp	r3, r2
 800908c:	d027      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 800908e:	687b      	ldr	r3, [r7, #4]
 8009090:	681b      	ldr	r3, [r3, #0]
 8009092:	4a24      	ldr	r2, [pc, #144]	@ (8009124 <HAL_DMA_Abort_IT+0x3e8>)
 8009094:	4293      	cmp	r3, r2
 8009096:	d022      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 8009098:	687b      	ldr	r3, [r7, #4]
 800909a:	681b      	ldr	r3, [r3, #0]
 800909c:	4a22      	ldr	r2, [pc, #136]	@ (8009128 <HAL_DMA_Abort_IT+0x3ec>)
 800909e:	4293      	cmp	r3, r2
 80090a0:	d01d      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 80090a2:	687b      	ldr	r3, [r7, #4]
 80090a4:	681b      	ldr	r3, [r3, #0]
 80090a6:	4a21      	ldr	r2, [pc, #132]	@ (800912c <HAL_DMA_Abort_IT+0x3f0>)
 80090a8:	4293      	cmp	r3, r2
 80090aa:	d018      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 80090ac:	687b      	ldr	r3, [r7, #4]
 80090ae:	681b      	ldr	r3, [r3, #0]
 80090b0:	4a1f      	ldr	r2, [pc, #124]	@ (8009130 <HAL_DMA_Abort_IT+0x3f4>)
 80090b2:	4293      	cmp	r3, r2
 80090b4:	d013      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 80090b6:	687b      	ldr	r3, [r7, #4]
 80090b8:	681b      	ldr	r3, [r3, #0]
 80090ba:	4a1e      	ldr	r2, [pc, #120]	@ (8009134 <HAL_DMA_Abort_IT+0x3f8>)
 80090bc:	4293      	cmp	r3, r2
 80090be:	d00e      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 80090c0:	687b      	ldr	r3, [r7, #4]
 80090c2:	681b      	ldr	r3, [r3, #0]
 80090c4:	4a1c      	ldr	r2, [pc, #112]	@ (8009138 <HAL_DMA_Abort_IT+0x3fc>)
 80090c6:	4293      	cmp	r3, r2
 80090c8:	d009      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 80090ca:	687b      	ldr	r3, [r7, #4]
 80090cc:	681b      	ldr	r3, [r3, #0]
 80090ce:	4a1b      	ldr	r2, [pc, #108]	@ (800913c <HAL_DMA_Abort_IT+0x400>)
 80090d0:	4293      	cmp	r3, r2
 80090d2:	d004      	beq.n	80090de <HAL_DMA_Abort_IT+0x3a2>
 80090d4:	687b      	ldr	r3, [r7, #4]
 80090d6:	681b      	ldr	r3, [r3, #0]
 80090d8:	4a19      	ldr	r2, [pc, #100]	@ (8009140 <HAL_DMA_Abort_IT+0x404>)
 80090da:	4293      	cmp	r3, r2
 80090dc:	d132      	bne.n	8009144 <HAL_DMA_Abort_IT+0x408>
 80090de:	2301      	movs	r3, #1
 80090e0:	e031      	b.n	8009146 <HAL_DMA_Abort_IT+0x40a>
 80090e2:	bf00      	nop
 80090e4:	40020010 	.word	0x40020010
 80090e8:	40020028 	.word	0x40020028
 80090ec:	40020040 	.word	0x40020040
 80090f0:	40020058 	.word	0x40020058
 80090f4:	40020070 	.word	0x40020070
 80090f8:	40020088 	.word	0x40020088
 80090fc:	400200a0 	.word	0x400200a0
 8009100:	400200b8 	.word	0x400200b8
 8009104:	40020410 	.word	0x40020410
 8009108:	40020428 	.word	0x40020428
 800910c:	40020440 	.word	0x40020440
 8009110:	40020458 	.word	0x40020458
 8009114:	40020470 	.word	0x40020470
 8009118:	40020488 	.word	0x40020488
 800911c:	400204a0 	.word	0x400204a0
 8009120:	400204b8 	.word	0x400204b8
 8009124:	58025408 	.word	0x58025408
 8009128:	5802541c 	.word	0x5802541c
 800912c:	58025430 	.word	0x58025430
 8009130:	58025444 	.word	0x58025444
 8009134:	58025458 	.word	0x58025458
 8009138:	5802546c 	.word	0x5802546c
 800913c:	58025480 	.word	0x58025480
 8009140:	58025494 	.word	0x58025494
 8009144:	2300      	movs	r3, #0
 8009146:	2b00      	cmp	r3, #0
 8009148:	d028      	beq.n	800919c <HAL_DMA_Abort_IT+0x460>
      {
        /* disable the DMAMUX sync overrun IT */
        hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
 800914a:	687b      	ldr	r3, [r7, #4]
 800914c:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 800914e:	681a      	ldr	r2, [r3, #0]
 8009150:	687b      	ldr	r3, [r7, #4]
 8009152:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8009154:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
 8009158:	601a      	str	r2, [r3, #0]

        /* Clear all flags */
        regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
 800915a:	687b      	ldr	r3, [r7, #4]
 800915c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800915e:	60fb      	str	r3, [r7, #12]
        regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
 8009160:	687b      	ldr	r3, [r7, #4]
 8009162:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8009164:	f003 031f 	and.w	r3, r3, #31
 8009168:	2201      	movs	r2, #1
 800916a:	409a      	lsls	r2, r3
 800916c:	68fb      	ldr	r3, [r7, #12]
 800916e:	605a      	str	r2, [r3, #4]

        /* Clear the DMAMUX synchro overrun flag */
        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 8009170:	687b      	ldr	r3, [r7, #4]
 8009172:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8009174:	687a      	ldr	r2, [r7, #4]
 8009176:	6e92      	ldr	r2, [r2, #104]	@ 0x68
 8009178:	605a      	str	r2, [r3, #4]

        if(hdma->DMAmuxRequestGen != 0U)
 800917a:	687b      	ldr	r3, [r7, #4]
 800917c:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800917e:	2b00      	cmp	r3, #0
 8009180:	d00c      	beq.n	800919c <HAL_DMA_Abort_IT+0x460>
        {
          /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
          /* disable the request gen overrun IT */
          hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
 8009182:	687b      	ldr	r3, [r7, #4]
 8009184:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8009186:	681a      	ldr	r2, [r3, #0]
 8009188:	687b      	ldr	r3, [r7, #4]
 800918a:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800918c:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
 8009190:	601a      	str	r2, [r3, #0]

          /* Clear the DMAMUX request generator overrun flag */
          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 8009192:	687b      	ldr	r3, [r7, #4]
 8009194:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8009196:	687a      	ldr	r2, [r7, #4]
 8009198:	6f52      	ldr	r2, [r2, #116]	@ 0x74
 800919a:	605a      	str	r2, [r3, #4]
        }
      }

      /* Change the DMA state */
      hdma->State = HAL_DMA_STATE_READY;
 800919c:	687b      	ldr	r3, [r7, #4]
 800919e:	2201      	movs	r2, #1
 80091a0:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

      /* Process Unlocked */
      __HAL_UNLOCK(hdma);
 80091a4:	687b      	ldr	r3, [r7, #4]
 80091a6:	2200      	movs	r2, #0
 80091a8:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

      /* Call User Abort callback */
      if(hdma->XferAbortCallback != NULL)
 80091ac:	687b      	ldr	r3, [r7, #4]
 80091ae:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80091b0:	2b00      	cmp	r3, #0
 80091b2:	d003      	beq.n	80091bc <HAL_DMA_Abort_IT+0x480>
      {
        hdma->XferAbortCallback(hdma);
 80091b4:	687b      	ldr	r3, [r7, #4]
 80091b6:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80091b8:	6878      	ldr	r0, [r7, #4]
 80091ba:	4798      	blx	r3
      }
    }
  }

  return HAL_OK;
 80091bc:	2300      	movs	r3, #0
}
 80091be:	4618      	mov	r0, r3
 80091c0:	3710      	adds	r7, #16
 80091c2:	46bd      	mov	sp, r7
 80091c4:	bd80      	pop	{r7, pc}
 80091c6:	bf00      	nop

080091c8 <HAL_DMA_IRQHandler>:
  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Stream.
  * @retval None
  */
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
 80091c8:	b580      	push	{r7, lr}
 80091ca:	b08a      	sub	sp, #40	@ 0x28
 80091cc:	af00      	add	r7, sp, #0
 80091ce:	6078      	str	r0, [r7, #4]
  uint32_t tmpisr_dma, tmpisr_bdma;
  uint32_t ccr_reg;
  __IO uint32_t count = 0U;
 80091d0:	2300      	movs	r3, #0
 80091d2:	60fb      	str	r3, [r7, #12]
  uint32_t timeout = SystemCoreClock / 9600U;
 80091d4:	4b67      	ldr	r3, [pc, #412]	@ (8009374 <HAL_DMA_IRQHandler+0x1ac>)
 80091d6:	681b      	ldr	r3, [r3, #0]
 80091d8:	4a67      	ldr	r2, [pc, #412]	@ (8009378 <HAL_DMA_IRQHandler+0x1b0>)
 80091da:	fba2 2303 	umull	r2, r3, r2, r3
 80091de:	0a9b      	lsrs	r3, r3, #10
 80091e0:	627b      	str	r3, [r7, #36]	@ 0x24

  /* calculate DMA base and stream number */
  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
 80091e2:	687b      	ldr	r3, [r7, #4]
 80091e4:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80091e6:	623b      	str	r3, [r7, #32]
  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
 80091e8:	687b      	ldr	r3, [r7, #4]
 80091ea:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80091ec:	61fb      	str	r3, [r7, #28]

  tmpisr_dma  = regs_dma->ISR;
 80091ee:	6a3b      	ldr	r3, [r7, #32]
 80091f0:	681b      	ldr	r3, [r3, #0]
 80091f2:	61bb      	str	r3, [r7, #24]
  tmpisr_bdma = regs_bdma->ISR;
 80091f4:	69fb      	ldr	r3, [r7, #28]
 80091f6:	681b      	ldr	r3, [r3, #0]
 80091f8:	617b      	str	r3, [r7, #20]

  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U)  /* DMA1 or DMA2 instance */
 80091fa:	687b      	ldr	r3, [r7, #4]
 80091fc:	681b      	ldr	r3, [r3, #0]
 80091fe:	4a5f      	ldr	r2, [pc, #380]	@ (800937c <HAL_DMA_IRQHandler+0x1b4>)
 8009200:	4293      	cmp	r3, r2
 8009202:	d04a      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 8009204:	687b      	ldr	r3, [r7, #4]
 8009206:	681b      	ldr	r3, [r3, #0]
 8009208:	4a5d      	ldr	r2, [pc, #372]	@ (8009380 <HAL_DMA_IRQHandler+0x1b8>)
 800920a:	4293      	cmp	r3, r2
 800920c:	d045      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 800920e:	687b      	ldr	r3, [r7, #4]
 8009210:	681b      	ldr	r3, [r3, #0]
 8009212:	4a5c      	ldr	r2, [pc, #368]	@ (8009384 <HAL_DMA_IRQHandler+0x1bc>)
 8009214:	4293      	cmp	r3, r2
 8009216:	d040      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 8009218:	687b      	ldr	r3, [r7, #4]
 800921a:	681b      	ldr	r3, [r3, #0]
 800921c:	4a5a      	ldr	r2, [pc, #360]	@ (8009388 <HAL_DMA_IRQHandler+0x1c0>)
 800921e:	4293      	cmp	r3, r2
 8009220:	d03b      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 8009222:	687b      	ldr	r3, [r7, #4]
 8009224:	681b      	ldr	r3, [r3, #0]
 8009226:	4a59      	ldr	r2, [pc, #356]	@ (800938c <HAL_DMA_IRQHandler+0x1c4>)
 8009228:	4293      	cmp	r3, r2
 800922a:	d036      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 800922c:	687b      	ldr	r3, [r7, #4]
 800922e:	681b      	ldr	r3, [r3, #0]
 8009230:	4a57      	ldr	r2, [pc, #348]	@ (8009390 <HAL_DMA_IRQHandler+0x1c8>)
 8009232:	4293      	cmp	r3, r2
 8009234:	d031      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 8009236:	687b      	ldr	r3, [r7, #4]
 8009238:	681b      	ldr	r3, [r3, #0]
 800923a:	4a56      	ldr	r2, [pc, #344]	@ (8009394 <HAL_DMA_IRQHandler+0x1cc>)
 800923c:	4293      	cmp	r3, r2
 800923e:	d02c      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 8009240:	687b      	ldr	r3, [r7, #4]
 8009242:	681b      	ldr	r3, [r3, #0]
 8009244:	4a54      	ldr	r2, [pc, #336]	@ (8009398 <HAL_DMA_IRQHandler+0x1d0>)
 8009246:	4293      	cmp	r3, r2
 8009248:	d027      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 800924a:	687b      	ldr	r3, [r7, #4]
 800924c:	681b      	ldr	r3, [r3, #0]
 800924e:	4a53      	ldr	r2, [pc, #332]	@ (800939c <HAL_DMA_IRQHandler+0x1d4>)
 8009250:	4293      	cmp	r3, r2
 8009252:	d022      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 8009254:	687b      	ldr	r3, [r7, #4]
 8009256:	681b      	ldr	r3, [r3, #0]
 8009258:	4a51      	ldr	r2, [pc, #324]	@ (80093a0 <HAL_DMA_IRQHandler+0x1d8>)
 800925a:	4293      	cmp	r3, r2
 800925c:	d01d      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 800925e:	687b      	ldr	r3, [r7, #4]
 8009260:	681b      	ldr	r3, [r3, #0]
 8009262:	4a50      	ldr	r2, [pc, #320]	@ (80093a4 <HAL_DMA_IRQHandler+0x1dc>)
 8009264:	4293      	cmp	r3, r2
 8009266:	d018      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 8009268:	687b      	ldr	r3, [r7, #4]
 800926a:	681b      	ldr	r3, [r3, #0]
 800926c:	4a4e      	ldr	r2, [pc, #312]	@ (80093a8 <HAL_DMA_IRQHandler+0x1e0>)
 800926e:	4293      	cmp	r3, r2
 8009270:	d013      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 8009272:	687b      	ldr	r3, [r7, #4]
 8009274:	681b      	ldr	r3, [r3, #0]
 8009276:	4a4d      	ldr	r2, [pc, #308]	@ (80093ac <HAL_DMA_IRQHandler+0x1e4>)
 8009278:	4293      	cmp	r3, r2
 800927a:	d00e      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 800927c:	687b      	ldr	r3, [r7, #4]
 800927e:	681b      	ldr	r3, [r3, #0]
 8009280:	4a4b      	ldr	r2, [pc, #300]	@ (80093b0 <HAL_DMA_IRQHandler+0x1e8>)
 8009282:	4293      	cmp	r3, r2
 8009284:	d009      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 8009286:	687b      	ldr	r3, [r7, #4]
 8009288:	681b      	ldr	r3, [r3, #0]
 800928a:	4a4a      	ldr	r2, [pc, #296]	@ (80093b4 <HAL_DMA_IRQHandler+0x1ec>)
 800928c:	4293      	cmp	r3, r2
 800928e:	d004      	beq.n	800929a <HAL_DMA_IRQHandler+0xd2>
 8009290:	687b      	ldr	r3, [r7, #4]
 8009292:	681b      	ldr	r3, [r3, #0]
 8009294:	4a48      	ldr	r2, [pc, #288]	@ (80093b8 <HAL_DMA_IRQHandler+0x1f0>)
 8009296:	4293      	cmp	r3, r2
 8009298:	d101      	bne.n	800929e <HAL_DMA_IRQHandler+0xd6>
 800929a:	2301      	movs	r3, #1
 800929c:	e000      	b.n	80092a0 <HAL_DMA_IRQHandler+0xd8>
 800929e:	2300      	movs	r3, #0
 80092a0:	2b00      	cmp	r3, #0
 80092a2:	f000 842b 	beq.w	8009afc <HAL_DMA_IRQHandler+0x934>
  {
    /* Transfer Error Interrupt management ***************************************/
    if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
 80092a6:	687b      	ldr	r3, [r7, #4]
 80092a8:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80092aa:	f003 031f 	and.w	r3, r3, #31
 80092ae:	2208      	movs	r2, #8
 80092b0:	409a      	lsls	r2, r3
 80092b2:	69bb      	ldr	r3, [r7, #24]
 80092b4:	4013      	ands	r3, r2
 80092b6:	2b00      	cmp	r3, #0
 80092b8:	f000 80a2 	beq.w	8009400 <HAL_DMA_IRQHandler+0x238>
    {
      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U)
 80092bc:	687b      	ldr	r3, [r7, #4]
 80092be:	681b      	ldr	r3, [r3, #0]
 80092c0:	4a2e      	ldr	r2, [pc, #184]	@ (800937c <HAL_DMA_IRQHandler+0x1b4>)
 80092c2:	4293      	cmp	r3, r2
 80092c4:	d04a      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 80092c6:	687b      	ldr	r3, [r7, #4]
 80092c8:	681b      	ldr	r3, [r3, #0]
 80092ca:	4a2d      	ldr	r2, [pc, #180]	@ (8009380 <HAL_DMA_IRQHandler+0x1b8>)
 80092cc:	4293      	cmp	r3, r2
 80092ce:	d045      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 80092d0:	687b      	ldr	r3, [r7, #4]
 80092d2:	681b      	ldr	r3, [r3, #0]
 80092d4:	4a2b      	ldr	r2, [pc, #172]	@ (8009384 <HAL_DMA_IRQHandler+0x1bc>)
 80092d6:	4293      	cmp	r3, r2
 80092d8:	d040      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 80092da:	687b      	ldr	r3, [r7, #4]
 80092dc:	681b      	ldr	r3, [r3, #0]
 80092de:	4a2a      	ldr	r2, [pc, #168]	@ (8009388 <HAL_DMA_IRQHandler+0x1c0>)
 80092e0:	4293      	cmp	r3, r2
 80092e2:	d03b      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 80092e4:	687b      	ldr	r3, [r7, #4]
 80092e6:	681b      	ldr	r3, [r3, #0]
 80092e8:	4a28      	ldr	r2, [pc, #160]	@ (800938c <HAL_DMA_IRQHandler+0x1c4>)
 80092ea:	4293      	cmp	r3, r2
 80092ec:	d036      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 80092ee:	687b      	ldr	r3, [r7, #4]
 80092f0:	681b      	ldr	r3, [r3, #0]
 80092f2:	4a27      	ldr	r2, [pc, #156]	@ (8009390 <HAL_DMA_IRQHandler+0x1c8>)
 80092f4:	4293      	cmp	r3, r2
 80092f6:	d031      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 80092f8:	687b      	ldr	r3, [r7, #4]
 80092fa:	681b      	ldr	r3, [r3, #0]
 80092fc:	4a25      	ldr	r2, [pc, #148]	@ (8009394 <HAL_DMA_IRQHandler+0x1cc>)
 80092fe:	4293      	cmp	r3, r2
 8009300:	d02c      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 8009302:	687b      	ldr	r3, [r7, #4]
 8009304:	681b      	ldr	r3, [r3, #0]
 8009306:	4a24      	ldr	r2, [pc, #144]	@ (8009398 <HAL_DMA_IRQHandler+0x1d0>)
 8009308:	4293      	cmp	r3, r2
 800930a:	d027      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 800930c:	687b      	ldr	r3, [r7, #4]
 800930e:	681b      	ldr	r3, [r3, #0]
 8009310:	4a22      	ldr	r2, [pc, #136]	@ (800939c <HAL_DMA_IRQHandler+0x1d4>)
 8009312:	4293      	cmp	r3, r2
 8009314:	d022      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 8009316:	687b      	ldr	r3, [r7, #4]
 8009318:	681b      	ldr	r3, [r3, #0]
 800931a:	4a21      	ldr	r2, [pc, #132]	@ (80093a0 <HAL_DMA_IRQHandler+0x1d8>)
 800931c:	4293      	cmp	r3, r2
 800931e:	d01d      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 8009320:	687b      	ldr	r3, [r7, #4]
 8009322:	681b      	ldr	r3, [r3, #0]
 8009324:	4a1f      	ldr	r2, [pc, #124]	@ (80093a4 <HAL_DMA_IRQHandler+0x1dc>)
 8009326:	4293      	cmp	r3, r2
 8009328:	d018      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 800932a:	687b      	ldr	r3, [r7, #4]
 800932c:	681b      	ldr	r3, [r3, #0]
 800932e:	4a1e      	ldr	r2, [pc, #120]	@ (80093a8 <HAL_DMA_IRQHandler+0x1e0>)
 8009330:	4293      	cmp	r3, r2
 8009332:	d013      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 8009334:	687b      	ldr	r3, [r7, #4]
 8009336:	681b      	ldr	r3, [r3, #0]
 8009338:	4a1c      	ldr	r2, [pc, #112]	@ (80093ac <HAL_DMA_IRQHandler+0x1e4>)
 800933a:	4293      	cmp	r3, r2
 800933c:	d00e      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 800933e:	687b      	ldr	r3, [r7, #4]
 8009340:	681b      	ldr	r3, [r3, #0]
 8009342:	4a1b      	ldr	r2, [pc, #108]	@ (80093b0 <HAL_DMA_IRQHandler+0x1e8>)
 8009344:	4293      	cmp	r3, r2
 8009346:	d009      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 8009348:	687b      	ldr	r3, [r7, #4]
 800934a:	681b      	ldr	r3, [r3, #0]
 800934c:	4a19      	ldr	r2, [pc, #100]	@ (80093b4 <HAL_DMA_IRQHandler+0x1ec>)
 800934e:	4293      	cmp	r3, r2
 8009350:	d004      	beq.n	800935c <HAL_DMA_IRQHandler+0x194>
 8009352:	687b      	ldr	r3, [r7, #4]
 8009354:	681b      	ldr	r3, [r3, #0]
 8009356:	4a18      	ldr	r2, [pc, #96]	@ (80093b8 <HAL_DMA_IRQHandler+0x1f0>)
 8009358:	4293      	cmp	r3, r2
 800935a:	d12f      	bne.n	80093bc <HAL_DMA_IRQHandler+0x1f4>
 800935c:	687b      	ldr	r3, [r7, #4]
 800935e:	681b      	ldr	r3, [r3, #0]
 8009360:	681b      	ldr	r3, [r3, #0]
 8009362:	f003 0304 	and.w	r3, r3, #4
 8009366:	2b00      	cmp	r3, #0
 8009368:	bf14      	ite	ne
 800936a:	2301      	movne	r3, #1
 800936c:	2300      	moveq	r3, #0
 800936e:	b2db      	uxtb	r3, r3
 8009370:	e02e      	b.n	80093d0 <HAL_DMA_IRQHandler+0x208>
 8009372:	bf00      	nop
 8009374:	24000034 	.word	0x24000034
 8009378:	1b4e81b5 	.word	0x1b4e81b5
 800937c:	40020010 	.word	0x40020010
 8009380:	40020028 	.word	0x40020028
 8009384:	40020040 	.word	0x40020040
 8009388:	40020058 	.word	0x40020058
 800938c:	40020070 	.word	0x40020070
 8009390:	40020088 	.word	0x40020088
 8009394:	400200a0 	.word	0x400200a0
 8009398:	400200b8 	.word	0x400200b8
 800939c:	40020410 	.word	0x40020410
 80093a0:	40020428 	.word	0x40020428
 80093a4:	40020440 	.word	0x40020440
 80093a8:	40020458 	.word	0x40020458
 80093ac:	40020470 	.word	0x40020470
 80093b0:	40020488 	.word	0x40020488
 80093b4:	400204a0 	.word	0x400204a0
 80093b8:	400204b8 	.word	0x400204b8
 80093bc:	687b      	ldr	r3, [r7, #4]
 80093be:	681b      	ldr	r3, [r3, #0]
 80093c0:	681b      	ldr	r3, [r3, #0]
 80093c2:	f003 0308 	and.w	r3, r3, #8
 80093c6:	2b00      	cmp	r3, #0
 80093c8:	bf14      	ite	ne
 80093ca:	2301      	movne	r3, #1
 80093cc:	2300      	moveq	r3, #0
 80093ce:	b2db      	uxtb	r3, r3
 80093d0:	2b00      	cmp	r3, #0
 80093d2:	d015      	beq.n	8009400 <HAL_DMA_IRQHandler+0x238>
      {
        /* Disable the transfer error interrupt */
        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TE);
 80093d4:	687b      	ldr	r3, [r7, #4]
 80093d6:	681b      	ldr	r3, [r3, #0]
 80093d8:	681a      	ldr	r2, [r3, #0]
 80093da:	687b      	ldr	r3, [r7, #4]
 80093dc:	681b      	ldr	r3, [r3, #0]
 80093de:	f022 0204 	bic.w	r2, r2, #4
 80093e2:	601a      	str	r2, [r3, #0]

        /* Clear the transfer error flag */
        regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
 80093e4:	687b      	ldr	r3, [r7, #4]
 80093e6:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80093e8:	f003 031f 	and.w	r3, r3, #31
 80093ec:	2208      	movs	r2, #8
 80093ee:	409a      	lsls	r2, r3
 80093f0:	6a3b      	ldr	r3, [r7, #32]
 80093f2:	609a      	str	r2, [r3, #8]

        /* Update error code */
        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
 80093f4:	687b      	ldr	r3, [r7, #4]
 80093f6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80093f8:	f043 0201 	orr.w	r2, r3, #1
 80093fc:	687b      	ldr	r3, [r7, #4]
 80093fe:	655a      	str	r2, [r3, #84]	@ 0x54
      }
    }
    /* FIFO Error Interrupt management ******************************************/
    if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
 8009400:	687b      	ldr	r3, [r7, #4]
 8009402:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8009404:	f003 031f 	and.w	r3, r3, #31
 8009408:	69ba      	ldr	r2, [r7, #24]
 800940a:	fa22 f303 	lsr.w	r3, r2, r3
 800940e:	f003 0301 	and.w	r3, r3, #1
 8009412:	2b00      	cmp	r3, #0
 8009414:	d06e      	beq.n	80094f4 <HAL_DMA_IRQHandler+0x32c>
    {
      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
 8009416:	687b      	ldr	r3, [r7, #4]
 8009418:	681b      	ldr	r3, [r3, #0]
 800941a:	4a69      	ldr	r2, [pc, #420]	@ (80095c0 <HAL_DMA_IRQHandler+0x3f8>)
 800941c:	4293      	cmp	r3, r2
 800941e:	d04a      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 8009420:	687b      	ldr	r3, [r7, #4]
 8009422:	681b      	ldr	r3, [r3, #0]
 8009424:	4a67      	ldr	r2, [pc, #412]	@ (80095c4 <HAL_DMA_IRQHandler+0x3fc>)
 8009426:	4293      	cmp	r3, r2
 8009428:	d045      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 800942a:	687b      	ldr	r3, [r7, #4]
 800942c:	681b      	ldr	r3, [r3, #0]
 800942e:	4a66      	ldr	r2, [pc, #408]	@ (80095c8 <HAL_DMA_IRQHandler+0x400>)
 8009430:	4293      	cmp	r3, r2
 8009432:	d040      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 8009434:	687b      	ldr	r3, [r7, #4]
 8009436:	681b      	ldr	r3, [r3, #0]
 8009438:	4a64      	ldr	r2, [pc, #400]	@ (80095cc <HAL_DMA_IRQHandler+0x404>)
 800943a:	4293      	cmp	r3, r2
 800943c:	d03b      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 800943e:	687b      	ldr	r3, [r7, #4]
 8009440:	681b      	ldr	r3, [r3, #0]
 8009442:	4a63      	ldr	r2, [pc, #396]	@ (80095d0 <HAL_DMA_IRQHandler+0x408>)
 8009444:	4293      	cmp	r3, r2
 8009446:	d036      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 8009448:	687b      	ldr	r3, [r7, #4]
 800944a:	681b      	ldr	r3, [r3, #0]
 800944c:	4a61      	ldr	r2, [pc, #388]	@ (80095d4 <HAL_DMA_IRQHandler+0x40c>)
 800944e:	4293      	cmp	r3, r2
 8009450:	d031      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 8009452:	687b      	ldr	r3, [r7, #4]
 8009454:	681b      	ldr	r3, [r3, #0]
 8009456:	4a60      	ldr	r2, [pc, #384]	@ (80095d8 <HAL_DMA_IRQHandler+0x410>)
 8009458:	4293      	cmp	r3, r2
 800945a:	d02c      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 800945c:	687b      	ldr	r3, [r7, #4]
 800945e:	681b      	ldr	r3, [r3, #0]
 8009460:	4a5e      	ldr	r2, [pc, #376]	@ (80095dc <HAL_DMA_IRQHandler+0x414>)
 8009462:	4293      	cmp	r3, r2
 8009464:	d027      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 8009466:	687b      	ldr	r3, [r7, #4]
 8009468:	681b      	ldr	r3, [r3, #0]
 800946a:	4a5d      	ldr	r2, [pc, #372]	@ (80095e0 <HAL_DMA_IRQHandler+0x418>)
 800946c:	4293      	cmp	r3, r2
 800946e:	d022      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 8009470:	687b      	ldr	r3, [r7, #4]
 8009472:	681b      	ldr	r3, [r3, #0]
 8009474:	4a5b      	ldr	r2, [pc, #364]	@ (80095e4 <HAL_DMA_IRQHandler+0x41c>)
 8009476:	4293      	cmp	r3, r2
 8009478:	d01d      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 800947a:	687b      	ldr	r3, [r7, #4]
 800947c:	681b      	ldr	r3, [r3, #0]
 800947e:	4a5a      	ldr	r2, [pc, #360]	@ (80095e8 <HAL_DMA_IRQHandler+0x420>)
 8009480:	4293      	cmp	r3, r2
 8009482:	d018      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 8009484:	687b      	ldr	r3, [r7, #4]
 8009486:	681b      	ldr	r3, [r3, #0]
 8009488:	4a58      	ldr	r2, [pc, #352]	@ (80095ec <HAL_DMA_IRQHandler+0x424>)
 800948a:	4293      	cmp	r3, r2
 800948c:	d013      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 800948e:	687b      	ldr	r3, [r7, #4]
 8009490:	681b      	ldr	r3, [r3, #0]
 8009492:	4a57      	ldr	r2, [pc, #348]	@ (80095f0 <HAL_DMA_IRQHandler+0x428>)
 8009494:	4293      	cmp	r3, r2
 8009496:	d00e      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 8009498:	687b      	ldr	r3, [r7, #4]
 800949a:	681b      	ldr	r3, [r3, #0]
 800949c:	4a55      	ldr	r2, [pc, #340]	@ (80095f4 <HAL_DMA_IRQHandler+0x42c>)
 800949e:	4293      	cmp	r3, r2
 80094a0:	d009      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 80094a2:	687b      	ldr	r3, [r7, #4]
 80094a4:	681b      	ldr	r3, [r3, #0]
 80094a6:	4a54      	ldr	r2, [pc, #336]	@ (80095f8 <HAL_DMA_IRQHandler+0x430>)
 80094a8:	4293      	cmp	r3, r2
 80094aa:	d004      	beq.n	80094b6 <HAL_DMA_IRQHandler+0x2ee>
 80094ac:	687b      	ldr	r3, [r7, #4]
 80094ae:	681b      	ldr	r3, [r3, #0]
 80094b0:	4a52      	ldr	r2, [pc, #328]	@ (80095fc <HAL_DMA_IRQHandler+0x434>)
 80094b2:	4293      	cmp	r3, r2
 80094b4:	d10a      	bne.n	80094cc <HAL_DMA_IRQHandler+0x304>
 80094b6:	687b      	ldr	r3, [r7, #4]
 80094b8:	681b      	ldr	r3, [r3, #0]
 80094ba:	695b      	ldr	r3, [r3, #20]
 80094bc:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80094c0:	2b00      	cmp	r3, #0
 80094c2:	bf14      	ite	ne
 80094c4:	2301      	movne	r3, #1
 80094c6:	2300      	moveq	r3, #0
 80094c8:	b2db      	uxtb	r3, r3
 80094ca:	e003      	b.n	80094d4 <HAL_DMA_IRQHandler+0x30c>
 80094cc:	687b      	ldr	r3, [r7, #4]
 80094ce:	681b      	ldr	r3, [r3, #0]
 80094d0:	681b      	ldr	r3, [r3, #0]
 80094d2:	2300      	movs	r3, #0
 80094d4:	2b00      	cmp	r3, #0
 80094d6:	d00d      	beq.n	80094f4 <HAL_DMA_IRQHandler+0x32c>
      {
        /* Clear the FIFO error flag */
        regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
 80094d8:	687b      	ldr	r3, [r7, #4]
 80094da:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80094dc:	f003 031f 	and.w	r3, r3, #31
 80094e0:	2201      	movs	r2, #1
 80094e2:	409a      	lsls	r2, r3
 80094e4:	6a3b      	ldr	r3, [r7, #32]
 80094e6:	609a      	str	r2, [r3, #8]

        /* Update error code */
        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
 80094e8:	687b      	ldr	r3, [r7, #4]
 80094ea:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80094ec:	f043 0202 	orr.w	r2, r3, #2
 80094f0:	687b      	ldr	r3, [r7, #4]
 80094f2:	655a      	str	r2, [r3, #84]	@ 0x54
      }
    }
    /* Direct Mode Error Interrupt management ***********************************/
    if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
 80094f4:	687b      	ldr	r3, [r7, #4]
 80094f6:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80094f8:	f003 031f 	and.w	r3, r3, #31
 80094fc:	2204      	movs	r2, #4
 80094fe:	409a      	lsls	r2, r3
 8009500:	69bb      	ldr	r3, [r7, #24]
 8009502:	4013      	ands	r3, r2
 8009504:	2b00      	cmp	r3, #0
 8009506:	f000 808f 	beq.w	8009628 <HAL_DMA_IRQHandler+0x460>
    {
      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)
 800950a:	687b      	ldr	r3, [r7, #4]
 800950c:	681b      	ldr	r3, [r3, #0]
 800950e:	4a2c      	ldr	r2, [pc, #176]	@ (80095c0 <HAL_DMA_IRQHandler+0x3f8>)
 8009510:	4293      	cmp	r3, r2
 8009512:	d04a      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 8009514:	687b      	ldr	r3, [r7, #4]
 8009516:	681b      	ldr	r3, [r3, #0]
 8009518:	4a2a      	ldr	r2, [pc, #168]	@ (80095c4 <HAL_DMA_IRQHandler+0x3fc>)
 800951a:	4293      	cmp	r3, r2
 800951c:	d045      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 800951e:	687b      	ldr	r3, [r7, #4]
 8009520:	681b      	ldr	r3, [r3, #0]
 8009522:	4a29      	ldr	r2, [pc, #164]	@ (80095c8 <HAL_DMA_IRQHandler+0x400>)
 8009524:	4293      	cmp	r3, r2
 8009526:	d040      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 8009528:	687b      	ldr	r3, [r7, #4]
 800952a:	681b      	ldr	r3, [r3, #0]
 800952c:	4a27      	ldr	r2, [pc, #156]	@ (80095cc <HAL_DMA_IRQHandler+0x404>)
 800952e:	4293      	cmp	r3, r2
 8009530:	d03b      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 8009532:	687b      	ldr	r3, [r7, #4]
 8009534:	681b      	ldr	r3, [r3, #0]
 8009536:	4a26      	ldr	r2, [pc, #152]	@ (80095d0 <HAL_DMA_IRQHandler+0x408>)
 8009538:	4293      	cmp	r3, r2
 800953a:	d036      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 800953c:	687b      	ldr	r3, [r7, #4]
 800953e:	681b      	ldr	r3, [r3, #0]
 8009540:	4a24      	ldr	r2, [pc, #144]	@ (80095d4 <HAL_DMA_IRQHandler+0x40c>)
 8009542:	4293      	cmp	r3, r2
 8009544:	d031      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 8009546:	687b      	ldr	r3, [r7, #4]
 8009548:	681b      	ldr	r3, [r3, #0]
 800954a:	4a23      	ldr	r2, [pc, #140]	@ (80095d8 <HAL_DMA_IRQHandler+0x410>)
 800954c:	4293      	cmp	r3, r2
 800954e:	d02c      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 8009550:	687b      	ldr	r3, [r7, #4]
 8009552:	681b      	ldr	r3, [r3, #0]
 8009554:	4a21      	ldr	r2, [pc, #132]	@ (80095dc <HAL_DMA_IRQHandler+0x414>)
 8009556:	4293      	cmp	r3, r2
 8009558:	d027      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 800955a:	687b      	ldr	r3, [r7, #4]
 800955c:	681b      	ldr	r3, [r3, #0]
 800955e:	4a20      	ldr	r2, [pc, #128]	@ (80095e0 <HAL_DMA_IRQHandler+0x418>)
 8009560:	4293      	cmp	r3, r2
 8009562:	d022      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 8009564:	687b      	ldr	r3, [r7, #4]
 8009566:	681b      	ldr	r3, [r3, #0]
 8009568:	4a1e      	ldr	r2, [pc, #120]	@ (80095e4 <HAL_DMA_IRQHandler+0x41c>)
 800956a:	4293      	cmp	r3, r2
 800956c:	d01d      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 800956e:	687b      	ldr	r3, [r7, #4]
 8009570:	681b      	ldr	r3, [r3, #0]
 8009572:	4a1d      	ldr	r2, [pc, #116]	@ (80095e8 <HAL_DMA_IRQHandler+0x420>)
 8009574:	4293      	cmp	r3, r2
 8009576:	d018      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 8009578:	687b      	ldr	r3, [r7, #4]
 800957a:	681b      	ldr	r3, [r3, #0]
 800957c:	4a1b      	ldr	r2, [pc, #108]	@ (80095ec <HAL_DMA_IRQHandler+0x424>)
 800957e:	4293      	cmp	r3, r2
 8009580:	d013      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 8009582:	687b      	ldr	r3, [r7, #4]
 8009584:	681b      	ldr	r3, [r3, #0]
 8009586:	4a1a      	ldr	r2, [pc, #104]	@ (80095f0 <HAL_DMA_IRQHandler+0x428>)
 8009588:	4293      	cmp	r3, r2
 800958a:	d00e      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 800958c:	687b      	ldr	r3, [r7, #4]
 800958e:	681b      	ldr	r3, [r3, #0]
 8009590:	4a18      	ldr	r2, [pc, #96]	@ (80095f4 <HAL_DMA_IRQHandler+0x42c>)
 8009592:	4293      	cmp	r3, r2
 8009594:	d009      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 8009596:	687b      	ldr	r3, [r7, #4]
 8009598:	681b      	ldr	r3, [r3, #0]
 800959a:	4a17      	ldr	r2, [pc, #92]	@ (80095f8 <HAL_DMA_IRQHandler+0x430>)
 800959c:	4293      	cmp	r3, r2
 800959e:	d004      	beq.n	80095aa <HAL_DMA_IRQHandler+0x3e2>
 80095a0:	687b      	ldr	r3, [r7, #4]
 80095a2:	681b      	ldr	r3, [r3, #0]
 80095a4:	4a15      	ldr	r2, [pc, #84]	@ (80095fc <HAL_DMA_IRQHandler+0x434>)
 80095a6:	4293      	cmp	r3, r2
 80095a8:	d12a      	bne.n	8009600 <HAL_DMA_IRQHandler+0x438>
 80095aa:	687b      	ldr	r3, [r7, #4]
 80095ac:	681b      	ldr	r3, [r3, #0]
 80095ae:	681b      	ldr	r3, [r3, #0]
 80095b0:	f003 0302 	and.w	r3, r3, #2
 80095b4:	2b00      	cmp	r3, #0
 80095b6:	bf14      	ite	ne
 80095b8:	2301      	movne	r3, #1
 80095ba:	2300      	moveq	r3, #0
 80095bc:	b2db      	uxtb	r3, r3
 80095be:	e023      	b.n	8009608 <HAL_DMA_IRQHandler+0x440>
 80095c0:	40020010 	.word	0x40020010
 80095c4:	40020028 	.word	0x40020028
 80095c8:	40020040 	.word	0x40020040
 80095cc:	40020058 	.word	0x40020058
 80095d0:	40020070 	.word	0x40020070
 80095d4:	40020088 	.word	0x40020088
 80095d8:	400200a0 	.word	0x400200a0
 80095dc:	400200b8 	.word	0x400200b8
 80095e0:	40020410 	.word	0x40020410
 80095e4:	40020428 	.word	0x40020428
 80095e8:	40020440 	.word	0x40020440
 80095ec:	40020458 	.word	0x40020458
 80095f0:	40020470 	.word	0x40020470
 80095f4:	40020488 	.word	0x40020488
 80095f8:	400204a0 	.word	0x400204a0
 80095fc:	400204b8 	.word	0x400204b8
 8009600:	687b      	ldr	r3, [r7, #4]
 8009602:	681b      	ldr	r3, [r3, #0]
 8009604:	681b      	ldr	r3, [r3, #0]
 8009606:	2300      	movs	r3, #0
 8009608:	2b00      	cmp	r3, #0
 800960a:	d00d      	beq.n	8009628 <HAL_DMA_IRQHandler+0x460>
      {
        /* Clear the direct mode error flag */
        regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
 800960c:	687b      	ldr	r3, [r7, #4]
 800960e:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8009610:	f003 031f 	and.w	r3, r3, #31
 8009614:	2204      	movs	r2, #4
 8009616:	409a      	lsls	r2, r3
 8009618:	6a3b      	ldr	r3, [r7, #32]
 800961a:	609a      	str	r2, [r3, #8]

        /* Update error code */
        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
 800961c:	687b      	ldr	r3, [r7, #4]
 800961e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8009620:	f043 0204 	orr.w	r2, r3, #4
 8009624:	687b      	ldr	r3, [r7, #4]
 8009626:	655a      	str	r2, [r3, #84]	@ 0x54
      }
    }
    /* Half Transfer Complete Interrupt management ******************************/
    if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
 8009628:	687b      	ldr	r3, [r7, #4]
 800962a:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800962c:	f003 031f 	and.w	r3, r3, #31
 8009630:	2210      	movs	r2, #16
 8009632:	409a      	lsls	r2, r3
 8009634:	69bb      	ldr	r3, [r7, #24]
 8009636:	4013      	ands	r3, r2
 8009638:	2b00      	cmp	r3, #0
 800963a:	f000 80a6 	beq.w	800978a <HAL_DMA_IRQHandler+0x5c2>
    {
      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
 800963e:	687b      	ldr	r3, [r7, #4]
 8009640:	681b      	ldr	r3, [r3, #0]
 8009642:	4a85      	ldr	r2, [pc, #532]	@ (8009858 <HAL_DMA_IRQHandler+0x690>)
 8009644:	4293      	cmp	r3, r2
 8009646:	d04a      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 8009648:	687b      	ldr	r3, [r7, #4]
 800964a:	681b      	ldr	r3, [r3, #0]
 800964c:	4a83      	ldr	r2, [pc, #524]	@ (800985c <HAL_DMA_IRQHandler+0x694>)
 800964e:	4293      	cmp	r3, r2
 8009650:	d045      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 8009652:	687b      	ldr	r3, [r7, #4]
 8009654:	681b      	ldr	r3, [r3, #0]
 8009656:	4a82      	ldr	r2, [pc, #520]	@ (8009860 <HAL_DMA_IRQHandler+0x698>)
 8009658:	4293      	cmp	r3, r2
 800965a:	d040      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 800965c:	687b      	ldr	r3, [r7, #4]
 800965e:	681b      	ldr	r3, [r3, #0]
 8009660:	4a80      	ldr	r2, [pc, #512]	@ (8009864 <HAL_DMA_IRQHandler+0x69c>)
 8009662:	4293      	cmp	r3, r2
 8009664:	d03b      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 8009666:	687b      	ldr	r3, [r7, #4]
 8009668:	681b      	ldr	r3, [r3, #0]
 800966a:	4a7f      	ldr	r2, [pc, #508]	@ (8009868 <HAL_DMA_IRQHandler+0x6a0>)
 800966c:	4293      	cmp	r3, r2
 800966e:	d036      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 8009670:	687b      	ldr	r3, [r7, #4]
 8009672:	681b      	ldr	r3, [r3, #0]
 8009674:	4a7d      	ldr	r2, [pc, #500]	@ (800986c <HAL_DMA_IRQHandler+0x6a4>)
 8009676:	4293      	cmp	r3, r2
 8009678:	d031      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 800967a:	687b      	ldr	r3, [r7, #4]
 800967c:	681b      	ldr	r3, [r3, #0]
 800967e:	4a7c      	ldr	r2, [pc, #496]	@ (8009870 <HAL_DMA_IRQHandler+0x6a8>)
 8009680:	4293      	cmp	r3, r2
 8009682:	d02c      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 8009684:	687b      	ldr	r3, [r7, #4]
 8009686:	681b      	ldr	r3, [r3, #0]
 8009688:	4a7a      	ldr	r2, [pc, #488]	@ (8009874 <HAL_DMA_IRQHandler+0x6ac>)
 800968a:	4293      	cmp	r3, r2
 800968c:	d027      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 800968e:	687b      	ldr	r3, [r7, #4]
 8009690:	681b      	ldr	r3, [r3, #0]
 8009692:	4a79      	ldr	r2, [pc, #484]	@ (8009878 <HAL_DMA_IRQHandler+0x6b0>)
 8009694:	4293      	cmp	r3, r2
 8009696:	d022      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 8009698:	687b      	ldr	r3, [r7, #4]
 800969a:	681b      	ldr	r3, [r3, #0]
 800969c:	4a77      	ldr	r2, [pc, #476]	@ (800987c <HAL_DMA_IRQHandler+0x6b4>)
 800969e:	4293      	cmp	r3, r2
 80096a0:	d01d      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 80096a2:	687b      	ldr	r3, [r7, #4]
 80096a4:	681b      	ldr	r3, [r3, #0]
 80096a6:	4a76      	ldr	r2, [pc, #472]	@ (8009880 <HAL_DMA_IRQHandler+0x6b8>)
 80096a8:	4293      	cmp	r3, r2
 80096aa:	d018      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 80096ac:	687b      	ldr	r3, [r7, #4]
 80096ae:	681b      	ldr	r3, [r3, #0]
 80096b0:	4a74      	ldr	r2, [pc, #464]	@ (8009884 <HAL_DMA_IRQHandler+0x6bc>)
 80096b2:	4293      	cmp	r3, r2
 80096b4:	d013      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 80096b6:	687b      	ldr	r3, [r7, #4]
 80096b8:	681b      	ldr	r3, [r3, #0]
 80096ba:	4a73      	ldr	r2, [pc, #460]	@ (8009888 <HAL_DMA_IRQHandler+0x6c0>)
 80096bc:	4293      	cmp	r3, r2
 80096be:	d00e      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 80096c0:	687b      	ldr	r3, [r7, #4]
 80096c2:	681b      	ldr	r3, [r3, #0]
 80096c4:	4a71      	ldr	r2, [pc, #452]	@ (800988c <HAL_DMA_IRQHandler+0x6c4>)
 80096c6:	4293      	cmp	r3, r2
 80096c8:	d009      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 80096ca:	687b      	ldr	r3, [r7, #4]
 80096cc:	681b      	ldr	r3, [r3, #0]
 80096ce:	4a70      	ldr	r2, [pc, #448]	@ (8009890 <HAL_DMA_IRQHandler+0x6c8>)
 80096d0:	4293      	cmp	r3, r2
 80096d2:	d004      	beq.n	80096de <HAL_DMA_IRQHandler+0x516>
 80096d4:	687b      	ldr	r3, [r7, #4]
 80096d6:	681b      	ldr	r3, [r3, #0]
 80096d8:	4a6e      	ldr	r2, [pc, #440]	@ (8009894 <HAL_DMA_IRQHandler+0x6cc>)
 80096da:	4293      	cmp	r3, r2
 80096dc:	d10a      	bne.n	80096f4 <HAL_DMA_IRQHandler+0x52c>
 80096de:	687b      	ldr	r3, [r7, #4]
 80096e0:	681b      	ldr	r3, [r3, #0]
 80096e2:	681b      	ldr	r3, [r3, #0]
 80096e4:	f003 0308 	and.w	r3, r3, #8
 80096e8:	2b00      	cmp	r3, #0
 80096ea:	bf14      	ite	ne
 80096ec:	2301      	movne	r3, #1
 80096ee:	2300      	moveq	r3, #0
 80096f0:	b2db      	uxtb	r3, r3
 80096f2:	e009      	b.n	8009708 <HAL_DMA_IRQHandler+0x540>
 80096f4:	687b      	ldr	r3, [r7, #4]
 80096f6:	681b      	ldr	r3, [r3, #0]
 80096f8:	681b      	ldr	r3, [r3, #0]
 80096fa:	f003 0304 	and.w	r3, r3, #4
 80096fe:	2b00      	cmp	r3, #0
 8009700:	bf14      	ite	ne
 8009702:	2301      	movne	r3, #1
 8009704:	2300      	moveq	r3, #0
 8009706:	b2db      	uxtb	r3, r3
 8009708:	2b00      	cmp	r3, #0
 800970a:	d03e      	beq.n	800978a <HAL_DMA_IRQHandler+0x5c2>
      {
        /* Clear the half transfer complete flag */
        regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
 800970c:	687b      	ldr	r3, [r7, #4]
 800970e:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8009710:	f003 031f 	and.w	r3, r3, #31
 8009714:	2210      	movs	r2, #16
 8009716:	409a      	lsls	r2, r3
 8009718:	6a3b      	ldr	r3, [r7, #32]
 800971a:	609a      	str	r2, [r3, #8]

        /* Multi_Buffering mode enabled */
        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
 800971c:	687b      	ldr	r3, [r7, #4]
 800971e:	681b      	ldr	r3, [r3, #0]
 8009720:	681b      	ldr	r3, [r3, #0]
 8009722:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 8009726:	2b00      	cmp	r3, #0
 8009728:	d018      	beq.n	800975c <HAL_DMA_IRQHandler+0x594>
        {
          /* Current memory buffer used is Memory 0 */
          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
 800972a:	687b      	ldr	r3, [r7, #4]
 800972c:	681b      	ldr	r3, [r3, #0]
 800972e:	681b      	ldr	r3, [r3, #0]
 8009730:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
 8009734:	2b00      	cmp	r3, #0
 8009736:	d108      	bne.n	800974a <HAL_DMA_IRQHandler+0x582>
          {
            if(hdma->XferHalfCpltCallback != NULL)
 8009738:	687b      	ldr	r3, [r7, #4]
 800973a:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800973c:	2b00      	cmp	r3, #0
 800973e:	d024      	beq.n	800978a <HAL_DMA_IRQHandler+0x5c2>
            {
              /* Half transfer callback */
              hdma->XferHalfCpltCallback(hdma);
 8009740:	687b      	ldr	r3, [r7, #4]
 8009742:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8009744:	6878      	ldr	r0, [r7, #4]
 8009746:	4798      	blx	r3
 8009748:	e01f      	b.n	800978a <HAL_DMA_IRQHandler+0x5c2>
            }
          }
          /* Current memory buffer used is Memory 1 */
          else
          {
            if(hdma->XferM1HalfCpltCallback != NULL)
 800974a:	687b      	ldr	r3, [r7, #4]
 800974c:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 800974e:	2b00      	cmp	r3, #0
 8009750:	d01b      	beq.n	800978a <HAL_DMA_IRQHandler+0x5c2>
            {
              /* Half transfer callback */
              hdma->XferM1HalfCpltCallback(hdma);
 8009752:	687b      	ldr	r3, [r7, #4]
 8009754:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8009756:	6878      	ldr	r0, [r7, #4]
 8009758:	4798      	blx	r3
 800975a:	e016      	b.n	800978a <HAL_DMA_IRQHandler+0x5c2>
          }
        }
        else
        {
          /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
 800975c:	687b      	ldr	r3, [r7, #4]
 800975e:	681b      	ldr	r3, [r3, #0]
 8009760:	681b      	ldr	r3, [r3, #0]
 8009762:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8009766:	2b00      	cmp	r3, #0
 8009768:	d107      	bne.n	800977a <HAL_DMA_IRQHandler+0x5b2>
          {
            /* Disable the half transfer interrupt */
            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
 800976a:	687b      	ldr	r3, [r7, #4]
 800976c:	681b      	ldr	r3, [r3, #0]
 800976e:	681a      	ldr	r2, [r3, #0]
 8009770:	687b      	ldr	r3, [r7, #4]
 8009772:	681b      	ldr	r3, [r3, #0]
 8009774:	f022 0208 	bic.w	r2, r2, #8
 8009778:	601a      	str	r2, [r3, #0]
          }

          if(hdma->XferHalfCpltCallback != NULL)
 800977a:	687b      	ldr	r3, [r7, #4]
 800977c:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800977e:	2b00      	cmp	r3, #0
 8009780:	d003      	beq.n	800978a <HAL_DMA_IRQHandler+0x5c2>
          {
            /* Half transfer callback */
            hdma->XferHalfCpltCallback(hdma);
 8009782:	687b      	ldr	r3, [r7, #4]
 8009784:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8009786:	6878      	ldr	r0, [r7, #4]
 8009788:	4798      	blx	r3
          }
        }
      }
    }
    /* Transfer Complete Interrupt management ***********************************/
    if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
 800978a:	687b      	ldr	r3, [r7, #4]
 800978c:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800978e:	f003 031f 	and.w	r3, r3, #31
 8009792:	2220      	movs	r2, #32
 8009794:	409a      	lsls	r2, r3
 8009796:	69bb      	ldr	r3, [r7, #24]
 8009798:	4013      	ands	r3, r2
 800979a:	2b00      	cmp	r3, #0
 800979c:	f000 8110 	beq.w	80099c0 <HAL_DMA_IRQHandler+0x7f8>
    {
      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
 80097a0:	687b      	ldr	r3, [r7, #4]
 80097a2:	681b      	ldr	r3, [r3, #0]
 80097a4:	4a2c      	ldr	r2, [pc, #176]	@ (8009858 <HAL_DMA_IRQHandler+0x690>)
 80097a6:	4293      	cmp	r3, r2
 80097a8:	d04a      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 80097aa:	687b      	ldr	r3, [r7, #4]
 80097ac:	681b      	ldr	r3, [r3, #0]
 80097ae:	4a2b      	ldr	r2, [pc, #172]	@ (800985c <HAL_DMA_IRQHandler+0x694>)
 80097b0:	4293      	cmp	r3, r2
 80097b2:	d045      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 80097b4:	687b      	ldr	r3, [r7, #4]
 80097b6:	681b      	ldr	r3, [r3, #0]
 80097b8:	4a29      	ldr	r2, [pc, #164]	@ (8009860 <HAL_DMA_IRQHandler+0x698>)
 80097ba:	4293      	cmp	r3, r2
 80097bc:	d040      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 80097be:	687b      	ldr	r3, [r7, #4]
 80097c0:	681b      	ldr	r3, [r3, #0]
 80097c2:	4a28      	ldr	r2, [pc, #160]	@ (8009864 <HAL_DMA_IRQHandler+0x69c>)
 80097c4:	4293      	cmp	r3, r2
 80097c6:	d03b      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 80097c8:	687b      	ldr	r3, [r7, #4]
 80097ca:	681b      	ldr	r3, [r3, #0]
 80097cc:	4a26      	ldr	r2, [pc, #152]	@ (8009868 <HAL_DMA_IRQHandler+0x6a0>)
 80097ce:	4293      	cmp	r3, r2
 80097d0:	d036      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 80097d2:	687b      	ldr	r3, [r7, #4]
 80097d4:	681b      	ldr	r3, [r3, #0]
 80097d6:	4a25      	ldr	r2, [pc, #148]	@ (800986c <HAL_DMA_IRQHandler+0x6a4>)
 80097d8:	4293      	cmp	r3, r2
 80097da:	d031      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 80097dc:	687b      	ldr	r3, [r7, #4]
 80097de:	681b      	ldr	r3, [r3, #0]
 80097e0:	4a23      	ldr	r2, [pc, #140]	@ (8009870 <HAL_DMA_IRQHandler+0x6a8>)
 80097e2:	4293      	cmp	r3, r2
 80097e4:	d02c      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 80097e6:	687b      	ldr	r3, [r7, #4]
 80097e8:	681b      	ldr	r3, [r3, #0]
 80097ea:	4a22      	ldr	r2, [pc, #136]	@ (8009874 <HAL_DMA_IRQHandler+0x6ac>)
 80097ec:	4293      	cmp	r3, r2
 80097ee:	d027      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 80097f0:	687b      	ldr	r3, [r7, #4]
 80097f2:	681b      	ldr	r3, [r3, #0]
 80097f4:	4a20      	ldr	r2, [pc, #128]	@ (8009878 <HAL_DMA_IRQHandler+0x6b0>)
 80097f6:	4293      	cmp	r3, r2
 80097f8:	d022      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 80097fa:	687b      	ldr	r3, [r7, #4]
 80097fc:	681b      	ldr	r3, [r3, #0]
 80097fe:	4a1f      	ldr	r2, [pc, #124]	@ (800987c <HAL_DMA_IRQHandler+0x6b4>)
 8009800:	4293      	cmp	r3, r2
 8009802:	d01d      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 8009804:	687b      	ldr	r3, [r7, #4]
 8009806:	681b      	ldr	r3, [r3, #0]
 8009808:	4a1d      	ldr	r2, [pc, #116]	@ (8009880 <HAL_DMA_IRQHandler+0x6b8>)
 800980a:	4293      	cmp	r3, r2
 800980c:	d018      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 800980e:	687b      	ldr	r3, [r7, #4]
 8009810:	681b      	ldr	r3, [r3, #0]
 8009812:	4a1c      	ldr	r2, [pc, #112]	@ (8009884 <HAL_DMA_IRQHandler+0x6bc>)
 8009814:	4293      	cmp	r3, r2
 8009816:	d013      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 8009818:	687b      	ldr	r3, [r7, #4]
 800981a:	681b      	ldr	r3, [r3, #0]
 800981c:	4a1a      	ldr	r2, [pc, #104]	@ (8009888 <HAL_DMA_IRQHandler+0x6c0>)
 800981e:	4293      	cmp	r3, r2
 8009820:	d00e      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 8009822:	687b      	ldr	r3, [r7, #4]
 8009824:	681b      	ldr	r3, [r3, #0]
 8009826:	4a19      	ldr	r2, [pc, #100]	@ (800988c <HAL_DMA_IRQHandler+0x6c4>)
 8009828:	4293      	cmp	r3, r2
 800982a:	d009      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 800982c:	687b      	ldr	r3, [r7, #4]
 800982e:	681b      	ldr	r3, [r3, #0]
 8009830:	4a17      	ldr	r2, [pc, #92]	@ (8009890 <HAL_DMA_IRQHandler+0x6c8>)
 8009832:	4293      	cmp	r3, r2
 8009834:	d004      	beq.n	8009840 <HAL_DMA_IRQHandler+0x678>
 8009836:	687b      	ldr	r3, [r7, #4]
 8009838:	681b      	ldr	r3, [r3, #0]
 800983a:	4a16      	ldr	r2, [pc, #88]	@ (8009894 <HAL_DMA_IRQHandler+0x6cc>)
 800983c:	4293      	cmp	r3, r2
 800983e:	d12b      	bne.n	8009898 <HAL_DMA_IRQHandler+0x6d0>
 8009840:	687b      	ldr	r3, [r7, #4]
 8009842:	681b      	ldr	r3, [r3, #0]
 8009844:	681b      	ldr	r3, [r3, #0]
 8009846:	f003 0310 	and.w	r3, r3, #16
 800984a:	2b00      	cmp	r3, #0
 800984c:	bf14      	ite	ne
 800984e:	2301      	movne	r3, #1
 8009850:	2300      	moveq	r3, #0
 8009852:	b2db      	uxtb	r3, r3
 8009854:	e02a      	b.n	80098ac <HAL_DMA_IRQHandler+0x6e4>
 8009856:	bf00      	nop
 8009858:	40020010 	.word	0x40020010
 800985c:	40020028 	.word	0x40020028
 8009860:	40020040 	.word	0x40020040
 8009864:	40020058 	.word	0x40020058
 8009868:	40020070 	.word	0x40020070
 800986c:	40020088 	.word	0x40020088
 8009870:	400200a0 	.word	0x400200a0
 8009874:	400200b8 	.word	0x400200b8
 8009878:	40020410 	.word	0x40020410
 800987c:	40020428 	.word	0x40020428
 8009880:	40020440 	.word	0x40020440
 8009884:	40020458 	.word	0x40020458
 8009888:	40020470 	.word	0x40020470
 800988c:	40020488 	.word	0x40020488
 8009890:	400204a0 	.word	0x400204a0
 8009894:	400204b8 	.word	0x400204b8
 8009898:	687b      	ldr	r3, [r7, #4]
 800989a:	681b      	ldr	r3, [r3, #0]
 800989c:	681b      	ldr	r3, [r3, #0]
 800989e:	f003 0302 	and.w	r3, r3, #2
 80098a2:	2b00      	cmp	r3, #0
 80098a4:	bf14      	ite	ne
 80098a6:	2301      	movne	r3, #1
 80098a8:	2300      	moveq	r3, #0
 80098aa:	b2db      	uxtb	r3, r3
 80098ac:	2b00      	cmp	r3, #0
 80098ae:	f000 8087 	beq.w	80099c0 <HAL_DMA_IRQHandler+0x7f8>
      {
        /* Clear the transfer complete flag */
        regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
 80098b2:	687b      	ldr	r3, [r7, #4]
 80098b4:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80098b6:	f003 031f 	and.w	r3, r3, #31
 80098ba:	2220      	movs	r2, #32
 80098bc:	409a      	lsls	r2, r3
 80098be:	6a3b      	ldr	r3, [r7, #32]
 80098c0:	609a      	str	r2, [r3, #8]

        if(HAL_DMA_STATE_ABORT == hdma->State)
 80098c2:	687b      	ldr	r3, [r7, #4]
 80098c4:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
 80098c8:	b2db      	uxtb	r3, r3
 80098ca:	2b04      	cmp	r3, #4
 80098cc:	d139      	bne.n	8009942 <HAL_DMA_IRQHandler+0x77a>
        {
          /* Disable all the transfer interrupts */
          ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
 80098ce:	687b      	ldr	r3, [r7, #4]
 80098d0:	681b      	ldr	r3, [r3, #0]
 80098d2:	681a      	ldr	r2, [r3, #0]
 80098d4:	687b      	ldr	r3, [r7, #4]
 80098d6:	681b      	ldr	r3, [r3, #0]
 80098d8:	f022 0216 	bic.w	r2, r2, #22
 80098dc:	601a      	str	r2, [r3, #0]
          ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
 80098de:	687b      	ldr	r3, [r7, #4]
 80098e0:	681b      	ldr	r3, [r3, #0]
 80098e2:	695a      	ldr	r2, [r3, #20]
 80098e4:	687b      	ldr	r3, [r7, #4]
 80098e6:	681b      	ldr	r3, [r3, #0]
 80098e8:	f022 0280 	bic.w	r2, r2, #128	@ 0x80
 80098ec:	615a      	str	r2, [r3, #20]

          if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
 80098ee:	687b      	ldr	r3, [r7, #4]
 80098f0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80098f2:	2b00      	cmp	r3, #0
 80098f4:	d103      	bne.n	80098fe <HAL_DMA_IRQHandler+0x736>
 80098f6:	687b      	ldr	r3, [r7, #4]
 80098f8:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 80098fa:	2b00      	cmp	r3, #0
 80098fc:	d007      	beq.n	800990e <HAL_DMA_IRQHandler+0x746>
          {
            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
 80098fe:	687b      	ldr	r3, [r7, #4]
 8009900:	681b      	ldr	r3, [r3, #0]
 8009902:	681a      	ldr	r2, [r3, #0]
 8009904:	687b      	ldr	r3, [r7, #4]
 8009906:	681b      	ldr	r3, [r3, #0]
 8009908:	f022 0208 	bic.w	r2, r2, #8
 800990c:	601a      	str	r2, [r3, #0]
          }

          /* Clear all interrupt flags at correct offset within the register */
          regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
 800990e:	687b      	ldr	r3, [r7, #4]
 8009910:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8009912:	f003 031f 	and.w	r3, r3, #31
 8009916:	223f      	movs	r2, #63	@ 0x3f
 8009918:	409a      	lsls	r2, r3
 800991a:	6a3b      	ldr	r3, [r7, #32]
 800991c:	609a      	str	r2, [r3, #8]

          /* Change the DMA state */
          hdma->State = HAL_DMA_STATE_READY;
 800991e:	687b      	ldr	r3, [r7, #4]
 8009920:	2201      	movs	r2, #1
 8009922:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

          /* Process Unlocked */
          __HAL_UNLOCK(hdma);
 8009926:	687b      	ldr	r3, [r7, #4]
 8009928:	2200      	movs	r2, #0
 800992a:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

          if(hdma->XferAbortCallback != NULL)
 800992e:	687b      	ldr	r3, [r7, #4]
 8009930:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8009932:	2b00      	cmp	r3, #0
 8009934:	f000 834a 	beq.w	8009fcc <HAL_DMA_IRQHandler+0xe04>
          {
            hdma->XferAbortCallback(hdma);
 8009938:	687b      	ldr	r3, [r7, #4]
 800993a:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800993c:	6878      	ldr	r0, [r7, #4]
 800993e:	4798      	blx	r3
          }
          return;
 8009940:	e344      	b.n	8009fcc <HAL_DMA_IRQHandler+0xe04>
        }

        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
 8009942:	687b      	ldr	r3, [r7, #4]
 8009944:	681b      	ldr	r3, [r3, #0]
 8009946:	681b      	ldr	r3, [r3, #0]
 8009948:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 800994c:	2b00      	cmp	r3, #0
 800994e:	d018      	beq.n	8009982 <HAL_DMA_IRQHandler+0x7ba>
        {
          /* Current memory buffer used is Memory 0 */
          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
 8009950:	687b      	ldr	r3, [r7, #4]
 8009952:	681b      	ldr	r3, [r3, #0]
 8009954:	681b      	ldr	r3, [r3, #0]
 8009956:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
 800995a:	2b00      	cmp	r3, #0
 800995c:	d108      	bne.n	8009970 <HAL_DMA_IRQHandler+0x7a8>
          {
            if(hdma->XferM1CpltCallback != NULL)
 800995e:	687b      	ldr	r3, [r7, #4]
 8009960:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 8009962:	2b00      	cmp	r3, #0
 8009964:	d02c      	beq.n	80099c0 <HAL_DMA_IRQHandler+0x7f8>
            {
              /* Transfer complete Callback for memory1 */
              hdma->XferM1CpltCallback(hdma);
 8009966:	687b      	ldr	r3, [r7, #4]
 8009968:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 800996a:	6878      	ldr	r0, [r7, #4]
 800996c:	4798      	blx	r3
 800996e:	e027      	b.n	80099c0 <HAL_DMA_IRQHandler+0x7f8>
            }
          }
          /* Current memory buffer used is Memory 1 */
          else
          {
            if(hdma->XferCpltCallback != NULL)
 8009970:	687b      	ldr	r3, [r7, #4]
 8009972:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8009974:	2b00      	cmp	r3, #0
 8009976:	d023      	beq.n	80099c0 <HAL_DMA_IRQHandler+0x7f8>
            {
              /* Transfer complete Callback for memory0 */
              hdma->XferCpltCallback(hdma);
 8009978:	687b      	ldr	r3, [r7, #4]
 800997a:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 800997c:	6878      	ldr	r0, [r7, #4]
 800997e:	4798      	blx	r3
 8009980:	e01e      	b.n	80099c0 <HAL_DMA_IRQHandler+0x7f8>
          }
        }
        /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
        else
        {
          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
 8009982:	687b      	ldr	r3, [r7, #4]
 8009984:	681b      	ldr	r3, [r3, #0]
 8009986:	681b      	ldr	r3, [r3, #0]
 8009988:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800998c:	2b00      	cmp	r3, #0
 800998e:	d10f      	bne.n	80099b0 <HAL_DMA_IRQHandler+0x7e8>
          {
            /* Disable the transfer complete interrupt */
            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
 8009990:	687b      	ldr	r3, [r7, #4]
 8009992:	681b      	ldr	r3, [r3, #0]
 8009994:	681a      	ldr	r2, [r3, #0]
 8009996:	687b      	ldr	r3, [r7, #4]
 8009998:	681b      	ldr	r3, [r3, #0]
 800999a:	f022 0210 	bic.w	r2, r2, #16
 800999e:	601a      	str	r2, [r3, #0]

            /* Change the DMA state */
            hdma->State = HAL_DMA_STATE_READY;
 80099a0:	687b      	ldr	r3, [r7, #4]
 80099a2:	2201      	movs	r2, #1
 80099a4:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

            /* Process Unlocked */
            __HAL_UNLOCK(hdma);
 80099a8:	687b      	ldr	r3, [r7, #4]
 80099aa:	2200      	movs	r2, #0
 80099ac:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
          }

          if(hdma->XferCpltCallback != NULL)
 80099b0:	687b      	ldr	r3, [r7, #4]
 80099b2:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80099b4:	2b00      	cmp	r3, #0
 80099b6:	d003      	beq.n	80099c0 <HAL_DMA_IRQHandler+0x7f8>
          {
            /* Transfer complete callback */
            hdma->XferCpltCallback(hdma);
 80099b8:	687b      	ldr	r3, [r7, #4]
 80099ba:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80099bc:	6878      	ldr	r0, [r7, #4]
 80099be:	4798      	blx	r3
        }
      }
    }

    /* manage error case */
    if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
 80099c0:	687b      	ldr	r3, [r7, #4]
 80099c2:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80099c4:	2b00      	cmp	r3, #0
 80099c6:	f000 8306 	beq.w	8009fd6 <HAL_DMA_IRQHandler+0xe0e>
    {
      if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)
 80099ca:	687b      	ldr	r3, [r7, #4]
 80099cc:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80099ce:	f003 0301 	and.w	r3, r3, #1
 80099d2:	2b00      	cmp	r3, #0
 80099d4:	f000 8088 	beq.w	8009ae8 <HAL_DMA_IRQHandler+0x920>
      {
        hdma->State = HAL_DMA_STATE_ABORT;
 80099d8:	687b      	ldr	r3, [r7, #4]
 80099da:	2204      	movs	r2, #4
 80099dc:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

        /* Disable the stream */
        __HAL_DMA_DISABLE(hdma);
 80099e0:	687b      	ldr	r3, [r7, #4]
 80099e2:	681b      	ldr	r3, [r3, #0]
 80099e4:	4a7a      	ldr	r2, [pc, #488]	@ (8009bd0 <HAL_DMA_IRQHandler+0xa08>)
 80099e6:	4293      	cmp	r3, r2
 80099e8:	d04a      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 80099ea:	687b      	ldr	r3, [r7, #4]
 80099ec:	681b      	ldr	r3, [r3, #0]
 80099ee:	4a79      	ldr	r2, [pc, #484]	@ (8009bd4 <HAL_DMA_IRQHandler+0xa0c>)
 80099f0:	4293      	cmp	r3, r2
 80099f2:	d045      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 80099f4:	687b      	ldr	r3, [r7, #4]
 80099f6:	681b      	ldr	r3, [r3, #0]
 80099f8:	4a77      	ldr	r2, [pc, #476]	@ (8009bd8 <HAL_DMA_IRQHandler+0xa10>)
 80099fa:	4293      	cmp	r3, r2
 80099fc:	d040      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 80099fe:	687b      	ldr	r3, [r7, #4]
 8009a00:	681b      	ldr	r3, [r3, #0]
 8009a02:	4a76      	ldr	r2, [pc, #472]	@ (8009bdc <HAL_DMA_IRQHandler+0xa14>)
 8009a04:	4293      	cmp	r3, r2
 8009a06:	d03b      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 8009a08:	687b      	ldr	r3, [r7, #4]
 8009a0a:	681b      	ldr	r3, [r3, #0]
 8009a0c:	4a74      	ldr	r2, [pc, #464]	@ (8009be0 <HAL_DMA_IRQHandler+0xa18>)
 8009a0e:	4293      	cmp	r3, r2
 8009a10:	d036      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 8009a12:	687b      	ldr	r3, [r7, #4]
 8009a14:	681b      	ldr	r3, [r3, #0]
 8009a16:	4a73      	ldr	r2, [pc, #460]	@ (8009be4 <HAL_DMA_IRQHandler+0xa1c>)
 8009a18:	4293      	cmp	r3, r2
 8009a1a:	d031      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 8009a1c:	687b      	ldr	r3, [r7, #4]
 8009a1e:	681b      	ldr	r3, [r3, #0]
 8009a20:	4a71      	ldr	r2, [pc, #452]	@ (8009be8 <HAL_DMA_IRQHandler+0xa20>)
 8009a22:	4293      	cmp	r3, r2
 8009a24:	d02c      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 8009a26:	687b      	ldr	r3, [r7, #4]
 8009a28:	681b      	ldr	r3, [r3, #0]
 8009a2a:	4a70      	ldr	r2, [pc, #448]	@ (8009bec <HAL_DMA_IRQHandler+0xa24>)
 8009a2c:	4293      	cmp	r3, r2
 8009a2e:	d027      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 8009a30:	687b      	ldr	r3, [r7, #4]
 8009a32:	681b      	ldr	r3, [r3, #0]
 8009a34:	4a6e      	ldr	r2, [pc, #440]	@ (8009bf0 <HAL_DMA_IRQHandler+0xa28>)
 8009a36:	4293      	cmp	r3, r2
 8009a38:	d022      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 8009a3a:	687b      	ldr	r3, [r7, #4]
 8009a3c:	681b      	ldr	r3, [r3, #0]
 8009a3e:	4a6d      	ldr	r2, [pc, #436]	@ (8009bf4 <HAL_DMA_IRQHandler+0xa2c>)
 8009a40:	4293      	cmp	r3, r2
 8009a42:	d01d      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 8009a44:	687b      	ldr	r3, [r7, #4]
 8009a46:	681b      	ldr	r3, [r3, #0]
 8009a48:	4a6b      	ldr	r2, [pc, #428]	@ (8009bf8 <HAL_DMA_IRQHandler+0xa30>)
 8009a4a:	4293      	cmp	r3, r2
 8009a4c:	d018      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 8009a4e:	687b      	ldr	r3, [r7, #4]
 8009a50:	681b      	ldr	r3, [r3, #0]
 8009a52:	4a6a      	ldr	r2, [pc, #424]	@ (8009bfc <HAL_DMA_IRQHandler+0xa34>)
 8009a54:	4293      	cmp	r3, r2
 8009a56:	d013      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 8009a58:	687b      	ldr	r3, [r7, #4]
 8009a5a:	681b      	ldr	r3, [r3, #0]
 8009a5c:	4a68      	ldr	r2, [pc, #416]	@ (8009c00 <HAL_DMA_IRQHandler+0xa38>)
 8009a5e:	4293      	cmp	r3, r2
 8009a60:	d00e      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 8009a62:	687b      	ldr	r3, [r7, #4]
 8009a64:	681b      	ldr	r3, [r3, #0]
 8009a66:	4a67      	ldr	r2, [pc, #412]	@ (8009c04 <HAL_DMA_IRQHandler+0xa3c>)
 8009a68:	4293      	cmp	r3, r2
 8009a6a:	d009      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 8009a6c:	687b      	ldr	r3, [r7, #4]
 8009a6e:	681b      	ldr	r3, [r3, #0]
 8009a70:	4a65      	ldr	r2, [pc, #404]	@ (8009c08 <HAL_DMA_IRQHandler+0xa40>)
 8009a72:	4293      	cmp	r3, r2
 8009a74:	d004      	beq.n	8009a80 <HAL_DMA_IRQHandler+0x8b8>
 8009a76:	687b      	ldr	r3, [r7, #4]
 8009a78:	681b      	ldr	r3, [r3, #0]
 8009a7a:	4a64      	ldr	r2, [pc, #400]	@ (8009c0c <HAL_DMA_IRQHandler+0xa44>)
 8009a7c:	4293      	cmp	r3, r2
 8009a7e:	d108      	bne.n	8009a92 <HAL_DMA_IRQHandler+0x8ca>
 8009a80:	687b      	ldr	r3, [r7, #4]
 8009a82:	681b      	ldr	r3, [r3, #0]
 8009a84:	681a      	ldr	r2, [r3, #0]
 8009a86:	687b      	ldr	r3, [r7, #4]
 8009a88:	681b      	ldr	r3, [r3, #0]
 8009a8a:	f022 0201 	bic.w	r2, r2, #1
 8009a8e:	601a      	str	r2, [r3, #0]
 8009a90:	e007      	b.n	8009aa2 <HAL_DMA_IRQHandler+0x8da>
 8009a92:	687b      	ldr	r3, [r7, #4]
 8009a94:	681b      	ldr	r3, [r3, #0]
 8009a96:	681a      	ldr	r2, [r3, #0]
 8009a98:	687b      	ldr	r3, [r7, #4]
 8009a9a:	681b      	ldr	r3, [r3, #0]
 8009a9c:	f022 0201 	bic.w	r2, r2, #1
 8009aa0:	601a      	str	r2, [r3, #0]

        do
        {
          if (++count > timeout)
 8009aa2:	68fb      	ldr	r3, [r7, #12]
 8009aa4:	3301      	adds	r3, #1
 8009aa6:	60fb      	str	r3, [r7, #12]
 8009aa8:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8009aaa:	429a      	cmp	r2, r3
 8009aac:	d307      	bcc.n	8009abe <HAL_DMA_IRQHandler+0x8f6>
          {
            break;
          }
        }
        while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
 8009aae:	687b      	ldr	r3, [r7, #4]
 8009ab0:	681b      	ldr	r3, [r3, #0]
 8009ab2:	681b      	ldr	r3, [r3, #0]
 8009ab4:	f003 0301 	and.w	r3, r3, #1
 8009ab8:	2b00      	cmp	r3, #0
 8009aba:	d1f2      	bne.n	8009aa2 <HAL_DMA_IRQHandler+0x8da>
 8009abc:	e000      	b.n	8009ac0 <HAL_DMA_IRQHandler+0x8f8>
            break;
 8009abe:	bf00      	nop

        if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
 8009ac0:	687b      	ldr	r3, [r7, #4]
 8009ac2:	681b      	ldr	r3, [r3, #0]
 8009ac4:	681b      	ldr	r3, [r3, #0]
 8009ac6:	f003 0301 	and.w	r3, r3, #1
 8009aca:	2b00      	cmp	r3, #0
 8009acc:	d004      	beq.n	8009ad8 <HAL_DMA_IRQHandler+0x910>
        {
          /* Change the DMA state to error if DMA disable fails */
          hdma->State = HAL_DMA_STATE_ERROR;
 8009ace:	687b      	ldr	r3, [r7, #4]
 8009ad0:	2203      	movs	r2, #3
 8009ad2:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
 8009ad6:	e003      	b.n	8009ae0 <HAL_DMA_IRQHandler+0x918>
        }
        else
        {
          /* Change the DMA state to Ready if DMA disable success */
          hdma->State = HAL_DMA_STATE_READY;
 8009ad8:	687b      	ldr	r3, [r7, #4]
 8009ada:	2201      	movs	r2, #1
 8009adc:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
        }

        /* Process Unlocked */
        __HAL_UNLOCK(hdma);
 8009ae0:	687b      	ldr	r3, [r7, #4]
 8009ae2:	2200      	movs	r2, #0
 8009ae4:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
      }

      if(hdma->XferErrorCallback != NULL)
 8009ae8:	687b      	ldr	r3, [r7, #4]
 8009aea:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8009aec:	2b00      	cmp	r3, #0
 8009aee:	f000 8272 	beq.w	8009fd6 <HAL_DMA_IRQHandler+0xe0e>
      {
        /* Transfer error callback */
        hdma->XferErrorCallback(hdma);
 8009af2:	687b      	ldr	r3, [r7, #4]
 8009af4:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8009af6:	6878      	ldr	r0, [r7, #4]
 8009af8:	4798      	blx	r3
 8009afa:	e26c      	b.n	8009fd6 <HAL_DMA_IRQHandler+0xe0e>
      }
    }
  }
  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U)  /* BDMA instance(s) */
 8009afc:	687b      	ldr	r3, [r7, #4]
 8009afe:	681b      	ldr	r3, [r3, #0]
 8009b00:	4a43      	ldr	r2, [pc, #268]	@ (8009c10 <HAL_DMA_IRQHandler+0xa48>)
 8009b02:	4293      	cmp	r3, r2
 8009b04:	d022      	beq.n	8009b4c <HAL_DMA_IRQHandler+0x984>
 8009b06:	687b      	ldr	r3, [r7, #4]
 8009b08:	681b      	ldr	r3, [r3, #0]
 8009b0a:	4a42      	ldr	r2, [pc, #264]	@ (8009c14 <HAL_DMA_IRQHandler+0xa4c>)
 8009b0c:	4293      	cmp	r3, r2
 8009b0e:	d01d      	beq.n	8009b4c <HAL_DMA_IRQHandler+0x984>
 8009b10:	687b      	ldr	r3, [r7, #4]
 8009b12:	681b      	ldr	r3, [r3, #0]
 8009b14:	4a40      	ldr	r2, [pc, #256]	@ (8009c18 <HAL_DMA_IRQHandler+0xa50>)
 8009b16:	4293      	cmp	r3, r2
 8009b18:	d018      	beq.n	8009b4c <HAL_DMA_IRQHandler+0x984>
 8009b1a:	687b      	ldr	r3, [r7, #4]
 8009b1c:	681b      	ldr	r3, [r3, #0]
 8009b1e:	4a3f      	ldr	r2, [pc, #252]	@ (8009c1c <HAL_DMA_IRQHandler+0xa54>)
 8009b20:	4293      	cmp	r3, r2
 8009b22:	d013      	beq.n	8009b4c <HAL_DMA_IRQHandler+0x984>
 8009b24:	687b      	ldr	r3, [r7, #4]
 8009b26:	681b      	ldr	r3, [r3, #0]
 8009b28:	4a3d      	ldr	r2, [pc, #244]	@ (8009c20 <HAL_DMA_IRQHandler+0xa58>)
 8009b2a:	4293      	cmp	r3, r2
 8009b2c:	d00e      	beq.n	8009b4c <HAL_DMA_IRQHandler+0x984>
 8009b2e:	687b      	ldr	r3, [r7, #4]
 8009b30:	681b      	ldr	r3, [r3, #0]
 8009b32:	4a3c      	ldr	r2, [pc, #240]	@ (8009c24 <HAL_DMA_IRQHandler+0xa5c>)
 8009b34:	4293      	cmp	r3, r2
 8009b36:	d009      	beq.n	8009b4c <HAL_DMA_IRQHandler+0x984>
 8009b38:	687b      	ldr	r3, [r7, #4]
 8009b3a:	681b      	ldr	r3, [r3, #0]
 8009b3c:	4a3a      	ldr	r2, [pc, #232]	@ (8009c28 <HAL_DMA_IRQHandler+0xa60>)
 8009b3e:	4293      	cmp	r3, r2
 8009b40:	d004      	beq.n	8009b4c <HAL_DMA_IRQHandler+0x984>
 8009b42:	687b      	ldr	r3, [r7, #4]
 8009b44:	681b      	ldr	r3, [r3, #0]
 8009b46:	4a39      	ldr	r2, [pc, #228]	@ (8009c2c <HAL_DMA_IRQHandler+0xa64>)
 8009b48:	4293      	cmp	r3, r2
 8009b4a:	d101      	bne.n	8009b50 <HAL_DMA_IRQHandler+0x988>
 8009b4c:	2301      	movs	r3, #1
 8009b4e:	e000      	b.n	8009b52 <HAL_DMA_IRQHandler+0x98a>
 8009b50:	2300      	movs	r3, #0
 8009b52:	2b00      	cmp	r3, #0
 8009b54:	f000 823f 	beq.w	8009fd6 <HAL_DMA_IRQHandler+0xe0e>
  {
    ccr_reg = (((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR);
 8009b58:	687b      	ldr	r3, [r7, #4]
 8009b5a:	681b      	ldr	r3, [r3, #0]
 8009b5c:	681b      	ldr	r3, [r3, #0]
 8009b5e:	613b      	str	r3, [r7, #16]

    /* Half Transfer Complete Interrupt management ******************************/
    if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U))
 8009b60:	687b      	ldr	r3, [r7, #4]
 8009b62:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8009b64:	f003 031f 	and.w	r3, r3, #31
 8009b68:	2204      	movs	r2, #4
 8009b6a:	409a      	lsls	r2, r3
 8009b6c:	697b      	ldr	r3, [r7, #20]
 8009b6e:	4013      	ands	r3, r2
 8009b70:	2b00      	cmp	r3, #0
 8009b72:	f000 80cd 	beq.w	8009d10 <HAL_DMA_IRQHandler+0xb48>
 8009b76:	693b      	ldr	r3, [r7, #16]
 8009b78:	f003 0304 	and.w	r3, r3, #4
 8009b7c:	2b00      	cmp	r3, #0
 8009b7e:	f000 80c7 	beq.w	8009d10 <HAL_DMA_IRQHandler+0xb48>
    {
      /* Clear the half transfer complete flag */
      regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU));
 8009b82:	687b      	ldr	r3, [r7, #4]
 8009b84:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8009b86:	f003 031f 	and.w	r3, r3, #31
 8009b8a:	2204      	movs	r2, #4
 8009b8c:	409a      	lsls	r2, r3
 8009b8e:	69fb      	ldr	r3, [r7, #28]
 8009b90:	605a      	str	r2, [r3, #4]

      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8009b92:	693b      	ldr	r3, [r7, #16]
 8009b94:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 8009b98:	2b00      	cmp	r3, #0
 8009b9a:	d049      	beq.n	8009c30 <HAL_DMA_IRQHandler+0xa68>
      {
        /* Current memory buffer used is Memory 0 */
        if((ccr_reg & BDMA_CCR_CT) == 0U)
 8009b9c:	693b      	ldr	r3, [r7, #16]
 8009b9e:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 8009ba2:	2b00      	cmp	r3, #0
 8009ba4:	d109      	bne.n	8009bba <HAL_DMA_IRQHandler+0x9f2>
        {
          if(hdma->XferM1HalfCpltCallback != NULL)
 8009ba6:	687b      	ldr	r3, [r7, #4]
 8009ba8:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8009baa:	2b00      	cmp	r3, #0
 8009bac:	f000 8210 	beq.w	8009fd0 <HAL_DMA_IRQHandler+0xe08>
          {
            /* Half transfer Callback for Memory 1 */
            hdma->XferM1HalfCpltCallback(hdma);
 8009bb0:	687b      	ldr	r3, [r7, #4]
 8009bb2:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 8009bb4:	6878      	ldr	r0, [r7, #4]
 8009bb6:	4798      	blx	r3
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8009bb8:	e20a      	b.n	8009fd0 <HAL_DMA_IRQHandler+0xe08>
          }
        }
        /* Current memory buffer used is Memory 1 */
        else
        {
          if(hdma->XferHalfCpltCallback != NULL)
 8009bba:	687b      	ldr	r3, [r7, #4]
 8009bbc:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8009bbe:	2b00      	cmp	r3, #0
 8009bc0:	f000 8206 	beq.w	8009fd0 <HAL_DMA_IRQHandler+0xe08>
          {
            /* Half transfer Callback for Memory 0 */
            hdma->XferHalfCpltCallback(hdma);
 8009bc4:	687b      	ldr	r3, [r7, #4]
 8009bc6:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8009bc8:	6878      	ldr	r0, [r7, #4]
 8009bca:	4798      	blx	r3
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8009bcc:	e200      	b.n	8009fd0 <HAL_DMA_IRQHandler+0xe08>
 8009bce:	bf00      	nop
 8009bd0:	40020010 	.word	0x40020010
 8009bd4:	40020028 	.word	0x40020028
 8009bd8:	40020040 	.word	0x40020040
 8009bdc:	40020058 	.word	0x40020058
 8009be0:	40020070 	.word	0x40020070
 8009be4:	40020088 	.word	0x40020088
 8009be8:	400200a0 	.word	0x400200a0
 8009bec:	400200b8 	.word	0x400200b8
 8009bf0:	40020410 	.word	0x40020410
 8009bf4:	40020428 	.word	0x40020428
 8009bf8:	40020440 	.word	0x40020440
 8009bfc:	40020458 	.word	0x40020458
 8009c00:	40020470 	.word	0x40020470
 8009c04:	40020488 	.word	0x40020488
 8009c08:	400204a0 	.word	0x400204a0
 8009c0c:	400204b8 	.word	0x400204b8
 8009c10:	58025408 	.word	0x58025408
 8009c14:	5802541c 	.word	0x5802541c
 8009c18:	58025430 	.word	0x58025430
 8009c1c:	58025444 	.word	0x58025444
 8009c20:	58025458 	.word	0x58025458
 8009c24:	5802546c 	.word	0x5802546c
 8009c28:	58025480 	.word	0x58025480
 8009c2c:	58025494 	.word	0x58025494
          }
        }
      }
      else
      {
        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
 8009c30:	693b      	ldr	r3, [r7, #16]
 8009c32:	f003 0320 	and.w	r3, r3, #32
 8009c36:	2b00      	cmp	r3, #0
 8009c38:	d160      	bne.n	8009cfc <HAL_DMA_IRQHandler+0xb34>
        {
          /* Disable the half transfer interrupt */
          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 8009c3a:	687b      	ldr	r3, [r7, #4]
 8009c3c:	681b      	ldr	r3, [r3, #0]
 8009c3e:	4a7f      	ldr	r2, [pc, #508]	@ (8009e3c <HAL_DMA_IRQHandler+0xc74>)
 8009c40:	4293      	cmp	r3, r2
 8009c42:	d04a      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009c44:	687b      	ldr	r3, [r7, #4]
 8009c46:	681b      	ldr	r3, [r3, #0]
 8009c48:	4a7d      	ldr	r2, [pc, #500]	@ (8009e40 <HAL_DMA_IRQHandler+0xc78>)
 8009c4a:	4293      	cmp	r3, r2
 8009c4c:	d045      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009c4e:	687b      	ldr	r3, [r7, #4]
 8009c50:	681b      	ldr	r3, [r3, #0]
 8009c52:	4a7c      	ldr	r2, [pc, #496]	@ (8009e44 <HAL_DMA_IRQHandler+0xc7c>)
 8009c54:	4293      	cmp	r3, r2
 8009c56:	d040      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009c58:	687b      	ldr	r3, [r7, #4]
 8009c5a:	681b      	ldr	r3, [r3, #0]
 8009c5c:	4a7a      	ldr	r2, [pc, #488]	@ (8009e48 <HAL_DMA_IRQHandler+0xc80>)
 8009c5e:	4293      	cmp	r3, r2
 8009c60:	d03b      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009c62:	687b      	ldr	r3, [r7, #4]
 8009c64:	681b      	ldr	r3, [r3, #0]
 8009c66:	4a79      	ldr	r2, [pc, #484]	@ (8009e4c <HAL_DMA_IRQHandler+0xc84>)
 8009c68:	4293      	cmp	r3, r2
 8009c6a:	d036      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009c6c:	687b      	ldr	r3, [r7, #4]
 8009c6e:	681b      	ldr	r3, [r3, #0]
 8009c70:	4a77      	ldr	r2, [pc, #476]	@ (8009e50 <HAL_DMA_IRQHandler+0xc88>)
 8009c72:	4293      	cmp	r3, r2
 8009c74:	d031      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009c76:	687b      	ldr	r3, [r7, #4]
 8009c78:	681b      	ldr	r3, [r3, #0]
 8009c7a:	4a76      	ldr	r2, [pc, #472]	@ (8009e54 <HAL_DMA_IRQHandler+0xc8c>)
 8009c7c:	4293      	cmp	r3, r2
 8009c7e:	d02c      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009c80:	687b      	ldr	r3, [r7, #4]
 8009c82:	681b      	ldr	r3, [r3, #0]
 8009c84:	4a74      	ldr	r2, [pc, #464]	@ (8009e58 <HAL_DMA_IRQHandler+0xc90>)
 8009c86:	4293      	cmp	r3, r2
 8009c88:	d027      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009c8a:	687b      	ldr	r3, [r7, #4]
 8009c8c:	681b      	ldr	r3, [r3, #0]
 8009c8e:	4a73      	ldr	r2, [pc, #460]	@ (8009e5c <HAL_DMA_IRQHandler+0xc94>)
 8009c90:	4293      	cmp	r3, r2
 8009c92:	d022      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009c94:	687b      	ldr	r3, [r7, #4]
 8009c96:	681b      	ldr	r3, [r3, #0]
 8009c98:	4a71      	ldr	r2, [pc, #452]	@ (8009e60 <HAL_DMA_IRQHandler+0xc98>)
 8009c9a:	4293      	cmp	r3, r2
 8009c9c:	d01d      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009c9e:	687b      	ldr	r3, [r7, #4]
 8009ca0:	681b      	ldr	r3, [r3, #0]
 8009ca2:	4a70      	ldr	r2, [pc, #448]	@ (8009e64 <HAL_DMA_IRQHandler+0xc9c>)
 8009ca4:	4293      	cmp	r3, r2
 8009ca6:	d018      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009ca8:	687b      	ldr	r3, [r7, #4]
 8009caa:	681b      	ldr	r3, [r3, #0]
 8009cac:	4a6e      	ldr	r2, [pc, #440]	@ (8009e68 <HAL_DMA_IRQHandler+0xca0>)
 8009cae:	4293      	cmp	r3, r2
 8009cb0:	d013      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009cb2:	687b      	ldr	r3, [r7, #4]
 8009cb4:	681b      	ldr	r3, [r3, #0]
 8009cb6:	4a6d      	ldr	r2, [pc, #436]	@ (8009e6c <HAL_DMA_IRQHandler+0xca4>)
 8009cb8:	4293      	cmp	r3, r2
 8009cba:	d00e      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009cbc:	687b      	ldr	r3, [r7, #4]
 8009cbe:	681b      	ldr	r3, [r3, #0]
 8009cc0:	4a6b      	ldr	r2, [pc, #428]	@ (8009e70 <HAL_DMA_IRQHandler+0xca8>)
 8009cc2:	4293      	cmp	r3, r2
 8009cc4:	d009      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009cc6:	687b      	ldr	r3, [r7, #4]
 8009cc8:	681b      	ldr	r3, [r3, #0]
 8009cca:	4a6a      	ldr	r2, [pc, #424]	@ (8009e74 <HAL_DMA_IRQHandler+0xcac>)
 8009ccc:	4293      	cmp	r3, r2
 8009cce:	d004      	beq.n	8009cda <HAL_DMA_IRQHandler+0xb12>
 8009cd0:	687b      	ldr	r3, [r7, #4]
 8009cd2:	681b      	ldr	r3, [r3, #0]
 8009cd4:	4a68      	ldr	r2, [pc, #416]	@ (8009e78 <HAL_DMA_IRQHandler+0xcb0>)
 8009cd6:	4293      	cmp	r3, r2
 8009cd8:	d108      	bne.n	8009cec <HAL_DMA_IRQHandler+0xb24>
 8009cda:	687b      	ldr	r3, [r7, #4]
 8009cdc:	681b      	ldr	r3, [r3, #0]
 8009cde:	681a      	ldr	r2, [r3, #0]
 8009ce0:	687b      	ldr	r3, [r7, #4]
 8009ce2:	681b      	ldr	r3, [r3, #0]
 8009ce4:	f022 0208 	bic.w	r2, r2, #8
 8009ce8:	601a      	str	r2, [r3, #0]
 8009cea:	e007      	b.n	8009cfc <HAL_DMA_IRQHandler+0xb34>
 8009cec:	687b      	ldr	r3, [r7, #4]
 8009cee:	681b      	ldr	r3, [r3, #0]
 8009cf0:	681a      	ldr	r2, [r3, #0]
 8009cf2:	687b      	ldr	r3, [r7, #4]
 8009cf4:	681b      	ldr	r3, [r3, #0]
 8009cf6:	f022 0204 	bic.w	r2, r2, #4
 8009cfa:	601a      	str	r2, [r3, #0]
        }

        /* DMA peripheral state is not updated in Half Transfer */
        /* but in Transfer Complete case */

       if(hdma->XferHalfCpltCallback != NULL)
 8009cfc:	687b      	ldr	r3, [r7, #4]
 8009cfe:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8009d00:	2b00      	cmp	r3, #0
 8009d02:	f000 8165 	beq.w	8009fd0 <HAL_DMA_IRQHandler+0xe08>
        {
          /* Half transfer callback */
          hdma->XferHalfCpltCallback(hdma);
 8009d06:	687b      	ldr	r3, [r7, #4]
 8009d08:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8009d0a:	6878      	ldr	r0, [r7, #4]
 8009d0c:	4798      	blx	r3
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8009d0e:	e15f      	b.n	8009fd0 <HAL_DMA_IRQHandler+0xe08>
        }
      }
    }

    /* Transfer Complete Interrupt management ***********************************/
    else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U))
 8009d10:	687b      	ldr	r3, [r7, #4]
 8009d12:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8009d14:	f003 031f 	and.w	r3, r3, #31
 8009d18:	2202      	movs	r2, #2
 8009d1a:	409a      	lsls	r2, r3
 8009d1c:	697b      	ldr	r3, [r7, #20]
 8009d1e:	4013      	ands	r3, r2
 8009d20:	2b00      	cmp	r3, #0
 8009d22:	f000 80c5 	beq.w	8009eb0 <HAL_DMA_IRQHandler+0xce8>
 8009d26:	693b      	ldr	r3, [r7, #16]
 8009d28:	f003 0302 	and.w	r3, r3, #2
 8009d2c:	2b00      	cmp	r3, #0
 8009d2e:	f000 80bf 	beq.w	8009eb0 <HAL_DMA_IRQHandler+0xce8>
    {
      /* Clear the transfer complete flag */
      regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU);
 8009d32:	687b      	ldr	r3, [r7, #4]
 8009d34:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8009d36:	f003 031f 	and.w	r3, r3, #31
 8009d3a:	2202      	movs	r2, #2
 8009d3c:	409a      	lsls	r2, r3
 8009d3e:	69fb      	ldr	r3, [r7, #28]
 8009d40:	605a      	str	r2, [r3, #4]

      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8009d42:	693b      	ldr	r3, [r7, #16]
 8009d44:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 8009d48:	2b00      	cmp	r3, #0
 8009d4a:	d018      	beq.n	8009d7e <HAL_DMA_IRQHandler+0xbb6>
      {
        /* Current memory buffer used is Memory 0 */
        if((ccr_reg & BDMA_CCR_CT) == 0U)
 8009d4c:	693b      	ldr	r3, [r7, #16]
 8009d4e:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 8009d52:	2b00      	cmp	r3, #0
 8009d54:	d109      	bne.n	8009d6a <HAL_DMA_IRQHandler+0xba2>
        {
          if(hdma->XferM1CpltCallback != NULL)
 8009d56:	687b      	ldr	r3, [r7, #4]
 8009d58:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 8009d5a:	2b00      	cmp	r3, #0
 8009d5c:	f000 813a 	beq.w	8009fd4 <HAL_DMA_IRQHandler+0xe0c>
          {
            /* Transfer complete Callback for Memory 1 */
            hdma->XferM1CpltCallback(hdma);
 8009d60:	687b      	ldr	r3, [r7, #4]
 8009d62:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 8009d64:	6878      	ldr	r0, [r7, #4]
 8009d66:	4798      	blx	r3
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8009d68:	e134      	b.n	8009fd4 <HAL_DMA_IRQHandler+0xe0c>
          }
        }
        /* Current memory buffer used is Memory 1 */
        else
        {
          if(hdma->XferCpltCallback != NULL)
 8009d6a:	687b      	ldr	r3, [r7, #4]
 8009d6c:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8009d6e:	2b00      	cmp	r3, #0
 8009d70:	f000 8130 	beq.w	8009fd4 <HAL_DMA_IRQHandler+0xe0c>
          {
            /* Transfer complete Callback for Memory 0 */
            hdma->XferCpltCallback(hdma);
 8009d74:	687b      	ldr	r3, [r7, #4]
 8009d76:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8009d78:	6878      	ldr	r0, [r7, #4]
 8009d7a:	4798      	blx	r3
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8009d7c:	e12a      	b.n	8009fd4 <HAL_DMA_IRQHandler+0xe0c>
          }
        }
      }
      else
      {
        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
 8009d7e:	693b      	ldr	r3, [r7, #16]
 8009d80:	f003 0320 	and.w	r3, r3, #32
 8009d84:	2b00      	cmp	r3, #0
 8009d86:	f040 8089 	bne.w	8009e9c <HAL_DMA_IRQHandler+0xcd4>
        {
          /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */
          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
 8009d8a:	687b      	ldr	r3, [r7, #4]
 8009d8c:	681b      	ldr	r3, [r3, #0]
 8009d8e:	4a2b      	ldr	r2, [pc, #172]	@ (8009e3c <HAL_DMA_IRQHandler+0xc74>)
 8009d90:	4293      	cmp	r3, r2
 8009d92:	d04a      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009d94:	687b      	ldr	r3, [r7, #4]
 8009d96:	681b      	ldr	r3, [r3, #0]
 8009d98:	4a29      	ldr	r2, [pc, #164]	@ (8009e40 <HAL_DMA_IRQHandler+0xc78>)
 8009d9a:	4293      	cmp	r3, r2
 8009d9c:	d045      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009d9e:	687b      	ldr	r3, [r7, #4]
 8009da0:	681b      	ldr	r3, [r3, #0]
 8009da2:	4a28      	ldr	r2, [pc, #160]	@ (8009e44 <HAL_DMA_IRQHandler+0xc7c>)
 8009da4:	4293      	cmp	r3, r2
 8009da6:	d040      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009da8:	687b      	ldr	r3, [r7, #4]
 8009daa:	681b      	ldr	r3, [r3, #0]
 8009dac:	4a26      	ldr	r2, [pc, #152]	@ (8009e48 <HAL_DMA_IRQHandler+0xc80>)
 8009dae:	4293      	cmp	r3, r2
 8009db0:	d03b      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009db2:	687b      	ldr	r3, [r7, #4]
 8009db4:	681b      	ldr	r3, [r3, #0]
 8009db6:	4a25      	ldr	r2, [pc, #148]	@ (8009e4c <HAL_DMA_IRQHandler+0xc84>)
 8009db8:	4293      	cmp	r3, r2
 8009dba:	d036      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009dbc:	687b      	ldr	r3, [r7, #4]
 8009dbe:	681b      	ldr	r3, [r3, #0]
 8009dc0:	4a23      	ldr	r2, [pc, #140]	@ (8009e50 <HAL_DMA_IRQHandler+0xc88>)
 8009dc2:	4293      	cmp	r3, r2
 8009dc4:	d031      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009dc6:	687b      	ldr	r3, [r7, #4]
 8009dc8:	681b      	ldr	r3, [r3, #0]
 8009dca:	4a22      	ldr	r2, [pc, #136]	@ (8009e54 <HAL_DMA_IRQHandler+0xc8c>)
 8009dcc:	4293      	cmp	r3, r2
 8009dce:	d02c      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009dd0:	687b      	ldr	r3, [r7, #4]
 8009dd2:	681b      	ldr	r3, [r3, #0]
 8009dd4:	4a20      	ldr	r2, [pc, #128]	@ (8009e58 <HAL_DMA_IRQHandler+0xc90>)
 8009dd6:	4293      	cmp	r3, r2
 8009dd8:	d027      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009dda:	687b      	ldr	r3, [r7, #4]
 8009ddc:	681b      	ldr	r3, [r3, #0]
 8009dde:	4a1f      	ldr	r2, [pc, #124]	@ (8009e5c <HAL_DMA_IRQHandler+0xc94>)
 8009de0:	4293      	cmp	r3, r2
 8009de2:	d022      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009de4:	687b      	ldr	r3, [r7, #4]
 8009de6:	681b      	ldr	r3, [r3, #0]
 8009de8:	4a1d      	ldr	r2, [pc, #116]	@ (8009e60 <HAL_DMA_IRQHandler+0xc98>)
 8009dea:	4293      	cmp	r3, r2
 8009dec:	d01d      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009dee:	687b      	ldr	r3, [r7, #4]
 8009df0:	681b      	ldr	r3, [r3, #0]
 8009df2:	4a1c      	ldr	r2, [pc, #112]	@ (8009e64 <HAL_DMA_IRQHandler+0xc9c>)
 8009df4:	4293      	cmp	r3, r2
 8009df6:	d018      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009df8:	687b      	ldr	r3, [r7, #4]
 8009dfa:	681b      	ldr	r3, [r3, #0]
 8009dfc:	4a1a      	ldr	r2, [pc, #104]	@ (8009e68 <HAL_DMA_IRQHandler+0xca0>)
 8009dfe:	4293      	cmp	r3, r2
 8009e00:	d013      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009e02:	687b      	ldr	r3, [r7, #4]
 8009e04:	681b      	ldr	r3, [r3, #0]
 8009e06:	4a19      	ldr	r2, [pc, #100]	@ (8009e6c <HAL_DMA_IRQHandler+0xca4>)
 8009e08:	4293      	cmp	r3, r2
 8009e0a:	d00e      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009e0c:	687b      	ldr	r3, [r7, #4]
 8009e0e:	681b      	ldr	r3, [r3, #0]
 8009e10:	4a17      	ldr	r2, [pc, #92]	@ (8009e70 <HAL_DMA_IRQHandler+0xca8>)
 8009e12:	4293      	cmp	r3, r2
 8009e14:	d009      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009e16:	687b      	ldr	r3, [r7, #4]
 8009e18:	681b      	ldr	r3, [r3, #0]
 8009e1a:	4a16      	ldr	r2, [pc, #88]	@ (8009e74 <HAL_DMA_IRQHandler+0xcac>)
 8009e1c:	4293      	cmp	r3, r2
 8009e1e:	d004      	beq.n	8009e2a <HAL_DMA_IRQHandler+0xc62>
 8009e20:	687b      	ldr	r3, [r7, #4]
 8009e22:	681b      	ldr	r3, [r3, #0]
 8009e24:	4a14      	ldr	r2, [pc, #80]	@ (8009e78 <HAL_DMA_IRQHandler+0xcb0>)
 8009e26:	4293      	cmp	r3, r2
 8009e28:	d128      	bne.n	8009e7c <HAL_DMA_IRQHandler+0xcb4>
 8009e2a:	687b      	ldr	r3, [r7, #4]
 8009e2c:	681b      	ldr	r3, [r3, #0]
 8009e2e:	681a      	ldr	r2, [r3, #0]
 8009e30:	687b      	ldr	r3, [r7, #4]
 8009e32:	681b      	ldr	r3, [r3, #0]
 8009e34:	f022 0214 	bic.w	r2, r2, #20
 8009e38:	601a      	str	r2, [r3, #0]
 8009e3a:	e027      	b.n	8009e8c <HAL_DMA_IRQHandler+0xcc4>
 8009e3c:	40020010 	.word	0x40020010
 8009e40:	40020028 	.word	0x40020028
 8009e44:	40020040 	.word	0x40020040
 8009e48:	40020058 	.word	0x40020058
 8009e4c:	40020070 	.word	0x40020070
 8009e50:	40020088 	.word	0x40020088
 8009e54:	400200a0 	.word	0x400200a0
 8009e58:	400200b8 	.word	0x400200b8
 8009e5c:	40020410 	.word	0x40020410
 8009e60:	40020428 	.word	0x40020428
 8009e64:	40020440 	.word	0x40020440
 8009e68:	40020458 	.word	0x40020458
 8009e6c:	40020470 	.word	0x40020470
 8009e70:	40020488 	.word	0x40020488
 8009e74:	400204a0 	.word	0x400204a0
 8009e78:	400204b8 	.word	0x400204b8
 8009e7c:	687b      	ldr	r3, [r7, #4]
 8009e7e:	681b      	ldr	r3, [r3, #0]
 8009e80:	681a      	ldr	r2, [r3, #0]
 8009e82:	687b      	ldr	r3, [r7, #4]
 8009e84:	681b      	ldr	r3, [r3, #0]
 8009e86:	f022 020a 	bic.w	r2, r2, #10
 8009e8a:	601a      	str	r2, [r3, #0]

          /* Change the DMA state */
          hdma->State = HAL_DMA_STATE_READY;
 8009e8c:	687b      	ldr	r3, [r7, #4]
 8009e8e:	2201      	movs	r2, #1
 8009e90:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

          /* Process Unlocked */
          __HAL_UNLOCK(hdma);
 8009e94:	687b      	ldr	r3, [r7, #4]
 8009e96:	2200      	movs	r2, #0
 8009e98:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
        }

        if(hdma->XferCpltCallback != NULL)
 8009e9c:	687b      	ldr	r3, [r7, #4]
 8009e9e:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8009ea0:	2b00      	cmp	r3, #0
 8009ea2:	f000 8097 	beq.w	8009fd4 <HAL_DMA_IRQHandler+0xe0c>
        {
          /* Transfer complete callback */
          hdma->XferCpltCallback(hdma);
 8009ea6:	687b      	ldr	r3, [r7, #4]
 8009ea8:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8009eaa:	6878      	ldr	r0, [r7, #4]
 8009eac:	4798      	blx	r3
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8009eae:	e091      	b.n	8009fd4 <HAL_DMA_IRQHandler+0xe0c>
        }
      }
    }
    /* Transfer Error Interrupt management **************************************/
    else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))
 8009eb0:	687b      	ldr	r3, [r7, #4]
 8009eb2:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8009eb4:	f003 031f 	and.w	r3, r3, #31
 8009eb8:	2208      	movs	r2, #8
 8009eba:	409a      	lsls	r2, r3
 8009ebc:	697b      	ldr	r3, [r7, #20]
 8009ebe:	4013      	ands	r3, r2
 8009ec0:	2b00      	cmp	r3, #0
 8009ec2:	f000 8088 	beq.w	8009fd6 <HAL_DMA_IRQHandler+0xe0e>
 8009ec6:	693b      	ldr	r3, [r7, #16]
 8009ec8:	f003 0308 	and.w	r3, r3, #8
 8009ecc:	2b00      	cmp	r3, #0
 8009ece:	f000 8082 	beq.w	8009fd6 <HAL_DMA_IRQHandler+0xe0e>
    {
      /* When a DMA transfer error occurs */
      /* A hardware clear of its EN bits is performed */
      /* Disable ALL DMA IT */
      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8009ed2:	687b      	ldr	r3, [r7, #4]
 8009ed4:	681b      	ldr	r3, [r3, #0]
 8009ed6:	4a41      	ldr	r2, [pc, #260]	@ (8009fdc <HAL_DMA_IRQHandler+0xe14>)
 8009ed8:	4293      	cmp	r3, r2
 8009eda:	d04a      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009edc:	687b      	ldr	r3, [r7, #4]
 8009ede:	681b      	ldr	r3, [r3, #0]
 8009ee0:	4a3f      	ldr	r2, [pc, #252]	@ (8009fe0 <HAL_DMA_IRQHandler+0xe18>)
 8009ee2:	4293      	cmp	r3, r2
 8009ee4:	d045      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009ee6:	687b      	ldr	r3, [r7, #4]
 8009ee8:	681b      	ldr	r3, [r3, #0]
 8009eea:	4a3e      	ldr	r2, [pc, #248]	@ (8009fe4 <HAL_DMA_IRQHandler+0xe1c>)
 8009eec:	4293      	cmp	r3, r2
 8009eee:	d040      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009ef0:	687b      	ldr	r3, [r7, #4]
 8009ef2:	681b      	ldr	r3, [r3, #0]
 8009ef4:	4a3c      	ldr	r2, [pc, #240]	@ (8009fe8 <HAL_DMA_IRQHandler+0xe20>)
 8009ef6:	4293      	cmp	r3, r2
 8009ef8:	d03b      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009efa:	687b      	ldr	r3, [r7, #4]
 8009efc:	681b      	ldr	r3, [r3, #0]
 8009efe:	4a3b      	ldr	r2, [pc, #236]	@ (8009fec <HAL_DMA_IRQHandler+0xe24>)
 8009f00:	4293      	cmp	r3, r2
 8009f02:	d036      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009f04:	687b      	ldr	r3, [r7, #4]
 8009f06:	681b      	ldr	r3, [r3, #0]
 8009f08:	4a39      	ldr	r2, [pc, #228]	@ (8009ff0 <HAL_DMA_IRQHandler+0xe28>)
 8009f0a:	4293      	cmp	r3, r2
 8009f0c:	d031      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009f0e:	687b      	ldr	r3, [r7, #4]
 8009f10:	681b      	ldr	r3, [r3, #0]
 8009f12:	4a38      	ldr	r2, [pc, #224]	@ (8009ff4 <HAL_DMA_IRQHandler+0xe2c>)
 8009f14:	4293      	cmp	r3, r2
 8009f16:	d02c      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009f18:	687b      	ldr	r3, [r7, #4]
 8009f1a:	681b      	ldr	r3, [r3, #0]
 8009f1c:	4a36      	ldr	r2, [pc, #216]	@ (8009ff8 <HAL_DMA_IRQHandler+0xe30>)
 8009f1e:	4293      	cmp	r3, r2
 8009f20:	d027      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009f22:	687b      	ldr	r3, [r7, #4]
 8009f24:	681b      	ldr	r3, [r3, #0]
 8009f26:	4a35      	ldr	r2, [pc, #212]	@ (8009ffc <HAL_DMA_IRQHandler+0xe34>)
 8009f28:	4293      	cmp	r3, r2
 8009f2a:	d022      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009f2c:	687b      	ldr	r3, [r7, #4]
 8009f2e:	681b      	ldr	r3, [r3, #0]
 8009f30:	4a33      	ldr	r2, [pc, #204]	@ (800a000 <HAL_DMA_IRQHandler+0xe38>)
 8009f32:	4293      	cmp	r3, r2
 8009f34:	d01d      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009f36:	687b      	ldr	r3, [r7, #4]
 8009f38:	681b      	ldr	r3, [r3, #0]
 8009f3a:	4a32      	ldr	r2, [pc, #200]	@ (800a004 <HAL_DMA_IRQHandler+0xe3c>)
 8009f3c:	4293      	cmp	r3, r2
 8009f3e:	d018      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009f40:	687b      	ldr	r3, [r7, #4]
 8009f42:	681b      	ldr	r3, [r3, #0]
 8009f44:	4a30      	ldr	r2, [pc, #192]	@ (800a008 <HAL_DMA_IRQHandler+0xe40>)
 8009f46:	4293      	cmp	r3, r2
 8009f48:	d013      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009f4a:	687b      	ldr	r3, [r7, #4]
 8009f4c:	681b      	ldr	r3, [r3, #0]
 8009f4e:	4a2f      	ldr	r2, [pc, #188]	@ (800a00c <HAL_DMA_IRQHandler+0xe44>)
 8009f50:	4293      	cmp	r3, r2
 8009f52:	d00e      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009f54:	687b      	ldr	r3, [r7, #4]
 8009f56:	681b      	ldr	r3, [r3, #0]
 8009f58:	4a2d      	ldr	r2, [pc, #180]	@ (800a010 <HAL_DMA_IRQHandler+0xe48>)
 8009f5a:	4293      	cmp	r3, r2
 8009f5c:	d009      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009f5e:	687b      	ldr	r3, [r7, #4]
 8009f60:	681b      	ldr	r3, [r3, #0]
 8009f62:	4a2c      	ldr	r2, [pc, #176]	@ (800a014 <HAL_DMA_IRQHandler+0xe4c>)
 8009f64:	4293      	cmp	r3, r2
 8009f66:	d004      	beq.n	8009f72 <HAL_DMA_IRQHandler+0xdaa>
 8009f68:	687b      	ldr	r3, [r7, #4]
 8009f6a:	681b      	ldr	r3, [r3, #0]
 8009f6c:	4a2a      	ldr	r2, [pc, #168]	@ (800a018 <HAL_DMA_IRQHandler+0xe50>)
 8009f6e:	4293      	cmp	r3, r2
 8009f70:	d108      	bne.n	8009f84 <HAL_DMA_IRQHandler+0xdbc>
 8009f72:	687b      	ldr	r3, [r7, #4]
 8009f74:	681b      	ldr	r3, [r3, #0]
 8009f76:	681a      	ldr	r2, [r3, #0]
 8009f78:	687b      	ldr	r3, [r7, #4]
 8009f7a:	681b      	ldr	r3, [r3, #0]
 8009f7c:	f022 021c 	bic.w	r2, r2, #28
 8009f80:	601a      	str	r2, [r3, #0]
 8009f82:	e007      	b.n	8009f94 <HAL_DMA_IRQHandler+0xdcc>
 8009f84:	687b      	ldr	r3, [r7, #4]
 8009f86:	681b      	ldr	r3, [r3, #0]
 8009f88:	681a      	ldr	r2, [r3, #0]
 8009f8a:	687b      	ldr	r3, [r7, #4]
 8009f8c:	681b      	ldr	r3, [r3, #0]
 8009f8e:	f022 020e 	bic.w	r2, r2, #14
 8009f92:	601a      	str	r2, [r3, #0]

      /* Clear all flags */
      regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
 8009f94:	687b      	ldr	r3, [r7, #4]
 8009f96:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8009f98:	f003 031f 	and.w	r3, r3, #31
 8009f9c:	2201      	movs	r2, #1
 8009f9e:	409a      	lsls	r2, r3
 8009fa0:	69fb      	ldr	r3, [r7, #28]
 8009fa2:	605a      	str	r2, [r3, #4]

      /* Update error code */
      hdma->ErrorCode = HAL_DMA_ERROR_TE;
 8009fa4:	687b      	ldr	r3, [r7, #4]
 8009fa6:	2201      	movs	r2, #1
 8009fa8:	655a      	str	r2, [r3, #84]	@ 0x54

      /* Change the DMA state */
      hdma->State = HAL_DMA_STATE_READY;
 8009faa:	687b      	ldr	r3, [r7, #4]
 8009fac:	2201      	movs	r2, #1
 8009fae:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35

      /* Process Unlocked */
      __HAL_UNLOCK(hdma);
 8009fb2:	687b      	ldr	r3, [r7, #4]
 8009fb4:	2200      	movs	r2, #0
 8009fb6:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34

      if (hdma->XferErrorCallback != NULL)
 8009fba:	687b      	ldr	r3, [r7, #4]
 8009fbc:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8009fbe:	2b00      	cmp	r3, #0
 8009fc0:	d009      	beq.n	8009fd6 <HAL_DMA_IRQHandler+0xe0e>
      {
        /* Transfer error callback */
        hdma->XferErrorCallback(hdma);
 8009fc2:	687b      	ldr	r3, [r7, #4]
 8009fc4:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8009fc6:	6878      	ldr	r0, [r7, #4]
 8009fc8:	4798      	blx	r3
 8009fca:	e004      	b.n	8009fd6 <HAL_DMA_IRQHandler+0xe0e>
          return;
 8009fcc:	bf00      	nop
 8009fce:	e002      	b.n	8009fd6 <HAL_DMA_IRQHandler+0xe0e>
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8009fd0:	bf00      	nop
 8009fd2:	e000      	b.n	8009fd6 <HAL_DMA_IRQHandler+0xe0e>
      if((ccr_reg & BDMA_CCR_DBM) != 0U)
 8009fd4:	bf00      	nop
  }
  else
  {
    /* Nothing To Do */
  }
}
 8009fd6:	3728      	adds	r7, #40	@ 0x28
 8009fd8:	46bd      	mov	sp, r7
 8009fda:	bd80      	pop	{r7, pc}
 8009fdc:	40020010 	.word	0x40020010
 8009fe0:	40020028 	.word	0x40020028
 8009fe4:	40020040 	.word	0x40020040
 8009fe8:	40020058 	.word	0x40020058
 8009fec:	40020070 	.word	0x40020070
 8009ff0:	40020088 	.word	0x40020088
 8009ff4:	400200a0 	.word	0x400200a0
 8009ff8:	400200b8 	.word	0x400200b8
 8009ffc:	40020410 	.word	0x40020410
 800a000:	40020428 	.word	0x40020428
 800a004:	40020440 	.word	0x40020440
 800a008:	40020458 	.word	0x40020458
 800a00c:	40020470 	.word	0x40020470
 800a010:	40020488 	.word	0x40020488
 800a014:	400204a0 	.word	0x400204a0
 800a018:	400204b8 	.word	0x400204b8

0800a01c <DMA_SetConfig>:
  * @param  DstAddress: The destination memory Buffer address
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval None
  */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 800a01c:	b480      	push	{r7}
 800a01e:	b087      	sub	sp, #28
 800a020:	af00      	add	r7, sp, #0
 800a022:	60f8      	str	r0, [r7, #12]
 800a024:	60b9      	str	r1, [r7, #8]
 800a026:	607a      	str	r2, [r7, #4]
 800a028:	603b      	str	r3, [r7, #0]
  /* calculate DMA base and stream number */
  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
 800a02a:	68fb      	ldr	r3, [r7, #12]
 800a02c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800a02e:	617b      	str	r3, [r7, #20]
  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
 800a030:	68fb      	ldr	r3, [r7, #12]
 800a032:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800a034:	613b      	str	r3, [r7, #16]

  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
 800a036:	68fb      	ldr	r3, [r7, #12]
 800a038:	681b      	ldr	r3, [r3, #0]
 800a03a:	4a7f      	ldr	r2, [pc, #508]	@ (800a238 <DMA_SetConfig+0x21c>)
 800a03c:	4293      	cmp	r3, r2
 800a03e:	d072      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a040:	68fb      	ldr	r3, [r7, #12]
 800a042:	681b      	ldr	r3, [r3, #0]
 800a044:	4a7d      	ldr	r2, [pc, #500]	@ (800a23c <DMA_SetConfig+0x220>)
 800a046:	4293      	cmp	r3, r2
 800a048:	d06d      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a04a:	68fb      	ldr	r3, [r7, #12]
 800a04c:	681b      	ldr	r3, [r3, #0]
 800a04e:	4a7c      	ldr	r2, [pc, #496]	@ (800a240 <DMA_SetConfig+0x224>)
 800a050:	4293      	cmp	r3, r2
 800a052:	d068      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a054:	68fb      	ldr	r3, [r7, #12]
 800a056:	681b      	ldr	r3, [r3, #0]
 800a058:	4a7a      	ldr	r2, [pc, #488]	@ (800a244 <DMA_SetConfig+0x228>)
 800a05a:	4293      	cmp	r3, r2
 800a05c:	d063      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a05e:	68fb      	ldr	r3, [r7, #12]
 800a060:	681b      	ldr	r3, [r3, #0]
 800a062:	4a79      	ldr	r2, [pc, #484]	@ (800a248 <DMA_SetConfig+0x22c>)
 800a064:	4293      	cmp	r3, r2
 800a066:	d05e      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a068:	68fb      	ldr	r3, [r7, #12]
 800a06a:	681b      	ldr	r3, [r3, #0]
 800a06c:	4a77      	ldr	r2, [pc, #476]	@ (800a24c <DMA_SetConfig+0x230>)
 800a06e:	4293      	cmp	r3, r2
 800a070:	d059      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a072:	68fb      	ldr	r3, [r7, #12]
 800a074:	681b      	ldr	r3, [r3, #0]
 800a076:	4a76      	ldr	r2, [pc, #472]	@ (800a250 <DMA_SetConfig+0x234>)
 800a078:	4293      	cmp	r3, r2
 800a07a:	d054      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a07c:	68fb      	ldr	r3, [r7, #12]
 800a07e:	681b      	ldr	r3, [r3, #0]
 800a080:	4a74      	ldr	r2, [pc, #464]	@ (800a254 <DMA_SetConfig+0x238>)
 800a082:	4293      	cmp	r3, r2
 800a084:	d04f      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a086:	68fb      	ldr	r3, [r7, #12]
 800a088:	681b      	ldr	r3, [r3, #0]
 800a08a:	4a73      	ldr	r2, [pc, #460]	@ (800a258 <DMA_SetConfig+0x23c>)
 800a08c:	4293      	cmp	r3, r2
 800a08e:	d04a      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a090:	68fb      	ldr	r3, [r7, #12]
 800a092:	681b      	ldr	r3, [r3, #0]
 800a094:	4a71      	ldr	r2, [pc, #452]	@ (800a25c <DMA_SetConfig+0x240>)
 800a096:	4293      	cmp	r3, r2
 800a098:	d045      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a09a:	68fb      	ldr	r3, [r7, #12]
 800a09c:	681b      	ldr	r3, [r3, #0]
 800a09e:	4a70      	ldr	r2, [pc, #448]	@ (800a260 <DMA_SetConfig+0x244>)
 800a0a0:	4293      	cmp	r3, r2
 800a0a2:	d040      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a0a4:	68fb      	ldr	r3, [r7, #12]
 800a0a6:	681b      	ldr	r3, [r3, #0]
 800a0a8:	4a6e      	ldr	r2, [pc, #440]	@ (800a264 <DMA_SetConfig+0x248>)
 800a0aa:	4293      	cmp	r3, r2
 800a0ac:	d03b      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a0ae:	68fb      	ldr	r3, [r7, #12]
 800a0b0:	681b      	ldr	r3, [r3, #0]
 800a0b2:	4a6d      	ldr	r2, [pc, #436]	@ (800a268 <DMA_SetConfig+0x24c>)
 800a0b4:	4293      	cmp	r3, r2
 800a0b6:	d036      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a0b8:	68fb      	ldr	r3, [r7, #12]
 800a0ba:	681b      	ldr	r3, [r3, #0]
 800a0bc:	4a6b      	ldr	r2, [pc, #428]	@ (800a26c <DMA_SetConfig+0x250>)
 800a0be:	4293      	cmp	r3, r2
 800a0c0:	d031      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a0c2:	68fb      	ldr	r3, [r7, #12]
 800a0c4:	681b      	ldr	r3, [r3, #0]
 800a0c6:	4a6a      	ldr	r2, [pc, #424]	@ (800a270 <DMA_SetConfig+0x254>)
 800a0c8:	4293      	cmp	r3, r2
 800a0ca:	d02c      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a0cc:	68fb      	ldr	r3, [r7, #12]
 800a0ce:	681b      	ldr	r3, [r3, #0]
 800a0d0:	4a68      	ldr	r2, [pc, #416]	@ (800a274 <DMA_SetConfig+0x258>)
 800a0d2:	4293      	cmp	r3, r2
 800a0d4:	d027      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a0d6:	68fb      	ldr	r3, [r7, #12]
 800a0d8:	681b      	ldr	r3, [r3, #0]
 800a0da:	4a67      	ldr	r2, [pc, #412]	@ (800a278 <DMA_SetConfig+0x25c>)
 800a0dc:	4293      	cmp	r3, r2
 800a0de:	d022      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a0e0:	68fb      	ldr	r3, [r7, #12]
 800a0e2:	681b      	ldr	r3, [r3, #0]
 800a0e4:	4a65      	ldr	r2, [pc, #404]	@ (800a27c <DMA_SetConfig+0x260>)
 800a0e6:	4293      	cmp	r3, r2
 800a0e8:	d01d      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a0ea:	68fb      	ldr	r3, [r7, #12]
 800a0ec:	681b      	ldr	r3, [r3, #0]
 800a0ee:	4a64      	ldr	r2, [pc, #400]	@ (800a280 <DMA_SetConfig+0x264>)
 800a0f0:	4293      	cmp	r3, r2
 800a0f2:	d018      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a0f4:	68fb      	ldr	r3, [r7, #12]
 800a0f6:	681b      	ldr	r3, [r3, #0]
 800a0f8:	4a62      	ldr	r2, [pc, #392]	@ (800a284 <DMA_SetConfig+0x268>)
 800a0fa:	4293      	cmp	r3, r2
 800a0fc:	d013      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a0fe:	68fb      	ldr	r3, [r7, #12]
 800a100:	681b      	ldr	r3, [r3, #0]
 800a102:	4a61      	ldr	r2, [pc, #388]	@ (800a288 <DMA_SetConfig+0x26c>)
 800a104:	4293      	cmp	r3, r2
 800a106:	d00e      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a108:	68fb      	ldr	r3, [r7, #12]
 800a10a:	681b      	ldr	r3, [r3, #0]
 800a10c:	4a5f      	ldr	r2, [pc, #380]	@ (800a28c <DMA_SetConfig+0x270>)
 800a10e:	4293      	cmp	r3, r2
 800a110:	d009      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a112:	68fb      	ldr	r3, [r7, #12]
 800a114:	681b      	ldr	r3, [r3, #0]
 800a116:	4a5e      	ldr	r2, [pc, #376]	@ (800a290 <DMA_SetConfig+0x274>)
 800a118:	4293      	cmp	r3, r2
 800a11a:	d004      	beq.n	800a126 <DMA_SetConfig+0x10a>
 800a11c:	68fb      	ldr	r3, [r7, #12]
 800a11e:	681b      	ldr	r3, [r3, #0]
 800a120:	4a5c      	ldr	r2, [pc, #368]	@ (800a294 <DMA_SetConfig+0x278>)
 800a122:	4293      	cmp	r3, r2
 800a124:	d101      	bne.n	800a12a <DMA_SetConfig+0x10e>
 800a126:	2301      	movs	r3, #1
 800a128:	e000      	b.n	800a12c <DMA_SetConfig+0x110>
 800a12a:	2300      	movs	r3, #0
 800a12c:	2b00      	cmp	r3, #0
 800a12e:	d00d      	beq.n	800a14c <DMA_SetConfig+0x130>
  {
    /* Clear the DMAMUX synchro overrun flag */
    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 800a130:	68fb      	ldr	r3, [r7, #12]
 800a132:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 800a134:	68fa      	ldr	r2, [r7, #12]
 800a136:	6e92      	ldr	r2, [r2, #104]	@ 0x68
 800a138:	605a      	str	r2, [r3, #4]

    if(hdma->DMAmuxRequestGen != 0U)
 800a13a:	68fb      	ldr	r3, [r7, #12]
 800a13c:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800a13e:	2b00      	cmp	r3, #0
 800a140:	d004      	beq.n	800a14c <DMA_SetConfig+0x130>
    {
      /* Clear the DMAMUX request generator overrun flag */
      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 800a142:	68fb      	ldr	r3, [r7, #12]
 800a144:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800a146:	68fa      	ldr	r2, [r7, #12]
 800a148:	6f52      	ldr	r2, [r2, #116]	@ 0x74
 800a14a:	605a      	str	r2, [r3, #4]
    }
  }

  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 800a14c:	68fb      	ldr	r3, [r7, #12]
 800a14e:	681b      	ldr	r3, [r3, #0]
 800a150:	4a39      	ldr	r2, [pc, #228]	@ (800a238 <DMA_SetConfig+0x21c>)
 800a152:	4293      	cmp	r3, r2
 800a154:	d04a      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a156:	68fb      	ldr	r3, [r7, #12]
 800a158:	681b      	ldr	r3, [r3, #0]
 800a15a:	4a38      	ldr	r2, [pc, #224]	@ (800a23c <DMA_SetConfig+0x220>)
 800a15c:	4293      	cmp	r3, r2
 800a15e:	d045      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a160:	68fb      	ldr	r3, [r7, #12]
 800a162:	681b      	ldr	r3, [r3, #0]
 800a164:	4a36      	ldr	r2, [pc, #216]	@ (800a240 <DMA_SetConfig+0x224>)
 800a166:	4293      	cmp	r3, r2
 800a168:	d040      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a16a:	68fb      	ldr	r3, [r7, #12]
 800a16c:	681b      	ldr	r3, [r3, #0]
 800a16e:	4a35      	ldr	r2, [pc, #212]	@ (800a244 <DMA_SetConfig+0x228>)
 800a170:	4293      	cmp	r3, r2
 800a172:	d03b      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a174:	68fb      	ldr	r3, [r7, #12]
 800a176:	681b      	ldr	r3, [r3, #0]
 800a178:	4a33      	ldr	r2, [pc, #204]	@ (800a248 <DMA_SetConfig+0x22c>)
 800a17a:	4293      	cmp	r3, r2
 800a17c:	d036      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a17e:	68fb      	ldr	r3, [r7, #12]
 800a180:	681b      	ldr	r3, [r3, #0]
 800a182:	4a32      	ldr	r2, [pc, #200]	@ (800a24c <DMA_SetConfig+0x230>)
 800a184:	4293      	cmp	r3, r2
 800a186:	d031      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a188:	68fb      	ldr	r3, [r7, #12]
 800a18a:	681b      	ldr	r3, [r3, #0]
 800a18c:	4a30      	ldr	r2, [pc, #192]	@ (800a250 <DMA_SetConfig+0x234>)
 800a18e:	4293      	cmp	r3, r2
 800a190:	d02c      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a192:	68fb      	ldr	r3, [r7, #12]
 800a194:	681b      	ldr	r3, [r3, #0]
 800a196:	4a2f      	ldr	r2, [pc, #188]	@ (800a254 <DMA_SetConfig+0x238>)
 800a198:	4293      	cmp	r3, r2
 800a19a:	d027      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a19c:	68fb      	ldr	r3, [r7, #12]
 800a19e:	681b      	ldr	r3, [r3, #0]
 800a1a0:	4a2d      	ldr	r2, [pc, #180]	@ (800a258 <DMA_SetConfig+0x23c>)
 800a1a2:	4293      	cmp	r3, r2
 800a1a4:	d022      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a1a6:	68fb      	ldr	r3, [r7, #12]
 800a1a8:	681b      	ldr	r3, [r3, #0]
 800a1aa:	4a2c      	ldr	r2, [pc, #176]	@ (800a25c <DMA_SetConfig+0x240>)
 800a1ac:	4293      	cmp	r3, r2
 800a1ae:	d01d      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a1b0:	68fb      	ldr	r3, [r7, #12]
 800a1b2:	681b      	ldr	r3, [r3, #0]
 800a1b4:	4a2a      	ldr	r2, [pc, #168]	@ (800a260 <DMA_SetConfig+0x244>)
 800a1b6:	4293      	cmp	r3, r2
 800a1b8:	d018      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a1ba:	68fb      	ldr	r3, [r7, #12]
 800a1bc:	681b      	ldr	r3, [r3, #0]
 800a1be:	4a29      	ldr	r2, [pc, #164]	@ (800a264 <DMA_SetConfig+0x248>)
 800a1c0:	4293      	cmp	r3, r2
 800a1c2:	d013      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a1c4:	68fb      	ldr	r3, [r7, #12]
 800a1c6:	681b      	ldr	r3, [r3, #0]
 800a1c8:	4a27      	ldr	r2, [pc, #156]	@ (800a268 <DMA_SetConfig+0x24c>)
 800a1ca:	4293      	cmp	r3, r2
 800a1cc:	d00e      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a1ce:	68fb      	ldr	r3, [r7, #12]
 800a1d0:	681b      	ldr	r3, [r3, #0]
 800a1d2:	4a26      	ldr	r2, [pc, #152]	@ (800a26c <DMA_SetConfig+0x250>)
 800a1d4:	4293      	cmp	r3, r2
 800a1d6:	d009      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a1d8:	68fb      	ldr	r3, [r7, #12]
 800a1da:	681b      	ldr	r3, [r3, #0]
 800a1dc:	4a24      	ldr	r2, [pc, #144]	@ (800a270 <DMA_SetConfig+0x254>)
 800a1de:	4293      	cmp	r3, r2
 800a1e0:	d004      	beq.n	800a1ec <DMA_SetConfig+0x1d0>
 800a1e2:	68fb      	ldr	r3, [r7, #12]
 800a1e4:	681b      	ldr	r3, [r3, #0]
 800a1e6:	4a23      	ldr	r2, [pc, #140]	@ (800a274 <DMA_SetConfig+0x258>)
 800a1e8:	4293      	cmp	r3, r2
 800a1ea:	d101      	bne.n	800a1f0 <DMA_SetConfig+0x1d4>
 800a1ec:	2301      	movs	r3, #1
 800a1ee:	e000      	b.n	800a1f2 <DMA_SetConfig+0x1d6>
 800a1f0:	2300      	movs	r3, #0
 800a1f2:	2b00      	cmp	r3, #0
 800a1f4:	d059      	beq.n	800a2aa <DMA_SetConfig+0x28e>
  {
    /* Clear all interrupt flags at correct offset within the register */
    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
 800a1f6:	68fb      	ldr	r3, [r7, #12]
 800a1f8:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800a1fa:	f003 031f 	and.w	r3, r3, #31
 800a1fe:	223f      	movs	r2, #63	@ 0x3f
 800a200:	409a      	lsls	r2, r3
 800a202:	697b      	ldr	r3, [r7, #20]
 800a204:	609a      	str	r2, [r3, #8]

    /* Clear DBM bit */
    ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);
 800a206:	68fb      	ldr	r3, [r7, #12]
 800a208:	681b      	ldr	r3, [r3, #0]
 800a20a:	681a      	ldr	r2, [r3, #0]
 800a20c:	68fb      	ldr	r3, [r7, #12]
 800a20e:	681b      	ldr	r3, [r3, #0]
 800a210:	f422 2280 	bic.w	r2, r2, #262144	@ 0x40000
 800a214:	601a      	str	r2, [r3, #0]

    /* Configure DMA Stream data length */
    ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
 800a216:	68fb      	ldr	r3, [r7, #12]
 800a218:	681b      	ldr	r3, [r3, #0]
 800a21a:	683a      	ldr	r2, [r7, #0]
 800a21c:	605a      	str	r2, [r3, #4]

    /* Peripheral to Memory */
    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 800a21e:	68fb      	ldr	r3, [r7, #12]
 800a220:	689b      	ldr	r3, [r3, #8]
 800a222:	2b40      	cmp	r3, #64	@ 0x40
 800a224:	d138      	bne.n	800a298 <DMA_SetConfig+0x27c>
    {
      /* Configure DMA Stream destination address */
      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
 800a226:	68fb      	ldr	r3, [r7, #12]
 800a228:	681b      	ldr	r3, [r3, #0]
 800a22a:	687a      	ldr	r2, [r7, #4]
 800a22c:	609a      	str	r2, [r3, #8]

      /* Configure DMA Stream source address */
      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
 800a22e:	68fb      	ldr	r3, [r7, #12]
 800a230:	681b      	ldr	r3, [r3, #0]
 800a232:	68ba      	ldr	r2, [r7, #8]
 800a234:	60da      	str	r2, [r3, #12]
  }
  else
  {
    /* Nothing To Do */
  }
}
 800a236:	e086      	b.n	800a346 <DMA_SetConfig+0x32a>
 800a238:	40020010 	.word	0x40020010
 800a23c:	40020028 	.word	0x40020028
 800a240:	40020040 	.word	0x40020040
 800a244:	40020058 	.word	0x40020058
 800a248:	40020070 	.word	0x40020070
 800a24c:	40020088 	.word	0x40020088
 800a250:	400200a0 	.word	0x400200a0
 800a254:	400200b8 	.word	0x400200b8
 800a258:	40020410 	.word	0x40020410
 800a25c:	40020428 	.word	0x40020428
 800a260:	40020440 	.word	0x40020440
 800a264:	40020458 	.word	0x40020458
 800a268:	40020470 	.word	0x40020470
 800a26c:	40020488 	.word	0x40020488
 800a270:	400204a0 	.word	0x400204a0
 800a274:	400204b8 	.word	0x400204b8
 800a278:	58025408 	.word	0x58025408
 800a27c:	5802541c 	.word	0x5802541c
 800a280:	58025430 	.word	0x58025430
 800a284:	58025444 	.word	0x58025444
 800a288:	58025458 	.word	0x58025458
 800a28c:	5802546c 	.word	0x5802546c
 800a290:	58025480 	.word	0x58025480
 800a294:	58025494 	.word	0x58025494
      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
 800a298:	68fb      	ldr	r3, [r7, #12]
 800a29a:	681b      	ldr	r3, [r3, #0]
 800a29c:	68ba      	ldr	r2, [r7, #8]
 800a29e:	609a      	str	r2, [r3, #8]
      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
 800a2a0:	68fb      	ldr	r3, [r7, #12]
 800a2a2:	681b      	ldr	r3, [r3, #0]
 800a2a4:	687a      	ldr	r2, [r7, #4]
 800a2a6:	60da      	str	r2, [r3, #12]
}
 800a2a8:	e04d      	b.n	800a346 <DMA_SetConfig+0x32a>
  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
 800a2aa:	68fb      	ldr	r3, [r7, #12]
 800a2ac:	681b      	ldr	r3, [r3, #0]
 800a2ae:	4a29      	ldr	r2, [pc, #164]	@ (800a354 <DMA_SetConfig+0x338>)
 800a2b0:	4293      	cmp	r3, r2
 800a2b2:	d022      	beq.n	800a2fa <DMA_SetConfig+0x2de>
 800a2b4:	68fb      	ldr	r3, [r7, #12]
 800a2b6:	681b      	ldr	r3, [r3, #0]
 800a2b8:	4a27      	ldr	r2, [pc, #156]	@ (800a358 <DMA_SetConfig+0x33c>)
 800a2ba:	4293      	cmp	r3, r2
 800a2bc:	d01d      	beq.n	800a2fa <DMA_SetConfig+0x2de>
 800a2be:	68fb      	ldr	r3, [r7, #12]
 800a2c0:	681b      	ldr	r3, [r3, #0]
 800a2c2:	4a26      	ldr	r2, [pc, #152]	@ (800a35c <DMA_SetConfig+0x340>)
 800a2c4:	4293      	cmp	r3, r2
 800a2c6:	d018      	beq.n	800a2fa <DMA_SetConfig+0x2de>
 800a2c8:	68fb      	ldr	r3, [r7, #12]
 800a2ca:	681b      	ldr	r3, [r3, #0]
 800a2cc:	4a24      	ldr	r2, [pc, #144]	@ (800a360 <DMA_SetConfig+0x344>)
 800a2ce:	4293      	cmp	r3, r2
 800a2d0:	d013      	beq.n	800a2fa <DMA_SetConfig+0x2de>
 800a2d2:	68fb      	ldr	r3, [r7, #12]
 800a2d4:	681b      	ldr	r3, [r3, #0]
 800a2d6:	4a23      	ldr	r2, [pc, #140]	@ (800a364 <DMA_SetConfig+0x348>)
 800a2d8:	4293      	cmp	r3, r2
 800a2da:	d00e      	beq.n	800a2fa <DMA_SetConfig+0x2de>
 800a2dc:	68fb      	ldr	r3, [r7, #12]
 800a2de:	681b      	ldr	r3, [r3, #0]
 800a2e0:	4a21      	ldr	r2, [pc, #132]	@ (800a368 <DMA_SetConfig+0x34c>)
 800a2e2:	4293      	cmp	r3, r2
 800a2e4:	d009      	beq.n	800a2fa <DMA_SetConfig+0x2de>
 800a2e6:	68fb      	ldr	r3, [r7, #12]
 800a2e8:	681b      	ldr	r3, [r3, #0]
 800a2ea:	4a20      	ldr	r2, [pc, #128]	@ (800a36c <DMA_SetConfig+0x350>)
 800a2ec:	4293      	cmp	r3, r2
 800a2ee:	d004      	beq.n	800a2fa <DMA_SetConfig+0x2de>
 800a2f0:	68fb      	ldr	r3, [r7, #12]
 800a2f2:	681b      	ldr	r3, [r3, #0]
 800a2f4:	4a1e      	ldr	r2, [pc, #120]	@ (800a370 <DMA_SetConfig+0x354>)
 800a2f6:	4293      	cmp	r3, r2
 800a2f8:	d101      	bne.n	800a2fe <DMA_SetConfig+0x2e2>
 800a2fa:	2301      	movs	r3, #1
 800a2fc:	e000      	b.n	800a300 <DMA_SetConfig+0x2e4>
 800a2fe:	2300      	movs	r3, #0
 800a300:	2b00      	cmp	r3, #0
 800a302:	d020      	beq.n	800a346 <DMA_SetConfig+0x32a>
    regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
 800a304:	68fb      	ldr	r3, [r7, #12]
 800a306:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800a308:	f003 031f 	and.w	r3, r3, #31
 800a30c:	2201      	movs	r2, #1
 800a30e:	409a      	lsls	r2, r3
 800a310:	693b      	ldr	r3, [r7, #16]
 800a312:	605a      	str	r2, [r3, #4]
    ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
 800a314:	68fb      	ldr	r3, [r7, #12]
 800a316:	681b      	ldr	r3, [r3, #0]
 800a318:	683a      	ldr	r2, [r7, #0]
 800a31a:	605a      	str	r2, [r3, #4]
    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 800a31c:	68fb      	ldr	r3, [r7, #12]
 800a31e:	689b      	ldr	r3, [r3, #8]
 800a320:	2b40      	cmp	r3, #64	@ 0x40
 800a322:	d108      	bne.n	800a336 <DMA_SetConfig+0x31a>
      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
 800a324:	68fb      	ldr	r3, [r7, #12]
 800a326:	681b      	ldr	r3, [r3, #0]
 800a328:	687a      	ldr	r2, [r7, #4]
 800a32a:	609a      	str	r2, [r3, #8]
      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
 800a32c:	68fb      	ldr	r3, [r7, #12]
 800a32e:	681b      	ldr	r3, [r3, #0]
 800a330:	68ba      	ldr	r2, [r7, #8]
 800a332:	60da      	str	r2, [r3, #12]
}
 800a334:	e007      	b.n	800a346 <DMA_SetConfig+0x32a>
      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
 800a336:	68fb      	ldr	r3, [r7, #12]
 800a338:	681b      	ldr	r3, [r3, #0]
 800a33a:	68ba      	ldr	r2, [r7, #8]
 800a33c:	609a      	str	r2, [r3, #8]
      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
 800a33e:	68fb      	ldr	r3, [r7, #12]
 800a340:	681b      	ldr	r3, [r3, #0]
 800a342:	687a      	ldr	r2, [r7, #4]
 800a344:	60da      	str	r2, [r3, #12]
}
 800a346:	bf00      	nop
 800a348:	371c      	adds	r7, #28
 800a34a:	46bd      	mov	sp, r7
 800a34c:	f85d 7b04 	ldr.w	r7, [sp], #4
 800a350:	4770      	bx	lr
 800a352:	bf00      	nop
 800a354:	58025408 	.word	0x58025408
 800a358:	5802541c 	.word	0x5802541c
 800a35c:	58025430 	.word	0x58025430
 800a360:	58025444 	.word	0x58025444
 800a364:	58025458 	.word	0x58025458
 800a368:	5802546c 	.word	0x5802546c
 800a36c:	58025480 	.word	0x58025480
 800a370:	58025494 	.word	0x58025494

0800a374 <DMA_CalcBaseAndBitshift>:
  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
  *                     the configuration information for the specified DMA Stream.
  * @retval Stream base address
  */
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
{
 800a374:	b480      	push	{r7}
 800a376:	b085      	sub	sp, #20
 800a378:	af00      	add	r7, sp, #0
 800a37a:	6078      	str	r0, [r7, #4]
  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
 800a37c:	687b      	ldr	r3, [r7, #4]
 800a37e:	681b      	ldr	r3, [r3, #0]
 800a380:	4a42      	ldr	r2, [pc, #264]	@ (800a48c <DMA_CalcBaseAndBitshift+0x118>)
 800a382:	4293      	cmp	r3, r2
 800a384:	d04a      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a386:	687b      	ldr	r3, [r7, #4]
 800a388:	681b      	ldr	r3, [r3, #0]
 800a38a:	4a41      	ldr	r2, [pc, #260]	@ (800a490 <DMA_CalcBaseAndBitshift+0x11c>)
 800a38c:	4293      	cmp	r3, r2
 800a38e:	d045      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a390:	687b      	ldr	r3, [r7, #4]
 800a392:	681b      	ldr	r3, [r3, #0]
 800a394:	4a3f      	ldr	r2, [pc, #252]	@ (800a494 <DMA_CalcBaseAndBitshift+0x120>)
 800a396:	4293      	cmp	r3, r2
 800a398:	d040      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a39a:	687b      	ldr	r3, [r7, #4]
 800a39c:	681b      	ldr	r3, [r3, #0]
 800a39e:	4a3e      	ldr	r2, [pc, #248]	@ (800a498 <DMA_CalcBaseAndBitshift+0x124>)
 800a3a0:	4293      	cmp	r3, r2
 800a3a2:	d03b      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a3a4:	687b      	ldr	r3, [r7, #4]
 800a3a6:	681b      	ldr	r3, [r3, #0]
 800a3a8:	4a3c      	ldr	r2, [pc, #240]	@ (800a49c <DMA_CalcBaseAndBitshift+0x128>)
 800a3aa:	4293      	cmp	r3, r2
 800a3ac:	d036      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a3ae:	687b      	ldr	r3, [r7, #4]
 800a3b0:	681b      	ldr	r3, [r3, #0]
 800a3b2:	4a3b      	ldr	r2, [pc, #236]	@ (800a4a0 <DMA_CalcBaseAndBitshift+0x12c>)
 800a3b4:	4293      	cmp	r3, r2
 800a3b6:	d031      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a3b8:	687b      	ldr	r3, [r7, #4]
 800a3ba:	681b      	ldr	r3, [r3, #0]
 800a3bc:	4a39      	ldr	r2, [pc, #228]	@ (800a4a4 <DMA_CalcBaseAndBitshift+0x130>)
 800a3be:	4293      	cmp	r3, r2
 800a3c0:	d02c      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a3c2:	687b      	ldr	r3, [r7, #4]
 800a3c4:	681b      	ldr	r3, [r3, #0]
 800a3c6:	4a38      	ldr	r2, [pc, #224]	@ (800a4a8 <DMA_CalcBaseAndBitshift+0x134>)
 800a3c8:	4293      	cmp	r3, r2
 800a3ca:	d027      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a3cc:	687b      	ldr	r3, [r7, #4]
 800a3ce:	681b      	ldr	r3, [r3, #0]
 800a3d0:	4a36      	ldr	r2, [pc, #216]	@ (800a4ac <DMA_CalcBaseAndBitshift+0x138>)
 800a3d2:	4293      	cmp	r3, r2
 800a3d4:	d022      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a3d6:	687b      	ldr	r3, [r7, #4]
 800a3d8:	681b      	ldr	r3, [r3, #0]
 800a3da:	4a35      	ldr	r2, [pc, #212]	@ (800a4b0 <DMA_CalcBaseAndBitshift+0x13c>)
 800a3dc:	4293      	cmp	r3, r2
 800a3de:	d01d      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a3e0:	687b      	ldr	r3, [r7, #4]
 800a3e2:	681b      	ldr	r3, [r3, #0]
 800a3e4:	4a33      	ldr	r2, [pc, #204]	@ (800a4b4 <DMA_CalcBaseAndBitshift+0x140>)
 800a3e6:	4293      	cmp	r3, r2
 800a3e8:	d018      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a3ea:	687b      	ldr	r3, [r7, #4]
 800a3ec:	681b      	ldr	r3, [r3, #0]
 800a3ee:	4a32      	ldr	r2, [pc, #200]	@ (800a4b8 <DMA_CalcBaseAndBitshift+0x144>)
 800a3f0:	4293      	cmp	r3, r2
 800a3f2:	d013      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a3f4:	687b      	ldr	r3, [r7, #4]
 800a3f6:	681b      	ldr	r3, [r3, #0]
 800a3f8:	4a30      	ldr	r2, [pc, #192]	@ (800a4bc <DMA_CalcBaseAndBitshift+0x148>)
 800a3fa:	4293      	cmp	r3, r2
 800a3fc:	d00e      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a3fe:	687b      	ldr	r3, [r7, #4]
 800a400:	681b      	ldr	r3, [r3, #0]
 800a402:	4a2f      	ldr	r2, [pc, #188]	@ (800a4c0 <DMA_CalcBaseAndBitshift+0x14c>)
 800a404:	4293      	cmp	r3, r2
 800a406:	d009      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a408:	687b      	ldr	r3, [r7, #4]
 800a40a:	681b      	ldr	r3, [r3, #0]
 800a40c:	4a2d      	ldr	r2, [pc, #180]	@ (800a4c4 <DMA_CalcBaseAndBitshift+0x150>)
 800a40e:	4293      	cmp	r3, r2
 800a410:	d004      	beq.n	800a41c <DMA_CalcBaseAndBitshift+0xa8>
 800a412:	687b      	ldr	r3, [r7, #4]
 800a414:	681b      	ldr	r3, [r3, #0]
 800a416:	4a2c      	ldr	r2, [pc, #176]	@ (800a4c8 <DMA_CalcBaseAndBitshift+0x154>)
 800a418:	4293      	cmp	r3, r2
 800a41a:	d101      	bne.n	800a420 <DMA_CalcBaseAndBitshift+0xac>
 800a41c:	2301      	movs	r3, #1
 800a41e:	e000      	b.n	800a422 <DMA_CalcBaseAndBitshift+0xae>
 800a420:	2300      	movs	r3, #0
 800a422:	2b00      	cmp	r3, #0
 800a424:	d024      	beq.n	800a470 <DMA_CalcBaseAndBitshift+0xfc>
  {
    uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
 800a426:	687b      	ldr	r3, [r7, #4]
 800a428:	681b      	ldr	r3, [r3, #0]
 800a42a:	b2db      	uxtb	r3, r3
 800a42c:	3b10      	subs	r3, #16
 800a42e:	4a27      	ldr	r2, [pc, #156]	@ (800a4cc <DMA_CalcBaseAndBitshift+0x158>)
 800a430:	fba2 2303 	umull	r2, r3, r2, r3
 800a434:	091b      	lsrs	r3, r3, #4
 800a436:	60fb      	str	r3, [r7, #12]

    /* lookup table for necessary bitshift of flags within status registers */
    static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
    hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
 800a438:	68fb      	ldr	r3, [r7, #12]
 800a43a:	f003 0307 	and.w	r3, r3, #7
 800a43e:	4a24      	ldr	r2, [pc, #144]	@ (800a4d0 <DMA_CalcBaseAndBitshift+0x15c>)
 800a440:	5cd3      	ldrb	r3, [r2, r3]
 800a442:	461a      	mov	r2, r3
 800a444:	687b      	ldr	r3, [r7, #4]
 800a446:	65da      	str	r2, [r3, #92]	@ 0x5c

    if (stream_number > 3U)
 800a448:	68fb      	ldr	r3, [r7, #12]
 800a44a:	2b03      	cmp	r3, #3
 800a44c:	d908      	bls.n	800a460 <DMA_CalcBaseAndBitshift+0xec>
    {
      /* return pointer to HISR and HIFCR */
      hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U);
 800a44e:	687b      	ldr	r3, [r7, #4]
 800a450:	681b      	ldr	r3, [r3, #0]
 800a452:	461a      	mov	r2, r3
 800a454:	4b1f      	ldr	r3, [pc, #124]	@ (800a4d4 <DMA_CalcBaseAndBitshift+0x160>)
 800a456:	4013      	ands	r3, r2
 800a458:	1d1a      	adds	r2, r3, #4
 800a45a:	687b      	ldr	r3, [r7, #4]
 800a45c:	659a      	str	r2, [r3, #88]	@ 0x58
 800a45e:	e00d      	b.n	800a47c <DMA_CalcBaseAndBitshift+0x108>
    }
    else
    {
      /* return pointer to LISR and LIFCR */
      hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU));
 800a460:	687b      	ldr	r3, [r7, #4]
 800a462:	681b      	ldr	r3, [r3, #0]
 800a464:	461a      	mov	r2, r3
 800a466:	4b1b      	ldr	r3, [pc, #108]	@ (800a4d4 <DMA_CalcBaseAndBitshift+0x160>)
 800a468:	4013      	ands	r3, r2
 800a46a:	687a      	ldr	r2, [r7, #4]
 800a46c:	6593      	str	r3, [r2, #88]	@ 0x58
 800a46e:	e005      	b.n	800a47c <DMA_CalcBaseAndBitshift+0x108>
    }
  }
  else /* BDMA instance(s) */
  {
    /* return pointer to ISR and IFCR */
    hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU));
 800a470:	687b      	ldr	r3, [r7, #4]
 800a472:	681b      	ldr	r3, [r3, #0]
 800a474:	f023 02ff 	bic.w	r2, r3, #255	@ 0xff
 800a478:	687b      	ldr	r3, [r7, #4]
 800a47a:	659a      	str	r2, [r3, #88]	@ 0x58
  }

  return hdma->StreamBaseAddress;
 800a47c:	687b      	ldr	r3, [r7, #4]
 800a47e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
}
 800a480:	4618      	mov	r0, r3
 800a482:	3714      	adds	r7, #20
 800a484:	46bd      	mov	sp, r7
 800a486:	f85d 7b04 	ldr.w	r7, [sp], #4
 800a48a:	4770      	bx	lr
 800a48c:	40020010 	.word	0x40020010
 800a490:	40020028 	.word	0x40020028
 800a494:	40020040 	.word	0x40020040
 800a498:	40020058 	.word	0x40020058
 800a49c:	40020070 	.word	0x40020070
 800a4a0:	40020088 	.word	0x40020088
 800a4a4:	400200a0 	.word	0x400200a0
 800a4a8:	400200b8 	.word	0x400200b8
 800a4ac:	40020410 	.word	0x40020410
 800a4b0:	40020428 	.word	0x40020428
 800a4b4:	40020440 	.word	0x40020440
 800a4b8:	40020458 	.word	0x40020458
 800a4bc:	40020470 	.word	0x40020470
 800a4c0:	40020488 	.word	0x40020488
 800a4c4:	400204a0 	.word	0x400204a0
 800a4c8:	400204b8 	.word	0x400204b8
 800a4cc:	aaaaaaab 	.word	0xaaaaaaab
 800a4d0:	08018a38 	.word	0x08018a38
 800a4d4:	fffffc00 	.word	0xfffffc00

0800a4d8 <DMA_CheckFifoParam>:
  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
  *                     the configuration information for the specified DMA Stream.
  * @retval HAL status
  */
static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{
 800a4d8:	b480      	push	{r7}
 800a4da:	b085      	sub	sp, #20
 800a4dc:	af00      	add	r7, sp, #0
 800a4de:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 800a4e0:	2300      	movs	r3, #0
 800a4e2:	73fb      	strb	r3, [r7, #15]

  /* Memory Data size equal to Byte */
  if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
 800a4e4:	687b      	ldr	r3, [r7, #4]
 800a4e6:	699b      	ldr	r3, [r3, #24]
 800a4e8:	2b00      	cmp	r3, #0
 800a4ea:	d120      	bne.n	800a52e <DMA_CheckFifoParam+0x56>
  {
    switch (hdma->Init.FIFOThreshold)
 800a4ec:	687b      	ldr	r3, [r7, #4]
 800a4ee:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800a4f0:	2b03      	cmp	r3, #3
 800a4f2:	d858      	bhi.n	800a5a6 <DMA_CheckFifoParam+0xce>
 800a4f4:	a201      	add	r2, pc, #4	@ (adr r2, 800a4fc <DMA_CheckFifoParam+0x24>)
 800a4f6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800a4fa:	bf00      	nop
 800a4fc:	0800a50d 	.word	0x0800a50d
 800a500:	0800a51f 	.word	0x0800a51f
 800a504:	0800a50d 	.word	0x0800a50d
 800a508:	0800a5a7 	.word	0x0800a5a7
    {
      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:

        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
 800a50c:	687b      	ldr	r3, [r7, #4]
 800a50e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800a510:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 800a514:	2b00      	cmp	r3, #0
 800a516:	d048      	beq.n	800a5aa <DMA_CheckFifoParam+0xd2>
        {
          status = HAL_ERROR;
 800a518:	2301      	movs	r3, #1
 800a51a:	73fb      	strb	r3, [r7, #15]
        }
        break;
 800a51c:	e045      	b.n	800a5aa <DMA_CheckFifoParam+0xd2>

      case DMA_FIFO_THRESHOLD_HALFFULL:
        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
 800a51e:	687b      	ldr	r3, [r7, #4]
 800a520:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800a522:	f1b3 7fc0 	cmp.w	r3, #25165824	@ 0x1800000
 800a526:	d142      	bne.n	800a5ae <DMA_CheckFifoParam+0xd6>
        {
          status = HAL_ERROR;
 800a528:	2301      	movs	r3, #1
 800a52a:	73fb      	strb	r3, [r7, #15]
        }
        break;
 800a52c:	e03f      	b.n	800a5ae <DMA_CheckFifoParam+0xd6>
        break;
    }
  }

  /* Memory Data size equal to Half-Word */
  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
 800a52e:	687b      	ldr	r3, [r7, #4]
 800a530:	699b      	ldr	r3, [r3, #24]
 800a532:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800a536:	d123      	bne.n	800a580 <DMA_CheckFifoParam+0xa8>
  {
    switch (hdma->Init.FIFOThreshold)
 800a538:	687b      	ldr	r3, [r7, #4]
 800a53a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800a53c:	2b03      	cmp	r3, #3
 800a53e:	d838      	bhi.n	800a5b2 <DMA_CheckFifoParam+0xda>
 800a540:	a201      	add	r2, pc, #4	@ (adr r2, 800a548 <DMA_CheckFifoParam+0x70>)
 800a542:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800a546:	bf00      	nop
 800a548:	0800a559 	.word	0x0800a559
 800a54c:	0800a55f 	.word	0x0800a55f
 800a550:	0800a559 	.word	0x0800a559
 800a554:	0800a571 	.word	0x0800a571
    {
      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
        status = HAL_ERROR;
 800a558:	2301      	movs	r3, #1
 800a55a:	73fb      	strb	r3, [r7, #15]
        break;
 800a55c:	e030      	b.n	800a5c0 <DMA_CheckFifoParam+0xe8>

      case DMA_FIFO_THRESHOLD_HALFFULL:
        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
 800a55e:	687b      	ldr	r3, [r7, #4]
 800a560:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800a562:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 800a566:	2b00      	cmp	r3, #0
 800a568:	d025      	beq.n	800a5b6 <DMA_CheckFifoParam+0xde>
        {
          status = HAL_ERROR;
 800a56a:	2301      	movs	r3, #1
 800a56c:	73fb      	strb	r3, [r7, #15]
        }
        break;
 800a56e:	e022      	b.n	800a5b6 <DMA_CheckFifoParam+0xde>

      case DMA_FIFO_THRESHOLD_FULL:
        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
 800a570:	687b      	ldr	r3, [r7, #4]
 800a572:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800a574:	f1b3 7fc0 	cmp.w	r3, #25165824	@ 0x1800000
 800a578:	d11f      	bne.n	800a5ba <DMA_CheckFifoParam+0xe2>
        {
          status = HAL_ERROR;
 800a57a:	2301      	movs	r3, #1
 800a57c:	73fb      	strb	r3, [r7, #15]
        }
        break;
 800a57e:	e01c      	b.n	800a5ba <DMA_CheckFifoParam+0xe2>
  }

  /* Memory Data size equal to Word */
  else
  {
    switch (hdma->Init.FIFOThreshold)
 800a580:	687b      	ldr	r3, [r7, #4]
 800a582:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800a584:	2b02      	cmp	r3, #2
 800a586:	d902      	bls.n	800a58e <DMA_CheckFifoParam+0xb6>
 800a588:	2b03      	cmp	r3, #3
 800a58a:	d003      	beq.n	800a594 <DMA_CheckFifoParam+0xbc>
          status = HAL_ERROR;
        }
    break;

      default:
        break;
 800a58c:	e018      	b.n	800a5c0 <DMA_CheckFifoParam+0xe8>
        status = HAL_ERROR;
 800a58e:	2301      	movs	r3, #1
 800a590:	73fb      	strb	r3, [r7, #15]
        break;
 800a592:	e015      	b.n	800a5c0 <DMA_CheckFifoParam+0xe8>
        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
 800a594:	687b      	ldr	r3, [r7, #4]
 800a596:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800a598:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 800a59c:	2b00      	cmp	r3, #0
 800a59e:	d00e      	beq.n	800a5be <DMA_CheckFifoParam+0xe6>
          status = HAL_ERROR;
 800a5a0:	2301      	movs	r3, #1
 800a5a2:	73fb      	strb	r3, [r7, #15]
    break;
 800a5a4:	e00b      	b.n	800a5be <DMA_CheckFifoParam+0xe6>
        break;
 800a5a6:	bf00      	nop
 800a5a8:	e00a      	b.n	800a5c0 <DMA_CheckFifoParam+0xe8>
        break;
 800a5aa:	bf00      	nop
 800a5ac:	e008      	b.n	800a5c0 <DMA_CheckFifoParam+0xe8>
        break;
 800a5ae:	bf00      	nop
 800a5b0:	e006      	b.n	800a5c0 <DMA_CheckFifoParam+0xe8>
        break;
 800a5b2:	bf00      	nop
 800a5b4:	e004      	b.n	800a5c0 <DMA_CheckFifoParam+0xe8>
        break;
 800a5b6:	bf00      	nop
 800a5b8:	e002      	b.n	800a5c0 <DMA_CheckFifoParam+0xe8>
        break;
 800a5ba:	bf00      	nop
 800a5bc:	e000      	b.n	800a5c0 <DMA_CheckFifoParam+0xe8>
    break;
 800a5be:	bf00      	nop
    }
  }

  return status;
 800a5c0:	7bfb      	ldrb	r3, [r7, #15]
}
 800a5c2:	4618      	mov	r0, r3
 800a5c4:	3714      	adds	r7, #20
 800a5c6:	46bd      	mov	sp, r7
 800a5c8:	f85d 7b04 	ldr.w	r7, [sp], #4
 800a5cc:	4770      	bx	lr
 800a5ce:	bf00      	nop

0800a5d0 <DMA_CalcDMAMUXChannelBaseAndMask>:
  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
  *                     the configuration information for the specified DMA Stream.
  * @retval HAL status
  */
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
{
 800a5d0:	b480      	push	{r7}
 800a5d2:	b085      	sub	sp, #20
 800a5d4:	af00      	add	r7, sp, #0
 800a5d6:	6078      	str	r0, [r7, #4]
  uint32_t stream_number;
  uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance);
 800a5d8:	687b      	ldr	r3, [r7, #4]
 800a5da:	681b      	ldr	r3, [r3, #0]
 800a5dc:	60bb      	str	r3, [r7, #8]

  if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
 800a5de:	687b      	ldr	r3, [r7, #4]
 800a5e0:	681b      	ldr	r3, [r3, #0]
 800a5e2:	4a38      	ldr	r2, [pc, #224]	@ (800a6c4 <DMA_CalcDMAMUXChannelBaseAndMask+0xf4>)
 800a5e4:	4293      	cmp	r3, r2
 800a5e6:	d022      	beq.n	800a62e <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 800a5e8:	687b      	ldr	r3, [r7, #4]
 800a5ea:	681b      	ldr	r3, [r3, #0]
 800a5ec:	4a36      	ldr	r2, [pc, #216]	@ (800a6c8 <DMA_CalcDMAMUXChannelBaseAndMask+0xf8>)
 800a5ee:	4293      	cmp	r3, r2
 800a5f0:	d01d      	beq.n	800a62e <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 800a5f2:	687b      	ldr	r3, [r7, #4]
 800a5f4:	681b      	ldr	r3, [r3, #0]
 800a5f6:	4a35      	ldr	r2, [pc, #212]	@ (800a6cc <DMA_CalcDMAMUXChannelBaseAndMask+0xfc>)
 800a5f8:	4293      	cmp	r3, r2
 800a5fa:	d018      	beq.n	800a62e <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 800a5fc:	687b      	ldr	r3, [r7, #4]
 800a5fe:	681b      	ldr	r3, [r3, #0]
 800a600:	4a33      	ldr	r2, [pc, #204]	@ (800a6d0 <DMA_CalcDMAMUXChannelBaseAndMask+0x100>)
 800a602:	4293      	cmp	r3, r2
 800a604:	d013      	beq.n	800a62e <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 800a606:	687b      	ldr	r3, [r7, #4]
 800a608:	681b      	ldr	r3, [r3, #0]
 800a60a:	4a32      	ldr	r2, [pc, #200]	@ (800a6d4 <DMA_CalcDMAMUXChannelBaseAndMask+0x104>)
 800a60c:	4293      	cmp	r3, r2
 800a60e:	d00e      	beq.n	800a62e <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 800a610:	687b      	ldr	r3, [r7, #4]
 800a612:	681b      	ldr	r3, [r3, #0]
 800a614:	4a30      	ldr	r2, [pc, #192]	@ (800a6d8 <DMA_CalcDMAMUXChannelBaseAndMask+0x108>)
 800a616:	4293      	cmp	r3, r2
 800a618:	d009      	beq.n	800a62e <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 800a61a:	687b      	ldr	r3, [r7, #4]
 800a61c:	681b      	ldr	r3, [r3, #0]
 800a61e:	4a2f      	ldr	r2, [pc, #188]	@ (800a6dc <DMA_CalcDMAMUXChannelBaseAndMask+0x10c>)
 800a620:	4293      	cmp	r3, r2
 800a622:	d004      	beq.n	800a62e <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
 800a624:	687b      	ldr	r3, [r7, #4]
 800a626:	681b      	ldr	r3, [r3, #0]
 800a628:	4a2d      	ldr	r2, [pc, #180]	@ (800a6e0 <DMA_CalcDMAMUXChannelBaseAndMask+0x110>)
 800a62a:	4293      	cmp	r3, r2
 800a62c:	d101      	bne.n	800a632 <DMA_CalcDMAMUXChannelBaseAndMask+0x62>
 800a62e:	2301      	movs	r3, #1
 800a630:	e000      	b.n	800a634 <DMA_CalcDMAMUXChannelBaseAndMask+0x64>
 800a632:	2300      	movs	r3, #0
 800a634:	2b00      	cmp	r3, #0
 800a636:	d01a      	beq.n	800a66e <DMA_CalcDMAMUXChannelBaseAndMask+0x9e>
  {
    /* BDMA Channels are connected to DMAMUX2 channels */
    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U;
 800a638:	687b      	ldr	r3, [r7, #4]
 800a63a:	681b      	ldr	r3, [r3, #0]
 800a63c:	b2db      	uxtb	r3, r3
 800a63e:	3b08      	subs	r3, #8
 800a640:	4a28      	ldr	r2, [pc, #160]	@ (800a6e4 <DMA_CalcDMAMUXChannelBaseAndMask+0x114>)
 800a642:	fba2 2303 	umull	r2, r3, r2, r3
 800a646:	091b      	lsrs	r3, r3, #4
 800a648:	60fb      	str	r3, [r7, #12]
    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
 800a64a:	68fa      	ldr	r2, [r7, #12]
 800a64c:	4b26      	ldr	r3, [pc, #152]	@ (800a6e8 <DMA_CalcDMAMUXChannelBaseAndMask+0x118>)
 800a64e:	4413      	add	r3, r2
 800a650:	009b      	lsls	r3, r3, #2
 800a652:	461a      	mov	r2, r3
 800a654:	687b      	ldr	r3, [r7, #4]
 800a656:	661a      	str	r2, [r3, #96]	@ 0x60
    hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;
 800a658:	687b      	ldr	r3, [r7, #4]
 800a65a:	4a24      	ldr	r2, [pc, #144]	@ (800a6ec <DMA_CalcDMAMUXChannelBaseAndMask+0x11c>)
 800a65c:	665a      	str	r2, [r3, #100]	@ 0x64
    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
 800a65e:	68fb      	ldr	r3, [r7, #12]
 800a660:	f003 031f 	and.w	r3, r3, #31
 800a664:	2201      	movs	r2, #1
 800a666:	409a      	lsls	r2, r3
 800a668:	687b      	ldr	r3, [r7, #4]
 800a66a:	669a      	str	r2, [r3, #104]	@ 0x68
    }
    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
    hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
  }
}
 800a66c:	e024      	b.n	800a6b8 <DMA_CalcDMAMUXChannelBaseAndMask+0xe8>
    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
 800a66e:	687b      	ldr	r3, [r7, #4]
 800a670:	681b      	ldr	r3, [r3, #0]
 800a672:	b2db      	uxtb	r3, r3
 800a674:	3b10      	subs	r3, #16
 800a676:	4a1e      	ldr	r2, [pc, #120]	@ (800a6f0 <DMA_CalcDMAMUXChannelBaseAndMask+0x120>)
 800a678:	fba2 2303 	umull	r2, r3, r2, r3
 800a67c:	091b      	lsrs	r3, r3, #4
 800a67e:	60fb      	str	r3, [r7, #12]
    if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
 800a680:	68bb      	ldr	r3, [r7, #8]
 800a682:	4a1c      	ldr	r2, [pc, #112]	@ (800a6f4 <DMA_CalcDMAMUXChannelBaseAndMask+0x124>)
 800a684:	4293      	cmp	r3, r2
 800a686:	d806      	bhi.n	800a696 <DMA_CalcDMAMUXChannelBaseAndMask+0xc6>
 800a688:	68bb      	ldr	r3, [r7, #8]
 800a68a:	4a1b      	ldr	r2, [pc, #108]	@ (800a6f8 <DMA_CalcDMAMUXChannelBaseAndMask+0x128>)
 800a68c:	4293      	cmp	r3, r2
 800a68e:	d902      	bls.n	800a696 <DMA_CalcDMAMUXChannelBaseAndMask+0xc6>
      stream_number += 8U;
 800a690:	68fb      	ldr	r3, [r7, #12]
 800a692:	3308      	adds	r3, #8
 800a694:	60fb      	str	r3, [r7, #12]
    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
 800a696:	68fa      	ldr	r2, [r7, #12]
 800a698:	4b18      	ldr	r3, [pc, #96]	@ (800a6fc <DMA_CalcDMAMUXChannelBaseAndMask+0x12c>)
 800a69a:	4413      	add	r3, r2
 800a69c:	009b      	lsls	r3, r3, #2
 800a69e:	461a      	mov	r2, r3
 800a6a0:	687b      	ldr	r3, [r7, #4]
 800a6a2:	661a      	str	r2, [r3, #96]	@ 0x60
    hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
 800a6a4:	687b      	ldr	r3, [r7, #4]
 800a6a6:	4a16      	ldr	r2, [pc, #88]	@ (800a700 <DMA_CalcDMAMUXChannelBaseAndMask+0x130>)
 800a6a8:	665a      	str	r2, [r3, #100]	@ 0x64
    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
 800a6aa:	68fb      	ldr	r3, [r7, #12]
 800a6ac:	f003 031f 	and.w	r3, r3, #31
 800a6b0:	2201      	movs	r2, #1
 800a6b2:	409a      	lsls	r2, r3
 800a6b4:	687b      	ldr	r3, [r7, #4]
 800a6b6:	669a      	str	r2, [r3, #104]	@ 0x68
}
 800a6b8:	bf00      	nop
 800a6ba:	3714      	adds	r7, #20
 800a6bc:	46bd      	mov	sp, r7
 800a6be:	f85d 7b04 	ldr.w	r7, [sp], #4
 800a6c2:	4770      	bx	lr
 800a6c4:	58025408 	.word	0x58025408
 800a6c8:	5802541c 	.word	0x5802541c
 800a6cc:	58025430 	.word	0x58025430
 800a6d0:	58025444 	.word	0x58025444
 800a6d4:	58025458 	.word	0x58025458
 800a6d8:	5802546c 	.word	0x5802546c
 800a6dc:	58025480 	.word	0x58025480
 800a6e0:	58025494 	.word	0x58025494
 800a6e4:	cccccccd 	.word	0xcccccccd
 800a6e8:	16009600 	.word	0x16009600
 800a6ec:	58025880 	.word	0x58025880
 800a6f0:	aaaaaaab 	.word	0xaaaaaaab
 800a6f4:	400204b8 	.word	0x400204b8
 800a6f8:	4002040f 	.word	0x4002040f
 800a6fc:	10008200 	.word	0x10008200
 800a700:	40020880 	.word	0x40020880

0800a704 <DMA_CalcDMAMUXRequestGenBaseAndMask>:
  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
  *                     the configuration information for the specified DMA Stream.
  * @retval HAL status
  */
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
{
 800a704:	b480      	push	{r7}
 800a706:	b085      	sub	sp, #20
 800a708:	af00      	add	r7, sp, #0
 800a70a:	6078      	str	r0, [r7, #4]
  uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
 800a70c:	687b      	ldr	r3, [r7, #4]
 800a70e:	685b      	ldr	r3, [r3, #4]
 800a710:	b2db      	uxtb	r3, r3
 800a712:	60fb      	str	r3, [r7, #12]

  if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
 800a714:	68fb      	ldr	r3, [r7, #12]
 800a716:	2b00      	cmp	r3, #0
 800a718:	d04a      	beq.n	800a7b0 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xac>
 800a71a:	68fb      	ldr	r3, [r7, #12]
 800a71c:	2b08      	cmp	r3, #8
 800a71e:	d847      	bhi.n	800a7b0 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xac>
  {
    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
 800a720:	687b      	ldr	r3, [r7, #4]
 800a722:	681b      	ldr	r3, [r3, #0]
 800a724:	4a25      	ldr	r2, [pc, #148]	@ (800a7bc <DMA_CalcDMAMUXRequestGenBaseAndMask+0xb8>)
 800a726:	4293      	cmp	r3, r2
 800a728:	d022      	beq.n	800a770 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 800a72a:	687b      	ldr	r3, [r7, #4]
 800a72c:	681b      	ldr	r3, [r3, #0]
 800a72e:	4a24      	ldr	r2, [pc, #144]	@ (800a7c0 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xbc>)
 800a730:	4293      	cmp	r3, r2
 800a732:	d01d      	beq.n	800a770 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 800a734:	687b      	ldr	r3, [r7, #4]
 800a736:	681b      	ldr	r3, [r3, #0]
 800a738:	4a22      	ldr	r2, [pc, #136]	@ (800a7c4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xc0>)
 800a73a:	4293      	cmp	r3, r2
 800a73c:	d018      	beq.n	800a770 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 800a73e:	687b      	ldr	r3, [r7, #4]
 800a740:	681b      	ldr	r3, [r3, #0]
 800a742:	4a21      	ldr	r2, [pc, #132]	@ (800a7c8 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xc4>)
 800a744:	4293      	cmp	r3, r2
 800a746:	d013      	beq.n	800a770 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 800a748:	687b      	ldr	r3, [r7, #4]
 800a74a:	681b      	ldr	r3, [r3, #0]
 800a74c:	4a1f      	ldr	r2, [pc, #124]	@ (800a7cc <DMA_CalcDMAMUXRequestGenBaseAndMask+0xc8>)
 800a74e:	4293      	cmp	r3, r2
 800a750:	d00e      	beq.n	800a770 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 800a752:	687b      	ldr	r3, [r7, #4]
 800a754:	681b      	ldr	r3, [r3, #0]
 800a756:	4a1e      	ldr	r2, [pc, #120]	@ (800a7d0 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xcc>)
 800a758:	4293      	cmp	r3, r2
 800a75a:	d009      	beq.n	800a770 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 800a75c:	687b      	ldr	r3, [r7, #4]
 800a75e:	681b      	ldr	r3, [r3, #0]
 800a760:	4a1c      	ldr	r2, [pc, #112]	@ (800a7d4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xd0>)
 800a762:	4293      	cmp	r3, r2
 800a764:	d004      	beq.n	800a770 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
 800a766:	687b      	ldr	r3, [r7, #4]
 800a768:	681b      	ldr	r3, [r3, #0]
 800a76a:	4a1b      	ldr	r2, [pc, #108]	@ (800a7d8 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xd4>)
 800a76c:	4293      	cmp	r3, r2
 800a76e:	d101      	bne.n	800a774 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x70>
 800a770:	2301      	movs	r3, #1
 800a772:	e000      	b.n	800a776 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x72>
 800a774:	2300      	movs	r3, #0
 800a776:	2b00      	cmp	r3, #0
 800a778:	d00a      	beq.n	800a790 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x8c>
    {
      /* BDMA Channels are connected to DMAMUX2 request generator blocks */
      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
 800a77a:	68fa      	ldr	r2, [r7, #12]
 800a77c:	4b17      	ldr	r3, [pc, #92]	@ (800a7dc <DMA_CalcDMAMUXRequestGenBaseAndMask+0xd8>)
 800a77e:	4413      	add	r3, r2
 800a780:	009b      	lsls	r3, r3, #2
 800a782:	461a      	mov	r2, r3
 800a784:	687b      	ldr	r3, [r7, #4]
 800a786:	66da      	str	r2, [r3, #108]	@ 0x6c

      hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;
 800a788:	687b      	ldr	r3, [r7, #4]
 800a78a:	4a15      	ldr	r2, [pc, #84]	@ (800a7e0 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xdc>)
 800a78c:	671a      	str	r2, [r3, #112]	@ 0x70
 800a78e:	e009      	b.n	800a7a4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xa0>
    }
    else
    {
      /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */
      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
 800a790:	68fa      	ldr	r2, [r7, #12]
 800a792:	4b14      	ldr	r3, [pc, #80]	@ (800a7e4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xe0>)
 800a794:	4413      	add	r3, r2
 800a796:	009b      	lsls	r3, r3, #2
 800a798:	461a      	mov	r2, r3
 800a79a:	687b      	ldr	r3, [r7, #4]
 800a79c:	66da      	str	r2, [r3, #108]	@ 0x6c

      hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
 800a79e:	687b      	ldr	r3, [r7, #4]
 800a7a0:	4a11      	ldr	r2, [pc, #68]	@ (800a7e8 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xe4>)
 800a7a2:	671a      	str	r2, [r3, #112]	@ 0x70
    }

    hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);
 800a7a4:	68fb      	ldr	r3, [r7, #12]
 800a7a6:	3b01      	subs	r3, #1
 800a7a8:	2201      	movs	r2, #1
 800a7aa:	409a      	lsls	r2, r3
 800a7ac:	687b      	ldr	r3, [r7, #4]
 800a7ae:	675a      	str	r2, [r3, #116]	@ 0x74
  }
}
 800a7b0:	bf00      	nop
 800a7b2:	3714      	adds	r7, #20
 800a7b4:	46bd      	mov	sp, r7
 800a7b6:	f85d 7b04 	ldr.w	r7, [sp], #4
 800a7ba:	4770      	bx	lr
 800a7bc:	58025408 	.word	0x58025408
 800a7c0:	5802541c 	.word	0x5802541c
 800a7c4:	58025430 	.word	0x58025430
 800a7c8:	58025444 	.word	0x58025444
 800a7cc:	58025458 	.word	0x58025458
 800a7d0:	5802546c 	.word	0x5802546c
 800a7d4:	58025480 	.word	0x58025480
 800a7d8:	58025494 	.word	0x58025494
 800a7dc:	1600963f 	.word	0x1600963f
 800a7e0:	58025940 	.word	0x58025940
 800a7e4:	1000823f 	.word	0x1000823f
 800a7e8:	40020940 	.word	0x40020940

0800a7ec <HAL_GPIO_Init>:
  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 800a7ec:	b480      	push	{r7}
 800a7ee:	b089      	sub	sp, #36	@ 0x24
 800a7f0:	af00      	add	r7, sp, #0
 800a7f2:	6078      	str	r0, [r7, #4]
 800a7f4:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00U;
 800a7f6:	2300      	movs	r3, #0
 800a7f8:	61fb      	str	r3, [r7, #28]
  EXTI_Core_TypeDef *EXTI_CurrentCPU;

#if defined(DUAL_CORE) && defined(CORE_CM4)
  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
#else
  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
 800a7fa:	4b89      	ldr	r3, [pc, #548]	@ (800aa20 <HAL_GPIO_Init+0x234>)
 800a7fc:	617b      	str	r3, [r7, #20]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0x00U)
 800a7fe:	e194      	b.n	800ab2a <HAL_GPIO_Init+0x33e>
  {
    /* Get current io position */
    iocurrent = (GPIO_Init->Pin) & (1UL << position);
 800a800:	683b      	ldr	r3, [r7, #0]
 800a802:	681a      	ldr	r2, [r3, #0]
 800a804:	2101      	movs	r1, #1
 800a806:	69fb      	ldr	r3, [r7, #28]
 800a808:	fa01 f303 	lsl.w	r3, r1, r3
 800a80c:	4013      	ands	r3, r2
 800a80e:	613b      	str	r3, [r7, #16]

    if (iocurrent != 0x00U)
 800a810:	693b      	ldr	r3, [r7, #16]
 800a812:	2b00      	cmp	r3, #0
 800a814:	f000 8186 	beq.w	800ab24 <HAL_GPIO_Init+0x338>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
 800a818:	683b      	ldr	r3, [r7, #0]
 800a81a:	685b      	ldr	r3, [r3, #4]
 800a81c:	f003 0303 	and.w	r3, r3, #3
 800a820:	2b01      	cmp	r3, #1
 800a822:	d005      	beq.n	800a830 <HAL_GPIO_Init+0x44>
 800a824:	683b      	ldr	r3, [r7, #0]
 800a826:	685b      	ldr	r3, [r3, #4]
 800a828:	f003 0303 	and.w	r3, r3, #3
 800a82c:	2b02      	cmp	r3, #2
 800a82e:	d130      	bne.n	800a892 <HAL_GPIO_Init+0xa6>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));

        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR;
 800a830:	687b      	ldr	r3, [r7, #4]
 800a832:	689b      	ldr	r3, [r3, #8]
 800a834:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
 800a836:	69fb      	ldr	r3, [r7, #28]
 800a838:	005b      	lsls	r3, r3, #1
 800a83a:	2203      	movs	r2, #3
 800a83c:	fa02 f303 	lsl.w	r3, r2, r3
 800a840:	43db      	mvns	r3, r3
 800a842:	69ba      	ldr	r2, [r7, #24]
 800a844:	4013      	ands	r3, r2
 800a846:	61bb      	str	r3, [r7, #24]
        temp |= (GPIO_Init->Speed << (position * 2U));
 800a848:	683b      	ldr	r3, [r7, #0]
 800a84a:	68da      	ldr	r2, [r3, #12]
 800a84c:	69fb      	ldr	r3, [r7, #28]
 800a84e:	005b      	lsls	r3, r3, #1
 800a850:	fa02 f303 	lsl.w	r3, r2, r3
 800a854:	69ba      	ldr	r2, [r7, #24]
 800a856:	4313      	orrs	r3, r2
 800a858:	61bb      	str	r3, [r7, #24]
        GPIOx->OSPEEDR = temp;
 800a85a:	687b      	ldr	r3, [r7, #4]
 800a85c:	69ba      	ldr	r2, [r7, #24]
 800a85e:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 800a860:	687b      	ldr	r3, [r7, #4]
 800a862:	685b      	ldr	r3, [r3, #4]
 800a864:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OTYPER_OT0 << position) ;
 800a866:	2201      	movs	r2, #1
 800a868:	69fb      	ldr	r3, [r7, #28]
 800a86a:	fa02 f303 	lsl.w	r3, r2, r3
 800a86e:	43db      	mvns	r3, r3
 800a870:	69ba      	ldr	r2, [r7, #24]
 800a872:	4013      	ands	r3, r2
 800a874:	61bb      	str	r3, [r7, #24]
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 800a876:	683b      	ldr	r3, [r7, #0]
 800a878:	685b      	ldr	r3, [r3, #4]
 800a87a:	091b      	lsrs	r3, r3, #4
 800a87c:	f003 0201 	and.w	r2, r3, #1
 800a880:	69fb      	ldr	r3, [r7, #28]
 800a882:	fa02 f303 	lsl.w	r3, r2, r3
 800a886:	69ba      	ldr	r2, [r7, #24]
 800a888:	4313      	orrs	r3, r2
 800a88a:	61bb      	str	r3, [r7, #24]
        GPIOx->OTYPER = temp;
 800a88c:	687b      	ldr	r3, [r7, #4]
 800a88e:	69ba      	ldr	r2, [r7, #24]
 800a890:	605a      	str	r2, [r3, #4]
      }

      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 800a892:	683b      	ldr	r3, [r7, #0]
 800a894:	685b      	ldr	r3, [r3, #4]
 800a896:	f003 0303 	and.w	r3, r3, #3
 800a89a:	2b03      	cmp	r3, #3
 800a89c:	d017      	beq.n	800a8ce <HAL_GPIO_Init+0xe2>
      {
       /* Check the Pull parameter */
       assert_param(IS_GPIO_PULL(GPIO_Init->Pull));

      /* Activate the Pull-up or Pull down resistor for the current IO */
      temp = GPIOx->PUPDR;
 800a89e:	687b      	ldr	r3, [r7, #4]
 800a8a0:	68db      	ldr	r3, [r3, #12]
 800a8a2:	61bb      	str	r3, [r7, #24]
      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
 800a8a4:	69fb      	ldr	r3, [r7, #28]
 800a8a6:	005b      	lsls	r3, r3, #1
 800a8a8:	2203      	movs	r2, #3
 800a8aa:	fa02 f303 	lsl.w	r3, r2, r3
 800a8ae:	43db      	mvns	r3, r3
 800a8b0:	69ba      	ldr	r2, [r7, #24]
 800a8b2:	4013      	ands	r3, r2
 800a8b4:	61bb      	str	r3, [r7, #24]
      temp |= ((GPIO_Init->Pull) << (position * 2U));
 800a8b6:	683b      	ldr	r3, [r7, #0]
 800a8b8:	689a      	ldr	r2, [r3, #8]
 800a8ba:	69fb      	ldr	r3, [r7, #28]
 800a8bc:	005b      	lsls	r3, r3, #1
 800a8be:	fa02 f303 	lsl.w	r3, r2, r3
 800a8c2:	69ba      	ldr	r2, [r7, #24]
 800a8c4:	4313      	orrs	r3, r2
 800a8c6:	61bb      	str	r3, [r7, #24]
      GPIOx->PUPDR = temp;
 800a8c8:	687b      	ldr	r3, [r7, #4]
 800a8ca:	69ba      	ldr	r2, [r7, #24]
 800a8cc:	60da      	str	r2, [r3, #12]
      }

      /* In case of Alternate function mode selection */
      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 800a8ce:	683b      	ldr	r3, [r7, #0]
 800a8d0:	685b      	ldr	r3, [r3, #4]
 800a8d2:	f003 0303 	and.w	r3, r3, #3
 800a8d6:	2b02      	cmp	r3, #2
 800a8d8:	d123      	bne.n	800a922 <HAL_GPIO_Init+0x136>
        /* Check the Alternate function parameters */
        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));

        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3U];
 800a8da:	69fb      	ldr	r3, [r7, #28]
 800a8dc:	08da      	lsrs	r2, r3, #3
 800a8de:	687b      	ldr	r3, [r7, #4]
 800a8e0:	3208      	adds	r2, #8
 800a8e2:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 800a8e6:	61bb      	str	r3, [r7, #24]
        temp &= ~(0xFU << ((position & 0x07U) * 4U));
 800a8e8:	69fb      	ldr	r3, [r7, #28]
 800a8ea:	f003 0307 	and.w	r3, r3, #7
 800a8ee:	009b      	lsls	r3, r3, #2
 800a8f0:	220f      	movs	r2, #15
 800a8f2:	fa02 f303 	lsl.w	r3, r2, r3
 800a8f6:	43db      	mvns	r3, r3
 800a8f8:	69ba      	ldr	r2, [r7, #24]
 800a8fa:	4013      	ands	r3, r2
 800a8fc:	61bb      	str	r3, [r7, #24]
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
 800a8fe:	683b      	ldr	r3, [r7, #0]
 800a900:	691a      	ldr	r2, [r3, #16]
 800a902:	69fb      	ldr	r3, [r7, #28]
 800a904:	f003 0307 	and.w	r3, r3, #7
 800a908:	009b      	lsls	r3, r3, #2
 800a90a:	fa02 f303 	lsl.w	r3, r2, r3
 800a90e:	69ba      	ldr	r2, [r7, #24]
 800a910:	4313      	orrs	r3, r2
 800a912:	61bb      	str	r3, [r7, #24]
        GPIOx->AFR[position >> 3U] = temp;
 800a914:	69fb      	ldr	r3, [r7, #28]
 800a916:	08da      	lsrs	r2, r3, #3
 800a918:	687b      	ldr	r3, [r7, #4]
 800a91a:	3208      	adds	r2, #8
 800a91c:	69b9      	ldr	r1, [r7, #24]
 800a91e:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 800a922:	687b      	ldr	r3, [r7, #4]
 800a924:	681b      	ldr	r3, [r3, #0]
 800a926:	61bb      	str	r3, [r7, #24]
      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
 800a928:	69fb      	ldr	r3, [r7, #28]
 800a92a:	005b      	lsls	r3, r3, #1
 800a92c:	2203      	movs	r2, #3
 800a92e:	fa02 f303 	lsl.w	r3, r2, r3
 800a932:	43db      	mvns	r3, r3
 800a934:	69ba      	ldr	r2, [r7, #24]
 800a936:	4013      	ands	r3, r2
 800a938:	61bb      	str	r3, [r7, #24]
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
 800a93a:	683b      	ldr	r3, [r7, #0]
 800a93c:	685b      	ldr	r3, [r3, #4]
 800a93e:	f003 0203 	and.w	r2, r3, #3
 800a942:	69fb      	ldr	r3, [r7, #28]
 800a944:	005b      	lsls	r3, r3, #1
 800a946:	fa02 f303 	lsl.w	r3, r2, r3
 800a94a:	69ba      	ldr	r2, [r7, #24]
 800a94c:	4313      	orrs	r3, r2
 800a94e:	61bb      	str	r3, [r7, #24]
      GPIOx->MODER = temp;
 800a950:	687b      	ldr	r3, [r7, #4]
 800a952:	69ba      	ldr	r2, [r7, #24]
 800a954:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
 800a956:	683b      	ldr	r3, [r7, #0]
 800a958:	685b      	ldr	r3, [r3, #4]
 800a95a:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 800a95e:	2b00      	cmp	r3, #0
 800a960:	f000 80e0 	beq.w	800ab24 <HAL_GPIO_Init+0x338>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 800a964:	4b2f      	ldr	r3, [pc, #188]	@ (800aa24 <HAL_GPIO_Init+0x238>)
 800a966:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 800a96a:	4a2e      	ldr	r2, [pc, #184]	@ (800aa24 <HAL_GPIO_Init+0x238>)
 800a96c:	f043 0302 	orr.w	r3, r3, #2
 800a970:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
 800a974:	4b2b      	ldr	r3, [pc, #172]	@ (800aa24 <HAL_GPIO_Init+0x238>)
 800a976:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
 800a97a:	f003 0302 	and.w	r3, r3, #2
 800a97e:	60fb      	str	r3, [r7, #12]
 800a980:	68fb      	ldr	r3, [r7, #12]

        temp = SYSCFG->EXTICR[position >> 2U];
 800a982:	4a29      	ldr	r2, [pc, #164]	@ (800aa28 <HAL_GPIO_Init+0x23c>)
 800a984:	69fb      	ldr	r3, [r7, #28]
 800a986:	089b      	lsrs	r3, r3, #2
 800a988:	3302      	adds	r3, #2
 800a98a:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 800a98e:	61bb      	str	r3, [r7, #24]
        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
 800a990:	69fb      	ldr	r3, [r7, #28]
 800a992:	f003 0303 	and.w	r3, r3, #3
 800a996:	009b      	lsls	r3, r3, #2
 800a998:	220f      	movs	r2, #15
 800a99a:	fa02 f303 	lsl.w	r3, r2, r3
 800a99e:	43db      	mvns	r3, r3
 800a9a0:	69ba      	ldr	r2, [r7, #24]
 800a9a2:	4013      	ands	r3, r2
 800a9a4:	61bb      	str	r3, [r7, #24]
        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
 800a9a6:	687b      	ldr	r3, [r7, #4]
 800a9a8:	4a20      	ldr	r2, [pc, #128]	@ (800aa2c <HAL_GPIO_Init+0x240>)
 800a9aa:	4293      	cmp	r3, r2
 800a9ac:	d052      	beq.n	800aa54 <HAL_GPIO_Init+0x268>
 800a9ae:	687b      	ldr	r3, [r7, #4]
 800a9b0:	4a1f      	ldr	r2, [pc, #124]	@ (800aa30 <HAL_GPIO_Init+0x244>)
 800a9b2:	4293      	cmp	r3, r2
 800a9b4:	d031      	beq.n	800aa1a <HAL_GPIO_Init+0x22e>
 800a9b6:	687b      	ldr	r3, [r7, #4]
 800a9b8:	4a1e      	ldr	r2, [pc, #120]	@ (800aa34 <HAL_GPIO_Init+0x248>)
 800a9ba:	4293      	cmp	r3, r2
 800a9bc:	d02b      	beq.n	800aa16 <HAL_GPIO_Init+0x22a>
 800a9be:	687b      	ldr	r3, [r7, #4]
 800a9c0:	4a1d      	ldr	r2, [pc, #116]	@ (800aa38 <HAL_GPIO_Init+0x24c>)
 800a9c2:	4293      	cmp	r3, r2
 800a9c4:	d025      	beq.n	800aa12 <HAL_GPIO_Init+0x226>
 800a9c6:	687b      	ldr	r3, [r7, #4]
 800a9c8:	4a1c      	ldr	r2, [pc, #112]	@ (800aa3c <HAL_GPIO_Init+0x250>)
 800a9ca:	4293      	cmp	r3, r2
 800a9cc:	d01f      	beq.n	800aa0e <HAL_GPIO_Init+0x222>
 800a9ce:	687b      	ldr	r3, [r7, #4]
 800a9d0:	4a1b      	ldr	r2, [pc, #108]	@ (800aa40 <HAL_GPIO_Init+0x254>)
 800a9d2:	4293      	cmp	r3, r2
 800a9d4:	d019      	beq.n	800aa0a <HAL_GPIO_Init+0x21e>
 800a9d6:	687b      	ldr	r3, [r7, #4]
 800a9d8:	4a1a      	ldr	r2, [pc, #104]	@ (800aa44 <HAL_GPIO_Init+0x258>)
 800a9da:	4293      	cmp	r3, r2
 800a9dc:	d013      	beq.n	800aa06 <HAL_GPIO_Init+0x21a>
 800a9de:	687b      	ldr	r3, [r7, #4]
 800a9e0:	4a19      	ldr	r2, [pc, #100]	@ (800aa48 <HAL_GPIO_Init+0x25c>)
 800a9e2:	4293      	cmp	r3, r2
 800a9e4:	d00d      	beq.n	800aa02 <HAL_GPIO_Init+0x216>
 800a9e6:	687b      	ldr	r3, [r7, #4]
 800a9e8:	4a18      	ldr	r2, [pc, #96]	@ (800aa4c <HAL_GPIO_Init+0x260>)
 800a9ea:	4293      	cmp	r3, r2
 800a9ec:	d007      	beq.n	800a9fe <HAL_GPIO_Init+0x212>
 800a9ee:	687b      	ldr	r3, [r7, #4]
 800a9f0:	4a17      	ldr	r2, [pc, #92]	@ (800aa50 <HAL_GPIO_Init+0x264>)
 800a9f2:	4293      	cmp	r3, r2
 800a9f4:	d101      	bne.n	800a9fa <HAL_GPIO_Init+0x20e>
 800a9f6:	2309      	movs	r3, #9
 800a9f8:	e02d      	b.n	800aa56 <HAL_GPIO_Init+0x26a>
 800a9fa:	230a      	movs	r3, #10
 800a9fc:	e02b      	b.n	800aa56 <HAL_GPIO_Init+0x26a>
 800a9fe:	2308      	movs	r3, #8
 800aa00:	e029      	b.n	800aa56 <HAL_GPIO_Init+0x26a>
 800aa02:	2307      	movs	r3, #7
 800aa04:	e027      	b.n	800aa56 <HAL_GPIO_Init+0x26a>
 800aa06:	2306      	movs	r3, #6
 800aa08:	e025      	b.n	800aa56 <HAL_GPIO_Init+0x26a>
 800aa0a:	2305      	movs	r3, #5
 800aa0c:	e023      	b.n	800aa56 <HAL_GPIO_Init+0x26a>
 800aa0e:	2304      	movs	r3, #4
 800aa10:	e021      	b.n	800aa56 <HAL_GPIO_Init+0x26a>
 800aa12:	2303      	movs	r3, #3
 800aa14:	e01f      	b.n	800aa56 <HAL_GPIO_Init+0x26a>
 800aa16:	2302      	movs	r3, #2
 800aa18:	e01d      	b.n	800aa56 <HAL_GPIO_Init+0x26a>
 800aa1a:	2301      	movs	r3, #1
 800aa1c:	e01b      	b.n	800aa56 <HAL_GPIO_Init+0x26a>
 800aa1e:	bf00      	nop
 800aa20:	58000080 	.word	0x58000080
 800aa24:	58024400 	.word	0x58024400
 800aa28:	58000400 	.word	0x58000400
 800aa2c:	58020000 	.word	0x58020000
 800aa30:	58020400 	.word	0x58020400
 800aa34:	58020800 	.word	0x58020800
 800aa38:	58020c00 	.word	0x58020c00
 800aa3c:	58021000 	.word	0x58021000
 800aa40:	58021400 	.word	0x58021400
 800aa44:	58021800 	.word	0x58021800
 800aa48:	58021c00 	.word	0x58021c00
 800aa4c:	58022000 	.word	0x58022000
 800aa50:	58022400 	.word	0x58022400
 800aa54:	2300      	movs	r3, #0
 800aa56:	69fa      	ldr	r2, [r7, #28]
 800aa58:	f002 0203 	and.w	r2, r2, #3
 800aa5c:	0092      	lsls	r2, r2, #2
 800aa5e:	4093      	lsls	r3, r2
 800aa60:	69ba      	ldr	r2, [r7, #24]
 800aa62:	4313      	orrs	r3, r2
 800aa64:	61bb      	str	r3, [r7, #24]
        SYSCFG->EXTICR[position >> 2U] = temp;
 800aa66:	4938      	ldr	r1, [pc, #224]	@ (800ab48 <HAL_GPIO_Init+0x35c>)
 800aa68:	69fb      	ldr	r3, [r7, #28]
 800aa6a:	089b      	lsrs	r3, r3, #2
 800aa6c:	3302      	adds	r3, #2
 800aa6e:	69ba      	ldr	r2, [r7, #24]
 800aa70:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR1;
 800aa74:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800aa78:	681b      	ldr	r3, [r3, #0]
 800aa7a:	61bb      	str	r3, [r7, #24]
        temp &= ~(iocurrent);
 800aa7c:	693b      	ldr	r3, [r7, #16]
 800aa7e:	43db      	mvns	r3, r3
 800aa80:	69ba      	ldr	r2, [r7, #24]
 800aa82:	4013      	ands	r3, r2
 800aa84:	61bb      	str	r3, [r7, #24]
        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
 800aa86:	683b      	ldr	r3, [r7, #0]
 800aa88:	685b      	ldr	r3, [r3, #4]
 800aa8a:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
 800aa8e:	2b00      	cmp	r3, #0
 800aa90:	d003      	beq.n	800aa9a <HAL_GPIO_Init+0x2ae>
        {
          temp |= iocurrent;
 800aa92:	69ba      	ldr	r2, [r7, #24]
 800aa94:	693b      	ldr	r3, [r7, #16]
 800aa96:	4313      	orrs	r3, r2
 800aa98:	61bb      	str	r3, [r7, #24]
        }
        EXTI->RTSR1 = temp;
 800aa9a:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800aa9e:	69bb      	ldr	r3, [r7, #24]
 800aaa0:	6013      	str	r3, [r2, #0]

        temp = EXTI->FTSR1;
 800aaa2:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800aaa6:	685b      	ldr	r3, [r3, #4]
 800aaa8:	61bb      	str	r3, [r7, #24]
        temp &= ~(iocurrent);
 800aaaa:	693b      	ldr	r3, [r7, #16]
 800aaac:	43db      	mvns	r3, r3
 800aaae:	69ba      	ldr	r2, [r7, #24]
 800aab0:	4013      	ands	r3, r2
 800aab2:	61bb      	str	r3, [r7, #24]
        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
 800aab4:	683b      	ldr	r3, [r7, #0]
 800aab6:	685b      	ldr	r3, [r3, #4]
 800aab8:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
 800aabc:	2b00      	cmp	r3, #0
 800aabe:	d003      	beq.n	800aac8 <HAL_GPIO_Init+0x2dc>
        {
          temp |= iocurrent;
 800aac0:	69ba      	ldr	r2, [r7, #24]
 800aac2:	693b      	ldr	r3, [r7, #16]
 800aac4:	4313      	orrs	r3, r2
 800aac6:	61bb      	str	r3, [r7, #24]
        }
        EXTI->FTSR1 = temp;
 800aac8:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800aacc:	69bb      	ldr	r3, [r7, #24]
 800aace:	6053      	str	r3, [r2, #4]

        temp = EXTI_CurrentCPU->EMR1;
 800aad0:	697b      	ldr	r3, [r7, #20]
 800aad2:	685b      	ldr	r3, [r3, #4]
 800aad4:	61bb      	str	r3, [r7, #24]
        temp &= ~(iocurrent);
 800aad6:	693b      	ldr	r3, [r7, #16]
 800aad8:	43db      	mvns	r3, r3
 800aada:	69ba      	ldr	r2, [r7, #24]
 800aadc:	4013      	ands	r3, r2
 800aade:	61bb      	str	r3, [r7, #24]
        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
 800aae0:	683b      	ldr	r3, [r7, #0]
 800aae2:	685b      	ldr	r3, [r3, #4]
 800aae4:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800aae8:	2b00      	cmp	r3, #0
 800aaea:	d003      	beq.n	800aaf4 <HAL_GPIO_Init+0x308>
        {
          temp |= iocurrent;
 800aaec:	69ba      	ldr	r2, [r7, #24]
 800aaee:	693b      	ldr	r3, [r7, #16]
 800aaf0:	4313      	orrs	r3, r2
 800aaf2:	61bb      	str	r3, [r7, #24]
        }
        EXTI_CurrentCPU->EMR1 = temp;
 800aaf4:	697b      	ldr	r3, [r7, #20]
 800aaf6:	69ba      	ldr	r2, [r7, #24]
 800aaf8:	605a      	str	r2, [r3, #4]

        /* Clear EXTI line configuration */
        temp = EXTI_CurrentCPU->IMR1;
 800aafa:	697b      	ldr	r3, [r7, #20]
 800aafc:	681b      	ldr	r3, [r3, #0]
 800aafe:	61bb      	str	r3, [r7, #24]
        temp &= ~(iocurrent);
 800ab00:	693b      	ldr	r3, [r7, #16]
 800ab02:	43db      	mvns	r3, r3
 800ab04:	69ba      	ldr	r2, [r7, #24]
 800ab06:	4013      	ands	r3, r2
 800ab08:	61bb      	str	r3, [r7, #24]
        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
 800ab0a:	683b      	ldr	r3, [r7, #0]
 800ab0c:	685b      	ldr	r3, [r3, #4]
 800ab0e:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 800ab12:	2b00      	cmp	r3, #0
 800ab14:	d003      	beq.n	800ab1e <HAL_GPIO_Init+0x332>
        {
          temp |= iocurrent;
 800ab16:	69ba      	ldr	r2, [r7, #24]
 800ab18:	693b      	ldr	r3, [r7, #16]
 800ab1a:	4313      	orrs	r3, r2
 800ab1c:	61bb      	str	r3, [r7, #24]
        }
        EXTI_CurrentCPU->IMR1 = temp;
 800ab1e:	697b      	ldr	r3, [r7, #20]
 800ab20:	69ba      	ldr	r2, [r7, #24]
 800ab22:	601a      	str	r2, [r3, #0]
      }
    }

    position++;
 800ab24:	69fb      	ldr	r3, [r7, #28]
 800ab26:	3301      	adds	r3, #1
 800ab28:	61fb      	str	r3, [r7, #28]
  while (((GPIO_Init->Pin) >> position) != 0x00U)
 800ab2a:	683b      	ldr	r3, [r7, #0]
 800ab2c:	681a      	ldr	r2, [r3, #0]
 800ab2e:	69fb      	ldr	r3, [r7, #28]
 800ab30:	fa22 f303 	lsr.w	r3, r2, r3
 800ab34:	2b00      	cmp	r3, #0
 800ab36:	f47f ae63 	bne.w	800a800 <HAL_GPIO_Init+0x14>
  }
}
 800ab3a:	bf00      	nop
 800ab3c:	bf00      	nop
 800ab3e:	3724      	adds	r7, #36	@ 0x24
 800ab40:	46bd      	mov	sp, r7
 800ab42:	f85d 7b04 	ldr.w	r7, [sp], #4
 800ab46:	4770      	bx	lr
 800ab48:	58000400 	.word	0x58000400

0800ab4c <HAL_GPIO_ReadPin>:
  * @param  GPIO_Pin: specifies the port bit to read.
  *         This parameter can be GPIO_PIN_x where x can be (0..15).
  * @retval The input port pin value.
  */
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
 800ab4c:	b480      	push	{r7}
 800ab4e:	b085      	sub	sp, #20
 800ab50:	af00      	add	r7, sp, #0
 800ab52:	6078      	str	r0, [r7, #4]
 800ab54:	460b      	mov	r3, r1
 800ab56:	807b      	strh	r3, [r7, #2]
  GPIO_PinState bitstatus;

  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
 800ab58:	687b      	ldr	r3, [r7, #4]
 800ab5a:	691a      	ldr	r2, [r3, #16]
 800ab5c:	887b      	ldrh	r3, [r7, #2]
 800ab5e:	4013      	ands	r3, r2
 800ab60:	2b00      	cmp	r3, #0
 800ab62:	d002      	beq.n	800ab6a <HAL_GPIO_ReadPin+0x1e>
  {
    bitstatus = GPIO_PIN_SET;
 800ab64:	2301      	movs	r3, #1
 800ab66:	73fb      	strb	r3, [r7, #15]
 800ab68:	e001      	b.n	800ab6e <HAL_GPIO_ReadPin+0x22>
  }
  else
  {
    bitstatus = GPIO_PIN_RESET;
 800ab6a:	2300      	movs	r3, #0
 800ab6c:	73fb      	strb	r3, [r7, #15]
  }
  return bitstatus;
 800ab6e:	7bfb      	ldrb	r3, [r7, #15]
}
 800ab70:	4618      	mov	r0, r3
 800ab72:	3714      	adds	r7, #20
 800ab74:	46bd      	mov	sp, r7
 800ab76:	f85d 7b04 	ldr.w	r7, [sp], #4
 800ab7a:	4770      	bx	lr

0800ab7c <HAL_GPIO_WritePin>:
  *            @arg GPIO_PIN_RESET: to clear the port pin
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
 800ab7c:	b480      	push	{r7}
 800ab7e:	b083      	sub	sp, #12
 800ab80:	af00      	add	r7, sp, #0
 800ab82:	6078      	str	r0, [r7, #4]
 800ab84:	460b      	mov	r3, r1
 800ab86:	807b      	strh	r3, [r7, #2]
 800ab88:	4613      	mov	r3, r2
 800ab8a:	707b      	strb	r3, [r7, #1]
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 800ab8c:	787b      	ldrb	r3, [r7, #1]
 800ab8e:	2b00      	cmp	r3, #0
 800ab90:	d003      	beq.n	800ab9a <HAL_GPIO_WritePin+0x1e>
  {
    GPIOx->BSRR = GPIO_Pin;
 800ab92:	887a      	ldrh	r2, [r7, #2]
 800ab94:	687b      	ldr	r3, [r7, #4]
 800ab96:	619a      	str	r2, [r3, #24]
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
  }
}
 800ab98:	e003      	b.n	800aba2 <HAL_GPIO_WritePin+0x26>
    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
 800ab9a:	887b      	ldrh	r3, [r7, #2]
 800ab9c:	041a      	lsls	r2, r3, #16
 800ab9e:	687b      	ldr	r3, [r7, #4]
 800aba0:	619a      	str	r2, [r3, #24]
}
 800aba2:	bf00      	nop
 800aba4:	370c      	adds	r7, #12
 800aba6:	46bd      	mov	sp, r7
 800aba8:	f85d 7b04 	ldr.w	r7, [sp], #4
 800abac:	4770      	bx	lr

0800abae <HAL_GPIO_TogglePin>:
  * @param  GPIOx: Where x can be (A..K) to select the GPIO peripheral.
  * @param  GPIO_Pin: Specifies the pins to be toggled.
  * @retval None
  */
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
 800abae:	b480      	push	{r7}
 800abb0:	b085      	sub	sp, #20
 800abb2:	af00      	add	r7, sp, #0
 800abb4:	6078      	str	r0, [r7, #4]
 800abb6:	460b      	mov	r3, r1
 800abb8:	807b      	strh	r3, [r7, #2]

  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  /* get current Output Data Register value */
  odr = GPIOx->ODR;
 800abba:	687b      	ldr	r3, [r7, #4]
 800abbc:	695b      	ldr	r3, [r3, #20]
 800abbe:	60fb      	str	r3, [r7, #12]

  /* Set selected pins that were at low level, and reset ones that were high */
  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
 800abc0:	887a      	ldrh	r2, [r7, #2]
 800abc2:	68fb      	ldr	r3, [r7, #12]
 800abc4:	4013      	ands	r3, r2
 800abc6:	041a      	lsls	r2, r3, #16
 800abc8:	68fb      	ldr	r3, [r7, #12]
 800abca:	43d9      	mvns	r1, r3
 800abcc:	887b      	ldrh	r3, [r7, #2]
 800abce:	400b      	ands	r3, r1
 800abd0:	431a      	orrs	r2, r3
 800abd2:	687b      	ldr	r3, [r7, #4]
 800abd4:	619a      	str	r2, [r3, #24]
}
 800abd6:	bf00      	nop
 800abd8:	3714      	adds	r7, #20
 800abda:	46bd      	mov	sp, r7
 800abdc:	f85d 7b04 	ldr.w	r7, [sp], #4
 800abe0:	4770      	bx	lr

0800abe2 <HAL_GPIO_EXTI_IRQHandler>:
  * @brief  Handle EXTI interrupt request.
  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
  * @retval None
  */
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
 800abe2:	b580      	push	{r7, lr}
 800abe4:	b082      	sub	sp, #8
 800abe6:	af00      	add	r7, sp, #0
 800abe8:	4603      	mov	r3, r0
 800abea:	80fb      	strh	r3, [r7, #6]
    __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);
    HAL_GPIO_EXTI_Callback(GPIO_Pin);
  }
#else
  /* EXTI line interrupt detected */
  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U)
 800abec:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800abf0:	f8d3 2088 	ldr.w	r2, [r3, #136]	@ 0x88
 800abf4:	88fb      	ldrh	r3, [r7, #6]
 800abf6:	4013      	ands	r3, r2
 800abf8:	2b00      	cmp	r3, #0
 800abfa:	d008      	beq.n	800ac0e <HAL_GPIO_EXTI_IRQHandler+0x2c>
  {
    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
 800abfc:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800ac00:	88fb      	ldrh	r3, [r7, #6]
 800ac02:	f8c2 3088 	str.w	r3, [r2, #136]	@ 0x88
    HAL_GPIO_EXTI_Callback(GPIO_Pin);
 800ac06:	88fb      	ldrh	r3, [r7, #6]
 800ac08:	4618      	mov	r0, r3
 800ac0a:	f7f5 fd65 	bl	80006d8 <HAL_GPIO_EXTI_Callback>
  }
#endif
}
 800ac0e:	bf00      	nop
 800ac10:	3708      	adds	r7, #8
 800ac12:	46bd      	mov	sp, r7
 800ac14:	bd80      	pop	{r7, pc}
	...

0800ac18 <HAL_PWR_ConfigPVD>:
  *         driver. All combination are allowed: wake up only Cortex-M7, wake up
  *         only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
  * @retval None.
  */
void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
{
 800ac18:	b480      	push	{r7}
 800ac1a:	b083      	sub	sp, #12
 800ac1c:	af00      	add	r7, sp, #0
 800ac1e:	6078      	str	r0, [r7, #4]
  /* Check the PVD configuration parameter */
  if (sConfigPVD == NULL)
 800ac20:	687b      	ldr	r3, [r7, #4]
 800ac22:	2b00      	cmp	r3, #0
 800ac24:	d069      	beq.n	800acfa <HAL_PWR_ConfigPVD+0xe2>
  /* Check the parameters */
  assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
  assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));

  /* Set PLS[7:5] bits according to PVDLevel value */
  MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
 800ac26:	4b38      	ldr	r3, [pc, #224]	@ (800ad08 <HAL_PWR_ConfigPVD+0xf0>)
 800ac28:	681b      	ldr	r3, [r3, #0]
 800ac2a:	f023 02e0 	bic.w	r2, r3, #224	@ 0xe0
 800ac2e:	687b      	ldr	r3, [r7, #4]
 800ac30:	681b      	ldr	r3, [r3, #0]
 800ac32:	4935      	ldr	r1, [pc, #212]	@ (800ad08 <HAL_PWR_ConfigPVD+0xf0>)
 800ac34:	4313      	orrs	r3, r2
 800ac36:	600b      	str	r3, [r1, #0]

  /* Clear previous config */
#if !defined (DUAL_CORE)
  __HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
 800ac38:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800ac3c:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 800ac40:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800ac44:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800ac48:	f8c2 3084 	str.w	r3, [r2, #132]	@ 0x84
  __HAL_PWR_PVD_EXTI_DISABLE_IT ();
 800ac4c:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800ac50:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800ac54:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800ac58:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800ac5c:	f8c2 3080 	str.w	r3, [r2, #128]	@ 0x80
#endif /* !defined (DUAL_CORE) */

  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
 800ac60:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800ac64:	681b      	ldr	r3, [r3, #0]
 800ac66:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800ac6a:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800ac6e:	6013      	str	r3, [r2, #0]
  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
 800ac70:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800ac74:	685b      	ldr	r3, [r3, #4]
 800ac76:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800ac7a:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800ac7e:	6053      	str	r3, [r2, #4]

#if !defined (DUAL_CORE)
  /* Interrupt mode configuration */
  if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
 800ac80:	687b      	ldr	r3, [r7, #4]
 800ac82:	685b      	ldr	r3, [r3, #4]
 800ac84:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 800ac88:	2b00      	cmp	r3, #0
 800ac8a:	d009      	beq.n	800aca0 <HAL_PWR_ConfigPVD+0x88>
  {
    __HAL_PWR_PVD_EXTI_ENABLE_IT ();
 800ac8c:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800ac90:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800ac94:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800ac98:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800ac9c:	f8c2 3080 	str.w	r3, [r2, #128]	@ 0x80
  }

  /* Event mode configuration */
  if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
 800aca0:	687b      	ldr	r3, [r7, #4]
 800aca2:	685b      	ldr	r3, [r3, #4]
 800aca4:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800aca8:	2b00      	cmp	r3, #0
 800acaa:	d009      	beq.n	800acc0 <HAL_PWR_ConfigPVD+0xa8>
  {
    __HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
 800acac:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800acb0:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 800acb4:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800acb8:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800acbc:	f8c2 3084 	str.w	r3, [r2, #132]	@ 0x84
  }
#endif /* !defined (DUAL_CORE) */

  /* Rising edge configuration */
  if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
 800acc0:	687b      	ldr	r3, [r7, #4]
 800acc2:	685b      	ldr	r3, [r3, #4]
 800acc4:	f003 0301 	and.w	r3, r3, #1
 800acc8:	2b00      	cmp	r3, #0
 800acca:	d007      	beq.n	800acdc <HAL_PWR_ConfigPVD+0xc4>
  {
    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
 800accc:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800acd0:	681b      	ldr	r3, [r3, #0]
 800acd2:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800acd6:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800acda:	6013      	str	r3, [r2, #0]
  }

  /* Falling edge configuration */
  if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
 800acdc:	687b      	ldr	r3, [r7, #4]
 800acde:	685b      	ldr	r3, [r3, #4]
 800ace0:	f003 0302 	and.w	r3, r3, #2
 800ace4:	2b00      	cmp	r3, #0
 800ace6:	d009      	beq.n	800acfc <HAL_PWR_ConfigPVD+0xe4>
  {
    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
 800ace8:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800acec:	685b      	ldr	r3, [r3, #4]
 800acee:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800acf2:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800acf6:	6053      	str	r3, [r2, #4]
 800acf8:	e000      	b.n	800acfc <HAL_PWR_ConfigPVD+0xe4>
    return;
 800acfa:	bf00      	nop
  }
}
 800acfc:	370c      	adds	r7, #12
 800acfe:	46bd      	mov	sp, r7
 800ad00:	f85d 7b04 	ldr.w	r7, [sp], #4
 800ad04:	4770      	bx	lr
 800ad06:	bf00      	nop
 800ad08:	58024800 	.word	0x58024800

0800ad0c <HAL_PWR_EnablePVD>:
/**
  * @brief Enable the Programmable Voltage Detector (PVD).
  * @retval None.
  */
void HAL_PWR_EnablePVD (void)
{
 800ad0c:	b480      	push	{r7}
 800ad0e:	af00      	add	r7, sp, #0
  /* Enable the power voltage detector */
  SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
 800ad10:	4b05      	ldr	r3, [pc, #20]	@ (800ad28 <HAL_PWR_EnablePVD+0x1c>)
 800ad12:	681b      	ldr	r3, [r3, #0]
 800ad14:	4a04      	ldr	r2, [pc, #16]	@ (800ad28 <HAL_PWR_EnablePVD+0x1c>)
 800ad16:	f043 0310 	orr.w	r3, r3, #16
 800ad1a:	6013      	str	r3, [r2, #0]
}
 800ad1c:	bf00      	nop
 800ad1e:	46bd      	mov	sp, r7
 800ad20:	f85d 7b04 	ldr.w	r7, [sp], #4
 800ad24:	4770      	bx	lr
 800ad26:	bf00      	nop
 800ad28:	58024800 	.word	0x58024800

0800ad2c <HAL_PWREx_ConfigSupply>:
  *         PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
  *         regulator.
  * @retval HAL status.
  */
HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
{
 800ad2c:	b580      	push	{r7, lr}
 800ad2e:	b084      	sub	sp, #16
 800ad30:	af00      	add	r7, sp, #0
 800ad32:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param (IS_PWR_SUPPLY (SupplySource));

  /* Check if supply source was configured */
#if defined (PWR_FLAG_SCUEN)
  if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
 800ad34:	4b19      	ldr	r3, [pc, #100]	@ (800ad9c <HAL_PWREx_ConfigSupply+0x70>)
 800ad36:	68db      	ldr	r3, [r3, #12]
 800ad38:	f003 0304 	and.w	r3, r3, #4
 800ad3c:	2b04      	cmp	r3, #4
 800ad3e:	d00a      	beq.n	800ad56 <HAL_PWREx_ConfigSupply+0x2a>
#else
  if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
#endif /* defined (PWR_FLAG_SCUEN) */
  {
    /* Check supply configuration */
    if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
 800ad40:	4b16      	ldr	r3, [pc, #88]	@ (800ad9c <HAL_PWREx_ConfigSupply+0x70>)
 800ad42:	68db      	ldr	r3, [r3, #12]
 800ad44:	f003 0307 	and.w	r3, r3, #7
 800ad48:	687a      	ldr	r2, [r7, #4]
 800ad4a:	429a      	cmp	r2, r3
 800ad4c:	d001      	beq.n	800ad52 <HAL_PWREx_ConfigSupply+0x26>
    {
      /* Supply configuration update locked, can't apply a new supply config */
      return HAL_ERROR;
 800ad4e:	2301      	movs	r3, #1
 800ad50:	e01f      	b.n	800ad92 <HAL_PWREx_ConfigSupply+0x66>
    else
    {
      /* Supply configuration update locked, but new supply configuration
         matches with old supply configuration : nothing to do
      */
      return HAL_OK;
 800ad52:	2300      	movs	r3, #0
 800ad54:	e01d      	b.n	800ad92 <HAL_PWREx_ConfigSupply+0x66>
    }
  }

  /* Set the power supply configuration */
  MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
 800ad56:	4b11      	ldr	r3, [pc, #68]	@ (800ad9c <HAL_PWREx_ConfigSupply+0x70>)
 800ad58:	68db      	ldr	r3, [r3, #12]
 800ad5a:	f023 0207 	bic.w	r2, r3, #7
 800ad5e:	490f      	ldr	r1, [pc, #60]	@ (800ad9c <HAL_PWREx_ConfigSupply+0x70>)
 800ad60:	687b      	ldr	r3, [r7, #4]
 800ad62:	4313      	orrs	r3, r2
 800ad64:	60cb      	str	r3, [r1, #12]

  /* Get tick */
  tickstart = HAL_GetTick ();
 800ad66:	f7fa fb69 	bl	800543c <HAL_GetTick>
 800ad6a:	60f8      	str	r0, [r7, #12]

  /* Wait till voltage level flag is set */
  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
 800ad6c:	e009      	b.n	800ad82 <HAL_PWREx_ConfigSupply+0x56>
  {
    if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
 800ad6e:	f7fa fb65 	bl	800543c <HAL_GetTick>
 800ad72:	4602      	mov	r2, r0
 800ad74:	68fb      	ldr	r3, [r7, #12]
 800ad76:	1ad3      	subs	r3, r2, r3
 800ad78:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
 800ad7c:	d901      	bls.n	800ad82 <HAL_PWREx_ConfigSupply+0x56>
    {
      return HAL_ERROR;
 800ad7e:	2301      	movs	r3, #1
 800ad80:	e007      	b.n	800ad92 <HAL_PWREx_ConfigSupply+0x66>
  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
 800ad82:	4b06      	ldr	r3, [pc, #24]	@ (800ad9c <HAL_PWREx_ConfigSupply+0x70>)
 800ad84:	685b      	ldr	r3, [r3, #4]
 800ad86:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 800ad8a:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800ad8e:	d1ee      	bne.n	800ad6e <HAL_PWREx_ConfigSupply+0x42>
      }
    }
  }
#endif /* defined (SMPS) */

  return HAL_OK;
 800ad90:	2300      	movs	r3, #0
}
 800ad92:	4618      	mov	r0, r3
 800ad94:	3710      	adds	r7, #16
 800ad96:	46bd      	mov	sp, r7
 800ad98:	bd80      	pop	{r7, pc}
 800ad9a:	bf00      	nop
 800ad9c:	58024800 	.word	0x58024800

0800ada0 <HAL_PWREx_ConfigAVD>:
  *         driver. All combination are allowed: wake up only Cortex-M7, wake up
  *         only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.
  * @retval None.
  */
void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
{
 800ada0:	b480      	push	{r7}
 800ada2:	b083      	sub	sp, #12
 800ada4:	af00      	add	r7, sp, #0
 800ada6:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel));
  assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode));

  /* Set the ALS[18:17] bits according to AVDLevel value */
  MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
 800ada8:	4b37      	ldr	r3, [pc, #220]	@ (800ae88 <HAL_PWREx_ConfigAVD+0xe8>)
 800adaa:	681b      	ldr	r3, [r3, #0]
 800adac:	f423 22c0 	bic.w	r2, r3, #393216	@ 0x60000
 800adb0:	687b      	ldr	r3, [r7, #4]
 800adb2:	681b      	ldr	r3, [r3, #0]
 800adb4:	4934      	ldr	r1, [pc, #208]	@ (800ae88 <HAL_PWREx_ConfigAVD+0xe8>)
 800adb6:	4313      	orrs	r3, r2
 800adb8:	600b      	str	r3, [r1, #0]

  /* Clear any previous config */
#if !defined (DUAL_CORE)
  __HAL_PWR_AVD_EXTI_DISABLE_EVENT ();
 800adba:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800adbe:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 800adc2:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800adc6:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800adca:	f8c2 3084 	str.w	r3, [r2, #132]	@ 0x84
  __HAL_PWR_AVD_EXTI_DISABLE_IT ();
 800adce:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800add2:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800add6:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800adda:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800adde:	f8c2 3080 	str.w	r3, [r2, #128]	@ 0x80
#endif /* !defined (DUAL_CORE) */

  __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE ();
 800ade2:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800ade6:	681b      	ldr	r3, [r3, #0]
 800ade8:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800adec:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800adf0:	6013      	str	r3, [r2, #0]
  __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE ();
 800adf2:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800adf6:	685b      	ldr	r3, [r3, #4]
 800adf8:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800adfc:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800ae00:	6053      	str	r3, [r2, #4]

#if !defined (DUAL_CORE)
  /* Configure the interrupt mode */
  if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT)
 800ae02:	687b      	ldr	r3, [r7, #4]
 800ae04:	685b      	ldr	r3, [r3, #4]
 800ae06:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 800ae0a:	2b00      	cmp	r3, #0
 800ae0c:	d009      	beq.n	800ae22 <HAL_PWREx_ConfigAVD+0x82>
  {
    __HAL_PWR_AVD_EXTI_ENABLE_IT ();
 800ae0e:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800ae12:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800ae16:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800ae1a:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800ae1e:	f8c2 3080 	str.w	r3, [r2, #128]	@ 0x80
  }

  /* Configure the event mode */
  if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT)
 800ae22:	687b      	ldr	r3, [r7, #4]
 800ae24:	685b      	ldr	r3, [r3, #4]
 800ae26:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800ae2a:	2b00      	cmp	r3, #0
 800ae2c:	d009      	beq.n	800ae42 <HAL_PWREx_ConfigAVD+0xa2>
  {
    __HAL_PWR_AVD_EXTI_ENABLE_EVENT ();
 800ae2e:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800ae32:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 800ae36:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800ae3a:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800ae3e:	f8c2 3084 	str.w	r3, [r2, #132]	@ 0x84
  }
#endif /* !defined (DUAL_CORE) */

  /* Rising edge configuration */
  if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE)
 800ae42:	687b      	ldr	r3, [r7, #4]
 800ae44:	685b      	ldr	r3, [r3, #4]
 800ae46:	f003 0301 	and.w	r3, r3, #1
 800ae4a:	2b00      	cmp	r3, #0
 800ae4c:	d007      	beq.n	800ae5e <HAL_PWREx_ConfigAVD+0xbe>
  {
    __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE ();
 800ae4e:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800ae52:	681b      	ldr	r3, [r3, #0]
 800ae54:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800ae58:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800ae5c:	6013      	str	r3, [r2, #0]
  }

  /* Falling edge configuration */
  if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE)
 800ae5e:	687b      	ldr	r3, [r7, #4]
 800ae60:	685b      	ldr	r3, [r3, #4]
 800ae62:	f003 0302 	and.w	r3, r3, #2
 800ae66:	2b00      	cmp	r3, #0
 800ae68:	d007      	beq.n	800ae7a <HAL_PWREx_ConfigAVD+0xda>
  {
    __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE ();
 800ae6a:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
 800ae6e:	685b      	ldr	r3, [r3, #4]
 800ae70:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
 800ae74:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800ae78:	6053      	str	r3, [r2, #4]
  }
}
 800ae7a:	bf00      	nop
 800ae7c:	370c      	adds	r7, #12
 800ae7e:	46bd      	mov	sp, r7
 800ae80:	f85d 7b04 	ldr.w	r7, [sp], #4
 800ae84:	4770      	bx	lr
 800ae86:	bf00      	nop
 800ae88:	58024800 	.word	0x58024800

0800ae8c <HAL_PWREx_EnableAVD>:
/**
  * @brief Enable the Analog Voltage Detector (AVD).
  * @retval None.
  */
void HAL_PWREx_EnableAVD (void)
{
 800ae8c:	b480      	push	{r7}
 800ae8e:	af00      	add	r7, sp, #0
  /* Enable the Analog Voltage Detector */
  SET_BIT (PWR->CR1, PWR_CR1_AVDEN);
 800ae90:	4b05      	ldr	r3, [pc, #20]	@ (800aea8 <HAL_PWREx_EnableAVD+0x1c>)
 800ae92:	681b      	ldr	r3, [r3, #0]
 800ae94:	4a04      	ldr	r2, [pc, #16]	@ (800aea8 <HAL_PWREx_EnableAVD+0x1c>)
 800ae96:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800ae9a:	6013      	str	r3, [r2, #0]
}
 800ae9c:	bf00      	nop
 800ae9e:	46bd      	mov	sp, r7
 800aea0:	f85d 7b04 	ldr.w	r7, [sp], #4
 800aea4:	4770      	bx	lr
 800aea6:	bf00      	nop
 800aea8:	58024800 	.word	0x58024800

0800aeac <HAL_RCC_OscConfig>:
  *         supported by this function. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 800aeac:	b580      	push	{r7, lr}
 800aeae:	b08c      	sub	sp, #48	@ 0x30
 800aeb0:	af00      	add	r7, sp, #0
 800aeb2:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  uint32_t temp1_pllckcfg, temp2_pllckcfg;

  /* Check Null pointer */
  if (RCC_OscInitStruct == NULL)
 800aeb4:	687b      	ldr	r3, [r7, #4]
 800aeb6:	2b00      	cmp	r3, #0
 800aeb8:	d102      	bne.n	800aec0 <HAL_RCC_OscConfig+0x14>
  {
    return HAL_ERROR;
 800aeba:	2301      	movs	r3, #1
 800aebc:	f000 bc48 	b.w	800b750 <HAL_RCC_OscConfig+0x8a4>
  }

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  /*------------------------------- HSE Configuration ------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 800aec0:	687b      	ldr	r3, [r7, #4]
 800aec2:	681b      	ldr	r3, [r3, #0]
 800aec4:	f003 0301 	and.w	r3, r3, #1
 800aec8:	2b00      	cmp	r3, #0
 800aeca:	f000 8088 	beq.w	800afde <HAL_RCC_OscConfig+0x132>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
 800aece:	4b99      	ldr	r3, [pc, #612]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800aed0:	691b      	ldr	r3, [r3, #16]
 800aed2:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 800aed6:	62fb      	str	r3, [r7, #44]	@ 0x2c
    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
 800aed8:	4b96      	ldr	r3, [pc, #600]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800aeda:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800aedc:	62bb      	str	r3, [r7, #40]	@ 0x28
    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
    if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
 800aede:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800aee0:	2b10      	cmp	r3, #16
 800aee2:	d007      	beq.n	800aef4 <HAL_RCC_OscConfig+0x48>
 800aee4:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800aee6:	2b18      	cmp	r3, #24
 800aee8:	d111      	bne.n	800af0e <HAL_RCC_OscConfig+0x62>
 800aeea:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800aeec:	f003 0303 	and.w	r3, r3, #3
 800aef0:	2b02      	cmp	r3, #2
 800aef2:	d10c      	bne.n	800af0e <HAL_RCC_OscConfig+0x62>
    {
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 800aef4:	4b8f      	ldr	r3, [pc, #572]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800aef6:	681b      	ldr	r3, [r3, #0]
 800aef8:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800aefc:	2b00      	cmp	r3, #0
 800aefe:	d06d      	beq.n	800afdc <HAL_RCC_OscConfig+0x130>
 800af00:	687b      	ldr	r3, [r7, #4]
 800af02:	685b      	ldr	r3, [r3, #4]
 800af04:	2b00      	cmp	r3, #0
 800af06:	d169      	bne.n	800afdc <HAL_RCC_OscConfig+0x130>
      {
        return HAL_ERROR;
 800af08:	2301      	movs	r3, #1
 800af0a:	f000 bc21 	b.w	800b750 <HAL_RCC_OscConfig+0x8a4>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 800af0e:	687b      	ldr	r3, [r7, #4]
 800af10:	685b      	ldr	r3, [r3, #4]
 800af12:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800af16:	d106      	bne.n	800af26 <HAL_RCC_OscConfig+0x7a>
 800af18:	4b86      	ldr	r3, [pc, #536]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af1a:	681b      	ldr	r3, [r3, #0]
 800af1c:	4a85      	ldr	r2, [pc, #532]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af1e:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800af22:	6013      	str	r3, [r2, #0]
 800af24:	e02e      	b.n	800af84 <HAL_RCC_OscConfig+0xd8>
 800af26:	687b      	ldr	r3, [r7, #4]
 800af28:	685b      	ldr	r3, [r3, #4]
 800af2a:	2b00      	cmp	r3, #0
 800af2c:	d10c      	bne.n	800af48 <HAL_RCC_OscConfig+0x9c>
 800af2e:	4b81      	ldr	r3, [pc, #516]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af30:	681b      	ldr	r3, [r3, #0]
 800af32:	4a80      	ldr	r2, [pc, #512]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af34:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800af38:	6013      	str	r3, [r2, #0]
 800af3a:	4b7e      	ldr	r3, [pc, #504]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af3c:	681b      	ldr	r3, [r3, #0]
 800af3e:	4a7d      	ldr	r2, [pc, #500]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af40:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
 800af44:	6013      	str	r3, [r2, #0]
 800af46:	e01d      	b.n	800af84 <HAL_RCC_OscConfig+0xd8>
 800af48:	687b      	ldr	r3, [r7, #4]
 800af4a:	685b      	ldr	r3, [r3, #4]
 800af4c:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 800af50:	d10c      	bne.n	800af6c <HAL_RCC_OscConfig+0xc0>
 800af52:	4b78      	ldr	r3, [pc, #480]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af54:	681b      	ldr	r3, [r3, #0]
 800af56:	4a77      	ldr	r2, [pc, #476]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af58:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
 800af5c:	6013      	str	r3, [r2, #0]
 800af5e:	4b75      	ldr	r3, [pc, #468]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af60:	681b      	ldr	r3, [r3, #0]
 800af62:	4a74      	ldr	r2, [pc, #464]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af64:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800af68:	6013      	str	r3, [r2, #0]
 800af6a:	e00b      	b.n	800af84 <HAL_RCC_OscConfig+0xd8>
 800af6c:	4b71      	ldr	r3, [pc, #452]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af6e:	681b      	ldr	r3, [r3, #0]
 800af70:	4a70      	ldr	r2, [pc, #448]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af72:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800af76:	6013      	str	r3, [r2, #0]
 800af78:	4b6e      	ldr	r3, [pc, #440]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af7a:	681b      	ldr	r3, [r3, #0]
 800af7c:	4a6d      	ldr	r2, [pc, #436]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800af7e:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
 800af82:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 800af84:	687b      	ldr	r3, [r7, #4]
 800af86:	685b      	ldr	r3, [r3, #4]
 800af88:	2b00      	cmp	r3, #0
 800af8a:	d013      	beq.n	800afb4 <HAL_RCC_OscConfig+0x108>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800af8c:	f7fa fa56 	bl	800543c <HAL_GetTick>
 800af90:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till HSE is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 800af92:	e008      	b.n	800afa6 <HAL_RCC_OscConfig+0xfa>
        {
          if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 800af94:	f7fa fa52 	bl	800543c <HAL_GetTick>
 800af98:	4602      	mov	r2, r0
 800af9a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800af9c:	1ad3      	subs	r3, r2, r3
 800af9e:	2b64      	cmp	r3, #100	@ 0x64
 800afa0:	d901      	bls.n	800afa6 <HAL_RCC_OscConfig+0xfa>
          {
            return HAL_TIMEOUT;
 800afa2:	2303      	movs	r3, #3
 800afa4:	e3d4      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 800afa6:	4b63      	ldr	r3, [pc, #396]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800afa8:	681b      	ldr	r3, [r3, #0]
 800afaa:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800afae:	2b00      	cmp	r3, #0
 800afb0:	d0f0      	beq.n	800af94 <HAL_RCC_OscConfig+0xe8>
 800afb2:	e014      	b.n	800afde <HAL_RCC_OscConfig+0x132>
        }
      }
      else
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800afb4:	f7fa fa42 	bl	800543c <HAL_GetTick>
 800afb8:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till HSE is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
 800afba:	e008      	b.n	800afce <HAL_RCC_OscConfig+0x122>
        {
          if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 800afbc:	f7fa fa3e 	bl	800543c <HAL_GetTick>
 800afc0:	4602      	mov	r2, r0
 800afc2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800afc4:	1ad3      	subs	r3, r2, r3
 800afc6:	2b64      	cmp	r3, #100	@ 0x64
 800afc8:	d901      	bls.n	800afce <HAL_RCC_OscConfig+0x122>
          {
            return HAL_TIMEOUT;
 800afca:	2303      	movs	r3, #3
 800afcc:	e3c0      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
 800afce:	4b59      	ldr	r3, [pc, #356]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800afd0:	681b      	ldr	r3, [r3, #0]
 800afd2:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800afd6:	2b00      	cmp	r3, #0
 800afd8:	d1f0      	bne.n	800afbc <HAL_RCC_OscConfig+0x110>
 800afda:	e000      	b.n	800afde <HAL_RCC_OscConfig+0x132>
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 800afdc:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 800afde:	687b      	ldr	r3, [r7, #4]
 800afe0:	681b      	ldr	r3, [r3, #0]
 800afe2:	f003 0302 	and.w	r3, r3, #2
 800afe6:	2b00      	cmp	r3, #0
 800afe8:	f000 80ca 	beq.w	800b180 <HAL_RCC_OscConfig+0x2d4>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* When the HSI is used as system clock it will not be disabled */
    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
 800afec:	4b51      	ldr	r3, [pc, #324]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800afee:	691b      	ldr	r3, [r3, #16]
 800aff0:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 800aff4:	623b      	str	r3, [r7, #32]
    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
 800aff6:	4b4f      	ldr	r3, [pc, #316]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800aff8:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800affa:	61fb      	str	r3, [r7, #28]
    if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
 800affc:	6a3b      	ldr	r3, [r7, #32]
 800affe:	2b00      	cmp	r3, #0
 800b000:	d007      	beq.n	800b012 <HAL_RCC_OscConfig+0x166>
 800b002:	6a3b      	ldr	r3, [r7, #32]
 800b004:	2b18      	cmp	r3, #24
 800b006:	d156      	bne.n	800b0b6 <HAL_RCC_OscConfig+0x20a>
 800b008:	69fb      	ldr	r3, [r7, #28]
 800b00a:	f003 0303 	and.w	r3, r3, #3
 800b00e:	2b00      	cmp	r3, #0
 800b010:	d151      	bne.n	800b0b6 <HAL_RCC_OscConfig+0x20a>
    {
      /* When HSI is used as system clock it will not be disabled */
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 800b012:	4b48      	ldr	r3, [pc, #288]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b014:	681b      	ldr	r3, [r3, #0]
 800b016:	f003 0304 	and.w	r3, r3, #4
 800b01a:	2b00      	cmp	r3, #0
 800b01c:	d005      	beq.n	800b02a <HAL_RCC_OscConfig+0x17e>
 800b01e:	687b      	ldr	r3, [r7, #4]
 800b020:	68db      	ldr	r3, [r3, #12]
 800b022:	2b00      	cmp	r3, #0
 800b024:	d101      	bne.n	800b02a <HAL_RCC_OscConfig+0x17e>
      {
        return HAL_ERROR;
 800b026:	2301      	movs	r3, #1
 800b028:	e392      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
      }
      /* Otherwise, only HSI division and calibration are allowed */
      else
      {
        /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */
        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
 800b02a:	4b42      	ldr	r3, [pc, #264]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b02c:	681b      	ldr	r3, [r3, #0]
 800b02e:	f023 0219 	bic.w	r2, r3, #25
 800b032:	687b      	ldr	r3, [r7, #4]
 800b034:	68db      	ldr	r3, [r3, #12]
 800b036:	493f      	ldr	r1, [pc, #252]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b038:	4313      	orrs	r3, r2
 800b03a:	600b      	str	r3, [r1, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800b03c:	f7fa f9fe 	bl	800543c <HAL_GetTick>
 800b040:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till HSI is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 800b042:	e008      	b.n	800b056 <HAL_RCC_OscConfig+0x1aa>
        {
          if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 800b044:	f7fa f9fa 	bl	800543c <HAL_GetTick>
 800b048:	4602      	mov	r2, r0
 800b04a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b04c:	1ad3      	subs	r3, r2, r3
 800b04e:	2b02      	cmp	r3, #2
 800b050:	d901      	bls.n	800b056 <HAL_RCC_OscConfig+0x1aa>
          {
            return HAL_TIMEOUT;
 800b052:	2303      	movs	r3, #3
 800b054:	e37c      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 800b056:	4b37      	ldr	r3, [pc, #220]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b058:	681b      	ldr	r3, [r3, #0]
 800b05a:	f003 0304 	and.w	r3, r3, #4
 800b05e:	2b00      	cmp	r3, #0
 800b060:	d0f0      	beq.n	800b044 <HAL_RCC_OscConfig+0x198>
          }
        }
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 800b062:	f7fa f9f7 	bl	8005454 <HAL_GetREVID>
 800b066:	4603      	mov	r3, r0
 800b068:	f241 0203 	movw	r2, #4099	@ 0x1003
 800b06c:	4293      	cmp	r3, r2
 800b06e:	d817      	bhi.n	800b0a0 <HAL_RCC_OscConfig+0x1f4>
 800b070:	687b      	ldr	r3, [r7, #4]
 800b072:	691b      	ldr	r3, [r3, #16]
 800b074:	2b40      	cmp	r3, #64	@ 0x40
 800b076:	d108      	bne.n	800b08a <HAL_RCC_OscConfig+0x1de>
 800b078:	4b2e      	ldr	r3, [pc, #184]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b07a:	685b      	ldr	r3, [r3, #4]
 800b07c:	f423 337c 	bic.w	r3, r3, #258048	@ 0x3f000
 800b080:	4a2c      	ldr	r2, [pc, #176]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b082:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800b086:	6053      	str	r3, [r2, #4]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 800b088:	e07a      	b.n	800b180 <HAL_RCC_OscConfig+0x2d4>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 800b08a:	4b2a      	ldr	r3, [pc, #168]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b08c:	685b      	ldr	r3, [r3, #4]
 800b08e:	f423 327c 	bic.w	r2, r3, #258048	@ 0x3f000
 800b092:	687b      	ldr	r3, [r7, #4]
 800b094:	691b      	ldr	r3, [r3, #16]
 800b096:	031b      	lsls	r3, r3, #12
 800b098:	4926      	ldr	r1, [pc, #152]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b09a:	4313      	orrs	r3, r2
 800b09c:	604b      	str	r3, [r1, #4]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 800b09e:	e06f      	b.n	800b180 <HAL_RCC_OscConfig+0x2d4>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 800b0a0:	4b24      	ldr	r3, [pc, #144]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b0a2:	685b      	ldr	r3, [r3, #4]
 800b0a4:	f023 42fe 	bic.w	r2, r3, #2130706432	@ 0x7f000000
 800b0a8:	687b      	ldr	r3, [r7, #4]
 800b0aa:	691b      	ldr	r3, [r3, #16]
 800b0ac:	061b      	lsls	r3, r3, #24
 800b0ae:	4921      	ldr	r1, [pc, #132]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b0b0:	4313      	orrs	r3, r2
 800b0b2:	604b      	str	r3, [r1, #4]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 800b0b4:	e064      	b.n	800b180 <HAL_RCC_OscConfig+0x2d4>
    }

    else
    {
      /* Check the HSI State */
      if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
 800b0b6:	687b      	ldr	r3, [r7, #4]
 800b0b8:	68db      	ldr	r3, [r3, #12]
 800b0ba:	2b00      	cmp	r3, #0
 800b0bc:	d047      	beq.n	800b14e <HAL_RCC_OscConfig+0x2a2>
      {
        /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
 800b0be:	4b1d      	ldr	r3, [pc, #116]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b0c0:	681b      	ldr	r3, [r3, #0]
 800b0c2:	f023 0219 	bic.w	r2, r3, #25
 800b0c6:	687b      	ldr	r3, [r7, #4]
 800b0c8:	68db      	ldr	r3, [r3, #12]
 800b0ca:	491a      	ldr	r1, [pc, #104]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b0cc:	4313      	orrs	r3, r2
 800b0ce:	600b      	str	r3, [r1, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800b0d0:	f7fa f9b4 	bl	800543c <HAL_GetTick>
 800b0d4:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till HSI is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 800b0d6:	e008      	b.n	800b0ea <HAL_RCC_OscConfig+0x23e>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 800b0d8:	f7fa f9b0 	bl	800543c <HAL_GetTick>
 800b0dc:	4602      	mov	r2, r0
 800b0de:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b0e0:	1ad3      	subs	r3, r2, r3
 800b0e2:	2b02      	cmp	r3, #2
 800b0e4:	d901      	bls.n	800b0ea <HAL_RCC_OscConfig+0x23e>
          {
            return HAL_TIMEOUT;
 800b0e6:	2303      	movs	r3, #3
 800b0e8:	e332      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 800b0ea:	4b12      	ldr	r3, [pc, #72]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b0ec:	681b      	ldr	r3, [r3, #0]
 800b0ee:	f003 0304 	and.w	r3, r3, #4
 800b0f2:	2b00      	cmp	r3, #0
 800b0f4:	d0f0      	beq.n	800b0d8 <HAL_RCC_OscConfig+0x22c>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 800b0f6:	f7fa f9ad 	bl	8005454 <HAL_GetREVID>
 800b0fa:	4603      	mov	r3, r0
 800b0fc:	f241 0203 	movw	r2, #4099	@ 0x1003
 800b100:	4293      	cmp	r3, r2
 800b102:	d819      	bhi.n	800b138 <HAL_RCC_OscConfig+0x28c>
 800b104:	687b      	ldr	r3, [r7, #4]
 800b106:	691b      	ldr	r3, [r3, #16]
 800b108:	2b40      	cmp	r3, #64	@ 0x40
 800b10a:	d108      	bne.n	800b11e <HAL_RCC_OscConfig+0x272>
 800b10c:	4b09      	ldr	r3, [pc, #36]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b10e:	685b      	ldr	r3, [r3, #4]
 800b110:	f423 337c 	bic.w	r3, r3, #258048	@ 0x3f000
 800b114:	4a07      	ldr	r2, [pc, #28]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b116:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800b11a:	6053      	str	r3, [r2, #4]
 800b11c:	e030      	b.n	800b180 <HAL_RCC_OscConfig+0x2d4>
 800b11e:	4b05      	ldr	r3, [pc, #20]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b120:	685b      	ldr	r3, [r3, #4]
 800b122:	f423 327c 	bic.w	r2, r3, #258048	@ 0x3f000
 800b126:	687b      	ldr	r3, [r7, #4]
 800b128:	691b      	ldr	r3, [r3, #16]
 800b12a:	031b      	lsls	r3, r3, #12
 800b12c:	4901      	ldr	r1, [pc, #4]	@ (800b134 <HAL_RCC_OscConfig+0x288>)
 800b12e:	4313      	orrs	r3, r2
 800b130:	604b      	str	r3, [r1, #4]
 800b132:	e025      	b.n	800b180 <HAL_RCC_OscConfig+0x2d4>
 800b134:	58024400 	.word	0x58024400
 800b138:	4b9a      	ldr	r3, [pc, #616]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b13a:	685b      	ldr	r3, [r3, #4]
 800b13c:	f023 42fe 	bic.w	r2, r3, #2130706432	@ 0x7f000000
 800b140:	687b      	ldr	r3, [r7, #4]
 800b142:	691b      	ldr	r3, [r3, #16]
 800b144:	061b      	lsls	r3, r3, #24
 800b146:	4997      	ldr	r1, [pc, #604]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b148:	4313      	orrs	r3, r2
 800b14a:	604b      	str	r3, [r1, #4]
 800b14c:	e018      	b.n	800b180 <HAL_RCC_OscConfig+0x2d4>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 800b14e:	4b95      	ldr	r3, [pc, #596]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b150:	681b      	ldr	r3, [r3, #0]
 800b152:	4a94      	ldr	r2, [pc, #592]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b154:	f023 0301 	bic.w	r3, r3, #1
 800b158:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800b15a:	f7fa f96f 	bl	800543c <HAL_GetTick>
 800b15e:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till HSI is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
 800b160:	e008      	b.n	800b174 <HAL_RCC_OscConfig+0x2c8>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 800b162:	f7fa f96b 	bl	800543c <HAL_GetTick>
 800b166:	4602      	mov	r2, r0
 800b168:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b16a:	1ad3      	subs	r3, r2, r3
 800b16c:	2b02      	cmp	r3, #2
 800b16e:	d901      	bls.n	800b174 <HAL_RCC_OscConfig+0x2c8>
          {
            return HAL_TIMEOUT;
 800b170:	2303      	movs	r3, #3
 800b172:	e2ed      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
 800b174:	4b8b      	ldr	r3, [pc, #556]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b176:	681b      	ldr	r3, [r3, #0]
 800b178:	f003 0304 	and.w	r3, r3, #4
 800b17c:	2b00      	cmp	r3, #0
 800b17e:	d1f0      	bne.n	800b162 <HAL_RCC_OscConfig+0x2b6>
        }
      }
    }
  }
  /*----------------------------- CSI Configuration --------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
 800b180:	687b      	ldr	r3, [r7, #4]
 800b182:	681b      	ldr	r3, [r3, #0]
 800b184:	f003 0310 	and.w	r3, r3, #16
 800b188:	2b00      	cmp	r3, #0
 800b18a:	f000 80a9 	beq.w	800b2e0 <HAL_RCC_OscConfig+0x434>
    /* Check the parameters */
    assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
    assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));

    /* When the CSI is used as system clock it will not disabled */
    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
 800b18e:	4b85      	ldr	r3, [pc, #532]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b190:	691b      	ldr	r3, [r3, #16]
 800b192:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 800b196:	61bb      	str	r3, [r7, #24]
    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
 800b198:	4b82      	ldr	r3, [pc, #520]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b19a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800b19c:	617b      	str	r3, [r7, #20]
    if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
 800b19e:	69bb      	ldr	r3, [r7, #24]
 800b1a0:	2b08      	cmp	r3, #8
 800b1a2:	d007      	beq.n	800b1b4 <HAL_RCC_OscConfig+0x308>
 800b1a4:	69bb      	ldr	r3, [r7, #24]
 800b1a6:	2b18      	cmp	r3, #24
 800b1a8:	d13a      	bne.n	800b220 <HAL_RCC_OscConfig+0x374>
 800b1aa:	697b      	ldr	r3, [r7, #20]
 800b1ac:	f003 0303 	and.w	r3, r3, #3
 800b1b0:	2b01      	cmp	r3, #1
 800b1b2:	d135      	bne.n	800b220 <HAL_RCC_OscConfig+0x374>
    {
      /* When CSI is used as system clock it will not disabled */
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
 800b1b4:	4b7b      	ldr	r3, [pc, #492]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b1b6:	681b      	ldr	r3, [r3, #0]
 800b1b8:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800b1bc:	2b00      	cmp	r3, #0
 800b1be:	d005      	beq.n	800b1cc <HAL_RCC_OscConfig+0x320>
 800b1c0:	687b      	ldr	r3, [r7, #4]
 800b1c2:	69db      	ldr	r3, [r3, #28]
 800b1c4:	2b80      	cmp	r3, #128	@ 0x80
 800b1c6:	d001      	beq.n	800b1cc <HAL_RCC_OscConfig+0x320>
      {
        return HAL_ERROR;
 800b1c8:	2301      	movs	r3, #1
 800b1ca:	e2c1      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
 800b1cc:	f7fa f942 	bl	8005454 <HAL_GetREVID>
 800b1d0:	4603      	mov	r3, r0
 800b1d2:	f241 0203 	movw	r2, #4099	@ 0x1003
 800b1d6:	4293      	cmp	r3, r2
 800b1d8:	d817      	bhi.n	800b20a <HAL_RCC_OscConfig+0x35e>
 800b1da:	687b      	ldr	r3, [r7, #4]
 800b1dc:	6a1b      	ldr	r3, [r3, #32]
 800b1de:	2b20      	cmp	r3, #32
 800b1e0:	d108      	bne.n	800b1f4 <HAL_RCC_OscConfig+0x348>
 800b1e2:	4b70      	ldr	r3, [pc, #448]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b1e4:	685b      	ldr	r3, [r3, #4]
 800b1e6:	f023 43f8 	bic.w	r3, r3, #2080374784	@ 0x7c000000
 800b1ea:	4a6e      	ldr	r2, [pc, #440]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b1ec:	f043 4380 	orr.w	r3, r3, #1073741824	@ 0x40000000
 800b1f0:	6053      	str	r3, [r2, #4]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
 800b1f2:	e075      	b.n	800b2e0 <HAL_RCC_OscConfig+0x434>
        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
 800b1f4:	4b6b      	ldr	r3, [pc, #428]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b1f6:	685b      	ldr	r3, [r3, #4]
 800b1f8:	f023 42f8 	bic.w	r2, r3, #2080374784	@ 0x7c000000
 800b1fc:	687b      	ldr	r3, [r7, #4]
 800b1fe:	6a1b      	ldr	r3, [r3, #32]
 800b200:	069b      	lsls	r3, r3, #26
 800b202:	4968      	ldr	r1, [pc, #416]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b204:	4313      	orrs	r3, r2
 800b206:	604b      	str	r3, [r1, #4]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
 800b208:	e06a      	b.n	800b2e0 <HAL_RCC_OscConfig+0x434>
        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
 800b20a:	4b66      	ldr	r3, [pc, #408]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b20c:	68db      	ldr	r3, [r3, #12]
 800b20e:	f023 527c 	bic.w	r2, r3, #1056964608	@ 0x3f000000
 800b212:	687b      	ldr	r3, [r7, #4]
 800b214:	6a1b      	ldr	r3, [r3, #32]
 800b216:	061b      	lsls	r3, r3, #24
 800b218:	4962      	ldr	r1, [pc, #392]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b21a:	4313      	orrs	r3, r2
 800b21c:	60cb      	str	r3, [r1, #12]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
 800b21e:	e05f      	b.n	800b2e0 <HAL_RCC_OscConfig+0x434>
      }
    }
    else
    {
      /* Check the CSI State */
      if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
 800b220:	687b      	ldr	r3, [r7, #4]
 800b222:	69db      	ldr	r3, [r3, #28]
 800b224:	2b00      	cmp	r3, #0
 800b226:	d042      	beq.n	800b2ae <HAL_RCC_OscConfig+0x402>
      {
        /* Enable the Internal High Speed oscillator (CSI). */
        __HAL_RCC_CSI_ENABLE();
 800b228:	4b5e      	ldr	r3, [pc, #376]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b22a:	681b      	ldr	r3, [r3, #0]
 800b22c:	4a5d      	ldr	r2, [pc, #372]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b22e:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 800b232:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800b234:	f7fa f902 	bl	800543c <HAL_GetTick>
 800b238:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till CSI is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
 800b23a:	e008      	b.n	800b24e <HAL_RCC_OscConfig+0x3a2>
        {
          if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
 800b23c:	f7fa f8fe 	bl	800543c <HAL_GetTick>
 800b240:	4602      	mov	r2, r0
 800b242:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b244:	1ad3      	subs	r3, r2, r3
 800b246:	2b02      	cmp	r3, #2
 800b248:	d901      	bls.n	800b24e <HAL_RCC_OscConfig+0x3a2>
          {
            return HAL_TIMEOUT;
 800b24a:	2303      	movs	r3, #3
 800b24c:	e280      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
 800b24e:	4b55      	ldr	r3, [pc, #340]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b250:	681b      	ldr	r3, [r3, #0]
 800b252:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800b256:	2b00      	cmp	r3, #0
 800b258:	d0f0      	beq.n	800b23c <HAL_RCC_OscConfig+0x390>
          }
        }

        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
 800b25a:	f7fa f8fb 	bl	8005454 <HAL_GetREVID>
 800b25e:	4603      	mov	r3, r0
 800b260:	f241 0203 	movw	r2, #4099	@ 0x1003
 800b264:	4293      	cmp	r3, r2
 800b266:	d817      	bhi.n	800b298 <HAL_RCC_OscConfig+0x3ec>
 800b268:	687b      	ldr	r3, [r7, #4]
 800b26a:	6a1b      	ldr	r3, [r3, #32]
 800b26c:	2b20      	cmp	r3, #32
 800b26e:	d108      	bne.n	800b282 <HAL_RCC_OscConfig+0x3d6>
 800b270:	4b4c      	ldr	r3, [pc, #304]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b272:	685b      	ldr	r3, [r3, #4]
 800b274:	f023 43f8 	bic.w	r3, r3, #2080374784	@ 0x7c000000
 800b278:	4a4a      	ldr	r2, [pc, #296]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b27a:	f043 4380 	orr.w	r3, r3, #1073741824	@ 0x40000000
 800b27e:	6053      	str	r3, [r2, #4]
 800b280:	e02e      	b.n	800b2e0 <HAL_RCC_OscConfig+0x434>
 800b282:	4b48      	ldr	r3, [pc, #288]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b284:	685b      	ldr	r3, [r3, #4]
 800b286:	f023 42f8 	bic.w	r2, r3, #2080374784	@ 0x7c000000
 800b28a:	687b      	ldr	r3, [r7, #4]
 800b28c:	6a1b      	ldr	r3, [r3, #32]
 800b28e:	069b      	lsls	r3, r3, #26
 800b290:	4944      	ldr	r1, [pc, #272]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b292:	4313      	orrs	r3, r2
 800b294:	604b      	str	r3, [r1, #4]
 800b296:	e023      	b.n	800b2e0 <HAL_RCC_OscConfig+0x434>
 800b298:	4b42      	ldr	r3, [pc, #264]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b29a:	68db      	ldr	r3, [r3, #12]
 800b29c:	f023 527c 	bic.w	r2, r3, #1056964608	@ 0x3f000000
 800b2a0:	687b      	ldr	r3, [r7, #4]
 800b2a2:	6a1b      	ldr	r3, [r3, #32]
 800b2a4:	061b      	lsls	r3, r3, #24
 800b2a6:	493f      	ldr	r1, [pc, #252]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b2a8:	4313      	orrs	r3, r2
 800b2aa:	60cb      	str	r3, [r1, #12]
 800b2ac:	e018      	b.n	800b2e0 <HAL_RCC_OscConfig+0x434>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (CSI). */
        __HAL_RCC_CSI_DISABLE();
 800b2ae:	4b3d      	ldr	r3, [pc, #244]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b2b0:	681b      	ldr	r3, [r3, #0]
 800b2b2:	4a3c      	ldr	r2, [pc, #240]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b2b4:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 800b2b8:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800b2ba:	f7fa f8bf 	bl	800543c <HAL_GetTick>
 800b2be:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till CSI is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
 800b2c0:	e008      	b.n	800b2d4 <HAL_RCC_OscConfig+0x428>
        {
          if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
 800b2c2:	f7fa f8bb 	bl	800543c <HAL_GetTick>
 800b2c6:	4602      	mov	r2, r0
 800b2c8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b2ca:	1ad3      	subs	r3, r2, r3
 800b2cc:	2b02      	cmp	r3, #2
 800b2ce:	d901      	bls.n	800b2d4 <HAL_RCC_OscConfig+0x428>
          {
            return HAL_TIMEOUT;
 800b2d0:	2303      	movs	r3, #3
 800b2d2:	e23d      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
 800b2d4:	4b33      	ldr	r3, [pc, #204]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b2d6:	681b      	ldr	r3, [r3, #0]
 800b2d8:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800b2dc:	2b00      	cmp	r3, #0
 800b2de:	d1f0      	bne.n	800b2c2 <HAL_RCC_OscConfig+0x416>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 800b2e0:	687b      	ldr	r3, [r7, #4]
 800b2e2:	681b      	ldr	r3, [r3, #0]
 800b2e4:	f003 0308 	and.w	r3, r3, #8
 800b2e8:	2b00      	cmp	r3, #0
 800b2ea:	d036      	beq.n	800b35a <HAL_RCC_OscConfig+0x4ae>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
 800b2ec:	687b      	ldr	r3, [r7, #4]
 800b2ee:	695b      	ldr	r3, [r3, #20]
 800b2f0:	2b00      	cmp	r3, #0
 800b2f2:	d019      	beq.n	800b328 <HAL_RCC_OscConfig+0x47c>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 800b2f4:	4b2b      	ldr	r3, [pc, #172]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b2f6:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 800b2f8:	4a2a      	ldr	r2, [pc, #168]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b2fa:	f043 0301 	orr.w	r3, r3, #1
 800b2fe:	6753      	str	r3, [r2, #116]	@ 0x74

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 800b300:	f7fa f89c 	bl	800543c <HAL_GetTick>
 800b304:	6278      	str	r0, [r7, #36]	@ 0x24

      /* Wait till LSI is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
 800b306:	e008      	b.n	800b31a <HAL_RCC_OscConfig+0x46e>
      {
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 800b308:	f7fa f898 	bl	800543c <HAL_GetTick>
 800b30c:	4602      	mov	r2, r0
 800b30e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b310:	1ad3      	subs	r3, r2, r3
 800b312:	2b02      	cmp	r3, #2
 800b314:	d901      	bls.n	800b31a <HAL_RCC_OscConfig+0x46e>
        {
          return HAL_TIMEOUT;
 800b316:	2303      	movs	r3, #3
 800b318:	e21a      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
 800b31a:	4b22      	ldr	r3, [pc, #136]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b31c:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 800b31e:	f003 0302 	and.w	r3, r3, #2
 800b322:	2b00      	cmp	r3, #0
 800b324:	d0f0      	beq.n	800b308 <HAL_RCC_OscConfig+0x45c>
 800b326:	e018      	b.n	800b35a <HAL_RCC_OscConfig+0x4ae>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 800b328:	4b1e      	ldr	r3, [pc, #120]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b32a:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 800b32c:	4a1d      	ldr	r2, [pc, #116]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b32e:	f023 0301 	bic.w	r3, r3, #1
 800b332:	6753      	str	r3, [r2, #116]	@ 0x74

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 800b334:	f7fa f882 	bl	800543c <HAL_GetTick>
 800b338:	6278      	str	r0, [r7, #36]	@ 0x24

      /* Wait till LSI is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
 800b33a:	e008      	b.n	800b34e <HAL_RCC_OscConfig+0x4a2>
      {
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 800b33c:	f7fa f87e 	bl	800543c <HAL_GetTick>
 800b340:	4602      	mov	r2, r0
 800b342:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b344:	1ad3      	subs	r3, r2, r3
 800b346:	2b02      	cmp	r3, #2
 800b348:	d901      	bls.n	800b34e <HAL_RCC_OscConfig+0x4a2>
        {
          return HAL_TIMEOUT;
 800b34a:	2303      	movs	r3, #3
 800b34c:	e200      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
 800b34e:	4b15      	ldr	r3, [pc, #84]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b350:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 800b352:	f003 0302 	and.w	r3, r3, #2
 800b356:	2b00      	cmp	r3, #0
 800b358:	d1f0      	bne.n	800b33c <HAL_RCC_OscConfig+0x490>
      }
    }
  }

  /*------------------------------ HSI48 Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
 800b35a:	687b      	ldr	r3, [r7, #4]
 800b35c:	681b      	ldr	r3, [r3, #0]
 800b35e:	f003 0320 	and.w	r3, r3, #32
 800b362:	2b00      	cmp	r3, #0
 800b364:	d039      	beq.n	800b3da <HAL_RCC_OscConfig+0x52e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));

    /* Check the HSI48 State */
    if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
 800b366:	687b      	ldr	r3, [r7, #4]
 800b368:	699b      	ldr	r3, [r3, #24]
 800b36a:	2b00      	cmp	r3, #0
 800b36c:	d01c      	beq.n	800b3a8 <HAL_RCC_OscConfig+0x4fc>
    {
      /* Enable the Internal Low Speed oscillator (HSI48). */
      __HAL_RCC_HSI48_ENABLE();
 800b36e:	4b0d      	ldr	r3, [pc, #52]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b370:	681b      	ldr	r3, [r3, #0]
 800b372:	4a0c      	ldr	r2, [pc, #48]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b374:	f443 5380 	orr.w	r3, r3, #4096	@ 0x1000
 800b378:	6013      	str	r3, [r2, #0]

      /* Get time-out */
      tickstart = HAL_GetTick();
 800b37a:	f7fa f85f 	bl	800543c <HAL_GetTick>
 800b37e:	6278      	str	r0, [r7, #36]	@ 0x24

      /* Wait till HSI48 is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
 800b380:	e008      	b.n	800b394 <HAL_RCC_OscConfig+0x4e8>
      {
        if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
 800b382:	f7fa f85b 	bl	800543c <HAL_GetTick>
 800b386:	4602      	mov	r2, r0
 800b388:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b38a:	1ad3      	subs	r3, r2, r3
 800b38c:	2b02      	cmp	r3, #2
 800b38e:	d901      	bls.n	800b394 <HAL_RCC_OscConfig+0x4e8>
        {
          return HAL_TIMEOUT;
 800b390:	2303      	movs	r3, #3
 800b392:	e1dd      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
 800b394:	4b03      	ldr	r3, [pc, #12]	@ (800b3a4 <HAL_RCC_OscConfig+0x4f8>)
 800b396:	681b      	ldr	r3, [r3, #0]
 800b398:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 800b39c:	2b00      	cmp	r3, #0
 800b39e:	d0f0      	beq.n	800b382 <HAL_RCC_OscConfig+0x4d6>
 800b3a0:	e01b      	b.n	800b3da <HAL_RCC_OscConfig+0x52e>
 800b3a2:	bf00      	nop
 800b3a4:	58024400 	.word	0x58024400
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (HSI48). */
      __HAL_RCC_HSI48_DISABLE();
 800b3a8:	4b9b      	ldr	r3, [pc, #620]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b3aa:	681b      	ldr	r3, [r3, #0]
 800b3ac:	4a9a      	ldr	r2, [pc, #616]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b3ae:	f423 5380 	bic.w	r3, r3, #4096	@ 0x1000
 800b3b2:	6013      	str	r3, [r2, #0]

      /* Get time-out */
      tickstart = HAL_GetTick();
 800b3b4:	f7fa f842 	bl	800543c <HAL_GetTick>
 800b3b8:	6278      	str	r0, [r7, #36]	@ 0x24

      /* Wait till HSI48 is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
 800b3ba:	e008      	b.n	800b3ce <HAL_RCC_OscConfig+0x522>
      {
        if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
 800b3bc:	f7fa f83e 	bl	800543c <HAL_GetTick>
 800b3c0:	4602      	mov	r2, r0
 800b3c2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b3c4:	1ad3      	subs	r3, r2, r3
 800b3c6:	2b02      	cmp	r3, #2
 800b3c8:	d901      	bls.n	800b3ce <HAL_RCC_OscConfig+0x522>
        {
          return HAL_TIMEOUT;
 800b3ca:	2303      	movs	r3, #3
 800b3cc:	e1c0      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
 800b3ce:	4b92      	ldr	r3, [pc, #584]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b3d0:	681b      	ldr	r3, [r3, #0]
 800b3d2:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 800b3d6:	2b00      	cmp	r3, #0
 800b3d8:	d1f0      	bne.n	800b3bc <HAL_RCC_OscConfig+0x510>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 800b3da:	687b      	ldr	r3, [r7, #4]
 800b3dc:	681b      	ldr	r3, [r3, #0]
 800b3de:	f003 0304 	and.w	r3, r3, #4
 800b3e2:	2b00      	cmp	r3, #0
 800b3e4:	f000 8081 	beq.w	800b4ea <HAL_RCC_OscConfig+0x63e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Enable write access to Backup domain */
    PWR->CR1 |= PWR_CR1_DBP;
 800b3e8:	4b8c      	ldr	r3, [pc, #560]	@ (800b61c <HAL_RCC_OscConfig+0x770>)
 800b3ea:	681b      	ldr	r3, [r3, #0]
 800b3ec:	4a8b      	ldr	r2, [pc, #556]	@ (800b61c <HAL_RCC_OscConfig+0x770>)
 800b3ee:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 800b3f2:	6013      	str	r3, [r2, #0]

    /* Wait for Backup domain Write protection disable */
    tickstart = HAL_GetTick();
 800b3f4:	f7fa f822 	bl	800543c <HAL_GetTick>
 800b3f8:	6278      	str	r0, [r7, #36]	@ 0x24

    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
 800b3fa:	e008      	b.n	800b40e <HAL_RCC_OscConfig+0x562>
    {
      if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 800b3fc:	f7fa f81e 	bl	800543c <HAL_GetTick>
 800b400:	4602      	mov	r2, r0
 800b402:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b404:	1ad3      	subs	r3, r2, r3
 800b406:	2b64      	cmp	r3, #100	@ 0x64
 800b408:	d901      	bls.n	800b40e <HAL_RCC_OscConfig+0x562>
      {
        return HAL_TIMEOUT;
 800b40a:	2303      	movs	r3, #3
 800b40c:	e1a0      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
 800b40e:	4b83      	ldr	r3, [pc, #524]	@ (800b61c <HAL_RCC_OscConfig+0x770>)
 800b410:	681b      	ldr	r3, [r3, #0]
 800b412:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800b416:	2b00      	cmp	r3, #0
 800b418:	d0f0      	beq.n	800b3fc <HAL_RCC_OscConfig+0x550>
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 800b41a:	687b      	ldr	r3, [r7, #4]
 800b41c:	689b      	ldr	r3, [r3, #8]
 800b41e:	2b01      	cmp	r3, #1
 800b420:	d106      	bne.n	800b430 <HAL_RCC_OscConfig+0x584>
 800b422:	4b7d      	ldr	r3, [pc, #500]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b424:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800b426:	4a7c      	ldr	r2, [pc, #496]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b428:	f043 0301 	orr.w	r3, r3, #1
 800b42c:	6713      	str	r3, [r2, #112]	@ 0x70
 800b42e:	e02d      	b.n	800b48c <HAL_RCC_OscConfig+0x5e0>
 800b430:	687b      	ldr	r3, [r7, #4]
 800b432:	689b      	ldr	r3, [r3, #8]
 800b434:	2b00      	cmp	r3, #0
 800b436:	d10c      	bne.n	800b452 <HAL_RCC_OscConfig+0x5a6>
 800b438:	4b77      	ldr	r3, [pc, #476]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b43a:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800b43c:	4a76      	ldr	r2, [pc, #472]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b43e:	f023 0301 	bic.w	r3, r3, #1
 800b442:	6713      	str	r3, [r2, #112]	@ 0x70
 800b444:	4b74      	ldr	r3, [pc, #464]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b446:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800b448:	4a73      	ldr	r2, [pc, #460]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b44a:	f023 0304 	bic.w	r3, r3, #4
 800b44e:	6713      	str	r3, [r2, #112]	@ 0x70
 800b450:	e01c      	b.n	800b48c <HAL_RCC_OscConfig+0x5e0>
 800b452:	687b      	ldr	r3, [r7, #4]
 800b454:	689b      	ldr	r3, [r3, #8]
 800b456:	2b05      	cmp	r3, #5
 800b458:	d10c      	bne.n	800b474 <HAL_RCC_OscConfig+0x5c8>
 800b45a:	4b6f      	ldr	r3, [pc, #444]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b45c:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800b45e:	4a6e      	ldr	r2, [pc, #440]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b460:	f043 0304 	orr.w	r3, r3, #4
 800b464:	6713      	str	r3, [r2, #112]	@ 0x70
 800b466:	4b6c      	ldr	r3, [pc, #432]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b468:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800b46a:	4a6b      	ldr	r2, [pc, #428]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b46c:	f043 0301 	orr.w	r3, r3, #1
 800b470:	6713      	str	r3, [r2, #112]	@ 0x70
 800b472:	e00b      	b.n	800b48c <HAL_RCC_OscConfig+0x5e0>
 800b474:	4b68      	ldr	r3, [pc, #416]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b476:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800b478:	4a67      	ldr	r2, [pc, #412]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b47a:	f023 0301 	bic.w	r3, r3, #1
 800b47e:	6713      	str	r3, [r2, #112]	@ 0x70
 800b480:	4b65      	ldr	r3, [pc, #404]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b482:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800b484:	4a64      	ldr	r2, [pc, #400]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b486:	f023 0304 	bic.w	r3, r3, #4
 800b48a:	6713      	str	r3, [r2, #112]	@ 0x70
    /* Check the LSE State */
    if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
 800b48c:	687b      	ldr	r3, [r7, #4]
 800b48e:	689b      	ldr	r3, [r3, #8]
 800b490:	2b00      	cmp	r3, #0
 800b492:	d015      	beq.n	800b4c0 <HAL_RCC_OscConfig+0x614>
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 800b494:	f7f9 ffd2 	bl	800543c <HAL_GetTick>
 800b498:	6278      	str	r0, [r7, #36]	@ 0x24

      /* Wait till LSE is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 800b49a:	e00a      	b.n	800b4b2 <HAL_RCC_OscConfig+0x606>
      {
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800b49c:	f7f9 ffce 	bl	800543c <HAL_GetTick>
 800b4a0:	4602      	mov	r2, r0
 800b4a2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b4a4:	1ad3      	subs	r3, r2, r3
 800b4a6:	f241 3288 	movw	r2, #5000	@ 0x1388
 800b4aa:	4293      	cmp	r3, r2
 800b4ac:	d901      	bls.n	800b4b2 <HAL_RCC_OscConfig+0x606>
        {
          return HAL_TIMEOUT;
 800b4ae:	2303      	movs	r3, #3
 800b4b0:	e14e      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 800b4b2:	4b59      	ldr	r3, [pc, #356]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b4b4:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800b4b6:	f003 0302 	and.w	r3, r3, #2
 800b4ba:	2b00      	cmp	r3, #0
 800b4bc:	d0ee      	beq.n	800b49c <HAL_RCC_OscConfig+0x5f0>
 800b4be:	e014      	b.n	800b4ea <HAL_RCC_OscConfig+0x63e>
      }
    }
    else
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 800b4c0:	f7f9 ffbc 	bl	800543c <HAL_GetTick>
 800b4c4:	6278      	str	r0, [r7, #36]	@ 0x24

      /* Wait till LSE is disabled */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
 800b4c6:	e00a      	b.n	800b4de <HAL_RCC_OscConfig+0x632>
      {
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800b4c8:	f7f9 ffb8 	bl	800543c <HAL_GetTick>
 800b4cc:	4602      	mov	r2, r0
 800b4ce:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b4d0:	1ad3      	subs	r3, r2, r3
 800b4d2:	f241 3288 	movw	r2, #5000	@ 0x1388
 800b4d6:	4293      	cmp	r3, r2
 800b4d8:	d901      	bls.n	800b4de <HAL_RCC_OscConfig+0x632>
        {
          return HAL_TIMEOUT;
 800b4da:	2303      	movs	r3, #3
 800b4dc:	e138      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
 800b4de:	4b4e      	ldr	r3, [pc, #312]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b4e0:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800b4e2:	f003 0302 	and.w	r3, r3, #2
 800b4e6:	2b00      	cmp	r3, #0
 800b4e8:	d1ee      	bne.n	800b4c8 <HAL_RCC_OscConfig+0x61c>
    }
  }
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 800b4ea:	687b      	ldr	r3, [r7, #4]
 800b4ec:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800b4ee:	2b00      	cmp	r3, #0
 800b4f0:	f000 812d 	beq.w	800b74e <HAL_RCC_OscConfig+0x8a2>
  {
    /* Check if the PLL is used as system clock or not */
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
 800b4f4:	4b48      	ldr	r3, [pc, #288]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b4f6:	691b      	ldr	r3, [r3, #16]
 800b4f8:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 800b4fc:	2b18      	cmp	r3, #24
 800b4fe:	f000 80bd 	beq.w	800b67c <HAL_RCC_OscConfig+0x7d0>
    {
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 800b502:	687b      	ldr	r3, [r7, #4]
 800b504:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800b506:	2b02      	cmp	r3, #2
 800b508:	f040 809e 	bne.w	800b648 <HAL_RCC_OscConfig+0x79c>
        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
        assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 800b50c:	4b42      	ldr	r3, [pc, #264]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b50e:	681b      	ldr	r3, [r3, #0]
 800b510:	4a41      	ldr	r2, [pc, #260]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b512:	f023 7380 	bic.w	r3, r3, #16777216	@ 0x1000000
 800b516:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800b518:	f7f9 ff90 	bl	800543c <HAL_GetTick>
 800b51c:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till PLL is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 800b51e:	e008      	b.n	800b532 <HAL_RCC_OscConfig+0x686>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 800b520:	f7f9 ff8c 	bl	800543c <HAL_GetTick>
 800b524:	4602      	mov	r2, r0
 800b526:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b528:	1ad3      	subs	r3, r2, r3
 800b52a:	2b02      	cmp	r3, #2
 800b52c:	d901      	bls.n	800b532 <HAL_RCC_OscConfig+0x686>
          {
            return HAL_TIMEOUT;
 800b52e:	2303      	movs	r3, #3
 800b530:	e10e      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 800b532:	4b39      	ldr	r3, [pc, #228]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b534:	681b      	ldr	r3, [r3, #0]
 800b536:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800b53a:	2b00      	cmp	r3, #0
 800b53c:	d1f0      	bne.n	800b520 <HAL_RCC_OscConfig+0x674>
          }
        }

        /* Configure the main PLL clock source, multiplication and division factors. */
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 800b53e:	4b36      	ldr	r3, [pc, #216]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b540:	6a9a      	ldr	r2, [r3, #40]	@ 0x28
 800b542:	4b37      	ldr	r3, [pc, #220]	@ (800b620 <HAL_RCC_OscConfig+0x774>)
 800b544:	4013      	ands	r3, r2
 800b546:	687a      	ldr	r2, [r7, #4]
 800b548:	6a91      	ldr	r1, [r2, #40]	@ 0x28
 800b54a:	687a      	ldr	r2, [r7, #4]
 800b54c:	6ad2      	ldr	r2, [r2, #44]	@ 0x2c
 800b54e:	0112      	lsls	r2, r2, #4
 800b550:	430a      	orrs	r2, r1
 800b552:	4931      	ldr	r1, [pc, #196]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b554:	4313      	orrs	r3, r2
 800b556:	628b      	str	r3, [r1, #40]	@ 0x28
 800b558:	687b      	ldr	r3, [r7, #4]
 800b55a:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800b55c:	3b01      	subs	r3, #1
 800b55e:	f3c3 0208 	ubfx	r2, r3, #0, #9
 800b562:	687b      	ldr	r3, [r7, #4]
 800b564:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 800b566:	3b01      	subs	r3, #1
 800b568:	025b      	lsls	r3, r3, #9
 800b56a:	b29b      	uxth	r3, r3
 800b56c:	431a      	orrs	r2, r3
 800b56e:	687b      	ldr	r3, [r7, #4]
 800b570:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800b572:	3b01      	subs	r3, #1
 800b574:	041b      	lsls	r3, r3, #16
 800b576:	f403 03fe 	and.w	r3, r3, #8323072	@ 0x7f0000
 800b57a:	431a      	orrs	r2, r3
 800b57c:	687b      	ldr	r3, [r7, #4]
 800b57e:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 800b580:	3b01      	subs	r3, #1
 800b582:	061b      	lsls	r3, r3, #24
 800b584:	f003 43fe 	and.w	r3, r3, #2130706432	@ 0x7f000000
 800b588:	4923      	ldr	r1, [pc, #140]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b58a:	4313      	orrs	r3, r2
 800b58c:	630b      	str	r3, [r1, #48]	@ 0x30
                             RCC_OscInitStruct->PLL.PLLP,
                             RCC_OscInitStruct->PLL.PLLQ,
                             RCC_OscInitStruct->PLL.PLLR);

        /* Disable PLLFRACN . */
        __HAL_RCC_PLLFRACN_DISABLE();
 800b58e:	4b22      	ldr	r3, [pc, #136]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b590:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800b592:	4a21      	ldr	r2, [pc, #132]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b594:	f023 0301 	bic.w	r3, r3, #1
 800b598:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* Configure PLL PLL1FRACN */
        __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
 800b59a:	4b1f      	ldr	r3, [pc, #124]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b59c:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 800b59e:	4b21      	ldr	r3, [pc, #132]	@ (800b624 <HAL_RCC_OscConfig+0x778>)
 800b5a0:	4013      	ands	r3, r2
 800b5a2:	687a      	ldr	r2, [r7, #4]
 800b5a4:	6c92      	ldr	r2, [r2, #72]	@ 0x48
 800b5a6:	00d2      	lsls	r2, r2, #3
 800b5a8:	491b      	ldr	r1, [pc, #108]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5aa:	4313      	orrs	r3, r2
 800b5ac:	634b      	str	r3, [r1, #52]	@ 0x34

        /* Select PLL1 input reference frequency range: VCI */
        __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
 800b5ae:	4b1a      	ldr	r3, [pc, #104]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5b0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800b5b2:	f023 020c 	bic.w	r2, r3, #12
 800b5b6:	687b      	ldr	r3, [r7, #4]
 800b5b8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800b5ba:	4917      	ldr	r1, [pc, #92]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5bc:	4313      	orrs	r3, r2
 800b5be:	62cb      	str	r3, [r1, #44]	@ 0x2c

        /* Select PLL1 output frequency range : VCO */
        __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
 800b5c0:	4b15      	ldr	r3, [pc, #84]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5c2:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800b5c4:	f023 0202 	bic.w	r2, r3, #2
 800b5c8:	687b      	ldr	r3, [r7, #4]
 800b5ca:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 800b5cc:	4912      	ldr	r1, [pc, #72]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5ce:	4313      	orrs	r3, r2
 800b5d0:	62cb      	str	r3, [r1, #44]	@ 0x2c

        /* Enable PLL System Clock output. */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
 800b5d2:	4b11      	ldr	r3, [pc, #68]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5d4:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800b5d6:	4a10      	ldr	r2, [pc, #64]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5d8:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800b5dc:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* Enable PLL1Q Clock output. */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800b5de:	4b0e      	ldr	r3, [pc, #56]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5e0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800b5e2:	4a0d      	ldr	r2, [pc, #52]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5e4:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800b5e8:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* Enable PLL1R  Clock output. */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
 800b5ea:	4b0b      	ldr	r3, [pc, #44]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5ec:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800b5ee:	4a0a      	ldr	r2, [pc, #40]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5f0:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
 800b5f4:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* Enable PLL1FRACN . */
        __HAL_RCC_PLLFRACN_ENABLE();
 800b5f6:	4b08      	ldr	r3, [pc, #32]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5f8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800b5fa:	4a07      	ldr	r2, [pc, #28]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b5fc:	f043 0301 	orr.w	r3, r3, #1
 800b600:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 800b602:	4b05      	ldr	r3, [pc, #20]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b604:	681b      	ldr	r3, [r3, #0]
 800b606:	4a04      	ldr	r2, [pc, #16]	@ (800b618 <HAL_RCC_OscConfig+0x76c>)
 800b608:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 800b60c:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800b60e:	f7f9 ff15 	bl	800543c <HAL_GetTick>
 800b612:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till PLL is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 800b614:	e011      	b.n	800b63a <HAL_RCC_OscConfig+0x78e>
 800b616:	bf00      	nop
 800b618:	58024400 	.word	0x58024400
 800b61c:	58024800 	.word	0x58024800
 800b620:	fffffc0c 	.word	0xfffffc0c
 800b624:	ffff0007 	.word	0xffff0007
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 800b628:	f7f9 ff08 	bl	800543c <HAL_GetTick>
 800b62c:	4602      	mov	r2, r0
 800b62e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b630:	1ad3      	subs	r3, r2, r3
 800b632:	2b02      	cmp	r3, #2
 800b634:	d901      	bls.n	800b63a <HAL_RCC_OscConfig+0x78e>
          {
            return HAL_TIMEOUT;
 800b636:	2303      	movs	r3, #3
 800b638:	e08a      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 800b63a:	4b47      	ldr	r3, [pc, #284]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b63c:	681b      	ldr	r3, [r3, #0]
 800b63e:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800b642:	2b00      	cmp	r3, #0
 800b644:	d0f0      	beq.n	800b628 <HAL_RCC_OscConfig+0x77c>
 800b646:	e082      	b.n	800b74e <HAL_RCC_OscConfig+0x8a2>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 800b648:	4b43      	ldr	r3, [pc, #268]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b64a:	681b      	ldr	r3, [r3, #0]
 800b64c:	4a42      	ldr	r2, [pc, #264]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b64e:	f023 7380 	bic.w	r3, r3, #16777216	@ 0x1000000
 800b652:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800b654:	f7f9 fef2 	bl	800543c <HAL_GetTick>
 800b658:	6278      	str	r0, [r7, #36]	@ 0x24

        /* Wait till PLL is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 800b65a:	e008      	b.n	800b66e <HAL_RCC_OscConfig+0x7c2>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 800b65c:	f7f9 feee 	bl	800543c <HAL_GetTick>
 800b660:	4602      	mov	r2, r0
 800b662:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b664:	1ad3      	subs	r3, r2, r3
 800b666:	2b02      	cmp	r3, #2
 800b668:	d901      	bls.n	800b66e <HAL_RCC_OscConfig+0x7c2>
          {
            return HAL_TIMEOUT;
 800b66a:	2303      	movs	r3, #3
 800b66c:	e070      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 800b66e:	4b3a      	ldr	r3, [pc, #232]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b670:	681b      	ldr	r3, [r3, #0]
 800b672:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800b676:	2b00      	cmp	r3, #0
 800b678:	d1f0      	bne.n	800b65c <HAL_RCC_OscConfig+0x7b0>
 800b67a:	e068      	b.n	800b74e <HAL_RCC_OscConfig+0x8a2>
      }
    }
    else
    {
      /* Do not return HAL_ERROR if request repeats the current configuration */
      temp1_pllckcfg = RCC->PLLCKSELR;
 800b67c:	4b36      	ldr	r3, [pc, #216]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b67e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800b680:	613b      	str	r3, [r7, #16]
      temp2_pllckcfg = RCC->PLL1DIVR;
 800b682:	4b35      	ldr	r3, [pc, #212]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b684:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800b686:	60fb      	str	r3, [r7, #12]
      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
 800b688:	687b      	ldr	r3, [r7, #4]
 800b68a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800b68c:	2b01      	cmp	r3, #1
 800b68e:	d031      	beq.n	800b6f4 <HAL_RCC_OscConfig+0x848>
          (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 800b690:	693b      	ldr	r3, [r7, #16]
 800b692:	f003 0203 	and.w	r2, r3, #3
 800b696:	687b      	ldr	r3, [r7, #4]
 800b698:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
 800b69a:	429a      	cmp	r2, r3
 800b69c:	d12a      	bne.n	800b6f4 <HAL_RCC_OscConfig+0x848>
          ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
 800b69e:	693b      	ldr	r3, [r7, #16]
 800b6a0:	091b      	lsrs	r3, r3, #4
 800b6a2:	f003 023f 	and.w	r2, r3, #63	@ 0x3f
 800b6a6:	687b      	ldr	r3, [r7, #4]
 800b6a8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
          (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 800b6aa:	429a      	cmp	r2, r3
 800b6ac:	d122      	bne.n	800b6f4 <HAL_RCC_OscConfig+0x848>
          (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
 800b6ae:	68fb      	ldr	r3, [r7, #12]
 800b6b0:	f3c3 0208 	ubfx	r2, r3, #0, #9
 800b6b4:	687b      	ldr	r3, [r7, #4]
 800b6b6:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800b6b8:	3b01      	subs	r3, #1
          ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
 800b6ba:	429a      	cmp	r2, r3
 800b6bc:	d11a      	bne.n	800b6f4 <HAL_RCC_OscConfig+0x848>
          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
 800b6be:	68fb      	ldr	r3, [r7, #12]
 800b6c0:	0a5b      	lsrs	r3, r3, #9
 800b6c2:	f003 027f 	and.w	r2, r3, #127	@ 0x7f
 800b6c6:	687b      	ldr	r3, [r7, #4]
 800b6c8:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 800b6ca:	3b01      	subs	r3, #1
          (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
 800b6cc:	429a      	cmp	r2, r3
 800b6ce:	d111      	bne.n	800b6f4 <HAL_RCC_OscConfig+0x848>
          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
 800b6d0:	68fb      	ldr	r3, [r7, #12]
 800b6d2:	0c1b      	lsrs	r3, r3, #16
 800b6d4:	f003 027f 	and.w	r2, r3, #127	@ 0x7f
 800b6d8:	687b      	ldr	r3, [r7, #4]
 800b6da:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800b6dc:	3b01      	subs	r3, #1
          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
 800b6de:	429a      	cmp	r2, r3
 800b6e0:	d108      	bne.n	800b6f4 <HAL_RCC_OscConfig+0x848>
          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
 800b6e2:	68fb      	ldr	r3, [r7, #12]
 800b6e4:	0e1b      	lsrs	r3, r3, #24
 800b6e6:	f003 027f 	and.w	r2, r3, #127	@ 0x7f
 800b6ea:	687b      	ldr	r3, [r7, #4]
 800b6ec:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 800b6ee:	3b01      	subs	r3, #1
          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
 800b6f0:	429a      	cmp	r2, r3
 800b6f2:	d001      	beq.n	800b6f8 <HAL_RCC_OscConfig+0x84c>
      {
        return HAL_ERROR;
 800b6f4:	2301      	movs	r3, #1
 800b6f6:	e02b      	b.n	800b750 <HAL_RCC_OscConfig+0x8a4>
      }
      else
      {
        /* Check if only fractional part needs to be updated  */
        temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
 800b6f8:	4b17      	ldr	r3, [pc, #92]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b6fa:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 800b6fc:	08db      	lsrs	r3, r3, #3
 800b6fe:	f3c3 030c 	ubfx	r3, r3, #0, #13
 800b702:	613b      	str	r3, [r7, #16]
        if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
 800b704:	687b      	ldr	r3, [r7, #4]
 800b706:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 800b708:	693a      	ldr	r2, [r7, #16]
 800b70a:	429a      	cmp	r2, r3
 800b70c:	d01f      	beq.n	800b74e <HAL_RCC_OscConfig+0x8a2>
        {
          assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
          /* Disable PLL1FRACEN */
          __HAL_RCC_PLLFRACN_DISABLE();
 800b70e:	4b12      	ldr	r3, [pc, #72]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b710:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800b712:	4a11      	ldr	r2, [pc, #68]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b714:	f023 0301 	bic.w	r3, r3, #1
 800b718:	62d3      	str	r3, [r2, #44]	@ 0x2c
          /* Get Start Tick*/
          tickstart = HAL_GetTick();
 800b71a:	f7f9 fe8f 	bl	800543c <HAL_GetTick>
 800b71e:	6278      	str	r0, [r7, #36]	@ 0x24
          /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */
          while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE)
 800b720:	bf00      	nop
 800b722:	f7f9 fe8b 	bl	800543c <HAL_GetTick>
 800b726:	4602      	mov	r2, r0
 800b728:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800b72a:	4293      	cmp	r3, r2
 800b72c:	d0f9      	beq.n	800b722 <HAL_RCC_OscConfig+0x876>
          {
          }
          /* Configure PLL1 PLL1FRACN */
          __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
 800b72e:	4b0a      	ldr	r3, [pc, #40]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b730:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 800b732:	4b0a      	ldr	r3, [pc, #40]	@ (800b75c <HAL_RCC_OscConfig+0x8b0>)
 800b734:	4013      	ands	r3, r2
 800b736:	687a      	ldr	r2, [r7, #4]
 800b738:	6c92      	ldr	r2, [r2, #72]	@ 0x48
 800b73a:	00d2      	lsls	r2, r2, #3
 800b73c:	4906      	ldr	r1, [pc, #24]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b73e:	4313      	orrs	r3, r2
 800b740:	634b      	str	r3, [r1, #52]	@ 0x34
          /* Enable PLL1FRACEN to latch new value. */
          __HAL_RCC_PLLFRACN_ENABLE();
 800b742:	4b05      	ldr	r3, [pc, #20]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b744:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800b746:	4a04      	ldr	r2, [pc, #16]	@ (800b758 <HAL_RCC_OscConfig+0x8ac>)
 800b748:	f043 0301 	orr.w	r3, r3, #1
 800b74c:	62d3      	str	r3, [r2, #44]	@ 0x2c
        }
      }
    }
  }
  return HAL_OK;
 800b74e:	2300      	movs	r3, #0
}
 800b750:	4618      	mov	r0, r3
 800b752:	3730      	adds	r7, #48	@ 0x30
 800b754:	46bd      	mov	sp, r7
 800b756:	bd80      	pop	{r7, pc}
 800b758:	58024400 	.word	0x58024400
 800b75c:	ffff0007 	.word	0xffff0007

0800b760 <HAL_RCC_ClockConfig>:
  *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 800b760:	b580      	push	{r7, lr}
 800b762:	b086      	sub	sp, #24
 800b764:	af00      	add	r7, sp, #0
 800b766:	6078      	str	r0, [r7, #4]
 800b768:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef halstatus;
  uint32_t tickstart;
  uint32_t common_system_clock;

  /* Check Null pointer */
  if (RCC_ClkInitStruct == NULL)
 800b76a:	687b      	ldr	r3, [r7, #4]
 800b76c:	2b00      	cmp	r3, #0
 800b76e:	d101      	bne.n	800b774 <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 800b770:	2301      	movs	r3, #1
 800b772:	e19c      	b.n	800baae <HAL_RCC_ClockConfig+0x34e>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the CPU clock
    (HCLK) and the supply voltage of the device. */

  /* Increasing the CPU frequency */
  if (FLatency > __HAL_FLASH_GET_LATENCY())
 800b774:	4b8a      	ldr	r3, [pc, #552]	@ (800b9a0 <HAL_RCC_ClockConfig+0x240>)
 800b776:	681b      	ldr	r3, [r3, #0]
 800b778:	f003 030f 	and.w	r3, r3, #15
 800b77c:	683a      	ldr	r2, [r7, #0]
 800b77e:	429a      	cmp	r2, r3
 800b780:	d910      	bls.n	800b7a4 <HAL_RCC_ClockConfig+0x44>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 800b782:	4b87      	ldr	r3, [pc, #540]	@ (800b9a0 <HAL_RCC_ClockConfig+0x240>)
 800b784:	681b      	ldr	r3, [r3, #0]
 800b786:	f023 020f 	bic.w	r2, r3, #15
 800b78a:	4985      	ldr	r1, [pc, #532]	@ (800b9a0 <HAL_RCC_ClockConfig+0x240>)
 800b78c:	683b      	ldr	r3, [r7, #0]
 800b78e:	4313      	orrs	r3, r2
 800b790:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 800b792:	4b83      	ldr	r3, [pc, #524]	@ (800b9a0 <HAL_RCC_ClockConfig+0x240>)
 800b794:	681b      	ldr	r3, [r3, #0]
 800b796:	f003 030f 	and.w	r3, r3, #15
 800b79a:	683a      	ldr	r2, [r7, #0]
 800b79c:	429a      	cmp	r2, r3
 800b79e:	d001      	beq.n	800b7a4 <HAL_RCC_ClockConfig+0x44>
    {
      return HAL_ERROR;
 800b7a0:	2301      	movs	r3, #1
 800b7a2:	e184      	b.n	800baae <HAL_RCC_ClockConfig+0x34e>

  }

  /* Increasing the BUS frequency divider */
  /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
 800b7a4:	687b      	ldr	r3, [r7, #4]
 800b7a6:	681b      	ldr	r3, [r3, #0]
 800b7a8:	f003 0304 	and.w	r3, r3, #4
 800b7ac:	2b00      	cmp	r3, #0
 800b7ae:	d010      	beq.n	800b7d2 <HAL_RCC_ClockConfig+0x72>
  {
#if defined (RCC_D1CFGR_D1PPRE)
    if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
 800b7b0:	687b      	ldr	r3, [r7, #4]
 800b7b2:	691a      	ldr	r2, [r3, #16]
 800b7b4:	4b7b      	ldr	r3, [pc, #492]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b7b6:	699b      	ldr	r3, [r3, #24]
 800b7b8:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 800b7bc:	429a      	cmp	r2, r3
 800b7be:	d908      	bls.n	800b7d2 <HAL_RCC_ClockConfig+0x72>
    {
      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
 800b7c0:	4b78      	ldr	r3, [pc, #480]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b7c2:	699b      	ldr	r3, [r3, #24]
 800b7c4:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
 800b7c8:	687b      	ldr	r3, [r7, #4]
 800b7ca:	691b      	ldr	r3, [r3, #16]
 800b7cc:	4975      	ldr	r1, [pc, #468]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b7ce:	4313      	orrs	r3, r2
 800b7d0:	618b      	str	r3, [r1, #24]
    }
#endif
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 800b7d2:	687b      	ldr	r3, [r7, #4]
 800b7d4:	681b      	ldr	r3, [r3, #0]
 800b7d6:	f003 0308 	and.w	r3, r3, #8
 800b7da:	2b00      	cmp	r3, #0
 800b7dc:	d010      	beq.n	800b800 <HAL_RCC_ClockConfig+0xa0>
  {
#if defined (RCC_D2CFGR_D2PPRE1)
    if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
 800b7de:	687b      	ldr	r3, [r7, #4]
 800b7e0:	695a      	ldr	r2, [r3, #20]
 800b7e2:	4b70      	ldr	r3, [pc, #448]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b7e4:	69db      	ldr	r3, [r3, #28]
 800b7e6:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 800b7ea:	429a      	cmp	r2, r3
 800b7ec:	d908      	bls.n	800b800 <HAL_RCC_ClockConfig+0xa0>
    {
      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
 800b7ee:	4b6d      	ldr	r3, [pc, #436]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b7f0:	69db      	ldr	r3, [r3, #28]
 800b7f2:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
 800b7f6:	687b      	ldr	r3, [r7, #4]
 800b7f8:	695b      	ldr	r3, [r3, #20]
 800b7fa:	496a      	ldr	r1, [pc, #424]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b7fc:	4313      	orrs	r3, r2
 800b7fe:	61cb      	str	r3, [r1, #28]
      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
    }
#endif
  }
  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 800b800:	687b      	ldr	r3, [r7, #4]
 800b802:	681b      	ldr	r3, [r3, #0]
 800b804:	f003 0310 	and.w	r3, r3, #16
 800b808:	2b00      	cmp	r3, #0
 800b80a:	d010      	beq.n	800b82e <HAL_RCC_ClockConfig+0xce>
  {
#if defined(RCC_D2CFGR_D2PPRE2)
    if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
 800b80c:	687b      	ldr	r3, [r7, #4]
 800b80e:	699a      	ldr	r2, [r3, #24]
 800b810:	4b64      	ldr	r3, [pc, #400]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b812:	69db      	ldr	r3, [r3, #28]
 800b814:	f403 63e0 	and.w	r3, r3, #1792	@ 0x700
 800b818:	429a      	cmp	r2, r3
 800b81a:	d908      	bls.n	800b82e <HAL_RCC_ClockConfig+0xce>
    {
      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
 800b81c:	4b61      	ldr	r3, [pc, #388]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b81e:	69db      	ldr	r3, [r3, #28]
 800b820:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
 800b824:	687b      	ldr	r3, [r7, #4]
 800b826:	699b      	ldr	r3, [r3, #24]
 800b828:	495e      	ldr	r1, [pc, #376]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b82a:	4313      	orrs	r3, r2
 800b82c:	61cb      	str	r3, [r1, #28]
    }
#endif
  }

  /*-------------------------- D3PCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
 800b82e:	687b      	ldr	r3, [r7, #4]
 800b830:	681b      	ldr	r3, [r3, #0]
 800b832:	f003 0320 	and.w	r3, r3, #32
 800b836:	2b00      	cmp	r3, #0
 800b838:	d010      	beq.n	800b85c <HAL_RCC_ClockConfig+0xfc>
  {
#if defined(RCC_D3CFGR_D3PPRE)
    if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
 800b83a:	687b      	ldr	r3, [r7, #4]
 800b83c:	69da      	ldr	r2, [r3, #28]
 800b83e:	4b59      	ldr	r3, [pc, #356]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b840:	6a1b      	ldr	r3, [r3, #32]
 800b842:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 800b846:	429a      	cmp	r2, r3
 800b848:	d908      	bls.n	800b85c <HAL_RCC_ClockConfig+0xfc>
    {
      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
 800b84a:	4b56      	ldr	r3, [pc, #344]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b84c:	6a1b      	ldr	r3, [r3, #32]
 800b84e:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
 800b852:	687b      	ldr	r3, [r7, #4]
 800b854:	69db      	ldr	r3, [r3, #28]
 800b856:	4953      	ldr	r1, [pc, #332]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b858:	4313      	orrs	r3, r2
 800b85a:	620b      	str	r3, [r1, #32]
    }
#endif
  }

  /*-------------------------- HCLK Configuration --------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 800b85c:	687b      	ldr	r3, [r7, #4]
 800b85e:	681b      	ldr	r3, [r3, #0]
 800b860:	f003 0302 	and.w	r3, r3, #2
 800b864:	2b00      	cmp	r3, #0
 800b866:	d010      	beq.n	800b88a <HAL_RCC_ClockConfig+0x12a>
  {
#if defined (RCC_D1CFGR_HPRE)
    if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
 800b868:	687b      	ldr	r3, [r7, #4]
 800b86a:	68da      	ldr	r2, [r3, #12]
 800b86c:	4b4d      	ldr	r3, [pc, #308]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b86e:	699b      	ldr	r3, [r3, #24]
 800b870:	f003 030f 	and.w	r3, r3, #15
 800b874:	429a      	cmp	r2, r3
 800b876:	d908      	bls.n	800b88a <HAL_RCC_ClockConfig+0x12a>
    {
      /* Set the new HCLK clock divider */
      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 800b878:	4b4a      	ldr	r3, [pc, #296]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b87a:	699b      	ldr	r3, [r3, #24]
 800b87c:	f023 020f 	bic.w	r2, r3, #15
 800b880:	687b      	ldr	r3, [r7, #4]
 800b882:	68db      	ldr	r3, [r3, #12]
 800b884:	4947      	ldr	r1, [pc, #284]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b886:	4313      	orrs	r3, r2
 800b888:	618b      	str	r3, [r1, #24]
    }
#endif
  }

  /*------------------------- SYSCLK Configuration -------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 800b88a:	687b      	ldr	r3, [r7, #4]
 800b88c:	681b      	ldr	r3, [r3, #0]
 800b88e:	f003 0301 	and.w	r3, r3, #1
 800b892:	2b00      	cmp	r3, #0
 800b894:	d055      	beq.n	800b942 <HAL_RCC_ClockConfig+0x1e2>
  {
    assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
#if defined(RCC_D1CFGR_D1CPRE)
    MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
 800b896:	4b43      	ldr	r3, [pc, #268]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b898:	699b      	ldr	r3, [r3, #24]
 800b89a:	f423 6270 	bic.w	r2, r3, #3840	@ 0xf00
 800b89e:	687b      	ldr	r3, [r7, #4]
 800b8a0:	689b      	ldr	r3, [r3, #8]
 800b8a2:	4940      	ldr	r1, [pc, #256]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b8a4:	4313      	orrs	r3, r2
 800b8a6:	618b      	str	r3, [r1, #24]
#else
    MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
#endif
    /* HSE is selected as System Clock Source */
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 800b8a8:	687b      	ldr	r3, [r7, #4]
 800b8aa:	685b      	ldr	r3, [r3, #4]
 800b8ac:	2b02      	cmp	r3, #2
 800b8ae:	d107      	bne.n	800b8c0 <HAL_RCC_ClockConfig+0x160>
    {
      /* Check the HSE ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 800b8b0:	4b3c      	ldr	r3, [pc, #240]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b8b2:	681b      	ldr	r3, [r3, #0]
 800b8b4:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800b8b8:	2b00      	cmp	r3, #0
 800b8ba:	d121      	bne.n	800b900 <HAL_RCC_ClockConfig+0x1a0>
      {
        return HAL_ERROR;
 800b8bc:	2301      	movs	r3, #1
 800b8be:	e0f6      	b.n	800baae <HAL_RCC_ClockConfig+0x34e>
      }
    }
    /* PLL is selected as System Clock Source */
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 800b8c0:	687b      	ldr	r3, [r7, #4]
 800b8c2:	685b      	ldr	r3, [r3, #4]
 800b8c4:	2b03      	cmp	r3, #3
 800b8c6:	d107      	bne.n	800b8d8 <HAL_RCC_ClockConfig+0x178>
    {
      /* Check the PLL ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 800b8c8:	4b36      	ldr	r3, [pc, #216]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b8ca:	681b      	ldr	r3, [r3, #0]
 800b8cc:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800b8d0:	2b00      	cmp	r3, #0
 800b8d2:	d115      	bne.n	800b900 <HAL_RCC_ClockConfig+0x1a0>
      {
        return HAL_ERROR;
 800b8d4:	2301      	movs	r3, #1
 800b8d6:	e0ea      	b.n	800baae <HAL_RCC_ClockConfig+0x34e>
      }
    }
    /* CSI is selected as System Clock Source */
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
 800b8d8:	687b      	ldr	r3, [r7, #4]
 800b8da:	685b      	ldr	r3, [r3, #4]
 800b8dc:	2b01      	cmp	r3, #1
 800b8de:	d107      	bne.n	800b8f0 <HAL_RCC_ClockConfig+0x190>
    {
      /* Check the PLL ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
 800b8e0:	4b30      	ldr	r3, [pc, #192]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b8e2:	681b      	ldr	r3, [r3, #0]
 800b8e4:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800b8e8:	2b00      	cmp	r3, #0
 800b8ea:	d109      	bne.n	800b900 <HAL_RCC_ClockConfig+0x1a0>
      {
        return HAL_ERROR;
 800b8ec:	2301      	movs	r3, #1
 800b8ee:	e0de      	b.n	800baae <HAL_RCC_ClockConfig+0x34e>
    }
    /* HSI is selected as System Clock Source */
    else
    {
      /* Check the HSI ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 800b8f0:	4b2c      	ldr	r3, [pc, #176]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b8f2:	681b      	ldr	r3, [r3, #0]
 800b8f4:	f003 0304 	and.w	r3, r3, #4
 800b8f8:	2b00      	cmp	r3, #0
 800b8fa:	d101      	bne.n	800b900 <HAL_RCC_ClockConfig+0x1a0>
      {
        return HAL_ERROR;
 800b8fc:	2301      	movs	r3, #1
 800b8fe:	e0d6      	b.n	800baae <HAL_RCC_ClockConfig+0x34e>
      }
    }
    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 800b900:	4b28      	ldr	r3, [pc, #160]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b902:	691b      	ldr	r3, [r3, #16]
 800b904:	f023 0207 	bic.w	r2, r3, #7
 800b908:	687b      	ldr	r3, [r7, #4]
 800b90a:	685b      	ldr	r3, [r3, #4]
 800b90c:	4925      	ldr	r1, [pc, #148]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b90e:	4313      	orrs	r3, r2
 800b910:	610b      	str	r3, [r1, #16]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 800b912:	f7f9 fd93 	bl	800543c <HAL_GetTick>
 800b916:	6178      	str	r0, [r7, #20]

    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 800b918:	e00a      	b.n	800b930 <HAL_RCC_ClockConfig+0x1d0>
    {
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 800b91a:	f7f9 fd8f 	bl	800543c <HAL_GetTick>
 800b91e:	4602      	mov	r2, r0
 800b920:	697b      	ldr	r3, [r7, #20]
 800b922:	1ad3      	subs	r3, r2, r3
 800b924:	f241 3288 	movw	r2, #5000	@ 0x1388
 800b928:	4293      	cmp	r3, r2
 800b92a:	d901      	bls.n	800b930 <HAL_RCC_ClockConfig+0x1d0>
      {
        return HAL_TIMEOUT;
 800b92c:	2303      	movs	r3, #3
 800b92e:	e0be      	b.n	800baae <HAL_RCC_ClockConfig+0x34e>
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 800b930:	4b1c      	ldr	r3, [pc, #112]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b932:	691b      	ldr	r3, [r3, #16]
 800b934:	f003 0238 	and.w	r2, r3, #56	@ 0x38
 800b938:	687b      	ldr	r3, [r7, #4]
 800b93a:	685b      	ldr	r3, [r3, #4]
 800b93c:	00db      	lsls	r3, r3, #3
 800b93e:	429a      	cmp	r2, r3
 800b940:	d1eb      	bne.n	800b91a <HAL_RCC_ClockConfig+0x1ba>

  }

  /* Decreasing the BUS frequency divider */
  /*-------------------------- HCLK Configuration --------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 800b942:	687b      	ldr	r3, [r7, #4]
 800b944:	681b      	ldr	r3, [r3, #0]
 800b946:	f003 0302 	and.w	r3, r3, #2
 800b94a:	2b00      	cmp	r3, #0
 800b94c:	d010      	beq.n	800b970 <HAL_RCC_ClockConfig+0x210>
  {
#if defined(RCC_D1CFGR_HPRE)
    if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
 800b94e:	687b      	ldr	r3, [r7, #4]
 800b950:	68da      	ldr	r2, [r3, #12]
 800b952:	4b14      	ldr	r3, [pc, #80]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b954:	699b      	ldr	r3, [r3, #24]
 800b956:	f003 030f 	and.w	r3, r3, #15
 800b95a:	429a      	cmp	r2, r3
 800b95c:	d208      	bcs.n	800b970 <HAL_RCC_ClockConfig+0x210>
    {
      /* Set the new HCLK clock divider */
      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 800b95e:	4b11      	ldr	r3, [pc, #68]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b960:	699b      	ldr	r3, [r3, #24]
 800b962:	f023 020f 	bic.w	r2, r3, #15
 800b966:	687b      	ldr	r3, [r7, #4]
 800b968:	68db      	ldr	r3, [r3, #12]
 800b96a:	490e      	ldr	r1, [pc, #56]	@ (800b9a4 <HAL_RCC_ClockConfig+0x244>)
 800b96c:	4313      	orrs	r3, r2
 800b96e:	618b      	str	r3, [r1, #24]
    }
#endif
  }

  /* Decreasing the number of wait states because of lower CPU frequency */
  if (FLatency < __HAL_FLASH_GET_LATENCY())
 800b970:	4b0b      	ldr	r3, [pc, #44]	@ (800b9a0 <HAL_RCC_ClockConfig+0x240>)
 800b972:	681b      	ldr	r3, [r3, #0]
 800b974:	f003 030f 	and.w	r3, r3, #15
 800b978:	683a      	ldr	r2, [r7, #0]
 800b97a:	429a      	cmp	r2, r3
 800b97c:	d214      	bcs.n	800b9a8 <HAL_RCC_ClockConfig+0x248>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 800b97e:	4b08      	ldr	r3, [pc, #32]	@ (800b9a0 <HAL_RCC_ClockConfig+0x240>)
 800b980:	681b      	ldr	r3, [r3, #0]
 800b982:	f023 020f 	bic.w	r2, r3, #15
 800b986:	4906      	ldr	r1, [pc, #24]	@ (800b9a0 <HAL_RCC_ClockConfig+0x240>)
 800b988:	683b      	ldr	r3, [r7, #0]
 800b98a:	4313      	orrs	r3, r2
 800b98c:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 800b98e:	4b04      	ldr	r3, [pc, #16]	@ (800b9a0 <HAL_RCC_ClockConfig+0x240>)
 800b990:	681b      	ldr	r3, [r3, #0]
 800b992:	f003 030f 	and.w	r3, r3, #15
 800b996:	683a      	ldr	r2, [r7, #0]
 800b998:	429a      	cmp	r2, r3
 800b99a:	d005      	beq.n	800b9a8 <HAL_RCC_ClockConfig+0x248>
    {
      return HAL_ERROR;
 800b99c:	2301      	movs	r3, #1
 800b99e:	e086      	b.n	800baae <HAL_RCC_ClockConfig+0x34e>
 800b9a0:	52002000 	.word	0x52002000
 800b9a4:	58024400 	.word	0x58024400
    }
  }

  /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
 800b9a8:	687b      	ldr	r3, [r7, #4]
 800b9aa:	681b      	ldr	r3, [r3, #0]
 800b9ac:	f003 0304 	and.w	r3, r3, #4
 800b9b0:	2b00      	cmp	r3, #0
 800b9b2:	d010      	beq.n	800b9d6 <HAL_RCC_ClockConfig+0x276>
  {
#if defined(RCC_D1CFGR_D1PPRE)
    if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
 800b9b4:	687b      	ldr	r3, [r7, #4]
 800b9b6:	691a      	ldr	r2, [r3, #16]
 800b9b8:	4b3f      	ldr	r3, [pc, #252]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800b9ba:	699b      	ldr	r3, [r3, #24]
 800b9bc:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 800b9c0:	429a      	cmp	r2, r3
 800b9c2:	d208      	bcs.n	800b9d6 <HAL_RCC_ClockConfig+0x276>
    {
      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
 800b9c4:	4b3c      	ldr	r3, [pc, #240]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800b9c6:	699b      	ldr	r3, [r3, #24]
 800b9c8:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
 800b9cc:	687b      	ldr	r3, [r7, #4]
 800b9ce:	691b      	ldr	r3, [r3, #16]
 800b9d0:	4939      	ldr	r1, [pc, #228]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800b9d2:	4313      	orrs	r3, r2
 800b9d4:	618b      	str	r3, [r1, #24]
    }
#endif
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 800b9d6:	687b      	ldr	r3, [r7, #4]
 800b9d8:	681b      	ldr	r3, [r3, #0]
 800b9da:	f003 0308 	and.w	r3, r3, #8
 800b9de:	2b00      	cmp	r3, #0
 800b9e0:	d010      	beq.n	800ba04 <HAL_RCC_ClockConfig+0x2a4>
  {
#if defined(RCC_D2CFGR_D2PPRE1)
    if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
 800b9e2:	687b      	ldr	r3, [r7, #4]
 800b9e4:	695a      	ldr	r2, [r3, #20]
 800b9e6:	4b34      	ldr	r3, [pc, #208]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800b9e8:	69db      	ldr	r3, [r3, #28]
 800b9ea:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 800b9ee:	429a      	cmp	r2, r3
 800b9f0:	d208      	bcs.n	800ba04 <HAL_RCC_ClockConfig+0x2a4>
    {
      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
 800b9f2:	4b31      	ldr	r3, [pc, #196]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800b9f4:	69db      	ldr	r3, [r3, #28]
 800b9f6:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
 800b9fa:	687b      	ldr	r3, [r7, #4]
 800b9fc:	695b      	ldr	r3, [r3, #20]
 800b9fe:	492e      	ldr	r1, [pc, #184]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800ba00:	4313      	orrs	r3, r2
 800ba02:	61cb      	str	r3, [r1, #28]
    }
#endif
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 800ba04:	687b      	ldr	r3, [r7, #4]
 800ba06:	681b      	ldr	r3, [r3, #0]
 800ba08:	f003 0310 	and.w	r3, r3, #16
 800ba0c:	2b00      	cmp	r3, #0
 800ba0e:	d010      	beq.n	800ba32 <HAL_RCC_ClockConfig+0x2d2>
  {
#if defined (RCC_D2CFGR_D2PPRE2)
    if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
 800ba10:	687b      	ldr	r3, [r7, #4]
 800ba12:	699a      	ldr	r2, [r3, #24]
 800ba14:	4b28      	ldr	r3, [pc, #160]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800ba16:	69db      	ldr	r3, [r3, #28]
 800ba18:	f403 63e0 	and.w	r3, r3, #1792	@ 0x700
 800ba1c:	429a      	cmp	r2, r3
 800ba1e:	d208      	bcs.n	800ba32 <HAL_RCC_ClockConfig+0x2d2>
    {
      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
 800ba20:	4b25      	ldr	r3, [pc, #148]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800ba22:	69db      	ldr	r3, [r3, #28]
 800ba24:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
 800ba28:	687b      	ldr	r3, [r7, #4]
 800ba2a:	699b      	ldr	r3, [r3, #24]
 800ba2c:	4922      	ldr	r1, [pc, #136]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800ba2e:	4313      	orrs	r3, r2
 800ba30:	61cb      	str	r3, [r1, #28]
    }
#endif
  }

  /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
 800ba32:	687b      	ldr	r3, [r7, #4]
 800ba34:	681b      	ldr	r3, [r3, #0]
 800ba36:	f003 0320 	and.w	r3, r3, #32
 800ba3a:	2b00      	cmp	r3, #0
 800ba3c:	d010      	beq.n	800ba60 <HAL_RCC_ClockConfig+0x300>
  {
#if defined(RCC_D3CFGR_D3PPRE)
    if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
 800ba3e:	687b      	ldr	r3, [r7, #4]
 800ba40:	69da      	ldr	r2, [r3, #28]
 800ba42:	4b1d      	ldr	r3, [pc, #116]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800ba44:	6a1b      	ldr	r3, [r3, #32]
 800ba46:	f003 0370 	and.w	r3, r3, #112	@ 0x70
 800ba4a:	429a      	cmp	r2, r3
 800ba4c:	d208      	bcs.n	800ba60 <HAL_RCC_ClockConfig+0x300>
    {
      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
 800ba4e:	4b1a      	ldr	r3, [pc, #104]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800ba50:	6a1b      	ldr	r3, [r3, #32]
 800ba52:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
 800ba56:	687b      	ldr	r3, [r7, #4]
 800ba58:	69db      	ldr	r3, [r3, #28]
 800ba5a:	4917      	ldr	r1, [pc, #92]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800ba5c:	4313      	orrs	r3, r2
 800ba5e:	620b      	str	r3, [r1, #32]
#endif
  }

  /* Update the SystemCoreClock global variable */
#if defined(RCC_D1CFGR_D1CPRE)
  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
 800ba60:	f000 f834 	bl	800bacc <HAL_RCC_GetSysClockFreq>
 800ba64:	4602      	mov	r2, r0
 800ba66:	4b14      	ldr	r3, [pc, #80]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800ba68:	699b      	ldr	r3, [r3, #24]
 800ba6a:	0a1b      	lsrs	r3, r3, #8
 800ba6c:	f003 030f 	and.w	r3, r3, #15
 800ba70:	4912      	ldr	r1, [pc, #72]	@ (800babc <HAL_RCC_ClockConfig+0x35c>)
 800ba72:	5ccb      	ldrb	r3, [r1, r3]
 800ba74:	f003 031f 	and.w	r3, r3, #31
 800ba78:	fa22 f303 	lsr.w	r3, r2, r3
 800ba7c:	613b      	str	r3, [r7, #16]
#else
  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif

#if defined(RCC_D1CFGR_HPRE)
  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 800ba7e:	4b0e      	ldr	r3, [pc, #56]	@ (800bab8 <HAL_RCC_ClockConfig+0x358>)
 800ba80:	699b      	ldr	r3, [r3, #24]
 800ba82:	f003 030f 	and.w	r3, r3, #15
 800ba86:	4a0d      	ldr	r2, [pc, #52]	@ (800babc <HAL_RCC_ClockConfig+0x35c>)
 800ba88:	5cd3      	ldrb	r3, [r2, r3]
 800ba8a:	f003 031f 	and.w	r3, r3, #31
 800ba8e:	693a      	ldr	r2, [r7, #16]
 800ba90:	fa22 f303 	lsr.w	r3, r2, r3
 800ba94:	4a0a      	ldr	r2, [pc, #40]	@ (800bac0 <HAL_RCC_ClockConfig+0x360>)
 800ba96:	6013      	str	r3, [r2, #0]
#endif

#if defined(DUAL_CORE) && defined(CORE_CM4)
  SystemCoreClock = SystemD2Clock;
#else
  SystemCoreClock = common_system_clock;
 800ba98:	4a0a      	ldr	r2, [pc, #40]	@ (800bac4 <HAL_RCC_ClockConfig+0x364>)
 800ba9a:	693b      	ldr	r3, [r7, #16]
 800ba9c:	6013      	str	r3, [r2, #0]
#endif /* DUAL_CORE && CORE_CM4 */

  /* Configure the source of time base considering new system clocks settings*/
  halstatus = HAL_InitTick(uwTickPrio);
 800ba9e:	4b0a      	ldr	r3, [pc, #40]	@ (800bac8 <HAL_RCC_ClockConfig+0x368>)
 800baa0:	681b      	ldr	r3, [r3, #0]
 800baa2:	4618      	mov	r0, r3
 800baa4:	f7f8 f986 	bl	8003db4 <HAL_InitTick>
 800baa8:	4603      	mov	r3, r0
 800baaa:	73fb      	strb	r3, [r7, #15]

  return halstatus;
 800baac:	7bfb      	ldrb	r3, [r7, #15]
}
 800baae:	4618      	mov	r0, r3
 800bab0:	3718      	adds	r7, #24
 800bab2:	46bd      	mov	sp, r7
 800bab4:	bd80      	pop	{r7, pc}
 800bab6:	bf00      	nop
 800bab8:	58024400 	.word	0x58024400
 800babc:	08018a28 	.word	0x08018a28
 800bac0:	24000038 	.word	0x24000038
 800bac4:	24000034 	.word	0x24000034
 800bac8:	2400003c 	.word	0x2400003c

0800bacc <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 800bacc:	b480      	push	{r7}
 800bace:	b089      	sub	sp, #36	@ 0x24
 800bad0:	af00      	add	r7, sp, #0
  float_t fracn1, pllvco;
  uint32_t sysclockfreq;

  /* Get SYSCLK source -------------------------------------------------------*/

  switch (RCC->CFGR & RCC_CFGR_SWS)
 800bad2:	4bb3      	ldr	r3, [pc, #716]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bad4:	691b      	ldr	r3, [r3, #16]
 800bad6:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 800bada:	2b18      	cmp	r3, #24
 800badc:	f200 8155 	bhi.w	800bd8a <HAL_RCC_GetSysClockFreq+0x2be>
 800bae0:	a201      	add	r2, pc, #4	@ (adr r2, 800bae8 <HAL_RCC_GetSysClockFreq+0x1c>)
 800bae2:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800bae6:	bf00      	nop
 800bae8:	0800bb4d 	.word	0x0800bb4d
 800baec:	0800bd8b 	.word	0x0800bd8b
 800baf0:	0800bd8b 	.word	0x0800bd8b
 800baf4:	0800bd8b 	.word	0x0800bd8b
 800baf8:	0800bd8b 	.word	0x0800bd8b
 800bafc:	0800bd8b 	.word	0x0800bd8b
 800bb00:	0800bd8b 	.word	0x0800bd8b
 800bb04:	0800bd8b 	.word	0x0800bd8b
 800bb08:	0800bb73 	.word	0x0800bb73
 800bb0c:	0800bd8b 	.word	0x0800bd8b
 800bb10:	0800bd8b 	.word	0x0800bd8b
 800bb14:	0800bd8b 	.word	0x0800bd8b
 800bb18:	0800bd8b 	.word	0x0800bd8b
 800bb1c:	0800bd8b 	.word	0x0800bd8b
 800bb20:	0800bd8b 	.word	0x0800bd8b
 800bb24:	0800bd8b 	.word	0x0800bd8b
 800bb28:	0800bb79 	.word	0x0800bb79
 800bb2c:	0800bd8b 	.word	0x0800bd8b
 800bb30:	0800bd8b 	.word	0x0800bd8b
 800bb34:	0800bd8b 	.word	0x0800bd8b
 800bb38:	0800bd8b 	.word	0x0800bd8b
 800bb3c:	0800bd8b 	.word	0x0800bd8b
 800bb40:	0800bd8b 	.word	0x0800bd8b
 800bb44:	0800bd8b 	.word	0x0800bd8b
 800bb48:	0800bb7f 	.word	0x0800bb7f
  {
    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */

      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 800bb4c:	4b94      	ldr	r3, [pc, #592]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bb4e:	681b      	ldr	r3, [r3, #0]
 800bb50:	f003 0320 	and.w	r3, r3, #32
 800bb54:	2b00      	cmp	r3, #0
 800bb56:	d009      	beq.n	800bb6c <HAL_RCC_GetSysClockFreq+0xa0>
      {
        sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800bb58:	4b91      	ldr	r3, [pc, #580]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bb5a:	681b      	ldr	r3, [r3, #0]
 800bb5c:	08db      	lsrs	r3, r3, #3
 800bb5e:	f003 0303 	and.w	r3, r3, #3
 800bb62:	4a90      	ldr	r2, [pc, #576]	@ (800bda4 <HAL_RCC_GetSysClockFreq+0x2d8>)
 800bb64:	fa22 f303 	lsr.w	r3, r2, r3
 800bb68:	61bb      	str	r3, [r7, #24]
      else
      {
        sysclockfreq = (uint32_t) HSI_VALUE;
      }

      break;
 800bb6a:	e111      	b.n	800bd90 <HAL_RCC_GetSysClockFreq+0x2c4>
        sysclockfreq = (uint32_t) HSI_VALUE;
 800bb6c:	4b8d      	ldr	r3, [pc, #564]	@ (800bda4 <HAL_RCC_GetSysClockFreq+0x2d8>)
 800bb6e:	61bb      	str	r3, [r7, #24]
      break;
 800bb70:	e10e      	b.n	800bd90 <HAL_RCC_GetSysClockFreq+0x2c4>

    case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
      sysclockfreq = CSI_VALUE;
 800bb72:	4b8d      	ldr	r3, [pc, #564]	@ (800bda8 <HAL_RCC_GetSysClockFreq+0x2dc>)
 800bb74:	61bb      	str	r3, [r7, #24]
      break;
 800bb76:	e10b      	b.n	800bd90 <HAL_RCC_GetSysClockFreq+0x2c4>

    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
      sysclockfreq = HSE_VALUE;
 800bb78:	4b8c      	ldr	r3, [pc, #560]	@ (800bdac <HAL_RCC_GetSysClockFreq+0x2e0>)
 800bb7a:	61bb      	str	r3, [r7, #24]
      break;
 800bb7c:	e108      	b.n	800bd90 <HAL_RCC_GetSysClockFreq+0x2c4>
    case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */

      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
      SYSCLK = PLL_VCO / PLLR
      */
      pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
 800bb7e:	4b88      	ldr	r3, [pc, #544]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bb80:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800bb82:	f003 0303 	and.w	r3, r3, #3
 800bb86:	617b      	str	r3, [r7, #20]
      pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4)  ;
 800bb88:	4b85      	ldr	r3, [pc, #532]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bb8a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800bb8c:	091b      	lsrs	r3, r3, #4
 800bb8e:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
 800bb92:	613b      	str	r3, [r7, #16]
      pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
 800bb94:	4b82      	ldr	r3, [pc, #520]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bb96:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800bb98:	f003 0301 	and.w	r3, r3, #1
 800bb9c:	60fb      	str	r3, [r7, #12]
      fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
 800bb9e:	4b80      	ldr	r3, [pc, #512]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bba0:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 800bba2:	08db      	lsrs	r3, r3, #3
 800bba4:	f3c3 030c 	ubfx	r3, r3, #0, #13
 800bba8:	68fa      	ldr	r2, [r7, #12]
 800bbaa:	fb02 f303 	mul.w	r3, r2, r3
 800bbae:	ee07 3a90 	vmov	s15, r3
 800bbb2:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800bbb6:	edc7 7a02 	vstr	s15, [r7, #8]

      if (pllm != 0U)
 800bbba:	693b      	ldr	r3, [r7, #16]
 800bbbc:	2b00      	cmp	r3, #0
 800bbbe:	f000 80e1 	beq.w	800bd84 <HAL_RCC_GetSysClockFreq+0x2b8>
 800bbc2:	697b      	ldr	r3, [r7, #20]
 800bbc4:	2b02      	cmp	r3, #2
 800bbc6:	f000 8083 	beq.w	800bcd0 <HAL_RCC_GetSysClockFreq+0x204>
 800bbca:	697b      	ldr	r3, [r7, #20]
 800bbcc:	2b02      	cmp	r3, #2
 800bbce:	f200 80a1 	bhi.w	800bd14 <HAL_RCC_GetSysClockFreq+0x248>
 800bbd2:	697b      	ldr	r3, [r7, #20]
 800bbd4:	2b00      	cmp	r3, #0
 800bbd6:	d003      	beq.n	800bbe0 <HAL_RCC_GetSysClockFreq+0x114>
 800bbd8:	697b      	ldr	r3, [r7, #20]
 800bbda:	2b01      	cmp	r3, #1
 800bbdc:	d056      	beq.n	800bc8c <HAL_RCC_GetSysClockFreq+0x1c0>
 800bbde:	e099      	b.n	800bd14 <HAL_RCC_GetSysClockFreq+0x248>
      {
        switch (pllsource)
        {
          case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */

            if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 800bbe0:	4b6f      	ldr	r3, [pc, #444]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bbe2:	681b      	ldr	r3, [r3, #0]
 800bbe4:	f003 0320 	and.w	r3, r3, #32
 800bbe8:	2b00      	cmp	r3, #0
 800bbea:	d02d      	beq.n	800bc48 <HAL_RCC_GetSysClockFreq+0x17c>
            {
              hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800bbec:	4b6c      	ldr	r3, [pc, #432]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bbee:	681b      	ldr	r3, [r3, #0]
 800bbf0:	08db      	lsrs	r3, r3, #3
 800bbf2:	f003 0303 	and.w	r3, r3, #3
 800bbf6:	4a6b      	ldr	r2, [pc, #428]	@ (800bda4 <HAL_RCC_GetSysClockFreq+0x2d8>)
 800bbf8:	fa22 f303 	lsr.w	r3, r2, r3
 800bbfc:	607b      	str	r3, [r7, #4]
              pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800bbfe:	687b      	ldr	r3, [r7, #4]
 800bc00:	ee07 3a90 	vmov	s15, r3
 800bc04:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800bc08:	693b      	ldr	r3, [r7, #16]
 800bc0a:	ee07 3a90 	vmov	s15, r3
 800bc0e:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800bc12:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800bc16:	4b62      	ldr	r3, [pc, #392]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bc18:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800bc1a:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800bc1e:	ee07 3a90 	vmov	s15, r3
 800bc22:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800bc26:	ed97 6a02 	vldr	s12, [r7, #8]
 800bc2a:	eddf 5a61 	vldr	s11, [pc, #388]	@ 800bdb0 <HAL_RCC_GetSysClockFreq+0x2e4>
 800bc2e:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800bc32:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800bc36:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800bc3a:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800bc3e:	ee67 7a27 	vmul.f32	s15, s14, s15
 800bc42:	edc7 7a07 	vstr	s15, [r7, #28]
            }
            else
            {
              pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
            }
            break;
 800bc46:	e087      	b.n	800bd58 <HAL_RCC_GetSysClockFreq+0x28c>
              pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800bc48:	693b      	ldr	r3, [r7, #16]
 800bc4a:	ee07 3a90 	vmov	s15, r3
 800bc4e:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800bc52:	eddf 6a58 	vldr	s13, [pc, #352]	@ 800bdb4 <HAL_RCC_GetSysClockFreq+0x2e8>
 800bc56:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800bc5a:	4b51      	ldr	r3, [pc, #324]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bc5c:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800bc5e:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800bc62:	ee07 3a90 	vmov	s15, r3
 800bc66:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800bc6a:	ed97 6a02 	vldr	s12, [r7, #8]
 800bc6e:	eddf 5a50 	vldr	s11, [pc, #320]	@ 800bdb0 <HAL_RCC_GetSysClockFreq+0x2e4>
 800bc72:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800bc76:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800bc7a:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800bc7e:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800bc82:	ee67 7a27 	vmul.f32	s15, s14, s15
 800bc86:	edc7 7a07 	vstr	s15, [r7, #28]
            break;
 800bc8a:	e065      	b.n	800bd58 <HAL_RCC_GetSysClockFreq+0x28c>

          case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
            pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800bc8c:	693b      	ldr	r3, [r7, #16]
 800bc8e:	ee07 3a90 	vmov	s15, r3
 800bc92:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800bc96:	eddf 6a48 	vldr	s13, [pc, #288]	@ 800bdb8 <HAL_RCC_GetSysClockFreq+0x2ec>
 800bc9a:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800bc9e:	4b40      	ldr	r3, [pc, #256]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bca0:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800bca2:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800bca6:	ee07 3a90 	vmov	s15, r3
 800bcaa:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800bcae:	ed97 6a02 	vldr	s12, [r7, #8]
 800bcb2:	eddf 5a3f 	vldr	s11, [pc, #252]	@ 800bdb0 <HAL_RCC_GetSysClockFreq+0x2e4>
 800bcb6:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800bcba:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800bcbe:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800bcc2:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800bcc6:	ee67 7a27 	vmul.f32	s15, s14, s15
 800bcca:	edc7 7a07 	vstr	s15, [r7, #28]
            break;
 800bcce:	e043      	b.n	800bd58 <HAL_RCC_GetSysClockFreq+0x28c>

          case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
            pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800bcd0:	693b      	ldr	r3, [r7, #16]
 800bcd2:	ee07 3a90 	vmov	s15, r3
 800bcd6:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800bcda:	eddf 6a38 	vldr	s13, [pc, #224]	@ 800bdbc <HAL_RCC_GetSysClockFreq+0x2f0>
 800bcde:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800bce2:	4b2f      	ldr	r3, [pc, #188]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bce4:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800bce6:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800bcea:	ee07 3a90 	vmov	s15, r3
 800bcee:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800bcf2:	ed97 6a02 	vldr	s12, [r7, #8]
 800bcf6:	eddf 5a2e 	vldr	s11, [pc, #184]	@ 800bdb0 <HAL_RCC_GetSysClockFreq+0x2e4>
 800bcfa:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800bcfe:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800bd02:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800bd06:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800bd0a:	ee67 7a27 	vmul.f32	s15, s14, s15
 800bd0e:	edc7 7a07 	vstr	s15, [r7, #28]
            break;
 800bd12:	e021      	b.n	800bd58 <HAL_RCC_GetSysClockFreq+0x28c>

          default:
            pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800bd14:	693b      	ldr	r3, [r7, #16]
 800bd16:	ee07 3a90 	vmov	s15, r3
 800bd1a:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800bd1e:	eddf 6a26 	vldr	s13, [pc, #152]	@ 800bdb8 <HAL_RCC_GetSysClockFreq+0x2ec>
 800bd22:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800bd26:	4b1e      	ldr	r3, [pc, #120]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bd28:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800bd2a:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800bd2e:	ee07 3a90 	vmov	s15, r3
 800bd32:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800bd36:	ed97 6a02 	vldr	s12, [r7, #8]
 800bd3a:	eddf 5a1d 	vldr	s11, [pc, #116]	@ 800bdb0 <HAL_RCC_GetSysClockFreq+0x2e4>
 800bd3e:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800bd42:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800bd46:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800bd4a:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800bd4e:	ee67 7a27 	vmul.f32	s15, s14, s15
 800bd52:	edc7 7a07 	vstr	s15, [r7, #28]
            break;
 800bd56:	bf00      	nop
        }
        pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
 800bd58:	4b11      	ldr	r3, [pc, #68]	@ (800bda0 <HAL_RCC_GetSysClockFreq+0x2d4>)
 800bd5a:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800bd5c:	0a5b      	lsrs	r3, r3, #9
 800bd5e:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800bd62:	3301      	adds	r3, #1
 800bd64:	603b      	str	r3, [r7, #0]
        sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
 800bd66:	683b      	ldr	r3, [r7, #0]
 800bd68:	ee07 3a90 	vmov	s15, r3
 800bd6c:	eeb8 7a67 	vcvt.f32.u32	s14, s15
 800bd70:	edd7 6a07 	vldr	s13, [r7, #28]
 800bd74:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800bd78:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800bd7c:	ee17 3a90 	vmov	r3, s15
 800bd80:	61bb      	str	r3, [r7, #24]
      }
      else
      {
        sysclockfreq = 0U;
      }
      break;
 800bd82:	e005      	b.n	800bd90 <HAL_RCC_GetSysClockFreq+0x2c4>
        sysclockfreq = 0U;
 800bd84:	2300      	movs	r3, #0
 800bd86:	61bb      	str	r3, [r7, #24]
      break;
 800bd88:	e002      	b.n	800bd90 <HAL_RCC_GetSysClockFreq+0x2c4>

    default:
      sysclockfreq = CSI_VALUE;
 800bd8a:	4b07      	ldr	r3, [pc, #28]	@ (800bda8 <HAL_RCC_GetSysClockFreq+0x2dc>)
 800bd8c:	61bb      	str	r3, [r7, #24]
      break;
 800bd8e:	bf00      	nop
  }

  return sysclockfreq;
 800bd90:	69bb      	ldr	r3, [r7, #24]
}
 800bd92:	4618      	mov	r0, r3
 800bd94:	3724      	adds	r7, #36	@ 0x24
 800bd96:	46bd      	mov	sp, r7
 800bd98:	f85d 7b04 	ldr.w	r7, [sp], #4
 800bd9c:	4770      	bx	lr
 800bd9e:	bf00      	nop
 800bda0:	58024400 	.word	0x58024400
 800bda4:	03d09000 	.word	0x03d09000
 800bda8:	003d0900 	.word	0x003d0900
 800bdac:	017d7840 	.word	0x017d7840
 800bdb0:	46000000 	.word	0x46000000
 800bdb4:	4c742400 	.word	0x4c742400
 800bdb8:	4a742400 	.word	0x4a742400
 800bdbc:	4bbebc20 	.word	0x4bbebc20

0800bdc0 <HAL_RCC_GetHCLKFreq>:
  * @note   The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
  *         and updated within this function
  * @retval HCLK frequency
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 800bdc0:	b580      	push	{r7, lr}
 800bdc2:	b082      	sub	sp, #8
 800bdc4:	af00      	add	r7, sp, #0
  uint32_t common_system_clock;

#if defined(RCC_D1CFGR_D1CPRE)
  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
 800bdc6:	f7ff fe81 	bl	800bacc <HAL_RCC_GetSysClockFreq>
 800bdca:	4602      	mov	r2, r0
 800bdcc:	4b10      	ldr	r3, [pc, #64]	@ (800be10 <HAL_RCC_GetHCLKFreq+0x50>)
 800bdce:	699b      	ldr	r3, [r3, #24]
 800bdd0:	0a1b      	lsrs	r3, r3, #8
 800bdd2:	f003 030f 	and.w	r3, r3, #15
 800bdd6:	490f      	ldr	r1, [pc, #60]	@ (800be14 <HAL_RCC_GetHCLKFreq+0x54>)
 800bdd8:	5ccb      	ldrb	r3, [r1, r3]
 800bdda:	f003 031f 	and.w	r3, r3, #31
 800bdde:	fa22 f303 	lsr.w	r3, r2, r3
 800bde2:	607b      	str	r3, [r7, #4]
#else
  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
#endif

#if defined(RCC_D1CFGR_HPRE)
  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 800bde4:	4b0a      	ldr	r3, [pc, #40]	@ (800be10 <HAL_RCC_GetHCLKFreq+0x50>)
 800bde6:	699b      	ldr	r3, [r3, #24]
 800bde8:	f003 030f 	and.w	r3, r3, #15
 800bdec:	4a09      	ldr	r2, [pc, #36]	@ (800be14 <HAL_RCC_GetHCLKFreq+0x54>)
 800bdee:	5cd3      	ldrb	r3, [r2, r3]
 800bdf0:	f003 031f 	and.w	r3, r3, #31
 800bdf4:	687a      	ldr	r2, [r7, #4]
 800bdf6:	fa22 f303 	lsr.w	r3, r2, r3
 800bdfa:	4a07      	ldr	r2, [pc, #28]	@ (800be18 <HAL_RCC_GetHCLKFreq+0x58>)
 800bdfc:	6013      	str	r3, [r2, #0]
#endif

#if defined(DUAL_CORE) && defined(CORE_CM4)
  SystemCoreClock = SystemD2Clock;
#else
  SystemCoreClock = common_system_clock;
 800bdfe:	4a07      	ldr	r2, [pc, #28]	@ (800be1c <HAL_RCC_GetHCLKFreq+0x5c>)
 800be00:	687b      	ldr	r3, [r7, #4]
 800be02:	6013      	str	r3, [r2, #0]
#endif /* DUAL_CORE && CORE_CM4 */

  return SystemD2Clock;
 800be04:	4b04      	ldr	r3, [pc, #16]	@ (800be18 <HAL_RCC_GetHCLKFreq+0x58>)
 800be06:	681b      	ldr	r3, [r3, #0]
}
 800be08:	4618      	mov	r0, r3
 800be0a:	3708      	adds	r7, #8
 800be0c:	46bd      	mov	sp, r7
 800be0e:	bd80      	pop	{r7, pc}
 800be10:	58024400 	.word	0x58024400
 800be14:	08018a28 	.word	0x08018a28
 800be18:	24000038 	.word	0x24000038
 800be1c:	24000034 	.word	0x24000034

0800be20 <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 800be20:	b580      	push	{r7, lr}
 800be22:	af00      	add	r7, sp, #0
#if defined (RCC_D2CFGR_D2PPRE1)
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
 800be24:	f7ff ffcc 	bl	800bdc0 <HAL_RCC_GetHCLKFreq>
 800be28:	4602      	mov	r2, r0
 800be2a:	4b06      	ldr	r3, [pc, #24]	@ (800be44 <HAL_RCC_GetPCLK1Freq+0x24>)
 800be2c:	69db      	ldr	r3, [r3, #28]
 800be2e:	091b      	lsrs	r3, r3, #4
 800be30:	f003 0307 	and.w	r3, r3, #7
 800be34:	4904      	ldr	r1, [pc, #16]	@ (800be48 <HAL_RCC_GetPCLK1Freq+0x28>)
 800be36:	5ccb      	ldrb	r3, [r1, r3]
 800be38:	f003 031f 	and.w	r3, r3, #31
 800be3c:	fa22 f303 	lsr.w	r3, r2, r3
#else
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
#endif
}
 800be40:	4618      	mov	r0, r3
 800be42:	bd80      	pop	{r7, pc}
 800be44:	58024400 	.word	0x58024400
 800be48:	08018a28 	.word	0x08018a28

0800be4c <HAL_RCC_GetPCLK2Freq>:
  * @note   Each time PCLK2 changes, this function must be called to update the
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
 800be4c:	b580      	push	{r7, lr}
 800be4e:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
#if defined(RCC_D2CFGR_D2PPRE2)
  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
 800be50:	f7ff ffb6 	bl	800bdc0 <HAL_RCC_GetHCLKFreq>
 800be54:	4602      	mov	r2, r0
 800be56:	4b06      	ldr	r3, [pc, #24]	@ (800be70 <HAL_RCC_GetPCLK2Freq+0x24>)
 800be58:	69db      	ldr	r3, [r3, #28]
 800be5a:	0a1b      	lsrs	r3, r3, #8
 800be5c:	f003 0307 	and.w	r3, r3, #7
 800be60:	4904      	ldr	r1, [pc, #16]	@ (800be74 <HAL_RCC_GetPCLK2Freq+0x28>)
 800be62:	5ccb      	ldrb	r3, [r1, r3]
 800be64:	f003 031f 	and.w	r3, r3, #31
 800be68:	fa22 f303 	lsr.w	r3, r2, r3
#else
  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
#endif
}
 800be6c:	4618      	mov	r0, r3
 800be6e:	bd80      	pop	{r7, pc}
 800be70:	58024400 	.word	0x58024400
 800be74:	08018a28 	.word	0x08018a28

0800be78 <HAL_RCC_GetClockConfig>:
  * will be configured.
  * @param  pFLatency: Pointer on the Flash Latency.
  * @retval None
  */
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
{
 800be78:	b480      	push	{r7}
 800be7a:	b083      	sub	sp, #12
 800be7c:	af00      	add	r7, sp, #0
 800be7e:	6078      	str	r0, [r7, #4]
 800be80:	6039      	str	r1, [r7, #0]
  /* Set all possible values for the Clock type parameter --------------------*/
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
 800be82:	687b      	ldr	r3, [r7, #4]
 800be84:	223f      	movs	r2, #63	@ 0x3f
 800be86:	601a      	str	r2, [r3, #0]
                                 RCC_CLOCKTYPE_PCLK2 |  RCC_CLOCKTYPE_D3PCLK1  ;

  /* Get the SYSCLK configuration --------------------------------------------*/
  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
 800be88:	4b1a      	ldr	r3, [pc, #104]	@ (800bef4 <HAL_RCC_GetClockConfig+0x7c>)
 800be8a:	691b      	ldr	r3, [r3, #16]
 800be8c:	f003 0207 	and.w	r2, r3, #7
 800be90:	687b      	ldr	r3, [r7, #4]
 800be92:	605a      	str	r2, [r3, #4]

#if defined(RCC_D1CFGR_D1CPRE)
  /* Get the SYSCLK configuration ----------------------------------------------*/
  RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
 800be94:	4b17      	ldr	r3, [pc, #92]	@ (800bef4 <HAL_RCC_GetClockConfig+0x7c>)
 800be96:	699b      	ldr	r3, [r3, #24]
 800be98:	f403 6270 	and.w	r2, r3, #3840	@ 0xf00
 800be9c:	687b      	ldr	r3, [r7, #4]
 800be9e:	609a      	str	r2, [r3, #8]

  /* Get the D1HCLK configuration ----------------------------------------------*/
  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
 800bea0:	4b14      	ldr	r3, [pc, #80]	@ (800bef4 <HAL_RCC_GetClockConfig+0x7c>)
 800bea2:	699b      	ldr	r3, [r3, #24]
 800bea4:	f003 020f 	and.w	r2, r3, #15
 800bea8:	687b      	ldr	r3, [r7, #4]
 800beaa:	60da      	str	r2, [r3, #12]

  /* Get the APB3 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
 800beac:	4b11      	ldr	r3, [pc, #68]	@ (800bef4 <HAL_RCC_GetClockConfig+0x7c>)
 800beae:	699b      	ldr	r3, [r3, #24]
 800beb0:	f003 0270 	and.w	r2, r3, #112	@ 0x70
 800beb4:	687b      	ldr	r3, [r7, #4]
 800beb6:	611a      	str	r2, [r3, #16]

  /* Get the APB1 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
 800beb8:	4b0e      	ldr	r3, [pc, #56]	@ (800bef4 <HAL_RCC_GetClockConfig+0x7c>)
 800beba:	69db      	ldr	r3, [r3, #28]
 800bebc:	f003 0270 	and.w	r2, r3, #112	@ 0x70
 800bec0:	687b      	ldr	r3, [r7, #4]
 800bec2:	615a      	str	r2, [r3, #20]

  /* Get the APB2 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
 800bec4:	4b0b      	ldr	r3, [pc, #44]	@ (800bef4 <HAL_RCC_GetClockConfig+0x7c>)
 800bec6:	69db      	ldr	r3, [r3, #28]
 800bec8:	f403 62e0 	and.w	r2, r3, #1792	@ 0x700
 800becc:	687b      	ldr	r3, [r7, #4]
 800bece:	619a      	str	r2, [r3, #24]

  /* Get the APB4 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
 800bed0:	4b08      	ldr	r3, [pc, #32]	@ (800bef4 <HAL_RCC_GetClockConfig+0x7c>)
 800bed2:	6a1b      	ldr	r3, [r3, #32]
 800bed4:	f003 0270 	and.w	r2, r3, #112	@ 0x70
 800bed8:	687b      	ldr	r3, [r7, #4]
 800beda:	61da      	str	r2, [r3, #28]
  /* Get the APB4 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE);
#endif

  /* Get the Flash Wait State (Latency) configuration ------------------------*/
  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
 800bedc:	4b06      	ldr	r3, [pc, #24]	@ (800bef8 <HAL_RCC_GetClockConfig+0x80>)
 800bede:	681b      	ldr	r3, [r3, #0]
 800bee0:	f003 020f 	and.w	r2, r3, #15
 800bee4:	683b      	ldr	r3, [r7, #0]
 800bee6:	601a      	str	r2, [r3, #0]
}
 800bee8:	bf00      	nop
 800beea:	370c      	adds	r7, #12
 800beec:	46bd      	mov	sp, r7
 800beee:	f85d 7b04 	ldr.w	r7, [sp], #4
 800bef2:	4770      	bx	lr
 800bef4:	58024400 	.word	0x58024400
 800bef8:	52002000 	.word	0x52002000

0800befc <HAL_RCCEx_PeriphCLKConfig>:
  * (*) : Available on some STM32H7 lines only.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
 800befc:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 800bf00:	b0c8      	sub	sp, #288	@ 0x120
 800bf02:	af00      	add	r7, sp, #0
 800bf04:	f8c7 010c 	str.w	r0, [r7, #268]	@ 0x10c
  uint32_t tmpreg;
  uint32_t tickstart;
  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
 800bf08:	2300      	movs	r3, #0
 800bf0a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
 800bf0e:	2300      	movs	r3, #0
 800bf10:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e

  /*---------------------------- SPDIFRX configuration -------------------------------*/

  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
 800bf14:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800bf18:	e9d3 2300 	ldrd	r2, r3, [r3]
 800bf1c:	f002 6400 	and.w	r4, r2, #134217728	@ 0x8000000
 800bf20:	2500      	movs	r5, #0
 800bf22:	ea54 0305 	orrs.w	r3, r4, r5
 800bf26:	d049      	beq.n	800bfbc <HAL_RCCEx_PeriphCLKConfig+0xc0>
  {

    switch (PeriphClkInit->SpdifrxClockSelection)
 800bf28:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800bf2c:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 800bf2e:	f5b3 1f40 	cmp.w	r3, #3145728	@ 0x300000
 800bf32:	d02f      	beq.n	800bf94 <HAL_RCCEx_PeriphCLKConfig+0x98>
 800bf34:	f5b3 1f40 	cmp.w	r3, #3145728	@ 0x300000
 800bf38:	d828      	bhi.n	800bf8c <HAL_RCCEx_PeriphCLKConfig+0x90>
 800bf3a:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 800bf3e:	d01a      	beq.n	800bf76 <HAL_RCCEx_PeriphCLKConfig+0x7a>
 800bf40:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 800bf44:	d822      	bhi.n	800bf8c <HAL_RCCEx_PeriphCLKConfig+0x90>
 800bf46:	2b00      	cmp	r3, #0
 800bf48:	d003      	beq.n	800bf52 <HAL_RCCEx_PeriphCLKConfig+0x56>
 800bf4a:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 800bf4e:	d007      	beq.n	800bf60 <HAL_RCCEx_PeriphCLKConfig+0x64>
 800bf50:	e01c      	b.n	800bf8c <HAL_RCCEx_PeriphCLKConfig+0x90>
    {
      case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
        /* Enable PLL1Q Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800bf52:	4bb8      	ldr	r3, [pc, #736]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800bf54:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800bf56:	4ab7      	ldr	r2, [pc, #732]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800bf58:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800bf5c:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SPDIFRX clock source configuration done later after clock selection check */
        break;
 800bf5e:	e01a      	b.n	800bf96 <HAL_RCCEx_PeriphCLKConfig+0x9a>

      case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 800bf60:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800bf64:	3308      	adds	r3, #8
 800bf66:	2102      	movs	r1, #2
 800bf68:	4618      	mov	r0, r3
 800bf6a:	f002 fb45 	bl	800e5f8 <RCCEx_PLL2_Config>
 800bf6e:	4603      	mov	r3, r0
 800bf70:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SPDIFRX clock source configuration done later after clock selection check */
        break;
 800bf74:	e00f      	b.n	800bf96 <HAL_RCCEx_PeriphCLKConfig+0x9a>

      case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 800bf76:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800bf7a:	3328      	adds	r3, #40	@ 0x28
 800bf7c:	2102      	movs	r1, #2
 800bf7e:	4618      	mov	r0, r3
 800bf80:	f002 fbec 	bl	800e75c <RCCEx_PLL3_Config>
 800bf84:	4603      	mov	r3, r0
 800bf86:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SPDIFRX clock source configuration done later after clock selection check */
        break;
 800bf8a:	e004      	b.n	800bf96 <HAL_RCCEx_PeriphCLKConfig+0x9a>
        /* Internal OSC clock is used as source of SPDIFRX clock*/
        /* SPDIFRX clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800bf8c:	2301      	movs	r3, #1
 800bf8e:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800bf92:	e000      	b.n	800bf96 <HAL_RCCEx_PeriphCLKConfig+0x9a>
        break;
 800bf94:	bf00      	nop
    }

    if (ret == HAL_OK)
 800bf96:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800bf9a:	2b00      	cmp	r3, #0
 800bf9c:	d10a      	bne.n	800bfb4 <HAL_RCCEx_PeriphCLKConfig+0xb8>
    {
      /* Set the source of SPDIFRX clock*/
      __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
 800bf9e:	4ba5      	ldr	r3, [pc, #660]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800bfa0:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800bfa2:	f423 1140 	bic.w	r1, r3, #3145728	@ 0x300000
 800bfa6:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800bfaa:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
 800bfac:	4aa1      	ldr	r2, [pc, #644]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800bfae:	430b      	orrs	r3, r1
 800bfb0:	6513      	str	r3, [r2, #80]	@ 0x50
 800bfb2:	e003      	b.n	800bfbc <HAL_RCCEx_PeriphCLKConfig+0xc0>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800bfb4:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800bfb8:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- SAI1 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
 800bfbc:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800bfc0:	e9d3 2300 	ldrd	r2, r3, [r3]
 800bfc4:	f402 7880 	and.w	r8, r2, #256	@ 0x100
 800bfc8:	f04f 0900 	mov.w	r9, #0
 800bfcc:	ea58 0309 	orrs.w	r3, r8, r9
 800bfd0:	d047      	beq.n	800c062 <HAL_RCCEx_PeriphCLKConfig+0x166>
  {
    switch (PeriphClkInit->Sai1ClockSelection)
 800bfd2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800bfd6:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800bfd8:	2b04      	cmp	r3, #4
 800bfda:	d82a      	bhi.n	800c032 <HAL_RCCEx_PeriphCLKConfig+0x136>
 800bfdc:	a201      	add	r2, pc, #4	@ (adr r2, 800bfe4 <HAL_RCCEx_PeriphCLKConfig+0xe8>)
 800bfde:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800bfe2:	bf00      	nop
 800bfe4:	0800bff9 	.word	0x0800bff9
 800bfe8:	0800c007 	.word	0x0800c007
 800bfec:	0800c01d 	.word	0x0800c01d
 800bff0:	0800c03b 	.word	0x0800c03b
 800bff4:	0800c03b 	.word	0x0800c03b
    {
      case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
        /* Enable SAI Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800bff8:	4b8e      	ldr	r3, [pc, #568]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800bffa:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800bffc:	4a8d      	ldr	r2, [pc, #564]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800bffe:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800c002:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 800c004:	e01a      	b.n	800c03c <HAL_RCCEx_PeriphCLKConfig+0x140>

      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800c006:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c00a:	3308      	adds	r3, #8
 800c00c:	2100      	movs	r1, #0
 800c00e:	4618      	mov	r0, r3
 800c010:	f002 faf2 	bl	800e5f8 <RCCEx_PLL2_Config>
 800c014:	4603      	mov	r3, r0
 800c016:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 800c01a:	e00f      	b.n	800c03c <HAL_RCCEx_PeriphCLKConfig+0x140>

      case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 800c01c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c020:	3328      	adds	r3, #40	@ 0x28
 800c022:	2100      	movs	r1, #0
 800c024:	4618      	mov	r0, r3
 800c026:	f002 fb99 	bl	800e75c <RCCEx_PLL3_Config>
 800c02a:	4603      	mov	r3, r0
 800c02c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 800c030:	e004      	b.n	800c03c <HAL_RCCEx_PeriphCLKConfig+0x140>
        /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
        /* SAI1 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800c032:	2301      	movs	r3, #1
 800c034:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c038:	e000      	b.n	800c03c <HAL_RCCEx_PeriphCLKConfig+0x140>
        break;
 800c03a:	bf00      	nop
    }

    if (ret == HAL_OK)
 800c03c:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c040:	2b00      	cmp	r3, #0
 800c042:	d10a      	bne.n	800c05a <HAL_RCCEx_PeriphCLKConfig+0x15e>
    {
      /* Set the source of SAI1 clock*/
      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
 800c044:	4b7b      	ldr	r3, [pc, #492]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800c046:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800c048:	f023 0107 	bic.w	r1, r3, #7
 800c04c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c050:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800c052:	4a78      	ldr	r2, [pc, #480]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800c054:	430b      	orrs	r3, r1
 800c056:	6513      	str	r3, [r2, #80]	@ 0x50
 800c058:	e003      	b.n	800c062 <HAL_RCCEx_PeriphCLKConfig+0x166>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c05a:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c05e:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

#if defined(SAI3)
  /*---------------------------- SAI2/3 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
 800c062:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c066:	e9d3 2300 	ldrd	r2, r3, [r3]
 800c06a:	f402 7a00 	and.w	sl, r2, #512	@ 0x200
 800c06e:	f04f 0b00 	mov.w	fp, #0
 800c072:	ea5a 030b 	orrs.w	r3, sl, fp
 800c076:	d04c      	beq.n	800c112 <HAL_RCCEx_PeriphCLKConfig+0x216>
  {
    switch (PeriphClkInit->Sai23ClockSelection)
 800c078:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c07c:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800c07e:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800c082:	d030      	beq.n	800c0e6 <HAL_RCCEx_PeriphCLKConfig+0x1ea>
 800c084:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800c088:	d829      	bhi.n	800c0de <HAL_RCCEx_PeriphCLKConfig+0x1e2>
 800c08a:	2bc0      	cmp	r3, #192	@ 0xc0
 800c08c:	d02d      	beq.n	800c0ea <HAL_RCCEx_PeriphCLKConfig+0x1ee>
 800c08e:	2bc0      	cmp	r3, #192	@ 0xc0
 800c090:	d825      	bhi.n	800c0de <HAL_RCCEx_PeriphCLKConfig+0x1e2>
 800c092:	2b80      	cmp	r3, #128	@ 0x80
 800c094:	d018      	beq.n	800c0c8 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
 800c096:	2b80      	cmp	r3, #128	@ 0x80
 800c098:	d821      	bhi.n	800c0de <HAL_RCCEx_PeriphCLKConfig+0x1e2>
 800c09a:	2b00      	cmp	r3, #0
 800c09c:	d002      	beq.n	800c0a4 <HAL_RCCEx_PeriphCLKConfig+0x1a8>
 800c09e:	2b40      	cmp	r3, #64	@ 0x40
 800c0a0:	d007      	beq.n	800c0b2 <HAL_RCCEx_PeriphCLKConfig+0x1b6>
 800c0a2:	e01c      	b.n	800c0de <HAL_RCCEx_PeriphCLKConfig+0x1e2>
    {
      case RCC_SAI23CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2/3 */
        /* Enable SAI Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800c0a4:	4b63      	ldr	r3, [pc, #396]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800c0a6:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800c0a8:	4a62      	ldr	r2, [pc, #392]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800c0aa:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800c0ae:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SAI2/3 clock source configuration done later after clock selection check */
        break;
 800c0b0:	e01c      	b.n	800c0ec <HAL_RCCEx_PeriphCLKConfig+0x1f0>

      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800c0b2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c0b6:	3308      	adds	r3, #8
 800c0b8:	2100      	movs	r1, #0
 800c0ba:	4618      	mov	r0, r3
 800c0bc:	f002 fa9c 	bl	800e5f8 <RCCEx_PLL2_Config>
 800c0c0:	4603      	mov	r3, r0
 800c0c2:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI2/3 clock source configuration done later after clock selection check */
        break;
 800c0c6:	e011      	b.n	800c0ec <HAL_RCCEx_PeriphCLKConfig+0x1f0>

      case RCC_SAI23CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2/3 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 800c0c8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c0cc:	3328      	adds	r3, #40	@ 0x28
 800c0ce:	2100      	movs	r1, #0
 800c0d0:	4618      	mov	r0, r3
 800c0d2:	f002 fb43 	bl	800e75c <RCCEx_PLL3_Config>
 800c0d6:	4603      	mov	r3, r0
 800c0d8:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI2/3 clock source configuration done later after clock selection check */
        break;
 800c0dc:	e006      	b.n	800c0ec <HAL_RCCEx_PeriphCLKConfig+0x1f0>
        /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
        /* SAI2/3 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800c0de:	2301      	movs	r3, #1
 800c0e0:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c0e4:	e002      	b.n	800c0ec <HAL_RCCEx_PeriphCLKConfig+0x1f0>
        break;
 800c0e6:	bf00      	nop
 800c0e8:	e000      	b.n	800c0ec <HAL_RCCEx_PeriphCLKConfig+0x1f0>
        break;
 800c0ea:	bf00      	nop
    }

    if (ret == HAL_OK)
 800c0ec:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c0f0:	2b00      	cmp	r3, #0
 800c0f2:	d10a      	bne.n	800c10a <HAL_RCCEx_PeriphCLKConfig+0x20e>
    {
      /* Set the source of SAI2/3 clock*/
      __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
 800c0f4:	4b4f      	ldr	r3, [pc, #316]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800c0f6:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800c0f8:	f423 71e0 	bic.w	r1, r3, #448	@ 0x1c0
 800c0fc:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c100:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 800c102:	4a4c      	ldr	r2, [pc, #304]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800c104:	430b      	orrs	r3, r1
 800c106:	6513      	str	r3, [r2, #80]	@ 0x50
 800c108:	e003      	b.n	800c112 <HAL_RCCEx_PeriphCLKConfig+0x216>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c10a:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c10e:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
  }
#endif  /*SAI2B*/

#if defined(SAI4)
  /*---------------------------- SAI4A configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
 800c112:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c116:	e9d3 2300 	ldrd	r2, r3, [r3]
 800c11a:	f402 6380 	and.w	r3, r2, #1024	@ 0x400
 800c11e:	f8c7 3100 	str.w	r3, [r7, #256]	@ 0x100
 800c122:	2300      	movs	r3, #0
 800c124:	f8c7 3104 	str.w	r3, [r7, #260]	@ 0x104
 800c128:	e9d7 1240 	ldrd	r1, r2, [r7, #256]	@ 0x100
 800c12c:	460b      	mov	r3, r1
 800c12e:	4313      	orrs	r3, r2
 800c130:	d053      	beq.n	800c1da <HAL_RCCEx_PeriphCLKConfig+0x2de>
  {
    switch (PeriphClkInit->Sai4AClockSelection)
 800c132:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c136:	f8d3 30a8 	ldr.w	r3, [r3, #168]	@ 0xa8
 800c13a:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 800c13e:	d035      	beq.n	800c1ac <HAL_RCCEx_PeriphCLKConfig+0x2b0>
 800c140:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 800c144:	d82e      	bhi.n	800c1a4 <HAL_RCCEx_PeriphCLKConfig+0x2a8>
 800c146:	f5b3 0fc0 	cmp.w	r3, #6291456	@ 0x600000
 800c14a:	d031      	beq.n	800c1b0 <HAL_RCCEx_PeriphCLKConfig+0x2b4>
 800c14c:	f5b3 0fc0 	cmp.w	r3, #6291456	@ 0x600000
 800c150:	d828      	bhi.n	800c1a4 <HAL_RCCEx_PeriphCLKConfig+0x2a8>
 800c152:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
 800c156:	d01a      	beq.n	800c18e <HAL_RCCEx_PeriphCLKConfig+0x292>
 800c158:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
 800c15c:	d822      	bhi.n	800c1a4 <HAL_RCCEx_PeriphCLKConfig+0x2a8>
 800c15e:	2b00      	cmp	r3, #0
 800c160:	d003      	beq.n	800c16a <HAL_RCCEx_PeriphCLKConfig+0x26e>
 800c162:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 800c166:	d007      	beq.n	800c178 <HAL_RCCEx_PeriphCLKConfig+0x27c>
 800c168:	e01c      	b.n	800c1a4 <HAL_RCCEx_PeriphCLKConfig+0x2a8>
    {
      case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
        /* Enable SAI Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800c16a:	4b32      	ldr	r3, [pc, #200]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800c16c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800c16e:	4a31      	ldr	r2, [pc, #196]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800c170:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800c174:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 800c176:	e01c      	b.n	800c1b2 <HAL_RCCEx_PeriphCLKConfig+0x2b6>

      case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800c178:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c17c:	3308      	adds	r3, #8
 800c17e:	2100      	movs	r1, #0
 800c180:	4618      	mov	r0, r3
 800c182:	f002 fa39 	bl	800e5f8 <RCCEx_PLL2_Config>
 800c186:	4603      	mov	r3, r0
 800c188:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI2 clock source configuration done later after clock selection check */
        break;
 800c18c:	e011      	b.n	800c1b2 <HAL_RCCEx_PeriphCLKConfig+0x2b6>

      case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 800c18e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c192:	3328      	adds	r3, #40	@ 0x28
 800c194:	2100      	movs	r1, #0
 800c196:	4618      	mov	r0, r3
 800c198:	f002 fae0 	bl	800e75c <RCCEx_PLL3_Config>
 800c19c:	4603      	mov	r3, r0
 800c19e:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 800c1a2:	e006      	b.n	800c1b2 <HAL_RCCEx_PeriphCLKConfig+0x2b6>
        /* SAI4A clock source configuration done later after clock selection check */
        break;
#endif /* RCC_VER_3_0 */

      default:
        ret = HAL_ERROR;
 800c1a4:	2301      	movs	r3, #1
 800c1a6:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c1aa:	e002      	b.n	800c1b2 <HAL_RCCEx_PeriphCLKConfig+0x2b6>
        break;
 800c1ac:	bf00      	nop
 800c1ae:	e000      	b.n	800c1b2 <HAL_RCCEx_PeriphCLKConfig+0x2b6>
        break;
 800c1b0:	bf00      	nop
    }

    if (ret == HAL_OK)
 800c1b2:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c1b6:	2b00      	cmp	r3, #0
 800c1b8:	d10b      	bne.n	800c1d2 <HAL_RCCEx_PeriphCLKConfig+0x2d6>
    {
      /* Set the source of SAI4A clock*/
      __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
 800c1ba:	4b1e      	ldr	r3, [pc, #120]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800c1bc:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800c1be:	f423 0160 	bic.w	r1, r3, #14680064	@ 0xe00000
 800c1c2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c1c6:	f8d3 30a8 	ldr.w	r3, [r3, #168]	@ 0xa8
 800c1ca:	4a1a      	ldr	r2, [pc, #104]	@ (800c234 <HAL_RCCEx_PeriphCLKConfig+0x338>)
 800c1cc:	430b      	orrs	r3, r1
 800c1ce:	6593      	str	r3, [r2, #88]	@ 0x58
 800c1d0:	e003      	b.n	800c1da <HAL_RCCEx_PeriphCLKConfig+0x2de>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c1d2:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c1d6:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
  /*---------------------------- SAI4B configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
 800c1da:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c1de:	e9d3 2300 	ldrd	r2, r3, [r3]
 800c1e2:	f402 6300 	and.w	r3, r2, #2048	@ 0x800
 800c1e6:	f8c7 30f8 	str.w	r3, [r7, #248]	@ 0xf8
 800c1ea:	2300      	movs	r3, #0
 800c1ec:	f8c7 30fc 	str.w	r3, [r7, #252]	@ 0xfc
 800c1f0:	e9d7 123e 	ldrd	r1, r2, [r7, #248]	@ 0xf8
 800c1f4:	460b      	mov	r3, r1
 800c1f6:	4313      	orrs	r3, r2
 800c1f8:	d056      	beq.n	800c2a8 <HAL_RCCEx_PeriphCLKConfig+0x3ac>
  {
    switch (PeriphClkInit->Sai4BClockSelection)
 800c1fa:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c1fe:	f8d3 30ac 	ldr.w	r3, [r3, #172]	@ 0xac
 800c202:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 800c206:	d038      	beq.n	800c27a <HAL_RCCEx_PeriphCLKConfig+0x37e>
 800c208:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 800c20c:	d831      	bhi.n	800c272 <HAL_RCCEx_PeriphCLKConfig+0x376>
 800c20e:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
 800c212:	d034      	beq.n	800c27e <HAL_RCCEx_PeriphCLKConfig+0x382>
 800c214:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
 800c218:	d82b      	bhi.n	800c272 <HAL_RCCEx_PeriphCLKConfig+0x376>
 800c21a:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800c21e:	d01d      	beq.n	800c25c <HAL_RCCEx_PeriphCLKConfig+0x360>
 800c220:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800c224:	d825      	bhi.n	800c272 <HAL_RCCEx_PeriphCLKConfig+0x376>
 800c226:	2b00      	cmp	r3, #0
 800c228:	d006      	beq.n	800c238 <HAL_RCCEx_PeriphCLKConfig+0x33c>
 800c22a:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
 800c22e:	d00a      	beq.n	800c246 <HAL_RCCEx_PeriphCLKConfig+0x34a>
 800c230:	e01f      	b.n	800c272 <HAL_RCCEx_PeriphCLKConfig+0x376>
 800c232:	bf00      	nop
 800c234:	58024400 	.word	0x58024400
    {
      case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
        /* Enable SAI Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800c238:	4ba2      	ldr	r3, [pc, #648]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c23a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800c23c:	4aa1      	ldr	r2, [pc, #644]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c23e:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800c242:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 800c244:	e01c      	b.n	800c280 <HAL_RCCEx_PeriphCLKConfig+0x384>

      case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800c246:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c24a:	3308      	adds	r3, #8
 800c24c:	2100      	movs	r1, #0
 800c24e:	4618      	mov	r0, r3
 800c250:	f002 f9d2 	bl	800e5f8 <RCCEx_PLL2_Config>
 800c254:	4603      	mov	r3, r0
 800c256:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI2 clock source configuration done later after clock selection check */
        break;
 800c25a:	e011      	b.n	800c280 <HAL_RCCEx_PeriphCLKConfig+0x384>

      case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 800c25c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c260:	3328      	adds	r3, #40	@ 0x28
 800c262:	2100      	movs	r1, #0
 800c264:	4618      	mov	r0, r3
 800c266:	f002 fa79 	bl	800e75c <RCCEx_PLL3_Config>
 800c26a:	4603      	mov	r3, r0
 800c26c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SAI1 clock source configuration done later after clock selection check */
        break;
 800c270:	e006      	b.n	800c280 <HAL_RCCEx_PeriphCLKConfig+0x384>
        /* SAI4B clock source configuration done later after clock selection check */
        break;
#endif /* RCC_VER_3_0 */

      default:
        ret = HAL_ERROR;
 800c272:	2301      	movs	r3, #1
 800c274:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c278:	e002      	b.n	800c280 <HAL_RCCEx_PeriphCLKConfig+0x384>
        break;
 800c27a:	bf00      	nop
 800c27c:	e000      	b.n	800c280 <HAL_RCCEx_PeriphCLKConfig+0x384>
        break;
 800c27e:	bf00      	nop
    }

    if (ret == HAL_OK)
 800c280:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c284:	2b00      	cmp	r3, #0
 800c286:	d10b      	bne.n	800c2a0 <HAL_RCCEx_PeriphCLKConfig+0x3a4>
    {
      /* Set the source of SAI4B clock*/
      __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
 800c288:	4b8e      	ldr	r3, [pc, #568]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c28a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800c28c:	f023 61e0 	bic.w	r1, r3, #117440512	@ 0x7000000
 800c290:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c294:	f8d3 30ac 	ldr.w	r3, [r3, #172]	@ 0xac
 800c298:	4a8a      	ldr	r2, [pc, #552]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c29a:	430b      	orrs	r3, r1
 800c29c:	6593      	str	r3, [r2, #88]	@ 0x58
 800c29e:	e003      	b.n	800c2a8 <HAL_RCCEx_PeriphCLKConfig+0x3ac>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c2a0:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c2a4:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
  }
#endif  /*SAI4*/

#if defined(QUADSPI)
  /*---------------------------- QSPI configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
 800c2a8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c2ac:	e9d3 2300 	ldrd	r2, r3, [r3]
 800c2b0:	f002 7300 	and.w	r3, r2, #33554432	@ 0x2000000
 800c2b4:	f8c7 30f0 	str.w	r3, [r7, #240]	@ 0xf0
 800c2b8:	2300      	movs	r3, #0
 800c2ba:	f8c7 30f4 	str.w	r3, [r7, #244]	@ 0xf4
 800c2be:	e9d7 123c 	ldrd	r1, r2, [r7, #240]	@ 0xf0
 800c2c2:	460b      	mov	r3, r1
 800c2c4:	4313      	orrs	r3, r2
 800c2c6:	d03a      	beq.n	800c33e <HAL_RCCEx_PeriphCLKConfig+0x442>
  {
    switch (PeriphClkInit->QspiClockSelection)
 800c2c8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c2cc:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800c2ce:	2b30      	cmp	r3, #48	@ 0x30
 800c2d0:	d01f      	beq.n	800c312 <HAL_RCCEx_PeriphCLKConfig+0x416>
 800c2d2:	2b30      	cmp	r3, #48	@ 0x30
 800c2d4:	d819      	bhi.n	800c30a <HAL_RCCEx_PeriphCLKConfig+0x40e>
 800c2d6:	2b20      	cmp	r3, #32
 800c2d8:	d00c      	beq.n	800c2f4 <HAL_RCCEx_PeriphCLKConfig+0x3f8>
 800c2da:	2b20      	cmp	r3, #32
 800c2dc:	d815      	bhi.n	800c30a <HAL_RCCEx_PeriphCLKConfig+0x40e>
 800c2de:	2b00      	cmp	r3, #0
 800c2e0:	d019      	beq.n	800c316 <HAL_RCCEx_PeriphCLKConfig+0x41a>
 800c2e2:	2b10      	cmp	r3, #16
 800c2e4:	d111      	bne.n	800c30a <HAL_RCCEx_PeriphCLKConfig+0x40e>
    {
      case RCC_QSPICLKSOURCE_PLL:      /* PLL is used as clock source for QSPI*/
        /* Enable QSPI Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800c2e6:	4b77      	ldr	r3, [pc, #476]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c2e8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800c2ea:	4a76      	ldr	r2, [pc, #472]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c2ec:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800c2f0:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* QSPI clock source configuration done later after clock selection check */
        break;
 800c2f2:	e011      	b.n	800c318 <HAL_RCCEx_PeriphCLKConfig+0x41c>

      case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 800c2f4:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c2f8:	3308      	adds	r3, #8
 800c2fa:	2102      	movs	r1, #2
 800c2fc:	4618      	mov	r0, r3
 800c2fe:	f002 f97b 	bl	800e5f8 <RCCEx_PLL2_Config>
 800c302:	4603      	mov	r3, r0
 800c304:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* QSPI clock source configuration done later after clock selection check */
        break;
 800c308:	e006      	b.n	800c318 <HAL_RCCEx_PeriphCLKConfig+0x41c>
      case RCC_QSPICLKSOURCE_D1HCLK:
        /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
        break;

      default:
        ret = HAL_ERROR;
 800c30a:	2301      	movs	r3, #1
 800c30c:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c310:	e002      	b.n	800c318 <HAL_RCCEx_PeriphCLKConfig+0x41c>
        break;
 800c312:	bf00      	nop
 800c314:	e000      	b.n	800c318 <HAL_RCCEx_PeriphCLKConfig+0x41c>
        break;
 800c316:	bf00      	nop
    }

    if (ret == HAL_OK)
 800c318:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c31c:	2b00      	cmp	r3, #0
 800c31e:	d10a      	bne.n	800c336 <HAL_RCCEx_PeriphCLKConfig+0x43a>
    {
      /* Set the source of QSPI clock*/
      __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
 800c320:	4b68      	ldr	r3, [pc, #416]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c322:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800c324:	f023 0130 	bic.w	r1, r3, #48	@ 0x30
 800c328:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c32c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800c32e:	4a65      	ldr	r2, [pc, #404]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c330:	430b      	orrs	r3, r1
 800c332:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800c334:	e003      	b.n	800c33e <HAL_RCCEx_PeriphCLKConfig+0x442>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c336:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c33a:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
#endif  /*OCTOSPI*/

  /*---------------------------- SPI1/2/3 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
 800c33e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c342:	e9d3 2300 	ldrd	r2, r3, [r3]
 800c346:	f402 5380 	and.w	r3, r2, #4096	@ 0x1000
 800c34a:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
 800c34e:	2300      	movs	r3, #0
 800c350:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
 800c354:	e9d7 123a 	ldrd	r1, r2, [r7, #232]	@ 0xe8
 800c358:	460b      	mov	r3, r1
 800c35a:	4313      	orrs	r3, r2
 800c35c:	d051      	beq.n	800c402 <HAL_RCCEx_PeriphCLKConfig+0x506>
  {
    switch (PeriphClkInit->Spi123ClockSelection)
 800c35e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c362:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 800c364:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 800c368:	d035      	beq.n	800c3d6 <HAL_RCCEx_PeriphCLKConfig+0x4da>
 800c36a:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 800c36e:	d82e      	bhi.n	800c3ce <HAL_RCCEx_PeriphCLKConfig+0x4d2>
 800c370:	f5b3 5f40 	cmp.w	r3, #12288	@ 0x3000
 800c374:	d031      	beq.n	800c3da <HAL_RCCEx_PeriphCLKConfig+0x4de>
 800c376:	f5b3 5f40 	cmp.w	r3, #12288	@ 0x3000
 800c37a:	d828      	bhi.n	800c3ce <HAL_RCCEx_PeriphCLKConfig+0x4d2>
 800c37c:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800c380:	d01a      	beq.n	800c3b8 <HAL_RCCEx_PeriphCLKConfig+0x4bc>
 800c382:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800c386:	d822      	bhi.n	800c3ce <HAL_RCCEx_PeriphCLKConfig+0x4d2>
 800c388:	2b00      	cmp	r3, #0
 800c38a:	d003      	beq.n	800c394 <HAL_RCCEx_PeriphCLKConfig+0x498>
 800c38c:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800c390:	d007      	beq.n	800c3a2 <HAL_RCCEx_PeriphCLKConfig+0x4a6>
 800c392:	e01c      	b.n	800c3ce <HAL_RCCEx_PeriphCLKConfig+0x4d2>
    {
      case RCC_SPI123CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1/2/3 */
        /* Enable SPI Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800c394:	4b4b      	ldr	r3, [pc, #300]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c396:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800c398:	4a4a      	ldr	r2, [pc, #296]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c39a:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800c39e:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SPI1/2/3 clock source configuration done later after clock selection check */
        break;
 800c3a0:	e01c      	b.n	800c3dc <HAL_RCCEx_PeriphCLKConfig+0x4e0>

      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800c3a2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c3a6:	3308      	adds	r3, #8
 800c3a8:	2100      	movs	r1, #0
 800c3aa:	4618      	mov	r0, r3
 800c3ac:	f002 f924 	bl	800e5f8 <RCCEx_PLL2_Config>
 800c3b0:	4603      	mov	r3, r0
 800c3b2:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SPI1/2/3 clock source configuration done later after clock selection check */
        break;
 800c3b6:	e011      	b.n	800c3dc <HAL_RCCEx_PeriphCLKConfig+0x4e0>

      case RCC_SPI123CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1/2/3 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 800c3b8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c3bc:	3328      	adds	r3, #40	@ 0x28
 800c3be:	2100      	movs	r1, #0
 800c3c0:	4618      	mov	r0, r3
 800c3c2:	f002 f9cb 	bl	800e75c <RCCEx_PLL3_Config>
 800c3c6:	4603      	mov	r3, r0
 800c3c8:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SPI1/2/3 clock source configuration done later after clock selection check */
        break;
 800c3cc:	e006      	b.n	800c3dc <HAL_RCCEx_PeriphCLKConfig+0x4e0>
        /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
        /* SPI1/2/3 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800c3ce:	2301      	movs	r3, #1
 800c3d0:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c3d4:	e002      	b.n	800c3dc <HAL_RCCEx_PeriphCLKConfig+0x4e0>
        break;
 800c3d6:	bf00      	nop
 800c3d8:	e000      	b.n	800c3dc <HAL_RCCEx_PeriphCLKConfig+0x4e0>
        break;
 800c3da:	bf00      	nop
    }

    if (ret == HAL_OK)
 800c3dc:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c3e0:	2b00      	cmp	r3, #0
 800c3e2:	d10a      	bne.n	800c3fa <HAL_RCCEx_PeriphCLKConfig+0x4fe>
    {
      /* Set the source of SPI1/2/3 clock*/
      __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
 800c3e4:	4b37      	ldr	r3, [pc, #220]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c3e6:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800c3e8:	f423 41e0 	bic.w	r1, r3, #28672	@ 0x7000
 800c3ec:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c3f0:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 800c3f2:	4a34      	ldr	r2, [pc, #208]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c3f4:	430b      	orrs	r3, r1
 800c3f6:	6513      	str	r3, [r2, #80]	@ 0x50
 800c3f8:	e003      	b.n	800c402 <HAL_RCCEx_PeriphCLKConfig+0x506>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c3fa:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c3fe:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- SPI4/5 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
 800c402:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c406:	e9d3 2300 	ldrd	r2, r3, [r3]
 800c40a:	f402 5300 	and.w	r3, r2, #8192	@ 0x2000
 800c40e:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
 800c412:	2300      	movs	r3, #0
 800c414:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
 800c418:	e9d7 1238 	ldrd	r1, r2, [r7, #224]	@ 0xe0
 800c41c:	460b      	mov	r3, r1
 800c41e:	4313      	orrs	r3, r2
 800c420:	d056      	beq.n	800c4d0 <HAL_RCCEx_PeriphCLKConfig+0x5d4>
  {
    switch (PeriphClkInit->Spi45ClockSelection)
 800c422:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c426:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 800c428:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 800c42c:	d033      	beq.n	800c496 <HAL_RCCEx_PeriphCLKConfig+0x59a>
 800c42e:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 800c432:	d82c      	bhi.n	800c48e <HAL_RCCEx_PeriphCLKConfig+0x592>
 800c434:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
 800c438:	d02f      	beq.n	800c49a <HAL_RCCEx_PeriphCLKConfig+0x59e>
 800c43a:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
 800c43e:	d826      	bhi.n	800c48e <HAL_RCCEx_PeriphCLKConfig+0x592>
 800c440:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
 800c444:	d02b      	beq.n	800c49e <HAL_RCCEx_PeriphCLKConfig+0x5a2>
 800c446:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
 800c44a:	d820      	bhi.n	800c48e <HAL_RCCEx_PeriphCLKConfig+0x592>
 800c44c:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800c450:	d012      	beq.n	800c478 <HAL_RCCEx_PeriphCLKConfig+0x57c>
 800c452:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800c456:	d81a      	bhi.n	800c48e <HAL_RCCEx_PeriphCLKConfig+0x592>
 800c458:	2b00      	cmp	r3, #0
 800c45a:	d022      	beq.n	800c4a2 <HAL_RCCEx_PeriphCLKConfig+0x5a6>
 800c45c:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800c460:	d115      	bne.n	800c48e <HAL_RCCEx_PeriphCLKConfig+0x592>
        /* SPI4/5 clock source configuration done later after clock selection check */
        break;

      case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 800c462:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c466:	3308      	adds	r3, #8
 800c468:	2101      	movs	r1, #1
 800c46a:	4618      	mov	r0, r3
 800c46c:	f002 f8c4 	bl	800e5f8 <RCCEx_PLL2_Config>
 800c470:	4603      	mov	r3, r0
 800c472:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SPI4/5 clock source configuration done later after clock selection check */
        break;
 800c476:	e015      	b.n	800c4a4 <HAL_RCCEx_PeriphCLKConfig+0x5a8>
      case RCC_SPI45CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4/5 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 800c478:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c47c:	3328      	adds	r3, #40	@ 0x28
 800c47e:	2101      	movs	r1, #1
 800c480:	4618      	mov	r0, r3
 800c482:	f002 f96b 	bl	800e75c <RCCEx_PLL3_Config>
 800c486:	4603      	mov	r3, r0
 800c488:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* SPI4/5 clock source configuration done later after clock selection check */
        break;
 800c48c:	e00a      	b.n	800c4a4 <HAL_RCCEx_PeriphCLKConfig+0x5a8>
        /* HSE,  oscillator is used as source of SPI4/5 clock */
        /* SPI4/5 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800c48e:	2301      	movs	r3, #1
 800c490:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c494:	e006      	b.n	800c4a4 <HAL_RCCEx_PeriphCLKConfig+0x5a8>
        break;
 800c496:	bf00      	nop
 800c498:	e004      	b.n	800c4a4 <HAL_RCCEx_PeriphCLKConfig+0x5a8>
        break;
 800c49a:	bf00      	nop
 800c49c:	e002      	b.n	800c4a4 <HAL_RCCEx_PeriphCLKConfig+0x5a8>
        break;
 800c49e:	bf00      	nop
 800c4a0:	e000      	b.n	800c4a4 <HAL_RCCEx_PeriphCLKConfig+0x5a8>
        break;
 800c4a2:	bf00      	nop
    }

    if (ret == HAL_OK)
 800c4a4:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c4a8:	2b00      	cmp	r3, #0
 800c4aa:	d10d      	bne.n	800c4c8 <HAL_RCCEx_PeriphCLKConfig+0x5cc>
    {
      /* Set the source of SPI4/5 clock*/
      __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
 800c4ac:	4b05      	ldr	r3, [pc, #20]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c4ae:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800c4b0:	f423 21e0 	bic.w	r1, r3, #458752	@ 0x70000
 800c4b4:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c4b8:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 800c4ba:	4a02      	ldr	r2, [pc, #8]	@ (800c4c4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
 800c4bc:	430b      	orrs	r3, r1
 800c4be:	6513      	str	r3, [r2, #80]	@ 0x50
 800c4c0:	e006      	b.n	800c4d0 <HAL_RCCEx_PeriphCLKConfig+0x5d4>
 800c4c2:	bf00      	nop
 800c4c4:	58024400 	.word	0x58024400
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c4c8:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c4cc:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- SPI6 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
 800c4d0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c4d4:	e9d3 2300 	ldrd	r2, r3, [r3]
 800c4d8:	f402 4380 	and.w	r3, r2, #16384	@ 0x4000
 800c4dc:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
 800c4e0:	2300      	movs	r3, #0
 800c4e2:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
 800c4e6:	e9d7 1236 	ldrd	r1, r2, [r7, #216]	@ 0xd8
 800c4ea:	460b      	mov	r3, r1
 800c4ec:	4313      	orrs	r3, r2
 800c4ee:	d055      	beq.n	800c59c <HAL_RCCEx_PeriphCLKConfig+0x6a0>
  {
    switch (PeriphClkInit->Spi6ClockSelection)
 800c4f0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c4f4:	f8d3 30b0 	ldr.w	r3, [r3, #176]	@ 0xb0
 800c4f8:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 800c4fc:	d033      	beq.n	800c566 <HAL_RCCEx_PeriphCLKConfig+0x66a>
 800c4fe:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 800c502:	d82c      	bhi.n	800c55e <HAL_RCCEx_PeriphCLKConfig+0x662>
 800c504:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800c508:	d02f      	beq.n	800c56a <HAL_RCCEx_PeriphCLKConfig+0x66e>
 800c50a:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800c50e:	d826      	bhi.n	800c55e <HAL_RCCEx_PeriphCLKConfig+0x662>
 800c510:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
 800c514:	d02b      	beq.n	800c56e <HAL_RCCEx_PeriphCLKConfig+0x672>
 800c516:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
 800c51a:	d820      	bhi.n	800c55e <HAL_RCCEx_PeriphCLKConfig+0x662>
 800c51c:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800c520:	d012      	beq.n	800c548 <HAL_RCCEx_PeriphCLKConfig+0x64c>
 800c522:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800c526:	d81a      	bhi.n	800c55e <HAL_RCCEx_PeriphCLKConfig+0x662>
 800c528:	2b00      	cmp	r3, #0
 800c52a:	d022      	beq.n	800c572 <HAL_RCCEx_PeriphCLKConfig+0x676>
 800c52c:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800c530:	d115      	bne.n	800c55e <HAL_RCCEx_PeriphCLKConfig+0x662>
        /* SPI6 clock source configuration done later after clock selection check */
        break;

      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 800c532:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c536:	3308      	adds	r3, #8
 800c538:	2101      	movs	r1, #1
 800c53a:	4618      	mov	r0, r3
 800c53c:	f002 f85c 	bl	800e5f8 <RCCEx_PLL2_Config>
 800c540:	4603      	mov	r3, r0
 800c542:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SPI6 clock source configuration done later after clock selection check */
        break;
 800c546:	e015      	b.n	800c574 <HAL_RCCEx_PeriphCLKConfig+0x678>
      case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 800c548:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c54c:	3328      	adds	r3, #40	@ 0x28
 800c54e:	2101      	movs	r1, #1
 800c550:	4618      	mov	r0, r3
 800c552:	f002 f903 	bl	800e75c <RCCEx_PLL3_Config>
 800c556:	4603      	mov	r3, r0
 800c558:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* SPI6 clock source configuration done later after clock selection check */
        break;
 800c55c:	e00a      	b.n	800c574 <HAL_RCCEx_PeriphCLKConfig+0x678>
        /* SPI6 clock source configuration done later after clock selection check */
        break;
#endif

      default:
        ret = HAL_ERROR;
 800c55e:	2301      	movs	r3, #1
 800c560:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c564:	e006      	b.n	800c574 <HAL_RCCEx_PeriphCLKConfig+0x678>
        break;
 800c566:	bf00      	nop
 800c568:	e004      	b.n	800c574 <HAL_RCCEx_PeriphCLKConfig+0x678>
        break;
 800c56a:	bf00      	nop
 800c56c:	e002      	b.n	800c574 <HAL_RCCEx_PeriphCLKConfig+0x678>
        break;
 800c56e:	bf00      	nop
 800c570:	e000      	b.n	800c574 <HAL_RCCEx_PeriphCLKConfig+0x678>
        break;
 800c572:	bf00      	nop
    }

    if (ret == HAL_OK)
 800c574:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c578:	2b00      	cmp	r3, #0
 800c57a:	d10b      	bne.n	800c594 <HAL_RCCEx_PeriphCLKConfig+0x698>
    {
      /* Set the source of SPI6 clock*/
      __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
 800c57c:	4ba3      	ldr	r3, [pc, #652]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c57e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800c580:	f023 41e0 	bic.w	r1, r3, #1879048192	@ 0x70000000
 800c584:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c588:	f8d3 30b0 	ldr.w	r3, [r3, #176]	@ 0xb0
 800c58c:	4a9f      	ldr	r2, [pc, #636]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c58e:	430b      	orrs	r3, r1
 800c590:	6593      	str	r3, [r2, #88]	@ 0x58
 800c592:	e003      	b.n	800c59c <HAL_RCCEx_PeriphCLKConfig+0x6a0>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c594:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c598:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
  }
#endif /*DSI*/

#if defined(FDCAN1) || defined(FDCAN2)
  /*---------------------------- FDCAN configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
 800c59c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c5a0:	e9d3 2300 	ldrd	r2, r3, [r3]
 800c5a4:	f402 4300 	and.w	r3, r2, #32768	@ 0x8000
 800c5a8:	f8c7 30d0 	str.w	r3, [r7, #208]	@ 0xd0
 800c5ac:	2300      	movs	r3, #0
 800c5ae:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
 800c5b2:	e9d7 1234 	ldrd	r1, r2, [r7, #208]	@ 0xd0
 800c5b6:	460b      	mov	r3, r1
 800c5b8:	4313      	orrs	r3, r2
 800c5ba:	d037      	beq.n	800c62c <HAL_RCCEx_PeriphCLKConfig+0x730>
  {
    switch (PeriphClkInit->FdcanClockSelection)
 800c5bc:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c5c0:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800c5c2:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800c5c6:	d00e      	beq.n	800c5e6 <HAL_RCCEx_PeriphCLKConfig+0x6ea>
 800c5c8:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800c5cc:	d816      	bhi.n	800c5fc <HAL_RCCEx_PeriphCLKConfig+0x700>
 800c5ce:	2b00      	cmp	r3, #0
 800c5d0:	d018      	beq.n	800c604 <HAL_RCCEx_PeriphCLKConfig+0x708>
 800c5d2:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800c5d6:	d111      	bne.n	800c5fc <HAL_RCCEx_PeriphCLKConfig+0x700>
    {
      case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
        /* Enable FDCAN Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800c5d8:	4b8c      	ldr	r3, [pc, #560]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c5da:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800c5dc:	4a8b      	ldr	r2, [pc, #556]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c5de:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800c5e2:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* FDCAN clock source configuration done later after clock selection check */
        break;
 800c5e4:	e00f      	b.n	800c606 <HAL_RCCEx_PeriphCLKConfig+0x70a>

      case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 800c5e6:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c5ea:	3308      	adds	r3, #8
 800c5ec:	2101      	movs	r1, #1
 800c5ee:	4618      	mov	r0, r3
 800c5f0:	f002 f802 	bl	800e5f8 <RCCEx_PLL2_Config>
 800c5f4:	4603      	mov	r3, r0
 800c5f6:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* FDCAN clock source configuration done later after clock selection check */
        break;
 800c5fa:	e004      	b.n	800c606 <HAL_RCCEx_PeriphCLKConfig+0x70a>
        /* HSE is used as clock source for FDCAN*/
        /* FDCAN clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800c5fc:	2301      	movs	r3, #1
 800c5fe:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c602:	e000      	b.n	800c606 <HAL_RCCEx_PeriphCLKConfig+0x70a>
        break;
 800c604:	bf00      	nop
    }

    if (ret == HAL_OK)
 800c606:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c60a:	2b00      	cmp	r3, #0
 800c60c:	d10a      	bne.n	800c624 <HAL_RCCEx_PeriphCLKConfig+0x728>
    {
      /* Set the source of FDCAN clock*/
      __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
 800c60e:	4b7f      	ldr	r3, [pc, #508]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c610:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800c612:	f023 5140 	bic.w	r1, r3, #805306368	@ 0x30000000
 800c616:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c61a:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800c61c:	4a7b      	ldr	r2, [pc, #492]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c61e:	430b      	orrs	r3, r1
 800c620:	6513      	str	r3, [r2, #80]	@ 0x50
 800c622:	e003      	b.n	800c62c <HAL_RCCEx_PeriphCLKConfig+0x730>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c624:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c628:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
#endif /*FDCAN1 || FDCAN2*/

  /*---------------------------- FMC configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
 800c62c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c630:	e9d3 2300 	ldrd	r2, r3, [r3]
 800c634:	f002 7380 	and.w	r3, r2, #16777216	@ 0x1000000
 800c638:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
 800c63c:	2300      	movs	r3, #0
 800c63e:	f8c7 30cc 	str.w	r3, [r7, #204]	@ 0xcc
 800c642:	e9d7 1232 	ldrd	r1, r2, [r7, #200]	@ 0xc8
 800c646:	460b      	mov	r3, r1
 800c648:	4313      	orrs	r3, r2
 800c64a:	d039      	beq.n	800c6c0 <HAL_RCCEx_PeriphCLKConfig+0x7c4>
  {
    switch (PeriphClkInit->FmcClockSelection)
 800c64c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c650:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 800c652:	2b03      	cmp	r3, #3
 800c654:	d81c      	bhi.n	800c690 <HAL_RCCEx_PeriphCLKConfig+0x794>
 800c656:	a201      	add	r2, pc, #4	@ (adr r2, 800c65c <HAL_RCCEx_PeriphCLKConfig+0x760>)
 800c658:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800c65c:	0800c699 	.word	0x0800c699
 800c660:	0800c66d 	.word	0x0800c66d
 800c664:	0800c67b 	.word	0x0800c67b
 800c668:	0800c699 	.word	0x0800c699
    {
      case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
        /* Enable FMC Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800c66c:	4b67      	ldr	r3, [pc, #412]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c66e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800c670:	4a66      	ldr	r2, [pc, #408]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c672:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800c676:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* FMC clock source configuration done later after clock selection check */
        break;
 800c678:	e00f      	b.n	800c69a <HAL_RCCEx_PeriphCLKConfig+0x79e>

      case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 800c67a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c67e:	3308      	adds	r3, #8
 800c680:	2102      	movs	r1, #2
 800c682:	4618      	mov	r0, r3
 800c684:	f001 ffb8 	bl	800e5f8 <RCCEx_PLL2_Config>
 800c688:	4603      	mov	r3, r0
 800c68a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* FMC clock source configuration done later after clock selection check */
        break;
 800c68e:	e004      	b.n	800c69a <HAL_RCCEx_PeriphCLKConfig+0x79e>
      case RCC_FMCCLKSOURCE_HCLK:
        /* D1/CD HCLK  clock selected as FMC kernel peripheral clock */
        break;

      default:
        ret = HAL_ERROR;
 800c690:	2301      	movs	r3, #1
 800c692:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c696:	e000      	b.n	800c69a <HAL_RCCEx_PeriphCLKConfig+0x79e>
        break;
 800c698:	bf00      	nop
    }

    if (ret == HAL_OK)
 800c69a:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c69e:	2b00      	cmp	r3, #0
 800c6a0:	d10a      	bne.n	800c6b8 <HAL_RCCEx_PeriphCLKConfig+0x7bc>
    {
      /* Set the source of FMC clock*/
      __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
 800c6a2:	4b5a      	ldr	r3, [pc, #360]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c6a4:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800c6a6:	f023 0103 	bic.w	r1, r3, #3
 800c6aa:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c6ae:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 800c6b0:	4a56      	ldr	r2, [pc, #344]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c6b2:	430b      	orrs	r3, r1
 800c6b4:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800c6b6:	e003      	b.n	800c6c0 <HAL_RCCEx_PeriphCLKConfig+0x7c4>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c6b8:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c6bc:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- RTC configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
 800c6c0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c6c4:	e9d3 2300 	ldrd	r2, r3, [r3]
 800c6c8:	f402 0380 	and.w	r3, r2, #4194304	@ 0x400000
 800c6cc:	f8c7 30c0 	str.w	r3, [r7, #192]	@ 0xc0
 800c6d0:	2300      	movs	r3, #0
 800c6d2:	f8c7 30c4 	str.w	r3, [r7, #196]	@ 0xc4
 800c6d6:	e9d7 1230 	ldrd	r1, r2, [r7, #192]	@ 0xc0
 800c6da:	460b      	mov	r3, r1
 800c6dc:	4313      	orrs	r3, r2
 800c6de:	f000 809f 	beq.w	800c820 <HAL_RCCEx_PeriphCLKConfig+0x924>
  {
    /* check for RTC Parameters used to output RTCCLK */
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));

    /* Enable write access to Backup domain */
    SET_BIT(PWR->CR1, PWR_CR1_DBP);
 800c6e2:	4b4b      	ldr	r3, [pc, #300]	@ (800c810 <HAL_RCCEx_PeriphCLKConfig+0x914>)
 800c6e4:	681b      	ldr	r3, [r3, #0]
 800c6e6:	4a4a      	ldr	r2, [pc, #296]	@ (800c810 <HAL_RCCEx_PeriphCLKConfig+0x914>)
 800c6e8:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 800c6ec:	6013      	str	r3, [r2, #0]

    /* Wait for Backup domain Write protection disable */
    tickstart = HAL_GetTick();
 800c6ee:	f7f8 fea5 	bl	800543c <HAL_GetTick>
 800c6f2:	f8c7 0118 	str.w	r0, [r7, #280]	@ 0x118

    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
 800c6f6:	e00b      	b.n	800c710 <HAL_RCCEx_PeriphCLKConfig+0x814>
    {
      if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 800c6f8:	f7f8 fea0 	bl	800543c <HAL_GetTick>
 800c6fc:	4602      	mov	r2, r0
 800c6fe:	f8d7 3118 	ldr.w	r3, [r7, #280]	@ 0x118
 800c702:	1ad3      	subs	r3, r2, r3
 800c704:	2b64      	cmp	r3, #100	@ 0x64
 800c706:	d903      	bls.n	800c710 <HAL_RCCEx_PeriphCLKConfig+0x814>
      {
        ret = HAL_TIMEOUT;
 800c708:	2303      	movs	r3, #3
 800c70a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c70e:	e005      	b.n	800c71c <HAL_RCCEx_PeriphCLKConfig+0x820>
    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
 800c710:	4b3f      	ldr	r3, [pc, #252]	@ (800c810 <HAL_RCCEx_PeriphCLKConfig+0x914>)
 800c712:	681b      	ldr	r3, [r3, #0]
 800c714:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800c718:	2b00      	cmp	r3, #0
 800c71a:	d0ed      	beq.n	800c6f8 <HAL_RCCEx_PeriphCLKConfig+0x7fc>
      }
    }

    if (ret == HAL_OK)
 800c71c:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c720:	2b00      	cmp	r3, #0
 800c722:	d179      	bne.n	800c818 <HAL_RCCEx_PeriphCLKConfig+0x91c>
    {
      /* Reset the Backup domain only if the RTC Clock source selection is modified */
      if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
 800c724:	4b39      	ldr	r3, [pc, #228]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c726:	6f1a      	ldr	r2, [r3, #112]	@ 0x70
 800c728:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c72c:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
 800c730:	4053      	eors	r3, r2
 800c732:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 800c736:	2b00      	cmp	r3, #0
 800c738:	d015      	beq.n	800c766 <HAL_RCCEx_PeriphCLKConfig+0x86a>
      {
        /* Store the content of BDCR register before the reset of Backup Domain */
        tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 800c73a:	4b34      	ldr	r3, [pc, #208]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c73c:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800c73e:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 800c742:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
        /* RTC Clock selection can be changed only if the Backup Domain is reset */
        __HAL_RCC_BACKUPRESET_FORCE();
 800c746:	4b31      	ldr	r3, [pc, #196]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c748:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800c74a:	4a30      	ldr	r2, [pc, #192]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c74c:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800c750:	6713      	str	r3, [r2, #112]	@ 0x70
        __HAL_RCC_BACKUPRESET_RELEASE();
 800c752:	4b2e      	ldr	r3, [pc, #184]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c754:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800c756:	4a2d      	ldr	r2, [pc, #180]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c758:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800c75c:	6713      	str	r3, [r2, #112]	@ 0x70
        /* Restore the Content of BDCR register */
        RCC->BDCR = tmpreg;
 800c75e:	4a2b      	ldr	r2, [pc, #172]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c760:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
 800c764:	6713      	str	r3, [r2, #112]	@ 0x70
      }

      /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
      if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
 800c766:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c76a:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
 800c76e:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800c772:	d118      	bne.n	800c7a6 <HAL_RCCEx_PeriphCLKConfig+0x8aa>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800c774:	f7f8 fe62 	bl	800543c <HAL_GetTick>
 800c778:	f8c7 0118 	str.w	r0, [r7, #280]	@ 0x118

        /* Wait till LSE is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 800c77c:	e00d      	b.n	800c79a <HAL_RCCEx_PeriphCLKConfig+0x89e>
        {
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800c77e:	f7f8 fe5d 	bl	800543c <HAL_GetTick>
 800c782:	4602      	mov	r2, r0
 800c784:	f8d7 3118 	ldr.w	r3, [r7, #280]	@ 0x118
 800c788:	1ad2      	subs	r2, r2, r3
 800c78a:	f241 3388 	movw	r3, #5000	@ 0x1388
 800c78e:	429a      	cmp	r2, r3
 800c790:	d903      	bls.n	800c79a <HAL_RCCEx_PeriphCLKConfig+0x89e>
          {
            ret = HAL_TIMEOUT;
 800c792:	2303      	movs	r3, #3
 800c794:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
            break;
 800c798:	e005      	b.n	800c7a6 <HAL_RCCEx_PeriphCLKConfig+0x8aa>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 800c79a:	4b1c      	ldr	r3, [pc, #112]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c79c:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 800c79e:	f003 0302 	and.w	r3, r3, #2
 800c7a2:	2b00      	cmp	r3, #0
 800c7a4:	d0eb      	beq.n	800c77e <HAL_RCCEx_PeriphCLKConfig+0x882>
          }
        }
      }

      if (ret == HAL_OK)
 800c7a6:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c7aa:	2b00      	cmp	r3, #0
 800c7ac:	d129      	bne.n	800c802 <HAL_RCCEx_PeriphCLKConfig+0x906>
      {
        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 800c7ae:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c7b2:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
 800c7b6:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 800c7ba:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 800c7be:	d10e      	bne.n	800c7de <HAL_RCCEx_PeriphCLKConfig+0x8e2>
 800c7c0:	4b12      	ldr	r3, [pc, #72]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c7c2:	691b      	ldr	r3, [r3, #16]
 800c7c4:	f423 517c 	bic.w	r1, r3, #16128	@ 0x3f00
 800c7c8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c7cc:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
 800c7d0:	091a      	lsrs	r2, r3, #4
 800c7d2:	4b10      	ldr	r3, [pc, #64]	@ (800c814 <HAL_RCCEx_PeriphCLKConfig+0x918>)
 800c7d4:	4013      	ands	r3, r2
 800c7d6:	4a0d      	ldr	r2, [pc, #52]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c7d8:	430b      	orrs	r3, r1
 800c7da:	6113      	str	r3, [r2, #16]
 800c7dc:	e005      	b.n	800c7ea <HAL_RCCEx_PeriphCLKConfig+0x8ee>
 800c7de:	4b0b      	ldr	r3, [pc, #44]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c7e0:	691b      	ldr	r3, [r3, #16]
 800c7e2:	4a0a      	ldr	r2, [pc, #40]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c7e4:	f423 537c 	bic.w	r3, r3, #16128	@ 0x3f00
 800c7e8:	6113      	str	r3, [r2, #16]
 800c7ea:	4b08      	ldr	r3, [pc, #32]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c7ec:	6f19      	ldr	r1, [r3, #112]	@ 0x70
 800c7ee:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c7f2:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
 800c7f6:	f3c3 030b 	ubfx	r3, r3, #0, #12
 800c7fa:	4a04      	ldr	r2, [pc, #16]	@ (800c80c <HAL_RCCEx_PeriphCLKConfig+0x910>)
 800c7fc:	430b      	orrs	r3, r1
 800c7fe:	6713      	str	r3, [r2, #112]	@ 0x70
 800c800:	e00e      	b.n	800c820 <HAL_RCCEx_PeriphCLKConfig+0x924>
      }
      else
      {
        /* set overall return value */
        status = ret;
 800c802:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c806:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
 800c80a:	e009      	b.n	800c820 <HAL_RCCEx_PeriphCLKConfig+0x924>
 800c80c:	58024400 	.word	0x58024400
 800c810:	58024800 	.word	0x58024800
 800c814:	00ffffcf 	.word	0x00ffffcf
      }
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c818:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c81c:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }


  /*-------------------------- USART1/6 configuration --------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
 800c820:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c824:	e9d3 2300 	ldrd	r2, r3, [r3]
 800c828:	f002 0301 	and.w	r3, r2, #1
 800c82c:	f8c7 30b8 	str.w	r3, [r7, #184]	@ 0xb8
 800c830:	2300      	movs	r3, #0
 800c832:	f8c7 30bc 	str.w	r3, [r7, #188]	@ 0xbc
 800c836:	e9d7 122e 	ldrd	r1, r2, [r7, #184]	@ 0xb8
 800c83a:	460b      	mov	r3, r1
 800c83c:	4313      	orrs	r3, r2
 800c83e:	f000 8089 	beq.w	800c954 <HAL_RCCEx_PeriphCLKConfig+0xa58>
  {
    switch (PeriphClkInit->Usart16ClockSelection)
 800c842:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c846:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 800c848:	2b28      	cmp	r3, #40	@ 0x28
 800c84a:	d86b      	bhi.n	800c924 <HAL_RCCEx_PeriphCLKConfig+0xa28>
 800c84c:	a201      	add	r2, pc, #4	@ (adr r2, 800c854 <HAL_RCCEx_PeriphCLKConfig+0x958>)
 800c84e:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800c852:	bf00      	nop
 800c854:	0800c92d 	.word	0x0800c92d
 800c858:	0800c925 	.word	0x0800c925
 800c85c:	0800c925 	.word	0x0800c925
 800c860:	0800c925 	.word	0x0800c925
 800c864:	0800c925 	.word	0x0800c925
 800c868:	0800c925 	.word	0x0800c925
 800c86c:	0800c925 	.word	0x0800c925
 800c870:	0800c925 	.word	0x0800c925
 800c874:	0800c8f9 	.word	0x0800c8f9
 800c878:	0800c925 	.word	0x0800c925
 800c87c:	0800c925 	.word	0x0800c925
 800c880:	0800c925 	.word	0x0800c925
 800c884:	0800c925 	.word	0x0800c925
 800c888:	0800c925 	.word	0x0800c925
 800c88c:	0800c925 	.word	0x0800c925
 800c890:	0800c925 	.word	0x0800c925
 800c894:	0800c90f 	.word	0x0800c90f
 800c898:	0800c925 	.word	0x0800c925
 800c89c:	0800c925 	.word	0x0800c925
 800c8a0:	0800c925 	.word	0x0800c925
 800c8a4:	0800c925 	.word	0x0800c925
 800c8a8:	0800c925 	.word	0x0800c925
 800c8ac:	0800c925 	.word	0x0800c925
 800c8b0:	0800c925 	.word	0x0800c925
 800c8b4:	0800c92d 	.word	0x0800c92d
 800c8b8:	0800c925 	.word	0x0800c925
 800c8bc:	0800c925 	.word	0x0800c925
 800c8c0:	0800c925 	.word	0x0800c925
 800c8c4:	0800c925 	.word	0x0800c925
 800c8c8:	0800c925 	.word	0x0800c925
 800c8cc:	0800c925 	.word	0x0800c925
 800c8d0:	0800c925 	.word	0x0800c925
 800c8d4:	0800c92d 	.word	0x0800c92d
 800c8d8:	0800c925 	.word	0x0800c925
 800c8dc:	0800c925 	.word	0x0800c925
 800c8e0:	0800c925 	.word	0x0800c925
 800c8e4:	0800c925 	.word	0x0800c925
 800c8e8:	0800c925 	.word	0x0800c925
 800c8ec:	0800c925 	.word	0x0800c925
 800c8f0:	0800c925 	.word	0x0800c925
 800c8f4:	0800c92d 	.word	0x0800c92d
      case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
        /* USART1/6 clock source configuration done later after clock selection check */
        break;

      case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 800c8f8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c8fc:	3308      	adds	r3, #8
 800c8fe:	2101      	movs	r1, #1
 800c900:	4618      	mov	r0, r3
 800c902:	f001 fe79 	bl	800e5f8 <RCCEx_PLL2_Config>
 800c906:	4603      	mov	r3, r0
 800c908:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* USART1/6 clock source configuration done later after clock selection check */
        break;
 800c90c:	e00f      	b.n	800c92e <HAL_RCCEx_PeriphCLKConfig+0xa32>

      case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 800c90e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c912:	3328      	adds	r3, #40	@ 0x28
 800c914:	2101      	movs	r1, #1
 800c916:	4618      	mov	r0, r3
 800c918:	f001 ff20 	bl	800e75c <RCCEx_PLL3_Config>
 800c91c:	4603      	mov	r3, r0
 800c91e:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* USART1/6 clock source configuration done later after clock selection check */
        break;
 800c922:	e004      	b.n	800c92e <HAL_RCCEx_PeriphCLKConfig+0xa32>
        /* LSE,  oscillator is used as source of USART1/6 clock */
        /* USART1/6 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800c924:	2301      	movs	r3, #1
 800c926:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c92a:	e000      	b.n	800c92e <HAL_RCCEx_PeriphCLKConfig+0xa32>
        break;
 800c92c:	bf00      	nop
    }

    if (ret == HAL_OK)
 800c92e:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c932:	2b00      	cmp	r3, #0
 800c934:	d10a      	bne.n	800c94c <HAL_RCCEx_PeriphCLKConfig+0xa50>
    {
      /* Set the source of USART1/6 clock */
      __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
 800c936:	4bbf      	ldr	r3, [pc, #764]	@ (800cc34 <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800c938:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800c93a:	f023 0138 	bic.w	r1, r3, #56	@ 0x38
 800c93e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c942:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 800c944:	4abb      	ldr	r2, [pc, #748]	@ (800cc34 <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800c946:	430b      	orrs	r3, r1
 800c948:	6553      	str	r3, [r2, #84]	@ 0x54
 800c94a:	e003      	b.n	800c954 <HAL_RCCEx_PeriphCLKConfig+0xa58>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c94c:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c950:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
 800c954:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c958:	e9d3 2300 	ldrd	r2, r3, [r3]
 800c95c:	f002 0302 	and.w	r3, r2, #2
 800c960:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
 800c964:	2300      	movs	r3, #0
 800c966:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
 800c96a:	e9d7 122c 	ldrd	r1, r2, [r7, #176]	@ 0xb0
 800c96e:	460b      	mov	r3, r1
 800c970:	4313      	orrs	r3, r2
 800c972:	d041      	beq.n	800c9f8 <HAL_RCCEx_PeriphCLKConfig+0xafc>
  {
    switch (PeriphClkInit->Usart234578ClockSelection)
 800c974:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c978:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 800c97a:	2b05      	cmp	r3, #5
 800c97c:	d824      	bhi.n	800c9c8 <HAL_RCCEx_PeriphCLKConfig+0xacc>
 800c97e:	a201      	add	r2, pc, #4	@ (adr r2, 800c984 <HAL_RCCEx_PeriphCLKConfig+0xa88>)
 800c980:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800c984:	0800c9d1 	.word	0x0800c9d1
 800c988:	0800c99d 	.word	0x0800c99d
 800c98c:	0800c9b3 	.word	0x0800c9b3
 800c990:	0800c9d1 	.word	0x0800c9d1
 800c994:	0800c9d1 	.word	0x0800c9d1
 800c998:	0800c9d1 	.word	0x0800c9d1
      case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
        break;

      case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 800c99c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c9a0:	3308      	adds	r3, #8
 800c9a2:	2101      	movs	r1, #1
 800c9a4:	4618      	mov	r0, r3
 800c9a6:	f001 fe27 	bl	800e5f8 <RCCEx_PLL2_Config>
 800c9aa:	4603      	mov	r3, r0
 800c9ac:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
        break;
 800c9b0:	e00f      	b.n	800c9d2 <HAL_RCCEx_PeriphCLKConfig+0xad6>

      case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 800c9b2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c9b6:	3328      	adds	r3, #40	@ 0x28
 800c9b8:	2101      	movs	r1, #1
 800c9ba:	4618      	mov	r0, r3
 800c9bc:	f001 fece 	bl	800e75c <RCCEx_PLL3_Config>
 800c9c0:	4603      	mov	r3, r0
 800c9c2:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
        break;
 800c9c6:	e004      	b.n	800c9d2 <HAL_RCCEx_PeriphCLKConfig+0xad6>
        /* LSE,  oscillator is used as source of USART2/3/4/5/7/8 clock */
        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800c9c8:	2301      	movs	r3, #1
 800c9ca:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800c9ce:	e000      	b.n	800c9d2 <HAL_RCCEx_PeriphCLKConfig+0xad6>
        break;
 800c9d0:	bf00      	nop
    }

    if (ret == HAL_OK)
 800c9d2:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c9d6:	2b00      	cmp	r3, #0
 800c9d8:	d10a      	bne.n	800c9f0 <HAL_RCCEx_PeriphCLKConfig+0xaf4>
    {
      /* Set the source of USART2/3/4/5/7/8 clock */
      __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
 800c9da:	4b96      	ldr	r3, [pc, #600]	@ (800cc34 <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800c9dc:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800c9de:	f023 0107 	bic.w	r1, r3, #7
 800c9e2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c9e6:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 800c9e8:	4a92      	ldr	r2, [pc, #584]	@ (800cc34 <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800c9ea:	430b      	orrs	r3, r1
 800c9ec:	6553      	str	r3, [r2, #84]	@ 0x54
 800c9ee:	e003      	b.n	800c9f8 <HAL_RCCEx_PeriphCLKConfig+0xafc>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800c9f0:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800c9f4:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*-------------------------- LPUART1 Configuration -------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
 800c9f8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800c9fc:	e9d3 2300 	ldrd	r2, r3, [r3]
 800ca00:	f002 0304 	and.w	r3, r2, #4
 800ca04:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
 800ca08:	2300      	movs	r3, #0
 800ca0a:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
 800ca0e:	e9d7 122a 	ldrd	r1, r2, [r7, #168]	@ 0xa8
 800ca12:	460b      	mov	r3, r1
 800ca14:	4313      	orrs	r3, r2
 800ca16:	d044      	beq.n	800caa2 <HAL_RCCEx_PeriphCLKConfig+0xba6>
  {
    switch (PeriphClkInit->Lpuart1ClockSelection)
 800ca18:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800ca1c:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 800ca20:	2b05      	cmp	r3, #5
 800ca22:	d825      	bhi.n	800ca70 <HAL_RCCEx_PeriphCLKConfig+0xb74>
 800ca24:	a201      	add	r2, pc, #4	@ (adr r2, 800ca2c <HAL_RCCEx_PeriphCLKConfig+0xb30>)
 800ca26:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800ca2a:	bf00      	nop
 800ca2c:	0800ca79 	.word	0x0800ca79
 800ca30:	0800ca45 	.word	0x0800ca45
 800ca34:	0800ca5b 	.word	0x0800ca5b
 800ca38:	0800ca79 	.word	0x0800ca79
 800ca3c:	0800ca79 	.word	0x0800ca79
 800ca40:	0800ca79 	.word	0x0800ca79
      case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
        /* LPUART1 clock source configuration done later after clock selection check */
        break;

      case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 800ca44:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800ca48:	3308      	adds	r3, #8
 800ca4a:	2101      	movs	r1, #1
 800ca4c:	4618      	mov	r0, r3
 800ca4e:	f001 fdd3 	bl	800e5f8 <RCCEx_PLL2_Config>
 800ca52:	4603      	mov	r3, r0
 800ca54:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* LPUART1 clock source configuration done later after clock selection check */
        break;
 800ca58:	e00f      	b.n	800ca7a <HAL_RCCEx_PeriphCLKConfig+0xb7e>

      case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 800ca5a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800ca5e:	3328      	adds	r3, #40	@ 0x28
 800ca60:	2101      	movs	r1, #1
 800ca62:	4618      	mov	r0, r3
 800ca64:	f001 fe7a 	bl	800e75c <RCCEx_PLL3_Config>
 800ca68:	4603      	mov	r3, r0
 800ca6a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        /* LPUART1 clock source configuration done later after clock selection check */
        break;
 800ca6e:	e004      	b.n	800ca7a <HAL_RCCEx_PeriphCLKConfig+0xb7e>
        /* LSE,  oscillator is used as source of LPUART1 clock */
        /* LPUART1 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800ca70:	2301      	movs	r3, #1
 800ca72:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800ca76:	e000      	b.n	800ca7a <HAL_RCCEx_PeriphCLKConfig+0xb7e>
        break;
 800ca78:	bf00      	nop
    }

    if (ret == HAL_OK)
 800ca7a:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800ca7e:	2b00      	cmp	r3, #0
 800ca80:	d10b      	bne.n	800ca9a <HAL_RCCEx_PeriphCLKConfig+0xb9e>
    {
      /* Set the source of LPUART1 clock */
      __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
 800ca82:	4b6c      	ldr	r3, [pc, #432]	@ (800cc34 <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800ca84:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800ca86:	f023 0107 	bic.w	r1, r3, #7
 800ca8a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800ca8e:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 800ca92:	4a68      	ldr	r2, [pc, #416]	@ (800cc34 <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800ca94:	430b      	orrs	r3, r1
 800ca96:	6593      	str	r3, [r2, #88]	@ 0x58
 800ca98:	e003      	b.n	800caa2 <HAL_RCCEx_PeriphCLKConfig+0xba6>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800ca9a:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800ca9e:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- LPTIM1 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
 800caa2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800caa6:	e9d3 2300 	ldrd	r2, r3, [r3]
 800caaa:	f002 0320 	and.w	r3, r2, #32
 800caae:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
 800cab2:	2300      	movs	r3, #0
 800cab4:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
 800cab8:	e9d7 1228 	ldrd	r1, r2, [r7, #160]	@ 0xa0
 800cabc:	460b      	mov	r3, r1
 800cabe:	4313      	orrs	r3, r2
 800cac0:	d055      	beq.n	800cb6e <HAL_RCCEx_PeriphCLKConfig+0xc72>
  {
    switch (PeriphClkInit->Lptim1ClockSelection)
 800cac2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cac6:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800caca:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 800cace:	d033      	beq.n	800cb38 <HAL_RCCEx_PeriphCLKConfig+0xc3c>
 800cad0:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 800cad4:	d82c      	bhi.n	800cb30 <HAL_RCCEx_PeriphCLKConfig+0xc34>
 800cad6:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800cada:	d02f      	beq.n	800cb3c <HAL_RCCEx_PeriphCLKConfig+0xc40>
 800cadc:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800cae0:	d826      	bhi.n	800cb30 <HAL_RCCEx_PeriphCLKConfig+0xc34>
 800cae2:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
 800cae6:	d02b      	beq.n	800cb40 <HAL_RCCEx_PeriphCLKConfig+0xc44>
 800cae8:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
 800caec:	d820      	bhi.n	800cb30 <HAL_RCCEx_PeriphCLKConfig+0xc34>
 800caee:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800caf2:	d012      	beq.n	800cb1a <HAL_RCCEx_PeriphCLKConfig+0xc1e>
 800caf4:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800caf8:	d81a      	bhi.n	800cb30 <HAL_RCCEx_PeriphCLKConfig+0xc34>
 800cafa:	2b00      	cmp	r3, #0
 800cafc:	d022      	beq.n	800cb44 <HAL_RCCEx_PeriphCLKConfig+0xc48>
 800cafe:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800cb02:	d115      	bne.n	800cb30 <HAL_RCCEx_PeriphCLKConfig+0xc34>
        /* LPTIM1 clock source configuration done later after clock selection check */
        break;

      case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800cb04:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cb08:	3308      	adds	r3, #8
 800cb0a:	2100      	movs	r1, #0
 800cb0c:	4618      	mov	r0, r3
 800cb0e:	f001 fd73 	bl	800e5f8 <RCCEx_PLL2_Config>
 800cb12:	4603      	mov	r3, r0
 800cb14:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* LPTIM1 clock source configuration done later after clock selection check */
        break;
 800cb18:	e015      	b.n	800cb46 <HAL_RCCEx_PeriphCLKConfig+0xc4a>

      case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 800cb1a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cb1e:	3328      	adds	r3, #40	@ 0x28
 800cb20:	2102      	movs	r1, #2
 800cb22:	4618      	mov	r0, r3
 800cb24:	f001 fe1a 	bl	800e75c <RCCEx_PLL3_Config>
 800cb28:	4603      	mov	r3, r0
 800cb2a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* LPTIM1 clock source configuration done later after clock selection check */
        break;
 800cb2e:	e00a      	b.n	800cb46 <HAL_RCCEx_PeriphCLKConfig+0xc4a>
        /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
        /* LPTIM1 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800cb30:	2301      	movs	r3, #1
 800cb32:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800cb36:	e006      	b.n	800cb46 <HAL_RCCEx_PeriphCLKConfig+0xc4a>
        break;
 800cb38:	bf00      	nop
 800cb3a:	e004      	b.n	800cb46 <HAL_RCCEx_PeriphCLKConfig+0xc4a>
        break;
 800cb3c:	bf00      	nop
 800cb3e:	e002      	b.n	800cb46 <HAL_RCCEx_PeriphCLKConfig+0xc4a>
        break;
 800cb40:	bf00      	nop
 800cb42:	e000      	b.n	800cb46 <HAL_RCCEx_PeriphCLKConfig+0xc4a>
        break;
 800cb44:	bf00      	nop
    }

    if (ret == HAL_OK)
 800cb46:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800cb4a:	2b00      	cmp	r3, #0
 800cb4c:	d10b      	bne.n	800cb66 <HAL_RCCEx_PeriphCLKConfig+0xc6a>
    {
      /* Set the source of LPTIM1 clock*/
      __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
 800cb4e:	4b39      	ldr	r3, [pc, #228]	@ (800cc34 <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800cb50:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800cb52:	f023 41e0 	bic.w	r1, r3, #1879048192	@ 0x70000000
 800cb56:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cb5a:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800cb5e:	4a35      	ldr	r2, [pc, #212]	@ (800cc34 <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800cb60:	430b      	orrs	r3, r1
 800cb62:	6553      	str	r3, [r2, #84]	@ 0x54
 800cb64:	e003      	b.n	800cb6e <HAL_RCCEx_PeriphCLKConfig+0xc72>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800cb66:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800cb6a:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- LPTIM2 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
 800cb6e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cb72:	e9d3 2300 	ldrd	r2, r3, [r3]
 800cb76:	f002 0340 	and.w	r3, r2, #64	@ 0x40
 800cb7a:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
 800cb7e:	2300      	movs	r3, #0
 800cb80:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
 800cb84:	e9d7 1226 	ldrd	r1, r2, [r7, #152]	@ 0x98
 800cb88:	460b      	mov	r3, r1
 800cb8a:	4313      	orrs	r3, r2
 800cb8c:	d058      	beq.n	800cc40 <HAL_RCCEx_PeriphCLKConfig+0xd44>
  {
    switch (PeriphClkInit->Lptim2ClockSelection)
 800cb8e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cb92:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
 800cb96:	f5b3 5fa0 	cmp.w	r3, #5120	@ 0x1400
 800cb9a:	d033      	beq.n	800cc04 <HAL_RCCEx_PeriphCLKConfig+0xd08>
 800cb9c:	f5b3 5fa0 	cmp.w	r3, #5120	@ 0x1400
 800cba0:	d82c      	bhi.n	800cbfc <HAL_RCCEx_PeriphCLKConfig+0xd00>
 800cba2:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800cba6:	d02f      	beq.n	800cc08 <HAL_RCCEx_PeriphCLKConfig+0xd0c>
 800cba8:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800cbac:	d826      	bhi.n	800cbfc <HAL_RCCEx_PeriphCLKConfig+0xd00>
 800cbae:	f5b3 6f40 	cmp.w	r3, #3072	@ 0xc00
 800cbb2:	d02b      	beq.n	800cc0c <HAL_RCCEx_PeriphCLKConfig+0xd10>
 800cbb4:	f5b3 6f40 	cmp.w	r3, #3072	@ 0xc00
 800cbb8:	d820      	bhi.n	800cbfc <HAL_RCCEx_PeriphCLKConfig+0xd00>
 800cbba:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 800cbbe:	d012      	beq.n	800cbe6 <HAL_RCCEx_PeriphCLKConfig+0xcea>
 800cbc0:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 800cbc4:	d81a      	bhi.n	800cbfc <HAL_RCCEx_PeriphCLKConfig+0xd00>
 800cbc6:	2b00      	cmp	r3, #0
 800cbc8:	d022      	beq.n	800cc10 <HAL_RCCEx_PeriphCLKConfig+0xd14>
 800cbca:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 800cbce:	d115      	bne.n	800cbfc <HAL_RCCEx_PeriphCLKConfig+0xd00>
        /* LPTIM2 clock source configuration done later after clock selection check */
        break;

      case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800cbd0:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cbd4:	3308      	adds	r3, #8
 800cbd6:	2100      	movs	r1, #0
 800cbd8:	4618      	mov	r0, r3
 800cbda:	f001 fd0d 	bl	800e5f8 <RCCEx_PLL2_Config>
 800cbde:	4603      	mov	r3, r0
 800cbe0:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* LPTIM2 clock source configuration done later after clock selection check */
        break;
 800cbe4:	e015      	b.n	800cc12 <HAL_RCCEx_PeriphCLKConfig+0xd16>

      case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 800cbe6:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cbea:	3328      	adds	r3, #40	@ 0x28
 800cbec:	2102      	movs	r1, #2
 800cbee:	4618      	mov	r0, r3
 800cbf0:	f001 fdb4 	bl	800e75c <RCCEx_PLL3_Config>
 800cbf4:	4603      	mov	r3, r0
 800cbf6:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* LPTIM2 clock source configuration done later after clock selection check */
        break;
 800cbfa:	e00a      	b.n	800cc12 <HAL_RCCEx_PeriphCLKConfig+0xd16>
        /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
        /* LPTIM2 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800cbfc:	2301      	movs	r3, #1
 800cbfe:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800cc02:	e006      	b.n	800cc12 <HAL_RCCEx_PeriphCLKConfig+0xd16>
        break;
 800cc04:	bf00      	nop
 800cc06:	e004      	b.n	800cc12 <HAL_RCCEx_PeriphCLKConfig+0xd16>
        break;
 800cc08:	bf00      	nop
 800cc0a:	e002      	b.n	800cc12 <HAL_RCCEx_PeriphCLKConfig+0xd16>
        break;
 800cc0c:	bf00      	nop
 800cc0e:	e000      	b.n	800cc12 <HAL_RCCEx_PeriphCLKConfig+0xd16>
        break;
 800cc10:	bf00      	nop
    }

    if (ret == HAL_OK)
 800cc12:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800cc16:	2b00      	cmp	r3, #0
 800cc18:	d10e      	bne.n	800cc38 <HAL_RCCEx_PeriphCLKConfig+0xd3c>
    {
      /* Set the source of LPTIM2 clock*/
      __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
 800cc1a:	4b06      	ldr	r3, [pc, #24]	@ (800cc34 <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800cc1c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800cc1e:	f423 51e0 	bic.w	r1, r3, #7168	@ 0x1c00
 800cc22:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cc26:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
 800cc2a:	4a02      	ldr	r2, [pc, #8]	@ (800cc34 <HAL_RCCEx_PeriphCLKConfig+0xd38>)
 800cc2c:	430b      	orrs	r3, r1
 800cc2e:	6593      	str	r3, [r2, #88]	@ 0x58
 800cc30:	e006      	b.n	800cc40 <HAL_RCCEx_PeriphCLKConfig+0xd44>
 800cc32:	bf00      	nop
 800cc34:	58024400 	.word	0x58024400
    }
    else
    {
      /* set overall return value */
      status = ret;
 800cc38:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800cc3c:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*---------------------------- LPTIM345 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
 800cc40:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cc44:	e9d3 2300 	ldrd	r2, r3, [r3]
 800cc48:	f002 0380 	and.w	r3, r2, #128	@ 0x80
 800cc4c:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
 800cc50:	2300      	movs	r3, #0
 800cc52:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
 800cc56:	e9d7 1224 	ldrd	r1, r2, [r7, #144]	@ 0x90
 800cc5a:	460b      	mov	r3, r1
 800cc5c:	4313      	orrs	r3, r2
 800cc5e:	d055      	beq.n	800cd0c <HAL_RCCEx_PeriphCLKConfig+0xe10>
  {
    switch (PeriphClkInit->Lptim345ClockSelection)
 800cc60:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cc64:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 800cc68:	f5b3 4f20 	cmp.w	r3, #40960	@ 0xa000
 800cc6c:	d033      	beq.n	800ccd6 <HAL_RCCEx_PeriphCLKConfig+0xdda>
 800cc6e:	f5b3 4f20 	cmp.w	r3, #40960	@ 0xa000
 800cc72:	d82c      	bhi.n	800ccce <HAL_RCCEx_PeriphCLKConfig+0xdd2>
 800cc74:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
 800cc78:	d02f      	beq.n	800ccda <HAL_RCCEx_PeriphCLKConfig+0xdde>
 800cc7a:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
 800cc7e:	d826      	bhi.n	800ccce <HAL_RCCEx_PeriphCLKConfig+0xdd2>
 800cc80:	f5b3 4fc0 	cmp.w	r3, #24576	@ 0x6000
 800cc84:	d02b      	beq.n	800ccde <HAL_RCCEx_PeriphCLKConfig+0xde2>
 800cc86:	f5b3 4fc0 	cmp.w	r3, #24576	@ 0x6000
 800cc8a:	d820      	bhi.n	800ccce <HAL_RCCEx_PeriphCLKConfig+0xdd2>
 800cc8c:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 800cc90:	d012      	beq.n	800ccb8 <HAL_RCCEx_PeriphCLKConfig+0xdbc>
 800cc92:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 800cc96:	d81a      	bhi.n	800ccce <HAL_RCCEx_PeriphCLKConfig+0xdd2>
 800cc98:	2b00      	cmp	r3, #0
 800cc9a:	d022      	beq.n	800cce2 <HAL_RCCEx_PeriphCLKConfig+0xde6>
 800cc9c:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800cca0:	d115      	bne.n	800ccce <HAL_RCCEx_PeriphCLKConfig+0xdd2>
      case RCC_LPTIM345CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
        break;

      case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800cca2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cca6:	3308      	adds	r3, #8
 800cca8:	2100      	movs	r1, #0
 800ccaa:	4618      	mov	r0, r3
 800ccac:	f001 fca4 	bl	800e5f8 <RCCEx_PLL2_Config>
 800ccb0:	4603      	mov	r3, r0
 800ccb2:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
        break;
 800ccb6:	e015      	b.n	800cce4 <HAL_RCCEx_PeriphCLKConfig+0xde8>

      case RCC_LPTIM345CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3/4/5 */
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 800ccb8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800ccbc:	3328      	adds	r3, #40	@ 0x28
 800ccbe:	2102      	movs	r1, #2
 800ccc0:	4618      	mov	r0, r3
 800ccc2:	f001 fd4b 	bl	800e75c <RCCEx_PLL3_Config>
 800ccc6:	4603      	mov	r3, r0
 800ccc8:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
        break;
 800cccc:	e00a      	b.n	800cce4 <HAL_RCCEx_PeriphCLKConfig+0xde8>
        /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800ccce:	2301      	movs	r3, #1
 800ccd0:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800ccd4:	e006      	b.n	800cce4 <HAL_RCCEx_PeriphCLKConfig+0xde8>
        break;
 800ccd6:	bf00      	nop
 800ccd8:	e004      	b.n	800cce4 <HAL_RCCEx_PeriphCLKConfig+0xde8>
        break;
 800ccda:	bf00      	nop
 800ccdc:	e002      	b.n	800cce4 <HAL_RCCEx_PeriphCLKConfig+0xde8>
        break;
 800ccde:	bf00      	nop
 800cce0:	e000      	b.n	800cce4 <HAL_RCCEx_PeriphCLKConfig+0xde8>
        break;
 800cce2:	bf00      	nop
    }

    if (ret == HAL_OK)
 800cce4:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800cce8:	2b00      	cmp	r3, #0
 800ccea:	d10b      	bne.n	800cd04 <HAL_RCCEx_PeriphCLKConfig+0xe08>
    {
      /* Set the source of LPTIM3/4/5 clock */
      __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
 800ccec:	4bbb      	ldr	r3, [pc, #748]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800ccee:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800ccf0:	f423 4160 	bic.w	r1, r3, #57344	@ 0xe000
 800ccf4:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800ccf8:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 800ccfc:	4ab7      	ldr	r2, [pc, #732]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800ccfe:	430b      	orrs	r3, r1
 800cd00:	6593      	str	r3, [r2, #88]	@ 0x58
 800cd02:	e003      	b.n	800cd0c <HAL_RCCEx_PeriphCLKConfig+0xe10>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800cd04:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800cd08:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e

    __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection);

  }
#else
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
 800cd0c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cd10:	e9d3 2300 	ldrd	r2, r3, [r3]
 800cd14:	f002 0308 	and.w	r3, r2, #8
 800cd18:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
 800cd1c:	2300      	movs	r3, #0
 800cd1e:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
 800cd22:	e9d7 1222 	ldrd	r1, r2, [r7, #136]	@ 0x88
 800cd26:	460b      	mov	r3, r1
 800cd28:	4313      	orrs	r3, r2
 800cd2a:	d01e      	beq.n	800cd6a <HAL_RCCEx_PeriphCLKConfig+0xe6e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));

    if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3)
 800cd2c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cd30:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 800cd34:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800cd38:	d10c      	bne.n	800cd54 <HAL_RCCEx_PeriphCLKConfig+0xe58>
    {
      if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
 800cd3a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cd3e:	3328      	adds	r3, #40	@ 0x28
 800cd40:	2102      	movs	r1, #2
 800cd42:	4618      	mov	r0, r3
 800cd44:	f001 fd0a 	bl	800e75c <RCCEx_PLL3_Config>
 800cd48:	4603      	mov	r3, r0
 800cd4a:	2b00      	cmp	r3, #0
 800cd4c:	d002      	beq.n	800cd54 <HAL_RCCEx_PeriphCLKConfig+0xe58>
      {
        status = HAL_ERROR;
 800cd4e:	2301      	movs	r3, #1
 800cd50:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
      }
    }

    __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
 800cd54:	4ba1      	ldr	r3, [pc, #644]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cd56:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800cd58:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
 800cd5c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cd60:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
 800cd64:	4a9d      	ldr	r2, [pc, #628]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cd66:	430b      	orrs	r3, r1
 800cd68:	6553      	str	r3, [r2, #84]	@ 0x54

  }
#endif /* I2C5 */

  /*------------------------------ I2C4 Configuration ------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
 800cd6a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cd6e:	e9d3 2300 	ldrd	r2, r3, [r3]
 800cd72:	f002 0310 	and.w	r3, r2, #16
 800cd76:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
 800cd7a:	2300      	movs	r3, #0
 800cd7c:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
 800cd80:	e9d7 1220 	ldrd	r1, r2, [r7, #128]	@ 0x80
 800cd84:	460b      	mov	r3, r1
 800cd86:	4313      	orrs	r3, r2
 800cd88:	d01e      	beq.n	800cdc8 <HAL_RCCEx_PeriphCLKConfig+0xecc>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));

    if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3)
 800cd8a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cd8e:	f8d3 3098 	ldr.w	r3, [r3, #152]	@ 0x98
 800cd92:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800cd96:	d10c      	bne.n	800cdb2 <HAL_RCCEx_PeriphCLKConfig+0xeb6>
    {
      if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
 800cd98:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cd9c:	3328      	adds	r3, #40	@ 0x28
 800cd9e:	2102      	movs	r1, #2
 800cda0:	4618      	mov	r0, r3
 800cda2:	f001 fcdb 	bl	800e75c <RCCEx_PLL3_Config>
 800cda6:	4603      	mov	r3, r0
 800cda8:	2b00      	cmp	r3, #0
 800cdaa:	d002      	beq.n	800cdb2 <HAL_RCCEx_PeriphCLKConfig+0xeb6>
      {
        status = HAL_ERROR;
 800cdac:	2301      	movs	r3, #1
 800cdae:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
      }
    }

    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
 800cdb2:	4b8a      	ldr	r3, [pc, #552]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cdb4:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800cdb6:	f423 7140 	bic.w	r1, r3, #768	@ 0x300
 800cdba:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cdbe:	f8d3 3098 	ldr.w	r3, [r3, #152]	@ 0x98
 800cdc2:	4a86      	ldr	r2, [pc, #536]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cdc4:	430b      	orrs	r3, r1
 800cdc6:	6593      	str	r3, [r2, #88]	@ 0x58

  }

  /*---------------------------- ADC configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 800cdc8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cdcc:	e9d3 2300 	ldrd	r2, r3, [r3]
 800cdd0:	f402 2300 	and.w	r3, r2, #524288	@ 0x80000
 800cdd4:	67bb      	str	r3, [r7, #120]	@ 0x78
 800cdd6:	2300      	movs	r3, #0
 800cdd8:	67fb      	str	r3, [r7, #124]	@ 0x7c
 800cdda:	e9d7 121e 	ldrd	r1, r2, [r7, #120]	@ 0x78
 800cdde:	460b      	mov	r3, r1
 800cde0:	4313      	orrs	r3, r2
 800cde2:	d03e      	beq.n	800ce62 <HAL_RCCEx_PeriphCLKConfig+0xf66>
  {
    switch (PeriphClkInit->AdcClockSelection)
 800cde4:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cde8:	f8d3 30a4 	ldr.w	r3, [r3, #164]	@ 0xa4
 800cdec:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800cdf0:	d022      	beq.n	800ce38 <HAL_RCCEx_PeriphCLKConfig+0xf3c>
 800cdf2:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800cdf6:	d81b      	bhi.n	800ce30 <HAL_RCCEx_PeriphCLKConfig+0xf34>
 800cdf8:	2b00      	cmp	r3, #0
 800cdfa:	d003      	beq.n	800ce04 <HAL_RCCEx_PeriphCLKConfig+0xf08>
 800cdfc:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800ce00:	d00b      	beq.n	800ce1a <HAL_RCCEx_PeriphCLKConfig+0xf1e>
 800ce02:	e015      	b.n	800ce30 <HAL_RCCEx_PeriphCLKConfig+0xf34>
    {

      case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800ce04:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800ce08:	3308      	adds	r3, #8
 800ce0a:	2100      	movs	r1, #0
 800ce0c:	4618      	mov	r0, r3
 800ce0e:	f001 fbf3 	bl	800e5f8 <RCCEx_PLL2_Config>
 800ce12:	4603      	mov	r3, r0
 800ce14:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* ADC clock source configuration done later after clock selection check */
        break;
 800ce18:	e00f      	b.n	800ce3a <HAL_RCCEx_PeriphCLKConfig+0xf3e>

      case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 800ce1a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800ce1e:	3328      	adds	r3, #40	@ 0x28
 800ce20:	2102      	movs	r1, #2
 800ce22:	4618      	mov	r0, r3
 800ce24:	f001 fc9a 	bl	800e75c <RCCEx_PLL3_Config>
 800ce28:	4603      	mov	r3, r0
 800ce2a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* ADC clock source configuration done later after clock selection check */
        break;
 800ce2e:	e004      	b.n	800ce3a <HAL_RCCEx_PeriphCLKConfig+0xf3e>
        /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
        /* ADC clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800ce30:	2301      	movs	r3, #1
 800ce32:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800ce36:	e000      	b.n	800ce3a <HAL_RCCEx_PeriphCLKConfig+0xf3e>
        break;
 800ce38:	bf00      	nop
    }

    if (ret == HAL_OK)
 800ce3a:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800ce3e:	2b00      	cmp	r3, #0
 800ce40:	d10b      	bne.n	800ce5a <HAL_RCCEx_PeriphCLKConfig+0xf5e>
    {
      /* Set the source of ADC clock*/
      __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 800ce42:	4b66      	ldr	r3, [pc, #408]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800ce44:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800ce46:	f423 3140 	bic.w	r1, r3, #196608	@ 0x30000
 800ce4a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800ce4e:	f8d3 30a4 	ldr.w	r3, [r3, #164]	@ 0xa4
 800ce52:	4a62      	ldr	r2, [pc, #392]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800ce54:	430b      	orrs	r3, r1
 800ce56:	6593      	str	r3, [r2, #88]	@ 0x58
 800ce58:	e003      	b.n	800ce62 <HAL_RCCEx_PeriphCLKConfig+0xf66>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800ce5a:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800ce5e:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }

  /*------------------------------ USB Configuration -------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
 800ce62:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800ce66:	e9d3 2300 	ldrd	r2, r3, [r3]
 800ce6a:	f402 2380 	and.w	r3, r2, #262144	@ 0x40000
 800ce6e:	673b      	str	r3, [r7, #112]	@ 0x70
 800ce70:	2300      	movs	r3, #0
 800ce72:	677b      	str	r3, [r7, #116]	@ 0x74
 800ce74:	e9d7 121c 	ldrd	r1, r2, [r7, #112]	@ 0x70
 800ce78:	460b      	mov	r3, r1
 800ce7a:	4313      	orrs	r3, r2
 800ce7c:	d03b      	beq.n	800cef6 <HAL_RCCEx_PeriphCLKConfig+0xffa>
  {

    switch (PeriphClkInit->UsbClockSelection)
 800ce7e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800ce82:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800ce86:	f5b3 1f40 	cmp.w	r3, #3145728	@ 0x300000
 800ce8a:	d01f      	beq.n	800cecc <HAL_RCCEx_PeriphCLKConfig+0xfd0>
 800ce8c:	f5b3 1f40 	cmp.w	r3, #3145728	@ 0x300000
 800ce90:	d818      	bhi.n	800cec4 <HAL_RCCEx_PeriphCLKConfig+0xfc8>
 800ce92:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 800ce96:	d003      	beq.n	800cea0 <HAL_RCCEx_PeriphCLKConfig+0xfa4>
 800ce98:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 800ce9c:	d007      	beq.n	800ceae <HAL_RCCEx_PeriphCLKConfig+0xfb2>
 800ce9e:	e011      	b.n	800cec4 <HAL_RCCEx_PeriphCLKConfig+0xfc8>
    {
      case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
        /* Enable USB Clock output generated form System USB . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800cea0:	4b4e      	ldr	r3, [pc, #312]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cea2:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800cea4:	4a4d      	ldr	r2, [pc, #308]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cea6:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800ceaa:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* USB clock source configuration done later after clock selection check */
        break;
 800ceac:	e00f      	b.n	800cece <HAL_RCCEx_PeriphCLKConfig+0xfd2>

      case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/

        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 800ceae:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800ceb2:	3328      	adds	r3, #40	@ 0x28
 800ceb4:	2101      	movs	r1, #1
 800ceb6:	4618      	mov	r0, r3
 800ceb8:	f001 fc50 	bl	800e75c <RCCEx_PLL3_Config>
 800cebc:	4603      	mov	r3, r0
 800cebe:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* USB clock source configuration done later after clock selection check */
        break;
 800cec2:	e004      	b.n	800cece <HAL_RCCEx_PeriphCLKConfig+0xfd2>
        /* HSI48 oscillator is used as source of USB clock */
        /* USB clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800cec4:	2301      	movs	r3, #1
 800cec6:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800ceca:	e000      	b.n	800cece <HAL_RCCEx_PeriphCLKConfig+0xfd2>
        break;
 800cecc:	bf00      	nop
    }

    if (ret == HAL_OK)
 800cece:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800ced2:	2b00      	cmp	r3, #0
 800ced4:	d10b      	bne.n	800ceee <HAL_RCCEx_PeriphCLKConfig+0xff2>
    {
      /* Set the source of USB clock*/
      __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 800ced6:	4b41      	ldr	r3, [pc, #260]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800ced8:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800ceda:	f423 1140 	bic.w	r1, r3, #3145728	@ 0x300000
 800cede:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cee2:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800cee6:	4a3d      	ldr	r2, [pc, #244]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cee8:	430b      	orrs	r3, r1
 800ceea:	6553      	str	r3, [r2, #84]	@ 0x54
 800ceec:	e003      	b.n	800cef6 <HAL_RCCEx_PeriphCLKConfig+0xffa>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800ceee:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800cef2:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }

  }

  /*------------------------------------- SDMMC Configuration ------------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
 800cef6:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cefa:	e9d3 2300 	ldrd	r2, r3, [r3]
 800cefe:	f402 3380 	and.w	r3, r2, #65536	@ 0x10000
 800cf02:	66bb      	str	r3, [r7, #104]	@ 0x68
 800cf04:	2300      	movs	r3, #0
 800cf06:	66fb      	str	r3, [r7, #108]	@ 0x6c
 800cf08:	e9d7 121a 	ldrd	r1, r2, [r7, #104]	@ 0x68
 800cf0c:	460b      	mov	r3, r1
 800cf0e:	4313      	orrs	r3, r2
 800cf10:	d031      	beq.n	800cf76 <HAL_RCCEx_PeriphCLKConfig+0x107a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));

    switch (PeriphClkInit->SdmmcClockSelection)
 800cf12:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cf16:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800cf18:	2b00      	cmp	r3, #0
 800cf1a:	d003      	beq.n	800cf24 <HAL_RCCEx_PeriphCLKConfig+0x1028>
 800cf1c:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800cf20:	d007      	beq.n	800cf32 <HAL_RCCEx_PeriphCLKConfig+0x1036>
 800cf22:	e011      	b.n	800cf48 <HAL_RCCEx_PeriphCLKConfig+0x104c>
    {
      case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
        /* Enable SDMMC Clock output generated form System PLL . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800cf24:	4b2d      	ldr	r3, [pc, #180]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cf26:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800cf28:	4a2c      	ldr	r2, [pc, #176]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cf2a:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800cf2e:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* SDMMC clock source configuration done later after clock selection check */
        break;
 800cf30:	e00e      	b.n	800cf50 <HAL_RCCEx_PeriphCLKConfig+0x1054>

      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/

        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 800cf32:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cf36:	3308      	adds	r3, #8
 800cf38:	2102      	movs	r1, #2
 800cf3a:	4618      	mov	r0, r3
 800cf3c:	f001 fb5c 	bl	800e5f8 <RCCEx_PLL2_Config>
 800cf40:	4603      	mov	r3, r0
 800cf42:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f

        /* SDMMC clock source configuration done later after clock selection check */
        break;
 800cf46:	e003      	b.n	800cf50 <HAL_RCCEx_PeriphCLKConfig+0x1054>

      default:
        ret = HAL_ERROR;
 800cf48:	2301      	movs	r3, #1
 800cf4a:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800cf4e:	bf00      	nop
    }

    if (ret == HAL_OK)
 800cf50:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800cf54:	2b00      	cmp	r3, #0
 800cf56:	d10a      	bne.n	800cf6e <HAL_RCCEx_PeriphCLKConfig+0x1072>
    {
      /* Set the source of SDMMC clock*/
      __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
 800cf58:	4b20      	ldr	r3, [pc, #128]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cf5a:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800cf5c:	f423 3180 	bic.w	r1, r3, #65536	@ 0x10000
 800cf60:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cf64:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800cf66:	4a1d      	ldr	r2, [pc, #116]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cf68:	430b      	orrs	r3, r1
 800cf6a:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800cf6c:	e003      	b.n	800cf76 <HAL_RCCEx_PeriphCLKConfig+0x107a>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800cf6e:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800cf72:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
#endif /* LTDC */

  /*------------------------------ RNG Configuration -------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
 800cf76:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cf7a:	e9d3 2300 	ldrd	r2, r3, [r3]
 800cf7e:	f402 3300 	and.w	r3, r2, #131072	@ 0x20000
 800cf82:	663b      	str	r3, [r7, #96]	@ 0x60
 800cf84:	2300      	movs	r3, #0
 800cf86:	667b      	str	r3, [r7, #100]	@ 0x64
 800cf88:	e9d7 1218 	ldrd	r1, r2, [r7, #96]	@ 0x60
 800cf8c:	460b      	mov	r3, r1
 800cf8e:	4313      	orrs	r3, r2
 800cf90:	d03b      	beq.n	800d00a <HAL_RCCEx_PeriphCLKConfig+0x110e>
  {

    switch (PeriphClkInit->RngClockSelection)
 800cf92:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cf96:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cf9a:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 800cf9e:	d018      	beq.n	800cfd2 <HAL_RCCEx_PeriphCLKConfig+0x10d6>
 800cfa0:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 800cfa4:	d811      	bhi.n	800cfca <HAL_RCCEx_PeriphCLKConfig+0x10ce>
 800cfa6:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 800cfaa:	d014      	beq.n	800cfd6 <HAL_RCCEx_PeriphCLKConfig+0x10da>
 800cfac:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 800cfb0:	d80b      	bhi.n	800cfca <HAL_RCCEx_PeriphCLKConfig+0x10ce>
 800cfb2:	2b00      	cmp	r3, #0
 800cfb4:	d014      	beq.n	800cfe0 <HAL_RCCEx_PeriphCLKConfig+0x10e4>
 800cfb6:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800cfba:	d106      	bne.n	800cfca <HAL_RCCEx_PeriphCLKConfig+0x10ce>
    {
      case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
        /* Enable RNG Clock output generated form System RNG . */
        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 800cfbc:	4b07      	ldr	r3, [pc, #28]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cfbe:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800cfc0:	4a06      	ldr	r2, [pc, #24]	@ (800cfdc <HAL_RCCEx_PeriphCLKConfig+0x10e0>)
 800cfc2:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 800cfc6:	62d3      	str	r3, [r2, #44]	@ 0x2c

        /* RNG clock source configuration done later after clock selection check */
        break;
 800cfc8:	e00b      	b.n	800cfe2 <HAL_RCCEx_PeriphCLKConfig+0x10e6>
        /* HSI48 oscillator is used as source of RNG clock */
        /* RNG clock source configuration done later after clock selection check */
        break;

      default:
        ret = HAL_ERROR;
 800cfca:	2301      	movs	r3, #1
 800cfcc:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
        break;
 800cfd0:	e007      	b.n	800cfe2 <HAL_RCCEx_PeriphCLKConfig+0x10e6>
        break;
 800cfd2:	bf00      	nop
 800cfd4:	e005      	b.n	800cfe2 <HAL_RCCEx_PeriphCLKConfig+0x10e6>
        break;
 800cfd6:	bf00      	nop
 800cfd8:	e003      	b.n	800cfe2 <HAL_RCCEx_PeriphCLKConfig+0x10e6>
 800cfda:	bf00      	nop
 800cfdc:	58024400 	.word	0x58024400
        break;
 800cfe0:	bf00      	nop
    }

    if (ret == HAL_OK)
 800cfe2:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800cfe6:	2b00      	cmp	r3, #0
 800cfe8:	d10b      	bne.n	800d002 <HAL_RCCEx_PeriphCLKConfig+0x1106>
    {
      /* Set the source of RNG clock*/
      __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
 800cfea:	4bba      	ldr	r3, [pc, #744]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800cfec:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800cfee:	f423 7140 	bic.w	r1, r3, #768	@ 0x300
 800cff2:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800cff6:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 800cffa:	4ab6      	ldr	r2, [pc, #728]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800cffc:	430b      	orrs	r3, r1
 800cffe:	6553      	str	r3, [r2, #84]	@ 0x54
 800d000:	e003      	b.n	800d00a <HAL_RCCEx_PeriphCLKConfig+0x110e>
    }
    else
    {
      /* set overall return value */
      status = ret;
 800d002:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d006:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }

  }

  /*------------------------------ SWPMI1 Configuration ------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
 800d00a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d00e:	e9d3 2300 	ldrd	r2, r3, [r3]
 800d012:	f402 1380 	and.w	r3, r2, #1048576	@ 0x100000
 800d016:	65bb      	str	r3, [r7, #88]	@ 0x58
 800d018:	2300      	movs	r3, #0
 800d01a:	65fb      	str	r3, [r7, #92]	@ 0x5c
 800d01c:	e9d7 1216 	ldrd	r1, r2, [r7, #88]	@ 0x58
 800d020:	460b      	mov	r3, r1
 800d022:	4313      	orrs	r3, r2
 800d024:	d009      	beq.n	800d03a <HAL_RCCEx_PeriphCLKConfig+0x113e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));

    /* Configure the SWPMI1 interface clock source */
    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
 800d026:	4bab      	ldr	r3, [pc, #684]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d028:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800d02a:	f023 4100 	bic.w	r1, r3, #2147483648	@ 0x80000000
 800d02e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d032:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 800d034:	4aa7      	ldr	r2, [pc, #668]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d036:	430b      	orrs	r3, r1
 800d038:	6513      	str	r3, [r2, #80]	@ 0x50
  }
#if defined(HRTIM1)
  /*------------------------------ HRTIM1 clock Configuration ----------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
 800d03a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d03e:	e9d3 2300 	ldrd	r2, r3, [r3]
 800d042:	f002 5380 	and.w	r3, r2, #268435456	@ 0x10000000
 800d046:	653b      	str	r3, [r7, #80]	@ 0x50
 800d048:	2300      	movs	r3, #0
 800d04a:	657b      	str	r3, [r7, #84]	@ 0x54
 800d04c:	e9d7 1214 	ldrd	r1, r2, [r7, #80]	@ 0x50
 800d050:	460b      	mov	r3, r1
 800d052:	4313      	orrs	r3, r2
 800d054:	d00a      	beq.n	800d06c <HAL_RCCEx_PeriphCLKConfig+0x1170>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));

    /* Configure the HRTIM1 clock source */
    __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
 800d056:	4b9f      	ldr	r3, [pc, #636]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d058:	691b      	ldr	r3, [r3, #16]
 800d05a:	f423 4180 	bic.w	r1, r3, #16384	@ 0x4000
 800d05e:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d062:	f8d3 30b8 	ldr.w	r3, [r3, #184]	@ 0xb8
 800d066:	4a9b      	ldr	r2, [pc, #620]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d068:	430b      	orrs	r3, r1
 800d06a:	6113      	str	r3, [r2, #16]
  }
#endif  /*HRTIM1*/
  /*------------------------------ DFSDM1 Configuration ------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
 800d06c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d070:	e9d3 2300 	ldrd	r2, r3, [r3]
 800d074:	f402 1300 	and.w	r3, r2, #2097152	@ 0x200000
 800d078:	64bb      	str	r3, [r7, #72]	@ 0x48
 800d07a:	2300      	movs	r3, #0
 800d07c:	64fb      	str	r3, [r7, #76]	@ 0x4c
 800d07e:	e9d7 1212 	ldrd	r1, r2, [r7, #72]	@ 0x48
 800d082:	460b      	mov	r3, r1
 800d084:	4313      	orrs	r3, r2
 800d086:	d009      	beq.n	800d09c <HAL_RCCEx_PeriphCLKConfig+0x11a0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));

    /* Configure the DFSDM1 interface clock source */
    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
 800d088:	4b92      	ldr	r3, [pc, #584]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d08a:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800d08c:	f023 7180 	bic.w	r1, r3, #16777216	@ 0x1000000
 800d090:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d094:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800d096:	4a8f      	ldr	r2, [pc, #572]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d098:	430b      	orrs	r3, r1
 800d09a:	6513      	str	r3, [r2, #80]	@ 0x50
    __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
  }
#endif  /* DFSDM2 */

  /*------------------------------------ TIM configuration --------------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
 800d09c:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d0a0:	e9d3 2300 	ldrd	r2, r3, [r3]
 800d0a4:	f002 4380 	and.w	r3, r2, #1073741824	@ 0x40000000
 800d0a8:	643b      	str	r3, [r7, #64]	@ 0x40
 800d0aa:	2300      	movs	r3, #0
 800d0ac:	647b      	str	r3, [r7, #68]	@ 0x44
 800d0ae:	e9d7 1210 	ldrd	r1, r2, [r7, #64]	@ 0x40
 800d0b2:	460b      	mov	r3, r1
 800d0b4:	4313      	orrs	r3, r2
 800d0b6:	d00e      	beq.n	800d0d6 <HAL_RCCEx_PeriphCLKConfig+0x11da>
  {
    /* Check the parameters */
    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));

    /* Configure Timer Prescaler */
    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
 800d0b8:	4b86      	ldr	r3, [pc, #536]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d0ba:	691b      	ldr	r3, [r3, #16]
 800d0bc:	4a85      	ldr	r2, [pc, #532]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d0be:	f423 4300 	bic.w	r3, r3, #32768	@ 0x8000
 800d0c2:	6113      	str	r3, [r2, #16]
 800d0c4:	4b83      	ldr	r3, [pc, #524]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d0c6:	6919      	ldr	r1, [r3, #16]
 800d0c8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d0cc:	f8d3 30bc 	ldr.w	r3, [r3, #188]	@ 0xbc
 800d0d0:	4a80      	ldr	r2, [pc, #512]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d0d2:	430b      	orrs	r3, r1
 800d0d4:	6113      	str	r3, [r2, #16]
  }

  /*------------------------------------ CKPER configuration --------------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
 800d0d6:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d0da:	e9d3 2300 	ldrd	r2, r3, [r3]
 800d0de:	f002 4300 	and.w	r3, r2, #2147483648	@ 0x80000000
 800d0e2:	63bb      	str	r3, [r7, #56]	@ 0x38
 800d0e4:	2300      	movs	r3, #0
 800d0e6:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d0e8:	e9d7 120e 	ldrd	r1, r2, [r7, #56]	@ 0x38
 800d0ec:	460b      	mov	r3, r1
 800d0ee:	4313      	orrs	r3, r2
 800d0f0:	d009      	beq.n	800d106 <HAL_RCCEx_PeriphCLKConfig+0x120a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));

    /* Configure the CKPER clock source */
    __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
 800d0f2:	4b78      	ldr	r3, [pc, #480]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d0f4:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800d0f6:	f023 5140 	bic.w	r1, r3, #805306368	@ 0x30000000
 800d0fa:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d0fe:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800d100:	4a74      	ldr	r2, [pc, #464]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d102:	430b      	orrs	r3, r1
 800d104:	64d3      	str	r3, [r2, #76]	@ 0x4c
  }

  /*------------------------------ CEC Configuration ------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
 800d106:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d10a:	e9d3 2300 	ldrd	r2, r3, [r3]
 800d10e:	f402 0300 	and.w	r3, r2, #8388608	@ 0x800000
 800d112:	633b      	str	r3, [r7, #48]	@ 0x30
 800d114:	2300      	movs	r3, #0
 800d116:	637b      	str	r3, [r7, #52]	@ 0x34
 800d118:	e9d7 120c 	ldrd	r1, r2, [r7, #48]	@ 0x30
 800d11c:	460b      	mov	r3, r1
 800d11e:	4313      	orrs	r3, r2
 800d120:	d00a      	beq.n	800d138 <HAL_RCCEx_PeriphCLKConfig+0x123c>
  {
    /* Check the parameters */
    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));

    /* Configure the CEC interface clock source */
    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
 800d122:	4b6c      	ldr	r3, [pc, #432]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d124:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 800d126:	f423 0140 	bic.w	r1, r3, #12582912	@ 0xc00000
 800d12a:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d12e:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 800d132:	4a68      	ldr	r2, [pc, #416]	@ (800d2d4 <HAL_RCCEx_PeriphCLKConfig+0x13d8>)
 800d134:	430b      	orrs	r3, r1
 800d136:	6553      	str	r3, [r2, #84]	@ 0x54
  }

  /*---------------------------- PLL2 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP)
 800d138:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d13c:	e9d3 2300 	ldrd	r2, r3, [r3]
 800d140:	2100      	movs	r1, #0
 800d142:	62b9      	str	r1, [r7, #40]	@ 0x28
 800d144:	f003 0301 	and.w	r3, r3, #1
 800d148:	62fb      	str	r3, [r7, #44]	@ 0x2c
 800d14a:	e9d7 120a 	ldrd	r1, r2, [r7, #40]	@ 0x28
 800d14e:	460b      	mov	r3, r1
 800d150:	4313      	orrs	r3, r2
 800d152:	d011      	beq.n	800d178 <HAL_RCCEx_PeriphCLKConfig+0x127c>
  {
    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 800d154:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d158:	3308      	adds	r3, #8
 800d15a:	2100      	movs	r1, #0
 800d15c:	4618      	mov	r0, r3
 800d15e:	f001 fa4b 	bl	800e5f8 <RCCEx_PLL2_Config>
 800d162:	4603      	mov	r3, r0
 800d164:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
    
    if (ret == HAL_OK)
 800d168:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d16c:	2b00      	cmp	r3, #0
 800d16e:	d003      	beq.n	800d178 <HAL_RCCEx_PeriphCLKConfig+0x127c>
      /*Nothing to do*/
    }
    else
    {
      /* set overall return value */
      status = ret;
 800d170:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d174:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    } 
  }
  
  
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
 800d178:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d17c:	e9d3 2300 	ldrd	r2, r3, [r3]
 800d180:	2100      	movs	r1, #0
 800d182:	6239      	str	r1, [r7, #32]
 800d184:	f003 0302 	and.w	r3, r3, #2
 800d188:	627b      	str	r3, [r7, #36]	@ 0x24
 800d18a:	e9d7 1208 	ldrd	r1, r2, [r7, #32]
 800d18e:	460b      	mov	r3, r1
 800d190:	4313      	orrs	r3, r2
 800d192:	d011      	beq.n	800d1b8 <HAL_RCCEx_PeriphCLKConfig+0x12bc>
  {
    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 800d194:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d198:	3308      	adds	r3, #8
 800d19a:	2101      	movs	r1, #1
 800d19c:	4618      	mov	r0, r3
 800d19e:	f001 fa2b 	bl	800e5f8 <RCCEx_PLL2_Config>
 800d1a2:	4603      	mov	r3, r0
 800d1a4:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
    
    if (ret == HAL_OK)
 800d1a8:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d1ac:	2b00      	cmp	r3, #0
 800d1ae:	d003      	beq.n	800d1b8 <HAL_RCCEx_PeriphCLKConfig+0x12bc>
      /*Nothing to do*/
    }
    else
    {
      /* set overall return value */
      status = ret;
 800d1b0:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d1b4:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
  
  
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
 800d1b8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d1bc:	e9d3 2300 	ldrd	r2, r3, [r3]
 800d1c0:	2100      	movs	r1, #0
 800d1c2:	61b9      	str	r1, [r7, #24]
 800d1c4:	f003 0304 	and.w	r3, r3, #4
 800d1c8:	61fb      	str	r3, [r7, #28]
 800d1ca:	e9d7 1206 	ldrd	r1, r2, [r7, #24]
 800d1ce:	460b      	mov	r3, r1
 800d1d0:	4313      	orrs	r3, r2
 800d1d2:	d011      	beq.n	800d1f8 <HAL_RCCEx_PeriphCLKConfig+0x12fc>
  {
    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 800d1d4:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d1d8:	3308      	adds	r3, #8
 800d1da:	2102      	movs	r1, #2
 800d1dc:	4618      	mov	r0, r3
 800d1de:	f001 fa0b 	bl	800e5f8 <RCCEx_PLL2_Config>
 800d1e2:	4603      	mov	r3, r0
 800d1e4:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
    
    if (ret == HAL_OK)
 800d1e8:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d1ec:	2b00      	cmp	r3, #0
 800d1ee:	d003      	beq.n	800d1f8 <HAL_RCCEx_PeriphCLKConfig+0x12fc>
      /*Nothing to do*/
    }
    else
    {
      /* set overall return value */
      status = ret;
 800d1f0:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d1f4:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
  

  /*---------------------------- PLL3 configuration -------------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
 800d1f8:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d1fc:	e9d3 2300 	ldrd	r2, r3, [r3]
 800d200:	2100      	movs	r1, #0
 800d202:	6139      	str	r1, [r7, #16]
 800d204:	f003 0308 	and.w	r3, r3, #8
 800d208:	617b      	str	r3, [r7, #20]
 800d20a:	e9d7 1204 	ldrd	r1, r2, [r7, #16]
 800d20e:	460b      	mov	r3, r1
 800d210:	4313      	orrs	r3, r2
 800d212:	d011      	beq.n	800d238 <HAL_RCCEx_PeriphCLKConfig+0x133c>
  {
    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 800d214:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d218:	3328      	adds	r3, #40	@ 0x28
 800d21a:	2100      	movs	r1, #0
 800d21c:	4618      	mov	r0, r3
 800d21e:	f001 fa9d 	bl	800e75c <RCCEx_PLL3_Config>
 800d222:	4603      	mov	r3, r0
 800d224:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
  
    if (ret == HAL_OK)
 800d228:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d22c:	2b00      	cmp	r3, #0
 800d22e:	d003      	beq.n	800d238 <HAL_RCCEx_PeriphCLKConfig+0x133c>
      /*Nothing to do*/
    }
    else
    {
      /* set overall return value */
      status = ret;
 800d230:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d234:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
  
  
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
 800d238:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d23c:	e9d3 2300 	ldrd	r2, r3, [r3]
 800d240:	2100      	movs	r1, #0
 800d242:	60b9      	str	r1, [r7, #8]
 800d244:	f003 0310 	and.w	r3, r3, #16
 800d248:	60fb      	str	r3, [r7, #12]
 800d24a:	e9d7 1202 	ldrd	r1, r2, [r7, #8]
 800d24e:	460b      	mov	r3, r1
 800d250:	4313      	orrs	r3, r2
 800d252:	d011      	beq.n	800d278 <HAL_RCCEx_PeriphCLKConfig+0x137c>
  {
    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 800d254:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d258:	3328      	adds	r3, #40	@ 0x28
 800d25a:	2101      	movs	r1, #1
 800d25c:	4618      	mov	r0, r3
 800d25e:	f001 fa7d 	bl	800e75c <RCCEx_PLL3_Config>
 800d262:	4603      	mov	r3, r0
 800d264:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
    
    if (ret == HAL_OK)
 800d268:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d26c:	2b00      	cmp	r3, #0
 800d26e:	d003      	beq.n	800d278 <HAL_RCCEx_PeriphCLKConfig+0x137c>
      /*Nothing to do*/
    }
    else
    {
      /* set overall return value */
      status = ret;
 800d270:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d274:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    }
  }
  
  
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
 800d278:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d27c:	e9d3 2300 	ldrd	r2, r3, [r3]
 800d280:	2100      	movs	r1, #0
 800d282:	6039      	str	r1, [r7, #0]
 800d284:	f003 0320 	and.w	r3, r3, #32
 800d288:	607b      	str	r3, [r7, #4]
 800d28a:	e9d7 1200 	ldrd	r1, r2, [r7]
 800d28e:	460b      	mov	r3, r1
 800d290:	4313      	orrs	r3, r2
 800d292:	d011      	beq.n	800d2b8 <HAL_RCCEx_PeriphCLKConfig+0x13bc>
  {
    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 800d294:	f8d7 310c 	ldr.w	r3, [r7, #268]	@ 0x10c
 800d298:	3328      	adds	r3, #40	@ 0x28
 800d29a:	2102      	movs	r1, #2
 800d29c:	4618      	mov	r0, r3
 800d29e:	f001 fa5d 	bl	800e75c <RCCEx_PLL3_Config>
 800d2a2:	4603      	mov	r3, r0
 800d2a4:	f887 311f 	strb.w	r3, [r7, #287]	@ 0x11f
    
    if (ret == HAL_OK)
 800d2a8:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d2ac:	2b00      	cmp	r3, #0
 800d2ae:	d003      	beq.n	800d2b8 <HAL_RCCEx_PeriphCLKConfig+0x13bc>
      /*Nothing to do*/
    }
    else
    {
      /* set overall return value */
      status = ret;
 800d2b0:	f897 311f 	ldrb.w	r3, [r7, #287]	@ 0x11f
 800d2b4:	f887 311e 	strb.w	r3, [r7, #286]	@ 0x11e
    } 
  }

  if (status == HAL_OK)
 800d2b8:	f897 311e 	ldrb.w	r3, [r7, #286]	@ 0x11e
 800d2bc:	2b00      	cmp	r3, #0
 800d2be:	d101      	bne.n	800d2c4 <HAL_RCCEx_PeriphCLKConfig+0x13c8>
  {
    return HAL_OK;
 800d2c0:	2300      	movs	r3, #0
 800d2c2:	e000      	b.n	800d2c6 <HAL_RCCEx_PeriphCLKConfig+0x13ca>
  }
  return HAL_ERROR;
 800d2c4:	2301      	movs	r3, #1
}
 800d2c6:	4618      	mov	r0, r3
 800d2c8:	f507 7790 	add.w	r7, r7, #288	@ 0x120
 800d2cc:	46bd      	mov	sp, r7
 800d2ce:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 800d2d2:	bf00      	nop
 800d2d4:	58024400 	.word	0x58024400

0800d2d8 <HAL_RCCEx_GetPeriphCLKFreq>:
  * @retval Frequency in KHz
  *
  *  (*) : Available on some STM32H7 lines only.
  */
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
{
 800d2d8:	b580      	push	{r7, lr}
 800d2da:	b090      	sub	sp, #64	@ 0x40
 800d2dc:	af00      	add	r7, sp, #0
 800d2de:	e9c7 0100 	strd	r0, r1, [r7]
  /* This variable is used to store the SAI and CKP clock source */
  uint32_t saiclocksource;
  uint32_t ckpclocksource;
  uint32_t srcclk;

  if (PeriphClk == RCC_PERIPHCLK_SAI1)
 800d2e2:	e9d7 2300 	ldrd	r2, r3, [r7]
 800d2e6:	f5a2 7180 	sub.w	r1, r2, #256	@ 0x100
 800d2ea:	430b      	orrs	r3, r1
 800d2ec:	f040 8094 	bne.w	800d418 <HAL_RCCEx_GetPeriphCLKFreq+0x140>
  {

    saiclocksource = __HAL_RCC_GET_SAI1_SOURCE();
 800d2f0:	4b9e      	ldr	r3, [pc, #632]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d2f2:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800d2f4:	f003 0307 	and.w	r3, r3, #7
 800d2f8:	633b      	str	r3, [r7, #48]	@ 0x30

    switch (saiclocksource)
 800d2fa:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d2fc:	2b04      	cmp	r3, #4
 800d2fe:	f200 8087 	bhi.w	800d410 <HAL_RCCEx_GetPeriphCLKFreq+0x138>
 800d302:	a201      	add	r2, pc, #4	@ (adr r2, 800d308 <HAL_RCCEx_GetPeriphCLKFreq+0x30>)
 800d304:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800d308:	0800d31d 	.word	0x0800d31d
 800d30c:	0800d345 	.word	0x0800d345
 800d310:	0800d36d 	.word	0x0800d36d
 800d314:	0800d409 	.word	0x0800d409
 800d318:	0800d395 	.word	0x0800d395
    {
      case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800d31c:	4b93      	ldr	r3, [pc, #588]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d31e:	681b      	ldr	r3, [r3, #0]
 800d320:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800d324:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800d328:	d108      	bne.n	800d33c <HAL_RCCEx_GetPeriphCLKFreq+0x64>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800d32a:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800d32e:	4618      	mov	r0, r3
 800d330:	f001 f810 	bl	800e354 <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800d334:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800d336:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d338:	f000 bd45 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d33c:	2300      	movs	r3, #0
 800d33e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d340:	f000 bd41 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800d344:	4b89      	ldr	r3, [pc, #548]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d346:	681b      	ldr	r3, [r3, #0]
 800d348:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800d34c:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800d350:	d108      	bne.n	800d364 <HAL_RCCEx_GetPeriphCLKFreq+0x8c>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800d352:	f107 0318 	add.w	r3, r7, #24
 800d356:	4618      	mov	r0, r3
 800d358:	f000 fd54 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_P_Frequency;
 800d35c:	69bb      	ldr	r3, [r7, #24]
 800d35e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d360:	f000 bd31 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d364:	2300      	movs	r3, #0
 800d366:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d368:	f000 bd2d 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800d36c:	4b7f      	ldr	r3, [pc, #508]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d36e:	681b      	ldr	r3, [r3, #0]
 800d370:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800d374:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800d378:	d108      	bne.n	800d38c <HAL_RCCEx_GetPeriphCLKFreq+0xb4>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800d37a:	f107 030c 	add.w	r3, r7, #12
 800d37e:	4618      	mov	r0, r3
 800d380:	f000 fe94 	bl	800e0ac <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_P_Frequency;
 800d384:	68fb      	ldr	r3, [r7, #12]
 800d386:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d388:	f000 bd1d 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d38c:	2300      	movs	r3, #0
 800d38e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d390:	f000 bd19 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
      {

        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
 800d394:	4b75      	ldr	r3, [pc, #468]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d396:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800d398:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800d39c:	637b      	str	r3, [r7, #52]	@ 0x34

        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
 800d39e:	4b73      	ldr	r3, [pc, #460]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d3a0:	681b      	ldr	r3, [r3, #0]
 800d3a2:	f003 0304 	and.w	r3, r3, #4
 800d3a6:	2b04      	cmp	r3, #4
 800d3a8:	d10c      	bne.n	800d3c4 <HAL_RCCEx_GetPeriphCLKFreq+0xec>
 800d3aa:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d3ac:	2b00      	cmp	r3, #0
 800d3ae:	d109      	bne.n	800d3c4 <HAL_RCCEx_GetPeriphCLKFreq+0xec>
        {
          /* In Case the CKPER Source is HSI */
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800d3b0:	4b6e      	ldr	r3, [pc, #440]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d3b2:	681b      	ldr	r3, [r3, #0]
 800d3b4:	08db      	lsrs	r3, r3, #3
 800d3b6:	f003 0303 	and.w	r3, r3, #3
 800d3ba:	4a6d      	ldr	r2, [pc, #436]	@ (800d570 <HAL_RCCEx_GetPeriphCLKFreq+0x298>)
 800d3bc:	fa22 f303 	lsr.w	r3, r2, r3
 800d3c0:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d3c2:	e01f      	b.n	800d404 <HAL_RCCEx_GetPeriphCLKFreq+0x12c>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
 800d3c4:	4b69      	ldr	r3, [pc, #420]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d3c6:	681b      	ldr	r3, [r3, #0]
 800d3c8:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800d3cc:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800d3d0:	d106      	bne.n	800d3e0 <HAL_RCCEx_GetPeriphCLKFreq+0x108>
 800d3d2:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d3d4:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800d3d8:	d102      	bne.n	800d3e0 <HAL_RCCEx_GetPeriphCLKFreq+0x108>
        {
          /* In Case the CKPER Source is CSI */
          frequency = CSI_VALUE;
 800d3da:	4b66      	ldr	r3, [pc, #408]	@ (800d574 <HAL_RCCEx_GetPeriphCLKFreq+0x29c>)
 800d3dc:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d3de:	e011      	b.n	800d404 <HAL_RCCEx_GetPeriphCLKFreq+0x12c>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
 800d3e0:	4b62      	ldr	r3, [pc, #392]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d3e2:	681b      	ldr	r3, [r3, #0]
 800d3e4:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800d3e8:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800d3ec:	d106      	bne.n	800d3fc <HAL_RCCEx_GetPeriphCLKFreq+0x124>
 800d3ee:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d3f0:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800d3f4:	d102      	bne.n	800d3fc <HAL_RCCEx_GetPeriphCLKFreq+0x124>
        {
          /* In Case the CKPER Source is HSE */
          frequency = HSE_VALUE;
 800d3f6:	4b60      	ldr	r3, [pc, #384]	@ (800d578 <HAL_RCCEx_GetPeriphCLKFreq+0x2a0>)
 800d3f8:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d3fa:	e003      	b.n	800d404 <HAL_RCCEx_GetPeriphCLKFreq+0x12c>
        }

        else
        {
          /* In Case the CKPER is disabled*/
          frequency = 0;
 800d3fc:	2300      	movs	r3, #0
 800d3fe:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }

        break;
 800d400:	f000 bce1 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800d404:	f000 bcdf 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
      {
        frequency = EXTERNAL_CLOCK_VALUE;
 800d408:	4b5c      	ldr	r3, [pc, #368]	@ (800d57c <HAL_RCCEx_GetPeriphCLKFreq+0x2a4>)
 800d40a:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d40c:	f000 bcdb 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      default :
      {
        frequency = 0;
 800d410:	2300      	movs	r3, #0
 800d412:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d414:	f000 bcd7 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }

#if defined(SAI3)
  else if (PeriphClk == RCC_PERIPHCLK_SAI23)
 800d418:	e9d7 2300 	ldrd	r2, r3, [r7]
 800d41c:	f5a2 7100 	sub.w	r1, r2, #512	@ 0x200
 800d420:	430b      	orrs	r3, r1
 800d422:	f040 80ad 	bne.w	800d580 <HAL_RCCEx_GetPeriphCLKFreq+0x2a8>
  {

    saiclocksource = __HAL_RCC_GET_SAI23_SOURCE();
 800d426:	4b51      	ldr	r3, [pc, #324]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d428:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800d42a:	f403 73e0 	and.w	r3, r3, #448	@ 0x1c0
 800d42e:	633b      	str	r3, [r7, #48]	@ 0x30

    switch (saiclocksource)
 800d430:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d432:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800d436:	d056      	beq.n	800d4e6 <HAL_RCCEx_GetPeriphCLKFreq+0x20e>
 800d438:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d43a:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800d43e:	f200 8090 	bhi.w	800d562 <HAL_RCCEx_GetPeriphCLKFreq+0x28a>
 800d442:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d444:	2bc0      	cmp	r3, #192	@ 0xc0
 800d446:	f000 8088 	beq.w	800d55a <HAL_RCCEx_GetPeriphCLKFreq+0x282>
 800d44a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d44c:	2bc0      	cmp	r3, #192	@ 0xc0
 800d44e:	f200 8088 	bhi.w	800d562 <HAL_RCCEx_GetPeriphCLKFreq+0x28a>
 800d452:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d454:	2b80      	cmp	r3, #128	@ 0x80
 800d456:	d032      	beq.n	800d4be <HAL_RCCEx_GetPeriphCLKFreq+0x1e6>
 800d458:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d45a:	2b80      	cmp	r3, #128	@ 0x80
 800d45c:	f200 8081 	bhi.w	800d562 <HAL_RCCEx_GetPeriphCLKFreq+0x28a>
 800d460:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d462:	2b00      	cmp	r3, #0
 800d464:	d003      	beq.n	800d46e <HAL_RCCEx_GetPeriphCLKFreq+0x196>
 800d466:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d468:	2b40      	cmp	r3, #64	@ 0x40
 800d46a:	d014      	beq.n	800d496 <HAL_RCCEx_GetPeriphCLKFreq+0x1be>
 800d46c:	e079      	b.n	800d562 <HAL_RCCEx_GetPeriphCLKFreq+0x28a>
    {
      case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800d46e:	4b3f      	ldr	r3, [pc, #252]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d470:	681b      	ldr	r3, [r3, #0]
 800d472:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800d476:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800d47a:	d108      	bne.n	800d48e <HAL_RCCEx_GetPeriphCLKFreq+0x1b6>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800d47c:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800d480:	4618      	mov	r0, r3
 800d482:	f000 ff67 	bl	800e354 <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800d486:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800d488:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d48a:	f000 bc9c 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d48e:	2300      	movs	r3, #0
 800d490:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d492:	f000 bc98 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800d496:	4b35      	ldr	r3, [pc, #212]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d498:	681b      	ldr	r3, [r3, #0]
 800d49a:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800d49e:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800d4a2:	d108      	bne.n	800d4b6 <HAL_RCCEx_GetPeriphCLKFreq+0x1de>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800d4a4:	f107 0318 	add.w	r3, r7, #24
 800d4a8:	4618      	mov	r0, r3
 800d4aa:	f000 fcab 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_P_Frequency;
 800d4ae:	69bb      	ldr	r3, [r7, #24]
 800d4b0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d4b2:	f000 bc88 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d4b6:	2300      	movs	r3, #0
 800d4b8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d4ba:	f000 bc84 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800d4be:	4b2b      	ldr	r3, [pc, #172]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d4c0:	681b      	ldr	r3, [r3, #0]
 800d4c2:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800d4c6:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800d4ca:	d108      	bne.n	800d4de <HAL_RCCEx_GetPeriphCLKFreq+0x206>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800d4cc:	f107 030c 	add.w	r3, r7, #12
 800d4d0:	4618      	mov	r0, r3
 800d4d2:	f000 fdeb 	bl	800e0ac <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_P_Frequency;
 800d4d6:	68fb      	ldr	r3, [r7, #12]
 800d4d8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d4da:	f000 bc74 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d4de:	2300      	movs	r3, #0
 800d4e0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d4e2:	f000 bc70 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
      {

        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
 800d4e6:	4b21      	ldr	r3, [pc, #132]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d4e8:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800d4ea:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800d4ee:	637b      	str	r3, [r7, #52]	@ 0x34

        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
 800d4f0:	4b1e      	ldr	r3, [pc, #120]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d4f2:	681b      	ldr	r3, [r3, #0]
 800d4f4:	f003 0304 	and.w	r3, r3, #4
 800d4f8:	2b04      	cmp	r3, #4
 800d4fa:	d10c      	bne.n	800d516 <HAL_RCCEx_GetPeriphCLKFreq+0x23e>
 800d4fc:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d4fe:	2b00      	cmp	r3, #0
 800d500:	d109      	bne.n	800d516 <HAL_RCCEx_GetPeriphCLKFreq+0x23e>
        {
          /* In Case the CKPER Source is HSI */
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800d502:	4b1a      	ldr	r3, [pc, #104]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d504:	681b      	ldr	r3, [r3, #0]
 800d506:	08db      	lsrs	r3, r3, #3
 800d508:	f003 0303 	and.w	r3, r3, #3
 800d50c:	4a18      	ldr	r2, [pc, #96]	@ (800d570 <HAL_RCCEx_GetPeriphCLKFreq+0x298>)
 800d50e:	fa22 f303 	lsr.w	r3, r2, r3
 800d512:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d514:	e01f      	b.n	800d556 <HAL_RCCEx_GetPeriphCLKFreq+0x27e>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
 800d516:	4b15      	ldr	r3, [pc, #84]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d518:	681b      	ldr	r3, [r3, #0]
 800d51a:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800d51e:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800d522:	d106      	bne.n	800d532 <HAL_RCCEx_GetPeriphCLKFreq+0x25a>
 800d524:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d526:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800d52a:	d102      	bne.n	800d532 <HAL_RCCEx_GetPeriphCLKFreq+0x25a>
        {
          /* In Case the CKPER Source is CSI */
          frequency = CSI_VALUE;
 800d52c:	4b11      	ldr	r3, [pc, #68]	@ (800d574 <HAL_RCCEx_GetPeriphCLKFreq+0x29c>)
 800d52e:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d530:	e011      	b.n	800d556 <HAL_RCCEx_GetPeriphCLKFreq+0x27e>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
 800d532:	4b0e      	ldr	r3, [pc, #56]	@ (800d56c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
 800d534:	681b      	ldr	r3, [r3, #0]
 800d536:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800d53a:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800d53e:	d106      	bne.n	800d54e <HAL_RCCEx_GetPeriphCLKFreq+0x276>
 800d540:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d542:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800d546:	d102      	bne.n	800d54e <HAL_RCCEx_GetPeriphCLKFreq+0x276>
        {
          /* In Case the CKPER Source is HSE */
          frequency = HSE_VALUE;
 800d548:	4b0b      	ldr	r3, [pc, #44]	@ (800d578 <HAL_RCCEx_GetPeriphCLKFreq+0x2a0>)
 800d54a:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d54c:	e003      	b.n	800d556 <HAL_RCCEx_GetPeriphCLKFreq+0x27e>
        }

        else
        {
          /* In Case the CKPER is disabled*/
          frequency = 0;
 800d54e:	2300      	movs	r3, #0
 800d550:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }

        break;
 800d552:	f000 bc38 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800d556:	f000 bc36 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
      {
        frequency = EXTERNAL_CLOCK_VALUE;
 800d55a:	4b08      	ldr	r3, [pc, #32]	@ (800d57c <HAL_RCCEx_GetPeriphCLKFreq+0x2a4>)
 800d55c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d55e:	f000 bc32 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      default :
      {
        frequency = 0;
 800d562:	2300      	movs	r3, #0
 800d564:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d566:	f000 bc2e 	b.w	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800d56a:	bf00      	nop
 800d56c:	58024400 	.word	0x58024400
 800d570:	03d09000 	.word	0x03d09000
 800d574:	003d0900 	.word	0x003d0900
 800d578:	017d7840 	.word	0x017d7840
 800d57c:	00bb8000 	.word	0x00bb8000
    }
  }
#endif

#if defined(SAI4)
  else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
 800d580:	e9d7 2300 	ldrd	r2, r3, [r7]
 800d584:	f5a2 6180 	sub.w	r1, r2, #1024	@ 0x400
 800d588:	430b      	orrs	r3, r1
 800d58a:	f040 809c 	bne.w	800d6c6 <HAL_RCCEx_GetPeriphCLKFreq+0x3ee>
  {

    saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE();
 800d58e:	4b9e      	ldr	r3, [pc, #632]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d590:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800d592:	f403 0360 	and.w	r3, r3, #14680064	@ 0xe00000
 800d596:	633b      	str	r3, [r7, #48]	@ 0x30

    switch (saiclocksource)
 800d598:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d59a:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 800d59e:	d054      	beq.n	800d64a <HAL_RCCEx_GetPeriphCLKFreq+0x372>
 800d5a0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d5a2:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 800d5a6:	f200 808b 	bhi.w	800d6c0 <HAL_RCCEx_GetPeriphCLKFreq+0x3e8>
 800d5aa:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d5ac:	f5b3 0fc0 	cmp.w	r3, #6291456	@ 0x600000
 800d5b0:	f000 8083 	beq.w	800d6ba <HAL_RCCEx_GetPeriphCLKFreq+0x3e2>
 800d5b4:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d5b6:	f5b3 0fc0 	cmp.w	r3, #6291456	@ 0x600000
 800d5ba:	f200 8081 	bhi.w	800d6c0 <HAL_RCCEx_GetPeriphCLKFreq+0x3e8>
 800d5be:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d5c0:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
 800d5c4:	d02f      	beq.n	800d626 <HAL_RCCEx_GetPeriphCLKFreq+0x34e>
 800d5c6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d5c8:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
 800d5cc:	d878      	bhi.n	800d6c0 <HAL_RCCEx_GetPeriphCLKFreq+0x3e8>
 800d5ce:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d5d0:	2b00      	cmp	r3, #0
 800d5d2:	d004      	beq.n	800d5de <HAL_RCCEx_GetPeriphCLKFreq+0x306>
 800d5d4:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d5d6:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
 800d5da:	d012      	beq.n	800d602 <HAL_RCCEx_GetPeriphCLKFreq+0x32a>
 800d5dc:	e070      	b.n	800d6c0 <HAL_RCCEx_GetPeriphCLKFreq+0x3e8>
    {
      case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800d5de:	4b8a      	ldr	r3, [pc, #552]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d5e0:	681b      	ldr	r3, [r3, #0]
 800d5e2:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800d5e6:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800d5ea:	d107      	bne.n	800d5fc <HAL_RCCEx_GetPeriphCLKFreq+0x324>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800d5ec:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800d5f0:	4618      	mov	r0, r3
 800d5f2:	f000 feaf 	bl	800e354 <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800d5f6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800d5f8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d5fa:	e3e4      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d5fc:	2300      	movs	r3, #0
 800d5fe:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d600:	e3e1      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800d602:	4b81      	ldr	r3, [pc, #516]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d604:	681b      	ldr	r3, [r3, #0]
 800d606:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800d60a:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800d60e:	d107      	bne.n	800d620 <HAL_RCCEx_GetPeriphCLKFreq+0x348>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800d610:	f107 0318 	add.w	r3, r7, #24
 800d614:	4618      	mov	r0, r3
 800d616:	f000 fbf5 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_P_Frequency;
 800d61a:	69bb      	ldr	r3, [r7, #24]
 800d61c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d61e:	e3d2      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d620:	2300      	movs	r3, #0
 800d622:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d624:	e3cf      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800d626:	4b78      	ldr	r3, [pc, #480]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d628:	681b      	ldr	r3, [r3, #0]
 800d62a:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800d62e:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800d632:	d107      	bne.n	800d644 <HAL_RCCEx_GetPeriphCLKFreq+0x36c>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800d634:	f107 030c 	add.w	r3, r7, #12
 800d638:	4618      	mov	r0, r3
 800d63a:	f000 fd37 	bl	800e0ac <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_P_Frequency;
 800d63e:	68fb      	ldr	r3, [r7, #12]
 800d640:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d642:	e3c0      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d644:	2300      	movs	r3, #0
 800d646:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d648:	e3bd      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/
      {

        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
 800d64a:	4b6f      	ldr	r3, [pc, #444]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d64c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800d64e:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800d652:	637b      	str	r3, [r7, #52]	@ 0x34

        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
 800d654:	4b6c      	ldr	r3, [pc, #432]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d656:	681b      	ldr	r3, [r3, #0]
 800d658:	f003 0304 	and.w	r3, r3, #4
 800d65c:	2b04      	cmp	r3, #4
 800d65e:	d10c      	bne.n	800d67a <HAL_RCCEx_GetPeriphCLKFreq+0x3a2>
 800d660:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d662:	2b00      	cmp	r3, #0
 800d664:	d109      	bne.n	800d67a <HAL_RCCEx_GetPeriphCLKFreq+0x3a2>
        {
          /* In Case the CKPER Source is HSI */
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800d666:	4b68      	ldr	r3, [pc, #416]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d668:	681b      	ldr	r3, [r3, #0]
 800d66a:	08db      	lsrs	r3, r3, #3
 800d66c:	f003 0303 	and.w	r3, r3, #3
 800d670:	4a66      	ldr	r2, [pc, #408]	@ (800d80c <HAL_RCCEx_GetPeriphCLKFreq+0x534>)
 800d672:	fa22 f303 	lsr.w	r3, r2, r3
 800d676:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d678:	e01e      	b.n	800d6b8 <HAL_RCCEx_GetPeriphCLKFreq+0x3e0>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
 800d67a:	4b63      	ldr	r3, [pc, #396]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d67c:	681b      	ldr	r3, [r3, #0]
 800d67e:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800d682:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800d686:	d106      	bne.n	800d696 <HAL_RCCEx_GetPeriphCLKFreq+0x3be>
 800d688:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d68a:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800d68e:	d102      	bne.n	800d696 <HAL_RCCEx_GetPeriphCLKFreq+0x3be>
        {
          /* In Case the CKPER Source is CSI */
          frequency = CSI_VALUE;
 800d690:	4b5f      	ldr	r3, [pc, #380]	@ (800d810 <HAL_RCCEx_GetPeriphCLKFreq+0x538>)
 800d692:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d694:	e010      	b.n	800d6b8 <HAL_RCCEx_GetPeriphCLKFreq+0x3e0>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
 800d696:	4b5c      	ldr	r3, [pc, #368]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d698:	681b      	ldr	r3, [r3, #0]
 800d69a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800d69e:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800d6a2:	d106      	bne.n	800d6b2 <HAL_RCCEx_GetPeriphCLKFreq+0x3da>
 800d6a4:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d6a6:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800d6aa:	d102      	bne.n	800d6b2 <HAL_RCCEx_GetPeriphCLKFreq+0x3da>
        {
          /* In Case the CKPER Source is HSE */
          frequency = HSE_VALUE;
 800d6ac:	4b59      	ldr	r3, [pc, #356]	@ (800d814 <HAL_RCCEx_GetPeriphCLKFreq+0x53c>)
 800d6ae:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d6b0:	e002      	b.n	800d6b8 <HAL_RCCEx_GetPeriphCLKFreq+0x3e0>
        }

        else
        {
          /* In Case the CKPER is disabled*/
          frequency = 0;
 800d6b2:	2300      	movs	r3, #0
 800d6b4:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }

        break;
 800d6b6:	e386      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800d6b8:	e385      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */
      {
        frequency = EXTERNAL_CLOCK_VALUE;
 800d6ba:	4b57      	ldr	r3, [pc, #348]	@ (800d818 <HAL_RCCEx_GetPeriphCLKFreq+0x540>)
 800d6bc:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d6be:	e382      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      default :
      {
        frequency = 0;
 800d6c0:	2300      	movs	r3, #0
 800d6c2:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d6c4:	e37f      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }

  else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
 800d6c6:	e9d7 2300 	ldrd	r2, r3, [r7]
 800d6ca:	f5a2 6100 	sub.w	r1, r2, #2048	@ 0x800
 800d6ce:	430b      	orrs	r3, r1
 800d6d0:	f040 80a7 	bne.w	800d822 <HAL_RCCEx_GetPeriphCLKFreq+0x54a>
  {

    saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE();
 800d6d4:	4b4c      	ldr	r3, [pc, #304]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d6d6:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800d6d8:	f003 63e0 	and.w	r3, r3, #117440512	@ 0x7000000
 800d6dc:	633b      	str	r3, [r7, #48]	@ 0x30

    switch (saiclocksource)
 800d6de:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d6e0:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 800d6e4:	d055      	beq.n	800d792 <HAL_RCCEx_GetPeriphCLKFreq+0x4ba>
 800d6e6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d6e8:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 800d6ec:	f200 8096 	bhi.w	800d81c <HAL_RCCEx_GetPeriphCLKFreq+0x544>
 800d6f0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d6f2:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
 800d6f6:	f000 8084 	beq.w	800d802 <HAL_RCCEx_GetPeriphCLKFreq+0x52a>
 800d6fa:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d6fc:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
 800d700:	f200 808c 	bhi.w	800d81c <HAL_RCCEx_GetPeriphCLKFreq+0x544>
 800d704:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d706:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800d70a:	d030      	beq.n	800d76e <HAL_RCCEx_GetPeriphCLKFreq+0x496>
 800d70c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d70e:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800d712:	f200 8083 	bhi.w	800d81c <HAL_RCCEx_GetPeriphCLKFreq+0x544>
 800d716:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d718:	2b00      	cmp	r3, #0
 800d71a:	d004      	beq.n	800d726 <HAL_RCCEx_GetPeriphCLKFreq+0x44e>
 800d71c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800d71e:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
 800d722:	d012      	beq.n	800d74a <HAL_RCCEx_GetPeriphCLKFreq+0x472>
 800d724:	e07a      	b.n	800d81c <HAL_RCCEx_GetPeriphCLKFreq+0x544>
    {
      case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800d726:	4b38      	ldr	r3, [pc, #224]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d728:	681b      	ldr	r3, [r3, #0]
 800d72a:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800d72e:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800d732:	d107      	bne.n	800d744 <HAL_RCCEx_GetPeriphCLKFreq+0x46c>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800d734:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800d738:	4618      	mov	r0, r3
 800d73a:	f000 fe0b 	bl	800e354 <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800d73e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800d740:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d742:	e340      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d744:	2300      	movs	r3, #0
 800d746:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d748:	e33d      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800d74a:	4b2f      	ldr	r3, [pc, #188]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d74c:	681b      	ldr	r3, [r3, #0]
 800d74e:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800d752:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800d756:	d107      	bne.n	800d768 <HAL_RCCEx_GetPeriphCLKFreq+0x490>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800d758:	f107 0318 	add.w	r3, r7, #24
 800d75c:	4618      	mov	r0, r3
 800d75e:	f000 fb51 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_P_Frequency;
 800d762:	69bb      	ldr	r3, [r7, #24]
 800d764:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d766:	e32e      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d768:	2300      	movs	r3, #0
 800d76a:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d76c:	e32b      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800d76e:	4b26      	ldr	r3, [pc, #152]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d770:	681b      	ldr	r3, [r3, #0]
 800d772:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800d776:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800d77a:	d107      	bne.n	800d78c <HAL_RCCEx_GetPeriphCLKFreq+0x4b4>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800d77c:	f107 030c 	add.w	r3, r7, #12
 800d780:	4618      	mov	r0, r3
 800d782:	f000 fc93 	bl	800e0ac <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_P_Frequency;
 800d786:	68fb      	ldr	r3, [r7, #12]
 800d788:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d78a:	e31c      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d78c:	2300      	movs	r3, #0
 800d78e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d790:	e319      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/
      {

        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
 800d792:	4b1d      	ldr	r3, [pc, #116]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d794:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800d796:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800d79a:	637b      	str	r3, [r7, #52]	@ 0x34

        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
 800d79c:	4b1a      	ldr	r3, [pc, #104]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d79e:	681b      	ldr	r3, [r3, #0]
 800d7a0:	f003 0304 	and.w	r3, r3, #4
 800d7a4:	2b04      	cmp	r3, #4
 800d7a6:	d10c      	bne.n	800d7c2 <HAL_RCCEx_GetPeriphCLKFreq+0x4ea>
 800d7a8:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d7aa:	2b00      	cmp	r3, #0
 800d7ac:	d109      	bne.n	800d7c2 <HAL_RCCEx_GetPeriphCLKFreq+0x4ea>
        {
          /* In Case the CKPER Source is HSI */
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800d7ae:	4b16      	ldr	r3, [pc, #88]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d7b0:	681b      	ldr	r3, [r3, #0]
 800d7b2:	08db      	lsrs	r3, r3, #3
 800d7b4:	f003 0303 	and.w	r3, r3, #3
 800d7b8:	4a14      	ldr	r2, [pc, #80]	@ (800d80c <HAL_RCCEx_GetPeriphCLKFreq+0x534>)
 800d7ba:	fa22 f303 	lsr.w	r3, r2, r3
 800d7be:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d7c0:	e01e      	b.n	800d800 <HAL_RCCEx_GetPeriphCLKFreq+0x528>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
 800d7c2:	4b11      	ldr	r3, [pc, #68]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d7c4:	681b      	ldr	r3, [r3, #0]
 800d7c6:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800d7ca:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800d7ce:	d106      	bne.n	800d7de <HAL_RCCEx_GetPeriphCLKFreq+0x506>
 800d7d0:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d7d2:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800d7d6:	d102      	bne.n	800d7de <HAL_RCCEx_GetPeriphCLKFreq+0x506>
        {
          /* In Case the CKPER Source is CSI */
          frequency = CSI_VALUE;
 800d7d8:	4b0d      	ldr	r3, [pc, #52]	@ (800d810 <HAL_RCCEx_GetPeriphCLKFreq+0x538>)
 800d7da:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d7dc:	e010      	b.n	800d800 <HAL_RCCEx_GetPeriphCLKFreq+0x528>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
 800d7de:	4b0a      	ldr	r3, [pc, #40]	@ (800d808 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
 800d7e0:	681b      	ldr	r3, [r3, #0]
 800d7e2:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800d7e6:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800d7ea:	d106      	bne.n	800d7fa <HAL_RCCEx_GetPeriphCLKFreq+0x522>
 800d7ec:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d7ee:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800d7f2:	d102      	bne.n	800d7fa <HAL_RCCEx_GetPeriphCLKFreq+0x522>
        {
          /* In Case the CKPER Source is HSE */
          frequency = HSE_VALUE;
 800d7f4:	4b07      	ldr	r3, [pc, #28]	@ (800d814 <HAL_RCCEx_GetPeriphCLKFreq+0x53c>)
 800d7f6:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d7f8:	e002      	b.n	800d800 <HAL_RCCEx_GetPeriphCLKFreq+0x528>
        }

        else
        {
          /* In Case the CKPER is disabled*/
          frequency = 0;
 800d7fa:	2300      	movs	r3, #0
 800d7fc:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }

        break;
 800d7fe:	e2e2      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800d800:	e2e1      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */
      {
        frequency = EXTERNAL_CLOCK_VALUE;
 800d802:	4b05      	ldr	r3, [pc, #20]	@ (800d818 <HAL_RCCEx_GetPeriphCLKFreq+0x540>)
 800d804:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d806:	e2de      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800d808:	58024400 	.word	0x58024400
 800d80c:	03d09000 	.word	0x03d09000
 800d810:	003d0900 	.word	0x003d0900
 800d814:	017d7840 	.word	0x017d7840
 800d818:	00bb8000 	.word	0x00bb8000
      }

      default :
      {
        frequency = 0;
 800d81c:	2300      	movs	r3, #0
 800d81e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d820:	e2d1      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }
#endif /*SAI4*/
  else if (PeriphClk == RCC_PERIPHCLK_SPI123)
 800d822:	e9d7 2300 	ldrd	r2, r3, [r7]
 800d826:	f5a2 5180 	sub.w	r1, r2, #4096	@ 0x1000
 800d82a:	430b      	orrs	r3, r1
 800d82c:	f040 809c 	bne.w	800d968 <HAL_RCCEx_GetPeriphCLKFreq+0x690>
  {
    /* Get SPI1/2/3 clock source */
    srcclk = __HAL_RCC_GET_SPI123_SOURCE();
 800d830:	4b93      	ldr	r3, [pc, #588]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800d832:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800d834:	f403 43e0 	and.w	r3, r3, #28672	@ 0x7000
 800d838:	63bb      	str	r3, [r7, #56]	@ 0x38

    switch (srcclk)
 800d83a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d83c:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 800d840:	d054      	beq.n	800d8ec <HAL_RCCEx_GetPeriphCLKFreq+0x614>
 800d842:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d844:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 800d848:	f200 808b 	bhi.w	800d962 <HAL_RCCEx_GetPeriphCLKFreq+0x68a>
 800d84c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d84e:	f5b3 5f40 	cmp.w	r3, #12288	@ 0x3000
 800d852:	f000 8083 	beq.w	800d95c <HAL_RCCEx_GetPeriphCLKFreq+0x684>
 800d856:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d858:	f5b3 5f40 	cmp.w	r3, #12288	@ 0x3000
 800d85c:	f200 8081 	bhi.w	800d962 <HAL_RCCEx_GetPeriphCLKFreq+0x68a>
 800d860:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d862:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800d866:	d02f      	beq.n	800d8c8 <HAL_RCCEx_GetPeriphCLKFreq+0x5f0>
 800d868:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d86a:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800d86e:	d878      	bhi.n	800d962 <HAL_RCCEx_GetPeriphCLKFreq+0x68a>
 800d870:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d872:	2b00      	cmp	r3, #0
 800d874:	d004      	beq.n	800d880 <HAL_RCCEx_GetPeriphCLKFreq+0x5a8>
 800d876:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d878:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800d87c:	d012      	beq.n	800d8a4 <HAL_RCCEx_GetPeriphCLKFreq+0x5cc>
 800d87e:	e070      	b.n	800d962 <HAL_RCCEx_GetPeriphCLKFreq+0x68a>
    {
      case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800d880:	4b7f      	ldr	r3, [pc, #508]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800d882:	681b      	ldr	r3, [r3, #0]
 800d884:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800d888:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800d88c:	d107      	bne.n	800d89e <HAL_RCCEx_GetPeriphCLKFreq+0x5c6>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800d88e:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800d892:	4618      	mov	r0, r3
 800d894:	f000 fd5e 	bl	800e354 <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800d898:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800d89a:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d89c:	e293      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d89e:	2300      	movs	r3, #0
 800d8a0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d8a2:	e290      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800d8a4:	4b76      	ldr	r3, [pc, #472]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800d8a6:	681b      	ldr	r3, [r3, #0]
 800d8a8:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800d8ac:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800d8b0:	d107      	bne.n	800d8c2 <HAL_RCCEx_GetPeriphCLKFreq+0x5ea>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800d8b2:	f107 0318 	add.w	r3, r7, #24
 800d8b6:	4618      	mov	r0, r3
 800d8b8:	f000 faa4 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_P_Frequency;
 800d8bc:	69bb      	ldr	r3, [r7, #24]
 800d8be:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d8c0:	e281      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d8c2:	2300      	movs	r3, #0
 800d8c4:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d8c6:	e27e      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800d8c8:	4b6d      	ldr	r3, [pc, #436]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800d8ca:	681b      	ldr	r3, [r3, #0]
 800d8cc:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800d8d0:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800d8d4:	d107      	bne.n	800d8e6 <HAL_RCCEx_GetPeriphCLKFreq+0x60e>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800d8d6:	f107 030c 	add.w	r3, r7, #12
 800d8da:	4618      	mov	r0, r3
 800d8dc:	f000 fbe6 	bl	800e0ac <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_P_Frequency;
 800d8e0:	68fb      	ldr	r3, [r7, #12]
 800d8e2:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d8e4:	e26f      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d8e6:	2300      	movs	r3, #0
 800d8e8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d8ea:	e26c      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */
      {

        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
 800d8ec:	4b64      	ldr	r3, [pc, #400]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800d8ee:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800d8f0:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800d8f4:	637b      	str	r3, [r7, #52]	@ 0x34

        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
 800d8f6:	4b62      	ldr	r3, [pc, #392]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800d8f8:	681b      	ldr	r3, [r3, #0]
 800d8fa:	f003 0304 	and.w	r3, r3, #4
 800d8fe:	2b04      	cmp	r3, #4
 800d900:	d10c      	bne.n	800d91c <HAL_RCCEx_GetPeriphCLKFreq+0x644>
 800d902:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d904:	2b00      	cmp	r3, #0
 800d906:	d109      	bne.n	800d91c <HAL_RCCEx_GetPeriphCLKFreq+0x644>
        {
          /* In Case the CKPER Source is HSI */
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800d908:	4b5d      	ldr	r3, [pc, #372]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800d90a:	681b      	ldr	r3, [r3, #0]
 800d90c:	08db      	lsrs	r3, r3, #3
 800d90e:	f003 0303 	and.w	r3, r3, #3
 800d912:	4a5c      	ldr	r2, [pc, #368]	@ (800da84 <HAL_RCCEx_GetPeriphCLKFreq+0x7ac>)
 800d914:	fa22 f303 	lsr.w	r3, r2, r3
 800d918:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d91a:	e01e      	b.n	800d95a <HAL_RCCEx_GetPeriphCLKFreq+0x682>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
 800d91c:	4b58      	ldr	r3, [pc, #352]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800d91e:	681b      	ldr	r3, [r3, #0]
 800d920:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800d924:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800d928:	d106      	bne.n	800d938 <HAL_RCCEx_GetPeriphCLKFreq+0x660>
 800d92a:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d92c:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800d930:	d102      	bne.n	800d938 <HAL_RCCEx_GetPeriphCLKFreq+0x660>
        {
          /* In Case the CKPER Source is CSI */
          frequency = CSI_VALUE;
 800d932:	4b55      	ldr	r3, [pc, #340]	@ (800da88 <HAL_RCCEx_GetPeriphCLKFreq+0x7b0>)
 800d934:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d936:	e010      	b.n	800d95a <HAL_RCCEx_GetPeriphCLKFreq+0x682>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
 800d938:	4b51      	ldr	r3, [pc, #324]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800d93a:	681b      	ldr	r3, [r3, #0]
 800d93c:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800d940:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800d944:	d106      	bne.n	800d954 <HAL_RCCEx_GetPeriphCLKFreq+0x67c>
 800d946:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800d948:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800d94c:	d102      	bne.n	800d954 <HAL_RCCEx_GetPeriphCLKFreq+0x67c>
        {
          /* In Case the CKPER Source is HSE */
          frequency = HSE_VALUE;
 800d94e:	4b4f      	ldr	r3, [pc, #316]	@ (800da8c <HAL_RCCEx_GetPeriphCLKFreq+0x7b4>)
 800d950:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800d952:	e002      	b.n	800d95a <HAL_RCCEx_GetPeriphCLKFreq+0x682>
        }

        else
        {
          /* In Case the CKPER is disabled*/
          frequency = 0;
 800d954:	2300      	movs	r3, #0
 800d956:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }

        break;
 800d958:	e235      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800d95a:	e234      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
      {
        frequency = EXTERNAL_CLOCK_VALUE;
 800d95c:	4b4c      	ldr	r3, [pc, #304]	@ (800da90 <HAL_RCCEx_GetPeriphCLKFreq+0x7b8>)
 800d95e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d960:	e231      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      default :
      {
        frequency = 0;
 800d962:	2300      	movs	r3, #0
 800d964:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d966:	e22e      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }
  else if (PeriphClk == RCC_PERIPHCLK_SPI45)
 800d968:	e9d7 2300 	ldrd	r2, r3, [r7]
 800d96c:	f5a2 5100 	sub.w	r1, r2, #8192	@ 0x2000
 800d970:	430b      	orrs	r3, r1
 800d972:	f040 808f 	bne.w	800da94 <HAL_RCCEx_GetPeriphCLKFreq+0x7bc>
  {
    /* Get SPI45 clock source */
    srcclk = __HAL_RCC_GET_SPI45_SOURCE();
 800d976:	4b42      	ldr	r3, [pc, #264]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800d978:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800d97a:	f403 23e0 	and.w	r3, r3, #458752	@ 0x70000
 800d97e:	63bb      	str	r3, [r7, #56]	@ 0x38
    switch (srcclk)
 800d980:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d982:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 800d986:	d06b      	beq.n	800da60 <HAL_RCCEx_GetPeriphCLKFreq+0x788>
 800d988:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d98a:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 800d98e:	d874      	bhi.n	800da7a <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
 800d990:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d992:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
 800d996:	d056      	beq.n	800da46 <HAL_RCCEx_GetPeriphCLKFreq+0x76e>
 800d998:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d99a:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
 800d99e:	d86c      	bhi.n	800da7a <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
 800d9a0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d9a2:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
 800d9a6:	d03b      	beq.n	800da20 <HAL_RCCEx_GetPeriphCLKFreq+0x748>
 800d9a8:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d9aa:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
 800d9ae:	d864      	bhi.n	800da7a <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
 800d9b0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d9b2:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800d9b6:	d021      	beq.n	800d9fc <HAL_RCCEx_GetPeriphCLKFreq+0x724>
 800d9b8:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d9ba:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800d9be:	d85c      	bhi.n	800da7a <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
 800d9c0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d9c2:	2b00      	cmp	r3, #0
 800d9c4:	d004      	beq.n	800d9d0 <HAL_RCCEx_GetPeriphCLKFreq+0x6f8>
 800d9c6:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800d9c8:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800d9cc:	d004      	beq.n	800d9d8 <HAL_RCCEx_GetPeriphCLKFreq+0x700>
 800d9ce:	e054      	b.n	800da7a <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
    {
      case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */
      {
        frequency = HAL_RCC_GetPCLK1Freq();
 800d9d0:	f7fe fa26 	bl	800be20 <HAL_RCC_GetPCLK1Freq>
 800d9d4:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 800d9d6:	e1f6      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800d9d8:	4b29      	ldr	r3, [pc, #164]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800d9da:	681b      	ldr	r3, [r3, #0]
 800d9dc:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800d9e0:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800d9e4:	d107      	bne.n	800d9f6 <HAL_RCCEx_GetPeriphCLKFreq+0x71e>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800d9e6:	f107 0318 	add.w	r3, r7, #24
 800d9ea:	4618      	mov	r0, r3
 800d9ec:	f000 fa0a 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_Q_Frequency;
 800d9f0:	69fb      	ldr	r3, [r7, #28]
 800d9f2:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800d9f4:	e1e7      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800d9f6:	2300      	movs	r3, #0
 800d9f8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800d9fa:	e1e4      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800d9fc:	4b20      	ldr	r3, [pc, #128]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800d9fe:	681b      	ldr	r3, [r3, #0]
 800da00:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800da04:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800da08:	d107      	bne.n	800da1a <HAL_RCCEx_GetPeriphCLKFreq+0x742>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800da0a:	f107 030c 	add.w	r3, r7, #12
 800da0e:	4618      	mov	r0, r3
 800da10:	f000 fb4c 	bl	800e0ac <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_Q_Frequency;
 800da14:	693b      	ldr	r3, [r7, #16]
 800da16:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800da18:	e1d5      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800da1a:	2300      	movs	r3, #0
 800da1c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800da1e:	e1d2      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
 800da20:	4b17      	ldr	r3, [pc, #92]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800da22:	681b      	ldr	r3, [r3, #0]
 800da24:	f003 0304 	and.w	r3, r3, #4
 800da28:	2b04      	cmp	r3, #4
 800da2a:	d109      	bne.n	800da40 <HAL_RCCEx_GetPeriphCLKFreq+0x768>
        {
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800da2c:	4b14      	ldr	r3, [pc, #80]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800da2e:	681b      	ldr	r3, [r3, #0]
 800da30:	08db      	lsrs	r3, r3, #3
 800da32:	f003 0303 	and.w	r3, r3, #3
 800da36:	4a13      	ldr	r2, [pc, #76]	@ (800da84 <HAL_RCCEx_GetPeriphCLKFreq+0x7ac>)
 800da38:	fa22 f303 	lsr.w	r3, r2, r3
 800da3c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800da3e:	e1c2      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800da40:	2300      	movs	r3, #0
 800da42:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800da44:	e1bf      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
 800da46:	4b0e      	ldr	r3, [pc, #56]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800da48:	681b      	ldr	r3, [r3, #0]
 800da4a:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800da4e:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800da52:	d102      	bne.n	800da5a <HAL_RCCEx_GetPeriphCLKFreq+0x782>
        {
          frequency = CSI_VALUE;
 800da54:	4b0c      	ldr	r3, [pc, #48]	@ (800da88 <HAL_RCCEx_GetPeriphCLKFreq+0x7b0>)
 800da56:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800da58:	e1b5      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800da5a:	2300      	movs	r3, #0
 800da5c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800da5e:	e1b2      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
 800da60:	4b07      	ldr	r3, [pc, #28]	@ (800da80 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
 800da62:	681b      	ldr	r3, [r3, #0]
 800da64:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800da68:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800da6c:	d102      	bne.n	800da74 <HAL_RCCEx_GetPeriphCLKFreq+0x79c>
        {
          frequency = HSE_VALUE;
 800da6e:	4b07      	ldr	r3, [pc, #28]	@ (800da8c <HAL_RCCEx_GetPeriphCLKFreq+0x7b4>)
 800da70:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800da72:	e1a8      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800da74:	2300      	movs	r3, #0
 800da76:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800da78:	e1a5      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      default :
      {
        frequency = 0;
 800da7a:	2300      	movs	r3, #0
 800da7c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800da7e:	e1a2      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800da80:	58024400 	.word	0x58024400
 800da84:	03d09000 	.word	0x03d09000
 800da88:	003d0900 	.word	0x003d0900
 800da8c:	017d7840 	.word	0x017d7840
 800da90:	00bb8000 	.word	0x00bb8000
      }
    }
  }
  else if (PeriphClk == RCC_PERIPHCLK_ADC)
 800da94:	e9d7 2300 	ldrd	r2, r3, [r7]
 800da98:	f5a2 2100 	sub.w	r1, r2, #524288	@ 0x80000
 800da9c:	430b      	orrs	r3, r1
 800da9e:	d173      	bne.n	800db88 <HAL_RCCEx_GetPeriphCLKFreq+0x8b0>
  {
    /* Get ADC clock source */
    srcclk = __HAL_RCC_GET_ADC_SOURCE();
 800daa0:	4b9c      	ldr	r3, [pc, #624]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800daa2:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800daa4:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 800daa8:	63bb      	str	r3, [r7, #56]	@ 0x38

    switch (srcclk)
 800daaa:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800daac:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800dab0:	d02f      	beq.n	800db12 <HAL_RCCEx_GetPeriphCLKFreq+0x83a>
 800dab2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dab4:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800dab8:	d863      	bhi.n	800db82 <HAL_RCCEx_GetPeriphCLKFreq+0x8aa>
 800daba:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dabc:	2b00      	cmp	r3, #0
 800dabe:	d004      	beq.n	800daca <HAL_RCCEx_GetPeriphCLKFreq+0x7f2>
 800dac0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dac2:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800dac6:	d012      	beq.n	800daee <HAL_RCCEx_GetPeriphCLKFreq+0x816>
 800dac8:	e05b      	b.n	800db82 <HAL_RCCEx_GetPeriphCLKFreq+0x8aa>
    {
      case RCC_ADCCLKSOURCE_PLL2:
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800daca:	4b92      	ldr	r3, [pc, #584]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800dacc:	681b      	ldr	r3, [r3, #0]
 800dace:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800dad2:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800dad6:	d107      	bne.n	800dae8 <HAL_RCCEx_GetPeriphCLKFreq+0x810>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800dad8:	f107 0318 	add.w	r3, r7, #24
 800dadc:	4618      	mov	r0, r3
 800dade:	f000 f991 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_P_Frequency;
 800dae2:	69bb      	ldr	r3, [r7, #24]
 800dae4:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800dae6:	e16e      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800dae8:	2300      	movs	r3, #0
 800daea:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800daec:	e16b      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_ADCCLKSOURCE_PLL3:
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800daee:	4b89      	ldr	r3, [pc, #548]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800daf0:	681b      	ldr	r3, [r3, #0]
 800daf2:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800daf6:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800dafa:	d107      	bne.n	800db0c <HAL_RCCEx_GetPeriphCLKFreq+0x834>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800dafc:	f107 030c 	add.w	r3, r7, #12
 800db00:	4618      	mov	r0, r3
 800db02:	f000 fad3 	bl	800e0ac <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_R_Frequency;
 800db06:	697b      	ldr	r3, [r7, #20]
 800db08:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800db0a:	e15c      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800db0c:	2300      	movs	r3, #0
 800db0e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800db10:	e159      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      case RCC_ADCCLKSOURCE_CLKP:
      {

        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
 800db12:	4b80      	ldr	r3, [pc, #512]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800db14:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800db16:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800db1a:	637b      	str	r3, [r7, #52]	@ 0x34

        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
 800db1c:	4b7d      	ldr	r3, [pc, #500]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800db1e:	681b      	ldr	r3, [r3, #0]
 800db20:	f003 0304 	and.w	r3, r3, #4
 800db24:	2b04      	cmp	r3, #4
 800db26:	d10c      	bne.n	800db42 <HAL_RCCEx_GetPeriphCLKFreq+0x86a>
 800db28:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800db2a:	2b00      	cmp	r3, #0
 800db2c:	d109      	bne.n	800db42 <HAL_RCCEx_GetPeriphCLKFreq+0x86a>
        {
          /* In Case the CKPER Source is HSI */
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800db2e:	4b79      	ldr	r3, [pc, #484]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800db30:	681b      	ldr	r3, [r3, #0]
 800db32:	08db      	lsrs	r3, r3, #3
 800db34:	f003 0303 	and.w	r3, r3, #3
 800db38:	4a77      	ldr	r2, [pc, #476]	@ (800dd18 <HAL_RCCEx_GetPeriphCLKFreq+0xa40>)
 800db3a:	fa22 f303 	lsr.w	r3, r2, r3
 800db3e:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800db40:	e01e      	b.n	800db80 <HAL_RCCEx_GetPeriphCLKFreq+0x8a8>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
 800db42:	4b74      	ldr	r3, [pc, #464]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800db44:	681b      	ldr	r3, [r3, #0]
 800db46:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800db4a:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800db4e:	d106      	bne.n	800db5e <HAL_RCCEx_GetPeriphCLKFreq+0x886>
 800db50:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800db52:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800db56:	d102      	bne.n	800db5e <HAL_RCCEx_GetPeriphCLKFreq+0x886>
        {
          /* In Case the CKPER Source is CSI */
          frequency = CSI_VALUE;
 800db58:	4b70      	ldr	r3, [pc, #448]	@ (800dd1c <HAL_RCCEx_GetPeriphCLKFreq+0xa44>)
 800db5a:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800db5c:	e010      	b.n	800db80 <HAL_RCCEx_GetPeriphCLKFreq+0x8a8>
        }

        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
 800db5e:	4b6d      	ldr	r3, [pc, #436]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800db60:	681b      	ldr	r3, [r3, #0]
 800db62:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800db66:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800db6a:	d106      	bne.n	800db7a <HAL_RCCEx_GetPeriphCLKFreq+0x8a2>
 800db6c:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800db6e:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800db72:	d102      	bne.n	800db7a <HAL_RCCEx_GetPeriphCLKFreq+0x8a2>
        {
          /* In Case the CKPER Source is HSE */
          frequency = HSE_VALUE;
 800db74:	4b6a      	ldr	r3, [pc, #424]	@ (800dd20 <HAL_RCCEx_GetPeriphCLKFreq+0xa48>)
 800db76:	63fb      	str	r3, [r7, #60]	@ 0x3c
 800db78:	e002      	b.n	800db80 <HAL_RCCEx_GetPeriphCLKFreq+0x8a8>
        }

        else
        {
          /* In Case the CKPER is disabled*/
          frequency = 0;
 800db7a:	2300      	movs	r3, #0
 800db7c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }

        break;
 800db7e:	e122      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800db80:	e121      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      default :
      {
        frequency = 0;
 800db82:	2300      	movs	r3, #0
 800db84:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800db86:	e11e      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }
  else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
 800db88:	e9d7 2300 	ldrd	r2, r3, [r7]
 800db8c:	f5a2 3180 	sub.w	r1, r2, #65536	@ 0x10000
 800db90:	430b      	orrs	r3, r1
 800db92:	d133      	bne.n	800dbfc <HAL_RCCEx_GetPeriphCLKFreq+0x924>
  {
    /* Get SDMMC clock source */
    srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
 800db94:	4b5f      	ldr	r3, [pc, #380]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800db96:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800db98:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 800db9c:	63bb      	str	r3, [r7, #56]	@ 0x38

    switch (srcclk)
 800db9e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dba0:	2b00      	cmp	r3, #0
 800dba2:	d004      	beq.n	800dbae <HAL_RCCEx_GetPeriphCLKFreq+0x8d6>
 800dba4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dba6:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800dbaa:	d012      	beq.n	800dbd2 <HAL_RCCEx_GetPeriphCLKFreq+0x8fa>
 800dbac:	e023      	b.n	800dbf6 <HAL_RCCEx_GetPeriphCLKFreq+0x91e>
    {
      case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800dbae:	4b59      	ldr	r3, [pc, #356]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800dbb0:	681b      	ldr	r3, [r3, #0]
 800dbb2:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800dbb6:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800dbba:	d107      	bne.n	800dbcc <HAL_RCCEx_GetPeriphCLKFreq+0x8f4>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800dbbc:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800dbc0:	4618      	mov	r0, r3
 800dbc2:	f000 fbc7 	bl	800e354 <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800dbc6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800dbc8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800dbca:	e0fc      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800dbcc:	2300      	movs	r3, #0
 800dbce:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dbd0:	e0f9      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800dbd2:	4b50      	ldr	r3, [pc, #320]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800dbd4:	681b      	ldr	r3, [r3, #0]
 800dbd6:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800dbda:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800dbde:	d107      	bne.n	800dbf0 <HAL_RCCEx_GetPeriphCLKFreq+0x918>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800dbe0:	f107 0318 	add.w	r3, r7, #24
 800dbe4:	4618      	mov	r0, r3
 800dbe6:	f000 f90d 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_R_Frequency;
 800dbea:	6a3b      	ldr	r3, [r7, #32]
 800dbec:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800dbee:	e0ea      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800dbf0:	2300      	movs	r3, #0
 800dbf2:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dbf4:	e0e7      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }

      default :
      {
        frequency = 0;
 800dbf6:	2300      	movs	r3, #0
 800dbf8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dbfa:	e0e4      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }
  else if (PeriphClk == RCC_PERIPHCLK_SPI6)
 800dbfc:	e9d7 2300 	ldrd	r2, r3, [r7]
 800dc00:	f5a2 4180 	sub.w	r1, r2, #16384	@ 0x4000
 800dc04:	430b      	orrs	r3, r1
 800dc06:	f040 808d 	bne.w	800dd24 <HAL_RCCEx_GetPeriphCLKFreq+0xa4c>
  {
    /* Get SPI6 clock source */
    srcclk = __HAL_RCC_GET_SPI6_SOURCE();
 800dc0a:	4b42      	ldr	r3, [pc, #264]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800dc0c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800dc0e:	f003 43e0 	and.w	r3, r3, #1879048192	@ 0x70000000
 800dc12:	63bb      	str	r3, [r7, #56]	@ 0x38

    switch (srcclk)
 800dc14:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc16:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 800dc1a:	d06b      	beq.n	800dcf4 <HAL_RCCEx_GetPeriphCLKFreq+0xa1c>
 800dc1c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc1e:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
 800dc22:	d874      	bhi.n	800dd0e <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
 800dc24:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc26:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800dc2a:	d056      	beq.n	800dcda <HAL_RCCEx_GetPeriphCLKFreq+0xa02>
 800dc2c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc2e:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800dc32:	d86c      	bhi.n	800dd0e <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
 800dc34:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc36:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
 800dc3a:	d03b      	beq.n	800dcb4 <HAL_RCCEx_GetPeriphCLKFreq+0x9dc>
 800dc3c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc3e:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
 800dc42:	d864      	bhi.n	800dd0e <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
 800dc44:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc46:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800dc4a:	d021      	beq.n	800dc90 <HAL_RCCEx_GetPeriphCLKFreq+0x9b8>
 800dc4c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc4e:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800dc52:	d85c      	bhi.n	800dd0e <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
 800dc54:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc56:	2b00      	cmp	r3, #0
 800dc58:	d004      	beq.n	800dc64 <HAL_RCCEx_GetPeriphCLKFreq+0x98c>
 800dc5a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dc5c:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800dc60:	d004      	beq.n	800dc6c <HAL_RCCEx_GetPeriphCLKFreq+0x994>
 800dc62:	e054      	b.n	800dd0e <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
    {
      case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
      {
        frequency = HAL_RCCEx_GetD3PCLK1Freq();
 800dc64:	f000 f8b8 	bl	800ddd8 <HAL_RCCEx_GetD3PCLK1Freq>
 800dc68:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 800dc6a:	e0ac      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800dc6c:	4b29      	ldr	r3, [pc, #164]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800dc6e:	681b      	ldr	r3, [r3, #0]
 800dc70:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800dc74:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800dc78:	d107      	bne.n	800dc8a <HAL_RCCEx_GetPeriphCLKFreq+0x9b2>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800dc7a:	f107 0318 	add.w	r3, r7, #24
 800dc7e:	4618      	mov	r0, r3
 800dc80:	f000 f8c0 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_Q_Frequency;
 800dc84:	69fb      	ldr	r3, [r7, #28]
 800dc86:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800dc88:	e09d      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800dc8a:	2300      	movs	r3, #0
 800dc8c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dc8e:	e09a      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
 800dc90:	4b20      	ldr	r3, [pc, #128]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800dc92:	681b      	ldr	r3, [r3, #0]
 800dc94:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800dc98:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800dc9c:	d107      	bne.n	800dcae <HAL_RCCEx_GetPeriphCLKFreq+0x9d6>
        {
          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 800dc9e:	f107 030c 	add.w	r3, r7, #12
 800dca2:	4618      	mov	r0, r3
 800dca4:	f000 fa02 	bl	800e0ac <HAL_RCCEx_GetPLL3ClockFreq>
          frequency = pll3_clocks.PLL3_Q_Frequency;
 800dca8:	693b      	ldr	r3, [r7, #16]
 800dcaa:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800dcac:	e08b      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800dcae:	2300      	movs	r3, #0
 800dcb0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dcb2:	e088      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
 800dcb4:	4b17      	ldr	r3, [pc, #92]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800dcb6:	681b      	ldr	r3, [r3, #0]
 800dcb8:	f003 0304 	and.w	r3, r3, #4
 800dcbc:	2b04      	cmp	r3, #4
 800dcbe:	d109      	bne.n	800dcd4 <HAL_RCCEx_GetPeriphCLKFreq+0x9fc>
        {
          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800dcc0:	4b14      	ldr	r3, [pc, #80]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800dcc2:	681b      	ldr	r3, [r3, #0]
 800dcc4:	08db      	lsrs	r3, r3, #3
 800dcc6:	f003 0303 	and.w	r3, r3, #3
 800dcca:	4a13      	ldr	r2, [pc, #76]	@ (800dd18 <HAL_RCCEx_GetPeriphCLKFreq+0xa40>)
 800dccc:	fa22 f303 	lsr.w	r3, r2, r3
 800dcd0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800dcd2:	e078      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800dcd4:	2300      	movs	r3, #0
 800dcd6:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dcd8:	e075      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
 800dcda:	4b0e      	ldr	r3, [pc, #56]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800dcdc:	681b      	ldr	r3, [r3, #0]
 800dcde:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800dce2:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 800dce6:	d102      	bne.n	800dcee <HAL_RCCEx_GetPeriphCLKFreq+0xa16>
        {
          frequency = CSI_VALUE;
 800dce8:	4b0c      	ldr	r3, [pc, #48]	@ (800dd1c <HAL_RCCEx_GetPeriphCLKFreq+0xa44>)
 800dcea:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800dcec:	e06b      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800dcee:	2300      	movs	r3, #0
 800dcf0:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dcf2:	e068      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
 800dcf4:	4b07      	ldr	r3, [pc, #28]	@ (800dd14 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
 800dcf6:	681b      	ldr	r3, [r3, #0]
 800dcf8:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800dcfc:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800dd00:	d102      	bne.n	800dd08 <HAL_RCCEx_GetPeriphCLKFreq+0xa30>
        {
          frequency = HSE_VALUE;
 800dd02:	4b07      	ldr	r3, [pc, #28]	@ (800dd20 <HAL_RCCEx_GetPeriphCLKFreq+0xa48>)
 800dd04:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800dd06:	e05e      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800dd08:	2300      	movs	r3, #0
 800dd0a:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dd0c:	e05b      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
        break;
      }
#endif /* RCC_SPI6CLKSOURCE_PIN */
      default :
      {
        frequency = 0;
 800dd0e:	2300      	movs	r3, #0
 800dd10:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dd12:	e058      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
 800dd14:	58024400 	.word	0x58024400
 800dd18:	03d09000 	.word	0x03d09000
 800dd1c:	003d0900 	.word	0x003d0900
 800dd20:	017d7840 	.word	0x017d7840
      }
    }
  }
  else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
 800dd24:	e9d7 2300 	ldrd	r2, r3, [r7]
 800dd28:	f5a2 4100 	sub.w	r1, r2, #32768	@ 0x8000
 800dd2c:	430b      	orrs	r3, r1
 800dd2e:	d148      	bne.n	800ddc2 <HAL_RCCEx_GetPeriphCLKFreq+0xaea>
  {
    /* Get FDCAN clock source */
    srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
 800dd30:	4b27      	ldr	r3, [pc, #156]	@ (800ddd0 <HAL_RCCEx_GetPeriphCLKFreq+0xaf8>)
 800dd32:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800dd34:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
 800dd38:	63bb      	str	r3, [r7, #56]	@ 0x38

    switch (srcclk)
 800dd3a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dd3c:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800dd40:	d02a      	beq.n	800dd98 <HAL_RCCEx_GetPeriphCLKFreq+0xac0>
 800dd42:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dd44:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 800dd48:	d838      	bhi.n	800ddbc <HAL_RCCEx_GetPeriphCLKFreq+0xae4>
 800dd4a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dd4c:	2b00      	cmp	r3, #0
 800dd4e:	d004      	beq.n	800dd5a <HAL_RCCEx_GetPeriphCLKFreq+0xa82>
 800dd50:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800dd52:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800dd56:	d00d      	beq.n	800dd74 <HAL_RCCEx_GetPeriphCLKFreq+0xa9c>
 800dd58:	e030      	b.n	800ddbc <HAL_RCCEx_GetPeriphCLKFreq+0xae4>
    {
      case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
 800dd5a:	4b1d      	ldr	r3, [pc, #116]	@ (800ddd0 <HAL_RCCEx_GetPeriphCLKFreq+0xaf8>)
 800dd5c:	681b      	ldr	r3, [r3, #0]
 800dd5e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800dd62:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
 800dd66:	d102      	bne.n	800dd6e <HAL_RCCEx_GetPeriphCLKFreq+0xa96>
        {
          frequency = HSE_VALUE;
 800dd68:	4b1a      	ldr	r3, [pc, #104]	@ (800ddd4 <HAL_RCCEx_GetPeriphCLKFreq+0xafc>)
 800dd6a:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800dd6c:	e02b      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800dd6e:	2300      	movs	r3, #0
 800dd70:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dd72:	e028      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
 800dd74:	4b16      	ldr	r3, [pc, #88]	@ (800ddd0 <HAL_RCCEx_GetPeriphCLKFreq+0xaf8>)
 800dd76:	681b      	ldr	r3, [r3, #0]
 800dd78:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 800dd7c:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
 800dd80:	d107      	bne.n	800dd92 <HAL_RCCEx_GetPeriphCLKFreq+0xaba>
        {
          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
 800dd82:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800dd86:	4618      	mov	r0, r3
 800dd88:	f000 fae4 	bl	800e354 <HAL_RCCEx_GetPLL1ClockFreq>
          frequency = pll1_clocks.PLL1_Q_Frequency;
 800dd8c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 800dd8e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800dd90:	e019      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800dd92:	2300      	movs	r3, #0
 800dd94:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800dd96:	e016      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
 800dd98:	4b0d      	ldr	r3, [pc, #52]	@ (800ddd0 <HAL_RCCEx_GetPeriphCLKFreq+0xaf8>)
 800dd9a:	681b      	ldr	r3, [r3, #0]
 800dd9c:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800dda0:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 800dda4:	d107      	bne.n	800ddb6 <HAL_RCCEx_GetPeriphCLKFreq+0xade>
        {
          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 800dda6:	f107 0318 	add.w	r3, r7, #24
 800ddaa:	4618      	mov	r0, r3
 800ddac:	f000 f82a 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
          frequency = pll2_clocks.PLL2_Q_Frequency;
 800ddb0:	69fb      	ldr	r3, [r7, #28]
 800ddb2:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          frequency = 0;
        }
        break;
 800ddb4:	e007      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
          frequency = 0;
 800ddb6:	2300      	movs	r3, #0
 800ddb8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ddba:	e004      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
      default :
      {
        frequency = 0;
 800ddbc:	2300      	movs	r3, #0
 800ddbe:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 800ddc0:	e001      	b.n	800ddc6 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
      }
    }
  }
  else
  {
    frequency = 0;
 800ddc2:	2300      	movs	r3, #0
 800ddc4:	63fb      	str	r3, [r7, #60]	@ 0x3c
  }

  return frequency;
 800ddc6:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
}
 800ddc8:	4618      	mov	r0, r3
 800ddca:	3740      	adds	r7, #64	@ 0x40
 800ddcc:	46bd      	mov	sp, r7
 800ddce:	bd80      	pop	{r7, pc}
 800ddd0:	58024400 	.word	0x58024400
 800ddd4:	017d7840 	.word	0x017d7840

0800ddd8 <HAL_RCCEx_GetD3PCLK1Freq>:
  * @note   Each time D3PCLK1 changes, this function must be called to update the
  *         right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval D3PCLK1 frequency
  */
uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
{
 800ddd8:	b580      	push	{r7, lr}
 800ddda:	af00      	add	r7, sp, #0
#if defined(RCC_D3CFGR_D3PPRE)
  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
 800dddc:	f7fd fff0 	bl	800bdc0 <HAL_RCC_GetHCLKFreq>
 800dde0:	4602      	mov	r2, r0
 800dde2:	4b06      	ldr	r3, [pc, #24]	@ (800ddfc <HAL_RCCEx_GetD3PCLK1Freq+0x24>)
 800dde4:	6a1b      	ldr	r3, [r3, #32]
 800dde6:	091b      	lsrs	r3, r3, #4
 800dde8:	f003 0307 	and.w	r3, r3, #7
 800ddec:	4904      	ldr	r1, [pc, #16]	@ (800de00 <HAL_RCCEx_GetD3PCLK1Freq+0x28>)
 800ddee:	5ccb      	ldrb	r3, [r1, r3]
 800ddf0:	f003 031f 	and.w	r3, r3, #31
 800ddf4:	fa22 f303 	lsr.w	r3, r2, r3
#else
  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
#endif
}
 800ddf8:	4618      	mov	r0, r3
 800ddfa:	bd80      	pop	{r7, pc}
 800ddfc:	58024400 	.word	0x58024400
 800de00:	08018a28 	.word	0x08018a28

0800de04 <HAL_RCCEx_GetPLL2ClockFreq>:
  *         right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
  * @param  PLL2_Clocks structure.
  * @retval None
  */
void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
{
 800de04:	b480      	push	{r7}
 800de06:	b089      	sub	sp, #36	@ 0x24
 800de08:	af00      	add	r7, sp, #0
 800de0a:	6078      	str	r0, [r7, #4]
  float_t fracn2, pll2vco;

  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
     PLL2xCLK = PLL2_VCO / PLL2x
  */
  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
 800de0c:	4ba1      	ldr	r3, [pc, #644]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800de0e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800de10:	f003 0303 	and.w	r3, r3, #3
 800de14:	61bb      	str	r3, [r7, #24]
  pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12);
 800de16:	4b9f      	ldr	r3, [pc, #636]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800de18:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800de1a:	0b1b      	lsrs	r3, r3, #12
 800de1c:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
 800de20:	617b      	str	r3, [r7, #20]
  pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
 800de22:	4b9c      	ldr	r3, [pc, #624]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800de24:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800de26:	091b      	lsrs	r3, r3, #4
 800de28:	f003 0301 	and.w	r3, r3, #1
 800de2c:	613b      	str	r3, [r7, #16]
  fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
 800de2e:	4b99      	ldr	r3, [pc, #612]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800de30:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 800de32:	08db      	lsrs	r3, r3, #3
 800de34:	f3c3 030c 	ubfx	r3, r3, #0, #13
 800de38:	693a      	ldr	r2, [r7, #16]
 800de3a:	fb02 f303 	mul.w	r3, r2, r3
 800de3e:	ee07 3a90 	vmov	s15, r3
 800de42:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800de46:	edc7 7a03 	vstr	s15, [r7, #12]

  if (pll2m != 0U)
 800de4a:	697b      	ldr	r3, [r7, #20]
 800de4c:	2b00      	cmp	r3, #0
 800de4e:	f000 8111 	beq.w	800e074 <HAL_RCCEx_GetPLL2ClockFreq+0x270>
  {
    switch (pllsource)
 800de52:	69bb      	ldr	r3, [r7, #24]
 800de54:	2b02      	cmp	r3, #2
 800de56:	f000 8083 	beq.w	800df60 <HAL_RCCEx_GetPLL2ClockFreq+0x15c>
 800de5a:	69bb      	ldr	r3, [r7, #24]
 800de5c:	2b02      	cmp	r3, #2
 800de5e:	f200 80a1 	bhi.w	800dfa4 <HAL_RCCEx_GetPLL2ClockFreq+0x1a0>
 800de62:	69bb      	ldr	r3, [r7, #24]
 800de64:	2b00      	cmp	r3, #0
 800de66:	d003      	beq.n	800de70 <HAL_RCCEx_GetPLL2ClockFreq+0x6c>
 800de68:	69bb      	ldr	r3, [r7, #24]
 800de6a:	2b01      	cmp	r3, #1
 800de6c:	d056      	beq.n	800df1c <HAL_RCCEx_GetPLL2ClockFreq+0x118>
 800de6e:	e099      	b.n	800dfa4 <HAL_RCCEx_GetPLL2ClockFreq+0x1a0>
    {

      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */

        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 800de70:	4b88      	ldr	r3, [pc, #544]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800de72:	681b      	ldr	r3, [r3, #0]
 800de74:	f003 0320 	and.w	r3, r3, #32
 800de78:	2b00      	cmp	r3, #0
 800de7a:	d02d      	beq.n	800ded8 <HAL_RCCEx_GetPLL2ClockFreq+0xd4>
        {
          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800de7c:	4b85      	ldr	r3, [pc, #532]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800de7e:	681b      	ldr	r3, [r3, #0]
 800de80:	08db      	lsrs	r3, r3, #3
 800de82:	f003 0303 	and.w	r3, r3, #3
 800de86:	4a84      	ldr	r2, [pc, #528]	@ (800e098 <HAL_RCCEx_GetPLL2ClockFreq+0x294>)
 800de88:	fa22 f303 	lsr.w	r3, r2, r3
 800de8c:	60bb      	str	r3, [r7, #8]
          pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
 800de8e:	68bb      	ldr	r3, [r7, #8]
 800de90:	ee07 3a90 	vmov	s15, r3
 800de94:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800de98:	697b      	ldr	r3, [r7, #20]
 800de9a:	ee07 3a90 	vmov	s15, r3
 800de9e:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800dea2:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800dea6:	4b7b      	ldr	r3, [pc, #492]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800dea8:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800deaa:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800deae:	ee07 3a90 	vmov	s15, r3
 800deb2:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800deb6:	ed97 6a03 	vldr	s12, [r7, #12]
 800deba:	eddf 5a78 	vldr	s11, [pc, #480]	@ 800e09c <HAL_RCCEx_GetPLL2ClockFreq+0x298>
 800debe:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800dec2:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800dec6:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800deca:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800dece:	ee67 7a27 	vmul.f32	s15, s14, s15
 800ded2:	edc7 7a07 	vstr	s15, [r7, #28]
        }
        else
        {
          pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
        }
        break;
 800ded6:	e087      	b.n	800dfe8 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>
          pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
 800ded8:	697b      	ldr	r3, [r7, #20]
 800deda:	ee07 3a90 	vmov	s15, r3
 800dede:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800dee2:	eddf 6a6f 	vldr	s13, [pc, #444]	@ 800e0a0 <HAL_RCCEx_GetPLL2ClockFreq+0x29c>
 800dee6:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800deea:	4b6a      	ldr	r3, [pc, #424]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800deec:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800deee:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800def2:	ee07 3a90 	vmov	s15, r3
 800def6:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800defa:	ed97 6a03 	vldr	s12, [r7, #12]
 800defe:	eddf 5a67 	vldr	s11, [pc, #412]	@ 800e09c <HAL_RCCEx_GetPLL2ClockFreq+0x298>
 800df02:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800df06:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800df0a:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800df0e:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800df12:	ee67 7a27 	vmul.f32	s15, s14, s15
 800df16:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800df1a:	e065      	b.n	800dfe8 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>

      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
        pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
 800df1c:	697b      	ldr	r3, [r7, #20]
 800df1e:	ee07 3a90 	vmov	s15, r3
 800df22:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800df26:	eddf 6a5f 	vldr	s13, [pc, #380]	@ 800e0a4 <HAL_RCCEx_GetPLL2ClockFreq+0x2a0>
 800df2a:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800df2e:	4b59      	ldr	r3, [pc, #356]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800df30:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800df32:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800df36:	ee07 3a90 	vmov	s15, r3
 800df3a:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800df3e:	ed97 6a03 	vldr	s12, [r7, #12]
 800df42:	eddf 5a56 	vldr	s11, [pc, #344]	@ 800e09c <HAL_RCCEx_GetPLL2ClockFreq+0x298>
 800df46:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800df4a:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800df4e:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800df52:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800df56:	ee67 7a27 	vmul.f32	s15, s14, s15
 800df5a:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800df5e:	e043      	b.n	800dfe8 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>

      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
        pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
 800df60:	697b      	ldr	r3, [r7, #20]
 800df62:	ee07 3a90 	vmov	s15, r3
 800df66:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800df6a:	eddf 6a4f 	vldr	s13, [pc, #316]	@ 800e0a8 <HAL_RCCEx_GetPLL2ClockFreq+0x2a4>
 800df6e:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800df72:	4b48      	ldr	r3, [pc, #288]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800df74:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800df76:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800df7a:	ee07 3a90 	vmov	s15, r3
 800df7e:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800df82:	ed97 6a03 	vldr	s12, [r7, #12]
 800df86:	eddf 5a45 	vldr	s11, [pc, #276]	@ 800e09c <HAL_RCCEx_GetPLL2ClockFreq+0x298>
 800df8a:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800df8e:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800df92:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800df96:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800df9a:	ee67 7a27 	vmul.f32	s15, s14, s15
 800df9e:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800dfa2:	e021      	b.n	800dfe8 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>

      default:
        pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
 800dfa4:	697b      	ldr	r3, [r7, #20]
 800dfa6:	ee07 3a90 	vmov	s15, r3
 800dfaa:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800dfae:	eddf 6a3d 	vldr	s13, [pc, #244]	@ 800e0a4 <HAL_RCCEx_GetPLL2ClockFreq+0x2a0>
 800dfb2:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800dfb6:	4b37      	ldr	r3, [pc, #220]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800dfb8:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800dfba:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800dfbe:	ee07 3a90 	vmov	s15, r3
 800dfc2:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800dfc6:	ed97 6a03 	vldr	s12, [r7, #12]
 800dfca:	eddf 5a34 	vldr	s11, [pc, #208]	@ 800e09c <HAL_RCCEx_GetPLL2ClockFreq+0x298>
 800dfce:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800dfd2:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800dfd6:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800dfda:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800dfde:	ee67 7a27 	vmul.f32	s15, s14, s15
 800dfe2:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800dfe6:	bf00      	nop
    }
    PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9)  + (float_t)1)) ;
 800dfe8:	4b2a      	ldr	r3, [pc, #168]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800dfea:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800dfec:	0a5b      	lsrs	r3, r3, #9
 800dfee:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800dff2:	ee07 3a90 	vmov	s15, r3
 800dff6:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800dffa:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800dffe:	ee37 7a87 	vadd.f32	s14, s15, s14
 800e002:	edd7 6a07 	vldr	s13, [r7, #28]
 800e006:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800e00a:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800e00e:	ee17 2a90 	vmov	r2, s15
 800e012:	687b      	ldr	r3, [r7, #4]
 800e014:	601a      	str	r2, [r3, #0]
    PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ;
 800e016:	4b1f      	ldr	r3, [pc, #124]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800e018:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800e01a:	0c1b      	lsrs	r3, r3, #16
 800e01c:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800e020:	ee07 3a90 	vmov	s15, r3
 800e024:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e028:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800e02c:	ee37 7a87 	vadd.f32	s14, s15, s14
 800e030:	edd7 6a07 	vldr	s13, [r7, #28]
 800e034:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800e038:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800e03c:	ee17 2a90 	vmov	r2, s15
 800e040:	687b      	ldr	r3, [r7, #4]
 800e042:	605a      	str	r2, [r3, #4]
    PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ;
 800e044:	4b13      	ldr	r3, [pc, #76]	@ (800e094 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
 800e046:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800e048:	0e1b      	lsrs	r3, r3, #24
 800e04a:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800e04e:	ee07 3a90 	vmov	s15, r3
 800e052:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e056:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800e05a:	ee37 7a87 	vadd.f32	s14, s15, s14
 800e05e:	edd7 6a07 	vldr	s13, [r7, #28]
 800e062:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800e066:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800e06a:	ee17 2a90 	vmov	r2, s15
 800e06e:	687b      	ldr	r3, [r7, #4]
 800e070:	609a      	str	r2, [r3, #8]
  {
    PLL2_Clocks->PLL2_P_Frequency = 0U;
    PLL2_Clocks->PLL2_Q_Frequency = 0U;
    PLL2_Clocks->PLL2_R_Frequency = 0U;
  }
}
 800e072:	e008      	b.n	800e086 <HAL_RCCEx_GetPLL2ClockFreq+0x282>
    PLL2_Clocks->PLL2_P_Frequency = 0U;
 800e074:	687b      	ldr	r3, [r7, #4]
 800e076:	2200      	movs	r2, #0
 800e078:	601a      	str	r2, [r3, #0]
    PLL2_Clocks->PLL2_Q_Frequency = 0U;
 800e07a:	687b      	ldr	r3, [r7, #4]
 800e07c:	2200      	movs	r2, #0
 800e07e:	605a      	str	r2, [r3, #4]
    PLL2_Clocks->PLL2_R_Frequency = 0U;
 800e080:	687b      	ldr	r3, [r7, #4]
 800e082:	2200      	movs	r2, #0
 800e084:	609a      	str	r2, [r3, #8]
}
 800e086:	bf00      	nop
 800e088:	3724      	adds	r7, #36	@ 0x24
 800e08a:	46bd      	mov	sp, r7
 800e08c:	f85d 7b04 	ldr.w	r7, [sp], #4
 800e090:	4770      	bx	lr
 800e092:	bf00      	nop
 800e094:	58024400 	.word	0x58024400
 800e098:	03d09000 	.word	0x03d09000
 800e09c:	46000000 	.word	0x46000000
 800e0a0:	4c742400 	.word	0x4c742400
 800e0a4:	4a742400 	.word	0x4a742400
 800e0a8:	4bbebc20 	.word	0x4bbebc20

0800e0ac <HAL_RCCEx_GetPLL3ClockFreq>:
  *         right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
  * @param  PLL3_Clocks structure.
  * @retval None
  */
void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
{
 800e0ac:	b480      	push	{r7}
 800e0ae:	b089      	sub	sp, #36	@ 0x24
 800e0b0:	af00      	add	r7, sp, #0
 800e0b2:	6078      	str	r0, [r7, #4]
  float_t fracn3, pll3vco;

  /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
     PLL3xCLK = PLL3_VCO / PLLxR
  */
  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
 800e0b4:	4ba1      	ldr	r3, [pc, #644]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e0b6:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800e0b8:	f003 0303 	and.w	r3, r3, #3
 800e0bc:	61bb      	str	r3, [r7, #24]
  pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20)  ;
 800e0be:	4b9f      	ldr	r3, [pc, #636]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e0c0:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800e0c2:	0d1b      	lsrs	r3, r3, #20
 800e0c4:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
 800e0c8:	617b      	str	r3, [r7, #20]
  pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
 800e0ca:	4b9c      	ldr	r3, [pc, #624]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e0cc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e0ce:	0a1b      	lsrs	r3, r3, #8
 800e0d0:	f003 0301 	and.w	r3, r3, #1
 800e0d4:	613b      	str	r3, [r7, #16]
  fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
 800e0d6:	4b99      	ldr	r3, [pc, #612]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e0d8:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 800e0da:	08db      	lsrs	r3, r3, #3
 800e0dc:	f3c3 030c 	ubfx	r3, r3, #0, #13
 800e0e0:	693a      	ldr	r2, [r7, #16]
 800e0e2:	fb02 f303 	mul.w	r3, r2, r3
 800e0e6:	ee07 3a90 	vmov	s15, r3
 800e0ea:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e0ee:	edc7 7a03 	vstr	s15, [r7, #12]

  if (pll3m != 0U)
 800e0f2:	697b      	ldr	r3, [r7, #20]
 800e0f4:	2b00      	cmp	r3, #0
 800e0f6:	f000 8111 	beq.w	800e31c <HAL_RCCEx_GetPLL3ClockFreq+0x270>
  {
    switch (pllsource)
 800e0fa:	69bb      	ldr	r3, [r7, #24]
 800e0fc:	2b02      	cmp	r3, #2
 800e0fe:	f000 8083 	beq.w	800e208 <HAL_RCCEx_GetPLL3ClockFreq+0x15c>
 800e102:	69bb      	ldr	r3, [r7, #24]
 800e104:	2b02      	cmp	r3, #2
 800e106:	f200 80a1 	bhi.w	800e24c <HAL_RCCEx_GetPLL3ClockFreq+0x1a0>
 800e10a:	69bb      	ldr	r3, [r7, #24]
 800e10c:	2b00      	cmp	r3, #0
 800e10e:	d003      	beq.n	800e118 <HAL_RCCEx_GetPLL3ClockFreq+0x6c>
 800e110:	69bb      	ldr	r3, [r7, #24]
 800e112:	2b01      	cmp	r3, #1
 800e114:	d056      	beq.n	800e1c4 <HAL_RCCEx_GetPLL3ClockFreq+0x118>
 800e116:	e099      	b.n	800e24c <HAL_RCCEx_GetPLL3ClockFreq+0x1a0>
    {
      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */

        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 800e118:	4b88      	ldr	r3, [pc, #544]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e11a:	681b      	ldr	r3, [r3, #0]
 800e11c:	f003 0320 	and.w	r3, r3, #32
 800e120:	2b00      	cmp	r3, #0
 800e122:	d02d      	beq.n	800e180 <HAL_RCCEx_GetPLL3ClockFreq+0xd4>
        {
          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800e124:	4b85      	ldr	r3, [pc, #532]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e126:	681b      	ldr	r3, [r3, #0]
 800e128:	08db      	lsrs	r3, r3, #3
 800e12a:	f003 0303 	and.w	r3, r3, #3
 800e12e:	4a84      	ldr	r2, [pc, #528]	@ (800e340 <HAL_RCCEx_GetPLL3ClockFreq+0x294>)
 800e130:	fa22 f303 	lsr.w	r3, r2, r3
 800e134:	60bb      	str	r3, [r7, #8]
          pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
 800e136:	68bb      	ldr	r3, [r7, #8]
 800e138:	ee07 3a90 	vmov	s15, r3
 800e13c:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800e140:	697b      	ldr	r3, [r7, #20]
 800e142:	ee07 3a90 	vmov	s15, r3
 800e146:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e14a:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800e14e:	4b7b      	ldr	r3, [pc, #492]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e150:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800e152:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800e156:	ee07 3a90 	vmov	s15, r3
 800e15a:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800e15e:	ed97 6a03 	vldr	s12, [r7, #12]
 800e162:	eddf 5a78 	vldr	s11, [pc, #480]	@ 800e344 <HAL_RCCEx_GetPLL3ClockFreq+0x298>
 800e166:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800e16a:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800e16e:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800e172:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800e176:	ee67 7a27 	vmul.f32	s15, s14, s15
 800e17a:	edc7 7a07 	vstr	s15, [r7, #28]
        }
        else
        {
          pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
        }
        break;
 800e17e:	e087      	b.n	800e290 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>
          pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
 800e180:	697b      	ldr	r3, [r7, #20]
 800e182:	ee07 3a90 	vmov	s15, r3
 800e186:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e18a:	eddf 6a6f 	vldr	s13, [pc, #444]	@ 800e348 <HAL_RCCEx_GetPLL3ClockFreq+0x29c>
 800e18e:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800e192:	4b6a      	ldr	r3, [pc, #424]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e194:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800e196:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800e19a:	ee07 3a90 	vmov	s15, r3
 800e19e:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800e1a2:	ed97 6a03 	vldr	s12, [r7, #12]
 800e1a6:	eddf 5a67 	vldr	s11, [pc, #412]	@ 800e344 <HAL_RCCEx_GetPLL3ClockFreq+0x298>
 800e1aa:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800e1ae:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800e1b2:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800e1b6:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800e1ba:	ee67 7a27 	vmul.f32	s15, s14, s15
 800e1be:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800e1c2:	e065      	b.n	800e290 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>
      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
        pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
 800e1c4:	697b      	ldr	r3, [r7, #20]
 800e1c6:	ee07 3a90 	vmov	s15, r3
 800e1ca:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e1ce:	eddf 6a5f 	vldr	s13, [pc, #380]	@ 800e34c <HAL_RCCEx_GetPLL3ClockFreq+0x2a0>
 800e1d2:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800e1d6:	4b59      	ldr	r3, [pc, #356]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e1d8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800e1da:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800e1de:	ee07 3a90 	vmov	s15, r3
 800e1e2:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800e1e6:	ed97 6a03 	vldr	s12, [r7, #12]
 800e1ea:	eddf 5a56 	vldr	s11, [pc, #344]	@ 800e344 <HAL_RCCEx_GetPLL3ClockFreq+0x298>
 800e1ee:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800e1f2:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800e1f6:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800e1fa:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800e1fe:	ee67 7a27 	vmul.f32	s15, s14, s15
 800e202:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800e206:	e043      	b.n	800e290 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>

      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
        pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
 800e208:	697b      	ldr	r3, [r7, #20]
 800e20a:	ee07 3a90 	vmov	s15, r3
 800e20e:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e212:	eddf 6a4f 	vldr	s13, [pc, #316]	@ 800e350 <HAL_RCCEx_GetPLL3ClockFreq+0x2a4>
 800e216:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800e21a:	4b48      	ldr	r3, [pc, #288]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e21c:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800e21e:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800e222:	ee07 3a90 	vmov	s15, r3
 800e226:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800e22a:	ed97 6a03 	vldr	s12, [r7, #12]
 800e22e:	eddf 5a45 	vldr	s11, [pc, #276]	@ 800e344 <HAL_RCCEx_GetPLL3ClockFreq+0x298>
 800e232:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800e236:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800e23a:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800e23e:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800e242:	ee67 7a27 	vmul.f32	s15, s14, s15
 800e246:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800e24a:	e021      	b.n	800e290 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>

      default:
        pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
 800e24c:	697b      	ldr	r3, [r7, #20]
 800e24e:	ee07 3a90 	vmov	s15, r3
 800e252:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e256:	eddf 6a3d 	vldr	s13, [pc, #244]	@ 800e34c <HAL_RCCEx_GetPLL3ClockFreq+0x2a0>
 800e25a:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800e25e:	4b37      	ldr	r3, [pc, #220]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e260:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800e262:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800e266:	ee07 3a90 	vmov	s15, r3
 800e26a:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800e26e:	ed97 6a03 	vldr	s12, [r7, #12]
 800e272:	eddf 5a34 	vldr	s11, [pc, #208]	@ 800e344 <HAL_RCCEx_GetPLL3ClockFreq+0x298>
 800e276:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800e27a:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800e27e:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800e282:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800e286:	ee67 7a27 	vmul.f32	s15, s14, s15
 800e28a:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800e28e:	bf00      	nop
    }
    PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9)  + (float_t)1)) ;
 800e290:	4b2a      	ldr	r3, [pc, #168]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e292:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800e294:	0a5b      	lsrs	r3, r3, #9
 800e296:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800e29a:	ee07 3a90 	vmov	s15, r3
 800e29e:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e2a2:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800e2a6:	ee37 7a87 	vadd.f32	s14, s15, s14
 800e2aa:	edd7 6a07 	vldr	s13, [r7, #28]
 800e2ae:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800e2b2:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800e2b6:	ee17 2a90 	vmov	r2, s15
 800e2ba:	687b      	ldr	r3, [r7, #4]
 800e2bc:	601a      	str	r2, [r3, #0]
    PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ;
 800e2be:	4b1f      	ldr	r3, [pc, #124]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e2c0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800e2c2:	0c1b      	lsrs	r3, r3, #16
 800e2c4:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800e2c8:	ee07 3a90 	vmov	s15, r3
 800e2cc:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e2d0:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800e2d4:	ee37 7a87 	vadd.f32	s14, s15, s14
 800e2d8:	edd7 6a07 	vldr	s13, [r7, #28]
 800e2dc:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800e2e0:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800e2e4:	ee17 2a90 	vmov	r2, s15
 800e2e8:	687b      	ldr	r3, [r7, #4]
 800e2ea:	605a      	str	r2, [r3, #4]
    PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ;
 800e2ec:	4b13      	ldr	r3, [pc, #76]	@ (800e33c <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
 800e2ee:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800e2f0:	0e1b      	lsrs	r3, r3, #24
 800e2f2:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800e2f6:	ee07 3a90 	vmov	s15, r3
 800e2fa:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e2fe:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800e302:	ee37 7a87 	vadd.f32	s14, s15, s14
 800e306:	edd7 6a07 	vldr	s13, [r7, #28]
 800e30a:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800e30e:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800e312:	ee17 2a90 	vmov	r2, s15
 800e316:	687b      	ldr	r3, [r7, #4]
 800e318:	609a      	str	r2, [r3, #8]
    PLL3_Clocks->PLL3_P_Frequency = 0U;
    PLL3_Clocks->PLL3_Q_Frequency = 0U;
    PLL3_Clocks->PLL3_R_Frequency = 0U;
  }

}
 800e31a:	e008      	b.n	800e32e <HAL_RCCEx_GetPLL3ClockFreq+0x282>
    PLL3_Clocks->PLL3_P_Frequency = 0U;
 800e31c:	687b      	ldr	r3, [r7, #4]
 800e31e:	2200      	movs	r2, #0
 800e320:	601a      	str	r2, [r3, #0]
    PLL3_Clocks->PLL3_Q_Frequency = 0U;
 800e322:	687b      	ldr	r3, [r7, #4]
 800e324:	2200      	movs	r2, #0
 800e326:	605a      	str	r2, [r3, #4]
    PLL3_Clocks->PLL3_R_Frequency = 0U;
 800e328:	687b      	ldr	r3, [r7, #4]
 800e32a:	2200      	movs	r2, #0
 800e32c:	609a      	str	r2, [r3, #8]
}
 800e32e:	bf00      	nop
 800e330:	3724      	adds	r7, #36	@ 0x24
 800e332:	46bd      	mov	sp, r7
 800e334:	f85d 7b04 	ldr.w	r7, [sp], #4
 800e338:	4770      	bx	lr
 800e33a:	bf00      	nop
 800e33c:	58024400 	.word	0x58024400
 800e340:	03d09000 	.word	0x03d09000
 800e344:	46000000 	.word	0x46000000
 800e348:	4c742400 	.word	0x4c742400
 800e34c:	4a742400 	.word	0x4a742400
 800e350:	4bbebc20 	.word	0x4bbebc20

0800e354 <HAL_RCCEx_GetPLL1ClockFreq>:
  *         right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
  * @param  PLL1_Clocks structure.
  * @retval None
  */
void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
{
 800e354:	b480      	push	{r7}
 800e356:	b089      	sub	sp, #36	@ 0x24
 800e358:	af00      	add	r7, sp, #0
 800e35a:	6078      	str	r0, [r7, #4]
  uint32_t pllsource, pll1m, pll1fracen, hsivalue;
  float_t fracn1, pll1vco;

  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
 800e35c:	4ba0      	ldr	r3, [pc, #640]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e35e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800e360:	f003 0303 	and.w	r3, r3, #3
 800e364:	61bb      	str	r3, [r7, #24]
  pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
 800e366:	4b9e      	ldr	r3, [pc, #632]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e368:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800e36a:	091b      	lsrs	r3, r3, #4
 800e36c:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
 800e370:	617b      	str	r3, [r7, #20]
  pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
 800e372:	4b9b      	ldr	r3, [pc, #620]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e374:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e376:	f003 0301 	and.w	r3, r3, #1
 800e37a:	613b      	str	r3, [r7, #16]
  fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
 800e37c:	4b98      	ldr	r3, [pc, #608]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e37e:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 800e380:	08db      	lsrs	r3, r3, #3
 800e382:	f3c3 030c 	ubfx	r3, r3, #0, #13
 800e386:	693a      	ldr	r2, [r7, #16]
 800e388:	fb02 f303 	mul.w	r3, r2, r3
 800e38c:	ee07 3a90 	vmov	s15, r3
 800e390:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e394:	edc7 7a03 	vstr	s15, [r7, #12]

  if (pll1m != 0U)
 800e398:	697b      	ldr	r3, [r7, #20]
 800e39a:	2b00      	cmp	r3, #0
 800e39c:	f000 8111 	beq.w	800e5c2 <HAL_RCCEx_GetPLL1ClockFreq+0x26e>
  {
    switch (pllsource)
 800e3a0:	69bb      	ldr	r3, [r7, #24]
 800e3a2:	2b02      	cmp	r3, #2
 800e3a4:	f000 8083 	beq.w	800e4ae <HAL_RCCEx_GetPLL1ClockFreq+0x15a>
 800e3a8:	69bb      	ldr	r3, [r7, #24]
 800e3aa:	2b02      	cmp	r3, #2
 800e3ac:	f200 80a1 	bhi.w	800e4f2 <HAL_RCCEx_GetPLL1ClockFreq+0x19e>
 800e3b0:	69bb      	ldr	r3, [r7, #24]
 800e3b2:	2b00      	cmp	r3, #0
 800e3b4:	d003      	beq.n	800e3be <HAL_RCCEx_GetPLL1ClockFreq+0x6a>
 800e3b6:	69bb      	ldr	r3, [r7, #24]
 800e3b8:	2b01      	cmp	r3, #1
 800e3ba:	d056      	beq.n	800e46a <HAL_RCCEx_GetPLL1ClockFreq+0x116>
 800e3bc:	e099      	b.n	800e4f2 <HAL_RCCEx_GetPLL1ClockFreq+0x19e>
    {

      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */

        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 800e3be:	4b88      	ldr	r3, [pc, #544]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e3c0:	681b      	ldr	r3, [r3, #0]
 800e3c2:	f003 0320 	and.w	r3, r3, #32
 800e3c6:	2b00      	cmp	r3, #0
 800e3c8:	d02d      	beq.n	800e426 <HAL_RCCEx_GetPLL1ClockFreq+0xd2>
        {
          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
 800e3ca:	4b85      	ldr	r3, [pc, #532]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e3cc:	681b      	ldr	r3, [r3, #0]
 800e3ce:	08db      	lsrs	r3, r3, #3
 800e3d0:	f003 0303 	and.w	r3, r3, #3
 800e3d4:	4a83      	ldr	r2, [pc, #524]	@ (800e5e4 <HAL_RCCEx_GetPLL1ClockFreq+0x290>)
 800e3d6:	fa22 f303 	lsr.w	r3, r2, r3
 800e3da:	60bb      	str	r3, [r7, #8]
          pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800e3dc:	68bb      	ldr	r3, [r7, #8]
 800e3de:	ee07 3a90 	vmov	s15, r3
 800e3e2:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800e3e6:	697b      	ldr	r3, [r7, #20]
 800e3e8:	ee07 3a90 	vmov	s15, r3
 800e3ec:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e3f0:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800e3f4:	4b7a      	ldr	r3, [pc, #488]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e3f6:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800e3f8:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800e3fc:	ee07 3a90 	vmov	s15, r3
 800e400:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800e404:	ed97 6a03 	vldr	s12, [r7, #12]
 800e408:	eddf 5a77 	vldr	s11, [pc, #476]	@ 800e5e8 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
 800e40c:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800e410:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800e414:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800e418:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800e41c:	ee67 7a27 	vmul.f32	s15, s14, s15
 800e420:	edc7 7a07 	vstr	s15, [r7, #28]
        }
        else
        {
          pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
        }
        break;
 800e424:	e087      	b.n	800e536 <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>
          pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800e426:	697b      	ldr	r3, [r7, #20]
 800e428:	ee07 3a90 	vmov	s15, r3
 800e42c:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e430:	eddf 6a6e 	vldr	s13, [pc, #440]	@ 800e5ec <HAL_RCCEx_GetPLL1ClockFreq+0x298>
 800e434:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800e438:	4b69      	ldr	r3, [pc, #420]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e43a:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800e43c:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800e440:	ee07 3a90 	vmov	s15, r3
 800e444:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800e448:	ed97 6a03 	vldr	s12, [r7, #12]
 800e44c:	eddf 5a66 	vldr	s11, [pc, #408]	@ 800e5e8 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
 800e450:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800e454:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800e458:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800e45c:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800e460:	ee67 7a27 	vmul.f32	s15, s14, s15
 800e464:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800e468:	e065      	b.n	800e536 <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>
      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
        pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800e46a:	697b      	ldr	r3, [r7, #20]
 800e46c:	ee07 3a90 	vmov	s15, r3
 800e470:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e474:	eddf 6a5e 	vldr	s13, [pc, #376]	@ 800e5f0 <HAL_RCCEx_GetPLL1ClockFreq+0x29c>
 800e478:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800e47c:	4b58      	ldr	r3, [pc, #352]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e47e:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800e480:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800e484:	ee07 3a90 	vmov	s15, r3
 800e488:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800e48c:	ed97 6a03 	vldr	s12, [r7, #12]
 800e490:	eddf 5a55 	vldr	s11, [pc, #340]	@ 800e5e8 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
 800e494:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800e498:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800e49c:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800e4a0:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800e4a4:	ee67 7a27 	vmul.f32	s15, s14, s15
 800e4a8:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800e4ac:	e043      	b.n	800e536 <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>

      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
        pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800e4ae:	697b      	ldr	r3, [r7, #20]
 800e4b0:	ee07 3a90 	vmov	s15, r3
 800e4b4:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e4b8:	eddf 6a4e 	vldr	s13, [pc, #312]	@ 800e5f4 <HAL_RCCEx_GetPLL1ClockFreq+0x2a0>
 800e4bc:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800e4c0:	4b47      	ldr	r3, [pc, #284]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e4c2:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800e4c4:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800e4c8:	ee07 3a90 	vmov	s15, r3
 800e4cc:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800e4d0:	ed97 6a03 	vldr	s12, [r7, #12]
 800e4d4:	eddf 5a44 	vldr	s11, [pc, #272]	@ 800e5e8 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
 800e4d8:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800e4dc:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800e4e0:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800e4e4:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800e4e8:	ee67 7a27 	vmul.f32	s15, s14, s15
 800e4ec:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800e4f0:	e021      	b.n	800e536 <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>

      default:
        pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
 800e4f2:	697b      	ldr	r3, [r7, #20]
 800e4f4:	ee07 3a90 	vmov	s15, r3
 800e4f8:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e4fc:	eddf 6a3b 	vldr	s13, [pc, #236]	@ 800e5ec <HAL_RCCEx_GetPLL1ClockFreq+0x298>
 800e500:	ee86 7aa7 	vdiv.f32	s14, s13, s15
 800e504:	4b36      	ldr	r3, [pc, #216]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e506:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800e508:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800e50c:	ee07 3a90 	vmov	s15, r3
 800e510:	eef8 6a67 	vcvt.f32.u32	s13, s15
 800e514:	ed97 6a03 	vldr	s12, [r7, #12]
 800e518:	eddf 5a33 	vldr	s11, [pc, #204]	@ 800e5e8 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
 800e51c:	eec6 7a25 	vdiv.f32	s15, s12, s11
 800e520:	ee76 7aa7 	vadd.f32	s15, s13, s15
 800e524:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800e528:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800e52c:	ee67 7a27 	vmul.f32	s15, s14, s15
 800e530:	edc7 7a07 	vstr	s15, [r7, #28]
        break;
 800e534:	bf00      	nop
    }

    PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9)  + (float_t)1)) ;
 800e536:	4b2a      	ldr	r3, [pc, #168]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e538:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800e53a:	0a5b      	lsrs	r3, r3, #9
 800e53c:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800e540:	ee07 3a90 	vmov	s15, r3
 800e544:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e548:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800e54c:	ee37 7a87 	vadd.f32	s14, s15, s14
 800e550:	edd7 6a07 	vldr	s13, [r7, #28]
 800e554:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800e558:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800e55c:	ee17 2a90 	vmov	r2, s15
 800e560:	687b      	ldr	r3, [r7, #4]
 800e562:	601a      	str	r2, [r3, #0]
    PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ;
 800e564:	4b1e      	ldr	r3, [pc, #120]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e566:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800e568:	0c1b      	lsrs	r3, r3, #16
 800e56a:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800e56e:	ee07 3a90 	vmov	s15, r3
 800e572:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e576:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800e57a:	ee37 7a87 	vadd.f32	s14, s15, s14
 800e57e:	edd7 6a07 	vldr	s13, [r7, #28]
 800e582:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800e586:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800e58a:	ee17 2a90 	vmov	r2, s15
 800e58e:	687b      	ldr	r3, [r7, #4]
 800e590:	605a      	str	r2, [r3, #4]
    PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ;
 800e592:	4b13      	ldr	r3, [pc, #76]	@ (800e5e0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
 800e594:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 800e596:	0e1b      	lsrs	r3, r3, #24
 800e598:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 800e59c:	ee07 3a90 	vmov	s15, r3
 800e5a0:	eef8 7a67 	vcvt.f32.u32	s15, s15
 800e5a4:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800e5a8:	ee37 7a87 	vadd.f32	s14, s15, s14
 800e5ac:	edd7 6a07 	vldr	s13, [r7, #28]
 800e5b0:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800e5b4:	eefc 7ae7 	vcvt.u32.f32	s15, s15
 800e5b8:	ee17 2a90 	vmov	r2, s15
 800e5bc:	687b      	ldr	r3, [r7, #4]
 800e5be:	609a      	str	r2, [r3, #8]
    PLL1_Clocks->PLL1_P_Frequency = 0U;
    PLL1_Clocks->PLL1_Q_Frequency = 0U;
    PLL1_Clocks->PLL1_R_Frequency = 0U;
  }

}
 800e5c0:	e008      	b.n	800e5d4 <HAL_RCCEx_GetPLL1ClockFreq+0x280>
    PLL1_Clocks->PLL1_P_Frequency = 0U;
 800e5c2:	687b      	ldr	r3, [r7, #4]
 800e5c4:	2200      	movs	r2, #0
 800e5c6:	601a      	str	r2, [r3, #0]
    PLL1_Clocks->PLL1_Q_Frequency = 0U;
 800e5c8:	687b      	ldr	r3, [r7, #4]
 800e5ca:	2200      	movs	r2, #0
 800e5cc:	605a      	str	r2, [r3, #4]
    PLL1_Clocks->PLL1_R_Frequency = 0U;
 800e5ce:	687b      	ldr	r3, [r7, #4]
 800e5d0:	2200      	movs	r2, #0
 800e5d2:	609a      	str	r2, [r3, #8]
}
 800e5d4:	bf00      	nop
 800e5d6:	3724      	adds	r7, #36	@ 0x24
 800e5d8:	46bd      	mov	sp, r7
 800e5da:	f85d 7b04 	ldr.w	r7, [sp], #4
 800e5de:	4770      	bx	lr
 800e5e0:	58024400 	.word	0x58024400
 800e5e4:	03d09000 	.word	0x03d09000
 800e5e8:	46000000 	.word	0x46000000
 800e5ec:	4c742400 	.word	0x4c742400
 800e5f0:	4a742400 	.word	0x4a742400
 800e5f4:	4bbebc20 	.word	0x4bbebc20

0800e5f8 <RCCEx_PLL2_Config>:
  * @note   PLL2 is temporary disabled to apply new parameters
  *
  * @retval HAL status
  */
static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
{
 800e5f8:	b580      	push	{r7, lr}
 800e5fa:	b084      	sub	sp, #16
 800e5fc:	af00      	add	r7, sp, #0
 800e5fe:	6078      	str	r0, [r7, #4]
 800e600:	6039      	str	r1, [r7, #0]

  uint32_t tickstart;
  HAL_StatusTypeDef status = HAL_OK;
 800e602:	2300      	movs	r3, #0
 800e604:	73fb      	strb	r3, [r7, #15]
  assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
  assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
  assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));

  /* Check that PLL2 OSC clock source is already set */
  if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
 800e606:	4b53      	ldr	r3, [pc, #332]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e608:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800e60a:	f003 0303 	and.w	r3, r3, #3
 800e60e:	2b03      	cmp	r3, #3
 800e610:	d101      	bne.n	800e616 <RCCEx_PLL2_Config+0x1e>
  {
    return HAL_ERROR;
 800e612:	2301      	movs	r3, #1
 800e614:	e099      	b.n	800e74a <RCCEx_PLL2_Config+0x152>


  else
  {
    /* Disable  PLL2. */
    __HAL_RCC_PLL2_DISABLE();
 800e616:	4b4f      	ldr	r3, [pc, #316]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e618:	681b      	ldr	r3, [r3, #0]
 800e61a:	4a4e      	ldr	r2, [pc, #312]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e61c:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 800e620:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 800e622:	f7f6 ff0b 	bl	800543c <HAL_GetTick>
 800e626:	60b8      	str	r0, [r7, #8]

    /* Wait till PLL is disabled */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
 800e628:	e008      	b.n	800e63c <RCCEx_PLL2_Config+0x44>
    {
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
 800e62a:	f7f6 ff07 	bl	800543c <HAL_GetTick>
 800e62e:	4602      	mov	r2, r0
 800e630:	68bb      	ldr	r3, [r7, #8]
 800e632:	1ad3      	subs	r3, r2, r3
 800e634:	2b02      	cmp	r3, #2
 800e636:	d901      	bls.n	800e63c <RCCEx_PLL2_Config+0x44>
      {
        return HAL_TIMEOUT;
 800e638:	2303      	movs	r3, #3
 800e63a:	e086      	b.n	800e74a <RCCEx_PLL2_Config+0x152>
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
 800e63c:	4b45      	ldr	r3, [pc, #276]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e63e:	681b      	ldr	r3, [r3, #0]
 800e640:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800e644:	2b00      	cmp	r3, #0
 800e646:	d1f0      	bne.n	800e62a <RCCEx_PLL2_Config+0x32>
      }
    }

    /* Configure PLL2 multiplication and division factors. */
    __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
 800e648:	4b42      	ldr	r3, [pc, #264]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e64a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800e64c:	f423 327c 	bic.w	r2, r3, #258048	@ 0x3f000
 800e650:	687b      	ldr	r3, [r7, #4]
 800e652:	681b      	ldr	r3, [r3, #0]
 800e654:	031b      	lsls	r3, r3, #12
 800e656:	493f      	ldr	r1, [pc, #252]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e658:	4313      	orrs	r3, r2
 800e65a:	628b      	str	r3, [r1, #40]	@ 0x28
 800e65c:	687b      	ldr	r3, [r7, #4]
 800e65e:	685b      	ldr	r3, [r3, #4]
 800e660:	3b01      	subs	r3, #1
 800e662:	f3c3 0208 	ubfx	r2, r3, #0, #9
 800e666:	687b      	ldr	r3, [r7, #4]
 800e668:	689b      	ldr	r3, [r3, #8]
 800e66a:	3b01      	subs	r3, #1
 800e66c:	025b      	lsls	r3, r3, #9
 800e66e:	b29b      	uxth	r3, r3
 800e670:	431a      	orrs	r2, r3
 800e672:	687b      	ldr	r3, [r7, #4]
 800e674:	68db      	ldr	r3, [r3, #12]
 800e676:	3b01      	subs	r3, #1
 800e678:	041b      	lsls	r3, r3, #16
 800e67a:	f403 03fe 	and.w	r3, r3, #8323072	@ 0x7f0000
 800e67e:	431a      	orrs	r2, r3
 800e680:	687b      	ldr	r3, [r7, #4]
 800e682:	691b      	ldr	r3, [r3, #16]
 800e684:	3b01      	subs	r3, #1
 800e686:	061b      	lsls	r3, r3, #24
 800e688:	f003 43fe 	and.w	r3, r3, #2130706432	@ 0x7f000000
 800e68c:	4931      	ldr	r1, [pc, #196]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e68e:	4313      	orrs	r3, r2
 800e690:	638b      	str	r3, [r1, #56]	@ 0x38
                          pll2->PLL2P,
                          pll2->PLL2Q,
                          pll2->PLL2R);

    /* Select PLL2 input reference frequency range: VCI */
    __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
 800e692:	4b30      	ldr	r3, [pc, #192]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e694:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e696:	f023 02c0 	bic.w	r2, r3, #192	@ 0xc0
 800e69a:	687b      	ldr	r3, [r7, #4]
 800e69c:	695b      	ldr	r3, [r3, #20]
 800e69e:	492d      	ldr	r1, [pc, #180]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e6a0:	4313      	orrs	r3, r2
 800e6a2:	62cb      	str	r3, [r1, #44]	@ 0x2c

    /* Select PLL2 output frequency range : VCO */
    __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
 800e6a4:	4b2b      	ldr	r3, [pc, #172]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e6a6:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e6a8:	f023 0220 	bic.w	r2, r3, #32
 800e6ac:	687b      	ldr	r3, [r7, #4]
 800e6ae:	699b      	ldr	r3, [r3, #24]
 800e6b0:	4928      	ldr	r1, [pc, #160]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e6b2:	4313      	orrs	r3, r2
 800e6b4:	62cb      	str	r3, [r1, #44]	@ 0x2c

    /* Disable PLL2FRACN . */
    __HAL_RCC_PLL2FRACN_DISABLE();
 800e6b6:	4b27      	ldr	r3, [pc, #156]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e6b8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e6ba:	4a26      	ldr	r2, [pc, #152]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e6bc:	f023 0310 	bic.w	r3, r3, #16
 800e6c0:	62d3      	str	r3, [r2, #44]	@ 0x2c

    /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
    __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
 800e6c2:	4b24      	ldr	r3, [pc, #144]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e6c4:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 800e6c6:	4b24      	ldr	r3, [pc, #144]	@ (800e758 <RCCEx_PLL2_Config+0x160>)
 800e6c8:	4013      	ands	r3, r2
 800e6ca:	687a      	ldr	r2, [r7, #4]
 800e6cc:	69d2      	ldr	r2, [r2, #28]
 800e6ce:	00d2      	lsls	r2, r2, #3
 800e6d0:	4920      	ldr	r1, [pc, #128]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e6d2:	4313      	orrs	r3, r2
 800e6d4:	63cb      	str	r3, [r1, #60]	@ 0x3c

    /* Enable PLL2FRACN . */
    __HAL_RCC_PLL2FRACN_ENABLE();
 800e6d6:	4b1f      	ldr	r3, [pc, #124]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e6d8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e6da:	4a1e      	ldr	r2, [pc, #120]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e6dc:	f043 0310 	orr.w	r3, r3, #16
 800e6e0:	62d3      	str	r3, [r2, #44]	@ 0x2c

    /* Enable the PLL2 clock output */
    if (Divider == DIVIDER_P_UPDATE)
 800e6e2:	683b      	ldr	r3, [r7, #0]
 800e6e4:	2b00      	cmp	r3, #0
 800e6e6:	d106      	bne.n	800e6f6 <RCCEx_PLL2_Config+0xfe>
    {
      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
 800e6e8:	4b1a      	ldr	r3, [pc, #104]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e6ea:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e6ec:	4a19      	ldr	r2, [pc, #100]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e6ee:	f443 2300 	orr.w	r3, r3, #524288	@ 0x80000
 800e6f2:	62d3      	str	r3, [r2, #44]	@ 0x2c
 800e6f4:	e00f      	b.n	800e716 <RCCEx_PLL2_Config+0x11e>
    }
    else if (Divider == DIVIDER_Q_UPDATE)
 800e6f6:	683b      	ldr	r3, [r7, #0]
 800e6f8:	2b01      	cmp	r3, #1
 800e6fa:	d106      	bne.n	800e70a <RCCEx_PLL2_Config+0x112>
    {
      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
 800e6fc:	4b15      	ldr	r3, [pc, #84]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e6fe:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e700:	4a14      	ldr	r2, [pc, #80]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e702:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 800e706:	62d3      	str	r3, [r2, #44]	@ 0x2c
 800e708:	e005      	b.n	800e716 <RCCEx_PLL2_Config+0x11e>
    }
    else
    {
      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
 800e70a:	4b12      	ldr	r3, [pc, #72]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e70c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e70e:	4a11      	ldr	r2, [pc, #68]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e710:	f443 1300 	orr.w	r3, r3, #2097152	@ 0x200000
 800e714:	62d3      	str	r3, [r2, #44]	@ 0x2c
    }

    /* Enable  PLL2. */
    __HAL_RCC_PLL2_ENABLE();
 800e716:	4b0f      	ldr	r3, [pc, #60]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e718:	681b      	ldr	r3, [r3, #0]
 800e71a:	4a0e      	ldr	r2, [pc, #56]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e71c:	f043 6380 	orr.w	r3, r3, #67108864	@ 0x4000000
 800e720:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 800e722:	f7f6 fe8b 	bl	800543c <HAL_GetTick>
 800e726:	60b8      	str	r0, [r7, #8]

    /* Wait till PLL2 is ready */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
 800e728:	e008      	b.n	800e73c <RCCEx_PLL2_Config+0x144>
    {
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
 800e72a:	f7f6 fe87 	bl	800543c <HAL_GetTick>
 800e72e:	4602      	mov	r2, r0
 800e730:	68bb      	ldr	r3, [r7, #8]
 800e732:	1ad3      	subs	r3, r2, r3
 800e734:	2b02      	cmp	r3, #2
 800e736:	d901      	bls.n	800e73c <RCCEx_PLL2_Config+0x144>
      {
        return HAL_TIMEOUT;
 800e738:	2303      	movs	r3, #3
 800e73a:	e006      	b.n	800e74a <RCCEx_PLL2_Config+0x152>
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
 800e73c:	4b05      	ldr	r3, [pc, #20]	@ (800e754 <RCCEx_PLL2_Config+0x15c>)
 800e73e:	681b      	ldr	r3, [r3, #0]
 800e740:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 800e744:	2b00      	cmp	r3, #0
 800e746:	d0f0      	beq.n	800e72a <RCCEx_PLL2_Config+0x132>
    }

  }


  return status;
 800e748:	7bfb      	ldrb	r3, [r7, #15]
}
 800e74a:	4618      	mov	r0, r3
 800e74c:	3710      	adds	r7, #16
 800e74e:	46bd      	mov	sp, r7
 800e750:	bd80      	pop	{r7, pc}
 800e752:	bf00      	nop
 800e754:	58024400 	.word	0x58024400
 800e758:	ffff0007 	.word	0xffff0007

0800e75c <RCCEx_PLL3_Config>:
  * @note   PLL3 is temporary disabled to apply new parameters
  *
  * @retval HAL status
  */
static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
{
 800e75c:	b580      	push	{r7, lr}
 800e75e:	b084      	sub	sp, #16
 800e760:	af00      	add	r7, sp, #0
 800e762:	6078      	str	r0, [r7, #4]
 800e764:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;
  HAL_StatusTypeDef status = HAL_OK;
 800e766:	2300      	movs	r3, #0
 800e768:	73fb      	strb	r3, [r7, #15]
  assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
  assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
  assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));

  /* Check that PLL3 OSC clock source is already set */
  if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
 800e76a:	4b53      	ldr	r3, [pc, #332]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e76c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800e76e:	f003 0303 	and.w	r3, r3, #3
 800e772:	2b03      	cmp	r3, #3
 800e774:	d101      	bne.n	800e77a <RCCEx_PLL3_Config+0x1e>
  {
    return HAL_ERROR;
 800e776:	2301      	movs	r3, #1
 800e778:	e099      	b.n	800e8ae <RCCEx_PLL3_Config+0x152>


  else
  {
    /* Disable  PLL3. */
    __HAL_RCC_PLL3_DISABLE();
 800e77a:	4b4f      	ldr	r3, [pc, #316]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e77c:	681b      	ldr	r3, [r3, #0]
 800e77e:	4a4e      	ldr	r2, [pc, #312]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e780:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 800e784:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 800e786:	f7f6 fe59 	bl	800543c <HAL_GetTick>
 800e78a:	60b8      	str	r0, [r7, #8]
    /* Wait till PLL3 is ready */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
 800e78c:	e008      	b.n	800e7a0 <RCCEx_PLL3_Config+0x44>
    {
      if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
 800e78e:	f7f6 fe55 	bl	800543c <HAL_GetTick>
 800e792:	4602      	mov	r2, r0
 800e794:	68bb      	ldr	r3, [r7, #8]
 800e796:	1ad3      	subs	r3, r2, r3
 800e798:	2b02      	cmp	r3, #2
 800e79a:	d901      	bls.n	800e7a0 <RCCEx_PLL3_Config+0x44>
      {
        return HAL_TIMEOUT;
 800e79c:	2303      	movs	r3, #3
 800e79e:	e086      	b.n	800e8ae <RCCEx_PLL3_Config+0x152>
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
 800e7a0:	4b45      	ldr	r3, [pc, #276]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e7a2:	681b      	ldr	r3, [r3, #0]
 800e7a4:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800e7a8:	2b00      	cmp	r3, #0
 800e7aa:	d1f0      	bne.n	800e78e <RCCEx_PLL3_Config+0x32>
      }
    }

    /* Configure the PLL3  multiplication and division factors. */
    __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
 800e7ac:	4b42      	ldr	r3, [pc, #264]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e7ae:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 800e7b0:	f023 727c 	bic.w	r2, r3, #66060288	@ 0x3f00000
 800e7b4:	687b      	ldr	r3, [r7, #4]
 800e7b6:	681b      	ldr	r3, [r3, #0]
 800e7b8:	051b      	lsls	r3, r3, #20
 800e7ba:	493f      	ldr	r1, [pc, #252]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e7bc:	4313      	orrs	r3, r2
 800e7be:	628b      	str	r3, [r1, #40]	@ 0x28
 800e7c0:	687b      	ldr	r3, [r7, #4]
 800e7c2:	685b      	ldr	r3, [r3, #4]
 800e7c4:	3b01      	subs	r3, #1
 800e7c6:	f3c3 0208 	ubfx	r2, r3, #0, #9
 800e7ca:	687b      	ldr	r3, [r7, #4]
 800e7cc:	689b      	ldr	r3, [r3, #8]
 800e7ce:	3b01      	subs	r3, #1
 800e7d0:	025b      	lsls	r3, r3, #9
 800e7d2:	b29b      	uxth	r3, r3
 800e7d4:	431a      	orrs	r2, r3
 800e7d6:	687b      	ldr	r3, [r7, #4]
 800e7d8:	68db      	ldr	r3, [r3, #12]
 800e7da:	3b01      	subs	r3, #1
 800e7dc:	041b      	lsls	r3, r3, #16
 800e7de:	f403 03fe 	and.w	r3, r3, #8323072	@ 0x7f0000
 800e7e2:	431a      	orrs	r2, r3
 800e7e4:	687b      	ldr	r3, [r7, #4]
 800e7e6:	691b      	ldr	r3, [r3, #16]
 800e7e8:	3b01      	subs	r3, #1
 800e7ea:	061b      	lsls	r3, r3, #24
 800e7ec:	f003 43fe 	and.w	r3, r3, #2130706432	@ 0x7f000000
 800e7f0:	4931      	ldr	r1, [pc, #196]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e7f2:	4313      	orrs	r3, r2
 800e7f4:	640b      	str	r3, [r1, #64]	@ 0x40
                          pll3->PLL3P,
                          pll3->PLL3Q,
                          pll3->PLL3R);

    /* Select PLL3 input reference frequency range: VCI */
    __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
 800e7f6:	4b30      	ldr	r3, [pc, #192]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e7f8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e7fa:	f423 6240 	bic.w	r2, r3, #3072	@ 0xc00
 800e7fe:	687b      	ldr	r3, [r7, #4]
 800e800:	695b      	ldr	r3, [r3, #20]
 800e802:	492d      	ldr	r1, [pc, #180]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e804:	4313      	orrs	r3, r2
 800e806:	62cb      	str	r3, [r1, #44]	@ 0x2c

    /* Select PLL3 output frequency range : VCO */
    __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
 800e808:	4b2b      	ldr	r3, [pc, #172]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e80a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e80c:	f423 7200 	bic.w	r2, r3, #512	@ 0x200
 800e810:	687b      	ldr	r3, [r7, #4]
 800e812:	699b      	ldr	r3, [r3, #24]
 800e814:	4928      	ldr	r1, [pc, #160]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e816:	4313      	orrs	r3, r2
 800e818:	62cb      	str	r3, [r1, #44]	@ 0x2c

    /* Disable PLL3FRACN . */
    __HAL_RCC_PLL3FRACN_DISABLE();
 800e81a:	4b27      	ldr	r3, [pc, #156]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e81c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e81e:	4a26      	ldr	r2, [pc, #152]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e820:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 800e824:	62d3      	str	r3, [r2, #44]	@ 0x2c

    /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
    __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
 800e826:	4b24      	ldr	r3, [pc, #144]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e828:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
 800e82a:	4b24      	ldr	r3, [pc, #144]	@ (800e8bc <RCCEx_PLL3_Config+0x160>)
 800e82c:	4013      	ands	r3, r2
 800e82e:	687a      	ldr	r2, [r7, #4]
 800e830:	69d2      	ldr	r2, [r2, #28]
 800e832:	00d2      	lsls	r2, r2, #3
 800e834:	4920      	ldr	r1, [pc, #128]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e836:	4313      	orrs	r3, r2
 800e838:	644b      	str	r3, [r1, #68]	@ 0x44

    /* Enable PLL3FRACN . */
    __HAL_RCC_PLL3FRACN_ENABLE();
 800e83a:	4b1f      	ldr	r3, [pc, #124]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e83c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e83e:	4a1e      	ldr	r2, [pc, #120]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e840:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 800e844:	62d3      	str	r3, [r2, #44]	@ 0x2c

    /* Enable the PLL3 clock output */
    if (Divider == DIVIDER_P_UPDATE)
 800e846:	683b      	ldr	r3, [r7, #0]
 800e848:	2b00      	cmp	r3, #0
 800e84a:	d106      	bne.n	800e85a <RCCEx_PLL3_Config+0xfe>
    {
      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
 800e84c:	4b1a      	ldr	r3, [pc, #104]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e84e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e850:	4a19      	ldr	r2, [pc, #100]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e852:	f443 0380 	orr.w	r3, r3, #4194304	@ 0x400000
 800e856:	62d3      	str	r3, [r2, #44]	@ 0x2c
 800e858:	e00f      	b.n	800e87a <RCCEx_PLL3_Config+0x11e>
    }
    else if (Divider == DIVIDER_Q_UPDATE)
 800e85a:	683b      	ldr	r3, [r7, #0]
 800e85c:	2b01      	cmp	r3, #1
 800e85e:	d106      	bne.n	800e86e <RCCEx_PLL3_Config+0x112>
    {
      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
 800e860:	4b15      	ldr	r3, [pc, #84]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e862:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e864:	4a14      	ldr	r2, [pc, #80]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e866:	f443 0300 	orr.w	r3, r3, #8388608	@ 0x800000
 800e86a:	62d3      	str	r3, [r2, #44]	@ 0x2c
 800e86c:	e005      	b.n	800e87a <RCCEx_PLL3_Config+0x11e>
    }
    else
    {
      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
 800e86e:	4b12      	ldr	r3, [pc, #72]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e870:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 800e872:	4a11      	ldr	r2, [pc, #68]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e874:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 800e878:	62d3      	str	r3, [r2, #44]	@ 0x2c
    }

    /* Enable  PLL3. */
    __HAL_RCC_PLL3_ENABLE();
 800e87a:	4b0f      	ldr	r3, [pc, #60]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e87c:	681b      	ldr	r3, [r3, #0]
 800e87e:	4a0e      	ldr	r2, [pc, #56]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e880:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 800e884:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 800e886:	f7f6 fdd9 	bl	800543c <HAL_GetTick>
 800e88a:	60b8      	str	r0, [r7, #8]

    /* Wait till PLL3 is ready */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
 800e88c:	e008      	b.n	800e8a0 <RCCEx_PLL3_Config+0x144>
    {
      if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
 800e88e:	f7f6 fdd5 	bl	800543c <HAL_GetTick>
 800e892:	4602      	mov	r2, r0
 800e894:	68bb      	ldr	r3, [r7, #8]
 800e896:	1ad3      	subs	r3, r2, r3
 800e898:	2b02      	cmp	r3, #2
 800e89a:	d901      	bls.n	800e8a0 <RCCEx_PLL3_Config+0x144>
      {
        return HAL_TIMEOUT;
 800e89c:	2303      	movs	r3, #3
 800e89e:	e006      	b.n	800e8ae <RCCEx_PLL3_Config+0x152>
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
 800e8a0:	4b05      	ldr	r3, [pc, #20]	@ (800e8b8 <RCCEx_PLL3_Config+0x15c>)
 800e8a2:	681b      	ldr	r3, [r3, #0]
 800e8a4:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
 800e8a8:	2b00      	cmp	r3, #0
 800e8aa:	d0f0      	beq.n	800e88e <RCCEx_PLL3_Config+0x132>
    }

  }


  return status;
 800e8ac:	7bfb      	ldrb	r3, [r7, #15]
}
 800e8ae:	4618      	mov	r0, r3
 800e8b0:	3710      	adds	r7, #16
 800e8b2:	46bd      	mov	sp, r7
 800e8b4:	bd80      	pop	{r7, pc}
 800e8b6:	bf00      	nop
 800e8b8:	58024400 	.word	0x58024400
 800e8bc:	ffff0007 	.word	0xffff0007

0800e8c0 <HAL_RNG_Init>:
  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
  *                the configuration information for RNG.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
 800e8c0:	b580      	push	{r7, lr}
 800e8c2:	b084      	sub	sp, #16
 800e8c4:	af00      	add	r7, sp, #0
 800e8c6:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  /* Check the RNG handle allocation */
  if (hrng == NULL)
 800e8c8:	687b      	ldr	r3, [r7, #4]
 800e8ca:	2b00      	cmp	r3, #0
 800e8cc:	d101      	bne.n	800e8d2 <HAL_RNG_Init+0x12>
  {
    return HAL_ERROR;
 800e8ce:	2301      	movs	r3, #1
 800e8d0:	e054      	b.n	800e97c <HAL_RNG_Init+0xbc>

    /* Init the low level hardware */
    hrng->MspInitCallback(hrng);
  }
#else
  if (hrng->State == HAL_RNG_STATE_RESET)
 800e8d2:	687b      	ldr	r3, [r7, #4]
 800e8d4:	7a5b      	ldrb	r3, [r3, #9]
 800e8d6:	b2db      	uxtb	r3, r3
 800e8d8:	2b00      	cmp	r3, #0
 800e8da:	d105      	bne.n	800e8e8 <HAL_RNG_Init+0x28>
  {
    /* Allocate lock resource and initialize it */
    hrng->Lock = HAL_UNLOCKED;
 800e8dc:	687b      	ldr	r3, [r7, #4]
 800e8de:	2200      	movs	r2, #0
 800e8e0:	721a      	strb	r2, [r3, #8]

    /* Init the low level hardware */
    HAL_RNG_MspInit(hrng);
 800e8e2:	6878      	ldr	r0, [r7, #4]
 800e8e4:	f7f5 f830 	bl	8003948 <HAL_RNG_MspInit>
  }
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */

  /* Change RNG peripheral state */
  hrng->State = HAL_RNG_STATE_BUSY;
 800e8e8:	687b      	ldr	r3, [r7, #4]
 800e8ea:	2202      	movs	r2, #2
 800e8ec:	725a      	strb	r2, [r3, #9]
      }
    }
  }
#else
  /* Clock Error Detection Configuration */
  MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
 800e8ee:	687b      	ldr	r3, [r7, #4]
 800e8f0:	681b      	ldr	r3, [r3, #0]
 800e8f2:	681b      	ldr	r3, [r3, #0]
 800e8f4:	f023 0120 	bic.w	r1, r3, #32
 800e8f8:	687b      	ldr	r3, [r7, #4]
 800e8fa:	685a      	ldr	r2, [r3, #4]
 800e8fc:	687b      	ldr	r3, [r7, #4]
 800e8fe:	681b      	ldr	r3, [r3, #0]
 800e900:	430a      	orrs	r2, r1
 800e902:	601a      	str	r2, [r3, #0]
#endif /* RNG_CR_CONDRST */

  /* Enable the RNG Peripheral */
  __HAL_RNG_ENABLE(hrng);
 800e904:	687b      	ldr	r3, [r7, #4]
 800e906:	681b      	ldr	r3, [r3, #0]
 800e908:	681a      	ldr	r2, [r3, #0]
 800e90a:	687b      	ldr	r3, [r7, #4]
 800e90c:	681b      	ldr	r3, [r3, #0]
 800e90e:	f042 0204 	orr.w	r2, r2, #4
 800e912:	601a      	str	r2, [r3, #0]

  /* verify that no seed error */
  if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
 800e914:	687b      	ldr	r3, [r7, #4]
 800e916:	681b      	ldr	r3, [r3, #0]
 800e918:	685b      	ldr	r3, [r3, #4]
 800e91a:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800e91e:	2b40      	cmp	r3, #64	@ 0x40
 800e920:	d104      	bne.n	800e92c <HAL_RNG_Init+0x6c>
  {
    hrng->State = HAL_RNG_STATE_ERROR;
 800e922:	687b      	ldr	r3, [r7, #4]
 800e924:	2204      	movs	r2, #4
 800e926:	725a      	strb	r2, [r3, #9]
    return HAL_ERROR;
 800e928:	2301      	movs	r3, #1
 800e92a:	e027      	b.n	800e97c <HAL_RNG_Init+0xbc>
  }
  /* Get tick */
  tickstart = HAL_GetTick();
 800e92c:	f7f6 fd86 	bl	800543c <HAL_GetTick>
 800e930:	60f8      	str	r0, [r7, #12]
  /* Check if data register contains valid random data */
  while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
 800e932:	e015      	b.n	800e960 <HAL_RNG_Init+0xa0>
  {
    if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
 800e934:	f7f6 fd82 	bl	800543c <HAL_GetTick>
 800e938:	4602      	mov	r2, r0
 800e93a:	68fb      	ldr	r3, [r7, #12]
 800e93c:	1ad3      	subs	r3, r2, r3
 800e93e:	2b02      	cmp	r3, #2
 800e940:	d90e      	bls.n	800e960 <HAL_RNG_Init+0xa0>
    {
      /* New check to avoid false timeout detection in case of preemption */
      if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
 800e942:	687b      	ldr	r3, [r7, #4]
 800e944:	681b      	ldr	r3, [r3, #0]
 800e946:	685b      	ldr	r3, [r3, #4]
 800e948:	f003 0304 	and.w	r3, r3, #4
 800e94c:	2b04      	cmp	r3, #4
 800e94e:	d107      	bne.n	800e960 <HAL_RNG_Init+0xa0>
      {
        hrng->State = HAL_RNG_STATE_ERROR;
 800e950:	687b      	ldr	r3, [r7, #4]
 800e952:	2204      	movs	r2, #4
 800e954:	725a      	strb	r2, [r3, #9]
        hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
 800e956:	687b      	ldr	r3, [r7, #4]
 800e958:	2202      	movs	r2, #2
 800e95a:	60da      	str	r2, [r3, #12]
        return HAL_ERROR;
 800e95c:	2301      	movs	r3, #1
 800e95e:	e00d      	b.n	800e97c <HAL_RNG_Init+0xbc>
  while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
 800e960:	687b      	ldr	r3, [r7, #4]
 800e962:	681b      	ldr	r3, [r3, #0]
 800e964:	685b      	ldr	r3, [r3, #4]
 800e966:	f003 0304 	and.w	r3, r3, #4
 800e96a:	2b04      	cmp	r3, #4
 800e96c:	d0e2      	beq.n	800e934 <HAL_RNG_Init+0x74>
      }
    }
  }

  /* Initialize the RNG state */
  hrng->State = HAL_RNG_STATE_READY;
 800e96e:	687b      	ldr	r3, [r7, #4]
 800e970:	2201      	movs	r2, #1
 800e972:	725a      	strb	r2, [r3, #9]

  /* Initialise the error code */
  hrng->ErrorCode = HAL_RNG_ERROR_NONE;
 800e974:	687b      	ldr	r3, [r7, #4]
 800e976:	2200      	movs	r2, #0
 800e978:	60da      	str	r2, [r3, #12]

  /* Return function status */
  return HAL_OK;
 800e97a:	2300      	movs	r3, #0
}
 800e97c:	4618      	mov	r0, r3
 800e97e:	3710      	adds	r7, #16
 800e980:	46bd      	mov	sp, r7
 800e982:	bd80      	pop	{r7, pc}

0800e984 <HAL_TIM_Base_Init>:
  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
 800e984:	b580      	push	{r7, lr}
 800e986:	b082      	sub	sp, #8
 800e988:	af00      	add	r7, sp, #0
 800e98a:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 800e98c:	687b      	ldr	r3, [r7, #4]
 800e98e:	2b00      	cmp	r3, #0
 800e990:	d101      	bne.n	800e996 <HAL_TIM_Base_Init+0x12>
  {
    return HAL_ERROR;
 800e992:	2301      	movs	r3, #1
 800e994:	e049      	b.n	800ea2a <HAL_TIM_Base_Init+0xa6>
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 800e996:	687b      	ldr	r3, [r7, #4]
 800e998:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 800e99c:	b2db      	uxtb	r3, r3
 800e99e:	2b00      	cmp	r3, #0
 800e9a0:	d106      	bne.n	800e9b0 <HAL_TIM_Base_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 800e9a2:	687b      	ldr	r3, [r7, #4]
 800e9a4:	2200      	movs	r2, #0
 800e9a6:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->Base_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_TIM_Base_MspInit(htim);
 800e9aa:	6878      	ldr	r0, [r7, #4]
 800e9ac:	f7f5 f840 	bl	8003a30 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 800e9b0:	687b      	ldr	r3, [r7, #4]
 800e9b2:	2202      	movs	r2, #2
 800e9b4:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Set the Time Base configuration */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 800e9b8:	687b      	ldr	r3, [r7, #4]
 800e9ba:	681a      	ldr	r2, [r3, #0]
 800e9bc:	687b      	ldr	r3, [r7, #4]
 800e9be:	3304      	adds	r3, #4
 800e9c0:	4619      	mov	r1, r3
 800e9c2:	4610      	mov	r0, r2
 800e9c4:	f001 f918 	bl	800fbf8 <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 800e9c8:	687b      	ldr	r3, [r7, #4]
 800e9ca:	2201      	movs	r2, #1
 800e9cc:	f883 2048 	strb.w	r2, [r3, #72]	@ 0x48

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 800e9d0:	687b      	ldr	r3, [r7, #4]
 800e9d2:	2201      	movs	r2, #1
 800e9d4:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 800e9d8:	687b      	ldr	r3, [r7, #4]
 800e9da:	2201      	movs	r2, #1
 800e9dc:	f883 203f 	strb.w	r2, [r3, #63]	@ 0x3f
 800e9e0:	687b      	ldr	r3, [r7, #4]
 800e9e2:	2201      	movs	r2, #1
 800e9e4:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 800e9e8:	687b      	ldr	r3, [r7, #4]
 800e9ea:	2201      	movs	r2, #1
 800e9ec:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 800e9f0:	687b      	ldr	r3, [r7, #4]
 800e9f2:	2201      	movs	r2, #1
 800e9f4:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
 800e9f8:	687b      	ldr	r3, [r7, #4]
 800e9fa:	2201      	movs	r2, #1
 800e9fc:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 800ea00:	687b      	ldr	r3, [r7, #4]
 800ea02:	2201      	movs	r2, #1
 800ea04:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 800ea08:	687b      	ldr	r3, [r7, #4]
 800ea0a:	2201      	movs	r2, #1
 800ea0c:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 800ea10:	687b      	ldr	r3, [r7, #4]
 800ea12:	2201      	movs	r2, #1
 800ea14:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
 800ea18:	687b      	ldr	r3, [r7, #4]
 800ea1a:	2201      	movs	r2, #1
 800ea1c:	f883 2047 	strb.w	r2, [r3, #71]	@ 0x47

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 800ea20:	687b      	ldr	r3, [r7, #4]
 800ea22:	2201      	movs	r2, #1
 800ea24:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  return HAL_OK;
 800ea28:	2300      	movs	r3, #0
}
 800ea2a:	4618      	mov	r0, r3
 800ea2c:	3708      	adds	r7, #8
 800ea2e:	46bd      	mov	sp, r7
 800ea30:	bd80      	pop	{r7, pc}
	...

0800ea34 <HAL_TIM_Base_Start>:
  * @brief  Starts the TIM Base generation.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
{
 800ea34:	b480      	push	{r7}
 800ea36:	b085      	sub	sp, #20
 800ea38:	af00      	add	r7, sp, #0
 800ea3a:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY)
 800ea3c:	687b      	ldr	r3, [r7, #4]
 800ea3e:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 800ea42:	b2db      	uxtb	r3, r3
 800ea44:	2b01      	cmp	r3, #1
 800ea46:	d001      	beq.n	800ea4c <HAL_TIM_Base_Start+0x18>
  {
    return HAL_ERROR;
 800ea48:	2301      	movs	r3, #1
 800ea4a:	e04c      	b.n	800eae6 <HAL_TIM_Base_Start+0xb2>
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 800ea4c:	687b      	ldr	r3, [r7, #4]
 800ea4e:	2202      	movs	r2, #2
 800ea50:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 800ea54:	687b      	ldr	r3, [r7, #4]
 800ea56:	681b      	ldr	r3, [r3, #0]
 800ea58:	4a26      	ldr	r2, [pc, #152]	@ (800eaf4 <HAL_TIM_Base_Start+0xc0>)
 800ea5a:	4293      	cmp	r3, r2
 800ea5c:	d022      	beq.n	800eaa4 <HAL_TIM_Base_Start+0x70>
 800ea5e:	687b      	ldr	r3, [r7, #4]
 800ea60:	681b      	ldr	r3, [r3, #0]
 800ea62:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800ea66:	d01d      	beq.n	800eaa4 <HAL_TIM_Base_Start+0x70>
 800ea68:	687b      	ldr	r3, [r7, #4]
 800ea6a:	681b      	ldr	r3, [r3, #0]
 800ea6c:	4a22      	ldr	r2, [pc, #136]	@ (800eaf8 <HAL_TIM_Base_Start+0xc4>)
 800ea6e:	4293      	cmp	r3, r2
 800ea70:	d018      	beq.n	800eaa4 <HAL_TIM_Base_Start+0x70>
 800ea72:	687b      	ldr	r3, [r7, #4]
 800ea74:	681b      	ldr	r3, [r3, #0]
 800ea76:	4a21      	ldr	r2, [pc, #132]	@ (800eafc <HAL_TIM_Base_Start+0xc8>)
 800ea78:	4293      	cmp	r3, r2
 800ea7a:	d013      	beq.n	800eaa4 <HAL_TIM_Base_Start+0x70>
 800ea7c:	687b      	ldr	r3, [r7, #4]
 800ea7e:	681b      	ldr	r3, [r3, #0]
 800ea80:	4a1f      	ldr	r2, [pc, #124]	@ (800eb00 <HAL_TIM_Base_Start+0xcc>)
 800ea82:	4293      	cmp	r3, r2
 800ea84:	d00e      	beq.n	800eaa4 <HAL_TIM_Base_Start+0x70>
 800ea86:	687b      	ldr	r3, [r7, #4]
 800ea88:	681b      	ldr	r3, [r3, #0]
 800ea8a:	4a1e      	ldr	r2, [pc, #120]	@ (800eb04 <HAL_TIM_Base_Start+0xd0>)
 800ea8c:	4293      	cmp	r3, r2
 800ea8e:	d009      	beq.n	800eaa4 <HAL_TIM_Base_Start+0x70>
 800ea90:	687b      	ldr	r3, [r7, #4]
 800ea92:	681b      	ldr	r3, [r3, #0]
 800ea94:	4a1c      	ldr	r2, [pc, #112]	@ (800eb08 <HAL_TIM_Base_Start+0xd4>)
 800ea96:	4293      	cmp	r3, r2
 800ea98:	d004      	beq.n	800eaa4 <HAL_TIM_Base_Start+0x70>
 800ea9a:	687b      	ldr	r3, [r7, #4]
 800ea9c:	681b      	ldr	r3, [r3, #0]
 800ea9e:	4a1b      	ldr	r2, [pc, #108]	@ (800eb0c <HAL_TIM_Base_Start+0xd8>)
 800eaa0:	4293      	cmp	r3, r2
 800eaa2:	d115      	bne.n	800ead0 <HAL_TIM_Base_Start+0x9c>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 800eaa4:	687b      	ldr	r3, [r7, #4]
 800eaa6:	681b      	ldr	r3, [r3, #0]
 800eaa8:	689a      	ldr	r2, [r3, #8]
 800eaaa:	4b19      	ldr	r3, [pc, #100]	@ (800eb10 <HAL_TIM_Base_Start+0xdc>)
 800eaac:	4013      	ands	r3, r2
 800eaae:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800eab0:	68fb      	ldr	r3, [r7, #12]
 800eab2:	2b06      	cmp	r3, #6
 800eab4:	d015      	beq.n	800eae2 <HAL_TIM_Base_Start+0xae>
 800eab6:	68fb      	ldr	r3, [r7, #12]
 800eab8:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800eabc:	d011      	beq.n	800eae2 <HAL_TIM_Base_Start+0xae>
    {
      __HAL_TIM_ENABLE(htim);
 800eabe:	687b      	ldr	r3, [r7, #4]
 800eac0:	681b      	ldr	r3, [r3, #0]
 800eac2:	681a      	ldr	r2, [r3, #0]
 800eac4:	687b      	ldr	r3, [r7, #4]
 800eac6:	681b      	ldr	r3, [r3, #0]
 800eac8:	f042 0201 	orr.w	r2, r2, #1
 800eacc:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800eace:	e008      	b.n	800eae2 <HAL_TIM_Base_Start+0xae>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 800ead0:	687b      	ldr	r3, [r7, #4]
 800ead2:	681b      	ldr	r3, [r3, #0]
 800ead4:	681a      	ldr	r2, [r3, #0]
 800ead6:	687b      	ldr	r3, [r7, #4]
 800ead8:	681b      	ldr	r3, [r3, #0]
 800eada:	f042 0201 	orr.w	r2, r2, #1
 800eade:	601a      	str	r2, [r3, #0]
 800eae0:	e000      	b.n	800eae4 <HAL_TIM_Base_Start+0xb0>
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800eae2:	bf00      	nop
  }

  /* Return function status */
  return HAL_OK;
 800eae4:	2300      	movs	r3, #0
}
 800eae6:	4618      	mov	r0, r3
 800eae8:	3714      	adds	r7, #20
 800eaea:	46bd      	mov	sp, r7
 800eaec:	f85d 7b04 	ldr.w	r7, [sp], #4
 800eaf0:	4770      	bx	lr
 800eaf2:	bf00      	nop
 800eaf4:	40010000 	.word	0x40010000
 800eaf8:	40000400 	.word	0x40000400
 800eafc:	40000800 	.word	0x40000800
 800eb00:	40000c00 	.word	0x40000c00
 800eb04:	40010400 	.word	0x40010400
 800eb08:	40001800 	.word	0x40001800
 800eb0c:	40014000 	.word	0x40014000
 800eb10:	00010007 	.word	0x00010007

0800eb14 <HAL_TIM_Base_Start_IT>:
  * @brief  Starts the TIM Base generation in interrupt mode.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
 800eb14:	b480      	push	{r7}
 800eb16:	b085      	sub	sp, #20
 800eb18:	af00      	add	r7, sp, #0
 800eb1a:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY)
 800eb1c:	687b      	ldr	r3, [r7, #4]
 800eb1e:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 800eb22:	b2db      	uxtb	r3, r3
 800eb24:	2b01      	cmp	r3, #1
 800eb26:	d001      	beq.n	800eb2c <HAL_TIM_Base_Start_IT+0x18>
  {
    return HAL_ERROR;
 800eb28:	2301      	movs	r3, #1
 800eb2a:	e054      	b.n	800ebd6 <HAL_TIM_Base_Start_IT+0xc2>
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 800eb2c:	687b      	ldr	r3, [r7, #4]
 800eb2e:	2202      	movs	r2, #2
 800eb30:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Enable the TIM Update interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 800eb34:	687b      	ldr	r3, [r7, #4]
 800eb36:	681b      	ldr	r3, [r3, #0]
 800eb38:	68da      	ldr	r2, [r3, #12]
 800eb3a:	687b      	ldr	r3, [r7, #4]
 800eb3c:	681b      	ldr	r3, [r3, #0]
 800eb3e:	f042 0201 	orr.w	r2, r2, #1
 800eb42:	60da      	str	r2, [r3, #12]

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 800eb44:	687b      	ldr	r3, [r7, #4]
 800eb46:	681b      	ldr	r3, [r3, #0]
 800eb48:	4a26      	ldr	r2, [pc, #152]	@ (800ebe4 <HAL_TIM_Base_Start_IT+0xd0>)
 800eb4a:	4293      	cmp	r3, r2
 800eb4c:	d022      	beq.n	800eb94 <HAL_TIM_Base_Start_IT+0x80>
 800eb4e:	687b      	ldr	r3, [r7, #4]
 800eb50:	681b      	ldr	r3, [r3, #0]
 800eb52:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800eb56:	d01d      	beq.n	800eb94 <HAL_TIM_Base_Start_IT+0x80>
 800eb58:	687b      	ldr	r3, [r7, #4]
 800eb5a:	681b      	ldr	r3, [r3, #0]
 800eb5c:	4a22      	ldr	r2, [pc, #136]	@ (800ebe8 <HAL_TIM_Base_Start_IT+0xd4>)
 800eb5e:	4293      	cmp	r3, r2
 800eb60:	d018      	beq.n	800eb94 <HAL_TIM_Base_Start_IT+0x80>
 800eb62:	687b      	ldr	r3, [r7, #4]
 800eb64:	681b      	ldr	r3, [r3, #0]
 800eb66:	4a21      	ldr	r2, [pc, #132]	@ (800ebec <HAL_TIM_Base_Start_IT+0xd8>)
 800eb68:	4293      	cmp	r3, r2
 800eb6a:	d013      	beq.n	800eb94 <HAL_TIM_Base_Start_IT+0x80>
 800eb6c:	687b      	ldr	r3, [r7, #4]
 800eb6e:	681b      	ldr	r3, [r3, #0]
 800eb70:	4a1f      	ldr	r2, [pc, #124]	@ (800ebf0 <HAL_TIM_Base_Start_IT+0xdc>)
 800eb72:	4293      	cmp	r3, r2
 800eb74:	d00e      	beq.n	800eb94 <HAL_TIM_Base_Start_IT+0x80>
 800eb76:	687b      	ldr	r3, [r7, #4]
 800eb78:	681b      	ldr	r3, [r3, #0]
 800eb7a:	4a1e      	ldr	r2, [pc, #120]	@ (800ebf4 <HAL_TIM_Base_Start_IT+0xe0>)
 800eb7c:	4293      	cmp	r3, r2
 800eb7e:	d009      	beq.n	800eb94 <HAL_TIM_Base_Start_IT+0x80>
 800eb80:	687b      	ldr	r3, [r7, #4]
 800eb82:	681b      	ldr	r3, [r3, #0]
 800eb84:	4a1c      	ldr	r2, [pc, #112]	@ (800ebf8 <HAL_TIM_Base_Start_IT+0xe4>)
 800eb86:	4293      	cmp	r3, r2
 800eb88:	d004      	beq.n	800eb94 <HAL_TIM_Base_Start_IT+0x80>
 800eb8a:	687b      	ldr	r3, [r7, #4]
 800eb8c:	681b      	ldr	r3, [r3, #0]
 800eb8e:	4a1b      	ldr	r2, [pc, #108]	@ (800ebfc <HAL_TIM_Base_Start_IT+0xe8>)
 800eb90:	4293      	cmp	r3, r2
 800eb92:	d115      	bne.n	800ebc0 <HAL_TIM_Base_Start_IT+0xac>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 800eb94:	687b      	ldr	r3, [r7, #4]
 800eb96:	681b      	ldr	r3, [r3, #0]
 800eb98:	689a      	ldr	r2, [r3, #8]
 800eb9a:	4b19      	ldr	r3, [pc, #100]	@ (800ec00 <HAL_TIM_Base_Start_IT+0xec>)
 800eb9c:	4013      	ands	r3, r2
 800eb9e:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800eba0:	68fb      	ldr	r3, [r7, #12]
 800eba2:	2b06      	cmp	r3, #6
 800eba4:	d015      	beq.n	800ebd2 <HAL_TIM_Base_Start_IT+0xbe>
 800eba6:	68fb      	ldr	r3, [r7, #12]
 800eba8:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800ebac:	d011      	beq.n	800ebd2 <HAL_TIM_Base_Start_IT+0xbe>
    {
      __HAL_TIM_ENABLE(htim);
 800ebae:	687b      	ldr	r3, [r7, #4]
 800ebb0:	681b      	ldr	r3, [r3, #0]
 800ebb2:	681a      	ldr	r2, [r3, #0]
 800ebb4:	687b      	ldr	r3, [r7, #4]
 800ebb6:	681b      	ldr	r3, [r3, #0]
 800ebb8:	f042 0201 	orr.w	r2, r2, #1
 800ebbc:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800ebbe:	e008      	b.n	800ebd2 <HAL_TIM_Base_Start_IT+0xbe>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 800ebc0:	687b      	ldr	r3, [r7, #4]
 800ebc2:	681b      	ldr	r3, [r3, #0]
 800ebc4:	681a      	ldr	r2, [r3, #0]
 800ebc6:	687b      	ldr	r3, [r7, #4]
 800ebc8:	681b      	ldr	r3, [r3, #0]
 800ebca:	f042 0201 	orr.w	r2, r2, #1
 800ebce:	601a      	str	r2, [r3, #0]
 800ebd0:	e000      	b.n	800ebd4 <HAL_TIM_Base_Start_IT+0xc0>
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800ebd2:	bf00      	nop
  }

  /* Return function status */
  return HAL_OK;
 800ebd4:	2300      	movs	r3, #0
}
 800ebd6:	4618      	mov	r0, r3
 800ebd8:	3714      	adds	r7, #20
 800ebda:	46bd      	mov	sp, r7
 800ebdc:	f85d 7b04 	ldr.w	r7, [sp], #4
 800ebe0:	4770      	bx	lr
 800ebe2:	bf00      	nop
 800ebe4:	40010000 	.word	0x40010000
 800ebe8:	40000400 	.word	0x40000400
 800ebec:	40000800 	.word	0x40000800
 800ebf0:	40000c00 	.word	0x40000c00
 800ebf4:	40010400 	.word	0x40010400
 800ebf8:	40001800 	.word	0x40001800
 800ebfc:	40014000 	.word	0x40014000
 800ec00:	00010007 	.word	0x00010007

0800ec04 <HAL_TIM_PWM_Init>:
  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
  * @param  htim TIM PWM handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
 800ec04:	b580      	push	{r7, lr}
 800ec06:	b082      	sub	sp, #8
 800ec08:	af00      	add	r7, sp, #0
 800ec0a:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 800ec0c:	687b      	ldr	r3, [r7, #4]
 800ec0e:	2b00      	cmp	r3, #0
 800ec10:	d101      	bne.n	800ec16 <HAL_TIM_PWM_Init+0x12>
  {
    return HAL_ERROR;
 800ec12:	2301      	movs	r3, #1
 800ec14:	e049      	b.n	800ecaa <HAL_TIM_PWM_Init+0xa6>
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 800ec16:	687b      	ldr	r3, [r7, #4]
 800ec18:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 800ec1c:	b2db      	uxtb	r3, r3
 800ec1e:	2b00      	cmp	r3, #0
 800ec20:	d106      	bne.n	800ec30 <HAL_TIM_PWM_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 800ec22:	687b      	ldr	r3, [r7, #4]
 800ec24:	2200      	movs	r2, #0
 800ec26:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->PWM_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
    HAL_TIM_PWM_MspInit(htim);
 800ec2a:	6878      	ldr	r0, [r7, #4]
 800ec2c:	f7f4 fec6 	bl	80039bc <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 800ec30:	687b      	ldr	r3, [r7, #4]
 800ec32:	2202      	movs	r2, #2
 800ec34:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Init the base time for the PWM */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 800ec38:	687b      	ldr	r3, [r7, #4]
 800ec3a:	681a      	ldr	r2, [r3, #0]
 800ec3c:	687b      	ldr	r3, [r7, #4]
 800ec3e:	3304      	adds	r3, #4
 800ec40:	4619      	mov	r1, r3
 800ec42:	4610      	mov	r0, r2
 800ec44:	f000 ffd8 	bl	800fbf8 <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 800ec48:	687b      	ldr	r3, [r7, #4]
 800ec4a:	2201      	movs	r2, #1
 800ec4c:	f883 2048 	strb.w	r2, [r3, #72]	@ 0x48

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 800ec50:	687b      	ldr	r3, [r7, #4]
 800ec52:	2201      	movs	r2, #1
 800ec54:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 800ec58:	687b      	ldr	r3, [r7, #4]
 800ec5a:	2201      	movs	r2, #1
 800ec5c:	f883 203f 	strb.w	r2, [r3, #63]	@ 0x3f
 800ec60:	687b      	ldr	r3, [r7, #4]
 800ec62:	2201      	movs	r2, #1
 800ec64:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 800ec68:	687b      	ldr	r3, [r7, #4]
 800ec6a:	2201      	movs	r2, #1
 800ec6c:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 800ec70:	687b      	ldr	r3, [r7, #4]
 800ec72:	2201      	movs	r2, #1
 800ec74:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
 800ec78:	687b      	ldr	r3, [r7, #4]
 800ec7a:	2201      	movs	r2, #1
 800ec7c:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 800ec80:	687b      	ldr	r3, [r7, #4]
 800ec82:	2201      	movs	r2, #1
 800ec84:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 800ec88:	687b      	ldr	r3, [r7, #4]
 800ec8a:	2201      	movs	r2, #1
 800ec8c:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 800ec90:	687b      	ldr	r3, [r7, #4]
 800ec92:	2201      	movs	r2, #1
 800ec94:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
 800ec98:	687b      	ldr	r3, [r7, #4]
 800ec9a:	2201      	movs	r2, #1
 800ec9c:	f883 2047 	strb.w	r2, [r3, #71]	@ 0x47

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 800eca0:	687b      	ldr	r3, [r7, #4]
 800eca2:	2201      	movs	r2, #1
 800eca4:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  return HAL_OK;
 800eca8:	2300      	movs	r3, #0
}
 800ecaa:	4618      	mov	r0, r3
 800ecac:	3708      	adds	r7, #8
 800ecae:	46bd      	mov	sp, r7
 800ecb0:	bd80      	pop	{r7, pc}
	...

0800ecb4 <HAL_TIM_PWM_Start>:
  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
 800ecb4:	b580      	push	{r7, lr}
 800ecb6:	b084      	sub	sp, #16
 800ecb8:	af00      	add	r7, sp, #0
 800ecba:	6078      	str	r0, [r7, #4]
 800ecbc:	6039      	str	r1, [r7, #0]

  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Check the TIM channel state */
  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
 800ecbe:	683b      	ldr	r3, [r7, #0]
 800ecc0:	2b00      	cmp	r3, #0
 800ecc2:	d109      	bne.n	800ecd8 <HAL_TIM_PWM_Start+0x24>
 800ecc4:	687b      	ldr	r3, [r7, #4]
 800ecc6:	f893 303e 	ldrb.w	r3, [r3, #62]	@ 0x3e
 800ecca:	b2db      	uxtb	r3, r3
 800eccc:	2b01      	cmp	r3, #1
 800ecce:	bf14      	ite	ne
 800ecd0:	2301      	movne	r3, #1
 800ecd2:	2300      	moveq	r3, #0
 800ecd4:	b2db      	uxtb	r3, r3
 800ecd6:	e03c      	b.n	800ed52 <HAL_TIM_PWM_Start+0x9e>
 800ecd8:	683b      	ldr	r3, [r7, #0]
 800ecda:	2b04      	cmp	r3, #4
 800ecdc:	d109      	bne.n	800ecf2 <HAL_TIM_PWM_Start+0x3e>
 800ecde:	687b      	ldr	r3, [r7, #4]
 800ece0:	f893 303f 	ldrb.w	r3, [r3, #63]	@ 0x3f
 800ece4:	b2db      	uxtb	r3, r3
 800ece6:	2b01      	cmp	r3, #1
 800ece8:	bf14      	ite	ne
 800ecea:	2301      	movne	r3, #1
 800ecec:	2300      	moveq	r3, #0
 800ecee:	b2db      	uxtb	r3, r3
 800ecf0:	e02f      	b.n	800ed52 <HAL_TIM_PWM_Start+0x9e>
 800ecf2:	683b      	ldr	r3, [r7, #0]
 800ecf4:	2b08      	cmp	r3, #8
 800ecf6:	d109      	bne.n	800ed0c <HAL_TIM_PWM_Start+0x58>
 800ecf8:	687b      	ldr	r3, [r7, #4]
 800ecfa:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
 800ecfe:	b2db      	uxtb	r3, r3
 800ed00:	2b01      	cmp	r3, #1
 800ed02:	bf14      	ite	ne
 800ed04:	2301      	movne	r3, #1
 800ed06:	2300      	moveq	r3, #0
 800ed08:	b2db      	uxtb	r3, r3
 800ed0a:	e022      	b.n	800ed52 <HAL_TIM_PWM_Start+0x9e>
 800ed0c:	683b      	ldr	r3, [r7, #0]
 800ed0e:	2b0c      	cmp	r3, #12
 800ed10:	d109      	bne.n	800ed26 <HAL_TIM_PWM_Start+0x72>
 800ed12:	687b      	ldr	r3, [r7, #4]
 800ed14:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 800ed18:	b2db      	uxtb	r3, r3
 800ed1a:	2b01      	cmp	r3, #1
 800ed1c:	bf14      	ite	ne
 800ed1e:	2301      	movne	r3, #1
 800ed20:	2300      	moveq	r3, #0
 800ed22:	b2db      	uxtb	r3, r3
 800ed24:	e015      	b.n	800ed52 <HAL_TIM_PWM_Start+0x9e>
 800ed26:	683b      	ldr	r3, [r7, #0]
 800ed28:	2b10      	cmp	r3, #16
 800ed2a:	d109      	bne.n	800ed40 <HAL_TIM_PWM_Start+0x8c>
 800ed2c:	687b      	ldr	r3, [r7, #4]
 800ed2e:	f893 3042 	ldrb.w	r3, [r3, #66]	@ 0x42
 800ed32:	b2db      	uxtb	r3, r3
 800ed34:	2b01      	cmp	r3, #1
 800ed36:	bf14      	ite	ne
 800ed38:	2301      	movne	r3, #1
 800ed3a:	2300      	moveq	r3, #0
 800ed3c:	b2db      	uxtb	r3, r3
 800ed3e:	e008      	b.n	800ed52 <HAL_TIM_PWM_Start+0x9e>
 800ed40:	687b      	ldr	r3, [r7, #4]
 800ed42:	f893 3043 	ldrb.w	r3, [r3, #67]	@ 0x43
 800ed46:	b2db      	uxtb	r3, r3
 800ed48:	2b01      	cmp	r3, #1
 800ed4a:	bf14      	ite	ne
 800ed4c:	2301      	movne	r3, #1
 800ed4e:	2300      	moveq	r3, #0
 800ed50:	b2db      	uxtb	r3, r3
 800ed52:	2b00      	cmp	r3, #0
 800ed54:	d001      	beq.n	800ed5a <HAL_TIM_PWM_Start+0xa6>
  {
    return HAL_ERROR;
 800ed56:	2301      	movs	r3, #1
 800ed58:	e0a1      	b.n	800ee9e <HAL_TIM_PWM_Start+0x1ea>
  }

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
 800ed5a:	683b      	ldr	r3, [r7, #0]
 800ed5c:	2b00      	cmp	r3, #0
 800ed5e:	d104      	bne.n	800ed6a <HAL_TIM_PWM_Start+0xb6>
 800ed60:	687b      	ldr	r3, [r7, #4]
 800ed62:	2202      	movs	r2, #2
 800ed64:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 800ed68:	e023      	b.n	800edb2 <HAL_TIM_PWM_Start+0xfe>
 800ed6a:	683b      	ldr	r3, [r7, #0]
 800ed6c:	2b04      	cmp	r3, #4
 800ed6e:	d104      	bne.n	800ed7a <HAL_TIM_PWM_Start+0xc6>
 800ed70:	687b      	ldr	r3, [r7, #4]
 800ed72:	2202      	movs	r2, #2
 800ed74:	f883 203f 	strb.w	r2, [r3, #63]	@ 0x3f
 800ed78:	e01b      	b.n	800edb2 <HAL_TIM_PWM_Start+0xfe>
 800ed7a:	683b      	ldr	r3, [r7, #0]
 800ed7c:	2b08      	cmp	r3, #8
 800ed7e:	d104      	bne.n	800ed8a <HAL_TIM_PWM_Start+0xd6>
 800ed80:	687b      	ldr	r3, [r7, #4]
 800ed82:	2202      	movs	r2, #2
 800ed84:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 800ed88:	e013      	b.n	800edb2 <HAL_TIM_PWM_Start+0xfe>
 800ed8a:	683b      	ldr	r3, [r7, #0]
 800ed8c:	2b0c      	cmp	r3, #12
 800ed8e:	d104      	bne.n	800ed9a <HAL_TIM_PWM_Start+0xe6>
 800ed90:	687b      	ldr	r3, [r7, #4]
 800ed92:	2202      	movs	r2, #2
 800ed94:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 800ed98:	e00b      	b.n	800edb2 <HAL_TIM_PWM_Start+0xfe>
 800ed9a:	683b      	ldr	r3, [r7, #0]
 800ed9c:	2b10      	cmp	r3, #16
 800ed9e:	d104      	bne.n	800edaa <HAL_TIM_PWM_Start+0xf6>
 800eda0:	687b      	ldr	r3, [r7, #4]
 800eda2:	2202      	movs	r2, #2
 800eda4:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
 800eda8:	e003      	b.n	800edb2 <HAL_TIM_PWM_Start+0xfe>
 800edaa:	687b      	ldr	r3, [r7, #4]
 800edac:	2202      	movs	r2, #2
 800edae:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43

  /* Enable the Capture compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 800edb2:	687b      	ldr	r3, [r7, #4]
 800edb4:	681b      	ldr	r3, [r3, #0]
 800edb6:	2201      	movs	r2, #1
 800edb8:	6839      	ldr	r1, [r7, #0]
 800edba:	4618      	mov	r0, r3
 800edbc:	f001 fc60 	bl	8010680 <TIM_CCxChannelCmd>

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
 800edc0:	687b      	ldr	r3, [r7, #4]
 800edc2:	681b      	ldr	r3, [r3, #0]
 800edc4:	4a38      	ldr	r2, [pc, #224]	@ (800eea8 <HAL_TIM_PWM_Start+0x1f4>)
 800edc6:	4293      	cmp	r3, r2
 800edc8:	d013      	beq.n	800edf2 <HAL_TIM_PWM_Start+0x13e>
 800edca:	687b      	ldr	r3, [r7, #4]
 800edcc:	681b      	ldr	r3, [r3, #0]
 800edce:	4a37      	ldr	r2, [pc, #220]	@ (800eeac <HAL_TIM_PWM_Start+0x1f8>)
 800edd0:	4293      	cmp	r3, r2
 800edd2:	d00e      	beq.n	800edf2 <HAL_TIM_PWM_Start+0x13e>
 800edd4:	687b      	ldr	r3, [r7, #4]
 800edd6:	681b      	ldr	r3, [r3, #0]
 800edd8:	4a35      	ldr	r2, [pc, #212]	@ (800eeb0 <HAL_TIM_PWM_Start+0x1fc>)
 800edda:	4293      	cmp	r3, r2
 800eddc:	d009      	beq.n	800edf2 <HAL_TIM_PWM_Start+0x13e>
 800edde:	687b      	ldr	r3, [r7, #4]
 800ede0:	681b      	ldr	r3, [r3, #0]
 800ede2:	4a34      	ldr	r2, [pc, #208]	@ (800eeb4 <HAL_TIM_PWM_Start+0x200>)
 800ede4:	4293      	cmp	r3, r2
 800ede6:	d004      	beq.n	800edf2 <HAL_TIM_PWM_Start+0x13e>
 800ede8:	687b      	ldr	r3, [r7, #4]
 800edea:	681b      	ldr	r3, [r3, #0]
 800edec:	4a32      	ldr	r2, [pc, #200]	@ (800eeb8 <HAL_TIM_PWM_Start+0x204>)
 800edee:	4293      	cmp	r3, r2
 800edf0:	d101      	bne.n	800edf6 <HAL_TIM_PWM_Start+0x142>
 800edf2:	2301      	movs	r3, #1
 800edf4:	e000      	b.n	800edf8 <HAL_TIM_PWM_Start+0x144>
 800edf6:	2300      	movs	r3, #0
 800edf8:	2b00      	cmp	r3, #0
 800edfa:	d007      	beq.n	800ee0c <HAL_TIM_PWM_Start+0x158>
  {
    /* Enable the main output */
    __HAL_TIM_MOE_ENABLE(htim);
 800edfc:	687b      	ldr	r3, [r7, #4]
 800edfe:	681b      	ldr	r3, [r3, #0]
 800ee00:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
 800ee02:	687b      	ldr	r3, [r7, #4]
 800ee04:	681b      	ldr	r3, [r3, #0]
 800ee06:	f442 4200 	orr.w	r2, r2, #32768	@ 0x8000
 800ee0a:	645a      	str	r2, [r3, #68]	@ 0x44
  }

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 800ee0c:	687b      	ldr	r3, [r7, #4]
 800ee0e:	681b      	ldr	r3, [r3, #0]
 800ee10:	4a25      	ldr	r2, [pc, #148]	@ (800eea8 <HAL_TIM_PWM_Start+0x1f4>)
 800ee12:	4293      	cmp	r3, r2
 800ee14:	d022      	beq.n	800ee5c <HAL_TIM_PWM_Start+0x1a8>
 800ee16:	687b      	ldr	r3, [r7, #4]
 800ee18:	681b      	ldr	r3, [r3, #0]
 800ee1a:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800ee1e:	d01d      	beq.n	800ee5c <HAL_TIM_PWM_Start+0x1a8>
 800ee20:	687b      	ldr	r3, [r7, #4]
 800ee22:	681b      	ldr	r3, [r3, #0]
 800ee24:	4a25      	ldr	r2, [pc, #148]	@ (800eebc <HAL_TIM_PWM_Start+0x208>)
 800ee26:	4293      	cmp	r3, r2
 800ee28:	d018      	beq.n	800ee5c <HAL_TIM_PWM_Start+0x1a8>
 800ee2a:	687b      	ldr	r3, [r7, #4]
 800ee2c:	681b      	ldr	r3, [r3, #0]
 800ee2e:	4a24      	ldr	r2, [pc, #144]	@ (800eec0 <HAL_TIM_PWM_Start+0x20c>)
 800ee30:	4293      	cmp	r3, r2
 800ee32:	d013      	beq.n	800ee5c <HAL_TIM_PWM_Start+0x1a8>
 800ee34:	687b      	ldr	r3, [r7, #4]
 800ee36:	681b      	ldr	r3, [r3, #0]
 800ee38:	4a22      	ldr	r2, [pc, #136]	@ (800eec4 <HAL_TIM_PWM_Start+0x210>)
 800ee3a:	4293      	cmp	r3, r2
 800ee3c:	d00e      	beq.n	800ee5c <HAL_TIM_PWM_Start+0x1a8>
 800ee3e:	687b      	ldr	r3, [r7, #4]
 800ee40:	681b      	ldr	r3, [r3, #0]
 800ee42:	4a1a      	ldr	r2, [pc, #104]	@ (800eeac <HAL_TIM_PWM_Start+0x1f8>)
 800ee44:	4293      	cmp	r3, r2
 800ee46:	d009      	beq.n	800ee5c <HAL_TIM_PWM_Start+0x1a8>
 800ee48:	687b      	ldr	r3, [r7, #4]
 800ee4a:	681b      	ldr	r3, [r3, #0]
 800ee4c:	4a1e      	ldr	r2, [pc, #120]	@ (800eec8 <HAL_TIM_PWM_Start+0x214>)
 800ee4e:	4293      	cmp	r3, r2
 800ee50:	d004      	beq.n	800ee5c <HAL_TIM_PWM_Start+0x1a8>
 800ee52:	687b      	ldr	r3, [r7, #4]
 800ee54:	681b      	ldr	r3, [r3, #0]
 800ee56:	4a16      	ldr	r2, [pc, #88]	@ (800eeb0 <HAL_TIM_PWM_Start+0x1fc>)
 800ee58:	4293      	cmp	r3, r2
 800ee5a:	d115      	bne.n	800ee88 <HAL_TIM_PWM_Start+0x1d4>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 800ee5c:	687b      	ldr	r3, [r7, #4]
 800ee5e:	681b      	ldr	r3, [r3, #0]
 800ee60:	689a      	ldr	r2, [r3, #8]
 800ee62:	4b1a      	ldr	r3, [pc, #104]	@ (800eecc <HAL_TIM_PWM_Start+0x218>)
 800ee64:	4013      	ands	r3, r2
 800ee66:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800ee68:	68fb      	ldr	r3, [r7, #12]
 800ee6a:	2b06      	cmp	r3, #6
 800ee6c:	d015      	beq.n	800ee9a <HAL_TIM_PWM_Start+0x1e6>
 800ee6e:	68fb      	ldr	r3, [r7, #12]
 800ee70:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800ee74:	d011      	beq.n	800ee9a <HAL_TIM_PWM_Start+0x1e6>
    {
      __HAL_TIM_ENABLE(htim);
 800ee76:	687b      	ldr	r3, [r7, #4]
 800ee78:	681b      	ldr	r3, [r3, #0]
 800ee7a:	681a      	ldr	r2, [r3, #0]
 800ee7c:	687b      	ldr	r3, [r7, #4]
 800ee7e:	681b      	ldr	r3, [r3, #0]
 800ee80:	f042 0201 	orr.w	r2, r2, #1
 800ee84:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800ee86:	e008      	b.n	800ee9a <HAL_TIM_PWM_Start+0x1e6>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 800ee88:	687b      	ldr	r3, [r7, #4]
 800ee8a:	681b      	ldr	r3, [r3, #0]
 800ee8c:	681a      	ldr	r2, [r3, #0]
 800ee8e:	687b      	ldr	r3, [r7, #4]
 800ee90:	681b      	ldr	r3, [r3, #0]
 800ee92:	f042 0201 	orr.w	r2, r2, #1
 800ee96:	601a      	str	r2, [r3, #0]
 800ee98:	e000      	b.n	800ee9c <HAL_TIM_PWM_Start+0x1e8>
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800ee9a:	bf00      	nop
  }

  /* Return function status */
  return HAL_OK;
 800ee9c:	2300      	movs	r3, #0
}
 800ee9e:	4618      	mov	r0, r3
 800eea0:	3710      	adds	r7, #16
 800eea2:	46bd      	mov	sp, r7
 800eea4:	bd80      	pop	{r7, pc}
 800eea6:	bf00      	nop
 800eea8:	40010000 	.word	0x40010000
 800eeac:	40010400 	.word	0x40010400
 800eeb0:	40014000 	.word	0x40014000
 800eeb4:	40014400 	.word	0x40014400
 800eeb8:	40014800 	.word	0x40014800
 800eebc:	40000400 	.word	0x40000400
 800eec0:	40000800 	.word	0x40000800
 800eec4:	40000c00 	.word	0x40000c00
 800eec8:	40001800 	.word	0x40001800
 800eecc:	00010007 	.word	0x00010007

0800eed0 <HAL_TIM_PWM_Stop>:
  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
 800eed0:	b580      	push	{r7, lr}
 800eed2:	b082      	sub	sp, #8
 800eed4:	af00      	add	r7, sp, #0
 800eed6:	6078      	str	r0, [r7, #4]
 800eed8:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Disable the Capture compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
 800eeda:	687b      	ldr	r3, [r7, #4]
 800eedc:	681b      	ldr	r3, [r3, #0]
 800eede:	2200      	movs	r2, #0
 800eee0:	6839      	ldr	r1, [r7, #0]
 800eee2:	4618      	mov	r0, r3
 800eee4:	f001 fbcc 	bl	8010680 <TIM_CCxChannelCmd>

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
 800eee8:	687b      	ldr	r3, [r7, #4]
 800eeea:	681b      	ldr	r3, [r3, #0]
 800eeec:	4a3e      	ldr	r2, [pc, #248]	@ (800efe8 <HAL_TIM_PWM_Stop+0x118>)
 800eeee:	4293      	cmp	r3, r2
 800eef0:	d013      	beq.n	800ef1a <HAL_TIM_PWM_Stop+0x4a>
 800eef2:	687b      	ldr	r3, [r7, #4]
 800eef4:	681b      	ldr	r3, [r3, #0]
 800eef6:	4a3d      	ldr	r2, [pc, #244]	@ (800efec <HAL_TIM_PWM_Stop+0x11c>)
 800eef8:	4293      	cmp	r3, r2
 800eefa:	d00e      	beq.n	800ef1a <HAL_TIM_PWM_Stop+0x4a>
 800eefc:	687b      	ldr	r3, [r7, #4]
 800eefe:	681b      	ldr	r3, [r3, #0]
 800ef00:	4a3b      	ldr	r2, [pc, #236]	@ (800eff0 <HAL_TIM_PWM_Stop+0x120>)
 800ef02:	4293      	cmp	r3, r2
 800ef04:	d009      	beq.n	800ef1a <HAL_TIM_PWM_Stop+0x4a>
 800ef06:	687b      	ldr	r3, [r7, #4]
 800ef08:	681b      	ldr	r3, [r3, #0]
 800ef0a:	4a3a      	ldr	r2, [pc, #232]	@ (800eff4 <HAL_TIM_PWM_Stop+0x124>)
 800ef0c:	4293      	cmp	r3, r2
 800ef0e:	d004      	beq.n	800ef1a <HAL_TIM_PWM_Stop+0x4a>
 800ef10:	687b      	ldr	r3, [r7, #4]
 800ef12:	681b      	ldr	r3, [r3, #0]
 800ef14:	4a38      	ldr	r2, [pc, #224]	@ (800eff8 <HAL_TIM_PWM_Stop+0x128>)
 800ef16:	4293      	cmp	r3, r2
 800ef18:	d101      	bne.n	800ef1e <HAL_TIM_PWM_Stop+0x4e>
 800ef1a:	2301      	movs	r3, #1
 800ef1c:	e000      	b.n	800ef20 <HAL_TIM_PWM_Stop+0x50>
 800ef1e:	2300      	movs	r3, #0
 800ef20:	2b00      	cmp	r3, #0
 800ef22:	d017      	beq.n	800ef54 <HAL_TIM_PWM_Stop+0x84>
  {
    /* Disable the Main Output */
    __HAL_TIM_MOE_DISABLE(htim);
 800ef24:	687b      	ldr	r3, [r7, #4]
 800ef26:	681b      	ldr	r3, [r3, #0]
 800ef28:	6a1a      	ldr	r2, [r3, #32]
 800ef2a:	f241 1311 	movw	r3, #4369	@ 0x1111
 800ef2e:	4013      	ands	r3, r2
 800ef30:	2b00      	cmp	r3, #0
 800ef32:	d10f      	bne.n	800ef54 <HAL_TIM_PWM_Stop+0x84>
 800ef34:	687b      	ldr	r3, [r7, #4]
 800ef36:	681b      	ldr	r3, [r3, #0]
 800ef38:	6a1a      	ldr	r2, [r3, #32]
 800ef3a:	f240 4344 	movw	r3, #1092	@ 0x444
 800ef3e:	4013      	ands	r3, r2
 800ef40:	2b00      	cmp	r3, #0
 800ef42:	d107      	bne.n	800ef54 <HAL_TIM_PWM_Stop+0x84>
 800ef44:	687b      	ldr	r3, [r7, #4]
 800ef46:	681b      	ldr	r3, [r3, #0]
 800ef48:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
 800ef4a:	687b      	ldr	r3, [r7, #4]
 800ef4c:	681b      	ldr	r3, [r3, #0]
 800ef4e:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
 800ef52:	645a      	str	r2, [r3, #68]	@ 0x44
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);
 800ef54:	687b      	ldr	r3, [r7, #4]
 800ef56:	681b      	ldr	r3, [r3, #0]
 800ef58:	6a1a      	ldr	r2, [r3, #32]
 800ef5a:	f241 1311 	movw	r3, #4369	@ 0x1111
 800ef5e:	4013      	ands	r3, r2
 800ef60:	2b00      	cmp	r3, #0
 800ef62:	d10f      	bne.n	800ef84 <HAL_TIM_PWM_Stop+0xb4>
 800ef64:	687b      	ldr	r3, [r7, #4]
 800ef66:	681b      	ldr	r3, [r3, #0]
 800ef68:	6a1a      	ldr	r2, [r3, #32]
 800ef6a:	f240 4344 	movw	r3, #1092	@ 0x444
 800ef6e:	4013      	ands	r3, r2
 800ef70:	2b00      	cmp	r3, #0
 800ef72:	d107      	bne.n	800ef84 <HAL_TIM_PWM_Stop+0xb4>
 800ef74:	687b      	ldr	r3, [r7, #4]
 800ef76:	681b      	ldr	r3, [r3, #0]
 800ef78:	681a      	ldr	r2, [r3, #0]
 800ef7a:	687b      	ldr	r3, [r7, #4]
 800ef7c:	681b      	ldr	r3, [r3, #0]
 800ef7e:	f022 0201 	bic.w	r2, r2, #1
 800ef82:	601a      	str	r2, [r3, #0]

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
 800ef84:	683b      	ldr	r3, [r7, #0]
 800ef86:	2b00      	cmp	r3, #0
 800ef88:	d104      	bne.n	800ef94 <HAL_TIM_PWM_Stop+0xc4>
 800ef8a:	687b      	ldr	r3, [r7, #4]
 800ef8c:	2201      	movs	r2, #1
 800ef8e:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 800ef92:	e023      	b.n	800efdc <HAL_TIM_PWM_Stop+0x10c>
 800ef94:	683b      	ldr	r3, [r7, #0]
 800ef96:	2b04      	cmp	r3, #4
 800ef98:	d104      	bne.n	800efa4 <HAL_TIM_PWM_Stop+0xd4>
 800ef9a:	687b      	ldr	r3, [r7, #4]
 800ef9c:	2201      	movs	r2, #1
 800ef9e:	f883 203f 	strb.w	r2, [r3, #63]	@ 0x3f
 800efa2:	e01b      	b.n	800efdc <HAL_TIM_PWM_Stop+0x10c>
 800efa4:	683b      	ldr	r3, [r7, #0]
 800efa6:	2b08      	cmp	r3, #8
 800efa8:	d104      	bne.n	800efb4 <HAL_TIM_PWM_Stop+0xe4>
 800efaa:	687b      	ldr	r3, [r7, #4]
 800efac:	2201      	movs	r2, #1
 800efae:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 800efb2:	e013      	b.n	800efdc <HAL_TIM_PWM_Stop+0x10c>
 800efb4:	683b      	ldr	r3, [r7, #0]
 800efb6:	2b0c      	cmp	r3, #12
 800efb8:	d104      	bne.n	800efc4 <HAL_TIM_PWM_Stop+0xf4>
 800efba:	687b      	ldr	r3, [r7, #4]
 800efbc:	2201      	movs	r2, #1
 800efbe:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 800efc2:	e00b      	b.n	800efdc <HAL_TIM_PWM_Stop+0x10c>
 800efc4:	683b      	ldr	r3, [r7, #0]
 800efc6:	2b10      	cmp	r3, #16
 800efc8:	d104      	bne.n	800efd4 <HAL_TIM_PWM_Stop+0x104>
 800efca:	687b      	ldr	r3, [r7, #4]
 800efcc:	2201      	movs	r2, #1
 800efce:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
 800efd2:	e003      	b.n	800efdc <HAL_TIM_PWM_Stop+0x10c>
 800efd4:	687b      	ldr	r3, [r7, #4]
 800efd6:	2201      	movs	r2, #1
 800efd8:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43

  /* Return function status */
  return HAL_OK;
 800efdc:	2300      	movs	r3, #0
}
 800efde:	4618      	mov	r0, r3
 800efe0:	3708      	adds	r7, #8
 800efe2:	46bd      	mov	sp, r7
 800efe4:	bd80      	pop	{r7, pc}
 800efe6:	bf00      	nop
 800efe8:	40010000 	.word	0x40010000
 800efec:	40010400 	.word	0x40010400
 800eff0:	40014000 	.word	0x40014000
 800eff4:	40014400 	.word	0x40014400
 800eff8:	40014800 	.word	0x40014800

0800effc <HAL_TIM_IC_Init>:
  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
  * @param  htim TIM Input Capture handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
{
 800effc:	b580      	push	{r7, lr}
 800effe:	b082      	sub	sp, #8
 800f000:	af00      	add	r7, sp, #0
 800f002:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 800f004:	687b      	ldr	r3, [r7, #4]
 800f006:	2b00      	cmp	r3, #0
 800f008:	d101      	bne.n	800f00e <HAL_TIM_IC_Init+0x12>
  {
    return HAL_ERROR;
 800f00a:	2301      	movs	r3, #1
 800f00c:	e049      	b.n	800f0a2 <HAL_TIM_IC_Init+0xa6>
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 800f00e:	687b      	ldr	r3, [r7, #4]
 800f010:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
 800f014:	b2db      	uxtb	r3, r3
 800f016:	2b00      	cmp	r3, #0
 800f018:	d106      	bne.n	800f028 <HAL_TIM_IC_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 800f01a:	687b      	ldr	r3, [r7, #4]
 800f01c:	2200      	movs	r2, #0
 800f01e:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->IC_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
    HAL_TIM_IC_MspInit(htim);
 800f022:	6878      	ldr	r0, [r7, #4]
 800f024:	f000 f841 	bl	800f0aa <HAL_TIM_IC_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 800f028:	687b      	ldr	r3, [r7, #4]
 800f02a:	2202      	movs	r2, #2
 800f02c:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Init the base time for the input capture */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 800f030:	687b      	ldr	r3, [r7, #4]
 800f032:	681a      	ldr	r2, [r3, #0]
 800f034:	687b      	ldr	r3, [r7, #4]
 800f036:	3304      	adds	r3, #4
 800f038:	4619      	mov	r1, r3
 800f03a:	4610      	mov	r0, r2
 800f03c:	f000 fddc 	bl	800fbf8 <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 800f040:	687b      	ldr	r3, [r7, #4]
 800f042:	2201      	movs	r2, #1
 800f044:	f883 2048 	strb.w	r2, [r3, #72]	@ 0x48

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 800f048:	687b      	ldr	r3, [r7, #4]
 800f04a:	2201      	movs	r2, #1
 800f04c:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 800f050:	687b      	ldr	r3, [r7, #4]
 800f052:	2201      	movs	r2, #1
 800f054:	f883 203f 	strb.w	r2, [r3, #63]	@ 0x3f
 800f058:	687b      	ldr	r3, [r7, #4]
 800f05a:	2201      	movs	r2, #1
 800f05c:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 800f060:	687b      	ldr	r3, [r7, #4]
 800f062:	2201      	movs	r2, #1
 800f064:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 800f068:	687b      	ldr	r3, [r7, #4]
 800f06a:	2201      	movs	r2, #1
 800f06c:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
 800f070:	687b      	ldr	r3, [r7, #4]
 800f072:	2201      	movs	r2, #1
 800f074:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 800f078:	687b      	ldr	r3, [r7, #4]
 800f07a:	2201      	movs	r2, #1
 800f07c:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 800f080:	687b      	ldr	r3, [r7, #4]
 800f082:	2201      	movs	r2, #1
 800f084:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 800f088:	687b      	ldr	r3, [r7, #4]
 800f08a:	2201      	movs	r2, #1
 800f08c:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
 800f090:	687b      	ldr	r3, [r7, #4]
 800f092:	2201      	movs	r2, #1
 800f094:	f883 2047 	strb.w	r2, [r3, #71]	@ 0x47

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 800f098:	687b      	ldr	r3, [r7, #4]
 800f09a:	2201      	movs	r2, #1
 800f09c:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  return HAL_OK;
 800f0a0:	2300      	movs	r3, #0
}
 800f0a2:	4618      	mov	r0, r3
 800f0a4:	3708      	adds	r7, #8
 800f0a6:	46bd      	mov	sp, r7
 800f0a8:	bd80      	pop	{r7, pc}

0800f0aa <HAL_TIM_IC_MspInit>:
  * @brief  Initializes the TIM Input Capture MSP.
  * @param  htim TIM Input Capture handle
  * @retval None
  */
__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
{
 800f0aa:	b480      	push	{r7}
 800f0ac:	b083      	sub	sp, #12
 800f0ae:	af00      	add	r7, sp, #0
 800f0b0:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_MspInit could be implemented in the user file
   */
}
 800f0b2:	bf00      	nop
 800f0b4:	370c      	adds	r7, #12
 800f0b6:	46bd      	mov	sp, r7
 800f0b8:	f85d 7b04 	ldr.w	r7, [sp], #4
 800f0bc:	4770      	bx	lr
	...

0800f0c0 <HAL_TIM_IC_Start_IT>:
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
 800f0c0:	b580      	push	{r7, lr}
 800f0c2:	b084      	sub	sp, #16
 800f0c4:	af00      	add	r7, sp, #0
 800f0c6:	6078      	str	r0, [r7, #4]
 800f0c8:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef status = HAL_OK;
 800f0ca:	2300      	movs	r3, #0
 800f0cc:	73fb      	strb	r3, [r7, #15]
  uint32_t tmpsmcr;

  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
 800f0ce:	683b      	ldr	r3, [r7, #0]
 800f0d0:	2b00      	cmp	r3, #0
 800f0d2:	d104      	bne.n	800f0de <HAL_TIM_IC_Start_IT+0x1e>
 800f0d4:	687b      	ldr	r3, [r7, #4]
 800f0d6:	f893 303e 	ldrb.w	r3, [r3, #62]	@ 0x3e
 800f0da:	b2db      	uxtb	r3, r3
 800f0dc:	e023      	b.n	800f126 <HAL_TIM_IC_Start_IT+0x66>
 800f0de:	683b      	ldr	r3, [r7, #0]
 800f0e0:	2b04      	cmp	r3, #4
 800f0e2:	d104      	bne.n	800f0ee <HAL_TIM_IC_Start_IT+0x2e>
 800f0e4:	687b      	ldr	r3, [r7, #4]
 800f0e6:	f893 303f 	ldrb.w	r3, [r3, #63]	@ 0x3f
 800f0ea:	b2db      	uxtb	r3, r3
 800f0ec:	e01b      	b.n	800f126 <HAL_TIM_IC_Start_IT+0x66>
 800f0ee:	683b      	ldr	r3, [r7, #0]
 800f0f0:	2b08      	cmp	r3, #8
 800f0f2:	d104      	bne.n	800f0fe <HAL_TIM_IC_Start_IT+0x3e>
 800f0f4:	687b      	ldr	r3, [r7, #4]
 800f0f6:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
 800f0fa:	b2db      	uxtb	r3, r3
 800f0fc:	e013      	b.n	800f126 <HAL_TIM_IC_Start_IT+0x66>
 800f0fe:	683b      	ldr	r3, [r7, #0]
 800f100:	2b0c      	cmp	r3, #12
 800f102:	d104      	bne.n	800f10e <HAL_TIM_IC_Start_IT+0x4e>
 800f104:	687b      	ldr	r3, [r7, #4]
 800f106:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 800f10a:	b2db      	uxtb	r3, r3
 800f10c:	e00b      	b.n	800f126 <HAL_TIM_IC_Start_IT+0x66>
 800f10e:	683b      	ldr	r3, [r7, #0]
 800f110:	2b10      	cmp	r3, #16
 800f112:	d104      	bne.n	800f11e <HAL_TIM_IC_Start_IT+0x5e>
 800f114:	687b      	ldr	r3, [r7, #4]
 800f116:	f893 3042 	ldrb.w	r3, [r3, #66]	@ 0x42
 800f11a:	b2db      	uxtb	r3, r3
 800f11c:	e003      	b.n	800f126 <HAL_TIM_IC_Start_IT+0x66>
 800f11e:	687b      	ldr	r3, [r7, #4]
 800f120:	f893 3043 	ldrb.w	r3, [r3, #67]	@ 0x43
 800f124:	b2db      	uxtb	r3, r3
 800f126:	73bb      	strb	r3, [r7, #14]
  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
 800f128:	683b      	ldr	r3, [r7, #0]
 800f12a:	2b00      	cmp	r3, #0
 800f12c:	d104      	bne.n	800f138 <HAL_TIM_IC_Start_IT+0x78>
 800f12e:	687b      	ldr	r3, [r7, #4]
 800f130:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 800f134:	b2db      	uxtb	r3, r3
 800f136:	e013      	b.n	800f160 <HAL_TIM_IC_Start_IT+0xa0>
 800f138:	683b      	ldr	r3, [r7, #0]
 800f13a:	2b04      	cmp	r3, #4
 800f13c:	d104      	bne.n	800f148 <HAL_TIM_IC_Start_IT+0x88>
 800f13e:	687b      	ldr	r3, [r7, #4]
 800f140:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 800f144:	b2db      	uxtb	r3, r3
 800f146:	e00b      	b.n	800f160 <HAL_TIM_IC_Start_IT+0xa0>
 800f148:	683b      	ldr	r3, [r7, #0]
 800f14a:	2b08      	cmp	r3, #8
 800f14c:	d104      	bne.n	800f158 <HAL_TIM_IC_Start_IT+0x98>
 800f14e:	687b      	ldr	r3, [r7, #4]
 800f150:	f893 3046 	ldrb.w	r3, [r3, #70]	@ 0x46
 800f154:	b2db      	uxtb	r3, r3
 800f156:	e003      	b.n	800f160 <HAL_TIM_IC_Start_IT+0xa0>
 800f158:	687b      	ldr	r3, [r7, #4]
 800f15a:	f893 3047 	ldrb.w	r3, [r3, #71]	@ 0x47
 800f15e:	b2db      	uxtb	r3, r3
 800f160:	737b      	strb	r3, [r7, #13]

  /* Check the parameters */
  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));

  /* Check the TIM channel state */
  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
 800f162:	7bbb      	ldrb	r3, [r7, #14]
 800f164:	2b01      	cmp	r3, #1
 800f166:	d102      	bne.n	800f16e <HAL_TIM_IC_Start_IT+0xae>
      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
 800f168:	7b7b      	ldrb	r3, [r7, #13]
 800f16a:	2b01      	cmp	r3, #1
 800f16c:	d001      	beq.n	800f172 <HAL_TIM_IC_Start_IT+0xb2>
  {
    return HAL_ERROR;
 800f16e:	2301      	movs	r3, #1
 800f170:	e0e2      	b.n	800f338 <HAL_TIM_IC_Start_IT+0x278>
  }

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
 800f172:	683b      	ldr	r3, [r7, #0]
 800f174:	2b00      	cmp	r3, #0
 800f176:	d104      	bne.n	800f182 <HAL_TIM_IC_Start_IT+0xc2>
 800f178:	687b      	ldr	r3, [r7, #4]
 800f17a:	2202      	movs	r2, #2
 800f17c:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
 800f180:	e023      	b.n	800f1ca <HAL_TIM_IC_Start_IT+0x10a>
 800f182:	683b      	ldr	r3, [r7, #0]
 800f184:	2b04      	cmp	r3, #4
 800f186:	d104      	bne.n	800f192 <HAL_TIM_IC_Start_IT+0xd2>
 800f188:	687b      	ldr	r3, [r7, #4]
 800f18a:	2202      	movs	r2, #2
 800f18c:	f883 203f 	strb.w	r2, [r3, #63]	@ 0x3f
 800f190:	e01b      	b.n	800f1ca <HAL_TIM_IC_Start_IT+0x10a>
 800f192:	683b      	ldr	r3, [r7, #0]
 800f194:	2b08      	cmp	r3, #8
 800f196:	d104      	bne.n	800f1a2 <HAL_TIM_IC_Start_IT+0xe2>
 800f198:	687b      	ldr	r3, [r7, #4]
 800f19a:	2202      	movs	r2, #2
 800f19c:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 800f1a0:	e013      	b.n	800f1ca <HAL_TIM_IC_Start_IT+0x10a>
 800f1a2:	683b      	ldr	r3, [r7, #0]
 800f1a4:	2b0c      	cmp	r3, #12
 800f1a6:	d104      	bne.n	800f1b2 <HAL_TIM_IC_Start_IT+0xf2>
 800f1a8:	687b      	ldr	r3, [r7, #4]
 800f1aa:	2202      	movs	r2, #2
 800f1ac:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 800f1b0:	e00b      	b.n	800f1ca <HAL_TIM_IC_Start_IT+0x10a>
 800f1b2:	683b      	ldr	r3, [r7, #0]
 800f1b4:	2b10      	cmp	r3, #16
 800f1b6:	d104      	bne.n	800f1c2 <HAL_TIM_IC_Start_IT+0x102>
 800f1b8:	687b      	ldr	r3, [r7, #4]
 800f1ba:	2202      	movs	r2, #2
 800f1bc:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
 800f1c0:	e003      	b.n	800f1ca <HAL_TIM_IC_Start_IT+0x10a>
 800f1c2:	687b      	ldr	r3, [r7, #4]
 800f1c4:	2202      	movs	r2, #2
 800f1c6:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
 800f1ca:	683b      	ldr	r3, [r7, #0]
 800f1cc:	2b00      	cmp	r3, #0
 800f1ce:	d104      	bne.n	800f1da <HAL_TIM_IC_Start_IT+0x11a>
 800f1d0:	687b      	ldr	r3, [r7, #4]
 800f1d2:	2202      	movs	r2, #2
 800f1d4:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 800f1d8:	e013      	b.n	800f202 <HAL_TIM_IC_Start_IT+0x142>
 800f1da:	683b      	ldr	r3, [r7, #0]
 800f1dc:	2b04      	cmp	r3, #4
 800f1de:	d104      	bne.n	800f1ea <HAL_TIM_IC_Start_IT+0x12a>
 800f1e0:	687b      	ldr	r3, [r7, #4]
 800f1e2:	2202      	movs	r2, #2
 800f1e4:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 800f1e8:	e00b      	b.n	800f202 <HAL_TIM_IC_Start_IT+0x142>
 800f1ea:	683b      	ldr	r3, [r7, #0]
 800f1ec:	2b08      	cmp	r3, #8
 800f1ee:	d104      	bne.n	800f1fa <HAL_TIM_IC_Start_IT+0x13a>
 800f1f0:	687b      	ldr	r3, [r7, #4]
 800f1f2:	2202      	movs	r2, #2
 800f1f4:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
 800f1f8:	e003      	b.n	800f202 <HAL_TIM_IC_Start_IT+0x142>
 800f1fa:	687b      	ldr	r3, [r7, #4]
 800f1fc:	2202      	movs	r2, #2
 800f1fe:	f883 2047 	strb.w	r2, [r3, #71]	@ 0x47

  switch (Channel)
 800f202:	683b      	ldr	r3, [r7, #0]
 800f204:	2b0c      	cmp	r3, #12
 800f206:	d841      	bhi.n	800f28c <HAL_TIM_IC_Start_IT+0x1cc>
 800f208:	a201      	add	r2, pc, #4	@ (adr r2, 800f210 <HAL_TIM_IC_Start_IT+0x150>)
 800f20a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800f20e:	bf00      	nop
 800f210:	0800f245 	.word	0x0800f245
 800f214:	0800f28d 	.word	0x0800f28d
 800f218:	0800f28d 	.word	0x0800f28d
 800f21c:	0800f28d 	.word	0x0800f28d
 800f220:	0800f257 	.word	0x0800f257
 800f224:	0800f28d 	.word	0x0800f28d
 800f228:	0800f28d 	.word	0x0800f28d
 800f22c:	0800f28d 	.word	0x0800f28d
 800f230:	0800f269 	.word	0x0800f269
 800f234:	0800f28d 	.word	0x0800f28d
 800f238:	0800f28d 	.word	0x0800f28d
 800f23c:	0800f28d 	.word	0x0800f28d
 800f240:	0800f27b 	.word	0x0800f27b
  {
    case TIM_CHANNEL_1:
    {
      /* Enable the TIM Capture/Compare 1 interrupt */
      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
 800f244:	687b      	ldr	r3, [r7, #4]
 800f246:	681b      	ldr	r3, [r3, #0]
 800f248:	68da      	ldr	r2, [r3, #12]
 800f24a:	687b      	ldr	r3, [r7, #4]
 800f24c:	681b      	ldr	r3, [r3, #0]
 800f24e:	f042 0202 	orr.w	r2, r2, #2
 800f252:	60da      	str	r2, [r3, #12]
      break;
 800f254:	e01d      	b.n	800f292 <HAL_TIM_IC_Start_IT+0x1d2>
    }

    case TIM_CHANNEL_2:
    {
      /* Enable the TIM Capture/Compare 2 interrupt */
      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
 800f256:	687b      	ldr	r3, [r7, #4]
 800f258:	681b      	ldr	r3, [r3, #0]
 800f25a:	68da      	ldr	r2, [r3, #12]
 800f25c:	687b      	ldr	r3, [r7, #4]
 800f25e:	681b      	ldr	r3, [r3, #0]
 800f260:	f042 0204 	orr.w	r2, r2, #4
 800f264:	60da      	str	r2, [r3, #12]
      break;
 800f266:	e014      	b.n	800f292 <HAL_TIM_IC_Start_IT+0x1d2>
    }

    case TIM_CHANNEL_3:
    {
      /* Enable the TIM Capture/Compare 3 interrupt */
      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
 800f268:	687b      	ldr	r3, [r7, #4]
 800f26a:	681b      	ldr	r3, [r3, #0]
 800f26c:	68da      	ldr	r2, [r3, #12]
 800f26e:	687b      	ldr	r3, [r7, #4]
 800f270:	681b      	ldr	r3, [r3, #0]
 800f272:	f042 0208 	orr.w	r2, r2, #8
 800f276:	60da      	str	r2, [r3, #12]
      break;
 800f278:	e00b      	b.n	800f292 <HAL_TIM_IC_Start_IT+0x1d2>
    }

    case TIM_CHANNEL_4:
    {
      /* Enable the TIM Capture/Compare 4 interrupt */
      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
 800f27a:	687b      	ldr	r3, [r7, #4]
 800f27c:	681b      	ldr	r3, [r3, #0]
 800f27e:	68da      	ldr	r2, [r3, #12]
 800f280:	687b      	ldr	r3, [r7, #4]
 800f282:	681b      	ldr	r3, [r3, #0]
 800f284:	f042 0210 	orr.w	r2, r2, #16
 800f288:	60da      	str	r2, [r3, #12]
      break;
 800f28a:	e002      	b.n	800f292 <HAL_TIM_IC_Start_IT+0x1d2>
    }

    default:
      status = HAL_ERROR;
 800f28c:	2301      	movs	r3, #1
 800f28e:	73fb      	strb	r3, [r7, #15]
      break;
 800f290:	bf00      	nop
  }

  if (status == HAL_OK)
 800f292:	7bfb      	ldrb	r3, [r7, #15]
 800f294:	2b00      	cmp	r3, #0
 800f296:	d14e      	bne.n	800f336 <HAL_TIM_IC_Start_IT+0x276>
  {
    /* Enable the Input Capture channel */
    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 800f298:	687b      	ldr	r3, [r7, #4]
 800f29a:	681b      	ldr	r3, [r3, #0]
 800f29c:	2201      	movs	r2, #1
 800f29e:	6839      	ldr	r1, [r7, #0]
 800f2a0:	4618      	mov	r0, r3
 800f2a2:	f001 f9ed 	bl	8010680 <TIM_CCxChannelCmd>

    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 800f2a6:	687b      	ldr	r3, [r7, #4]
 800f2a8:	681b      	ldr	r3, [r3, #0]
 800f2aa:	4a25      	ldr	r2, [pc, #148]	@ (800f340 <HAL_TIM_IC_Start_IT+0x280>)
 800f2ac:	4293      	cmp	r3, r2
 800f2ae:	d022      	beq.n	800f2f6 <HAL_TIM_IC_Start_IT+0x236>
 800f2b0:	687b      	ldr	r3, [r7, #4]
 800f2b2:	681b      	ldr	r3, [r3, #0]
 800f2b4:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800f2b8:	d01d      	beq.n	800f2f6 <HAL_TIM_IC_Start_IT+0x236>
 800f2ba:	687b      	ldr	r3, [r7, #4]
 800f2bc:	681b      	ldr	r3, [r3, #0]
 800f2be:	4a21      	ldr	r2, [pc, #132]	@ (800f344 <HAL_TIM_IC_Start_IT+0x284>)
 800f2c0:	4293      	cmp	r3, r2
 800f2c2:	d018      	beq.n	800f2f6 <HAL_TIM_IC_Start_IT+0x236>
 800f2c4:	687b      	ldr	r3, [r7, #4]
 800f2c6:	681b      	ldr	r3, [r3, #0]
 800f2c8:	4a1f      	ldr	r2, [pc, #124]	@ (800f348 <HAL_TIM_IC_Start_IT+0x288>)
 800f2ca:	4293      	cmp	r3, r2
 800f2cc:	d013      	beq.n	800f2f6 <HAL_TIM_IC_Start_IT+0x236>
 800f2ce:	687b      	ldr	r3, [r7, #4]
 800f2d0:	681b      	ldr	r3, [r3, #0]
 800f2d2:	4a1e      	ldr	r2, [pc, #120]	@ (800f34c <HAL_TIM_IC_Start_IT+0x28c>)
 800f2d4:	4293      	cmp	r3, r2
 800f2d6:	d00e      	beq.n	800f2f6 <HAL_TIM_IC_Start_IT+0x236>
 800f2d8:	687b      	ldr	r3, [r7, #4]
 800f2da:	681b      	ldr	r3, [r3, #0]
 800f2dc:	4a1c      	ldr	r2, [pc, #112]	@ (800f350 <HAL_TIM_IC_Start_IT+0x290>)
 800f2de:	4293      	cmp	r3, r2
 800f2e0:	d009      	beq.n	800f2f6 <HAL_TIM_IC_Start_IT+0x236>
 800f2e2:	687b      	ldr	r3, [r7, #4]
 800f2e4:	681b      	ldr	r3, [r3, #0]
 800f2e6:	4a1b      	ldr	r2, [pc, #108]	@ (800f354 <HAL_TIM_IC_Start_IT+0x294>)
 800f2e8:	4293      	cmp	r3, r2
 800f2ea:	d004      	beq.n	800f2f6 <HAL_TIM_IC_Start_IT+0x236>
 800f2ec:	687b      	ldr	r3, [r7, #4]
 800f2ee:	681b      	ldr	r3, [r3, #0]
 800f2f0:	4a19      	ldr	r2, [pc, #100]	@ (800f358 <HAL_TIM_IC_Start_IT+0x298>)
 800f2f2:	4293      	cmp	r3, r2
 800f2f4:	d115      	bne.n	800f322 <HAL_TIM_IC_Start_IT+0x262>
    {
      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 800f2f6:	687b      	ldr	r3, [r7, #4]
 800f2f8:	681b      	ldr	r3, [r3, #0]
 800f2fa:	689a      	ldr	r2, [r3, #8]
 800f2fc:	4b17      	ldr	r3, [pc, #92]	@ (800f35c <HAL_TIM_IC_Start_IT+0x29c>)
 800f2fe:	4013      	ands	r3, r2
 800f300:	60bb      	str	r3, [r7, #8]
      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800f302:	68bb      	ldr	r3, [r7, #8]
 800f304:	2b06      	cmp	r3, #6
 800f306:	d015      	beq.n	800f334 <HAL_TIM_IC_Start_IT+0x274>
 800f308:	68bb      	ldr	r3, [r7, #8]
 800f30a:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 800f30e:	d011      	beq.n	800f334 <HAL_TIM_IC_Start_IT+0x274>
      {
        __HAL_TIM_ENABLE(htim);
 800f310:	687b      	ldr	r3, [r7, #4]
 800f312:	681b      	ldr	r3, [r3, #0]
 800f314:	681a      	ldr	r2, [r3, #0]
 800f316:	687b      	ldr	r3, [r7, #4]
 800f318:	681b      	ldr	r3, [r3, #0]
 800f31a:	f042 0201 	orr.w	r2, r2, #1
 800f31e:	601a      	str	r2, [r3, #0]
      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800f320:	e008      	b.n	800f334 <HAL_TIM_IC_Start_IT+0x274>
      }
    }
    else
    {
      __HAL_TIM_ENABLE(htim);
 800f322:	687b      	ldr	r3, [r7, #4]
 800f324:	681b      	ldr	r3, [r3, #0]
 800f326:	681a      	ldr	r2, [r3, #0]
 800f328:	687b      	ldr	r3, [r7, #4]
 800f32a:	681b      	ldr	r3, [r3, #0]
 800f32c:	f042 0201 	orr.w	r2, r2, #1
 800f330:	601a      	str	r2, [r3, #0]
 800f332:	e000      	b.n	800f336 <HAL_TIM_IC_Start_IT+0x276>
      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800f334:	bf00      	nop
    }
  }

  /* Return function status */
  return status;
 800f336:	7bfb      	ldrb	r3, [r7, #15]
}
 800f338:	4618      	mov	r0, r3
 800f33a:	3710      	adds	r7, #16
 800f33c:	46bd      	mov	sp, r7
 800f33e:	bd80      	pop	{r7, pc}
 800f340:	40010000 	.word	0x40010000
 800f344:	40000400 	.word	0x40000400
 800f348:	40000800 	.word	0x40000800
 800f34c:	40000c00 	.word	0x40000c00
 800f350:	40010400 	.word	0x40010400
 800f354:	40001800 	.word	0x40001800
 800f358:	40014000 	.word	0x40014000
 800f35c:	00010007 	.word	0x00010007

0800f360 <HAL_TIM_IRQHandler>:
  * @brief  This function handles TIM interrupts requests.
  * @param  htim TIM  handle
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
 800f360:	b580      	push	{r7, lr}
 800f362:	b084      	sub	sp, #16
 800f364:	af00      	add	r7, sp, #0
 800f366:	6078      	str	r0, [r7, #4]
  uint32_t itsource = htim->Instance->DIER;
 800f368:	687b      	ldr	r3, [r7, #4]
 800f36a:	681b      	ldr	r3, [r3, #0]
 800f36c:	68db      	ldr	r3, [r3, #12]
 800f36e:	60fb      	str	r3, [r7, #12]
  uint32_t itflag   = htim->Instance->SR;
 800f370:	687b      	ldr	r3, [r7, #4]
 800f372:	681b      	ldr	r3, [r3, #0]
 800f374:	691b      	ldr	r3, [r3, #16]
 800f376:	60bb      	str	r3, [r7, #8]

  /* Capture compare 1 event */
  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
 800f378:	68bb      	ldr	r3, [r7, #8]
 800f37a:	f003 0302 	and.w	r3, r3, #2
 800f37e:	2b00      	cmp	r3, #0
 800f380:	d020      	beq.n	800f3c4 <HAL_TIM_IRQHandler+0x64>
  {
    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
 800f382:	68fb      	ldr	r3, [r7, #12]
 800f384:	f003 0302 	and.w	r3, r3, #2
 800f388:	2b00      	cmp	r3, #0
 800f38a:	d01b      	beq.n	800f3c4 <HAL_TIM_IRQHandler+0x64>
    {
      {
        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
 800f38c:	687b      	ldr	r3, [r7, #4]
 800f38e:	681b      	ldr	r3, [r3, #0]
 800f390:	f06f 0202 	mvn.w	r2, #2
 800f394:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 800f396:	687b      	ldr	r3, [r7, #4]
 800f398:	2201      	movs	r2, #1
 800f39a:	771a      	strb	r2, [r3, #28]

        /* Input capture event */
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 800f39c:	687b      	ldr	r3, [r7, #4]
 800f39e:	681b      	ldr	r3, [r3, #0]
 800f3a0:	699b      	ldr	r3, [r3, #24]
 800f3a2:	f003 0303 	and.w	r3, r3, #3
 800f3a6:	2b00      	cmp	r3, #0
 800f3a8:	d003      	beq.n	800f3b2 <HAL_TIM_IRQHandler+0x52>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->IC_CaptureCallback(htim);
#else
          HAL_TIM_IC_CaptureCallback(htim);
 800f3aa:	6878      	ldr	r0, [r7, #4]
 800f3ac:	f7f2 fade 	bl	800196c <HAL_TIM_IC_CaptureCallback>
 800f3b0:	e005      	b.n	800f3be <HAL_TIM_IRQHandler+0x5e>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->OC_DelayElapsedCallback(htim);
          htim->PWM_PulseFinishedCallback(htim);
#else
          HAL_TIM_OC_DelayElapsedCallback(htim);
 800f3b2:	6878      	ldr	r0, [r7, #4]
 800f3b4:	f000 fbc8 	bl	800fb48 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 800f3b8:	6878      	ldr	r0, [r7, #4]
 800f3ba:	f000 fbcf 	bl	800fb5c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800f3be:	687b      	ldr	r3, [r7, #4]
 800f3c0:	2200      	movs	r2, #0
 800f3c2:	771a      	strb	r2, [r3, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
 800f3c4:	68bb      	ldr	r3, [r7, #8]
 800f3c6:	f003 0304 	and.w	r3, r3, #4
 800f3ca:	2b00      	cmp	r3, #0
 800f3cc:	d020      	beq.n	800f410 <HAL_TIM_IRQHandler+0xb0>
  {
    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
 800f3ce:	68fb      	ldr	r3, [r7, #12]
 800f3d0:	f003 0304 	and.w	r3, r3, #4
 800f3d4:	2b00      	cmp	r3, #0
 800f3d6:	d01b      	beq.n	800f410 <HAL_TIM_IRQHandler+0xb0>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
 800f3d8:	687b      	ldr	r3, [r7, #4]
 800f3da:	681b      	ldr	r3, [r3, #0]
 800f3dc:	f06f 0204 	mvn.w	r2, #4
 800f3e0:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 800f3e2:	687b      	ldr	r3, [r7, #4]
 800f3e4:	2202      	movs	r2, #2
 800f3e6:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 800f3e8:	687b      	ldr	r3, [r7, #4]
 800f3ea:	681b      	ldr	r3, [r3, #0]
 800f3ec:	699b      	ldr	r3, [r3, #24]
 800f3ee:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 800f3f2:	2b00      	cmp	r3, #0
 800f3f4:	d003      	beq.n	800f3fe <HAL_TIM_IRQHandler+0x9e>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800f3f6:	6878      	ldr	r0, [r7, #4]
 800f3f8:	f7f2 fab8 	bl	800196c <HAL_TIM_IC_CaptureCallback>
 800f3fc:	e005      	b.n	800f40a <HAL_TIM_IRQHandler+0xaa>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 800f3fe:	6878      	ldr	r0, [r7, #4]
 800f400:	f000 fba2 	bl	800fb48 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 800f404:	6878      	ldr	r0, [r7, #4]
 800f406:	f000 fba9 	bl	800fb5c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800f40a:	687b      	ldr	r3, [r7, #4]
 800f40c:	2200      	movs	r2, #0
 800f40e:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 3 event */
  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
 800f410:	68bb      	ldr	r3, [r7, #8]
 800f412:	f003 0308 	and.w	r3, r3, #8
 800f416:	2b00      	cmp	r3, #0
 800f418:	d020      	beq.n	800f45c <HAL_TIM_IRQHandler+0xfc>
  {
    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
 800f41a:	68fb      	ldr	r3, [r7, #12]
 800f41c:	f003 0308 	and.w	r3, r3, #8
 800f420:	2b00      	cmp	r3, #0
 800f422:	d01b      	beq.n	800f45c <HAL_TIM_IRQHandler+0xfc>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
 800f424:	687b      	ldr	r3, [r7, #4]
 800f426:	681b      	ldr	r3, [r3, #0]
 800f428:	f06f 0208 	mvn.w	r2, #8
 800f42c:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 800f42e:	687b      	ldr	r3, [r7, #4]
 800f430:	2204      	movs	r2, #4
 800f432:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 800f434:	687b      	ldr	r3, [r7, #4]
 800f436:	681b      	ldr	r3, [r3, #0]
 800f438:	69db      	ldr	r3, [r3, #28]
 800f43a:	f003 0303 	and.w	r3, r3, #3
 800f43e:	2b00      	cmp	r3, #0
 800f440:	d003      	beq.n	800f44a <HAL_TIM_IRQHandler+0xea>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800f442:	6878      	ldr	r0, [r7, #4]
 800f444:	f7f2 fa92 	bl	800196c <HAL_TIM_IC_CaptureCallback>
 800f448:	e005      	b.n	800f456 <HAL_TIM_IRQHandler+0xf6>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 800f44a:	6878      	ldr	r0, [r7, #4]
 800f44c:	f000 fb7c 	bl	800fb48 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 800f450:	6878      	ldr	r0, [r7, #4]
 800f452:	f000 fb83 	bl	800fb5c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800f456:	687b      	ldr	r3, [r7, #4]
 800f458:	2200      	movs	r2, #0
 800f45a:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 4 event */
  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
 800f45c:	68bb      	ldr	r3, [r7, #8]
 800f45e:	f003 0310 	and.w	r3, r3, #16
 800f462:	2b00      	cmp	r3, #0
 800f464:	d020      	beq.n	800f4a8 <HAL_TIM_IRQHandler+0x148>
  {
    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
 800f466:	68fb      	ldr	r3, [r7, #12]
 800f468:	f003 0310 	and.w	r3, r3, #16
 800f46c:	2b00      	cmp	r3, #0
 800f46e:	d01b      	beq.n	800f4a8 <HAL_TIM_IRQHandler+0x148>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
 800f470:	687b      	ldr	r3, [r7, #4]
 800f472:	681b      	ldr	r3, [r3, #0]
 800f474:	f06f 0210 	mvn.w	r2, #16
 800f478:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 800f47a:	687b      	ldr	r3, [r7, #4]
 800f47c:	2208      	movs	r2, #8
 800f47e:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 800f480:	687b      	ldr	r3, [r7, #4]
 800f482:	681b      	ldr	r3, [r3, #0]
 800f484:	69db      	ldr	r3, [r3, #28]
 800f486:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 800f48a:	2b00      	cmp	r3, #0
 800f48c:	d003      	beq.n	800f496 <HAL_TIM_IRQHandler+0x136>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800f48e:	6878      	ldr	r0, [r7, #4]
 800f490:	f7f2 fa6c 	bl	800196c <HAL_TIM_IC_CaptureCallback>
 800f494:	e005      	b.n	800f4a2 <HAL_TIM_IRQHandler+0x142>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 800f496:	6878      	ldr	r0, [r7, #4]
 800f498:	f000 fb56 	bl	800fb48 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 800f49c:	6878      	ldr	r0, [r7, #4]
 800f49e:	f000 fb5d 	bl	800fb5c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800f4a2:	687b      	ldr	r3, [r7, #4]
 800f4a4:	2200      	movs	r2, #0
 800f4a6:	771a      	strb	r2, [r3, #28]
    }
  }
  /* TIM Update event */
  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
 800f4a8:	68bb      	ldr	r3, [r7, #8]
 800f4aa:	f003 0301 	and.w	r3, r3, #1
 800f4ae:	2b00      	cmp	r3, #0
 800f4b0:	d00c      	beq.n	800f4cc <HAL_TIM_IRQHandler+0x16c>
  {
    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
 800f4b2:	68fb      	ldr	r3, [r7, #12]
 800f4b4:	f003 0301 	and.w	r3, r3, #1
 800f4b8:	2b00      	cmp	r3, #0
 800f4ba:	d007      	beq.n	800f4cc <HAL_TIM_IRQHandler+0x16c>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
 800f4bc:	687b      	ldr	r3, [r7, #4]
 800f4be:	681b      	ldr	r3, [r3, #0]
 800f4c0:	f06f 0201 	mvn.w	r2, #1
 800f4c4:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->PeriodElapsedCallback(htim);
#else
      HAL_TIM_PeriodElapsedCallback(htim);
 800f4c6:	6878      	ldr	r0, [r7, #4]
 800f4c8:	f7f2 fc5a 	bl	8001d80 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break input event */
  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
 800f4cc:	68bb      	ldr	r3, [r7, #8]
 800f4ce:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 800f4d2:	2b00      	cmp	r3, #0
 800f4d4:	d104      	bne.n	800f4e0 <HAL_TIM_IRQHandler+0x180>
      ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
 800f4d6:	68bb      	ldr	r3, [r7, #8]
 800f4d8:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
 800f4dc:	2b00      	cmp	r3, #0
 800f4de:	d00c      	beq.n	800f4fa <HAL_TIM_IRQHandler+0x19a>
  {
    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
 800f4e0:	68fb      	ldr	r3, [r7, #12]
 800f4e2:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 800f4e6:	2b00      	cmp	r3, #0
 800f4e8:	d007      	beq.n	800f4fa <HAL_TIM_IRQHandler+0x19a>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
 800f4ea:	687b      	ldr	r3, [r7, #4]
 800f4ec:	681b      	ldr	r3, [r3, #0]
 800f4ee:	f46f 5202 	mvn.w	r2, #8320	@ 0x2080
 800f4f2:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->BreakCallback(htim);
#else
      HAL_TIMEx_BreakCallback(htim);
 800f4f4:	6878      	ldr	r0, [r7, #4]
 800f4f6:	f001 f9ff 	bl	80108f8 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break2 input event */
  if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
 800f4fa:	68bb      	ldr	r3, [r7, #8]
 800f4fc:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800f500:	2b00      	cmp	r3, #0
 800f502:	d00c      	beq.n	800f51e <HAL_TIM_IRQHandler+0x1be>
  {
    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
 800f504:	68fb      	ldr	r3, [r7, #12]
 800f506:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 800f50a:	2b00      	cmp	r3, #0
 800f50c:	d007      	beq.n	800f51e <HAL_TIM_IRQHandler+0x1be>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
 800f50e:	687b      	ldr	r3, [r7, #4]
 800f510:	681b      	ldr	r3, [r3, #0]
 800f512:	f46f 7280 	mvn.w	r2, #256	@ 0x100
 800f516:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->Break2Callback(htim);
#else
      HAL_TIMEx_Break2Callback(htim);
 800f518:	6878      	ldr	r0, [r7, #4]
 800f51a:	f001 f9f7 	bl	801090c <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Trigger detection event */
  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
 800f51e:	68bb      	ldr	r3, [r7, #8]
 800f520:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800f524:	2b00      	cmp	r3, #0
 800f526:	d00c      	beq.n	800f542 <HAL_TIM_IRQHandler+0x1e2>
  {
    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
 800f528:	68fb      	ldr	r3, [r7, #12]
 800f52a:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 800f52e:	2b00      	cmp	r3, #0
 800f530:	d007      	beq.n	800f542 <HAL_TIM_IRQHandler+0x1e2>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
 800f532:	687b      	ldr	r3, [r7, #4]
 800f534:	681b      	ldr	r3, [r3, #0]
 800f536:	f06f 0240 	mvn.w	r2, #64	@ 0x40
 800f53a:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->TriggerCallback(htim);
#else
      HAL_TIM_TriggerCallback(htim);
 800f53c:	6878      	ldr	r0, [r7, #4]
 800f53e:	f000 fb17 	bl	800fb70 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM commutation event */
  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
 800f542:	68bb      	ldr	r3, [r7, #8]
 800f544:	f003 0320 	and.w	r3, r3, #32
 800f548:	2b00      	cmp	r3, #0
 800f54a:	d00c      	beq.n	800f566 <HAL_TIM_IRQHandler+0x206>
  {
    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
 800f54c:	68fb      	ldr	r3, [r7, #12]
 800f54e:	f003 0320 	and.w	r3, r3, #32
 800f552:	2b00      	cmp	r3, #0
 800f554:	d007      	beq.n	800f566 <HAL_TIM_IRQHandler+0x206>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
 800f556:	687b      	ldr	r3, [r7, #4]
 800f558:	681b      	ldr	r3, [r3, #0]
 800f55a:	f06f 0220 	mvn.w	r2, #32
 800f55e:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->CommutationCallback(htim);
#else
      HAL_TIMEx_CommutCallback(htim);
 800f560:	6878      	ldr	r0, [r7, #4]
 800f562:	f001 f9bf 	bl	80108e4 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
}
 800f566:	bf00      	nop
 800f568:	3710      	adds	r7, #16
 800f56a:	46bd      	mov	sp, r7
 800f56c:	bd80      	pop	{r7, pc}

0800f56e <HAL_TIM_IC_ConfigChannel>:
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
{
 800f56e:	b580      	push	{r7, lr}
 800f570:	b086      	sub	sp, #24
 800f572:	af00      	add	r7, sp, #0
 800f574:	60f8      	str	r0, [r7, #12]
 800f576:	60b9      	str	r1, [r7, #8]
 800f578:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 800f57a:	2300      	movs	r3, #0
 800f57c:	75fb      	strb	r3, [r7, #23]
  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));

  /* Process Locked */
  __HAL_LOCK(htim);
 800f57e:	68fb      	ldr	r3, [r7, #12]
 800f580:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
 800f584:	2b01      	cmp	r3, #1
 800f586:	d101      	bne.n	800f58c <HAL_TIM_IC_ConfigChannel+0x1e>
 800f588:	2302      	movs	r3, #2
 800f58a:	e088      	b.n	800f69e <HAL_TIM_IC_ConfigChannel+0x130>
 800f58c:	68fb      	ldr	r3, [r7, #12]
 800f58e:	2201      	movs	r2, #1
 800f590:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  if (Channel == TIM_CHANNEL_1)
 800f594:	687b      	ldr	r3, [r7, #4]
 800f596:	2b00      	cmp	r3, #0
 800f598:	d11b      	bne.n	800f5d2 <HAL_TIM_IC_ConfigChannel+0x64>
  {
    /* TI1 Configuration */
    TIM_TI1_SetConfig(htim->Instance,
 800f59a:	68fb      	ldr	r3, [r7, #12]
 800f59c:	6818      	ldr	r0, [r3, #0]
                      sConfig->ICPolarity,
 800f59e:	68bb      	ldr	r3, [r7, #8]
 800f5a0:	6819      	ldr	r1, [r3, #0]
                      sConfig->ICSelection,
 800f5a2:	68bb      	ldr	r3, [r7, #8]
 800f5a4:	685a      	ldr	r2, [r3, #4]
                      sConfig->ICFilter);
 800f5a6:	68bb      	ldr	r3, [r7, #8]
 800f5a8:	68db      	ldr	r3, [r3, #12]
    TIM_TI1_SetConfig(htim->Instance,
 800f5aa:	f000 fea1 	bl	80102f0 <TIM_TI1_SetConfig>

    /* Reset the IC1PSC Bits */
    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
 800f5ae:	68fb      	ldr	r3, [r7, #12]
 800f5b0:	681b      	ldr	r3, [r3, #0]
 800f5b2:	699a      	ldr	r2, [r3, #24]
 800f5b4:	68fb      	ldr	r3, [r7, #12]
 800f5b6:	681b      	ldr	r3, [r3, #0]
 800f5b8:	f022 020c 	bic.w	r2, r2, #12
 800f5bc:	619a      	str	r2, [r3, #24]

    /* Set the IC1PSC value */
    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
 800f5be:	68fb      	ldr	r3, [r7, #12]
 800f5c0:	681b      	ldr	r3, [r3, #0]
 800f5c2:	6999      	ldr	r1, [r3, #24]
 800f5c4:	68bb      	ldr	r3, [r7, #8]
 800f5c6:	689a      	ldr	r2, [r3, #8]
 800f5c8:	68fb      	ldr	r3, [r7, #12]
 800f5ca:	681b      	ldr	r3, [r3, #0]
 800f5cc:	430a      	orrs	r2, r1
 800f5ce:	619a      	str	r2, [r3, #24]
 800f5d0:	e060      	b.n	800f694 <HAL_TIM_IC_ConfigChannel+0x126>
  }
  else if (Channel == TIM_CHANNEL_2)
 800f5d2:	687b      	ldr	r3, [r7, #4]
 800f5d4:	2b04      	cmp	r3, #4
 800f5d6:	d11c      	bne.n	800f612 <HAL_TIM_IC_ConfigChannel+0xa4>
  {
    /* TI2 Configuration */
    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

    TIM_TI2_SetConfig(htim->Instance,
 800f5d8:	68fb      	ldr	r3, [r7, #12]
 800f5da:	6818      	ldr	r0, [r3, #0]
                      sConfig->ICPolarity,
 800f5dc:	68bb      	ldr	r3, [r7, #8]
 800f5de:	6819      	ldr	r1, [r3, #0]
                      sConfig->ICSelection,
 800f5e0:	68bb      	ldr	r3, [r7, #8]
 800f5e2:	685a      	ldr	r2, [r3, #4]
                      sConfig->ICFilter);
 800f5e4:	68bb      	ldr	r3, [r7, #8]
 800f5e6:	68db      	ldr	r3, [r3, #12]
    TIM_TI2_SetConfig(htim->Instance,
 800f5e8:	f000 ff25 	bl	8010436 <TIM_TI2_SetConfig>

    /* Reset the IC2PSC Bits */
    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
 800f5ec:	68fb      	ldr	r3, [r7, #12]
 800f5ee:	681b      	ldr	r3, [r3, #0]
 800f5f0:	699a      	ldr	r2, [r3, #24]
 800f5f2:	68fb      	ldr	r3, [r7, #12]
 800f5f4:	681b      	ldr	r3, [r3, #0]
 800f5f6:	f422 6240 	bic.w	r2, r2, #3072	@ 0xc00
 800f5fa:	619a      	str	r2, [r3, #24]

    /* Set the IC2PSC value */
    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
 800f5fc:	68fb      	ldr	r3, [r7, #12]
 800f5fe:	681b      	ldr	r3, [r3, #0]
 800f600:	6999      	ldr	r1, [r3, #24]
 800f602:	68bb      	ldr	r3, [r7, #8]
 800f604:	689b      	ldr	r3, [r3, #8]
 800f606:	021a      	lsls	r2, r3, #8
 800f608:	68fb      	ldr	r3, [r7, #12]
 800f60a:	681b      	ldr	r3, [r3, #0]
 800f60c:	430a      	orrs	r2, r1
 800f60e:	619a      	str	r2, [r3, #24]
 800f610:	e040      	b.n	800f694 <HAL_TIM_IC_ConfigChannel+0x126>
  }
  else if (Channel == TIM_CHANNEL_3)
 800f612:	687b      	ldr	r3, [r7, #4]
 800f614:	2b08      	cmp	r3, #8
 800f616:	d11b      	bne.n	800f650 <HAL_TIM_IC_ConfigChannel+0xe2>
  {
    /* TI3 Configuration */
    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));

    TIM_TI3_SetConfig(htim->Instance,
 800f618:	68fb      	ldr	r3, [r7, #12]
 800f61a:	6818      	ldr	r0, [r3, #0]
                      sConfig->ICPolarity,
 800f61c:	68bb      	ldr	r3, [r7, #8]
 800f61e:	6819      	ldr	r1, [r3, #0]
                      sConfig->ICSelection,
 800f620:	68bb      	ldr	r3, [r7, #8]
 800f622:	685a      	ldr	r2, [r3, #4]
                      sConfig->ICFilter);
 800f624:	68bb      	ldr	r3, [r7, #8]
 800f626:	68db      	ldr	r3, [r3, #12]
    TIM_TI3_SetConfig(htim->Instance,
 800f628:	f000 ff72 	bl	8010510 <TIM_TI3_SetConfig>

    /* Reset the IC3PSC Bits */
    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
 800f62c:	68fb      	ldr	r3, [r7, #12]
 800f62e:	681b      	ldr	r3, [r3, #0]
 800f630:	69da      	ldr	r2, [r3, #28]
 800f632:	68fb      	ldr	r3, [r7, #12]
 800f634:	681b      	ldr	r3, [r3, #0]
 800f636:	f022 020c 	bic.w	r2, r2, #12
 800f63a:	61da      	str	r2, [r3, #28]

    /* Set the IC3PSC value */
    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
 800f63c:	68fb      	ldr	r3, [r7, #12]
 800f63e:	681b      	ldr	r3, [r3, #0]
 800f640:	69d9      	ldr	r1, [r3, #28]
 800f642:	68bb      	ldr	r3, [r7, #8]
 800f644:	689a      	ldr	r2, [r3, #8]
 800f646:	68fb      	ldr	r3, [r7, #12]
 800f648:	681b      	ldr	r3, [r3, #0]
 800f64a:	430a      	orrs	r2, r1
 800f64c:	61da      	str	r2, [r3, #28]
 800f64e:	e021      	b.n	800f694 <HAL_TIM_IC_ConfigChannel+0x126>
  }
  else if (Channel == TIM_CHANNEL_4)
 800f650:	687b      	ldr	r3, [r7, #4]
 800f652:	2b0c      	cmp	r3, #12
 800f654:	d11c      	bne.n	800f690 <HAL_TIM_IC_ConfigChannel+0x122>
  {
    /* TI4 Configuration */
    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));

    TIM_TI4_SetConfig(htim->Instance,
 800f656:	68fb      	ldr	r3, [r7, #12]
 800f658:	6818      	ldr	r0, [r3, #0]
                      sConfig->ICPolarity,
 800f65a:	68bb      	ldr	r3, [r7, #8]
 800f65c:	6819      	ldr	r1, [r3, #0]
                      sConfig->ICSelection,
 800f65e:	68bb      	ldr	r3, [r7, #8]
 800f660:	685a      	ldr	r2, [r3, #4]
                      sConfig->ICFilter);
 800f662:	68bb      	ldr	r3, [r7, #8]
 800f664:	68db      	ldr	r3, [r3, #12]
    TIM_TI4_SetConfig(htim->Instance,
 800f666:	f000 ff8f 	bl	8010588 <TIM_TI4_SetConfig>

    /* Reset the IC4PSC Bits */
    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
 800f66a:	68fb      	ldr	r3, [r7, #12]
 800f66c:	681b      	ldr	r3, [r3, #0]
 800f66e:	69da      	ldr	r2, [r3, #28]
 800f670:	68fb      	ldr	r3, [r7, #12]
 800f672:	681b      	ldr	r3, [r3, #0]
 800f674:	f422 6240 	bic.w	r2, r2, #3072	@ 0xc00
 800f678:	61da      	str	r2, [r3, #28]

    /* Set the IC4PSC value */
    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
 800f67a:	68fb      	ldr	r3, [r7, #12]
 800f67c:	681b      	ldr	r3, [r3, #0]
 800f67e:	69d9      	ldr	r1, [r3, #28]
 800f680:	68bb      	ldr	r3, [r7, #8]
 800f682:	689b      	ldr	r3, [r3, #8]
 800f684:	021a      	lsls	r2, r3, #8
 800f686:	68fb      	ldr	r3, [r7, #12]
 800f688:	681b      	ldr	r3, [r3, #0]
 800f68a:	430a      	orrs	r2, r1
 800f68c:	61da      	str	r2, [r3, #28]
 800f68e:	e001      	b.n	800f694 <HAL_TIM_IC_ConfigChannel+0x126>
  }
  else
  {
    status = HAL_ERROR;
 800f690:	2301      	movs	r3, #1
 800f692:	75fb      	strb	r3, [r7, #23]
  }

  __HAL_UNLOCK(htim);
 800f694:	68fb      	ldr	r3, [r7, #12]
 800f696:	2200      	movs	r2, #0
 800f698:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  return status;
 800f69c:	7dfb      	ldrb	r3, [r7, #23]
}
 800f69e:	4618      	mov	r0, r3
 800f6a0:	3718      	adds	r7, #24
 800f6a2:	46bd      	mov	sp, r7
 800f6a4:	bd80      	pop	{r7, pc}
	...

0800f6a8 <HAL_TIM_PWM_ConfigChannel>:
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
                                            const TIM_OC_InitTypeDef *sConfig,
                                            uint32_t Channel)
{
 800f6a8:	b580      	push	{r7, lr}
 800f6aa:	b086      	sub	sp, #24
 800f6ac:	af00      	add	r7, sp, #0
 800f6ae:	60f8      	str	r0, [r7, #12]
 800f6b0:	60b9      	str	r1, [r7, #8]
 800f6b2:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 800f6b4:	2300      	movs	r3, #0
 800f6b6:	75fb      	strb	r3, [r7, #23]
  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));

  /* Process Locked */
  __HAL_LOCK(htim);
 800f6b8:	68fb      	ldr	r3, [r7, #12]
 800f6ba:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
 800f6be:	2b01      	cmp	r3, #1
 800f6c0:	d101      	bne.n	800f6c6 <HAL_TIM_PWM_ConfigChannel+0x1e>
 800f6c2:	2302      	movs	r3, #2
 800f6c4:	e0ff      	b.n	800f8c6 <HAL_TIM_PWM_ConfigChannel+0x21e>
 800f6c6:	68fb      	ldr	r3, [r7, #12]
 800f6c8:	2201      	movs	r2, #1
 800f6ca:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  switch (Channel)
 800f6ce:	687b      	ldr	r3, [r7, #4]
 800f6d0:	2b14      	cmp	r3, #20
 800f6d2:	f200 80f0 	bhi.w	800f8b6 <HAL_TIM_PWM_ConfigChannel+0x20e>
 800f6d6:	a201      	add	r2, pc, #4	@ (adr r2, 800f6dc <HAL_TIM_PWM_ConfigChannel+0x34>)
 800f6d8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800f6dc:	0800f731 	.word	0x0800f731
 800f6e0:	0800f8b7 	.word	0x0800f8b7
 800f6e4:	0800f8b7 	.word	0x0800f8b7
 800f6e8:	0800f8b7 	.word	0x0800f8b7
 800f6ec:	0800f771 	.word	0x0800f771
 800f6f0:	0800f8b7 	.word	0x0800f8b7
 800f6f4:	0800f8b7 	.word	0x0800f8b7
 800f6f8:	0800f8b7 	.word	0x0800f8b7
 800f6fc:	0800f7b3 	.word	0x0800f7b3
 800f700:	0800f8b7 	.word	0x0800f8b7
 800f704:	0800f8b7 	.word	0x0800f8b7
 800f708:	0800f8b7 	.word	0x0800f8b7
 800f70c:	0800f7f3 	.word	0x0800f7f3
 800f710:	0800f8b7 	.word	0x0800f8b7
 800f714:	0800f8b7 	.word	0x0800f8b7
 800f718:	0800f8b7 	.word	0x0800f8b7
 800f71c:	0800f835 	.word	0x0800f835
 800f720:	0800f8b7 	.word	0x0800f8b7
 800f724:	0800f8b7 	.word	0x0800f8b7
 800f728:	0800f8b7 	.word	0x0800f8b7
 800f72c:	0800f875 	.word	0x0800f875
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));

      /* Configure the Channel 1 in PWM mode */
      TIM_OC1_SetConfig(htim->Instance, sConfig);
 800f730:	68fb      	ldr	r3, [r7, #12]
 800f732:	681b      	ldr	r3, [r3, #0]
 800f734:	68b9      	ldr	r1, [r7, #8]
 800f736:	4618      	mov	r0, r3
 800f738:	f000 fb04 	bl	800fd44 <TIM_OC1_SetConfig>

      /* Set the Preload enable bit for channel1 */
      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
 800f73c:	68fb      	ldr	r3, [r7, #12]
 800f73e:	681b      	ldr	r3, [r3, #0]
 800f740:	699a      	ldr	r2, [r3, #24]
 800f742:	68fb      	ldr	r3, [r7, #12]
 800f744:	681b      	ldr	r3, [r3, #0]
 800f746:	f042 0208 	orr.w	r2, r2, #8
 800f74a:	619a      	str	r2, [r3, #24]

      /* Configure the Output Fast mode */
      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
 800f74c:	68fb      	ldr	r3, [r7, #12]
 800f74e:	681b      	ldr	r3, [r3, #0]
 800f750:	699a      	ldr	r2, [r3, #24]
 800f752:	68fb      	ldr	r3, [r7, #12]
 800f754:	681b      	ldr	r3, [r3, #0]
 800f756:	f022 0204 	bic.w	r2, r2, #4
 800f75a:	619a      	str	r2, [r3, #24]
      htim->Instance->CCMR1 |= sConfig->OCFastMode;
 800f75c:	68fb      	ldr	r3, [r7, #12]
 800f75e:	681b      	ldr	r3, [r3, #0]
 800f760:	6999      	ldr	r1, [r3, #24]
 800f762:	68bb      	ldr	r3, [r7, #8]
 800f764:	691a      	ldr	r2, [r3, #16]
 800f766:	68fb      	ldr	r3, [r7, #12]
 800f768:	681b      	ldr	r3, [r3, #0]
 800f76a:	430a      	orrs	r2, r1
 800f76c:	619a      	str	r2, [r3, #24]
      break;
 800f76e:	e0a5      	b.n	800f8bc <HAL_TIM_PWM_ConfigChannel+0x214>
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

      /* Configure the Channel 2 in PWM mode */
      TIM_OC2_SetConfig(htim->Instance, sConfig);
 800f770:	68fb      	ldr	r3, [r7, #12]
 800f772:	681b      	ldr	r3, [r3, #0]
 800f774:	68b9      	ldr	r1, [r7, #8]
 800f776:	4618      	mov	r0, r3
 800f778:	f000 fb74 	bl	800fe64 <TIM_OC2_SetConfig>

      /* Set the Preload enable bit for channel2 */
      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
 800f77c:	68fb      	ldr	r3, [r7, #12]
 800f77e:	681b      	ldr	r3, [r3, #0]
 800f780:	699a      	ldr	r2, [r3, #24]
 800f782:	68fb      	ldr	r3, [r7, #12]
 800f784:	681b      	ldr	r3, [r3, #0]
 800f786:	f442 6200 	orr.w	r2, r2, #2048	@ 0x800
 800f78a:	619a      	str	r2, [r3, #24]

      /* Configure the Output Fast mode */
      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
 800f78c:	68fb      	ldr	r3, [r7, #12]
 800f78e:	681b      	ldr	r3, [r3, #0]
 800f790:	699a      	ldr	r2, [r3, #24]
 800f792:	68fb      	ldr	r3, [r7, #12]
 800f794:	681b      	ldr	r3, [r3, #0]
 800f796:	f422 6280 	bic.w	r2, r2, #1024	@ 0x400
 800f79a:	619a      	str	r2, [r3, #24]
      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
 800f79c:	68fb      	ldr	r3, [r7, #12]
 800f79e:	681b      	ldr	r3, [r3, #0]
 800f7a0:	6999      	ldr	r1, [r3, #24]
 800f7a2:	68bb      	ldr	r3, [r7, #8]
 800f7a4:	691b      	ldr	r3, [r3, #16]
 800f7a6:	021a      	lsls	r2, r3, #8
 800f7a8:	68fb      	ldr	r3, [r7, #12]
 800f7aa:	681b      	ldr	r3, [r3, #0]
 800f7ac:	430a      	orrs	r2, r1
 800f7ae:	619a      	str	r2, [r3, #24]
      break;
 800f7b0:	e084      	b.n	800f8bc <HAL_TIM_PWM_ConfigChannel+0x214>
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));

      /* Configure the Channel 3 in PWM mode */
      TIM_OC3_SetConfig(htim->Instance, sConfig);
 800f7b2:	68fb      	ldr	r3, [r7, #12]
 800f7b4:	681b      	ldr	r3, [r3, #0]
 800f7b6:	68b9      	ldr	r1, [r7, #8]
 800f7b8:	4618      	mov	r0, r3
 800f7ba:	f000 fbdd 	bl	800ff78 <TIM_OC3_SetConfig>

      /* Set the Preload enable bit for channel3 */
      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
 800f7be:	68fb      	ldr	r3, [r7, #12]
 800f7c0:	681b      	ldr	r3, [r3, #0]
 800f7c2:	69da      	ldr	r2, [r3, #28]
 800f7c4:	68fb      	ldr	r3, [r7, #12]
 800f7c6:	681b      	ldr	r3, [r3, #0]
 800f7c8:	f042 0208 	orr.w	r2, r2, #8
 800f7cc:	61da      	str	r2, [r3, #28]

      /* Configure the Output Fast mode */
      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
 800f7ce:	68fb      	ldr	r3, [r7, #12]
 800f7d0:	681b      	ldr	r3, [r3, #0]
 800f7d2:	69da      	ldr	r2, [r3, #28]
 800f7d4:	68fb      	ldr	r3, [r7, #12]
 800f7d6:	681b      	ldr	r3, [r3, #0]
 800f7d8:	f022 0204 	bic.w	r2, r2, #4
 800f7dc:	61da      	str	r2, [r3, #28]
      htim->Instance->CCMR2 |= sConfig->OCFastMode;
 800f7de:	68fb      	ldr	r3, [r7, #12]
 800f7e0:	681b      	ldr	r3, [r3, #0]
 800f7e2:	69d9      	ldr	r1, [r3, #28]
 800f7e4:	68bb      	ldr	r3, [r7, #8]
 800f7e6:	691a      	ldr	r2, [r3, #16]
 800f7e8:	68fb      	ldr	r3, [r7, #12]
 800f7ea:	681b      	ldr	r3, [r3, #0]
 800f7ec:	430a      	orrs	r2, r1
 800f7ee:	61da      	str	r2, [r3, #28]
      break;
 800f7f0:	e064      	b.n	800f8bc <HAL_TIM_PWM_ConfigChannel+0x214>
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));

      /* Configure the Channel 4 in PWM mode */
      TIM_OC4_SetConfig(htim->Instance, sConfig);
 800f7f2:	68fb      	ldr	r3, [r7, #12]
 800f7f4:	681b      	ldr	r3, [r3, #0]
 800f7f6:	68b9      	ldr	r1, [r7, #8]
 800f7f8:	4618      	mov	r0, r3
 800f7fa:	f000 fc45 	bl	8010088 <TIM_OC4_SetConfig>

      /* Set the Preload enable bit for channel4 */
      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
 800f7fe:	68fb      	ldr	r3, [r7, #12]
 800f800:	681b      	ldr	r3, [r3, #0]
 800f802:	69da      	ldr	r2, [r3, #28]
 800f804:	68fb      	ldr	r3, [r7, #12]
 800f806:	681b      	ldr	r3, [r3, #0]
 800f808:	f442 6200 	orr.w	r2, r2, #2048	@ 0x800
 800f80c:	61da      	str	r2, [r3, #28]

      /* Configure the Output Fast mode */
      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
 800f80e:	68fb      	ldr	r3, [r7, #12]
 800f810:	681b      	ldr	r3, [r3, #0]
 800f812:	69da      	ldr	r2, [r3, #28]
 800f814:	68fb      	ldr	r3, [r7, #12]
 800f816:	681b      	ldr	r3, [r3, #0]
 800f818:	f422 6280 	bic.w	r2, r2, #1024	@ 0x400
 800f81c:	61da      	str	r2, [r3, #28]
      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
 800f81e:	68fb      	ldr	r3, [r7, #12]
 800f820:	681b      	ldr	r3, [r3, #0]
 800f822:	69d9      	ldr	r1, [r3, #28]
 800f824:	68bb      	ldr	r3, [r7, #8]
 800f826:	691b      	ldr	r3, [r3, #16]
 800f828:	021a      	lsls	r2, r3, #8
 800f82a:	68fb      	ldr	r3, [r7, #12]
 800f82c:	681b      	ldr	r3, [r3, #0]
 800f82e:	430a      	orrs	r2, r1
 800f830:	61da      	str	r2, [r3, #28]
      break;
 800f832:	e043      	b.n	800f8bc <HAL_TIM_PWM_ConfigChannel+0x214>
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));

      /* Configure the Channel 5 in PWM mode */
      TIM_OC5_SetConfig(htim->Instance, sConfig);
 800f834:	68fb      	ldr	r3, [r7, #12]
 800f836:	681b      	ldr	r3, [r3, #0]
 800f838:	68b9      	ldr	r1, [r7, #8]
 800f83a:	4618      	mov	r0, r3
 800f83c:	f000 fc8e 	bl	801015c <TIM_OC5_SetConfig>

      /* Set the Preload enable bit for channel5*/
      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
 800f840:	68fb      	ldr	r3, [r7, #12]
 800f842:	681b      	ldr	r3, [r3, #0]
 800f844:	6d5a      	ldr	r2, [r3, #84]	@ 0x54
 800f846:	68fb      	ldr	r3, [r7, #12]
 800f848:	681b      	ldr	r3, [r3, #0]
 800f84a:	f042 0208 	orr.w	r2, r2, #8
 800f84e:	655a      	str	r2, [r3, #84]	@ 0x54

      /* Configure the Output Fast mode */
      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
 800f850:	68fb      	ldr	r3, [r7, #12]
 800f852:	681b      	ldr	r3, [r3, #0]
 800f854:	6d5a      	ldr	r2, [r3, #84]	@ 0x54
 800f856:	68fb      	ldr	r3, [r7, #12]
 800f858:	681b      	ldr	r3, [r3, #0]
 800f85a:	f022 0204 	bic.w	r2, r2, #4
 800f85e:	655a      	str	r2, [r3, #84]	@ 0x54
      htim->Instance->CCMR3 |= sConfig->OCFastMode;
 800f860:	68fb      	ldr	r3, [r7, #12]
 800f862:	681b      	ldr	r3, [r3, #0]
 800f864:	6d59      	ldr	r1, [r3, #84]	@ 0x54
 800f866:	68bb      	ldr	r3, [r7, #8]
 800f868:	691a      	ldr	r2, [r3, #16]
 800f86a:	68fb      	ldr	r3, [r7, #12]
 800f86c:	681b      	ldr	r3, [r3, #0]
 800f86e:	430a      	orrs	r2, r1
 800f870:	655a      	str	r2, [r3, #84]	@ 0x54
      break;
 800f872:	e023      	b.n	800f8bc <HAL_TIM_PWM_ConfigChannel+0x214>
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));

      /* Configure the Channel 6 in PWM mode */
      TIM_OC6_SetConfig(htim->Instance, sConfig);
 800f874:	68fb      	ldr	r3, [r7, #12]
 800f876:	681b      	ldr	r3, [r3, #0]
 800f878:	68b9      	ldr	r1, [r7, #8]
 800f87a:	4618      	mov	r0, r3
 800f87c:	f000 fcd2 	bl	8010224 <TIM_OC6_SetConfig>

      /* Set the Preload enable bit for channel6 */
      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
 800f880:	68fb      	ldr	r3, [r7, #12]
 800f882:	681b      	ldr	r3, [r3, #0]
 800f884:	6d5a      	ldr	r2, [r3, #84]	@ 0x54
 800f886:	68fb      	ldr	r3, [r7, #12]
 800f888:	681b      	ldr	r3, [r3, #0]
 800f88a:	f442 6200 	orr.w	r2, r2, #2048	@ 0x800
 800f88e:	655a      	str	r2, [r3, #84]	@ 0x54

      /* Configure the Output Fast mode */
      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
 800f890:	68fb      	ldr	r3, [r7, #12]
 800f892:	681b      	ldr	r3, [r3, #0]
 800f894:	6d5a      	ldr	r2, [r3, #84]	@ 0x54
 800f896:	68fb      	ldr	r3, [r7, #12]
 800f898:	681b      	ldr	r3, [r3, #0]
 800f89a:	f422 6280 	bic.w	r2, r2, #1024	@ 0x400
 800f89e:	655a      	str	r2, [r3, #84]	@ 0x54
      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
 800f8a0:	68fb      	ldr	r3, [r7, #12]
 800f8a2:	681b      	ldr	r3, [r3, #0]
 800f8a4:	6d59      	ldr	r1, [r3, #84]	@ 0x54
 800f8a6:	68bb      	ldr	r3, [r7, #8]
 800f8a8:	691b      	ldr	r3, [r3, #16]
 800f8aa:	021a      	lsls	r2, r3, #8
 800f8ac:	68fb      	ldr	r3, [r7, #12]
 800f8ae:	681b      	ldr	r3, [r3, #0]
 800f8b0:	430a      	orrs	r2, r1
 800f8b2:	655a      	str	r2, [r3, #84]	@ 0x54
      break;
 800f8b4:	e002      	b.n	800f8bc <HAL_TIM_PWM_ConfigChannel+0x214>
    }

    default:
      status = HAL_ERROR;
 800f8b6:	2301      	movs	r3, #1
 800f8b8:	75fb      	strb	r3, [r7, #23]
      break;
 800f8ba:	bf00      	nop
  }

  __HAL_UNLOCK(htim);
 800f8bc:	68fb      	ldr	r3, [r7, #12]
 800f8be:	2200      	movs	r2, #0
 800f8c0:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  return status;
 800f8c4:	7dfb      	ldrb	r3, [r7, #23]
}
 800f8c6:	4618      	mov	r0, r3
 800f8c8:	3718      	adds	r7, #24
 800f8ca:	46bd      	mov	sp, r7
 800f8cc:	bd80      	pop	{r7, pc}
 800f8ce:	bf00      	nop

0800f8d0 <HAL_TIM_ConfigClockSource>:
  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
  *         contains the clock source information for the TIM peripheral.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
 800f8d0:	b580      	push	{r7, lr}
 800f8d2:	b084      	sub	sp, #16
 800f8d4:	af00      	add	r7, sp, #0
 800f8d6:	6078      	str	r0, [r7, #4]
 800f8d8:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef status = HAL_OK;
 800f8da:	2300      	movs	r3, #0
 800f8dc:	73fb      	strb	r3, [r7, #15]
  uint32_t tmpsmcr;

  /* Process Locked */
  __HAL_LOCK(htim);
 800f8de:	687b      	ldr	r3, [r7, #4]
 800f8e0:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
 800f8e4:	2b01      	cmp	r3, #1
 800f8e6:	d101      	bne.n	800f8ec <HAL_TIM_ConfigClockSource+0x1c>
 800f8e8:	2302      	movs	r3, #2
 800f8ea:	e0dc      	b.n	800faa6 <HAL_TIM_ConfigClockSource+0x1d6>
 800f8ec:	687b      	ldr	r3, [r7, #4]
 800f8ee:	2201      	movs	r2, #1
 800f8f0:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  htim->State = HAL_TIM_STATE_BUSY;
 800f8f4:	687b      	ldr	r3, [r7, #4]
 800f8f6:	2202      	movs	r2, #2
 800f8f8:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Check the parameters */
  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));

  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
  tmpsmcr = htim->Instance->SMCR;
 800f8fc:	687b      	ldr	r3, [r7, #4]
 800f8fe:	681b      	ldr	r3, [r3, #0]
 800f900:	689b      	ldr	r3, [r3, #8]
 800f902:	60bb      	str	r3, [r7, #8]
  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
 800f904:	68ba      	ldr	r2, [r7, #8]
 800f906:	4b6a      	ldr	r3, [pc, #424]	@ (800fab0 <HAL_TIM_ConfigClockSource+0x1e0>)
 800f908:	4013      	ands	r3, r2
 800f90a:	60bb      	str	r3, [r7, #8]
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 800f90c:	68bb      	ldr	r3, [r7, #8]
 800f90e:	f423 437f 	bic.w	r3, r3, #65280	@ 0xff00
 800f912:	60bb      	str	r3, [r7, #8]
  htim->Instance->SMCR = tmpsmcr;
 800f914:	687b      	ldr	r3, [r7, #4]
 800f916:	681b      	ldr	r3, [r3, #0]
 800f918:	68ba      	ldr	r2, [r7, #8]
 800f91a:	609a      	str	r2, [r3, #8]

  switch (sClockSourceConfig->ClockSource)
 800f91c:	683b      	ldr	r3, [r7, #0]
 800f91e:	681b      	ldr	r3, [r3, #0]
 800f920:	4a64      	ldr	r2, [pc, #400]	@ (800fab4 <HAL_TIM_ConfigClockSource+0x1e4>)
 800f922:	4293      	cmp	r3, r2
 800f924:	f000 80a9 	beq.w	800fa7a <HAL_TIM_ConfigClockSource+0x1aa>
 800f928:	4a62      	ldr	r2, [pc, #392]	@ (800fab4 <HAL_TIM_ConfigClockSource+0x1e4>)
 800f92a:	4293      	cmp	r3, r2
 800f92c:	f200 80ae 	bhi.w	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f930:	4a61      	ldr	r2, [pc, #388]	@ (800fab8 <HAL_TIM_ConfigClockSource+0x1e8>)
 800f932:	4293      	cmp	r3, r2
 800f934:	f000 80a1 	beq.w	800fa7a <HAL_TIM_ConfigClockSource+0x1aa>
 800f938:	4a5f      	ldr	r2, [pc, #380]	@ (800fab8 <HAL_TIM_ConfigClockSource+0x1e8>)
 800f93a:	4293      	cmp	r3, r2
 800f93c:	f200 80a6 	bhi.w	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f940:	4a5e      	ldr	r2, [pc, #376]	@ (800fabc <HAL_TIM_ConfigClockSource+0x1ec>)
 800f942:	4293      	cmp	r3, r2
 800f944:	f000 8099 	beq.w	800fa7a <HAL_TIM_ConfigClockSource+0x1aa>
 800f948:	4a5c      	ldr	r2, [pc, #368]	@ (800fabc <HAL_TIM_ConfigClockSource+0x1ec>)
 800f94a:	4293      	cmp	r3, r2
 800f94c:	f200 809e 	bhi.w	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f950:	f1b3 1f10 	cmp.w	r3, #1048592	@ 0x100010
 800f954:	f000 8091 	beq.w	800fa7a <HAL_TIM_ConfigClockSource+0x1aa>
 800f958:	f1b3 1f10 	cmp.w	r3, #1048592	@ 0x100010
 800f95c:	f200 8096 	bhi.w	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f960:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 800f964:	f000 8089 	beq.w	800fa7a <HAL_TIM_ConfigClockSource+0x1aa>
 800f968:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 800f96c:	f200 808e 	bhi.w	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f970:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800f974:	d03e      	beq.n	800f9f4 <HAL_TIM_ConfigClockSource+0x124>
 800f976:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
 800f97a:	f200 8087 	bhi.w	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f97e:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800f982:	f000 8086 	beq.w	800fa92 <HAL_TIM_ConfigClockSource+0x1c2>
 800f986:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 800f98a:	d87f      	bhi.n	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f98c:	2b70      	cmp	r3, #112	@ 0x70
 800f98e:	d01a      	beq.n	800f9c6 <HAL_TIM_ConfigClockSource+0xf6>
 800f990:	2b70      	cmp	r3, #112	@ 0x70
 800f992:	d87b      	bhi.n	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f994:	2b60      	cmp	r3, #96	@ 0x60
 800f996:	d050      	beq.n	800fa3a <HAL_TIM_ConfigClockSource+0x16a>
 800f998:	2b60      	cmp	r3, #96	@ 0x60
 800f99a:	d877      	bhi.n	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f99c:	2b50      	cmp	r3, #80	@ 0x50
 800f99e:	d03c      	beq.n	800fa1a <HAL_TIM_ConfigClockSource+0x14a>
 800f9a0:	2b50      	cmp	r3, #80	@ 0x50
 800f9a2:	d873      	bhi.n	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f9a4:	2b40      	cmp	r3, #64	@ 0x40
 800f9a6:	d058      	beq.n	800fa5a <HAL_TIM_ConfigClockSource+0x18a>
 800f9a8:	2b40      	cmp	r3, #64	@ 0x40
 800f9aa:	d86f      	bhi.n	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f9ac:	2b30      	cmp	r3, #48	@ 0x30
 800f9ae:	d064      	beq.n	800fa7a <HAL_TIM_ConfigClockSource+0x1aa>
 800f9b0:	2b30      	cmp	r3, #48	@ 0x30
 800f9b2:	d86b      	bhi.n	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f9b4:	2b20      	cmp	r3, #32
 800f9b6:	d060      	beq.n	800fa7a <HAL_TIM_ConfigClockSource+0x1aa>
 800f9b8:	2b20      	cmp	r3, #32
 800f9ba:	d867      	bhi.n	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
 800f9bc:	2b00      	cmp	r3, #0
 800f9be:	d05c      	beq.n	800fa7a <HAL_TIM_ConfigClockSource+0x1aa>
 800f9c0:	2b10      	cmp	r3, #16
 800f9c2:	d05a      	beq.n	800fa7a <HAL_TIM_ConfigClockSource+0x1aa>
 800f9c4:	e062      	b.n	800fa8c <HAL_TIM_ConfigClockSource+0x1bc>
      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      /* Configure the ETR Clock source */
      TIM_ETR_SetConfig(htim->Instance,
 800f9c6:	687b      	ldr	r3, [r7, #4]
 800f9c8:	6818      	ldr	r0, [r3, #0]
                        sClockSourceConfig->ClockPrescaler,
 800f9ca:	683b      	ldr	r3, [r7, #0]
 800f9cc:	6899      	ldr	r1, [r3, #8]
                        sClockSourceConfig->ClockPolarity,
 800f9ce:	683b      	ldr	r3, [r7, #0]
 800f9d0:	685a      	ldr	r2, [r3, #4]
                        sClockSourceConfig->ClockFilter);
 800f9d2:	683b      	ldr	r3, [r7, #0]
 800f9d4:	68db      	ldr	r3, [r3, #12]
      TIM_ETR_SetConfig(htim->Instance,
 800f9d6:	f000 fe33 	bl	8010640 <TIM_ETR_SetConfig>

      /* Select the External clock mode1 and the ETRF trigger */
      tmpsmcr = htim->Instance->SMCR;
 800f9da:	687b      	ldr	r3, [r7, #4]
 800f9dc:	681b      	ldr	r3, [r3, #0]
 800f9de:	689b      	ldr	r3, [r3, #8]
 800f9e0:	60bb      	str	r3, [r7, #8]
      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
 800f9e2:	68bb      	ldr	r3, [r7, #8]
 800f9e4:	f043 0377 	orr.w	r3, r3, #119	@ 0x77
 800f9e8:	60bb      	str	r3, [r7, #8]
      /* Write to TIMx SMCR */
      htim->Instance->SMCR = tmpsmcr;
 800f9ea:	687b      	ldr	r3, [r7, #4]
 800f9ec:	681b      	ldr	r3, [r3, #0]
 800f9ee:	68ba      	ldr	r2, [r7, #8]
 800f9f0:	609a      	str	r2, [r3, #8]
      break;
 800f9f2:	e04f      	b.n	800fa94 <HAL_TIM_ConfigClockSource+0x1c4>
      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      /* Configure the ETR Clock source */
      TIM_ETR_SetConfig(htim->Instance,
 800f9f4:	687b      	ldr	r3, [r7, #4]
 800f9f6:	6818      	ldr	r0, [r3, #0]
                        sClockSourceConfig->ClockPrescaler,
 800f9f8:	683b      	ldr	r3, [r7, #0]
 800f9fa:	6899      	ldr	r1, [r3, #8]
                        sClockSourceConfig->ClockPolarity,
 800f9fc:	683b      	ldr	r3, [r7, #0]
 800f9fe:	685a      	ldr	r2, [r3, #4]
                        sClockSourceConfig->ClockFilter);
 800fa00:	683b      	ldr	r3, [r7, #0]
 800fa02:	68db      	ldr	r3, [r3, #12]
      TIM_ETR_SetConfig(htim->Instance,
 800fa04:	f000 fe1c 	bl	8010640 <TIM_ETR_SetConfig>
      /* Enable the External clock mode2 */
      htim->Instance->SMCR |= TIM_SMCR_ECE;
 800fa08:	687b      	ldr	r3, [r7, #4]
 800fa0a:	681b      	ldr	r3, [r3, #0]
 800fa0c:	689a      	ldr	r2, [r3, #8]
 800fa0e:	687b      	ldr	r3, [r7, #4]
 800fa10:	681b      	ldr	r3, [r3, #0]
 800fa12:	f442 4280 	orr.w	r2, r2, #16384	@ 0x4000
 800fa16:	609a      	str	r2, [r3, #8]
      break;
 800fa18:	e03c      	b.n	800fa94 <HAL_TIM_ConfigClockSource+0x1c4>

      /* Check TI1 input conditioning related parameters */
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      TIM_TI1_ConfigInputStage(htim->Instance,
 800fa1a:	687b      	ldr	r3, [r7, #4]
 800fa1c:	6818      	ldr	r0, [r3, #0]
                               sClockSourceConfig->ClockPolarity,
 800fa1e:	683b      	ldr	r3, [r7, #0]
 800fa20:	6859      	ldr	r1, [r3, #4]
                               sClockSourceConfig->ClockFilter);
 800fa22:	683b      	ldr	r3, [r7, #0]
 800fa24:	68db      	ldr	r3, [r3, #12]
      TIM_TI1_ConfigInputStage(htim->Instance,
 800fa26:	461a      	mov	r2, r3
 800fa28:	f000 fcd6 	bl	80103d8 <TIM_TI1_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
 800fa2c:	687b      	ldr	r3, [r7, #4]
 800fa2e:	681b      	ldr	r3, [r3, #0]
 800fa30:	2150      	movs	r1, #80	@ 0x50
 800fa32:	4618      	mov	r0, r3
 800fa34:	f000 fde6 	bl	8010604 <TIM_ITRx_SetConfig>
      break;
 800fa38:	e02c      	b.n	800fa94 <HAL_TIM_ConfigClockSource+0x1c4>

      /* Check TI2 input conditioning related parameters */
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      TIM_TI2_ConfigInputStage(htim->Instance,
 800fa3a:	687b      	ldr	r3, [r7, #4]
 800fa3c:	6818      	ldr	r0, [r3, #0]
                               sClockSourceConfig->ClockPolarity,
 800fa3e:	683b      	ldr	r3, [r7, #0]
 800fa40:	6859      	ldr	r1, [r3, #4]
                               sClockSourceConfig->ClockFilter);
 800fa42:	683b      	ldr	r3, [r7, #0]
 800fa44:	68db      	ldr	r3, [r3, #12]
      TIM_TI2_ConfigInputStage(htim->Instance,
 800fa46:	461a      	mov	r2, r3
 800fa48:	f000 fd32 	bl	80104b0 <TIM_TI2_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
 800fa4c:	687b      	ldr	r3, [r7, #4]
 800fa4e:	681b      	ldr	r3, [r3, #0]
 800fa50:	2160      	movs	r1, #96	@ 0x60
 800fa52:	4618      	mov	r0, r3
 800fa54:	f000 fdd6 	bl	8010604 <TIM_ITRx_SetConfig>
      break;
 800fa58:	e01c      	b.n	800fa94 <HAL_TIM_ConfigClockSource+0x1c4>

      /* Check TI1 input conditioning related parameters */
      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

      TIM_TI1_ConfigInputStage(htim->Instance,
 800fa5a:	687b      	ldr	r3, [r7, #4]
 800fa5c:	6818      	ldr	r0, [r3, #0]
                               sClockSourceConfig->ClockPolarity,
 800fa5e:	683b      	ldr	r3, [r7, #0]
 800fa60:	6859      	ldr	r1, [r3, #4]
                               sClockSourceConfig->ClockFilter);
 800fa62:	683b      	ldr	r3, [r7, #0]
 800fa64:	68db      	ldr	r3, [r3, #12]
      TIM_TI1_ConfigInputStage(htim->Instance,
 800fa66:	461a      	mov	r2, r3
 800fa68:	f000 fcb6 	bl	80103d8 <TIM_TI1_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
 800fa6c:	687b      	ldr	r3, [r7, #4]
 800fa6e:	681b      	ldr	r3, [r3, #0]
 800fa70:	2140      	movs	r1, #64	@ 0x40
 800fa72:	4618      	mov	r0, r3
 800fa74:	f000 fdc6 	bl	8010604 <TIM_ITRx_SetConfig>
      break;
 800fa78:	e00c      	b.n	800fa94 <HAL_TIM_ConfigClockSource+0x1c4>
    case TIM_CLOCKSOURCE_ITR8:
    {
      /* Check whether or not the timer instance supports internal trigger input */
      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));

      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
 800fa7a:	687b      	ldr	r3, [r7, #4]
 800fa7c:	681a      	ldr	r2, [r3, #0]
 800fa7e:	683b      	ldr	r3, [r7, #0]
 800fa80:	681b      	ldr	r3, [r3, #0]
 800fa82:	4619      	mov	r1, r3
 800fa84:	4610      	mov	r0, r2
 800fa86:	f000 fdbd 	bl	8010604 <TIM_ITRx_SetConfig>
      break;
 800fa8a:	e003      	b.n	800fa94 <HAL_TIM_ConfigClockSource+0x1c4>
    }

    default:
      status = HAL_ERROR;
 800fa8c:	2301      	movs	r3, #1
 800fa8e:	73fb      	strb	r3, [r7, #15]
      break;
 800fa90:	e000      	b.n	800fa94 <HAL_TIM_ConfigClockSource+0x1c4>
      break;
 800fa92:	bf00      	nop
  }
  htim->State = HAL_TIM_STATE_READY;
 800fa94:	687b      	ldr	r3, [r7, #4]
 800fa96:	2201      	movs	r2, #1
 800fa98:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  __HAL_UNLOCK(htim);
 800fa9c:	687b      	ldr	r3, [r7, #4]
 800fa9e:	2200      	movs	r2, #0
 800faa0:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  return status;
 800faa4:	7bfb      	ldrb	r3, [r7, #15]
}
 800faa6:	4618      	mov	r0, r3
 800faa8:	3710      	adds	r7, #16
 800faaa:	46bd      	mov	sp, r7
 800faac:	bd80      	pop	{r7, pc}
 800faae:	bf00      	nop
 800fab0:	ffceff88 	.word	0xffceff88
 800fab4:	00100040 	.word	0x00100040
 800fab8:	00100030 	.word	0x00100030
 800fabc:	00100020 	.word	0x00100020

0800fac0 <HAL_TIM_ReadCapturedValue>:
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  * @retval Captured value
  */
uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
{
 800fac0:	b480      	push	{r7}
 800fac2:	b085      	sub	sp, #20
 800fac4:	af00      	add	r7, sp, #0
 800fac6:	6078      	str	r0, [r7, #4]
 800fac8:	6039      	str	r1, [r7, #0]
  uint32_t tmpreg = 0U;
 800faca:	2300      	movs	r3, #0
 800facc:	60fb      	str	r3, [r7, #12]

  switch (Channel)
 800face:	683b      	ldr	r3, [r7, #0]
 800fad0:	2b0c      	cmp	r3, #12
 800fad2:	d831      	bhi.n	800fb38 <HAL_TIM_ReadCapturedValue+0x78>
 800fad4:	a201      	add	r2, pc, #4	@ (adr r2, 800fadc <HAL_TIM_ReadCapturedValue+0x1c>)
 800fad6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800fada:	bf00      	nop
 800fadc:	0800fb11 	.word	0x0800fb11
 800fae0:	0800fb39 	.word	0x0800fb39
 800fae4:	0800fb39 	.word	0x0800fb39
 800fae8:	0800fb39 	.word	0x0800fb39
 800faec:	0800fb1b 	.word	0x0800fb1b
 800faf0:	0800fb39 	.word	0x0800fb39
 800faf4:	0800fb39 	.word	0x0800fb39
 800faf8:	0800fb39 	.word	0x0800fb39
 800fafc:	0800fb25 	.word	0x0800fb25
 800fb00:	0800fb39 	.word	0x0800fb39
 800fb04:	0800fb39 	.word	0x0800fb39
 800fb08:	0800fb39 	.word	0x0800fb39
 800fb0c:	0800fb2f 	.word	0x0800fb2f
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));

      /* Return the capture 1 value */
      tmpreg =  htim->Instance->CCR1;
 800fb10:	687b      	ldr	r3, [r7, #4]
 800fb12:	681b      	ldr	r3, [r3, #0]
 800fb14:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 800fb16:	60fb      	str	r3, [r7, #12]

      break;
 800fb18:	e00f      	b.n	800fb3a <HAL_TIM_ReadCapturedValue+0x7a>
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

      /* Return the capture 2 value */
      tmpreg =   htim->Instance->CCR2;
 800fb1a:	687b      	ldr	r3, [r7, #4]
 800fb1c:	681b      	ldr	r3, [r3, #0]
 800fb1e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 800fb20:	60fb      	str	r3, [r7, #12]

      break;
 800fb22:	e00a      	b.n	800fb3a <HAL_TIM_ReadCapturedValue+0x7a>
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));

      /* Return the capture 3 value */
      tmpreg =   htim->Instance->CCR3;
 800fb24:	687b      	ldr	r3, [r7, #4]
 800fb26:	681b      	ldr	r3, [r3, #0]
 800fb28:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 800fb2a:	60fb      	str	r3, [r7, #12]

      break;
 800fb2c:	e005      	b.n	800fb3a <HAL_TIM_ReadCapturedValue+0x7a>
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));

      /* Return the capture 4 value */
      tmpreg =   htim->Instance->CCR4;
 800fb2e:	687b      	ldr	r3, [r7, #4]
 800fb30:	681b      	ldr	r3, [r3, #0]
 800fb32:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800fb34:	60fb      	str	r3, [r7, #12]

      break;
 800fb36:	e000      	b.n	800fb3a <HAL_TIM_ReadCapturedValue+0x7a>
    }

    default:
      break;
 800fb38:	bf00      	nop
  }

  return tmpreg;
 800fb3a:	68fb      	ldr	r3, [r7, #12]
}
 800fb3c:	4618      	mov	r0, r3
 800fb3e:	3714      	adds	r7, #20
 800fb40:	46bd      	mov	sp, r7
 800fb42:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fb46:	4770      	bx	lr

0800fb48 <HAL_TIM_OC_DelayElapsedCallback>:
  * @brief  Output Compare callback in non-blocking mode
  * @param  htim TIM OC handle
  * @retval None
  */
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
 800fb48:	b480      	push	{r7}
 800fb4a:	b083      	sub	sp, #12
 800fb4c:	af00      	add	r7, sp, #0
 800fb4e:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
   */
}
 800fb50:	bf00      	nop
 800fb52:	370c      	adds	r7, #12
 800fb54:	46bd      	mov	sp, r7
 800fb56:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fb5a:	4770      	bx	lr

0800fb5c <HAL_TIM_PWM_PulseFinishedCallback>:
  * @brief  PWM Pulse finished callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
 800fb5c:	b480      	push	{r7}
 800fb5e:	b083      	sub	sp, #12
 800fb60:	af00      	add	r7, sp, #0
 800fb62:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
   */
}
 800fb64:	bf00      	nop
 800fb66:	370c      	adds	r7, #12
 800fb68:	46bd      	mov	sp, r7
 800fb6a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fb6e:	4770      	bx	lr

0800fb70 <HAL_TIM_TriggerCallback>:
  * @brief  Hall Trigger detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
 800fb70:	b480      	push	{r7}
 800fb72:	b083      	sub	sp, #12
 800fb74:	af00      	add	r7, sp, #0
 800fb76:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_TriggerCallback could be implemented in the user file
   */
}
 800fb78:	bf00      	nop
 800fb7a:	370c      	adds	r7, #12
 800fb7c:	46bd      	mov	sp, r7
 800fb7e:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fb82:	4770      	bx	lr

0800fb84 <HAL_TIM_GetChannelState>:
  *            @arg TIM_CHANNEL_5: TIM Channel 5
  *            @arg TIM_CHANNEL_6: TIM Channel 6
  * @retval TIM Channel state
  */
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel)
{
 800fb84:	b480      	push	{r7}
 800fb86:	b085      	sub	sp, #20
 800fb88:	af00      	add	r7, sp, #0
 800fb8a:	6078      	str	r0, [r7, #4]
 800fb8c:	6039      	str	r1, [r7, #0]
  HAL_TIM_ChannelStateTypeDef channel_state;

  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
 800fb8e:	683b      	ldr	r3, [r7, #0]
 800fb90:	2b00      	cmp	r3, #0
 800fb92:	d104      	bne.n	800fb9e <HAL_TIM_GetChannelState+0x1a>
 800fb94:	687b      	ldr	r3, [r7, #4]
 800fb96:	f893 303e 	ldrb.w	r3, [r3, #62]	@ 0x3e
 800fb9a:	b2db      	uxtb	r3, r3
 800fb9c:	e023      	b.n	800fbe6 <HAL_TIM_GetChannelState+0x62>
 800fb9e:	683b      	ldr	r3, [r7, #0]
 800fba0:	2b04      	cmp	r3, #4
 800fba2:	d104      	bne.n	800fbae <HAL_TIM_GetChannelState+0x2a>
 800fba4:	687b      	ldr	r3, [r7, #4]
 800fba6:	f893 303f 	ldrb.w	r3, [r3, #63]	@ 0x3f
 800fbaa:	b2db      	uxtb	r3, r3
 800fbac:	e01b      	b.n	800fbe6 <HAL_TIM_GetChannelState+0x62>
 800fbae:	683b      	ldr	r3, [r7, #0]
 800fbb0:	2b08      	cmp	r3, #8
 800fbb2:	d104      	bne.n	800fbbe <HAL_TIM_GetChannelState+0x3a>
 800fbb4:	687b      	ldr	r3, [r7, #4]
 800fbb6:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
 800fbba:	b2db      	uxtb	r3, r3
 800fbbc:	e013      	b.n	800fbe6 <HAL_TIM_GetChannelState+0x62>
 800fbbe:	683b      	ldr	r3, [r7, #0]
 800fbc0:	2b0c      	cmp	r3, #12
 800fbc2:	d104      	bne.n	800fbce <HAL_TIM_GetChannelState+0x4a>
 800fbc4:	687b      	ldr	r3, [r7, #4]
 800fbc6:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 800fbca:	b2db      	uxtb	r3, r3
 800fbcc:	e00b      	b.n	800fbe6 <HAL_TIM_GetChannelState+0x62>
 800fbce:	683b      	ldr	r3, [r7, #0]
 800fbd0:	2b10      	cmp	r3, #16
 800fbd2:	d104      	bne.n	800fbde <HAL_TIM_GetChannelState+0x5a>
 800fbd4:	687b      	ldr	r3, [r7, #4]
 800fbd6:	f893 3042 	ldrb.w	r3, [r3, #66]	@ 0x42
 800fbda:	b2db      	uxtb	r3, r3
 800fbdc:	e003      	b.n	800fbe6 <HAL_TIM_GetChannelState+0x62>
 800fbde:	687b      	ldr	r3, [r7, #4]
 800fbe0:	f893 3043 	ldrb.w	r3, [r3, #67]	@ 0x43
 800fbe4:	b2db      	uxtb	r3, r3
 800fbe6:	73fb      	strb	r3, [r7, #15]

  return channel_state;
 800fbe8:	7bfb      	ldrb	r3, [r7, #15]
}
 800fbea:	4618      	mov	r0, r3
 800fbec:	3714      	adds	r7, #20
 800fbee:	46bd      	mov	sp, r7
 800fbf0:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fbf4:	4770      	bx	lr
	...

0800fbf8 <TIM_Base_SetConfig>:
  * @param  TIMx TIM peripheral
  * @param  Structure TIM Base configuration structure
  * @retval None
  */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
 800fbf8:	b480      	push	{r7}
 800fbfa:	b085      	sub	sp, #20
 800fbfc:	af00      	add	r7, sp, #0
 800fbfe:	6078      	str	r0, [r7, #4]
 800fc00:	6039      	str	r1, [r7, #0]
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;
 800fc02:	687b      	ldr	r3, [r7, #4]
 800fc04:	681b      	ldr	r3, [r3, #0]
 800fc06:	60fb      	str	r3, [r7, #12]

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 800fc08:	687b      	ldr	r3, [r7, #4]
 800fc0a:	4a46      	ldr	r2, [pc, #280]	@ (800fd24 <TIM_Base_SetConfig+0x12c>)
 800fc0c:	4293      	cmp	r3, r2
 800fc0e:	d013      	beq.n	800fc38 <TIM_Base_SetConfig+0x40>
 800fc10:	687b      	ldr	r3, [r7, #4]
 800fc12:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800fc16:	d00f      	beq.n	800fc38 <TIM_Base_SetConfig+0x40>
 800fc18:	687b      	ldr	r3, [r7, #4]
 800fc1a:	4a43      	ldr	r2, [pc, #268]	@ (800fd28 <TIM_Base_SetConfig+0x130>)
 800fc1c:	4293      	cmp	r3, r2
 800fc1e:	d00b      	beq.n	800fc38 <TIM_Base_SetConfig+0x40>
 800fc20:	687b      	ldr	r3, [r7, #4]
 800fc22:	4a42      	ldr	r2, [pc, #264]	@ (800fd2c <TIM_Base_SetConfig+0x134>)
 800fc24:	4293      	cmp	r3, r2
 800fc26:	d007      	beq.n	800fc38 <TIM_Base_SetConfig+0x40>
 800fc28:	687b      	ldr	r3, [r7, #4]
 800fc2a:	4a41      	ldr	r2, [pc, #260]	@ (800fd30 <TIM_Base_SetConfig+0x138>)
 800fc2c:	4293      	cmp	r3, r2
 800fc2e:	d003      	beq.n	800fc38 <TIM_Base_SetConfig+0x40>
 800fc30:	687b      	ldr	r3, [r7, #4]
 800fc32:	4a40      	ldr	r2, [pc, #256]	@ (800fd34 <TIM_Base_SetConfig+0x13c>)
 800fc34:	4293      	cmp	r3, r2
 800fc36:	d108      	bne.n	800fc4a <TIM_Base_SetConfig+0x52>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 800fc38:	68fb      	ldr	r3, [r7, #12]
 800fc3a:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
 800fc3e:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= Structure->CounterMode;
 800fc40:	683b      	ldr	r3, [r7, #0]
 800fc42:	685b      	ldr	r3, [r3, #4]
 800fc44:	68fa      	ldr	r2, [r7, #12]
 800fc46:	4313      	orrs	r3, r2
 800fc48:	60fb      	str	r3, [r7, #12]
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 800fc4a:	687b      	ldr	r3, [r7, #4]
 800fc4c:	4a35      	ldr	r2, [pc, #212]	@ (800fd24 <TIM_Base_SetConfig+0x12c>)
 800fc4e:	4293      	cmp	r3, r2
 800fc50:	d01f      	beq.n	800fc92 <TIM_Base_SetConfig+0x9a>
 800fc52:	687b      	ldr	r3, [r7, #4]
 800fc54:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 800fc58:	d01b      	beq.n	800fc92 <TIM_Base_SetConfig+0x9a>
 800fc5a:	687b      	ldr	r3, [r7, #4]
 800fc5c:	4a32      	ldr	r2, [pc, #200]	@ (800fd28 <TIM_Base_SetConfig+0x130>)
 800fc5e:	4293      	cmp	r3, r2
 800fc60:	d017      	beq.n	800fc92 <TIM_Base_SetConfig+0x9a>
 800fc62:	687b      	ldr	r3, [r7, #4]
 800fc64:	4a31      	ldr	r2, [pc, #196]	@ (800fd2c <TIM_Base_SetConfig+0x134>)
 800fc66:	4293      	cmp	r3, r2
 800fc68:	d013      	beq.n	800fc92 <TIM_Base_SetConfig+0x9a>
 800fc6a:	687b      	ldr	r3, [r7, #4]
 800fc6c:	4a30      	ldr	r2, [pc, #192]	@ (800fd30 <TIM_Base_SetConfig+0x138>)
 800fc6e:	4293      	cmp	r3, r2
 800fc70:	d00f      	beq.n	800fc92 <TIM_Base_SetConfig+0x9a>
 800fc72:	687b      	ldr	r3, [r7, #4]
 800fc74:	4a2f      	ldr	r2, [pc, #188]	@ (800fd34 <TIM_Base_SetConfig+0x13c>)
 800fc76:	4293      	cmp	r3, r2
 800fc78:	d00b      	beq.n	800fc92 <TIM_Base_SetConfig+0x9a>
 800fc7a:	687b      	ldr	r3, [r7, #4]
 800fc7c:	4a2e      	ldr	r2, [pc, #184]	@ (800fd38 <TIM_Base_SetConfig+0x140>)
 800fc7e:	4293      	cmp	r3, r2
 800fc80:	d007      	beq.n	800fc92 <TIM_Base_SetConfig+0x9a>
 800fc82:	687b      	ldr	r3, [r7, #4]
 800fc84:	4a2d      	ldr	r2, [pc, #180]	@ (800fd3c <TIM_Base_SetConfig+0x144>)
 800fc86:	4293      	cmp	r3, r2
 800fc88:	d003      	beq.n	800fc92 <TIM_Base_SetConfig+0x9a>
 800fc8a:	687b      	ldr	r3, [r7, #4]
 800fc8c:	4a2c      	ldr	r2, [pc, #176]	@ (800fd40 <TIM_Base_SetConfig+0x148>)
 800fc8e:	4293      	cmp	r3, r2
 800fc90:	d108      	bne.n	800fca4 <TIM_Base_SetConfig+0xac>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
 800fc92:	68fb      	ldr	r3, [r7, #12]
 800fc94:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 800fc98:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 800fc9a:	683b      	ldr	r3, [r7, #0]
 800fc9c:	68db      	ldr	r3, [r3, #12]
 800fc9e:	68fa      	ldr	r2, [r7, #12]
 800fca0:	4313      	orrs	r3, r2
 800fca2:	60fb      	str	r3, [r7, #12]
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 800fca4:	68fb      	ldr	r3, [r7, #12]
 800fca6:	f023 0280 	bic.w	r2, r3, #128	@ 0x80
 800fcaa:	683b      	ldr	r3, [r7, #0]
 800fcac:	695b      	ldr	r3, [r3, #20]
 800fcae:	4313      	orrs	r3, r2
 800fcb0:	60fb      	str	r3, [r7, #12]

  TIMx->CR1 = tmpcr1;
 800fcb2:	687b      	ldr	r3, [r7, #4]
 800fcb4:	68fa      	ldr	r2, [r7, #12]
 800fcb6:	601a      	str	r2, [r3, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 800fcb8:	683b      	ldr	r3, [r7, #0]
 800fcba:	689a      	ldr	r2, [r3, #8]
 800fcbc:	687b      	ldr	r3, [r7, #4]
 800fcbe:	62da      	str	r2, [r3, #44]	@ 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 800fcc0:	683b      	ldr	r3, [r7, #0]
 800fcc2:	681a      	ldr	r2, [r3, #0]
 800fcc4:	687b      	ldr	r3, [r7, #4]
 800fcc6:	629a      	str	r2, [r3, #40]	@ 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 800fcc8:	687b      	ldr	r3, [r7, #4]
 800fcca:	4a16      	ldr	r2, [pc, #88]	@ (800fd24 <TIM_Base_SetConfig+0x12c>)
 800fccc:	4293      	cmp	r3, r2
 800fcce:	d00f      	beq.n	800fcf0 <TIM_Base_SetConfig+0xf8>
 800fcd0:	687b      	ldr	r3, [r7, #4]
 800fcd2:	4a18      	ldr	r2, [pc, #96]	@ (800fd34 <TIM_Base_SetConfig+0x13c>)
 800fcd4:	4293      	cmp	r3, r2
 800fcd6:	d00b      	beq.n	800fcf0 <TIM_Base_SetConfig+0xf8>
 800fcd8:	687b      	ldr	r3, [r7, #4]
 800fcda:	4a17      	ldr	r2, [pc, #92]	@ (800fd38 <TIM_Base_SetConfig+0x140>)
 800fcdc:	4293      	cmp	r3, r2
 800fcde:	d007      	beq.n	800fcf0 <TIM_Base_SetConfig+0xf8>
 800fce0:	687b      	ldr	r3, [r7, #4]
 800fce2:	4a16      	ldr	r2, [pc, #88]	@ (800fd3c <TIM_Base_SetConfig+0x144>)
 800fce4:	4293      	cmp	r3, r2
 800fce6:	d003      	beq.n	800fcf0 <TIM_Base_SetConfig+0xf8>
 800fce8:	687b      	ldr	r3, [r7, #4]
 800fcea:	4a15      	ldr	r2, [pc, #84]	@ (800fd40 <TIM_Base_SetConfig+0x148>)
 800fcec:	4293      	cmp	r3, r2
 800fcee:	d103      	bne.n	800fcf8 <TIM_Base_SetConfig+0x100>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 800fcf0:	683b      	ldr	r3, [r7, #0]
 800fcf2:	691a      	ldr	r2, [r3, #16]
 800fcf4:	687b      	ldr	r3, [r7, #4]
 800fcf6:	631a      	str	r2, [r3, #48]	@ 0x30
  }

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 800fcf8:	687b      	ldr	r3, [r7, #4]
 800fcfa:	2201      	movs	r2, #1
 800fcfc:	615a      	str	r2, [r3, #20]

  /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
  if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
 800fcfe:	687b      	ldr	r3, [r7, #4]
 800fd00:	691b      	ldr	r3, [r3, #16]
 800fd02:	f003 0301 	and.w	r3, r3, #1
 800fd06:	2b01      	cmp	r3, #1
 800fd08:	d105      	bne.n	800fd16 <TIM_Base_SetConfig+0x11e>
  {
    /* Clear the update flag */
    CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
 800fd0a:	687b      	ldr	r3, [r7, #4]
 800fd0c:	691b      	ldr	r3, [r3, #16]
 800fd0e:	f023 0201 	bic.w	r2, r3, #1
 800fd12:	687b      	ldr	r3, [r7, #4]
 800fd14:	611a      	str	r2, [r3, #16]
  }
}
 800fd16:	bf00      	nop
 800fd18:	3714      	adds	r7, #20
 800fd1a:	46bd      	mov	sp, r7
 800fd1c:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fd20:	4770      	bx	lr
 800fd22:	bf00      	nop
 800fd24:	40010000 	.word	0x40010000
 800fd28:	40000400 	.word	0x40000400
 800fd2c:	40000800 	.word	0x40000800
 800fd30:	40000c00 	.word	0x40000c00
 800fd34:	40010400 	.word	0x40010400
 800fd38:	40014000 	.word	0x40014000
 800fd3c:	40014400 	.word	0x40014400
 800fd40:	40014800 	.word	0x40014800

0800fd44 <TIM_OC1_SetConfig>:
  * @param  TIMx to select the TIM peripheral
  * @param  OC_Config The output configuration structure
  * @retval None
  */
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
 800fd44:	b480      	push	{r7}
 800fd46:	b087      	sub	sp, #28
 800fd48:	af00      	add	r7, sp, #0
 800fd4a:	6078      	str	r0, [r7, #4]
 800fd4c:	6039      	str	r1, [r7, #0]
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 800fd4e:	687b      	ldr	r3, [r7, #4]
 800fd50:	6a1b      	ldr	r3, [r3, #32]
 800fd52:	617b      	str	r3, [r7, #20]

  /* Disable the Channel 1: Reset the CC1E Bit */
  TIMx->CCER &= ~TIM_CCER_CC1E;
 800fd54:	687b      	ldr	r3, [r7, #4]
 800fd56:	6a1b      	ldr	r3, [r3, #32]
 800fd58:	f023 0201 	bic.w	r2, r3, #1
 800fd5c:	687b      	ldr	r3, [r7, #4]
 800fd5e:	621a      	str	r2, [r3, #32]

  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 800fd60:	687b      	ldr	r3, [r7, #4]
 800fd62:	685b      	ldr	r3, [r3, #4]
 800fd64:	613b      	str	r3, [r7, #16]

  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR1;
 800fd66:	687b      	ldr	r3, [r7, #4]
 800fd68:	699b      	ldr	r3, [r3, #24]
 800fd6a:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Compare Mode Bits */
  tmpccmrx &= ~TIM_CCMR1_OC1M;
 800fd6c:	68fa      	ldr	r2, [r7, #12]
 800fd6e:	4b37      	ldr	r3, [pc, #220]	@ (800fe4c <TIM_OC1_SetConfig+0x108>)
 800fd70:	4013      	ands	r3, r2
 800fd72:	60fb      	str	r3, [r7, #12]
  tmpccmrx &= ~TIM_CCMR1_CC1S;
 800fd74:	68fb      	ldr	r3, [r7, #12]
 800fd76:	f023 0303 	bic.w	r3, r3, #3
 800fd7a:	60fb      	str	r3, [r7, #12]
  /* Select the Output Compare Mode */
  tmpccmrx |= OC_Config->OCMode;
 800fd7c:	683b      	ldr	r3, [r7, #0]
 800fd7e:	681b      	ldr	r3, [r3, #0]
 800fd80:	68fa      	ldr	r2, [r7, #12]
 800fd82:	4313      	orrs	r3, r2
 800fd84:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC1P;
 800fd86:	697b      	ldr	r3, [r7, #20]
 800fd88:	f023 0302 	bic.w	r3, r3, #2
 800fd8c:	617b      	str	r3, [r7, #20]
  /* Set the Output Compare Polarity */
  tmpccer |= OC_Config->OCPolarity;
 800fd8e:	683b      	ldr	r3, [r7, #0]
 800fd90:	689b      	ldr	r3, [r3, #8]
 800fd92:	697a      	ldr	r2, [r7, #20]
 800fd94:	4313      	orrs	r3, r2
 800fd96:	617b      	str	r3, [r7, #20]

  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
 800fd98:	687b      	ldr	r3, [r7, #4]
 800fd9a:	4a2d      	ldr	r2, [pc, #180]	@ (800fe50 <TIM_OC1_SetConfig+0x10c>)
 800fd9c:	4293      	cmp	r3, r2
 800fd9e:	d00f      	beq.n	800fdc0 <TIM_OC1_SetConfig+0x7c>
 800fda0:	687b      	ldr	r3, [r7, #4]
 800fda2:	4a2c      	ldr	r2, [pc, #176]	@ (800fe54 <TIM_OC1_SetConfig+0x110>)
 800fda4:	4293      	cmp	r3, r2
 800fda6:	d00b      	beq.n	800fdc0 <TIM_OC1_SetConfig+0x7c>
 800fda8:	687b      	ldr	r3, [r7, #4]
 800fdaa:	4a2b      	ldr	r2, [pc, #172]	@ (800fe58 <TIM_OC1_SetConfig+0x114>)
 800fdac:	4293      	cmp	r3, r2
 800fdae:	d007      	beq.n	800fdc0 <TIM_OC1_SetConfig+0x7c>
 800fdb0:	687b      	ldr	r3, [r7, #4]
 800fdb2:	4a2a      	ldr	r2, [pc, #168]	@ (800fe5c <TIM_OC1_SetConfig+0x118>)
 800fdb4:	4293      	cmp	r3, r2
 800fdb6:	d003      	beq.n	800fdc0 <TIM_OC1_SetConfig+0x7c>
 800fdb8:	687b      	ldr	r3, [r7, #4]
 800fdba:	4a29      	ldr	r2, [pc, #164]	@ (800fe60 <TIM_OC1_SetConfig+0x11c>)
 800fdbc:	4293      	cmp	r3, r2
 800fdbe:	d10c      	bne.n	800fdda <TIM_OC1_SetConfig+0x96>
  {
    /* Check parameters */
    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));

    /* Reset the Output N Polarity level */
    tmpccer &= ~TIM_CCER_CC1NP;
 800fdc0:	697b      	ldr	r3, [r7, #20]
 800fdc2:	f023 0308 	bic.w	r3, r3, #8
 800fdc6:	617b      	str	r3, [r7, #20]
    /* Set the Output N Polarity */
    tmpccer |= OC_Config->OCNPolarity;
 800fdc8:	683b      	ldr	r3, [r7, #0]
 800fdca:	68db      	ldr	r3, [r3, #12]
 800fdcc:	697a      	ldr	r2, [r7, #20]
 800fdce:	4313      	orrs	r3, r2
 800fdd0:	617b      	str	r3, [r7, #20]
    /* Reset the Output N State */
    tmpccer &= ~TIM_CCER_CC1NE;
 800fdd2:	697b      	ldr	r3, [r7, #20]
 800fdd4:	f023 0304 	bic.w	r3, r3, #4
 800fdd8:	617b      	str	r3, [r7, #20]
  }

  if (IS_TIM_BREAK_INSTANCE(TIMx))
 800fdda:	687b      	ldr	r3, [r7, #4]
 800fddc:	4a1c      	ldr	r2, [pc, #112]	@ (800fe50 <TIM_OC1_SetConfig+0x10c>)
 800fdde:	4293      	cmp	r3, r2
 800fde0:	d00f      	beq.n	800fe02 <TIM_OC1_SetConfig+0xbe>
 800fde2:	687b      	ldr	r3, [r7, #4]
 800fde4:	4a1b      	ldr	r2, [pc, #108]	@ (800fe54 <TIM_OC1_SetConfig+0x110>)
 800fde6:	4293      	cmp	r3, r2
 800fde8:	d00b      	beq.n	800fe02 <TIM_OC1_SetConfig+0xbe>
 800fdea:	687b      	ldr	r3, [r7, #4]
 800fdec:	4a1a      	ldr	r2, [pc, #104]	@ (800fe58 <TIM_OC1_SetConfig+0x114>)
 800fdee:	4293      	cmp	r3, r2
 800fdf0:	d007      	beq.n	800fe02 <TIM_OC1_SetConfig+0xbe>
 800fdf2:	687b      	ldr	r3, [r7, #4]
 800fdf4:	4a19      	ldr	r2, [pc, #100]	@ (800fe5c <TIM_OC1_SetConfig+0x118>)
 800fdf6:	4293      	cmp	r3, r2
 800fdf8:	d003      	beq.n	800fe02 <TIM_OC1_SetConfig+0xbe>
 800fdfa:	687b      	ldr	r3, [r7, #4]
 800fdfc:	4a18      	ldr	r2, [pc, #96]	@ (800fe60 <TIM_OC1_SetConfig+0x11c>)
 800fdfe:	4293      	cmp	r3, r2
 800fe00:	d111      	bne.n	800fe26 <TIM_OC1_SetConfig+0xe2>
    /* Check parameters */
    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare and Output Compare N IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS1;
 800fe02:	693b      	ldr	r3, [r7, #16]
 800fe04:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 800fe08:	613b      	str	r3, [r7, #16]
    tmpcr2 &= ~TIM_CR2_OIS1N;
 800fe0a:	693b      	ldr	r3, [r7, #16]
 800fe0c:	f423 7300 	bic.w	r3, r3, #512	@ 0x200
 800fe10:	613b      	str	r3, [r7, #16]
    /* Set the Output Idle state */
    tmpcr2 |= OC_Config->OCIdleState;
 800fe12:	683b      	ldr	r3, [r7, #0]
 800fe14:	695b      	ldr	r3, [r3, #20]
 800fe16:	693a      	ldr	r2, [r7, #16]
 800fe18:	4313      	orrs	r3, r2
 800fe1a:	613b      	str	r3, [r7, #16]
    /* Set the Output N Idle state */
    tmpcr2 |= OC_Config->OCNIdleState;
 800fe1c:	683b      	ldr	r3, [r7, #0]
 800fe1e:	699b      	ldr	r3, [r3, #24]
 800fe20:	693a      	ldr	r2, [r7, #16]
 800fe22:	4313      	orrs	r3, r2
 800fe24:	613b      	str	r3, [r7, #16]
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 800fe26:	687b      	ldr	r3, [r7, #4]
 800fe28:	693a      	ldr	r2, [r7, #16]
 800fe2a:	605a      	str	r2, [r3, #4]

  /* Write to TIMx CCMR1 */
  TIMx->CCMR1 = tmpccmrx;
 800fe2c:	687b      	ldr	r3, [r7, #4]
 800fe2e:	68fa      	ldr	r2, [r7, #12]
 800fe30:	619a      	str	r2, [r3, #24]

  /* Set the Capture Compare Register value */
  TIMx->CCR1 = OC_Config->Pulse;
 800fe32:	683b      	ldr	r3, [r7, #0]
 800fe34:	685a      	ldr	r2, [r3, #4]
 800fe36:	687b      	ldr	r3, [r7, #4]
 800fe38:	635a      	str	r2, [r3, #52]	@ 0x34

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 800fe3a:	687b      	ldr	r3, [r7, #4]
 800fe3c:	697a      	ldr	r2, [r7, #20]
 800fe3e:	621a      	str	r2, [r3, #32]
}
 800fe40:	bf00      	nop
 800fe42:	371c      	adds	r7, #28
 800fe44:	46bd      	mov	sp, r7
 800fe46:	f85d 7b04 	ldr.w	r7, [sp], #4
 800fe4a:	4770      	bx	lr
 800fe4c:	fffeff8f 	.word	0xfffeff8f
 800fe50:	40010000 	.word	0x40010000
 800fe54:	40010400 	.word	0x40010400
 800fe58:	40014000 	.word	0x40014000
 800fe5c:	40014400 	.word	0x40014400
 800fe60:	40014800 	.word	0x40014800

0800fe64 <TIM_OC2_SetConfig>:
  * @param  TIMx to select the TIM peripheral
  * @param  OC_Config The output configuration structure
  * @retval None
  */
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
 800fe64:	b480      	push	{r7}
 800fe66:	b087      	sub	sp, #28
 800fe68:	af00      	add	r7, sp, #0
 800fe6a:	6078      	str	r0, [r7, #4]
 800fe6c:	6039      	str	r1, [r7, #0]
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 800fe6e:	687b      	ldr	r3, [r7, #4]
 800fe70:	6a1b      	ldr	r3, [r3, #32]
 800fe72:	617b      	str	r3, [r7, #20]

  /* Disable the Channel 2: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC2E;
 800fe74:	687b      	ldr	r3, [r7, #4]
 800fe76:	6a1b      	ldr	r3, [r3, #32]
 800fe78:	f023 0210 	bic.w	r2, r3, #16
 800fe7c:	687b      	ldr	r3, [r7, #4]
 800fe7e:	621a      	str	r2, [r3, #32]

  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 800fe80:	687b      	ldr	r3, [r7, #4]
 800fe82:	685b      	ldr	r3, [r3, #4]
 800fe84:	613b      	str	r3, [r7, #16]

  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR1;
 800fe86:	687b      	ldr	r3, [r7, #4]
 800fe88:	699b      	ldr	r3, [r3, #24]
 800fe8a:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR1_OC2M;
 800fe8c:	68fa      	ldr	r2, [r7, #12]
 800fe8e:	4b34      	ldr	r3, [pc, #208]	@ (800ff60 <TIM_OC2_SetConfig+0xfc>)
 800fe90:	4013      	ands	r3, r2
 800fe92:	60fb      	str	r3, [r7, #12]
  tmpccmrx &= ~TIM_CCMR1_CC2S;
 800fe94:	68fb      	ldr	r3, [r7, #12]
 800fe96:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 800fe9a:	60fb      	str	r3, [r7, #12]

  /* Select the Output Compare Mode */
  tmpccmrx |= (OC_Config->OCMode << 8U);
 800fe9c:	683b      	ldr	r3, [r7, #0]
 800fe9e:	681b      	ldr	r3, [r3, #0]
 800fea0:	021b      	lsls	r3, r3, #8
 800fea2:	68fa      	ldr	r2, [r7, #12]
 800fea4:	4313      	orrs	r3, r2
 800fea6:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC2P;
 800fea8:	697b      	ldr	r3, [r7, #20]
 800feaa:	f023 0320 	bic.w	r3, r3, #32
 800feae:	617b      	str	r3, [r7, #20]
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 4U);
 800feb0:	683b      	ldr	r3, [r7, #0]
 800feb2:	689b      	ldr	r3, [r3, #8]
 800feb4:	011b      	lsls	r3, r3, #4
 800feb6:	697a      	ldr	r2, [r7, #20]
 800feb8:	4313      	orrs	r3, r2
 800feba:	617b      	str	r3, [r7, #20]

  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
 800febc:	687b      	ldr	r3, [r7, #4]
 800febe:	4a29      	ldr	r2, [pc, #164]	@ (800ff64 <TIM_OC2_SetConfig+0x100>)
 800fec0:	4293      	cmp	r3, r2
 800fec2:	d003      	beq.n	800fecc <TIM_OC2_SetConfig+0x68>
 800fec4:	687b      	ldr	r3, [r7, #4]
 800fec6:	4a28      	ldr	r2, [pc, #160]	@ (800ff68 <TIM_OC2_SetConfig+0x104>)
 800fec8:	4293      	cmp	r3, r2
 800feca:	d10d      	bne.n	800fee8 <TIM_OC2_SetConfig+0x84>
  {
    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));

    /* Reset the Output N Polarity level */
    tmpccer &= ~TIM_CCER_CC2NP;
 800fecc:	697b      	ldr	r3, [r7, #20]
 800fece:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 800fed2:	617b      	str	r3, [r7, #20]
    /* Set the Output N Polarity */
    tmpccer |= (OC_Config->OCNPolarity << 4U);
 800fed4:	683b      	ldr	r3, [r7, #0]
 800fed6:	68db      	ldr	r3, [r3, #12]
 800fed8:	011b      	lsls	r3, r3, #4
 800feda:	697a      	ldr	r2, [r7, #20]
 800fedc:	4313      	orrs	r3, r2
 800fede:	617b      	str	r3, [r7, #20]
    /* Reset the Output N State */
    tmpccer &= ~TIM_CCER_CC2NE;
 800fee0:	697b      	ldr	r3, [r7, #20]
 800fee2:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
 800fee6:	617b      	str	r3, [r7, #20]
  }

  if (IS_TIM_BREAK_INSTANCE(TIMx))
 800fee8:	687b      	ldr	r3, [r7, #4]
 800feea:	4a1e      	ldr	r2, [pc, #120]	@ (800ff64 <TIM_OC2_SetConfig+0x100>)
 800feec:	4293      	cmp	r3, r2
 800feee:	d00f      	beq.n	800ff10 <TIM_OC2_SetConfig+0xac>
 800fef0:	687b      	ldr	r3, [r7, #4]
 800fef2:	4a1d      	ldr	r2, [pc, #116]	@ (800ff68 <TIM_OC2_SetConfig+0x104>)
 800fef4:	4293      	cmp	r3, r2
 800fef6:	d00b      	beq.n	800ff10 <TIM_OC2_SetConfig+0xac>
 800fef8:	687b      	ldr	r3, [r7, #4]
 800fefa:	4a1c      	ldr	r2, [pc, #112]	@ (800ff6c <TIM_OC2_SetConfig+0x108>)
 800fefc:	4293      	cmp	r3, r2
 800fefe:	d007      	beq.n	800ff10 <TIM_OC2_SetConfig+0xac>
 800ff00:	687b      	ldr	r3, [r7, #4]
 800ff02:	4a1b      	ldr	r2, [pc, #108]	@ (800ff70 <TIM_OC2_SetConfig+0x10c>)
 800ff04:	4293      	cmp	r3, r2
 800ff06:	d003      	beq.n	800ff10 <TIM_OC2_SetConfig+0xac>
 800ff08:	687b      	ldr	r3, [r7, #4]
 800ff0a:	4a1a      	ldr	r2, [pc, #104]	@ (800ff74 <TIM_OC2_SetConfig+0x110>)
 800ff0c:	4293      	cmp	r3, r2
 800ff0e:	d113      	bne.n	800ff38 <TIM_OC2_SetConfig+0xd4>
    /* Check parameters */
    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare and Output Compare N IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS2;
 800ff10:	693b      	ldr	r3, [r7, #16]
 800ff12:	f423 6380 	bic.w	r3, r3, #1024	@ 0x400
 800ff16:	613b      	str	r3, [r7, #16]
    tmpcr2 &= ~TIM_CR2_OIS2N;
 800ff18:	693b      	ldr	r3, [r7, #16]
 800ff1a:	f423 6300 	bic.w	r3, r3, #2048	@ 0x800
 800ff1e:	613b      	str	r3, [r7, #16]
    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 2U);
 800ff20:	683b      	ldr	r3, [r7, #0]
 800ff22:	695b      	ldr	r3, [r3, #20]
 800ff24:	009b      	lsls	r3, r3, #2
 800ff26:	693a      	ldr	r2, [r7, #16]
 800ff28:	4313      	orrs	r3, r2
 800ff2a:	613b      	str	r3, [r7, #16]
    /* Set the Output N Idle state */
    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
 800ff2c:	683b      	ldr	r3, [r7, #0]
 800ff2e:	699b      	ldr	r3, [r3, #24]
 800ff30:	009b      	lsls	r3, r3, #2
 800ff32:	693a      	ldr	r2, [r7, #16]
 800ff34:	4313      	orrs	r3, r2
 800ff36:	613b      	str	r3, [r7, #16]
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 800ff38:	687b      	ldr	r3, [r7, #4]
 800ff3a:	693a      	ldr	r2, [r7, #16]
 800ff3c:	605a      	str	r2, [r3, #4]

  /* Write to TIMx CCMR1 */
  TIMx->CCMR1 = tmpccmrx;
 800ff3e:	687b      	ldr	r3, [r7, #4]
 800ff40:	68fa      	ldr	r2, [r7, #12]
 800ff42:	619a      	str	r2, [r3, #24]

  /* Set the Capture Compare Register value */
  TIMx->CCR2 = OC_Config->Pulse;
 800ff44:	683b      	ldr	r3, [r7, #0]
 800ff46:	685a      	ldr	r2, [r3, #4]
 800ff48:	687b      	ldr	r3, [r7, #4]
 800ff4a:	639a      	str	r2, [r3, #56]	@ 0x38

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 800ff4c:	687b      	ldr	r3, [r7, #4]
 800ff4e:	697a      	ldr	r2, [r7, #20]
 800ff50:	621a      	str	r2, [r3, #32]
}
 800ff52:	bf00      	nop
 800ff54:	371c      	adds	r7, #28
 800ff56:	46bd      	mov	sp, r7
 800ff58:	f85d 7b04 	ldr.w	r7, [sp], #4
 800ff5c:	4770      	bx	lr
 800ff5e:	bf00      	nop
 800ff60:	feff8fff 	.word	0xfeff8fff
 800ff64:	40010000 	.word	0x40010000
 800ff68:	40010400 	.word	0x40010400
 800ff6c:	40014000 	.word	0x40014000
 800ff70:	40014400 	.word	0x40014400
 800ff74:	40014800 	.word	0x40014800

0800ff78 <TIM_OC3_SetConfig>:
  * @param  TIMx to select the TIM peripheral
  * @param  OC_Config The output configuration structure
  * @retval None
  */
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
 800ff78:	b480      	push	{r7}
 800ff7a:	b087      	sub	sp, #28
 800ff7c:	af00      	add	r7, sp, #0
 800ff7e:	6078      	str	r0, [r7, #4]
 800ff80:	6039      	str	r1, [r7, #0]
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 800ff82:	687b      	ldr	r3, [r7, #4]
 800ff84:	6a1b      	ldr	r3, [r3, #32]
 800ff86:	617b      	str	r3, [r7, #20]

  /* Disable the Channel 3: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC3E;
 800ff88:	687b      	ldr	r3, [r7, #4]
 800ff8a:	6a1b      	ldr	r3, [r3, #32]
 800ff8c:	f423 7280 	bic.w	r2, r3, #256	@ 0x100
 800ff90:	687b      	ldr	r3, [r7, #4]
 800ff92:	621a      	str	r2, [r3, #32]

  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 800ff94:	687b      	ldr	r3, [r7, #4]
 800ff96:	685b      	ldr	r3, [r3, #4]
 800ff98:	613b      	str	r3, [r7, #16]

  /* Get the TIMx CCMR2 register value */
  tmpccmrx = TIMx->CCMR2;
 800ff9a:	687b      	ldr	r3, [r7, #4]
 800ff9c:	69db      	ldr	r3, [r3, #28]
 800ff9e:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR2_OC3M;
 800ffa0:	68fa      	ldr	r2, [r7, #12]
 800ffa2:	4b33      	ldr	r3, [pc, #204]	@ (8010070 <TIM_OC3_SetConfig+0xf8>)
 800ffa4:	4013      	ands	r3, r2
 800ffa6:	60fb      	str	r3, [r7, #12]
  tmpccmrx &= ~TIM_CCMR2_CC3S;
 800ffa8:	68fb      	ldr	r3, [r7, #12]
 800ffaa:	f023 0303 	bic.w	r3, r3, #3
 800ffae:	60fb      	str	r3, [r7, #12]
  /* Select the Output Compare Mode */
  tmpccmrx |= OC_Config->OCMode;
 800ffb0:	683b      	ldr	r3, [r7, #0]
 800ffb2:	681b      	ldr	r3, [r3, #0]
 800ffb4:	68fa      	ldr	r2, [r7, #12]
 800ffb6:	4313      	orrs	r3, r2
 800ffb8:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC3P;
 800ffba:	697b      	ldr	r3, [r7, #20]
 800ffbc:	f423 7300 	bic.w	r3, r3, #512	@ 0x200
 800ffc0:	617b      	str	r3, [r7, #20]
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 8U);
 800ffc2:	683b      	ldr	r3, [r7, #0]
 800ffc4:	689b      	ldr	r3, [r3, #8]
 800ffc6:	021b      	lsls	r3, r3, #8
 800ffc8:	697a      	ldr	r2, [r7, #20]
 800ffca:	4313      	orrs	r3, r2
 800ffcc:	617b      	str	r3, [r7, #20]

  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
 800ffce:	687b      	ldr	r3, [r7, #4]
 800ffd0:	4a28      	ldr	r2, [pc, #160]	@ (8010074 <TIM_OC3_SetConfig+0xfc>)
 800ffd2:	4293      	cmp	r3, r2
 800ffd4:	d003      	beq.n	800ffde <TIM_OC3_SetConfig+0x66>
 800ffd6:	687b      	ldr	r3, [r7, #4]
 800ffd8:	4a27      	ldr	r2, [pc, #156]	@ (8010078 <TIM_OC3_SetConfig+0x100>)
 800ffda:	4293      	cmp	r3, r2
 800ffdc:	d10d      	bne.n	800fffa <TIM_OC3_SetConfig+0x82>
  {
    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));

    /* Reset the Output N Polarity level */
    tmpccer &= ~TIM_CCER_CC3NP;
 800ffde:	697b      	ldr	r3, [r7, #20]
 800ffe0:	f423 6300 	bic.w	r3, r3, #2048	@ 0x800
 800ffe4:	617b      	str	r3, [r7, #20]
    /* Set the Output N Polarity */
    tmpccer |= (OC_Config->OCNPolarity << 8U);
 800ffe6:	683b      	ldr	r3, [r7, #0]
 800ffe8:	68db      	ldr	r3, [r3, #12]
 800ffea:	021b      	lsls	r3, r3, #8
 800ffec:	697a      	ldr	r2, [r7, #20]
 800ffee:	4313      	orrs	r3, r2
 800fff0:	617b      	str	r3, [r7, #20]
    /* Reset the Output N State */
    tmpccer &= ~TIM_CCER_CC3NE;
 800fff2:	697b      	ldr	r3, [r7, #20]
 800fff4:	f423 6380 	bic.w	r3, r3, #1024	@ 0x400
 800fff8:	617b      	str	r3, [r7, #20]
  }

  if (IS_TIM_BREAK_INSTANCE(TIMx))
 800fffa:	687b      	ldr	r3, [r7, #4]
 800fffc:	4a1d      	ldr	r2, [pc, #116]	@ (8010074 <TIM_OC3_SetConfig+0xfc>)
 800fffe:	4293      	cmp	r3, r2
 8010000:	d00f      	beq.n	8010022 <TIM_OC3_SetConfig+0xaa>
 8010002:	687b      	ldr	r3, [r7, #4]
 8010004:	4a1c      	ldr	r2, [pc, #112]	@ (8010078 <TIM_OC3_SetConfig+0x100>)
 8010006:	4293      	cmp	r3, r2
 8010008:	d00b      	beq.n	8010022 <TIM_OC3_SetConfig+0xaa>
 801000a:	687b      	ldr	r3, [r7, #4]
 801000c:	4a1b      	ldr	r2, [pc, #108]	@ (801007c <TIM_OC3_SetConfig+0x104>)
 801000e:	4293      	cmp	r3, r2
 8010010:	d007      	beq.n	8010022 <TIM_OC3_SetConfig+0xaa>
 8010012:	687b      	ldr	r3, [r7, #4]
 8010014:	4a1a      	ldr	r2, [pc, #104]	@ (8010080 <TIM_OC3_SetConfig+0x108>)
 8010016:	4293      	cmp	r3, r2
 8010018:	d003      	beq.n	8010022 <TIM_OC3_SetConfig+0xaa>
 801001a:	687b      	ldr	r3, [r7, #4]
 801001c:	4a19      	ldr	r2, [pc, #100]	@ (8010084 <TIM_OC3_SetConfig+0x10c>)
 801001e:	4293      	cmp	r3, r2
 8010020:	d113      	bne.n	801004a <TIM_OC3_SetConfig+0xd2>
    /* Check parameters */
    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare and Output Compare N IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS3;
 8010022:	693b      	ldr	r3, [r7, #16]
 8010024:	f423 5380 	bic.w	r3, r3, #4096	@ 0x1000
 8010028:	613b      	str	r3, [r7, #16]
    tmpcr2 &= ~TIM_CR2_OIS3N;
 801002a:	693b      	ldr	r3, [r7, #16]
 801002c:	f423 5300 	bic.w	r3, r3, #8192	@ 0x2000
 8010030:	613b      	str	r3, [r7, #16]
    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 4U);
 8010032:	683b      	ldr	r3, [r7, #0]
 8010034:	695b      	ldr	r3, [r3, #20]
 8010036:	011b      	lsls	r3, r3, #4
 8010038:	693a      	ldr	r2, [r7, #16]
 801003a:	4313      	orrs	r3, r2
 801003c:	613b      	str	r3, [r7, #16]
    /* Set the Output N Idle state */
    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
 801003e:	683b      	ldr	r3, [r7, #0]
 8010040:	699b      	ldr	r3, [r3, #24]
 8010042:	011b      	lsls	r3, r3, #4
 8010044:	693a      	ldr	r2, [r7, #16]
 8010046:	4313      	orrs	r3, r2
 8010048:	613b      	str	r3, [r7, #16]
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 801004a:	687b      	ldr	r3, [r7, #4]
 801004c:	693a      	ldr	r2, [r7, #16]
 801004e:	605a      	str	r2, [r3, #4]

  /* Write to TIMx CCMR2 */
  TIMx->CCMR2 = tmpccmrx;
 8010050:	687b      	ldr	r3, [r7, #4]
 8010052:	68fa      	ldr	r2, [r7, #12]
 8010054:	61da      	str	r2, [r3, #28]

  /* Set the Capture Compare Register value */
  TIMx->CCR3 = OC_Config->Pulse;
 8010056:	683b      	ldr	r3, [r7, #0]
 8010058:	685a      	ldr	r2, [r3, #4]
 801005a:	687b      	ldr	r3, [r7, #4]
 801005c:	63da      	str	r2, [r3, #60]	@ 0x3c

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 801005e:	687b      	ldr	r3, [r7, #4]
 8010060:	697a      	ldr	r2, [r7, #20]
 8010062:	621a      	str	r2, [r3, #32]
}
 8010064:	bf00      	nop
 8010066:	371c      	adds	r7, #28
 8010068:	46bd      	mov	sp, r7
 801006a:	f85d 7b04 	ldr.w	r7, [sp], #4
 801006e:	4770      	bx	lr
 8010070:	fffeff8f 	.word	0xfffeff8f
 8010074:	40010000 	.word	0x40010000
 8010078:	40010400 	.word	0x40010400
 801007c:	40014000 	.word	0x40014000
 8010080:	40014400 	.word	0x40014400
 8010084:	40014800 	.word	0x40014800

08010088 <TIM_OC4_SetConfig>:
  * @param  TIMx to select the TIM peripheral
  * @param  OC_Config The output configuration structure
  * @retval None
  */
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
 8010088:	b480      	push	{r7}
 801008a:	b087      	sub	sp, #28
 801008c:	af00      	add	r7, sp, #0
 801008e:	6078      	str	r0, [r7, #4]
 8010090:	6039      	str	r1, [r7, #0]
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 8010092:	687b      	ldr	r3, [r7, #4]
 8010094:	6a1b      	ldr	r3, [r3, #32]
 8010096:	613b      	str	r3, [r7, #16]

  /* Disable the Channel 4: Reset the CC4E Bit */
  TIMx->CCER &= ~TIM_CCER_CC4E;
 8010098:	687b      	ldr	r3, [r7, #4]
 801009a:	6a1b      	ldr	r3, [r3, #32]
 801009c:	f423 5280 	bic.w	r2, r3, #4096	@ 0x1000
 80100a0:	687b      	ldr	r3, [r7, #4]
 80100a2:	621a      	str	r2, [r3, #32]

  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 80100a4:	687b      	ldr	r3, [r7, #4]
 80100a6:	685b      	ldr	r3, [r3, #4]
 80100a8:	617b      	str	r3, [r7, #20]

  /* Get the TIMx CCMR2 register value */
  tmpccmrx = TIMx->CCMR2;
 80100aa:	687b      	ldr	r3, [r7, #4]
 80100ac:	69db      	ldr	r3, [r3, #28]
 80100ae:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR2_OC4M;
 80100b0:	68fa      	ldr	r2, [r7, #12]
 80100b2:	4b24      	ldr	r3, [pc, #144]	@ (8010144 <TIM_OC4_SetConfig+0xbc>)
 80100b4:	4013      	ands	r3, r2
 80100b6:	60fb      	str	r3, [r7, #12]
  tmpccmrx &= ~TIM_CCMR2_CC4S;
 80100b8:	68fb      	ldr	r3, [r7, #12]
 80100ba:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 80100be:	60fb      	str	r3, [r7, #12]

  /* Select the Output Compare Mode */
  tmpccmrx |= (OC_Config->OCMode << 8U);
 80100c0:	683b      	ldr	r3, [r7, #0]
 80100c2:	681b      	ldr	r3, [r3, #0]
 80100c4:	021b      	lsls	r3, r3, #8
 80100c6:	68fa      	ldr	r2, [r7, #12]
 80100c8:	4313      	orrs	r3, r2
 80100ca:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC4P;
 80100cc:	693b      	ldr	r3, [r7, #16]
 80100ce:	f423 5300 	bic.w	r3, r3, #8192	@ 0x2000
 80100d2:	613b      	str	r3, [r7, #16]
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 12U);
 80100d4:	683b      	ldr	r3, [r7, #0]
 80100d6:	689b      	ldr	r3, [r3, #8]
 80100d8:	031b      	lsls	r3, r3, #12
 80100da:	693a      	ldr	r2, [r7, #16]
 80100dc:	4313      	orrs	r3, r2
 80100de:	613b      	str	r3, [r7, #16]

  if (IS_TIM_BREAK_INSTANCE(TIMx))
 80100e0:	687b      	ldr	r3, [r7, #4]
 80100e2:	4a19      	ldr	r2, [pc, #100]	@ (8010148 <TIM_OC4_SetConfig+0xc0>)
 80100e4:	4293      	cmp	r3, r2
 80100e6:	d00f      	beq.n	8010108 <TIM_OC4_SetConfig+0x80>
 80100e8:	687b      	ldr	r3, [r7, #4]
 80100ea:	4a18      	ldr	r2, [pc, #96]	@ (801014c <TIM_OC4_SetConfig+0xc4>)
 80100ec:	4293      	cmp	r3, r2
 80100ee:	d00b      	beq.n	8010108 <TIM_OC4_SetConfig+0x80>
 80100f0:	687b      	ldr	r3, [r7, #4]
 80100f2:	4a17      	ldr	r2, [pc, #92]	@ (8010150 <TIM_OC4_SetConfig+0xc8>)
 80100f4:	4293      	cmp	r3, r2
 80100f6:	d007      	beq.n	8010108 <TIM_OC4_SetConfig+0x80>
 80100f8:	687b      	ldr	r3, [r7, #4]
 80100fa:	4a16      	ldr	r2, [pc, #88]	@ (8010154 <TIM_OC4_SetConfig+0xcc>)
 80100fc:	4293      	cmp	r3, r2
 80100fe:	d003      	beq.n	8010108 <TIM_OC4_SetConfig+0x80>
 8010100:	687b      	ldr	r3, [r7, #4]
 8010102:	4a15      	ldr	r2, [pc, #84]	@ (8010158 <TIM_OC4_SetConfig+0xd0>)
 8010104:	4293      	cmp	r3, r2
 8010106:	d109      	bne.n	801011c <TIM_OC4_SetConfig+0x94>
  {
    /* Check parameters */
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS4;
 8010108:	697b      	ldr	r3, [r7, #20]
 801010a:	f423 4380 	bic.w	r3, r3, #16384	@ 0x4000
 801010e:	617b      	str	r3, [r7, #20]

    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 6U);
 8010110:	683b      	ldr	r3, [r7, #0]
 8010112:	695b      	ldr	r3, [r3, #20]
 8010114:	019b      	lsls	r3, r3, #6
 8010116:	697a      	ldr	r2, [r7, #20]
 8010118:	4313      	orrs	r3, r2
 801011a:	617b      	str	r3, [r7, #20]
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 801011c:	687b      	ldr	r3, [r7, #4]
 801011e:	697a      	ldr	r2, [r7, #20]
 8010120:	605a      	str	r2, [r3, #4]

  /* Write to TIMx CCMR2 */
  TIMx->CCMR2 = tmpccmrx;
 8010122:	687b      	ldr	r3, [r7, #4]
 8010124:	68fa      	ldr	r2, [r7, #12]
 8010126:	61da      	str	r2, [r3, #28]

  /* Set the Capture Compare Register value */
  TIMx->CCR4 = OC_Config->Pulse;
 8010128:	683b      	ldr	r3, [r7, #0]
 801012a:	685a      	ldr	r2, [r3, #4]
 801012c:	687b      	ldr	r3, [r7, #4]
 801012e:	641a      	str	r2, [r3, #64]	@ 0x40

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 8010130:	687b      	ldr	r3, [r7, #4]
 8010132:	693a      	ldr	r2, [r7, #16]
 8010134:	621a      	str	r2, [r3, #32]
}
 8010136:	bf00      	nop
 8010138:	371c      	adds	r7, #28
 801013a:	46bd      	mov	sp, r7
 801013c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8010140:	4770      	bx	lr
 8010142:	bf00      	nop
 8010144:	feff8fff 	.word	0xfeff8fff
 8010148:	40010000 	.word	0x40010000
 801014c:	40010400 	.word	0x40010400
 8010150:	40014000 	.word	0x40014000
 8010154:	40014400 	.word	0x40014400
 8010158:	40014800 	.word	0x40014800

0801015c <TIM_OC5_SetConfig>:
  * @param  OC_Config The output configuration structure
  * @retval None
  */
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
                              const TIM_OC_InitTypeDef *OC_Config)
{
 801015c:	b480      	push	{r7}
 801015e:	b087      	sub	sp, #28
 8010160:	af00      	add	r7, sp, #0
 8010162:	6078      	str	r0, [r7, #4]
 8010164:	6039      	str	r1, [r7, #0]
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 8010166:	687b      	ldr	r3, [r7, #4]
 8010168:	6a1b      	ldr	r3, [r3, #32]
 801016a:	613b      	str	r3, [r7, #16]

  /* Disable the output: Reset the CCxE Bit */
  TIMx->CCER &= ~TIM_CCER_CC5E;
 801016c:	687b      	ldr	r3, [r7, #4]
 801016e:	6a1b      	ldr	r3, [r3, #32]
 8010170:	f423 3280 	bic.w	r2, r3, #65536	@ 0x10000
 8010174:	687b      	ldr	r3, [r7, #4]
 8010176:	621a      	str	r2, [r3, #32]

  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 8010178:	687b      	ldr	r3, [r7, #4]
 801017a:	685b      	ldr	r3, [r3, #4]
 801017c:	617b      	str	r3, [r7, #20]
  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR3;
 801017e:	687b      	ldr	r3, [r7, #4]
 8010180:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8010182:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Compare Mode Bits */
  tmpccmrx &= ~(TIM_CCMR3_OC5M);
 8010184:	68fa      	ldr	r2, [r7, #12]
 8010186:	4b21      	ldr	r3, [pc, #132]	@ (801020c <TIM_OC5_SetConfig+0xb0>)
 8010188:	4013      	ands	r3, r2
 801018a:	60fb      	str	r3, [r7, #12]
  /* Select the Output Compare Mode */
  tmpccmrx |= OC_Config->OCMode;
 801018c:	683b      	ldr	r3, [r7, #0]
 801018e:	681b      	ldr	r3, [r3, #0]
 8010190:	68fa      	ldr	r2, [r7, #12]
 8010192:	4313      	orrs	r3, r2
 8010194:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC5P;
 8010196:	693b      	ldr	r3, [r7, #16]
 8010198:	f423 3300 	bic.w	r3, r3, #131072	@ 0x20000
 801019c:	613b      	str	r3, [r7, #16]
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 16U);
 801019e:	683b      	ldr	r3, [r7, #0]
 80101a0:	689b      	ldr	r3, [r3, #8]
 80101a2:	041b      	lsls	r3, r3, #16
 80101a4:	693a      	ldr	r2, [r7, #16]
 80101a6:	4313      	orrs	r3, r2
 80101a8:	613b      	str	r3, [r7, #16]

  if (IS_TIM_BREAK_INSTANCE(TIMx))
 80101aa:	687b      	ldr	r3, [r7, #4]
 80101ac:	4a18      	ldr	r2, [pc, #96]	@ (8010210 <TIM_OC5_SetConfig+0xb4>)
 80101ae:	4293      	cmp	r3, r2
 80101b0:	d00f      	beq.n	80101d2 <TIM_OC5_SetConfig+0x76>
 80101b2:	687b      	ldr	r3, [r7, #4]
 80101b4:	4a17      	ldr	r2, [pc, #92]	@ (8010214 <TIM_OC5_SetConfig+0xb8>)
 80101b6:	4293      	cmp	r3, r2
 80101b8:	d00b      	beq.n	80101d2 <TIM_OC5_SetConfig+0x76>
 80101ba:	687b      	ldr	r3, [r7, #4]
 80101bc:	4a16      	ldr	r2, [pc, #88]	@ (8010218 <TIM_OC5_SetConfig+0xbc>)
 80101be:	4293      	cmp	r3, r2
 80101c0:	d007      	beq.n	80101d2 <TIM_OC5_SetConfig+0x76>
 80101c2:	687b      	ldr	r3, [r7, #4]
 80101c4:	4a15      	ldr	r2, [pc, #84]	@ (801021c <TIM_OC5_SetConfig+0xc0>)
 80101c6:	4293      	cmp	r3, r2
 80101c8:	d003      	beq.n	80101d2 <TIM_OC5_SetConfig+0x76>
 80101ca:	687b      	ldr	r3, [r7, #4]
 80101cc:	4a14      	ldr	r2, [pc, #80]	@ (8010220 <TIM_OC5_SetConfig+0xc4>)
 80101ce:	4293      	cmp	r3, r2
 80101d0:	d109      	bne.n	80101e6 <TIM_OC5_SetConfig+0x8a>
  {
    /* Reset the Output Compare IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS5;
 80101d2:	697b      	ldr	r3, [r7, #20]
 80101d4:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 80101d8:	617b      	str	r3, [r7, #20]
    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 8U);
 80101da:	683b      	ldr	r3, [r7, #0]
 80101dc:	695b      	ldr	r3, [r3, #20]
 80101de:	021b      	lsls	r3, r3, #8
 80101e0:	697a      	ldr	r2, [r7, #20]
 80101e2:	4313      	orrs	r3, r2
 80101e4:	617b      	str	r3, [r7, #20]
  }
  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 80101e6:	687b      	ldr	r3, [r7, #4]
 80101e8:	697a      	ldr	r2, [r7, #20]
 80101ea:	605a      	str	r2, [r3, #4]

  /* Write to TIMx CCMR3 */
  TIMx->CCMR3 = tmpccmrx;
 80101ec:	687b      	ldr	r3, [r7, #4]
 80101ee:	68fa      	ldr	r2, [r7, #12]
 80101f0:	655a      	str	r2, [r3, #84]	@ 0x54

  /* Set the Capture Compare Register value */
  TIMx->CCR5 = OC_Config->Pulse;
 80101f2:	683b      	ldr	r3, [r7, #0]
 80101f4:	685a      	ldr	r2, [r3, #4]
 80101f6:	687b      	ldr	r3, [r7, #4]
 80101f8:	659a      	str	r2, [r3, #88]	@ 0x58

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 80101fa:	687b      	ldr	r3, [r7, #4]
 80101fc:	693a      	ldr	r2, [r7, #16]
 80101fe:	621a      	str	r2, [r3, #32]
}
 8010200:	bf00      	nop
 8010202:	371c      	adds	r7, #28
 8010204:	46bd      	mov	sp, r7
 8010206:	f85d 7b04 	ldr.w	r7, [sp], #4
 801020a:	4770      	bx	lr
 801020c:	fffeff8f 	.word	0xfffeff8f
 8010210:	40010000 	.word	0x40010000
 8010214:	40010400 	.word	0x40010400
 8010218:	40014000 	.word	0x40014000
 801021c:	40014400 	.word	0x40014400
 8010220:	40014800 	.word	0x40014800

08010224 <TIM_OC6_SetConfig>:
  * @param  OC_Config The output configuration structure
  * @retval None
  */
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
                              const TIM_OC_InitTypeDef *OC_Config)
{
 8010224:	b480      	push	{r7}
 8010226:	b087      	sub	sp, #28
 8010228:	af00      	add	r7, sp, #0
 801022a:	6078      	str	r0, [r7, #4]
 801022c:	6039      	str	r1, [r7, #0]
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 801022e:	687b      	ldr	r3, [r7, #4]
 8010230:	6a1b      	ldr	r3, [r3, #32]
 8010232:	613b      	str	r3, [r7, #16]

  /* Disable the output: Reset the CCxE Bit */
  TIMx->CCER &= ~TIM_CCER_CC6E;
 8010234:	687b      	ldr	r3, [r7, #4]
 8010236:	6a1b      	ldr	r3, [r3, #32]
 8010238:	f423 1280 	bic.w	r2, r3, #1048576	@ 0x100000
 801023c:	687b      	ldr	r3, [r7, #4]
 801023e:	621a      	str	r2, [r3, #32]

  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 8010240:	687b      	ldr	r3, [r7, #4]
 8010242:	685b      	ldr	r3, [r3, #4]
 8010244:	617b      	str	r3, [r7, #20]
  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR3;
 8010246:	687b      	ldr	r3, [r7, #4]
 8010248:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 801024a:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Compare Mode Bits */
  tmpccmrx &= ~(TIM_CCMR3_OC6M);
 801024c:	68fa      	ldr	r2, [r7, #12]
 801024e:	4b22      	ldr	r3, [pc, #136]	@ (80102d8 <TIM_OC6_SetConfig+0xb4>)
 8010250:	4013      	ands	r3, r2
 8010252:	60fb      	str	r3, [r7, #12]
  /* Select the Output Compare Mode */
  tmpccmrx |= (OC_Config->OCMode << 8U);
 8010254:	683b      	ldr	r3, [r7, #0]
 8010256:	681b      	ldr	r3, [r3, #0]
 8010258:	021b      	lsls	r3, r3, #8
 801025a:	68fa      	ldr	r2, [r7, #12]
 801025c:	4313      	orrs	r3, r2
 801025e:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Polarity level */
  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
 8010260:	693b      	ldr	r3, [r7, #16]
 8010262:	f423 1300 	bic.w	r3, r3, #2097152	@ 0x200000
 8010266:	613b      	str	r3, [r7, #16]
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 20U);
 8010268:	683b      	ldr	r3, [r7, #0]
 801026a:	689b      	ldr	r3, [r3, #8]
 801026c:	051b      	lsls	r3, r3, #20
 801026e:	693a      	ldr	r2, [r7, #16]
 8010270:	4313      	orrs	r3, r2
 8010272:	613b      	str	r3, [r7, #16]

  if (IS_TIM_BREAK_INSTANCE(TIMx))
 8010274:	687b      	ldr	r3, [r7, #4]
 8010276:	4a19      	ldr	r2, [pc, #100]	@ (80102dc <TIM_OC6_SetConfig+0xb8>)
 8010278:	4293      	cmp	r3, r2
 801027a:	d00f      	beq.n	801029c <TIM_OC6_SetConfig+0x78>
 801027c:	687b      	ldr	r3, [r7, #4]
 801027e:	4a18      	ldr	r2, [pc, #96]	@ (80102e0 <TIM_OC6_SetConfig+0xbc>)
 8010280:	4293      	cmp	r3, r2
 8010282:	d00b      	beq.n	801029c <TIM_OC6_SetConfig+0x78>
 8010284:	687b      	ldr	r3, [r7, #4]
 8010286:	4a17      	ldr	r2, [pc, #92]	@ (80102e4 <TIM_OC6_SetConfig+0xc0>)
 8010288:	4293      	cmp	r3, r2
 801028a:	d007      	beq.n	801029c <TIM_OC6_SetConfig+0x78>
 801028c:	687b      	ldr	r3, [r7, #4]
 801028e:	4a16      	ldr	r2, [pc, #88]	@ (80102e8 <TIM_OC6_SetConfig+0xc4>)
 8010290:	4293      	cmp	r3, r2
 8010292:	d003      	beq.n	801029c <TIM_OC6_SetConfig+0x78>
 8010294:	687b      	ldr	r3, [r7, #4]
 8010296:	4a15      	ldr	r2, [pc, #84]	@ (80102ec <TIM_OC6_SetConfig+0xc8>)
 8010298:	4293      	cmp	r3, r2
 801029a:	d109      	bne.n	80102b0 <TIM_OC6_SetConfig+0x8c>
  {
    /* Reset the Output Compare IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS6;
 801029c:	697b      	ldr	r3, [r7, #20]
 801029e:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
 80102a2:	617b      	str	r3, [r7, #20]
    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 10U);
 80102a4:	683b      	ldr	r3, [r7, #0]
 80102a6:	695b      	ldr	r3, [r3, #20]
 80102a8:	029b      	lsls	r3, r3, #10
 80102aa:	697a      	ldr	r2, [r7, #20]
 80102ac:	4313      	orrs	r3, r2
 80102ae:	617b      	str	r3, [r7, #20]
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 80102b0:	687b      	ldr	r3, [r7, #4]
 80102b2:	697a      	ldr	r2, [r7, #20]
 80102b4:	605a      	str	r2, [r3, #4]

  /* Write to TIMx CCMR3 */
  TIMx->CCMR3 = tmpccmrx;
 80102b6:	687b      	ldr	r3, [r7, #4]
 80102b8:	68fa      	ldr	r2, [r7, #12]
 80102ba:	655a      	str	r2, [r3, #84]	@ 0x54

  /* Set the Capture Compare Register value */
  TIMx->CCR6 = OC_Config->Pulse;
 80102bc:	683b      	ldr	r3, [r7, #0]
 80102be:	685a      	ldr	r2, [r3, #4]
 80102c0:	687b      	ldr	r3, [r7, #4]
 80102c2:	65da      	str	r2, [r3, #92]	@ 0x5c

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 80102c4:	687b      	ldr	r3, [r7, #4]
 80102c6:	693a      	ldr	r2, [r7, #16]
 80102c8:	621a      	str	r2, [r3, #32]
}
 80102ca:	bf00      	nop
 80102cc:	371c      	adds	r7, #28
 80102ce:	46bd      	mov	sp, r7
 80102d0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80102d4:	4770      	bx	lr
 80102d6:	bf00      	nop
 80102d8:	feff8fff 	.word	0xfeff8fff
 80102dc:	40010000 	.word	0x40010000
 80102e0:	40010400 	.word	0x40010400
 80102e4:	40014000 	.word	0x40014000
 80102e8:	40014400 	.word	0x40014400
 80102ec:	40014800 	.word	0x40014800

080102f0 <TIM_TI1_SetConfig>:
  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
  *        protected against un-initialized filter and polarity values.
  */
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
                       uint32_t TIM_ICFilter)
{
 80102f0:	b480      	push	{r7}
 80102f2:	b087      	sub	sp, #28
 80102f4:	af00      	add	r7, sp, #0
 80102f6:	60f8      	str	r0, [r7, #12]
 80102f8:	60b9      	str	r1, [r7, #8]
 80102fa:	607a      	str	r2, [r7, #4]
 80102fc:	603b      	str	r3, [r7, #0]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 1: Reset the CC1E Bit */
  tmpccer = TIMx->CCER;
 80102fe:	68fb      	ldr	r3, [r7, #12]
 8010300:	6a1b      	ldr	r3, [r3, #32]
 8010302:	613b      	str	r3, [r7, #16]
  TIMx->CCER &= ~TIM_CCER_CC1E;
 8010304:	68fb      	ldr	r3, [r7, #12]
 8010306:	6a1b      	ldr	r3, [r3, #32]
 8010308:	f023 0201 	bic.w	r2, r3, #1
 801030c:	68fb      	ldr	r3, [r7, #12]
 801030e:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 8010310:	68fb      	ldr	r3, [r7, #12]
 8010312:	699b      	ldr	r3, [r3, #24]
 8010314:	617b      	str	r3, [r7, #20]

  /* Select the Input */
  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
 8010316:	68fb      	ldr	r3, [r7, #12]
 8010318:	4a28      	ldr	r2, [pc, #160]	@ (80103bc <TIM_TI1_SetConfig+0xcc>)
 801031a:	4293      	cmp	r3, r2
 801031c:	d01b      	beq.n	8010356 <TIM_TI1_SetConfig+0x66>
 801031e:	68fb      	ldr	r3, [r7, #12]
 8010320:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8010324:	d017      	beq.n	8010356 <TIM_TI1_SetConfig+0x66>
 8010326:	68fb      	ldr	r3, [r7, #12]
 8010328:	4a25      	ldr	r2, [pc, #148]	@ (80103c0 <TIM_TI1_SetConfig+0xd0>)
 801032a:	4293      	cmp	r3, r2
 801032c:	d013      	beq.n	8010356 <TIM_TI1_SetConfig+0x66>
 801032e:	68fb      	ldr	r3, [r7, #12]
 8010330:	4a24      	ldr	r2, [pc, #144]	@ (80103c4 <TIM_TI1_SetConfig+0xd4>)
 8010332:	4293      	cmp	r3, r2
 8010334:	d00f      	beq.n	8010356 <TIM_TI1_SetConfig+0x66>
 8010336:	68fb      	ldr	r3, [r7, #12]
 8010338:	4a23      	ldr	r2, [pc, #140]	@ (80103c8 <TIM_TI1_SetConfig+0xd8>)
 801033a:	4293      	cmp	r3, r2
 801033c:	d00b      	beq.n	8010356 <TIM_TI1_SetConfig+0x66>
 801033e:	68fb      	ldr	r3, [r7, #12]
 8010340:	4a22      	ldr	r2, [pc, #136]	@ (80103cc <TIM_TI1_SetConfig+0xdc>)
 8010342:	4293      	cmp	r3, r2
 8010344:	d007      	beq.n	8010356 <TIM_TI1_SetConfig+0x66>
 8010346:	68fb      	ldr	r3, [r7, #12]
 8010348:	4a21      	ldr	r2, [pc, #132]	@ (80103d0 <TIM_TI1_SetConfig+0xe0>)
 801034a:	4293      	cmp	r3, r2
 801034c:	d003      	beq.n	8010356 <TIM_TI1_SetConfig+0x66>
 801034e:	68fb      	ldr	r3, [r7, #12]
 8010350:	4a20      	ldr	r2, [pc, #128]	@ (80103d4 <TIM_TI1_SetConfig+0xe4>)
 8010352:	4293      	cmp	r3, r2
 8010354:	d101      	bne.n	801035a <TIM_TI1_SetConfig+0x6a>
 8010356:	2301      	movs	r3, #1
 8010358:	e000      	b.n	801035c <TIM_TI1_SetConfig+0x6c>
 801035a:	2300      	movs	r3, #0
 801035c:	2b00      	cmp	r3, #0
 801035e:	d008      	beq.n	8010372 <TIM_TI1_SetConfig+0x82>
  {
    tmpccmr1 &= ~TIM_CCMR1_CC1S;
 8010360:	697b      	ldr	r3, [r7, #20]
 8010362:	f023 0303 	bic.w	r3, r3, #3
 8010366:	617b      	str	r3, [r7, #20]
    tmpccmr1 |= TIM_ICSelection;
 8010368:	697a      	ldr	r2, [r7, #20]
 801036a:	687b      	ldr	r3, [r7, #4]
 801036c:	4313      	orrs	r3, r2
 801036e:	617b      	str	r3, [r7, #20]
 8010370:	e003      	b.n	801037a <TIM_TI1_SetConfig+0x8a>
  }
  else
  {
    tmpccmr1 |= TIM_CCMR1_CC1S_0;
 8010372:	697b      	ldr	r3, [r7, #20]
 8010374:	f043 0301 	orr.w	r3, r3, #1
 8010378:	617b      	str	r3, [r7, #20]
  }

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC1F;
 801037a:	697b      	ldr	r3, [r7, #20]
 801037c:	f023 03f0 	bic.w	r3, r3, #240	@ 0xf0
 8010380:	617b      	str	r3, [r7, #20]
  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
 8010382:	683b      	ldr	r3, [r7, #0]
 8010384:	011b      	lsls	r3, r3, #4
 8010386:	b2db      	uxtb	r3, r3
 8010388:	697a      	ldr	r2, [r7, #20]
 801038a:	4313      	orrs	r3, r2
 801038c:	617b      	str	r3, [r7, #20]

  /* Select the Polarity and set the CC1E Bit */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
 801038e:	693b      	ldr	r3, [r7, #16]
 8010390:	f023 030a 	bic.w	r3, r3, #10
 8010394:	613b      	str	r3, [r7, #16]
  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
 8010396:	68bb      	ldr	r3, [r7, #8]
 8010398:	f003 030a 	and.w	r3, r3, #10
 801039c:	693a      	ldr	r2, [r7, #16]
 801039e:	4313      	orrs	r3, r2
 80103a0:	613b      	str	r3, [r7, #16]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
 80103a2:	68fb      	ldr	r3, [r7, #12]
 80103a4:	697a      	ldr	r2, [r7, #20]
 80103a6:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 80103a8:	68fb      	ldr	r3, [r7, #12]
 80103aa:	693a      	ldr	r2, [r7, #16]
 80103ac:	621a      	str	r2, [r3, #32]
}
 80103ae:	bf00      	nop
 80103b0:	371c      	adds	r7, #28
 80103b2:	46bd      	mov	sp, r7
 80103b4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80103b8:	4770      	bx	lr
 80103ba:	bf00      	nop
 80103bc:	40010000 	.word	0x40010000
 80103c0:	40000400 	.word	0x40000400
 80103c4:	40000800 	.word	0x40000800
 80103c8:	40000c00 	.word	0x40000c00
 80103cc:	40010400 	.word	0x40010400
 80103d0:	40001800 	.word	0x40001800
 80103d4:	40014000 	.word	0x40014000

080103d8 <TIM_TI1_ConfigInputStage>:
  * @param  TIM_ICFilter Specifies the Input Capture Filter.
  *          This parameter must be a value between 0x00 and 0x0F.
  * @retval None
  */
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
 80103d8:	b480      	push	{r7}
 80103da:	b087      	sub	sp, #28
 80103dc:	af00      	add	r7, sp, #0
 80103de:	60f8      	str	r0, [r7, #12]
 80103e0:	60b9      	str	r1, [r7, #8]
 80103e2:	607a      	str	r2, [r7, #4]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 1: Reset the CC1E Bit */
  tmpccer = TIMx->CCER;
 80103e4:	68fb      	ldr	r3, [r7, #12]
 80103e6:	6a1b      	ldr	r3, [r3, #32]
 80103e8:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC1E;
 80103ea:	68fb      	ldr	r3, [r7, #12]
 80103ec:	6a1b      	ldr	r3, [r3, #32]
 80103ee:	f023 0201 	bic.w	r2, r3, #1
 80103f2:	68fb      	ldr	r3, [r7, #12]
 80103f4:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 80103f6:	68fb      	ldr	r3, [r7, #12]
 80103f8:	699b      	ldr	r3, [r3, #24]
 80103fa:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC1F;
 80103fc:	693b      	ldr	r3, [r7, #16]
 80103fe:	f023 03f0 	bic.w	r3, r3, #240	@ 0xf0
 8010402:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= (TIM_ICFilter << 4U);
 8010404:	687b      	ldr	r3, [r7, #4]
 8010406:	011b      	lsls	r3, r3, #4
 8010408:	693a      	ldr	r2, [r7, #16]
 801040a:	4313      	orrs	r3, r2
 801040c:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC1E Bit */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
 801040e:	697b      	ldr	r3, [r7, #20]
 8010410:	f023 030a 	bic.w	r3, r3, #10
 8010414:	617b      	str	r3, [r7, #20]
  tmpccer |= TIM_ICPolarity;
 8010416:	697a      	ldr	r2, [r7, #20]
 8010418:	68bb      	ldr	r3, [r7, #8]
 801041a:	4313      	orrs	r3, r2
 801041c:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
 801041e:	68fb      	ldr	r3, [r7, #12]
 8010420:	693a      	ldr	r2, [r7, #16]
 8010422:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 8010424:	68fb      	ldr	r3, [r7, #12]
 8010426:	697a      	ldr	r2, [r7, #20]
 8010428:	621a      	str	r2, [r3, #32]
}
 801042a:	bf00      	nop
 801042c:	371c      	adds	r7, #28
 801042e:	46bd      	mov	sp, r7
 8010430:	f85d 7b04 	ldr.w	r7, [sp], #4
 8010434:	4770      	bx	lr

08010436 <TIM_TI2_SetConfig>:
  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
  *        protected against un-initialized filter and polarity values.
  */
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
                              uint32_t TIM_ICFilter)
{
 8010436:	b480      	push	{r7}
 8010438:	b087      	sub	sp, #28
 801043a:	af00      	add	r7, sp, #0
 801043c:	60f8      	str	r0, [r7, #12]
 801043e:	60b9      	str	r1, [r7, #8]
 8010440:	607a      	str	r2, [r7, #4]
 8010442:	603b      	str	r3, [r7, #0]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 2: Reset the CC2E Bit */
  tmpccer = TIMx->CCER;
 8010444:	68fb      	ldr	r3, [r7, #12]
 8010446:	6a1b      	ldr	r3, [r3, #32]
 8010448:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC2E;
 801044a:	68fb      	ldr	r3, [r7, #12]
 801044c:	6a1b      	ldr	r3, [r3, #32]
 801044e:	f023 0210 	bic.w	r2, r3, #16
 8010452:	68fb      	ldr	r3, [r7, #12]
 8010454:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 8010456:	68fb      	ldr	r3, [r7, #12]
 8010458:	699b      	ldr	r3, [r3, #24]
 801045a:	613b      	str	r3, [r7, #16]

  /* Select the Input */
  tmpccmr1 &= ~TIM_CCMR1_CC2S;
 801045c:	693b      	ldr	r3, [r7, #16]
 801045e:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 8010462:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= (TIM_ICSelection << 8U);
 8010464:	687b      	ldr	r3, [r7, #4]
 8010466:	021b      	lsls	r3, r3, #8
 8010468:	693a      	ldr	r2, [r7, #16]
 801046a:	4313      	orrs	r3, r2
 801046c:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC2F;
 801046e:	693b      	ldr	r3, [r7, #16]
 8010470:	f423 4370 	bic.w	r3, r3, #61440	@ 0xf000
 8010474:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
 8010476:	683b      	ldr	r3, [r7, #0]
 8010478:	031b      	lsls	r3, r3, #12
 801047a:	b29b      	uxth	r3, r3
 801047c:	693a      	ldr	r2, [r7, #16]
 801047e:	4313      	orrs	r3, r2
 8010480:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC2E Bit */
  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
 8010482:	697b      	ldr	r3, [r7, #20]
 8010484:	f023 03a0 	bic.w	r3, r3, #160	@ 0xa0
 8010488:	617b      	str	r3, [r7, #20]
  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
 801048a:	68bb      	ldr	r3, [r7, #8]
 801048c:	011b      	lsls	r3, r3, #4
 801048e:	f003 03a0 	and.w	r3, r3, #160	@ 0xa0
 8010492:	697a      	ldr	r2, [r7, #20]
 8010494:	4313      	orrs	r3, r2
 8010496:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1 ;
 8010498:	68fb      	ldr	r3, [r7, #12]
 801049a:	693a      	ldr	r2, [r7, #16]
 801049c:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 801049e:	68fb      	ldr	r3, [r7, #12]
 80104a0:	697a      	ldr	r2, [r7, #20]
 80104a2:	621a      	str	r2, [r3, #32]
}
 80104a4:	bf00      	nop
 80104a6:	371c      	adds	r7, #28
 80104a8:	46bd      	mov	sp, r7
 80104aa:	f85d 7b04 	ldr.w	r7, [sp], #4
 80104ae:	4770      	bx	lr

080104b0 <TIM_TI2_ConfigInputStage>:
  * @param  TIM_ICFilter Specifies the Input Capture Filter.
  *          This parameter must be a value between 0x00 and 0x0F.
  * @retval None
  */
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
 80104b0:	b480      	push	{r7}
 80104b2:	b087      	sub	sp, #28
 80104b4:	af00      	add	r7, sp, #0
 80104b6:	60f8      	str	r0, [r7, #12]
 80104b8:	60b9      	str	r1, [r7, #8]
 80104ba:	607a      	str	r2, [r7, #4]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 2: Reset the CC2E Bit */
  tmpccer = TIMx->CCER;
 80104bc:	68fb      	ldr	r3, [r7, #12]
 80104be:	6a1b      	ldr	r3, [r3, #32]
 80104c0:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC2E;
 80104c2:	68fb      	ldr	r3, [r7, #12]
 80104c4:	6a1b      	ldr	r3, [r3, #32]
 80104c6:	f023 0210 	bic.w	r2, r3, #16
 80104ca:	68fb      	ldr	r3, [r7, #12]
 80104cc:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 80104ce:	68fb      	ldr	r3, [r7, #12]
 80104d0:	699b      	ldr	r3, [r3, #24]
 80104d2:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC2F;
 80104d4:	693b      	ldr	r3, [r7, #16]
 80104d6:	f423 4370 	bic.w	r3, r3, #61440	@ 0xf000
 80104da:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= (TIM_ICFilter << 12U);
 80104dc:	687b      	ldr	r3, [r7, #4]
 80104de:	031b      	lsls	r3, r3, #12
 80104e0:	693a      	ldr	r2, [r7, #16]
 80104e2:	4313      	orrs	r3, r2
 80104e4:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC2E Bit */
  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
 80104e6:	697b      	ldr	r3, [r7, #20]
 80104e8:	f023 03a0 	bic.w	r3, r3, #160	@ 0xa0
 80104ec:	617b      	str	r3, [r7, #20]
  tmpccer |= (TIM_ICPolarity << 4U);
 80104ee:	68bb      	ldr	r3, [r7, #8]
 80104f0:	011b      	lsls	r3, r3, #4
 80104f2:	697a      	ldr	r2, [r7, #20]
 80104f4:	4313      	orrs	r3, r2
 80104f6:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1 ;
 80104f8:	68fb      	ldr	r3, [r7, #12]
 80104fa:	693a      	ldr	r2, [r7, #16]
 80104fc:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 80104fe:	68fb      	ldr	r3, [r7, #12]
 8010500:	697a      	ldr	r2, [r7, #20]
 8010502:	621a      	str	r2, [r3, #32]
}
 8010504:	bf00      	nop
 8010506:	371c      	adds	r7, #28
 8010508:	46bd      	mov	sp, r7
 801050a:	f85d 7b04 	ldr.w	r7, [sp], #4
 801050e:	4770      	bx	lr

08010510 <TIM_TI3_SetConfig>:
  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
  *        protected against un-initialized filter and polarity values.
  */
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
                              uint32_t TIM_ICFilter)
{
 8010510:	b480      	push	{r7}
 8010512:	b087      	sub	sp, #28
 8010514:	af00      	add	r7, sp, #0
 8010516:	60f8      	str	r0, [r7, #12]
 8010518:	60b9      	str	r1, [r7, #8]
 801051a:	607a      	str	r2, [r7, #4]
 801051c:	603b      	str	r3, [r7, #0]
  uint32_t tmpccmr2;
  uint32_t tmpccer;

  /* Disable the Channel 3: Reset the CC3E Bit */
  tmpccer = TIMx->CCER;
 801051e:	68fb      	ldr	r3, [r7, #12]
 8010520:	6a1b      	ldr	r3, [r3, #32]
 8010522:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC3E;
 8010524:	68fb      	ldr	r3, [r7, #12]
 8010526:	6a1b      	ldr	r3, [r3, #32]
 8010528:	f423 7280 	bic.w	r2, r3, #256	@ 0x100
 801052c:	68fb      	ldr	r3, [r7, #12]
 801052e:	621a      	str	r2, [r3, #32]
  tmpccmr2 = TIMx->CCMR2;
 8010530:	68fb      	ldr	r3, [r7, #12]
 8010532:	69db      	ldr	r3, [r3, #28]
 8010534:	613b      	str	r3, [r7, #16]

  /* Select the Input */
  tmpccmr2 &= ~TIM_CCMR2_CC3S;
 8010536:	693b      	ldr	r3, [r7, #16]
 8010538:	f023 0303 	bic.w	r3, r3, #3
 801053c:	613b      	str	r3, [r7, #16]
  tmpccmr2 |= TIM_ICSelection;
 801053e:	693a      	ldr	r2, [r7, #16]
 8010540:	687b      	ldr	r3, [r7, #4]
 8010542:	4313      	orrs	r3, r2
 8010544:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr2 &= ~TIM_CCMR2_IC3F;
 8010546:	693b      	ldr	r3, [r7, #16]
 8010548:	f023 03f0 	bic.w	r3, r3, #240	@ 0xf0
 801054c:	613b      	str	r3, [r7, #16]
  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
 801054e:	683b      	ldr	r3, [r7, #0]
 8010550:	011b      	lsls	r3, r3, #4
 8010552:	b2db      	uxtb	r3, r3
 8010554:	693a      	ldr	r2, [r7, #16]
 8010556:	4313      	orrs	r3, r2
 8010558:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC3E Bit */
  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
 801055a:	697b      	ldr	r3, [r7, #20]
 801055c:	f423 6320 	bic.w	r3, r3, #2560	@ 0xa00
 8010560:	617b      	str	r3, [r7, #20]
  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
 8010562:	68bb      	ldr	r3, [r7, #8]
 8010564:	021b      	lsls	r3, r3, #8
 8010566:	f403 6320 	and.w	r3, r3, #2560	@ 0xa00
 801056a:	697a      	ldr	r2, [r7, #20]
 801056c:	4313      	orrs	r3, r2
 801056e:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR2 and CCER registers */
  TIMx->CCMR2 = tmpccmr2;
 8010570:	68fb      	ldr	r3, [r7, #12]
 8010572:	693a      	ldr	r2, [r7, #16]
 8010574:	61da      	str	r2, [r3, #28]
  TIMx->CCER = tmpccer;
 8010576:	68fb      	ldr	r3, [r7, #12]
 8010578:	697a      	ldr	r2, [r7, #20]
 801057a:	621a      	str	r2, [r3, #32]
}
 801057c:	bf00      	nop
 801057e:	371c      	adds	r7, #28
 8010580:	46bd      	mov	sp, r7
 8010582:	f85d 7b04 	ldr.w	r7, [sp], #4
 8010586:	4770      	bx	lr

08010588 <TIM_TI4_SetConfig>:
  *        protected against un-initialized filter and polarity values.
  * @retval None
  */
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
                              uint32_t TIM_ICFilter)
{
 8010588:	b480      	push	{r7}
 801058a:	b087      	sub	sp, #28
 801058c:	af00      	add	r7, sp, #0
 801058e:	60f8      	str	r0, [r7, #12]
 8010590:	60b9      	str	r1, [r7, #8]
 8010592:	607a      	str	r2, [r7, #4]
 8010594:	603b      	str	r3, [r7, #0]
  uint32_t tmpccmr2;
  uint32_t tmpccer;

  /* Disable the Channel 4: Reset the CC4E Bit */
  tmpccer = TIMx->CCER;
 8010596:	68fb      	ldr	r3, [r7, #12]
 8010598:	6a1b      	ldr	r3, [r3, #32]
 801059a:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC4E;
 801059c:	68fb      	ldr	r3, [r7, #12]
 801059e:	6a1b      	ldr	r3, [r3, #32]
 80105a0:	f423 5280 	bic.w	r2, r3, #4096	@ 0x1000
 80105a4:	68fb      	ldr	r3, [r7, #12]
 80105a6:	621a      	str	r2, [r3, #32]
  tmpccmr2 = TIMx->CCMR2;
 80105a8:	68fb      	ldr	r3, [r7, #12]
 80105aa:	69db      	ldr	r3, [r3, #28]
 80105ac:	613b      	str	r3, [r7, #16]

  /* Select the Input */
  tmpccmr2 &= ~TIM_CCMR2_CC4S;
 80105ae:	693b      	ldr	r3, [r7, #16]
 80105b0:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 80105b4:	613b      	str	r3, [r7, #16]
  tmpccmr2 |= (TIM_ICSelection << 8U);
 80105b6:	687b      	ldr	r3, [r7, #4]
 80105b8:	021b      	lsls	r3, r3, #8
 80105ba:	693a      	ldr	r2, [r7, #16]
 80105bc:	4313      	orrs	r3, r2
 80105be:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr2 &= ~TIM_CCMR2_IC4F;
 80105c0:	693b      	ldr	r3, [r7, #16]
 80105c2:	f423 4370 	bic.w	r3, r3, #61440	@ 0xf000
 80105c6:	613b      	str	r3, [r7, #16]
  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
 80105c8:	683b      	ldr	r3, [r7, #0]
 80105ca:	031b      	lsls	r3, r3, #12
 80105cc:	b29b      	uxth	r3, r3
 80105ce:	693a      	ldr	r2, [r7, #16]
 80105d0:	4313      	orrs	r3, r2
 80105d2:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC4E Bit */
  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
 80105d4:	697b      	ldr	r3, [r7, #20]
 80105d6:	f423 4320 	bic.w	r3, r3, #40960	@ 0xa000
 80105da:	617b      	str	r3, [r7, #20]
  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
 80105dc:	68bb      	ldr	r3, [r7, #8]
 80105de:	031b      	lsls	r3, r3, #12
 80105e0:	f403 4320 	and.w	r3, r3, #40960	@ 0xa000
 80105e4:	697a      	ldr	r2, [r7, #20]
 80105e6:	4313      	orrs	r3, r2
 80105e8:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR2 and CCER registers */
  TIMx->CCMR2 = tmpccmr2;
 80105ea:	68fb      	ldr	r3, [r7, #12]
 80105ec:	693a      	ldr	r2, [r7, #16]
 80105ee:	61da      	str	r2, [r3, #28]
  TIMx->CCER = tmpccer ;
 80105f0:	68fb      	ldr	r3, [r7, #12]
 80105f2:	697a      	ldr	r2, [r7, #20]
 80105f4:	621a      	str	r2, [r3, #32]
}
 80105f6:	bf00      	nop
 80105f8:	371c      	adds	r7, #28
 80105fa:	46bd      	mov	sp, r7
 80105fc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8010600:	4770      	bx	lr
	...

08010604 <TIM_ITRx_SetConfig>:
  *       (*)  Value not defined in all devices.
  *
  * @retval None
  */
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
 8010604:	b480      	push	{r7}
 8010606:	b085      	sub	sp, #20
 8010608:	af00      	add	r7, sp, #0
 801060a:	6078      	str	r0, [r7, #4]
 801060c:	6039      	str	r1, [r7, #0]
  uint32_t tmpsmcr;

  /* Get the TIMx SMCR register value */
  tmpsmcr = TIMx->SMCR;
 801060e:	687b      	ldr	r3, [r7, #4]
 8010610:	689b      	ldr	r3, [r3, #8]
 8010612:	60fb      	str	r3, [r7, #12]
  /* Reset the TS Bits */
  tmpsmcr &= ~TIM_SMCR_TS;
 8010614:	68fa      	ldr	r2, [r7, #12]
 8010616:	4b09      	ldr	r3, [pc, #36]	@ (801063c <TIM_ITRx_SetConfig+0x38>)
 8010618:	4013      	ands	r3, r2
 801061a:	60fb      	str	r3, [r7, #12]
  /* Set the Input Trigger source and the slave mode*/
  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
 801061c:	683a      	ldr	r2, [r7, #0]
 801061e:	68fb      	ldr	r3, [r7, #12]
 8010620:	4313      	orrs	r3, r2
 8010622:	f043 0307 	orr.w	r3, r3, #7
 8010626:	60fb      	str	r3, [r7, #12]
  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
 8010628:	687b      	ldr	r3, [r7, #4]
 801062a:	68fa      	ldr	r2, [r7, #12]
 801062c:	609a      	str	r2, [r3, #8]
}
 801062e:	bf00      	nop
 8010630:	3714      	adds	r7, #20
 8010632:	46bd      	mov	sp, r7
 8010634:	f85d 7b04 	ldr.w	r7, [sp], #4
 8010638:	4770      	bx	lr
 801063a:	bf00      	nop
 801063c:	ffcfff8f 	.word	0xffcfff8f

08010640 <TIM_ETR_SetConfig>:
  *          This parameter must be a value between 0x00 and 0x0F
  * @retval None
  */
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
 8010640:	b480      	push	{r7}
 8010642:	b087      	sub	sp, #28
 8010644:	af00      	add	r7, sp, #0
 8010646:	60f8      	str	r0, [r7, #12]
 8010648:	60b9      	str	r1, [r7, #8]
 801064a:	607a      	str	r2, [r7, #4]
 801064c:	603b      	str	r3, [r7, #0]
  uint32_t tmpsmcr;

  tmpsmcr = TIMx->SMCR;
 801064e:	68fb      	ldr	r3, [r7, #12]
 8010650:	689b      	ldr	r3, [r3, #8]
 8010652:	617b      	str	r3, [r7, #20]

  /* Reset the ETR Bits */
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 8010654:	697b      	ldr	r3, [r7, #20]
 8010656:	f423 437f 	bic.w	r3, r3, #65280	@ 0xff00
 801065a:	617b      	str	r3, [r7, #20]

  /* Set the Prescaler, the Filter value and the Polarity */
  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
 801065c:	683b      	ldr	r3, [r7, #0]
 801065e:	021a      	lsls	r2, r3, #8
 8010660:	687b      	ldr	r3, [r7, #4]
 8010662:	431a      	orrs	r2, r3
 8010664:	68bb      	ldr	r3, [r7, #8]
 8010666:	4313      	orrs	r3, r2
 8010668:	697a      	ldr	r2, [r7, #20]
 801066a:	4313      	orrs	r3, r2
 801066c:	617b      	str	r3, [r7, #20]

  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
 801066e:	68fb      	ldr	r3, [r7, #12]
 8010670:	697a      	ldr	r2, [r7, #20]
 8010672:	609a      	str	r2, [r3, #8]
}
 8010674:	bf00      	nop
 8010676:	371c      	adds	r7, #28
 8010678:	46bd      	mov	sp, r7
 801067a:	f85d 7b04 	ldr.w	r7, [sp], #4
 801067e:	4770      	bx	lr

08010680 <TIM_CCxChannelCmd>:
  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
  * @retval None
  */
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
 8010680:	b480      	push	{r7}
 8010682:	b087      	sub	sp, #28
 8010684:	af00      	add	r7, sp, #0
 8010686:	60f8      	str	r0, [r7, #12]
 8010688:	60b9      	str	r1, [r7, #8]
 801068a:	607a      	str	r2, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  assert_param(IS_TIM_CHANNELS(Channel));

  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
 801068c:	68bb      	ldr	r3, [r7, #8]
 801068e:	f003 031f 	and.w	r3, r3, #31
 8010692:	2201      	movs	r2, #1
 8010694:	fa02 f303 	lsl.w	r3, r2, r3
 8010698:	617b      	str	r3, [r7, #20]

  /* Reset the CCxE Bit */
  TIMx->CCER &= ~tmp;
 801069a:	68fb      	ldr	r3, [r7, #12]
 801069c:	6a1a      	ldr	r2, [r3, #32]
 801069e:	697b      	ldr	r3, [r7, #20]
 80106a0:	43db      	mvns	r3, r3
 80106a2:	401a      	ands	r2, r3
 80106a4:	68fb      	ldr	r3, [r7, #12]
 80106a6:	621a      	str	r2, [r3, #32]

  /* Set or reset the CCxE Bit */
  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
 80106a8:	68fb      	ldr	r3, [r7, #12]
 80106aa:	6a1a      	ldr	r2, [r3, #32]
 80106ac:	68bb      	ldr	r3, [r7, #8]
 80106ae:	f003 031f 	and.w	r3, r3, #31
 80106b2:	6879      	ldr	r1, [r7, #4]
 80106b4:	fa01 f303 	lsl.w	r3, r1, r3
 80106b8:	431a      	orrs	r2, r3
 80106ba:	68fb      	ldr	r3, [r7, #12]
 80106bc:	621a      	str	r2, [r3, #32]
}
 80106be:	bf00      	nop
 80106c0:	371c      	adds	r7, #28
 80106c2:	46bd      	mov	sp, r7
 80106c4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80106c8:	4770      	bx	lr
	...

080106cc <HAL_TIMEx_MasterConfigSynchronization>:
  *         mode.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
{
 80106cc:	b480      	push	{r7}
 80106ce:	b085      	sub	sp, #20
 80106d0:	af00      	add	r7, sp, #0
 80106d2:	6078      	str	r0, [r7, #4]
 80106d4:	6039      	str	r1, [r7, #0]
  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  /* Check input state */
  __HAL_LOCK(htim);
 80106d6:	687b      	ldr	r3, [r7, #4]
 80106d8:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
 80106dc:	2b01      	cmp	r3, #1
 80106de:	d101      	bne.n	80106e4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
 80106e0:	2302      	movs	r3, #2
 80106e2:	e06d      	b.n	80107c0 <HAL_TIMEx_MasterConfigSynchronization+0xf4>
 80106e4:	687b      	ldr	r3, [r7, #4]
 80106e6:	2201      	movs	r2, #1
 80106e8:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  /* Change the handler state */
  htim->State = HAL_TIM_STATE_BUSY;
 80106ec:	687b      	ldr	r3, [r7, #4]
 80106ee:	2202      	movs	r2, #2
 80106f0:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  /* Get the TIMx CR2 register value */
  tmpcr2 = htim->Instance->CR2;
 80106f4:	687b      	ldr	r3, [r7, #4]
 80106f6:	681b      	ldr	r3, [r3, #0]
 80106f8:	685b      	ldr	r3, [r3, #4]
 80106fa:	60fb      	str	r3, [r7, #12]

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;
 80106fc:	687b      	ldr	r3, [r7, #4]
 80106fe:	681b      	ldr	r3, [r3, #0]
 8010700:	689b      	ldr	r3, [r3, #8]
 8010702:	60bb      	str	r3, [r7, #8]

  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
 8010704:	687b      	ldr	r3, [r7, #4]
 8010706:	681b      	ldr	r3, [r3, #0]
 8010708:	4a30      	ldr	r2, [pc, #192]	@ (80107cc <HAL_TIMEx_MasterConfigSynchronization+0x100>)
 801070a:	4293      	cmp	r3, r2
 801070c:	d004      	beq.n	8010718 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
 801070e:	687b      	ldr	r3, [r7, #4]
 8010710:	681b      	ldr	r3, [r3, #0]
 8010712:	4a2f      	ldr	r2, [pc, #188]	@ (80107d0 <HAL_TIMEx_MasterConfigSynchronization+0x104>)
 8010714:	4293      	cmp	r3, r2
 8010716:	d108      	bne.n	801072a <HAL_TIMEx_MasterConfigSynchronization+0x5e>
  {
    /* Check the parameters */
    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));

    /* Clear the MMS2 bits */
    tmpcr2 &= ~TIM_CR2_MMS2;
 8010718:	68fb      	ldr	r3, [r7, #12]
 801071a:	f423 0370 	bic.w	r3, r3, #15728640	@ 0xf00000
 801071e:	60fb      	str	r3, [r7, #12]
    /* Select the TRGO2 source*/
    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
 8010720:	683b      	ldr	r3, [r7, #0]
 8010722:	685b      	ldr	r3, [r3, #4]
 8010724:	68fa      	ldr	r2, [r7, #12]
 8010726:	4313      	orrs	r3, r2
 8010728:	60fb      	str	r3, [r7, #12]
  }

  /* Reset the MMS Bits */
  tmpcr2 &= ~TIM_CR2_MMS;
 801072a:	68fb      	ldr	r3, [r7, #12]
 801072c:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
 8010730:	60fb      	str	r3, [r7, #12]
  /* Select the TRGO source */
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 8010732:	683b      	ldr	r3, [r7, #0]
 8010734:	681b      	ldr	r3, [r3, #0]
 8010736:	68fa      	ldr	r2, [r7, #12]
 8010738:	4313      	orrs	r3, r2
 801073a:	60fb      	str	r3, [r7, #12]

  /* Update TIMx CR2 */
  htim->Instance->CR2 = tmpcr2;
 801073c:	687b      	ldr	r3, [r7, #4]
 801073e:	681b      	ldr	r3, [r3, #0]
 8010740:	68fa      	ldr	r2, [r7, #12]
 8010742:	605a      	str	r2, [r3, #4]

  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8010744:	687b      	ldr	r3, [r7, #4]
 8010746:	681b      	ldr	r3, [r3, #0]
 8010748:	4a20      	ldr	r2, [pc, #128]	@ (80107cc <HAL_TIMEx_MasterConfigSynchronization+0x100>)
 801074a:	4293      	cmp	r3, r2
 801074c:	d022      	beq.n	8010794 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 801074e:	687b      	ldr	r3, [r7, #4]
 8010750:	681b      	ldr	r3, [r3, #0]
 8010752:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8010756:	d01d      	beq.n	8010794 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 8010758:	687b      	ldr	r3, [r7, #4]
 801075a:	681b      	ldr	r3, [r3, #0]
 801075c:	4a1d      	ldr	r2, [pc, #116]	@ (80107d4 <HAL_TIMEx_MasterConfigSynchronization+0x108>)
 801075e:	4293      	cmp	r3, r2
 8010760:	d018      	beq.n	8010794 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 8010762:	687b      	ldr	r3, [r7, #4]
 8010764:	681b      	ldr	r3, [r3, #0]
 8010766:	4a1c      	ldr	r2, [pc, #112]	@ (80107d8 <HAL_TIMEx_MasterConfigSynchronization+0x10c>)
 8010768:	4293      	cmp	r3, r2
 801076a:	d013      	beq.n	8010794 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 801076c:	687b      	ldr	r3, [r7, #4]
 801076e:	681b      	ldr	r3, [r3, #0]
 8010770:	4a1a      	ldr	r2, [pc, #104]	@ (80107dc <HAL_TIMEx_MasterConfigSynchronization+0x110>)
 8010772:	4293      	cmp	r3, r2
 8010774:	d00e      	beq.n	8010794 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 8010776:	687b      	ldr	r3, [r7, #4]
 8010778:	681b      	ldr	r3, [r3, #0]
 801077a:	4a15      	ldr	r2, [pc, #84]	@ (80107d0 <HAL_TIMEx_MasterConfigSynchronization+0x104>)
 801077c:	4293      	cmp	r3, r2
 801077e:	d009      	beq.n	8010794 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 8010780:	687b      	ldr	r3, [r7, #4]
 8010782:	681b      	ldr	r3, [r3, #0]
 8010784:	4a16      	ldr	r2, [pc, #88]	@ (80107e0 <HAL_TIMEx_MasterConfigSynchronization+0x114>)
 8010786:	4293      	cmp	r3, r2
 8010788:	d004      	beq.n	8010794 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
 801078a:	687b      	ldr	r3, [r7, #4]
 801078c:	681b      	ldr	r3, [r3, #0]
 801078e:	4a15      	ldr	r2, [pc, #84]	@ (80107e4 <HAL_TIMEx_MasterConfigSynchronization+0x118>)
 8010790:	4293      	cmp	r3, r2
 8010792:	d10c      	bne.n	80107ae <HAL_TIMEx_MasterConfigSynchronization+0xe2>
  {
    /* Reset the MSM Bit */
    tmpsmcr &= ~TIM_SMCR_MSM;
 8010794:	68bb      	ldr	r3, [r7, #8]
 8010796:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 801079a:	60bb      	str	r3, [r7, #8]
    /* Set master mode */
    tmpsmcr |= sMasterConfig->MasterSlaveMode;
 801079c:	683b      	ldr	r3, [r7, #0]
 801079e:	689b      	ldr	r3, [r3, #8]
 80107a0:	68ba      	ldr	r2, [r7, #8]
 80107a2:	4313      	orrs	r3, r2
 80107a4:	60bb      	str	r3, [r7, #8]

    /* Update TIMx SMCR */
    htim->Instance->SMCR = tmpsmcr;
 80107a6:	687b      	ldr	r3, [r7, #4]
 80107a8:	681b      	ldr	r3, [r3, #0]
 80107aa:	68ba      	ldr	r2, [r7, #8]
 80107ac:	609a      	str	r2, [r3, #8]
  }

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;
 80107ae:	687b      	ldr	r3, [r7, #4]
 80107b0:	2201      	movs	r2, #1
 80107b2:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d

  __HAL_UNLOCK(htim);
 80107b6:	687b      	ldr	r3, [r7, #4]
 80107b8:	2200      	movs	r2, #0
 80107ba:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  return HAL_OK;
 80107be:	2300      	movs	r3, #0
}
 80107c0:	4618      	mov	r0, r3
 80107c2:	3714      	adds	r7, #20
 80107c4:	46bd      	mov	sp, r7
 80107c6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80107ca:	4770      	bx	lr
 80107cc:	40010000 	.word	0x40010000
 80107d0:	40010400 	.word	0x40010400
 80107d4:	40000400 	.word	0x40000400
 80107d8:	40000800 	.word	0x40000800
 80107dc:	40000c00 	.word	0x40000c00
 80107e0:	40001800 	.word	0x40001800
 80107e4:	40014000 	.word	0x40014000

080107e8 <HAL_TIMEx_ConfigBreakDeadTime>:
  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
                                                const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
 80107e8:	b480      	push	{r7}
 80107ea:	b085      	sub	sp, #20
 80107ec:	af00      	add	r7, sp, #0
 80107ee:	6078      	str	r0, [r7, #4]
 80107f0:	6039      	str	r1, [r7, #0]
  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
  uint32_t tmpbdtr = 0U;
 80107f2:	2300      	movs	r3, #0
 80107f4:	60fb      	str	r3, [r7, #12]
#if defined(TIM_BDTR_BKBID)
  assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
#endif /* TIM_BDTR_BKBID */

  /* Check input state */
  __HAL_LOCK(htim);
 80107f6:	687b      	ldr	r3, [r7, #4]
 80107f8:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
 80107fc:	2b01      	cmp	r3, #1
 80107fe:	d101      	bne.n	8010804 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
 8010800:	2302      	movs	r3, #2
 8010802:	e065      	b.n	80108d0 <HAL_TIMEx_ConfigBreakDeadTime+0xe8>
 8010804:	687b      	ldr	r3, [r7, #4]
 8010806:	2201      	movs	r2, #1
 8010808:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
     the OSSI State, the dead time value and the Automatic Output Enable Bit */

  /* Set the BDTR bits */
  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
 801080c:	68fb      	ldr	r3, [r7, #12]
 801080e:	f023 02ff 	bic.w	r2, r3, #255	@ 0xff
 8010812:	683b      	ldr	r3, [r7, #0]
 8010814:	68db      	ldr	r3, [r3, #12]
 8010816:	4313      	orrs	r3, r2
 8010818:	60fb      	str	r3, [r7, #12]
  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
 801081a:	68fb      	ldr	r3, [r7, #12]
 801081c:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
 8010820:	683b      	ldr	r3, [r7, #0]
 8010822:	689b      	ldr	r3, [r3, #8]
 8010824:	4313      	orrs	r3, r2
 8010826:	60fb      	str	r3, [r7, #12]
  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
 8010828:	68fb      	ldr	r3, [r7, #12]
 801082a:	f423 6280 	bic.w	r2, r3, #1024	@ 0x400
 801082e:	683b      	ldr	r3, [r7, #0]
 8010830:	685b      	ldr	r3, [r3, #4]
 8010832:	4313      	orrs	r3, r2
 8010834:	60fb      	str	r3, [r7, #12]
  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
 8010836:	68fb      	ldr	r3, [r7, #12]
 8010838:	f423 6200 	bic.w	r2, r3, #2048	@ 0x800
 801083c:	683b      	ldr	r3, [r7, #0]
 801083e:	681b      	ldr	r3, [r3, #0]
 8010840:	4313      	orrs	r3, r2
 8010842:	60fb      	str	r3, [r7, #12]
  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
 8010844:	68fb      	ldr	r3, [r7, #12]
 8010846:	f423 5280 	bic.w	r2, r3, #4096	@ 0x1000
 801084a:	683b      	ldr	r3, [r7, #0]
 801084c:	691b      	ldr	r3, [r3, #16]
 801084e:	4313      	orrs	r3, r2
 8010850:	60fb      	str	r3, [r7, #12]
  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
 8010852:	68fb      	ldr	r3, [r7, #12]
 8010854:	f423 5200 	bic.w	r2, r3, #8192	@ 0x2000
 8010858:	683b      	ldr	r3, [r7, #0]
 801085a:	695b      	ldr	r3, [r3, #20]
 801085c:	4313      	orrs	r3, r2
 801085e:	60fb      	str	r3, [r7, #12]
  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
 8010860:	68fb      	ldr	r3, [r7, #12]
 8010862:	f423 4280 	bic.w	r2, r3, #16384	@ 0x4000
 8010866:	683b      	ldr	r3, [r7, #0]
 8010868:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 801086a:	4313      	orrs	r3, r2
 801086c:	60fb      	str	r3, [r7, #12]
  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
 801086e:	68fb      	ldr	r3, [r7, #12]
 8010870:	f423 2270 	bic.w	r2, r3, #983040	@ 0xf0000
 8010874:	683b      	ldr	r3, [r7, #0]
 8010876:	699b      	ldr	r3, [r3, #24]
 8010878:	041b      	lsls	r3, r3, #16
 801087a:	4313      	orrs	r3, r2
 801087c:	60fb      	str	r3, [r7, #12]
#if defined(TIM_BDTR_BKBID)
  MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
#endif /* TIM_BDTR_BKBID */

  if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
 801087e:	687b      	ldr	r3, [r7, #4]
 8010880:	681b      	ldr	r3, [r3, #0]
 8010882:	4a16      	ldr	r2, [pc, #88]	@ (80108dc <HAL_TIMEx_ConfigBreakDeadTime+0xf4>)
 8010884:	4293      	cmp	r3, r2
 8010886:	d004      	beq.n	8010892 <HAL_TIMEx_ConfigBreakDeadTime+0xaa>
 8010888:	687b      	ldr	r3, [r7, #4]
 801088a:	681b      	ldr	r3, [r3, #0]
 801088c:	4a14      	ldr	r2, [pc, #80]	@ (80108e0 <HAL_TIMEx_ConfigBreakDeadTime+0xf8>)
 801088e:	4293      	cmp	r3, r2
 8010890:	d115      	bne.n	80108be <HAL_TIMEx_ConfigBreakDeadTime+0xd6>
#if defined(TIM_BDTR_BKBID)
    assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
#endif /* TIM_BDTR_BKBID */

    /* Set the BREAK2 input related BDTR bits */
    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
 8010892:	68fb      	ldr	r3, [r7, #12]
 8010894:	f423 0270 	bic.w	r2, r3, #15728640	@ 0xf00000
 8010898:	683b      	ldr	r3, [r7, #0]
 801089a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 801089c:	051b      	lsls	r3, r3, #20
 801089e:	4313      	orrs	r3, r2
 80108a0:	60fb      	str	r3, [r7, #12]
    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
 80108a2:	68fb      	ldr	r3, [r7, #12]
 80108a4:	f023 7280 	bic.w	r2, r3, #16777216	@ 0x1000000
 80108a8:	683b      	ldr	r3, [r7, #0]
 80108aa:	69db      	ldr	r3, [r3, #28]
 80108ac:	4313      	orrs	r3, r2
 80108ae:	60fb      	str	r3, [r7, #12]
    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
 80108b0:	68fb      	ldr	r3, [r7, #12]
 80108b2:	f023 7200 	bic.w	r2, r3, #33554432	@ 0x2000000
 80108b6:	683b      	ldr	r3, [r7, #0]
 80108b8:	6a1b      	ldr	r3, [r3, #32]
 80108ba:	4313      	orrs	r3, r2
 80108bc:	60fb      	str	r3, [r7, #12]
    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
#endif /* TIM_BDTR_BKBID */
  }

  /* Set TIMx_BDTR */
  htim->Instance->BDTR = tmpbdtr;
 80108be:	687b      	ldr	r3, [r7, #4]
 80108c0:	681b      	ldr	r3, [r3, #0]
 80108c2:	68fa      	ldr	r2, [r7, #12]
 80108c4:	645a      	str	r2, [r3, #68]	@ 0x44

  __HAL_UNLOCK(htim);
 80108c6:	687b      	ldr	r3, [r7, #4]
 80108c8:	2200      	movs	r2, #0
 80108ca:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c

  return HAL_OK;
 80108ce:	2300      	movs	r3, #0
}
 80108d0:	4618      	mov	r0, r3
 80108d2:	3714      	adds	r7, #20
 80108d4:	46bd      	mov	sp, r7
 80108d6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80108da:	4770      	bx	lr
 80108dc:	40010000 	.word	0x40010000
 80108e0:	40010400 	.word	0x40010400

080108e4 <HAL_TIMEx_CommutCallback>:
  * @brief  Commutation callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
 80108e4:	b480      	push	{r7}
 80108e6:	b083      	sub	sp, #12
 80108e8:	af00      	add	r7, sp, #0
 80108ea:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_CommutCallback could be implemented in the user file
   */
}
 80108ec:	bf00      	nop
 80108ee:	370c      	adds	r7, #12
 80108f0:	46bd      	mov	sp, r7
 80108f2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80108f6:	4770      	bx	lr

080108f8 <HAL_TIMEx_BreakCallback>:
  * @brief  Break detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 80108f8:	b480      	push	{r7}
 80108fa:	b083      	sub	sp, #12
 80108fc:	af00      	add	r7, sp, #0
 80108fe:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_BreakCallback could be implemented in the user file
   */
}
 8010900:	bf00      	nop
 8010902:	370c      	adds	r7, #12
 8010904:	46bd      	mov	sp, r7
 8010906:	f85d 7b04 	ldr.w	r7, [sp], #4
 801090a:	4770      	bx	lr

0801090c <HAL_TIMEx_Break2Callback>:
  * @brief  Break2 detection callback in non blocking mode
  * @param  htim: TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
 801090c:	b480      	push	{r7}
 801090e:	b083      	sub	sp, #12
 8010910:	af00      	add	r7, sp, #0
 8010912:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_TIMEx_Break2Callback could be implemented in the user file
   */
}
 8010914:	bf00      	nop
 8010916:	370c      	adds	r7, #12
 8010918:	46bd      	mov	sp, r7
 801091a:	f85d 7b04 	ldr.w	r7, [sp], #4
 801091e:	4770      	bx	lr

08010920 <HAL_UART_Init>:
  *        parameters in the UART_InitTypeDef and initialize the associated handle.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
 8010920:	b580      	push	{r7, lr}
 8010922:	b082      	sub	sp, #8
 8010924:	af00      	add	r7, sp, #0
 8010926:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 8010928:	687b      	ldr	r3, [r7, #4]
 801092a:	2b00      	cmp	r3, #0
 801092c:	d101      	bne.n	8010932 <HAL_UART_Init+0x12>
  {
    return HAL_ERROR;
 801092e:	2301      	movs	r3, #1
 8010930:	e042      	b.n	80109b8 <HAL_UART_Init+0x98>
  {
    /* Check the parameters */
    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
  }

  if (huart->gState == HAL_UART_STATE_RESET)
 8010932:	687b      	ldr	r3, [r7, #4]
 8010934:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8010938:	2b00      	cmp	r3, #0
 801093a:	d106      	bne.n	801094a <HAL_UART_Init+0x2a>
  {
    /* Allocate lock resource and initialize it */
    huart->Lock = HAL_UNLOCKED;
 801093c:	687b      	ldr	r3, [r7, #4]
 801093e:	2200      	movs	r2, #0
 8010940:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

    /* Init the low level hardware */
    huart->MspInitCallback(huart);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_UART_MspInit(huart);
 8010944:	6878      	ldr	r0, [r7, #4]
 8010946:	f7f3 f96b 	bl	8003c20 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  }

  huart->gState = HAL_UART_STATE_BUSY;
 801094a:	687b      	ldr	r3, [r7, #4]
 801094c:	2224      	movs	r2, #36	@ 0x24
 801094e:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  __HAL_UART_DISABLE(huart);
 8010952:	687b      	ldr	r3, [r7, #4]
 8010954:	681b      	ldr	r3, [r3, #0]
 8010956:	681a      	ldr	r2, [r3, #0]
 8010958:	687b      	ldr	r3, [r7, #4]
 801095a:	681b      	ldr	r3, [r3, #0]
 801095c:	f022 0201 	bic.w	r2, r2, #1
 8010960:	601a      	str	r2, [r3, #0]

  /* Perform advanced settings configuration */
  /* For some items, configuration requires to be done prior TE and RE bits are set */
  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
 8010962:	687b      	ldr	r3, [r7, #4]
 8010964:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8010966:	2b00      	cmp	r3, #0
 8010968:	d002      	beq.n	8010970 <HAL_UART_Init+0x50>
  {
    UART_AdvFeatureConfig(huart);
 801096a:	6878      	ldr	r0, [r7, #4]
 801096c:	f001 fa76 	bl	8011e5c <UART_AdvFeatureConfig>
  }

  /* Set the UART Communication parameters */
  if (UART_SetConfig(huart) == HAL_ERROR)
 8010970:	6878      	ldr	r0, [r7, #4]
 8010972:	f000 fd0b 	bl	801138c <UART_SetConfig>
 8010976:	4603      	mov	r3, r0
 8010978:	2b01      	cmp	r3, #1
 801097a:	d101      	bne.n	8010980 <HAL_UART_Init+0x60>
  {
    return HAL_ERROR;
 801097c:	2301      	movs	r3, #1
 801097e:	e01b      	b.n	80109b8 <HAL_UART_Init+0x98>
  }

  /* In asynchronous mode, the following bits must be kept cleared:
  - LINEN and CLKEN bits in the USART_CR2 register,
  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8010980:	687b      	ldr	r3, [r7, #4]
 8010982:	681b      	ldr	r3, [r3, #0]
 8010984:	685a      	ldr	r2, [r3, #4]
 8010986:	687b      	ldr	r3, [r7, #4]
 8010988:	681b      	ldr	r3, [r3, #0]
 801098a:	f422 4290 	bic.w	r2, r2, #18432	@ 0x4800
 801098e:	605a      	str	r2, [r3, #4]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8010990:	687b      	ldr	r3, [r7, #4]
 8010992:	681b      	ldr	r3, [r3, #0]
 8010994:	689a      	ldr	r2, [r3, #8]
 8010996:	687b      	ldr	r3, [r7, #4]
 8010998:	681b      	ldr	r3, [r3, #0]
 801099a:	f022 022a 	bic.w	r2, r2, #42	@ 0x2a
 801099e:	609a      	str	r2, [r3, #8]

  __HAL_UART_ENABLE(huart);
 80109a0:	687b      	ldr	r3, [r7, #4]
 80109a2:	681b      	ldr	r3, [r3, #0]
 80109a4:	681a      	ldr	r2, [r3, #0]
 80109a6:	687b      	ldr	r3, [r7, #4]
 80109a8:	681b      	ldr	r3, [r3, #0]
 80109aa:	f042 0201 	orr.w	r2, r2, #1
 80109ae:	601a      	str	r2, [r3, #0]

  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
  return (UART_CheckIdleState(huart));
 80109b0:	6878      	ldr	r0, [r7, #4]
 80109b2:	f001 faf5 	bl	8011fa0 <UART_CheckIdleState>
 80109b6:	4603      	mov	r3, r0
}
 80109b8:	4618      	mov	r0, r3
 80109ba:	3708      	adds	r7, #8
 80109bc:	46bd      	mov	sp, r7
 80109be:	bd80      	pop	{r7, pc}

080109c0 <HAL_UART_Transmit>:
  * @param Size    Amount of data elements (u8 or u16) to be sent.
  * @param Timeout Timeout duration.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
 80109c0:	b580      	push	{r7, lr}
 80109c2:	b08a      	sub	sp, #40	@ 0x28
 80109c4:	af02      	add	r7, sp, #8
 80109c6:	60f8      	str	r0, [r7, #12]
 80109c8:	60b9      	str	r1, [r7, #8]
 80109ca:	603b      	str	r3, [r7, #0]
 80109cc:	4613      	mov	r3, r2
 80109ce:	80fb      	strh	r3, [r7, #6]
  const uint8_t  *pdata8bits;
  const uint16_t *pdata16bits;
  uint32_t tickstart;

  /* Check that a Tx process is not already ongoing */
  if (huart->gState == HAL_UART_STATE_READY)
 80109d0:	68fb      	ldr	r3, [r7, #12]
 80109d2:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80109d6:	2b20      	cmp	r3, #32
 80109d8:	d17b      	bne.n	8010ad2 <HAL_UART_Transmit+0x112>
  {
    if ((pData == NULL) || (Size == 0U))
 80109da:	68bb      	ldr	r3, [r7, #8]
 80109dc:	2b00      	cmp	r3, #0
 80109de:	d002      	beq.n	80109e6 <HAL_UART_Transmit+0x26>
 80109e0:	88fb      	ldrh	r3, [r7, #6]
 80109e2:	2b00      	cmp	r3, #0
 80109e4:	d101      	bne.n	80109ea <HAL_UART_Transmit+0x2a>
    {
      return  HAL_ERROR;
 80109e6:	2301      	movs	r3, #1
 80109e8:	e074      	b.n	8010ad4 <HAL_UART_Transmit+0x114>
    }

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 80109ea:	68fb      	ldr	r3, [r7, #12]
 80109ec:	2200      	movs	r2, #0
 80109ee:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    huart->gState = HAL_UART_STATE_BUSY_TX;
 80109f2:	68fb      	ldr	r3, [r7, #12]
 80109f4:	2221      	movs	r2, #33	@ 0x21
 80109f6:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

    /* Init tickstart for timeout management */
    tickstart = HAL_GetTick();
 80109fa:	f7f4 fd1f 	bl	800543c <HAL_GetTick>
 80109fe:	6178      	str	r0, [r7, #20]

    huart->TxXferSize  = Size;
 8010a00:	68fb      	ldr	r3, [r7, #12]
 8010a02:	88fa      	ldrh	r2, [r7, #6]
 8010a04:	f8a3 2054 	strh.w	r2, [r3, #84]	@ 0x54
    huart->TxXferCount = Size;
 8010a08:	68fb      	ldr	r3, [r7, #12]
 8010a0a:	88fa      	ldrh	r2, [r7, #6]
 8010a0c:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56

    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 8010a10:	68fb      	ldr	r3, [r7, #12]
 8010a12:	689b      	ldr	r3, [r3, #8]
 8010a14:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 8010a18:	d108      	bne.n	8010a2c <HAL_UART_Transmit+0x6c>
 8010a1a:	68fb      	ldr	r3, [r7, #12]
 8010a1c:	691b      	ldr	r3, [r3, #16]
 8010a1e:	2b00      	cmp	r3, #0
 8010a20:	d104      	bne.n	8010a2c <HAL_UART_Transmit+0x6c>
    {
      pdata8bits  = NULL;
 8010a22:	2300      	movs	r3, #0
 8010a24:	61fb      	str	r3, [r7, #28]
      pdata16bits = (const uint16_t *) pData;
 8010a26:	68bb      	ldr	r3, [r7, #8]
 8010a28:	61bb      	str	r3, [r7, #24]
 8010a2a:	e003      	b.n	8010a34 <HAL_UART_Transmit+0x74>
    }
    else
    {
      pdata8bits  = pData;
 8010a2c:	68bb      	ldr	r3, [r7, #8]
 8010a2e:	61fb      	str	r3, [r7, #28]
      pdata16bits = NULL;
 8010a30:	2300      	movs	r3, #0
 8010a32:	61bb      	str	r3, [r7, #24]
    }

    while (huart->TxXferCount > 0U)
 8010a34:	e030      	b.n	8010a98 <HAL_UART_Transmit+0xd8>
    {
      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 8010a36:	683b      	ldr	r3, [r7, #0]
 8010a38:	9300      	str	r3, [sp, #0]
 8010a3a:	697b      	ldr	r3, [r7, #20]
 8010a3c:	2200      	movs	r2, #0
 8010a3e:	2180      	movs	r1, #128	@ 0x80
 8010a40:	68f8      	ldr	r0, [r7, #12]
 8010a42:	f001 fb57 	bl	80120f4 <UART_WaitOnFlagUntilTimeout>
 8010a46:	4603      	mov	r3, r0
 8010a48:	2b00      	cmp	r3, #0
 8010a4a:	d005      	beq.n	8010a58 <HAL_UART_Transmit+0x98>
      {

        huart->gState = HAL_UART_STATE_READY;
 8010a4c:	68fb      	ldr	r3, [r7, #12]
 8010a4e:	2220      	movs	r2, #32
 8010a50:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

        return HAL_TIMEOUT;
 8010a54:	2303      	movs	r3, #3
 8010a56:	e03d      	b.n	8010ad4 <HAL_UART_Transmit+0x114>
      }
      if (pdata8bits == NULL)
 8010a58:	69fb      	ldr	r3, [r7, #28]
 8010a5a:	2b00      	cmp	r3, #0
 8010a5c:	d10b      	bne.n	8010a76 <HAL_UART_Transmit+0xb6>
      {
        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
 8010a5e:	69bb      	ldr	r3, [r7, #24]
 8010a60:	881b      	ldrh	r3, [r3, #0]
 8010a62:	461a      	mov	r2, r3
 8010a64:	68fb      	ldr	r3, [r7, #12]
 8010a66:	681b      	ldr	r3, [r3, #0]
 8010a68:	f3c2 0208 	ubfx	r2, r2, #0, #9
 8010a6c:	629a      	str	r2, [r3, #40]	@ 0x28
        pdata16bits++;
 8010a6e:	69bb      	ldr	r3, [r7, #24]
 8010a70:	3302      	adds	r3, #2
 8010a72:	61bb      	str	r3, [r7, #24]
 8010a74:	e007      	b.n	8010a86 <HAL_UART_Transmit+0xc6>
      }
      else
      {
        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
 8010a76:	69fb      	ldr	r3, [r7, #28]
 8010a78:	781a      	ldrb	r2, [r3, #0]
 8010a7a:	68fb      	ldr	r3, [r7, #12]
 8010a7c:	681b      	ldr	r3, [r3, #0]
 8010a7e:	629a      	str	r2, [r3, #40]	@ 0x28
        pdata8bits++;
 8010a80:	69fb      	ldr	r3, [r7, #28]
 8010a82:	3301      	adds	r3, #1
 8010a84:	61fb      	str	r3, [r7, #28]
      }
      huart->TxXferCount--;
 8010a86:	68fb      	ldr	r3, [r7, #12]
 8010a88:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 8010a8c:	b29b      	uxth	r3, r3
 8010a8e:	3b01      	subs	r3, #1
 8010a90:	b29a      	uxth	r2, r3
 8010a92:	68fb      	ldr	r3, [r7, #12]
 8010a94:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
    while (huart->TxXferCount > 0U)
 8010a98:	68fb      	ldr	r3, [r7, #12]
 8010a9a:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 8010a9e:	b29b      	uxth	r3, r3
 8010aa0:	2b00      	cmp	r3, #0
 8010aa2:	d1c8      	bne.n	8010a36 <HAL_UART_Transmit+0x76>
    }

    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
 8010aa4:	683b      	ldr	r3, [r7, #0]
 8010aa6:	9300      	str	r3, [sp, #0]
 8010aa8:	697b      	ldr	r3, [r7, #20]
 8010aaa:	2200      	movs	r2, #0
 8010aac:	2140      	movs	r1, #64	@ 0x40
 8010aae:	68f8      	ldr	r0, [r7, #12]
 8010ab0:	f001 fb20 	bl	80120f4 <UART_WaitOnFlagUntilTimeout>
 8010ab4:	4603      	mov	r3, r0
 8010ab6:	2b00      	cmp	r3, #0
 8010ab8:	d005      	beq.n	8010ac6 <HAL_UART_Transmit+0x106>
    {
      huart->gState = HAL_UART_STATE_READY;
 8010aba:	68fb      	ldr	r3, [r7, #12]
 8010abc:	2220      	movs	r2, #32
 8010abe:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

      return HAL_TIMEOUT;
 8010ac2:	2303      	movs	r3, #3
 8010ac4:	e006      	b.n	8010ad4 <HAL_UART_Transmit+0x114>
    }

    /* At end of Tx process, restore huart->gState to Ready */
    huart->gState = HAL_UART_STATE_READY;
 8010ac6:	68fb      	ldr	r3, [r7, #12]
 8010ac8:	2220      	movs	r2, #32
 8010aca:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

    return HAL_OK;
 8010ace:	2300      	movs	r3, #0
 8010ad0:	e000      	b.n	8010ad4 <HAL_UART_Transmit+0x114>
  }
  else
  {
    return HAL_BUSY;
 8010ad2:	2302      	movs	r3, #2
  }
}
 8010ad4:	4618      	mov	r0, r3
 8010ad6:	3720      	adds	r7, #32
 8010ad8:	46bd      	mov	sp, r7
 8010ada:	bd80      	pop	{r7, pc}

08010adc <HAL_UART_Transmit_IT>:
  * @param pData Pointer to data buffer (u8 or u16 data elements).
  * @param Size  Amount of data elements (u8 or u16) to be sent.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
 8010adc:	b480      	push	{r7}
 8010ade:	b091      	sub	sp, #68	@ 0x44
 8010ae0:	af00      	add	r7, sp, #0
 8010ae2:	60f8      	str	r0, [r7, #12]
 8010ae4:	60b9      	str	r1, [r7, #8]
 8010ae6:	4613      	mov	r3, r2
 8010ae8:	80fb      	strh	r3, [r7, #6]
  /* Check that a Tx process is not already ongoing */
  if (huart->gState == HAL_UART_STATE_READY)
 8010aea:	68fb      	ldr	r3, [r7, #12]
 8010aec:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8010af0:	2b20      	cmp	r3, #32
 8010af2:	d178      	bne.n	8010be6 <HAL_UART_Transmit_IT+0x10a>
  {
    if ((pData == NULL) || (Size == 0U))
 8010af4:	68bb      	ldr	r3, [r7, #8]
 8010af6:	2b00      	cmp	r3, #0
 8010af8:	d002      	beq.n	8010b00 <HAL_UART_Transmit_IT+0x24>
 8010afa:	88fb      	ldrh	r3, [r7, #6]
 8010afc:	2b00      	cmp	r3, #0
 8010afe:	d101      	bne.n	8010b04 <HAL_UART_Transmit_IT+0x28>
    {
      return HAL_ERROR;
 8010b00:	2301      	movs	r3, #1
 8010b02:	e071      	b.n	8010be8 <HAL_UART_Transmit_IT+0x10c>
    }

    huart->pTxBuffPtr  = pData;
 8010b04:	68fb      	ldr	r3, [r7, #12]
 8010b06:	68ba      	ldr	r2, [r7, #8]
 8010b08:	651a      	str	r2, [r3, #80]	@ 0x50
    huart->TxXferSize  = Size;
 8010b0a:	68fb      	ldr	r3, [r7, #12]
 8010b0c:	88fa      	ldrh	r2, [r7, #6]
 8010b0e:	f8a3 2054 	strh.w	r2, [r3, #84]	@ 0x54
    huart->TxXferCount = Size;
 8010b12:	68fb      	ldr	r3, [r7, #12]
 8010b14:	88fa      	ldrh	r2, [r7, #6]
 8010b16:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
    huart->TxISR       = NULL;
 8010b1a:	68fb      	ldr	r3, [r7, #12]
 8010b1c:	2200      	movs	r2, #0
 8010b1e:	679a      	str	r2, [r3, #120]	@ 0x78

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8010b20:	68fb      	ldr	r3, [r7, #12]
 8010b22:	2200      	movs	r2, #0
 8010b24:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8010b28:	68fb      	ldr	r3, [r7, #12]
 8010b2a:	2221      	movs	r2, #33	@ 0x21
 8010b2c:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

    /* Configure Tx interrupt processing */
    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
 8010b30:	68fb      	ldr	r3, [r7, #12]
 8010b32:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8010b34:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 8010b38:	d12a      	bne.n	8010b90 <HAL_UART_Transmit_IT+0xb4>
    {
      /* Set the Tx ISR function pointer according to the data word length */
      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 8010b3a:	68fb      	ldr	r3, [r7, #12]
 8010b3c:	689b      	ldr	r3, [r3, #8]
 8010b3e:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 8010b42:	d107      	bne.n	8010b54 <HAL_UART_Transmit_IT+0x78>
 8010b44:	68fb      	ldr	r3, [r7, #12]
 8010b46:	691b      	ldr	r3, [r3, #16]
 8010b48:	2b00      	cmp	r3, #0
 8010b4a:	d103      	bne.n	8010b54 <HAL_UART_Transmit_IT+0x78>
      {
        huart->TxISR = UART_TxISR_16BIT_FIFOEN;
 8010b4c:	68fb      	ldr	r3, [r7, #12]
 8010b4e:	4a29      	ldr	r2, [pc, #164]	@ (8010bf4 <HAL_UART_Transmit_IT+0x118>)
 8010b50:	679a      	str	r2, [r3, #120]	@ 0x78
 8010b52:	e002      	b.n	8010b5a <HAL_UART_Transmit_IT+0x7e>
      }
      else
      {
        huart->TxISR = UART_TxISR_8BIT_FIFOEN;
 8010b54:	68fb      	ldr	r3, [r7, #12]
 8010b56:	4a28      	ldr	r2, [pc, #160]	@ (8010bf8 <HAL_UART_Transmit_IT+0x11c>)
 8010b58:	679a      	str	r2, [r3, #120]	@ 0x78
      }

      /* Enable the TX FIFO threshold interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
 8010b5a:	68fb      	ldr	r3, [r7, #12]
 8010b5c:	681b      	ldr	r3, [r3, #0]
 8010b5e:	3308      	adds	r3, #8
 8010b60:	62bb      	str	r3, [r7, #40]	@ 0x28
 */
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
    uint32_t result;

   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8010b62:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8010b64:	e853 3f00 	ldrex	r3, [r3]
 8010b68:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 8010b6a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8010b6c:	f443 0300 	orr.w	r3, r3, #8388608	@ 0x800000
 8010b70:	63bb      	str	r3, [r7, #56]	@ 0x38
 8010b72:	68fb      	ldr	r3, [r7, #12]
 8010b74:	681b      	ldr	r3, [r3, #0]
 8010b76:	3308      	adds	r3, #8
 8010b78:	6bba      	ldr	r2, [r7, #56]	@ 0x38
 8010b7a:	637a      	str	r2, [r7, #52]	@ 0x34
 8010b7c:	633b      	str	r3, [r7, #48]	@ 0x30
 */
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
   uint32_t result;

   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8010b7e:	6b39      	ldr	r1, [r7, #48]	@ 0x30
 8010b80:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 8010b82:	e841 2300 	strex	r3, r2, [r1]
 8010b86:	62fb      	str	r3, [r7, #44]	@ 0x2c
   return(result);
 8010b88:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8010b8a:	2b00      	cmp	r3, #0
 8010b8c:	d1e5      	bne.n	8010b5a <HAL_UART_Transmit_IT+0x7e>
 8010b8e:	e028      	b.n	8010be2 <HAL_UART_Transmit_IT+0x106>
    }
    else
    {
      /* Set the Tx ISR function pointer according to the data word length */
      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 8010b90:	68fb      	ldr	r3, [r7, #12]
 8010b92:	689b      	ldr	r3, [r3, #8]
 8010b94:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 8010b98:	d107      	bne.n	8010baa <HAL_UART_Transmit_IT+0xce>
 8010b9a:	68fb      	ldr	r3, [r7, #12]
 8010b9c:	691b      	ldr	r3, [r3, #16]
 8010b9e:	2b00      	cmp	r3, #0
 8010ba0:	d103      	bne.n	8010baa <HAL_UART_Transmit_IT+0xce>
      {
        huart->TxISR = UART_TxISR_16BIT;
 8010ba2:	68fb      	ldr	r3, [r7, #12]
 8010ba4:	4a15      	ldr	r2, [pc, #84]	@ (8010bfc <HAL_UART_Transmit_IT+0x120>)
 8010ba6:	679a      	str	r2, [r3, #120]	@ 0x78
 8010ba8:	e002      	b.n	8010bb0 <HAL_UART_Transmit_IT+0xd4>
      }
      else
      {
        huart->TxISR = UART_TxISR_8BIT;
 8010baa:	68fb      	ldr	r3, [r7, #12]
 8010bac:	4a14      	ldr	r2, [pc, #80]	@ (8010c00 <HAL_UART_Transmit_IT+0x124>)
 8010bae:	679a      	str	r2, [r3, #120]	@ 0x78
      }

      /* Enable the Transmit Data Register Empty interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
 8010bb0:	68fb      	ldr	r3, [r7, #12]
 8010bb2:	681b      	ldr	r3, [r3, #0]
 8010bb4:	617b      	str	r3, [r7, #20]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8010bb6:	697b      	ldr	r3, [r7, #20]
 8010bb8:	e853 3f00 	ldrex	r3, [r3]
 8010bbc:	613b      	str	r3, [r7, #16]
   return(result);
 8010bbe:	693b      	ldr	r3, [r7, #16]
 8010bc0:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 8010bc4:	63fb      	str	r3, [r7, #60]	@ 0x3c
 8010bc6:	68fb      	ldr	r3, [r7, #12]
 8010bc8:	681b      	ldr	r3, [r3, #0]
 8010bca:	461a      	mov	r2, r3
 8010bcc:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8010bce:	623b      	str	r3, [r7, #32]
 8010bd0:	61fa      	str	r2, [r7, #28]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8010bd2:	69f9      	ldr	r1, [r7, #28]
 8010bd4:	6a3a      	ldr	r2, [r7, #32]
 8010bd6:	e841 2300 	strex	r3, r2, [r1]
 8010bda:	61bb      	str	r3, [r7, #24]
   return(result);
 8010bdc:	69bb      	ldr	r3, [r7, #24]
 8010bde:	2b00      	cmp	r3, #0
 8010be0:	d1e6      	bne.n	8010bb0 <HAL_UART_Transmit_IT+0xd4>
    }

    return HAL_OK;
 8010be2:	2300      	movs	r3, #0
 8010be4:	e000      	b.n	8010be8 <HAL_UART_Transmit_IT+0x10c>
  }
  else
  {
    return HAL_BUSY;
 8010be6:	2302      	movs	r3, #2
  }
}
 8010be8:	4618      	mov	r0, r3
 8010bea:	3744      	adds	r7, #68	@ 0x44
 8010bec:	46bd      	mov	sp, r7
 8010bee:	f85d 7b04 	ldr.w	r7, [sp], #4
 8010bf2:	4770      	bx	lr
 8010bf4:	08012767 	.word	0x08012767
 8010bf8:	08012687 	.word	0x08012687
 8010bfc:	080125c5 	.word	0x080125c5
 8010c00:	0801250d 	.word	0x0801250d

08010c04 <HAL_UART_IRQHandler>:
  * @brief Handle UART interrupt request.
  * @param huart UART handle.
  * @retval None
  */
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
 8010c04:	b580      	push	{r7, lr}
 8010c06:	b0ba      	sub	sp, #232	@ 0xe8
 8010c08:	af00      	add	r7, sp, #0
 8010c0a:	6078      	str	r0, [r7, #4]
  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
 8010c0c:	687b      	ldr	r3, [r7, #4]
 8010c0e:	681b      	ldr	r3, [r3, #0]
 8010c10:	69db      	ldr	r3, [r3, #28]
 8010c12:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
 8010c16:	687b      	ldr	r3, [r7, #4]
 8010c18:	681b      	ldr	r3, [r3, #0]
 8010c1a:	681b      	ldr	r3, [r3, #0]
 8010c1c:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
 8010c20:	687b      	ldr	r3, [r7, #4]
 8010c22:	681b      	ldr	r3, [r3, #0]
 8010c24:	689b      	ldr	r3, [r3, #8]
 8010c26:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc

  uint32_t errorflags;
  uint32_t errorcode;

  /* If no error occurs */
  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
 8010c2a:	f8d7 20e4 	ldr.w	r2, [r7, #228]	@ 0xe4
 8010c2e:	f640 030f 	movw	r3, #2063	@ 0x80f
 8010c32:	4013      	ands	r3, r2
 8010c34:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
  if (errorflags == 0U)
 8010c38:	f8d7 30d8 	ldr.w	r3, [r7, #216]	@ 0xd8
 8010c3c:	2b00      	cmp	r3, #0
 8010c3e:	d11b      	bne.n	8010c78 <HAL_UART_IRQHandler+0x74>
  {
    /* UART in mode Receiver ---------------------------------------------------*/
    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
 8010c40:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8010c44:	f003 0320 	and.w	r3, r3, #32
 8010c48:	2b00      	cmp	r3, #0
 8010c4a:	d015      	beq.n	8010c78 <HAL_UART_IRQHandler+0x74>
        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
 8010c4c:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 8010c50:	f003 0320 	and.w	r3, r3, #32
 8010c54:	2b00      	cmp	r3, #0
 8010c56:	d105      	bne.n	8010c64 <HAL_UART_IRQHandler+0x60>
            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
 8010c58:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 8010c5c:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8010c60:	2b00      	cmp	r3, #0
 8010c62:	d009      	beq.n	8010c78 <HAL_UART_IRQHandler+0x74>
    {
      if (huart->RxISR != NULL)
 8010c64:	687b      	ldr	r3, [r7, #4]
 8010c66:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 8010c68:	2b00      	cmp	r3, #0
 8010c6a:	f000 8377 	beq.w	801135c <HAL_UART_IRQHandler+0x758>
      {
        huart->RxISR(huart);
 8010c6e:	687b      	ldr	r3, [r7, #4]
 8010c70:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 8010c72:	6878      	ldr	r0, [r7, #4]
 8010c74:	4798      	blx	r3
      }
      return;
 8010c76:	e371      	b.n	801135c <HAL_UART_IRQHandler+0x758>
    }
  }

  /* If some errors occur */
  if ((errorflags != 0U)
 8010c78:	f8d7 30d8 	ldr.w	r3, [r7, #216]	@ 0xd8
 8010c7c:	2b00      	cmp	r3, #0
 8010c7e:	f000 8123 	beq.w	8010ec8 <HAL_UART_IRQHandler+0x2c4>
      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
 8010c82:	f8d7 20dc 	ldr.w	r2, [r7, #220]	@ 0xdc
 8010c86:	4b8d      	ldr	r3, [pc, #564]	@ (8010ebc <HAL_UART_IRQHandler+0x2b8>)
 8010c88:	4013      	ands	r3, r2
 8010c8a:	2b00      	cmp	r3, #0
 8010c8c:	d106      	bne.n	8010c9c <HAL_UART_IRQHandler+0x98>
           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
 8010c8e:	f8d7 20e0 	ldr.w	r2, [r7, #224]	@ 0xe0
 8010c92:	4b8b      	ldr	r3, [pc, #556]	@ (8010ec0 <HAL_UART_IRQHandler+0x2bc>)
 8010c94:	4013      	ands	r3, r2
 8010c96:	2b00      	cmp	r3, #0
 8010c98:	f000 8116 	beq.w	8010ec8 <HAL_UART_IRQHandler+0x2c4>
  {
    /* UART parity error interrupt occurred -------------------------------------*/
    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
 8010c9c:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8010ca0:	f003 0301 	and.w	r3, r3, #1
 8010ca4:	2b00      	cmp	r3, #0
 8010ca6:	d011      	beq.n	8010ccc <HAL_UART_IRQHandler+0xc8>
 8010ca8:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 8010cac:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8010cb0:	2b00      	cmp	r3, #0
 8010cb2:	d00b      	beq.n	8010ccc <HAL_UART_IRQHandler+0xc8>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
 8010cb4:	687b      	ldr	r3, [r7, #4]
 8010cb6:	681b      	ldr	r3, [r3, #0]
 8010cb8:	2201      	movs	r2, #1
 8010cba:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_PE;
 8010cbc:	687b      	ldr	r3, [r7, #4]
 8010cbe:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8010cc2:	f043 0201 	orr.w	r2, r3, #1
 8010cc6:	687b      	ldr	r3, [r7, #4]
 8010cc8:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    }

    /* UART frame error interrupt occurred --------------------------------------*/
    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 8010ccc:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8010cd0:	f003 0302 	and.w	r3, r3, #2
 8010cd4:	2b00      	cmp	r3, #0
 8010cd6:	d011      	beq.n	8010cfc <HAL_UART_IRQHandler+0xf8>
 8010cd8:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 8010cdc:	f003 0301 	and.w	r3, r3, #1
 8010ce0:	2b00      	cmp	r3, #0
 8010ce2:	d00b      	beq.n	8010cfc <HAL_UART_IRQHandler+0xf8>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
 8010ce4:	687b      	ldr	r3, [r7, #4]
 8010ce6:	681b      	ldr	r3, [r3, #0]
 8010ce8:	2202      	movs	r2, #2
 8010cea:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_FE;
 8010cec:	687b      	ldr	r3, [r7, #4]
 8010cee:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8010cf2:	f043 0204 	orr.w	r2, r3, #4
 8010cf6:	687b      	ldr	r3, [r7, #4]
 8010cf8:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    }

    /* UART noise error interrupt occurred --------------------------------------*/
    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 8010cfc:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8010d00:	f003 0304 	and.w	r3, r3, #4
 8010d04:	2b00      	cmp	r3, #0
 8010d06:	d011      	beq.n	8010d2c <HAL_UART_IRQHandler+0x128>
 8010d08:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 8010d0c:	f003 0301 	and.w	r3, r3, #1
 8010d10:	2b00      	cmp	r3, #0
 8010d12:	d00b      	beq.n	8010d2c <HAL_UART_IRQHandler+0x128>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
 8010d14:	687b      	ldr	r3, [r7, #4]
 8010d16:	681b      	ldr	r3, [r3, #0]
 8010d18:	2204      	movs	r2, #4
 8010d1a:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_NE;
 8010d1c:	687b      	ldr	r3, [r7, #4]
 8010d1e:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8010d22:	f043 0202 	orr.w	r2, r3, #2
 8010d26:	687b      	ldr	r3, [r7, #4]
 8010d28:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    }

    /* UART Over-Run interrupt occurred -----------------------------------------*/
    if (((isrflags & USART_ISR_ORE) != 0U)
 8010d2c:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8010d30:	f003 0308 	and.w	r3, r3, #8
 8010d34:	2b00      	cmp	r3, #0
 8010d36:	d017      	beq.n	8010d68 <HAL_UART_IRQHandler+0x164>
        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
 8010d38:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 8010d3c:	f003 0320 	and.w	r3, r3, #32
 8010d40:	2b00      	cmp	r3, #0
 8010d42:	d105      	bne.n	8010d50 <HAL_UART_IRQHandler+0x14c>
            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
 8010d44:	f8d7 20dc 	ldr.w	r2, [r7, #220]	@ 0xdc
 8010d48:	4b5c      	ldr	r3, [pc, #368]	@ (8010ebc <HAL_UART_IRQHandler+0x2b8>)
 8010d4a:	4013      	ands	r3, r2
        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
 8010d4c:	2b00      	cmp	r3, #0
 8010d4e:	d00b      	beq.n	8010d68 <HAL_UART_IRQHandler+0x164>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 8010d50:	687b      	ldr	r3, [r7, #4]
 8010d52:	681b      	ldr	r3, [r3, #0]
 8010d54:	2208      	movs	r2, #8
 8010d56:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_ORE;
 8010d58:	687b      	ldr	r3, [r7, #4]
 8010d5a:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8010d5e:	f043 0208 	orr.w	r2, r3, #8
 8010d62:	687b      	ldr	r3, [r7, #4]
 8010d64:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    }

    /* UART Receiver Timeout interrupt occurred ---------------------------------*/
    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
 8010d68:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8010d6c:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 8010d70:	2b00      	cmp	r3, #0
 8010d72:	d012      	beq.n	8010d9a <HAL_UART_IRQHandler+0x196>
 8010d74:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 8010d78:	f003 6380 	and.w	r3, r3, #67108864	@ 0x4000000
 8010d7c:	2b00      	cmp	r3, #0
 8010d7e:	d00c      	beq.n	8010d9a <HAL_UART_IRQHandler+0x196>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 8010d80:	687b      	ldr	r3, [r7, #4]
 8010d82:	681b      	ldr	r3, [r3, #0]
 8010d84:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 8010d88:	621a      	str	r2, [r3, #32]

      huart->ErrorCode |= HAL_UART_ERROR_RTO;
 8010d8a:	687b      	ldr	r3, [r7, #4]
 8010d8c:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8010d90:	f043 0220 	orr.w	r2, r3, #32
 8010d94:	687b      	ldr	r3, [r7, #4]
 8010d96:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
    }

    /* Call UART Error Call back function if need be ----------------------------*/
    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
 8010d9a:	687b      	ldr	r3, [r7, #4]
 8010d9c:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8010da0:	2b00      	cmp	r3, #0
 8010da2:	f000 82dd 	beq.w	8011360 <HAL_UART_IRQHandler+0x75c>
    {
      /* UART in mode Receiver --------------------------------------------------*/
      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
 8010da6:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8010daa:	f003 0320 	and.w	r3, r3, #32
 8010dae:	2b00      	cmp	r3, #0
 8010db0:	d013      	beq.n	8010dda <HAL_UART_IRQHandler+0x1d6>
          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
 8010db2:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 8010db6:	f003 0320 	and.w	r3, r3, #32
 8010dba:	2b00      	cmp	r3, #0
 8010dbc:	d105      	bne.n	8010dca <HAL_UART_IRQHandler+0x1c6>
              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
 8010dbe:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 8010dc2:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8010dc6:	2b00      	cmp	r3, #0
 8010dc8:	d007      	beq.n	8010dda <HAL_UART_IRQHandler+0x1d6>
      {
        if (huart->RxISR != NULL)
 8010dca:	687b      	ldr	r3, [r7, #4]
 8010dcc:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 8010dce:	2b00      	cmp	r3, #0
 8010dd0:	d003      	beq.n	8010dda <HAL_UART_IRQHandler+0x1d6>
        {
          huart->RxISR(huart);
 8010dd2:	687b      	ldr	r3, [r7, #4]
 8010dd4:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
 8010dd6:	6878      	ldr	r0, [r7, #4]
 8010dd8:	4798      	blx	r3
      /* If Error is to be considered as blocking :
          - Receiver Timeout error in Reception
          - Overrun error in Reception
          - any error occurs in DMA mode reception
      */
      errorcode = huart->ErrorCode;
 8010dda:	687b      	ldr	r3, [r7, #4]
 8010ddc:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8010de0:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
 8010de4:	687b      	ldr	r3, [r7, #4]
 8010de6:	681b      	ldr	r3, [r3, #0]
 8010de8:	689b      	ldr	r3, [r3, #8]
 8010dea:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8010dee:	2b40      	cmp	r3, #64	@ 0x40
 8010df0:	d005      	beq.n	8010dfe <HAL_UART_IRQHandler+0x1fa>
          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
 8010df2:	f8d7 30d4 	ldr.w	r3, [r7, #212]	@ 0xd4
 8010df6:	f003 0328 	and.w	r3, r3, #40	@ 0x28
      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
 8010dfa:	2b00      	cmp	r3, #0
 8010dfc:	d054      	beq.n	8010ea8 <HAL_UART_IRQHandler+0x2a4>
      {
        /* Blocking error : transfer is aborted
           Set the UART state ready to be able to start again the process,
           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
        UART_EndRxTransfer(huart);
 8010dfe:	6878      	ldr	r0, [r7, #4]
 8010e00:	f001 fb08 	bl	8012414 <UART_EndRxTransfer>

        /* Abort the UART DMA Rx channel if enabled */
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8010e04:	687b      	ldr	r3, [r7, #4]
 8010e06:	681b      	ldr	r3, [r3, #0]
 8010e08:	689b      	ldr	r3, [r3, #8]
 8010e0a:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8010e0e:	2b40      	cmp	r3, #64	@ 0x40
 8010e10:	d146      	bne.n	8010ea0 <HAL_UART_IRQHandler+0x29c>
        {
          /* Disable the UART DMA Rx request if enabled */
          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8010e12:	687b      	ldr	r3, [r7, #4]
 8010e14:	681b      	ldr	r3, [r3, #0]
 8010e16:	3308      	adds	r3, #8
 8010e18:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8010e1c:	f8d7 309c 	ldr.w	r3, [r7, #156]	@ 0x9c
 8010e20:	e853 3f00 	ldrex	r3, [r3]
 8010e24:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
   return(result);
 8010e28:	f8d7 3098 	ldr.w	r3, [r7, #152]	@ 0x98
 8010e2c:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
 8010e30:	f8c7 30d0 	str.w	r3, [r7, #208]	@ 0xd0
 8010e34:	687b      	ldr	r3, [r7, #4]
 8010e36:	681b      	ldr	r3, [r3, #0]
 8010e38:	3308      	adds	r3, #8
 8010e3a:	f8d7 20d0 	ldr.w	r2, [r7, #208]	@ 0xd0
 8010e3e:	f8c7 20a8 	str.w	r2, [r7, #168]	@ 0xa8
 8010e42:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8010e46:	f8d7 10a4 	ldr.w	r1, [r7, #164]	@ 0xa4
 8010e4a:	f8d7 20a8 	ldr.w	r2, [r7, #168]	@ 0xa8
 8010e4e:	e841 2300 	strex	r3, r2, [r1]
 8010e52:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
   return(result);
 8010e56:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
 8010e5a:	2b00      	cmp	r3, #0
 8010e5c:	d1d9      	bne.n	8010e12 <HAL_UART_IRQHandler+0x20e>

          /* Abort the UART DMA Rx channel */
          if (huart->hdmarx != NULL)
 8010e5e:	687b      	ldr	r3, [r7, #4]
 8010e60:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010e64:	2b00      	cmp	r3, #0
 8010e66:	d017      	beq.n	8010e98 <HAL_UART_IRQHandler+0x294>
          {
            /* Set the UART DMA Abort callback :
               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
 8010e68:	687b      	ldr	r3, [r7, #4]
 8010e6a:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010e6e:	4a15      	ldr	r2, [pc, #84]	@ (8010ec4 <HAL_UART_IRQHandler+0x2c0>)
 8010e70:	651a      	str	r2, [r3, #80]	@ 0x50

            /* Abort DMA RX */
            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
 8010e72:	687b      	ldr	r3, [r7, #4]
 8010e74:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010e78:	4618      	mov	r0, r3
 8010e7a:	f7f7 ff5f 	bl	8008d3c <HAL_DMA_Abort_IT>
 8010e7e:	4603      	mov	r3, r0
 8010e80:	2b00      	cmp	r3, #0
 8010e82:	d019      	beq.n	8010eb8 <HAL_UART_IRQHandler+0x2b4>
            {
              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 8010e84:	687b      	ldr	r3, [r7, #4]
 8010e86:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010e8a:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8010e8c:	687a      	ldr	r2, [r7, #4]
 8010e8e:	f8d2 2080 	ldr.w	r2, [r2, #128]	@ 0x80
 8010e92:	4610      	mov	r0, r2
 8010e94:	4798      	blx	r3
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8010e96:	e00f      	b.n	8010eb8 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
            /*Call registered error callback*/
            huart->ErrorCallback(huart);
#else
            /*Call legacy weak error callback*/
            HAL_UART_ErrorCallback(huart);
 8010e98:	6878      	ldr	r0, [r7, #4]
 8010e9a:	f000 fa6d 	bl	8011378 <HAL_UART_ErrorCallback>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8010e9e:	e00b      	b.n	8010eb8 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered error callback*/
          huart->ErrorCallback(huart);
#else
          /*Call legacy weak error callback*/
          HAL_UART_ErrorCallback(huart);
 8010ea0:	6878      	ldr	r0, [r7, #4]
 8010ea2:	f000 fa69 	bl	8011378 <HAL_UART_ErrorCallback>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8010ea6:	e007      	b.n	8010eb8 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered error callback*/
        huart->ErrorCallback(huart);
#else
        /*Call legacy weak error callback*/
        HAL_UART_ErrorCallback(huart);
 8010ea8:	6878      	ldr	r0, [r7, #4]
 8010eaa:	f000 fa65 	bl	8011378 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
        huart->ErrorCode = HAL_UART_ERROR_NONE;
 8010eae:	687b      	ldr	r3, [r7, #4]
 8010eb0:	2200      	movs	r2, #0
 8010eb2:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
      }
    }
    return;
 8010eb6:	e253      	b.n	8011360 <HAL_UART_IRQHandler+0x75c>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8010eb8:	bf00      	nop
    return;
 8010eba:	e251      	b.n	8011360 <HAL_UART_IRQHandler+0x75c>
 8010ebc:	10000001 	.word	0x10000001
 8010ec0:	04000120 	.word	0x04000120
 8010ec4:	080124e1 	.word	0x080124e1

  } /* End if some error occurs */

  /* Check current reception Mode :
     If Reception till IDLE event has been selected : */
  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8010ec8:	687b      	ldr	r3, [r7, #4]
 8010eca:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8010ecc:	2b01      	cmp	r3, #1
 8010ece:	f040 81e7 	bne.w	80112a0 <HAL_UART_IRQHandler+0x69c>
      && ((isrflags & USART_ISR_IDLE) != 0U)
 8010ed2:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8010ed6:	f003 0310 	and.w	r3, r3, #16
 8010eda:	2b00      	cmp	r3, #0
 8010edc:	f000 81e0 	beq.w	80112a0 <HAL_UART_IRQHandler+0x69c>
      && ((cr1its & USART_ISR_IDLE) != 0U))
 8010ee0:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 8010ee4:	f003 0310 	and.w	r3, r3, #16
 8010ee8:	2b00      	cmp	r3, #0
 8010eea:	f000 81d9 	beq.w	80112a0 <HAL_UART_IRQHandler+0x69c>
  {
    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 8010eee:	687b      	ldr	r3, [r7, #4]
 8010ef0:	681b      	ldr	r3, [r3, #0]
 8010ef2:	2210      	movs	r2, #16
 8010ef4:	621a      	str	r2, [r3, #32]

    /* Check if DMA mode is enabled in UART */
    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8010ef6:	687b      	ldr	r3, [r7, #4]
 8010ef8:	681b      	ldr	r3, [r3, #0]
 8010efa:	689b      	ldr	r3, [r3, #8]
 8010efc:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8010f00:	2b40      	cmp	r3, #64	@ 0x40
 8010f02:	f040 8151 	bne.w	80111a8 <HAL_UART_IRQHandler+0x5a4>
    {
      /* DMA mode enabled */
      /* Check received length : If all expected data are received, do nothing,
         (DMA cplt callback will be called).
         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
 8010f06:	687b      	ldr	r3, [r7, #4]
 8010f08:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010f0c:	681b      	ldr	r3, [r3, #0]
 8010f0e:	4a96      	ldr	r2, [pc, #600]	@ (8011168 <HAL_UART_IRQHandler+0x564>)
 8010f10:	4293      	cmp	r3, r2
 8010f12:	d068      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010f14:	687b      	ldr	r3, [r7, #4]
 8010f16:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010f1a:	681b      	ldr	r3, [r3, #0]
 8010f1c:	4a93      	ldr	r2, [pc, #588]	@ (801116c <HAL_UART_IRQHandler+0x568>)
 8010f1e:	4293      	cmp	r3, r2
 8010f20:	d061      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010f22:	687b      	ldr	r3, [r7, #4]
 8010f24:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010f28:	681b      	ldr	r3, [r3, #0]
 8010f2a:	4a91      	ldr	r2, [pc, #580]	@ (8011170 <HAL_UART_IRQHandler+0x56c>)
 8010f2c:	4293      	cmp	r3, r2
 8010f2e:	d05a      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010f30:	687b      	ldr	r3, [r7, #4]
 8010f32:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010f36:	681b      	ldr	r3, [r3, #0]
 8010f38:	4a8e      	ldr	r2, [pc, #568]	@ (8011174 <HAL_UART_IRQHandler+0x570>)
 8010f3a:	4293      	cmp	r3, r2
 8010f3c:	d053      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010f3e:	687b      	ldr	r3, [r7, #4]
 8010f40:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010f44:	681b      	ldr	r3, [r3, #0]
 8010f46:	4a8c      	ldr	r2, [pc, #560]	@ (8011178 <HAL_UART_IRQHandler+0x574>)
 8010f48:	4293      	cmp	r3, r2
 8010f4a:	d04c      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010f4c:	687b      	ldr	r3, [r7, #4]
 8010f4e:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010f52:	681b      	ldr	r3, [r3, #0]
 8010f54:	4a89      	ldr	r2, [pc, #548]	@ (801117c <HAL_UART_IRQHandler+0x578>)
 8010f56:	4293      	cmp	r3, r2
 8010f58:	d045      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010f5a:	687b      	ldr	r3, [r7, #4]
 8010f5c:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010f60:	681b      	ldr	r3, [r3, #0]
 8010f62:	4a87      	ldr	r2, [pc, #540]	@ (8011180 <HAL_UART_IRQHandler+0x57c>)
 8010f64:	4293      	cmp	r3, r2
 8010f66:	d03e      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010f68:	687b      	ldr	r3, [r7, #4]
 8010f6a:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010f6e:	681b      	ldr	r3, [r3, #0]
 8010f70:	4a84      	ldr	r2, [pc, #528]	@ (8011184 <HAL_UART_IRQHandler+0x580>)
 8010f72:	4293      	cmp	r3, r2
 8010f74:	d037      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010f76:	687b      	ldr	r3, [r7, #4]
 8010f78:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010f7c:	681b      	ldr	r3, [r3, #0]
 8010f7e:	4a82      	ldr	r2, [pc, #520]	@ (8011188 <HAL_UART_IRQHandler+0x584>)
 8010f80:	4293      	cmp	r3, r2
 8010f82:	d030      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010f84:	687b      	ldr	r3, [r7, #4]
 8010f86:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010f8a:	681b      	ldr	r3, [r3, #0]
 8010f8c:	4a7f      	ldr	r2, [pc, #508]	@ (801118c <HAL_UART_IRQHandler+0x588>)
 8010f8e:	4293      	cmp	r3, r2
 8010f90:	d029      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010f92:	687b      	ldr	r3, [r7, #4]
 8010f94:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010f98:	681b      	ldr	r3, [r3, #0]
 8010f9a:	4a7d      	ldr	r2, [pc, #500]	@ (8011190 <HAL_UART_IRQHandler+0x58c>)
 8010f9c:	4293      	cmp	r3, r2
 8010f9e:	d022      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010fa0:	687b      	ldr	r3, [r7, #4]
 8010fa2:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010fa6:	681b      	ldr	r3, [r3, #0]
 8010fa8:	4a7a      	ldr	r2, [pc, #488]	@ (8011194 <HAL_UART_IRQHandler+0x590>)
 8010faa:	4293      	cmp	r3, r2
 8010fac:	d01b      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010fae:	687b      	ldr	r3, [r7, #4]
 8010fb0:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010fb4:	681b      	ldr	r3, [r3, #0]
 8010fb6:	4a78      	ldr	r2, [pc, #480]	@ (8011198 <HAL_UART_IRQHandler+0x594>)
 8010fb8:	4293      	cmp	r3, r2
 8010fba:	d014      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010fbc:	687b      	ldr	r3, [r7, #4]
 8010fbe:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010fc2:	681b      	ldr	r3, [r3, #0]
 8010fc4:	4a75      	ldr	r2, [pc, #468]	@ (801119c <HAL_UART_IRQHandler+0x598>)
 8010fc6:	4293      	cmp	r3, r2
 8010fc8:	d00d      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010fca:	687b      	ldr	r3, [r7, #4]
 8010fcc:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010fd0:	681b      	ldr	r3, [r3, #0]
 8010fd2:	4a73      	ldr	r2, [pc, #460]	@ (80111a0 <HAL_UART_IRQHandler+0x59c>)
 8010fd4:	4293      	cmp	r3, r2
 8010fd6:	d006      	beq.n	8010fe6 <HAL_UART_IRQHandler+0x3e2>
 8010fd8:	687b      	ldr	r3, [r7, #4]
 8010fda:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010fde:	681b      	ldr	r3, [r3, #0]
 8010fe0:	4a70      	ldr	r2, [pc, #448]	@ (80111a4 <HAL_UART_IRQHandler+0x5a0>)
 8010fe2:	4293      	cmp	r3, r2
 8010fe4:	d106      	bne.n	8010ff4 <HAL_UART_IRQHandler+0x3f0>
 8010fe6:	687b      	ldr	r3, [r7, #4]
 8010fe8:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010fec:	681b      	ldr	r3, [r3, #0]
 8010fee:	685b      	ldr	r3, [r3, #4]
 8010ff0:	b29b      	uxth	r3, r3
 8010ff2:	e005      	b.n	8011000 <HAL_UART_IRQHandler+0x3fc>
 8010ff4:	687b      	ldr	r3, [r7, #4]
 8010ff6:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8010ffa:	681b      	ldr	r3, [r3, #0]
 8010ffc:	685b      	ldr	r3, [r3, #4]
 8010ffe:	b29b      	uxth	r3, r3
 8011000:	f8a7 30be 	strh.w	r3, [r7, #190]	@ 0xbe
      if ((nb_remaining_rx_data > 0U)
 8011004:	f8b7 30be 	ldrh.w	r3, [r7, #190]	@ 0xbe
 8011008:	2b00      	cmp	r3, #0
 801100a:	f000 81ab 	beq.w	8011364 <HAL_UART_IRQHandler+0x760>
          && (nb_remaining_rx_data < huart->RxXferSize))
 801100e:	687b      	ldr	r3, [r7, #4]
 8011010:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
 8011014:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
 8011018:	429a      	cmp	r2, r3
 801101a:	f080 81a3 	bcs.w	8011364 <HAL_UART_IRQHandler+0x760>
      {
        /* Reception is not complete */
        huart->RxXferCount = nb_remaining_rx_data;
 801101e:	687b      	ldr	r3, [r7, #4]
 8011020:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
 8011024:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e

        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
        if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
 8011028:	687b      	ldr	r3, [r7, #4]
 801102a:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 801102e:	69db      	ldr	r3, [r3, #28]
 8011030:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
 8011034:	f000 8087 	beq.w	8011146 <HAL_UART_IRQHandler+0x542>
        {
          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 8011038:	687b      	ldr	r3, [r7, #4]
 801103a:	681b      	ldr	r3, [r3, #0]
 801103c:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8011040:	f8d7 3088 	ldr.w	r3, [r7, #136]	@ 0x88
 8011044:	e853 3f00 	ldrex	r3, [r3]
 8011048:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
   return(result);
 801104c:	f8d7 3084 	ldr.w	r3, [r7, #132]	@ 0x84
 8011050:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 8011054:	f8c7 30b8 	str.w	r3, [r7, #184]	@ 0xb8
 8011058:	687b      	ldr	r3, [r7, #4]
 801105a:	681b      	ldr	r3, [r3, #0]
 801105c:	461a      	mov	r2, r3
 801105e:	f8d7 30b8 	ldr.w	r3, [r7, #184]	@ 0xb8
 8011062:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
 8011066:	f8c7 2090 	str.w	r2, [r7, #144]	@ 0x90
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 801106a:	f8d7 1090 	ldr.w	r1, [r7, #144]	@ 0x90
 801106e:	f8d7 2094 	ldr.w	r2, [r7, #148]	@ 0x94
 8011072:	e841 2300 	strex	r3, r2, [r1]
 8011076:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
   return(result);
 801107a:	f8d7 308c 	ldr.w	r3, [r7, #140]	@ 0x8c
 801107e:	2b00      	cmp	r3, #0
 8011080:	d1da      	bne.n	8011038 <HAL_UART_IRQHandler+0x434>
          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8011082:	687b      	ldr	r3, [r7, #4]
 8011084:	681b      	ldr	r3, [r3, #0]
 8011086:	3308      	adds	r3, #8
 8011088:	677b      	str	r3, [r7, #116]	@ 0x74
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 801108a:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
 801108c:	e853 3f00 	ldrex	r3, [r3]
 8011090:	673b      	str	r3, [r7, #112]	@ 0x70
   return(result);
 8011092:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
 8011094:	f023 0301 	bic.w	r3, r3, #1
 8011098:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
 801109c:	687b      	ldr	r3, [r7, #4]
 801109e:	681b      	ldr	r3, [r3, #0]
 80110a0:	3308      	adds	r3, #8
 80110a2:	f8d7 20b4 	ldr.w	r2, [r7, #180]	@ 0xb4
 80110a6:	f8c7 2080 	str.w	r2, [r7, #128]	@ 0x80
 80110aa:	67fb      	str	r3, [r7, #124]	@ 0x7c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80110ac:	6ff9      	ldr	r1, [r7, #124]	@ 0x7c
 80110ae:	f8d7 2080 	ldr.w	r2, [r7, #128]	@ 0x80
 80110b2:	e841 2300 	strex	r3, r2, [r1]
 80110b6:	67bb      	str	r3, [r7, #120]	@ 0x78
   return(result);
 80110b8:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
 80110ba:	2b00      	cmp	r3, #0
 80110bc:	d1e1      	bne.n	8011082 <HAL_UART_IRQHandler+0x47e>

          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
             in the UART CR3 register */
          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 80110be:	687b      	ldr	r3, [r7, #4]
 80110c0:	681b      	ldr	r3, [r3, #0]
 80110c2:	3308      	adds	r3, #8
 80110c4:	663b      	str	r3, [r7, #96]	@ 0x60
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80110c6:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 80110c8:	e853 3f00 	ldrex	r3, [r3]
 80110cc:	65fb      	str	r3, [r7, #92]	@ 0x5c
   return(result);
 80110ce:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 80110d0:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
 80110d4:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
 80110d8:	687b      	ldr	r3, [r7, #4]
 80110da:	681b      	ldr	r3, [r3, #0]
 80110dc:	3308      	adds	r3, #8
 80110de:	f8d7 20b0 	ldr.w	r2, [r7, #176]	@ 0xb0
 80110e2:	66fa      	str	r2, [r7, #108]	@ 0x6c
 80110e4:	66bb      	str	r3, [r7, #104]	@ 0x68
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80110e6:	6eb9      	ldr	r1, [r7, #104]	@ 0x68
 80110e8:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
 80110ea:	e841 2300 	strex	r3, r2, [r1]
 80110ee:	667b      	str	r3, [r7, #100]	@ 0x64
   return(result);
 80110f0:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 80110f2:	2b00      	cmp	r3, #0
 80110f4:	d1e3      	bne.n	80110be <HAL_UART_IRQHandler+0x4ba>

          /* At end of Rx process, restore huart->RxState to Ready */
          huart->RxState = HAL_UART_STATE_READY;
 80110f6:	687b      	ldr	r3, [r7, #4]
 80110f8:	2220      	movs	r2, #32
 80110fa:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 80110fe:	687b      	ldr	r3, [r7, #4]
 8011100:	2200      	movs	r2, #0
 8011102:	66da      	str	r2, [r3, #108]	@ 0x6c

          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 8011104:	687b      	ldr	r3, [r7, #4]
 8011106:	681b      	ldr	r3, [r3, #0]
 8011108:	64fb      	str	r3, [r7, #76]	@ 0x4c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 801110a:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 801110c:	e853 3f00 	ldrex	r3, [r3]
 8011110:	64bb      	str	r3, [r7, #72]	@ 0x48
   return(result);
 8011112:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 8011114:	f023 0310 	bic.w	r3, r3, #16
 8011118:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
 801111c:	687b      	ldr	r3, [r7, #4]
 801111e:	681b      	ldr	r3, [r3, #0]
 8011120:	461a      	mov	r2, r3
 8011122:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 8011126:	65bb      	str	r3, [r7, #88]	@ 0x58
 8011128:	657a      	str	r2, [r7, #84]	@ 0x54
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 801112a:	6d79      	ldr	r1, [r7, #84]	@ 0x54
 801112c:	6dba      	ldr	r2, [r7, #88]	@ 0x58
 801112e:	e841 2300 	strex	r3, r2, [r1]
 8011132:	653b      	str	r3, [r7, #80]	@ 0x50
   return(result);
 8011134:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 8011136:	2b00      	cmp	r3, #0
 8011138:	d1e4      	bne.n	8011104 <HAL_UART_IRQHandler+0x500>

          /* Last bytes received, so no need as the abort is immediate */
          (void)HAL_DMA_Abort(huart->hdmarx);
 801113a:	687b      	ldr	r3, [r7, #4]
 801113c:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
 8011140:	4618      	mov	r0, r3
 8011142:	f7f7 fadd 	bl	8008700 <HAL_DMA_Abort>
        }

        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
           In this case, Rx Event type is Idle Event */
        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
 8011146:	687b      	ldr	r3, [r7, #4]
 8011148:	2202      	movs	r2, #2
 801114a:	671a      	str	r2, [r3, #112]	@ 0x70
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered Rx Event callback*/
        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
        /*Call legacy weak Rx Event callback*/
        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
 801114c:	687b      	ldr	r3, [r7, #4]
 801114e:	f8b3 205c 	ldrh.w	r2, [r3, #92]	@ 0x5c
 8011152:	687b      	ldr	r3, [r7, #4]
 8011154:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 8011158:	b29b      	uxth	r3, r3
 801115a:	1ad3      	subs	r3, r2, r3
 801115c:	b29b      	uxth	r3, r3
 801115e:	4619      	mov	r1, r3
 8011160:	6878      	ldr	r0, [r7, #4]
 8011162:	f7f3 f8d1 	bl	8004308 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
      }
      return;
 8011166:	e0fd      	b.n	8011364 <HAL_UART_IRQHandler+0x760>
 8011168:	40020010 	.word	0x40020010
 801116c:	40020028 	.word	0x40020028
 8011170:	40020040 	.word	0x40020040
 8011174:	40020058 	.word	0x40020058
 8011178:	40020070 	.word	0x40020070
 801117c:	40020088 	.word	0x40020088
 8011180:	400200a0 	.word	0x400200a0
 8011184:	400200b8 	.word	0x400200b8
 8011188:	40020410 	.word	0x40020410
 801118c:	40020428 	.word	0x40020428
 8011190:	40020440 	.word	0x40020440
 8011194:	40020458 	.word	0x40020458
 8011198:	40020470 	.word	0x40020470
 801119c:	40020488 	.word	0x40020488
 80111a0:	400204a0 	.word	0x400204a0
 80111a4:	400204b8 	.word	0x400204b8
    else
    {
      /* DMA mode not enabled */
      /* Check received length : If all expected data are received, do nothing.
         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
 80111a8:	687b      	ldr	r3, [r7, #4]
 80111aa:	f8b3 205c 	ldrh.w	r2, [r3, #92]	@ 0x5c
 80111ae:	687b      	ldr	r3, [r7, #4]
 80111b0:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 80111b4:	b29b      	uxth	r3, r3
 80111b6:	1ad3      	subs	r3, r2, r3
 80111b8:	f8a7 30ce 	strh.w	r3, [r7, #206]	@ 0xce
      if ((huart->RxXferCount > 0U)
 80111bc:	687b      	ldr	r3, [r7, #4]
 80111be:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 80111c2:	b29b      	uxth	r3, r3
 80111c4:	2b00      	cmp	r3, #0
 80111c6:	f000 80cf 	beq.w	8011368 <HAL_UART_IRQHandler+0x764>
          && (nb_rx_data > 0U))
 80111ca:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
 80111ce:	2b00      	cmp	r3, #0
 80111d0:	f000 80ca 	beq.w	8011368 <HAL_UART_IRQHandler+0x764>
      {
        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 80111d4:	687b      	ldr	r3, [r7, #4]
 80111d6:	681b      	ldr	r3, [r3, #0]
 80111d8:	63bb      	str	r3, [r7, #56]	@ 0x38
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80111da:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80111dc:	e853 3f00 	ldrex	r3, [r3]
 80111e0:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 80111e2:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80111e4:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 80111e8:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
 80111ec:	687b      	ldr	r3, [r7, #4]
 80111ee:	681b      	ldr	r3, [r3, #0]
 80111f0:	461a      	mov	r2, r3
 80111f2:	f8d7 30c8 	ldr.w	r3, [r7, #200]	@ 0xc8
 80111f6:	647b      	str	r3, [r7, #68]	@ 0x44
 80111f8:	643a      	str	r2, [r7, #64]	@ 0x40
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80111fa:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 80111fc:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 80111fe:	e841 2300 	strex	r3, r2, [r1]
 8011202:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 8011204:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8011206:	2b00      	cmp	r3, #0
 8011208:	d1e4      	bne.n	80111d4 <HAL_UART_IRQHandler+0x5d0>

        /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 801120a:	687b      	ldr	r3, [r7, #4]
 801120c:	681b      	ldr	r3, [r3, #0]
 801120e:	3308      	adds	r3, #8
 8011210:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8011212:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8011214:	e853 3f00 	ldrex	r3, [r3]
 8011218:	623b      	str	r3, [r7, #32]
   return(result);
 801121a:	6a3a      	ldr	r2, [r7, #32]
 801121c:	4b55      	ldr	r3, [pc, #340]	@ (8011374 <HAL_UART_IRQHandler+0x770>)
 801121e:	4013      	ands	r3, r2
 8011220:	f8c7 30c4 	str.w	r3, [r7, #196]	@ 0xc4
 8011224:	687b      	ldr	r3, [r7, #4]
 8011226:	681b      	ldr	r3, [r3, #0]
 8011228:	3308      	adds	r3, #8
 801122a:	f8d7 20c4 	ldr.w	r2, [r7, #196]	@ 0xc4
 801122e:	633a      	str	r2, [r7, #48]	@ 0x30
 8011230:	62fb      	str	r3, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8011232:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 8011234:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8011236:	e841 2300 	strex	r3, r2, [r1]
 801123a:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 801123c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 801123e:	2b00      	cmp	r3, #0
 8011240:	d1e3      	bne.n	801120a <HAL_UART_IRQHandler+0x606>

        /* Rx process is completed, restore huart->RxState to Ready */
        huart->RxState = HAL_UART_STATE_READY;
 8011242:	687b      	ldr	r3, [r7, #4]
 8011244:	2220      	movs	r2, #32
 8011246:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 801124a:	687b      	ldr	r3, [r7, #4]
 801124c:	2200      	movs	r2, #0
 801124e:	66da      	str	r2, [r3, #108]	@ 0x6c

        /* Clear RxISR function pointer */
        huart->RxISR = NULL;
 8011250:	687b      	ldr	r3, [r7, #4]
 8011252:	2200      	movs	r2, #0
 8011254:	675a      	str	r2, [r3, #116]	@ 0x74

        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 8011256:	687b      	ldr	r3, [r7, #4]
 8011258:	681b      	ldr	r3, [r3, #0]
 801125a:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 801125c:	693b      	ldr	r3, [r7, #16]
 801125e:	e853 3f00 	ldrex	r3, [r3]
 8011262:	60fb      	str	r3, [r7, #12]
   return(result);
 8011264:	68fb      	ldr	r3, [r7, #12]
 8011266:	f023 0310 	bic.w	r3, r3, #16
 801126a:	f8c7 30c0 	str.w	r3, [r7, #192]	@ 0xc0
 801126e:	687b      	ldr	r3, [r7, #4]
 8011270:	681b      	ldr	r3, [r3, #0]
 8011272:	461a      	mov	r2, r3
 8011274:	f8d7 30c0 	ldr.w	r3, [r7, #192]	@ 0xc0
 8011278:	61fb      	str	r3, [r7, #28]
 801127a:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 801127c:	69b9      	ldr	r1, [r7, #24]
 801127e:	69fa      	ldr	r2, [r7, #28]
 8011280:	e841 2300 	strex	r3, r2, [r1]
 8011284:	617b      	str	r3, [r7, #20]
   return(result);
 8011286:	697b      	ldr	r3, [r7, #20]
 8011288:	2b00      	cmp	r3, #0
 801128a:	d1e4      	bne.n	8011256 <HAL_UART_IRQHandler+0x652>

        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
           In this case, Rx Event type is Idle Event */
        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
 801128c:	687b      	ldr	r3, [r7, #4]
 801128e:	2202      	movs	r2, #2
 8011290:	671a      	str	r2, [r3, #112]	@ 0x70
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered Rx complete callback*/
        huart->RxEventCallback(huart, nb_rx_data);
#else
        /*Call legacy weak Rx Event callback*/
        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
 8011292:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
 8011296:	4619      	mov	r1, r3
 8011298:	6878      	ldr	r0, [r7, #4]
 801129a:	f7f3 f835 	bl	8004308 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
      }
      return;
 801129e:	e063      	b.n	8011368 <HAL_UART_IRQHandler+0x764>
    }
  }

  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
 80112a0:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 80112a4:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
 80112a8:	2b00      	cmp	r3, #0
 80112aa:	d00e      	beq.n	80112ca <HAL_UART_IRQHandler+0x6c6>
 80112ac:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 80112b0:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
 80112b4:	2b00      	cmp	r3, #0
 80112b6:	d008      	beq.n	80112ca <HAL_UART_IRQHandler+0x6c6>
  {
    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
 80112b8:	687b      	ldr	r3, [r7, #4]
 80112ba:	681b      	ldr	r3, [r3, #0]
 80112bc:	f44f 1280 	mov.w	r2, #1048576	@ 0x100000
 80112c0:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
    /* Call registered Wakeup Callback */
    huart->WakeupCallback(huart);
#else
    /* Call legacy weak Wakeup Callback */
    HAL_UARTEx_WakeupCallback(huart);
 80112c2:	6878      	ldr	r0, [r7, #4]
 80112c4:	f002 f80c 	bl	80132e0 <HAL_UARTEx_WakeupCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
    return;
 80112c8:	e051      	b.n	801136e <HAL_UART_IRQHandler+0x76a>
  }

  /* UART in mode Transmitter ------------------------------------------------*/
  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
 80112ca:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 80112ce:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80112d2:	2b00      	cmp	r3, #0
 80112d4:	d014      	beq.n	8011300 <HAL_UART_IRQHandler+0x6fc>
      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
 80112d6:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 80112da:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80112de:	2b00      	cmp	r3, #0
 80112e0:	d105      	bne.n	80112ee <HAL_UART_IRQHandler+0x6ea>
          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
 80112e2:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 80112e6:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 80112ea:	2b00      	cmp	r3, #0
 80112ec:	d008      	beq.n	8011300 <HAL_UART_IRQHandler+0x6fc>
  {
    if (huart->TxISR != NULL)
 80112ee:	687b      	ldr	r3, [r7, #4]
 80112f0:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 80112f2:	2b00      	cmp	r3, #0
 80112f4:	d03a      	beq.n	801136c <HAL_UART_IRQHandler+0x768>
    {
      huart->TxISR(huart);
 80112f6:	687b      	ldr	r3, [r7, #4]
 80112f8:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
 80112fa:	6878      	ldr	r0, [r7, #4]
 80112fc:	4798      	blx	r3
    }
    return;
 80112fe:	e035      	b.n	801136c <HAL_UART_IRQHandler+0x768>
  }

  /* UART in mode Transmitter (transmission end) -----------------------------*/
  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
 8011300:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8011304:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8011308:	2b00      	cmp	r3, #0
 801130a:	d009      	beq.n	8011320 <HAL_UART_IRQHandler+0x71c>
 801130c:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 8011310:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8011314:	2b00      	cmp	r3, #0
 8011316:	d003      	beq.n	8011320 <HAL_UART_IRQHandler+0x71c>
  {
    UART_EndTransmit_IT(huart);
 8011318:	6878      	ldr	r0, [r7, #4]
 801131a:	f001 fa99 	bl	8012850 <UART_EndTransmit_IT>
    return;
 801131e:	e026      	b.n	801136e <HAL_UART_IRQHandler+0x76a>
  }

  /* UART TX Fifo Empty occurred ----------------------------------------------*/
  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
 8011320:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8011324:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 8011328:	2b00      	cmp	r3, #0
 801132a:	d009      	beq.n	8011340 <HAL_UART_IRQHandler+0x73c>
 801132c:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 8011330:	f003 4380 	and.w	r3, r3, #1073741824	@ 0x40000000
 8011334:	2b00      	cmp	r3, #0
 8011336:	d003      	beq.n	8011340 <HAL_UART_IRQHandler+0x73c>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
    /* Call registered Tx Fifo Empty Callback */
    huart->TxFifoEmptyCallback(huart);
#else
    /* Call legacy weak Tx Fifo Empty Callback */
    HAL_UARTEx_TxFifoEmptyCallback(huart);
 8011338:	6878      	ldr	r0, [r7, #4]
 801133a:	f001 ffe5 	bl	8013308 <HAL_UARTEx_TxFifoEmptyCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
    return;
 801133e:	e016      	b.n	801136e <HAL_UART_IRQHandler+0x76a>
  }

  /* UART RX Fifo Full occurred ----------------------------------------------*/
  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
 8011340:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8011344:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
 8011348:	2b00      	cmp	r3, #0
 801134a:	d010      	beq.n	801136e <HAL_UART_IRQHandler+0x76a>
 801134c:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 8011350:	2b00      	cmp	r3, #0
 8011352:	da0c      	bge.n	801136e <HAL_UART_IRQHandler+0x76a>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
    /* Call registered Rx Fifo Full Callback */
    huart->RxFifoFullCallback(huart);
#else
    /* Call legacy weak Rx Fifo Full Callback */
    HAL_UARTEx_RxFifoFullCallback(huart);
 8011354:	6878      	ldr	r0, [r7, #4]
 8011356:	f001 ffcd 	bl	80132f4 <HAL_UARTEx_RxFifoFullCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
    return;
 801135a:	e008      	b.n	801136e <HAL_UART_IRQHandler+0x76a>
      return;
 801135c:	bf00      	nop
 801135e:	e006      	b.n	801136e <HAL_UART_IRQHandler+0x76a>
    return;
 8011360:	bf00      	nop
 8011362:	e004      	b.n	801136e <HAL_UART_IRQHandler+0x76a>
      return;
 8011364:	bf00      	nop
 8011366:	e002      	b.n	801136e <HAL_UART_IRQHandler+0x76a>
      return;
 8011368:	bf00      	nop
 801136a:	e000      	b.n	801136e <HAL_UART_IRQHandler+0x76a>
    return;
 801136c:	bf00      	nop
  }
}
 801136e:	37e8      	adds	r7, #232	@ 0xe8
 8011370:	46bd      	mov	sp, r7
 8011372:	bd80      	pop	{r7, pc}
 8011374:	effffffe 	.word	0xeffffffe

08011378 <HAL_UART_ErrorCallback>:
  * @brief  UART error callback.
  * @param  huart UART handle.
  * @retval None
  */
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
 8011378:	b480      	push	{r7}
 801137a:	b083      	sub	sp, #12
 801137c:	af00      	add	r7, sp, #0
 801137e:	6078      	str	r0, [r7, #4]
  UNUSED(huart);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_UART_ErrorCallback can be implemented in the user file.
   */
}
 8011380:	bf00      	nop
 8011382:	370c      	adds	r7, #12
 8011384:	46bd      	mov	sp, r7
 8011386:	f85d 7b04 	ldr.w	r7, [sp], #4
 801138a:	4770      	bx	lr

0801138c <UART_SetConfig>:
  * @brief Configure the UART peripheral.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
 801138c:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 8011390:	b092      	sub	sp, #72	@ 0x48
 8011392:	af00      	add	r7, sp, #0
 8011394:	6178      	str	r0, [r7, #20]
  uint32_t tmpreg;
  uint16_t brrtemp;
  UART_ClockSourceTypeDef clocksource;
  uint32_t usartdiv;
  HAL_StatusTypeDef ret               = HAL_OK;
 8011396:	2300      	movs	r3, #0
 8011398:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
  *  the UART Word Length, Parity, Mode and oversampling:
  *  set the M bits according to huart->Init.WordLength value
  *  set PCE and PS bits according to huart->Init.Parity value
  *  set TE and RE bits according to huart->Init.Mode value
  *  set OVER8 bit according to huart->Init.OverSampling value */
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
 801139c:	697b      	ldr	r3, [r7, #20]
 801139e:	689a      	ldr	r2, [r3, #8]
 80113a0:	697b      	ldr	r3, [r7, #20]
 80113a2:	691b      	ldr	r3, [r3, #16]
 80113a4:	431a      	orrs	r2, r3
 80113a6:	697b      	ldr	r3, [r7, #20]
 80113a8:	695b      	ldr	r3, [r3, #20]
 80113aa:	431a      	orrs	r2, r3
 80113ac:	697b      	ldr	r3, [r7, #20]
 80113ae:	69db      	ldr	r3, [r3, #28]
 80113b0:	4313      	orrs	r3, r2
 80113b2:	647b      	str	r3, [r7, #68]	@ 0x44
  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
 80113b4:	697b      	ldr	r3, [r7, #20]
 80113b6:	681b      	ldr	r3, [r3, #0]
 80113b8:	681a      	ldr	r2, [r3, #0]
 80113ba:	4bbe      	ldr	r3, [pc, #760]	@ (80116b4 <UART_SetConfig+0x328>)
 80113bc:	4013      	ands	r3, r2
 80113be:	697a      	ldr	r2, [r7, #20]
 80113c0:	6812      	ldr	r2, [r2, #0]
 80113c2:	6c79      	ldr	r1, [r7, #68]	@ 0x44
 80113c4:	430b      	orrs	r3, r1
 80113c6:	6013      	str	r3, [r2, #0]

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
  * to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 80113c8:	697b      	ldr	r3, [r7, #20]
 80113ca:	681b      	ldr	r3, [r3, #0]
 80113cc:	685b      	ldr	r3, [r3, #4]
 80113ce:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
 80113d2:	697b      	ldr	r3, [r7, #20]
 80113d4:	68da      	ldr	r2, [r3, #12]
 80113d6:	697b      	ldr	r3, [r7, #20]
 80113d8:	681b      	ldr	r3, [r3, #0]
 80113da:	430a      	orrs	r2, r1
 80113dc:	605a      	str	r2, [r3, #4]
  /* Configure
  * - UART HardWare Flow Control: set CTSE and RTSE bits according
  *   to huart->Init.HwFlowCtl value
  * - one-bit sampling method versus three samples' majority rule according
  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
 80113de:	697b      	ldr	r3, [r7, #20]
 80113e0:	699b      	ldr	r3, [r3, #24]
 80113e2:	647b      	str	r3, [r7, #68]	@ 0x44

  if (!(UART_INSTANCE_LOWPOWER(huart)))
 80113e4:	697b      	ldr	r3, [r7, #20]
 80113e6:	681b      	ldr	r3, [r3, #0]
 80113e8:	4ab3      	ldr	r2, [pc, #716]	@ (80116b8 <UART_SetConfig+0x32c>)
 80113ea:	4293      	cmp	r3, r2
 80113ec:	d004      	beq.n	80113f8 <UART_SetConfig+0x6c>
  {
    tmpreg |= huart->Init.OneBitSampling;
 80113ee:	697b      	ldr	r3, [r7, #20]
 80113f0:	6a1b      	ldr	r3, [r3, #32]
 80113f2:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 80113f4:	4313      	orrs	r3, r2
 80113f6:	647b      	str	r3, [r7, #68]	@ 0x44
  }
  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
 80113f8:	697b      	ldr	r3, [r7, #20]
 80113fa:	681b      	ldr	r3, [r3, #0]
 80113fc:	689a      	ldr	r2, [r3, #8]
 80113fe:	4baf      	ldr	r3, [pc, #700]	@ (80116bc <UART_SetConfig+0x330>)
 8011400:	4013      	ands	r3, r2
 8011402:	697a      	ldr	r2, [r7, #20]
 8011404:	6812      	ldr	r2, [r2, #0]
 8011406:	6c79      	ldr	r1, [r7, #68]	@ 0x44
 8011408:	430b      	orrs	r3, r1
 801140a:	6093      	str	r3, [r2, #8]

  /*-------------------------- USART PRESC Configuration -----------------------*/
  /* Configure
  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
 801140c:	697b      	ldr	r3, [r7, #20]
 801140e:	681b      	ldr	r3, [r3, #0]
 8011410:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8011412:	f023 010f 	bic.w	r1, r3, #15
 8011416:	697b      	ldr	r3, [r7, #20]
 8011418:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
 801141a:	697b      	ldr	r3, [r7, #20]
 801141c:	681b      	ldr	r3, [r3, #0]
 801141e:	430a      	orrs	r2, r1
 8011420:	62da      	str	r2, [r3, #44]	@ 0x2c

  /*-------------------------- USART BRR Configuration -----------------------*/
  UART_GETCLOCKSOURCE(huart, clocksource);
 8011422:	697b      	ldr	r3, [r7, #20]
 8011424:	681b      	ldr	r3, [r3, #0]
 8011426:	4aa6      	ldr	r2, [pc, #664]	@ (80116c0 <UART_SetConfig+0x334>)
 8011428:	4293      	cmp	r3, r2
 801142a:	d177      	bne.n	801151c <UART_SetConfig+0x190>
 801142c:	4ba5      	ldr	r3, [pc, #660]	@ (80116c4 <UART_SetConfig+0x338>)
 801142e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8011430:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 8011434:	2b28      	cmp	r3, #40	@ 0x28
 8011436:	d86d      	bhi.n	8011514 <UART_SetConfig+0x188>
 8011438:	a201      	add	r2, pc, #4	@ (adr r2, 8011440 <UART_SetConfig+0xb4>)
 801143a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 801143e:	bf00      	nop
 8011440:	080114e5 	.word	0x080114e5
 8011444:	08011515 	.word	0x08011515
 8011448:	08011515 	.word	0x08011515
 801144c:	08011515 	.word	0x08011515
 8011450:	08011515 	.word	0x08011515
 8011454:	08011515 	.word	0x08011515
 8011458:	08011515 	.word	0x08011515
 801145c:	08011515 	.word	0x08011515
 8011460:	080114ed 	.word	0x080114ed
 8011464:	08011515 	.word	0x08011515
 8011468:	08011515 	.word	0x08011515
 801146c:	08011515 	.word	0x08011515
 8011470:	08011515 	.word	0x08011515
 8011474:	08011515 	.word	0x08011515
 8011478:	08011515 	.word	0x08011515
 801147c:	08011515 	.word	0x08011515
 8011480:	080114f5 	.word	0x080114f5
 8011484:	08011515 	.word	0x08011515
 8011488:	08011515 	.word	0x08011515
 801148c:	08011515 	.word	0x08011515
 8011490:	08011515 	.word	0x08011515
 8011494:	08011515 	.word	0x08011515
 8011498:	08011515 	.word	0x08011515
 801149c:	08011515 	.word	0x08011515
 80114a0:	080114fd 	.word	0x080114fd
 80114a4:	08011515 	.word	0x08011515
 80114a8:	08011515 	.word	0x08011515
 80114ac:	08011515 	.word	0x08011515
 80114b0:	08011515 	.word	0x08011515
 80114b4:	08011515 	.word	0x08011515
 80114b8:	08011515 	.word	0x08011515
 80114bc:	08011515 	.word	0x08011515
 80114c0:	08011505 	.word	0x08011505
 80114c4:	08011515 	.word	0x08011515
 80114c8:	08011515 	.word	0x08011515
 80114cc:	08011515 	.word	0x08011515
 80114d0:	08011515 	.word	0x08011515
 80114d4:	08011515 	.word	0x08011515
 80114d8:	08011515 	.word	0x08011515
 80114dc:	08011515 	.word	0x08011515
 80114e0:	0801150d 	.word	0x0801150d
 80114e4:	2301      	movs	r3, #1
 80114e6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80114ea:	e222      	b.n	8011932 <UART_SetConfig+0x5a6>
 80114ec:	2304      	movs	r3, #4
 80114ee:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80114f2:	e21e      	b.n	8011932 <UART_SetConfig+0x5a6>
 80114f4:	2308      	movs	r3, #8
 80114f6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80114fa:	e21a      	b.n	8011932 <UART_SetConfig+0x5a6>
 80114fc:	2310      	movs	r3, #16
 80114fe:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011502:	e216      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011504:	2320      	movs	r3, #32
 8011506:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801150a:	e212      	b.n	8011932 <UART_SetConfig+0x5a6>
 801150c:	2340      	movs	r3, #64	@ 0x40
 801150e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011512:	e20e      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011514:	2380      	movs	r3, #128	@ 0x80
 8011516:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801151a:	e20a      	b.n	8011932 <UART_SetConfig+0x5a6>
 801151c:	697b      	ldr	r3, [r7, #20]
 801151e:	681b      	ldr	r3, [r3, #0]
 8011520:	4a69      	ldr	r2, [pc, #420]	@ (80116c8 <UART_SetConfig+0x33c>)
 8011522:	4293      	cmp	r3, r2
 8011524:	d130      	bne.n	8011588 <UART_SetConfig+0x1fc>
 8011526:	4b67      	ldr	r3, [pc, #412]	@ (80116c4 <UART_SetConfig+0x338>)
 8011528:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 801152a:	f003 0307 	and.w	r3, r3, #7
 801152e:	2b05      	cmp	r3, #5
 8011530:	d826      	bhi.n	8011580 <UART_SetConfig+0x1f4>
 8011532:	a201      	add	r2, pc, #4	@ (adr r2, 8011538 <UART_SetConfig+0x1ac>)
 8011534:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8011538:	08011551 	.word	0x08011551
 801153c:	08011559 	.word	0x08011559
 8011540:	08011561 	.word	0x08011561
 8011544:	08011569 	.word	0x08011569
 8011548:	08011571 	.word	0x08011571
 801154c:	08011579 	.word	0x08011579
 8011550:	2300      	movs	r3, #0
 8011552:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011556:	e1ec      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011558:	2304      	movs	r3, #4
 801155a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801155e:	e1e8      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011560:	2308      	movs	r3, #8
 8011562:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011566:	e1e4      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011568:	2310      	movs	r3, #16
 801156a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801156e:	e1e0      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011570:	2320      	movs	r3, #32
 8011572:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011576:	e1dc      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011578:	2340      	movs	r3, #64	@ 0x40
 801157a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801157e:	e1d8      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011580:	2380      	movs	r3, #128	@ 0x80
 8011582:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011586:	e1d4      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011588:	697b      	ldr	r3, [r7, #20]
 801158a:	681b      	ldr	r3, [r3, #0]
 801158c:	4a4f      	ldr	r2, [pc, #316]	@ (80116cc <UART_SetConfig+0x340>)
 801158e:	4293      	cmp	r3, r2
 8011590:	d130      	bne.n	80115f4 <UART_SetConfig+0x268>
 8011592:	4b4c      	ldr	r3, [pc, #304]	@ (80116c4 <UART_SetConfig+0x338>)
 8011594:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8011596:	f003 0307 	and.w	r3, r3, #7
 801159a:	2b05      	cmp	r3, #5
 801159c:	d826      	bhi.n	80115ec <UART_SetConfig+0x260>
 801159e:	a201      	add	r2, pc, #4	@ (adr r2, 80115a4 <UART_SetConfig+0x218>)
 80115a0:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80115a4:	080115bd 	.word	0x080115bd
 80115a8:	080115c5 	.word	0x080115c5
 80115ac:	080115cd 	.word	0x080115cd
 80115b0:	080115d5 	.word	0x080115d5
 80115b4:	080115dd 	.word	0x080115dd
 80115b8:	080115e5 	.word	0x080115e5
 80115bc:	2300      	movs	r3, #0
 80115be:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80115c2:	e1b6      	b.n	8011932 <UART_SetConfig+0x5a6>
 80115c4:	2304      	movs	r3, #4
 80115c6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80115ca:	e1b2      	b.n	8011932 <UART_SetConfig+0x5a6>
 80115cc:	2308      	movs	r3, #8
 80115ce:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80115d2:	e1ae      	b.n	8011932 <UART_SetConfig+0x5a6>
 80115d4:	2310      	movs	r3, #16
 80115d6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80115da:	e1aa      	b.n	8011932 <UART_SetConfig+0x5a6>
 80115dc:	2320      	movs	r3, #32
 80115de:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80115e2:	e1a6      	b.n	8011932 <UART_SetConfig+0x5a6>
 80115e4:	2340      	movs	r3, #64	@ 0x40
 80115e6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80115ea:	e1a2      	b.n	8011932 <UART_SetConfig+0x5a6>
 80115ec:	2380      	movs	r3, #128	@ 0x80
 80115ee:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80115f2:	e19e      	b.n	8011932 <UART_SetConfig+0x5a6>
 80115f4:	697b      	ldr	r3, [r7, #20]
 80115f6:	681b      	ldr	r3, [r3, #0]
 80115f8:	4a35      	ldr	r2, [pc, #212]	@ (80116d0 <UART_SetConfig+0x344>)
 80115fa:	4293      	cmp	r3, r2
 80115fc:	d130      	bne.n	8011660 <UART_SetConfig+0x2d4>
 80115fe:	4b31      	ldr	r3, [pc, #196]	@ (80116c4 <UART_SetConfig+0x338>)
 8011600:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8011602:	f003 0307 	and.w	r3, r3, #7
 8011606:	2b05      	cmp	r3, #5
 8011608:	d826      	bhi.n	8011658 <UART_SetConfig+0x2cc>
 801160a:	a201      	add	r2, pc, #4	@ (adr r2, 8011610 <UART_SetConfig+0x284>)
 801160c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8011610:	08011629 	.word	0x08011629
 8011614:	08011631 	.word	0x08011631
 8011618:	08011639 	.word	0x08011639
 801161c:	08011641 	.word	0x08011641
 8011620:	08011649 	.word	0x08011649
 8011624:	08011651 	.word	0x08011651
 8011628:	2300      	movs	r3, #0
 801162a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801162e:	e180      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011630:	2304      	movs	r3, #4
 8011632:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011636:	e17c      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011638:	2308      	movs	r3, #8
 801163a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801163e:	e178      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011640:	2310      	movs	r3, #16
 8011642:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011646:	e174      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011648:	2320      	movs	r3, #32
 801164a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801164e:	e170      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011650:	2340      	movs	r3, #64	@ 0x40
 8011652:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011656:	e16c      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011658:	2380      	movs	r3, #128	@ 0x80
 801165a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801165e:	e168      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011660:	697b      	ldr	r3, [r7, #20]
 8011662:	681b      	ldr	r3, [r3, #0]
 8011664:	4a1b      	ldr	r2, [pc, #108]	@ (80116d4 <UART_SetConfig+0x348>)
 8011666:	4293      	cmp	r3, r2
 8011668:	d142      	bne.n	80116f0 <UART_SetConfig+0x364>
 801166a:	4b16      	ldr	r3, [pc, #88]	@ (80116c4 <UART_SetConfig+0x338>)
 801166c:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 801166e:	f003 0307 	and.w	r3, r3, #7
 8011672:	2b05      	cmp	r3, #5
 8011674:	d838      	bhi.n	80116e8 <UART_SetConfig+0x35c>
 8011676:	a201      	add	r2, pc, #4	@ (adr r2, 801167c <UART_SetConfig+0x2f0>)
 8011678:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 801167c:	08011695 	.word	0x08011695
 8011680:	0801169d 	.word	0x0801169d
 8011684:	080116a5 	.word	0x080116a5
 8011688:	080116ad 	.word	0x080116ad
 801168c:	080116d9 	.word	0x080116d9
 8011690:	080116e1 	.word	0x080116e1
 8011694:	2300      	movs	r3, #0
 8011696:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801169a:	e14a      	b.n	8011932 <UART_SetConfig+0x5a6>
 801169c:	2304      	movs	r3, #4
 801169e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80116a2:	e146      	b.n	8011932 <UART_SetConfig+0x5a6>
 80116a4:	2308      	movs	r3, #8
 80116a6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80116aa:	e142      	b.n	8011932 <UART_SetConfig+0x5a6>
 80116ac:	2310      	movs	r3, #16
 80116ae:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80116b2:	e13e      	b.n	8011932 <UART_SetConfig+0x5a6>
 80116b4:	cfff69f3 	.word	0xcfff69f3
 80116b8:	58000c00 	.word	0x58000c00
 80116bc:	11fff4ff 	.word	0x11fff4ff
 80116c0:	40011000 	.word	0x40011000
 80116c4:	58024400 	.word	0x58024400
 80116c8:	40004400 	.word	0x40004400
 80116cc:	40004800 	.word	0x40004800
 80116d0:	40004c00 	.word	0x40004c00
 80116d4:	40005000 	.word	0x40005000
 80116d8:	2320      	movs	r3, #32
 80116da:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80116de:	e128      	b.n	8011932 <UART_SetConfig+0x5a6>
 80116e0:	2340      	movs	r3, #64	@ 0x40
 80116e2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80116e6:	e124      	b.n	8011932 <UART_SetConfig+0x5a6>
 80116e8:	2380      	movs	r3, #128	@ 0x80
 80116ea:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80116ee:	e120      	b.n	8011932 <UART_SetConfig+0x5a6>
 80116f0:	697b      	ldr	r3, [r7, #20]
 80116f2:	681b      	ldr	r3, [r3, #0]
 80116f4:	4acb      	ldr	r2, [pc, #812]	@ (8011a24 <UART_SetConfig+0x698>)
 80116f6:	4293      	cmp	r3, r2
 80116f8:	d176      	bne.n	80117e8 <UART_SetConfig+0x45c>
 80116fa:	4bcb      	ldr	r3, [pc, #812]	@ (8011a28 <UART_SetConfig+0x69c>)
 80116fc:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80116fe:	f003 0338 	and.w	r3, r3, #56	@ 0x38
 8011702:	2b28      	cmp	r3, #40	@ 0x28
 8011704:	d86c      	bhi.n	80117e0 <UART_SetConfig+0x454>
 8011706:	a201      	add	r2, pc, #4	@ (adr r2, 801170c <UART_SetConfig+0x380>)
 8011708:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 801170c:	080117b1 	.word	0x080117b1
 8011710:	080117e1 	.word	0x080117e1
 8011714:	080117e1 	.word	0x080117e1
 8011718:	080117e1 	.word	0x080117e1
 801171c:	080117e1 	.word	0x080117e1
 8011720:	080117e1 	.word	0x080117e1
 8011724:	080117e1 	.word	0x080117e1
 8011728:	080117e1 	.word	0x080117e1
 801172c:	080117b9 	.word	0x080117b9
 8011730:	080117e1 	.word	0x080117e1
 8011734:	080117e1 	.word	0x080117e1
 8011738:	080117e1 	.word	0x080117e1
 801173c:	080117e1 	.word	0x080117e1
 8011740:	080117e1 	.word	0x080117e1
 8011744:	080117e1 	.word	0x080117e1
 8011748:	080117e1 	.word	0x080117e1
 801174c:	080117c1 	.word	0x080117c1
 8011750:	080117e1 	.word	0x080117e1
 8011754:	080117e1 	.word	0x080117e1
 8011758:	080117e1 	.word	0x080117e1
 801175c:	080117e1 	.word	0x080117e1
 8011760:	080117e1 	.word	0x080117e1
 8011764:	080117e1 	.word	0x080117e1
 8011768:	080117e1 	.word	0x080117e1
 801176c:	080117c9 	.word	0x080117c9
 8011770:	080117e1 	.word	0x080117e1
 8011774:	080117e1 	.word	0x080117e1
 8011778:	080117e1 	.word	0x080117e1
 801177c:	080117e1 	.word	0x080117e1
 8011780:	080117e1 	.word	0x080117e1
 8011784:	080117e1 	.word	0x080117e1
 8011788:	080117e1 	.word	0x080117e1
 801178c:	080117d1 	.word	0x080117d1
 8011790:	080117e1 	.word	0x080117e1
 8011794:	080117e1 	.word	0x080117e1
 8011798:	080117e1 	.word	0x080117e1
 801179c:	080117e1 	.word	0x080117e1
 80117a0:	080117e1 	.word	0x080117e1
 80117a4:	080117e1 	.word	0x080117e1
 80117a8:	080117e1 	.word	0x080117e1
 80117ac:	080117d9 	.word	0x080117d9
 80117b0:	2301      	movs	r3, #1
 80117b2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80117b6:	e0bc      	b.n	8011932 <UART_SetConfig+0x5a6>
 80117b8:	2304      	movs	r3, #4
 80117ba:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80117be:	e0b8      	b.n	8011932 <UART_SetConfig+0x5a6>
 80117c0:	2308      	movs	r3, #8
 80117c2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80117c6:	e0b4      	b.n	8011932 <UART_SetConfig+0x5a6>
 80117c8:	2310      	movs	r3, #16
 80117ca:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80117ce:	e0b0      	b.n	8011932 <UART_SetConfig+0x5a6>
 80117d0:	2320      	movs	r3, #32
 80117d2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80117d6:	e0ac      	b.n	8011932 <UART_SetConfig+0x5a6>
 80117d8:	2340      	movs	r3, #64	@ 0x40
 80117da:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80117de:	e0a8      	b.n	8011932 <UART_SetConfig+0x5a6>
 80117e0:	2380      	movs	r3, #128	@ 0x80
 80117e2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80117e6:	e0a4      	b.n	8011932 <UART_SetConfig+0x5a6>
 80117e8:	697b      	ldr	r3, [r7, #20]
 80117ea:	681b      	ldr	r3, [r3, #0]
 80117ec:	4a8f      	ldr	r2, [pc, #572]	@ (8011a2c <UART_SetConfig+0x6a0>)
 80117ee:	4293      	cmp	r3, r2
 80117f0:	d130      	bne.n	8011854 <UART_SetConfig+0x4c8>
 80117f2:	4b8d      	ldr	r3, [pc, #564]	@ (8011a28 <UART_SetConfig+0x69c>)
 80117f4:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80117f6:	f003 0307 	and.w	r3, r3, #7
 80117fa:	2b05      	cmp	r3, #5
 80117fc:	d826      	bhi.n	801184c <UART_SetConfig+0x4c0>
 80117fe:	a201      	add	r2, pc, #4	@ (adr r2, 8011804 <UART_SetConfig+0x478>)
 8011800:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8011804:	0801181d 	.word	0x0801181d
 8011808:	08011825 	.word	0x08011825
 801180c:	0801182d 	.word	0x0801182d
 8011810:	08011835 	.word	0x08011835
 8011814:	0801183d 	.word	0x0801183d
 8011818:	08011845 	.word	0x08011845
 801181c:	2300      	movs	r3, #0
 801181e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011822:	e086      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011824:	2304      	movs	r3, #4
 8011826:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801182a:	e082      	b.n	8011932 <UART_SetConfig+0x5a6>
 801182c:	2308      	movs	r3, #8
 801182e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011832:	e07e      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011834:	2310      	movs	r3, #16
 8011836:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801183a:	e07a      	b.n	8011932 <UART_SetConfig+0x5a6>
 801183c:	2320      	movs	r3, #32
 801183e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011842:	e076      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011844:	2340      	movs	r3, #64	@ 0x40
 8011846:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801184a:	e072      	b.n	8011932 <UART_SetConfig+0x5a6>
 801184c:	2380      	movs	r3, #128	@ 0x80
 801184e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011852:	e06e      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011854:	697b      	ldr	r3, [r7, #20]
 8011856:	681b      	ldr	r3, [r3, #0]
 8011858:	4a75      	ldr	r2, [pc, #468]	@ (8011a30 <UART_SetConfig+0x6a4>)
 801185a:	4293      	cmp	r3, r2
 801185c:	d130      	bne.n	80118c0 <UART_SetConfig+0x534>
 801185e:	4b72      	ldr	r3, [pc, #456]	@ (8011a28 <UART_SetConfig+0x69c>)
 8011860:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 8011862:	f003 0307 	and.w	r3, r3, #7
 8011866:	2b05      	cmp	r3, #5
 8011868:	d826      	bhi.n	80118b8 <UART_SetConfig+0x52c>
 801186a:	a201      	add	r2, pc, #4	@ (adr r2, 8011870 <UART_SetConfig+0x4e4>)
 801186c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8011870:	08011889 	.word	0x08011889
 8011874:	08011891 	.word	0x08011891
 8011878:	08011899 	.word	0x08011899
 801187c:	080118a1 	.word	0x080118a1
 8011880:	080118a9 	.word	0x080118a9
 8011884:	080118b1 	.word	0x080118b1
 8011888:	2300      	movs	r3, #0
 801188a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801188e:	e050      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011890:	2304      	movs	r3, #4
 8011892:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011896:	e04c      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011898:	2308      	movs	r3, #8
 801189a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801189e:	e048      	b.n	8011932 <UART_SetConfig+0x5a6>
 80118a0:	2310      	movs	r3, #16
 80118a2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80118a6:	e044      	b.n	8011932 <UART_SetConfig+0x5a6>
 80118a8:	2320      	movs	r3, #32
 80118aa:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80118ae:	e040      	b.n	8011932 <UART_SetConfig+0x5a6>
 80118b0:	2340      	movs	r3, #64	@ 0x40
 80118b2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80118b6:	e03c      	b.n	8011932 <UART_SetConfig+0x5a6>
 80118b8:	2380      	movs	r3, #128	@ 0x80
 80118ba:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80118be:	e038      	b.n	8011932 <UART_SetConfig+0x5a6>
 80118c0:	697b      	ldr	r3, [r7, #20]
 80118c2:	681b      	ldr	r3, [r3, #0]
 80118c4:	4a5b      	ldr	r2, [pc, #364]	@ (8011a34 <UART_SetConfig+0x6a8>)
 80118c6:	4293      	cmp	r3, r2
 80118c8:	d130      	bne.n	801192c <UART_SetConfig+0x5a0>
 80118ca:	4b57      	ldr	r3, [pc, #348]	@ (8011a28 <UART_SetConfig+0x69c>)
 80118cc:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80118ce:	f003 0307 	and.w	r3, r3, #7
 80118d2:	2b05      	cmp	r3, #5
 80118d4:	d826      	bhi.n	8011924 <UART_SetConfig+0x598>
 80118d6:	a201      	add	r2, pc, #4	@ (adr r2, 80118dc <UART_SetConfig+0x550>)
 80118d8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80118dc:	080118f5 	.word	0x080118f5
 80118e0:	080118fd 	.word	0x080118fd
 80118e4:	08011905 	.word	0x08011905
 80118e8:	0801190d 	.word	0x0801190d
 80118ec:	08011915 	.word	0x08011915
 80118f0:	0801191d 	.word	0x0801191d
 80118f4:	2302      	movs	r3, #2
 80118f6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 80118fa:	e01a      	b.n	8011932 <UART_SetConfig+0x5a6>
 80118fc:	2304      	movs	r3, #4
 80118fe:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011902:	e016      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011904:	2308      	movs	r3, #8
 8011906:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801190a:	e012      	b.n	8011932 <UART_SetConfig+0x5a6>
 801190c:	2310      	movs	r3, #16
 801190e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011912:	e00e      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011914:	2320      	movs	r3, #32
 8011916:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801191a:	e00a      	b.n	8011932 <UART_SetConfig+0x5a6>
 801191c:	2340      	movs	r3, #64	@ 0x40
 801191e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 8011922:	e006      	b.n	8011932 <UART_SetConfig+0x5a6>
 8011924:	2380      	movs	r3, #128	@ 0x80
 8011926:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
 801192a:	e002      	b.n	8011932 <UART_SetConfig+0x5a6>
 801192c:	2380      	movs	r3, #128	@ 0x80
 801192e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43

  /* Check LPUART instance */
  if (UART_INSTANCE_LOWPOWER(huart))
 8011932:	697b      	ldr	r3, [r7, #20]
 8011934:	681b      	ldr	r3, [r3, #0]
 8011936:	4a3f      	ldr	r2, [pc, #252]	@ (8011a34 <UART_SetConfig+0x6a8>)
 8011938:	4293      	cmp	r3, r2
 801193a:	f040 80f8 	bne.w	8011b2e <UART_SetConfig+0x7a2>
  {
    /* Retrieve frequency clock */
    switch (clocksource)
 801193e:	f897 3043 	ldrb.w	r3, [r7, #67]	@ 0x43
 8011942:	2b20      	cmp	r3, #32
 8011944:	dc46      	bgt.n	80119d4 <UART_SetConfig+0x648>
 8011946:	2b02      	cmp	r3, #2
 8011948:	f2c0 8082 	blt.w	8011a50 <UART_SetConfig+0x6c4>
 801194c:	3b02      	subs	r3, #2
 801194e:	2b1e      	cmp	r3, #30
 8011950:	d87e      	bhi.n	8011a50 <UART_SetConfig+0x6c4>
 8011952:	a201      	add	r2, pc, #4	@ (adr r2, 8011958 <UART_SetConfig+0x5cc>)
 8011954:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8011958:	080119db 	.word	0x080119db
 801195c:	08011a51 	.word	0x08011a51
 8011960:	080119e3 	.word	0x080119e3
 8011964:	08011a51 	.word	0x08011a51
 8011968:	08011a51 	.word	0x08011a51
 801196c:	08011a51 	.word	0x08011a51
 8011970:	080119f3 	.word	0x080119f3
 8011974:	08011a51 	.word	0x08011a51
 8011978:	08011a51 	.word	0x08011a51
 801197c:	08011a51 	.word	0x08011a51
 8011980:	08011a51 	.word	0x08011a51
 8011984:	08011a51 	.word	0x08011a51
 8011988:	08011a51 	.word	0x08011a51
 801198c:	08011a51 	.word	0x08011a51
 8011990:	08011a03 	.word	0x08011a03
 8011994:	08011a51 	.word	0x08011a51
 8011998:	08011a51 	.word	0x08011a51
 801199c:	08011a51 	.word	0x08011a51
 80119a0:	08011a51 	.word	0x08011a51
 80119a4:	08011a51 	.word	0x08011a51
 80119a8:	08011a51 	.word	0x08011a51
 80119ac:	08011a51 	.word	0x08011a51
 80119b0:	08011a51 	.word	0x08011a51
 80119b4:	08011a51 	.word	0x08011a51
 80119b8:	08011a51 	.word	0x08011a51
 80119bc:	08011a51 	.word	0x08011a51
 80119c0:	08011a51 	.word	0x08011a51
 80119c4:	08011a51 	.word	0x08011a51
 80119c8:	08011a51 	.word	0x08011a51
 80119cc:	08011a51 	.word	0x08011a51
 80119d0:	08011a43 	.word	0x08011a43
 80119d4:	2b40      	cmp	r3, #64	@ 0x40
 80119d6:	d037      	beq.n	8011a48 <UART_SetConfig+0x6bc>
 80119d8:	e03a      	b.n	8011a50 <UART_SetConfig+0x6c4>
    {
      case UART_CLOCKSOURCE_D3PCLK1:
        pclk = HAL_RCCEx_GetD3PCLK1Freq();
 80119da:	f7fc f9fd 	bl	800ddd8 <HAL_RCCEx_GetD3PCLK1Freq>
 80119de:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 80119e0:	e03c      	b.n	8011a5c <UART_SetConfig+0x6d0>
      case UART_CLOCKSOURCE_PLL2:
        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 80119e2:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 80119e6:	4618      	mov	r0, r3
 80119e8:	f7fc fa0c 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
        pclk = pll2_clocks.PLL2_Q_Frequency;
 80119ec:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80119ee:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 80119f0:	e034      	b.n	8011a5c <UART_SetConfig+0x6d0>
      case UART_CLOCKSOURCE_PLL3:
        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 80119f2:	f107 0318 	add.w	r3, r7, #24
 80119f6:	4618      	mov	r0, r3
 80119f8:	f7fc fb58 	bl	800e0ac <HAL_RCCEx_GetPLL3ClockFreq>
        pclk = pll3_clocks.PLL3_Q_Frequency;
 80119fc:	69fb      	ldr	r3, [r7, #28]
 80119fe:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011a00:	e02c      	b.n	8011a5c <UART_SetConfig+0x6d0>
      case UART_CLOCKSOURCE_HSI:
        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 8011a02:	4b09      	ldr	r3, [pc, #36]	@ (8011a28 <UART_SetConfig+0x69c>)
 8011a04:	681b      	ldr	r3, [r3, #0]
 8011a06:	f003 0320 	and.w	r3, r3, #32
 8011a0a:	2b00      	cmp	r3, #0
 8011a0c:	d016      	beq.n	8011a3c <UART_SetConfig+0x6b0>
        {
          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
 8011a0e:	4b06      	ldr	r3, [pc, #24]	@ (8011a28 <UART_SetConfig+0x69c>)
 8011a10:	681b      	ldr	r3, [r3, #0]
 8011a12:	08db      	lsrs	r3, r3, #3
 8011a14:	f003 0303 	and.w	r3, r3, #3
 8011a18:	4a07      	ldr	r2, [pc, #28]	@ (8011a38 <UART_SetConfig+0x6ac>)
 8011a1a:	fa22 f303 	lsr.w	r3, r2, r3
 8011a1e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          pclk = (uint32_t) HSI_VALUE;
        }
        break;
 8011a20:	e01c      	b.n	8011a5c <UART_SetConfig+0x6d0>
 8011a22:	bf00      	nop
 8011a24:	40011400 	.word	0x40011400
 8011a28:	58024400 	.word	0x58024400
 8011a2c:	40007800 	.word	0x40007800
 8011a30:	40007c00 	.word	0x40007c00
 8011a34:	58000c00 	.word	0x58000c00
 8011a38:	03d09000 	.word	0x03d09000
          pclk = (uint32_t) HSI_VALUE;
 8011a3c:	4b9d      	ldr	r3, [pc, #628]	@ (8011cb4 <UART_SetConfig+0x928>)
 8011a3e:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011a40:	e00c      	b.n	8011a5c <UART_SetConfig+0x6d0>
      case UART_CLOCKSOURCE_CSI:
        pclk = (uint32_t) CSI_VALUE;
 8011a42:	4b9d      	ldr	r3, [pc, #628]	@ (8011cb8 <UART_SetConfig+0x92c>)
 8011a44:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011a46:	e009      	b.n	8011a5c <UART_SetConfig+0x6d0>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 8011a48:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 8011a4c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011a4e:	e005      	b.n	8011a5c <UART_SetConfig+0x6d0>
      default:
        pclk = 0U;
 8011a50:	2300      	movs	r3, #0
 8011a52:	63fb      	str	r3, [r7, #60]	@ 0x3c
        ret = HAL_ERROR;
 8011a54:	2301      	movs	r3, #1
 8011a56:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
        break;
 8011a5a:	bf00      	nop
    }

    /* If proper clock source reported */
    if (pclk != 0U)
 8011a5c:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8011a5e:	2b00      	cmp	r3, #0
 8011a60:	f000 81de 	beq.w	8011e20 <UART_SetConfig+0xa94>
    {
      /* Compute clock after Prescaler */
      lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
 8011a64:	697b      	ldr	r3, [r7, #20]
 8011a66:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8011a68:	4a94      	ldr	r2, [pc, #592]	@ (8011cbc <UART_SetConfig+0x930>)
 8011a6a:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
 8011a6e:	461a      	mov	r2, r3
 8011a70:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8011a72:	fbb3 f3f2 	udiv	r3, r3, r2
 8011a76:	633b      	str	r3, [r7, #48]	@ 0x30

      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
 8011a78:	697b      	ldr	r3, [r7, #20]
 8011a7a:	685a      	ldr	r2, [r3, #4]
 8011a7c:	4613      	mov	r3, r2
 8011a7e:	005b      	lsls	r3, r3, #1
 8011a80:	4413      	add	r3, r2
 8011a82:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8011a84:	429a      	cmp	r2, r3
 8011a86:	d305      	bcc.n	8011a94 <UART_SetConfig+0x708>
          (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
 8011a88:	697b      	ldr	r3, [r7, #20]
 8011a8a:	685b      	ldr	r3, [r3, #4]
 8011a8c:	031b      	lsls	r3, r3, #12
      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
 8011a8e:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8011a90:	429a      	cmp	r2, r3
 8011a92:	d903      	bls.n	8011a9c <UART_SetConfig+0x710>
      {
        ret = HAL_ERROR;
 8011a94:	2301      	movs	r3, #1
 8011a96:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
 8011a9a:	e1c1      	b.n	8011e20 <UART_SetConfig+0xa94>
      }
      else
      {
        /* Check computed UsartDiv value is in allocated range
           (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
 8011a9c:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8011a9e:	2200      	movs	r2, #0
 8011aa0:	60bb      	str	r3, [r7, #8]
 8011aa2:	60fa      	str	r2, [r7, #12]
 8011aa4:	697b      	ldr	r3, [r7, #20]
 8011aa6:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8011aa8:	4a84      	ldr	r2, [pc, #528]	@ (8011cbc <UART_SetConfig+0x930>)
 8011aaa:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
 8011aae:	b29b      	uxth	r3, r3
 8011ab0:	2200      	movs	r2, #0
 8011ab2:	603b      	str	r3, [r7, #0]
 8011ab4:	607a      	str	r2, [r7, #4]
 8011ab6:	e9d7 2300 	ldrd	r2, r3, [r7]
 8011aba:	e9d7 0102 	ldrd	r0, r1, [r7, #8]
 8011abe:	f7ee fc5f 	bl	8000380 <__aeabi_uldivmod>
 8011ac2:	4602      	mov	r2, r0
 8011ac4:	460b      	mov	r3, r1
 8011ac6:	4610      	mov	r0, r2
 8011ac8:	4619      	mov	r1, r3
 8011aca:	f04f 0200 	mov.w	r2, #0
 8011ace:	f04f 0300 	mov.w	r3, #0
 8011ad2:	020b      	lsls	r3, r1, #8
 8011ad4:	ea43 6310 	orr.w	r3, r3, r0, lsr #24
 8011ad8:	0202      	lsls	r2, r0, #8
 8011ada:	6979      	ldr	r1, [r7, #20]
 8011adc:	6849      	ldr	r1, [r1, #4]
 8011ade:	0849      	lsrs	r1, r1, #1
 8011ae0:	2000      	movs	r0, #0
 8011ae2:	460c      	mov	r4, r1
 8011ae4:	4605      	mov	r5, r0
 8011ae6:	eb12 0804 	adds.w	r8, r2, r4
 8011aea:	eb43 0905 	adc.w	r9, r3, r5
 8011aee:	697b      	ldr	r3, [r7, #20]
 8011af0:	685b      	ldr	r3, [r3, #4]
 8011af2:	2200      	movs	r2, #0
 8011af4:	469a      	mov	sl, r3
 8011af6:	4693      	mov	fp, r2
 8011af8:	4652      	mov	r2, sl
 8011afa:	465b      	mov	r3, fp
 8011afc:	4640      	mov	r0, r8
 8011afe:	4649      	mov	r1, r9
 8011b00:	f7ee fc3e 	bl	8000380 <__aeabi_uldivmod>
 8011b04:	4602      	mov	r2, r0
 8011b06:	460b      	mov	r3, r1
 8011b08:	4613      	mov	r3, r2
 8011b0a:	63bb      	str	r3, [r7, #56]	@ 0x38
        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
 8011b0c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8011b0e:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 8011b12:	d308      	bcc.n	8011b26 <UART_SetConfig+0x79a>
 8011b14:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8011b16:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 8011b1a:	d204      	bcs.n	8011b26 <UART_SetConfig+0x79a>
        {
          huart->Instance->BRR = usartdiv;
 8011b1c:	697b      	ldr	r3, [r7, #20]
 8011b1e:	681b      	ldr	r3, [r3, #0]
 8011b20:	6bba      	ldr	r2, [r7, #56]	@ 0x38
 8011b22:	60da      	str	r2, [r3, #12]
 8011b24:	e17c      	b.n	8011e20 <UART_SetConfig+0xa94>
        }
        else
        {
          ret = HAL_ERROR;
 8011b26:	2301      	movs	r3, #1
 8011b28:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
 8011b2c:	e178      	b.n	8011e20 <UART_SetConfig+0xa94>
      } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
                (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
    } /* if (pclk != 0) */
  }
  /* Check UART Over Sampling to set Baud Rate Register */
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8011b2e:	697b      	ldr	r3, [r7, #20]
 8011b30:	69db      	ldr	r3, [r3, #28]
 8011b32:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
 8011b36:	f040 80c5 	bne.w	8011cc4 <UART_SetConfig+0x938>
  {
    switch (clocksource)
 8011b3a:	f897 3043 	ldrb.w	r3, [r7, #67]	@ 0x43
 8011b3e:	2b20      	cmp	r3, #32
 8011b40:	dc48      	bgt.n	8011bd4 <UART_SetConfig+0x848>
 8011b42:	2b00      	cmp	r3, #0
 8011b44:	db7b      	blt.n	8011c3e <UART_SetConfig+0x8b2>
 8011b46:	2b20      	cmp	r3, #32
 8011b48:	d879      	bhi.n	8011c3e <UART_SetConfig+0x8b2>
 8011b4a:	a201      	add	r2, pc, #4	@ (adr r2, 8011b50 <UART_SetConfig+0x7c4>)
 8011b4c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8011b50:	08011bdb 	.word	0x08011bdb
 8011b54:	08011be3 	.word	0x08011be3
 8011b58:	08011c3f 	.word	0x08011c3f
 8011b5c:	08011c3f 	.word	0x08011c3f
 8011b60:	08011beb 	.word	0x08011beb
 8011b64:	08011c3f 	.word	0x08011c3f
 8011b68:	08011c3f 	.word	0x08011c3f
 8011b6c:	08011c3f 	.word	0x08011c3f
 8011b70:	08011bfb 	.word	0x08011bfb
 8011b74:	08011c3f 	.word	0x08011c3f
 8011b78:	08011c3f 	.word	0x08011c3f
 8011b7c:	08011c3f 	.word	0x08011c3f
 8011b80:	08011c3f 	.word	0x08011c3f
 8011b84:	08011c3f 	.word	0x08011c3f
 8011b88:	08011c3f 	.word	0x08011c3f
 8011b8c:	08011c3f 	.word	0x08011c3f
 8011b90:	08011c0b 	.word	0x08011c0b
 8011b94:	08011c3f 	.word	0x08011c3f
 8011b98:	08011c3f 	.word	0x08011c3f
 8011b9c:	08011c3f 	.word	0x08011c3f
 8011ba0:	08011c3f 	.word	0x08011c3f
 8011ba4:	08011c3f 	.word	0x08011c3f
 8011ba8:	08011c3f 	.word	0x08011c3f
 8011bac:	08011c3f 	.word	0x08011c3f
 8011bb0:	08011c3f 	.word	0x08011c3f
 8011bb4:	08011c3f 	.word	0x08011c3f
 8011bb8:	08011c3f 	.word	0x08011c3f
 8011bbc:	08011c3f 	.word	0x08011c3f
 8011bc0:	08011c3f 	.word	0x08011c3f
 8011bc4:	08011c3f 	.word	0x08011c3f
 8011bc8:	08011c3f 	.word	0x08011c3f
 8011bcc:	08011c3f 	.word	0x08011c3f
 8011bd0:	08011c31 	.word	0x08011c31
 8011bd4:	2b40      	cmp	r3, #64	@ 0x40
 8011bd6:	d02e      	beq.n	8011c36 <UART_SetConfig+0x8aa>
 8011bd8:	e031      	b.n	8011c3e <UART_SetConfig+0x8b2>
    {
      case UART_CLOCKSOURCE_D2PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8011bda:	f7fa f921 	bl	800be20 <HAL_RCC_GetPCLK1Freq>
 8011bde:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 8011be0:	e033      	b.n	8011c4a <UART_SetConfig+0x8be>
      case UART_CLOCKSOURCE_D2PCLK2:
        pclk = HAL_RCC_GetPCLK2Freq();
 8011be2:	f7fa f933 	bl	800be4c <HAL_RCC_GetPCLK2Freq>
 8011be6:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 8011be8:	e02f      	b.n	8011c4a <UART_SetConfig+0x8be>
      case UART_CLOCKSOURCE_PLL2:
        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 8011bea:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 8011bee:	4618      	mov	r0, r3
 8011bf0:	f7fc f908 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
        pclk = pll2_clocks.PLL2_Q_Frequency;
 8011bf4:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8011bf6:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011bf8:	e027      	b.n	8011c4a <UART_SetConfig+0x8be>
      case UART_CLOCKSOURCE_PLL3:
        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 8011bfa:	f107 0318 	add.w	r3, r7, #24
 8011bfe:	4618      	mov	r0, r3
 8011c00:	f7fc fa54 	bl	800e0ac <HAL_RCCEx_GetPLL3ClockFreq>
        pclk = pll3_clocks.PLL3_Q_Frequency;
 8011c04:	69fb      	ldr	r3, [r7, #28]
 8011c06:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011c08:	e01f      	b.n	8011c4a <UART_SetConfig+0x8be>
      case UART_CLOCKSOURCE_HSI:
        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 8011c0a:	4b2d      	ldr	r3, [pc, #180]	@ (8011cc0 <UART_SetConfig+0x934>)
 8011c0c:	681b      	ldr	r3, [r3, #0]
 8011c0e:	f003 0320 	and.w	r3, r3, #32
 8011c12:	2b00      	cmp	r3, #0
 8011c14:	d009      	beq.n	8011c2a <UART_SetConfig+0x89e>
        {
          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
 8011c16:	4b2a      	ldr	r3, [pc, #168]	@ (8011cc0 <UART_SetConfig+0x934>)
 8011c18:	681b      	ldr	r3, [r3, #0]
 8011c1a:	08db      	lsrs	r3, r3, #3
 8011c1c:	f003 0303 	and.w	r3, r3, #3
 8011c20:	4a24      	ldr	r2, [pc, #144]	@ (8011cb4 <UART_SetConfig+0x928>)
 8011c22:	fa22 f303 	lsr.w	r3, r2, r3
 8011c26:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          pclk = (uint32_t) HSI_VALUE;
        }
        break;
 8011c28:	e00f      	b.n	8011c4a <UART_SetConfig+0x8be>
          pclk = (uint32_t) HSI_VALUE;
 8011c2a:	4b22      	ldr	r3, [pc, #136]	@ (8011cb4 <UART_SetConfig+0x928>)
 8011c2c:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011c2e:	e00c      	b.n	8011c4a <UART_SetConfig+0x8be>
      case UART_CLOCKSOURCE_CSI:
        pclk = (uint32_t) CSI_VALUE;
 8011c30:	4b21      	ldr	r3, [pc, #132]	@ (8011cb8 <UART_SetConfig+0x92c>)
 8011c32:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011c34:	e009      	b.n	8011c4a <UART_SetConfig+0x8be>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 8011c36:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 8011c3a:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011c3c:	e005      	b.n	8011c4a <UART_SetConfig+0x8be>
      default:
        pclk = 0U;
 8011c3e:	2300      	movs	r3, #0
 8011c40:	63fb      	str	r3, [r7, #60]	@ 0x3c
        ret = HAL_ERROR;
 8011c42:	2301      	movs	r3, #1
 8011c44:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
        break;
 8011c48:	bf00      	nop
    }

    /* USARTDIV must be greater than or equal to 0d16 */
    if (pclk != 0U)
 8011c4a:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8011c4c:	2b00      	cmp	r3, #0
 8011c4e:	f000 80e7 	beq.w	8011e20 <UART_SetConfig+0xa94>
    {
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
 8011c52:	697b      	ldr	r3, [r7, #20]
 8011c54:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8011c56:	4a19      	ldr	r2, [pc, #100]	@ (8011cbc <UART_SetConfig+0x930>)
 8011c58:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
 8011c5c:	461a      	mov	r2, r3
 8011c5e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8011c60:	fbb3 f3f2 	udiv	r3, r3, r2
 8011c64:	005a      	lsls	r2, r3, #1
 8011c66:	697b      	ldr	r3, [r7, #20]
 8011c68:	685b      	ldr	r3, [r3, #4]
 8011c6a:	085b      	lsrs	r3, r3, #1
 8011c6c:	441a      	add	r2, r3
 8011c6e:	697b      	ldr	r3, [r7, #20]
 8011c70:	685b      	ldr	r3, [r3, #4]
 8011c72:	fbb2 f3f3 	udiv	r3, r2, r3
 8011c76:	63bb      	str	r3, [r7, #56]	@ 0x38
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 8011c78:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8011c7a:	2b0f      	cmp	r3, #15
 8011c7c:	d916      	bls.n	8011cac <UART_SetConfig+0x920>
 8011c7e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8011c80:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 8011c84:	d212      	bcs.n	8011cac <UART_SetConfig+0x920>
      {
        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
 8011c86:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8011c88:	b29b      	uxth	r3, r3
 8011c8a:	f023 030f 	bic.w	r3, r3, #15
 8011c8e:	86fb      	strh	r3, [r7, #54]	@ 0x36
        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
 8011c90:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8011c92:	085b      	lsrs	r3, r3, #1
 8011c94:	b29b      	uxth	r3, r3
 8011c96:	f003 0307 	and.w	r3, r3, #7
 8011c9a:	b29a      	uxth	r2, r3
 8011c9c:	8efb      	ldrh	r3, [r7, #54]	@ 0x36
 8011c9e:	4313      	orrs	r3, r2
 8011ca0:	86fb      	strh	r3, [r7, #54]	@ 0x36
        huart->Instance->BRR = brrtemp;
 8011ca2:	697b      	ldr	r3, [r7, #20]
 8011ca4:	681b      	ldr	r3, [r3, #0]
 8011ca6:	8efa      	ldrh	r2, [r7, #54]	@ 0x36
 8011ca8:	60da      	str	r2, [r3, #12]
 8011caa:	e0b9      	b.n	8011e20 <UART_SetConfig+0xa94>
      }
      else
      {
        ret = HAL_ERROR;
 8011cac:	2301      	movs	r3, #1
 8011cae:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
 8011cb2:	e0b5      	b.n	8011e20 <UART_SetConfig+0xa94>
 8011cb4:	03d09000 	.word	0x03d09000
 8011cb8:	003d0900 	.word	0x003d0900
 8011cbc:	08018a40 	.word	0x08018a40
 8011cc0:	58024400 	.word	0x58024400
      }
    }
  }
  else
  {
    switch (clocksource)
 8011cc4:	f897 3043 	ldrb.w	r3, [r7, #67]	@ 0x43
 8011cc8:	2b20      	cmp	r3, #32
 8011cca:	dc49      	bgt.n	8011d60 <UART_SetConfig+0x9d4>
 8011ccc:	2b00      	cmp	r3, #0
 8011cce:	db7c      	blt.n	8011dca <UART_SetConfig+0xa3e>
 8011cd0:	2b20      	cmp	r3, #32
 8011cd2:	d87a      	bhi.n	8011dca <UART_SetConfig+0xa3e>
 8011cd4:	a201      	add	r2, pc, #4	@ (adr r2, 8011cdc <UART_SetConfig+0x950>)
 8011cd6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8011cda:	bf00      	nop
 8011cdc:	08011d67 	.word	0x08011d67
 8011ce0:	08011d6f 	.word	0x08011d6f
 8011ce4:	08011dcb 	.word	0x08011dcb
 8011ce8:	08011dcb 	.word	0x08011dcb
 8011cec:	08011d77 	.word	0x08011d77
 8011cf0:	08011dcb 	.word	0x08011dcb
 8011cf4:	08011dcb 	.word	0x08011dcb
 8011cf8:	08011dcb 	.word	0x08011dcb
 8011cfc:	08011d87 	.word	0x08011d87
 8011d00:	08011dcb 	.word	0x08011dcb
 8011d04:	08011dcb 	.word	0x08011dcb
 8011d08:	08011dcb 	.word	0x08011dcb
 8011d0c:	08011dcb 	.word	0x08011dcb
 8011d10:	08011dcb 	.word	0x08011dcb
 8011d14:	08011dcb 	.word	0x08011dcb
 8011d18:	08011dcb 	.word	0x08011dcb
 8011d1c:	08011d97 	.word	0x08011d97
 8011d20:	08011dcb 	.word	0x08011dcb
 8011d24:	08011dcb 	.word	0x08011dcb
 8011d28:	08011dcb 	.word	0x08011dcb
 8011d2c:	08011dcb 	.word	0x08011dcb
 8011d30:	08011dcb 	.word	0x08011dcb
 8011d34:	08011dcb 	.word	0x08011dcb
 8011d38:	08011dcb 	.word	0x08011dcb
 8011d3c:	08011dcb 	.word	0x08011dcb
 8011d40:	08011dcb 	.word	0x08011dcb
 8011d44:	08011dcb 	.word	0x08011dcb
 8011d48:	08011dcb 	.word	0x08011dcb
 8011d4c:	08011dcb 	.word	0x08011dcb
 8011d50:	08011dcb 	.word	0x08011dcb
 8011d54:	08011dcb 	.word	0x08011dcb
 8011d58:	08011dcb 	.word	0x08011dcb
 8011d5c:	08011dbd 	.word	0x08011dbd
 8011d60:	2b40      	cmp	r3, #64	@ 0x40
 8011d62:	d02e      	beq.n	8011dc2 <UART_SetConfig+0xa36>
 8011d64:	e031      	b.n	8011dca <UART_SetConfig+0xa3e>
    {
      case UART_CLOCKSOURCE_D2PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8011d66:	f7fa f85b 	bl	800be20 <HAL_RCC_GetPCLK1Freq>
 8011d6a:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 8011d6c:	e033      	b.n	8011dd6 <UART_SetConfig+0xa4a>
      case UART_CLOCKSOURCE_D2PCLK2:
        pclk = HAL_RCC_GetPCLK2Freq();
 8011d6e:	f7fa f86d 	bl	800be4c <HAL_RCC_GetPCLK2Freq>
 8011d72:	63f8      	str	r0, [r7, #60]	@ 0x3c
        break;
 8011d74:	e02f      	b.n	8011dd6 <UART_SetConfig+0xa4a>
      case UART_CLOCKSOURCE_PLL2:
        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
 8011d76:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 8011d7a:	4618      	mov	r0, r3
 8011d7c:	f7fc f842 	bl	800de04 <HAL_RCCEx_GetPLL2ClockFreq>
        pclk = pll2_clocks.PLL2_Q_Frequency;
 8011d80:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8011d82:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011d84:	e027      	b.n	8011dd6 <UART_SetConfig+0xa4a>
      case UART_CLOCKSOURCE_PLL3:
        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
 8011d86:	f107 0318 	add.w	r3, r7, #24
 8011d8a:	4618      	mov	r0, r3
 8011d8c:	f7fc f98e 	bl	800e0ac <HAL_RCCEx_GetPLL3ClockFreq>
        pclk = pll3_clocks.PLL3_Q_Frequency;
 8011d90:	69fb      	ldr	r3, [r7, #28]
 8011d92:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011d94:	e01f      	b.n	8011dd6 <UART_SetConfig+0xa4a>
      case UART_CLOCKSOURCE_HSI:
        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
 8011d96:	4b2d      	ldr	r3, [pc, #180]	@ (8011e4c <UART_SetConfig+0xac0>)
 8011d98:	681b      	ldr	r3, [r3, #0]
 8011d9a:	f003 0320 	and.w	r3, r3, #32
 8011d9e:	2b00      	cmp	r3, #0
 8011da0:	d009      	beq.n	8011db6 <UART_SetConfig+0xa2a>
        {
          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
 8011da2:	4b2a      	ldr	r3, [pc, #168]	@ (8011e4c <UART_SetConfig+0xac0>)
 8011da4:	681b      	ldr	r3, [r3, #0]
 8011da6:	08db      	lsrs	r3, r3, #3
 8011da8:	f003 0303 	and.w	r3, r3, #3
 8011dac:	4a28      	ldr	r2, [pc, #160]	@ (8011e50 <UART_SetConfig+0xac4>)
 8011dae:	fa22 f303 	lsr.w	r3, r2, r3
 8011db2:	63fb      	str	r3, [r7, #60]	@ 0x3c
        }
        else
        {
          pclk = (uint32_t) HSI_VALUE;
        }
        break;
 8011db4:	e00f      	b.n	8011dd6 <UART_SetConfig+0xa4a>
          pclk = (uint32_t) HSI_VALUE;
 8011db6:	4b26      	ldr	r3, [pc, #152]	@ (8011e50 <UART_SetConfig+0xac4>)
 8011db8:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011dba:	e00c      	b.n	8011dd6 <UART_SetConfig+0xa4a>
      case UART_CLOCKSOURCE_CSI:
        pclk = (uint32_t) CSI_VALUE;
 8011dbc:	4b25      	ldr	r3, [pc, #148]	@ (8011e54 <UART_SetConfig+0xac8>)
 8011dbe:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011dc0:	e009      	b.n	8011dd6 <UART_SetConfig+0xa4a>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 8011dc2:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 8011dc6:	63fb      	str	r3, [r7, #60]	@ 0x3c
        break;
 8011dc8:	e005      	b.n	8011dd6 <UART_SetConfig+0xa4a>
      default:
        pclk = 0U;
 8011dca:	2300      	movs	r3, #0
 8011dcc:	63fb      	str	r3, [r7, #60]	@ 0x3c
        ret = HAL_ERROR;
 8011dce:	2301      	movs	r3, #1
 8011dd0:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
        break;
 8011dd4:	bf00      	nop
    }

    if (pclk != 0U)
 8011dd6:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8011dd8:	2b00      	cmp	r3, #0
 8011dda:	d021      	beq.n	8011e20 <UART_SetConfig+0xa94>
    {
      /* USARTDIV must be greater than or equal to 0d16 */
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
 8011ddc:	697b      	ldr	r3, [r7, #20]
 8011dde:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8011de0:	4a1d      	ldr	r2, [pc, #116]	@ (8011e58 <UART_SetConfig+0xacc>)
 8011de2:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
 8011de6:	461a      	mov	r2, r3
 8011de8:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8011dea:	fbb3 f2f2 	udiv	r2, r3, r2
 8011dee:	697b      	ldr	r3, [r7, #20]
 8011df0:	685b      	ldr	r3, [r3, #4]
 8011df2:	085b      	lsrs	r3, r3, #1
 8011df4:	441a      	add	r2, r3
 8011df6:	697b      	ldr	r3, [r7, #20]
 8011df8:	685b      	ldr	r3, [r3, #4]
 8011dfa:	fbb2 f3f3 	udiv	r3, r2, r3
 8011dfe:	63bb      	str	r3, [r7, #56]	@ 0x38
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 8011e00:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8011e02:	2b0f      	cmp	r3, #15
 8011e04:	d909      	bls.n	8011e1a <UART_SetConfig+0xa8e>
 8011e06:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8011e08:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 8011e0c:	d205      	bcs.n	8011e1a <UART_SetConfig+0xa8e>
      {
        huart->Instance->BRR = (uint16_t)usartdiv;
 8011e0e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8011e10:	b29a      	uxth	r2, r3
 8011e12:	697b      	ldr	r3, [r7, #20]
 8011e14:	681b      	ldr	r3, [r3, #0]
 8011e16:	60da      	str	r2, [r3, #12]
 8011e18:	e002      	b.n	8011e20 <UART_SetConfig+0xa94>
      }
      else
      {
        ret = HAL_ERROR;
 8011e1a:	2301      	movs	r3, #1
 8011e1c:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
      }
    }
  }

  /* Initialize the number of data to process during RX/TX ISR execution */
  huart->NbTxDataToProcess = 1;
 8011e20:	697b      	ldr	r3, [r7, #20]
 8011e22:	2201      	movs	r2, #1
 8011e24:	f8a3 206a 	strh.w	r2, [r3, #106]	@ 0x6a
  huart->NbRxDataToProcess = 1;
 8011e28:	697b      	ldr	r3, [r7, #20]
 8011e2a:	2201      	movs	r2, #1
 8011e2c:	f8a3 2068 	strh.w	r2, [r3, #104]	@ 0x68

  /* Clear ISR function pointers */
  huart->RxISR = NULL;
 8011e30:	697b      	ldr	r3, [r7, #20]
 8011e32:	2200      	movs	r2, #0
 8011e34:	675a      	str	r2, [r3, #116]	@ 0x74
  huart->TxISR = NULL;
 8011e36:	697b      	ldr	r3, [r7, #20]
 8011e38:	2200      	movs	r2, #0
 8011e3a:	679a      	str	r2, [r3, #120]	@ 0x78

  return ret;
 8011e3c:	f897 3042 	ldrb.w	r3, [r7, #66]	@ 0x42
}
 8011e40:	4618      	mov	r0, r3
 8011e42:	3748      	adds	r7, #72	@ 0x48
 8011e44:	46bd      	mov	sp, r7
 8011e46:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 8011e4a:	bf00      	nop
 8011e4c:	58024400 	.word	0x58024400
 8011e50:	03d09000 	.word	0x03d09000
 8011e54:	003d0900 	.word	0x003d0900
 8011e58:	08018a40 	.word	0x08018a40

08011e5c <UART_AdvFeatureConfig>:
  * @brief Configure the UART peripheral advanced features.
  * @param huart UART handle.
  * @retval None
  */
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
 8011e5c:	b480      	push	{r7}
 8011e5e:	b083      	sub	sp, #12
 8011e60:	af00      	add	r7, sp, #0
 8011e62:	6078      	str	r0, [r7, #4]
  /* Check whether the set of advanced features to configure is properly set */
  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));

  /* if required, configure RX/TX pins swap */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
 8011e64:	687b      	ldr	r3, [r7, #4]
 8011e66:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8011e68:	f003 0308 	and.w	r3, r3, #8
 8011e6c:	2b00      	cmp	r3, #0
 8011e6e:	d00a      	beq.n	8011e86 <UART_AdvFeatureConfig+0x2a>
  {
    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
 8011e70:	687b      	ldr	r3, [r7, #4]
 8011e72:	681b      	ldr	r3, [r3, #0]
 8011e74:	685b      	ldr	r3, [r3, #4]
 8011e76:	f423 4100 	bic.w	r1, r3, #32768	@ 0x8000
 8011e7a:	687b      	ldr	r3, [r7, #4]
 8011e7c:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 8011e7e:	687b      	ldr	r3, [r7, #4]
 8011e80:	681b      	ldr	r3, [r3, #0]
 8011e82:	430a      	orrs	r2, r1
 8011e84:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure TX pin active level inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
 8011e86:	687b      	ldr	r3, [r7, #4]
 8011e88:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8011e8a:	f003 0301 	and.w	r3, r3, #1
 8011e8e:	2b00      	cmp	r3, #0
 8011e90:	d00a      	beq.n	8011ea8 <UART_AdvFeatureConfig+0x4c>
  {
    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
 8011e92:	687b      	ldr	r3, [r7, #4]
 8011e94:	681b      	ldr	r3, [r3, #0]
 8011e96:	685b      	ldr	r3, [r3, #4]
 8011e98:	f423 3100 	bic.w	r1, r3, #131072	@ 0x20000
 8011e9c:	687b      	ldr	r3, [r7, #4]
 8011e9e:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8011ea0:	687b      	ldr	r3, [r7, #4]
 8011ea2:	681b      	ldr	r3, [r3, #0]
 8011ea4:	430a      	orrs	r2, r1
 8011ea6:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX pin active level inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
 8011ea8:	687b      	ldr	r3, [r7, #4]
 8011eaa:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8011eac:	f003 0302 	and.w	r3, r3, #2
 8011eb0:	2b00      	cmp	r3, #0
 8011eb2:	d00a      	beq.n	8011eca <UART_AdvFeatureConfig+0x6e>
  {
    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
 8011eb4:	687b      	ldr	r3, [r7, #4]
 8011eb6:	681b      	ldr	r3, [r3, #0]
 8011eb8:	685b      	ldr	r3, [r3, #4]
 8011eba:	f423 3180 	bic.w	r1, r3, #65536	@ 0x10000
 8011ebe:	687b      	ldr	r3, [r7, #4]
 8011ec0:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
 8011ec2:	687b      	ldr	r3, [r7, #4]
 8011ec4:	681b      	ldr	r3, [r3, #0]
 8011ec6:	430a      	orrs	r2, r1
 8011ec8:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure data inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
 8011eca:	687b      	ldr	r3, [r7, #4]
 8011ecc:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8011ece:	f003 0304 	and.w	r3, r3, #4
 8011ed2:	2b00      	cmp	r3, #0
 8011ed4:	d00a      	beq.n	8011eec <UART_AdvFeatureConfig+0x90>
  {
    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
 8011ed6:	687b      	ldr	r3, [r7, #4]
 8011ed8:	681b      	ldr	r3, [r3, #0]
 8011eda:	685b      	ldr	r3, [r3, #4]
 8011edc:	f423 2180 	bic.w	r1, r3, #262144	@ 0x40000
 8011ee0:	687b      	ldr	r3, [r7, #4]
 8011ee2:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 8011ee4:	687b      	ldr	r3, [r7, #4]
 8011ee6:	681b      	ldr	r3, [r3, #0]
 8011ee8:	430a      	orrs	r2, r1
 8011eea:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX overrun detection disabling */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
 8011eec:	687b      	ldr	r3, [r7, #4]
 8011eee:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8011ef0:	f003 0310 	and.w	r3, r3, #16
 8011ef4:	2b00      	cmp	r3, #0
 8011ef6:	d00a      	beq.n	8011f0e <UART_AdvFeatureConfig+0xb2>
  {
    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
 8011ef8:	687b      	ldr	r3, [r7, #4]
 8011efa:	681b      	ldr	r3, [r3, #0]
 8011efc:	689b      	ldr	r3, [r3, #8]
 8011efe:	f423 5180 	bic.w	r1, r3, #4096	@ 0x1000
 8011f02:	687b      	ldr	r3, [r7, #4]
 8011f04:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 8011f06:	687b      	ldr	r3, [r7, #4]
 8011f08:	681b      	ldr	r3, [r3, #0]
 8011f0a:	430a      	orrs	r2, r1
 8011f0c:	609a      	str	r2, [r3, #8]
  }

  /* if required, configure DMA disabling on reception error */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
 8011f0e:	687b      	ldr	r3, [r7, #4]
 8011f10:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8011f12:	f003 0320 	and.w	r3, r3, #32
 8011f16:	2b00      	cmp	r3, #0
 8011f18:	d00a      	beq.n	8011f30 <UART_AdvFeatureConfig+0xd4>
  {
    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
 8011f1a:	687b      	ldr	r3, [r7, #4]
 8011f1c:	681b      	ldr	r3, [r3, #0]
 8011f1e:	689b      	ldr	r3, [r3, #8]
 8011f20:	f423 5100 	bic.w	r1, r3, #8192	@ 0x2000
 8011f24:	687b      	ldr	r3, [r7, #4]
 8011f26:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
 8011f28:	687b      	ldr	r3, [r7, #4]
 8011f2a:	681b      	ldr	r3, [r3, #0]
 8011f2c:	430a      	orrs	r2, r1
 8011f2e:	609a      	str	r2, [r3, #8]
  }

  /* if required, configure auto Baud rate detection scheme */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
 8011f30:	687b      	ldr	r3, [r7, #4]
 8011f32:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8011f34:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8011f38:	2b00      	cmp	r3, #0
 8011f3a:	d01a      	beq.n	8011f72 <UART_AdvFeatureConfig+0x116>
  {
    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
 8011f3c:	687b      	ldr	r3, [r7, #4]
 8011f3e:	681b      	ldr	r3, [r3, #0]
 8011f40:	685b      	ldr	r3, [r3, #4]
 8011f42:	f423 1180 	bic.w	r1, r3, #1048576	@ 0x100000
 8011f46:	687b      	ldr	r3, [r7, #4]
 8011f48:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
 8011f4a:	687b      	ldr	r3, [r7, #4]
 8011f4c:	681b      	ldr	r3, [r3, #0]
 8011f4e:	430a      	orrs	r2, r1
 8011f50:	605a      	str	r2, [r3, #4]
    /* set auto Baudrate detection parameters if detection is enabled */
    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
 8011f52:	687b      	ldr	r3, [r7, #4]
 8011f54:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 8011f56:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 8011f5a:	d10a      	bne.n	8011f72 <UART_AdvFeatureConfig+0x116>
    {
      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
 8011f5c:	687b      	ldr	r3, [r7, #4]
 8011f5e:	681b      	ldr	r3, [r3, #0]
 8011f60:	685b      	ldr	r3, [r3, #4]
 8011f62:	f423 01c0 	bic.w	r1, r3, #6291456	@ 0x600000
 8011f66:	687b      	ldr	r3, [r7, #4]
 8011f68:	6c9a      	ldr	r2, [r3, #72]	@ 0x48
 8011f6a:	687b      	ldr	r3, [r7, #4]
 8011f6c:	681b      	ldr	r3, [r3, #0]
 8011f6e:	430a      	orrs	r2, r1
 8011f70:	605a      	str	r2, [r3, #4]
    }
  }

  /* if required, configure MSB first on communication line */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
 8011f72:	687b      	ldr	r3, [r7, #4]
 8011f74:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8011f76:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8011f7a:	2b00      	cmp	r3, #0
 8011f7c:	d00a      	beq.n	8011f94 <UART_AdvFeatureConfig+0x138>
  {
    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
 8011f7e:	687b      	ldr	r3, [r7, #4]
 8011f80:	681b      	ldr	r3, [r3, #0]
 8011f82:	685b      	ldr	r3, [r3, #4]
 8011f84:	f423 2100 	bic.w	r1, r3, #524288	@ 0x80000
 8011f88:	687b      	ldr	r3, [r7, #4]
 8011f8a:	6cda      	ldr	r2, [r3, #76]	@ 0x4c
 8011f8c:	687b      	ldr	r3, [r7, #4]
 8011f8e:	681b      	ldr	r3, [r3, #0]
 8011f90:	430a      	orrs	r2, r1
 8011f92:	605a      	str	r2, [r3, #4]
  }
}
 8011f94:	bf00      	nop
 8011f96:	370c      	adds	r7, #12
 8011f98:	46bd      	mov	sp, r7
 8011f9a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8011f9e:	4770      	bx	lr

08011fa0 <UART_CheckIdleState>:
  * @brief Check the UART Idle State.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
 8011fa0:	b580      	push	{r7, lr}
 8011fa2:	b098      	sub	sp, #96	@ 0x60
 8011fa4:	af02      	add	r7, sp, #8
 8011fa6:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;

  /* Initialize the UART ErrorCode */
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8011fa8:	687b      	ldr	r3, [r7, #4]
 8011faa:	2200      	movs	r2, #0
 8011fac:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90

  /* Init tickstart for timeout management */
  tickstart = HAL_GetTick();
 8011fb0:	f7f3 fa44 	bl	800543c <HAL_GetTick>
 8011fb4:	6578      	str	r0, [r7, #84]	@ 0x54

  /* Check if the Transmitter is enabled */
  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
 8011fb6:	687b      	ldr	r3, [r7, #4]
 8011fb8:	681b      	ldr	r3, [r3, #0]
 8011fba:	681b      	ldr	r3, [r3, #0]
 8011fbc:	f003 0308 	and.w	r3, r3, #8
 8011fc0:	2b08      	cmp	r3, #8
 8011fc2:	d12f      	bne.n	8012024 <UART_CheckIdleState+0x84>
  {
    /* Wait until TEACK flag is set */
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 8011fc4:	f06f 437e 	mvn.w	r3, #4261412864	@ 0xfe000000
 8011fc8:	9300      	str	r3, [sp, #0]
 8011fca:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 8011fcc:	2200      	movs	r2, #0
 8011fce:	f44f 1100 	mov.w	r1, #2097152	@ 0x200000
 8011fd2:	6878      	ldr	r0, [r7, #4]
 8011fd4:	f000 f88e 	bl	80120f4 <UART_WaitOnFlagUntilTimeout>
 8011fd8:	4603      	mov	r3, r0
 8011fda:	2b00      	cmp	r3, #0
 8011fdc:	d022      	beq.n	8012024 <UART_CheckIdleState+0x84>
    {
      /* Disable TXE interrupt for the interrupt process */
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
 8011fde:	687b      	ldr	r3, [r7, #4]
 8011fe0:	681b      	ldr	r3, [r3, #0]
 8011fe2:	63bb      	str	r3, [r7, #56]	@ 0x38
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8011fe4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8011fe6:	e853 3f00 	ldrex	r3, [r3]
 8011fea:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 8011fec:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8011fee:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 8011ff2:	653b      	str	r3, [r7, #80]	@ 0x50
 8011ff4:	687b      	ldr	r3, [r7, #4]
 8011ff6:	681b      	ldr	r3, [r3, #0]
 8011ff8:	461a      	mov	r2, r3
 8011ffa:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 8011ffc:	647b      	str	r3, [r7, #68]	@ 0x44
 8011ffe:	643a      	str	r2, [r7, #64]	@ 0x40
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012000:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 8012002:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 8012004:	e841 2300 	strex	r3, r2, [r1]
 8012008:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 801200a:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 801200c:	2b00      	cmp	r3, #0
 801200e:	d1e6      	bne.n	8011fde <UART_CheckIdleState+0x3e>

      huart->gState = HAL_UART_STATE_READY;
 8012010:	687b      	ldr	r3, [r7, #4]
 8012012:	2220      	movs	r2, #32
 8012014:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

      __HAL_UNLOCK(huart);
 8012018:	687b      	ldr	r3, [r7, #4]
 801201a:	2200      	movs	r2, #0
 801201c:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

      /* Timeout occurred */
      return HAL_TIMEOUT;
 8012020:	2303      	movs	r3, #3
 8012022:	e063      	b.n	80120ec <UART_CheckIdleState+0x14c>
    }
  }

  /* Check if the Receiver is enabled */
  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
 8012024:	687b      	ldr	r3, [r7, #4]
 8012026:	681b      	ldr	r3, [r3, #0]
 8012028:	681b      	ldr	r3, [r3, #0]
 801202a:	f003 0304 	and.w	r3, r3, #4
 801202e:	2b04      	cmp	r3, #4
 8012030:	d149      	bne.n	80120c6 <UART_CheckIdleState+0x126>
  {
    /* Wait until REACK flag is set */
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 8012032:	f06f 437e 	mvn.w	r3, #4261412864	@ 0xfe000000
 8012036:	9300      	str	r3, [sp, #0]
 8012038:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 801203a:	2200      	movs	r2, #0
 801203c:	f44f 0180 	mov.w	r1, #4194304	@ 0x400000
 8012040:	6878      	ldr	r0, [r7, #4]
 8012042:	f000 f857 	bl	80120f4 <UART_WaitOnFlagUntilTimeout>
 8012046:	4603      	mov	r3, r0
 8012048:	2b00      	cmp	r3, #0
 801204a:	d03c      	beq.n	80120c6 <UART_CheckIdleState+0x126>
    {
      /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
      interrupts for the interrupt process */
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 801204c:	687b      	ldr	r3, [r7, #4]
 801204e:	681b      	ldr	r3, [r3, #0]
 8012050:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012052:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8012054:	e853 3f00 	ldrex	r3, [r3]
 8012058:	623b      	str	r3, [r7, #32]
   return(result);
 801205a:	6a3b      	ldr	r3, [r7, #32]
 801205c:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 8012060:	64fb      	str	r3, [r7, #76]	@ 0x4c
 8012062:	687b      	ldr	r3, [r7, #4]
 8012064:	681b      	ldr	r3, [r3, #0]
 8012066:	461a      	mov	r2, r3
 8012068:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 801206a:	633b      	str	r3, [r7, #48]	@ 0x30
 801206c:	62fa      	str	r2, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 801206e:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 8012070:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8012072:	e841 2300 	strex	r3, r2, [r1]
 8012076:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 8012078:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 801207a:	2b00      	cmp	r3, #0
 801207c:	d1e6      	bne.n	801204c <UART_CheckIdleState+0xac>
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 801207e:	687b      	ldr	r3, [r7, #4]
 8012080:	681b      	ldr	r3, [r3, #0]
 8012082:	3308      	adds	r3, #8
 8012084:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012086:	693b      	ldr	r3, [r7, #16]
 8012088:	e853 3f00 	ldrex	r3, [r3]
 801208c:	60fb      	str	r3, [r7, #12]
   return(result);
 801208e:	68fb      	ldr	r3, [r7, #12]
 8012090:	f023 0301 	bic.w	r3, r3, #1
 8012094:	64bb      	str	r3, [r7, #72]	@ 0x48
 8012096:	687b      	ldr	r3, [r7, #4]
 8012098:	681b      	ldr	r3, [r3, #0]
 801209a:	3308      	adds	r3, #8
 801209c:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 801209e:	61fa      	str	r2, [r7, #28]
 80120a0:	61bb      	str	r3, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80120a2:	69b9      	ldr	r1, [r7, #24]
 80120a4:	69fa      	ldr	r2, [r7, #28]
 80120a6:	e841 2300 	strex	r3, r2, [r1]
 80120aa:	617b      	str	r3, [r7, #20]
   return(result);
 80120ac:	697b      	ldr	r3, [r7, #20]
 80120ae:	2b00      	cmp	r3, #0
 80120b0:	d1e5      	bne.n	801207e <UART_CheckIdleState+0xde>

      huart->RxState = HAL_UART_STATE_READY;
 80120b2:	687b      	ldr	r3, [r7, #4]
 80120b4:	2220      	movs	r2, #32
 80120b6:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c

      __HAL_UNLOCK(huart);
 80120ba:	687b      	ldr	r3, [r7, #4]
 80120bc:	2200      	movs	r2, #0
 80120be:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

      /* Timeout occurred */
      return HAL_TIMEOUT;
 80120c2:	2303      	movs	r3, #3
 80120c4:	e012      	b.n	80120ec <UART_CheckIdleState+0x14c>
    }
  }

  /* Initialize the UART State */
  huart->gState = HAL_UART_STATE_READY;
 80120c6:	687b      	ldr	r3, [r7, #4]
 80120c8:	2220      	movs	r2, #32
 80120ca:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
  huart->RxState = HAL_UART_STATE_READY;
 80120ce:	687b      	ldr	r3, [r7, #4]
 80120d0:	2220      	movs	r2, #32
 80120d2:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 80120d6:	687b      	ldr	r3, [r7, #4]
 80120d8:	2200      	movs	r2, #0
 80120da:	66da      	str	r2, [r3, #108]	@ 0x6c
  huart->RxEventType = HAL_UART_RXEVENT_TC;
 80120dc:	687b      	ldr	r3, [r7, #4]
 80120de:	2200      	movs	r2, #0
 80120e0:	671a      	str	r2, [r3, #112]	@ 0x70

  __HAL_UNLOCK(huart);
 80120e2:	687b      	ldr	r3, [r7, #4]
 80120e4:	2200      	movs	r2, #0
 80120e6:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  return HAL_OK;
 80120ea:	2300      	movs	r3, #0
}
 80120ec:	4618      	mov	r0, r3
 80120ee:	3758      	adds	r7, #88	@ 0x58
 80120f0:	46bd      	mov	sp, r7
 80120f2:	bd80      	pop	{r7, pc}

080120f4 <UART_WaitOnFlagUntilTimeout>:
  * @param Timeout   Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
                                              uint32_t Tickstart, uint32_t Timeout)
{
 80120f4:	b580      	push	{r7, lr}
 80120f6:	b084      	sub	sp, #16
 80120f8:	af00      	add	r7, sp, #0
 80120fa:	60f8      	str	r0, [r7, #12]
 80120fc:	60b9      	str	r1, [r7, #8]
 80120fe:	603b      	str	r3, [r7, #0]
 8012100:	4613      	mov	r3, r2
 8012102:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is set */
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8012104:	e04f      	b.n	80121a6 <UART_WaitOnFlagUntilTimeout+0xb2>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8012106:	69bb      	ldr	r3, [r7, #24]
 8012108:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 801210c:	d04b      	beq.n	80121a6 <UART_WaitOnFlagUntilTimeout+0xb2>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 801210e:	f7f3 f995 	bl	800543c <HAL_GetTick>
 8012112:	4602      	mov	r2, r0
 8012114:	683b      	ldr	r3, [r7, #0]
 8012116:	1ad3      	subs	r3, r2, r3
 8012118:	69ba      	ldr	r2, [r7, #24]
 801211a:	429a      	cmp	r2, r3
 801211c:	d302      	bcc.n	8012124 <UART_WaitOnFlagUntilTimeout+0x30>
 801211e:	69bb      	ldr	r3, [r7, #24]
 8012120:	2b00      	cmp	r3, #0
 8012122:	d101      	bne.n	8012128 <UART_WaitOnFlagUntilTimeout+0x34>
      {

        return HAL_TIMEOUT;
 8012124:	2303      	movs	r3, #3
 8012126:	e04e      	b.n	80121c6 <UART_WaitOnFlagUntilTimeout+0xd2>
      }

      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
 8012128:	68fb      	ldr	r3, [r7, #12]
 801212a:	681b      	ldr	r3, [r3, #0]
 801212c:	681b      	ldr	r3, [r3, #0]
 801212e:	f003 0304 	and.w	r3, r3, #4
 8012132:	2b00      	cmp	r3, #0
 8012134:	d037      	beq.n	80121a6 <UART_WaitOnFlagUntilTimeout+0xb2>
 8012136:	68bb      	ldr	r3, [r7, #8]
 8012138:	2b80      	cmp	r3, #128	@ 0x80
 801213a:	d034      	beq.n	80121a6 <UART_WaitOnFlagUntilTimeout+0xb2>
 801213c:	68bb      	ldr	r3, [r7, #8]
 801213e:	2b40      	cmp	r3, #64	@ 0x40
 8012140:	d031      	beq.n	80121a6 <UART_WaitOnFlagUntilTimeout+0xb2>
      {
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
 8012142:	68fb      	ldr	r3, [r7, #12]
 8012144:	681b      	ldr	r3, [r3, #0]
 8012146:	69db      	ldr	r3, [r3, #28]
 8012148:	f003 0308 	and.w	r3, r3, #8
 801214c:	2b08      	cmp	r3, #8
 801214e:	d110      	bne.n	8012172 <UART_WaitOnFlagUntilTimeout+0x7e>
        {
          /* Clear Overrun Error flag*/
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 8012150:	68fb      	ldr	r3, [r7, #12]
 8012152:	681b      	ldr	r3, [r3, #0]
 8012154:	2208      	movs	r2, #8
 8012156:	621a      	str	r2, [r3, #32]

          /* Blocking error : transfer is aborted
          Set the UART state ready to be able to start again the process,
          Disable Rx Interrupts if ongoing */
          UART_EndRxTransfer(huart);
 8012158:	68f8      	ldr	r0, [r7, #12]
 801215a:	f000 f95b 	bl	8012414 <UART_EndRxTransfer>

          huart->ErrorCode = HAL_UART_ERROR_ORE;
 801215e:	68fb      	ldr	r3, [r7, #12]
 8012160:	2208      	movs	r2, #8
 8012162:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90

          /* Process Unlocked */
          __HAL_UNLOCK(huart);
 8012166:	68fb      	ldr	r3, [r7, #12]
 8012168:	2200      	movs	r2, #0
 801216a:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

          return HAL_ERROR;
 801216e:	2301      	movs	r3, #1
 8012170:	e029      	b.n	80121c6 <UART_WaitOnFlagUntilTimeout+0xd2>
        }
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
 8012172:	68fb      	ldr	r3, [r7, #12]
 8012174:	681b      	ldr	r3, [r3, #0]
 8012176:	69db      	ldr	r3, [r3, #28]
 8012178:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 801217c:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 8012180:	d111      	bne.n	80121a6 <UART_WaitOnFlagUntilTimeout+0xb2>
        {
          /* Clear Receiver Timeout flag*/
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 8012182:	68fb      	ldr	r3, [r7, #12]
 8012184:	681b      	ldr	r3, [r3, #0]
 8012186:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 801218a:	621a      	str	r2, [r3, #32]

          /* Blocking error : transfer is aborted
          Set the UART state ready to be able to start again the process,
          Disable Rx Interrupts if ongoing */
          UART_EndRxTransfer(huart);
 801218c:	68f8      	ldr	r0, [r7, #12]
 801218e:	f000 f941 	bl	8012414 <UART_EndRxTransfer>

          huart->ErrorCode = HAL_UART_ERROR_RTO;
 8012192:	68fb      	ldr	r3, [r7, #12]
 8012194:	2220      	movs	r2, #32
 8012196:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90

          /* Process Unlocked */
          __HAL_UNLOCK(huart);
 801219a:	68fb      	ldr	r3, [r7, #12]
 801219c:	2200      	movs	r2, #0
 801219e:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

          return HAL_TIMEOUT;
 80121a2:	2303      	movs	r3, #3
 80121a4:	e00f      	b.n	80121c6 <UART_WaitOnFlagUntilTimeout+0xd2>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 80121a6:	68fb      	ldr	r3, [r7, #12]
 80121a8:	681b      	ldr	r3, [r3, #0]
 80121aa:	69da      	ldr	r2, [r3, #28]
 80121ac:	68bb      	ldr	r3, [r7, #8]
 80121ae:	4013      	ands	r3, r2
 80121b0:	68ba      	ldr	r2, [r7, #8]
 80121b2:	429a      	cmp	r2, r3
 80121b4:	bf0c      	ite	eq
 80121b6:	2301      	moveq	r3, #1
 80121b8:	2300      	movne	r3, #0
 80121ba:	b2db      	uxtb	r3, r3
 80121bc:	461a      	mov	r2, r3
 80121be:	79fb      	ldrb	r3, [r7, #7]
 80121c0:	429a      	cmp	r2, r3
 80121c2:	d0a0      	beq.n	8012106 <UART_WaitOnFlagUntilTimeout+0x12>
        }
      }
    }
  }
  return HAL_OK;
 80121c4:	2300      	movs	r3, #0
}
 80121c6:	4618      	mov	r0, r3
 80121c8:	3710      	adds	r7, #16
 80121ca:	46bd      	mov	sp, r7
 80121cc:	bd80      	pop	{r7, pc}
	...

080121d0 <UART_Start_Receive_IT>:
  * @param  pData Pointer to data buffer (u8 or u16 data elements).
  * @param  Size  Amount of data elements (u8 or u16) to be received.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
 80121d0:	b480      	push	{r7}
 80121d2:	b0a3      	sub	sp, #140	@ 0x8c
 80121d4:	af00      	add	r7, sp, #0
 80121d6:	60f8      	str	r0, [r7, #12]
 80121d8:	60b9      	str	r1, [r7, #8]
 80121da:	4613      	mov	r3, r2
 80121dc:	80fb      	strh	r3, [r7, #6]
  huart->pRxBuffPtr  = pData;
 80121de:	68fb      	ldr	r3, [r7, #12]
 80121e0:	68ba      	ldr	r2, [r7, #8]
 80121e2:	659a      	str	r2, [r3, #88]	@ 0x58
  huart->RxXferSize  = Size;
 80121e4:	68fb      	ldr	r3, [r7, #12]
 80121e6:	88fa      	ldrh	r2, [r7, #6]
 80121e8:	f8a3 205c 	strh.w	r2, [r3, #92]	@ 0x5c
  huart->RxXferCount = Size;
 80121ec:	68fb      	ldr	r3, [r7, #12]
 80121ee:	88fa      	ldrh	r2, [r7, #6]
 80121f0:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
  huart->RxISR       = NULL;
 80121f4:	68fb      	ldr	r3, [r7, #12]
 80121f6:	2200      	movs	r2, #0
 80121f8:	675a      	str	r2, [r3, #116]	@ 0x74

  /* Computation of UART mask to apply to RDR register */
  UART_MASK_COMPUTATION(huart);
 80121fa:	68fb      	ldr	r3, [r7, #12]
 80121fc:	689b      	ldr	r3, [r3, #8]
 80121fe:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 8012202:	d10e      	bne.n	8012222 <UART_Start_Receive_IT+0x52>
 8012204:	68fb      	ldr	r3, [r7, #12]
 8012206:	691b      	ldr	r3, [r3, #16]
 8012208:	2b00      	cmp	r3, #0
 801220a:	d105      	bne.n	8012218 <UART_Start_Receive_IT+0x48>
 801220c:	68fb      	ldr	r3, [r7, #12]
 801220e:	f240 12ff 	movw	r2, #511	@ 0x1ff
 8012212:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
 8012216:	e02d      	b.n	8012274 <UART_Start_Receive_IT+0xa4>
 8012218:	68fb      	ldr	r3, [r7, #12]
 801221a:	22ff      	movs	r2, #255	@ 0xff
 801221c:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
 8012220:	e028      	b.n	8012274 <UART_Start_Receive_IT+0xa4>
 8012222:	68fb      	ldr	r3, [r7, #12]
 8012224:	689b      	ldr	r3, [r3, #8]
 8012226:	2b00      	cmp	r3, #0
 8012228:	d10d      	bne.n	8012246 <UART_Start_Receive_IT+0x76>
 801222a:	68fb      	ldr	r3, [r7, #12]
 801222c:	691b      	ldr	r3, [r3, #16]
 801222e:	2b00      	cmp	r3, #0
 8012230:	d104      	bne.n	801223c <UART_Start_Receive_IT+0x6c>
 8012232:	68fb      	ldr	r3, [r7, #12]
 8012234:	22ff      	movs	r2, #255	@ 0xff
 8012236:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
 801223a:	e01b      	b.n	8012274 <UART_Start_Receive_IT+0xa4>
 801223c:	68fb      	ldr	r3, [r7, #12]
 801223e:	227f      	movs	r2, #127	@ 0x7f
 8012240:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
 8012244:	e016      	b.n	8012274 <UART_Start_Receive_IT+0xa4>
 8012246:	68fb      	ldr	r3, [r7, #12]
 8012248:	689b      	ldr	r3, [r3, #8]
 801224a:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 801224e:	d10d      	bne.n	801226c <UART_Start_Receive_IT+0x9c>
 8012250:	68fb      	ldr	r3, [r7, #12]
 8012252:	691b      	ldr	r3, [r3, #16]
 8012254:	2b00      	cmp	r3, #0
 8012256:	d104      	bne.n	8012262 <UART_Start_Receive_IT+0x92>
 8012258:	68fb      	ldr	r3, [r7, #12]
 801225a:	227f      	movs	r2, #127	@ 0x7f
 801225c:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
 8012260:	e008      	b.n	8012274 <UART_Start_Receive_IT+0xa4>
 8012262:	68fb      	ldr	r3, [r7, #12]
 8012264:	223f      	movs	r2, #63	@ 0x3f
 8012266:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
 801226a:	e003      	b.n	8012274 <UART_Start_Receive_IT+0xa4>
 801226c:	68fb      	ldr	r3, [r7, #12]
 801226e:	2200      	movs	r2, #0
 8012270:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60

  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8012274:	68fb      	ldr	r3, [r7, #12]
 8012276:	2200      	movs	r2, #0
 8012278:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
  huart->RxState = HAL_UART_STATE_BUSY_RX;
 801227c:	68fb      	ldr	r3, [r7, #12]
 801227e:	2222      	movs	r2, #34	@ 0x22
 8012280:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c

  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8012284:	68fb      	ldr	r3, [r7, #12]
 8012286:	681b      	ldr	r3, [r3, #0]
 8012288:	3308      	adds	r3, #8
 801228a:	667b      	str	r3, [r7, #100]	@ 0x64
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 801228c:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 801228e:	e853 3f00 	ldrex	r3, [r3]
 8012292:	663b      	str	r3, [r7, #96]	@ 0x60
   return(result);
 8012294:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 8012296:	f043 0301 	orr.w	r3, r3, #1
 801229a:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
 801229e:	68fb      	ldr	r3, [r7, #12]
 80122a0:	681b      	ldr	r3, [r3, #0]
 80122a2:	3308      	adds	r3, #8
 80122a4:	f8d7 2084 	ldr.w	r2, [r7, #132]	@ 0x84
 80122a8:	673a      	str	r2, [r7, #112]	@ 0x70
 80122aa:	66fb      	str	r3, [r7, #108]	@ 0x6c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80122ac:	6ef9      	ldr	r1, [r7, #108]	@ 0x6c
 80122ae:	6f3a      	ldr	r2, [r7, #112]	@ 0x70
 80122b0:	e841 2300 	strex	r3, r2, [r1]
 80122b4:	66bb      	str	r3, [r7, #104]	@ 0x68
   return(result);
 80122b6:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 80122b8:	2b00      	cmp	r3, #0
 80122ba:	d1e3      	bne.n	8012284 <UART_Start_Receive_IT+0xb4>

  /* Configure Rx interrupt processing */
  if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
 80122bc:	68fb      	ldr	r3, [r7, #12]
 80122be:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 80122c0:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
 80122c4:	d14f      	bne.n	8012366 <UART_Start_Receive_IT+0x196>
 80122c6:	68fb      	ldr	r3, [r7, #12]
 80122c8:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
 80122cc:	88fa      	ldrh	r2, [r7, #6]
 80122ce:	429a      	cmp	r2, r3
 80122d0:	d349      	bcc.n	8012366 <UART_Start_Receive_IT+0x196>
  {
    /* Set the Rx ISR function pointer according to the data word length */
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 80122d2:	68fb      	ldr	r3, [r7, #12]
 80122d4:	689b      	ldr	r3, [r3, #8]
 80122d6:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 80122da:	d107      	bne.n	80122ec <UART_Start_Receive_IT+0x11c>
 80122dc:	68fb      	ldr	r3, [r7, #12]
 80122de:	691b      	ldr	r3, [r3, #16]
 80122e0:	2b00      	cmp	r3, #0
 80122e2:	d103      	bne.n	80122ec <UART_Start_Receive_IT+0x11c>
    {
      huart->RxISR = UART_RxISR_16BIT_FIFOEN;
 80122e4:	68fb      	ldr	r3, [r7, #12]
 80122e6:	4a47      	ldr	r2, [pc, #284]	@ (8012404 <UART_Start_Receive_IT+0x234>)
 80122e8:	675a      	str	r2, [r3, #116]	@ 0x74
 80122ea:	e002      	b.n	80122f2 <UART_Start_Receive_IT+0x122>
    }
    else
    {
      huart->RxISR = UART_RxISR_8BIT_FIFOEN;
 80122ec:	68fb      	ldr	r3, [r7, #12]
 80122ee:	4a46      	ldr	r2, [pc, #280]	@ (8012408 <UART_Start_Receive_IT+0x238>)
 80122f0:	675a      	str	r2, [r3, #116]	@ 0x74
    }

    /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
    if (huart->Init.Parity != UART_PARITY_NONE)
 80122f2:	68fb      	ldr	r3, [r7, #12]
 80122f4:	691b      	ldr	r3, [r3, #16]
 80122f6:	2b00      	cmp	r3, #0
 80122f8:	d01a      	beq.n	8012330 <UART_Start_Receive_IT+0x160>
    {
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 80122fa:	68fb      	ldr	r3, [r7, #12]
 80122fc:	681b      	ldr	r3, [r3, #0]
 80122fe:	653b      	str	r3, [r7, #80]	@ 0x50
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012300:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 8012302:	e853 3f00 	ldrex	r3, [r3]
 8012306:	64fb      	str	r3, [r7, #76]	@ 0x4c
   return(result);
 8012308:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 801230a:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 801230e:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
 8012312:	68fb      	ldr	r3, [r7, #12]
 8012314:	681b      	ldr	r3, [r3, #0]
 8012316:	461a      	mov	r2, r3
 8012318:	f8d7 3080 	ldr.w	r3, [r7, #128]	@ 0x80
 801231c:	65fb      	str	r3, [r7, #92]	@ 0x5c
 801231e:	65ba      	str	r2, [r7, #88]	@ 0x58
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012320:	6db9      	ldr	r1, [r7, #88]	@ 0x58
 8012322:	6dfa      	ldr	r2, [r7, #92]	@ 0x5c
 8012324:	e841 2300 	strex	r3, r2, [r1]
 8012328:	657b      	str	r3, [r7, #84]	@ 0x54
   return(result);
 801232a:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 801232c:	2b00      	cmp	r3, #0
 801232e:	d1e4      	bne.n	80122fa <UART_Start_Receive_IT+0x12a>
    }
    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
 8012330:	68fb      	ldr	r3, [r7, #12]
 8012332:	681b      	ldr	r3, [r3, #0]
 8012334:	3308      	adds	r3, #8
 8012336:	63fb      	str	r3, [r7, #60]	@ 0x3c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012338:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 801233a:	e853 3f00 	ldrex	r3, [r3]
 801233e:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 8012340:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8012342:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8012346:	67fb      	str	r3, [r7, #124]	@ 0x7c
 8012348:	68fb      	ldr	r3, [r7, #12]
 801234a:	681b      	ldr	r3, [r3, #0]
 801234c:	3308      	adds	r3, #8
 801234e:	6ffa      	ldr	r2, [r7, #124]	@ 0x7c
 8012350:	64ba      	str	r2, [r7, #72]	@ 0x48
 8012352:	647b      	str	r3, [r7, #68]	@ 0x44
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012354:	6c79      	ldr	r1, [r7, #68]	@ 0x44
 8012356:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 8012358:	e841 2300 	strex	r3, r2, [r1]
 801235c:	643b      	str	r3, [r7, #64]	@ 0x40
   return(result);
 801235e:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 8012360:	2b00      	cmp	r3, #0
 8012362:	d1e5      	bne.n	8012330 <UART_Start_Receive_IT+0x160>
 8012364:	e046      	b.n	80123f4 <UART_Start_Receive_IT+0x224>
  }
  else
  {
    /* Set the Rx ISR function pointer according to the data word length */
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 8012366:	68fb      	ldr	r3, [r7, #12]
 8012368:	689b      	ldr	r3, [r3, #8]
 801236a:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 801236e:	d107      	bne.n	8012380 <UART_Start_Receive_IT+0x1b0>
 8012370:	68fb      	ldr	r3, [r7, #12]
 8012372:	691b      	ldr	r3, [r3, #16]
 8012374:	2b00      	cmp	r3, #0
 8012376:	d103      	bne.n	8012380 <UART_Start_Receive_IT+0x1b0>
    {
      huart->RxISR = UART_RxISR_16BIT;
 8012378:	68fb      	ldr	r3, [r7, #12]
 801237a:	4a24      	ldr	r2, [pc, #144]	@ (801240c <UART_Start_Receive_IT+0x23c>)
 801237c:	675a      	str	r2, [r3, #116]	@ 0x74
 801237e:	e002      	b.n	8012386 <UART_Start_Receive_IT+0x1b6>
    }
    else
    {
      huart->RxISR = UART_RxISR_8BIT;
 8012380:	68fb      	ldr	r3, [r7, #12]
 8012382:	4a23      	ldr	r2, [pc, #140]	@ (8012410 <UART_Start_Receive_IT+0x240>)
 8012384:	675a      	str	r2, [r3, #116]	@ 0x74
    }

    /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
    if (huart->Init.Parity != UART_PARITY_NONE)
 8012386:	68fb      	ldr	r3, [r7, #12]
 8012388:	691b      	ldr	r3, [r3, #16]
 801238a:	2b00      	cmp	r3, #0
 801238c:	d019      	beq.n	80123c2 <UART_Start_Receive_IT+0x1f2>
    {
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
 801238e:	68fb      	ldr	r3, [r7, #12]
 8012390:	681b      	ldr	r3, [r3, #0]
 8012392:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012394:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012396:	e853 3f00 	ldrex	r3, [r3]
 801239a:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 801239c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 801239e:	f443 7390 	orr.w	r3, r3, #288	@ 0x120
 80123a2:	677b      	str	r3, [r7, #116]	@ 0x74
 80123a4:	68fb      	ldr	r3, [r7, #12]
 80123a6:	681b      	ldr	r3, [r3, #0]
 80123a8:	461a      	mov	r2, r3
 80123aa:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
 80123ac:	637b      	str	r3, [r7, #52]	@ 0x34
 80123ae:	633a      	str	r2, [r7, #48]	@ 0x30
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80123b0:	6b39      	ldr	r1, [r7, #48]	@ 0x30
 80123b2:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 80123b4:	e841 2300 	strex	r3, r2, [r1]
 80123b8:	62fb      	str	r3, [r7, #44]	@ 0x2c
   return(result);
 80123ba:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80123bc:	2b00      	cmp	r3, #0
 80123be:	d1e6      	bne.n	801238e <UART_Start_Receive_IT+0x1be>
 80123c0:	e018      	b.n	80123f4 <UART_Start_Receive_IT+0x224>
    }
    else
    {
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
 80123c2:	68fb      	ldr	r3, [r7, #12]
 80123c4:	681b      	ldr	r3, [r3, #0]
 80123c6:	617b      	str	r3, [r7, #20]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80123c8:	697b      	ldr	r3, [r7, #20]
 80123ca:	e853 3f00 	ldrex	r3, [r3]
 80123ce:	613b      	str	r3, [r7, #16]
   return(result);
 80123d0:	693b      	ldr	r3, [r7, #16]
 80123d2:	f043 0320 	orr.w	r3, r3, #32
 80123d6:	67bb      	str	r3, [r7, #120]	@ 0x78
 80123d8:	68fb      	ldr	r3, [r7, #12]
 80123da:	681b      	ldr	r3, [r3, #0]
 80123dc:	461a      	mov	r2, r3
 80123de:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
 80123e0:	623b      	str	r3, [r7, #32]
 80123e2:	61fa      	str	r2, [r7, #28]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80123e4:	69f9      	ldr	r1, [r7, #28]
 80123e6:	6a3a      	ldr	r2, [r7, #32]
 80123e8:	e841 2300 	strex	r3, r2, [r1]
 80123ec:	61bb      	str	r3, [r7, #24]
   return(result);
 80123ee:	69bb      	ldr	r3, [r7, #24]
 80123f0:	2b00      	cmp	r3, #0
 80123f2:	d1e6      	bne.n	80123c2 <UART_Start_Receive_IT+0x1f2>
    }
  }
  return HAL_OK;
 80123f4:	2300      	movs	r3, #0
}
 80123f6:	4618      	mov	r0, r3
 80123f8:	378c      	adds	r7, #140	@ 0x8c
 80123fa:	46bd      	mov	sp, r7
 80123fc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8012400:	4770      	bx	lr
 8012402:	bf00      	nop
 8012404:	08012f79 	.word	0x08012f79
 8012408:	08012c19 	.word	0x08012c19
 801240c:	08012a61 	.word	0x08012a61
 8012410:	080128a9 	.word	0x080128a9

08012414 <UART_EndRxTransfer>:
  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
  * @param  huart UART handle.
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
 8012414:	b480      	push	{r7}
 8012416:	b095      	sub	sp, #84	@ 0x54
 8012418:	af00      	add	r7, sp, #0
 801241a:	6078      	str	r0, [r7, #4]
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 801241c:	687b      	ldr	r3, [r7, #4]
 801241e:	681b      	ldr	r3, [r3, #0]
 8012420:	637b      	str	r3, [r7, #52]	@ 0x34
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012422:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8012424:	e853 3f00 	ldrex	r3, [r3]
 8012428:	633b      	str	r3, [r7, #48]	@ 0x30
   return(result);
 801242a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801242c:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 8012430:	64fb      	str	r3, [r7, #76]	@ 0x4c
 8012432:	687b      	ldr	r3, [r7, #4]
 8012434:	681b      	ldr	r3, [r3, #0]
 8012436:	461a      	mov	r2, r3
 8012438:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 801243a:	643b      	str	r3, [r7, #64]	@ 0x40
 801243c:	63fa      	str	r2, [r7, #60]	@ 0x3c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 801243e:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
 8012440:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
 8012442:	e841 2300 	strex	r3, r2, [r1]
 8012446:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 8012448:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 801244a:	2b00      	cmp	r3, #0
 801244c:	d1e6      	bne.n	801241c <UART_EndRxTransfer+0x8>
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 801244e:	687b      	ldr	r3, [r7, #4]
 8012450:	681b      	ldr	r3, [r3, #0]
 8012452:	3308      	adds	r3, #8
 8012454:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012456:	6a3b      	ldr	r3, [r7, #32]
 8012458:	e853 3f00 	ldrex	r3, [r3]
 801245c:	61fb      	str	r3, [r7, #28]
   return(result);
 801245e:	69fa      	ldr	r2, [r7, #28]
 8012460:	4b1e      	ldr	r3, [pc, #120]	@ (80124dc <UART_EndRxTransfer+0xc8>)
 8012462:	4013      	ands	r3, r2
 8012464:	64bb      	str	r3, [r7, #72]	@ 0x48
 8012466:	687b      	ldr	r3, [r7, #4]
 8012468:	681b      	ldr	r3, [r3, #0]
 801246a:	3308      	adds	r3, #8
 801246c:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 801246e:	62fa      	str	r2, [r7, #44]	@ 0x2c
 8012470:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012472:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 8012474:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8012476:	e841 2300 	strex	r3, r2, [r1]
 801247a:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 801247c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 801247e:	2b00      	cmp	r3, #0
 8012480:	d1e5      	bne.n	801244e <UART_EndRxTransfer+0x3a>

  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8012482:	687b      	ldr	r3, [r7, #4]
 8012484:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8012486:	2b01      	cmp	r3, #1
 8012488:	d118      	bne.n	80124bc <UART_EndRxTransfer+0xa8>
  {
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 801248a:	687b      	ldr	r3, [r7, #4]
 801248c:	681b      	ldr	r3, [r3, #0]
 801248e:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012490:	68fb      	ldr	r3, [r7, #12]
 8012492:	e853 3f00 	ldrex	r3, [r3]
 8012496:	60bb      	str	r3, [r7, #8]
   return(result);
 8012498:	68bb      	ldr	r3, [r7, #8]
 801249a:	f023 0310 	bic.w	r3, r3, #16
 801249e:	647b      	str	r3, [r7, #68]	@ 0x44
 80124a0:	687b      	ldr	r3, [r7, #4]
 80124a2:	681b      	ldr	r3, [r3, #0]
 80124a4:	461a      	mov	r2, r3
 80124a6:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 80124a8:	61bb      	str	r3, [r7, #24]
 80124aa:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80124ac:	6979      	ldr	r1, [r7, #20]
 80124ae:	69ba      	ldr	r2, [r7, #24]
 80124b0:	e841 2300 	strex	r3, r2, [r1]
 80124b4:	613b      	str	r3, [r7, #16]
   return(result);
 80124b6:	693b      	ldr	r3, [r7, #16]
 80124b8:	2b00      	cmp	r3, #0
 80124ba:	d1e6      	bne.n	801248a <UART_EndRxTransfer+0x76>
  }

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 80124bc:	687b      	ldr	r3, [r7, #4]
 80124be:	2220      	movs	r2, #32
 80124c0:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 80124c4:	687b      	ldr	r3, [r7, #4]
 80124c6:	2200      	movs	r2, #0
 80124c8:	66da      	str	r2, [r3, #108]	@ 0x6c

  /* Reset RxIsr function pointer */
  huart->RxISR = NULL;
 80124ca:	687b      	ldr	r3, [r7, #4]
 80124cc:	2200      	movs	r2, #0
 80124ce:	675a      	str	r2, [r3, #116]	@ 0x74
}
 80124d0:	bf00      	nop
 80124d2:	3754      	adds	r7, #84	@ 0x54
 80124d4:	46bd      	mov	sp, r7
 80124d6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80124da:	4770      	bx	lr
 80124dc:	effffffe 	.word	0xeffffffe

080124e0 <UART_DMAAbortOnError>:
  *         (To be called at end of DMA Abort procedure following error occurrence).
  * @param  hdma DMA handle.
  * @retval None
  */
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
 80124e0:	b580      	push	{r7, lr}
 80124e2:	b084      	sub	sp, #16
 80124e4:	af00      	add	r7, sp, #0
 80124e6:	6078      	str	r0, [r7, #4]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
 80124e8:	687b      	ldr	r3, [r7, #4]
 80124ea:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 80124ec:	60fb      	str	r3, [r7, #12]
  huart->RxXferCount = 0U;
 80124ee:	68fb      	ldr	r3, [r7, #12]
 80124f0:	2200      	movs	r2, #0
 80124f2:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
  huart->TxXferCount = 0U;
 80124f6:	68fb      	ldr	r3, [r7, #12]
 80124f8:	2200      	movs	r2, #0
 80124fa:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  /*Call registered error callback*/
  huart->ErrorCallback(huart);
#else
  /*Call legacy weak error callback*/
  HAL_UART_ErrorCallback(huart);
 80124fe:	68f8      	ldr	r0, [r7, #12]
 8012500:	f7fe ff3a 	bl	8011378 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
 8012504:	bf00      	nop
 8012506:	3710      	adds	r7, #16
 8012508:	46bd      	mov	sp, r7
 801250a:	bd80      	pop	{r7, pc}

0801250c <UART_TxISR_8BIT>:
  *         interruptions have been enabled by HAL_UART_Transmit_IT().
  * @param huart UART handle.
  * @retval None
  */
static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
{
 801250c:	b480      	push	{r7}
 801250e:	b08f      	sub	sp, #60	@ 0x3c
 8012510:	af00      	add	r7, sp, #0
 8012512:	6078      	str	r0, [r7, #4]
  /* Check that a Tx process is ongoing */
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 8012514:	687b      	ldr	r3, [r7, #4]
 8012516:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 801251a:	2b21      	cmp	r3, #33	@ 0x21
 801251c:	d14c      	bne.n	80125b8 <UART_TxISR_8BIT+0xac>
  {
    if (huart->TxXferCount == 0U)
 801251e:	687b      	ldr	r3, [r7, #4]
 8012520:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 8012524:	b29b      	uxth	r3, r3
 8012526:	2b00      	cmp	r3, #0
 8012528:	d132      	bne.n	8012590 <UART_TxISR_8BIT+0x84>
    {
      /* Disable the UART Transmit Data Register Empty Interrupt */
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
 801252a:	687b      	ldr	r3, [r7, #4]
 801252c:	681b      	ldr	r3, [r3, #0]
 801252e:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012530:	6a3b      	ldr	r3, [r7, #32]
 8012532:	e853 3f00 	ldrex	r3, [r3]
 8012536:	61fb      	str	r3, [r7, #28]
   return(result);
 8012538:	69fb      	ldr	r3, [r7, #28]
 801253a:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 801253e:	637b      	str	r3, [r7, #52]	@ 0x34
 8012540:	687b      	ldr	r3, [r7, #4]
 8012542:	681b      	ldr	r3, [r3, #0]
 8012544:	461a      	mov	r2, r3
 8012546:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8012548:	62fb      	str	r3, [r7, #44]	@ 0x2c
 801254a:	62ba      	str	r2, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 801254c:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 801254e:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8012550:	e841 2300 	strex	r3, r2, [r1]
 8012554:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 8012556:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8012558:	2b00      	cmp	r3, #0
 801255a:	d1e6      	bne.n	801252a <UART_TxISR_8BIT+0x1e>

      /* Enable the UART Transmit Complete Interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 801255c:	687b      	ldr	r3, [r7, #4]
 801255e:	681b      	ldr	r3, [r3, #0]
 8012560:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012562:	68fb      	ldr	r3, [r7, #12]
 8012564:	e853 3f00 	ldrex	r3, [r3]
 8012568:	60bb      	str	r3, [r7, #8]
   return(result);
 801256a:	68bb      	ldr	r3, [r7, #8]
 801256c:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 8012570:	633b      	str	r3, [r7, #48]	@ 0x30
 8012572:	687b      	ldr	r3, [r7, #4]
 8012574:	681b      	ldr	r3, [r3, #0]
 8012576:	461a      	mov	r2, r3
 8012578:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801257a:	61bb      	str	r3, [r7, #24]
 801257c:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 801257e:	6979      	ldr	r1, [r7, #20]
 8012580:	69ba      	ldr	r2, [r7, #24]
 8012582:	e841 2300 	strex	r3, r2, [r1]
 8012586:	613b      	str	r3, [r7, #16]
   return(result);
 8012588:	693b      	ldr	r3, [r7, #16]
 801258a:	2b00      	cmp	r3, #0
 801258c:	d1e6      	bne.n	801255c <UART_TxISR_8BIT+0x50>
      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
      huart->pTxBuffPtr++;
      huart->TxXferCount--;
    }
  }
}
 801258e:	e013      	b.n	80125b8 <UART_TxISR_8BIT+0xac>
      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
 8012590:	687b      	ldr	r3, [r7, #4]
 8012592:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8012594:	781a      	ldrb	r2, [r3, #0]
 8012596:	687b      	ldr	r3, [r7, #4]
 8012598:	681b      	ldr	r3, [r3, #0]
 801259a:	629a      	str	r2, [r3, #40]	@ 0x28
      huart->pTxBuffPtr++;
 801259c:	687b      	ldr	r3, [r7, #4]
 801259e:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80125a0:	1c5a      	adds	r2, r3, #1
 80125a2:	687b      	ldr	r3, [r7, #4]
 80125a4:	651a      	str	r2, [r3, #80]	@ 0x50
      huart->TxXferCount--;
 80125a6:	687b      	ldr	r3, [r7, #4]
 80125a8:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 80125ac:	b29b      	uxth	r3, r3
 80125ae:	3b01      	subs	r3, #1
 80125b0:	b29a      	uxth	r2, r3
 80125b2:	687b      	ldr	r3, [r7, #4]
 80125b4:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
}
 80125b8:	bf00      	nop
 80125ba:	373c      	adds	r7, #60	@ 0x3c
 80125bc:	46bd      	mov	sp, r7
 80125be:	f85d 7b04 	ldr.w	r7, [sp], #4
 80125c2:	4770      	bx	lr

080125c4 <UART_TxISR_16BIT>:
  *         interruptions have been enabled by HAL_UART_Transmit_IT().
  * @param huart UART handle.
  * @retval None
  */
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
{
 80125c4:	b480      	push	{r7}
 80125c6:	b091      	sub	sp, #68	@ 0x44
 80125c8:	af00      	add	r7, sp, #0
 80125ca:	6078      	str	r0, [r7, #4]
  const uint16_t *tmp;

  /* Check that a Tx process is ongoing */
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 80125cc:	687b      	ldr	r3, [r7, #4]
 80125ce:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80125d2:	2b21      	cmp	r3, #33	@ 0x21
 80125d4:	d151      	bne.n	801267a <UART_TxISR_16BIT+0xb6>
  {
    if (huart->TxXferCount == 0U)
 80125d6:	687b      	ldr	r3, [r7, #4]
 80125d8:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 80125dc:	b29b      	uxth	r3, r3
 80125de:	2b00      	cmp	r3, #0
 80125e0:	d132      	bne.n	8012648 <UART_TxISR_16BIT+0x84>
    {
      /* Disable the UART Transmit Data Register Empty Interrupt */
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
 80125e2:	687b      	ldr	r3, [r7, #4]
 80125e4:	681b      	ldr	r3, [r3, #0]
 80125e6:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80125e8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80125ea:	e853 3f00 	ldrex	r3, [r3]
 80125ee:	623b      	str	r3, [r7, #32]
   return(result);
 80125f0:	6a3b      	ldr	r3, [r7, #32]
 80125f2:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 80125f6:	63bb      	str	r3, [r7, #56]	@ 0x38
 80125f8:	687b      	ldr	r3, [r7, #4]
 80125fa:	681b      	ldr	r3, [r3, #0]
 80125fc:	461a      	mov	r2, r3
 80125fe:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8012600:	633b      	str	r3, [r7, #48]	@ 0x30
 8012602:	62fa      	str	r2, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012604:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 8012606:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8012608:	e841 2300 	strex	r3, r2, [r1]
 801260c:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 801260e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8012610:	2b00      	cmp	r3, #0
 8012612:	d1e6      	bne.n	80125e2 <UART_TxISR_16BIT+0x1e>

      /* Enable the UART Transmit Complete Interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 8012614:	687b      	ldr	r3, [r7, #4]
 8012616:	681b      	ldr	r3, [r3, #0]
 8012618:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 801261a:	693b      	ldr	r3, [r7, #16]
 801261c:	e853 3f00 	ldrex	r3, [r3]
 8012620:	60fb      	str	r3, [r7, #12]
   return(result);
 8012622:	68fb      	ldr	r3, [r7, #12]
 8012624:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 8012628:	637b      	str	r3, [r7, #52]	@ 0x34
 801262a:	687b      	ldr	r3, [r7, #4]
 801262c:	681b      	ldr	r3, [r3, #0]
 801262e:	461a      	mov	r2, r3
 8012630:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8012632:	61fb      	str	r3, [r7, #28]
 8012634:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012636:	69b9      	ldr	r1, [r7, #24]
 8012638:	69fa      	ldr	r2, [r7, #28]
 801263a:	e841 2300 	strex	r3, r2, [r1]
 801263e:	617b      	str	r3, [r7, #20]
   return(result);
 8012640:	697b      	ldr	r3, [r7, #20]
 8012642:	2b00      	cmp	r3, #0
 8012644:	d1e6      	bne.n	8012614 <UART_TxISR_16BIT+0x50>
      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
      huart->pTxBuffPtr += 2U;
      huart->TxXferCount--;
    }
  }
}
 8012646:	e018      	b.n	801267a <UART_TxISR_16BIT+0xb6>
      tmp = (const uint16_t *) huart->pTxBuffPtr;
 8012648:	687b      	ldr	r3, [r7, #4]
 801264a:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 801264c:	63fb      	str	r3, [r7, #60]	@ 0x3c
      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
 801264e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8012650:	881b      	ldrh	r3, [r3, #0]
 8012652:	461a      	mov	r2, r3
 8012654:	687b      	ldr	r3, [r7, #4]
 8012656:	681b      	ldr	r3, [r3, #0]
 8012658:	f3c2 0208 	ubfx	r2, r2, #0, #9
 801265c:	629a      	str	r2, [r3, #40]	@ 0x28
      huart->pTxBuffPtr += 2U;
 801265e:	687b      	ldr	r3, [r7, #4]
 8012660:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8012662:	1c9a      	adds	r2, r3, #2
 8012664:	687b      	ldr	r3, [r7, #4]
 8012666:	651a      	str	r2, [r3, #80]	@ 0x50
      huart->TxXferCount--;
 8012668:	687b      	ldr	r3, [r7, #4]
 801266a:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 801266e:	b29b      	uxth	r3, r3
 8012670:	3b01      	subs	r3, #1
 8012672:	b29a      	uxth	r2, r3
 8012674:	687b      	ldr	r3, [r7, #4]
 8012676:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
}
 801267a:	bf00      	nop
 801267c:	3744      	adds	r7, #68	@ 0x44
 801267e:	46bd      	mov	sp, r7
 8012680:	f85d 7b04 	ldr.w	r7, [sp], #4
 8012684:	4770      	bx	lr

08012686 <UART_TxISR_8BIT_FIFOEN>:
  *         interruptions have been enabled by HAL_UART_Transmit_IT().
  * @param huart UART handle.
  * @retval None
  */
static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
{
 8012686:	b480      	push	{r7}
 8012688:	b091      	sub	sp, #68	@ 0x44
 801268a:	af00      	add	r7, sp, #0
 801268c:	6078      	str	r0, [r7, #4]
  uint16_t  nb_tx_data;

  /* Check that a Tx process is ongoing */
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 801268e:	687b      	ldr	r3, [r7, #4]
 8012690:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8012694:	2b21      	cmp	r3, #33	@ 0x21
 8012696:	d160      	bne.n	801275a <UART_TxISR_8BIT_FIFOEN+0xd4>
  {
    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
 8012698:	687b      	ldr	r3, [r7, #4]
 801269a:	f8b3 306a 	ldrh.w	r3, [r3, #106]	@ 0x6a
 801269e:	87fb      	strh	r3, [r7, #62]	@ 0x3e
 80126a0:	e057      	b.n	8012752 <UART_TxISR_8BIT_FIFOEN+0xcc>
    {
      if (huart->TxXferCount == 0U)
 80126a2:	687b      	ldr	r3, [r7, #4]
 80126a4:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 80126a8:	b29b      	uxth	r3, r3
 80126aa:	2b00      	cmp	r3, #0
 80126ac:	d133      	bne.n	8012716 <UART_TxISR_8BIT_FIFOEN+0x90>
      {
        /* Disable the TX FIFO threshold interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
 80126ae:	687b      	ldr	r3, [r7, #4]
 80126b0:	681b      	ldr	r3, [r3, #0]
 80126b2:	3308      	adds	r3, #8
 80126b4:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80126b6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80126b8:	e853 3f00 	ldrex	r3, [r3]
 80126bc:	623b      	str	r3, [r7, #32]
   return(result);
 80126be:	6a3b      	ldr	r3, [r7, #32]
 80126c0:	f423 0300 	bic.w	r3, r3, #8388608	@ 0x800000
 80126c4:	63bb      	str	r3, [r7, #56]	@ 0x38
 80126c6:	687b      	ldr	r3, [r7, #4]
 80126c8:	681b      	ldr	r3, [r3, #0]
 80126ca:	3308      	adds	r3, #8
 80126cc:	6bba      	ldr	r2, [r7, #56]	@ 0x38
 80126ce:	633a      	str	r2, [r7, #48]	@ 0x30
 80126d0:	62fb      	str	r3, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80126d2:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 80126d4:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 80126d6:	e841 2300 	strex	r3, r2, [r1]
 80126da:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 80126dc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80126de:	2b00      	cmp	r3, #0
 80126e0:	d1e5      	bne.n	80126ae <UART_TxISR_8BIT_FIFOEN+0x28>

        /* Enable the UART Transmit Complete Interrupt */
        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 80126e2:	687b      	ldr	r3, [r7, #4]
 80126e4:	681b      	ldr	r3, [r3, #0]
 80126e6:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80126e8:	693b      	ldr	r3, [r7, #16]
 80126ea:	e853 3f00 	ldrex	r3, [r3]
 80126ee:	60fb      	str	r3, [r7, #12]
   return(result);
 80126f0:	68fb      	ldr	r3, [r7, #12]
 80126f2:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 80126f6:	637b      	str	r3, [r7, #52]	@ 0x34
 80126f8:	687b      	ldr	r3, [r7, #4]
 80126fa:	681b      	ldr	r3, [r3, #0]
 80126fc:	461a      	mov	r2, r3
 80126fe:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8012700:	61fb      	str	r3, [r7, #28]
 8012702:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012704:	69b9      	ldr	r1, [r7, #24]
 8012706:	69fa      	ldr	r2, [r7, #28]
 8012708:	e841 2300 	strex	r3, r2, [r1]
 801270c:	617b      	str	r3, [r7, #20]
   return(result);
 801270e:	697b      	ldr	r3, [r7, #20]
 8012710:	2b00      	cmp	r3, #0
 8012712:	d1e6      	bne.n	80126e2 <UART_TxISR_8BIT_FIFOEN+0x5c>

        break; /* force exit loop */
 8012714:	e021      	b.n	801275a <UART_TxISR_8BIT_FIFOEN+0xd4>
      }
      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
 8012716:	687b      	ldr	r3, [r7, #4]
 8012718:	681b      	ldr	r3, [r3, #0]
 801271a:	69db      	ldr	r3, [r3, #28]
 801271c:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8012720:	2b00      	cmp	r3, #0
 8012722:	d013      	beq.n	801274c <UART_TxISR_8BIT_FIFOEN+0xc6>
      {
        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
 8012724:	687b      	ldr	r3, [r7, #4]
 8012726:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8012728:	781a      	ldrb	r2, [r3, #0]
 801272a:	687b      	ldr	r3, [r7, #4]
 801272c:	681b      	ldr	r3, [r3, #0]
 801272e:	629a      	str	r2, [r3, #40]	@ 0x28
        huart->pTxBuffPtr++;
 8012730:	687b      	ldr	r3, [r7, #4]
 8012732:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8012734:	1c5a      	adds	r2, r3, #1
 8012736:	687b      	ldr	r3, [r7, #4]
 8012738:	651a      	str	r2, [r3, #80]	@ 0x50
        huart->TxXferCount--;
 801273a:	687b      	ldr	r3, [r7, #4]
 801273c:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 8012740:	b29b      	uxth	r3, r3
 8012742:	3b01      	subs	r3, #1
 8012744:	b29a      	uxth	r2, r3
 8012746:	687b      	ldr	r3, [r7, #4]
 8012748:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
 801274c:	8ffb      	ldrh	r3, [r7, #62]	@ 0x3e
 801274e:	3b01      	subs	r3, #1
 8012750:	87fb      	strh	r3, [r7, #62]	@ 0x3e
 8012752:	8ffb      	ldrh	r3, [r7, #62]	@ 0x3e
 8012754:	2b00      	cmp	r3, #0
 8012756:	d1a4      	bne.n	80126a2 <UART_TxISR_8BIT_FIFOEN+0x1c>
      {
        /* Nothing to do */
      }
    }
  }
}
 8012758:	e7ff      	b.n	801275a <UART_TxISR_8BIT_FIFOEN+0xd4>
 801275a:	bf00      	nop
 801275c:	3744      	adds	r7, #68	@ 0x44
 801275e:	46bd      	mov	sp, r7
 8012760:	f85d 7b04 	ldr.w	r7, [sp], #4
 8012764:	4770      	bx	lr

08012766 <UART_TxISR_16BIT_FIFOEN>:
  *         interruptions have been enabled by HAL_UART_Transmit_IT().
  * @param huart UART handle.
  * @retval None
  */
static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
{
 8012766:	b480      	push	{r7}
 8012768:	b091      	sub	sp, #68	@ 0x44
 801276a:	af00      	add	r7, sp, #0
 801276c:	6078      	str	r0, [r7, #4]
  const uint16_t *tmp;
  uint16_t  nb_tx_data;

  /* Check that a Tx process is ongoing */
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 801276e:	687b      	ldr	r3, [r7, #4]
 8012770:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8012774:	2b21      	cmp	r3, #33	@ 0x21
 8012776:	d165      	bne.n	8012844 <UART_TxISR_16BIT_FIFOEN+0xde>
  {
    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
 8012778:	687b      	ldr	r3, [r7, #4]
 801277a:	f8b3 306a 	ldrh.w	r3, [r3, #106]	@ 0x6a
 801277e:	87fb      	strh	r3, [r7, #62]	@ 0x3e
 8012780:	e05c      	b.n	801283c <UART_TxISR_16BIT_FIFOEN+0xd6>
    {
      if (huart->TxXferCount == 0U)
 8012782:	687b      	ldr	r3, [r7, #4]
 8012784:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 8012788:	b29b      	uxth	r3, r3
 801278a:	2b00      	cmp	r3, #0
 801278c:	d133      	bne.n	80127f6 <UART_TxISR_16BIT_FIFOEN+0x90>
      {
        /* Disable the TX FIFO threshold interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
 801278e:	687b      	ldr	r3, [r7, #4]
 8012790:	681b      	ldr	r3, [r3, #0]
 8012792:	3308      	adds	r3, #8
 8012794:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012796:	6a3b      	ldr	r3, [r7, #32]
 8012798:	e853 3f00 	ldrex	r3, [r3]
 801279c:	61fb      	str	r3, [r7, #28]
   return(result);
 801279e:	69fb      	ldr	r3, [r7, #28]
 80127a0:	f423 0300 	bic.w	r3, r3, #8388608	@ 0x800000
 80127a4:	637b      	str	r3, [r7, #52]	@ 0x34
 80127a6:	687b      	ldr	r3, [r7, #4]
 80127a8:	681b      	ldr	r3, [r3, #0]
 80127aa:	3308      	adds	r3, #8
 80127ac:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 80127ae:	62fa      	str	r2, [r7, #44]	@ 0x2c
 80127b0:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80127b2:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 80127b4:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 80127b6:	e841 2300 	strex	r3, r2, [r1]
 80127ba:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 80127bc:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80127be:	2b00      	cmp	r3, #0
 80127c0:	d1e5      	bne.n	801278e <UART_TxISR_16BIT_FIFOEN+0x28>

        /* Enable the UART Transmit Complete Interrupt */
        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 80127c2:	687b      	ldr	r3, [r7, #4]
 80127c4:	681b      	ldr	r3, [r3, #0]
 80127c6:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80127c8:	68fb      	ldr	r3, [r7, #12]
 80127ca:	e853 3f00 	ldrex	r3, [r3]
 80127ce:	60bb      	str	r3, [r7, #8]
   return(result);
 80127d0:	68bb      	ldr	r3, [r7, #8]
 80127d2:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 80127d6:	633b      	str	r3, [r7, #48]	@ 0x30
 80127d8:	687b      	ldr	r3, [r7, #4]
 80127da:	681b      	ldr	r3, [r3, #0]
 80127dc:	461a      	mov	r2, r3
 80127de:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80127e0:	61bb      	str	r3, [r7, #24]
 80127e2:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80127e4:	6979      	ldr	r1, [r7, #20]
 80127e6:	69ba      	ldr	r2, [r7, #24]
 80127e8:	e841 2300 	strex	r3, r2, [r1]
 80127ec:	613b      	str	r3, [r7, #16]
   return(result);
 80127ee:	693b      	ldr	r3, [r7, #16]
 80127f0:	2b00      	cmp	r3, #0
 80127f2:	d1e6      	bne.n	80127c2 <UART_TxISR_16BIT_FIFOEN+0x5c>

        break; /* force exit loop */
 80127f4:	e026      	b.n	8012844 <UART_TxISR_16BIT_FIFOEN+0xde>
      }
      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
 80127f6:	687b      	ldr	r3, [r7, #4]
 80127f8:	681b      	ldr	r3, [r3, #0]
 80127fa:	69db      	ldr	r3, [r3, #28]
 80127fc:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 8012800:	2b00      	cmp	r3, #0
 8012802:	d018      	beq.n	8012836 <UART_TxISR_16BIT_FIFOEN+0xd0>
      {
        tmp = (const uint16_t *) huart->pTxBuffPtr;
 8012804:	687b      	ldr	r3, [r7, #4]
 8012806:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8012808:	63bb      	str	r3, [r7, #56]	@ 0x38
        huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
 801280a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 801280c:	881b      	ldrh	r3, [r3, #0]
 801280e:	461a      	mov	r2, r3
 8012810:	687b      	ldr	r3, [r7, #4]
 8012812:	681b      	ldr	r3, [r3, #0]
 8012814:	f3c2 0208 	ubfx	r2, r2, #0, #9
 8012818:	629a      	str	r2, [r3, #40]	@ 0x28
        huart->pTxBuffPtr += 2U;
 801281a:	687b      	ldr	r3, [r7, #4]
 801281c:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 801281e:	1c9a      	adds	r2, r3, #2
 8012820:	687b      	ldr	r3, [r7, #4]
 8012822:	651a      	str	r2, [r3, #80]	@ 0x50
        huart->TxXferCount--;
 8012824:	687b      	ldr	r3, [r7, #4]
 8012826:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
 801282a:	b29b      	uxth	r3, r3
 801282c:	3b01      	subs	r3, #1
 801282e:	b29a      	uxth	r2, r3
 8012830:	687b      	ldr	r3, [r7, #4]
 8012832:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
 8012836:	8ffb      	ldrh	r3, [r7, #62]	@ 0x3e
 8012838:	3b01      	subs	r3, #1
 801283a:	87fb      	strh	r3, [r7, #62]	@ 0x3e
 801283c:	8ffb      	ldrh	r3, [r7, #62]	@ 0x3e
 801283e:	2b00      	cmp	r3, #0
 8012840:	d19f      	bne.n	8012782 <UART_TxISR_16BIT_FIFOEN+0x1c>
      {
        /* Nothing to do */
      }
    }
  }
}
 8012842:	e7ff      	b.n	8012844 <UART_TxISR_16BIT_FIFOEN+0xde>
 8012844:	bf00      	nop
 8012846:	3744      	adds	r7, #68	@ 0x44
 8012848:	46bd      	mov	sp, r7
 801284a:	f85d 7b04 	ldr.w	r7, [sp], #4
 801284e:	4770      	bx	lr

08012850 <UART_EndTransmit_IT>:
  * @param  huart pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
 8012850:	b580      	push	{r7, lr}
 8012852:	b088      	sub	sp, #32
 8012854:	af00      	add	r7, sp, #0
 8012856:	6078      	str	r0, [r7, #4]
  /* Disable the UART Transmit Complete Interrupt */
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 8012858:	687b      	ldr	r3, [r7, #4]
 801285a:	681b      	ldr	r3, [r3, #0]
 801285c:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 801285e:	68fb      	ldr	r3, [r7, #12]
 8012860:	e853 3f00 	ldrex	r3, [r3]
 8012864:	60bb      	str	r3, [r7, #8]
   return(result);
 8012866:	68bb      	ldr	r3, [r7, #8]
 8012868:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
 801286c:	61fb      	str	r3, [r7, #28]
 801286e:	687b      	ldr	r3, [r7, #4]
 8012870:	681b      	ldr	r3, [r3, #0]
 8012872:	461a      	mov	r2, r3
 8012874:	69fb      	ldr	r3, [r7, #28]
 8012876:	61bb      	str	r3, [r7, #24]
 8012878:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 801287a:	6979      	ldr	r1, [r7, #20]
 801287c:	69ba      	ldr	r2, [r7, #24]
 801287e:	e841 2300 	strex	r3, r2, [r1]
 8012882:	613b      	str	r3, [r7, #16]
   return(result);
 8012884:	693b      	ldr	r3, [r7, #16]
 8012886:	2b00      	cmp	r3, #0
 8012888:	d1e6      	bne.n	8012858 <UART_EndTransmit_IT+0x8>

  /* Tx process is ended, restore huart->gState to Ready */
  huart->gState = HAL_UART_STATE_READY;
 801288a:	687b      	ldr	r3, [r7, #4]
 801288c:	2220      	movs	r2, #32
 801288e:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Cleat TxISR function pointer */
  huart->TxISR = NULL;
 8012892:	687b      	ldr	r3, [r7, #4]
 8012894:	2200      	movs	r2, #0
 8012896:	679a      	str	r2, [r3, #120]	@ 0x78
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  /*Call registered Tx complete callback*/
  huart->TxCpltCallback(huart);
#else
  /*Call legacy weak Tx complete callback*/
  HAL_UART_TxCpltCallback(huart);
 8012898:	6878      	ldr	r0, [r7, #4]
 801289a:	f7f1 fd5f 	bl	800435c <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
 801289e:	bf00      	nop
 80128a0:	3720      	adds	r7, #32
 80128a2:	46bd      	mov	sp, r7
 80128a4:	bd80      	pop	{r7, pc}
	...

080128a8 <UART_RxISR_8BIT>:
  * @brief RX interrupt handler for 7 or 8 bits data word length .
  * @param huart UART handle.
  * @retval None
  */
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
{
 80128a8:	b580      	push	{r7, lr}
 80128aa:	b09c      	sub	sp, #112	@ 0x70
 80128ac:	af00      	add	r7, sp, #0
 80128ae:	6078      	str	r0, [r7, #4]
  uint16_t uhMask = huart->Mask;
 80128b0:	687b      	ldr	r3, [r7, #4]
 80128b2:	f8b3 3060 	ldrh.w	r3, [r3, #96]	@ 0x60
 80128b6:	f8a7 306e 	strh.w	r3, [r7, #110]	@ 0x6e
  uint16_t  uhdata;

  /* Check that a Rx process is ongoing */
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 80128ba:	687b      	ldr	r3, [r7, #4]
 80128bc:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 80128c0:	2b22      	cmp	r3, #34	@ 0x22
 80128c2:	f040 80be 	bne.w	8012a42 <UART_RxISR_8BIT+0x19a>
  {
    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
 80128c6:	687b      	ldr	r3, [r7, #4]
 80128c8:	681b      	ldr	r3, [r3, #0]
 80128ca:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80128cc:	f8a7 306c 	strh.w	r3, [r7, #108]	@ 0x6c
    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
 80128d0:	f8b7 306c 	ldrh.w	r3, [r7, #108]	@ 0x6c
 80128d4:	b2d9      	uxtb	r1, r3
 80128d6:	f8b7 306e 	ldrh.w	r3, [r7, #110]	@ 0x6e
 80128da:	b2da      	uxtb	r2, r3
 80128dc:	687b      	ldr	r3, [r7, #4]
 80128de:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80128e0:	400a      	ands	r2, r1
 80128e2:	b2d2      	uxtb	r2, r2
 80128e4:	701a      	strb	r2, [r3, #0]
    huart->pRxBuffPtr++;
 80128e6:	687b      	ldr	r3, [r7, #4]
 80128e8:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80128ea:	1c5a      	adds	r2, r3, #1
 80128ec:	687b      	ldr	r3, [r7, #4]
 80128ee:	659a      	str	r2, [r3, #88]	@ 0x58
    huart->RxXferCount--;
 80128f0:	687b      	ldr	r3, [r7, #4]
 80128f2:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 80128f6:	b29b      	uxth	r3, r3
 80128f8:	3b01      	subs	r3, #1
 80128fa:	b29a      	uxth	r2, r3
 80128fc:	687b      	ldr	r3, [r7, #4]
 80128fe:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e

    if (huart->RxXferCount == 0U)
 8012902:	687b      	ldr	r3, [r7, #4]
 8012904:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 8012908:	b29b      	uxth	r3, r3
 801290a:	2b00      	cmp	r3, #0
 801290c:	f040 80a1 	bne.w	8012a52 <UART_RxISR_8BIT+0x1aa>
    {
      /* Disable the UART Parity Error Interrupt and RXNE interrupts */
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 8012910:	687b      	ldr	r3, [r7, #4]
 8012912:	681b      	ldr	r3, [r3, #0]
 8012914:	64fb      	str	r3, [r7, #76]	@ 0x4c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012916:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8012918:	e853 3f00 	ldrex	r3, [r3]
 801291c:	64bb      	str	r3, [r7, #72]	@ 0x48
   return(result);
 801291e:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 8012920:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 8012924:	66bb      	str	r3, [r7, #104]	@ 0x68
 8012926:	687b      	ldr	r3, [r7, #4]
 8012928:	681b      	ldr	r3, [r3, #0]
 801292a:	461a      	mov	r2, r3
 801292c:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 801292e:	65bb      	str	r3, [r7, #88]	@ 0x58
 8012930:	657a      	str	r2, [r7, #84]	@ 0x54
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012932:	6d79      	ldr	r1, [r7, #84]	@ 0x54
 8012934:	6dba      	ldr	r2, [r7, #88]	@ 0x58
 8012936:	e841 2300 	strex	r3, r2, [r1]
 801293a:	653b      	str	r3, [r7, #80]	@ 0x50
   return(result);
 801293c:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 801293e:	2b00      	cmp	r3, #0
 8012940:	d1e6      	bne.n	8012910 <UART_RxISR_8BIT+0x68>

      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8012942:	687b      	ldr	r3, [r7, #4]
 8012944:	681b      	ldr	r3, [r3, #0]
 8012946:	3308      	adds	r3, #8
 8012948:	63bb      	str	r3, [r7, #56]	@ 0x38
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 801294a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 801294c:	e853 3f00 	ldrex	r3, [r3]
 8012950:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 8012952:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8012954:	f023 0301 	bic.w	r3, r3, #1
 8012958:	667b      	str	r3, [r7, #100]	@ 0x64
 801295a:	687b      	ldr	r3, [r7, #4]
 801295c:	681b      	ldr	r3, [r3, #0]
 801295e:	3308      	adds	r3, #8
 8012960:	6e7a      	ldr	r2, [r7, #100]	@ 0x64
 8012962:	647a      	str	r2, [r7, #68]	@ 0x44
 8012964:	643b      	str	r3, [r7, #64]	@ 0x40
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012966:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 8012968:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 801296a:	e841 2300 	strex	r3, r2, [r1]
 801296e:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 8012970:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8012972:	2b00      	cmp	r3, #0
 8012974:	d1e5      	bne.n	8012942 <UART_RxISR_8BIT+0x9a>

      /* Rx process is completed, restore huart->RxState to Ready */
      huart->RxState = HAL_UART_STATE_READY;
 8012976:	687b      	ldr	r3, [r7, #4]
 8012978:	2220      	movs	r2, #32
 801297a:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c

      /* Clear RxISR function pointer */
      huart->RxISR = NULL;
 801297e:	687b      	ldr	r3, [r7, #4]
 8012980:	2200      	movs	r2, #0
 8012982:	675a      	str	r2, [r3, #116]	@ 0x74

      /* Initialize type of RxEvent to Transfer Complete */
      huart->RxEventType = HAL_UART_RXEVENT_TC;
 8012984:	687b      	ldr	r3, [r7, #4]
 8012986:	2200      	movs	r2, #0
 8012988:	671a      	str	r2, [r3, #112]	@ 0x70

      if (!(IS_LPUART_INSTANCE(huart->Instance)))
 801298a:	687b      	ldr	r3, [r7, #4]
 801298c:	681b      	ldr	r3, [r3, #0]
 801298e:	4a33      	ldr	r2, [pc, #204]	@ (8012a5c <UART_RxISR_8BIT+0x1b4>)
 8012990:	4293      	cmp	r3, r2
 8012992:	d01f      	beq.n	80129d4 <UART_RxISR_8BIT+0x12c>
      {
        /* Check that USART RTOEN bit is set */
        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
 8012994:	687b      	ldr	r3, [r7, #4]
 8012996:	681b      	ldr	r3, [r3, #0]
 8012998:	685b      	ldr	r3, [r3, #4]
 801299a:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 801299e:	2b00      	cmp	r3, #0
 80129a0:	d018      	beq.n	80129d4 <UART_RxISR_8BIT+0x12c>
        {
          /* Enable the UART Receiver Timeout Interrupt */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
 80129a2:	687b      	ldr	r3, [r7, #4]
 80129a4:	681b      	ldr	r3, [r3, #0]
 80129a6:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80129a8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80129aa:	e853 3f00 	ldrex	r3, [r3]
 80129ae:	623b      	str	r3, [r7, #32]
   return(result);
 80129b0:	6a3b      	ldr	r3, [r7, #32]
 80129b2:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 80129b6:	663b      	str	r3, [r7, #96]	@ 0x60
 80129b8:	687b      	ldr	r3, [r7, #4]
 80129ba:	681b      	ldr	r3, [r3, #0]
 80129bc:	461a      	mov	r2, r3
 80129be:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 80129c0:	633b      	str	r3, [r7, #48]	@ 0x30
 80129c2:	62fa      	str	r2, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80129c4:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 80129c6:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 80129c8:	e841 2300 	strex	r3, r2, [r1]
 80129cc:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 80129ce:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80129d0:	2b00      	cmp	r3, #0
 80129d2:	d1e6      	bne.n	80129a2 <UART_RxISR_8BIT+0xfa>
        }
      }

      /* Check current reception Mode :
         If Reception till IDLE event has been selected : */
      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 80129d4:	687b      	ldr	r3, [r7, #4]
 80129d6:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 80129d8:	2b01      	cmp	r3, #1
 80129da:	d12e      	bne.n	8012a3a <UART_RxISR_8BIT+0x192>
      {
        /* Set reception type to Standard */
        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 80129dc:	687b      	ldr	r3, [r7, #4]
 80129de:	2200      	movs	r2, #0
 80129e0:	66da      	str	r2, [r3, #108]	@ 0x6c

        /* Disable IDLE interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 80129e2:	687b      	ldr	r3, [r7, #4]
 80129e4:	681b      	ldr	r3, [r3, #0]
 80129e6:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80129e8:	693b      	ldr	r3, [r7, #16]
 80129ea:	e853 3f00 	ldrex	r3, [r3]
 80129ee:	60fb      	str	r3, [r7, #12]
   return(result);
 80129f0:	68fb      	ldr	r3, [r7, #12]
 80129f2:	f023 0310 	bic.w	r3, r3, #16
 80129f6:	65fb      	str	r3, [r7, #92]	@ 0x5c
 80129f8:	687b      	ldr	r3, [r7, #4]
 80129fa:	681b      	ldr	r3, [r3, #0]
 80129fc:	461a      	mov	r2, r3
 80129fe:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 8012a00:	61fb      	str	r3, [r7, #28]
 8012a02:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012a04:	69b9      	ldr	r1, [r7, #24]
 8012a06:	69fa      	ldr	r2, [r7, #28]
 8012a08:	e841 2300 	strex	r3, r2, [r1]
 8012a0c:	617b      	str	r3, [r7, #20]
   return(result);
 8012a0e:	697b      	ldr	r3, [r7, #20]
 8012a10:	2b00      	cmp	r3, #0
 8012a12:	d1e6      	bne.n	80129e2 <UART_RxISR_8BIT+0x13a>

        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
 8012a14:	687b      	ldr	r3, [r7, #4]
 8012a16:	681b      	ldr	r3, [r3, #0]
 8012a18:	69db      	ldr	r3, [r3, #28]
 8012a1a:	f003 0310 	and.w	r3, r3, #16
 8012a1e:	2b10      	cmp	r3, #16
 8012a20:	d103      	bne.n	8012a2a <UART_RxISR_8BIT+0x182>
        {
          /* Clear IDLE Flag */
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 8012a22:	687b      	ldr	r3, [r7, #4]
 8012a24:	681b      	ldr	r3, [r3, #0]
 8012a26:	2210      	movs	r2, #16
 8012a28:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered Rx Event callback*/
        huart->RxEventCallback(huart, huart->RxXferSize);
#else
        /*Call legacy weak Rx Event callback*/
        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
 8012a2a:	687b      	ldr	r3, [r7, #4]
 8012a2c:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
 8012a30:	4619      	mov	r1, r3
 8012a32:	6878      	ldr	r0, [r7, #4]
 8012a34:	f7f1 fc68 	bl	8004308 <HAL_UARTEx_RxEventCallback>
  else
  {
    /* Clear RXNE interrupt flag */
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  }
}
 8012a38:	e00b      	b.n	8012a52 <UART_RxISR_8BIT+0x1aa>
        HAL_UART_RxCpltCallback(huart);
 8012a3a:	6878      	ldr	r0, [r7, #4]
 8012a3c:	f7f1 fc5a 	bl	80042f4 <HAL_UART_RxCpltCallback>
}
 8012a40:	e007      	b.n	8012a52 <UART_RxISR_8BIT+0x1aa>
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
 8012a42:	687b      	ldr	r3, [r7, #4]
 8012a44:	681b      	ldr	r3, [r3, #0]
 8012a46:	699a      	ldr	r2, [r3, #24]
 8012a48:	687b      	ldr	r3, [r7, #4]
 8012a4a:	681b      	ldr	r3, [r3, #0]
 8012a4c:	f042 0208 	orr.w	r2, r2, #8
 8012a50:	619a      	str	r2, [r3, #24]
}
 8012a52:	bf00      	nop
 8012a54:	3770      	adds	r7, #112	@ 0x70
 8012a56:	46bd      	mov	sp, r7
 8012a58:	bd80      	pop	{r7, pc}
 8012a5a:	bf00      	nop
 8012a5c:	58000c00 	.word	0x58000c00

08012a60 <UART_RxISR_16BIT>:
  *         interruptions have been enabled by HAL_UART_Receive_IT()
  * @param huart UART handle.
  * @retval None
  */
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
{
 8012a60:	b580      	push	{r7, lr}
 8012a62:	b09c      	sub	sp, #112	@ 0x70
 8012a64:	af00      	add	r7, sp, #0
 8012a66:	6078      	str	r0, [r7, #4]
  uint16_t *tmp;
  uint16_t uhMask = huart->Mask;
 8012a68:	687b      	ldr	r3, [r7, #4]
 8012a6a:	f8b3 3060 	ldrh.w	r3, [r3, #96]	@ 0x60
 8012a6e:	f8a7 306e 	strh.w	r3, [r7, #110]	@ 0x6e
  uint16_t  uhdata;

  /* Check that a Rx process is ongoing */
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 8012a72:	687b      	ldr	r3, [r7, #4]
 8012a74:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 8012a78:	2b22      	cmp	r3, #34	@ 0x22
 8012a7a:	f040 80be 	bne.w	8012bfa <UART_RxISR_16BIT+0x19a>
  {
    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
 8012a7e:	687b      	ldr	r3, [r7, #4]
 8012a80:	681b      	ldr	r3, [r3, #0]
 8012a82:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8012a84:	f8a7 306c 	strh.w	r3, [r7, #108]	@ 0x6c
    tmp = (uint16_t *) huart->pRxBuffPtr ;
 8012a88:	687b      	ldr	r3, [r7, #4]
 8012a8a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8012a8c:	66bb      	str	r3, [r7, #104]	@ 0x68
    *tmp = (uint16_t)(uhdata & uhMask);
 8012a8e:	f8b7 206c 	ldrh.w	r2, [r7, #108]	@ 0x6c
 8012a92:	f8b7 306e 	ldrh.w	r3, [r7, #110]	@ 0x6e
 8012a96:	4013      	ands	r3, r2
 8012a98:	b29a      	uxth	r2, r3
 8012a9a:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
 8012a9c:	801a      	strh	r2, [r3, #0]
    huart->pRxBuffPtr += 2U;
 8012a9e:	687b      	ldr	r3, [r7, #4]
 8012aa0:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8012aa2:	1c9a      	adds	r2, r3, #2
 8012aa4:	687b      	ldr	r3, [r7, #4]
 8012aa6:	659a      	str	r2, [r3, #88]	@ 0x58
    huart->RxXferCount--;
 8012aa8:	687b      	ldr	r3, [r7, #4]
 8012aaa:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 8012aae:	b29b      	uxth	r3, r3
 8012ab0:	3b01      	subs	r3, #1
 8012ab2:	b29a      	uxth	r2, r3
 8012ab4:	687b      	ldr	r3, [r7, #4]
 8012ab6:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e

    if (huart->RxXferCount == 0U)
 8012aba:	687b      	ldr	r3, [r7, #4]
 8012abc:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 8012ac0:	b29b      	uxth	r3, r3
 8012ac2:	2b00      	cmp	r3, #0
 8012ac4:	f040 80a1 	bne.w	8012c0a <UART_RxISR_16BIT+0x1aa>
    {
      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 8012ac8:	687b      	ldr	r3, [r7, #4]
 8012aca:	681b      	ldr	r3, [r3, #0]
 8012acc:	64bb      	str	r3, [r7, #72]	@ 0x48
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012ace:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 8012ad0:	e853 3f00 	ldrex	r3, [r3]
 8012ad4:	647b      	str	r3, [r7, #68]	@ 0x44
   return(result);
 8012ad6:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 8012ad8:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 8012adc:	667b      	str	r3, [r7, #100]	@ 0x64
 8012ade:	687b      	ldr	r3, [r7, #4]
 8012ae0:	681b      	ldr	r3, [r3, #0]
 8012ae2:	461a      	mov	r2, r3
 8012ae4:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 8012ae6:	657b      	str	r3, [r7, #84]	@ 0x54
 8012ae8:	653a      	str	r2, [r7, #80]	@ 0x50
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012aea:	6d39      	ldr	r1, [r7, #80]	@ 0x50
 8012aec:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
 8012aee:	e841 2300 	strex	r3, r2, [r1]
 8012af2:	64fb      	str	r3, [r7, #76]	@ 0x4c
   return(result);
 8012af4:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8012af6:	2b00      	cmp	r3, #0
 8012af8:	d1e6      	bne.n	8012ac8 <UART_RxISR_16BIT+0x68>

      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8012afa:	687b      	ldr	r3, [r7, #4]
 8012afc:	681b      	ldr	r3, [r3, #0]
 8012afe:	3308      	adds	r3, #8
 8012b00:	637b      	str	r3, [r7, #52]	@ 0x34
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012b02:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8012b04:	e853 3f00 	ldrex	r3, [r3]
 8012b08:	633b      	str	r3, [r7, #48]	@ 0x30
   return(result);
 8012b0a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012b0c:	f023 0301 	bic.w	r3, r3, #1
 8012b10:	663b      	str	r3, [r7, #96]	@ 0x60
 8012b12:	687b      	ldr	r3, [r7, #4]
 8012b14:	681b      	ldr	r3, [r3, #0]
 8012b16:	3308      	adds	r3, #8
 8012b18:	6e3a      	ldr	r2, [r7, #96]	@ 0x60
 8012b1a:	643a      	str	r2, [r7, #64]	@ 0x40
 8012b1c:	63fb      	str	r3, [r7, #60]	@ 0x3c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012b1e:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
 8012b20:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
 8012b22:	e841 2300 	strex	r3, r2, [r1]
 8012b26:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 8012b28:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8012b2a:	2b00      	cmp	r3, #0
 8012b2c:	d1e5      	bne.n	8012afa <UART_RxISR_16BIT+0x9a>

      /* Rx process is completed, restore huart->RxState to Ready */
      huart->RxState = HAL_UART_STATE_READY;
 8012b2e:	687b      	ldr	r3, [r7, #4]
 8012b30:	2220      	movs	r2, #32
 8012b32:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c

      /* Clear RxISR function pointer */
      huart->RxISR = NULL;
 8012b36:	687b      	ldr	r3, [r7, #4]
 8012b38:	2200      	movs	r2, #0
 8012b3a:	675a      	str	r2, [r3, #116]	@ 0x74

      /* Initialize type of RxEvent to Transfer Complete */
      huart->RxEventType = HAL_UART_RXEVENT_TC;
 8012b3c:	687b      	ldr	r3, [r7, #4]
 8012b3e:	2200      	movs	r2, #0
 8012b40:	671a      	str	r2, [r3, #112]	@ 0x70

      if (!(IS_LPUART_INSTANCE(huart->Instance)))
 8012b42:	687b      	ldr	r3, [r7, #4]
 8012b44:	681b      	ldr	r3, [r3, #0]
 8012b46:	4a33      	ldr	r2, [pc, #204]	@ (8012c14 <UART_RxISR_16BIT+0x1b4>)
 8012b48:	4293      	cmp	r3, r2
 8012b4a:	d01f      	beq.n	8012b8c <UART_RxISR_16BIT+0x12c>
      {
        /* Check that USART RTOEN bit is set */
        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
 8012b4c:	687b      	ldr	r3, [r7, #4]
 8012b4e:	681b      	ldr	r3, [r3, #0]
 8012b50:	685b      	ldr	r3, [r3, #4]
 8012b52:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 8012b56:	2b00      	cmp	r3, #0
 8012b58:	d018      	beq.n	8012b8c <UART_RxISR_16BIT+0x12c>
        {
          /* Enable the UART Receiver Timeout Interrupt */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
 8012b5a:	687b      	ldr	r3, [r7, #4]
 8012b5c:	681b      	ldr	r3, [r3, #0]
 8012b5e:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012b60:	6a3b      	ldr	r3, [r7, #32]
 8012b62:	e853 3f00 	ldrex	r3, [r3]
 8012b66:	61fb      	str	r3, [r7, #28]
   return(result);
 8012b68:	69fb      	ldr	r3, [r7, #28]
 8012b6a:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 8012b6e:	65fb      	str	r3, [r7, #92]	@ 0x5c
 8012b70:	687b      	ldr	r3, [r7, #4]
 8012b72:	681b      	ldr	r3, [r3, #0]
 8012b74:	461a      	mov	r2, r3
 8012b76:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 8012b78:	62fb      	str	r3, [r7, #44]	@ 0x2c
 8012b7a:	62ba      	str	r2, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012b7c:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 8012b7e:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8012b80:	e841 2300 	strex	r3, r2, [r1]
 8012b84:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 8012b86:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8012b88:	2b00      	cmp	r3, #0
 8012b8a:	d1e6      	bne.n	8012b5a <UART_RxISR_16BIT+0xfa>
        }
      }

      /* Check current reception Mode :
         If Reception till IDLE event has been selected : */
      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8012b8c:	687b      	ldr	r3, [r7, #4]
 8012b8e:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8012b90:	2b01      	cmp	r3, #1
 8012b92:	d12e      	bne.n	8012bf2 <UART_RxISR_16BIT+0x192>
      {
        /* Set reception type to Standard */
        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8012b94:	687b      	ldr	r3, [r7, #4]
 8012b96:	2200      	movs	r2, #0
 8012b98:	66da      	str	r2, [r3, #108]	@ 0x6c

        /* Disable IDLE interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 8012b9a:	687b      	ldr	r3, [r7, #4]
 8012b9c:	681b      	ldr	r3, [r3, #0]
 8012b9e:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012ba0:	68fb      	ldr	r3, [r7, #12]
 8012ba2:	e853 3f00 	ldrex	r3, [r3]
 8012ba6:	60bb      	str	r3, [r7, #8]
   return(result);
 8012ba8:	68bb      	ldr	r3, [r7, #8]
 8012baa:	f023 0310 	bic.w	r3, r3, #16
 8012bae:	65bb      	str	r3, [r7, #88]	@ 0x58
 8012bb0:	687b      	ldr	r3, [r7, #4]
 8012bb2:	681b      	ldr	r3, [r3, #0]
 8012bb4:	461a      	mov	r2, r3
 8012bb6:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
 8012bb8:	61bb      	str	r3, [r7, #24]
 8012bba:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012bbc:	6979      	ldr	r1, [r7, #20]
 8012bbe:	69ba      	ldr	r2, [r7, #24]
 8012bc0:	e841 2300 	strex	r3, r2, [r1]
 8012bc4:	613b      	str	r3, [r7, #16]
   return(result);
 8012bc6:	693b      	ldr	r3, [r7, #16]
 8012bc8:	2b00      	cmp	r3, #0
 8012bca:	d1e6      	bne.n	8012b9a <UART_RxISR_16BIT+0x13a>

        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
 8012bcc:	687b      	ldr	r3, [r7, #4]
 8012bce:	681b      	ldr	r3, [r3, #0]
 8012bd0:	69db      	ldr	r3, [r3, #28]
 8012bd2:	f003 0310 	and.w	r3, r3, #16
 8012bd6:	2b10      	cmp	r3, #16
 8012bd8:	d103      	bne.n	8012be2 <UART_RxISR_16BIT+0x182>
        {
          /* Clear IDLE Flag */
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 8012bda:	687b      	ldr	r3, [r7, #4]
 8012bdc:	681b      	ldr	r3, [r3, #0]
 8012bde:	2210      	movs	r2, #16
 8012be0:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered Rx Event callback*/
        huart->RxEventCallback(huart, huart->RxXferSize);
#else
        /*Call legacy weak Rx Event callback*/
        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
 8012be2:	687b      	ldr	r3, [r7, #4]
 8012be4:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
 8012be8:	4619      	mov	r1, r3
 8012bea:	6878      	ldr	r0, [r7, #4]
 8012bec:	f7f1 fb8c 	bl	8004308 <HAL_UARTEx_RxEventCallback>
  else
  {
    /* Clear RXNE interrupt flag */
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  }
}
 8012bf0:	e00b      	b.n	8012c0a <UART_RxISR_16BIT+0x1aa>
        HAL_UART_RxCpltCallback(huart);
 8012bf2:	6878      	ldr	r0, [r7, #4]
 8012bf4:	f7f1 fb7e 	bl	80042f4 <HAL_UART_RxCpltCallback>
}
 8012bf8:	e007      	b.n	8012c0a <UART_RxISR_16BIT+0x1aa>
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
 8012bfa:	687b      	ldr	r3, [r7, #4]
 8012bfc:	681b      	ldr	r3, [r3, #0]
 8012bfe:	699a      	ldr	r2, [r3, #24]
 8012c00:	687b      	ldr	r3, [r7, #4]
 8012c02:	681b      	ldr	r3, [r3, #0]
 8012c04:	f042 0208 	orr.w	r2, r2, #8
 8012c08:	619a      	str	r2, [r3, #24]
}
 8012c0a:	bf00      	nop
 8012c0c:	3770      	adds	r7, #112	@ 0x70
 8012c0e:	46bd      	mov	sp, r7
 8012c10:	bd80      	pop	{r7, pc}
 8012c12:	bf00      	nop
 8012c14:	58000c00 	.word	0x58000c00

08012c18 <UART_RxISR_8BIT_FIFOEN>:
  *         interruptions have been enabled by HAL_UART_Receive_IT()
  * @param huart UART handle.
  * @retval None
  */
static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
{
 8012c18:	b580      	push	{r7, lr}
 8012c1a:	b0ac      	sub	sp, #176	@ 0xb0
 8012c1c:	af00      	add	r7, sp, #0
 8012c1e:	6078      	str	r0, [r7, #4]
  uint16_t  uhMask = huart->Mask;
 8012c20:	687b      	ldr	r3, [r7, #4]
 8012c22:	f8b3 3060 	ldrh.w	r3, [r3, #96]	@ 0x60
 8012c26:	f8a7 30aa 	strh.w	r3, [r7, #170]	@ 0xaa
  uint16_t  uhdata;
  uint16_t  nb_rx_data;
  uint16_t  rxdatacount;
  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
 8012c2a:	687b      	ldr	r3, [r7, #4]
 8012c2c:	681b      	ldr	r3, [r3, #0]
 8012c2e:	69db      	ldr	r3, [r3, #28]
 8012c30:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
 8012c34:	687b      	ldr	r3, [r7, #4]
 8012c36:	681b      	ldr	r3, [r3, #0]
 8012c38:	681b      	ldr	r3, [r3, #0]
 8012c3a:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
 8012c3e:	687b      	ldr	r3, [r7, #4]
 8012c40:	681b      	ldr	r3, [r3, #0]
 8012c42:	689b      	ldr	r3, [r3, #8]
 8012c44:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0

  /* Check that a Rx process is ongoing */
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 8012c48:	687b      	ldr	r3, [r7, #4]
 8012c4a:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 8012c4e:	2b22      	cmp	r3, #34	@ 0x22
 8012c50:	f040 8180 	bne.w	8012f54 <UART_RxISR_8BIT_FIFOEN+0x33c>
  {
    nb_rx_data = huart->NbRxDataToProcess;
 8012c54:	687b      	ldr	r3, [r7, #4]
 8012c56:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
 8012c5a:	f8a7 309e 	strh.w	r3, [r7, #158]	@ 0x9e
    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
 8012c5e:	e123      	b.n	8012ea8 <UART_RxISR_8BIT_FIFOEN+0x290>
    {
      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
 8012c60:	687b      	ldr	r3, [r7, #4]
 8012c62:	681b      	ldr	r3, [r3, #0]
 8012c64:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8012c66:	f8a7 309c 	strh.w	r3, [r7, #156]	@ 0x9c
      *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
 8012c6a:	f8b7 309c 	ldrh.w	r3, [r7, #156]	@ 0x9c
 8012c6e:	b2d9      	uxtb	r1, r3
 8012c70:	f8b7 30aa 	ldrh.w	r3, [r7, #170]	@ 0xaa
 8012c74:	b2da      	uxtb	r2, r3
 8012c76:	687b      	ldr	r3, [r7, #4]
 8012c78:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8012c7a:	400a      	ands	r2, r1
 8012c7c:	b2d2      	uxtb	r2, r2
 8012c7e:	701a      	strb	r2, [r3, #0]
      huart->pRxBuffPtr++;
 8012c80:	687b      	ldr	r3, [r7, #4]
 8012c82:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8012c84:	1c5a      	adds	r2, r3, #1
 8012c86:	687b      	ldr	r3, [r7, #4]
 8012c88:	659a      	str	r2, [r3, #88]	@ 0x58
      huart->RxXferCount--;
 8012c8a:	687b      	ldr	r3, [r7, #4]
 8012c8c:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 8012c90:	b29b      	uxth	r3, r3
 8012c92:	3b01      	subs	r3, #1
 8012c94:	b29a      	uxth	r2, r3
 8012c96:	687b      	ldr	r3, [r7, #4]
 8012c98:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
      isrflags = READ_REG(huart->Instance->ISR);
 8012c9c:	687b      	ldr	r3, [r7, #4]
 8012c9e:	681b      	ldr	r3, [r3, #0]
 8012ca0:	69db      	ldr	r3, [r3, #28]
 8012ca2:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac

      /* If some non blocking errors occurred */
      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
 8012ca6:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 8012caa:	f003 0307 	and.w	r3, r3, #7
 8012cae:	2b00      	cmp	r3, #0
 8012cb0:	d053      	beq.n	8012d5a <UART_RxISR_8BIT_FIFOEN+0x142>
      {
        /* UART parity error interrupt occurred -------------------------------------*/
        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
 8012cb2:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 8012cb6:	f003 0301 	and.w	r3, r3, #1
 8012cba:	2b00      	cmp	r3, #0
 8012cbc:	d011      	beq.n	8012ce2 <UART_RxISR_8BIT_FIFOEN+0xca>
 8012cbe:	f8d7 30a4 	ldr.w	r3, [r7, #164]	@ 0xa4
 8012cc2:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8012cc6:	2b00      	cmp	r3, #0
 8012cc8:	d00b      	beq.n	8012ce2 <UART_RxISR_8BIT_FIFOEN+0xca>
        {
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
 8012cca:	687b      	ldr	r3, [r7, #4]
 8012ccc:	681b      	ldr	r3, [r3, #0]
 8012cce:	2201      	movs	r2, #1
 8012cd0:	621a      	str	r2, [r3, #32]

          huart->ErrorCode |= HAL_UART_ERROR_PE;
 8012cd2:	687b      	ldr	r3, [r7, #4]
 8012cd4:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8012cd8:	f043 0201 	orr.w	r2, r3, #1
 8012cdc:	687b      	ldr	r3, [r7, #4]
 8012cde:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }

        /* UART frame error interrupt occurred --------------------------------------*/
        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 8012ce2:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 8012ce6:	f003 0302 	and.w	r3, r3, #2
 8012cea:	2b00      	cmp	r3, #0
 8012cec:	d011      	beq.n	8012d12 <UART_RxISR_8BIT_FIFOEN+0xfa>
 8012cee:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
 8012cf2:	f003 0301 	and.w	r3, r3, #1
 8012cf6:	2b00      	cmp	r3, #0
 8012cf8:	d00b      	beq.n	8012d12 <UART_RxISR_8BIT_FIFOEN+0xfa>
        {
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
 8012cfa:	687b      	ldr	r3, [r7, #4]
 8012cfc:	681b      	ldr	r3, [r3, #0]
 8012cfe:	2202      	movs	r2, #2
 8012d00:	621a      	str	r2, [r3, #32]

          huart->ErrorCode |= HAL_UART_ERROR_FE;
 8012d02:	687b      	ldr	r3, [r7, #4]
 8012d04:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8012d08:	f043 0204 	orr.w	r2, r3, #4
 8012d0c:	687b      	ldr	r3, [r7, #4]
 8012d0e:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }

        /* UART noise error interrupt occurred --------------------------------------*/
        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 8012d12:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 8012d16:	f003 0304 	and.w	r3, r3, #4
 8012d1a:	2b00      	cmp	r3, #0
 8012d1c:	d011      	beq.n	8012d42 <UART_RxISR_8BIT_FIFOEN+0x12a>
 8012d1e:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
 8012d22:	f003 0301 	and.w	r3, r3, #1
 8012d26:	2b00      	cmp	r3, #0
 8012d28:	d00b      	beq.n	8012d42 <UART_RxISR_8BIT_FIFOEN+0x12a>
        {
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
 8012d2a:	687b      	ldr	r3, [r7, #4]
 8012d2c:	681b      	ldr	r3, [r3, #0]
 8012d2e:	2204      	movs	r2, #4
 8012d30:	621a      	str	r2, [r3, #32]

          huart->ErrorCode |= HAL_UART_ERROR_NE;
 8012d32:	687b      	ldr	r3, [r7, #4]
 8012d34:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8012d38:	f043 0202 	orr.w	r2, r3, #2
 8012d3c:	687b      	ldr	r3, [r7, #4]
 8012d3e:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }

        /* Call UART Error Call back function if need be ----------------------------*/
        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
 8012d42:	687b      	ldr	r3, [r7, #4]
 8012d44:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8012d48:	2b00      	cmp	r3, #0
 8012d4a:	d006      	beq.n	8012d5a <UART_RxISR_8BIT_FIFOEN+0x142>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered error callback*/
          huart->ErrorCallback(huart);
#else
          /*Call legacy weak error callback*/
          HAL_UART_ErrorCallback(huart);
 8012d4c:	6878      	ldr	r0, [r7, #4]
 8012d4e:	f7fe fb13 	bl	8011378 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
          huart->ErrorCode = HAL_UART_ERROR_NONE;
 8012d52:	687b      	ldr	r3, [r7, #4]
 8012d54:	2200      	movs	r2, #0
 8012d56:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }
      }

      if (huart->RxXferCount == 0U)
 8012d5a:	687b      	ldr	r3, [r7, #4]
 8012d5c:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 8012d60:	b29b      	uxth	r3, r3
 8012d62:	2b00      	cmp	r3, #0
 8012d64:	f040 80a0 	bne.w	8012ea8 <UART_RxISR_8BIT_FIFOEN+0x290>
      {
        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 8012d68:	687b      	ldr	r3, [r7, #4]
 8012d6a:	681b      	ldr	r3, [r3, #0]
 8012d6c:	673b      	str	r3, [r7, #112]	@ 0x70
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012d6e:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
 8012d70:	e853 3f00 	ldrex	r3, [r3]
 8012d74:	66fb      	str	r3, [r7, #108]	@ 0x6c
   return(result);
 8012d76:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
 8012d78:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 8012d7c:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
 8012d80:	687b      	ldr	r3, [r7, #4]
 8012d82:	681b      	ldr	r3, [r3, #0]
 8012d84:	461a      	mov	r2, r3
 8012d86:	f8d7 3098 	ldr.w	r3, [r7, #152]	@ 0x98
 8012d8a:	67fb      	str	r3, [r7, #124]	@ 0x7c
 8012d8c:	67ba      	str	r2, [r7, #120]	@ 0x78
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012d8e:	6fb9      	ldr	r1, [r7, #120]	@ 0x78
 8012d90:	6ffa      	ldr	r2, [r7, #124]	@ 0x7c
 8012d92:	e841 2300 	strex	r3, r2, [r1]
 8012d96:	677b      	str	r3, [r7, #116]	@ 0x74
   return(result);
 8012d98:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
 8012d9a:	2b00      	cmp	r3, #0
 8012d9c:	d1e4      	bne.n	8012d68 <UART_RxISR_8BIT_FIFOEN+0x150>

        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
           and RX FIFO Threshold interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 8012d9e:	687b      	ldr	r3, [r7, #4]
 8012da0:	681b      	ldr	r3, [r3, #0]
 8012da2:	3308      	adds	r3, #8
 8012da4:	65fb      	str	r3, [r7, #92]	@ 0x5c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012da6:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
 8012da8:	e853 3f00 	ldrex	r3, [r3]
 8012dac:	65bb      	str	r3, [r7, #88]	@ 0x58
   return(result);
 8012dae:	6dba      	ldr	r2, [r7, #88]	@ 0x58
 8012db0:	4b6e      	ldr	r3, [pc, #440]	@ (8012f6c <UART_RxISR_8BIT_FIFOEN+0x354>)
 8012db2:	4013      	ands	r3, r2
 8012db4:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
 8012db8:	687b      	ldr	r3, [r7, #4]
 8012dba:	681b      	ldr	r3, [r3, #0]
 8012dbc:	3308      	adds	r3, #8
 8012dbe:	f8d7 2094 	ldr.w	r2, [r7, #148]	@ 0x94
 8012dc2:	66ba      	str	r2, [r7, #104]	@ 0x68
 8012dc4:	667b      	str	r3, [r7, #100]	@ 0x64
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012dc6:	6e79      	ldr	r1, [r7, #100]	@ 0x64
 8012dc8:	6eba      	ldr	r2, [r7, #104]	@ 0x68
 8012dca:	e841 2300 	strex	r3, r2, [r1]
 8012dce:	663b      	str	r3, [r7, #96]	@ 0x60
   return(result);
 8012dd0:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 8012dd2:	2b00      	cmp	r3, #0
 8012dd4:	d1e3      	bne.n	8012d9e <UART_RxISR_8BIT_FIFOEN+0x186>

        /* Rx process is completed, restore huart->RxState to Ready */
        huart->RxState = HAL_UART_STATE_READY;
 8012dd6:	687b      	ldr	r3, [r7, #4]
 8012dd8:	2220      	movs	r2, #32
 8012dda:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c

        /* Clear RxISR function pointer */
        huart->RxISR = NULL;
 8012dde:	687b      	ldr	r3, [r7, #4]
 8012de0:	2200      	movs	r2, #0
 8012de2:	675a      	str	r2, [r3, #116]	@ 0x74

        /* Initialize type of RxEvent to Transfer Complete */
        huart->RxEventType = HAL_UART_RXEVENT_TC;
 8012de4:	687b      	ldr	r3, [r7, #4]
 8012de6:	2200      	movs	r2, #0
 8012de8:	671a      	str	r2, [r3, #112]	@ 0x70

        if (!(IS_LPUART_INSTANCE(huart->Instance)))
 8012dea:	687b      	ldr	r3, [r7, #4]
 8012dec:	681b      	ldr	r3, [r3, #0]
 8012dee:	4a60      	ldr	r2, [pc, #384]	@ (8012f70 <UART_RxISR_8BIT_FIFOEN+0x358>)
 8012df0:	4293      	cmp	r3, r2
 8012df2:	d021      	beq.n	8012e38 <UART_RxISR_8BIT_FIFOEN+0x220>
        {
          /* Check that USART RTOEN bit is set */
          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
 8012df4:	687b      	ldr	r3, [r7, #4]
 8012df6:	681b      	ldr	r3, [r3, #0]
 8012df8:	685b      	ldr	r3, [r3, #4]
 8012dfa:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 8012dfe:	2b00      	cmp	r3, #0
 8012e00:	d01a      	beq.n	8012e38 <UART_RxISR_8BIT_FIFOEN+0x220>
          {
            /* Enable the UART Receiver Timeout Interrupt */
            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
 8012e02:	687b      	ldr	r3, [r7, #4]
 8012e04:	681b      	ldr	r3, [r3, #0]
 8012e06:	64bb      	str	r3, [r7, #72]	@ 0x48
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012e08:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 8012e0a:	e853 3f00 	ldrex	r3, [r3]
 8012e0e:	647b      	str	r3, [r7, #68]	@ 0x44
   return(result);
 8012e10:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 8012e12:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 8012e16:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
 8012e1a:	687b      	ldr	r3, [r7, #4]
 8012e1c:	681b      	ldr	r3, [r3, #0]
 8012e1e:	461a      	mov	r2, r3
 8012e20:	f8d7 3090 	ldr.w	r3, [r7, #144]	@ 0x90
 8012e24:	657b      	str	r3, [r7, #84]	@ 0x54
 8012e26:	653a      	str	r2, [r7, #80]	@ 0x50
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012e28:	6d39      	ldr	r1, [r7, #80]	@ 0x50
 8012e2a:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
 8012e2c:	e841 2300 	strex	r3, r2, [r1]
 8012e30:	64fb      	str	r3, [r7, #76]	@ 0x4c
   return(result);
 8012e32:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8012e34:	2b00      	cmp	r3, #0
 8012e36:	d1e4      	bne.n	8012e02 <UART_RxISR_8BIT_FIFOEN+0x1ea>
          }
        }

        /* Check current reception Mode :
           If Reception till IDLE event has been selected : */
        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8012e38:	687b      	ldr	r3, [r7, #4]
 8012e3a:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8012e3c:	2b01      	cmp	r3, #1
 8012e3e:	d130      	bne.n	8012ea2 <UART_RxISR_8BIT_FIFOEN+0x28a>
        {
          /* Set reception type to Standard */
          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8012e40:	687b      	ldr	r3, [r7, #4]
 8012e42:	2200      	movs	r2, #0
 8012e44:	66da      	str	r2, [r3, #108]	@ 0x6c

          /* Disable IDLE interrupt */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 8012e46:	687b      	ldr	r3, [r7, #4]
 8012e48:	681b      	ldr	r3, [r3, #0]
 8012e4a:	637b      	str	r3, [r7, #52]	@ 0x34
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012e4c:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8012e4e:	e853 3f00 	ldrex	r3, [r3]
 8012e52:	633b      	str	r3, [r7, #48]	@ 0x30
   return(result);
 8012e54:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8012e56:	f023 0310 	bic.w	r3, r3, #16
 8012e5a:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
 8012e5e:	687b      	ldr	r3, [r7, #4]
 8012e60:	681b      	ldr	r3, [r3, #0]
 8012e62:	461a      	mov	r2, r3
 8012e64:	f8d7 308c 	ldr.w	r3, [r7, #140]	@ 0x8c
 8012e68:	643b      	str	r3, [r7, #64]	@ 0x40
 8012e6a:	63fa      	str	r2, [r7, #60]	@ 0x3c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012e6c:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
 8012e6e:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
 8012e70:	e841 2300 	strex	r3, r2, [r1]
 8012e74:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 8012e76:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8012e78:	2b00      	cmp	r3, #0
 8012e7a:	d1e4      	bne.n	8012e46 <UART_RxISR_8BIT_FIFOEN+0x22e>

          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
 8012e7c:	687b      	ldr	r3, [r7, #4]
 8012e7e:	681b      	ldr	r3, [r3, #0]
 8012e80:	69db      	ldr	r3, [r3, #28]
 8012e82:	f003 0310 	and.w	r3, r3, #16
 8012e86:	2b10      	cmp	r3, #16
 8012e88:	d103      	bne.n	8012e92 <UART_RxISR_8BIT_FIFOEN+0x27a>
          {
            /* Clear IDLE Flag */
            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 8012e8a:	687b      	ldr	r3, [r7, #4]
 8012e8c:	681b      	ldr	r3, [r3, #0]
 8012e8e:	2210      	movs	r2, #16
 8012e90:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered Rx Event callback*/
          huart->RxEventCallback(huart, huart->RxXferSize);
#else
          /*Call legacy weak Rx Event callback*/
          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
 8012e92:	687b      	ldr	r3, [r7, #4]
 8012e94:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
 8012e98:	4619      	mov	r1, r3
 8012e9a:	6878      	ldr	r0, [r7, #4]
 8012e9c:	f7f1 fa34 	bl	8004308 <HAL_UARTEx_RxEventCallback>
 8012ea0:	e002      	b.n	8012ea8 <UART_RxISR_8BIT_FIFOEN+0x290>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered Rx complete callback*/
          huart->RxCpltCallback(huart);
#else
          /*Call legacy weak Rx complete callback*/
          HAL_UART_RxCpltCallback(huart);
 8012ea2:	6878      	ldr	r0, [r7, #4]
 8012ea4:	f7f1 fa26 	bl	80042f4 <HAL_UART_RxCpltCallback>
    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
 8012ea8:	f8b7 309e 	ldrh.w	r3, [r7, #158]	@ 0x9e
 8012eac:	2b00      	cmp	r3, #0
 8012eae:	d006      	beq.n	8012ebe <UART_RxISR_8BIT_FIFOEN+0x2a6>
 8012eb0:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 8012eb4:	f003 0320 	and.w	r3, r3, #32
 8012eb8:	2b00      	cmp	r3, #0
 8012eba:	f47f aed1 	bne.w	8012c60 <UART_RxISR_8BIT_FIFOEN+0x48>

    /* When remaining number of bytes to receive is less than the RX FIFO
    threshold, next incoming frames are processed as if FIFO mode was
    disabled (i.e. one interrupt per received frame).
    */
    rxdatacount = huart->RxXferCount;
 8012ebe:	687b      	ldr	r3, [r7, #4]
 8012ec0:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 8012ec4:	f8a7 308a 	strh.w	r3, [r7, #138]	@ 0x8a
    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
 8012ec8:	f8b7 308a 	ldrh.w	r3, [r7, #138]	@ 0x8a
 8012ecc:	2b00      	cmp	r3, #0
 8012ece:	d049      	beq.n	8012f64 <UART_RxISR_8BIT_FIFOEN+0x34c>
 8012ed0:	687b      	ldr	r3, [r7, #4]
 8012ed2:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
 8012ed6:	f8b7 208a 	ldrh.w	r2, [r7, #138]	@ 0x8a
 8012eda:	429a      	cmp	r2, r3
 8012edc:	d242      	bcs.n	8012f64 <UART_RxISR_8BIT_FIFOEN+0x34c>
    {
      /* Disable the UART RXFT interrupt*/
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
 8012ede:	687b      	ldr	r3, [r7, #4]
 8012ee0:	681b      	ldr	r3, [r3, #0]
 8012ee2:	3308      	adds	r3, #8
 8012ee4:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012ee6:	6a3b      	ldr	r3, [r7, #32]
 8012ee8:	e853 3f00 	ldrex	r3, [r3]
 8012eec:	61fb      	str	r3, [r7, #28]
   return(result);
 8012eee:	69fb      	ldr	r3, [r7, #28]
 8012ef0:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 8012ef4:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
 8012ef8:	687b      	ldr	r3, [r7, #4]
 8012efa:	681b      	ldr	r3, [r3, #0]
 8012efc:	3308      	adds	r3, #8
 8012efe:	f8d7 2084 	ldr.w	r2, [r7, #132]	@ 0x84
 8012f02:	62fa      	str	r2, [r7, #44]	@ 0x2c
 8012f04:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012f06:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 8012f08:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8012f0a:	e841 2300 	strex	r3, r2, [r1]
 8012f0e:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 8012f10:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8012f12:	2b00      	cmp	r3, #0
 8012f14:	d1e3      	bne.n	8012ede <UART_RxISR_8BIT_FIFOEN+0x2c6>

      /* Update the RxISR function pointer */
      huart->RxISR = UART_RxISR_8BIT;
 8012f16:	687b      	ldr	r3, [r7, #4]
 8012f18:	4a16      	ldr	r2, [pc, #88]	@ (8012f74 <UART_RxISR_8BIT_FIFOEN+0x35c>)
 8012f1a:	675a      	str	r2, [r3, #116]	@ 0x74

      /* Enable the UART Data Register Not Empty interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
 8012f1c:	687b      	ldr	r3, [r7, #4]
 8012f1e:	681b      	ldr	r3, [r3, #0]
 8012f20:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8012f22:	68fb      	ldr	r3, [r7, #12]
 8012f24:	e853 3f00 	ldrex	r3, [r3]
 8012f28:	60bb      	str	r3, [r7, #8]
   return(result);
 8012f2a:	68bb      	ldr	r3, [r7, #8]
 8012f2c:	f043 0320 	orr.w	r3, r3, #32
 8012f30:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
 8012f34:	687b      	ldr	r3, [r7, #4]
 8012f36:	681b      	ldr	r3, [r3, #0]
 8012f38:	461a      	mov	r2, r3
 8012f3a:	f8d7 3080 	ldr.w	r3, [r7, #128]	@ 0x80
 8012f3e:	61bb      	str	r3, [r7, #24]
 8012f40:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8012f42:	6979      	ldr	r1, [r7, #20]
 8012f44:	69ba      	ldr	r2, [r7, #24]
 8012f46:	e841 2300 	strex	r3, r2, [r1]
 8012f4a:	613b      	str	r3, [r7, #16]
   return(result);
 8012f4c:	693b      	ldr	r3, [r7, #16]
 8012f4e:	2b00      	cmp	r3, #0
 8012f50:	d1e4      	bne.n	8012f1c <UART_RxISR_8BIT_FIFOEN+0x304>
  else
  {
    /* Clear RXNE interrupt flag */
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  }
}
 8012f52:	e007      	b.n	8012f64 <UART_RxISR_8BIT_FIFOEN+0x34c>
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
 8012f54:	687b      	ldr	r3, [r7, #4]
 8012f56:	681b      	ldr	r3, [r3, #0]
 8012f58:	699a      	ldr	r2, [r3, #24]
 8012f5a:	687b      	ldr	r3, [r7, #4]
 8012f5c:	681b      	ldr	r3, [r3, #0]
 8012f5e:	f042 0208 	orr.w	r2, r2, #8
 8012f62:	619a      	str	r2, [r3, #24]
}
 8012f64:	bf00      	nop
 8012f66:	37b0      	adds	r7, #176	@ 0xb0
 8012f68:	46bd      	mov	sp, r7
 8012f6a:	bd80      	pop	{r7, pc}
 8012f6c:	effffffe 	.word	0xeffffffe
 8012f70:	58000c00 	.word	0x58000c00
 8012f74:	080128a9 	.word	0x080128a9

08012f78 <UART_RxISR_16BIT_FIFOEN>:
  *         interruptions have been enabled by HAL_UART_Receive_IT()
  * @param huart UART handle.
  * @retval None
  */
static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
{
 8012f78:	b580      	push	{r7, lr}
 8012f7a:	b0ae      	sub	sp, #184	@ 0xb8
 8012f7c:	af00      	add	r7, sp, #0
 8012f7e:	6078      	str	r0, [r7, #4]
  uint16_t *tmp;
  uint16_t  uhMask = huart->Mask;
 8012f80:	687b      	ldr	r3, [r7, #4]
 8012f82:	f8b3 3060 	ldrh.w	r3, [r3, #96]	@ 0x60
 8012f86:	f8a7 30b2 	strh.w	r3, [r7, #178]	@ 0xb2
  uint16_t  uhdata;
  uint16_t  nb_rx_data;
  uint16_t  rxdatacount;
  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
 8012f8a:	687b      	ldr	r3, [r7, #4]
 8012f8c:	681b      	ldr	r3, [r3, #0]
 8012f8e:	69db      	ldr	r3, [r3, #28]
 8012f90:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
 8012f94:	687b      	ldr	r3, [r7, #4]
 8012f96:	681b      	ldr	r3, [r3, #0]
 8012f98:	681b      	ldr	r3, [r3, #0]
 8012f9a:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
 8012f9e:	687b      	ldr	r3, [r7, #4]
 8012fa0:	681b      	ldr	r3, [r3, #0]
 8012fa2:	689b      	ldr	r3, [r3, #8]
 8012fa4:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8

  /* Check that a Rx process is ongoing */
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 8012fa8:	687b      	ldr	r3, [r7, #4]
 8012faa:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 8012fae:	2b22      	cmp	r3, #34	@ 0x22
 8012fb0:	f040 8184 	bne.w	80132bc <UART_RxISR_16BIT_FIFOEN+0x344>
  {
    nb_rx_data = huart->NbRxDataToProcess;
 8012fb4:	687b      	ldr	r3, [r7, #4]
 8012fb6:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
 8012fba:	f8a7 30a6 	strh.w	r3, [r7, #166]	@ 0xa6
    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
 8012fbe:	e127      	b.n	8013210 <UART_RxISR_16BIT_FIFOEN+0x298>
    {
      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
 8012fc0:	687b      	ldr	r3, [r7, #4]
 8012fc2:	681b      	ldr	r3, [r3, #0]
 8012fc4:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8012fc6:	f8a7 30a4 	strh.w	r3, [r7, #164]	@ 0xa4
      tmp = (uint16_t *) huart->pRxBuffPtr ;
 8012fca:	687b      	ldr	r3, [r7, #4]
 8012fcc:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8012fce:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
      *tmp = (uint16_t)(uhdata & uhMask);
 8012fd2:	f8b7 20a4 	ldrh.w	r2, [r7, #164]	@ 0xa4
 8012fd6:	f8b7 30b2 	ldrh.w	r3, [r7, #178]	@ 0xb2
 8012fda:	4013      	ands	r3, r2
 8012fdc:	b29a      	uxth	r2, r3
 8012fde:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
 8012fe2:	801a      	strh	r2, [r3, #0]
      huart->pRxBuffPtr += 2U;
 8012fe4:	687b      	ldr	r3, [r7, #4]
 8012fe6:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8012fe8:	1c9a      	adds	r2, r3, #2
 8012fea:	687b      	ldr	r3, [r7, #4]
 8012fec:	659a      	str	r2, [r3, #88]	@ 0x58
      huart->RxXferCount--;
 8012fee:	687b      	ldr	r3, [r7, #4]
 8012ff0:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 8012ff4:	b29b      	uxth	r3, r3
 8012ff6:	3b01      	subs	r3, #1
 8012ff8:	b29a      	uxth	r2, r3
 8012ffa:	687b      	ldr	r3, [r7, #4]
 8012ffc:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
      isrflags = READ_REG(huart->Instance->ISR);
 8013000:	687b      	ldr	r3, [r7, #4]
 8013002:	681b      	ldr	r3, [r3, #0]
 8013004:	69db      	ldr	r3, [r3, #28]
 8013006:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4

      /* If some non blocking errors occurred */
      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
 801300a:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
 801300e:	f003 0307 	and.w	r3, r3, #7
 8013012:	2b00      	cmp	r3, #0
 8013014:	d053      	beq.n	80130be <UART_RxISR_16BIT_FIFOEN+0x146>
      {
        /* UART parity error interrupt occurred -------------------------------------*/
        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
 8013016:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
 801301a:	f003 0301 	and.w	r3, r3, #1
 801301e:	2b00      	cmp	r3, #0
 8013020:	d011      	beq.n	8013046 <UART_RxISR_16BIT_FIFOEN+0xce>
 8013022:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
 8013026:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 801302a:	2b00      	cmp	r3, #0
 801302c:	d00b      	beq.n	8013046 <UART_RxISR_16BIT_FIFOEN+0xce>
        {
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
 801302e:	687b      	ldr	r3, [r7, #4]
 8013030:	681b      	ldr	r3, [r3, #0]
 8013032:	2201      	movs	r2, #1
 8013034:	621a      	str	r2, [r3, #32]

          huart->ErrorCode |= HAL_UART_ERROR_PE;
 8013036:	687b      	ldr	r3, [r7, #4]
 8013038:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 801303c:	f043 0201 	orr.w	r2, r3, #1
 8013040:	687b      	ldr	r3, [r7, #4]
 8013042:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }

        /* UART frame error interrupt occurred --------------------------------------*/
        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 8013046:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
 801304a:	f003 0302 	and.w	r3, r3, #2
 801304e:	2b00      	cmp	r3, #0
 8013050:	d011      	beq.n	8013076 <UART_RxISR_16BIT_FIFOEN+0xfe>
 8013052:	f8d7 30a8 	ldr.w	r3, [r7, #168]	@ 0xa8
 8013056:	f003 0301 	and.w	r3, r3, #1
 801305a:	2b00      	cmp	r3, #0
 801305c:	d00b      	beq.n	8013076 <UART_RxISR_16BIT_FIFOEN+0xfe>
        {
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
 801305e:	687b      	ldr	r3, [r7, #4]
 8013060:	681b      	ldr	r3, [r3, #0]
 8013062:	2202      	movs	r2, #2
 8013064:	621a      	str	r2, [r3, #32]

          huart->ErrorCode |= HAL_UART_ERROR_FE;
 8013066:	687b      	ldr	r3, [r7, #4]
 8013068:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 801306c:	f043 0204 	orr.w	r2, r3, #4
 8013070:	687b      	ldr	r3, [r7, #4]
 8013072:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }

        /* UART noise error interrupt occurred --------------------------------------*/
        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
 8013076:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
 801307a:	f003 0304 	and.w	r3, r3, #4
 801307e:	2b00      	cmp	r3, #0
 8013080:	d011      	beq.n	80130a6 <UART_RxISR_16BIT_FIFOEN+0x12e>
 8013082:	f8d7 30a8 	ldr.w	r3, [r7, #168]	@ 0xa8
 8013086:	f003 0301 	and.w	r3, r3, #1
 801308a:	2b00      	cmp	r3, #0
 801308c:	d00b      	beq.n	80130a6 <UART_RxISR_16BIT_FIFOEN+0x12e>
        {
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
 801308e:	687b      	ldr	r3, [r7, #4]
 8013090:	681b      	ldr	r3, [r3, #0]
 8013092:	2204      	movs	r2, #4
 8013094:	621a      	str	r2, [r3, #32]

          huart->ErrorCode |= HAL_UART_ERROR_NE;
 8013096:	687b      	ldr	r3, [r7, #4]
 8013098:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 801309c:	f043 0202 	orr.w	r2, r3, #2
 80130a0:	687b      	ldr	r3, [r7, #4]
 80130a2:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }

        /* Call UART Error Call back function if need be ----------------------------*/
        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
 80130a6:	687b      	ldr	r3, [r7, #4]
 80130a8:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 80130ac:	2b00      	cmp	r3, #0
 80130ae:	d006      	beq.n	80130be <UART_RxISR_16BIT_FIFOEN+0x146>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered error callback*/
          huart->ErrorCallback(huart);
#else
          /*Call legacy weak error callback*/
          HAL_UART_ErrorCallback(huart);
 80130b0:	6878      	ldr	r0, [r7, #4]
 80130b2:	f7fe f961 	bl	8011378 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
          huart->ErrorCode = HAL_UART_ERROR_NONE;
 80130b6:	687b      	ldr	r3, [r7, #4]
 80130b8:	2200      	movs	r2, #0
 80130ba:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
        }
      }

      if (huart->RxXferCount == 0U)
 80130be:	687b      	ldr	r3, [r7, #4]
 80130c0:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 80130c4:	b29b      	uxth	r3, r3
 80130c6:	2b00      	cmp	r3, #0
 80130c8:	f040 80a2 	bne.w	8013210 <UART_RxISR_16BIT_FIFOEN+0x298>
      {
        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 80130cc:	687b      	ldr	r3, [r7, #4]
 80130ce:	681b      	ldr	r3, [r3, #0]
 80130d0:	677b      	str	r3, [r7, #116]	@ 0x74
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80130d2:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
 80130d4:	e853 3f00 	ldrex	r3, [r3]
 80130d8:	673b      	str	r3, [r7, #112]	@ 0x70
   return(result);
 80130da:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
 80130dc:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 80130e0:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
 80130e4:	687b      	ldr	r3, [r7, #4]
 80130e6:	681b      	ldr	r3, [r3, #0]
 80130e8:	461a      	mov	r2, r3
 80130ea:	f8d7 309c 	ldr.w	r3, [r7, #156]	@ 0x9c
 80130ee:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
 80130f2:	67fa      	str	r2, [r7, #124]	@ 0x7c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80130f4:	6ff9      	ldr	r1, [r7, #124]	@ 0x7c
 80130f6:	f8d7 2080 	ldr.w	r2, [r7, #128]	@ 0x80
 80130fa:	e841 2300 	strex	r3, r2, [r1]
 80130fe:	67bb      	str	r3, [r7, #120]	@ 0x78
   return(result);
 8013100:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
 8013102:	2b00      	cmp	r3, #0
 8013104:	d1e2      	bne.n	80130cc <UART_RxISR_16BIT_FIFOEN+0x154>

        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
           and RX FIFO Threshold interrupt */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 8013106:	687b      	ldr	r3, [r7, #4]
 8013108:	681b      	ldr	r3, [r3, #0]
 801310a:	3308      	adds	r3, #8
 801310c:	663b      	str	r3, [r7, #96]	@ 0x60
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 801310e:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
 8013110:	e853 3f00 	ldrex	r3, [r3]
 8013114:	65fb      	str	r3, [r7, #92]	@ 0x5c
   return(result);
 8013116:	6dfa      	ldr	r2, [r7, #92]	@ 0x5c
 8013118:	4b6e      	ldr	r3, [pc, #440]	@ (80132d4 <UART_RxISR_16BIT_FIFOEN+0x35c>)
 801311a:	4013      	ands	r3, r2
 801311c:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
 8013120:	687b      	ldr	r3, [r7, #4]
 8013122:	681b      	ldr	r3, [r3, #0]
 8013124:	3308      	adds	r3, #8
 8013126:	f8d7 2098 	ldr.w	r2, [r7, #152]	@ 0x98
 801312a:	66fa      	str	r2, [r7, #108]	@ 0x6c
 801312c:	66bb      	str	r3, [r7, #104]	@ 0x68
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 801312e:	6eb9      	ldr	r1, [r7, #104]	@ 0x68
 8013130:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
 8013132:	e841 2300 	strex	r3, r2, [r1]
 8013136:	667b      	str	r3, [r7, #100]	@ 0x64
   return(result);
 8013138:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
 801313a:	2b00      	cmp	r3, #0
 801313c:	d1e3      	bne.n	8013106 <UART_RxISR_16BIT_FIFOEN+0x18e>

        /* Rx process is completed, restore huart->RxState to Ready */
        huart->RxState = HAL_UART_STATE_READY;
 801313e:	687b      	ldr	r3, [r7, #4]
 8013140:	2220      	movs	r2, #32
 8013142:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c

        /* Clear RxISR function pointer */
        huart->RxISR = NULL;
 8013146:	687b      	ldr	r3, [r7, #4]
 8013148:	2200      	movs	r2, #0
 801314a:	675a      	str	r2, [r3, #116]	@ 0x74

        /* Initialize type of RxEvent to Transfer Complete */
        huart->RxEventType = HAL_UART_RXEVENT_TC;
 801314c:	687b      	ldr	r3, [r7, #4]
 801314e:	2200      	movs	r2, #0
 8013150:	671a      	str	r2, [r3, #112]	@ 0x70

        if (!(IS_LPUART_INSTANCE(huart->Instance)))
 8013152:	687b      	ldr	r3, [r7, #4]
 8013154:	681b      	ldr	r3, [r3, #0]
 8013156:	4a60      	ldr	r2, [pc, #384]	@ (80132d8 <UART_RxISR_16BIT_FIFOEN+0x360>)
 8013158:	4293      	cmp	r3, r2
 801315a:	d021      	beq.n	80131a0 <UART_RxISR_16BIT_FIFOEN+0x228>
        {
          /* Check that USART RTOEN bit is set */
          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
 801315c:	687b      	ldr	r3, [r7, #4]
 801315e:	681b      	ldr	r3, [r3, #0]
 8013160:	685b      	ldr	r3, [r3, #4]
 8013162:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
 8013166:	2b00      	cmp	r3, #0
 8013168:	d01a      	beq.n	80131a0 <UART_RxISR_16BIT_FIFOEN+0x228>
          {
            /* Enable the UART Receiver Timeout Interrupt */
            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
 801316a:	687b      	ldr	r3, [r7, #4]
 801316c:	681b      	ldr	r3, [r3, #0]
 801316e:	64fb      	str	r3, [r7, #76]	@ 0x4c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8013170:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8013172:	e853 3f00 	ldrex	r3, [r3]
 8013176:	64bb      	str	r3, [r7, #72]	@ 0x48
   return(result);
 8013178:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 801317a:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 801317e:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
 8013182:	687b      	ldr	r3, [r7, #4]
 8013184:	681b      	ldr	r3, [r3, #0]
 8013186:	461a      	mov	r2, r3
 8013188:	f8d7 3094 	ldr.w	r3, [r7, #148]	@ 0x94
 801318c:	65bb      	str	r3, [r7, #88]	@ 0x58
 801318e:	657a      	str	r2, [r7, #84]	@ 0x54
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8013190:	6d79      	ldr	r1, [r7, #84]	@ 0x54
 8013192:	6dba      	ldr	r2, [r7, #88]	@ 0x58
 8013194:	e841 2300 	strex	r3, r2, [r1]
 8013198:	653b      	str	r3, [r7, #80]	@ 0x50
   return(result);
 801319a:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 801319c:	2b00      	cmp	r3, #0
 801319e:	d1e4      	bne.n	801316a <UART_RxISR_16BIT_FIFOEN+0x1f2>
          }
        }

        /* Check current reception Mode :
           If Reception till IDLE event has been selected : */
        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 80131a0:	687b      	ldr	r3, [r7, #4]
 80131a2:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 80131a4:	2b01      	cmp	r3, #1
 80131a6:	d130      	bne.n	801320a <UART_RxISR_16BIT_FIFOEN+0x292>
        {
          /* Set reception type to Standard */
          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 80131a8:	687b      	ldr	r3, [r7, #4]
 80131aa:	2200      	movs	r2, #0
 80131ac:	66da      	str	r2, [r3, #108]	@ 0x6c

          /* Disable IDLE interrupt */
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 80131ae:	687b      	ldr	r3, [r7, #4]
 80131b0:	681b      	ldr	r3, [r3, #0]
 80131b2:	63bb      	str	r3, [r7, #56]	@ 0x38
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80131b4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80131b6:	e853 3f00 	ldrex	r3, [r3]
 80131ba:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 80131bc:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80131be:	f023 0310 	bic.w	r3, r3, #16
 80131c2:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
 80131c6:	687b      	ldr	r3, [r7, #4]
 80131c8:	681b      	ldr	r3, [r3, #0]
 80131ca:	461a      	mov	r2, r3
 80131cc:	f8d7 3090 	ldr.w	r3, [r7, #144]	@ 0x90
 80131d0:	647b      	str	r3, [r7, #68]	@ 0x44
 80131d2:	643a      	str	r2, [r7, #64]	@ 0x40
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80131d4:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 80131d6:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 80131d8:	e841 2300 	strex	r3, r2, [r1]
 80131dc:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 80131de:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 80131e0:	2b00      	cmp	r3, #0
 80131e2:	d1e4      	bne.n	80131ae <UART_RxISR_16BIT_FIFOEN+0x236>

          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
 80131e4:	687b      	ldr	r3, [r7, #4]
 80131e6:	681b      	ldr	r3, [r3, #0]
 80131e8:	69db      	ldr	r3, [r3, #28]
 80131ea:	f003 0310 	and.w	r3, r3, #16
 80131ee:	2b10      	cmp	r3, #16
 80131f0:	d103      	bne.n	80131fa <UART_RxISR_16BIT_FIFOEN+0x282>
          {
            /* Clear IDLE Flag */
            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 80131f2:	687b      	ldr	r3, [r7, #4]
 80131f4:	681b      	ldr	r3, [r3, #0]
 80131f6:	2210      	movs	r2, #16
 80131f8:	621a      	str	r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered Rx Event callback*/
          huart->RxEventCallback(huart, huart->RxXferSize);
#else
          /*Call legacy weak Rx Event callback*/
          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
 80131fa:	687b      	ldr	r3, [r7, #4]
 80131fc:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
 8013200:	4619      	mov	r1, r3
 8013202:	6878      	ldr	r0, [r7, #4]
 8013204:	f7f1 f880 	bl	8004308 <HAL_UARTEx_RxEventCallback>
 8013208:	e002      	b.n	8013210 <UART_RxISR_16BIT_FIFOEN+0x298>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered Rx complete callback*/
          huart->RxCpltCallback(huart);
#else
          /*Call legacy weak Rx complete callback*/
          HAL_UART_RxCpltCallback(huart);
 801320a:	6878      	ldr	r0, [r7, #4]
 801320c:	f7f1 f872 	bl	80042f4 <HAL_UART_RxCpltCallback>
    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
 8013210:	f8b7 30a6 	ldrh.w	r3, [r7, #166]	@ 0xa6
 8013214:	2b00      	cmp	r3, #0
 8013216:	d006      	beq.n	8013226 <UART_RxISR_16BIT_FIFOEN+0x2ae>
 8013218:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
 801321c:	f003 0320 	and.w	r3, r3, #32
 8013220:	2b00      	cmp	r3, #0
 8013222:	f47f aecd 	bne.w	8012fc0 <UART_RxISR_16BIT_FIFOEN+0x48>

    /* When remaining number of bytes to receive is less than the RX FIFO
    threshold, next incoming frames are processed as if FIFO mode was
    disabled (i.e. one interrupt per received frame).
    */
    rxdatacount = huart->RxXferCount;
 8013226:	687b      	ldr	r3, [r7, #4]
 8013228:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
 801322c:	f8a7 308e 	strh.w	r3, [r7, #142]	@ 0x8e
    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
 8013230:	f8b7 308e 	ldrh.w	r3, [r7, #142]	@ 0x8e
 8013234:	2b00      	cmp	r3, #0
 8013236:	d049      	beq.n	80132cc <UART_RxISR_16BIT_FIFOEN+0x354>
 8013238:	687b      	ldr	r3, [r7, #4]
 801323a:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
 801323e:	f8b7 208e 	ldrh.w	r2, [r7, #142]	@ 0x8e
 8013242:	429a      	cmp	r2, r3
 8013244:	d242      	bcs.n	80132cc <UART_RxISR_16BIT_FIFOEN+0x354>
    {
      /* Disable the UART RXFT interrupt*/
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
 8013246:	687b      	ldr	r3, [r7, #4]
 8013248:	681b      	ldr	r3, [r3, #0]
 801324a:	3308      	adds	r3, #8
 801324c:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 801324e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8013250:	e853 3f00 	ldrex	r3, [r3]
 8013254:	623b      	str	r3, [r7, #32]
   return(result);
 8013256:	6a3b      	ldr	r3, [r7, #32]
 8013258:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 801325c:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
 8013260:	687b      	ldr	r3, [r7, #4]
 8013262:	681b      	ldr	r3, [r3, #0]
 8013264:	3308      	adds	r3, #8
 8013266:	f8d7 2088 	ldr.w	r2, [r7, #136]	@ 0x88
 801326a:	633a      	str	r2, [r7, #48]	@ 0x30
 801326c:	62fb      	str	r3, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 801326e:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 8013270:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8013272:	e841 2300 	strex	r3, r2, [r1]
 8013276:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 8013278:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 801327a:	2b00      	cmp	r3, #0
 801327c:	d1e3      	bne.n	8013246 <UART_RxISR_16BIT_FIFOEN+0x2ce>

      /* Update the RxISR function pointer */
      huart->RxISR = UART_RxISR_16BIT;
 801327e:	687b      	ldr	r3, [r7, #4]
 8013280:	4a16      	ldr	r2, [pc, #88]	@ (80132dc <UART_RxISR_16BIT_FIFOEN+0x364>)
 8013282:	675a      	str	r2, [r3, #116]	@ 0x74

      /* Enable the UART Data Register Not Empty interrupt */
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
 8013284:	687b      	ldr	r3, [r7, #4]
 8013286:	681b      	ldr	r3, [r3, #0]
 8013288:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 801328a:	693b      	ldr	r3, [r7, #16]
 801328c:	e853 3f00 	ldrex	r3, [r3]
 8013290:	60fb      	str	r3, [r7, #12]
   return(result);
 8013292:	68fb      	ldr	r3, [r7, #12]
 8013294:	f043 0320 	orr.w	r3, r3, #32
 8013298:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
 801329c:	687b      	ldr	r3, [r7, #4]
 801329e:	681b      	ldr	r3, [r3, #0]
 80132a0:	461a      	mov	r2, r3
 80132a2:	f8d7 3084 	ldr.w	r3, [r7, #132]	@ 0x84
 80132a6:	61fb      	str	r3, [r7, #28]
 80132a8:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80132aa:	69b9      	ldr	r1, [r7, #24]
 80132ac:	69fa      	ldr	r2, [r7, #28]
 80132ae:	e841 2300 	strex	r3, r2, [r1]
 80132b2:	617b      	str	r3, [r7, #20]
   return(result);
 80132b4:	697b      	ldr	r3, [r7, #20]
 80132b6:	2b00      	cmp	r3, #0
 80132b8:	d1e4      	bne.n	8013284 <UART_RxISR_16BIT_FIFOEN+0x30c>
  else
  {
    /* Clear RXNE interrupt flag */
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  }
}
 80132ba:	e007      	b.n	80132cc <UART_RxISR_16BIT_FIFOEN+0x354>
    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
 80132bc:	687b      	ldr	r3, [r7, #4]
 80132be:	681b      	ldr	r3, [r3, #0]
 80132c0:	699a      	ldr	r2, [r3, #24]
 80132c2:	687b      	ldr	r3, [r7, #4]
 80132c4:	681b      	ldr	r3, [r3, #0]
 80132c6:	f042 0208 	orr.w	r2, r2, #8
 80132ca:	619a      	str	r2, [r3, #24]
}
 80132cc:	bf00      	nop
 80132ce:	37b8      	adds	r7, #184	@ 0xb8
 80132d0:	46bd      	mov	sp, r7
 80132d2:	bd80      	pop	{r7, pc}
 80132d4:	effffffe 	.word	0xeffffffe
 80132d8:	58000c00 	.word	0x58000c00
 80132dc:	08012a61 	.word	0x08012a61

080132e0 <HAL_UARTEx_WakeupCallback>:
  * @brief UART wakeup from Stop mode callback.
  * @param huart UART handle.
  * @retval None
  */
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
 80132e0:	b480      	push	{r7}
 80132e2:	b083      	sub	sp, #12
 80132e4:	af00      	add	r7, sp, #0
 80132e6:	6078      	str	r0, [r7, #4]
  UNUSED(huart);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
   */
}
 80132e8:	bf00      	nop
 80132ea:	370c      	adds	r7, #12
 80132ec:	46bd      	mov	sp, r7
 80132ee:	f85d 7b04 	ldr.w	r7, [sp], #4
 80132f2:	4770      	bx	lr

080132f4 <HAL_UARTEx_RxFifoFullCallback>:
  * @brief  UART RX Fifo full callback.
  * @param  huart UART handle.
  * @retval None
  */
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
{
 80132f4:	b480      	push	{r7}
 80132f6:	b083      	sub	sp, #12
 80132f8:	af00      	add	r7, sp, #0
 80132fa:	6078      	str	r0, [r7, #4]
  UNUSED(huart);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
   */
}
 80132fc:	bf00      	nop
 80132fe:	370c      	adds	r7, #12
 8013300:	46bd      	mov	sp, r7
 8013302:	f85d 7b04 	ldr.w	r7, [sp], #4
 8013306:	4770      	bx	lr

08013308 <HAL_UARTEx_TxFifoEmptyCallback>:
  * @brief  UART TX Fifo empty callback.
  * @param  huart UART handle.
  * @retval None
  */
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
{
 8013308:	b480      	push	{r7}
 801330a:	b083      	sub	sp, #12
 801330c:	af00      	add	r7, sp, #0
 801330e:	6078      	str	r0, [r7, #4]
  UNUSED(huart);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
   */
}
 8013310:	bf00      	nop
 8013312:	370c      	adds	r7, #12
 8013314:	46bd      	mov	sp, r7
 8013316:	f85d 7b04 	ldr.w	r7, [sp], #4
 801331a:	4770      	bx	lr

0801331c <HAL_UARTEx_DisableFifoMode>:
  * @brief  Disable the FIFO mode.
  * @param huart      UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
{
 801331c:	b480      	push	{r7}
 801331e:	b085      	sub	sp, #20
 8013320:	af00      	add	r7, sp, #0
 8013322:	6078      	str	r0, [r7, #4]

  /* Check parameters */
  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));

  /* Process Locked */
  __HAL_LOCK(huart);
 8013324:	687b      	ldr	r3, [r7, #4]
 8013326:	f893 3084 	ldrb.w	r3, [r3, #132]	@ 0x84
 801332a:	2b01      	cmp	r3, #1
 801332c:	d101      	bne.n	8013332 <HAL_UARTEx_DisableFifoMode+0x16>
 801332e:	2302      	movs	r3, #2
 8013330:	e027      	b.n	8013382 <HAL_UARTEx_DisableFifoMode+0x66>
 8013332:	687b      	ldr	r3, [r7, #4]
 8013334:	2201      	movs	r2, #1
 8013336:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  huart->gState = HAL_UART_STATE_BUSY;
 801333a:	687b      	ldr	r3, [r7, #4]
 801333c:	2224      	movs	r2, #36	@ 0x24
 801333e:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Save actual UART configuration */
  tmpcr1 = READ_REG(huart->Instance->CR1);
 8013342:	687b      	ldr	r3, [r7, #4]
 8013344:	681b      	ldr	r3, [r3, #0]
 8013346:	681b      	ldr	r3, [r3, #0]
 8013348:	60fb      	str	r3, [r7, #12]

  /* Disable UART */
  __HAL_UART_DISABLE(huart);
 801334a:	687b      	ldr	r3, [r7, #4]
 801334c:	681b      	ldr	r3, [r3, #0]
 801334e:	681a      	ldr	r2, [r3, #0]
 8013350:	687b      	ldr	r3, [r7, #4]
 8013352:	681b      	ldr	r3, [r3, #0]
 8013354:	f022 0201 	bic.w	r2, r2, #1
 8013358:	601a      	str	r2, [r3, #0]

  /* Enable FIFO mode */
  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
 801335a:	68fb      	ldr	r3, [r7, #12]
 801335c:	f023 5300 	bic.w	r3, r3, #536870912	@ 0x20000000
 8013360:	60fb      	str	r3, [r7, #12]
  huart->FifoMode = UART_FIFOMODE_DISABLE;
 8013362:	687b      	ldr	r3, [r7, #4]
 8013364:	2200      	movs	r2, #0
 8013366:	665a      	str	r2, [r3, #100]	@ 0x64

  /* Restore UART configuration */
  WRITE_REG(huart->Instance->CR1, tmpcr1);
 8013368:	687b      	ldr	r3, [r7, #4]
 801336a:	681b      	ldr	r3, [r3, #0]
 801336c:	68fa      	ldr	r2, [r7, #12]
 801336e:	601a      	str	r2, [r3, #0]

  huart->gState = HAL_UART_STATE_READY;
 8013370:	687b      	ldr	r3, [r7, #4]
 8013372:	2220      	movs	r2, #32
 8013374:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Process Unlocked */
  __HAL_UNLOCK(huart);
 8013378:	687b      	ldr	r3, [r7, #4]
 801337a:	2200      	movs	r2, #0
 801337c:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  return HAL_OK;
 8013380:	2300      	movs	r3, #0
}
 8013382:	4618      	mov	r0, r3
 8013384:	3714      	adds	r7, #20
 8013386:	46bd      	mov	sp, r7
 8013388:	f85d 7b04 	ldr.w	r7, [sp], #4
 801338c:	4770      	bx	lr

0801338e <HAL_UARTEx_SetTxFifoThreshold>:
  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
 801338e:	b580      	push	{r7, lr}
 8013390:	b084      	sub	sp, #16
 8013392:	af00      	add	r7, sp, #0
 8013394:	6078      	str	r0, [r7, #4]
 8013396:	6039      	str	r1, [r7, #0]
  /* Check parameters */
  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));

  /* Process Locked */
  __HAL_LOCK(huart);
 8013398:	687b      	ldr	r3, [r7, #4]
 801339a:	f893 3084 	ldrb.w	r3, [r3, #132]	@ 0x84
 801339e:	2b01      	cmp	r3, #1
 80133a0:	d101      	bne.n	80133a6 <HAL_UARTEx_SetTxFifoThreshold+0x18>
 80133a2:	2302      	movs	r3, #2
 80133a4:	e02d      	b.n	8013402 <HAL_UARTEx_SetTxFifoThreshold+0x74>
 80133a6:	687b      	ldr	r3, [r7, #4]
 80133a8:	2201      	movs	r2, #1
 80133aa:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  huart->gState = HAL_UART_STATE_BUSY;
 80133ae:	687b      	ldr	r3, [r7, #4]
 80133b0:	2224      	movs	r2, #36	@ 0x24
 80133b2:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Save actual UART configuration */
  tmpcr1 = READ_REG(huart->Instance->CR1);
 80133b6:	687b      	ldr	r3, [r7, #4]
 80133b8:	681b      	ldr	r3, [r3, #0]
 80133ba:	681b      	ldr	r3, [r3, #0]
 80133bc:	60fb      	str	r3, [r7, #12]

  /* Disable UART */
  __HAL_UART_DISABLE(huart);
 80133be:	687b      	ldr	r3, [r7, #4]
 80133c0:	681b      	ldr	r3, [r3, #0]
 80133c2:	681a      	ldr	r2, [r3, #0]
 80133c4:	687b      	ldr	r3, [r7, #4]
 80133c6:	681b      	ldr	r3, [r3, #0]
 80133c8:	f022 0201 	bic.w	r2, r2, #1
 80133cc:	601a      	str	r2, [r3, #0]

  /* Update TX threshold configuration */
  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
 80133ce:	687b      	ldr	r3, [r7, #4]
 80133d0:	681b      	ldr	r3, [r3, #0]
 80133d2:	689b      	ldr	r3, [r3, #8]
 80133d4:	f023 4160 	bic.w	r1, r3, #3758096384	@ 0xe0000000
 80133d8:	687b      	ldr	r3, [r7, #4]
 80133da:	681b      	ldr	r3, [r3, #0]
 80133dc:	683a      	ldr	r2, [r7, #0]
 80133de:	430a      	orrs	r2, r1
 80133e0:	609a      	str	r2, [r3, #8]

  /* Determine the number of data to process during RX/TX ISR execution */
  UARTEx_SetNbDataToProcess(huart);
 80133e2:	6878      	ldr	r0, [r7, #4]
 80133e4:	f000 f8a0 	bl	8013528 <UARTEx_SetNbDataToProcess>

  /* Restore UART configuration */
  WRITE_REG(huart->Instance->CR1, tmpcr1);
 80133e8:	687b      	ldr	r3, [r7, #4]
 80133ea:	681b      	ldr	r3, [r3, #0]
 80133ec:	68fa      	ldr	r2, [r7, #12]
 80133ee:	601a      	str	r2, [r3, #0]

  huart->gState = HAL_UART_STATE_READY;
 80133f0:	687b      	ldr	r3, [r7, #4]
 80133f2:	2220      	movs	r2, #32
 80133f4:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Process Unlocked */
  __HAL_UNLOCK(huart);
 80133f8:	687b      	ldr	r3, [r7, #4]
 80133fa:	2200      	movs	r2, #0
 80133fc:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  return HAL_OK;
 8013400:	2300      	movs	r3, #0
}
 8013402:	4618      	mov	r0, r3
 8013404:	3710      	adds	r7, #16
 8013406:	46bd      	mov	sp, r7
 8013408:	bd80      	pop	{r7, pc}

0801340a <HAL_UARTEx_SetRxFifoThreshold>:
  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
 801340a:	b580      	push	{r7, lr}
 801340c:	b084      	sub	sp, #16
 801340e:	af00      	add	r7, sp, #0
 8013410:	6078      	str	r0, [r7, #4]
 8013412:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));

  /* Process Locked */
  __HAL_LOCK(huart);
 8013414:	687b      	ldr	r3, [r7, #4]
 8013416:	f893 3084 	ldrb.w	r3, [r3, #132]	@ 0x84
 801341a:	2b01      	cmp	r3, #1
 801341c:	d101      	bne.n	8013422 <HAL_UARTEx_SetRxFifoThreshold+0x18>
 801341e:	2302      	movs	r3, #2
 8013420:	e02d      	b.n	801347e <HAL_UARTEx_SetRxFifoThreshold+0x74>
 8013422:	687b      	ldr	r3, [r7, #4]
 8013424:	2201      	movs	r2, #1
 8013426:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  huart->gState = HAL_UART_STATE_BUSY;
 801342a:	687b      	ldr	r3, [r7, #4]
 801342c:	2224      	movs	r2, #36	@ 0x24
 801342e:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Save actual UART configuration */
  tmpcr1 = READ_REG(huart->Instance->CR1);
 8013432:	687b      	ldr	r3, [r7, #4]
 8013434:	681b      	ldr	r3, [r3, #0]
 8013436:	681b      	ldr	r3, [r3, #0]
 8013438:	60fb      	str	r3, [r7, #12]

  /* Disable UART */
  __HAL_UART_DISABLE(huart);
 801343a:	687b      	ldr	r3, [r7, #4]
 801343c:	681b      	ldr	r3, [r3, #0]
 801343e:	681a      	ldr	r2, [r3, #0]
 8013440:	687b      	ldr	r3, [r7, #4]
 8013442:	681b      	ldr	r3, [r3, #0]
 8013444:	f022 0201 	bic.w	r2, r2, #1
 8013448:	601a      	str	r2, [r3, #0]

  /* Update RX threshold configuration */
  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
 801344a:	687b      	ldr	r3, [r7, #4]
 801344c:	681b      	ldr	r3, [r3, #0]
 801344e:	689b      	ldr	r3, [r3, #8]
 8013450:	f023 6160 	bic.w	r1, r3, #234881024	@ 0xe000000
 8013454:	687b      	ldr	r3, [r7, #4]
 8013456:	681b      	ldr	r3, [r3, #0]
 8013458:	683a      	ldr	r2, [r7, #0]
 801345a:	430a      	orrs	r2, r1
 801345c:	609a      	str	r2, [r3, #8]

  /* Determine the number of data to process during RX/TX ISR execution */
  UARTEx_SetNbDataToProcess(huart);
 801345e:	6878      	ldr	r0, [r7, #4]
 8013460:	f000 f862 	bl	8013528 <UARTEx_SetNbDataToProcess>

  /* Restore UART configuration */
  WRITE_REG(huart->Instance->CR1, tmpcr1);
 8013464:	687b      	ldr	r3, [r7, #4]
 8013466:	681b      	ldr	r3, [r3, #0]
 8013468:	68fa      	ldr	r2, [r7, #12]
 801346a:	601a      	str	r2, [r3, #0]

  huart->gState = HAL_UART_STATE_READY;
 801346c:	687b      	ldr	r3, [r7, #4]
 801346e:	2220      	movs	r2, #32
 8013470:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88

  /* Process Unlocked */
  __HAL_UNLOCK(huart);
 8013474:	687b      	ldr	r3, [r7, #4]
 8013476:	2200      	movs	r2, #0
 8013478:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84

  return HAL_OK;
 801347c:	2300      	movs	r3, #0
}
 801347e:	4618      	mov	r0, r3
 8013480:	3710      	adds	r7, #16
 8013482:	46bd      	mov	sp, r7
 8013484:	bd80      	pop	{r7, pc}

08013486 <HAL_UARTEx_ReceiveToIdle_IT>:
  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
 8013486:	b580      	push	{r7, lr}
 8013488:	b08c      	sub	sp, #48	@ 0x30
 801348a:	af00      	add	r7, sp, #0
 801348c:	60f8      	str	r0, [r7, #12]
 801348e:	60b9      	str	r1, [r7, #8]
 8013490:	4613      	mov	r3, r2
 8013492:	80fb      	strh	r3, [r7, #6]
  HAL_StatusTypeDef status = HAL_OK;
 8013494:	2300      	movs	r3, #0
 8013496:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f

  /* Check that a Rx process is not already ongoing */
  if (huart->RxState == HAL_UART_STATE_READY)
 801349a:	68fb      	ldr	r3, [r7, #12]
 801349c:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
 80134a0:	2b20      	cmp	r3, #32
 80134a2:	d13b      	bne.n	801351c <HAL_UARTEx_ReceiveToIdle_IT+0x96>
  {
    if ((pData == NULL) || (Size == 0U))
 80134a4:	68bb      	ldr	r3, [r7, #8]
 80134a6:	2b00      	cmp	r3, #0
 80134a8:	d002      	beq.n	80134b0 <HAL_UARTEx_ReceiveToIdle_IT+0x2a>
 80134aa:	88fb      	ldrh	r3, [r7, #6]
 80134ac:	2b00      	cmp	r3, #0
 80134ae:	d101      	bne.n	80134b4 <HAL_UARTEx_ReceiveToIdle_IT+0x2e>
    {
      return HAL_ERROR;
 80134b0:	2301      	movs	r3, #1
 80134b2:	e034      	b.n	801351e <HAL_UARTEx_ReceiveToIdle_IT+0x98>
    }

    /* Set Reception type to reception till IDLE Event*/
    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
 80134b4:	68fb      	ldr	r3, [r7, #12]
 80134b6:	2201      	movs	r2, #1
 80134b8:	66da      	str	r2, [r3, #108]	@ 0x6c
    huart->RxEventType = HAL_UART_RXEVENT_TC;
 80134ba:	68fb      	ldr	r3, [r7, #12]
 80134bc:	2200      	movs	r2, #0
 80134be:	671a      	str	r2, [r3, #112]	@ 0x70

    (void)UART_Start_Receive_IT(huart, pData, Size);
 80134c0:	88fb      	ldrh	r3, [r7, #6]
 80134c2:	461a      	mov	r2, r3
 80134c4:	68b9      	ldr	r1, [r7, #8]
 80134c6:	68f8      	ldr	r0, [r7, #12]
 80134c8:	f7fe fe82 	bl	80121d0 <UART_Start_Receive_IT>

    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 80134cc:	68fb      	ldr	r3, [r7, #12]
 80134ce:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 80134d0:	2b01      	cmp	r3, #1
 80134d2:	d11d      	bne.n	8013510 <HAL_UARTEx_ReceiveToIdle_IT+0x8a>
    {
      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
 80134d4:	68fb      	ldr	r3, [r7, #12]
 80134d6:	681b      	ldr	r3, [r3, #0]
 80134d8:	2210      	movs	r2, #16
 80134da:	621a      	str	r2, [r3, #32]
      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 80134dc:	68fb      	ldr	r3, [r7, #12]
 80134de:	681b      	ldr	r3, [r3, #0]
 80134e0:	61bb      	str	r3, [r7, #24]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80134e2:	69bb      	ldr	r3, [r7, #24]
 80134e4:	e853 3f00 	ldrex	r3, [r3]
 80134e8:	617b      	str	r3, [r7, #20]
   return(result);
 80134ea:	697b      	ldr	r3, [r7, #20]
 80134ec:	f043 0310 	orr.w	r3, r3, #16
 80134f0:	62bb      	str	r3, [r7, #40]	@ 0x28
 80134f2:	68fb      	ldr	r3, [r7, #12]
 80134f4:	681b      	ldr	r3, [r3, #0]
 80134f6:	461a      	mov	r2, r3
 80134f8:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80134fa:	627b      	str	r3, [r7, #36]	@ 0x24
 80134fc:	623a      	str	r2, [r7, #32]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80134fe:	6a39      	ldr	r1, [r7, #32]
 8013500:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8013502:	e841 2300 	strex	r3, r2, [r1]
 8013506:	61fb      	str	r3, [r7, #28]
   return(result);
 8013508:	69fb      	ldr	r3, [r7, #28]
 801350a:	2b00      	cmp	r3, #0
 801350c:	d1e6      	bne.n	80134dc <HAL_UARTEx_ReceiveToIdle_IT+0x56>
 801350e:	e002      	b.n	8013516 <HAL_UARTEx_ReceiveToIdle_IT+0x90>
    {
      /* In case of errors already pending when reception is started,
         Interrupts may have already been raised and lead to reception abortion.
         (Overrun error for instance).
         In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
      status = HAL_ERROR;
 8013510:	2301      	movs	r3, #1
 8013512:	f887 302f 	strb.w	r3, [r7, #47]	@ 0x2f
    }

    return status;
 8013516:	f897 302f 	ldrb.w	r3, [r7, #47]	@ 0x2f
 801351a:	e000      	b.n	801351e <HAL_UARTEx_ReceiveToIdle_IT+0x98>
  }
  else
  {
    return HAL_BUSY;
 801351c:	2302      	movs	r3, #2
  }
}
 801351e:	4618      	mov	r0, r3
 8013520:	3730      	adds	r7, #48	@ 0x30
 8013522:	46bd      	mov	sp, r7
 8013524:	bd80      	pop	{r7, pc}
	...

08013528 <UARTEx_SetNbDataToProcess>:
  *       the UART configuration registers.
  * @param huart UART handle.
  * @retval None
  */
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
{
 8013528:	b480      	push	{r7}
 801352a:	b085      	sub	sp, #20
 801352c:	af00      	add	r7, sp, #0
 801352e:	6078      	str	r0, [r7, #4]
  uint8_t rx_fifo_threshold;
  uint8_t tx_fifo_threshold;
  static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};

  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
 8013530:	687b      	ldr	r3, [r7, #4]
 8013532:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8013534:	2b00      	cmp	r3, #0
 8013536:	d108      	bne.n	801354a <UARTEx_SetNbDataToProcess+0x22>
  {
    huart->NbTxDataToProcess = 1U;
 8013538:	687b      	ldr	r3, [r7, #4]
 801353a:	2201      	movs	r2, #1
 801353c:	f8a3 206a 	strh.w	r2, [r3, #106]	@ 0x6a
    huart->NbRxDataToProcess = 1U;
 8013540:	687b      	ldr	r3, [r7, #4]
 8013542:	2201      	movs	r2, #1
 8013544:	f8a3 2068 	strh.w	r2, [r3, #104]	@ 0x68
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
                               (uint16_t)denominator[tx_fifo_threshold];
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
                               (uint16_t)denominator[rx_fifo_threshold];
  }
}
 8013548:	e031      	b.n	80135ae <UARTEx_SetNbDataToProcess+0x86>
    rx_fifo_depth = RX_FIFO_DEPTH;
 801354a:	2310      	movs	r3, #16
 801354c:	73fb      	strb	r3, [r7, #15]
    tx_fifo_depth = TX_FIFO_DEPTH;
 801354e:	2310      	movs	r3, #16
 8013550:	73bb      	strb	r3, [r7, #14]
    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
 8013552:	687b      	ldr	r3, [r7, #4]
 8013554:	681b      	ldr	r3, [r3, #0]
 8013556:	689b      	ldr	r3, [r3, #8]
 8013558:	0e5b      	lsrs	r3, r3, #25
 801355a:	b2db      	uxtb	r3, r3
 801355c:	f003 0307 	and.w	r3, r3, #7
 8013560:	737b      	strb	r3, [r7, #13]
    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
 8013562:	687b      	ldr	r3, [r7, #4]
 8013564:	681b      	ldr	r3, [r3, #0]
 8013566:	689b      	ldr	r3, [r3, #8]
 8013568:	0f5b      	lsrs	r3, r3, #29
 801356a:	b2db      	uxtb	r3, r3
 801356c:	f003 0307 	and.w	r3, r3, #7
 8013570:	733b      	strb	r3, [r7, #12]
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
 8013572:	7bbb      	ldrb	r3, [r7, #14]
 8013574:	7b3a      	ldrb	r2, [r7, #12]
 8013576:	4911      	ldr	r1, [pc, #68]	@ (80135bc <UARTEx_SetNbDataToProcess+0x94>)
 8013578:	5c8a      	ldrb	r2, [r1, r2]
 801357a:	fb02 f303 	mul.w	r3, r2, r3
                               (uint16_t)denominator[tx_fifo_threshold];
 801357e:	7b3a      	ldrb	r2, [r7, #12]
 8013580:	490f      	ldr	r1, [pc, #60]	@ (80135c0 <UARTEx_SetNbDataToProcess+0x98>)
 8013582:	5c8a      	ldrb	r2, [r1, r2]
    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
 8013584:	fb93 f3f2 	sdiv	r3, r3, r2
 8013588:	b29a      	uxth	r2, r3
 801358a:	687b      	ldr	r3, [r7, #4]
 801358c:	f8a3 206a 	strh.w	r2, [r3, #106]	@ 0x6a
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
 8013590:	7bfb      	ldrb	r3, [r7, #15]
 8013592:	7b7a      	ldrb	r2, [r7, #13]
 8013594:	4909      	ldr	r1, [pc, #36]	@ (80135bc <UARTEx_SetNbDataToProcess+0x94>)
 8013596:	5c8a      	ldrb	r2, [r1, r2]
 8013598:	fb02 f303 	mul.w	r3, r2, r3
                               (uint16_t)denominator[rx_fifo_threshold];
 801359c:	7b7a      	ldrb	r2, [r7, #13]
 801359e:	4908      	ldr	r1, [pc, #32]	@ (80135c0 <UARTEx_SetNbDataToProcess+0x98>)
 80135a0:	5c8a      	ldrb	r2, [r1, r2]
    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
 80135a2:	fb93 f3f2 	sdiv	r3, r3, r2
 80135a6:	b29a      	uxth	r2, r3
 80135a8:	687b      	ldr	r3, [r7, #4]
 80135aa:	f8a3 2068 	strh.w	r2, [r3, #104]	@ 0x68
}
 80135ae:	bf00      	nop
 80135b0:	3714      	adds	r7, #20
 80135b2:	46bd      	mov	sp, r7
 80135b4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80135b8:	4770      	bx	lr
 80135ba:	bf00      	nop
 80135bc:	08018a58 	.word	0x08018a58
 80135c0:	08018a60 	.word	0x08018a60

080135c4 <__NVIC_SetPriority>:
{
 80135c4:	b480      	push	{r7}
 80135c6:	b083      	sub	sp, #12
 80135c8:	af00      	add	r7, sp, #0
 80135ca:	4603      	mov	r3, r0
 80135cc:	6039      	str	r1, [r7, #0]
 80135ce:	80fb      	strh	r3, [r7, #6]
  if ((int32_t)(IRQn) >= 0)
 80135d0:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 80135d4:	2b00      	cmp	r3, #0
 80135d6:	db0a      	blt.n	80135ee <__NVIC_SetPriority+0x2a>
    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80135d8:	683b      	ldr	r3, [r7, #0]
 80135da:	b2da      	uxtb	r2, r3
 80135dc:	490c      	ldr	r1, [pc, #48]	@ (8013610 <__NVIC_SetPriority+0x4c>)
 80135de:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
 80135e2:	0112      	lsls	r2, r2, #4
 80135e4:	b2d2      	uxtb	r2, r2
 80135e6:	440b      	add	r3, r1
 80135e8:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
}
 80135ec:	e00a      	b.n	8013604 <__NVIC_SetPriority+0x40>
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80135ee:	683b      	ldr	r3, [r7, #0]
 80135f0:	b2da      	uxtb	r2, r3
 80135f2:	4908      	ldr	r1, [pc, #32]	@ (8013614 <__NVIC_SetPriority+0x50>)
 80135f4:	88fb      	ldrh	r3, [r7, #6]
 80135f6:	f003 030f 	and.w	r3, r3, #15
 80135fa:	3b04      	subs	r3, #4
 80135fc:	0112      	lsls	r2, r2, #4
 80135fe:	b2d2      	uxtb	r2, r2
 8013600:	440b      	add	r3, r1
 8013602:	761a      	strb	r2, [r3, #24]
}
 8013604:	bf00      	nop
 8013606:	370c      	adds	r7, #12
 8013608:	46bd      	mov	sp, r7
 801360a:	f85d 7b04 	ldr.w	r7, [sp], #4
 801360e:	4770      	bx	lr
 8013610:	e000e100 	.word	0xe000e100
 8013614:	e000ed00 	.word	0xe000ed00

08013618 <SysTick_Handler>:

/*
  SysTick handler implementation that also clears overflow flag.
*/
#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
void SysTick_Handler (void) {
 8013618:	b580      	push	{r7, lr}
 801361a:	af00      	add	r7, sp, #0
  /* Clear overflow flag */
  SysTick->CTRL;
 801361c:	4b05      	ldr	r3, [pc, #20]	@ (8013634 <SysTick_Handler+0x1c>)
 801361e:	681b      	ldr	r3, [r3, #0]

  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
 8013620:	f002 fd1e 	bl	8016060 <xTaskGetSchedulerState>
 8013624:	4603      	mov	r3, r0
 8013626:	2b01      	cmp	r3, #1
 8013628:	d001      	beq.n	801362e <SysTick_Handler+0x16>
    /* Call tick handler */
    xPortSysTickHandler();
 801362a:	f003 ff2d 	bl	8017488 <xPortSysTickHandler>
  }
}
 801362e:	bf00      	nop
 8013630:	bd80      	pop	{r7, pc}
 8013632:	bf00      	nop
 8013634:	e000e010 	.word	0xe000e010

08013638 <SVC_Setup>:
#endif /* SysTick */

/*
  Setup SVC to reset value.
*/
__STATIC_INLINE void SVC_Setup (void) {
 8013638:	b580      	push	{r7, lr}
 801363a:	af00      	add	r7, sp, #0
#if (__ARM_ARCH_7A__ == 0U)
  /* Service Call interrupt might be configured before kernel start     */
  /* and when its priority is lower or equal to BASEPRI, svc intruction */
  /* causes a Hard Fault.                                               */
  NVIC_SetPriority (SVCall_IRQ_NBR, 0U);
 801363c:	2100      	movs	r1, #0
 801363e:	f06f 0004 	mvn.w	r0, #4
 8013642:	f7ff ffbf 	bl	80135c4 <__NVIC_SetPriority>
#endif
}
 8013646:	bf00      	nop
 8013648:	bd80      	pop	{r7, pc}
	...

0801364c <osKernelInitialize>:
static uint32_t OS_Tick_GetOverflow (void);
/* Get OS Tick interval */
static uint32_t OS_Tick_GetInterval (void);
/*---------------------------------------------------------------------------*/

osStatus_t osKernelInitialize (void) {
 801364c:	b480      	push	{r7}
 801364e:	b083      	sub	sp, #12
 8013650:	af00      	add	r7, sp, #0
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 8013652:	f3ef 8305 	mrs	r3, IPSR
 8013656:	603b      	str	r3, [r7, #0]
  return(result);
 8013658:	683b      	ldr	r3, [r7, #0]
  osStatus_t stat;

  if (IS_IRQ()) {
 801365a:	2b00      	cmp	r3, #0
 801365c:	d003      	beq.n	8013666 <osKernelInitialize+0x1a>
    stat = osErrorISR;
 801365e:	f06f 0305 	mvn.w	r3, #5
 8013662:	607b      	str	r3, [r7, #4]
 8013664:	e00c      	b.n	8013680 <osKernelInitialize+0x34>
  }
  else {
    if (KernelState == osKernelInactive) {
 8013666:	4b0a      	ldr	r3, [pc, #40]	@ (8013690 <osKernelInitialize+0x44>)
 8013668:	681b      	ldr	r3, [r3, #0]
 801366a:	2b00      	cmp	r3, #0
 801366c:	d105      	bne.n	801367a <osKernelInitialize+0x2e>
        EvrFreeRTOSSetup(0U);
      #endif
      #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
        vPortDefineHeapRegions (configHEAP_5_REGIONS);
      #endif
      KernelState = osKernelReady;
 801366e:	4b08      	ldr	r3, [pc, #32]	@ (8013690 <osKernelInitialize+0x44>)
 8013670:	2201      	movs	r2, #1
 8013672:	601a      	str	r2, [r3, #0]
      stat = osOK;
 8013674:	2300      	movs	r3, #0
 8013676:	607b      	str	r3, [r7, #4]
 8013678:	e002      	b.n	8013680 <osKernelInitialize+0x34>
    } else {
      stat = osError;
 801367a:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 801367e:	607b      	str	r3, [r7, #4]
    }
  }

  return (stat);
 8013680:	687b      	ldr	r3, [r7, #4]
}
 8013682:	4618      	mov	r0, r3
 8013684:	370c      	adds	r7, #12
 8013686:	46bd      	mov	sp, r7
 8013688:	f85d 7b04 	ldr.w	r7, [sp], #4
 801368c:	4770      	bx	lr
 801368e:	bf00      	nop
 8013690:	24000cac 	.word	0x24000cac

08013694 <osKernelStart>:
  }

  return (state);
}

osStatus_t osKernelStart (void) {
 8013694:	b580      	push	{r7, lr}
 8013696:	b082      	sub	sp, #8
 8013698:	af00      	add	r7, sp, #0
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 801369a:	f3ef 8305 	mrs	r3, IPSR
 801369e:	603b      	str	r3, [r7, #0]
  return(result);
 80136a0:	683b      	ldr	r3, [r7, #0]
  osStatus_t stat;

  if (IS_IRQ()) {
 80136a2:	2b00      	cmp	r3, #0
 80136a4:	d003      	beq.n	80136ae <osKernelStart+0x1a>
    stat = osErrorISR;
 80136a6:	f06f 0305 	mvn.w	r3, #5
 80136aa:	607b      	str	r3, [r7, #4]
 80136ac:	e010      	b.n	80136d0 <osKernelStart+0x3c>
  }
  else {
    if (KernelState == osKernelReady) {
 80136ae:	4b0b      	ldr	r3, [pc, #44]	@ (80136dc <osKernelStart+0x48>)
 80136b0:	681b      	ldr	r3, [r3, #0]
 80136b2:	2b01      	cmp	r3, #1
 80136b4:	d109      	bne.n	80136ca <osKernelStart+0x36>
      /* Ensure SVC priority is at the reset value */
      SVC_Setup();
 80136b6:	f7ff ffbf 	bl	8013638 <SVC_Setup>
      /* Change state to enable IRQ masking check */
      KernelState = osKernelRunning;
 80136ba:	4b08      	ldr	r3, [pc, #32]	@ (80136dc <osKernelStart+0x48>)
 80136bc:	2202      	movs	r2, #2
 80136be:	601a      	str	r2, [r3, #0]
      /* Start the kernel scheduler */
      vTaskStartScheduler();
 80136c0:	f002 f824 	bl	801570c <vTaskStartScheduler>
      stat = osOK;
 80136c4:	2300      	movs	r3, #0
 80136c6:	607b      	str	r3, [r7, #4]
 80136c8:	e002      	b.n	80136d0 <osKernelStart+0x3c>
    } else {
      stat = osError;
 80136ca:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 80136ce:	607b      	str	r3, [r7, #4]
    }
  }

  return (stat);
 80136d0:	687b      	ldr	r3, [r7, #4]
}
 80136d2:	4618      	mov	r0, r3
 80136d4:	3708      	adds	r7, #8
 80136d6:	46bd      	mov	sp, r7
 80136d8:	bd80      	pop	{r7, pc}
 80136da:	bf00      	nop
 80136dc:	24000cac 	.word	0x24000cac

080136e0 <osThreadNew>:
  return (configCPU_CLOCK_HZ);
}

/*---------------------------------------------------------------------------*/

osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
 80136e0:	b580      	push	{r7, lr}
 80136e2:	b08e      	sub	sp, #56	@ 0x38
 80136e4:	af04      	add	r7, sp, #16
 80136e6:	60f8      	str	r0, [r7, #12]
 80136e8:	60b9      	str	r1, [r7, #8]
 80136ea:	607a      	str	r2, [r7, #4]
  uint32_t stack;
  TaskHandle_t hTask;
  UBaseType_t prio;
  int32_t mem;

  hTask = NULL;
 80136ec:	2300      	movs	r3, #0
 80136ee:	613b      	str	r3, [r7, #16]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 80136f0:	f3ef 8305 	mrs	r3, IPSR
 80136f4:	617b      	str	r3, [r7, #20]
  return(result);
 80136f6:	697b      	ldr	r3, [r7, #20]

  if (!IS_IRQ() && (func != NULL)) {
 80136f8:	2b00      	cmp	r3, #0
 80136fa:	d17f      	bne.n	80137fc <osThreadNew+0x11c>
 80136fc:	68fb      	ldr	r3, [r7, #12]
 80136fe:	2b00      	cmp	r3, #0
 8013700:	d07c      	beq.n	80137fc <osThreadNew+0x11c>
    stack = configMINIMAL_STACK_SIZE;
 8013702:	f44f 7300 	mov.w	r3, #512	@ 0x200
 8013706:	623b      	str	r3, [r7, #32]
    prio  = (UBaseType_t)osPriorityNormal;
 8013708:	2318      	movs	r3, #24
 801370a:	61fb      	str	r3, [r7, #28]

    name = NULL;
 801370c:	2300      	movs	r3, #0
 801370e:	627b      	str	r3, [r7, #36]	@ 0x24
    mem  = -1;
 8013710:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8013714:	61bb      	str	r3, [r7, #24]

    if (attr != NULL) {
 8013716:	687b      	ldr	r3, [r7, #4]
 8013718:	2b00      	cmp	r3, #0
 801371a:	d045      	beq.n	80137a8 <osThreadNew+0xc8>
      if (attr->name != NULL) {
 801371c:	687b      	ldr	r3, [r7, #4]
 801371e:	681b      	ldr	r3, [r3, #0]
 8013720:	2b00      	cmp	r3, #0
 8013722:	d002      	beq.n	801372a <osThreadNew+0x4a>
        name = attr->name;
 8013724:	687b      	ldr	r3, [r7, #4]
 8013726:	681b      	ldr	r3, [r3, #0]
 8013728:	627b      	str	r3, [r7, #36]	@ 0x24
      }
      if (attr->priority != osPriorityNone) {
 801372a:	687b      	ldr	r3, [r7, #4]
 801372c:	699b      	ldr	r3, [r3, #24]
 801372e:	2b00      	cmp	r3, #0
 8013730:	d002      	beq.n	8013738 <osThreadNew+0x58>
        prio = (UBaseType_t)attr->priority;
 8013732:	687b      	ldr	r3, [r7, #4]
 8013734:	699b      	ldr	r3, [r3, #24]
 8013736:	61fb      	str	r3, [r7, #28]
      }

      if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
 8013738:	69fb      	ldr	r3, [r7, #28]
 801373a:	2b00      	cmp	r3, #0
 801373c:	d008      	beq.n	8013750 <osThreadNew+0x70>
 801373e:	69fb      	ldr	r3, [r7, #28]
 8013740:	2b38      	cmp	r3, #56	@ 0x38
 8013742:	d805      	bhi.n	8013750 <osThreadNew+0x70>
 8013744:	687b      	ldr	r3, [r7, #4]
 8013746:	685b      	ldr	r3, [r3, #4]
 8013748:	f003 0301 	and.w	r3, r3, #1
 801374c:	2b00      	cmp	r3, #0
 801374e:	d001      	beq.n	8013754 <osThreadNew+0x74>
        return (NULL);
 8013750:	2300      	movs	r3, #0
 8013752:	e054      	b.n	80137fe <osThreadNew+0x11e>
      }

      if (attr->stack_size > 0U) {
 8013754:	687b      	ldr	r3, [r7, #4]
 8013756:	695b      	ldr	r3, [r3, #20]
 8013758:	2b00      	cmp	r3, #0
 801375a:	d003      	beq.n	8013764 <osThreadNew+0x84>
        /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports.       */
        /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
        stack = attr->stack_size / sizeof(StackType_t);
 801375c:	687b      	ldr	r3, [r7, #4]
 801375e:	695b      	ldr	r3, [r3, #20]
 8013760:	089b      	lsrs	r3, r3, #2
 8013762:	623b      	str	r3, [r7, #32]
      }

      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
 8013764:	687b      	ldr	r3, [r7, #4]
 8013766:	689b      	ldr	r3, [r3, #8]
 8013768:	2b00      	cmp	r3, #0
 801376a:	d00e      	beq.n	801378a <osThreadNew+0xaa>
 801376c:	687b      	ldr	r3, [r7, #4]
 801376e:	68db      	ldr	r3, [r3, #12]
 8013770:	2ba7      	cmp	r3, #167	@ 0xa7
 8013772:	d90a      	bls.n	801378a <osThreadNew+0xaa>
          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
 8013774:	687b      	ldr	r3, [r7, #4]
 8013776:	691b      	ldr	r3, [r3, #16]
      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
 8013778:	2b00      	cmp	r3, #0
 801377a:	d006      	beq.n	801378a <osThreadNew+0xaa>
          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
 801377c:	687b      	ldr	r3, [r7, #4]
 801377e:	695b      	ldr	r3, [r3, #20]
 8013780:	2b00      	cmp	r3, #0
 8013782:	d002      	beq.n	801378a <osThreadNew+0xaa>
        mem = 1;
 8013784:	2301      	movs	r3, #1
 8013786:	61bb      	str	r3, [r7, #24]
 8013788:	e010      	b.n	80137ac <osThreadNew+0xcc>
      }
      else {
        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
 801378a:	687b      	ldr	r3, [r7, #4]
 801378c:	689b      	ldr	r3, [r3, #8]
 801378e:	2b00      	cmp	r3, #0
 8013790:	d10c      	bne.n	80137ac <osThreadNew+0xcc>
 8013792:	687b      	ldr	r3, [r7, #4]
 8013794:	68db      	ldr	r3, [r3, #12]
 8013796:	2b00      	cmp	r3, #0
 8013798:	d108      	bne.n	80137ac <osThreadNew+0xcc>
 801379a:	687b      	ldr	r3, [r7, #4]
 801379c:	691b      	ldr	r3, [r3, #16]
 801379e:	2b00      	cmp	r3, #0
 80137a0:	d104      	bne.n	80137ac <osThreadNew+0xcc>
          mem = 0;
 80137a2:	2300      	movs	r3, #0
 80137a4:	61bb      	str	r3, [r7, #24]
 80137a6:	e001      	b.n	80137ac <osThreadNew+0xcc>
        }
      }
    }
    else {
      mem = 0;
 80137a8:	2300      	movs	r3, #0
 80137aa:	61bb      	str	r3, [r7, #24]
    }

    if (mem == 1) {
 80137ac:	69bb      	ldr	r3, [r7, #24]
 80137ae:	2b01      	cmp	r3, #1
 80137b0:	d110      	bne.n	80137d4 <osThreadNew+0xf4>
      #if (configSUPPORT_STATIC_ALLOCATION == 1)
        hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
 80137b2:	687b      	ldr	r3, [r7, #4]
 80137b4:	691b      	ldr	r3, [r3, #16]
                                                                                      (StaticTask_t *)attr->cb_mem);
 80137b6:	687a      	ldr	r2, [r7, #4]
 80137b8:	6892      	ldr	r2, [r2, #8]
        hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
 80137ba:	9202      	str	r2, [sp, #8]
 80137bc:	9301      	str	r3, [sp, #4]
 80137be:	69fb      	ldr	r3, [r7, #28]
 80137c0:	9300      	str	r3, [sp, #0]
 80137c2:	68bb      	ldr	r3, [r7, #8]
 80137c4:	6a3a      	ldr	r2, [r7, #32]
 80137c6:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 80137c8:	68f8      	ldr	r0, [r7, #12]
 80137ca:	f001 fdac 	bl	8015326 <xTaskCreateStatic>
 80137ce:	4603      	mov	r3, r0
 80137d0:	613b      	str	r3, [r7, #16]
 80137d2:	e013      	b.n	80137fc <osThreadNew+0x11c>
      #endif
    }
    else {
      if (mem == 0) {
 80137d4:	69bb      	ldr	r3, [r7, #24]
 80137d6:	2b00      	cmp	r3, #0
 80137d8:	d110      	bne.n	80137fc <osThreadNew+0x11c>
        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
          if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
 80137da:	6a3b      	ldr	r3, [r7, #32]
 80137dc:	b29a      	uxth	r2, r3
 80137de:	f107 0310 	add.w	r3, r7, #16
 80137e2:	9301      	str	r3, [sp, #4]
 80137e4:	69fb      	ldr	r3, [r7, #28]
 80137e6:	9300      	str	r3, [sp, #0]
 80137e8:	68bb      	ldr	r3, [r7, #8]
 80137ea:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 80137ec:	68f8      	ldr	r0, [r7, #12]
 80137ee:	f001 fdfa 	bl	80153e6 <xTaskCreate>
 80137f2:	4603      	mov	r3, r0
 80137f4:	2b01      	cmp	r3, #1
 80137f6:	d001      	beq.n	80137fc <osThreadNew+0x11c>
            hTask = NULL;
 80137f8:	2300      	movs	r3, #0
 80137fa:	613b      	str	r3, [r7, #16]
        #endif
      }
    }
  }

  return ((osThreadId_t)hTask);
 80137fc:	693b      	ldr	r3, [r7, #16]
}
 80137fe:	4618      	mov	r0, r3
 8013800:	3728      	adds	r7, #40	@ 0x28
 8013802:	46bd      	mov	sp, r7
 8013804:	bd80      	pop	{r7, pc}

08013806 <osDelay>:
  /* Return flags before clearing */
  return (rflags);
}
#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */

osStatus_t osDelay (uint32_t ticks) {
 8013806:	b580      	push	{r7, lr}
 8013808:	b084      	sub	sp, #16
 801380a:	af00      	add	r7, sp, #0
 801380c:	6078      	str	r0, [r7, #4]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 801380e:	f3ef 8305 	mrs	r3, IPSR
 8013812:	60bb      	str	r3, [r7, #8]
  return(result);
 8013814:	68bb      	ldr	r3, [r7, #8]
  osStatus_t stat;

  if (IS_IRQ()) {
 8013816:	2b00      	cmp	r3, #0
 8013818:	d003      	beq.n	8013822 <osDelay+0x1c>
    stat = osErrorISR;
 801381a:	f06f 0305 	mvn.w	r3, #5
 801381e:	60fb      	str	r3, [r7, #12]
 8013820:	e007      	b.n	8013832 <osDelay+0x2c>
  }
  else {
    stat = osOK;
 8013822:	2300      	movs	r3, #0
 8013824:	60fb      	str	r3, [r7, #12]

    if (ticks != 0U) {
 8013826:	687b      	ldr	r3, [r7, #4]
 8013828:	2b00      	cmp	r3, #0
 801382a:	d002      	beq.n	8013832 <osDelay+0x2c>
      vTaskDelay(ticks);
 801382c:	6878      	ldr	r0, [r7, #4]
 801382e:	f001 ff37 	bl	80156a0 <vTaskDelay>
    }
  }

  return (stat);
 8013832:	68fb      	ldr	r3, [r7, #12]
}
 8013834:	4618      	mov	r0, r3
 8013836:	3710      	adds	r7, #16
 8013838:	46bd      	mov	sp, r7
 801383a:	bd80      	pop	{r7, pc}

0801383c <TimerCallback>:
}

/*---------------------------------------------------------------------------*/
#if (configUSE_OS2_TIMER == 1)

static void TimerCallback (TimerHandle_t hTimer) {
 801383c:	b580      	push	{r7, lr}
 801383e:	b084      	sub	sp, #16
 8013840:	af00      	add	r7, sp, #0
 8013842:	6078      	str	r0, [r7, #4]
  TimerCallback_t *callb;

  callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer);
 8013844:	6878      	ldr	r0, [r7, #4]
 8013846:	f003 fc3d 	bl	80170c4 <pvTimerGetTimerID>
 801384a:	60f8      	str	r0, [r7, #12]

  if (callb != NULL) {
 801384c:	68fb      	ldr	r3, [r7, #12]
 801384e:	2b00      	cmp	r3, #0
 8013850:	d005      	beq.n	801385e <TimerCallback+0x22>
    callb->func (callb->arg);
 8013852:	68fb      	ldr	r3, [r7, #12]
 8013854:	681b      	ldr	r3, [r3, #0]
 8013856:	68fa      	ldr	r2, [r7, #12]
 8013858:	6852      	ldr	r2, [r2, #4]
 801385a:	4610      	mov	r0, r2
 801385c:	4798      	blx	r3
  }
}
 801385e:	bf00      	nop
 8013860:	3710      	adds	r7, #16
 8013862:	46bd      	mov	sp, r7
 8013864:	bd80      	pop	{r7, pc}
	...

08013868 <osTimerNew>:

osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {
 8013868:	b580      	push	{r7, lr}
 801386a:	b08c      	sub	sp, #48	@ 0x30
 801386c:	af02      	add	r7, sp, #8
 801386e:	60f8      	str	r0, [r7, #12]
 8013870:	607a      	str	r2, [r7, #4]
 8013872:	603b      	str	r3, [r7, #0]
 8013874:	460b      	mov	r3, r1
 8013876:	72fb      	strb	r3, [r7, #11]
  TimerHandle_t hTimer;
  TimerCallback_t *callb;
  UBaseType_t reload;
  int32_t mem;

  hTimer = NULL;
 8013878:	2300      	movs	r3, #0
 801387a:	623b      	str	r3, [r7, #32]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 801387c:	f3ef 8305 	mrs	r3, IPSR
 8013880:	613b      	str	r3, [r7, #16]
  return(result);
 8013882:	693b      	ldr	r3, [r7, #16]

  if (!IS_IRQ() && (func != NULL)) {
 8013884:	2b00      	cmp	r3, #0
 8013886:	d163      	bne.n	8013950 <osTimerNew+0xe8>
 8013888:	68fb      	ldr	r3, [r7, #12]
 801388a:	2b00      	cmp	r3, #0
 801388c:	d060      	beq.n	8013950 <osTimerNew+0xe8>
    /* Allocate memory to store callback function and argument */
    callb = pvPortMalloc (sizeof(TimerCallback_t));
 801388e:	2008      	movs	r0, #8
 8013890:	f003 fe8c 	bl	80175ac <pvPortMalloc>
 8013894:	6178      	str	r0, [r7, #20]

    if (callb != NULL) {
 8013896:	697b      	ldr	r3, [r7, #20]
 8013898:	2b00      	cmp	r3, #0
 801389a:	d059      	beq.n	8013950 <osTimerNew+0xe8>
      callb->func = func;
 801389c:	697b      	ldr	r3, [r7, #20]
 801389e:	68fa      	ldr	r2, [r7, #12]
 80138a0:	601a      	str	r2, [r3, #0]
      callb->arg  = argument;
 80138a2:	697b      	ldr	r3, [r7, #20]
 80138a4:	687a      	ldr	r2, [r7, #4]
 80138a6:	605a      	str	r2, [r3, #4]

      if (type == osTimerOnce) {
 80138a8:	7afb      	ldrb	r3, [r7, #11]
 80138aa:	2b00      	cmp	r3, #0
 80138ac:	d102      	bne.n	80138b4 <osTimerNew+0x4c>
        reload = pdFALSE;
 80138ae:	2300      	movs	r3, #0
 80138b0:	61fb      	str	r3, [r7, #28]
 80138b2:	e001      	b.n	80138b8 <osTimerNew+0x50>
      } else {
        reload = pdTRUE;
 80138b4:	2301      	movs	r3, #1
 80138b6:	61fb      	str	r3, [r7, #28]
      }

      mem  = -1;
 80138b8:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 80138bc:	61bb      	str	r3, [r7, #24]
      name = NULL;
 80138be:	2300      	movs	r3, #0
 80138c0:	627b      	str	r3, [r7, #36]	@ 0x24

      if (attr != NULL) {
 80138c2:	683b      	ldr	r3, [r7, #0]
 80138c4:	2b00      	cmp	r3, #0
 80138c6:	d01c      	beq.n	8013902 <osTimerNew+0x9a>
        if (attr->name != NULL) {
 80138c8:	683b      	ldr	r3, [r7, #0]
 80138ca:	681b      	ldr	r3, [r3, #0]
 80138cc:	2b00      	cmp	r3, #0
 80138ce:	d002      	beq.n	80138d6 <osTimerNew+0x6e>
          name = attr->name;
 80138d0:	683b      	ldr	r3, [r7, #0]
 80138d2:	681b      	ldr	r3, [r3, #0]
 80138d4:	627b      	str	r3, [r7, #36]	@ 0x24
        }

        if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) {
 80138d6:	683b      	ldr	r3, [r7, #0]
 80138d8:	689b      	ldr	r3, [r3, #8]
 80138da:	2b00      	cmp	r3, #0
 80138dc:	d006      	beq.n	80138ec <osTimerNew+0x84>
 80138de:	683b      	ldr	r3, [r7, #0]
 80138e0:	68db      	ldr	r3, [r3, #12]
 80138e2:	2b2b      	cmp	r3, #43	@ 0x2b
 80138e4:	d902      	bls.n	80138ec <osTimerNew+0x84>
          mem = 1;
 80138e6:	2301      	movs	r3, #1
 80138e8:	61bb      	str	r3, [r7, #24]
 80138ea:	e00c      	b.n	8013906 <osTimerNew+0x9e>
        }
        else {
          if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
 80138ec:	683b      	ldr	r3, [r7, #0]
 80138ee:	689b      	ldr	r3, [r3, #8]
 80138f0:	2b00      	cmp	r3, #0
 80138f2:	d108      	bne.n	8013906 <osTimerNew+0x9e>
 80138f4:	683b      	ldr	r3, [r7, #0]
 80138f6:	68db      	ldr	r3, [r3, #12]
 80138f8:	2b00      	cmp	r3, #0
 80138fa:	d104      	bne.n	8013906 <osTimerNew+0x9e>
            mem = 0;
 80138fc:	2300      	movs	r3, #0
 80138fe:	61bb      	str	r3, [r7, #24]
 8013900:	e001      	b.n	8013906 <osTimerNew+0x9e>
          }
        }
      }
      else {
        mem = 0;
 8013902:	2300      	movs	r3, #0
 8013904:	61bb      	str	r3, [r7, #24]
      }

      if (mem == 1) {
 8013906:	69bb      	ldr	r3, [r7, #24]
 8013908:	2b01      	cmp	r3, #1
 801390a:	d10c      	bne.n	8013926 <osTimerNew+0xbe>
        #if (configSUPPORT_STATIC_ALLOCATION == 1)
          hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem);
 801390c:	683b      	ldr	r3, [r7, #0]
 801390e:	689b      	ldr	r3, [r3, #8]
 8013910:	9301      	str	r3, [sp, #4]
 8013912:	4b12      	ldr	r3, [pc, #72]	@ (801395c <osTimerNew+0xf4>)
 8013914:	9300      	str	r3, [sp, #0]
 8013916:	697b      	ldr	r3, [r7, #20]
 8013918:	69fa      	ldr	r2, [r7, #28]
 801391a:	2101      	movs	r1, #1
 801391c:	6a78      	ldr	r0, [r7, #36]	@ 0x24
 801391e:	f003 f81a 	bl	8016956 <xTimerCreateStatic>
 8013922:	6238      	str	r0, [r7, #32]
 8013924:	e00b      	b.n	801393e <osTimerNew+0xd6>
        #endif
      }
      else {
        if (mem == 0) {
 8013926:	69bb      	ldr	r3, [r7, #24]
 8013928:	2b00      	cmp	r3, #0
 801392a:	d108      	bne.n	801393e <osTimerNew+0xd6>
          #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
            hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback);
 801392c:	4b0b      	ldr	r3, [pc, #44]	@ (801395c <osTimerNew+0xf4>)
 801392e:	9300      	str	r3, [sp, #0]
 8013930:	697b      	ldr	r3, [r7, #20]
 8013932:	69fa      	ldr	r2, [r7, #28]
 8013934:	2101      	movs	r1, #1
 8013936:	6a78      	ldr	r0, [r7, #36]	@ 0x24
 8013938:	f002 ffec 	bl	8016914 <xTimerCreate>
 801393c:	6238      	str	r0, [r7, #32]
          #endif
        }
      }

      if ((hTimer == NULL) && (callb != NULL)) {
 801393e:	6a3b      	ldr	r3, [r7, #32]
 8013940:	2b00      	cmp	r3, #0
 8013942:	d105      	bne.n	8013950 <osTimerNew+0xe8>
 8013944:	697b      	ldr	r3, [r7, #20]
 8013946:	2b00      	cmp	r3, #0
 8013948:	d002      	beq.n	8013950 <osTimerNew+0xe8>
        vPortFree (callb);
 801394a:	6978      	ldr	r0, [r7, #20]
 801394c:	f003 fefc 	bl	8017748 <vPortFree>
      }
    }
  }

  return ((osTimerId_t)hTimer);
 8013950:	6a3b      	ldr	r3, [r7, #32]
}
 8013952:	4618      	mov	r0, r3
 8013954:	3728      	adds	r7, #40	@ 0x28
 8013956:	46bd      	mov	sp, r7
 8013958:	bd80      	pop	{r7, pc}
 801395a:	bf00      	nop
 801395c:	0801383d 	.word	0x0801383d

08013960 <osTimerStart>:
  }

  return (p);
}

osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) {
 8013960:	b580      	push	{r7, lr}
 8013962:	b088      	sub	sp, #32
 8013964:	af02      	add	r7, sp, #8
 8013966:	6078      	str	r0, [r7, #4]
 8013968:	6039      	str	r1, [r7, #0]
  TimerHandle_t hTimer = (TimerHandle_t)timer_id;
 801396a:	687b      	ldr	r3, [r7, #4]
 801396c:	613b      	str	r3, [r7, #16]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 801396e:	f3ef 8305 	mrs	r3, IPSR
 8013972:	60fb      	str	r3, [r7, #12]
  return(result);
 8013974:	68fb      	ldr	r3, [r7, #12]
  osStatus_t stat;

  if (IS_IRQ()) {
 8013976:	2b00      	cmp	r3, #0
 8013978:	d003      	beq.n	8013982 <osTimerStart+0x22>
    stat = osErrorISR;
 801397a:	f06f 0305 	mvn.w	r3, #5
 801397e:	617b      	str	r3, [r7, #20]
 8013980:	e017      	b.n	80139b2 <osTimerStart+0x52>
  }
  else if (hTimer == NULL) {
 8013982:	693b      	ldr	r3, [r7, #16]
 8013984:	2b00      	cmp	r3, #0
 8013986:	d103      	bne.n	8013990 <osTimerStart+0x30>
    stat = osErrorParameter;
 8013988:	f06f 0303 	mvn.w	r3, #3
 801398c:	617b      	str	r3, [r7, #20]
 801398e:	e010      	b.n	80139b2 <osTimerStart+0x52>
  }
  else {
    if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) {
 8013990:	2300      	movs	r3, #0
 8013992:	9300      	str	r3, [sp, #0]
 8013994:	2300      	movs	r3, #0
 8013996:	683a      	ldr	r2, [r7, #0]
 8013998:	2104      	movs	r1, #4
 801399a:	6938      	ldr	r0, [r7, #16]
 801399c:	f003 f858 	bl	8016a50 <xTimerGenericCommand>
 80139a0:	4603      	mov	r3, r0
 80139a2:	2b01      	cmp	r3, #1
 80139a4:	d102      	bne.n	80139ac <osTimerStart+0x4c>
      stat = osOK;
 80139a6:	2300      	movs	r3, #0
 80139a8:	617b      	str	r3, [r7, #20]
 80139aa:	e002      	b.n	80139b2 <osTimerStart+0x52>
    } else {
      stat = osErrorResource;
 80139ac:	f06f 0302 	mvn.w	r3, #2
 80139b0:	617b      	str	r3, [r7, #20]
    }
  }

  return (stat);
 80139b2:	697b      	ldr	r3, [r7, #20]
}
 80139b4:	4618      	mov	r0, r3
 80139b6:	3718      	adds	r7, #24
 80139b8:	46bd      	mov	sp, r7
 80139ba:	bd80      	pop	{r7, pc}

080139bc <osTimerStop>:

osStatus_t osTimerStop (osTimerId_t timer_id) {
 80139bc:	b580      	push	{r7, lr}
 80139be:	b088      	sub	sp, #32
 80139c0:	af02      	add	r7, sp, #8
 80139c2:	6078      	str	r0, [r7, #4]
  TimerHandle_t hTimer = (TimerHandle_t)timer_id;
 80139c4:	687b      	ldr	r3, [r7, #4]
 80139c6:	613b      	str	r3, [r7, #16]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 80139c8:	f3ef 8305 	mrs	r3, IPSR
 80139cc:	60fb      	str	r3, [r7, #12]
  return(result);
 80139ce:	68fb      	ldr	r3, [r7, #12]
  osStatus_t stat;

  if (IS_IRQ()) {
 80139d0:	2b00      	cmp	r3, #0
 80139d2:	d003      	beq.n	80139dc <osTimerStop+0x20>
    stat = osErrorISR;
 80139d4:	f06f 0305 	mvn.w	r3, #5
 80139d8:	617b      	str	r3, [r7, #20]
 80139da:	e021      	b.n	8013a20 <osTimerStop+0x64>
  }
  else if (hTimer == NULL) {
 80139dc:	693b      	ldr	r3, [r7, #16]
 80139de:	2b00      	cmp	r3, #0
 80139e0:	d103      	bne.n	80139ea <osTimerStop+0x2e>
    stat = osErrorParameter;
 80139e2:	f06f 0303 	mvn.w	r3, #3
 80139e6:	617b      	str	r3, [r7, #20]
 80139e8:	e01a      	b.n	8013a20 <osTimerStop+0x64>
  }
  else {
    if (xTimerIsTimerActive (hTimer) == pdFALSE) {
 80139ea:	6938      	ldr	r0, [r7, #16]
 80139ec:	f003 fb40 	bl	8017070 <xTimerIsTimerActive>
 80139f0:	4603      	mov	r3, r0
 80139f2:	2b00      	cmp	r3, #0
 80139f4:	d103      	bne.n	80139fe <osTimerStop+0x42>
      stat = osErrorResource;
 80139f6:	f06f 0302 	mvn.w	r3, #2
 80139fa:	617b      	str	r3, [r7, #20]
 80139fc:	e010      	b.n	8013a20 <osTimerStop+0x64>
    }
    else {
      if (xTimerStop (hTimer, 0) == pdPASS) {
 80139fe:	2300      	movs	r3, #0
 8013a00:	9300      	str	r3, [sp, #0]
 8013a02:	2300      	movs	r3, #0
 8013a04:	2200      	movs	r2, #0
 8013a06:	2103      	movs	r1, #3
 8013a08:	6938      	ldr	r0, [r7, #16]
 8013a0a:	f003 f821 	bl	8016a50 <xTimerGenericCommand>
 8013a0e:	4603      	mov	r3, r0
 8013a10:	2b01      	cmp	r3, #1
 8013a12:	d102      	bne.n	8013a1a <osTimerStop+0x5e>
        stat = osOK;
 8013a14:	2300      	movs	r3, #0
 8013a16:	617b      	str	r3, [r7, #20]
 8013a18:	e002      	b.n	8013a20 <osTimerStop+0x64>
      } else {
        stat = osError;
 8013a1a:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8013a1e:	617b      	str	r3, [r7, #20]
      }
    }
  }

  return (stat);
 8013a20:	697b      	ldr	r3, [r7, #20]
}
 8013a22:	4618      	mov	r0, r3
 8013a24:	3718      	adds	r7, #24
 8013a26:	46bd      	mov	sp, r7
 8013a28:	bd80      	pop	{r7, pc}

08013a2a <osMutexNew>:
}

/*---------------------------------------------------------------------------*/
#if (configUSE_OS2_MUTEX == 1)

osMutexId_t osMutexNew (const osMutexAttr_t *attr) {
 8013a2a:	b580      	push	{r7, lr}
 8013a2c:	b088      	sub	sp, #32
 8013a2e:	af00      	add	r7, sp, #0
 8013a30:	6078      	str	r0, [r7, #4]
  int32_t  mem;
  #if (configQUEUE_REGISTRY_SIZE > 0)
  const char *name;
  #endif

  hMutex = NULL;
 8013a32:	2300      	movs	r3, #0
 8013a34:	61fb      	str	r3, [r7, #28]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 8013a36:	f3ef 8305 	mrs	r3, IPSR
 8013a3a:	60bb      	str	r3, [r7, #8]
  return(result);
 8013a3c:	68bb      	ldr	r3, [r7, #8]

  if (!IS_IRQ()) {
 8013a3e:	2b00      	cmp	r3, #0
 8013a40:	d174      	bne.n	8013b2c <osMutexNew+0x102>
    if (attr != NULL) {
 8013a42:	687b      	ldr	r3, [r7, #4]
 8013a44:	2b00      	cmp	r3, #0
 8013a46:	d003      	beq.n	8013a50 <osMutexNew+0x26>
      type = attr->attr_bits;
 8013a48:	687b      	ldr	r3, [r7, #4]
 8013a4a:	685b      	ldr	r3, [r3, #4]
 8013a4c:	61bb      	str	r3, [r7, #24]
 8013a4e:	e001      	b.n	8013a54 <osMutexNew+0x2a>
    } else {
      type = 0U;
 8013a50:	2300      	movs	r3, #0
 8013a52:	61bb      	str	r3, [r7, #24]
    }

    if ((type & osMutexRecursive) == osMutexRecursive) {
 8013a54:	69bb      	ldr	r3, [r7, #24]
 8013a56:	f003 0301 	and.w	r3, r3, #1
 8013a5a:	2b00      	cmp	r3, #0
 8013a5c:	d002      	beq.n	8013a64 <osMutexNew+0x3a>
      rmtx = 1U;
 8013a5e:	2301      	movs	r3, #1
 8013a60:	617b      	str	r3, [r7, #20]
 8013a62:	e001      	b.n	8013a68 <osMutexNew+0x3e>
    } else {
      rmtx = 0U;
 8013a64:	2300      	movs	r3, #0
 8013a66:	617b      	str	r3, [r7, #20]
    }

    if ((type & osMutexRobust) != osMutexRobust) {
 8013a68:	69bb      	ldr	r3, [r7, #24]
 8013a6a:	f003 0308 	and.w	r3, r3, #8
 8013a6e:	2b00      	cmp	r3, #0
 8013a70:	d15c      	bne.n	8013b2c <osMutexNew+0x102>
      mem = -1;
 8013a72:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8013a76:	613b      	str	r3, [r7, #16]

      if (attr != NULL) {
 8013a78:	687b      	ldr	r3, [r7, #4]
 8013a7a:	2b00      	cmp	r3, #0
 8013a7c:	d015      	beq.n	8013aaa <osMutexNew+0x80>
        if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {
 8013a7e:	687b      	ldr	r3, [r7, #4]
 8013a80:	689b      	ldr	r3, [r3, #8]
 8013a82:	2b00      	cmp	r3, #0
 8013a84:	d006      	beq.n	8013a94 <osMutexNew+0x6a>
 8013a86:	687b      	ldr	r3, [r7, #4]
 8013a88:	68db      	ldr	r3, [r3, #12]
 8013a8a:	2b4f      	cmp	r3, #79	@ 0x4f
 8013a8c:	d902      	bls.n	8013a94 <osMutexNew+0x6a>
          mem = 1;
 8013a8e:	2301      	movs	r3, #1
 8013a90:	613b      	str	r3, [r7, #16]
 8013a92:	e00c      	b.n	8013aae <osMutexNew+0x84>
        }
        else {
          if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
 8013a94:	687b      	ldr	r3, [r7, #4]
 8013a96:	689b      	ldr	r3, [r3, #8]
 8013a98:	2b00      	cmp	r3, #0
 8013a9a:	d108      	bne.n	8013aae <osMutexNew+0x84>
 8013a9c:	687b      	ldr	r3, [r7, #4]
 8013a9e:	68db      	ldr	r3, [r3, #12]
 8013aa0:	2b00      	cmp	r3, #0
 8013aa2:	d104      	bne.n	8013aae <osMutexNew+0x84>
            mem = 0;
 8013aa4:	2300      	movs	r3, #0
 8013aa6:	613b      	str	r3, [r7, #16]
 8013aa8:	e001      	b.n	8013aae <osMutexNew+0x84>
          }
        }
      }
      else {
        mem = 0;
 8013aaa:	2300      	movs	r3, #0
 8013aac:	613b      	str	r3, [r7, #16]
      }

      if (mem == 1) {
 8013aae:	693b      	ldr	r3, [r7, #16]
 8013ab0:	2b01      	cmp	r3, #1
 8013ab2:	d112      	bne.n	8013ada <osMutexNew+0xb0>
        #if (configSUPPORT_STATIC_ALLOCATION == 1)
          if (rmtx != 0U) {
 8013ab4:	697b      	ldr	r3, [r7, #20]
 8013ab6:	2b00      	cmp	r3, #0
 8013ab8:	d007      	beq.n	8013aca <osMutexNew+0xa0>
            #if (configUSE_RECURSIVE_MUTEXES == 1)
            hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem);
 8013aba:	687b      	ldr	r3, [r7, #4]
 8013abc:	689b      	ldr	r3, [r3, #8]
 8013abe:	4619      	mov	r1, r3
 8013ac0:	2004      	movs	r0, #4
 8013ac2:	f000 fc50 	bl	8014366 <xQueueCreateMutexStatic>
 8013ac6:	61f8      	str	r0, [r7, #28]
 8013ac8:	e016      	b.n	8013af8 <osMutexNew+0xce>
            #endif
          }
          else {
            hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem);
 8013aca:	687b      	ldr	r3, [r7, #4]
 8013acc:	689b      	ldr	r3, [r3, #8]
 8013ace:	4619      	mov	r1, r3
 8013ad0:	2001      	movs	r0, #1
 8013ad2:	f000 fc48 	bl	8014366 <xQueueCreateMutexStatic>
 8013ad6:	61f8      	str	r0, [r7, #28]
 8013ad8:	e00e      	b.n	8013af8 <osMutexNew+0xce>
          }
        #endif
      }
      else {
        if (mem == 0) {
 8013ada:	693b      	ldr	r3, [r7, #16]
 8013adc:	2b00      	cmp	r3, #0
 8013ade:	d10b      	bne.n	8013af8 <osMutexNew+0xce>
          #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
            if (rmtx != 0U) {
 8013ae0:	697b      	ldr	r3, [r7, #20]
 8013ae2:	2b00      	cmp	r3, #0
 8013ae4:	d004      	beq.n	8013af0 <osMutexNew+0xc6>
              #if (configUSE_RECURSIVE_MUTEXES == 1)
              hMutex = xSemaphoreCreateRecursiveMutex ();
 8013ae6:	2004      	movs	r0, #4
 8013ae8:	f000 fc25 	bl	8014336 <xQueueCreateMutex>
 8013aec:	61f8      	str	r0, [r7, #28]
 8013aee:	e003      	b.n	8013af8 <osMutexNew+0xce>
              #endif
            } else {
              hMutex = xSemaphoreCreateMutex ();
 8013af0:	2001      	movs	r0, #1
 8013af2:	f000 fc20 	bl	8014336 <xQueueCreateMutex>
 8013af6:	61f8      	str	r0, [r7, #28]
          #endif
        }
      }

      #if (configQUEUE_REGISTRY_SIZE > 0)
      if (hMutex != NULL) {
 8013af8:	69fb      	ldr	r3, [r7, #28]
 8013afa:	2b00      	cmp	r3, #0
 8013afc:	d00c      	beq.n	8013b18 <osMutexNew+0xee>
        if (attr != NULL) {
 8013afe:	687b      	ldr	r3, [r7, #4]
 8013b00:	2b00      	cmp	r3, #0
 8013b02:	d003      	beq.n	8013b0c <osMutexNew+0xe2>
          name = attr->name;
 8013b04:	687b      	ldr	r3, [r7, #4]
 8013b06:	681b      	ldr	r3, [r3, #0]
 8013b08:	60fb      	str	r3, [r7, #12]
 8013b0a:	e001      	b.n	8013b10 <osMutexNew+0xe6>
        } else {
          name = NULL;
 8013b0c:	2300      	movs	r3, #0
 8013b0e:	60fb      	str	r3, [r7, #12]
        }
        vQueueAddToRegistry (hMutex, name);
 8013b10:	68f9      	ldr	r1, [r7, #12]
 8013b12:	69f8      	ldr	r0, [r7, #28]
 8013b14:	f001 f9ea 	bl	8014eec <vQueueAddToRegistry>
      }
      #endif

      if ((hMutex != NULL) && (rmtx != 0U)) {
 8013b18:	69fb      	ldr	r3, [r7, #28]
 8013b1a:	2b00      	cmp	r3, #0
 8013b1c:	d006      	beq.n	8013b2c <osMutexNew+0x102>
 8013b1e:	697b      	ldr	r3, [r7, #20]
 8013b20:	2b00      	cmp	r3, #0
 8013b22:	d003      	beq.n	8013b2c <osMutexNew+0x102>
        hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U);
 8013b24:	69fb      	ldr	r3, [r7, #28]
 8013b26:	f043 0301 	orr.w	r3, r3, #1
 8013b2a:	61fb      	str	r3, [r7, #28]
      }
    }
  }

  return ((osMutexId_t)hMutex);
 8013b2c:	69fb      	ldr	r3, [r7, #28]
}
 8013b2e:	4618      	mov	r0, r3
 8013b30:	3720      	adds	r7, #32
 8013b32:	46bd      	mov	sp, r7
 8013b34:	bd80      	pop	{r7, pc}

08013b36 <osMutexAcquire>:

osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
 8013b36:	b580      	push	{r7, lr}
 8013b38:	b086      	sub	sp, #24
 8013b3a:	af00      	add	r7, sp, #0
 8013b3c:	6078      	str	r0, [r7, #4]
 8013b3e:	6039      	str	r1, [r7, #0]
  SemaphoreHandle_t hMutex;
  osStatus_t stat;
  uint32_t rmtx;

  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
 8013b40:	687b      	ldr	r3, [r7, #4]
 8013b42:	f023 0301 	bic.w	r3, r3, #1
 8013b46:	613b      	str	r3, [r7, #16]

  rmtx = (uint32_t)mutex_id & 1U;
 8013b48:	687b      	ldr	r3, [r7, #4]
 8013b4a:	f003 0301 	and.w	r3, r3, #1
 8013b4e:	60fb      	str	r3, [r7, #12]

  stat = osOK;
 8013b50:	2300      	movs	r3, #0
 8013b52:	617b      	str	r3, [r7, #20]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 8013b54:	f3ef 8305 	mrs	r3, IPSR
 8013b58:	60bb      	str	r3, [r7, #8]
  return(result);
 8013b5a:	68bb      	ldr	r3, [r7, #8]

  if (IS_IRQ()) {
 8013b5c:	2b00      	cmp	r3, #0
 8013b5e:	d003      	beq.n	8013b68 <osMutexAcquire+0x32>
    stat = osErrorISR;
 8013b60:	f06f 0305 	mvn.w	r3, #5
 8013b64:	617b      	str	r3, [r7, #20]
 8013b66:	e02c      	b.n	8013bc2 <osMutexAcquire+0x8c>
  }
  else if (hMutex == NULL) {
 8013b68:	693b      	ldr	r3, [r7, #16]
 8013b6a:	2b00      	cmp	r3, #0
 8013b6c:	d103      	bne.n	8013b76 <osMutexAcquire+0x40>
    stat = osErrorParameter;
 8013b6e:	f06f 0303 	mvn.w	r3, #3
 8013b72:	617b      	str	r3, [r7, #20]
 8013b74:	e025      	b.n	8013bc2 <osMutexAcquire+0x8c>
  }
  else {
    if (rmtx != 0U) {
 8013b76:	68fb      	ldr	r3, [r7, #12]
 8013b78:	2b00      	cmp	r3, #0
 8013b7a:	d011      	beq.n	8013ba0 <osMutexAcquire+0x6a>
      #if (configUSE_RECURSIVE_MUTEXES == 1)
      if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) {
 8013b7c:	6839      	ldr	r1, [r7, #0]
 8013b7e:	6938      	ldr	r0, [r7, #16]
 8013b80:	f000 fc41 	bl	8014406 <xQueueTakeMutexRecursive>
 8013b84:	4603      	mov	r3, r0
 8013b86:	2b01      	cmp	r3, #1
 8013b88:	d01b      	beq.n	8013bc2 <osMutexAcquire+0x8c>
        if (timeout != 0U) {
 8013b8a:	683b      	ldr	r3, [r7, #0]
 8013b8c:	2b00      	cmp	r3, #0
 8013b8e:	d003      	beq.n	8013b98 <osMutexAcquire+0x62>
          stat = osErrorTimeout;
 8013b90:	f06f 0301 	mvn.w	r3, #1
 8013b94:	617b      	str	r3, [r7, #20]
 8013b96:	e014      	b.n	8013bc2 <osMutexAcquire+0x8c>
        } else {
          stat = osErrorResource;
 8013b98:	f06f 0302 	mvn.w	r3, #2
 8013b9c:	617b      	str	r3, [r7, #20]
 8013b9e:	e010      	b.n	8013bc2 <osMutexAcquire+0x8c>
        }
      }
      #endif
    }
    else {
      if (xSemaphoreTake (hMutex, timeout) != pdPASS) {
 8013ba0:	6839      	ldr	r1, [r7, #0]
 8013ba2:	6938      	ldr	r0, [r7, #16]
 8013ba4:	f000 fee8 	bl	8014978 <xQueueSemaphoreTake>
 8013ba8:	4603      	mov	r3, r0
 8013baa:	2b01      	cmp	r3, #1
 8013bac:	d009      	beq.n	8013bc2 <osMutexAcquire+0x8c>
        if (timeout != 0U) {
 8013bae:	683b      	ldr	r3, [r7, #0]
 8013bb0:	2b00      	cmp	r3, #0
 8013bb2:	d003      	beq.n	8013bbc <osMutexAcquire+0x86>
          stat = osErrorTimeout;
 8013bb4:	f06f 0301 	mvn.w	r3, #1
 8013bb8:	617b      	str	r3, [r7, #20]
 8013bba:	e002      	b.n	8013bc2 <osMutexAcquire+0x8c>
        } else {
          stat = osErrorResource;
 8013bbc:	f06f 0302 	mvn.w	r3, #2
 8013bc0:	617b      	str	r3, [r7, #20]
        }
      }
    }
  }

  return (stat);
 8013bc2:	697b      	ldr	r3, [r7, #20]
}
 8013bc4:	4618      	mov	r0, r3
 8013bc6:	3718      	adds	r7, #24
 8013bc8:	46bd      	mov	sp, r7
 8013bca:	bd80      	pop	{r7, pc}

08013bcc <osMutexRelease>:

osStatus_t osMutexRelease (osMutexId_t mutex_id) {
 8013bcc:	b580      	push	{r7, lr}
 8013bce:	b086      	sub	sp, #24
 8013bd0:	af00      	add	r7, sp, #0
 8013bd2:	6078      	str	r0, [r7, #4]
  SemaphoreHandle_t hMutex;
  osStatus_t stat;
  uint32_t rmtx;

  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
 8013bd4:	687b      	ldr	r3, [r7, #4]
 8013bd6:	f023 0301 	bic.w	r3, r3, #1
 8013bda:	613b      	str	r3, [r7, #16]

  rmtx = (uint32_t)mutex_id & 1U;
 8013bdc:	687b      	ldr	r3, [r7, #4]
 8013bde:	f003 0301 	and.w	r3, r3, #1
 8013be2:	60fb      	str	r3, [r7, #12]

  stat = osOK;
 8013be4:	2300      	movs	r3, #0
 8013be6:	617b      	str	r3, [r7, #20]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 8013be8:	f3ef 8305 	mrs	r3, IPSR
 8013bec:	60bb      	str	r3, [r7, #8]
  return(result);
 8013bee:	68bb      	ldr	r3, [r7, #8]

  if (IS_IRQ()) {
 8013bf0:	2b00      	cmp	r3, #0
 8013bf2:	d003      	beq.n	8013bfc <osMutexRelease+0x30>
    stat = osErrorISR;
 8013bf4:	f06f 0305 	mvn.w	r3, #5
 8013bf8:	617b      	str	r3, [r7, #20]
 8013bfa:	e01f      	b.n	8013c3c <osMutexRelease+0x70>
  }
  else if (hMutex == NULL) {
 8013bfc:	693b      	ldr	r3, [r7, #16]
 8013bfe:	2b00      	cmp	r3, #0
 8013c00:	d103      	bne.n	8013c0a <osMutexRelease+0x3e>
    stat = osErrorParameter;
 8013c02:	f06f 0303 	mvn.w	r3, #3
 8013c06:	617b      	str	r3, [r7, #20]
 8013c08:	e018      	b.n	8013c3c <osMutexRelease+0x70>
  }
  else {
    if (rmtx != 0U) {
 8013c0a:	68fb      	ldr	r3, [r7, #12]
 8013c0c:	2b00      	cmp	r3, #0
 8013c0e:	d009      	beq.n	8013c24 <osMutexRelease+0x58>
      #if (configUSE_RECURSIVE_MUTEXES == 1)
      if (xSemaphoreGiveRecursive (hMutex) != pdPASS) {
 8013c10:	6938      	ldr	r0, [r7, #16]
 8013c12:	f000 fbc3 	bl	801439c <xQueueGiveMutexRecursive>
 8013c16:	4603      	mov	r3, r0
 8013c18:	2b01      	cmp	r3, #1
 8013c1a:	d00f      	beq.n	8013c3c <osMutexRelease+0x70>
        stat = osErrorResource;
 8013c1c:	f06f 0302 	mvn.w	r3, #2
 8013c20:	617b      	str	r3, [r7, #20]
 8013c22:	e00b      	b.n	8013c3c <osMutexRelease+0x70>
      }
      #endif
    }
    else {
      if (xSemaphoreGive (hMutex) != pdPASS) {
 8013c24:	2300      	movs	r3, #0
 8013c26:	2200      	movs	r2, #0
 8013c28:	2100      	movs	r1, #0
 8013c2a:	6938      	ldr	r0, [r7, #16]
 8013c2c:	f000 fc22 	bl	8014474 <xQueueGenericSend>
 8013c30:	4603      	mov	r3, r0
 8013c32:	2b01      	cmp	r3, #1
 8013c34:	d002      	beq.n	8013c3c <osMutexRelease+0x70>
        stat = osErrorResource;
 8013c36:	f06f 0302 	mvn.w	r3, #2
 8013c3a:	617b      	str	r3, [r7, #20]
      }
    }
  }

  return (stat);
 8013c3c:	697b      	ldr	r3, [r7, #20]
}
 8013c3e:	4618      	mov	r0, r3
 8013c40:	3718      	adds	r7, #24
 8013c42:	46bd      	mov	sp, r7
 8013c44:	bd80      	pop	{r7, pc}

08013c46 <osMessageQueueNew>:
  return (stat);
}

/*---------------------------------------------------------------------------*/

osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
 8013c46:	b580      	push	{r7, lr}
 8013c48:	b08a      	sub	sp, #40	@ 0x28
 8013c4a:	af02      	add	r7, sp, #8
 8013c4c:	60f8      	str	r0, [r7, #12]
 8013c4e:	60b9      	str	r1, [r7, #8]
 8013c50:	607a      	str	r2, [r7, #4]
  int32_t mem;
  #if (configQUEUE_REGISTRY_SIZE > 0)
  const char *name;
  #endif

  hQueue = NULL;
 8013c52:	2300      	movs	r3, #0
 8013c54:	61fb      	str	r3, [r7, #28]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 8013c56:	f3ef 8305 	mrs	r3, IPSR
 8013c5a:	613b      	str	r3, [r7, #16]
  return(result);
 8013c5c:	693b      	ldr	r3, [r7, #16]

  if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) {
 8013c5e:	2b00      	cmp	r3, #0
 8013c60:	d15f      	bne.n	8013d22 <osMessageQueueNew+0xdc>
 8013c62:	68fb      	ldr	r3, [r7, #12]
 8013c64:	2b00      	cmp	r3, #0
 8013c66:	d05c      	beq.n	8013d22 <osMessageQueueNew+0xdc>
 8013c68:	68bb      	ldr	r3, [r7, #8]
 8013c6a:	2b00      	cmp	r3, #0
 8013c6c:	d059      	beq.n	8013d22 <osMessageQueueNew+0xdc>
    mem = -1;
 8013c6e:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8013c72:	61bb      	str	r3, [r7, #24]

    if (attr != NULL) {
 8013c74:	687b      	ldr	r3, [r7, #4]
 8013c76:	2b00      	cmp	r3, #0
 8013c78:	d029      	beq.n	8013cce <osMessageQueueNew+0x88>
      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&
 8013c7a:	687b      	ldr	r3, [r7, #4]
 8013c7c:	689b      	ldr	r3, [r3, #8]
 8013c7e:	2b00      	cmp	r3, #0
 8013c80:	d012      	beq.n	8013ca8 <osMessageQueueNew+0x62>
 8013c82:	687b      	ldr	r3, [r7, #4]
 8013c84:	68db      	ldr	r3, [r3, #12]
 8013c86:	2b4f      	cmp	r3, #79	@ 0x4f
 8013c88:	d90e      	bls.n	8013ca8 <osMessageQueueNew+0x62>
          (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {
 8013c8a:	687b      	ldr	r3, [r7, #4]
 8013c8c:	691b      	ldr	r3, [r3, #16]
      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&
 8013c8e:	2b00      	cmp	r3, #0
 8013c90:	d00a      	beq.n	8013ca8 <osMessageQueueNew+0x62>
          (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {
 8013c92:	687b      	ldr	r3, [r7, #4]
 8013c94:	695a      	ldr	r2, [r3, #20]
 8013c96:	68fb      	ldr	r3, [r7, #12]
 8013c98:	68b9      	ldr	r1, [r7, #8]
 8013c9a:	fb01 f303 	mul.w	r3, r1, r3
 8013c9e:	429a      	cmp	r2, r3
 8013ca0:	d302      	bcc.n	8013ca8 <osMessageQueueNew+0x62>
        mem = 1;
 8013ca2:	2301      	movs	r3, #1
 8013ca4:	61bb      	str	r3, [r7, #24]
 8013ca6:	e014      	b.n	8013cd2 <osMessageQueueNew+0x8c>
      }
      else {
        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&
 8013ca8:	687b      	ldr	r3, [r7, #4]
 8013caa:	689b      	ldr	r3, [r3, #8]
 8013cac:	2b00      	cmp	r3, #0
 8013cae:	d110      	bne.n	8013cd2 <osMessageQueueNew+0x8c>
 8013cb0:	687b      	ldr	r3, [r7, #4]
 8013cb2:	68db      	ldr	r3, [r3, #12]
 8013cb4:	2b00      	cmp	r3, #0
 8013cb6:	d10c      	bne.n	8013cd2 <osMessageQueueNew+0x8c>
            (attr->mq_mem == NULL) && (attr->mq_size == 0U)) {
 8013cb8:	687b      	ldr	r3, [r7, #4]
 8013cba:	691b      	ldr	r3, [r3, #16]
        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&
 8013cbc:	2b00      	cmp	r3, #0
 8013cbe:	d108      	bne.n	8013cd2 <osMessageQueueNew+0x8c>
            (attr->mq_mem == NULL) && (attr->mq_size == 0U)) {
 8013cc0:	687b      	ldr	r3, [r7, #4]
 8013cc2:	695b      	ldr	r3, [r3, #20]
 8013cc4:	2b00      	cmp	r3, #0
 8013cc6:	d104      	bne.n	8013cd2 <osMessageQueueNew+0x8c>
          mem = 0;
 8013cc8:	2300      	movs	r3, #0
 8013cca:	61bb      	str	r3, [r7, #24]
 8013ccc:	e001      	b.n	8013cd2 <osMessageQueueNew+0x8c>
        }
      }
    }
    else {
      mem = 0;
 8013cce:	2300      	movs	r3, #0
 8013cd0:	61bb      	str	r3, [r7, #24]
    }

    if (mem == 1) {
 8013cd2:	69bb      	ldr	r3, [r7, #24]
 8013cd4:	2b01      	cmp	r3, #1
 8013cd6:	d10b      	bne.n	8013cf0 <osMessageQueueNew+0xaa>
      #if (configSUPPORT_STATIC_ALLOCATION == 1)
        hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem);
 8013cd8:	687b      	ldr	r3, [r7, #4]
 8013cda:	691a      	ldr	r2, [r3, #16]
 8013cdc:	687b      	ldr	r3, [r7, #4]
 8013cde:	689b      	ldr	r3, [r3, #8]
 8013ce0:	2100      	movs	r1, #0
 8013ce2:	9100      	str	r1, [sp, #0]
 8013ce4:	68b9      	ldr	r1, [r7, #8]
 8013ce6:	68f8      	ldr	r0, [r7, #12]
 8013ce8:	f000 fa30 	bl	801414c <xQueueGenericCreateStatic>
 8013cec:	61f8      	str	r0, [r7, #28]
 8013cee:	e008      	b.n	8013d02 <osMessageQueueNew+0xbc>
      #endif
    }
    else {
      if (mem == 0) {
 8013cf0:	69bb      	ldr	r3, [r7, #24]
 8013cf2:	2b00      	cmp	r3, #0
 8013cf4:	d105      	bne.n	8013d02 <osMessageQueueNew+0xbc>
        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
          hQueue = xQueueCreate (msg_count, msg_size);
 8013cf6:	2200      	movs	r2, #0
 8013cf8:	68b9      	ldr	r1, [r7, #8]
 8013cfa:	68f8      	ldr	r0, [r7, #12]
 8013cfc:	f000 faa3 	bl	8014246 <xQueueGenericCreate>
 8013d00:	61f8      	str	r0, [r7, #28]
        #endif
      }
    }

    #if (configQUEUE_REGISTRY_SIZE > 0)
    if (hQueue != NULL) {
 8013d02:	69fb      	ldr	r3, [r7, #28]
 8013d04:	2b00      	cmp	r3, #0
 8013d06:	d00c      	beq.n	8013d22 <osMessageQueueNew+0xdc>
      if (attr != NULL) {
 8013d08:	687b      	ldr	r3, [r7, #4]
 8013d0a:	2b00      	cmp	r3, #0
 8013d0c:	d003      	beq.n	8013d16 <osMessageQueueNew+0xd0>
        name = attr->name;
 8013d0e:	687b      	ldr	r3, [r7, #4]
 8013d10:	681b      	ldr	r3, [r3, #0]
 8013d12:	617b      	str	r3, [r7, #20]
 8013d14:	e001      	b.n	8013d1a <osMessageQueueNew+0xd4>
      } else {
        name = NULL;
 8013d16:	2300      	movs	r3, #0
 8013d18:	617b      	str	r3, [r7, #20]
      }
      vQueueAddToRegistry (hQueue, name);
 8013d1a:	6979      	ldr	r1, [r7, #20]
 8013d1c:	69f8      	ldr	r0, [r7, #28]
 8013d1e:	f001 f8e5 	bl	8014eec <vQueueAddToRegistry>
    }
    #endif

  }

  return ((osMessageQueueId_t)hQueue);
 8013d22:	69fb      	ldr	r3, [r7, #28]
}
 8013d24:	4618      	mov	r0, r3
 8013d26:	3720      	adds	r7, #32
 8013d28:	46bd      	mov	sp, r7
 8013d2a:	bd80      	pop	{r7, pc}

08013d2c <osMessageQueuePut>:

osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
 8013d2c:	b580      	push	{r7, lr}
 8013d2e:	b088      	sub	sp, #32
 8013d30:	af00      	add	r7, sp, #0
 8013d32:	60f8      	str	r0, [r7, #12]
 8013d34:	60b9      	str	r1, [r7, #8]
 8013d36:	603b      	str	r3, [r7, #0]
 8013d38:	4613      	mov	r3, r2
 8013d3a:	71fb      	strb	r3, [r7, #7]
  QueueHandle_t hQueue = (QueueHandle_t)mq_id;
 8013d3c:	68fb      	ldr	r3, [r7, #12]
 8013d3e:	61bb      	str	r3, [r7, #24]
  osStatus_t stat;
  BaseType_t yield;

  (void)msg_prio; /* Message priority is ignored */

  stat = osOK;
 8013d40:	2300      	movs	r3, #0
 8013d42:	61fb      	str	r3, [r7, #28]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 8013d44:	f3ef 8305 	mrs	r3, IPSR
 8013d48:	617b      	str	r3, [r7, #20]
  return(result);
 8013d4a:	697b      	ldr	r3, [r7, #20]

  if (IS_IRQ()) {
 8013d4c:	2b00      	cmp	r3, #0
 8013d4e:	d028      	beq.n	8013da2 <osMessageQueuePut+0x76>
    if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
 8013d50:	69bb      	ldr	r3, [r7, #24]
 8013d52:	2b00      	cmp	r3, #0
 8013d54:	d005      	beq.n	8013d62 <osMessageQueuePut+0x36>
 8013d56:	68bb      	ldr	r3, [r7, #8]
 8013d58:	2b00      	cmp	r3, #0
 8013d5a:	d002      	beq.n	8013d62 <osMessageQueuePut+0x36>
 8013d5c:	683b      	ldr	r3, [r7, #0]
 8013d5e:	2b00      	cmp	r3, #0
 8013d60:	d003      	beq.n	8013d6a <osMessageQueuePut+0x3e>
      stat = osErrorParameter;
 8013d62:	f06f 0303 	mvn.w	r3, #3
 8013d66:	61fb      	str	r3, [r7, #28]
 8013d68:	e038      	b.n	8013ddc <osMessageQueuePut+0xb0>
    }
    else {
      yield = pdFALSE;
 8013d6a:	2300      	movs	r3, #0
 8013d6c:	613b      	str	r3, [r7, #16]

      if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) {
 8013d6e:	f107 0210 	add.w	r2, r7, #16
 8013d72:	2300      	movs	r3, #0
 8013d74:	68b9      	ldr	r1, [r7, #8]
 8013d76:	69b8      	ldr	r0, [r7, #24]
 8013d78:	f000 fc7e 	bl	8014678 <xQueueGenericSendFromISR>
 8013d7c:	4603      	mov	r3, r0
 8013d7e:	2b01      	cmp	r3, #1
 8013d80:	d003      	beq.n	8013d8a <osMessageQueuePut+0x5e>
        stat = osErrorResource;
 8013d82:	f06f 0302 	mvn.w	r3, #2
 8013d86:	61fb      	str	r3, [r7, #28]
 8013d88:	e028      	b.n	8013ddc <osMessageQueuePut+0xb0>
      } else {
        portYIELD_FROM_ISR (yield);
 8013d8a:	693b      	ldr	r3, [r7, #16]
 8013d8c:	2b00      	cmp	r3, #0
 8013d8e:	d025      	beq.n	8013ddc <osMessageQueuePut+0xb0>
 8013d90:	4b15      	ldr	r3, [pc, #84]	@ (8013de8 <osMessageQueuePut+0xbc>)
 8013d92:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8013d96:	601a      	str	r2, [r3, #0]
 8013d98:	f3bf 8f4f 	dsb	sy
 8013d9c:	f3bf 8f6f 	isb	sy
 8013da0:	e01c      	b.n	8013ddc <osMessageQueuePut+0xb0>
      }
    }
  }
  else {
    if ((hQueue == NULL) || (msg_ptr == NULL)) {
 8013da2:	69bb      	ldr	r3, [r7, #24]
 8013da4:	2b00      	cmp	r3, #0
 8013da6:	d002      	beq.n	8013dae <osMessageQueuePut+0x82>
 8013da8:	68bb      	ldr	r3, [r7, #8]
 8013daa:	2b00      	cmp	r3, #0
 8013dac:	d103      	bne.n	8013db6 <osMessageQueuePut+0x8a>
      stat = osErrorParameter;
 8013dae:	f06f 0303 	mvn.w	r3, #3
 8013db2:	61fb      	str	r3, [r7, #28]
 8013db4:	e012      	b.n	8013ddc <osMessageQueuePut+0xb0>
    }
    else {
      if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
 8013db6:	2300      	movs	r3, #0
 8013db8:	683a      	ldr	r2, [r7, #0]
 8013dba:	68b9      	ldr	r1, [r7, #8]
 8013dbc:	69b8      	ldr	r0, [r7, #24]
 8013dbe:	f000 fb59 	bl	8014474 <xQueueGenericSend>
 8013dc2:	4603      	mov	r3, r0
 8013dc4:	2b01      	cmp	r3, #1
 8013dc6:	d009      	beq.n	8013ddc <osMessageQueuePut+0xb0>
        if (timeout != 0U) {
 8013dc8:	683b      	ldr	r3, [r7, #0]
 8013dca:	2b00      	cmp	r3, #0
 8013dcc:	d003      	beq.n	8013dd6 <osMessageQueuePut+0xaa>
          stat = osErrorTimeout;
 8013dce:	f06f 0301 	mvn.w	r3, #1
 8013dd2:	61fb      	str	r3, [r7, #28]
 8013dd4:	e002      	b.n	8013ddc <osMessageQueuePut+0xb0>
        } else {
          stat = osErrorResource;
 8013dd6:	f06f 0302 	mvn.w	r3, #2
 8013dda:	61fb      	str	r3, [r7, #28]
        }
      }
    }
  }

  return (stat);
 8013ddc:	69fb      	ldr	r3, [r7, #28]
}
 8013dde:	4618      	mov	r0, r3
 8013de0:	3720      	adds	r7, #32
 8013de2:	46bd      	mov	sp, r7
 8013de4:	bd80      	pop	{r7, pc}
 8013de6:	bf00      	nop
 8013de8:	e000ed04 	.word	0xe000ed04

08013dec <osMessageQueueGet>:

osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
 8013dec:	b580      	push	{r7, lr}
 8013dee:	b088      	sub	sp, #32
 8013df0:	af00      	add	r7, sp, #0
 8013df2:	60f8      	str	r0, [r7, #12]
 8013df4:	60b9      	str	r1, [r7, #8]
 8013df6:	607a      	str	r2, [r7, #4]
 8013df8:	603b      	str	r3, [r7, #0]
  QueueHandle_t hQueue = (QueueHandle_t)mq_id;
 8013dfa:	68fb      	ldr	r3, [r7, #12]
 8013dfc:	61bb      	str	r3, [r7, #24]
  osStatus_t stat;
  BaseType_t yield;

  (void)msg_prio; /* Message priority is ignored */

  stat = osOK;
 8013dfe:	2300      	movs	r3, #0
 8013e00:	61fb      	str	r3, [r7, #28]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 8013e02:	f3ef 8305 	mrs	r3, IPSR
 8013e06:	617b      	str	r3, [r7, #20]
  return(result);
 8013e08:	697b      	ldr	r3, [r7, #20]

  if (IS_IRQ()) {
 8013e0a:	2b00      	cmp	r3, #0
 8013e0c:	d028      	beq.n	8013e60 <osMessageQueueGet+0x74>
    if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
 8013e0e:	69bb      	ldr	r3, [r7, #24]
 8013e10:	2b00      	cmp	r3, #0
 8013e12:	d005      	beq.n	8013e20 <osMessageQueueGet+0x34>
 8013e14:	68bb      	ldr	r3, [r7, #8]
 8013e16:	2b00      	cmp	r3, #0
 8013e18:	d002      	beq.n	8013e20 <osMessageQueueGet+0x34>
 8013e1a:	683b      	ldr	r3, [r7, #0]
 8013e1c:	2b00      	cmp	r3, #0
 8013e1e:	d003      	beq.n	8013e28 <osMessageQueueGet+0x3c>
      stat = osErrorParameter;
 8013e20:	f06f 0303 	mvn.w	r3, #3
 8013e24:	61fb      	str	r3, [r7, #28]
 8013e26:	e037      	b.n	8013e98 <osMessageQueueGet+0xac>
    }
    else {
      yield = pdFALSE;
 8013e28:	2300      	movs	r3, #0
 8013e2a:	613b      	str	r3, [r7, #16]

      if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) {
 8013e2c:	f107 0310 	add.w	r3, r7, #16
 8013e30:	461a      	mov	r2, r3
 8013e32:	68b9      	ldr	r1, [r7, #8]
 8013e34:	69b8      	ldr	r0, [r7, #24]
 8013e36:	f000 feaf 	bl	8014b98 <xQueueReceiveFromISR>
 8013e3a:	4603      	mov	r3, r0
 8013e3c:	2b01      	cmp	r3, #1
 8013e3e:	d003      	beq.n	8013e48 <osMessageQueueGet+0x5c>
        stat = osErrorResource;
 8013e40:	f06f 0302 	mvn.w	r3, #2
 8013e44:	61fb      	str	r3, [r7, #28]
 8013e46:	e027      	b.n	8013e98 <osMessageQueueGet+0xac>
      } else {
        portYIELD_FROM_ISR (yield);
 8013e48:	693b      	ldr	r3, [r7, #16]
 8013e4a:	2b00      	cmp	r3, #0
 8013e4c:	d024      	beq.n	8013e98 <osMessageQueueGet+0xac>
 8013e4e:	4b15      	ldr	r3, [pc, #84]	@ (8013ea4 <osMessageQueueGet+0xb8>)
 8013e50:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8013e54:	601a      	str	r2, [r3, #0]
 8013e56:	f3bf 8f4f 	dsb	sy
 8013e5a:	f3bf 8f6f 	isb	sy
 8013e5e:	e01b      	b.n	8013e98 <osMessageQueueGet+0xac>
      }
    }
  }
  else {
    if ((hQueue == NULL) || (msg_ptr == NULL)) {
 8013e60:	69bb      	ldr	r3, [r7, #24]
 8013e62:	2b00      	cmp	r3, #0
 8013e64:	d002      	beq.n	8013e6c <osMessageQueueGet+0x80>
 8013e66:	68bb      	ldr	r3, [r7, #8]
 8013e68:	2b00      	cmp	r3, #0
 8013e6a:	d103      	bne.n	8013e74 <osMessageQueueGet+0x88>
      stat = osErrorParameter;
 8013e6c:	f06f 0303 	mvn.w	r3, #3
 8013e70:	61fb      	str	r3, [r7, #28]
 8013e72:	e011      	b.n	8013e98 <osMessageQueueGet+0xac>
    }
    else {
      if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
 8013e74:	683a      	ldr	r2, [r7, #0]
 8013e76:	68b9      	ldr	r1, [r7, #8]
 8013e78:	69b8      	ldr	r0, [r7, #24]
 8013e7a:	f000 fc9b 	bl	80147b4 <xQueueReceive>
 8013e7e:	4603      	mov	r3, r0
 8013e80:	2b01      	cmp	r3, #1
 8013e82:	d009      	beq.n	8013e98 <osMessageQueueGet+0xac>
        if (timeout != 0U) {
 8013e84:	683b      	ldr	r3, [r7, #0]
 8013e86:	2b00      	cmp	r3, #0
 8013e88:	d003      	beq.n	8013e92 <osMessageQueueGet+0xa6>
          stat = osErrorTimeout;
 8013e8a:	f06f 0301 	mvn.w	r3, #1
 8013e8e:	61fb      	str	r3, [r7, #28]
 8013e90:	e002      	b.n	8013e98 <osMessageQueueGet+0xac>
        } else {
          stat = osErrorResource;
 8013e92:	f06f 0302 	mvn.w	r3, #2
 8013e96:	61fb      	str	r3, [r7, #28]
        }
      }
    }
  }

  return (stat);
 8013e98:	69fb      	ldr	r3, [r7, #28]
}
 8013e9a:	4618      	mov	r0, r3
 8013e9c:	3720      	adds	r7, #32
 8013e9e:	46bd      	mov	sp, r7
 8013ea0:	bd80      	pop	{r7, pc}
 8013ea2:	bf00      	nop
 8013ea4:	e000ed04 	.word	0xe000ed04

08013ea8 <vApplicationGetIdleTaskMemory>:

/*
  vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
  equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
 8013ea8:	b480      	push	{r7}
 8013eaa:	b085      	sub	sp, #20
 8013eac:	af00      	add	r7, sp, #0
 8013eae:	60f8      	str	r0, [r7, #12]
 8013eb0:	60b9      	str	r1, [r7, #8]
 8013eb2:	607a      	str	r2, [r7, #4]
  /* Idle task control block and stack */
  static StaticTask_t Idle_TCB;
  static StackType_t  Idle_Stack[configMINIMAL_STACK_SIZE];

  *ppxIdleTaskTCBBuffer   = &Idle_TCB;
 8013eb4:	68fb      	ldr	r3, [r7, #12]
 8013eb6:	4a07      	ldr	r2, [pc, #28]	@ (8013ed4 <vApplicationGetIdleTaskMemory+0x2c>)
 8013eb8:	601a      	str	r2, [r3, #0]
  *ppxIdleTaskStackBuffer = &Idle_Stack[0];
 8013eba:	68bb      	ldr	r3, [r7, #8]
 8013ebc:	4a06      	ldr	r2, [pc, #24]	@ (8013ed8 <vApplicationGetIdleTaskMemory+0x30>)
 8013ebe:	601a      	str	r2, [r3, #0]
  *pulIdleTaskStackSize   = (uint32_t)configMINIMAL_STACK_SIZE;
 8013ec0:	687b      	ldr	r3, [r7, #4]
 8013ec2:	f44f 7200 	mov.w	r2, #512	@ 0x200
 8013ec6:	601a      	str	r2, [r3, #0]
}
 8013ec8:	bf00      	nop
 8013eca:	3714      	adds	r7, #20
 8013ecc:	46bd      	mov	sp, r7
 8013ece:	f85d 7b04 	ldr.w	r7, [sp], #4
 8013ed2:	4770      	bx	lr
 8013ed4:	24000cb0 	.word	0x24000cb0
 8013ed8:	24000d58 	.word	0x24000d58

08013edc <vApplicationGetTimerTaskMemory>:

/*
  vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
  equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
 8013edc:	b480      	push	{r7}
 8013ede:	b085      	sub	sp, #20
 8013ee0:	af00      	add	r7, sp, #0
 8013ee2:	60f8      	str	r0, [r7, #12]
 8013ee4:	60b9      	str	r1, [r7, #8]
 8013ee6:	607a      	str	r2, [r7, #4]
  /* Timer task control block and stack */
  static StaticTask_t Timer_TCB;
  static StackType_t  Timer_Stack[configTIMER_TASK_STACK_DEPTH];

  *ppxTimerTaskTCBBuffer   = &Timer_TCB;
 8013ee8:	68fb      	ldr	r3, [r7, #12]
 8013eea:	4a07      	ldr	r2, [pc, #28]	@ (8013f08 <vApplicationGetTimerTaskMemory+0x2c>)
 8013eec:	601a      	str	r2, [r3, #0]
  *ppxTimerTaskStackBuffer = &Timer_Stack[0];
 8013eee:	68bb      	ldr	r3, [r7, #8]
 8013ef0:	4a06      	ldr	r2, [pc, #24]	@ (8013f0c <vApplicationGetTimerTaskMemory+0x30>)
 8013ef2:	601a      	str	r2, [r3, #0]
  *pulTimerTaskStackSize   = (uint32_t)configTIMER_TASK_STACK_DEPTH;
 8013ef4:	687b      	ldr	r3, [r7, #4]
 8013ef6:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 8013efa:	601a      	str	r2, [r3, #0]
}
 8013efc:	bf00      	nop
 8013efe:	3714      	adds	r7, #20
 8013f00:	46bd      	mov	sp, r7
 8013f02:	f85d 7b04 	ldr.w	r7, [sp], #4
 8013f06:	4770      	bx	lr
 8013f08:	24001558 	.word	0x24001558
 8013f0c:	24001600 	.word	0x24001600

08013f10 <vListInitialise>:
/*-----------------------------------------------------------
 * PUBLIC LIST API documented in list.h
 *----------------------------------------------------------*/

void vListInitialise( List_t * const pxList )
{
 8013f10:	b480      	push	{r7}
 8013f12:	b083      	sub	sp, #12
 8013f14:	af00      	add	r7, sp, #0
 8013f16:	6078      	str	r0, [r7, #4]
	/* The list structure contains a list item which is used to mark the
	end of the list.  To initialise the list the list end is inserted
	as the only list entry. */
	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 8013f18:	687b      	ldr	r3, [r7, #4]
 8013f1a:	f103 0208 	add.w	r2, r3, #8
 8013f1e:	687b      	ldr	r3, [r7, #4]
 8013f20:	605a      	str	r2, [r3, #4]

	/* The list end value is the highest possible value in the list to
	ensure it remains at the end of the list. */
	pxList->xListEnd.xItemValue = portMAX_DELAY;
 8013f22:	687b      	ldr	r3, [r7, #4]
 8013f24:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8013f28:	609a      	str	r2, [r3, #8]

	/* The list end next and previous pointers point to itself so we know
	when the list is empty. */
	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 8013f2a:	687b      	ldr	r3, [r7, #4]
 8013f2c:	f103 0208 	add.w	r2, r3, #8
 8013f30:	687b      	ldr	r3, [r7, #4]
 8013f32:	60da      	str	r2, [r3, #12]
	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 8013f34:	687b      	ldr	r3, [r7, #4]
 8013f36:	f103 0208 	add.w	r2, r3, #8
 8013f3a:	687b      	ldr	r3, [r7, #4]
 8013f3c:	611a      	str	r2, [r3, #16]

	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
 8013f3e:	687b      	ldr	r3, [r7, #4]
 8013f40:	2200      	movs	r2, #0
 8013f42:	601a      	str	r2, [r3, #0]

	/* Write known values into the list if
	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
 8013f44:	bf00      	nop
 8013f46:	370c      	adds	r7, #12
 8013f48:	46bd      	mov	sp, r7
 8013f4a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8013f4e:	4770      	bx	lr

08013f50 <vListInitialiseItem>:
/*-----------------------------------------------------------*/

void vListInitialiseItem( ListItem_t * const pxItem )
{
 8013f50:	b480      	push	{r7}
 8013f52:	b083      	sub	sp, #12
 8013f54:	af00      	add	r7, sp, #0
 8013f56:	6078      	str	r0, [r7, #4]
	/* Make sure the list item is not recorded as being on a list. */
	pxItem->pxContainer = NULL;
 8013f58:	687b      	ldr	r3, [r7, #4]
 8013f5a:	2200      	movs	r2, #0
 8013f5c:	611a      	str	r2, [r3, #16]

	/* Write known values into the list item if
	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
 8013f5e:	bf00      	nop
 8013f60:	370c      	adds	r7, #12
 8013f62:	46bd      	mov	sp, r7
 8013f64:	f85d 7b04 	ldr.w	r7, [sp], #4
 8013f68:	4770      	bx	lr

08013f6a <vListInsertEnd>:
/*-----------------------------------------------------------*/

void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
 8013f6a:	b480      	push	{r7}
 8013f6c:	b085      	sub	sp, #20
 8013f6e:	af00      	add	r7, sp, #0
 8013f70:	6078      	str	r0, [r7, #4]
 8013f72:	6039      	str	r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
 8013f74:	687b      	ldr	r3, [r7, #4]
 8013f76:	685b      	ldr	r3, [r3, #4]
 8013f78:	60fb      	str	r3, [r7, #12]
	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );

	/* Insert a new list item into pxList, but rather than sort the list,
	makes the new list item the last item to be removed by a call to
	listGET_OWNER_OF_NEXT_ENTRY(). */
	pxNewListItem->pxNext = pxIndex;
 8013f7a:	683b      	ldr	r3, [r7, #0]
 8013f7c:	68fa      	ldr	r2, [r7, #12]
 8013f7e:	605a      	str	r2, [r3, #4]
	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
 8013f80:	68fb      	ldr	r3, [r7, #12]
 8013f82:	689a      	ldr	r2, [r3, #8]
 8013f84:	683b      	ldr	r3, [r7, #0]
 8013f86:	609a      	str	r2, [r3, #8]

	/* Only used during decision coverage testing. */
	mtCOVERAGE_TEST_DELAY();

	pxIndex->pxPrevious->pxNext = pxNewListItem;
 8013f88:	68fb      	ldr	r3, [r7, #12]
 8013f8a:	689b      	ldr	r3, [r3, #8]
 8013f8c:	683a      	ldr	r2, [r7, #0]
 8013f8e:	605a      	str	r2, [r3, #4]
	pxIndex->pxPrevious = pxNewListItem;
 8013f90:	68fb      	ldr	r3, [r7, #12]
 8013f92:	683a      	ldr	r2, [r7, #0]
 8013f94:	609a      	str	r2, [r3, #8]

	/* Remember which list the item is in. */
	pxNewListItem->pxContainer = pxList;
 8013f96:	683b      	ldr	r3, [r7, #0]
 8013f98:	687a      	ldr	r2, [r7, #4]
 8013f9a:	611a      	str	r2, [r3, #16]

	( pxList->uxNumberOfItems )++;
 8013f9c:	687b      	ldr	r3, [r7, #4]
 8013f9e:	681b      	ldr	r3, [r3, #0]
 8013fa0:	1c5a      	adds	r2, r3, #1
 8013fa2:	687b      	ldr	r3, [r7, #4]
 8013fa4:	601a      	str	r2, [r3, #0]
}
 8013fa6:	bf00      	nop
 8013fa8:	3714      	adds	r7, #20
 8013faa:	46bd      	mov	sp, r7
 8013fac:	f85d 7b04 	ldr.w	r7, [sp], #4
 8013fb0:	4770      	bx	lr

08013fb2 <vListInsert>:
/*-----------------------------------------------------------*/

void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
 8013fb2:	b480      	push	{r7}
 8013fb4:	b085      	sub	sp, #20
 8013fb6:	af00      	add	r7, sp, #0
 8013fb8:	6078      	str	r0, [r7, #4]
 8013fba:	6039      	str	r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 8013fbc:	683b      	ldr	r3, [r7, #0]
 8013fbe:	681b      	ldr	r3, [r3, #0]
 8013fc0:	60bb      	str	r3, [r7, #8]
	new list item should be placed after it.  This ensures that TCBs which are
	stored in ready lists (all of which have the same xItemValue value) get a
	share of the CPU.  However, if the xItemValue is the same as the back marker
	the iteration loop below will not end.  Therefore the value is checked
	first, and the algorithm slightly modified if necessary. */
	if( xValueOfInsertion == portMAX_DELAY )
 8013fc2:	68bb      	ldr	r3, [r7, #8]
 8013fc4:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8013fc8:	d103      	bne.n	8013fd2 <vListInsert+0x20>
	{
		pxIterator = pxList->xListEnd.pxPrevious;
 8013fca:	687b      	ldr	r3, [r7, #4]
 8013fcc:	691b      	ldr	r3, [r3, #16]
 8013fce:	60fb      	str	r3, [r7, #12]
 8013fd0:	e00c      	b.n	8013fec <vListInsert+0x3a>
			4) Using a queue or semaphore before it has been initialised or
			   before the scheduler has been started (are interrupts firing
			   before vTaskStartScheduler() has been called?).
		**********************************************************************/

		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
 8013fd2:	687b      	ldr	r3, [r7, #4]
 8013fd4:	3308      	adds	r3, #8
 8013fd6:	60fb      	str	r3, [r7, #12]
 8013fd8:	e002      	b.n	8013fe0 <vListInsert+0x2e>
 8013fda:	68fb      	ldr	r3, [r7, #12]
 8013fdc:	685b      	ldr	r3, [r3, #4]
 8013fde:	60fb      	str	r3, [r7, #12]
 8013fe0:	68fb      	ldr	r3, [r7, #12]
 8013fe2:	685b      	ldr	r3, [r3, #4]
 8013fe4:	681b      	ldr	r3, [r3, #0]
 8013fe6:	68ba      	ldr	r2, [r7, #8]
 8013fe8:	429a      	cmp	r2, r3
 8013fea:	d2f6      	bcs.n	8013fda <vListInsert+0x28>
			/* There is nothing to do here, just iterating to the wanted
			insertion position. */
		}
	}

	pxNewListItem->pxNext = pxIterator->pxNext;
 8013fec:	68fb      	ldr	r3, [r7, #12]
 8013fee:	685a      	ldr	r2, [r3, #4]
 8013ff0:	683b      	ldr	r3, [r7, #0]
 8013ff2:	605a      	str	r2, [r3, #4]
	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
 8013ff4:	683b      	ldr	r3, [r7, #0]
 8013ff6:	685b      	ldr	r3, [r3, #4]
 8013ff8:	683a      	ldr	r2, [r7, #0]
 8013ffa:	609a      	str	r2, [r3, #8]
	pxNewListItem->pxPrevious = pxIterator;
 8013ffc:	683b      	ldr	r3, [r7, #0]
 8013ffe:	68fa      	ldr	r2, [r7, #12]
 8014000:	609a      	str	r2, [r3, #8]
	pxIterator->pxNext = pxNewListItem;
 8014002:	68fb      	ldr	r3, [r7, #12]
 8014004:	683a      	ldr	r2, [r7, #0]
 8014006:	605a      	str	r2, [r3, #4]

	/* Remember which list the item is in.  This allows fast removal of the
	item later. */
	pxNewListItem->pxContainer = pxList;
 8014008:	683b      	ldr	r3, [r7, #0]
 801400a:	687a      	ldr	r2, [r7, #4]
 801400c:	611a      	str	r2, [r3, #16]

	( pxList->uxNumberOfItems )++;
 801400e:	687b      	ldr	r3, [r7, #4]
 8014010:	681b      	ldr	r3, [r3, #0]
 8014012:	1c5a      	adds	r2, r3, #1
 8014014:	687b      	ldr	r3, [r7, #4]
 8014016:	601a      	str	r2, [r3, #0]
}
 8014018:	bf00      	nop
 801401a:	3714      	adds	r7, #20
 801401c:	46bd      	mov	sp, r7
 801401e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8014022:	4770      	bx	lr

08014024 <uxListRemove>:
/*-----------------------------------------------------------*/

UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
 8014024:	b480      	push	{r7}
 8014026:	b085      	sub	sp, #20
 8014028:	af00      	add	r7, sp, #0
 801402a:	6078      	str	r0, [r7, #4]
/* The list item knows which list it is in.  Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
 801402c:	687b      	ldr	r3, [r7, #4]
 801402e:	691b      	ldr	r3, [r3, #16]
 8014030:	60fb      	str	r3, [r7, #12]

	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
 8014032:	687b      	ldr	r3, [r7, #4]
 8014034:	685b      	ldr	r3, [r3, #4]
 8014036:	687a      	ldr	r2, [r7, #4]
 8014038:	6892      	ldr	r2, [r2, #8]
 801403a:	609a      	str	r2, [r3, #8]
	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
 801403c:	687b      	ldr	r3, [r7, #4]
 801403e:	689b      	ldr	r3, [r3, #8]
 8014040:	687a      	ldr	r2, [r7, #4]
 8014042:	6852      	ldr	r2, [r2, #4]
 8014044:	605a      	str	r2, [r3, #4]

	/* Only used during decision coverage testing. */
	mtCOVERAGE_TEST_DELAY();

	/* Make sure the index is left pointing to a valid item. */
	if( pxList->pxIndex == pxItemToRemove )
 8014046:	68fb      	ldr	r3, [r7, #12]
 8014048:	685b      	ldr	r3, [r3, #4]
 801404a:	687a      	ldr	r2, [r7, #4]
 801404c:	429a      	cmp	r2, r3
 801404e:	d103      	bne.n	8014058 <uxListRemove+0x34>
	{
		pxList->pxIndex = pxItemToRemove->pxPrevious;
 8014050:	687b      	ldr	r3, [r7, #4]
 8014052:	689a      	ldr	r2, [r3, #8]
 8014054:	68fb      	ldr	r3, [r7, #12]
 8014056:	605a      	str	r2, [r3, #4]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxItemToRemove->pxContainer = NULL;
 8014058:	687b      	ldr	r3, [r7, #4]
 801405a:	2200      	movs	r2, #0
 801405c:	611a      	str	r2, [r3, #16]
	( pxList->uxNumberOfItems )--;
 801405e:	68fb      	ldr	r3, [r7, #12]
 8014060:	681b      	ldr	r3, [r3, #0]
 8014062:	1e5a      	subs	r2, r3, #1
 8014064:	68fb      	ldr	r3, [r7, #12]
 8014066:	601a      	str	r2, [r3, #0]

	return pxList->uxNumberOfItems;
 8014068:	68fb      	ldr	r3, [r7, #12]
 801406a:	681b      	ldr	r3, [r3, #0]
}
 801406c:	4618      	mov	r0, r3
 801406e:	3714      	adds	r7, #20
 8014070:	46bd      	mov	sp, r7
 8014072:	f85d 7b04 	ldr.w	r7, [sp], #4
 8014076:	4770      	bx	lr

08014078 <xQueueGenericReset>:
	}														\
	taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
 8014078:	b580      	push	{r7, lr}
 801407a:	b084      	sub	sp, #16
 801407c:	af00      	add	r7, sp, #0
 801407e:	6078      	str	r0, [r7, #4]
 8014080:	6039      	str	r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
 8014082:	687b      	ldr	r3, [r7, #4]
 8014084:	60fb      	str	r3, [r7, #12]

	configASSERT( pxQueue );
 8014086:	68fb      	ldr	r3, [r7, #12]
 8014088:	2b00      	cmp	r3, #0
 801408a:	d10b      	bne.n	80140a4 <xQueueGenericReset+0x2c>

portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;

	__asm volatile
 801408c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014090:	f383 8811 	msr	BASEPRI, r3
 8014094:	f3bf 8f6f 	isb	sy
 8014098:	f3bf 8f4f 	dsb	sy
 801409c:	60bb      	str	r3, [r7, #8]
		"	msr basepri, %0											\n" \
		"	isb														\n" \
		"	dsb														\n" \
		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
	);
}
 801409e:	bf00      	nop
 80140a0:	bf00      	nop
 80140a2:	e7fd      	b.n	80140a0 <xQueueGenericReset+0x28>

	taskENTER_CRITICAL();
 80140a4:	f003 f960 	bl	8017368 <vPortEnterCritical>
	{
		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 80140a8:	68fb      	ldr	r3, [r7, #12]
 80140aa:	681a      	ldr	r2, [r3, #0]
 80140ac:	68fb      	ldr	r3, [r7, #12]
 80140ae:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80140b0:	68f9      	ldr	r1, [r7, #12]
 80140b2:	6c09      	ldr	r1, [r1, #64]	@ 0x40
 80140b4:	fb01 f303 	mul.w	r3, r1, r3
 80140b8:	441a      	add	r2, r3
 80140ba:	68fb      	ldr	r3, [r7, #12]
 80140bc:	609a      	str	r2, [r3, #8]
		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
 80140be:	68fb      	ldr	r3, [r7, #12]
 80140c0:	2200      	movs	r2, #0
 80140c2:	639a      	str	r2, [r3, #56]	@ 0x38
		pxQueue->pcWriteTo = pxQueue->pcHead;
 80140c4:	68fb      	ldr	r3, [r7, #12]
 80140c6:	681a      	ldr	r2, [r3, #0]
 80140c8:	68fb      	ldr	r3, [r7, #12]
 80140ca:	605a      	str	r2, [r3, #4]
		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 80140cc:	68fb      	ldr	r3, [r7, #12]
 80140ce:	681a      	ldr	r2, [r3, #0]
 80140d0:	68fb      	ldr	r3, [r7, #12]
 80140d2:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80140d4:	3b01      	subs	r3, #1
 80140d6:	68f9      	ldr	r1, [r7, #12]
 80140d8:	6c09      	ldr	r1, [r1, #64]	@ 0x40
 80140da:	fb01 f303 	mul.w	r3, r1, r3
 80140de:	441a      	add	r2, r3
 80140e0:	68fb      	ldr	r3, [r7, #12]
 80140e2:	60da      	str	r2, [r3, #12]
		pxQueue->cRxLock = queueUNLOCKED;
 80140e4:	68fb      	ldr	r3, [r7, #12]
 80140e6:	22ff      	movs	r2, #255	@ 0xff
 80140e8:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
		pxQueue->cTxLock = queueUNLOCKED;
 80140ec:	68fb      	ldr	r3, [r7, #12]
 80140ee:	22ff      	movs	r2, #255	@ 0xff
 80140f0:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45

		if( xNewQueue == pdFALSE )
 80140f4:	683b      	ldr	r3, [r7, #0]
 80140f6:	2b00      	cmp	r3, #0
 80140f8:	d114      	bne.n	8014124 <xQueueGenericReset+0xac>
			/* If there are tasks blocked waiting to read from the queue, then
			the tasks will remain blocked as after this function exits the queue
			will still be empty.  If there are tasks blocked waiting to write to
			the queue, then one should be unblocked as after this function exits
			it will be possible to write to it. */
			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 80140fa:	68fb      	ldr	r3, [r7, #12]
 80140fc:	691b      	ldr	r3, [r3, #16]
 80140fe:	2b00      	cmp	r3, #0
 8014100:	d01a      	beq.n	8014138 <xQueueGenericReset+0xc0>
			{
				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8014102:	68fb      	ldr	r3, [r7, #12]
 8014104:	3310      	adds	r3, #16
 8014106:	4618      	mov	r0, r3
 8014108:	f001 fdac 	bl	8015c64 <xTaskRemoveFromEventList>
 801410c:	4603      	mov	r3, r0
 801410e:	2b00      	cmp	r3, #0
 8014110:	d012      	beq.n	8014138 <xQueueGenericReset+0xc0>
				{
					queueYIELD_IF_USING_PREEMPTION();
 8014112:	4b0d      	ldr	r3, [pc, #52]	@ (8014148 <xQueueGenericReset+0xd0>)
 8014114:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8014118:	601a      	str	r2, [r3, #0]
 801411a:	f3bf 8f4f 	dsb	sy
 801411e:	f3bf 8f6f 	isb	sy
 8014122:	e009      	b.n	8014138 <xQueueGenericReset+0xc0>
			}
		}
		else
		{
			/* Ensure the event queues start in the correct state. */
			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
 8014124:	68fb      	ldr	r3, [r7, #12]
 8014126:	3310      	adds	r3, #16
 8014128:	4618      	mov	r0, r3
 801412a:	f7ff fef1 	bl	8013f10 <vListInitialise>
			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
 801412e:	68fb      	ldr	r3, [r7, #12]
 8014130:	3324      	adds	r3, #36	@ 0x24
 8014132:	4618      	mov	r0, r3
 8014134:	f7ff feec 	bl	8013f10 <vListInitialise>
		}
	}
	taskEXIT_CRITICAL();
 8014138:	f003 f948 	bl	80173cc <vPortExitCritical>

	/* A value is returned for calling semantic consistency with previous
	versions. */
	return pdPASS;
 801413c:	2301      	movs	r3, #1
}
 801413e:	4618      	mov	r0, r3
 8014140:	3710      	adds	r7, #16
 8014142:	46bd      	mov	sp, r7
 8014144:	bd80      	pop	{r7, pc}
 8014146:	bf00      	nop
 8014148:	e000ed04 	.word	0xe000ed04

0801414c <xQueueGenericCreateStatic>:
/*-----------------------------------------------------------*/

#if( configSUPPORT_STATIC_ALLOCATION == 1 )

	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
	{
 801414c:	b580      	push	{r7, lr}
 801414e:	b08e      	sub	sp, #56	@ 0x38
 8014150:	af02      	add	r7, sp, #8
 8014152:	60f8      	str	r0, [r7, #12]
 8014154:	60b9      	str	r1, [r7, #8]
 8014156:	607a      	str	r2, [r7, #4]
 8014158:	603b      	str	r3, [r7, #0]
	Queue_t *pxNewQueue;

		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
 801415a:	68fb      	ldr	r3, [r7, #12]
 801415c:	2b00      	cmp	r3, #0
 801415e:	d10b      	bne.n	8014178 <xQueueGenericCreateStatic+0x2c>
	__asm volatile
 8014160:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014164:	f383 8811 	msr	BASEPRI, r3
 8014168:	f3bf 8f6f 	isb	sy
 801416c:	f3bf 8f4f 	dsb	sy
 8014170:	62bb      	str	r3, [r7, #40]	@ 0x28
}
 8014172:	bf00      	nop
 8014174:	bf00      	nop
 8014176:	e7fd      	b.n	8014174 <xQueueGenericCreateStatic+0x28>

		/* The StaticQueue_t structure and the queue storage area must be
		supplied. */
		configASSERT( pxStaticQueue != NULL );
 8014178:	683b      	ldr	r3, [r7, #0]
 801417a:	2b00      	cmp	r3, #0
 801417c:	d10b      	bne.n	8014196 <xQueueGenericCreateStatic+0x4a>
	__asm volatile
 801417e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014182:	f383 8811 	msr	BASEPRI, r3
 8014186:	f3bf 8f6f 	isb	sy
 801418a:	f3bf 8f4f 	dsb	sy
 801418e:	627b      	str	r3, [r7, #36]	@ 0x24
}
 8014190:	bf00      	nop
 8014192:	bf00      	nop
 8014194:	e7fd      	b.n	8014192 <xQueueGenericCreateStatic+0x46>

		/* A queue storage area should be provided if the item size is not 0, and
		should not be provided if the item size is 0. */
		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
 8014196:	687b      	ldr	r3, [r7, #4]
 8014198:	2b00      	cmp	r3, #0
 801419a:	d002      	beq.n	80141a2 <xQueueGenericCreateStatic+0x56>
 801419c:	68bb      	ldr	r3, [r7, #8]
 801419e:	2b00      	cmp	r3, #0
 80141a0:	d001      	beq.n	80141a6 <xQueueGenericCreateStatic+0x5a>
 80141a2:	2301      	movs	r3, #1
 80141a4:	e000      	b.n	80141a8 <xQueueGenericCreateStatic+0x5c>
 80141a6:	2300      	movs	r3, #0
 80141a8:	2b00      	cmp	r3, #0
 80141aa:	d10b      	bne.n	80141c4 <xQueueGenericCreateStatic+0x78>
	__asm volatile
 80141ac:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80141b0:	f383 8811 	msr	BASEPRI, r3
 80141b4:	f3bf 8f6f 	isb	sy
 80141b8:	f3bf 8f4f 	dsb	sy
 80141bc:	623b      	str	r3, [r7, #32]
}
 80141be:	bf00      	nop
 80141c0:	bf00      	nop
 80141c2:	e7fd      	b.n	80141c0 <xQueueGenericCreateStatic+0x74>
		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
 80141c4:	687b      	ldr	r3, [r7, #4]
 80141c6:	2b00      	cmp	r3, #0
 80141c8:	d102      	bne.n	80141d0 <xQueueGenericCreateStatic+0x84>
 80141ca:	68bb      	ldr	r3, [r7, #8]
 80141cc:	2b00      	cmp	r3, #0
 80141ce:	d101      	bne.n	80141d4 <xQueueGenericCreateStatic+0x88>
 80141d0:	2301      	movs	r3, #1
 80141d2:	e000      	b.n	80141d6 <xQueueGenericCreateStatic+0x8a>
 80141d4:	2300      	movs	r3, #0
 80141d6:	2b00      	cmp	r3, #0
 80141d8:	d10b      	bne.n	80141f2 <xQueueGenericCreateStatic+0xa6>
	__asm volatile
 80141da:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80141de:	f383 8811 	msr	BASEPRI, r3
 80141e2:	f3bf 8f6f 	isb	sy
 80141e6:	f3bf 8f4f 	dsb	sy
 80141ea:	61fb      	str	r3, [r7, #28]
}
 80141ec:	bf00      	nop
 80141ee:	bf00      	nop
 80141f0:	e7fd      	b.n	80141ee <xQueueGenericCreateStatic+0xa2>
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
			the real queue and semaphore structures. */
			volatile size_t xSize = sizeof( StaticQueue_t );
 80141f2:	2350      	movs	r3, #80	@ 0x50
 80141f4:	617b      	str	r3, [r7, #20]
			configASSERT( xSize == sizeof( Queue_t ) );
 80141f6:	697b      	ldr	r3, [r7, #20]
 80141f8:	2b50      	cmp	r3, #80	@ 0x50
 80141fa:	d00b      	beq.n	8014214 <xQueueGenericCreateStatic+0xc8>
	__asm volatile
 80141fc:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014200:	f383 8811 	msr	BASEPRI, r3
 8014204:	f3bf 8f6f 	isb	sy
 8014208:	f3bf 8f4f 	dsb	sy
 801420c:	61bb      	str	r3, [r7, #24]
}
 801420e:	bf00      	nop
 8014210:	bf00      	nop
 8014212:	e7fd      	b.n	8014210 <xQueueGenericCreateStatic+0xc4>
			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
 8014214:	697b      	ldr	r3, [r7, #20]
		#endif /* configASSERT_DEFINED */

		/* The address of a statically allocated queue was passed in, use it.
		The address of a statically allocated storage area was also passed in
		but is already set. */
		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 8014216:	683b      	ldr	r3, [r7, #0]
 8014218:	62fb      	str	r3, [r7, #44]	@ 0x2c

		if( pxNewQueue != NULL )
 801421a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 801421c:	2b00      	cmp	r3, #0
 801421e:	d00d      	beq.n	801423c <xQueueGenericCreateStatic+0xf0>
			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
			{
				/* Queues can be allocated wither statically or dynamically, so
				note this queue was allocated statically in case the queue is
				later deleted. */
				pxNewQueue->ucStaticallyAllocated = pdTRUE;
 8014220:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014222:	2201      	movs	r2, #1
 8014224:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
			}
			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */

			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
 8014228:	f897 2038 	ldrb.w	r2, [r7, #56]	@ 0x38
 801422c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 801422e:	9300      	str	r3, [sp, #0]
 8014230:	4613      	mov	r3, r2
 8014232:	687a      	ldr	r2, [r7, #4]
 8014234:	68b9      	ldr	r1, [r7, #8]
 8014236:	68f8      	ldr	r0, [r7, #12]
 8014238:	f000 f840 	bl	80142bc <prvInitialiseNewQueue>
		{
			traceQUEUE_CREATE_FAILED( ucQueueType );
			mtCOVERAGE_TEST_MARKER();
		}

		return pxNewQueue;
 801423c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
	}
 801423e:	4618      	mov	r0, r3
 8014240:	3730      	adds	r7, #48	@ 0x30
 8014242:	46bd      	mov	sp, r7
 8014244:	bd80      	pop	{r7, pc}

08014246 <xQueueGenericCreate>:
/*-----------------------------------------------------------*/

#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )

	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
	{
 8014246:	b580      	push	{r7, lr}
 8014248:	b08a      	sub	sp, #40	@ 0x28
 801424a:	af02      	add	r7, sp, #8
 801424c:	60f8      	str	r0, [r7, #12]
 801424e:	60b9      	str	r1, [r7, #8]
 8014250:	4613      	mov	r3, r2
 8014252:	71fb      	strb	r3, [r7, #7]
	Queue_t *pxNewQueue;
	size_t xQueueSizeInBytes;
	uint8_t *pucQueueStorage;

		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
 8014254:	68fb      	ldr	r3, [r7, #12]
 8014256:	2b00      	cmp	r3, #0
 8014258:	d10b      	bne.n	8014272 <xQueueGenericCreate+0x2c>
	__asm volatile
 801425a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801425e:	f383 8811 	msr	BASEPRI, r3
 8014262:	f3bf 8f6f 	isb	sy
 8014266:	f3bf 8f4f 	dsb	sy
 801426a:	613b      	str	r3, [r7, #16]
}
 801426c:	bf00      	nop
 801426e:	bf00      	nop
 8014270:	e7fd      	b.n	801426e <xQueueGenericCreate+0x28>

		/* Allocate enough space to hold the maximum number of items that
		can be in the queue at any time.  It is valid for uxItemSize to be
		zero in the case the queue is used as a semaphore. */
		xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8014272:	68fb      	ldr	r3, [r7, #12]
 8014274:	68ba      	ldr	r2, [r7, #8]
 8014276:	fb02 f303 	mul.w	r3, r2, r3
 801427a:	61fb      	str	r3, [r7, #28]
		alignment requirements of the Queue_t structure - which in this case
		is an int8_t *.  Therefore, whenever the stack alignment requirements
		are greater than or equal to the pointer to char requirements the cast
		is safe.  In other cases alignment requirements are not strict (one or
		two bytes). */
		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
 801427c:	69fb      	ldr	r3, [r7, #28]
 801427e:	3350      	adds	r3, #80	@ 0x50
 8014280:	4618      	mov	r0, r3
 8014282:	f003 f993 	bl	80175ac <pvPortMalloc>
 8014286:	61b8      	str	r0, [r7, #24]

		if( pxNewQueue != NULL )
 8014288:	69bb      	ldr	r3, [r7, #24]
 801428a:	2b00      	cmp	r3, #0
 801428c:	d011      	beq.n	80142b2 <xQueueGenericCreate+0x6c>
		{
			/* Jump past the queue structure to find the location of the queue
			storage area. */
			pucQueueStorage = ( uint8_t * ) pxNewQueue;
 801428e:	69bb      	ldr	r3, [r7, #24]
 8014290:	617b      	str	r3, [r7, #20]
			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 8014292:	697b      	ldr	r3, [r7, #20]
 8014294:	3350      	adds	r3, #80	@ 0x50
 8014296:	617b      	str	r3, [r7, #20]
			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
			{
				/* Queues can be created either statically or dynamically, so
				note this task was created dynamically in case it is later
				deleted. */
				pxNewQueue->ucStaticallyAllocated = pdFALSE;
 8014298:	69bb      	ldr	r3, [r7, #24]
 801429a:	2200      	movs	r2, #0
 801429c:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
			}
			#endif /* configSUPPORT_STATIC_ALLOCATION */

			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
 80142a0:	79fa      	ldrb	r2, [r7, #7]
 80142a2:	69bb      	ldr	r3, [r7, #24]
 80142a4:	9300      	str	r3, [sp, #0]
 80142a6:	4613      	mov	r3, r2
 80142a8:	697a      	ldr	r2, [r7, #20]
 80142aa:	68b9      	ldr	r1, [r7, #8]
 80142ac:	68f8      	ldr	r0, [r7, #12]
 80142ae:	f000 f805 	bl	80142bc <prvInitialiseNewQueue>
		{
			traceQUEUE_CREATE_FAILED( ucQueueType );
			mtCOVERAGE_TEST_MARKER();
		}

		return pxNewQueue;
 80142b2:	69bb      	ldr	r3, [r7, #24]
	}
 80142b4:	4618      	mov	r0, r3
 80142b6:	3720      	adds	r7, #32
 80142b8:	46bd      	mov	sp, r7
 80142ba:	bd80      	pop	{r7, pc}

080142bc <prvInitialiseNewQueue>:

#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
 80142bc:	b580      	push	{r7, lr}
 80142be:	b084      	sub	sp, #16
 80142c0:	af00      	add	r7, sp, #0
 80142c2:	60f8      	str	r0, [r7, #12]
 80142c4:	60b9      	str	r1, [r7, #8]
 80142c6:	607a      	str	r2, [r7, #4]
 80142c8:	70fb      	strb	r3, [r7, #3]
	/* Remove compiler warnings about unused parameters should
	configUSE_TRACE_FACILITY not be set to 1. */
	( void ) ucQueueType;

	if( uxItemSize == ( UBaseType_t ) 0 )
 80142ca:	68bb      	ldr	r3, [r7, #8]
 80142cc:	2b00      	cmp	r3, #0
 80142ce:	d103      	bne.n	80142d8 <prvInitialiseNewQueue+0x1c>
	{
		/* No RAM was allocated for the queue storage area, but PC head cannot
		be set to NULL because NULL is used as a key to say the queue is used as
		a mutex.  Therefore just set pcHead to point to the queue as a benign
		value that is known to be within the memory map. */
		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
 80142d0:	69bb      	ldr	r3, [r7, #24]
 80142d2:	69ba      	ldr	r2, [r7, #24]
 80142d4:	601a      	str	r2, [r3, #0]
 80142d6:	e002      	b.n	80142de <prvInitialiseNewQueue+0x22>
	}
	else
	{
		/* Set the head to the start of the queue storage area. */
		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
 80142d8:	69bb      	ldr	r3, [r7, #24]
 80142da:	687a      	ldr	r2, [r7, #4]
 80142dc:	601a      	str	r2, [r3, #0]
	}

	/* Initialise the queue members as described where the queue type is
	defined. */
	pxNewQueue->uxLength = uxQueueLength;
 80142de:	69bb      	ldr	r3, [r7, #24]
 80142e0:	68fa      	ldr	r2, [r7, #12]
 80142e2:	63da      	str	r2, [r3, #60]	@ 0x3c
	pxNewQueue->uxItemSize = uxItemSize;
 80142e4:	69bb      	ldr	r3, [r7, #24]
 80142e6:	68ba      	ldr	r2, [r7, #8]
 80142e8:	641a      	str	r2, [r3, #64]	@ 0x40
	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
 80142ea:	2101      	movs	r1, #1
 80142ec:	69b8      	ldr	r0, [r7, #24]
 80142ee:	f7ff fec3 	bl	8014078 <xQueueGenericReset>

	#if ( configUSE_TRACE_FACILITY == 1 )
	{
		pxNewQueue->ucQueueType = ucQueueType;
 80142f2:	69bb      	ldr	r3, [r7, #24]
 80142f4:	78fa      	ldrb	r2, [r7, #3]
 80142f6:	f883 204c 	strb.w	r2, [r3, #76]	@ 0x4c
		pxNewQueue->pxQueueSetContainer = NULL;
	}
	#endif /* configUSE_QUEUE_SETS */

	traceQUEUE_CREATE( pxNewQueue );
}
 80142fa:	bf00      	nop
 80142fc:	3710      	adds	r7, #16
 80142fe:	46bd      	mov	sp, r7
 8014300:	bd80      	pop	{r7, pc}

08014302 <prvInitialiseMutex>:
/*-----------------------------------------------------------*/

#if( configUSE_MUTEXES == 1 )

	static void prvInitialiseMutex( Queue_t *pxNewQueue )
	{
 8014302:	b580      	push	{r7, lr}
 8014304:	b082      	sub	sp, #8
 8014306:	af00      	add	r7, sp, #0
 8014308:	6078      	str	r0, [r7, #4]
		if( pxNewQueue != NULL )
 801430a:	687b      	ldr	r3, [r7, #4]
 801430c:	2b00      	cmp	r3, #0
 801430e:	d00e      	beq.n	801432e <prvInitialiseMutex+0x2c>
		{
			/* The queue create function will set all the queue structure members
			correctly for a generic queue, but this function is creating a
			mutex.  Overwrite those members that need to be set differently -
			in particular the information required for priority inheritance. */
			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
 8014310:	687b      	ldr	r3, [r7, #4]
 8014312:	2200      	movs	r2, #0
 8014314:	609a      	str	r2, [r3, #8]
			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
 8014316:	687b      	ldr	r3, [r7, #4]
 8014318:	2200      	movs	r2, #0
 801431a:	601a      	str	r2, [r3, #0]

			/* In case this is a recursive mutex. */
			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
 801431c:	687b      	ldr	r3, [r7, #4]
 801431e:	2200      	movs	r2, #0
 8014320:	60da      	str	r2, [r3, #12]

			traceCREATE_MUTEX( pxNewQueue );

			/* Start with the semaphore in the expected state. */
			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
 8014322:	2300      	movs	r3, #0
 8014324:	2200      	movs	r2, #0
 8014326:	2100      	movs	r1, #0
 8014328:	6878      	ldr	r0, [r7, #4]
 801432a:	f000 f8a3 	bl	8014474 <xQueueGenericSend>
		}
		else
		{
			traceCREATE_MUTEX_FAILED();
		}
	}
 801432e:	bf00      	nop
 8014330:	3708      	adds	r7, #8
 8014332:	46bd      	mov	sp, r7
 8014334:	bd80      	pop	{r7, pc}

08014336 <xQueueCreateMutex>:
/*-----------------------------------------------------------*/

#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )

	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
	{
 8014336:	b580      	push	{r7, lr}
 8014338:	b086      	sub	sp, #24
 801433a:	af00      	add	r7, sp, #0
 801433c:	4603      	mov	r3, r0
 801433e:	71fb      	strb	r3, [r7, #7]
	QueueHandle_t xNewQueue;
	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
 8014340:	2301      	movs	r3, #1
 8014342:	617b      	str	r3, [r7, #20]
 8014344:	2300      	movs	r3, #0
 8014346:	613b      	str	r3, [r7, #16]

		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
 8014348:	79fb      	ldrb	r3, [r7, #7]
 801434a:	461a      	mov	r2, r3
 801434c:	6939      	ldr	r1, [r7, #16]
 801434e:	6978      	ldr	r0, [r7, #20]
 8014350:	f7ff ff79 	bl	8014246 <xQueueGenericCreate>
 8014354:	60f8      	str	r0, [r7, #12]
		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
 8014356:	68f8      	ldr	r0, [r7, #12]
 8014358:	f7ff ffd3 	bl	8014302 <prvInitialiseMutex>

		return xNewQueue;
 801435c:	68fb      	ldr	r3, [r7, #12]
	}
 801435e:	4618      	mov	r0, r3
 8014360:	3718      	adds	r7, #24
 8014362:	46bd      	mov	sp, r7
 8014364:	bd80      	pop	{r7, pc}

08014366 <xQueueCreateMutexStatic>:
/*-----------------------------------------------------------*/

#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )

	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
	{
 8014366:	b580      	push	{r7, lr}
 8014368:	b088      	sub	sp, #32
 801436a:	af02      	add	r7, sp, #8
 801436c:	4603      	mov	r3, r0
 801436e:	6039      	str	r1, [r7, #0]
 8014370:	71fb      	strb	r3, [r7, #7]
	QueueHandle_t xNewQueue;
	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
 8014372:	2301      	movs	r3, #1
 8014374:	617b      	str	r3, [r7, #20]
 8014376:	2300      	movs	r3, #0
 8014378:	613b      	str	r3, [r7, #16]

		/* Prevent compiler warnings about unused parameters if
		configUSE_TRACE_FACILITY does not equal 1. */
		( void ) ucQueueType;

		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
 801437a:	79fb      	ldrb	r3, [r7, #7]
 801437c:	9300      	str	r3, [sp, #0]
 801437e:	683b      	ldr	r3, [r7, #0]
 8014380:	2200      	movs	r2, #0
 8014382:	6939      	ldr	r1, [r7, #16]
 8014384:	6978      	ldr	r0, [r7, #20]
 8014386:	f7ff fee1 	bl	801414c <xQueueGenericCreateStatic>
 801438a:	60f8      	str	r0, [r7, #12]
		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
 801438c:	68f8      	ldr	r0, [r7, #12]
 801438e:	f7ff ffb8 	bl	8014302 <prvInitialiseMutex>

		return xNewQueue;
 8014392:	68fb      	ldr	r3, [r7, #12]
	}
 8014394:	4618      	mov	r0, r3
 8014396:	3718      	adds	r7, #24
 8014398:	46bd      	mov	sp, r7
 801439a:	bd80      	pop	{r7, pc}

0801439c <xQueueGiveMutexRecursive>:
/*-----------------------------------------------------------*/

#if ( configUSE_RECURSIVE_MUTEXES == 1 )

	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
	{
 801439c:	b590      	push	{r4, r7, lr}
 801439e:	b087      	sub	sp, #28
 80143a0:	af00      	add	r7, sp, #0
 80143a2:	6078      	str	r0, [r7, #4]
	BaseType_t xReturn;
	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
 80143a4:	687b      	ldr	r3, [r7, #4]
 80143a6:	613b      	str	r3, [r7, #16]

		configASSERT( pxMutex );
 80143a8:	693b      	ldr	r3, [r7, #16]
 80143aa:	2b00      	cmp	r3, #0
 80143ac:	d10b      	bne.n	80143c6 <xQueueGiveMutexRecursive+0x2a>
	__asm volatile
 80143ae:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80143b2:	f383 8811 	msr	BASEPRI, r3
 80143b6:	f3bf 8f6f 	isb	sy
 80143ba:	f3bf 8f4f 	dsb	sy
 80143be:	60fb      	str	r3, [r7, #12]
}
 80143c0:	bf00      	nop
 80143c2:	bf00      	nop
 80143c4:	e7fd      	b.n	80143c2 <xQueueGiveMutexRecursive+0x26>
		change outside of this task.  If this task does not hold the mutex then
		pxMutexHolder can never coincidentally equal the tasks handle, and as
		this is the only condition we are interested in it does not matter if
		pxMutexHolder is accessed simultaneously by another task.  Therefore no
		mutual exclusion is required to test the pxMutexHolder variable. */
		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
 80143c6:	693b      	ldr	r3, [r7, #16]
 80143c8:	689c      	ldr	r4, [r3, #8]
 80143ca:	f001 fe39 	bl	8016040 <xTaskGetCurrentTaskHandle>
 80143ce:	4603      	mov	r3, r0
 80143d0:	429c      	cmp	r4, r3
 80143d2:	d111      	bne.n	80143f8 <xQueueGiveMutexRecursive+0x5c>
			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
			the task handle, therefore no underflow check is required.  Also,
			uxRecursiveCallCount is only modified by the mutex holder, and as
			there can only be one, no mutual exclusion is required to modify the
			uxRecursiveCallCount member. */
			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
 80143d4:	693b      	ldr	r3, [r7, #16]
 80143d6:	68db      	ldr	r3, [r3, #12]
 80143d8:	1e5a      	subs	r2, r3, #1
 80143da:	693b      	ldr	r3, [r7, #16]
 80143dc:	60da      	str	r2, [r3, #12]

			/* Has the recursive call count unwound to 0? */
			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
 80143de:	693b      	ldr	r3, [r7, #16]
 80143e0:	68db      	ldr	r3, [r3, #12]
 80143e2:	2b00      	cmp	r3, #0
 80143e4:	d105      	bne.n	80143f2 <xQueueGiveMutexRecursive+0x56>
			{
				/* Return the mutex.  This will automatically unblock any other
				task that might be waiting to access the mutex. */
				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
 80143e6:	2300      	movs	r3, #0
 80143e8:	2200      	movs	r2, #0
 80143ea:	2100      	movs	r1, #0
 80143ec:	6938      	ldr	r0, [r7, #16]
 80143ee:	f000 f841 	bl	8014474 <xQueueGenericSend>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}

			xReturn = pdPASS;
 80143f2:	2301      	movs	r3, #1
 80143f4:	617b      	str	r3, [r7, #20]
 80143f6:	e001      	b.n	80143fc <xQueueGiveMutexRecursive+0x60>
		}
		else
		{
			/* The mutex cannot be given because the calling task is not the
			holder. */
			xReturn = pdFAIL;
 80143f8:	2300      	movs	r3, #0
 80143fa:	617b      	str	r3, [r7, #20]

			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
		}

		return xReturn;
 80143fc:	697b      	ldr	r3, [r7, #20]
	}
 80143fe:	4618      	mov	r0, r3
 8014400:	371c      	adds	r7, #28
 8014402:	46bd      	mov	sp, r7
 8014404:	bd90      	pop	{r4, r7, pc}

08014406 <xQueueTakeMutexRecursive>:
/*-----------------------------------------------------------*/

#if ( configUSE_RECURSIVE_MUTEXES == 1 )

	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
	{
 8014406:	b590      	push	{r4, r7, lr}
 8014408:	b087      	sub	sp, #28
 801440a:	af00      	add	r7, sp, #0
 801440c:	6078      	str	r0, [r7, #4]
 801440e:	6039      	str	r1, [r7, #0]
	BaseType_t xReturn;
	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
 8014410:	687b      	ldr	r3, [r7, #4]
 8014412:	613b      	str	r3, [r7, #16]

		configASSERT( pxMutex );
 8014414:	693b      	ldr	r3, [r7, #16]
 8014416:	2b00      	cmp	r3, #0
 8014418:	d10b      	bne.n	8014432 <xQueueTakeMutexRecursive+0x2c>
	__asm volatile
 801441a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801441e:	f383 8811 	msr	BASEPRI, r3
 8014422:	f3bf 8f6f 	isb	sy
 8014426:	f3bf 8f4f 	dsb	sy
 801442a:	60fb      	str	r3, [r7, #12]
}
 801442c:	bf00      	nop
 801442e:	bf00      	nop
 8014430:	e7fd      	b.n	801442e <xQueueTakeMutexRecursive+0x28>
		/* Comments regarding mutual exclusion as per those within
		xQueueGiveMutexRecursive(). */

		traceTAKE_MUTEX_RECURSIVE( pxMutex );

		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
 8014432:	693b      	ldr	r3, [r7, #16]
 8014434:	689c      	ldr	r4, [r3, #8]
 8014436:	f001 fe03 	bl	8016040 <xTaskGetCurrentTaskHandle>
 801443a:	4603      	mov	r3, r0
 801443c:	429c      	cmp	r4, r3
 801443e:	d107      	bne.n	8014450 <xQueueTakeMutexRecursive+0x4a>
		{
			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
 8014440:	693b      	ldr	r3, [r7, #16]
 8014442:	68db      	ldr	r3, [r3, #12]
 8014444:	1c5a      	adds	r2, r3, #1
 8014446:	693b      	ldr	r3, [r7, #16]
 8014448:	60da      	str	r2, [r3, #12]
			xReturn = pdPASS;
 801444a:	2301      	movs	r3, #1
 801444c:	617b      	str	r3, [r7, #20]
 801444e:	e00c      	b.n	801446a <xQueueTakeMutexRecursive+0x64>
		}
		else
		{
			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
 8014450:	6839      	ldr	r1, [r7, #0]
 8014452:	6938      	ldr	r0, [r7, #16]
 8014454:	f000 fa90 	bl	8014978 <xQueueSemaphoreTake>
 8014458:	6178      	str	r0, [r7, #20]

			/* pdPASS will only be returned if the mutex was successfully
			obtained.  The calling task may have entered the Blocked state
			before reaching here. */
			if( xReturn != pdFAIL )
 801445a:	697b      	ldr	r3, [r7, #20]
 801445c:	2b00      	cmp	r3, #0
 801445e:	d004      	beq.n	801446a <xQueueTakeMutexRecursive+0x64>
			{
				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
 8014460:	693b      	ldr	r3, [r7, #16]
 8014462:	68db      	ldr	r3, [r3, #12]
 8014464:	1c5a      	adds	r2, r3, #1
 8014466:	693b      	ldr	r3, [r7, #16]
 8014468:	60da      	str	r2, [r3, #12]
			{
				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
			}
		}

		return xReturn;
 801446a:	697b      	ldr	r3, [r7, #20]
	}
 801446c:	4618      	mov	r0, r3
 801446e:	371c      	adds	r7, #28
 8014470:	46bd      	mov	sp, r7
 8014472:	bd90      	pop	{r4, r7, pc}

08014474 <xQueueGenericSend>:

#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
 8014474:	b580      	push	{r7, lr}
 8014476:	b08e      	sub	sp, #56	@ 0x38
 8014478:	af00      	add	r7, sp, #0
 801447a:	60f8      	str	r0, [r7, #12]
 801447c:	60b9      	str	r1, [r7, #8]
 801447e:	607a      	str	r2, [r7, #4]
 8014480:	603b      	str	r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
 8014482:	2300      	movs	r3, #0
 8014484:	637b      	str	r3, [r7, #52]	@ 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 8014486:	68fb      	ldr	r3, [r7, #12]
 8014488:	633b      	str	r3, [r7, #48]	@ 0x30

	configASSERT( pxQueue );
 801448a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801448c:	2b00      	cmp	r3, #0
 801448e:	d10b      	bne.n	80144a8 <xQueueGenericSend+0x34>
	__asm volatile
 8014490:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014494:	f383 8811 	msr	BASEPRI, r3
 8014498:	f3bf 8f6f 	isb	sy
 801449c:	f3bf 8f4f 	dsb	sy
 80144a0:	62bb      	str	r3, [r7, #40]	@ 0x28
}
 80144a2:	bf00      	nop
 80144a4:	bf00      	nop
 80144a6:	e7fd      	b.n	80144a4 <xQueueGenericSend+0x30>
	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 80144a8:	68bb      	ldr	r3, [r7, #8]
 80144aa:	2b00      	cmp	r3, #0
 80144ac:	d103      	bne.n	80144b6 <xQueueGenericSend+0x42>
 80144ae:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80144b0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80144b2:	2b00      	cmp	r3, #0
 80144b4:	d101      	bne.n	80144ba <xQueueGenericSend+0x46>
 80144b6:	2301      	movs	r3, #1
 80144b8:	e000      	b.n	80144bc <xQueueGenericSend+0x48>
 80144ba:	2300      	movs	r3, #0
 80144bc:	2b00      	cmp	r3, #0
 80144be:	d10b      	bne.n	80144d8 <xQueueGenericSend+0x64>
	__asm volatile
 80144c0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80144c4:	f383 8811 	msr	BASEPRI, r3
 80144c8:	f3bf 8f6f 	isb	sy
 80144cc:	f3bf 8f4f 	dsb	sy
 80144d0:	627b      	str	r3, [r7, #36]	@ 0x24
}
 80144d2:	bf00      	nop
 80144d4:	bf00      	nop
 80144d6:	e7fd      	b.n	80144d4 <xQueueGenericSend+0x60>
	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 80144d8:	683b      	ldr	r3, [r7, #0]
 80144da:	2b02      	cmp	r3, #2
 80144dc:	d103      	bne.n	80144e6 <xQueueGenericSend+0x72>
 80144de:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80144e0:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80144e2:	2b01      	cmp	r3, #1
 80144e4:	d101      	bne.n	80144ea <xQueueGenericSend+0x76>
 80144e6:	2301      	movs	r3, #1
 80144e8:	e000      	b.n	80144ec <xQueueGenericSend+0x78>
 80144ea:	2300      	movs	r3, #0
 80144ec:	2b00      	cmp	r3, #0
 80144ee:	d10b      	bne.n	8014508 <xQueueGenericSend+0x94>
	__asm volatile
 80144f0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80144f4:	f383 8811 	msr	BASEPRI, r3
 80144f8:	f3bf 8f6f 	isb	sy
 80144fc:	f3bf 8f4f 	dsb	sy
 8014500:	623b      	str	r3, [r7, #32]
}
 8014502:	bf00      	nop
 8014504:	bf00      	nop
 8014506:	e7fd      	b.n	8014504 <xQueueGenericSend+0x90>
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 8014508:	f001 fdaa 	bl	8016060 <xTaskGetSchedulerState>
 801450c:	4603      	mov	r3, r0
 801450e:	2b00      	cmp	r3, #0
 8014510:	d102      	bne.n	8014518 <xQueueGenericSend+0xa4>
 8014512:	687b      	ldr	r3, [r7, #4]
 8014514:	2b00      	cmp	r3, #0
 8014516:	d101      	bne.n	801451c <xQueueGenericSend+0xa8>
 8014518:	2301      	movs	r3, #1
 801451a:	e000      	b.n	801451e <xQueueGenericSend+0xaa>
 801451c:	2300      	movs	r3, #0
 801451e:	2b00      	cmp	r3, #0
 8014520:	d10b      	bne.n	801453a <xQueueGenericSend+0xc6>
	__asm volatile
 8014522:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014526:	f383 8811 	msr	BASEPRI, r3
 801452a:	f3bf 8f6f 	isb	sy
 801452e:	f3bf 8f4f 	dsb	sy
 8014532:	61fb      	str	r3, [r7, #28]
}
 8014534:	bf00      	nop
 8014536:	bf00      	nop
 8014538:	e7fd      	b.n	8014536 <xQueueGenericSend+0xc2>
	/*lint -save -e904 This function relaxes the coding standard somewhat to
	allow return statements within the function itself.  This is done in the
	interest of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 801453a:	f002 ff15 	bl	8017368 <vPortEnterCritical>
		{
			/* Is there room on the queue now?  The running task must be the
			highest priority task wanting to access the queue.  If the head item
			in the queue is to be overwritten then it does not matter if the
			queue is full. */
			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 801453e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014540:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 8014542:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014544:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8014546:	429a      	cmp	r2, r3
 8014548:	d302      	bcc.n	8014550 <xQueueGenericSend+0xdc>
 801454a:	683b      	ldr	r3, [r7, #0]
 801454c:	2b02      	cmp	r3, #2
 801454e:	d129      	bne.n	80145a4 <xQueueGenericSend+0x130>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 8014550:	683a      	ldr	r2, [r7, #0]
 8014552:	68b9      	ldr	r1, [r7, #8]
 8014554:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8014556:	f000 fbb9 	bl	8014ccc <prvCopyDataToQueue>
 801455a:	62f8      	str	r0, [r7, #44]	@ 0x2c

					/* If there was a task waiting for data to arrive on the
					queue then unblock it now. */
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 801455c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801455e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8014560:	2b00      	cmp	r3, #0
 8014562:	d010      	beq.n	8014586 <xQueueGenericSend+0x112>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8014564:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014566:	3324      	adds	r3, #36	@ 0x24
 8014568:	4618      	mov	r0, r3
 801456a:	f001 fb7b 	bl	8015c64 <xTaskRemoveFromEventList>
 801456e:	4603      	mov	r3, r0
 8014570:	2b00      	cmp	r3, #0
 8014572:	d013      	beq.n	801459c <xQueueGenericSend+0x128>
						{
							/* The unblocked task has a priority higher than
							our own so yield immediately.  Yes it is ok to do
							this from within the critical section - the kernel
							takes care of that. */
							queueYIELD_IF_USING_PREEMPTION();
 8014574:	4b3f      	ldr	r3, [pc, #252]	@ (8014674 <xQueueGenericSend+0x200>)
 8014576:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 801457a:	601a      	str	r2, [r3, #0]
 801457c:	f3bf 8f4f 	dsb	sy
 8014580:	f3bf 8f6f 	isb	sy
 8014584:	e00a      	b.n	801459c <xQueueGenericSend+0x128>
						else
						{
							mtCOVERAGE_TEST_MARKER();
						}
					}
					else if( xYieldRequired != pdFALSE )
 8014586:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014588:	2b00      	cmp	r3, #0
 801458a:	d007      	beq.n	801459c <xQueueGenericSend+0x128>
					{
						/* This path is a special case that will only get
						executed if the task was holding multiple mutexes and
						the mutexes were given back in an order that is
						different to that in which they were taken. */
						queueYIELD_IF_USING_PREEMPTION();
 801458c:	4b39      	ldr	r3, [pc, #228]	@ (8014674 <xQueueGenericSend+0x200>)
 801458e:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8014592:	601a      	str	r2, [r3, #0]
 8014594:	f3bf 8f4f 	dsb	sy
 8014598:	f3bf 8f6f 	isb	sy
						mtCOVERAGE_TEST_MARKER();
					}
				}
				#endif /* configUSE_QUEUE_SETS */

				taskEXIT_CRITICAL();
 801459c:	f002 ff16 	bl	80173cc <vPortExitCritical>
				return pdPASS;
 80145a0:	2301      	movs	r3, #1
 80145a2:	e063      	b.n	801466c <xQueueGenericSend+0x1f8>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 80145a4:	687b      	ldr	r3, [r7, #4]
 80145a6:	2b00      	cmp	r3, #0
 80145a8:	d103      	bne.n	80145b2 <xQueueGenericSend+0x13e>
				{
					/* The queue was full and no block time is specified (or
					the block time has expired) so leave now. */
					taskEXIT_CRITICAL();
 80145aa:	f002 ff0f 	bl	80173cc <vPortExitCritical>

					/* Return to the original privilege level before exiting
					the function. */
					traceQUEUE_SEND_FAILED( pxQueue );
					return errQUEUE_FULL;
 80145ae:	2300      	movs	r3, #0
 80145b0:	e05c      	b.n	801466c <xQueueGenericSend+0x1f8>
				}
				else if( xEntryTimeSet == pdFALSE )
 80145b2:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80145b4:	2b00      	cmp	r3, #0
 80145b6:	d106      	bne.n	80145c6 <xQueueGenericSend+0x152>
				{
					/* The queue was full and a block time was specified so
					configure the timeout structure. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 80145b8:	f107 0314 	add.w	r3, r7, #20
 80145bc:	4618      	mov	r0, r3
 80145be:	f001 fbdd 	bl	8015d7c <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 80145c2:	2301      	movs	r3, #1
 80145c4:	637b      	str	r3, [r7, #52]	@ 0x34
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 80145c6:	f002 ff01 	bl	80173cc <vPortExitCritical>

		/* Interrupts and other tasks can send to and receive from the queue
		now the critical section has been exited. */

		vTaskSuspendAll();
 80145ca:	f001 f90f 	bl	80157ec <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 80145ce:	f002 fecb 	bl	8017368 <vPortEnterCritical>
 80145d2:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80145d4:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 80145d8:	b25b      	sxtb	r3, r3
 80145da:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80145de:	d103      	bne.n	80145e8 <xQueueGenericSend+0x174>
 80145e0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80145e2:	2200      	movs	r2, #0
 80145e4:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 80145e8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80145ea:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 80145ee:	b25b      	sxtb	r3, r3
 80145f0:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80145f4:	d103      	bne.n	80145fe <xQueueGenericSend+0x18a>
 80145f6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80145f8:	2200      	movs	r2, #0
 80145fa:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 80145fe:	f002 fee5 	bl	80173cc <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 8014602:	1d3a      	adds	r2, r7, #4
 8014604:	f107 0314 	add.w	r3, r7, #20
 8014608:	4611      	mov	r1, r2
 801460a:	4618      	mov	r0, r3
 801460c:	f001 fbcc 	bl	8015da8 <xTaskCheckForTimeOut>
 8014610:	4603      	mov	r3, r0
 8014612:	2b00      	cmp	r3, #0
 8014614:	d124      	bne.n	8014660 <xQueueGenericSend+0x1ec>
		{
			if( prvIsQueueFull( pxQueue ) != pdFALSE )
 8014616:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8014618:	f000 fc50 	bl	8014ebc <prvIsQueueFull>
 801461c:	4603      	mov	r3, r0
 801461e:	2b00      	cmp	r3, #0
 8014620:	d018      	beq.n	8014654 <xQueueGenericSend+0x1e0>
			{
				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
 8014622:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014624:	3310      	adds	r3, #16
 8014626:	687a      	ldr	r2, [r7, #4]
 8014628:	4611      	mov	r1, r2
 801462a:	4618      	mov	r0, r3
 801462c:	f001 fac8 	bl	8015bc0 <vTaskPlaceOnEventList>
				/* Unlocking the queue means queue events can effect the
				event list.  It is possible that interrupts occurring now
				remove this task from the event list again - but as the
				scheduler is suspended the task will go onto the pending
				ready last instead of the actual ready list. */
				prvUnlockQueue( pxQueue );
 8014630:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8014632:	f000 fbdb 	bl	8014dec <prvUnlockQueue>
				/* Resuming the scheduler will move tasks from the pending
				ready list into the ready list - so it is feasible that this
				task is already in a ready list before it yields - in which
				case the yield will not cause a context switch unless there
				is also a higher priority task in the pending ready list. */
				if( xTaskResumeAll() == pdFALSE )
 8014636:	f001 f8e7 	bl	8015808 <xTaskResumeAll>
 801463a:	4603      	mov	r3, r0
 801463c:	2b00      	cmp	r3, #0
 801463e:	f47f af7c 	bne.w	801453a <xQueueGenericSend+0xc6>
				{
					portYIELD_WITHIN_API();
 8014642:	4b0c      	ldr	r3, [pc, #48]	@ (8014674 <xQueueGenericSend+0x200>)
 8014644:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8014648:	601a      	str	r2, [r3, #0]
 801464a:	f3bf 8f4f 	dsb	sy
 801464e:	f3bf 8f6f 	isb	sy
 8014652:	e772      	b.n	801453a <xQueueGenericSend+0xc6>
				}
			}
			else
			{
				/* Try again. */
				prvUnlockQueue( pxQueue );
 8014654:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8014656:	f000 fbc9 	bl	8014dec <prvUnlockQueue>
				( void ) xTaskResumeAll();
 801465a:	f001 f8d5 	bl	8015808 <xTaskResumeAll>
 801465e:	e76c      	b.n	801453a <xQueueGenericSend+0xc6>
			}
		}
		else
		{
			/* The timeout has expired. */
			prvUnlockQueue( pxQueue );
 8014660:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8014662:	f000 fbc3 	bl	8014dec <prvUnlockQueue>
			( void ) xTaskResumeAll();
 8014666:	f001 f8cf 	bl	8015808 <xTaskResumeAll>

			traceQUEUE_SEND_FAILED( pxQueue );
			return errQUEUE_FULL;
 801466a:	2300      	movs	r3, #0
		}
	} /*lint -restore */
}
 801466c:	4618      	mov	r0, r3
 801466e:	3738      	adds	r7, #56	@ 0x38
 8014670:	46bd      	mov	sp, r7
 8014672:	bd80      	pop	{r7, pc}
 8014674:	e000ed04 	.word	0xe000ed04

08014678 <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
 8014678:	b580      	push	{r7, lr}
 801467a:	b090      	sub	sp, #64	@ 0x40
 801467c:	af00      	add	r7, sp, #0
 801467e:	60f8      	str	r0, [r7, #12]
 8014680:	60b9      	str	r1, [r7, #8]
 8014682:	607a      	str	r2, [r7, #4]
 8014684:	603b      	str	r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
 8014686:	68fb      	ldr	r3, [r7, #12]
 8014688:	63bb      	str	r3, [r7, #56]	@ 0x38

	configASSERT( pxQueue );
 801468a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 801468c:	2b00      	cmp	r3, #0
 801468e:	d10b      	bne.n	80146a8 <xQueueGenericSendFromISR+0x30>
	__asm volatile
 8014690:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014694:	f383 8811 	msr	BASEPRI, r3
 8014698:	f3bf 8f6f 	isb	sy
 801469c:	f3bf 8f4f 	dsb	sy
 80146a0:	62bb      	str	r3, [r7, #40]	@ 0x28
}
 80146a2:	bf00      	nop
 80146a4:	bf00      	nop
 80146a6:	e7fd      	b.n	80146a4 <xQueueGenericSendFromISR+0x2c>
	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 80146a8:	68bb      	ldr	r3, [r7, #8]
 80146aa:	2b00      	cmp	r3, #0
 80146ac:	d103      	bne.n	80146b6 <xQueueGenericSendFromISR+0x3e>
 80146ae:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80146b0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80146b2:	2b00      	cmp	r3, #0
 80146b4:	d101      	bne.n	80146ba <xQueueGenericSendFromISR+0x42>
 80146b6:	2301      	movs	r3, #1
 80146b8:	e000      	b.n	80146bc <xQueueGenericSendFromISR+0x44>
 80146ba:	2300      	movs	r3, #0
 80146bc:	2b00      	cmp	r3, #0
 80146be:	d10b      	bne.n	80146d8 <xQueueGenericSendFromISR+0x60>
	__asm volatile
 80146c0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80146c4:	f383 8811 	msr	BASEPRI, r3
 80146c8:	f3bf 8f6f 	isb	sy
 80146cc:	f3bf 8f4f 	dsb	sy
 80146d0:	627b      	str	r3, [r7, #36]	@ 0x24
}
 80146d2:	bf00      	nop
 80146d4:	bf00      	nop
 80146d6:	e7fd      	b.n	80146d4 <xQueueGenericSendFromISR+0x5c>
	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 80146d8:	683b      	ldr	r3, [r7, #0]
 80146da:	2b02      	cmp	r3, #2
 80146dc:	d103      	bne.n	80146e6 <xQueueGenericSendFromISR+0x6e>
 80146de:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80146e0:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 80146e2:	2b01      	cmp	r3, #1
 80146e4:	d101      	bne.n	80146ea <xQueueGenericSendFromISR+0x72>
 80146e6:	2301      	movs	r3, #1
 80146e8:	e000      	b.n	80146ec <xQueueGenericSendFromISR+0x74>
 80146ea:	2300      	movs	r3, #0
 80146ec:	2b00      	cmp	r3, #0
 80146ee:	d10b      	bne.n	8014708 <xQueueGenericSendFromISR+0x90>
	__asm volatile
 80146f0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80146f4:	f383 8811 	msr	BASEPRI, r3
 80146f8:	f3bf 8f6f 	isb	sy
 80146fc:	f3bf 8f4f 	dsb	sy
 8014700:	623b      	str	r3, [r7, #32]
}
 8014702:	bf00      	nop
 8014704:	bf00      	nop
 8014706:	e7fd      	b.n	8014704 <xQueueGenericSendFromISR+0x8c>
	that have been assigned a priority at or (logically) below the maximum
	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
	safe API to ensure interrupt entry is as fast and as simple as possible.
	More information (albeit Cortex-M specific) is provided on the following
	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 8014708:	f002 ff0e 	bl	8017528 <vPortValidateInterruptPriority>

portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;

	__asm volatile
 801470c:	f3ef 8211 	mrs	r2, BASEPRI
 8014710:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014714:	f383 8811 	msr	BASEPRI, r3
 8014718:	f3bf 8f6f 	isb	sy
 801471c:	f3bf 8f4f 	dsb	sy
 8014720:	61fa      	str	r2, [r7, #28]
 8014722:	61bb      	str	r3, [r7, #24]
		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
	);

	/* This return will not be reached but is necessary to prevent compiler
	warnings. */
	return ulOriginalBASEPRI;
 8014724:	69fb      	ldr	r3, [r7, #28]
	/* Similar to xQueueGenericSend, except without blocking if there is no room
	in the queue.  Also don't directly wake a task that was blocked on a queue
	read, instead return a flag to say whether a context switch is required or
	not (i.e. has a task with a higher priority than us been woken by this
	post). */
	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 8014726:	637b      	str	r3, [r7, #52]	@ 0x34
	{
		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 8014728:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 801472a:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 801472c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 801472e:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8014730:	429a      	cmp	r2, r3
 8014732:	d302      	bcc.n	801473a <xQueueGenericSendFromISR+0xc2>
 8014734:	683b      	ldr	r3, [r7, #0]
 8014736:	2b02      	cmp	r3, #2
 8014738:	d12f      	bne.n	801479a <xQueueGenericSendFromISR+0x122>
		{
			const int8_t cTxLock = pxQueue->cTxLock;
 801473a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 801473c:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8014740:	f887 3033 	strb.w	r3, [r7, #51]	@ 0x33
			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
 8014744:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8014746:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8014748:	62fb      	str	r3, [r7, #44]	@ 0x2c
			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
			in a task disinheriting a priority and prvCopyDataToQueue() can be
			called here even though the disinherit function does not check if
			the scheduler is suspended before accessing the ready lists. */
			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 801474a:	683a      	ldr	r2, [r7, #0]
 801474c:	68b9      	ldr	r1, [r7, #8]
 801474e:	6bb8      	ldr	r0, [r7, #56]	@ 0x38
 8014750:	f000 fabc 	bl	8014ccc <prvCopyDataToQueue>

			/* The event list is not altered if the queue is locked.  This will
			be done when the queue is unlocked later. */
			if( cTxLock == queueUNLOCKED )
 8014754:	f997 3033 	ldrsb.w	r3, [r7, #51]	@ 0x33
 8014758:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 801475c:	d112      	bne.n	8014784 <xQueueGenericSendFromISR+0x10c>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 801475e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8014760:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8014762:	2b00      	cmp	r3, #0
 8014764:	d016      	beq.n	8014794 <xQueueGenericSendFromISR+0x11c>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8014766:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8014768:	3324      	adds	r3, #36	@ 0x24
 801476a:	4618      	mov	r0, r3
 801476c:	f001 fa7a 	bl	8015c64 <xTaskRemoveFromEventList>
 8014770:	4603      	mov	r3, r0
 8014772:	2b00      	cmp	r3, #0
 8014774:	d00e      	beq.n	8014794 <xQueueGenericSendFromISR+0x11c>
						{
							/* The task waiting has a higher priority so record that a
							context	switch is required. */
							if( pxHigherPriorityTaskWoken != NULL )
 8014776:	687b      	ldr	r3, [r7, #4]
 8014778:	2b00      	cmp	r3, #0
 801477a:	d00b      	beq.n	8014794 <xQueueGenericSendFromISR+0x11c>
							{
								*pxHigherPriorityTaskWoken = pdTRUE;
 801477c:	687b      	ldr	r3, [r7, #4]
 801477e:	2201      	movs	r2, #1
 8014780:	601a      	str	r2, [r3, #0]
 8014782:	e007      	b.n	8014794 <xQueueGenericSendFromISR+0x11c>
			}
			else
			{
				/* Increment the lock count so the task that unlocks the queue
				knows that data was posted while it was locked. */
				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
 8014784:	f897 3033 	ldrb.w	r3, [r7, #51]	@ 0x33
 8014788:	3301      	adds	r3, #1
 801478a:	b2db      	uxtb	r3, r3
 801478c:	b25a      	sxtb	r2, r3
 801478e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8014790:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
			}

			xReturn = pdPASS;
 8014794:	2301      	movs	r3, #1
 8014796:	63fb      	str	r3, [r7, #60]	@ 0x3c
		{
 8014798:	e001      	b.n	801479e <xQueueGenericSendFromISR+0x126>
		}
		else
		{
			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
			xReturn = errQUEUE_FULL;
 801479a:	2300      	movs	r3, #0
 801479c:	63fb      	str	r3, [r7, #60]	@ 0x3c
 801479e:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 80147a0:	617b      	str	r3, [r7, #20]
}
/*-----------------------------------------------------------*/

portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
	__asm volatile
 80147a2:	697b      	ldr	r3, [r7, #20]
 80147a4:	f383 8811 	msr	BASEPRI, r3
	(
		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
	);
}
 80147a8:	bf00      	nop
		}
	}
	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

	return xReturn;
 80147aa:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
}
 80147ac:	4618      	mov	r0, r3
 80147ae:	3740      	adds	r7, #64	@ 0x40
 80147b0:	46bd      	mov	sp, r7
 80147b2:	bd80      	pop	{r7, pc}

080147b4 <xQueueReceive>:
	return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
 80147b4:	b580      	push	{r7, lr}
 80147b6:	b08c      	sub	sp, #48	@ 0x30
 80147b8:	af00      	add	r7, sp, #0
 80147ba:	60f8      	str	r0, [r7, #12]
 80147bc:	60b9      	str	r1, [r7, #8]
 80147be:	607a      	str	r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
 80147c0:	2300      	movs	r3, #0
 80147c2:	62fb      	str	r3, [r7, #44]	@ 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 80147c4:	68fb      	ldr	r3, [r7, #12]
 80147c6:	62bb      	str	r3, [r7, #40]	@ 0x28

	/* Check the pointer is not NULL. */
	configASSERT( ( pxQueue ) );
 80147c8:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80147ca:	2b00      	cmp	r3, #0
 80147cc:	d10b      	bne.n	80147e6 <xQueueReceive+0x32>
	__asm volatile
 80147ce:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80147d2:	f383 8811 	msr	BASEPRI, r3
 80147d6:	f3bf 8f6f 	isb	sy
 80147da:	f3bf 8f4f 	dsb	sy
 80147de:	623b      	str	r3, [r7, #32]
}
 80147e0:	bf00      	nop
 80147e2:	bf00      	nop
 80147e4:	e7fd      	b.n	80147e2 <xQueueReceive+0x2e>

	/* The buffer into which data is received can only be NULL if the data size
	is zero (so no data is copied into the buffer. */
	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
 80147e6:	68bb      	ldr	r3, [r7, #8]
 80147e8:	2b00      	cmp	r3, #0
 80147ea:	d103      	bne.n	80147f4 <xQueueReceive+0x40>
 80147ec:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80147ee:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80147f0:	2b00      	cmp	r3, #0
 80147f2:	d101      	bne.n	80147f8 <xQueueReceive+0x44>
 80147f4:	2301      	movs	r3, #1
 80147f6:	e000      	b.n	80147fa <xQueueReceive+0x46>
 80147f8:	2300      	movs	r3, #0
 80147fa:	2b00      	cmp	r3, #0
 80147fc:	d10b      	bne.n	8014816 <xQueueReceive+0x62>
	__asm volatile
 80147fe:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014802:	f383 8811 	msr	BASEPRI, r3
 8014806:	f3bf 8f6f 	isb	sy
 801480a:	f3bf 8f4f 	dsb	sy
 801480e:	61fb      	str	r3, [r7, #28]
}
 8014810:	bf00      	nop
 8014812:	bf00      	nop
 8014814:	e7fd      	b.n	8014812 <xQueueReceive+0x5e>

	/* Cannot block if the scheduler is suspended. */
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 8014816:	f001 fc23 	bl	8016060 <xTaskGetSchedulerState>
 801481a:	4603      	mov	r3, r0
 801481c:	2b00      	cmp	r3, #0
 801481e:	d102      	bne.n	8014826 <xQueueReceive+0x72>
 8014820:	687b      	ldr	r3, [r7, #4]
 8014822:	2b00      	cmp	r3, #0
 8014824:	d101      	bne.n	801482a <xQueueReceive+0x76>
 8014826:	2301      	movs	r3, #1
 8014828:	e000      	b.n	801482c <xQueueReceive+0x78>
 801482a:	2300      	movs	r3, #0
 801482c:	2b00      	cmp	r3, #0
 801482e:	d10b      	bne.n	8014848 <xQueueReceive+0x94>
	__asm volatile
 8014830:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014834:	f383 8811 	msr	BASEPRI, r3
 8014838:	f3bf 8f6f 	isb	sy
 801483c:	f3bf 8f4f 	dsb	sy
 8014840:	61bb      	str	r3, [r7, #24]
}
 8014842:	bf00      	nop
 8014844:	bf00      	nop
 8014846:	e7fd      	b.n	8014844 <xQueueReceive+0x90>
	/*lint -save -e904  This function relaxes the coding standard somewhat to
	allow return statements within the function itself.  This is done in the
	interest of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 8014848:	f002 fd8e 	bl	8017368 <vPortEnterCritical>
		{
			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 801484c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 801484e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8014850:	627b      	str	r3, [r7, #36]	@ 0x24

			/* Is there data in the queue now?  To be running the calling task
			must be the highest priority task wanting to access the queue. */
			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8014852:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8014854:	2b00      	cmp	r3, #0
 8014856:	d01f      	beq.n	8014898 <xQueueReceive+0xe4>
			{
				/* Data available, remove one item. */
				prvCopyDataFromQueue( pxQueue, pvBuffer );
 8014858:	68b9      	ldr	r1, [r7, #8]
 801485a:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 801485c:	f000 faa0 	bl	8014da0 <prvCopyDataFromQueue>
				traceQUEUE_RECEIVE( pxQueue );
				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
 8014860:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8014862:	1e5a      	subs	r2, r3, #1
 8014864:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8014866:	639a      	str	r2, [r3, #56]	@ 0x38

				/* There is now space in the queue, were any tasks waiting to
				post to the queue?  If so, unblock the highest priority waiting
				task. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8014868:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 801486a:	691b      	ldr	r3, [r3, #16]
 801486c:	2b00      	cmp	r3, #0
 801486e:	d00f      	beq.n	8014890 <xQueueReceive+0xdc>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8014870:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8014872:	3310      	adds	r3, #16
 8014874:	4618      	mov	r0, r3
 8014876:	f001 f9f5 	bl	8015c64 <xTaskRemoveFromEventList>
 801487a:	4603      	mov	r3, r0
 801487c:	2b00      	cmp	r3, #0
 801487e:	d007      	beq.n	8014890 <xQueueReceive+0xdc>
					{
						queueYIELD_IF_USING_PREEMPTION();
 8014880:	4b3c      	ldr	r3, [pc, #240]	@ (8014974 <xQueueReceive+0x1c0>)
 8014882:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8014886:	601a      	str	r2, [r3, #0]
 8014888:	f3bf 8f4f 	dsb	sy
 801488c:	f3bf 8f6f 	isb	sy
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				taskEXIT_CRITICAL();
 8014890:	f002 fd9c 	bl	80173cc <vPortExitCritical>
				return pdPASS;
 8014894:	2301      	movs	r3, #1
 8014896:	e069      	b.n	801496c <xQueueReceive+0x1b8>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 8014898:	687b      	ldr	r3, [r7, #4]
 801489a:	2b00      	cmp	r3, #0
 801489c:	d103      	bne.n	80148a6 <xQueueReceive+0xf2>
				{
					/* The queue was empty and no block time is specified (or
					the block time has expired) so leave now. */
					taskEXIT_CRITICAL();
 801489e:	f002 fd95 	bl	80173cc <vPortExitCritical>
					traceQUEUE_RECEIVE_FAILED( pxQueue );
					return errQUEUE_EMPTY;
 80148a2:	2300      	movs	r3, #0
 80148a4:	e062      	b.n	801496c <xQueueReceive+0x1b8>
				}
				else if( xEntryTimeSet == pdFALSE )
 80148a6:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80148a8:	2b00      	cmp	r3, #0
 80148aa:	d106      	bne.n	80148ba <xQueueReceive+0x106>
				{
					/* The queue was empty and a block time was specified so
					configure the timeout structure. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 80148ac:	f107 0310 	add.w	r3, r7, #16
 80148b0:	4618      	mov	r0, r3
 80148b2:	f001 fa63 	bl	8015d7c <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 80148b6:	2301      	movs	r3, #1
 80148b8:	62fb      	str	r3, [r7, #44]	@ 0x2c
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 80148ba:	f002 fd87 	bl	80173cc <vPortExitCritical>

		/* Interrupts and other tasks can send to and receive from the queue
		now the critical section has been exited. */

		vTaskSuspendAll();
 80148be:	f000 ff95 	bl	80157ec <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 80148c2:	f002 fd51 	bl	8017368 <vPortEnterCritical>
 80148c6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80148c8:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 80148cc:	b25b      	sxtb	r3, r3
 80148ce:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80148d2:	d103      	bne.n	80148dc <xQueueReceive+0x128>
 80148d4:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80148d6:	2200      	movs	r2, #0
 80148d8:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 80148dc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80148de:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 80148e2:	b25b      	sxtb	r3, r3
 80148e4:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80148e8:	d103      	bne.n	80148f2 <xQueueReceive+0x13e>
 80148ea:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80148ec:	2200      	movs	r2, #0
 80148ee:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 80148f2:	f002 fd6b 	bl	80173cc <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 80148f6:	1d3a      	adds	r2, r7, #4
 80148f8:	f107 0310 	add.w	r3, r7, #16
 80148fc:	4611      	mov	r1, r2
 80148fe:	4618      	mov	r0, r3
 8014900:	f001 fa52 	bl	8015da8 <xTaskCheckForTimeOut>
 8014904:	4603      	mov	r3, r0
 8014906:	2b00      	cmp	r3, #0
 8014908:	d123      	bne.n	8014952 <xQueueReceive+0x19e>
		{
			/* The timeout has not expired.  If the queue is still empty place
			the task on the list of tasks waiting to receive from the queue. */
			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 801490a:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 801490c:	f000 fac0 	bl	8014e90 <prvIsQueueEmpty>
 8014910:	4603      	mov	r3, r0
 8014912:	2b00      	cmp	r3, #0
 8014914:	d017      	beq.n	8014946 <xQueueReceive+0x192>
			{
				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
 8014916:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8014918:	3324      	adds	r3, #36	@ 0x24
 801491a:	687a      	ldr	r2, [r7, #4]
 801491c:	4611      	mov	r1, r2
 801491e:	4618      	mov	r0, r3
 8014920:	f001 f94e 	bl	8015bc0 <vTaskPlaceOnEventList>
				prvUnlockQueue( pxQueue );
 8014924:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8014926:	f000 fa61 	bl	8014dec <prvUnlockQueue>
				if( xTaskResumeAll() == pdFALSE )
 801492a:	f000 ff6d 	bl	8015808 <xTaskResumeAll>
 801492e:	4603      	mov	r3, r0
 8014930:	2b00      	cmp	r3, #0
 8014932:	d189      	bne.n	8014848 <xQueueReceive+0x94>
				{
					portYIELD_WITHIN_API();
 8014934:	4b0f      	ldr	r3, [pc, #60]	@ (8014974 <xQueueReceive+0x1c0>)
 8014936:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 801493a:	601a      	str	r2, [r3, #0]
 801493c:	f3bf 8f4f 	dsb	sy
 8014940:	f3bf 8f6f 	isb	sy
 8014944:	e780      	b.n	8014848 <xQueueReceive+0x94>
			}
			else
			{
				/* The queue contains data again.  Loop back to try and read the
				data. */
				prvUnlockQueue( pxQueue );
 8014946:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8014948:	f000 fa50 	bl	8014dec <prvUnlockQueue>
				( void ) xTaskResumeAll();
 801494c:	f000 ff5c 	bl	8015808 <xTaskResumeAll>
 8014950:	e77a      	b.n	8014848 <xQueueReceive+0x94>
		}
		else
		{
			/* Timed out.  If there is no data in the queue exit, otherwise loop
			back and attempt to read the data. */
			prvUnlockQueue( pxQueue );
 8014952:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8014954:	f000 fa4a 	bl	8014dec <prvUnlockQueue>
			( void ) xTaskResumeAll();
 8014958:	f000 ff56 	bl	8015808 <xTaskResumeAll>

			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 801495c:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 801495e:	f000 fa97 	bl	8014e90 <prvIsQueueEmpty>
 8014962:	4603      	mov	r3, r0
 8014964:	2b00      	cmp	r3, #0
 8014966:	f43f af6f 	beq.w	8014848 <xQueueReceive+0x94>
			{
				traceQUEUE_RECEIVE_FAILED( pxQueue );
				return errQUEUE_EMPTY;
 801496a:	2300      	movs	r3, #0
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	} /*lint -restore */
}
 801496c:	4618      	mov	r0, r3
 801496e:	3730      	adds	r7, #48	@ 0x30
 8014970:	46bd      	mov	sp, r7
 8014972:	bd80      	pop	{r7, pc}
 8014974:	e000ed04 	.word	0xe000ed04

08014978 <xQueueSemaphoreTake>:
/*-----------------------------------------------------------*/

BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
{
 8014978:	b580      	push	{r7, lr}
 801497a:	b08e      	sub	sp, #56	@ 0x38
 801497c:	af00      	add	r7, sp, #0
 801497e:	6078      	str	r0, [r7, #4]
 8014980:	6039      	str	r1, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE;
 8014982:	2300      	movs	r3, #0
 8014984:	637b      	str	r3, [r7, #52]	@ 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 8014986:	687b      	ldr	r3, [r7, #4]
 8014988:	62fb      	str	r3, [r7, #44]	@ 0x2c

#if( configUSE_MUTEXES == 1 )
	BaseType_t xInheritanceOccurred = pdFALSE;
 801498a:	2300      	movs	r3, #0
 801498c:	633b      	str	r3, [r7, #48]	@ 0x30
#endif

	/* Check the queue pointer is not NULL. */
	configASSERT( ( pxQueue ) );
 801498e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014990:	2b00      	cmp	r3, #0
 8014992:	d10b      	bne.n	80149ac <xQueueSemaphoreTake+0x34>
	__asm volatile
 8014994:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014998:	f383 8811 	msr	BASEPRI, r3
 801499c:	f3bf 8f6f 	isb	sy
 80149a0:	f3bf 8f4f 	dsb	sy
 80149a4:	623b      	str	r3, [r7, #32]
}
 80149a6:	bf00      	nop
 80149a8:	bf00      	nop
 80149aa:	e7fd      	b.n	80149a8 <xQueueSemaphoreTake+0x30>

	/* Check this really is a semaphore, in which case the item size will be
	0. */
	configASSERT( pxQueue->uxItemSize == 0 );
 80149ac:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80149ae:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 80149b0:	2b00      	cmp	r3, #0
 80149b2:	d00b      	beq.n	80149cc <xQueueSemaphoreTake+0x54>
	__asm volatile
 80149b4:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80149b8:	f383 8811 	msr	BASEPRI, r3
 80149bc:	f3bf 8f6f 	isb	sy
 80149c0:	f3bf 8f4f 	dsb	sy
 80149c4:	61fb      	str	r3, [r7, #28]
}
 80149c6:	bf00      	nop
 80149c8:	bf00      	nop
 80149ca:	e7fd      	b.n	80149c8 <xQueueSemaphoreTake+0x50>

	/* Cannot block if the scheduler is suspended. */
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 80149cc:	f001 fb48 	bl	8016060 <xTaskGetSchedulerState>
 80149d0:	4603      	mov	r3, r0
 80149d2:	2b00      	cmp	r3, #0
 80149d4:	d102      	bne.n	80149dc <xQueueSemaphoreTake+0x64>
 80149d6:	683b      	ldr	r3, [r7, #0]
 80149d8:	2b00      	cmp	r3, #0
 80149da:	d101      	bne.n	80149e0 <xQueueSemaphoreTake+0x68>
 80149dc:	2301      	movs	r3, #1
 80149de:	e000      	b.n	80149e2 <xQueueSemaphoreTake+0x6a>
 80149e0:	2300      	movs	r3, #0
 80149e2:	2b00      	cmp	r3, #0
 80149e4:	d10b      	bne.n	80149fe <xQueueSemaphoreTake+0x86>
	__asm volatile
 80149e6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80149ea:	f383 8811 	msr	BASEPRI, r3
 80149ee:	f3bf 8f6f 	isb	sy
 80149f2:	f3bf 8f4f 	dsb	sy
 80149f6:	61bb      	str	r3, [r7, #24]
}
 80149f8:	bf00      	nop
 80149fa:	bf00      	nop
 80149fc:	e7fd      	b.n	80149fa <xQueueSemaphoreTake+0x82>
	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
	statements within the function itself.  This is done in the interest
	of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 80149fe:	f002 fcb3 	bl	8017368 <vPortEnterCritical>
		{
			/* Semaphores are queues with an item size of 0, and where the
			number of messages in the queue is the semaphore's count value. */
			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
 8014a02:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014a04:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8014a06:	62bb      	str	r3, [r7, #40]	@ 0x28

			/* Is there data in the queue now?  To be running the calling task
			must be the highest priority task wanting to access the queue. */
			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
 8014a08:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8014a0a:	2b00      	cmp	r3, #0
 8014a0c:	d024      	beq.n	8014a58 <xQueueSemaphoreTake+0xe0>
			{
				traceQUEUE_RECEIVE( pxQueue );

				/* Semaphores are queues with a data size of zero and where the
				messages waiting is the semaphore's count.  Reduce the count. */
				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
 8014a0e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8014a10:	1e5a      	subs	r2, r3, #1
 8014a12:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014a14:	639a      	str	r2, [r3, #56]	@ 0x38

				#if ( configUSE_MUTEXES == 1 )
				{
					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 8014a16:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014a18:	681b      	ldr	r3, [r3, #0]
 8014a1a:	2b00      	cmp	r3, #0
 8014a1c:	d104      	bne.n	8014a28 <xQueueSemaphoreTake+0xb0>
					{
						/* Record the information required to implement
						priority inheritance should it become necessary. */
						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
 8014a1e:	f001 fc99 	bl	8016354 <pvTaskIncrementMutexHeldCount>
 8014a22:	4602      	mov	r2, r0
 8014a24:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014a26:	609a      	str	r2, [r3, #8]
				}
				#endif /* configUSE_MUTEXES */

				/* Check to see if other tasks are blocked waiting to give the
				semaphore, and if so, unblock the highest priority such task. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8014a28:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014a2a:	691b      	ldr	r3, [r3, #16]
 8014a2c:	2b00      	cmp	r3, #0
 8014a2e:	d00f      	beq.n	8014a50 <xQueueSemaphoreTake+0xd8>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8014a30:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014a32:	3310      	adds	r3, #16
 8014a34:	4618      	mov	r0, r3
 8014a36:	f001 f915 	bl	8015c64 <xTaskRemoveFromEventList>
 8014a3a:	4603      	mov	r3, r0
 8014a3c:	2b00      	cmp	r3, #0
 8014a3e:	d007      	beq.n	8014a50 <xQueueSemaphoreTake+0xd8>
					{
						queueYIELD_IF_USING_PREEMPTION();
 8014a40:	4b54      	ldr	r3, [pc, #336]	@ (8014b94 <xQueueSemaphoreTake+0x21c>)
 8014a42:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8014a46:	601a      	str	r2, [r3, #0]
 8014a48:	f3bf 8f4f 	dsb	sy
 8014a4c:	f3bf 8f6f 	isb	sy
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				taskEXIT_CRITICAL();
 8014a50:	f002 fcbc 	bl	80173cc <vPortExitCritical>
				return pdPASS;
 8014a54:	2301      	movs	r3, #1
 8014a56:	e098      	b.n	8014b8a <xQueueSemaphoreTake+0x212>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 8014a58:	683b      	ldr	r3, [r7, #0]
 8014a5a:	2b00      	cmp	r3, #0
 8014a5c:	d112      	bne.n	8014a84 <xQueueSemaphoreTake+0x10c>
					/* For inheritance to have occurred there must have been an
					initial timeout, and an adjusted timeout cannot become 0, as
					if it were 0 the function would have exited. */
					#if( configUSE_MUTEXES == 1 )
					{
						configASSERT( xInheritanceOccurred == pdFALSE );
 8014a5e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014a60:	2b00      	cmp	r3, #0
 8014a62:	d00b      	beq.n	8014a7c <xQueueSemaphoreTake+0x104>
	__asm volatile
 8014a64:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014a68:	f383 8811 	msr	BASEPRI, r3
 8014a6c:	f3bf 8f6f 	isb	sy
 8014a70:	f3bf 8f4f 	dsb	sy
 8014a74:	617b      	str	r3, [r7, #20]
}
 8014a76:	bf00      	nop
 8014a78:	bf00      	nop
 8014a7a:	e7fd      	b.n	8014a78 <xQueueSemaphoreTake+0x100>
					}
					#endif /* configUSE_MUTEXES */

					/* The semaphore count was 0 and no block time is specified
					(or the block time has expired) so exit now. */
					taskEXIT_CRITICAL();
 8014a7c:	f002 fca6 	bl	80173cc <vPortExitCritical>
					traceQUEUE_RECEIVE_FAILED( pxQueue );
					return errQUEUE_EMPTY;
 8014a80:	2300      	movs	r3, #0
 8014a82:	e082      	b.n	8014b8a <xQueueSemaphoreTake+0x212>
				}
				else if( xEntryTimeSet == pdFALSE )
 8014a84:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8014a86:	2b00      	cmp	r3, #0
 8014a88:	d106      	bne.n	8014a98 <xQueueSemaphoreTake+0x120>
				{
					/* The semaphore count was 0 and a block time was specified
					so configure the timeout structure ready to block. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 8014a8a:	f107 030c 	add.w	r3, r7, #12
 8014a8e:	4618      	mov	r0, r3
 8014a90:	f001 f974 	bl	8015d7c <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 8014a94:	2301      	movs	r3, #1
 8014a96:	637b      	str	r3, [r7, #52]	@ 0x34
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 8014a98:	f002 fc98 	bl	80173cc <vPortExitCritical>

		/* Interrupts and other tasks can give to and take from the semaphore
		now the critical section has been exited. */

		vTaskSuspendAll();
 8014a9c:	f000 fea6 	bl	80157ec <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 8014aa0:	f002 fc62 	bl	8017368 <vPortEnterCritical>
 8014aa4:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014aa6:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8014aaa:	b25b      	sxtb	r3, r3
 8014aac:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8014ab0:	d103      	bne.n	8014aba <xQueueSemaphoreTake+0x142>
 8014ab2:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014ab4:	2200      	movs	r2, #0
 8014ab6:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 8014aba:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014abc:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8014ac0:	b25b      	sxtb	r3, r3
 8014ac2:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8014ac6:	d103      	bne.n	8014ad0 <xQueueSemaphoreTake+0x158>
 8014ac8:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014aca:	2200      	movs	r2, #0
 8014acc:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 8014ad0:	f002 fc7c 	bl	80173cc <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 8014ad4:	463a      	mov	r2, r7
 8014ad6:	f107 030c 	add.w	r3, r7, #12
 8014ada:	4611      	mov	r1, r2
 8014adc:	4618      	mov	r0, r3
 8014ade:	f001 f963 	bl	8015da8 <xTaskCheckForTimeOut>
 8014ae2:	4603      	mov	r3, r0
 8014ae4:	2b00      	cmp	r3, #0
 8014ae6:	d132      	bne.n	8014b4e <xQueueSemaphoreTake+0x1d6>
		{
			/* A block time is specified and not expired.  If the semaphore
			count is 0 then enter the Blocked state to wait for a semaphore to
			become available.  As semaphores are implemented with queues the
			queue being empty is equivalent to the semaphore count being 0. */
			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 8014ae8:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8014aea:	f000 f9d1 	bl	8014e90 <prvIsQueueEmpty>
 8014aee:	4603      	mov	r3, r0
 8014af0:	2b00      	cmp	r3, #0
 8014af2:	d026      	beq.n	8014b42 <xQueueSemaphoreTake+0x1ca>
			{
				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );

				#if ( configUSE_MUTEXES == 1 )
				{
					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 8014af4:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014af6:	681b      	ldr	r3, [r3, #0]
 8014af8:	2b00      	cmp	r3, #0
 8014afa:	d109      	bne.n	8014b10 <xQueueSemaphoreTake+0x198>
					{
						taskENTER_CRITICAL();
 8014afc:	f002 fc34 	bl	8017368 <vPortEnterCritical>
						{
							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
 8014b00:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014b02:	689b      	ldr	r3, [r3, #8]
 8014b04:	4618      	mov	r0, r3
 8014b06:	f001 fac9 	bl	801609c <xTaskPriorityInherit>
 8014b0a:	6338      	str	r0, [r7, #48]	@ 0x30
						}
						taskEXIT_CRITICAL();
 8014b0c:	f002 fc5e 	bl	80173cc <vPortExitCritical>
						mtCOVERAGE_TEST_MARKER();
					}
				}
				#endif

				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
 8014b10:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014b12:	3324      	adds	r3, #36	@ 0x24
 8014b14:	683a      	ldr	r2, [r7, #0]
 8014b16:	4611      	mov	r1, r2
 8014b18:	4618      	mov	r0, r3
 8014b1a:	f001 f851 	bl	8015bc0 <vTaskPlaceOnEventList>
				prvUnlockQueue( pxQueue );
 8014b1e:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8014b20:	f000 f964 	bl	8014dec <prvUnlockQueue>
				if( xTaskResumeAll() == pdFALSE )
 8014b24:	f000 fe70 	bl	8015808 <xTaskResumeAll>
 8014b28:	4603      	mov	r3, r0
 8014b2a:	2b00      	cmp	r3, #0
 8014b2c:	f47f af67 	bne.w	80149fe <xQueueSemaphoreTake+0x86>
				{
					portYIELD_WITHIN_API();
 8014b30:	4b18      	ldr	r3, [pc, #96]	@ (8014b94 <xQueueSemaphoreTake+0x21c>)
 8014b32:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8014b36:	601a      	str	r2, [r3, #0]
 8014b38:	f3bf 8f4f 	dsb	sy
 8014b3c:	f3bf 8f6f 	isb	sy
 8014b40:	e75d      	b.n	80149fe <xQueueSemaphoreTake+0x86>
			}
			else
			{
				/* There was no timeout and the semaphore count was not 0, so
				attempt to take the semaphore again. */
				prvUnlockQueue( pxQueue );
 8014b42:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8014b44:	f000 f952 	bl	8014dec <prvUnlockQueue>
				( void ) xTaskResumeAll();
 8014b48:	f000 fe5e 	bl	8015808 <xTaskResumeAll>
 8014b4c:	e757      	b.n	80149fe <xQueueSemaphoreTake+0x86>
			}
		}
		else
		{
			/* Timed out. */
			prvUnlockQueue( pxQueue );
 8014b4e:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8014b50:	f000 f94c 	bl	8014dec <prvUnlockQueue>
			( void ) xTaskResumeAll();
 8014b54:	f000 fe58 	bl	8015808 <xTaskResumeAll>

			/* If the semaphore count is 0 exit now as the timeout has
			expired.  Otherwise return to attempt to take the semaphore that is
			known to be available.  As semaphores are implemented by queues the
			queue being empty is equivalent to the semaphore count being 0. */
			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 8014b58:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8014b5a:	f000 f999 	bl	8014e90 <prvIsQueueEmpty>
 8014b5e:	4603      	mov	r3, r0
 8014b60:	2b00      	cmp	r3, #0
 8014b62:	f43f af4c 	beq.w	80149fe <xQueueSemaphoreTake+0x86>
				#if ( configUSE_MUTEXES == 1 )
				{
					/* xInheritanceOccurred could only have be set if
					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
					test the mutex type again to check it is actually a mutex. */
					if( xInheritanceOccurred != pdFALSE )
 8014b66:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014b68:	2b00      	cmp	r3, #0
 8014b6a:	d00d      	beq.n	8014b88 <xQueueSemaphoreTake+0x210>
					{
						taskENTER_CRITICAL();
 8014b6c:	f002 fbfc 	bl	8017368 <vPortEnterCritical>
							/* This task blocking on the mutex caused another
							task to inherit this task's priority.  Now this task
							has timed out the priority should be disinherited
							again, but only as low as the next highest priority
							task that is waiting for the same mutex. */
							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
 8014b70:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8014b72:	f000 f893 	bl	8014c9c <prvGetDisinheritPriorityAfterTimeout>
 8014b76:	6278      	str	r0, [r7, #36]	@ 0x24
							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
 8014b78:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014b7a:	689b      	ldr	r3, [r3, #8]
 8014b7c:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 8014b7e:	4618      	mov	r0, r3
 8014b80:	f001 fb64 	bl	801624c <vTaskPriorityDisinheritAfterTimeout>
						}
						taskEXIT_CRITICAL();
 8014b84:	f002 fc22 	bl	80173cc <vPortExitCritical>
					}
				}
				#endif /* configUSE_MUTEXES */

				traceQUEUE_RECEIVE_FAILED( pxQueue );
				return errQUEUE_EMPTY;
 8014b88:	2300      	movs	r3, #0
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	} /*lint -restore */
}
 8014b8a:	4618      	mov	r0, r3
 8014b8c:	3738      	adds	r7, #56	@ 0x38
 8014b8e:	46bd      	mov	sp, r7
 8014b90:	bd80      	pop	{r7, pc}
 8014b92:	bf00      	nop
 8014b94:	e000ed04 	.word	0xe000ed04

08014b98 <xQueueReceiveFromISR>:
	} /*lint -restore */
}
/*-----------------------------------------------------------*/

BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
{
 8014b98:	b580      	push	{r7, lr}
 8014b9a:	b08e      	sub	sp, #56	@ 0x38
 8014b9c:	af00      	add	r7, sp, #0
 8014b9e:	60f8      	str	r0, [r7, #12]
 8014ba0:	60b9      	str	r1, [r7, #8]
 8014ba2:	607a      	str	r2, [r7, #4]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
 8014ba4:	68fb      	ldr	r3, [r7, #12]
 8014ba6:	633b      	str	r3, [r7, #48]	@ 0x30

	configASSERT( pxQueue );
 8014ba8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014baa:	2b00      	cmp	r3, #0
 8014bac:	d10b      	bne.n	8014bc6 <xQueueReceiveFromISR+0x2e>
	__asm volatile
 8014bae:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014bb2:	f383 8811 	msr	BASEPRI, r3
 8014bb6:	f3bf 8f6f 	isb	sy
 8014bba:	f3bf 8f4f 	dsb	sy
 8014bbe:	623b      	str	r3, [r7, #32]
}
 8014bc0:	bf00      	nop
 8014bc2:	bf00      	nop
 8014bc4:	e7fd      	b.n	8014bc2 <xQueueReceiveFromISR+0x2a>
	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 8014bc6:	68bb      	ldr	r3, [r7, #8]
 8014bc8:	2b00      	cmp	r3, #0
 8014bca:	d103      	bne.n	8014bd4 <xQueueReceiveFromISR+0x3c>
 8014bcc:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014bce:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8014bd0:	2b00      	cmp	r3, #0
 8014bd2:	d101      	bne.n	8014bd8 <xQueueReceiveFromISR+0x40>
 8014bd4:	2301      	movs	r3, #1
 8014bd6:	e000      	b.n	8014bda <xQueueReceiveFromISR+0x42>
 8014bd8:	2300      	movs	r3, #0
 8014bda:	2b00      	cmp	r3, #0
 8014bdc:	d10b      	bne.n	8014bf6 <xQueueReceiveFromISR+0x5e>
	__asm volatile
 8014bde:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014be2:	f383 8811 	msr	BASEPRI, r3
 8014be6:	f3bf 8f6f 	isb	sy
 8014bea:	f3bf 8f4f 	dsb	sy
 8014bee:	61fb      	str	r3, [r7, #28]
}
 8014bf0:	bf00      	nop
 8014bf2:	bf00      	nop
 8014bf4:	e7fd      	b.n	8014bf2 <xQueueReceiveFromISR+0x5a>
	that have been assigned a priority at or (logically) below the maximum
	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
	safe API to ensure interrupt entry is as fast and as simple as possible.
	More information (albeit Cortex-M specific) is provided on the following
	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 8014bf6:	f002 fc97 	bl	8017528 <vPortValidateInterruptPriority>
	__asm volatile
 8014bfa:	f3ef 8211 	mrs	r2, BASEPRI
 8014bfe:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014c02:	f383 8811 	msr	BASEPRI, r3
 8014c06:	f3bf 8f6f 	isb	sy
 8014c0a:	f3bf 8f4f 	dsb	sy
 8014c0e:	61ba      	str	r2, [r7, #24]
 8014c10:	617b      	str	r3, [r7, #20]
	return ulOriginalBASEPRI;
 8014c12:	69bb      	ldr	r3, [r7, #24]

	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 8014c14:	62fb      	str	r3, [r7, #44]	@ 0x2c
	{
		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 8014c16:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014c18:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8014c1a:	62bb      	str	r3, [r7, #40]	@ 0x28

		/* Cannot block in an ISR, so check there is data available. */
		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8014c1c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8014c1e:	2b00      	cmp	r3, #0
 8014c20:	d02f      	beq.n	8014c82 <xQueueReceiveFromISR+0xea>
		{
			const int8_t cRxLock = pxQueue->cRxLock;
 8014c22:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014c24:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8014c28:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27

			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );

			prvCopyDataFromQueue( pxQueue, pvBuffer );
 8014c2c:	68b9      	ldr	r1, [r7, #8]
 8014c2e:	6b38      	ldr	r0, [r7, #48]	@ 0x30
 8014c30:	f000 f8b6 	bl	8014da0 <prvCopyDataFromQueue>
			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
 8014c34:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8014c36:	1e5a      	subs	r2, r3, #1
 8014c38:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014c3a:	639a      	str	r2, [r3, #56]	@ 0x38

			/* If the queue is locked the event list will not be modified.
			Instead update the lock count so the task that unlocks the queue
			will know that an ISR has removed data while the queue was
			locked. */
			if( cRxLock == queueUNLOCKED )
 8014c3c:	f997 3027 	ldrsb.w	r3, [r7, #39]	@ 0x27
 8014c40:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8014c44:	d112      	bne.n	8014c6c <xQueueReceiveFromISR+0xd4>
			{
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8014c46:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014c48:	691b      	ldr	r3, [r3, #16]
 8014c4a:	2b00      	cmp	r3, #0
 8014c4c:	d016      	beq.n	8014c7c <xQueueReceiveFromISR+0xe4>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8014c4e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014c50:	3310      	adds	r3, #16
 8014c52:	4618      	mov	r0, r3
 8014c54:	f001 f806 	bl	8015c64 <xTaskRemoveFromEventList>
 8014c58:	4603      	mov	r3, r0
 8014c5a:	2b00      	cmp	r3, #0
 8014c5c:	d00e      	beq.n	8014c7c <xQueueReceiveFromISR+0xe4>
					{
						/* The task waiting has a higher priority than us so
						force a context switch. */
						if( pxHigherPriorityTaskWoken != NULL )
 8014c5e:	687b      	ldr	r3, [r7, #4]
 8014c60:	2b00      	cmp	r3, #0
 8014c62:	d00b      	beq.n	8014c7c <xQueueReceiveFromISR+0xe4>
						{
							*pxHigherPriorityTaskWoken = pdTRUE;
 8014c64:	687b      	ldr	r3, [r7, #4]
 8014c66:	2201      	movs	r2, #1
 8014c68:	601a      	str	r2, [r3, #0]
 8014c6a:	e007      	b.n	8014c7c <xQueueReceiveFromISR+0xe4>
			}
			else
			{
				/* Increment the lock count so the task that unlocks the queue
				knows that data was removed while it was locked. */
				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
 8014c6c:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 8014c70:	3301      	adds	r3, #1
 8014c72:	b2db      	uxtb	r3, r3
 8014c74:	b25a      	sxtb	r2, r3
 8014c76:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8014c78:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
			}

			xReturn = pdPASS;
 8014c7c:	2301      	movs	r3, #1
 8014c7e:	637b      	str	r3, [r7, #52]	@ 0x34
 8014c80:	e001      	b.n	8014c86 <xQueueReceiveFromISR+0xee>
		}
		else
		{
			xReturn = pdFAIL;
 8014c82:	2300      	movs	r3, #0
 8014c84:	637b      	str	r3, [r7, #52]	@ 0x34
 8014c86:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8014c88:	613b      	str	r3, [r7, #16]
	__asm volatile
 8014c8a:	693b      	ldr	r3, [r7, #16]
 8014c8c:	f383 8811 	msr	BASEPRI, r3
}
 8014c90:	bf00      	nop
			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
		}
	}
	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

	return xReturn;
 8014c92:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
}
 8014c94:	4618      	mov	r0, r3
 8014c96:	3738      	adds	r7, #56	@ 0x38
 8014c98:	46bd      	mov	sp, r7
 8014c9a:	bd80      	pop	{r7, pc}

08014c9c <prvGetDisinheritPriorityAfterTimeout>:
/*-----------------------------------------------------------*/

#if( configUSE_MUTEXES == 1 )

	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
	{
 8014c9c:	b480      	push	{r7}
 8014c9e:	b085      	sub	sp, #20
 8014ca0:	af00      	add	r7, sp, #0
 8014ca2:	6078      	str	r0, [r7, #4]
		priority, but the waiting task times out, then the holder should
		disinherit the priority - but only down to the highest priority of any
		other tasks that are waiting for the same mutex.  For this purpose,
		return the priority of the highest priority task that is waiting for the
		mutex. */
		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
 8014ca4:	687b      	ldr	r3, [r7, #4]
 8014ca6:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8014ca8:	2b00      	cmp	r3, #0
 8014caa:	d006      	beq.n	8014cba <prvGetDisinheritPriorityAfterTimeout+0x1e>
		{
			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
 8014cac:	687b      	ldr	r3, [r7, #4]
 8014cae:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8014cb0:	681b      	ldr	r3, [r3, #0]
 8014cb2:	f1c3 0338 	rsb	r3, r3, #56	@ 0x38
 8014cb6:	60fb      	str	r3, [r7, #12]
 8014cb8:	e001      	b.n	8014cbe <prvGetDisinheritPriorityAfterTimeout+0x22>
		}
		else
		{
			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
 8014cba:	2300      	movs	r3, #0
 8014cbc:	60fb      	str	r3, [r7, #12]
		}

		return uxHighestPriorityOfWaitingTasks;
 8014cbe:	68fb      	ldr	r3, [r7, #12]
	}
 8014cc0:	4618      	mov	r0, r3
 8014cc2:	3714      	adds	r7, #20
 8014cc4:	46bd      	mov	sp, r7
 8014cc6:	f85d 7b04 	ldr.w	r7, [sp], #4
 8014cca:	4770      	bx	lr

08014ccc <prvCopyDataToQueue>:

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
 8014ccc:	b580      	push	{r7, lr}
 8014cce:	b086      	sub	sp, #24
 8014cd0:	af00      	add	r7, sp, #0
 8014cd2:	60f8      	str	r0, [r7, #12]
 8014cd4:	60b9      	str	r1, [r7, #8]
 8014cd6:	607a      	str	r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
 8014cd8:	2300      	movs	r3, #0
 8014cda:	617b      	str	r3, [r7, #20]
UBaseType_t uxMessagesWaiting;

	/* This function is called from a critical section. */

	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 8014cdc:	68fb      	ldr	r3, [r7, #12]
 8014cde:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8014ce0:	613b      	str	r3, [r7, #16]

	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
 8014ce2:	68fb      	ldr	r3, [r7, #12]
 8014ce4:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8014ce6:	2b00      	cmp	r3, #0
 8014ce8:	d10d      	bne.n	8014d06 <prvCopyDataToQueue+0x3a>
	{
		#if ( configUSE_MUTEXES == 1 )
		{
			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 8014cea:	68fb      	ldr	r3, [r7, #12]
 8014cec:	681b      	ldr	r3, [r3, #0]
 8014cee:	2b00      	cmp	r3, #0
 8014cf0:	d14d      	bne.n	8014d8e <prvCopyDataToQueue+0xc2>
			{
				/* The mutex is no longer being held. */
				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
 8014cf2:	68fb      	ldr	r3, [r7, #12]
 8014cf4:	689b      	ldr	r3, [r3, #8]
 8014cf6:	4618      	mov	r0, r3
 8014cf8:	f001 fa38 	bl	801616c <xTaskPriorityDisinherit>
 8014cfc:	6178      	str	r0, [r7, #20]
				pxQueue->u.xSemaphore.xMutexHolder = NULL;
 8014cfe:	68fb      	ldr	r3, [r7, #12]
 8014d00:	2200      	movs	r2, #0
 8014d02:	609a      	str	r2, [r3, #8]
 8014d04:	e043      	b.n	8014d8e <prvCopyDataToQueue+0xc2>
				mtCOVERAGE_TEST_MARKER();
			}
		}
		#endif /* configUSE_MUTEXES */
	}
	else if( xPosition == queueSEND_TO_BACK )
 8014d06:	687b      	ldr	r3, [r7, #4]
 8014d08:	2b00      	cmp	r3, #0
 8014d0a:	d119      	bne.n	8014d40 <prvCopyDataToQueue+0x74>
	{
		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 8014d0c:	68fb      	ldr	r3, [r7, #12]
 8014d0e:	6858      	ldr	r0, [r3, #4]
 8014d10:	68fb      	ldr	r3, [r7, #12]
 8014d12:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8014d14:	461a      	mov	r2, r3
 8014d16:	68b9      	ldr	r1, [r7, #8]
 8014d18:	f003 f81f 	bl	8017d5a <memcpy>
		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
 8014d1c:	68fb      	ldr	r3, [r7, #12]
 8014d1e:	685a      	ldr	r2, [r3, #4]
 8014d20:	68fb      	ldr	r3, [r7, #12]
 8014d22:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8014d24:	441a      	add	r2, r3
 8014d26:	68fb      	ldr	r3, [r7, #12]
 8014d28:	605a      	str	r2, [r3, #4]
		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 8014d2a:	68fb      	ldr	r3, [r7, #12]
 8014d2c:	685a      	ldr	r2, [r3, #4]
 8014d2e:	68fb      	ldr	r3, [r7, #12]
 8014d30:	689b      	ldr	r3, [r3, #8]
 8014d32:	429a      	cmp	r2, r3
 8014d34:	d32b      	bcc.n	8014d8e <prvCopyDataToQueue+0xc2>
		{
			pxQueue->pcWriteTo = pxQueue->pcHead;
 8014d36:	68fb      	ldr	r3, [r7, #12]
 8014d38:	681a      	ldr	r2, [r3, #0]
 8014d3a:	68fb      	ldr	r3, [r7, #12]
 8014d3c:	605a      	str	r2, [r3, #4]
 8014d3e:	e026      	b.n	8014d8e <prvCopyDataToQueue+0xc2>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	else
	{
		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
 8014d40:	68fb      	ldr	r3, [r7, #12]
 8014d42:	68d8      	ldr	r0, [r3, #12]
 8014d44:	68fb      	ldr	r3, [r7, #12]
 8014d46:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8014d48:	461a      	mov	r2, r3
 8014d4a:	68b9      	ldr	r1, [r7, #8]
 8014d4c:	f003 f805 	bl	8017d5a <memcpy>
		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
 8014d50:	68fb      	ldr	r3, [r7, #12]
 8014d52:	68da      	ldr	r2, [r3, #12]
 8014d54:	68fb      	ldr	r3, [r7, #12]
 8014d56:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8014d58:	425b      	negs	r3, r3
 8014d5a:	441a      	add	r2, r3
 8014d5c:	68fb      	ldr	r3, [r7, #12]
 8014d5e:	60da      	str	r2, [r3, #12]
		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 8014d60:	68fb      	ldr	r3, [r7, #12]
 8014d62:	68da      	ldr	r2, [r3, #12]
 8014d64:	68fb      	ldr	r3, [r7, #12]
 8014d66:	681b      	ldr	r3, [r3, #0]
 8014d68:	429a      	cmp	r2, r3
 8014d6a:	d207      	bcs.n	8014d7c <prvCopyDataToQueue+0xb0>
		{
			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
 8014d6c:	68fb      	ldr	r3, [r7, #12]
 8014d6e:	689a      	ldr	r2, [r3, #8]
 8014d70:	68fb      	ldr	r3, [r7, #12]
 8014d72:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8014d74:	425b      	negs	r3, r3
 8014d76:	441a      	add	r2, r3
 8014d78:	68fb      	ldr	r3, [r7, #12]
 8014d7a:	60da      	str	r2, [r3, #12]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		if( xPosition == queueOVERWRITE )
 8014d7c:	687b      	ldr	r3, [r7, #4]
 8014d7e:	2b02      	cmp	r3, #2
 8014d80:	d105      	bne.n	8014d8e <prvCopyDataToQueue+0xc2>
		{
			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8014d82:	693b      	ldr	r3, [r7, #16]
 8014d84:	2b00      	cmp	r3, #0
 8014d86:	d002      	beq.n	8014d8e <prvCopyDataToQueue+0xc2>
			{
				/* An item is not being added but overwritten, so subtract
				one from the recorded number of items in the queue so when
				one is added again below the number of recorded items remains
				correct. */
				--uxMessagesWaiting;
 8014d88:	693b      	ldr	r3, [r7, #16]
 8014d8a:	3b01      	subs	r3, #1
 8014d8c:	613b      	str	r3, [r7, #16]
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}

	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
 8014d8e:	693b      	ldr	r3, [r7, #16]
 8014d90:	1c5a      	adds	r2, r3, #1
 8014d92:	68fb      	ldr	r3, [r7, #12]
 8014d94:	639a      	str	r2, [r3, #56]	@ 0x38

	return xReturn;
 8014d96:	697b      	ldr	r3, [r7, #20]
}
 8014d98:	4618      	mov	r0, r3
 8014d9a:	3718      	adds	r7, #24
 8014d9c:	46bd      	mov	sp, r7
 8014d9e:	bd80      	pop	{r7, pc}

08014da0 <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/

static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
 8014da0:	b580      	push	{r7, lr}
 8014da2:	b082      	sub	sp, #8
 8014da4:	af00      	add	r7, sp, #0
 8014da6:	6078      	str	r0, [r7, #4]
 8014da8:	6039      	str	r1, [r7, #0]
	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
 8014daa:	687b      	ldr	r3, [r7, #4]
 8014dac:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8014dae:	2b00      	cmp	r3, #0
 8014db0:	d018      	beq.n	8014de4 <prvCopyDataFromQueue+0x44>
	{
		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
 8014db2:	687b      	ldr	r3, [r7, #4]
 8014db4:	68da      	ldr	r2, [r3, #12]
 8014db6:	687b      	ldr	r3, [r7, #4]
 8014db8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8014dba:	441a      	add	r2, r3
 8014dbc:	687b      	ldr	r3, [r7, #4]
 8014dbe:	60da      	str	r2, [r3, #12]
		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
 8014dc0:	687b      	ldr	r3, [r7, #4]
 8014dc2:	68da      	ldr	r2, [r3, #12]
 8014dc4:	687b      	ldr	r3, [r7, #4]
 8014dc6:	689b      	ldr	r3, [r3, #8]
 8014dc8:	429a      	cmp	r2, r3
 8014dca:	d303      	bcc.n	8014dd4 <prvCopyDataFromQueue+0x34>
		{
			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
 8014dcc:	687b      	ldr	r3, [r7, #4]
 8014dce:	681a      	ldr	r2, [r3, #0]
 8014dd0:	687b      	ldr	r3, [r7, #4]
 8014dd2:	60da      	str	r2, [r3, #12]
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 8014dd4:	687b      	ldr	r3, [r7, #4]
 8014dd6:	68d9      	ldr	r1, [r3, #12]
 8014dd8:	687b      	ldr	r3, [r7, #4]
 8014dda:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8014ddc:	461a      	mov	r2, r3
 8014dde:	6838      	ldr	r0, [r7, #0]
 8014de0:	f002 ffbb 	bl	8017d5a <memcpy>
	}
}
 8014de4:	bf00      	nop
 8014de6:	3708      	adds	r7, #8
 8014de8:	46bd      	mov	sp, r7
 8014dea:	bd80      	pop	{r7, pc}

08014dec <prvUnlockQueue>:
/*-----------------------------------------------------------*/

static void prvUnlockQueue( Queue_t * const pxQueue )
{
 8014dec:	b580      	push	{r7, lr}
 8014dee:	b084      	sub	sp, #16
 8014df0:	af00      	add	r7, sp, #0
 8014df2:	6078      	str	r0, [r7, #4]

	/* The lock counts contains the number of extra data items placed or
	removed from the queue while the queue was locked.  When a queue is
	locked items can be added or removed, but the event lists cannot be
	updated. */
	taskENTER_CRITICAL();
 8014df4:	f002 fab8 	bl	8017368 <vPortEnterCritical>
	{
		int8_t cTxLock = pxQueue->cTxLock;
 8014df8:	687b      	ldr	r3, [r7, #4]
 8014dfa:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8014dfe:	73fb      	strb	r3, [r7, #15]

		/* See if data was added to the queue while it was locked. */
		while( cTxLock > queueLOCKED_UNMODIFIED )
 8014e00:	e011      	b.n	8014e26 <prvUnlockQueue+0x3a>
			}
			#else /* configUSE_QUEUE_SETS */
			{
				/* Tasks that are removed from the event list will get added to
				the pending ready list as the scheduler is still suspended. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8014e02:	687b      	ldr	r3, [r7, #4]
 8014e04:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8014e06:	2b00      	cmp	r3, #0
 8014e08:	d012      	beq.n	8014e30 <prvUnlockQueue+0x44>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8014e0a:	687b      	ldr	r3, [r7, #4]
 8014e0c:	3324      	adds	r3, #36	@ 0x24
 8014e0e:	4618      	mov	r0, r3
 8014e10:	f000 ff28 	bl	8015c64 <xTaskRemoveFromEventList>
 8014e14:	4603      	mov	r3, r0
 8014e16:	2b00      	cmp	r3, #0
 8014e18:	d001      	beq.n	8014e1e <prvUnlockQueue+0x32>
					{
						/* The task waiting has a higher priority so record that
						a context switch is required. */
						vTaskMissedYield();
 8014e1a:	f001 f829 	bl	8015e70 <vTaskMissedYield>
					break;
				}
			}
			#endif /* configUSE_QUEUE_SETS */

			--cTxLock;
 8014e1e:	7bfb      	ldrb	r3, [r7, #15]
 8014e20:	3b01      	subs	r3, #1
 8014e22:	b2db      	uxtb	r3, r3
 8014e24:	73fb      	strb	r3, [r7, #15]
		while( cTxLock > queueLOCKED_UNMODIFIED )
 8014e26:	f997 300f 	ldrsb.w	r3, [r7, #15]
 8014e2a:	2b00      	cmp	r3, #0
 8014e2c:	dce9      	bgt.n	8014e02 <prvUnlockQueue+0x16>
 8014e2e:	e000      	b.n	8014e32 <prvUnlockQueue+0x46>
					break;
 8014e30:	bf00      	nop
		}

		pxQueue->cTxLock = queueUNLOCKED;
 8014e32:	687b      	ldr	r3, [r7, #4]
 8014e34:	22ff      	movs	r2, #255	@ 0xff
 8014e36:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
	}
	taskEXIT_CRITICAL();
 8014e3a:	f002 fac7 	bl	80173cc <vPortExitCritical>

	/* Do the same for the Rx lock. */
	taskENTER_CRITICAL();
 8014e3e:	f002 fa93 	bl	8017368 <vPortEnterCritical>
	{
		int8_t cRxLock = pxQueue->cRxLock;
 8014e42:	687b      	ldr	r3, [r7, #4]
 8014e44:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8014e48:	73bb      	strb	r3, [r7, #14]

		while( cRxLock > queueLOCKED_UNMODIFIED )
 8014e4a:	e011      	b.n	8014e70 <prvUnlockQueue+0x84>
		{
			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8014e4c:	687b      	ldr	r3, [r7, #4]
 8014e4e:	691b      	ldr	r3, [r3, #16]
 8014e50:	2b00      	cmp	r3, #0
 8014e52:	d012      	beq.n	8014e7a <prvUnlockQueue+0x8e>
			{
				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8014e54:	687b      	ldr	r3, [r7, #4]
 8014e56:	3310      	adds	r3, #16
 8014e58:	4618      	mov	r0, r3
 8014e5a:	f000 ff03 	bl	8015c64 <xTaskRemoveFromEventList>
 8014e5e:	4603      	mov	r3, r0
 8014e60:	2b00      	cmp	r3, #0
 8014e62:	d001      	beq.n	8014e68 <prvUnlockQueue+0x7c>
				{
					vTaskMissedYield();
 8014e64:	f001 f804 	bl	8015e70 <vTaskMissedYield>
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				--cRxLock;
 8014e68:	7bbb      	ldrb	r3, [r7, #14]
 8014e6a:	3b01      	subs	r3, #1
 8014e6c:	b2db      	uxtb	r3, r3
 8014e6e:	73bb      	strb	r3, [r7, #14]
		while( cRxLock > queueLOCKED_UNMODIFIED )
 8014e70:	f997 300e 	ldrsb.w	r3, [r7, #14]
 8014e74:	2b00      	cmp	r3, #0
 8014e76:	dce9      	bgt.n	8014e4c <prvUnlockQueue+0x60>
 8014e78:	e000      	b.n	8014e7c <prvUnlockQueue+0x90>
			}
			else
			{
				break;
 8014e7a:	bf00      	nop
			}
		}

		pxQueue->cRxLock = queueUNLOCKED;
 8014e7c:	687b      	ldr	r3, [r7, #4]
 8014e7e:	22ff      	movs	r2, #255	@ 0xff
 8014e80:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
	}
	taskEXIT_CRITICAL();
 8014e84:	f002 faa2 	bl	80173cc <vPortExitCritical>
}
 8014e88:	bf00      	nop
 8014e8a:	3710      	adds	r7, #16
 8014e8c:	46bd      	mov	sp, r7
 8014e8e:	bd80      	pop	{r7, pc}

08014e90 <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
 8014e90:	b580      	push	{r7, lr}
 8014e92:	b084      	sub	sp, #16
 8014e94:	af00      	add	r7, sp, #0
 8014e96:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;

	taskENTER_CRITICAL();
 8014e98:	f002 fa66 	bl	8017368 <vPortEnterCritical>
	{
		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
 8014e9c:	687b      	ldr	r3, [r7, #4]
 8014e9e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8014ea0:	2b00      	cmp	r3, #0
 8014ea2:	d102      	bne.n	8014eaa <prvIsQueueEmpty+0x1a>
		{
			xReturn = pdTRUE;
 8014ea4:	2301      	movs	r3, #1
 8014ea6:	60fb      	str	r3, [r7, #12]
 8014ea8:	e001      	b.n	8014eae <prvIsQueueEmpty+0x1e>
		}
		else
		{
			xReturn = pdFALSE;
 8014eaa:	2300      	movs	r3, #0
 8014eac:	60fb      	str	r3, [r7, #12]
		}
	}
	taskEXIT_CRITICAL();
 8014eae:	f002 fa8d 	bl	80173cc <vPortExitCritical>

	return xReturn;
 8014eb2:	68fb      	ldr	r3, [r7, #12]
}
 8014eb4:	4618      	mov	r0, r3
 8014eb6:	3710      	adds	r7, #16
 8014eb8:	46bd      	mov	sp, r7
 8014eba:	bd80      	pop	{r7, pc}

08014ebc <prvIsQueueFull>:
	return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
 8014ebc:	b580      	push	{r7, lr}
 8014ebe:	b084      	sub	sp, #16
 8014ec0:	af00      	add	r7, sp, #0
 8014ec2:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;

	taskENTER_CRITICAL();
 8014ec4:	f002 fa50 	bl	8017368 <vPortEnterCritical>
	{
		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
 8014ec8:	687b      	ldr	r3, [r7, #4]
 8014eca:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 8014ecc:	687b      	ldr	r3, [r7, #4]
 8014ece:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8014ed0:	429a      	cmp	r2, r3
 8014ed2:	d102      	bne.n	8014eda <prvIsQueueFull+0x1e>
		{
			xReturn = pdTRUE;
 8014ed4:	2301      	movs	r3, #1
 8014ed6:	60fb      	str	r3, [r7, #12]
 8014ed8:	e001      	b.n	8014ede <prvIsQueueFull+0x22>
		}
		else
		{
			xReturn = pdFALSE;
 8014eda:	2300      	movs	r3, #0
 8014edc:	60fb      	str	r3, [r7, #12]
		}
	}
	taskEXIT_CRITICAL();
 8014ede:	f002 fa75 	bl	80173cc <vPortExitCritical>

	return xReturn;
 8014ee2:	68fb      	ldr	r3, [r7, #12]
}
 8014ee4:	4618      	mov	r0, r3
 8014ee6:	3710      	adds	r7, #16
 8014ee8:	46bd      	mov	sp, r7
 8014eea:	bd80      	pop	{r7, pc}

08014eec <vQueueAddToRegistry>:
/*-----------------------------------------------------------*/

#if ( configQUEUE_REGISTRY_SIZE > 0 )

	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
	{
 8014eec:	b480      	push	{r7}
 8014eee:	b085      	sub	sp, #20
 8014ef0:	af00      	add	r7, sp, #0
 8014ef2:	6078      	str	r0, [r7, #4]
 8014ef4:	6039      	str	r1, [r7, #0]
	UBaseType_t ux;

		/* See if there is an empty space in the registry.  A NULL name denotes
		a free slot. */
		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
 8014ef6:	2300      	movs	r3, #0
 8014ef8:	60fb      	str	r3, [r7, #12]
 8014efa:	e014      	b.n	8014f26 <vQueueAddToRegistry+0x3a>
		{
			if( xQueueRegistry[ ux ].pcQueueName == NULL )
 8014efc:	4a0f      	ldr	r2, [pc, #60]	@ (8014f3c <vQueueAddToRegistry+0x50>)
 8014efe:	68fb      	ldr	r3, [r7, #12]
 8014f00:	f852 3033 	ldr.w	r3, [r2, r3, lsl #3]
 8014f04:	2b00      	cmp	r3, #0
 8014f06:	d10b      	bne.n	8014f20 <vQueueAddToRegistry+0x34>
			{
				/* Store the information on this queue. */
				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
 8014f08:	490c      	ldr	r1, [pc, #48]	@ (8014f3c <vQueueAddToRegistry+0x50>)
 8014f0a:	68fb      	ldr	r3, [r7, #12]
 8014f0c:	683a      	ldr	r2, [r7, #0]
 8014f0e:	f841 2033 	str.w	r2, [r1, r3, lsl #3]
				xQueueRegistry[ ux ].xHandle = xQueue;
 8014f12:	4a0a      	ldr	r2, [pc, #40]	@ (8014f3c <vQueueAddToRegistry+0x50>)
 8014f14:	68fb      	ldr	r3, [r7, #12]
 8014f16:	00db      	lsls	r3, r3, #3
 8014f18:	4413      	add	r3, r2
 8014f1a:	687a      	ldr	r2, [r7, #4]
 8014f1c:	605a      	str	r2, [r3, #4]

				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
				break;
 8014f1e:	e006      	b.n	8014f2e <vQueueAddToRegistry+0x42>
		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
 8014f20:	68fb      	ldr	r3, [r7, #12]
 8014f22:	3301      	adds	r3, #1
 8014f24:	60fb      	str	r3, [r7, #12]
 8014f26:	68fb      	ldr	r3, [r7, #12]
 8014f28:	2b07      	cmp	r3, #7
 8014f2a:	d9e7      	bls.n	8014efc <vQueueAddToRegistry+0x10>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	}
 8014f2c:	bf00      	nop
 8014f2e:	bf00      	nop
 8014f30:	3714      	adds	r7, #20
 8014f32:	46bd      	mov	sp, r7
 8014f34:	f85d 7b04 	ldr.w	r7, [sp], #4
 8014f38:	4770      	bx	lr
 8014f3a:	bf00      	nop
 8014f3c:	24002600 	.word	0x24002600

08014f40 <vQueueWaitForMessageRestricted>:
/*-----------------------------------------------------------*/

#if ( configUSE_TIMERS == 1 )

	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
	{
 8014f40:	b580      	push	{r7, lr}
 8014f42:	b086      	sub	sp, #24
 8014f44:	af00      	add	r7, sp, #0
 8014f46:	60f8      	str	r0, [r7, #12]
 8014f48:	60b9      	str	r1, [r7, #8]
 8014f4a:	607a      	str	r2, [r7, #4]
	Queue_t * const pxQueue = xQueue;
 8014f4c:	68fb      	ldr	r3, [r7, #12]
 8014f4e:	617b      	str	r3, [r7, #20]
		will not actually cause the task to block, just place it on a blocked
		list.  It will not block until the scheduler is unlocked - at which
		time a yield will be performed.  If an item is added to the queue while
		the queue is locked, and the calling task blocks on the queue, then the
		calling task will be immediately unblocked when the queue is unlocked. */
		prvLockQueue( pxQueue );
 8014f50:	f002 fa0a 	bl	8017368 <vPortEnterCritical>
 8014f54:	697b      	ldr	r3, [r7, #20]
 8014f56:	f893 3044 	ldrb.w	r3, [r3, #68]	@ 0x44
 8014f5a:	b25b      	sxtb	r3, r3
 8014f5c:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8014f60:	d103      	bne.n	8014f6a <vQueueWaitForMessageRestricted+0x2a>
 8014f62:	697b      	ldr	r3, [r7, #20]
 8014f64:	2200      	movs	r2, #0
 8014f66:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
 8014f6a:	697b      	ldr	r3, [r7, #20]
 8014f6c:	f893 3045 	ldrb.w	r3, [r3, #69]	@ 0x45
 8014f70:	b25b      	sxtb	r3, r3
 8014f72:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8014f76:	d103      	bne.n	8014f80 <vQueueWaitForMessageRestricted+0x40>
 8014f78:	697b      	ldr	r3, [r7, #20]
 8014f7a:	2200      	movs	r2, #0
 8014f7c:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
 8014f80:	f002 fa24 	bl	80173cc <vPortExitCritical>
		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
 8014f84:	697b      	ldr	r3, [r7, #20]
 8014f86:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8014f88:	2b00      	cmp	r3, #0
 8014f8a:	d106      	bne.n	8014f9a <vQueueWaitForMessageRestricted+0x5a>
		{
			/* There is nothing in the queue, block for the specified period. */
			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
 8014f8c:	697b      	ldr	r3, [r7, #20]
 8014f8e:	3324      	adds	r3, #36	@ 0x24
 8014f90:	687a      	ldr	r2, [r7, #4]
 8014f92:	68b9      	ldr	r1, [r7, #8]
 8014f94:	4618      	mov	r0, r3
 8014f96:	f000 fe39 	bl	8015c0c <vTaskPlaceOnEventListRestricted>
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
		prvUnlockQueue( pxQueue );
 8014f9a:	6978      	ldr	r0, [r7, #20]
 8014f9c:	f7ff ff26 	bl	8014dec <prvUnlockQueue>
	}
 8014fa0:	bf00      	nop
 8014fa2:	3718      	adds	r7, #24
 8014fa4:	46bd      	mov	sp, r7
 8014fa6:	bd80      	pop	{r7, pc}

08014fa8 <xStreamBufferSpacesAvailable>:
	return xReturn;
}
/*-----------------------------------------------------------*/

size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
{
 8014fa8:	b480      	push	{r7}
 8014faa:	b087      	sub	sp, #28
 8014fac:	af00      	add	r7, sp, #0
 8014fae:	6078      	str	r0, [r7, #4]
const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 8014fb0:	687b      	ldr	r3, [r7, #4]
 8014fb2:	613b      	str	r3, [r7, #16]
size_t xSpace;

	configASSERT( pxStreamBuffer );
 8014fb4:	693b      	ldr	r3, [r7, #16]
 8014fb6:	2b00      	cmp	r3, #0
 8014fb8:	d10b      	bne.n	8014fd2 <xStreamBufferSpacesAvailable+0x2a>
	__asm volatile
 8014fba:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8014fbe:	f383 8811 	msr	BASEPRI, r3
 8014fc2:	f3bf 8f6f 	isb	sy
 8014fc6:	f3bf 8f4f 	dsb	sy
 8014fca:	60fb      	str	r3, [r7, #12]
}
 8014fcc:	bf00      	nop
 8014fce:	bf00      	nop
 8014fd0:	e7fd      	b.n	8014fce <xStreamBufferSpacesAvailable+0x26>

	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
 8014fd2:	693b      	ldr	r3, [r7, #16]
 8014fd4:	689a      	ldr	r2, [r3, #8]
 8014fd6:	693b      	ldr	r3, [r7, #16]
 8014fd8:	681b      	ldr	r3, [r3, #0]
 8014fda:	4413      	add	r3, r2
 8014fdc:	617b      	str	r3, [r7, #20]
	xSpace -= pxStreamBuffer->xHead;
 8014fde:	693b      	ldr	r3, [r7, #16]
 8014fe0:	685b      	ldr	r3, [r3, #4]
 8014fe2:	697a      	ldr	r2, [r7, #20]
 8014fe4:	1ad3      	subs	r3, r2, r3
 8014fe6:	617b      	str	r3, [r7, #20]
	xSpace -= ( size_t ) 1;
 8014fe8:	697b      	ldr	r3, [r7, #20]
 8014fea:	3b01      	subs	r3, #1
 8014fec:	617b      	str	r3, [r7, #20]

	if( xSpace >= pxStreamBuffer->xLength )
 8014fee:	693b      	ldr	r3, [r7, #16]
 8014ff0:	689b      	ldr	r3, [r3, #8]
 8014ff2:	697a      	ldr	r2, [r7, #20]
 8014ff4:	429a      	cmp	r2, r3
 8014ff6:	d304      	bcc.n	8015002 <xStreamBufferSpacesAvailable+0x5a>
	{
		xSpace -= pxStreamBuffer->xLength;
 8014ff8:	693b      	ldr	r3, [r7, #16]
 8014ffa:	689b      	ldr	r3, [r3, #8]
 8014ffc:	697a      	ldr	r2, [r7, #20]
 8014ffe:	1ad3      	subs	r3, r2, r3
 8015000:	617b      	str	r3, [r7, #20]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	return xSpace;
 8015002:	697b      	ldr	r3, [r7, #20]
}
 8015004:	4618      	mov	r0, r3
 8015006:	371c      	adds	r7, #28
 8015008:	46bd      	mov	sp, r7
 801500a:	f85d 7b04 	ldr.w	r7, [sp], #4
 801500e:	4770      	bx	lr

08015010 <xStreamBufferSend>:

size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
						  const void *pvTxData,
						  size_t xDataLengthBytes,
						  TickType_t xTicksToWait )
{
 8015010:	b580      	push	{r7, lr}
 8015012:	b090      	sub	sp, #64	@ 0x40
 8015014:	af02      	add	r7, sp, #8
 8015016:	60f8      	str	r0, [r7, #12]
 8015018:	60b9      	str	r1, [r7, #8]
 801501a:	607a      	str	r2, [r7, #4]
 801501c:	603b      	str	r3, [r7, #0]
StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 801501e:	68fb      	ldr	r3, [r7, #12]
 8015020:	62fb      	str	r3, [r7, #44]	@ 0x2c
size_t xReturn, xSpace = 0;
 8015022:	2300      	movs	r3, #0
 8015024:	637b      	str	r3, [r7, #52]	@ 0x34
size_t xRequiredSpace = xDataLengthBytes;
 8015026:	687b      	ldr	r3, [r7, #4]
 8015028:	633b      	str	r3, [r7, #48]	@ 0x30
TimeOut_t xTimeOut;

	configASSERT( pvTxData );
 801502a:	68bb      	ldr	r3, [r7, #8]
 801502c:	2b00      	cmp	r3, #0
 801502e:	d10b      	bne.n	8015048 <xStreamBufferSend+0x38>
	__asm volatile
 8015030:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015034:	f383 8811 	msr	BASEPRI, r3
 8015038:	f3bf 8f6f 	isb	sy
 801503c:	f3bf 8f4f 	dsb	sy
 8015040:	627b      	str	r3, [r7, #36]	@ 0x24
}
 8015042:	bf00      	nop
 8015044:	bf00      	nop
 8015046:	e7fd      	b.n	8015044 <xStreamBufferSend+0x34>
	configASSERT( pxStreamBuffer );
 8015048:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 801504a:	2b00      	cmp	r3, #0
 801504c:	d10b      	bne.n	8015066 <xStreamBufferSend+0x56>
	__asm volatile
 801504e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015052:	f383 8811 	msr	BASEPRI, r3
 8015056:	f3bf 8f6f 	isb	sy
 801505a:	f3bf 8f4f 	dsb	sy
 801505e:	623b      	str	r3, [r7, #32]
}
 8015060:	bf00      	nop
 8015062:	bf00      	nop
 8015064:	e7fd      	b.n	8015062 <xStreamBufferSend+0x52>

	/* This send function is used to write to both message buffers and stream
	buffers.  If this is a message buffer then the space needed must be
	increased by the amount of bytes needed to store the length of the
	message. */
	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
 8015066:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8015068:	7f1b      	ldrb	r3, [r3, #28]
 801506a:	f003 0301 	and.w	r3, r3, #1
 801506e:	2b00      	cmp	r3, #0
 8015070:	d012      	beq.n	8015098 <xStreamBufferSend+0x88>
	{
		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
 8015072:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015074:	3304      	adds	r3, #4
 8015076:	633b      	str	r3, [r7, #48]	@ 0x30

		/* Overflow? */
		configASSERT( xRequiredSpace > xDataLengthBytes );
 8015078:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 801507a:	687b      	ldr	r3, [r7, #4]
 801507c:	429a      	cmp	r2, r3
 801507e:	d80b      	bhi.n	8015098 <xStreamBufferSend+0x88>
	__asm volatile
 8015080:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015084:	f383 8811 	msr	BASEPRI, r3
 8015088:	f3bf 8f6f 	isb	sy
 801508c:	f3bf 8f4f 	dsb	sy
 8015090:	61fb      	str	r3, [r7, #28]
}
 8015092:	bf00      	nop
 8015094:	bf00      	nop
 8015096:	e7fd      	b.n	8015094 <xStreamBufferSend+0x84>
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	if( xTicksToWait != ( TickType_t ) 0 )
 8015098:	683b      	ldr	r3, [r7, #0]
 801509a:	2b00      	cmp	r3, #0
 801509c:	d03f      	beq.n	801511e <xStreamBufferSend+0x10e>
	{
		vTaskSetTimeOutState( &xTimeOut );
 801509e:	f107 0310 	add.w	r3, r7, #16
 80150a2:	4618      	mov	r0, r3
 80150a4:	f000 fe42 	bl	8015d2c <vTaskSetTimeOutState>

		do
		{
			/* Wait until the required number of bytes are free in the message
			buffer. */
			taskENTER_CRITICAL();
 80150a8:	f002 f95e 	bl	8017368 <vPortEnterCritical>
			{
				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
 80150ac:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 80150ae:	f7ff ff7b 	bl	8014fa8 <xStreamBufferSpacesAvailable>
 80150b2:	6378      	str	r0, [r7, #52]	@ 0x34

				if( xSpace < xRequiredSpace )
 80150b4:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 80150b6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80150b8:	429a      	cmp	r2, r3
 80150ba:	d218      	bcs.n	80150ee <xStreamBufferSend+0xde>
				{
					/* Clear notification state as going to wait for space. */
					( void ) xTaskNotifyStateClear( NULL );
 80150bc:	2000      	movs	r0, #0
 80150be:	f001 fb65 	bl	801678c <xTaskNotifyStateClear>

					/* Should only be one writer. */
					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
 80150c2:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80150c4:	695b      	ldr	r3, [r3, #20]
 80150c6:	2b00      	cmp	r3, #0
 80150c8:	d00b      	beq.n	80150e2 <xStreamBufferSend+0xd2>
	__asm volatile
 80150ca:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80150ce:	f383 8811 	msr	BASEPRI, r3
 80150d2:	f3bf 8f6f 	isb	sy
 80150d6:	f3bf 8f4f 	dsb	sy
 80150da:	61bb      	str	r3, [r7, #24]
}
 80150dc:	bf00      	nop
 80150de:	bf00      	nop
 80150e0:	e7fd      	b.n	80150de <xStreamBufferSend+0xce>
					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
 80150e2:	f000 ffad 	bl	8016040 <xTaskGetCurrentTaskHandle>
 80150e6:	4602      	mov	r2, r0
 80150e8:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80150ea:	615a      	str	r2, [r3, #20]
 80150ec:	e002      	b.n	80150f4 <xStreamBufferSend+0xe4>
				}
				else
				{
					taskEXIT_CRITICAL();
 80150ee:	f002 f96d 	bl	80173cc <vPortExitCritical>
					break;
 80150f2:	e014      	b.n	801511e <xStreamBufferSend+0x10e>
				}
			}
			taskEXIT_CRITICAL();
 80150f4:	f002 f96a 	bl	80173cc <vPortExitCritical>

			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
 80150f8:	683b      	ldr	r3, [r7, #0]
 80150fa:	2200      	movs	r2, #0
 80150fc:	2100      	movs	r1, #0
 80150fe:	2000      	movs	r0, #0
 8015100:	f001 f93c 	bl	801637c <xTaskNotifyWait>
			pxStreamBuffer->xTaskWaitingToSend = NULL;
 8015104:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8015106:	2200      	movs	r2, #0
 8015108:	615a      	str	r2, [r3, #20]

		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
 801510a:	463a      	mov	r2, r7
 801510c:	f107 0310 	add.w	r3, r7, #16
 8015110:	4611      	mov	r1, r2
 8015112:	4618      	mov	r0, r3
 8015114:	f000 fe48 	bl	8015da8 <xTaskCheckForTimeOut>
 8015118:	4603      	mov	r3, r0
 801511a:	2b00      	cmp	r3, #0
 801511c:	d0c4      	beq.n	80150a8 <xStreamBufferSend+0x98>
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	if( xSpace == ( size_t ) 0 )
 801511e:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8015120:	2b00      	cmp	r3, #0
 8015122:	d103      	bne.n	801512c <xStreamBufferSend+0x11c>
	{
		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
 8015124:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8015126:	f7ff ff3f 	bl	8014fa8 <xStreamBufferSpacesAvailable>
 801512a:	6378      	str	r0, [r7, #52]	@ 0x34
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
 801512c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801512e:	9300      	str	r3, [sp, #0]
 8015130:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8015132:	687a      	ldr	r2, [r7, #4]
 8015134:	68b9      	ldr	r1, [r7, #8]
 8015136:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8015138:	f000 f823 	bl	8015182 <prvWriteMessageToBuffer>
 801513c:	62b8      	str	r0, [r7, #40]	@ 0x28

	if( xReturn > ( size_t ) 0 )
 801513e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8015140:	2b00      	cmp	r3, #0
 8015142:	d019      	beq.n	8015178 <xStreamBufferSend+0x168>
	{
		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );

		/* Was a task waiting for the data? */
		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
 8015144:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8015146:	f000 f8ce 	bl	80152e6 <prvBytesInBuffer>
 801514a:	4602      	mov	r2, r0
 801514c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 801514e:	68db      	ldr	r3, [r3, #12]
 8015150:	429a      	cmp	r2, r3
 8015152:	d311      	bcc.n	8015178 <xStreamBufferSend+0x168>
		{
			sbSEND_COMPLETED( pxStreamBuffer );
 8015154:	f000 fb4a 	bl	80157ec <vTaskSuspendAll>
 8015158:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 801515a:	691b      	ldr	r3, [r3, #16]
 801515c:	2b00      	cmp	r3, #0
 801515e:	d009      	beq.n	8015174 <xStreamBufferSend+0x164>
 8015160:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8015162:	6918      	ldr	r0, [r3, #16]
 8015164:	2300      	movs	r3, #0
 8015166:	2200      	movs	r2, #0
 8015168:	2100      	movs	r1, #0
 801516a:	f001 f967 	bl	801643c <xTaskGenericNotify>
 801516e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8015170:	2200      	movs	r2, #0
 8015172:	611a      	str	r2, [r3, #16]
 8015174:	f000 fb48 	bl	8015808 <xTaskResumeAll>
	{
		mtCOVERAGE_TEST_MARKER();
		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
	}

	return xReturn;
 8015178:	6abb      	ldr	r3, [r7, #40]	@ 0x28
}
 801517a:	4618      	mov	r0, r3
 801517c:	3738      	adds	r7, #56	@ 0x38
 801517e:	46bd      	mov	sp, r7
 8015180:	bd80      	pop	{r7, pc}

08015182 <prvWriteMessageToBuffer>:
static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
									   const void * pvTxData,
									   size_t xDataLengthBytes,
									   size_t xSpace,
									   size_t xRequiredSpace )
{
 8015182:	b580      	push	{r7, lr}
 8015184:	b086      	sub	sp, #24
 8015186:	af00      	add	r7, sp, #0
 8015188:	60f8      	str	r0, [r7, #12]
 801518a:	60b9      	str	r1, [r7, #8]
 801518c:	607a      	str	r2, [r7, #4]
 801518e:	603b      	str	r3, [r7, #0]
	BaseType_t xShouldWrite;
	size_t xReturn;

	if( xSpace == ( size_t ) 0 )
 8015190:	683b      	ldr	r3, [r7, #0]
 8015192:	2b00      	cmp	r3, #0
 8015194:	d102      	bne.n	801519c <prvWriteMessageToBuffer+0x1a>
	{
		/* Doesn't matter if this is a stream buffer or a message buffer, there
		is no space to write. */
		xShouldWrite = pdFALSE;
 8015196:	2300      	movs	r3, #0
 8015198:	617b      	str	r3, [r7, #20]
 801519a:	e01d      	b.n	80151d8 <prvWriteMessageToBuffer+0x56>
	}
	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
 801519c:	68fb      	ldr	r3, [r7, #12]
 801519e:	7f1b      	ldrb	r3, [r3, #28]
 80151a0:	f003 0301 	and.w	r3, r3, #1
 80151a4:	2b00      	cmp	r3, #0
 80151a6:	d108      	bne.n	80151ba <prvWriteMessageToBuffer+0x38>
	{
		/* This is a stream buffer, as opposed to a message buffer, so writing a
		stream of bytes rather than discrete messages.  Write as many bytes as
		possible. */
		xShouldWrite = pdTRUE;
 80151a8:	2301      	movs	r3, #1
 80151aa:	617b      	str	r3, [r7, #20]
		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
 80151ac:	687a      	ldr	r2, [r7, #4]
 80151ae:	683b      	ldr	r3, [r7, #0]
 80151b0:	4293      	cmp	r3, r2
 80151b2:	bf28      	it	cs
 80151b4:	4613      	movcs	r3, r2
 80151b6:	607b      	str	r3, [r7, #4]
 80151b8:	e00e      	b.n	80151d8 <prvWriteMessageToBuffer+0x56>
	}
	else if( xSpace >= xRequiredSpace )
 80151ba:	683a      	ldr	r2, [r7, #0]
 80151bc:	6a3b      	ldr	r3, [r7, #32]
 80151be:	429a      	cmp	r2, r3
 80151c0:	d308      	bcc.n	80151d4 <prvWriteMessageToBuffer+0x52>
	{
		/* This is a message buffer, as opposed to a stream buffer, and there
		is enough space to write both the message length and the message itself
		into the buffer.  Start by writing the length of the data, the data
		itself will be written later in this function. */
		xShouldWrite = pdTRUE;
 80151c2:	2301      	movs	r3, #1
 80151c4:	617b      	str	r3, [r7, #20]
		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
 80151c6:	1d3b      	adds	r3, r7, #4
 80151c8:	2204      	movs	r2, #4
 80151ca:	4619      	mov	r1, r3
 80151cc:	68f8      	ldr	r0, [r7, #12]
 80151ce:	f000 f815 	bl	80151fc <prvWriteBytesToBuffer>
 80151d2:	e001      	b.n	80151d8 <prvWriteMessageToBuffer+0x56>
	}
	else
	{
		/* There is space available, but not enough space. */
		xShouldWrite = pdFALSE;
 80151d4:	2300      	movs	r3, #0
 80151d6:	617b      	str	r3, [r7, #20]
	}

	if( xShouldWrite != pdFALSE )
 80151d8:	697b      	ldr	r3, [r7, #20]
 80151da:	2b00      	cmp	r3, #0
 80151dc:	d007      	beq.n	80151ee <prvWriteMessageToBuffer+0x6c>
	{
		/* Writes the data itself. */
		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
 80151de:	687b      	ldr	r3, [r7, #4]
 80151e0:	461a      	mov	r2, r3
 80151e2:	68b9      	ldr	r1, [r7, #8]
 80151e4:	68f8      	ldr	r0, [r7, #12]
 80151e6:	f000 f809 	bl	80151fc <prvWriteBytesToBuffer>
 80151ea:	6138      	str	r0, [r7, #16]
 80151ec:	e001      	b.n	80151f2 <prvWriteMessageToBuffer+0x70>
	}
	else
	{
		xReturn = 0;
 80151ee:	2300      	movs	r3, #0
 80151f0:	613b      	str	r3, [r7, #16]
	}

	return xReturn;
 80151f2:	693b      	ldr	r3, [r7, #16]
}
 80151f4:	4618      	mov	r0, r3
 80151f6:	3718      	adds	r7, #24
 80151f8:	46bd      	mov	sp, r7
 80151fa:	bd80      	pop	{r7, pc}

080151fc <prvWriteBytesToBuffer>:
	return xReturn;
}
/*-----------------------------------------------------------*/

static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
{
 80151fc:	b580      	push	{r7, lr}
 80151fe:	b08a      	sub	sp, #40	@ 0x28
 8015200:	af00      	add	r7, sp, #0
 8015202:	60f8      	str	r0, [r7, #12]
 8015204:	60b9      	str	r1, [r7, #8]
 8015206:	607a      	str	r2, [r7, #4]
size_t xNextHead, xFirstLength;

	configASSERT( xCount > ( size_t ) 0 );
 8015208:	687b      	ldr	r3, [r7, #4]
 801520a:	2b00      	cmp	r3, #0
 801520c:	d10b      	bne.n	8015226 <prvWriteBytesToBuffer+0x2a>
	__asm volatile
 801520e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015212:	f383 8811 	msr	BASEPRI, r3
 8015216:	f3bf 8f6f 	isb	sy
 801521a:	f3bf 8f4f 	dsb	sy
 801521e:	61fb      	str	r3, [r7, #28]
}
 8015220:	bf00      	nop
 8015222:	bf00      	nop
 8015224:	e7fd      	b.n	8015222 <prvWriteBytesToBuffer+0x26>

	xNextHead = pxStreamBuffer->xHead;
 8015226:	68fb      	ldr	r3, [r7, #12]
 8015228:	685b      	ldr	r3, [r3, #4]
 801522a:	627b      	str	r3, [r7, #36]	@ 0x24

	/* Calculate the number of bytes that can be added in the first write -
	which may be less than the total number of bytes that need to be added if
	the buffer will wrap back to the beginning. */
	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
 801522c:	68fb      	ldr	r3, [r7, #12]
 801522e:	689a      	ldr	r2, [r3, #8]
 8015230:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8015232:	1ad3      	subs	r3, r2, r3
 8015234:	687a      	ldr	r2, [r7, #4]
 8015236:	4293      	cmp	r3, r2
 8015238:	bf28      	it	cs
 801523a:	4613      	movcs	r3, r2
 801523c:	623b      	str	r3, [r7, #32]

	/* Write as many bytes as can be written in the first write. */
	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
 801523e:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8015240:	6a3b      	ldr	r3, [r7, #32]
 8015242:	441a      	add	r2, r3
 8015244:	68fb      	ldr	r3, [r7, #12]
 8015246:	689b      	ldr	r3, [r3, #8]
 8015248:	429a      	cmp	r2, r3
 801524a:	d90b      	bls.n	8015264 <prvWriteBytesToBuffer+0x68>
	__asm volatile
 801524c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015250:	f383 8811 	msr	BASEPRI, r3
 8015254:	f3bf 8f6f 	isb	sy
 8015258:	f3bf 8f4f 	dsb	sy
 801525c:	61bb      	str	r3, [r7, #24]
}
 801525e:	bf00      	nop
 8015260:	bf00      	nop
 8015262:	e7fd      	b.n	8015260 <prvWriteBytesToBuffer+0x64>
	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
 8015264:	68fb      	ldr	r3, [r7, #12]
 8015266:	699a      	ldr	r2, [r3, #24]
 8015268:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 801526a:	4413      	add	r3, r2
 801526c:	6a3a      	ldr	r2, [r7, #32]
 801526e:	68b9      	ldr	r1, [r7, #8]
 8015270:	4618      	mov	r0, r3
 8015272:	f002 fd72 	bl	8017d5a <memcpy>

	/* If the number of bytes written was less than the number that could be
	written in the first write... */
	if( xCount > xFirstLength )
 8015276:	687a      	ldr	r2, [r7, #4]
 8015278:	6a3b      	ldr	r3, [r7, #32]
 801527a:	429a      	cmp	r2, r3
 801527c:	d91d      	bls.n	80152ba <prvWriteBytesToBuffer+0xbe>
	{
		/* ...then write the remaining bytes to the start of the buffer. */
		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
 801527e:	687a      	ldr	r2, [r7, #4]
 8015280:	6a3b      	ldr	r3, [r7, #32]
 8015282:	1ad2      	subs	r2, r2, r3
 8015284:	68fb      	ldr	r3, [r7, #12]
 8015286:	689b      	ldr	r3, [r3, #8]
 8015288:	429a      	cmp	r2, r3
 801528a:	d90b      	bls.n	80152a4 <prvWriteBytesToBuffer+0xa8>
	__asm volatile
 801528c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015290:	f383 8811 	msr	BASEPRI, r3
 8015294:	f3bf 8f6f 	isb	sy
 8015298:	f3bf 8f4f 	dsb	sy
 801529c:	617b      	str	r3, [r7, #20]
}
 801529e:	bf00      	nop
 80152a0:	bf00      	nop
 80152a2:	e7fd      	b.n	80152a0 <prvWriteBytesToBuffer+0xa4>
		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
 80152a4:	68fb      	ldr	r3, [r7, #12]
 80152a6:	6998      	ldr	r0, [r3, #24]
 80152a8:	68ba      	ldr	r2, [r7, #8]
 80152aa:	6a3b      	ldr	r3, [r7, #32]
 80152ac:	18d1      	adds	r1, r2, r3
 80152ae:	687a      	ldr	r2, [r7, #4]
 80152b0:	6a3b      	ldr	r3, [r7, #32]
 80152b2:	1ad3      	subs	r3, r2, r3
 80152b4:	461a      	mov	r2, r3
 80152b6:	f002 fd50 	bl	8017d5a <memcpy>
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	xNextHead += xCount;
 80152ba:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 80152bc:	687b      	ldr	r3, [r7, #4]
 80152be:	4413      	add	r3, r2
 80152c0:	627b      	str	r3, [r7, #36]	@ 0x24
	if( xNextHead >= pxStreamBuffer->xLength )
 80152c2:	68fb      	ldr	r3, [r7, #12]
 80152c4:	689b      	ldr	r3, [r3, #8]
 80152c6:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 80152c8:	429a      	cmp	r2, r3
 80152ca:	d304      	bcc.n	80152d6 <prvWriteBytesToBuffer+0xda>
	{
		xNextHead -= pxStreamBuffer->xLength;
 80152cc:	68fb      	ldr	r3, [r7, #12]
 80152ce:	689b      	ldr	r3, [r3, #8]
 80152d0:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 80152d2:	1ad3      	subs	r3, r2, r3
 80152d4:	627b      	str	r3, [r7, #36]	@ 0x24
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxStreamBuffer->xHead = xNextHead;
 80152d6:	68fb      	ldr	r3, [r7, #12]
 80152d8:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 80152da:	605a      	str	r2, [r3, #4]

	return xCount;
 80152dc:	687b      	ldr	r3, [r7, #4]
}
 80152de:	4618      	mov	r0, r3
 80152e0:	3728      	adds	r7, #40	@ 0x28
 80152e2:	46bd      	mov	sp, r7
 80152e4:	bd80      	pop	{r7, pc}

080152e6 <prvBytesInBuffer>:
	return xCount;
}
/*-----------------------------------------------------------*/

static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
{
 80152e6:	b480      	push	{r7}
 80152e8:	b085      	sub	sp, #20
 80152ea:	af00      	add	r7, sp, #0
 80152ec:	6078      	str	r0, [r7, #4]
/* Returns the distance between xTail and xHead. */
size_t xCount;

	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
 80152ee:	687b      	ldr	r3, [r7, #4]
 80152f0:	689a      	ldr	r2, [r3, #8]
 80152f2:	687b      	ldr	r3, [r7, #4]
 80152f4:	685b      	ldr	r3, [r3, #4]
 80152f6:	4413      	add	r3, r2
 80152f8:	60fb      	str	r3, [r7, #12]
	xCount -= pxStreamBuffer->xTail;
 80152fa:	687b      	ldr	r3, [r7, #4]
 80152fc:	681b      	ldr	r3, [r3, #0]
 80152fe:	68fa      	ldr	r2, [r7, #12]
 8015300:	1ad3      	subs	r3, r2, r3
 8015302:	60fb      	str	r3, [r7, #12]
	if ( xCount >= pxStreamBuffer->xLength )
 8015304:	687b      	ldr	r3, [r7, #4]
 8015306:	689b      	ldr	r3, [r3, #8]
 8015308:	68fa      	ldr	r2, [r7, #12]
 801530a:	429a      	cmp	r2, r3
 801530c:	d304      	bcc.n	8015318 <prvBytesInBuffer+0x32>
	{
		xCount -= pxStreamBuffer->xLength;
 801530e:	687b      	ldr	r3, [r7, #4]
 8015310:	689b      	ldr	r3, [r3, #8]
 8015312:	68fa      	ldr	r2, [r7, #12]
 8015314:	1ad3      	subs	r3, r2, r3
 8015316:	60fb      	str	r3, [r7, #12]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	return xCount;
 8015318:	68fb      	ldr	r3, [r7, #12]
}
 801531a:	4618      	mov	r0, r3
 801531c:	3714      	adds	r7, #20
 801531e:	46bd      	mov	sp, r7
 8015320:	f85d 7b04 	ldr.w	r7, [sp], #4
 8015324:	4770      	bx	lr

08015326 <xTaskCreateStatic>:
									const uint32_t ulStackDepth,
									void * const pvParameters,
									UBaseType_t uxPriority,
									StackType_t * const puxStackBuffer,
									StaticTask_t * const pxTaskBuffer )
	{
 8015326:	b580      	push	{r7, lr}
 8015328:	b08e      	sub	sp, #56	@ 0x38
 801532a:	af04      	add	r7, sp, #16
 801532c:	60f8      	str	r0, [r7, #12]
 801532e:	60b9      	str	r1, [r7, #8]
 8015330:	607a      	str	r2, [r7, #4]
 8015332:	603b      	str	r3, [r7, #0]
	TCB_t *pxNewTCB;
	TaskHandle_t xReturn;

		configASSERT( puxStackBuffer != NULL );
 8015334:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8015336:	2b00      	cmp	r3, #0
 8015338:	d10b      	bne.n	8015352 <xTaskCreateStatic+0x2c>
	__asm volatile
 801533a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801533e:	f383 8811 	msr	BASEPRI, r3
 8015342:	f3bf 8f6f 	isb	sy
 8015346:	f3bf 8f4f 	dsb	sy
 801534a:	623b      	str	r3, [r7, #32]
}
 801534c:	bf00      	nop
 801534e:	bf00      	nop
 8015350:	e7fd      	b.n	801534e <xTaskCreateStatic+0x28>
		configASSERT( pxTaskBuffer != NULL );
 8015352:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8015354:	2b00      	cmp	r3, #0
 8015356:	d10b      	bne.n	8015370 <xTaskCreateStatic+0x4a>
	__asm volatile
 8015358:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801535c:	f383 8811 	msr	BASEPRI, r3
 8015360:	f3bf 8f6f 	isb	sy
 8015364:	f3bf 8f4f 	dsb	sy
 8015368:	61fb      	str	r3, [r7, #28]
}
 801536a:	bf00      	nop
 801536c:	bf00      	nop
 801536e:	e7fd      	b.n	801536c <xTaskCreateStatic+0x46>
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticTask_t equals the size of the real task
			structure. */
			volatile size_t xSize = sizeof( StaticTask_t );
 8015370:	23a8      	movs	r3, #168	@ 0xa8
 8015372:	613b      	str	r3, [r7, #16]
			configASSERT( xSize == sizeof( TCB_t ) );
 8015374:	693b      	ldr	r3, [r7, #16]
 8015376:	2ba8      	cmp	r3, #168	@ 0xa8
 8015378:	d00b      	beq.n	8015392 <xTaskCreateStatic+0x6c>
	__asm volatile
 801537a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801537e:	f383 8811 	msr	BASEPRI, r3
 8015382:	f3bf 8f6f 	isb	sy
 8015386:	f3bf 8f4f 	dsb	sy
 801538a:	61bb      	str	r3, [r7, #24]
}
 801538c:	bf00      	nop
 801538e:	bf00      	nop
 8015390:	e7fd      	b.n	801538e <xTaskCreateStatic+0x68>
			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
 8015392:	693b      	ldr	r3, [r7, #16]
		}
		#endif /* configASSERT_DEFINED */


		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
 8015394:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8015396:	2b00      	cmp	r3, #0
 8015398:	d01e      	beq.n	80153d8 <xTaskCreateStatic+0xb2>
 801539a:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 801539c:	2b00      	cmp	r3, #0
 801539e:	d01b      	beq.n	80153d8 <xTaskCreateStatic+0xb2>
		{
			/* The memory used for the task's TCB and stack are passed into this
			function - use them. */
			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 80153a0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 80153a2:	627b      	str	r3, [r7, #36]	@ 0x24
			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
 80153a4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80153a6:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 80153a8:	631a      	str	r2, [r3, #48]	@ 0x30

			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
			{
				/* Tasks can be created statically or dynamically, so note this
				task was created statically in case the task is later deleted. */
				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
 80153aa:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80153ac:	2202      	movs	r2, #2
 80153ae:	f883 20a5 	strb.w	r2, [r3, #165]	@ 0xa5
			}
			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
 80153b2:	2300      	movs	r3, #0
 80153b4:	9303      	str	r3, [sp, #12]
 80153b6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80153b8:	9302      	str	r3, [sp, #8]
 80153ba:	f107 0314 	add.w	r3, r7, #20
 80153be:	9301      	str	r3, [sp, #4]
 80153c0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80153c2:	9300      	str	r3, [sp, #0]
 80153c4:	683b      	ldr	r3, [r7, #0]
 80153c6:	687a      	ldr	r2, [r7, #4]
 80153c8:	68b9      	ldr	r1, [r7, #8]
 80153ca:	68f8      	ldr	r0, [r7, #12]
 80153cc:	f000 f850 	bl	8015470 <prvInitialiseNewTask>
			prvAddNewTaskToReadyList( pxNewTCB );
 80153d0:	6a78      	ldr	r0, [r7, #36]	@ 0x24
 80153d2:	f000 f8f5 	bl	80155c0 <prvAddNewTaskToReadyList>
 80153d6:	e001      	b.n	80153dc <xTaskCreateStatic+0xb6>
		}
		else
		{
			xReturn = NULL;
 80153d8:	2300      	movs	r3, #0
 80153da:	617b      	str	r3, [r7, #20]
		}

		return xReturn;
 80153dc:	697b      	ldr	r3, [r7, #20]
	}
 80153de:	4618      	mov	r0, r3
 80153e0:	3728      	adds	r7, #40	@ 0x28
 80153e2:	46bd      	mov	sp, r7
 80153e4:	bd80      	pop	{r7, pc}

080153e6 <xTaskCreate>:
							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
							const configSTACK_DEPTH_TYPE usStackDepth,
							void * const pvParameters,
							UBaseType_t uxPriority,
							TaskHandle_t * const pxCreatedTask )
	{
 80153e6:	b580      	push	{r7, lr}
 80153e8:	b08c      	sub	sp, #48	@ 0x30
 80153ea:	af04      	add	r7, sp, #16
 80153ec:	60f8      	str	r0, [r7, #12]
 80153ee:	60b9      	str	r1, [r7, #8]
 80153f0:	603b      	str	r3, [r7, #0]
 80153f2:	4613      	mov	r3, r2
 80153f4:	80fb      	strh	r3, [r7, #6]
		#else /* portSTACK_GROWTH */
		{
		StackType_t *pxStack;

			/* Allocate space for the stack used by the task being created. */
			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
 80153f6:	88fb      	ldrh	r3, [r7, #6]
 80153f8:	009b      	lsls	r3, r3, #2
 80153fa:	4618      	mov	r0, r3
 80153fc:	f002 f8d6 	bl	80175ac <pvPortMalloc>
 8015400:	6178      	str	r0, [r7, #20]

			if( pxStack != NULL )
 8015402:	697b      	ldr	r3, [r7, #20]
 8015404:	2b00      	cmp	r3, #0
 8015406:	d00e      	beq.n	8015426 <xTaskCreate+0x40>
			{
				/* Allocate space for the TCB. */
				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
 8015408:	20a8      	movs	r0, #168	@ 0xa8
 801540a:	f002 f8cf 	bl	80175ac <pvPortMalloc>
 801540e:	61f8      	str	r0, [r7, #28]

				if( pxNewTCB != NULL )
 8015410:	69fb      	ldr	r3, [r7, #28]
 8015412:	2b00      	cmp	r3, #0
 8015414:	d003      	beq.n	801541e <xTaskCreate+0x38>
				{
					/* Store the stack location in the TCB. */
					pxNewTCB->pxStack = pxStack;
 8015416:	69fb      	ldr	r3, [r7, #28]
 8015418:	697a      	ldr	r2, [r7, #20]
 801541a:	631a      	str	r2, [r3, #48]	@ 0x30
 801541c:	e005      	b.n	801542a <xTaskCreate+0x44>
				}
				else
				{
					/* The stack cannot be used as the TCB was not created.  Free
					it again. */
					vPortFree( pxStack );
 801541e:	6978      	ldr	r0, [r7, #20]
 8015420:	f002 f992 	bl	8017748 <vPortFree>
 8015424:	e001      	b.n	801542a <xTaskCreate+0x44>
				}
			}
			else
			{
				pxNewTCB = NULL;
 8015426:	2300      	movs	r3, #0
 8015428:	61fb      	str	r3, [r7, #28]
			}
		}
		#endif /* portSTACK_GROWTH */

		if( pxNewTCB != NULL )
 801542a:	69fb      	ldr	r3, [r7, #28]
 801542c:	2b00      	cmp	r3, #0
 801542e:	d017      	beq.n	8015460 <xTaskCreate+0x7a>
		{
			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
			{
				/* Tasks can be created statically or dynamically, so note this
				task was created dynamically in case it is later deleted. */
				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
 8015430:	69fb      	ldr	r3, [r7, #28]
 8015432:	2200      	movs	r2, #0
 8015434:	f883 20a5 	strb.w	r2, [r3, #165]	@ 0xa5
			}
			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
 8015438:	88fa      	ldrh	r2, [r7, #6]
 801543a:	2300      	movs	r3, #0
 801543c:	9303      	str	r3, [sp, #12]
 801543e:	69fb      	ldr	r3, [r7, #28]
 8015440:	9302      	str	r3, [sp, #8]
 8015442:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8015444:	9301      	str	r3, [sp, #4]
 8015446:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8015448:	9300      	str	r3, [sp, #0]
 801544a:	683b      	ldr	r3, [r7, #0]
 801544c:	68b9      	ldr	r1, [r7, #8]
 801544e:	68f8      	ldr	r0, [r7, #12]
 8015450:	f000 f80e 	bl	8015470 <prvInitialiseNewTask>
			prvAddNewTaskToReadyList( pxNewTCB );
 8015454:	69f8      	ldr	r0, [r7, #28]
 8015456:	f000 f8b3 	bl	80155c0 <prvAddNewTaskToReadyList>
			xReturn = pdPASS;
 801545a:	2301      	movs	r3, #1
 801545c:	61bb      	str	r3, [r7, #24]
 801545e:	e002      	b.n	8015466 <xTaskCreate+0x80>
		}
		else
		{
			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
 8015460:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8015464:	61bb      	str	r3, [r7, #24]
		}

		return xReturn;
 8015466:	69bb      	ldr	r3, [r7, #24]
	}
 8015468:	4618      	mov	r0, r3
 801546a:	3720      	adds	r7, #32
 801546c:	46bd      	mov	sp, r7
 801546e:	bd80      	pop	{r7, pc}

08015470 <prvInitialiseNewTask>:
									void * const pvParameters,
									UBaseType_t uxPriority,
									TaskHandle_t * const pxCreatedTask,
									TCB_t *pxNewTCB,
									const MemoryRegion_t * const xRegions )
{
 8015470:	b580      	push	{r7, lr}
 8015472:	b088      	sub	sp, #32
 8015474:	af00      	add	r7, sp, #0
 8015476:	60f8      	str	r0, [r7, #12]
 8015478:	60b9      	str	r1, [r7, #8]
 801547a:	607a      	str	r2, [r7, #4]
 801547c:	603b      	str	r3, [r7, #0]

	/* Avoid dependency on memset() if it is not required. */
	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
	{
		/* Fill the stack with a known value to assist debugging. */
		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
 801547e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015480:	6b18      	ldr	r0, [r3, #48]	@ 0x30
 8015482:	687b      	ldr	r3, [r7, #4]
 8015484:	009b      	lsls	r3, r3, #2
 8015486:	461a      	mov	r2, r3
 8015488:	21a5      	movs	r1, #165	@ 0xa5
 801548a:	f002 fb94 	bl	8017bb6 <memset>
	grows from high memory to low (as per the 80x86) or vice versa.
	portSTACK_GROWTH is used to make the result positive or negative as required
	by the port. */
	#if( portSTACK_GROWTH < 0 )
	{
		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
 801548e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015490:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
 8015492:	6879      	ldr	r1, [r7, #4]
 8015494:	f06f 4340 	mvn.w	r3, #3221225472	@ 0xc0000000
 8015498:	440b      	add	r3, r1
 801549a:	009b      	lsls	r3, r3, #2
 801549c:	4413      	add	r3, r2
 801549e:	61bb      	str	r3, [r7, #24]
		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
 80154a0:	69bb      	ldr	r3, [r7, #24]
 80154a2:	f023 0307 	bic.w	r3, r3, #7
 80154a6:	61bb      	str	r3, [r7, #24]

		/* Check the alignment of the calculated top of stack is correct. */
		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
 80154a8:	69bb      	ldr	r3, [r7, #24]
 80154aa:	f003 0307 	and.w	r3, r3, #7
 80154ae:	2b00      	cmp	r3, #0
 80154b0:	d00b      	beq.n	80154ca <prvInitialiseNewTask+0x5a>
	__asm volatile
 80154b2:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80154b6:	f383 8811 	msr	BASEPRI, r3
 80154ba:	f3bf 8f6f 	isb	sy
 80154be:	f3bf 8f4f 	dsb	sy
 80154c2:	617b      	str	r3, [r7, #20]
}
 80154c4:	bf00      	nop
 80154c6:	bf00      	nop
 80154c8:	e7fd      	b.n	80154c6 <prvInitialiseNewTask+0x56>
		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
	}
	#endif /* portSTACK_GROWTH */

	/* Store the task name in the TCB. */
	if( pcName != NULL )
 80154ca:	68bb      	ldr	r3, [r7, #8]
 80154cc:	2b00      	cmp	r3, #0
 80154ce:	d01f      	beq.n	8015510 <prvInitialiseNewTask+0xa0>
	{
		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 80154d0:	2300      	movs	r3, #0
 80154d2:	61fb      	str	r3, [r7, #28]
 80154d4:	e012      	b.n	80154fc <prvInitialiseNewTask+0x8c>
		{
			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
 80154d6:	68ba      	ldr	r2, [r7, #8]
 80154d8:	69fb      	ldr	r3, [r7, #28]
 80154da:	4413      	add	r3, r2
 80154dc:	7819      	ldrb	r1, [r3, #0]
 80154de:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 80154e0:	69fb      	ldr	r3, [r7, #28]
 80154e2:	4413      	add	r3, r2
 80154e4:	3334      	adds	r3, #52	@ 0x34
 80154e6:	460a      	mov	r2, r1
 80154e8:	701a      	strb	r2, [r3, #0]

			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
			configMAX_TASK_NAME_LEN characters just in case the memory after the
			string is not accessible (extremely unlikely). */
			if( pcName[ x ] == ( char ) 0x00 )
 80154ea:	68ba      	ldr	r2, [r7, #8]
 80154ec:	69fb      	ldr	r3, [r7, #28]
 80154ee:	4413      	add	r3, r2
 80154f0:	781b      	ldrb	r3, [r3, #0]
 80154f2:	2b00      	cmp	r3, #0
 80154f4:	d006      	beq.n	8015504 <prvInitialiseNewTask+0x94>
		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 80154f6:	69fb      	ldr	r3, [r7, #28]
 80154f8:	3301      	adds	r3, #1
 80154fa:	61fb      	str	r3, [r7, #28]
 80154fc:	69fb      	ldr	r3, [r7, #28]
 80154fe:	2b0f      	cmp	r3, #15
 8015500:	d9e9      	bls.n	80154d6 <prvInitialiseNewTask+0x66>
 8015502:	e000      	b.n	8015506 <prvInitialiseNewTask+0x96>
			{
				break;
 8015504:	bf00      	nop
			}
		}

		/* Ensure the name string is terminated in the case that the string length
		was greater or equal to configMAX_TASK_NAME_LEN. */
		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
 8015506:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015508:	2200      	movs	r2, #0
 801550a:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
 801550e:	e003      	b.n	8015518 <prvInitialiseNewTask+0xa8>
	}
	else
	{
		/* The task has not been given a name, so just ensure there is a NULL
		terminator when it is read out. */
		pxNewTCB->pcTaskName[ 0 ] = 0x00;
 8015510:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015512:	2200      	movs	r2, #0
 8015514:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
	}

	/* This is used as an array index so must ensure it's not too large.  First
	remove the privilege bit if one is present. */
	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
 8015518:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 801551a:	2b37      	cmp	r3, #55	@ 0x37
 801551c:	d901      	bls.n	8015522 <prvInitialiseNewTask+0xb2>
	{
		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
 801551e:	2337      	movs	r3, #55	@ 0x37
 8015520:	62bb      	str	r3, [r7, #40]	@ 0x28
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxNewTCB->uxPriority = uxPriority;
 8015522:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015524:	6aba      	ldr	r2, [r7, #40]	@ 0x28
 8015526:	62da      	str	r2, [r3, #44]	@ 0x2c
	#if ( configUSE_MUTEXES == 1 )
	{
		pxNewTCB->uxBasePriority = uxPriority;
 8015528:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801552a:	6aba      	ldr	r2, [r7, #40]	@ 0x28
 801552c:	64da      	str	r2, [r3, #76]	@ 0x4c
		pxNewTCB->uxMutexesHeld = 0;
 801552e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015530:	2200      	movs	r2, #0
 8015532:	651a      	str	r2, [r3, #80]	@ 0x50
	}
	#endif /* configUSE_MUTEXES */

	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
 8015534:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015536:	3304      	adds	r3, #4
 8015538:	4618      	mov	r0, r3
 801553a:	f7fe fd09 	bl	8013f50 <vListInitialiseItem>
	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
 801553e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015540:	3318      	adds	r3, #24
 8015542:	4618      	mov	r0, r3
 8015544:	f7fe fd04 	bl	8013f50 <vListInitialiseItem>

	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
	back to	the containing TCB from a generic item in a list. */
	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
 8015548:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801554a:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 801554c:	611a      	str	r2, [r3, #16]

	/* Event lists are always in priority order. */
	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 801554e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8015550:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 8015554:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015556:	619a      	str	r2, [r3, #24]
	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
 8015558:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801555a:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 801555c:	625a      	str	r2, [r3, #36]	@ 0x24
	}
	#endif

	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
	{
		pxNewTCB->ulNotifiedValue = 0;
 801555e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015560:	2200      	movs	r2, #0
 8015562:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
 8015566:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015568:	2200      	movs	r2, #0
 801556a:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4
	#if ( configUSE_NEWLIB_REENTRANT == 1 )
	{
		/* Initialise this task's Newlib reent structure.
		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
		for additional information. */
		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
 801556e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015570:	3354      	adds	r3, #84	@ 0x54
 8015572:	224c      	movs	r2, #76	@ 0x4c
 8015574:	2100      	movs	r1, #0
 8015576:	4618      	mov	r0, r3
 8015578:	f002 fb1d 	bl	8017bb6 <memset>
 801557c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801557e:	4a0d      	ldr	r2, [pc, #52]	@ (80155b4 <prvInitialiseNewTask+0x144>)
 8015580:	659a      	str	r2, [r3, #88]	@ 0x58
 8015582:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8015584:	4a0c      	ldr	r2, [pc, #48]	@ (80155b8 <prvInitialiseNewTask+0x148>)
 8015586:	65da      	str	r2, [r3, #92]	@ 0x5c
 8015588:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801558a:	4a0c      	ldr	r2, [pc, #48]	@ (80155bc <prvInitialiseNewTask+0x14c>)
 801558c:	661a      	str	r2, [r3, #96]	@ 0x60
			}
			#endif /* portSTACK_GROWTH */
		}
		#else /* portHAS_STACK_OVERFLOW_CHECKING */
		{
			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
 801558e:	683a      	ldr	r2, [r7, #0]
 8015590:	68f9      	ldr	r1, [r7, #12]
 8015592:	69b8      	ldr	r0, [r7, #24]
 8015594:	f001 fdb8 	bl	8017108 <pxPortInitialiseStack>
 8015598:	4602      	mov	r2, r0
 801559a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801559c:	601a      	str	r2, [r3, #0]
		}
		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
	}
	#endif /* portUSING_MPU_WRAPPERS */

	if( pxCreatedTask != NULL )
 801559e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80155a0:	2b00      	cmp	r3, #0
 80155a2:	d002      	beq.n	80155aa <prvInitialiseNewTask+0x13a>
	{
		/* Pass the handle out in an anonymous way.  The handle can be used to
		change the created task's priority, delete the created task, etc.*/
		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
 80155a4:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80155a6:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 80155a8:	601a      	str	r2, [r3, #0]
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 80155aa:	bf00      	nop
 80155ac:	3720      	adds	r7, #32
 80155ae:	46bd      	mov	sp, r7
 80155b0:	bd80      	pop	{r7, pc}
 80155b2:	bf00      	nop
 80155b4:	24012c94 	.word	0x24012c94
 80155b8:	24012cfc 	.word	0x24012cfc
 80155bc:	24012d64 	.word	0x24012d64

080155c0 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/

static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
 80155c0:	b580      	push	{r7, lr}
 80155c2:	b082      	sub	sp, #8
 80155c4:	af00      	add	r7, sp, #0
 80155c6:	6078      	str	r0, [r7, #4]
	/* Ensure interrupts don't access the task lists while the lists are being
	updated. */
	taskENTER_CRITICAL();
 80155c8:	f001 fece 	bl	8017368 <vPortEnterCritical>
	{
		uxCurrentNumberOfTasks++;
 80155cc:	4b2d      	ldr	r3, [pc, #180]	@ (8015684 <prvAddNewTaskToReadyList+0xc4>)
 80155ce:	681b      	ldr	r3, [r3, #0]
 80155d0:	3301      	adds	r3, #1
 80155d2:	4a2c      	ldr	r2, [pc, #176]	@ (8015684 <prvAddNewTaskToReadyList+0xc4>)
 80155d4:	6013      	str	r3, [r2, #0]
		if( pxCurrentTCB == NULL )
 80155d6:	4b2c      	ldr	r3, [pc, #176]	@ (8015688 <prvAddNewTaskToReadyList+0xc8>)
 80155d8:	681b      	ldr	r3, [r3, #0]
 80155da:	2b00      	cmp	r3, #0
 80155dc:	d109      	bne.n	80155f2 <prvAddNewTaskToReadyList+0x32>
		{
			/* There are no other tasks, or all the other tasks are in
			the suspended state - make this the current task. */
			pxCurrentTCB = pxNewTCB;
 80155de:	4a2a      	ldr	r2, [pc, #168]	@ (8015688 <prvAddNewTaskToReadyList+0xc8>)
 80155e0:	687b      	ldr	r3, [r7, #4]
 80155e2:	6013      	str	r3, [r2, #0]

			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
 80155e4:	4b27      	ldr	r3, [pc, #156]	@ (8015684 <prvAddNewTaskToReadyList+0xc4>)
 80155e6:	681b      	ldr	r3, [r3, #0]
 80155e8:	2b01      	cmp	r3, #1
 80155ea:	d110      	bne.n	801560e <prvAddNewTaskToReadyList+0x4e>
			{
				/* This is the first task to be created so do the preliminary
				initialisation required.  We will not recover if this call
				fails, but we will report the failure. */
				prvInitialiseTaskLists();
 80155ec:	f000 fc64 	bl	8015eb8 <prvInitialiseTaskLists>
 80155f0:	e00d      	b.n	801560e <prvAddNewTaskToReadyList+0x4e>
		else
		{
			/* If the scheduler is not already running, make this task the
			current task if it is the highest priority task to be created
			so far. */
			if( xSchedulerRunning == pdFALSE )
 80155f2:	4b26      	ldr	r3, [pc, #152]	@ (801568c <prvAddNewTaskToReadyList+0xcc>)
 80155f4:	681b      	ldr	r3, [r3, #0]
 80155f6:	2b00      	cmp	r3, #0
 80155f8:	d109      	bne.n	801560e <prvAddNewTaskToReadyList+0x4e>
			{
				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
 80155fa:	4b23      	ldr	r3, [pc, #140]	@ (8015688 <prvAddNewTaskToReadyList+0xc8>)
 80155fc:	681b      	ldr	r3, [r3, #0]
 80155fe:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8015600:	687b      	ldr	r3, [r7, #4]
 8015602:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8015604:	429a      	cmp	r2, r3
 8015606:	d802      	bhi.n	801560e <prvAddNewTaskToReadyList+0x4e>
				{
					pxCurrentTCB = pxNewTCB;
 8015608:	4a1f      	ldr	r2, [pc, #124]	@ (8015688 <prvAddNewTaskToReadyList+0xc8>)
 801560a:	687b      	ldr	r3, [r7, #4]
 801560c:	6013      	str	r3, [r2, #0]
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}

		uxTaskNumber++;
 801560e:	4b20      	ldr	r3, [pc, #128]	@ (8015690 <prvAddNewTaskToReadyList+0xd0>)
 8015610:	681b      	ldr	r3, [r3, #0]
 8015612:	3301      	adds	r3, #1
 8015614:	4a1e      	ldr	r2, [pc, #120]	@ (8015690 <prvAddNewTaskToReadyList+0xd0>)
 8015616:	6013      	str	r3, [r2, #0]

		#if ( configUSE_TRACE_FACILITY == 1 )
		{
			/* Add a counter into the TCB for tracing only. */
			pxNewTCB->uxTCBNumber = uxTaskNumber;
 8015618:	4b1d      	ldr	r3, [pc, #116]	@ (8015690 <prvAddNewTaskToReadyList+0xd0>)
 801561a:	681a      	ldr	r2, [r3, #0]
 801561c:	687b      	ldr	r3, [r7, #4]
 801561e:	645a      	str	r2, [r3, #68]	@ 0x44
		}
		#endif /* configUSE_TRACE_FACILITY */
		traceTASK_CREATE( pxNewTCB );

		prvAddTaskToReadyList( pxNewTCB );
 8015620:	687b      	ldr	r3, [r7, #4]
 8015622:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8015624:	4b1b      	ldr	r3, [pc, #108]	@ (8015694 <prvAddNewTaskToReadyList+0xd4>)
 8015626:	681b      	ldr	r3, [r3, #0]
 8015628:	429a      	cmp	r2, r3
 801562a:	d903      	bls.n	8015634 <prvAddNewTaskToReadyList+0x74>
 801562c:	687b      	ldr	r3, [r7, #4]
 801562e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8015630:	4a18      	ldr	r2, [pc, #96]	@ (8015694 <prvAddNewTaskToReadyList+0xd4>)
 8015632:	6013      	str	r3, [r2, #0]
 8015634:	687b      	ldr	r3, [r7, #4]
 8015636:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8015638:	4613      	mov	r3, r2
 801563a:	009b      	lsls	r3, r3, #2
 801563c:	4413      	add	r3, r2
 801563e:	009b      	lsls	r3, r3, #2
 8015640:	4a15      	ldr	r2, [pc, #84]	@ (8015698 <prvAddNewTaskToReadyList+0xd8>)
 8015642:	441a      	add	r2, r3
 8015644:	687b      	ldr	r3, [r7, #4]
 8015646:	3304      	adds	r3, #4
 8015648:	4619      	mov	r1, r3
 801564a:	4610      	mov	r0, r2
 801564c:	f7fe fc8d 	bl	8013f6a <vListInsertEnd>

		portSETUP_TCB( pxNewTCB );
	}
	taskEXIT_CRITICAL();
 8015650:	f001 febc 	bl	80173cc <vPortExitCritical>

	if( xSchedulerRunning != pdFALSE )
 8015654:	4b0d      	ldr	r3, [pc, #52]	@ (801568c <prvAddNewTaskToReadyList+0xcc>)
 8015656:	681b      	ldr	r3, [r3, #0]
 8015658:	2b00      	cmp	r3, #0
 801565a:	d00e      	beq.n	801567a <prvAddNewTaskToReadyList+0xba>
	{
		/* If the created task is of a higher priority than the current task
		then it should run now. */
		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
 801565c:	4b0a      	ldr	r3, [pc, #40]	@ (8015688 <prvAddNewTaskToReadyList+0xc8>)
 801565e:	681b      	ldr	r3, [r3, #0]
 8015660:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8015662:	687b      	ldr	r3, [r7, #4]
 8015664:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8015666:	429a      	cmp	r2, r3
 8015668:	d207      	bcs.n	801567a <prvAddNewTaskToReadyList+0xba>
		{
			taskYIELD_IF_USING_PREEMPTION();
 801566a:	4b0c      	ldr	r3, [pc, #48]	@ (801569c <prvAddNewTaskToReadyList+0xdc>)
 801566c:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8015670:	601a      	str	r2, [r3, #0]
 8015672:	f3bf 8f4f 	dsb	sy
 8015676:	f3bf 8f6f 	isb	sy
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 801567a:	bf00      	nop
 801567c:	3708      	adds	r7, #8
 801567e:	46bd      	mov	sp, r7
 8015680:	bd80      	pop	{r7, pc}
 8015682:	bf00      	nop
 8015684:	24002b14 	.word	0x24002b14
 8015688:	24002640 	.word	0x24002640
 801568c:	24002b20 	.word	0x24002b20
 8015690:	24002b30 	.word	0x24002b30
 8015694:	24002b1c 	.word	0x24002b1c
 8015698:	24002644 	.word	0x24002644
 801569c:	e000ed04 	.word	0xe000ed04

080156a0 <vTaskDelay>:
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelay == 1 )

	void vTaskDelay( const TickType_t xTicksToDelay )
	{
 80156a0:	b580      	push	{r7, lr}
 80156a2:	b084      	sub	sp, #16
 80156a4:	af00      	add	r7, sp, #0
 80156a6:	6078      	str	r0, [r7, #4]
	BaseType_t xAlreadyYielded = pdFALSE;
 80156a8:	2300      	movs	r3, #0
 80156aa:	60fb      	str	r3, [r7, #12]

		/* A delay time of zero just forces a reschedule. */
		if( xTicksToDelay > ( TickType_t ) 0U )
 80156ac:	687b      	ldr	r3, [r7, #4]
 80156ae:	2b00      	cmp	r3, #0
 80156b0:	d018      	beq.n	80156e4 <vTaskDelay+0x44>
		{
			configASSERT( uxSchedulerSuspended == 0 );
 80156b2:	4b14      	ldr	r3, [pc, #80]	@ (8015704 <vTaskDelay+0x64>)
 80156b4:	681b      	ldr	r3, [r3, #0]
 80156b6:	2b00      	cmp	r3, #0
 80156b8:	d00b      	beq.n	80156d2 <vTaskDelay+0x32>
	__asm volatile
 80156ba:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80156be:	f383 8811 	msr	BASEPRI, r3
 80156c2:	f3bf 8f6f 	isb	sy
 80156c6:	f3bf 8f4f 	dsb	sy
 80156ca:	60bb      	str	r3, [r7, #8]
}
 80156cc:	bf00      	nop
 80156ce:	bf00      	nop
 80156d0:	e7fd      	b.n	80156ce <vTaskDelay+0x2e>
			vTaskSuspendAll();
 80156d2:	f000 f88b 	bl	80157ec <vTaskSuspendAll>
				list or removed from the blocked list until the scheduler
				is resumed.

				This task cannot be in an event list as it is the currently
				executing task. */
				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
 80156d6:	2100      	movs	r1, #0
 80156d8:	6878      	ldr	r0, [r7, #4]
 80156da:	f001 f87d 	bl	80167d8 <prvAddCurrentTaskToDelayedList>
			}
			xAlreadyYielded = xTaskResumeAll();
 80156de:	f000 f893 	bl	8015808 <xTaskResumeAll>
 80156e2:	60f8      	str	r0, [r7, #12]
			mtCOVERAGE_TEST_MARKER();
		}

		/* Force a reschedule if xTaskResumeAll has not already done so, we may
		have put ourselves to sleep. */
		if( xAlreadyYielded == pdFALSE )
 80156e4:	68fb      	ldr	r3, [r7, #12]
 80156e6:	2b00      	cmp	r3, #0
 80156e8:	d107      	bne.n	80156fa <vTaskDelay+0x5a>
		{
			portYIELD_WITHIN_API();
 80156ea:	4b07      	ldr	r3, [pc, #28]	@ (8015708 <vTaskDelay+0x68>)
 80156ec:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80156f0:	601a      	str	r2, [r3, #0]
 80156f2:	f3bf 8f4f 	dsb	sy
 80156f6:	f3bf 8f6f 	isb	sy
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
 80156fa:	bf00      	nop
 80156fc:	3710      	adds	r7, #16
 80156fe:	46bd      	mov	sp, r7
 8015700:	bd80      	pop	{r7, pc}
 8015702:	bf00      	nop
 8015704:	24002b3c 	.word	0x24002b3c
 8015708:	e000ed04 	.word	0xe000ed04

0801570c <vTaskStartScheduler>:

#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/

void vTaskStartScheduler( void )
{
 801570c:	b580      	push	{r7, lr}
 801570e:	b08a      	sub	sp, #40	@ 0x28
 8015710:	af04      	add	r7, sp, #16
BaseType_t xReturn;

	/* Add the idle task at the lowest priority. */
	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
	{
		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
 8015712:	2300      	movs	r3, #0
 8015714:	60bb      	str	r3, [r7, #8]
		StackType_t *pxIdleTaskStackBuffer = NULL;
 8015716:	2300      	movs	r3, #0
 8015718:	607b      	str	r3, [r7, #4]
		uint32_t ulIdleTaskStackSize;

		/* The Idle task is created using user provided RAM - obtain the
		address of the RAM then create the idle task. */
		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
 801571a:	463a      	mov	r2, r7
 801571c:	1d39      	adds	r1, r7, #4
 801571e:	f107 0308 	add.w	r3, r7, #8
 8015722:	4618      	mov	r0, r3
 8015724:	f7fe fbc0 	bl	8013ea8 <vApplicationGetIdleTaskMemory>
		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
 8015728:	6839      	ldr	r1, [r7, #0]
 801572a:	687b      	ldr	r3, [r7, #4]
 801572c:	68ba      	ldr	r2, [r7, #8]
 801572e:	9202      	str	r2, [sp, #8]
 8015730:	9301      	str	r3, [sp, #4]
 8015732:	2300      	movs	r3, #0
 8015734:	9300      	str	r3, [sp, #0]
 8015736:	2300      	movs	r3, #0
 8015738:	460a      	mov	r2, r1
 801573a:	4924      	ldr	r1, [pc, #144]	@ (80157cc <vTaskStartScheduler+0xc0>)
 801573c:	4824      	ldr	r0, [pc, #144]	@ (80157d0 <vTaskStartScheduler+0xc4>)
 801573e:	f7ff fdf2 	bl	8015326 <xTaskCreateStatic>
 8015742:	4603      	mov	r3, r0
 8015744:	4a23      	ldr	r2, [pc, #140]	@ (80157d4 <vTaskStartScheduler+0xc8>)
 8015746:	6013      	str	r3, [r2, #0]
												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
												pxIdleTaskStackBuffer,
												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */

		if( xIdleTaskHandle != NULL )
 8015748:	4b22      	ldr	r3, [pc, #136]	@ (80157d4 <vTaskStartScheduler+0xc8>)
 801574a:	681b      	ldr	r3, [r3, #0]
 801574c:	2b00      	cmp	r3, #0
 801574e:	d002      	beq.n	8015756 <vTaskStartScheduler+0x4a>
		{
			xReturn = pdPASS;
 8015750:	2301      	movs	r3, #1
 8015752:	617b      	str	r3, [r7, #20]
 8015754:	e001      	b.n	801575a <vTaskStartScheduler+0x4e>
		}
		else
		{
			xReturn = pdFAIL;
 8015756:	2300      	movs	r3, #0
 8015758:	617b      	str	r3, [r7, #20]
	}
	#endif /* configSUPPORT_STATIC_ALLOCATION */

	#if ( configUSE_TIMERS == 1 )
	{
		if( xReturn == pdPASS )
 801575a:	697b      	ldr	r3, [r7, #20]
 801575c:	2b01      	cmp	r3, #1
 801575e:	d102      	bne.n	8015766 <vTaskStartScheduler+0x5a>
		{
			xReturn = xTimerCreateTimerTask();
 8015760:	f001 f88e 	bl	8016880 <xTimerCreateTimerTask>
 8015764:	6178      	str	r0, [r7, #20]
			mtCOVERAGE_TEST_MARKER();
		}
	}
	#endif /* configUSE_TIMERS */

	if( xReturn == pdPASS )
 8015766:	697b      	ldr	r3, [r7, #20]
 8015768:	2b01      	cmp	r3, #1
 801576a:	d11b      	bne.n	80157a4 <vTaskStartScheduler+0x98>
	__asm volatile
 801576c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015770:	f383 8811 	msr	BASEPRI, r3
 8015774:	f3bf 8f6f 	isb	sy
 8015778:	f3bf 8f4f 	dsb	sy
 801577c:	613b      	str	r3, [r7, #16]
}
 801577e:	bf00      	nop
		{
			/* Switch Newlib's _impure_ptr variable to point to the _reent
			structure specific to the task that will run first.
			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
			for additional information. */
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
 8015780:	4b15      	ldr	r3, [pc, #84]	@ (80157d8 <vTaskStartScheduler+0xcc>)
 8015782:	681b      	ldr	r3, [r3, #0]
 8015784:	3354      	adds	r3, #84	@ 0x54
 8015786:	4a15      	ldr	r2, [pc, #84]	@ (80157dc <vTaskStartScheduler+0xd0>)
 8015788:	6013      	str	r3, [r2, #0]
		}
		#endif /* configUSE_NEWLIB_REENTRANT */

		xNextTaskUnblockTime = portMAX_DELAY;
 801578a:	4b15      	ldr	r3, [pc, #84]	@ (80157e0 <vTaskStartScheduler+0xd4>)
 801578c:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8015790:	601a      	str	r2, [r3, #0]
		xSchedulerRunning = pdTRUE;
 8015792:	4b14      	ldr	r3, [pc, #80]	@ (80157e4 <vTaskStartScheduler+0xd8>)
 8015794:	2201      	movs	r2, #1
 8015796:	601a      	str	r2, [r3, #0]
		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
 8015798:	4b13      	ldr	r3, [pc, #76]	@ (80157e8 <vTaskStartScheduler+0xdc>)
 801579a:	2200      	movs	r2, #0
 801579c:	601a      	str	r2, [r3, #0]

		traceTASK_SWITCHED_IN();

		/* Setting up the timer tick is hardware specific and thus in the
		portable interface. */
		if( xPortStartScheduler() != pdFALSE )
 801579e:	f001 fd3f 	bl	8017220 <xPortStartScheduler>
	}

	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
	meaning xIdleTaskHandle is not used anywhere else. */
	( void ) xIdleTaskHandle;
}
 80157a2:	e00f      	b.n	80157c4 <vTaskStartScheduler+0xb8>
		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
 80157a4:	697b      	ldr	r3, [r7, #20]
 80157a6:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80157aa:	d10b      	bne.n	80157c4 <vTaskStartScheduler+0xb8>
	__asm volatile
 80157ac:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80157b0:	f383 8811 	msr	BASEPRI, r3
 80157b4:	f3bf 8f6f 	isb	sy
 80157b8:	f3bf 8f4f 	dsb	sy
 80157bc:	60fb      	str	r3, [r7, #12]
}
 80157be:	bf00      	nop
 80157c0:	bf00      	nop
 80157c2:	e7fd      	b.n	80157c0 <vTaskStartScheduler+0xb4>
}
 80157c4:	bf00      	nop
 80157c6:	3718      	adds	r7, #24
 80157c8:	46bd      	mov	sp, r7
 80157ca:	bd80      	pop	{r7, pc}
 80157cc:	080189ac 	.word	0x080189ac
 80157d0:	08015e89 	.word	0x08015e89
 80157d4:	24002b38 	.word	0x24002b38
 80157d8:	24002640 	.word	0x24002640
 80157dc:	24000054 	.word	0x24000054
 80157e0:	24002b34 	.word	0x24002b34
 80157e4:	24002b20 	.word	0x24002b20
 80157e8:	24002b18 	.word	0x24002b18

080157ec <vTaskSuspendAll>:
	vPortEndScheduler();
}
/*----------------------------------------------------------*/

void vTaskSuspendAll( void )
{
 80157ec:	b480      	push	{r7}
 80157ee:	af00      	add	r7, sp, #0
	do not otherwise exhibit real time behaviour. */
	portSOFTWARE_BARRIER();

	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
	is used to allow calls to vTaskSuspendAll() to nest. */
	++uxSchedulerSuspended;
 80157f0:	4b04      	ldr	r3, [pc, #16]	@ (8015804 <vTaskSuspendAll+0x18>)
 80157f2:	681b      	ldr	r3, [r3, #0]
 80157f4:	3301      	adds	r3, #1
 80157f6:	4a03      	ldr	r2, [pc, #12]	@ (8015804 <vTaskSuspendAll+0x18>)
 80157f8:	6013      	str	r3, [r2, #0]

	/* Enforces ordering for ports and optimised compilers that may otherwise place
	the above increment elsewhere. */
	portMEMORY_BARRIER();
}
 80157fa:	bf00      	nop
 80157fc:	46bd      	mov	sp, r7
 80157fe:	f85d 7b04 	ldr.w	r7, [sp], #4
 8015802:	4770      	bx	lr
 8015804:	24002b3c 	.word	0x24002b3c

08015808 <xTaskResumeAll>:

#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/

BaseType_t xTaskResumeAll( void )
{
 8015808:	b580      	push	{r7, lr}
 801580a:	b084      	sub	sp, #16
 801580c:	af00      	add	r7, sp, #0
TCB_t *pxTCB = NULL;
 801580e:	2300      	movs	r3, #0
 8015810:	60fb      	str	r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
 8015812:	2300      	movs	r3, #0
 8015814:	60bb      	str	r3, [r7, #8]

	/* If uxSchedulerSuspended is zero then this function does not match a
	previous call to vTaskSuspendAll(). */
	configASSERT( uxSchedulerSuspended );
 8015816:	4b42      	ldr	r3, [pc, #264]	@ (8015920 <xTaskResumeAll+0x118>)
 8015818:	681b      	ldr	r3, [r3, #0]
 801581a:	2b00      	cmp	r3, #0
 801581c:	d10b      	bne.n	8015836 <xTaskResumeAll+0x2e>
	__asm volatile
 801581e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015822:	f383 8811 	msr	BASEPRI, r3
 8015826:	f3bf 8f6f 	isb	sy
 801582a:	f3bf 8f4f 	dsb	sy
 801582e:	603b      	str	r3, [r7, #0]
}
 8015830:	bf00      	nop
 8015832:	bf00      	nop
 8015834:	e7fd      	b.n	8015832 <xTaskResumeAll+0x2a>
	/* It is possible that an ISR caused a task to be removed from an event
	list while the scheduler was suspended.  If this was the case then the
	removed task will have been added to the xPendingReadyList.  Once the
	scheduler has been resumed it is safe to move all the pending ready
	tasks from this list into their appropriate ready list. */
	taskENTER_CRITICAL();
 8015836:	f001 fd97 	bl	8017368 <vPortEnterCritical>
	{
		--uxSchedulerSuspended;
 801583a:	4b39      	ldr	r3, [pc, #228]	@ (8015920 <xTaskResumeAll+0x118>)
 801583c:	681b      	ldr	r3, [r3, #0]
 801583e:	3b01      	subs	r3, #1
 8015840:	4a37      	ldr	r2, [pc, #220]	@ (8015920 <xTaskResumeAll+0x118>)
 8015842:	6013      	str	r3, [r2, #0]

		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8015844:	4b36      	ldr	r3, [pc, #216]	@ (8015920 <xTaskResumeAll+0x118>)
 8015846:	681b      	ldr	r3, [r3, #0]
 8015848:	2b00      	cmp	r3, #0
 801584a:	d162      	bne.n	8015912 <xTaskResumeAll+0x10a>
		{
			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
 801584c:	4b35      	ldr	r3, [pc, #212]	@ (8015924 <xTaskResumeAll+0x11c>)
 801584e:	681b      	ldr	r3, [r3, #0]
 8015850:	2b00      	cmp	r3, #0
 8015852:	d05e      	beq.n	8015912 <xTaskResumeAll+0x10a>
			{
				/* Move any readied tasks from the pending list into the
				appropriate ready list. */
				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 8015854:	e02f      	b.n	80158b6 <xTaskResumeAll+0xae>
				{
					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8015856:	4b34      	ldr	r3, [pc, #208]	@ (8015928 <xTaskResumeAll+0x120>)
 8015858:	68db      	ldr	r3, [r3, #12]
 801585a:	68db      	ldr	r3, [r3, #12]
 801585c:	60fb      	str	r3, [r7, #12]
					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 801585e:	68fb      	ldr	r3, [r7, #12]
 8015860:	3318      	adds	r3, #24
 8015862:	4618      	mov	r0, r3
 8015864:	f7fe fbde 	bl	8014024 <uxListRemove>
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8015868:	68fb      	ldr	r3, [r7, #12]
 801586a:	3304      	adds	r3, #4
 801586c:	4618      	mov	r0, r3
 801586e:	f7fe fbd9 	bl	8014024 <uxListRemove>
					prvAddTaskToReadyList( pxTCB );
 8015872:	68fb      	ldr	r3, [r7, #12]
 8015874:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8015876:	4b2d      	ldr	r3, [pc, #180]	@ (801592c <xTaskResumeAll+0x124>)
 8015878:	681b      	ldr	r3, [r3, #0]
 801587a:	429a      	cmp	r2, r3
 801587c:	d903      	bls.n	8015886 <xTaskResumeAll+0x7e>
 801587e:	68fb      	ldr	r3, [r7, #12]
 8015880:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8015882:	4a2a      	ldr	r2, [pc, #168]	@ (801592c <xTaskResumeAll+0x124>)
 8015884:	6013      	str	r3, [r2, #0]
 8015886:	68fb      	ldr	r3, [r7, #12]
 8015888:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 801588a:	4613      	mov	r3, r2
 801588c:	009b      	lsls	r3, r3, #2
 801588e:	4413      	add	r3, r2
 8015890:	009b      	lsls	r3, r3, #2
 8015892:	4a27      	ldr	r2, [pc, #156]	@ (8015930 <xTaskResumeAll+0x128>)
 8015894:	441a      	add	r2, r3
 8015896:	68fb      	ldr	r3, [r7, #12]
 8015898:	3304      	adds	r3, #4
 801589a:	4619      	mov	r1, r3
 801589c:	4610      	mov	r0, r2
 801589e:	f7fe fb64 	bl	8013f6a <vListInsertEnd>

					/* If the moved task has a priority higher than the current
					task then a yield must be performed. */
					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 80158a2:	68fb      	ldr	r3, [r7, #12]
 80158a4:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80158a6:	4b23      	ldr	r3, [pc, #140]	@ (8015934 <xTaskResumeAll+0x12c>)
 80158a8:	681b      	ldr	r3, [r3, #0]
 80158aa:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80158ac:	429a      	cmp	r2, r3
 80158ae:	d302      	bcc.n	80158b6 <xTaskResumeAll+0xae>
					{
						xYieldPending = pdTRUE;
 80158b0:	4b21      	ldr	r3, [pc, #132]	@ (8015938 <xTaskResumeAll+0x130>)
 80158b2:	2201      	movs	r2, #1
 80158b4:	601a      	str	r2, [r3, #0]
				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 80158b6:	4b1c      	ldr	r3, [pc, #112]	@ (8015928 <xTaskResumeAll+0x120>)
 80158b8:	681b      	ldr	r3, [r3, #0]
 80158ba:	2b00      	cmp	r3, #0
 80158bc:	d1cb      	bne.n	8015856 <xTaskResumeAll+0x4e>
					{
						mtCOVERAGE_TEST_MARKER();
					}
				}

				if( pxTCB != NULL )
 80158be:	68fb      	ldr	r3, [r7, #12]
 80158c0:	2b00      	cmp	r3, #0
 80158c2:	d001      	beq.n	80158c8 <xTaskResumeAll+0xc0>
					which may have prevented the next unblock time from being
					re-calculated, in which case re-calculate it now.  Mainly
					important for low power tickless implementations, where
					this can prevent an unnecessary exit from low power
					state. */
					prvResetNextTaskUnblockTime();
 80158c4:	f000 fb9c 	bl	8016000 <prvResetNextTaskUnblockTime>
				/* If any ticks occurred while the scheduler was suspended then
				they should be processed now.  This ensures the tick count does
				not	slip, and that any delayed tasks are resumed at the correct
				time. */
				{
					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
 80158c8:	4b1c      	ldr	r3, [pc, #112]	@ (801593c <xTaskResumeAll+0x134>)
 80158ca:	681b      	ldr	r3, [r3, #0]
 80158cc:	607b      	str	r3, [r7, #4]

					if( xPendedCounts > ( TickType_t ) 0U )
 80158ce:	687b      	ldr	r3, [r7, #4]
 80158d0:	2b00      	cmp	r3, #0
 80158d2:	d010      	beq.n	80158f6 <xTaskResumeAll+0xee>
					{
						do
						{
							if( xTaskIncrementTick() != pdFALSE )
 80158d4:	f000 f846 	bl	8015964 <xTaskIncrementTick>
 80158d8:	4603      	mov	r3, r0
 80158da:	2b00      	cmp	r3, #0
 80158dc:	d002      	beq.n	80158e4 <xTaskResumeAll+0xdc>
							{
								xYieldPending = pdTRUE;
 80158de:	4b16      	ldr	r3, [pc, #88]	@ (8015938 <xTaskResumeAll+0x130>)
 80158e0:	2201      	movs	r2, #1
 80158e2:	601a      	str	r2, [r3, #0]
							}
							else
							{
								mtCOVERAGE_TEST_MARKER();
							}
							--xPendedCounts;
 80158e4:	687b      	ldr	r3, [r7, #4]
 80158e6:	3b01      	subs	r3, #1
 80158e8:	607b      	str	r3, [r7, #4]
						} while( xPendedCounts > ( TickType_t ) 0U );
 80158ea:	687b      	ldr	r3, [r7, #4]
 80158ec:	2b00      	cmp	r3, #0
 80158ee:	d1f1      	bne.n	80158d4 <xTaskResumeAll+0xcc>

						xPendedTicks = 0;
 80158f0:	4b12      	ldr	r3, [pc, #72]	@ (801593c <xTaskResumeAll+0x134>)
 80158f2:	2200      	movs	r2, #0
 80158f4:	601a      	str	r2, [r3, #0]
					{
						mtCOVERAGE_TEST_MARKER();
					}
				}

				if( xYieldPending != pdFALSE )
 80158f6:	4b10      	ldr	r3, [pc, #64]	@ (8015938 <xTaskResumeAll+0x130>)
 80158f8:	681b      	ldr	r3, [r3, #0]
 80158fa:	2b00      	cmp	r3, #0
 80158fc:	d009      	beq.n	8015912 <xTaskResumeAll+0x10a>
				{
					#if( configUSE_PREEMPTION != 0 )
					{
						xAlreadyYielded = pdTRUE;
 80158fe:	2301      	movs	r3, #1
 8015900:	60bb      	str	r3, [r7, #8]
					}
					#endif
					taskYIELD_IF_USING_PREEMPTION();
 8015902:	4b0f      	ldr	r3, [pc, #60]	@ (8015940 <xTaskResumeAll+0x138>)
 8015904:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8015908:	601a      	str	r2, [r3, #0]
 801590a:	f3bf 8f4f 	dsb	sy
 801590e:	f3bf 8f6f 	isb	sy
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
	taskEXIT_CRITICAL();
 8015912:	f001 fd5b 	bl	80173cc <vPortExitCritical>

	return xAlreadyYielded;
 8015916:	68bb      	ldr	r3, [r7, #8]
}
 8015918:	4618      	mov	r0, r3
 801591a:	3710      	adds	r7, #16
 801591c:	46bd      	mov	sp, r7
 801591e:	bd80      	pop	{r7, pc}
 8015920:	24002b3c 	.word	0x24002b3c
 8015924:	24002b14 	.word	0x24002b14
 8015928:	24002ad4 	.word	0x24002ad4
 801592c:	24002b1c 	.word	0x24002b1c
 8015930:	24002644 	.word	0x24002644
 8015934:	24002640 	.word	0x24002640
 8015938:	24002b28 	.word	0x24002b28
 801593c:	24002b24 	.word	0x24002b24
 8015940:	e000ed04 	.word	0xe000ed04

08015944 <xTaskGetTickCount>:
/*-----------------------------------------------------------*/

TickType_t xTaskGetTickCount( void )
{
 8015944:	b480      	push	{r7}
 8015946:	b083      	sub	sp, #12
 8015948:	af00      	add	r7, sp, #0
TickType_t xTicks;

	/* Critical section required if running on a 16 bit processor. */
	portTICK_TYPE_ENTER_CRITICAL();
	{
		xTicks = xTickCount;
 801594a:	4b05      	ldr	r3, [pc, #20]	@ (8015960 <xTaskGetTickCount+0x1c>)
 801594c:	681b      	ldr	r3, [r3, #0]
 801594e:	607b      	str	r3, [r7, #4]
	}
	portTICK_TYPE_EXIT_CRITICAL();

	return xTicks;
 8015950:	687b      	ldr	r3, [r7, #4]
}
 8015952:	4618      	mov	r0, r3
 8015954:	370c      	adds	r7, #12
 8015956:	46bd      	mov	sp, r7
 8015958:	f85d 7b04 	ldr.w	r7, [sp], #4
 801595c:	4770      	bx	lr
 801595e:	bf00      	nop
 8015960:	24002b18 	.word	0x24002b18

08015964 <xTaskIncrementTick>:

#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/

BaseType_t xTaskIncrementTick( void )
{
 8015964:	b580      	push	{r7, lr}
 8015966:	b086      	sub	sp, #24
 8015968:	af00      	add	r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
 801596a:	2300      	movs	r3, #0
 801596c:	617b      	str	r3, [r7, #20]

	/* Called by the portable layer each time a tick interrupt occurs.
	Increments the tick then checks to see if the new tick value will cause any
	tasks to be unblocked. */
	traceTASK_INCREMENT_TICK( xTickCount );
	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 801596e:	4b4f      	ldr	r3, [pc, #316]	@ (8015aac <xTaskIncrementTick+0x148>)
 8015970:	681b      	ldr	r3, [r3, #0]
 8015972:	2b00      	cmp	r3, #0
 8015974:	f040 8090 	bne.w	8015a98 <xTaskIncrementTick+0x134>
	{
		/* Minor optimisation.  The tick count cannot change in this
		block. */
		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
 8015978:	4b4d      	ldr	r3, [pc, #308]	@ (8015ab0 <xTaskIncrementTick+0x14c>)
 801597a:	681b      	ldr	r3, [r3, #0]
 801597c:	3301      	adds	r3, #1
 801597e:	613b      	str	r3, [r7, #16]

		/* Increment the RTOS tick, switching the delayed and overflowed
		delayed lists if it wraps to 0. */
		xTickCount = xConstTickCount;
 8015980:	4a4b      	ldr	r2, [pc, #300]	@ (8015ab0 <xTaskIncrementTick+0x14c>)
 8015982:	693b      	ldr	r3, [r7, #16]
 8015984:	6013      	str	r3, [r2, #0]

		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
 8015986:	693b      	ldr	r3, [r7, #16]
 8015988:	2b00      	cmp	r3, #0
 801598a:	d121      	bne.n	80159d0 <xTaskIncrementTick+0x6c>
		{
			taskSWITCH_DELAYED_LISTS();
 801598c:	4b49      	ldr	r3, [pc, #292]	@ (8015ab4 <xTaskIncrementTick+0x150>)
 801598e:	681b      	ldr	r3, [r3, #0]
 8015990:	681b      	ldr	r3, [r3, #0]
 8015992:	2b00      	cmp	r3, #0
 8015994:	d00b      	beq.n	80159ae <xTaskIncrementTick+0x4a>
	__asm volatile
 8015996:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801599a:	f383 8811 	msr	BASEPRI, r3
 801599e:	f3bf 8f6f 	isb	sy
 80159a2:	f3bf 8f4f 	dsb	sy
 80159a6:	603b      	str	r3, [r7, #0]
}
 80159a8:	bf00      	nop
 80159aa:	bf00      	nop
 80159ac:	e7fd      	b.n	80159aa <xTaskIncrementTick+0x46>
 80159ae:	4b41      	ldr	r3, [pc, #260]	@ (8015ab4 <xTaskIncrementTick+0x150>)
 80159b0:	681b      	ldr	r3, [r3, #0]
 80159b2:	60fb      	str	r3, [r7, #12]
 80159b4:	4b40      	ldr	r3, [pc, #256]	@ (8015ab8 <xTaskIncrementTick+0x154>)
 80159b6:	681b      	ldr	r3, [r3, #0]
 80159b8:	4a3e      	ldr	r2, [pc, #248]	@ (8015ab4 <xTaskIncrementTick+0x150>)
 80159ba:	6013      	str	r3, [r2, #0]
 80159bc:	4a3e      	ldr	r2, [pc, #248]	@ (8015ab8 <xTaskIncrementTick+0x154>)
 80159be:	68fb      	ldr	r3, [r7, #12]
 80159c0:	6013      	str	r3, [r2, #0]
 80159c2:	4b3e      	ldr	r3, [pc, #248]	@ (8015abc <xTaskIncrementTick+0x158>)
 80159c4:	681b      	ldr	r3, [r3, #0]
 80159c6:	3301      	adds	r3, #1
 80159c8:	4a3c      	ldr	r2, [pc, #240]	@ (8015abc <xTaskIncrementTick+0x158>)
 80159ca:	6013      	str	r3, [r2, #0]
 80159cc:	f000 fb18 	bl	8016000 <prvResetNextTaskUnblockTime>

		/* See if this tick has made a timeout expire.  Tasks are stored in
		the	queue in the order of their wake time - meaning once one task
		has been found whose block time has not expired there is no need to
		look any further down the list. */
		if( xConstTickCount >= xNextTaskUnblockTime )
 80159d0:	4b3b      	ldr	r3, [pc, #236]	@ (8015ac0 <xTaskIncrementTick+0x15c>)
 80159d2:	681b      	ldr	r3, [r3, #0]
 80159d4:	693a      	ldr	r2, [r7, #16]
 80159d6:	429a      	cmp	r2, r3
 80159d8:	d349      	bcc.n	8015a6e <xTaskIncrementTick+0x10a>
		{
			for( ;; )
			{
				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 80159da:	4b36      	ldr	r3, [pc, #216]	@ (8015ab4 <xTaskIncrementTick+0x150>)
 80159dc:	681b      	ldr	r3, [r3, #0]
 80159de:	681b      	ldr	r3, [r3, #0]
 80159e0:	2b00      	cmp	r3, #0
 80159e2:	d104      	bne.n	80159ee <xTaskIncrementTick+0x8a>
					/* The delayed list is empty.  Set xNextTaskUnblockTime
					to the maximum possible value so it is extremely
					unlikely that the
					if( xTickCount >= xNextTaskUnblockTime ) test will pass
					next time through. */
					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80159e4:	4b36      	ldr	r3, [pc, #216]	@ (8015ac0 <xTaskIncrementTick+0x15c>)
 80159e6:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 80159ea:	601a      	str	r2, [r3, #0]
					break;
 80159ec:	e03f      	b.n	8015a6e <xTaskIncrementTick+0x10a>
				{
					/* The delayed list is not empty, get the value of the
					item at the head of the delayed list.  This is the time
					at which the task at the head of the delayed list must
					be removed from the Blocked state. */
					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80159ee:	4b31      	ldr	r3, [pc, #196]	@ (8015ab4 <xTaskIncrementTick+0x150>)
 80159f0:	681b      	ldr	r3, [r3, #0]
 80159f2:	68db      	ldr	r3, [r3, #12]
 80159f4:	68db      	ldr	r3, [r3, #12]
 80159f6:	60bb      	str	r3, [r7, #8]
					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
 80159f8:	68bb      	ldr	r3, [r7, #8]
 80159fa:	685b      	ldr	r3, [r3, #4]
 80159fc:	607b      	str	r3, [r7, #4]

					if( xConstTickCount < xItemValue )
 80159fe:	693a      	ldr	r2, [r7, #16]
 8015a00:	687b      	ldr	r3, [r7, #4]
 8015a02:	429a      	cmp	r2, r3
 8015a04:	d203      	bcs.n	8015a0e <xTaskIncrementTick+0xaa>
						/* It is not time to unblock this item yet, but the
						item value is the time at which the task at the head
						of the blocked list must be removed from the Blocked
						state -	so record the item value in
						xNextTaskUnblockTime. */
						xNextTaskUnblockTime = xItemValue;
 8015a06:	4a2e      	ldr	r2, [pc, #184]	@ (8015ac0 <xTaskIncrementTick+0x15c>)
 8015a08:	687b      	ldr	r3, [r7, #4]
 8015a0a:	6013      	str	r3, [r2, #0]
						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
 8015a0c:	e02f      	b.n	8015a6e <xTaskIncrementTick+0x10a>
					{
						mtCOVERAGE_TEST_MARKER();
					}

					/* It is time to remove the item from the Blocked state. */
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8015a0e:	68bb      	ldr	r3, [r7, #8]
 8015a10:	3304      	adds	r3, #4
 8015a12:	4618      	mov	r0, r3
 8015a14:	f7fe fb06 	bl	8014024 <uxListRemove>

					/* Is the task waiting on an event also?  If so remove
					it from the event list. */
					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
 8015a18:	68bb      	ldr	r3, [r7, #8]
 8015a1a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8015a1c:	2b00      	cmp	r3, #0
 8015a1e:	d004      	beq.n	8015a2a <xTaskIncrementTick+0xc6>
					{
						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 8015a20:	68bb      	ldr	r3, [r7, #8]
 8015a22:	3318      	adds	r3, #24
 8015a24:	4618      	mov	r0, r3
 8015a26:	f7fe fafd 	bl	8014024 <uxListRemove>
						mtCOVERAGE_TEST_MARKER();
					}

					/* Place the unblocked task into the appropriate ready
					list. */
					prvAddTaskToReadyList( pxTCB );
 8015a2a:	68bb      	ldr	r3, [r7, #8]
 8015a2c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8015a2e:	4b25      	ldr	r3, [pc, #148]	@ (8015ac4 <xTaskIncrementTick+0x160>)
 8015a30:	681b      	ldr	r3, [r3, #0]
 8015a32:	429a      	cmp	r2, r3
 8015a34:	d903      	bls.n	8015a3e <xTaskIncrementTick+0xda>
 8015a36:	68bb      	ldr	r3, [r7, #8]
 8015a38:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8015a3a:	4a22      	ldr	r2, [pc, #136]	@ (8015ac4 <xTaskIncrementTick+0x160>)
 8015a3c:	6013      	str	r3, [r2, #0]
 8015a3e:	68bb      	ldr	r3, [r7, #8]
 8015a40:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8015a42:	4613      	mov	r3, r2
 8015a44:	009b      	lsls	r3, r3, #2
 8015a46:	4413      	add	r3, r2
 8015a48:	009b      	lsls	r3, r3, #2
 8015a4a:	4a1f      	ldr	r2, [pc, #124]	@ (8015ac8 <xTaskIncrementTick+0x164>)
 8015a4c:	441a      	add	r2, r3
 8015a4e:	68bb      	ldr	r3, [r7, #8]
 8015a50:	3304      	adds	r3, #4
 8015a52:	4619      	mov	r1, r3
 8015a54:	4610      	mov	r0, r2
 8015a56:	f7fe fa88 	bl	8013f6a <vListInsertEnd>
					{
						/* Preemption is on, but a context switch should
						only be performed if the unblocked task has a
						priority that is equal to or higher than the
						currently executing task. */
						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 8015a5a:	68bb      	ldr	r3, [r7, #8]
 8015a5c:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8015a5e:	4b1b      	ldr	r3, [pc, #108]	@ (8015acc <xTaskIncrementTick+0x168>)
 8015a60:	681b      	ldr	r3, [r3, #0]
 8015a62:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8015a64:	429a      	cmp	r2, r3
 8015a66:	d3b8      	bcc.n	80159da <xTaskIncrementTick+0x76>
						{
							xSwitchRequired = pdTRUE;
 8015a68:	2301      	movs	r3, #1
 8015a6a:	617b      	str	r3, [r7, #20]
				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 8015a6c:	e7b5      	b.n	80159da <xTaskIncrementTick+0x76>
		/* Tasks of equal priority to the currently running task will share
		processing time (time slice) if preemption is on, and the application
		writer has not explicitly turned time slicing off. */
		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
		{
			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
 8015a6e:	4b17      	ldr	r3, [pc, #92]	@ (8015acc <xTaskIncrementTick+0x168>)
 8015a70:	681b      	ldr	r3, [r3, #0]
 8015a72:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8015a74:	4914      	ldr	r1, [pc, #80]	@ (8015ac8 <xTaskIncrementTick+0x164>)
 8015a76:	4613      	mov	r3, r2
 8015a78:	009b      	lsls	r3, r3, #2
 8015a7a:	4413      	add	r3, r2
 8015a7c:	009b      	lsls	r3, r3, #2
 8015a7e:	440b      	add	r3, r1
 8015a80:	681b      	ldr	r3, [r3, #0]
 8015a82:	2b01      	cmp	r3, #1
 8015a84:	d901      	bls.n	8015a8a <xTaskIncrementTick+0x126>
			{
				xSwitchRequired = pdTRUE;
 8015a86:	2301      	movs	r3, #1
 8015a88:	617b      	str	r3, [r7, #20]
		}
		#endif /* configUSE_TICK_HOOK */

		#if ( configUSE_PREEMPTION == 1 )
		{
			if( xYieldPending != pdFALSE )
 8015a8a:	4b11      	ldr	r3, [pc, #68]	@ (8015ad0 <xTaskIncrementTick+0x16c>)
 8015a8c:	681b      	ldr	r3, [r3, #0]
 8015a8e:	2b00      	cmp	r3, #0
 8015a90:	d007      	beq.n	8015aa2 <xTaskIncrementTick+0x13e>
			{
				xSwitchRequired = pdTRUE;
 8015a92:	2301      	movs	r3, #1
 8015a94:	617b      	str	r3, [r7, #20]
 8015a96:	e004      	b.n	8015aa2 <xTaskIncrementTick+0x13e>
		}
		#endif /* configUSE_PREEMPTION */
	}
	else
	{
		++xPendedTicks;
 8015a98:	4b0e      	ldr	r3, [pc, #56]	@ (8015ad4 <xTaskIncrementTick+0x170>)
 8015a9a:	681b      	ldr	r3, [r3, #0]
 8015a9c:	3301      	adds	r3, #1
 8015a9e:	4a0d      	ldr	r2, [pc, #52]	@ (8015ad4 <xTaskIncrementTick+0x170>)
 8015aa0:	6013      	str	r3, [r2, #0]
			vApplicationTickHook();
		}
		#endif
	}

	return xSwitchRequired;
 8015aa2:	697b      	ldr	r3, [r7, #20]
}
 8015aa4:	4618      	mov	r0, r3
 8015aa6:	3718      	adds	r7, #24
 8015aa8:	46bd      	mov	sp, r7
 8015aaa:	bd80      	pop	{r7, pc}
 8015aac:	24002b3c 	.word	0x24002b3c
 8015ab0:	24002b18 	.word	0x24002b18
 8015ab4:	24002acc 	.word	0x24002acc
 8015ab8:	24002ad0 	.word	0x24002ad0
 8015abc:	24002b2c 	.word	0x24002b2c
 8015ac0:	24002b34 	.word	0x24002b34
 8015ac4:	24002b1c 	.word	0x24002b1c
 8015ac8:	24002644 	.word	0x24002644
 8015acc:	24002640 	.word	0x24002640
 8015ad0:	24002b28 	.word	0x24002b28
 8015ad4:	24002b24 	.word	0x24002b24

08015ad8 <vTaskSwitchContext>:

#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/

void vTaskSwitchContext( void )
{
 8015ad8:	b580      	push	{r7, lr}
 8015ada:	b084      	sub	sp, #16
 8015adc:	af00      	add	r7, sp, #0
	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
 8015ade:	4b32      	ldr	r3, [pc, #200]	@ (8015ba8 <vTaskSwitchContext+0xd0>)
 8015ae0:	681b      	ldr	r3, [r3, #0]
 8015ae2:	2b00      	cmp	r3, #0
 8015ae4:	d003      	beq.n	8015aee <vTaskSwitchContext+0x16>
	{
		/* The scheduler is currently suspended - do not allow a context
		switch. */
		xYieldPending = pdTRUE;
 8015ae6:	4b31      	ldr	r3, [pc, #196]	@ (8015bac <vTaskSwitchContext+0xd4>)
 8015ae8:	2201      	movs	r2, #1
 8015aea:	601a      	str	r2, [r3, #0]
			for additional information. */
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
		}
		#endif /* configUSE_NEWLIB_REENTRANT */
	}
}
 8015aec:	e058      	b.n	8015ba0 <vTaskSwitchContext+0xc8>
		xYieldPending = pdFALSE;
 8015aee:	4b2f      	ldr	r3, [pc, #188]	@ (8015bac <vTaskSwitchContext+0xd4>)
 8015af0:	2200      	movs	r2, #0
 8015af2:	601a      	str	r2, [r3, #0]
		taskCHECK_FOR_STACK_OVERFLOW();
 8015af4:	4b2e      	ldr	r3, [pc, #184]	@ (8015bb0 <vTaskSwitchContext+0xd8>)
 8015af6:	681b      	ldr	r3, [r3, #0]
 8015af8:	681a      	ldr	r2, [r3, #0]
 8015afa:	4b2d      	ldr	r3, [pc, #180]	@ (8015bb0 <vTaskSwitchContext+0xd8>)
 8015afc:	681b      	ldr	r3, [r3, #0]
 8015afe:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8015b00:	429a      	cmp	r2, r3
 8015b02:	d808      	bhi.n	8015b16 <vTaskSwitchContext+0x3e>
 8015b04:	4b2a      	ldr	r3, [pc, #168]	@ (8015bb0 <vTaskSwitchContext+0xd8>)
 8015b06:	681a      	ldr	r2, [r3, #0]
 8015b08:	4b29      	ldr	r3, [pc, #164]	@ (8015bb0 <vTaskSwitchContext+0xd8>)
 8015b0a:	681b      	ldr	r3, [r3, #0]
 8015b0c:	3334      	adds	r3, #52	@ 0x34
 8015b0e:	4619      	mov	r1, r3
 8015b10:	4610      	mov	r0, r2
 8015b12:	f7ea fdad 	bl	8000670 <vApplicationStackOverflowHook>
		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8015b16:	4b27      	ldr	r3, [pc, #156]	@ (8015bb4 <vTaskSwitchContext+0xdc>)
 8015b18:	681b      	ldr	r3, [r3, #0]
 8015b1a:	60fb      	str	r3, [r7, #12]
 8015b1c:	e011      	b.n	8015b42 <vTaskSwitchContext+0x6a>
 8015b1e:	68fb      	ldr	r3, [r7, #12]
 8015b20:	2b00      	cmp	r3, #0
 8015b22:	d10b      	bne.n	8015b3c <vTaskSwitchContext+0x64>
	__asm volatile
 8015b24:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015b28:	f383 8811 	msr	BASEPRI, r3
 8015b2c:	f3bf 8f6f 	isb	sy
 8015b30:	f3bf 8f4f 	dsb	sy
 8015b34:	607b      	str	r3, [r7, #4]
}
 8015b36:	bf00      	nop
 8015b38:	bf00      	nop
 8015b3a:	e7fd      	b.n	8015b38 <vTaskSwitchContext+0x60>
 8015b3c:	68fb      	ldr	r3, [r7, #12]
 8015b3e:	3b01      	subs	r3, #1
 8015b40:	60fb      	str	r3, [r7, #12]
 8015b42:	491d      	ldr	r1, [pc, #116]	@ (8015bb8 <vTaskSwitchContext+0xe0>)
 8015b44:	68fa      	ldr	r2, [r7, #12]
 8015b46:	4613      	mov	r3, r2
 8015b48:	009b      	lsls	r3, r3, #2
 8015b4a:	4413      	add	r3, r2
 8015b4c:	009b      	lsls	r3, r3, #2
 8015b4e:	440b      	add	r3, r1
 8015b50:	681b      	ldr	r3, [r3, #0]
 8015b52:	2b00      	cmp	r3, #0
 8015b54:	d0e3      	beq.n	8015b1e <vTaskSwitchContext+0x46>
 8015b56:	68fa      	ldr	r2, [r7, #12]
 8015b58:	4613      	mov	r3, r2
 8015b5a:	009b      	lsls	r3, r3, #2
 8015b5c:	4413      	add	r3, r2
 8015b5e:	009b      	lsls	r3, r3, #2
 8015b60:	4a15      	ldr	r2, [pc, #84]	@ (8015bb8 <vTaskSwitchContext+0xe0>)
 8015b62:	4413      	add	r3, r2
 8015b64:	60bb      	str	r3, [r7, #8]
 8015b66:	68bb      	ldr	r3, [r7, #8]
 8015b68:	685b      	ldr	r3, [r3, #4]
 8015b6a:	685a      	ldr	r2, [r3, #4]
 8015b6c:	68bb      	ldr	r3, [r7, #8]
 8015b6e:	605a      	str	r2, [r3, #4]
 8015b70:	68bb      	ldr	r3, [r7, #8]
 8015b72:	685a      	ldr	r2, [r3, #4]
 8015b74:	68bb      	ldr	r3, [r7, #8]
 8015b76:	3308      	adds	r3, #8
 8015b78:	429a      	cmp	r2, r3
 8015b7a:	d104      	bne.n	8015b86 <vTaskSwitchContext+0xae>
 8015b7c:	68bb      	ldr	r3, [r7, #8]
 8015b7e:	685b      	ldr	r3, [r3, #4]
 8015b80:	685a      	ldr	r2, [r3, #4]
 8015b82:	68bb      	ldr	r3, [r7, #8]
 8015b84:	605a      	str	r2, [r3, #4]
 8015b86:	68bb      	ldr	r3, [r7, #8]
 8015b88:	685b      	ldr	r3, [r3, #4]
 8015b8a:	68db      	ldr	r3, [r3, #12]
 8015b8c:	4a08      	ldr	r2, [pc, #32]	@ (8015bb0 <vTaskSwitchContext+0xd8>)
 8015b8e:	6013      	str	r3, [r2, #0]
 8015b90:	4a08      	ldr	r2, [pc, #32]	@ (8015bb4 <vTaskSwitchContext+0xdc>)
 8015b92:	68fb      	ldr	r3, [r7, #12]
 8015b94:	6013      	str	r3, [r2, #0]
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
 8015b96:	4b06      	ldr	r3, [pc, #24]	@ (8015bb0 <vTaskSwitchContext+0xd8>)
 8015b98:	681b      	ldr	r3, [r3, #0]
 8015b9a:	3354      	adds	r3, #84	@ 0x54
 8015b9c:	4a07      	ldr	r2, [pc, #28]	@ (8015bbc <vTaskSwitchContext+0xe4>)
 8015b9e:	6013      	str	r3, [r2, #0]
}
 8015ba0:	bf00      	nop
 8015ba2:	3710      	adds	r7, #16
 8015ba4:	46bd      	mov	sp, r7
 8015ba6:	bd80      	pop	{r7, pc}
 8015ba8:	24002b3c 	.word	0x24002b3c
 8015bac:	24002b28 	.word	0x24002b28
 8015bb0:	24002640 	.word	0x24002640
 8015bb4:	24002b1c 	.word	0x24002b1c
 8015bb8:	24002644 	.word	0x24002644
 8015bbc:	24000054 	.word	0x24000054

08015bc0 <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/

void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
 8015bc0:	b580      	push	{r7, lr}
 8015bc2:	b084      	sub	sp, #16
 8015bc4:	af00      	add	r7, sp, #0
 8015bc6:	6078      	str	r0, [r7, #4]
 8015bc8:	6039      	str	r1, [r7, #0]
	configASSERT( pxEventList );
 8015bca:	687b      	ldr	r3, [r7, #4]
 8015bcc:	2b00      	cmp	r3, #0
 8015bce:	d10b      	bne.n	8015be8 <vTaskPlaceOnEventList+0x28>
	__asm volatile
 8015bd0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015bd4:	f383 8811 	msr	BASEPRI, r3
 8015bd8:	f3bf 8f6f 	isb	sy
 8015bdc:	f3bf 8f4f 	dsb	sy
 8015be0:	60fb      	str	r3, [r7, #12]
}
 8015be2:	bf00      	nop
 8015be4:	bf00      	nop
 8015be6:	e7fd      	b.n	8015be4 <vTaskPlaceOnEventList+0x24>

	/* Place the event list item of the TCB in the appropriate event list.
	This is placed in the list in priority order so the highest priority task
	is the first to be woken by the event.  The queue that contains the event
	list is locked, preventing simultaneous access from interrupts. */
	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 8015be8:	4b07      	ldr	r3, [pc, #28]	@ (8015c08 <vTaskPlaceOnEventList+0x48>)
 8015bea:	681b      	ldr	r3, [r3, #0]
 8015bec:	3318      	adds	r3, #24
 8015bee:	4619      	mov	r1, r3
 8015bf0:	6878      	ldr	r0, [r7, #4]
 8015bf2:	f7fe f9de 	bl	8013fb2 <vListInsert>

	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
 8015bf6:	2101      	movs	r1, #1
 8015bf8:	6838      	ldr	r0, [r7, #0]
 8015bfa:	f000 fded 	bl	80167d8 <prvAddCurrentTaskToDelayedList>
}
 8015bfe:	bf00      	nop
 8015c00:	3710      	adds	r7, #16
 8015c02:	46bd      	mov	sp, r7
 8015c04:	bd80      	pop	{r7, pc}
 8015c06:	bf00      	nop
 8015c08:	24002640 	.word	0x24002640

08015c0c <vTaskPlaceOnEventListRestricted>:
/*-----------------------------------------------------------*/

#if( configUSE_TIMERS == 1 )

	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
	{
 8015c0c:	b580      	push	{r7, lr}
 8015c0e:	b086      	sub	sp, #24
 8015c10:	af00      	add	r7, sp, #0
 8015c12:	60f8      	str	r0, [r7, #12]
 8015c14:	60b9      	str	r1, [r7, #8]
 8015c16:	607a      	str	r2, [r7, #4]
		configASSERT( pxEventList );
 8015c18:	68fb      	ldr	r3, [r7, #12]
 8015c1a:	2b00      	cmp	r3, #0
 8015c1c:	d10b      	bne.n	8015c36 <vTaskPlaceOnEventListRestricted+0x2a>
	__asm volatile
 8015c1e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015c22:	f383 8811 	msr	BASEPRI, r3
 8015c26:	f3bf 8f6f 	isb	sy
 8015c2a:	f3bf 8f4f 	dsb	sy
 8015c2e:	617b      	str	r3, [r7, #20]
}
 8015c30:	bf00      	nop
 8015c32:	bf00      	nop
 8015c34:	e7fd      	b.n	8015c32 <vTaskPlaceOnEventListRestricted+0x26>

		/* Place the event list item of the TCB in the appropriate event list.
		In this case it is assume that this is the only task that is going to
		be waiting on this event list, so the faster vListInsertEnd() function
		can be used in place of vListInsert. */
		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 8015c36:	4b0a      	ldr	r3, [pc, #40]	@ (8015c60 <vTaskPlaceOnEventListRestricted+0x54>)
 8015c38:	681b      	ldr	r3, [r3, #0]
 8015c3a:	3318      	adds	r3, #24
 8015c3c:	4619      	mov	r1, r3
 8015c3e:	68f8      	ldr	r0, [r7, #12]
 8015c40:	f7fe f993 	bl	8013f6a <vListInsertEnd>

		/* If the task should block indefinitely then set the block time to a
		value that will be recognised as an indefinite delay inside the
		prvAddCurrentTaskToDelayedList() function. */
		if( xWaitIndefinitely != pdFALSE )
 8015c44:	687b      	ldr	r3, [r7, #4]
 8015c46:	2b00      	cmp	r3, #0
 8015c48:	d002      	beq.n	8015c50 <vTaskPlaceOnEventListRestricted+0x44>
		{
			xTicksToWait = portMAX_DELAY;
 8015c4a:	f04f 33ff 	mov.w	r3, #4294967295	@ 0xffffffff
 8015c4e:	60bb      	str	r3, [r7, #8]
		}

		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
 8015c50:	6879      	ldr	r1, [r7, #4]
 8015c52:	68b8      	ldr	r0, [r7, #8]
 8015c54:	f000 fdc0 	bl	80167d8 <prvAddCurrentTaskToDelayedList>
	}
 8015c58:	bf00      	nop
 8015c5a:	3718      	adds	r7, #24
 8015c5c:	46bd      	mov	sp, r7
 8015c5e:	bd80      	pop	{r7, pc}
 8015c60:	24002640 	.word	0x24002640

08015c64 <xTaskRemoveFromEventList>:

#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/

BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
 8015c64:	b580      	push	{r7, lr}
 8015c66:	b086      	sub	sp, #24
 8015c68:	af00      	add	r7, sp, #0
 8015c6a:	6078      	str	r0, [r7, #4]
	get called - the lock count on the queue will get modified instead.  This
	means exclusive access to the event list is guaranteed here.

	This function assumes that a check has already been made to ensure that
	pxEventList is not empty. */
	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8015c6c:	687b      	ldr	r3, [r7, #4]
 8015c6e:	68db      	ldr	r3, [r3, #12]
 8015c70:	68db      	ldr	r3, [r3, #12]
 8015c72:	613b      	str	r3, [r7, #16]
	configASSERT( pxUnblockedTCB );
 8015c74:	693b      	ldr	r3, [r7, #16]
 8015c76:	2b00      	cmp	r3, #0
 8015c78:	d10b      	bne.n	8015c92 <xTaskRemoveFromEventList+0x2e>
	__asm volatile
 8015c7a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015c7e:	f383 8811 	msr	BASEPRI, r3
 8015c82:	f3bf 8f6f 	isb	sy
 8015c86:	f3bf 8f4f 	dsb	sy
 8015c8a:	60fb      	str	r3, [r7, #12]
}
 8015c8c:	bf00      	nop
 8015c8e:	bf00      	nop
 8015c90:	e7fd      	b.n	8015c8e <xTaskRemoveFromEventList+0x2a>
	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
 8015c92:	693b      	ldr	r3, [r7, #16]
 8015c94:	3318      	adds	r3, #24
 8015c96:	4618      	mov	r0, r3
 8015c98:	f7fe f9c4 	bl	8014024 <uxListRemove>

	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8015c9c:	4b1d      	ldr	r3, [pc, #116]	@ (8015d14 <xTaskRemoveFromEventList+0xb0>)
 8015c9e:	681b      	ldr	r3, [r3, #0]
 8015ca0:	2b00      	cmp	r3, #0
 8015ca2:	d11d      	bne.n	8015ce0 <xTaskRemoveFromEventList+0x7c>
	{
		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
 8015ca4:	693b      	ldr	r3, [r7, #16]
 8015ca6:	3304      	adds	r3, #4
 8015ca8:	4618      	mov	r0, r3
 8015caa:	f7fe f9bb 	bl	8014024 <uxListRemove>
		prvAddTaskToReadyList( pxUnblockedTCB );
 8015cae:	693b      	ldr	r3, [r7, #16]
 8015cb0:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8015cb2:	4b19      	ldr	r3, [pc, #100]	@ (8015d18 <xTaskRemoveFromEventList+0xb4>)
 8015cb4:	681b      	ldr	r3, [r3, #0]
 8015cb6:	429a      	cmp	r2, r3
 8015cb8:	d903      	bls.n	8015cc2 <xTaskRemoveFromEventList+0x5e>
 8015cba:	693b      	ldr	r3, [r7, #16]
 8015cbc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8015cbe:	4a16      	ldr	r2, [pc, #88]	@ (8015d18 <xTaskRemoveFromEventList+0xb4>)
 8015cc0:	6013      	str	r3, [r2, #0]
 8015cc2:	693b      	ldr	r3, [r7, #16]
 8015cc4:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8015cc6:	4613      	mov	r3, r2
 8015cc8:	009b      	lsls	r3, r3, #2
 8015cca:	4413      	add	r3, r2
 8015ccc:	009b      	lsls	r3, r3, #2
 8015cce:	4a13      	ldr	r2, [pc, #76]	@ (8015d1c <xTaskRemoveFromEventList+0xb8>)
 8015cd0:	441a      	add	r2, r3
 8015cd2:	693b      	ldr	r3, [r7, #16]
 8015cd4:	3304      	adds	r3, #4
 8015cd6:	4619      	mov	r1, r3
 8015cd8:	4610      	mov	r0, r2
 8015cda:	f7fe f946 	bl	8013f6a <vListInsertEnd>
 8015cde:	e005      	b.n	8015cec <xTaskRemoveFromEventList+0x88>
	}
	else
	{
		/* The delayed and ready lists cannot be accessed, so hold this task
		pending until the scheduler is resumed. */
		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
 8015ce0:	693b      	ldr	r3, [r7, #16]
 8015ce2:	3318      	adds	r3, #24
 8015ce4:	4619      	mov	r1, r3
 8015ce6:	480e      	ldr	r0, [pc, #56]	@ (8015d20 <xTaskRemoveFromEventList+0xbc>)
 8015ce8:	f7fe f93f 	bl	8013f6a <vListInsertEnd>
	}

	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
 8015cec:	693b      	ldr	r3, [r7, #16]
 8015cee:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8015cf0:	4b0c      	ldr	r3, [pc, #48]	@ (8015d24 <xTaskRemoveFromEventList+0xc0>)
 8015cf2:	681b      	ldr	r3, [r3, #0]
 8015cf4:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8015cf6:	429a      	cmp	r2, r3
 8015cf8:	d905      	bls.n	8015d06 <xTaskRemoveFromEventList+0xa2>
	{
		/* Return true if the task removed from the event list has a higher
		priority than the calling task.  This allows the calling task to know if
		it should force a context switch now. */
		xReturn = pdTRUE;
 8015cfa:	2301      	movs	r3, #1
 8015cfc:	617b      	str	r3, [r7, #20]

		/* Mark that a yield is pending in case the user is not using the
		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
		xYieldPending = pdTRUE;
 8015cfe:	4b0a      	ldr	r3, [pc, #40]	@ (8015d28 <xTaskRemoveFromEventList+0xc4>)
 8015d00:	2201      	movs	r2, #1
 8015d02:	601a      	str	r2, [r3, #0]
 8015d04:	e001      	b.n	8015d0a <xTaskRemoveFromEventList+0xa6>
	}
	else
	{
		xReturn = pdFALSE;
 8015d06:	2300      	movs	r3, #0
 8015d08:	617b      	str	r3, [r7, #20]
	}

	return xReturn;
 8015d0a:	697b      	ldr	r3, [r7, #20]
}
 8015d0c:	4618      	mov	r0, r3
 8015d0e:	3718      	adds	r7, #24
 8015d10:	46bd      	mov	sp, r7
 8015d12:	bd80      	pop	{r7, pc}
 8015d14:	24002b3c 	.word	0x24002b3c
 8015d18:	24002b1c 	.word	0x24002b1c
 8015d1c:	24002644 	.word	0x24002644
 8015d20:	24002ad4 	.word	0x24002ad4
 8015d24:	24002640 	.word	0x24002640
 8015d28:	24002b28 	.word	0x24002b28

08015d2c <vTaskSetTimeOutState>:
	}
}
/*-----------------------------------------------------------*/

void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
{
 8015d2c:	b580      	push	{r7, lr}
 8015d2e:	b084      	sub	sp, #16
 8015d30:	af00      	add	r7, sp, #0
 8015d32:	6078      	str	r0, [r7, #4]
	configASSERT( pxTimeOut );
 8015d34:	687b      	ldr	r3, [r7, #4]
 8015d36:	2b00      	cmp	r3, #0
 8015d38:	d10b      	bne.n	8015d52 <vTaskSetTimeOutState+0x26>
	__asm volatile
 8015d3a:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015d3e:	f383 8811 	msr	BASEPRI, r3
 8015d42:	f3bf 8f6f 	isb	sy
 8015d46:	f3bf 8f4f 	dsb	sy
 8015d4a:	60fb      	str	r3, [r7, #12]
}
 8015d4c:	bf00      	nop
 8015d4e:	bf00      	nop
 8015d50:	e7fd      	b.n	8015d4e <vTaskSetTimeOutState+0x22>
	taskENTER_CRITICAL();
 8015d52:	f001 fb09 	bl	8017368 <vPortEnterCritical>
	{
		pxTimeOut->xOverflowCount = xNumOfOverflows;
 8015d56:	4b07      	ldr	r3, [pc, #28]	@ (8015d74 <vTaskSetTimeOutState+0x48>)
 8015d58:	681a      	ldr	r2, [r3, #0]
 8015d5a:	687b      	ldr	r3, [r7, #4]
 8015d5c:	601a      	str	r2, [r3, #0]
		pxTimeOut->xTimeOnEntering = xTickCount;
 8015d5e:	4b06      	ldr	r3, [pc, #24]	@ (8015d78 <vTaskSetTimeOutState+0x4c>)
 8015d60:	681a      	ldr	r2, [r3, #0]
 8015d62:	687b      	ldr	r3, [r7, #4]
 8015d64:	605a      	str	r2, [r3, #4]
	}
	taskEXIT_CRITICAL();
 8015d66:	f001 fb31 	bl	80173cc <vPortExitCritical>
}
 8015d6a:	bf00      	nop
 8015d6c:	3710      	adds	r7, #16
 8015d6e:	46bd      	mov	sp, r7
 8015d70:	bd80      	pop	{r7, pc}
 8015d72:	bf00      	nop
 8015d74:	24002b2c 	.word	0x24002b2c
 8015d78:	24002b18 	.word	0x24002b18

08015d7c <vTaskInternalSetTimeOutState>:
/*-----------------------------------------------------------*/

void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
 8015d7c:	b480      	push	{r7}
 8015d7e:	b083      	sub	sp, #12
 8015d80:	af00      	add	r7, sp, #0
 8015d82:	6078      	str	r0, [r7, #4]
	/* For internal use only as it does not use a critical section. */
	pxTimeOut->xOverflowCount = xNumOfOverflows;
 8015d84:	4b06      	ldr	r3, [pc, #24]	@ (8015da0 <vTaskInternalSetTimeOutState+0x24>)
 8015d86:	681a      	ldr	r2, [r3, #0]
 8015d88:	687b      	ldr	r3, [r7, #4]
 8015d8a:	601a      	str	r2, [r3, #0]
	pxTimeOut->xTimeOnEntering = xTickCount;
 8015d8c:	4b05      	ldr	r3, [pc, #20]	@ (8015da4 <vTaskInternalSetTimeOutState+0x28>)
 8015d8e:	681a      	ldr	r2, [r3, #0]
 8015d90:	687b      	ldr	r3, [r7, #4]
 8015d92:	605a      	str	r2, [r3, #4]
}
 8015d94:	bf00      	nop
 8015d96:	370c      	adds	r7, #12
 8015d98:	46bd      	mov	sp, r7
 8015d9a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8015d9e:	4770      	bx	lr
 8015da0:	24002b2c 	.word	0x24002b2c
 8015da4:	24002b18 	.word	0x24002b18

08015da8 <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/

BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
 8015da8:	b580      	push	{r7, lr}
 8015daa:	b088      	sub	sp, #32
 8015dac:	af00      	add	r7, sp, #0
 8015dae:	6078      	str	r0, [r7, #4]
 8015db0:	6039      	str	r1, [r7, #0]
BaseType_t xReturn;

	configASSERT( pxTimeOut );
 8015db2:	687b      	ldr	r3, [r7, #4]
 8015db4:	2b00      	cmp	r3, #0
 8015db6:	d10b      	bne.n	8015dd0 <xTaskCheckForTimeOut+0x28>
	__asm volatile
 8015db8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015dbc:	f383 8811 	msr	BASEPRI, r3
 8015dc0:	f3bf 8f6f 	isb	sy
 8015dc4:	f3bf 8f4f 	dsb	sy
 8015dc8:	613b      	str	r3, [r7, #16]
}
 8015dca:	bf00      	nop
 8015dcc:	bf00      	nop
 8015dce:	e7fd      	b.n	8015dcc <xTaskCheckForTimeOut+0x24>
	configASSERT( pxTicksToWait );
 8015dd0:	683b      	ldr	r3, [r7, #0]
 8015dd2:	2b00      	cmp	r3, #0
 8015dd4:	d10b      	bne.n	8015dee <xTaskCheckForTimeOut+0x46>
	__asm volatile
 8015dd6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015dda:	f383 8811 	msr	BASEPRI, r3
 8015dde:	f3bf 8f6f 	isb	sy
 8015de2:	f3bf 8f4f 	dsb	sy
 8015de6:	60fb      	str	r3, [r7, #12]
}
 8015de8:	bf00      	nop
 8015dea:	bf00      	nop
 8015dec:	e7fd      	b.n	8015dea <xTaskCheckForTimeOut+0x42>

	taskENTER_CRITICAL();
 8015dee:	f001 fabb 	bl	8017368 <vPortEnterCritical>
	{
		/* Minor optimisation.  The tick count cannot change in this block. */
		const TickType_t xConstTickCount = xTickCount;
 8015df2:	4b1d      	ldr	r3, [pc, #116]	@ (8015e68 <xTaskCheckForTimeOut+0xc0>)
 8015df4:	681b      	ldr	r3, [r3, #0]
 8015df6:	61bb      	str	r3, [r7, #24]
		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
 8015df8:	687b      	ldr	r3, [r7, #4]
 8015dfa:	685b      	ldr	r3, [r3, #4]
 8015dfc:	69ba      	ldr	r2, [r7, #24]
 8015dfe:	1ad3      	subs	r3, r2, r3
 8015e00:	617b      	str	r3, [r7, #20]
			}
			else
		#endif

		#if ( INCLUDE_vTaskSuspend == 1 )
			if( *pxTicksToWait == portMAX_DELAY )
 8015e02:	683b      	ldr	r3, [r7, #0]
 8015e04:	681b      	ldr	r3, [r3, #0]
 8015e06:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8015e0a:	d102      	bne.n	8015e12 <xTaskCheckForTimeOut+0x6a>
			{
				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
				specified is the maximum block time then the task should block
				indefinitely, and therefore never time out. */
				xReturn = pdFALSE;
 8015e0c:	2300      	movs	r3, #0
 8015e0e:	61fb      	str	r3, [r7, #28]
 8015e10:	e023      	b.n	8015e5a <xTaskCheckForTimeOut+0xb2>
			}
			else
		#endif

		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
 8015e12:	687b      	ldr	r3, [r7, #4]
 8015e14:	681a      	ldr	r2, [r3, #0]
 8015e16:	4b15      	ldr	r3, [pc, #84]	@ (8015e6c <xTaskCheckForTimeOut+0xc4>)
 8015e18:	681b      	ldr	r3, [r3, #0]
 8015e1a:	429a      	cmp	r2, r3
 8015e1c:	d007      	beq.n	8015e2e <xTaskCheckForTimeOut+0x86>
 8015e1e:	687b      	ldr	r3, [r7, #4]
 8015e20:	685b      	ldr	r3, [r3, #4]
 8015e22:	69ba      	ldr	r2, [r7, #24]
 8015e24:	429a      	cmp	r2, r3
 8015e26:	d302      	bcc.n	8015e2e <xTaskCheckForTimeOut+0x86>
			/* The tick count is greater than the time at which
			vTaskSetTimeout() was called, but has also overflowed since
			vTaskSetTimeOut() was called.  It must have wrapped all the way
			around and gone past again. This passed since vTaskSetTimeout()
			was called. */
			xReturn = pdTRUE;
 8015e28:	2301      	movs	r3, #1
 8015e2a:	61fb      	str	r3, [r7, #28]
 8015e2c:	e015      	b.n	8015e5a <xTaskCheckForTimeOut+0xb2>
		}
		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
 8015e2e:	683b      	ldr	r3, [r7, #0]
 8015e30:	681b      	ldr	r3, [r3, #0]
 8015e32:	697a      	ldr	r2, [r7, #20]
 8015e34:	429a      	cmp	r2, r3
 8015e36:	d20b      	bcs.n	8015e50 <xTaskCheckForTimeOut+0xa8>
		{
			/* Not a genuine timeout. Adjust parameters for time remaining. */
			*pxTicksToWait -= xElapsedTime;
 8015e38:	683b      	ldr	r3, [r7, #0]
 8015e3a:	681a      	ldr	r2, [r3, #0]
 8015e3c:	697b      	ldr	r3, [r7, #20]
 8015e3e:	1ad2      	subs	r2, r2, r3
 8015e40:	683b      	ldr	r3, [r7, #0]
 8015e42:	601a      	str	r2, [r3, #0]
			vTaskInternalSetTimeOutState( pxTimeOut );
 8015e44:	6878      	ldr	r0, [r7, #4]
 8015e46:	f7ff ff99 	bl	8015d7c <vTaskInternalSetTimeOutState>
			xReturn = pdFALSE;
 8015e4a:	2300      	movs	r3, #0
 8015e4c:	61fb      	str	r3, [r7, #28]
 8015e4e:	e004      	b.n	8015e5a <xTaskCheckForTimeOut+0xb2>
		}
		else
		{
			*pxTicksToWait = 0;
 8015e50:	683b      	ldr	r3, [r7, #0]
 8015e52:	2200      	movs	r2, #0
 8015e54:	601a      	str	r2, [r3, #0]
			xReturn = pdTRUE;
 8015e56:	2301      	movs	r3, #1
 8015e58:	61fb      	str	r3, [r7, #28]
		}
	}
	taskEXIT_CRITICAL();
 8015e5a:	f001 fab7 	bl	80173cc <vPortExitCritical>

	return xReturn;
 8015e5e:	69fb      	ldr	r3, [r7, #28]
}
 8015e60:	4618      	mov	r0, r3
 8015e62:	3720      	adds	r7, #32
 8015e64:	46bd      	mov	sp, r7
 8015e66:	bd80      	pop	{r7, pc}
 8015e68:	24002b18 	.word	0x24002b18
 8015e6c:	24002b2c 	.word	0x24002b2c

08015e70 <vTaskMissedYield>:
/*-----------------------------------------------------------*/

void vTaskMissedYield( void )
{
 8015e70:	b480      	push	{r7}
 8015e72:	af00      	add	r7, sp, #0
	xYieldPending = pdTRUE;
 8015e74:	4b03      	ldr	r3, [pc, #12]	@ (8015e84 <vTaskMissedYield+0x14>)
 8015e76:	2201      	movs	r2, #1
 8015e78:	601a      	str	r2, [r3, #0]
}
 8015e7a:	bf00      	nop
 8015e7c:	46bd      	mov	sp, r7
 8015e7e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8015e82:	4770      	bx	lr
 8015e84:	24002b28 	.word	0x24002b28

08015e88 <prvIdleTask>:
 *
 * void prvIdleTask( void *pvParameters );
 *
 */
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
 8015e88:	b580      	push	{r7, lr}
 8015e8a:	b082      	sub	sp, #8
 8015e8c:	af00      	add	r7, sp, #0
 8015e8e:	6078      	str	r0, [r7, #4]

	for( ;; )
	{
		/* See if any tasks have deleted themselves - if so then the idle task
		is responsible for freeing the deleted task's TCB and stack. */
		prvCheckTasksWaitingTermination();
 8015e90:	f000 f852 	bl	8015f38 <prvCheckTasksWaitingTermination>

			A critical region is not required here as we are just reading from
			the list, and an occasional incorrect value will not matter.  If
			the ready list at the idle priority contains more than one task
			then a task other than the idle task is ready to execute. */
			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
 8015e94:	4b06      	ldr	r3, [pc, #24]	@ (8015eb0 <prvIdleTask+0x28>)
 8015e96:	681b      	ldr	r3, [r3, #0]
 8015e98:	2b01      	cmp	r3, #1
 8015e9a:	d9f9      	bls.n	8015e90 <prvIdleTask+0x8>
			{
				taskYIELD();
 8015e9c:	4b05      	ldr	r3, [pc, #20]	@ (8015eb4 <prvIdleTask+0x2c>)
 8015e9e:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8015ea2:	601a      	str	r2, [r3, #0]
 8015ea4:	f3bf 8f4f 	dsb	sy
 8015ea8:	f3bf 8f6f 	isb	sy
		prvCheckTasksWaitingTermination();
 8015eac:	e7f0      	b.n	8015e90 <prvIdleTask+0x8>
 8015eae:	bf00      	nop
 8015eb0:	24002644 	.word	0x24002644
 8015eb4:	e000ed04 	.word	0xe000ed04

08015eb8 <prvInitialiseTaskLists>:

#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/

static void prvInitialiseTaskLists( void )
{
 8015eb8:	b580      	push	{r7, lr}
 8015eba:	b082      	sub	sp, #8
 8015ebc:	af00      	add	r7, sp, #0
UBaseType_t uxPriority;

	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
 8015ebe:	2300      	movs	r3, #0
 8015ec0:	607b      	str	r3, [r7, #4]
 8015ec2:	e00c      	b.n	8015ede <prvInitialiseTaskLists+0x26>
	{
		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
 8015ec4:	687a      	ldr	r2, [r7, #4]
 8015ec6:	4613      	mov	r3, r2
 8015ec8:	009b      	lsls	r3, r3, #2
 8015eca:	4413      	add	r3, r2
 8015ecc:	009b      	lsls	r3, r3, #2
 8015ece:	4a12      	ldr	r2, [pc, #72]	@ (8015f18 <prvInitialiseTaskLists+0x60>)
 8015ed0:	4413      	add	r3, r2
 8015ed2:	4618      	mov	r0, r3
 8015ed4:	f7fe f81c 	bl	8013f10 <vListInitialise>
	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
 8015ed8:	687b      	ldr	r3, [r7, #4]
 8015eda:	3301      	adds	r3, #1
 8015edc:	607b      	str	r3, [r7, #4]
 8015ede:	687b      	ldr	r3, [r7, #4]
 8015ee0:	2b37      	cmp	r3, #55	@ 0x37
 8015ee2:	d9ef      	bls.n	8015ec4 <prvInitialiseTaskLists+0xc>
	}

	vListInitialise( &xDelayedTaskList1 );
 8015ee4:	480d      	ldr	r0, [pc, #52]	@ (8015f1c <prvInitialiseTaskLists+0x64>)
 8015ee6:	f7fe f813 	bl	8013f10 <vListInitialise>
	vListInitialise( &xDelayedTaskList2 );
 8015eea:	480d      	ldr	r0, [pc, #52]	@ (8015f20 <prvInitialiseTaskLists+0x68>)
 8015eec:	f7fe f810 	bl	8013f10 <vListInitialise>
	vListInitialise( &xPendingReadyList );
 8015ef0:	480c      	ldr	r0, [pc, #48]	@ (8015f24 <prvInitialiseTaskLists+0x6c>)
 8015ef2:	f7fe f80d 	bl	8013f10 <vListInitialise>

	#if ( INCLUDE_vTaskDelete == 1 )
	{
		vListInitialise( &xTasksWaitingTermination );
 8015ef6:	480c      	ldr	r0, [pc, #48]	@ (8015f28 <prvInitialiseTaskLists+0x70>)
 8015ef8:	f7fe f80a 	bl	8013f10 <vListInitialise>
	}
	#endif /* INCLUDE_vTaskDelete */

	#if ( INCLUDE_vTaskSuspend == 1 )
	{
		vListInitialise( &xSuspendedTaskList );
 8015efc:	480b      	ldr	r0, [pc, #44]	@ (8015f2c <prvInitialiseTaskLists+0x74>)
 8015efe:	f7fe f807 	bl	8013f10 <vListInitialise>
	}
	#endif /* INCLUDE_vTaskSuspend */

	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
	using list2. */
	pxDelayedTaskList = &xDelayedTaskList1;
 8015f02:	4b0b      	ldr	r3, [pc, #44]	@ (8015f30 <prvInitialiseTaskLists+0x78>)
 8015f04:	4a05      	ldr	r2, [pc, #20]	@ (8015f1c <prvInitialiseTaskLists+0x64>)
 8015f06:	601a      	str	r2, [r3, #0]
	pxOverflowDelayedTaskList = &xDelayedTaskList2;
 8015f08:	4b0a      	ldr	r3, [pc, #40]	@ (8015f34 <prvInitialiseTaskLists+0x7c>)
 8015f0a:	4a05      	ldr	r2, [pc, #20]	@ (8015f20 <prvInitialiseTaskLists+0x68>)
 8015f0c:	601a      	str	r2, [r3, #0]
}
 8015f0e:	bf00      	nop
 8015f10:	3708      	adds	r7, #8
 8015f12:	46bd      	mov	sp, r7
 8015f14:	bd80      	pop	{r7, pc}
 8015f16:	bf00      	nop
 8015f18:	24002644 	.word	0x24002644
 8015f1c:	24002aa4 	.word	0x24002aa4
 8015f20:	24002ab8 	.word	0x24002ab8
 8015f24:	24002ad4 	.word	0x24002ad4
 8015f28:	24002ae8 	.word	0x24002ae8
 8015f2c:	24002b00 	.word	0x24002b00
 8015f30:	24002acc 	.word	0x24002acc
 8015f34:	24002ad0 	.word	0x24002ad0

08015f38 <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/

static void prvCheckTasksWaitingTermination( void )
{
 8015f38:	b580      	push	{r7, lr}
 8015f3a:	b082      	sub	sp, #8
 8015f3c:	af00      	add	r7, sp, #0
	{
		TCB_t *pxTCB;

		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
		being called too often in the idle task. */
		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 8015f3e:	e019      	b.n	8015f74 <prvCheckTasksWaitingTermination+0x3c>
		{
			taskENTER_CRITICAL();
 8015f40:	f001 fa12 	bl	8017368 <vPortEnterCritical>
			{
				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8015f44:	4b10      	ldr	r3, [pc, #64]	@ (8015f88 <prvCheckTasksWaitingTermination+0x50>)
 8015f46:	68db      	ldr	r3, [r3, #12]
 8015f48:	68db      	ldr	r3, [r3, #12]
 8015f4a:	607b      	str	r3, [r7, #4]
				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8015f4c:	687b      	ldr	r3, [r7, #4]
 8015f4e:	3304      	adds	r3, #4
 8015f50:	4618      	mov	r0, r3
 8015f52:	f7fe f867 	bl	8014024 <uxListRemove>
				--uxCurrentNumberOfTasks;
 8015f56:	4b0d      	ldr	r3, [pc, #52]	@ (8015f8c <prvCheckTasksWaitingTermination+0x54>)
 8015f58:	681b      	ldr	r3, [r3, #0]
 8015f5a:	3b01      	subs	r3, #1
 8015f5c:	4a0b      	ldr	r2, [pc, #44]	@ (8015f8c <prvCheckTasksWaitingTermination+0x54>)
 8015f5e:	6013      	str	r3, [r2, #0]
				--uxDeletedTasksWaitingCleanUp;
 8015f60:	4b0b      	ldr	r3, [pc, #44]	@ (8015f90 <prvCheckTasksWaitingTermination+0x58>)
 8015f62:	681b      	ldr	r3, [r3, #0]
 8015f64:	3b01      	subs	r3, #1
 8015f66:	4a0a      	ldr	r2, [pc, #40]	@ (8015f90 <prvCheckTasksWaitingTermination+0x58>)
 8015f68:	6013      	str	r3, [r2, #0]
			}
			taskEXIT_CRITICAL();
 8015f6a:	f001 fa2f 	bl	80173cc <vPortExitCritical>

			prvDeleteTCB( pxTCB );
 8015f6e:	6878      	ldr	r0, [r7, #4]
 8015f70:	f000 f810 	bl	8015f94 <prvDeleteTCB>
		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 8015f74:	4b06      	ldr	r3, [pc, #24]	@ (8015f90 <prvCheckTasksWaitingTermination+0x58>)
 8015f76:	681b      	ldr	r3, [r3, #0]
 8015f78:	2b00      	cmp	r3, #0
 8015f7a:	d1e1      	bne.n	8015f40 <prvCheckTasksWaitingTermination+0x8>
		}
	}
	#endif /* INCLUDE_vTaskDelete */
}
 8015f7c:	bf00      	nop
 8015f7e:	bf00      	nop
 8015f80:	3708      	adds	r7, #8
 8015f82:	46bd      	mov	sp, r7
 8015f84:	bd80      	pop	{r7, pc}
 8015f86:	bf00      	nop
 8015f88:	24002ae8 	.word	0x24002ae8
 8015f8c:	24002b14 	.word	0x24002b14
 8015f90:	24002afc 	.word	0x24002afc

08015f94 <prvDeleteTCB>:
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelete == 1 )

	static void prvDeleteTCB( TCB_t *pxTCB )
	{
 8015f94:	b580      	push	{r7, lr}
 8015f96:	b084      	sub	sp, #16
 8015f98:	af00      	add	r7, sp, #0
 8015f9a:	6078      	str	r0, [r7, #4]
		to the task to free any memory allocated at the application level.
		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
		for additional information. */
		#if ( configUSE_NEWLIB_REENTRANT == 1 )
		{
			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
 8015f9c:	687b      	ldr	r3, [r7, #4]
 8015f9e:	3354      	adds	r3, #84	@ 0x54
 8015fa0:	4618      	mov	r0, r3
 8015fa2:	f001 fe21 	bl	8017be8 <_reclaim_reent>
		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
		{
			/* The task could have been allocated statically or dynamically, so
			check what was statically allocated before trying to free the
			memory. */
			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
 8015fa6:	687b      	ldr	r3, [r7, #4]
 8015fa8:	f893 30a5 	ldrb.w	r3, [r3, #165]	@ 0xa5
 8015fac:	2b00      	cmp	r3, #0
 8015fae:	d108      	bne.n	8015fc2 <prvDeleteTCB+0x2e>
			{
				/* Both the stack and TCB were allocated dynamically, so both
				must be freed. */
				vPortFree( pxTCB->pxStack );
 8015fb0:	687b      	ldr	r3, [r7, #4]
 8015fb2:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8015fb4:	4618      	mov	r0, r3
 8015fb6:	f001 fbc7 	bl	8017748 <vPortFree>
				vPortFree( pxTCB );
 8015fba:	6878      	ldr	r0, [r7, #4]
 8015fbc:	f001 fbc4 	bl	8017748 <vPortFree>
				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
				mtCOVERAGE_TEST_MARKER();
			}
		}
		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
	}
 8015fc0:	e019      	b.n	8015ff6 <prvDeleteTCB+0x62>
			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
 8015fc2:	687b      	ldr	r3, [r7, #4]
 8015fc4:	f893 30a5 	ldrb.w	r3, [r3, #165]	@ 0xa5
 8015fc8:	2b01      	cmp	r3, #1
 8015fca:	d103      	bne.n	8015fd4 <prvDeleteTCB+0x40>
				vPortFree( pxTCB );
 8015fcc:	6878      	ldr	r0, [r7, #4]
 8015fce:	f001 fbbb 	bl	8017748 <vPortFree>
	}
 8015fd2:	e010      	b.n	8015ff6 <prvDeleteTCB+0x62>
				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
 8015fd4:	687b      	ldr	r3, [r7, #4]
 8015fd6:	f893 30a5 	ldrb.w	r3, [r3, #165]	@ 0xa5
 8015fda:	2b02      	cmp	r3, #2
 8015fdc:	d00b      	beq.n	8015ff6 <prvDeleteTCB+0x62>
	__asm volatile
 8015fde:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8015fe2:	f383 8811 	msr	BASEPRI, r3
 8015fe6:	f3bf 8f6f 	isb	sy
 8015fea:	f3bf 8f4f 	dsb	sy
 8015fee:	60fb      	str	r3, [r7, #12]
}
 8015ff0:	bf00      	nop
 8015ff2:	bf00      	nop
 8015ff4:	e7fd      	b.n	8015ff2 <prvDeleteTCB+0x5e>
	}
 8015ff6:	bf00      	nop
 8015ff8:	3710      	adds	r7, #16
 8015ffa:	46bd      	mov	sp, r7
 8015ffc:	bd80      	pop	{r7, pc}
	...

08016000 <prvResetNextTaskUnblockTime>:

#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/

static void prvResetNextTaskUnblockTime( void )
{
 8016000:	b480      	push	{r7}
 8016002:	b083      	sub	sp, #12
 8016004:	af00      	add	r7, sp, #0
TCB_t *pxTCB;

	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 8016006:	4b0c      	ldr	r3, [pc, #48]	@ (8016038 <prvResetNextTaskUnblockTime+0x38>)
 8016008:	681b      	ldr	r3, [r3, #0]
 801600a:	681b      	ldr	r3, [r3, #0]
 801600c:	2b00      	cmp	r3, #0
 801600e:	d104      	bne.n	801601a <prvResetNextTaskUnblockTime+0x1a>
	{
		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
		the maximum possible value so it is	extremely unlikely that the
		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
		there is an item in the delayed list. */
		xNextTaskUnblockTime = portMAX_DELAY;
 8016010:	4b0a      	ldr	r3, [pc, #40]	@ (801603c <prvResetNextTaskUnblockTime+0x3c>)
 8016012:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8016016:	601a      	str	r2, [r3, #0]
		which the task at the head of the delayed list should be removed
		from the Blocked state. */
		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
	}
}
 8016018:	e008      	b.n	801602c <prvResetNextTaskUnblockTime+0x2c>
		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 801601a:	4b07      	ldr	r3, [pc, #28]	@ (8016038 <prvResetNextTaskUnblockTime+0x38>)
 801601c:	681b      	ldr	r3, [r3, #0]
 801601e:	68db      	ldr	r3, [r3, #12]
 8016020:	68db      	ldr	r3, [r3, #12]
 8016022:	607b      	str	r3, [r7, #4]
		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
 8016024:	687b      	ldr	r3, [r7, #4]
 8016026:	685b      	ldr	r3, [r3, #4]
 8016028:	4a04      	ldr	r2, [pc, #16]	@ (801603c <prvResetNextTaskUnblockTime+0x3c>)
 801602a:	6013      	str	r3, [r2, #0]
}
 801602c:	bf00      	nop
 801602e:	370c      	adds	r7, #12
 8016030:	46bd      	mov	sp, r7
 8016032:	f85d 7b04 	ldr.w	r7, [sp], #4
 8016036:	4770      	bx	lr
 8016038:	24002acc 	.word	0x24002acc
 801603c:	24002b34 	.word	0x24002b34

08016040 <xTaskGetCurrentTaskHandle>:
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )

	TaskHandle_t xTaskGetCurrentTaskHandle( void )
	{
 8016040:	b480      	push	{r7}
 8016042:	b083      	sub	sp, #12
 8016044:	af00      	add	r7, sp, #0
	TaskHandle_t xReturn;

		/* A critical section is not required as this is not called from
		an interrupt and the current TCB will always be the same for any
		individual execution thread. */
		xReturn = pxCurrentTCB;
 8016046:	4b05      	ldr	r3, [pc, #20]	@ (801605c <xTaskGetCurrentTaskHandle+0x1c>)
 8016048:	681b      	ldr	r3, [r3, #0]
 801604a:	607b      	str	r3, [r7, #4]

		return xReturn;
 801604c:	687b      	ldr	r3, [r7, #4]
	}
 801604e:	4618      	mov	r0, r3
 8016050:	370c      	adds	r7, #12
 8016052:	46bd      	mov	sp, r7
 8016054:	f85d 7b04 	ldr.w	r7, [sp], #4
 8016058:	4770      	bx	lr
 801605a:	bf00      	nop
 801605c:	24002640 	.word	0x24002640

08016060 <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

	BaseType_t xTaskGetSchedulerState( void )
	{
 8016060:	b480      	push	{r7}
 8016062:	b083      	sub	sp, #12
 8016064:	af00      	add	r7, sp, #0
	BaseType_t xReturn;

		if( xSchedulerRunning == pdFALSE )
 8016066:	4b0b      	ldr	r3, [pc, #44]	@ (8016094 <xTaskGetSchedulerState+0x34>)
 8016068:	681b      	ldr	r3, [r3, #0]
 801606a:	2b00      	cmp	r3, #0
 801606c:	d102      	bne.n	8016074 <xTaskGetSchedulerState+0x14>
		{
			xReturn = taskSCHEDULER_NOT_STARTED;
 801606e:	2301      	movs	r3, #1
 8016070:	607b      	str	r3, [r7, #4]
 8016072:	e008      	b.n	8016086 <xTaskGetSchedulerState+0x26>
		}
		else
		{
			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8016074:	4b08      	ldr	r3, [pc, #32]	@ (8016098 <xTaskGetSchedulerState+0x38>)
 8016076:	681b      	ldr	r3, [r3, #0]
 8016078:	2b00      	cmp	r3, #0
 801607a:	d102      	bne.n	8016082 <xTaskGetSchedulerState+0x22>
			{
				xReturn = taskSCHEDULER_RUNNING;
 801607c:	2302      	movs	r3, #2
 801607e:	607b      	str	r3, [r7, #4]
 8016080:	e001      	b.n	8016086 <xTaskGetSchedulerState+0x26>
			}
			else
			{
				xReturn = taskSCHEDULER_SUSPENDED;
 8016082:	2300      	movs	r3, #0
 8016084:	607b      	str	r3, [r7, #4]
			}
		}

		return xReturn;
 8016086:	687b      	ldr	r3, [r7, #4]
	}
 8016088:	4618      	mov	r0, r3
 801608a:	370c      	adds	r7, #12
 801608c:	46bd      	mov	sp, r7
 801608e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8016092:	4770      	bx	lr
 8016094:	24002b20 	.word	0x24002b20
 8016098:	24002b3c 	.word	0x24002b3c

0801609c <xTaskPriorityInherit>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
	{
 801609c:	b580      	push	{r7, lr}
 801609e:	b084      	sub	sp, #16
 80160a0:	af00      	add	r7, sp, #0
 80160a2:	6078      	str	r0, [r7, #4]
	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
 80160a4:	687b      	ldr	r3, [r7, #4]
 80160a6:	60bb      	str	r3, [r7, #8]
	BaseType_t xReturn = pdFALSE;
 80160a8:	2300      	movs	r3, #0
 80160aa:	60fb      	str	r3, [r7, #12]

		/* If the mutex was given back by an interrupt while the queue was
		locked then the mutex holder might now be NULL.  _RB_ Is this still
		needed as interrupts can no longer use mutexes? */
		if( pxMutexHolder != NULL )
 80160ac:	687b      	ldr	r3, [r7, #4]
 80160ae:	2b00      	cmp	r3, #0
 80160b0:	d051      	beq.n	8016156 <xTaskPriorityInherit+0xba>
		{
			/* If the holder of the mutex has a priority below the priority of
			the task attempting to obtain the mutex then it will temporarily
			inherit the priority of the task attempting to obtain the mutex. */
			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
 80160b2:	68bb      	ldr	r3, [r7, #8]
 80160b4:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80160b6:	4b2a      	ldr	r3, [pc, #168]	@ (8016160 <xTaskPriorityInherit+0xc4>)
 80160b8:	681b      	ldr	r3, [r3, #0]
 80160ba:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80160bc:	429a      	cmp	r2, r3
 80160be:	d241      	bcs.n	8016144 <xTaskPriorityInherit+0xa8>
			{
				/* Adjust the mutex holder state to account for its new
				priority.  Only reset the event list item value if the value is
				not being used for anything else. */
				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
 80160c0:	68bb      	ldr	r3, [r7, #8]
 80160c2:	699b      	ldr	r3, [r3, #24]
 80160c4:	2b00      	cmp	r3, #0
 80160c6:	db06      	blt.n	80160d6 <xTaskPriorityInherit+0x3a>
				{
					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80160c8:	4b25      	ldr	r3, [pc, #148]	@ (8016160 <xTaskPriorityInherit+0xc4>)
 80160ca:	681b      	ldr	r3, [r3, #0]
 80160cc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80160ce:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 80160d2:	68bb      	ldr	r3, [r7, #8]
 80160d4:	619a      	str	r2, [r3, #24]
					mtCOVERAGE_TEST_MARKER();
				}

				/* If the task being modified is in the ready state it will need
				to be moved into a new list. */
				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
 80160d6:	68bb      	ldr	r3, [r7, #8]
 80160d8:	6959      	ldr	r1, [r3, #20]
 80160da:	68bb      	ldr	r3, [r7, #8]
 80160dc:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80160de:	4613      	mov	r3, r2
 80160e0:	009b      	lsls	r3, r3, #2
 80160e2:	4413      	add	r3, r2
 80160e4:	009b      	lsls	r3, r3, #2
 80160e6:	4a1f      	ldr	r2, [pc, #124]	@ (8016164 <xTaskPriorityInherit+0xc8>)
 80160e8:	4413      	add	r3, r2
 80160ea:	4299      	cmp	r1, r3
 80160ec:	d122      	bne.n	8016134 <xTaskPriorityInherit+0x98>
				{
					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 80160ee:	68bb      	ldr	r3, [r7, #8]
 80160f0:	3304      	adds	r3, #4
 80160f2:	4618      	mov	r0, r3
 80160f4:	f7fd ff96 	bl	8014024 <uxListRemove>
					{
						mtCOVERAGE_TEST_MARKER();
					}

					/* Inherit the priority before being moved into the new list. */
					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
 80160f8:	4b19      	ldr	r3, [pc, #100]	@ (8016160 <xTaskPriorityInherit+0xc4>)
 80160fa:	681b      	ldr	r3, [r3, #0]
 80160fc:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80160fe:	68bb      	ldr	r3, [r7, #8]
 8016100:	62da      	str	r2, [r3, #44]	@ 0x2c
					prvAddTaskToReadyList( pxMutexHolderTCB );
 8016102:	68bb      	ldr	r3, [r7, #8]
 8016104:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8016106:	4b18      	ldr	r3, [pc, #96]	@ (8016168 <xTaskPriorityInherit+0xcc>)
 8016108:	681b      	ldr	r3, [r3, #0]
 801610a:	429a      	cmp	r2, r3
 801610c:	d903      	bls.n	8016116 <xTaskPriorityInherit+0x7a>
 801610e:	68bb      	ldr	r3, [r7, #8]
 8016110:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8016112:	4a15      	ldr	r2, [pc, #84]	@ (8016168 <xTaskPriorityInherit+0xcc>)
 8016114:	6013      	str	r3, [r2, #0]
 8016116:	68bb      	ldr	r3, [r7, #8]
 8016118:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 801611a:	4613      	mov	r3, r2
 801611c:	009b      	lsls	r3, r3, #2
 801611e:	4413      	add	r3, r2
 8016120:	009b      	lsls	r3, r3, #2
 8016122:	4a10      	ldr	r2, [pc, #64]	@ (8016164 <xTaskPriorityInherit+0xc8>)
 8016124:	441a      	add	r2, r3
 8016126:	68bb      	ldr	r3, [r7, #8]
 8016128:	3304      	adds	r3, #4
 801612a:	4619      	mov	r1, r3
 801612c:	4610      	mov	r0, r2
 801612e:	f7fd ff1c 	bl	8013f6a <vListInsertEnd>
 8016132:	e004      	b.n	801613e <xTaskPriorityInherit+0xa2>
				}
				else
				{
					/* Just inherit the priority. */
					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
 8016134:	4b0a      	ldr	r3, [pc, #40]	@ (8016160 <xTaskPriorityInherit+0xc4>)
 8016136:	681b      	ldr	r3, [r3, #0]
 8016138:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 801613a:	68bb      	ldr	r3, [r7, #8]
 801613c:	62da      	str	r2, [r3, #44]	@ 0x2c
				}

				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );

				/* Inheritance occurred. */
				xReturn = pdTRUE;
 801613e:	2301      	movs	r3, #1
 8016140:	60fb      	str	r3, [r7, #12]
 8016142:	e008      	b.n	8016156 <xTaskPriorityInherit+0xba>
			}
			else
			{
				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
 8016144:	68bb      	ldr	r3, [r7, #8]
 8016146:	6cda      	ldr	r2, [r3, #76]	@ 0x4c
 8016148:	4b05      	ldr	r3, [pc, #20]	@ (8016160 <xTaskPriorityInherit+0xc4>)
 801614a:	681b      	ldr	r3, [r3, #0]
 801614c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 801614e:	429a      	cmp	r2, r3
 8016150:	d201      	bcs.n	8016156 <xTaskPriorityInherit+0xba>
					current priority of the mutex holder is not lower than the
					priority of the task attempting to take the mutex.
					Therefore the mutex holder must have already inherited a
					priority, but inheritance would have occurred if that had
					not been the case. */
					xReturn = pdTRUE;
 8016152:	2301      	movs	r3, #1
 8016154:	60fb      	str	r3, [r7, #12]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		return xReturn;
 8016156:	68fb      	ldr	r3, [r7, #12]
	}
 8016158:	4618      	mov	r0, r3
 801615a:	3710      	adds	r7, #16
 801615c:	46bd      	mov	sp, r7
 801615e:	bd80      	pop	{r7, pc}
 8016160:	24002640 	.word	0x24002640
 8016164:	24002644 	.word	0x24002644
 8016168:	24002b1c 	.word	0x24002b1c

0801616c <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
	{
 801616c:	b580      	push	{r7, lr}
 801616e:	b086      	sub	sp, #24
 8016170:	af00      	add	r7, sp, #0
 8016172:	6078      	str	r0, [r7, #4]
	TCB_t * const pxTCB = pxMutexHolder;
 8016174:	687b      	ldr	r3, [r7, #4]
 8016176:	613b      	str	r3, [r7, #16]
	BaseType_t xReturn = pdFALSE;
 8016178:	2300      	movs	r3, #0
 801617a:	617b      	str	r3, [r7, #20]

		if( pxMutexHolder != NULL )
 801617c:	687b      	ldr	r3, [r7, #4]
 801617e:	2b00      	cmp	r3, #0
 8016180:	d058      	beq.n	8016234 <xTaskPriorityDisinherit+0xc8>
		{
			/* A task can only have an inherited priority if it holds the mutex.
			If the mutex is held by a task then it cannot be given from an
			interrupt, and if a mutex is given by the holding task then it must
			be the running state task. */
			configASSERT( pxTCB == pxCurrentTCB );
 8016182:	4b2f      	ldr	r3, [pc, #188]	@ (8016240 <xTaskPriorityDisinherit+0xd4>)
 8016184:	681b      	ldr	r3, [r3, #0]
 8016186:	693a      	ldr	r2, [r7, #16]
 8016188:	429a      	cmp	r2, r3
 801618a:	d00b      	beq.n	80161a4 <xTaskPriorityDisinherit+0x38>
	__asm volatile
 801618c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8016190:	f383 8811 	msr	BASEPRI, r3
 8016194:	f3bf 8f6f 	isb	sy
 8016198:	f3bf 8f4f 	dsb	sy
 801619c:	60fb      	str	r3, [r7, #12]
}
 801619e:	bf00      	nop
 80161a0:	bf00      	nop
 80161a2:	e7fd      	b.n	80161a0 <xTaskPriorityDisinherit+0x34>
			configASSERT( pxTCB->uxMutexesHeld );
 80161a4:	693b      	ldr	r3, [r7, #16]
 80161a6:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80161a8:	2b00      	cmp	r3, #0
 80161aa:	d10b      	bne.n	80161c4 <xTaskPriorityDisinherit+0x58>
	__asm volatile
 80161ac:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80161b0:	f383 8811 	msr	BASEPRI, r3
 80161b4:	f3bf 8f6f 	isb	sy
 80161b8:	f3bf 8f4f 	dsb	sy
 80161bc:	60bb      	str	r3, [r7, #8]
}
 80161be:	bf00      	nop
 80161c0:	bf00      	nop
 80161c2:	e7fd      	b.n	80161c0 <xTaskPriorityDisinherit+0x54>
			( pxTCB->uxMutexesHeld )--;
 80161c4:	693b      	ldr	r3, [r7, #16]
 80161c6:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80161c8:	1e5a      	subs	r2, r3, #1
 80161ca:	693b      	ldr	r3, [r7, #16]
 80161cc:	651a      	str	r2, [r3, #80]	@ 0x50

			/* Has the holder of the mutex inherited the priority of another
			task? */
			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
 80161ce:	693b      	ldr	r3, [r7, #16]
 80161d0:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 80161d2:	693b      	ldr	r3, [r7, #16]
 80161d4:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 80161d6:	429a      	cmp	r2, r3
 80161d8:	d02c      	beq.n	8016234 <xTaskPriorityDisinherit+0xc8>
			{
				/* Only disinherit if no other mutexes are held. */
				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
 80161da:	693b      	ldr	r3, [r7, #16]
 80161dc:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80161de:	2b00      	cmp	r3, #0
 80161e0:	d128      	bne.n	8016234 <xTaskPriorityDisinherit+0xc8>
					/* A task can only have an inherited priority if it holds
					the mutex.  If the mutex is held by a task then it cannot be
					given from an interrupt, and if a mutex is given by the
					holding task then it must be the running state task.  Remove
					the holding task from the ready/delayed list. */
					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 80161e2:	693b      	ldr	r3, [r7, #16]
 80161e4:	3304      	adds	r3, #4
 80161e6:	4618      	mov	r0, r3
 80161e8:	f7fd ff1c 	bl	8014024 <uxListRemove>
					}

					/* Disinherit the priority before adding the task into the
					new	ready list. */
					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
					pxTCB->uxPriority = pxTCB->uxBasePriority;
 80161ec:	693b      	ldr	r3, [r7, #16]
 80161ee:	6cda      	ldr	r2, [r3, #76]	@ 0x4c
 80161f0:	693b      	ldr	r3, [r7, #16]
 80161f2:	62da      	str	r2, [r3, #44]	@ 0x2c

					/* Reset the event list item value.  It cannot be in use for
					any other purpose if this task is running, and it must be
					running to give back the mutex. */
					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80161f4:	693b      	ldr	r3, [r7, #16]
 80161f6:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80161f8:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 80161fc:	693b      	ldr	r3, [r7, #16]
 80161fe:	619a      	str	r2, [r3, #24]
					prvAddTaskToReadyList( pxTCB );
 8016200:	693b      	ldr	r3, [r7, #16]
 8016202:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8016204:	4b0f      	ldr	r3, [pc, #60]	@ (8016244 <xTaskPriorityDisinherit+0xd8>)
 8016206:	681b      	ldr	r3, [r3, #0]
 8016208:	429a      	cmp	r2, r3
 801620a:	d903      	bls.n	8016214 <xTaskPriorityDisinherit+0xa8>
 801620c:	693b      	ldr	r3, [r7, #16]
 801620e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8016210:	4a0c      	ldr	r2, [pc, #48]	@ (8016244 <xTaskPriorityDisinherit+0xd8>)
 8016212:	6013      	str	r3, [r2, #0]
 8016214:	693b      	ldr	r3, [r7, #16]
 8016216:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8016218:	4613      	mov	r3, r2
 801621a:	009b      	lsls	r3, r3, #2
 801621c:	4413      	add	r3, r2
 801621e:	009b      	lsls	r3, r3, #2
 8016220:	4a09      	ldr	r2, [pc, #36]	@ (8016248 <xTaskPriorityDisinherit+0xdc>)
 8016222:	441a      	add	r2, r3
 8016224:	693b      	ldr	r3, [r7, #16]
 8016226:	3304      	adds	r3, #4
 8016228:	4619      	mov	r1, r3
 801622a:	4610      	mov	r0, r2
 801622c:	f7fd fe9d 	bl	8013f6a <vListInsertEnd>
					in an order different to that in which they were taken.
					If a context switch did not occur when the first mutex was
					returned, even if a task was waiting on it, then a context
					switch should occur when the last mutex is returned whether
					a task is waiting on it or not. */
					xReturn = pdTRUE;
 8016230:	2301      	movs	r3, #1
 8016232:	617b      	str	r3, [r7, #20]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		return xReturn;
 8016234:	697b      	ldr	r3, [r7, #20]
	}
 8016236:	4618      	mov	r0, r3
 8016238:	3718      	adds	r7, #24
 801623a:	46bd      	mov	sp, r7
 801623c:	bd80      	pop	{r7, pc}
 801623e:	bf00      	nop
 8016240:	24002640 	.word	0x24002640
 8016244:	24002b1c 	.word	0x24002b1c
 8016248:	24002644 	.word	0x24002644

0801624c <vTaskPriorityDisinheritAfterTimeout>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
	{
 801624c:	b580      	push	{r7, lr}
 801624e:	b088      	sub	sp, #32
 8016250:	af00      	add	r7, sp, #0
 8016252:	6078      	str	r0, [r7, #4]
 8016254:	6039      	str	r1, [r7, #0]
	TCB_t * const pxTCB = pxMutexHolder;
 8016256:	687b      	ldr	r3, [r7, #4]
 8016258:	61bb      	str	r3, [r7, #24]
	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
 801625a:	2301      	movs	r3, #1
 801625c:	617b      	str	r3, [r7, #20]

		if( pxMutexHolder != NULL )
 801625e:	687b      	ldr	r3, [r7, #4]
 8016260:	2b00      	cmp	r3, #0
 8016262:	d06c      	beq.n	801633e <vTaskPriorityDisinheritAfterTimeout+0xf2>
		{
			/* If pxMutexHolder is not NULL then the holder must hold at least
			one mutex. */
			configASSERT( pxTCB->uxMutexesHeld );
 8016264:	69bb      	ldr	r3, [r7, #24]
 8016266:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8016268:	2b00      	cmp	r3, #0
 801626a:	d10b      	bne.n	8016284 <vTaskPriorityDisinheritAfterTimeout+0x38>
	__asm volatile
 801626c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8016270:	f383 8811 	msr	BASEPRI, r3
 8016274:	f3bf 8f6f 	isb	sy
 8016278:	f3bf 8f4f 	dsb	sy
 801627c:	60fb      	str	r3, [r7, #12]
}
 801627e:	bf00      	nop
 8016280:	bf00      	nop
 8016282:	e7fd      	b.n	8016280 <vTaskPriorityDisinheritAfterTimeout+0x34>

			/* Determine the priority to which the priority of the task that
			holds the mutex should be set.  This will be the greater of the
			holding task's base priority and the priority of the highest
			priority task that is waiting to obtain the mutex. */
			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
 8016284:	69bb      	ldr	r3, [r7, #24]
 8016286:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8016288:	683a      	ldr	r2, [r7, #0]
 801628a:	429a      	cmp	r2, r3
 801628c:	d902      	bls.n	8016294 <vTaskPriorityDisinheritAfterTimeout+0x48>
			{
				uxPriorityToUse = uxHighestPriorityWaitingTask;
 801628e:	683b      	ldr	r3, [r7, #0]
 8016290:	61fb      	str	r3, [r7, #28]
 8016292:	e002      	b.n	801629a <vTaskPriorityDisinheritAfterTimeout+0x4e>
			}
			else
			{
				uxPriorityToUse = pxTCB->uxBasePriority;
 8016294:	69bb      	ldr	r3, [r7, #24]
 8016296:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8016298:	61fb      	str	r3, [r7, #28]
			}

			/* Does the priority need to change? */
			if( pxTCB->uxPriority != uxPriorityToUse )
 801629a:	69bb      	ldr	r3, [r7, #24]
 801629c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 801629e:	69fa      	ldr	r2, [r7, #28]
 80162a0:	429a      	cmp	r2, r3
 80162a2:	d04c      	beq.n	801633e <vTaskPriorityDisinheritAfterTimeout+0xf2>
			{
				/* Only disinherit if no other mutexes are held.  This is a
				simplification in the priority inheritance implementation.  If
				the task that holds the mutex is also holding other mutexes then
				the other mutexes may have caused the priority inheritance. */
				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
 80162a4:	69bb      	ldr	r3, [r7, #24]
 80162a6:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 80162a8:	697a      	ldr	r2, [r7, #20]
 80162aa:	429a      	cmp	r2, r3
 80162ac:	d147      	bne.n	801633e <vTaskPriorityDisinheritAfterTimeout+0xf2>
				{
					/* If a task has timed out because it already holds the
					mutex it was trying to obtain then it cannot of inherited
					its own priority. */
					configASSERT( pxTCB != pxCurrentTCB );
 80162ae:	4b26      	ldr	r3, [pc, #152]	@ (8016348 <vTaskPriorityDisinheritAfterTimeout+0xfc>)
 80162b0:	681b      	ldr	r3, [r3, #0]
 80162b2:	69ba      	ldr	r2, [r7, #24]
 80162b4:	429a      	cmp	r2, r3
 80162b6:	d10b      	bne.n	80162d0 <vTaskPriorityDisinheritAfterTimeout+0x84>
	__asm volatile
 80162b8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80162bc:	f383 8811 	msr	BASEPRI, r3
 80162c0:	f3bf 8f6f 	isb	sy
 80162c4:	f3bf 8f4f 	dsb	sy
 80162c8:	60bb      	str	r3, [r7, #8]
}
 80162ca:	bf00      	nop
 80162cc:	bf00      	nop
 80162ce:	e7fd      	b.n	80162cc <vTaskPriorityDisinheritAfterTimeout+0x80>

					/* Disinherit the priority, remembering the previous
					priority to facilitate determining the subject task's
					state. */
					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
					uxPriorityUsedOnEntry = pxTCB->uxPriority;
 80162d0:	69bb      	ldr	r3, [r7, #24]
 80162d2:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 80162d4:	613b      	str	r3, [r7, #16]
					pxTCB->uxPriority = uxPriorityToUse;
 80162d6:	69bb      	ldr	r3, [r7, #24]
 80162d8:	69fa      	ldr	r2, [r7, #28]
 80162da:	62da      	str	r2, [r3, #44]	@ 0x2c

					/* Only reset the event list item value if the value is not
					being used for anything else. */
					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
 80162dc:	69bb      	ldr	r3, [r7, #24]
 80162de:	699b      	ldr	r3, [r3, #24]
 80162e0:	2b00      	cmp	r3, #0
 80162e2:	db04      	blt.n	80162ee <vTaskPriorityDisinheritAfterTimeout+0xa2>
					{
						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80162e4:	69fb      	ldr	r3, [r7, #28]
 80162e6:	f1c3 0238 	rsb	r2, r3, #56	@ 0x38
 80162ea:	69bb      	ldr	r3, [r7, #24]
 80162ec:	619a      	str	r2, [r3, #24]
					then the task that holds the mutex could be in either the
					Ready, Blocked or Suspended states.  Only remove the task
					from its current state list if it is in the Ready state as
					the task's priority is going to change and there is one
					Ready list per priority. */
					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
 80162ee:	69bb      	ldr	r3, [r7, #24]
 80162f0:	6959      	ldr	r1, [r3, #20]
 80162f2:	693a      	ldr	r2, [r7, #16]
 80162f4:	4613      	mov	r3, r2
 80162f6:	009b      	lsls	r3, r3, #2
 80162f8:	4413      	add	r3, r2
 80162fa:	009b      	lsls	r3, r3, #2
 80162fc:	4a13      	ldr	r2, [pc, #76]	@ (801634c <vTaskPriorityDisinheritAfterTimeout+0x100>)
 80162fe:	4413      	add	r3, r2
 8016300:	4299      	cmp	r1, r3
 8016302:	d11c      	bne.n	801633e <vTaskPriorityDisinheritAfterTimeout+0xf2>
					{
						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 8016304:	69bb      	ldr	r3, [r7, #24]
 8016306:	3304      	adds	r3, #4
 8016308:	4618      	mov	r0, r3
 801630a:	f7fd fe8b 	bl	8014024 <uxListRemove>
						else
						{
							mtCOVERAGE_TEST_MARKER();
						}

						prvAddTaskToReadyList( pxTCB );
 801630e:	69bb      	ldr	r3, [r7, #24]
 8016310:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8016312:	4b0f      	ldr	r3, [pc, #60]	@ (8016350 <vTaskPriorityDisinheritAfterTimeout+0x104>)
 8016314:	681b      	ldr	r3, [r3, #0]
 8016316:	429a      	cmp	r2, r3
 8016318:	d903      	bls.n	8016322 <vTaskPriorityDisinheritAfterTimeout+0xd6>
 801631a:	69bb      	ldr	r3, [r7, #24]
 801631c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 801631e:	4a0c      	ldr	r2, [pc, #48]	@ (8016350 <vTaskPriorityDisinheritAfterTimeout+0x104>)
 8016320:	6013      	str	r3, [r2, #0]
 8016322:	69bb      	ldr	r3, [r7, #24]
 8016324:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8016326:	4613      	mov	r3, r2
 8016328:	009b      	lsls	r3, r3, #2
 801632a:	4413      	add	r3, r2
 801632c:	009b      	lsls	r3, r3, #2
 801632e:	4a07      	ldr	r2, [pc, #28]	@ (801634c <vTaskPriorityDisinheritAfterTimeout+0x100>)
 8016330:	441a      	add	r2, r3
 8016332:	69bb      	ldr	r3, [r7, #24]
 8016334:	3304      	adds	r3, #4
 8016336:	4619      	mov	r1, r3
 8016338:	4610      	mov	r0, r2
 801633a:	f7fd fe16 	bl	8013f6a <vListInsertEnd>
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
 801633e:	bf00      	nop
 8016340:	3720      	adds	r7, #32
 8016342:	46bd      	mov	sp, r7
 8016344:	bd80      	pop	{r7, pc}
 8016346:	bf00      	nop
 8016348:	24002640 	.word	0x24002640
 801634c:	24002644 	.word	0x24002644
 8016350:	24002b1c 	.word	0x24002b1c

08016354 <pvTaskIncrementMutexHeldCount>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
	{
 8016354:	b480      	push	{r7}
 8016356:	af00      	add	r7, sp, #0
		/* If xSemaphoreCreateMutex() is called before any tasks have been created
		then pxCurrentTCB will be NULL. */
		if( pxCurrentTCB != NULL )
 8016358:	4b07      	ldr	r3, [pc, #28]	@ (8016378 <pvTaskIncrementMutexHeldCount+0x24>)
 801635a:	681b      	ldr	r3, [r3, #0]
 801635c:	2b00      	cmp	r3, #0
 801635e:	d004      	beq.n	801636a <pvTaskIncrementMutexHeldCount+0x16>
		{
			( pxCurrentTCB->uxMutexesHeld )++;
 8016360:	4b05      	ldr	r3, [pc, #20]	@ (8016378 <pvTaskIncrementMutexHeldCount+0x24>)
 8016362:	681b      	ldr	r3, [r3, #0]
 8016364:	6d1a      	ldr	r2, [r3, #80]	@ 0x50
 8016366:	3201      	adds	r2, #1
 8016368:	651a      	str	r2, [r3, #80]	@ 0x50
		}

		return pxCurrentTCB;
 801636a:	4b03      	ldr	r3, [pc, #12]	@ (8016378 <pvTaskIncrementMutexHeldCount+0x24>)
 801636c:	681b      	ldr	r3, [r3, #0]
	}
 801636e:	4618      	mov	r0, r3
 8016370:	46bd      	mov	sp, r7
 8016372:	f85d 7b04 	ldr.w	r7, [sp], #4
 8016376:	4770      	bx	lr
 8016378:	24002640 	.word	0x24002640

0801637c <xTaskNotifyWait>:
/*-----------------------------------------------------------*/

#if( configUSE_TASK_NOTIFICATIONS == 1 )

	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
	{
 801637c:	b580      	push	{r7, lr}
 801637e:	b086      	sub	sp, #24
 8016380:	af00      	add	r7, sp, #0
 8016382:	60f8      	str	r0, [r7, #12]
 8016384:	60b9      	str	r1, [r7, #8]
 8016386:	607a      	str	r2, [r7, #4]
 8016388:	603b      	str	r3, [r7, #0]
	BaseType_t xReturn;

		taskENTER_CRITICAL();
 801638a:	f000 ffed 	bl	8017368 <vPortEnterCritical>
		{
			/* Only block if a notification is not already pending. */
			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
 801638e:	4b29      	ldr	r3, [pc, #164]	@ (8016434 <xTaskNotifyWait+0xb8>)
 8016390:	681b      	ldr	r3, [r3, #0]
 8016392:	f893 30a4 	ldrb.w	r3, [r3, #164]	@ 0xa4
 8016396:	b2db      	uxtb	r3, r3
 8016398:	2b02      	cmp	r3, #2
 801639a:	d01c      	beq.n	80163d6 <xTaskNotifyWait+0x5a>
			{
				/* Clear bits in the task's notification value as bits may get
				set	by the notifying task or interrupt.  This can be used to
				clear the value to zero. */
				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
 801639c:	4b25      	ldr	r3, [pc, #148]	@ (8016434 <xTaskNotifyWait+0xb8>)
 801639e:	681b      	ldr	r3, [r3, #0]
 80163a0:	f8d3 10a0 	ldr.w	r1, [r3, #160]	@ 0xa0
 80163a4:	68fa      	ldr	r2, [r7, #12]
 80163a6:	43d2      	mvns	r2, r2
 80163a8:	400a      	ands	r2, r1
 80163aa:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0

				/* Mark this task as waiting for a notification. */
				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
 80163ae:	4b21      	ldr	r3, [pc, #132]	@ (8016434 <xTaskNotifyWait+0xb8>)
 80163b0:	681b      	ldr	r3, [r3, #0]
 80163b2:	2201      	movs	r2, #1
 80163b4:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4

				if( xTicksToWait > ( TickType_t ) 0 )
 80163b8:	683b      	ldr	r3, [r7, #0]
 80163ba:	2b00      	cmp	r3, #0
 80163bc:	d00b      	beq.n	80163d6 <xTaskNotifyWait+0x5a>
				{
					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
 80163be:	2101      	movs	r1, #1
 80163c0:	6838      	ldr	r0, [r7, #0]
 80163c2:	f000 fa09 	bl	80167d8 <prvAddCurrentTaskToDelayedList>

					/* All ports are written to allow a yield in a critical
					section (some will yield immediately, others wait until the
					critical section exits) - but it is not something that
					application code should ever do. */
					portYIELD_WITHIN_API();
 80163c6:	4b1c      	ldr	r3, [pc, #112]	@ (8016438 <xTaskNotifyWait+0xbc>)
 80163c8:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80163cc:	601a      	str	r2, [r3, #0]
 80163ce:	f3bf 8f4f 	dsb	sy
 80163d2:	f3bf 8f6f 	isb	sy
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
		taskEXIT_CRITICAL();
 80163d6:	f000 fff9 	bl	80173cc <vPortExitCritical>

		taskENTER_CRITICAL();
 80163da:	f000 ffc5 	bl	8017368 <vPortEnterCritical>
		{
			traceTASK_NOTIFY_WAIT();

			if( pulNotificationValue != NULL )
 80163de:	687b      	ldr	r3, [r7, #4]
 80163e0:	2b00      	cmp	r3, #0
 80163e2:	d005      	beq.n	80163f0 <xTaskNotifyWait+0x74>
			{
				/* Output the current notification value, which may or may not
				have changed. */
				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
 80163e4:	4b13      	ldr	r3, [pc, #76]	@ (8016434 <xTaskNotifyWait+0xb8>)
 80163e6:	681b      	ldr	r3, [r3, #0]
 80163e8:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
 80163ec:	687b      	ldr	r3, [r7, #4]
 80163ee:	601a      	str	r2, [r3, #0]

			/* If ucNotifyValue is set then either the task never entered the
			blocked state (because a notification was already pending) or the
			task unblocked because of a notification.  Otherwise the task
			unblocked because of a timeout. */
			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
 80163f0:	4b10      	ldr	r3, [pc, #64]	@ (8016434 <xTaskNotifyWait+0xb8>)
 80163f2:	681b      	ldr	r3, [r3, #0]
 80163f4:	f893 30a4 	ldrb.w	r3, [r3, #164]	@ 0xa4
 80163f8:	b2db      	uxtb	r3, r3
 80163fa:	2b02      	cmp	r3, #2
 80163fc:	d002      	beq.n	8016404 <xTaskNotifyWait+0x88>
			{
				/* A notification was not received. */
				xReturn = pdFALSE;
 80163fe:	2300      	movs	r3, #0
 8016400:	617b      	str	r3, [r7, #20]
 8016402:	e00a      	b.n	801641a <xTaskNotifyWait+0x9e>
			}
			else
			{
				/* A notification was already pending or a notification was
				received while the task was waiting. */
				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
 8016404:	4b0b      	ldr	r3, [pc, #44]	@ (8016434 <xTaskNotifyWait+0xb8>)
 8016406:	681b      	ldr	r3, [r3, #0]
 8016408:	f8d3 10a0 	ldr.w	r1, [r3, #160]	@ 0xa0
 801640c:	68ba      	ldr	r2, [r7, #8]
 801640e:	43d2      	mvns	r2, r2
 8016410:	400a      	ands	r2, r1
 8016412:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
				xReturn = pdTRUE;
 8016416:	2301      	movs	r3, #1
 8016418:	617b      	str	r3, [r7, #20]
			}

			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
 801641a:	4b06      	ldr	r3, [pc, #24]	@ (8016434 <xTaskNotifyWait+0xb8>)
 801641c:	681b      	ldr	r3, [r3, #0]
 801641e:	2200      	movs	r2, #0
 8016420:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4
		}
		taskEXIT_CRITICAL();
 8016424:	f000 ffd2 	bl	80173cc <vPortExitCritical>

		return xReturn;
 8016428:	697b      	ldr	r3, [r7, #20]
	}
 801642a:	4618      	mov	r0, r3
 801642c:	3718      	adds	r7, #24
 801642e:	46bd      	mov	sp, r7
 8016430:	bd80      	pop	{r7, pc}
 8016432:	bf00      	nop
 8016434:	24002640 	.word	0x24002640
 8016438:	e000ed04 	.word	0xe000ed04

0801643c <xTaskGenericNotify>:
/*-----------------------------------------------------------*/

#if( configUSE_TASK_NOTIFICATIONS == 1 )

	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
	{
 801643c:	b580      	push	{r7, lr}
 801643e:	b08a      	sub	sp, #40	@ 0x28
 8016440:	af00      	add	r7, sp, #0
 8016442:	60f8      	str	r0, [r7, #12]
 8016444:	60b9      	str	r1, [r7, #8]
 8016446:	603b      	str	r3, [r7, #0]
 8016448:	4613      	mov	r3, r2
 801644a:	71fb      	strb	r3, [r7, #7]
	TCB_t * pxTCB;
	BaseType_t xReturn = pdPASS;
 801644c:	2301      	movs	r3, #1
 801644e:	627b      	str	r3, [r7, #36]	@ 0x24
	uint8_t ucOriginalNotifyState;

		configASSERT( xTaskToNotify );
 8016450:	68fb      	ldr	r3, [r7, #12]
 8016452:	2b00      	cmp	r3, #0
 8016454:	d10b      	bne.n	801646e <xTaskGenericNotify+0x32>
	__asm volatile
 8016456:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801645a:	f383 8811 	msr	BASEPRI, r3
 801645e:	f3bf 8f6f 	isb	sy
 8016462:	f3bf 8f4f 	dsb	sy
 8016466:	61bb      	str	r3, [r7, #24]
}
 8016468:	bf00      	nop
 801646a:	bf00      	nop
 801646c:	e7fd      	b.n	801646a <xTaskGenericNotify+0x2e>
		pxTCB = xTaskToNotify;
 801646e:	68fb      	ldr	r3, [r7, #12]
 8016470:	623b      	str	r3, [r7, #32]

		taskENTER_CRITICAL();
 8016472:	f000 ff79 	bl	8017368 <vPortEnterCritical>
		{
			if( pulPreviousNotificationValue != NULL )
 8016476:	683b      	ldr	r3, [r7, #0]
 8016478:	2b00      	cmp	r3, #0
 801647a:	d004      	beq.n	8016486 <xTaskGenericNotify+0x4a>
			{
				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
 801647c:	6a3b      	ldr	r3, [r7, #32]
 801647e:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
 8016482:	683b      	ldr	r3, [r7, #0]
 8016484:	601a      	str	r2, [r3, #0]
			}

			ucOriginalNotifyState = pxTCB->ucNotifyState;
 8016486:	6a3b      	ldr	r3, [r7, #32]
 8016488:	f893 30a4 	ldrb.w	r3, [r3, #164]	@ 0xa4
 801648c:	77fb      	strb	r3, [r7, #31]

			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
 801648e:	6a3b      	ldr	r3, [r7, #32]
 8016490:	2202      	movs	r2, #2
 8016492:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4

			switch( eAction )
 8016496:	79fb      	ldrb	r3, [r7, #7]
 8016498:	2b04      	cmp	r3, #4
 801649a:	d82e      	bhi.n	80164fa <xTaskGenericNotify+0xbe>
 801649c:	a201      	add	r2, pc, #4	@ (adr r2, 80164a4 <xTaskGenericNotify+0x68>)
 801649e:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80164a2:	bf00      	nop
 80164a4:	0801651f 	.word	0x0801651f
 80164a8:	080164b9 	.word	0x080164b9
 80164ac:	080164cb 	.word	0x080164cb
 80164b0:	080164db 	.word	0x080164db
 80164b4:	080164e5 	.word	0x080164e5
			{
				case eSetBits	:
					pxTCB->ulNotifiedValue |= ulValue;
 80164b8:	6a3b      	ldr	r3, [r7, #32]
 80164ba:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
 80164be:	68bb      	ldr	r3, [r7, #8]
 80164c0:	431a      	orrs	r2, r3
 80164c2:	6a3b      	ldr	r3, [r7, #32]
 80164c4:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 80164c8:	e02c      	b.n	8016524 <xTaskGenericNotify+0xe8>

				case eIncrement	:
					( pxTCB->ulNotifiedValue )++;
 80164ca:	6a3b      	ldr	r3, [r7, #32]
 80164cc:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 80164d0:	1c5a      	adds	r2, r3, #1
 80164d2:	6a3b      	ldr	r3, [r7, #32]
 80164d4:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 80164d8:	e024      	b.n	8016524 <xTaskGenericNotify+0xe8>

				case eSetValueWithOverwrite	:
					pxTCB->ulNotifiedValue = ulValue;
 80164da:	6a3b      	ldr	r3, [r7, #32]
 80164dc:	68ba      	ldr	r2, [r7, #8]
 80164de:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 80164e2:	e01f      	b.n	8016524 <xTaskGenericNotify+0xe8>

				case eSetValueWithoutOverwrite :
					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
 80164e4:	7ffb      	ldrb	r3, [r7, #31]
 80164e6:	2b02      	cmp	r3, #2
 80164e8:	d004      	beq.n	80164f4 <xTaskGenericNotify+0xb8>
					{
						pxTCB->ulNotifiedValue = ulValue;
 80164ea:	6a3b      	ldr	r3, [r7, #32]
 80164ec:	68ba      	ldr	r2, [r7, #8]
 80164ee:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					else
					{
						/* The value could not be written to the task. */
						xReturn = pdFAIL;
					}
					break;
 80164f2:	e017      	b.n	8016524 <xTaskGenericNotify+0xe8>
						xReturn = pdFAIL;
 80164f4:	2300      	movs	r3, #0
 80164f6:	627b      	str	r3, [r7, #36]	@ 0x24
					break;
 80164f8:	e014      	b.n	8016524 <xTaskGenericNotify+0xe8>

				default:
					/* Should not get here if all enums are handled.
					Artificially force an assert by testing a value the
					compiler can't assume is const. */
					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
 80164fa:	6a3b      	ldr	r3, [r7, #32]
 80164fc:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 8016500:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8016504:	d00d      	beq.n	8016522 <xTaskGenericNotify+0xe6>
	__asm volatile
 8016506:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801650a:	f383 8811 	msr	BASEPRI, r3
 801650e:	f3bf 8f6f 	isb	sy
 8016512:	f3bf 8f4f 	dsb	sy
 8016516:	617b      	str	r3, [r7, #20]
}
 8016518:	bf00      	nop
 801651a:	bf00      	nop
 801651c:	e7fd      	b.n	801651a <xTaskGenericNotify+0xde>
					break;
 801651e:	bf00      	nop
 8016520:	e000      	b.n	8016524 <xTaskGenericNotify+0xe8>

					break;
 8016522:	bf00      	nop

			traceTASK_NOTIFY();

			/* If the task is in the blocked state specifically to wait for a
			notification then unblock it now. */
			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
 8016524:	7ffb      	ldrb	r3, [r7, #31]
 8016526:	2b01      	cmp	r3, #1
 8016528:	d13b      	bne.n	80165a2 <xTaskGenericNotify+0x166>
			{
				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 801652a:	6a3b      	ldr	r3, [r7, #32]
 801652c:	3304      	adds	r3, #4
 801652e:	4618      	mov	r0, r3
 8016530:	f7fd fd78 	bl	8014024 <uxListRemove>
				prvAddTaskToReadyList( pxTCB );
 8016534:	6a3b      	ldr	r3, [r7, #32]
 8016536:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8016538:	4b1d      	ldr	r3, [pc, #116]	@ (80165b0 <xTaskGenericNotify+0x174>)
 801653a:	681b      	ldr	r3, [r3, #0]
 801653c:	429a      	cmp	r2, r3
 801653e:	d903      	bls.n	8016548 <xTaskGenericNotify+0x10c>
 8016540:	6a3b      	ldr	r3, [r7, #32]
 8016542:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8016544:	4a1a      	ldr	r2, [pc, #104]	@ (80165b0 <xTaskGenericNotify+0x174>)
 8016546:	6013      	str	r3, [r2, #0]
 8016548:	6a3b      	ldr	r3, [r7, #32]
 801654a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 801654c:	4613      	mov	r3, r2
 801654e:	009b      	lsls	r3, r3, #2
 8016550:	4413      	add	r3, r2
 8016552:	009b      	lsls	r3, r3, #2
 8016554:	4a17      	ldr	r2, [pc, #92]	@ (80165b4 <xTaskGenericNotify+0x178>)
 8016556:	441a      	add	r2, r3
 8016558:	6a3b      	ldr	r3, [r7, #32]
 801655a:	3304      	adds	r3, #4
 801655c:	4619      	mov	r1, r3
 801655e:	4610      	mov	r0, r2
 8016560:	f7fd fd03 	bl	8013f6a <vListInsertEnd>

				/* The task should not have been on an event list. */
				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
 8016564:	6a3b      	ldr	r3, [r7, #32]
 8016566:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8016568:	2b00      	cmp	r3, #0
 801656a:	d00b      	beq.n	8016584 <xTaskGenericNotify+0x148>
	__asm volatile
 801656c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8016570:	f383 8811 	msr	BASEPRI, r3
 8016574:	f3bf 8f6f 	isb	sy
 8016578:	f3bf 8f4f 	dsb	sy
 801657c:	613b      	str	r3, [r7, #16]
}
 801657e:	bf00      	nop
 8016580:	bf00      	nop
 8016582:	e7fd      	b.n	8016580 <xTaskGenericNotify+0x144>
					earliest possible time. */
					prvResetNextTaskUnblockTime();
				}
				#endif

				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
 8016584:	6a3b      	ldr	r3, [r7, #32]
 8016586:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8016588:	4b0b      	ldr	r3, [pc, #44]	@ (80165b8 <xTaskGenericNotify+0x17c>)
 801658a:	681b      	ldr	r3, [r3, #0]
 801658c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 801658e:	429a      	cmp	r2, r3
 8016590:	d907      	bls.n	80165a2 <xTaskGenericNotify+0x166>
				{
					/* The notified task has a priority above the currently
					executing task so a yield is required. */
					taskYIELD_IF_USING_PREEMPTION();
 8016592:	4b0a      	ldr	r3, [pc, #40]	@ (80165bc <xTaskGenericNotify+0x180>)
 8016594:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8016598:	601a      	str	r2, [r3, #0]
 801659a:	f3bf 8f4f 	dsb	sy
 801659e:	f3bf 8f6f 	isb	sy
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
		taskEXIT_CRITICAL();
 80165a2:	f000 ff13 	bl	80173cc <vPortExitCritical>

		return xReturn;
 80165a6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
	}
 80165a8:	4618      	mov	r0, r3
 80165aa:	3728      	adds	r7, #40	@ 0x28
 80165ac:	46bd      	mov	sp, r7
 80165ae:	bd80      	pop	{r7, pc}
 80165b0:	24002b1c 	.word	0x24002b1c
 80165b4:	24002644 	.word	0x24002644
 80165b8:	24002640 	.word	0x24002640
 80165bc:	e000ed04 	.word	0xe000ed04

080165c0 <xTaskGenericNotifyFromISR>:
/*-----------------------------------------------------------*/

#if( configUSE_TASK_NOTIFICATIONS == 1 )

	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
	{
 80165c0:	b580      	push	{r7, lr}
 80165c2:	b08e      	sub	sp, #56	@ 0x38
 80165c4:	af00      	add	r7, sp, #0
 80165c6:	60f8      	str	r0, [r7, #12]
 80165c8:	60b9      	str	r1, [r7, #8]
 80165ca:	603b      	str	r3, [r7, #0]
 80165cc:	4613      	mov	r3, r2
 80165ce:	71fb      	strb	r3, [r7, #7]
	TCB_t * pxTCB;
	uint8_t ucOriginalNotifyState;
	BaseType_t xReturn = pdPASS;
 80165d0:	2301      	movs	r3, #1
 80165d2:	637b      	str	r3, [r7, #52]	@ 0x34
	UBaseType_t uxSavedInterruptStatus;

		configASSERT( xTaskToNotify );
 80165d4:	68fb      	ldr	r3, [r7, #12]
 80165d6:	2b00      	cmp	r3, #0
 80165d8:	d10b      	bne.n	80165f2 <xTaskGenericNotifyFromISR+0x32>
	__asm volatile
 80165da:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80165de:	f383 8811 	msr	BASEPRI, r3
 80165e2:	f3bf 8f6f 	isb	sy
 80165e6:	f3bf 8f4f 	dsb	sy
 80165ea:	627b      	str	r3, [r7, #36]	@ 0x24
}
 80165ec:	bf00      	nop
 80165ee:	bf00      	nop
 80165f0:	e7fd      	b.n	80165ee <xTaskGenericNotifyFromISR+0x2e>
		below the maximum system call interrupt priority.  FreeRTOS maintains a
		separate interrupt safe API to ensure interrupt entry is as fast and as
		simple as possible.  More information (albeit Cortex-M specific) is
		provided on the following link:
		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 80165f2:	f000 ff99 	bl	8017528 <vPortValidateInterruptPriority>

		pxTCB = xTaskToNotify;
 80165f6:	68fb      	ldr	r3, [r7, #12]
 80165f8:	633b      	str	r3, [r7, #48]	@ 0x30
	__asm volatile
 80165fa:	f3ef 8211 	mrs	r2, BASEPRI
 80165fe:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8016602:	f383 8811 	msr	BASEPRI, r3
 8016606:	f3bf 8f6f 	isb	sy
 801660a:	f3bf 8f4f 	dsb	sy
 801660e:	623a      	str	r2, [r7, #32]
 8016610:	61fb      	str	r3, [r7, #28]
	return ulOriginalBASEPRI;
 8016612:	6a3b      	ldr	r3, [r7, #32]

		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 8016614:	62fb      	str	r3, [r7, #44]	@ 0x2c
		{
			if( pulPreviousNotificationValue != NULL )
 8016616:	683b      	ldr	r3, [r7, #0]
 8016618:	2b00      	cmp	r3, #0
 801661a:	d004      	beq.n	8016626 <xTaskGenericNotifyFromISR+0x66>
			{
				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
 801661c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801661e:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
 8016622:	683b      	ldr	r3, [r7, #0]
 8016624:	601a      	str	r2, [r3, #0]
			}

			ucOriginalNotifyState = pxTCB->ucNotifyState;
 8016626:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8016628:	f893 30a4 	ldrb.w	r3, [r3, #164]	@ 0xa4
 801662c:	f887 302b 	strb.w	r3, [r7, #43]	@ 0x2b
			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
 8016630:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8016632:	2202      	movs	r2, #2
 8016634:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4

			switch( eAction )
 8016638:	79fb      	ldrb	r3, [r7, #7]
 801663a:	2b04      	cmp	r3, #4
 801663c:	d82e      	bhi.n	801669c <xTaskGenericNotifyFromISR+0xdc>
 801663e:	a201      	add	r2, pc, #4	@ (adr r2, 8016644 <xTaskGenericNotifyFromISR+0x84>)
 8016640:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8016644:	080166c1 	.word	0x080166c1
 8016648:	08016659 	.word	0x08016659
 801664c:	0801666b 	.word	0x0801666b
 8016650:	0801667b 	.word	0x0801667b
 8016654:	08016685 	.word	0x08016685
			{
				case eSetBits	:
					pxTCB->ulNotifiedValue |= ulValue;
 8016658:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801665a:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
 801665e:	68bb      	ldr	r3, [r7, #8]
 8016660:	431a      	orrs	r2, r3
 8016662:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8016664:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 8016668:	e02d      	b.n	80166c6 <xTaskGenericNotifyFromISR+0x106>

				case eIncrement	:
					( pxTCB->ulNotifiedValue )++;
 801666a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801666c:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 8016670:	1c5a      	adds	r2, r3, #1
 8016672:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8016674:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 8016678:	e025      	b.n	80166c6 <xTaskGenericNotifyFromISR+0x106>

				case eSetValueWithOverwrite	:
					pxTCB->ulNotifiedValue = ulValue;
 801667a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801667c:	68ba      	ldr	r2, [r7, #8]
 801667e:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					break;
 8016682:	e020      	b.n	80166c6 <xTaskGenericNotifyFromISR+0x106>

				case eSetValueWithoutOverwrite :
					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
 8016684:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
 8016688:	2b02      	cmp	r3, #2
 801668a:	d004      	beq.n	8016696 <xTaskGenericNotifyFromISR+0xd6>
					{
						pxTCB->ulNotifiedValue = ulValue;
 801668c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801668e:	68ba      	ldr	r2, [r7, #8]
 8016690:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
					else
					{
						/* The value could not be written to the task. */
						xReturn = pdFAIL;
					}
					break;
 8016694:	e017      	b.n	80166c6 <xTaskGenericNotifyFromISR+0x106>
						xReturn = pdFAIL;
 8016696:	2300      	movs	r3, #0
 8016698:	637b      	str	r3, [r7, #52]	@ 0x34
					break;
 801669a:	e014      	b.n	80166c6 <xTaskGenericNotifyFromISR+0x106>

				default:
					/* Should not get here if all enums are handled.
					Artificially force an assert by testing a value the
					compiler can't assume is const. */
					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
 801669c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801669e:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
 80166a2:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80166a6:	d00d      	beq.n	80166c4 <xTaskGenericNotifyFromISR+0x104>
	__asm volatile
 80166a8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80166ac:	f383 8811 	msr	BASEPRI, r3
 80166b0:	f3bf 8f6f 	isb	sy
 80166b4:	f3bf 8f4f 	dsb	sy
 80166b8:	61bb      	str	r3, [r7, #24]
}
 80166ba:	bf00      	nop
 80166bc:	bf00      	nop
 80166be:	e7fd      	b.n	80166bc <xTaskGenericNotifyFromISR+0xfc>
					break;
 80166c0:	bf00      	nop
 80166c2:	e000      	b.n	80166c6 <xTaskGenericNotifyFromISR+0x106>
					break;
 80166c4:	bf00      	nop

			traceTASK_NOTIFY_FROM_ISR();

			/* If the task is in the blocked state specifically to wait for a
			notification then unblock it now. */
			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
 80166c6:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
 80166ca:	2b01      	cmp	r3, #1
 80166cc:	d147      	bne.n	801675e <xTaskGenericNotifyFromISR+0x19e>
			{
				/* The task should not have been on an event list. */
				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
 80166ce:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80166d0:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 80166d2:	2b00      	cmp	r3, #0
 80166d4:	d00b      	beq.n	80166ee <xTaskGenericNotifyFromISR+0x12e>
	__asm volatile
 80166d6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80166da:	f383 8811 	msr	BASEPRI, r3
 80166de:	f3bf 8f6f 	isb	sy
 80166e2:	f3bf 8f4f 	dsb	sy
 80166e6:	617b      	str	r3, [r7, #20]
}
 80166e8:	bf00      	nop
 80166ea:	bf00      	nop
 80166ec:	e7fd      	b.n	80166ea <xTaskGenericNotifyFromISR+0x12a>

				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 80166ee:	4b21      	ldr	r3, [pc, #132]	@ (8016774 <xTaskGenericNotifyFromISR+0x1b4>)
 80166f0:	681b      	ldr	r3, [r3, #0]
 80166f2:	2b00      	cmp	r3, #0
 80166f4:	d11d      	bne.n	8016732 <xTaskGenericNotifyFromISR+0x172>
				{
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 80166f6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80166f8:	3304      	adds	r3, #4
 80166fa:	4618      	mov	r0, r3
 80166fc:	f7fd fc92 	bl	8014024 <uxListRemove>
					prvAddTaskToReadyList( pxTCB );
 8016700:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8016702:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8016704:	4b1c      	ldr	r3, [pc, #112]	@ (8016778 <xTaskGenericNotifyFromISR+0x1b8>)
 8016706:	681b      	ldr	r3, [r3, #0]
 8016708:	429a      	cmp	r2, r3
 801670a:	d903      	bls.n	8016714 <xTaskGenericNotifyFromISR+0x154>
 801670c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 801670e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8016710:	4a19      	ldr	r2, [pc, #100]	@ (8016778 <xTaskGenericNotifyFromISR+0x1b8>)
 8016712:	6013      	str	r3, [r2, #0]
 8016714:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8016716:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8016718:	4613      	mov	r3, r2
 801671a:	009b      	lsls	r3, r3, #2
 801671c:	4413      	add	r3, r2
 801671e:	009b      	lsls	r3, r3, #2
 8016720:	4a16      	ldr	r2, [pc, #88]	@ (801677c <xTaskGenericNotifyFromISR+0x1bc>)
 8016722:	441a      	add	r2, r3
 8016724:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8016726:	3304      	adds	r3, #4
 8016728:	4619      	mov	r1, r3
 801672a:	4610      	mov	r0, r2
 801672c:	f7fd fc1d 	bl	8013f6a <vListInsertEnd>
 8016730:	e005      	b.n	801673e <xTaskGenericNotifyFromISR+0x17e>
				}
				else
				{
					/* The delayed and ready lists cannot be accessed, so hold
					this task pending until the scheduler is resumed. */
					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
 8016732:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8016734:	3318      	adds	r3, #24
 8016736:	4619      	mov	r1, r3
 8016738:	4811      	ldr	r0, [pc, #68]	@ (8016780 <xTaskGenericNotifyFromISR+0x1c0>)
 801673a:	f7fd fc16 	bl	8013f6a <vListInsertEnd>
				}

				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
 801673e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 8016740:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8016742:	4b10      	ldr	r3, [pc, #64]	@ (8016784 <xTaskGenericNotifyFromISR+0x1c4>)
 8016744:	681b      	ldr	r3, [r3, #0]
 8016746:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8016748:	429a      	cmp	r2, r3
 801674a:	d908      	bls.n	801675e <xTaskGenericNotifyFromISR+0x19e>
				{
					/* The notified task has a priority above the currently
					executing task so a yield is required. */
					if( pxHigherPriorityTaskWoken != NULL )
 801674c:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 801674e:	2b00      	cmp	r3, #0
 8016750:	d002      	beq.n	8016758 <xTaskGenericNotifyFromISR+0x198>
					{
						*pxHigherPriorityTaskWoken = pdTRUE;
 8016752:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 8016754:	2201      	movs	r2, #1
 8016756:	601a      	str	r2, [r3, #0]
					}

					/* Mark that a yield is pending in case the user is not
					using the "xHigherPriorityTaskWoken" parameter to an ISR
					safe FreeRTOS function. */
					xYieldPending = pdTRUE;
 8016758:	4b0b      	ldr	r3, [pc, #44]	@ (8016788 <xTaskGenericNotifyFromISR+0x1c8>)
 801675a:	2201      	movs	r2, #1
 801675c:	601a      	str	r2, [r3, #0]
 801675e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8016760:	613b      	str	r3, [r7, #16]
	__asm volatile
 8016762:	693b      	ldr	r3, [r7, #16]
 8016764:	f383 8811 	msr	BASEPRI, r3
}
 8016768:	bf00      	nop
				}
			}
		}
		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

		return xReturn;
 801676a:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
	}
 801676c:	4618      	mov	r0, r3
 801676e:	3738      	adds	r7, #56	@ 0x38
 8016770:	46bd      	mov	sp, r7
 8016772:	bd80      	pop	{r7, pc}
 8016774:	24002b3c 	.word	0x24002b3c
 8016778:	24002b1c 	.word	0x24002b1c
 801677c:	24002644 	.word	0x24002644
 8016780:	24002ad4 	.word	0x24002ad4
 8016784:	24002640 	.word	0x24002640
 8016788:	24002b28 	.word	0x24002b28

0801678c <xTaskNotifyStateClear>:
/*-----------------------------------------------------------*/

#if( configUSE_TASK_NOTIFICATIONS == 1 )

	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
	{
 801678c:	b580      	push	{r7, lr}
 801678e:	b084      	sub	sp, #16
 8016790:	af00      	add	r7, sp, #0
 8016792:	6078      	str	r0, [r7, #4]
	TCB_t *pxTCB;
	BaseType_t xReturn;

		/* If null is passed in here then it is the calling task that is having
		its notification state cleared. */
		pxTCB = prvGetTCBFromHandle( xTask );
 8016794:	687b      	ldr	r3, [r7, #4]
 8016796:	2b00      	cmp	r3, #0
 8016798:	d102      	bne.n	80167a0 <xTaskNotifyStateClear+0x14>
 801679a:	4b0e      	ldr	r3, [pc, #56]	@ (80167d4 <xTaskNotifyStateClear+0x48>)
 801679c:	681b      	ldr	r3, [r3, #0]
 801679e:	e000      	b.n	80167a2 <xTaskNotifyStateClear+0x16>
 80167a0:	687b      	ldr	r3, [r7, #4]
 80167a2:	60bb      	str	r3, [r7, #8]

		taskENTER_CRITICAL();
 80167a4:	f000 fde0 	bl	8017368 <vPortEnterCritical>
		{
			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
 80167a8:	68bb      	ldr	r3, [r7, #8]
 80167aa:	f893 30a4 	ldrb.w	r3, [r3, #164]	@ 0xa4
 80167ae:	b2db      	uxtb	r3, r3
 80167b0:	2b02      	cmp	r3, #2
 80167b2:	d106      	bne.n	80167c2 <xTaskNotifyStateClear+0x36>
			{
				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
 80167b4:	68bb      	ldr	r3, [r7, #8]
 80167b6:	2200      	movs	r2, #0
 80167b8:	f883 20a4 	strb.w	r2, [r3, #164]	@ 0xa4
				xReturn = pdPASS;
 80167bc:	2301      	movs	r3, #1
 80167be:	60fb      	str	r3, [r7, #12]
 80167c0:	e001      	b.n	80167c6 <xTaskNotifyStateClear+0x3a>
			}
			else
			{
				xReturn = pdFAIL;
 80167c2:	2300      	movs	r3, #0
 80167c4:	60fb      	str	r3, [r7, #12]
			}
		}
		taskEXIT_CRITICAL();
 80167c6:	f000 fe01 	bl	80173cc <vPortExitCritical>

		return xReturn;
 80167ca:	68fb      	ldr	r3, [r7, #12]
	}
 80167cc:	4618      	mov	r0, r3
 80167ce:	3710      	adds	r7, #16
 80167d0:	46bd      	mov	sp, r7
 80167d2:	bd80      	pop	{r7, pc}
 80167d4:	24002640 	.word	0x24002640

080167d8 <prvAddCurrentTaskToDelayedList>:

#endif
/*-----------------------------------------------------------*/

static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
 80167d8:	b580      	push	{r7, lr}
 80167da:	b084      	sub	sp, #16
 80167dc:	af00      	add	r7, sp, #0
 80167de:	6078      	str	r0, [r7, #4]
 80167e0:	6039      	str	r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
 80167e2:	4b21      	ldr	r3, [pc, #132]	@ (8016868 <prvAddCurrentTaskToDelayedList+0x90>)
 80167e4:	681b      	ldr	r3, [r3, #0]
 80167e6:	60fb      	str	r3, [r7, #12]
	}
	#endif

	/* Remove the task from the ready list before adding it to the blocked list
	as the same list item is used for both lists. */
	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 80167e8:	4b20      	ldr	r3, [pc, #128]	@ (801686c <prvAddCurrentTaskToDelayedList+0x94>)
 80167ea:	681b      	ldr	r3, [r3, #0]
 80167ec:	3304      	adds	r3, #4
 80167ee:	4618      	mov	r0, r3
 80167f0:	f7fd fc18 	bl	8014024 <uxListRemove>
		mtCOVERAGE_TEST_MARKER();
	}

	#if ( INCLUDE_vTaskSuspend == 1 )
	{
		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
 80167f4:	687b      	ldr	r3, [r7, #4]
 80167f6:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 80167fa:	d10a      	bne.n	8016812 <prvAddCurrentTaskToDelayedList+0x3a>
 80167fc:	683b      	ldr	r3, [r7, #0]
 80167fe:	2b00      	cmp	r3, #0
 8016800:	d007      	beq.n	8016812 <prvAddCurrentTaskToDelayedList+0x3a>
		{
			/* Add the task to the suspended task list instead of a delayed task
			list to ensure it is not woken by a timing event.  It will block
			indefinitely. */
			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
 8016802:	4b1a      	ldr	r3, [pc, #104]	@ (801686c <prvAddCurrentTaskToDelayedList+0x94>)
 8016804:	681b      	ldr	r3, [r3, #0]
 8016806:	3304      	adds	r3, #4
 8016808:	4619      	mov	r1, r3
 801680a:	4819      	ldr	r0, [pc, #100]	@ (8016870 <prvAddCurrentTaskToDelayedList+0x98>)
 801680c:	f7fd fbad 	bl	8013f6a <vListInsertEnd>

		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
		( void ) xCanBlockIndefinitely;
	}
	#endif /* INCLUDE_vTaskSuspend */
}
 8016810:	e026      	b.n	8016860 <prvAddCurrentTaskToDelayedList+0x88>
			xTimeToWake = xConstTickCount + xTicksToWait;
 8016812:	68fa      	ldr	r2, [r7, #12]
 8016814:	687b      	ldr	r3, [r7, #4]
 8016816:	4413      	add	r3, r2
 8016818:	60bb      	str	r3, [r7, #8]
			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
 801681a:	4b14      	ldr	r3, [pc, #80]	@ (801686c <prvAddCurrentTaskToDelayedList+0x94>)
 801681c:	681b      	ldr	r3, [r3, #0]
 801681e:	68ba      	ldr	r2, [r7, #8]
 8016820:	605a      	str	r2, [r3, #4]
			if( xTimeToWake < xConstTickCount )
 8016822:	68ba      	ldr	r2, [r7, #8]
 8016824:	68fb      	ldr	r3, [r7, #12]
 8016826:	429a      	cmp	r2, r3
 8016828:	d209      	bcs.n	801683e <prvAddCurrentTaskToDelayedList+0x66>
				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 801682a:	4b12      	ldr	r3, [pc, #72]	@ (8016874 <prvAddCurrentTaskToDelayedList+0x9c>)
 801682c:	681a      	ldr	r2, [r3, #0]
 801682e:	4b0f      	ldr	r3, [pc, #60]	@ (801686c <prvAddCurrentTaskToDelayedList+0x94>)
 8016830:	681b      	ldr	r3, [r3, #0]
 8016832:	3304      	adds	r3, #4
 8016834:	4619      	mov	r1, r3
 8016836:	4610      	mov	r0, r2
 8016838:	f7fd fbbb 	bl	8013fb2 <vListInsert>
}
 801683c:	e010      	b.n	8016860 <prvAddCurrentTaskToDelayedList+0x88>
				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 801683e:	4b0e      	ldr	r3, [pc, #56]	@ (8016878 <prvAddCurrentTaskToDelayedList+0xa0>)
 8016840:	681a      	ldr	r2, [r3, #0]
 8016842:	4b0a      	ldr	r3, [pc, #40]	@ (801686c <prvAddCurrentTaskToDelayedList+0x94>)
 8016844:	681b      	ldr	r3, [r3, #0]
 8016846:	3304      	adds	r3, #4
 8016848:	4619      	mov	r1, r3
 801684a:	4610      	mov	r0, r2
 801684c:	f7fd fbb1 	bl	8013fb2 <vListInsert>
				if( xTimeToWake < xNextTaskUnblockTime )
 8016850:	4b0a      	ldr	r3, [pc, #40]	@ (801687c <prvAddCurrentTaskToDelayedList+0xa4>)
 8016852:	681b      	ldr	r3, [r3, #0]
 8016854:	68ba      	ldr	r2, [r7, #8]
 8016856:	429a      	cmp	r2, r3
 8016858:	d202      	bcs.n	8016860 <prvAddCurrentTaskToDelayedList+0x88>
					xNextTaskUnblockTime = xTimeToWake;
 801685a:	4a08      	ldr	r2, [pc, #32]	@ (801687c <prvAddCurrentTaskToDelayedList+0xa4>)
 801685c:	68bb      	ldr	r3, [r7, #8]
 801685e:	6013      	str	r3, [r2, #0]
}
 8016860:	bf00      	nop
 8016862:	3710      	adds	r7, #16
 8016864:	46bd      	mov	sp, r7
 8016866:	bd80      	pop	{r7, pc}
 8016868:	24002b18 	.word	0x24002b18
 801686c:	24002640 	.word	0x24002640
 8016870:	24002b00 	.word	0x24002b00
 8016874:	24002ad0 	.word	0x24002ad0
 8016878:	24002acc 	.word	0x24002acc
 801687c:	24002b34 	.word	0x24002b34

08016880 <xTimerCreateTimerTask>:
									TimerCallbackFunction_t pxCallbackFunction,
									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/

BaseType_t xTimerCreateTimerTask( void )
{
 8016880:	b580      	push	{r7, lr}
 8016882:	b08a      	sub	sp, #40	@ 0x28
 8016884:	af04      	add	r7, sp, #16
BaseType_t xReturn = pdFAIL;
 8016886:	2300      	movs	r3, #0
 8016888:	617b      	str	r3, [r7, #20]

	/* This function is called when the scheduler is started if
	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
	timer service task has been created/initialised.  If timers have already
	been created then the initialisation will already have been performed. */
	prvCheckForValidListAndQueue();
 801688a:	f000 fbb1 	bl	8016ff0 <prvCheckForValidListAndQueue>

	if( xTimerQueue != NULL )
 801688e:	4b1d      	ldr	r3, [pc, #116]	@ (8016904 <xTimerCreateTimerTask+0x84>)
 8016890:	681b      	ldr	r3, [r3, #0]
 8016892:	2b00      	cmp	r3, #0
 8016894:	d021      	beq.n	80168da <xTimerCreateTimerTask+0x5a>
	{
		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
		{
			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
 8016896:	2300      	movs	r3, #0
 8016898:	60fb      	str	r3, [r7, #12]
			StackType_t *pxTimerTaskStackBuffer = NULL;
 801689a:	2300      	movs	r3, #0
 801689c:	60bb      	str	r3, [r7, #8]
			uint32_t ulTimerTaskStackSize;

			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
 801689e:	1d3a      	adds	r2, r7, #4
 80168a0:	f107 0108 	add.w	r1, r7, #8
 80168a4:	f107 030c 	add.w	r3, r7, #12
 80168a8:	4618      	mov	r0, r3
 80168aa:	f7fd fb17 	bl	8013edc <vApplicationGetTimerTaskMemory>
			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
 80168ae:	6879      	ldr	r1, [r7, #4]
 80168b0:	68bb      	ldr	r3, [r7, #8]
 80168b2:	68fa      	ldr	r2, [r7, #12]
 80168b4:	9202      	str	r2, [sp, #8]
 80168b6:	9301      	str	r3, [sp, #4]
 80168b8:	2302      	movs	r3, #2
 80168ba:	9300      	str	r3, [sp, #0]
 80168bc:	2300      	movs	r3, #0
 80168be:	460a      	mov	r2, r1
 80168c0:	4911      	ldr	r1, [pc, #68]	@ (8016908 <xTimerCreateTimerTask+0x88>)
 80168c2:	4812      	ldr	r0, [pc, #72]	@ (801690c <xTimerCreateTimerTask+0x8c>)
 80168c4:	f7fe fd2f 	bl	8015326 <xTaskCreateStatic>
 80168c8:	4603      	mov	r3, r0
 80168ca:	4a11      	ldr	r2, [pc, #68]	@ (8016910 <xTimerCreateTimerTask+0x90>)
 80168cc:	6013      	str	r3, [r2, #0]
													NULL,
													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
													pxTimerTaskStackBuffer,
													pxTimerTaskTCBBuffer );

			if( xTimerTaskHandle != NULL )
 80168ce:	4b10      	ldr	r3, [pc, #64]	@ (8016910 <xTimerCreateTimerTask+0x90>)
 80168d0:	681b      	ldr	r3, [r3, #0]
 80168d2:	2b00      	cmp	r3, #0
 80168d4:	d001      	beq.n	80168da <xTimerCreateTimerTask+0x5a>
			{
				xReturn = pdPASS;
 80168d6:	2301      	movs	r3, #1
 80168d8:	617b      	str	r3, [r7, #20]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	configASSERT( xReturn );
 80168da:	697b      	ldr	r3, [r7, #20]
 80168dc:	2b00      	cmp	r3, #0
 80168de:	d10b      	bne.n	80168f8 <xTimerCreateTimerTask+0x78>
	__asm volatile
 80168e0:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80168e4:	f383 8811 	msr	BASEPRI, r3
 80168e8:	f3bf 8f6f 	isb	sy
 80168ec:	f3bf 8f4f 	dsb	sy
 80168f0:	613b      	str	r3, [r7, #16]
}
 80168f2:	bf00      	nop
 80168f4:	bf00      	nop
 80168f6:	e7fd      	b.n	80168f4 <xTimerCreateTimerTask+0x74>
	return xReturn;
 80168f8:	697b      	ldr	r3, [r7, #20]
}
 80168fa:	4618      	mov	r0, r3
 80168fc:	3718      	adds	r7, #24
 80168fe:	46bd      	mov	sp, r7
 8016900:	bd80      	pop	{r7, pc}
 8016902:	bf00      	nop
 8016904:	24002b70 	.word	0x24002b70
 8016908:	080189b4 	.word	0x080189b4
 801690c:	08016b89 	.word	0x08016b89
 8016910:	24002b74 	.word	0x24002b74

08016914 <xTimerCreate>:
	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
								const TickType_t xTimerPeriodInTicks,
								const UBaseType_t uxAutoReload,
								void * const pvTimerID,
								TimerCallbackFunction_t pxCallbackFunction )
	{
 8016914:	b580      	push	{r7, lr}
 8016916:	b088      	sub	sp, #32
 8016918:	af02      	add	r7, sp, #8
 801691a:	60f8      	str	r0, [r7, #12]
 801691c:	60b9      	str	r1, [r7, #8]
 801691e:	607a      	str	r2, [r7, #4]
 8016920:	603b      	str	r3, [r7, #0]
	Timer_t *pxNewTimer;

		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
 8016922:	202c      	movs	r0, #44	@ 0x2c
 8016924:	f000 fe42 	bl	80175ac <pvPortMalloc>
 8016928:	6178      	str	r0, [r7, #20]

		if( pxNewTimer != NULL )
 801692a:	697b      	ldr	r3, [r7, #20]
 801692c:	2b00      	cmp	r3, #0
 801692e:	d00d      	beq.n	801694c <xTimerCreate+0x38>
		{
			/* Status is thus far zero as the timer is not created statically
			and has not been started.  The auto-reload bit may get set in
			prvInitialiseNewTimer. */
			pxNewTimer->ucStatus = 0x00;
 8016930:	697b      	ldr	r3, [r7, #20]
 8016932:	2200      	movs	r2, #0
 8016934:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
 8016938:	697b      	ldr	r3, [r7, #20]
 801693a:	9301      	str	r3, [sp, #4]
 801693c:	6a3b      	ldr	r3, [r7, #32]
 801693e:	9300      	str	r3, [sp, #0]
 8016940:	683b      	ldr	r3, [r7, #0]
 8016942:	687a      	ldr	r2, [r7, #4]
 8016944:	68b9      	ldr	r1, [r7, #8]
 8016946:	68f8      	ldr	r0, [r7, #12]
 8016948:	f000 f845 	bl	80169d6 <prvInitialiseNewTimer>
		}

		return pxNewTimer;
 801694c:	697b      	ldr	r3, [r7, #20]
	}
 801694e:	4618      	mov	r0, r3
 8016950:	3718      	adds	r7, #24
 8016952:	46bd      	mov	sp, r7
 8016954:	bd80      	pop	{r7, pc}

08016956 <xTimerCreateStatic>:
										const TickType_t xTimerPeriodInTicks,
										const UBaseType_t uxAutoReload,
										void * const pvTimerID,
										TimerCallbackFunction_t pxCallbackFunction,
										StaticTimer_t *pxTimerBuffer )
	{
 8016956:	b580      	push	{r7, lr}
 8016958:	b08a      	sub	sp, #40	@ 0x28
 801695a:	af02      	add	r7, sp, #8
 801695c:	60f8      	str	r0, [r7, #12]
 801695e:	60b9      	str	r1, [r7, #8]
 8016960:	607a      	str	r2, [r7, #4]
 8016962:	603b      	str	r3, [r7, #0]
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticTimer_t equals the size of the real timer
			structure. */
			volatile size_t xSize = sizeof( StaticTimer_t );
 8016964:	232c      	movs	r3, #44	@ 0x2c
 8016966:	613b      	str	r3, [r7, #16]
			configASSERT( xSize == sizeof( Timer_t ) );
 8016968:	693b      	ldr	r3, [r7, #16]
 801696a:	2b2c      	cmp	r3, #44	@ 0x2c
 801696c:	d00b      	beq.n	8016986 <xTimerCreateStatic+0x30>
	__asm volatile
 801696e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8016972:	f383 8811 	msr	BASEPRI, r3
 8016976:	f3bf 8f6f 	isb	sy
 801697a:	f3bf 8f4f 	dsb	sy
 801697e:	61bb      	str	r3, [r7, #24]
}
 8016980:	bf00      	nop
 8016982:	bf00      	nop
 8016984:	e7fd      	b.n	8016982 <xTimerCreateStatic+0x2c>
			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
 8016986:	693b      	ldr	r3, [r7, #16]
		}
		#endif /* configASSERT_DEFINED */

		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
		configASSERT( pxTimerBuffer );
 8016988:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 801698a:	2b00      	cmp	r3, #0
 801698c:	d10b      	bne.n	80169a6 <xTimerCreateStatic+0x50>
	__asm volatile
 801698e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8016992:	f383 8811 	msr	BASEPRI, r3
 8016996:	f3bf 8f6f 	isb	sy
 801699a:	f3bf 8f4f 	dsb	sy
 801699e:	617b      	str	r3, [r7, #20]
}
 80169a0:	bf00      	nop
 80169a2:	bf00      	nop
 80169a4:	e7fd      	b.n	80169a2 <xTimerCreateStatic+0x4c>
		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
 80169a6:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80169a8:	61fb      	str	r3, [r7, #28]

		if( pxNewTimer != NULL )
 80169aa:	69fb      	ldr	r3, [r7, #28]
 80169ac:	2b00      	cmp	r3, #0
 80169ae:	d00d      	beq.n	80169cc <xTimerCreateStatic+0x76>
		{
			/* Timers can be created statically or dynamically so note this
			timer was created statically in case it is later deleted.  The
			auto-reload bit may get set in prvInitialiseNewTimer(). */
			pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
 80169b0:	69fb      	ldr	r3, [r7, #28]
 80169b2:	2202      	movs	r2, #2
 80169b4:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28

			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
 80169b8:	69fb      	ldr	r3, [r7, #28]
 80169ba:	9301      	str	r3, [sp, #4]
 80169bc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80169be:	9300      	str	r3, [sp, #0]
 80169c0:	683b      	ldr	r3, [r7, #0]
 80169c2:	687a      	ldr	r2, [r7, #4]
 80169c4:	68b9      	ldr	r1, [r7, #8]
 80169c6:	68f8      	ldr	r0, [r7, #12]
 80169c8:	f000 f805 	bl	80169d6 <prvInitialiseNewTimer>
		}

		return pxNewTimer;
 80169cc:	69fb      	ldr	r3, [r7, #28]
	}
 80169ce:	4618      	mov	r0, r3
 80169d0:	3720      	adds	r7, #32
 80169d2:	46bd      	mov	sp, r7
 80169d4:	bd80      	pop	{r7, pc}

080169d6 <prvInitialiseNewTimer>:
									const TickType_t xTimerPeriodInTicks,
									const UBaseType_t uxAutoReload,
									void * const pvTimerID,
									TimerCallbackFunction_t pxCallbackFunction,
									Timer_t *pxNewTimer )
{
 80169d6:	b580      	push	{r7, lr}
 80169d8:	b086      	sub	sp, #24
 80169da:	af00      	add	r7, sp, #0
 80169dc:	60f8      	str	r0, [r7, #12]
 80169de:	60b9      	str	r1, [r7, #8]
 80169e0:	607a      	str	r2, [r7, #4]
 80169e2:	603b      	str	r3, [r7, #0]
	/* 0 is not a valid value for xTimerPeriodInTicks. */
	configASSERT( ( xTimerPeriodInTicks > 0 ) );
 80169e4:	68bb      	ldr	r3, [r7, #8]
 80169e6:	2b00      	cmp	r3, #0
 80169e8:	d10b      	bne.n	8016a02 <prvInitialiseNewTimer+0x2c>
	__asm volatile
 80169ea:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80169ee:	f383 8811 	msr	BASEPRI, r3
 80169f2:	f3bf 8f6f 	isb	sy
 80169f6:	f3bf 8f4f 	dsb	sy
 80169fa:	617b      	str	r3, [r7, #20]
}
 80169fc:	bf00      	nop
 80169fe:	bf00      	nop
 8016a00:	e7fd      	b.n	80169fe <prvInitialiseNewTimer+0x28>

	if( pxNewTimer != NULL )
 8016a02:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8016a04:	2b00      	cmp	r3, #0
 8016a06:	d01e      	beq.n	8016a46 <prvInitialiseNewTimer+0x70>
	{
		/* Ensure the infrastructure used by the timer service task has been
		created/initialised. */
		prvCheckForValidListAndQueue();
 8016a08:	f000 faf2 	bl	8016ff0 <prvCheckForValidListAndQueue>

		/* Initialise the timer structure members using the function
		parameters. */
		pxNewTimer->pcTimerName = pcTimerName;
 8016a0c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8016a0e:	68fa      	ldr	r2, [r7, #12]
 8016a10:	601a      	str	r2, [r3, #0]
		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
 8016a12:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8016a14:	68ba      	ldr	r2, [r7, #8]
 8016a16:	619a      	str	r2, [r3, #24]
		pxNewTimer->pvTimerID = pvTimerID;
 8016a18:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8016a1a:	683a      	ldr	r2, [r7, #0]
 8016a1c:	61da      	str	r2, [r3, #28]
		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
 8016a1e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8016a20:	6a3a      	ldr	r2, [r7, #32]
 8016a22:	621a      	str	r2, [r3, #32]
		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
 8016a24:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8016a26:	3304      	adds	r3, #4
 8016a28:	4618      	mov	r0, r3
 8016a2a:	f7fd fa91 	bl	8013f50 <vListInitialiseItem>
		if( uxAutoReload != pdFALSE )
 8016a2e:	687b      	ldr	r3, [r7, #4]
 8016a30:	2b00      	cmp	r3, #0
 8016a32:	d008      	beq.n	8016a46 <prvInitialiseNewTimer+0x70>
		{
			pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
 8016a34:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8016a36:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8016a3a:	f043 0304 	orr.w	r3, r3, #4
 8016a3e:	b2da      	uxtb	r2, r3
 8016a40:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8016a42:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
		}
		traceTIMER_CREATE( pxNewTimer );
	}
}
 8016a46:	bf00      	nop
 8016a48:	3718      	adds	r7, #24
 8016a4a:	46bd      	mov	sp, r7
 8016a4c:	bd80      	pop	{r7, pc}
	...

08016a50 <xTimerGenericCommand>:
/*-----------------------------------------------------------*/

BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
{
 8016a50:	b580      	push	{r7, lr}
 8016a52:	b08a      	sub	sp, #40	@ 0x28
 8016a54:	af00      	add	r7, sp, #0
 8016a56:	60f8      	str	r0, [r7, #12]
 8016a58:	60b9      	str	r1, [r7, #8]
 8016a5a:	607a      	str	r2, [r7, #4]
 8016a5c:	603b      	str	r3, [r7, #0]
BaseType_t xReturn = pdFAIL;
 8016a5e:	2300      	movs	r3, #0
 8016a60:	627b      	str	r3, [r7, #36]	@ 0x24
DaemonTaskMessage_t xMessage;

	configASSERT( xTimer );
 8016a62:	68fb      	ldr	r3, [r7, #12]
 8016a64:	2b00      	cmp	r3, #0
 8016a66:	d10b      	bne.n	8016a80 <xTimerGenericCommand+0x30>
	__asm volatile
 8016a68:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8016a6c:	f383 8811 	msr	BASEPRI, r3
 8016a70:	f3bf 8f6f 	isb	sy
 8016a74:	f3bf 8f4f 	dsb	sy
 8016a78:	623b      	str	r3, [r7, #32]
}
 8016a7a:	bf00      	nop
 8016a7c:	bf00      	nop
 8016a7e:	e7fd      	b.n	8016a7c <xTimerGenericCommand+0x2c>

	/* Send a message to the timer service task to perform a particular action
	on a particular timer definition. */
	if( xTimerQueue != NULL )
 8016a80:	4b19      	ldr	r3, [pc, #100]	@ (8016ae8 <xTimerGenericCommand+0x98>)
 8016a82:	681b      	ldr	r3, [r3, #0]
 8016a84:	2b00      	cmp	r3, #0
 8016a86:	d02a      	beq.n	8016ade <xTimerGenericCommand+0x8e>
	{
		/* Send a command to the timer service task to start the xTimer timer. */
		xMessage.xMessageID = xCommandID;
 8016a88:	68bb      	ldr	r3, [r7, #8]
 8016a8a:	613b      	str	r3, [r7, #16]
		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
 8016a8c:	687b      	ldr	r3, [r7, #4]
 8016a8e:	617b      	str	r3, [r7, #20]
		xMessage.u.xTimerParameters.pxTimer = xTimer;
 8016a90:	68fb      	ldr	r3, [r7, #12]
 8016a92:	61bb      	str	r3, [r7, #24]

		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
 8016a94:	68bb      	ldr	r3, [r7, #8]
 8016a96:	2b05      	cmp	r3, #5
 8016a98:	dc18      	bgt.n	8016acc <xTimerGenericCommand+0x7c>
		{
			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
 8016a9a:	f7ff fae1 	bl	8016060 <xTaskGetSchedulerState>
 8016a9e:	4603      	mov	r3, r0
 8016aa0:	2b02      	cmp	r3, #2
 8016aa2:	d109      	bne.n	8016ab8 <xTimerGenericCommand+0x68>
			{
				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
 8016aa4:	4b10      	ldr	r3, [pc, #64]	@ (8016ae8 <xTimerGenericCommand+0x98>)
 8016aa6:	6818      	ldr	r0, [r3, #0]
 8016aa8:	f107 0110 	add.w	r1, r7, #16
 8016aac:	2300      	movs	r3, #0
 8016aae:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 8016ab0:	f7fd fce0 	bl	8014474 <xQueueGenericSend>
 8016ab4:	6278      	str	r0, [r7, #36]	@ 0x24
 8016ab6:	e012      	b.n	8016ade <xTimerGenericCommand+0x8e>
			}
			else
			{
				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
 8016ab8:	4b0b      	ldr	r3, [pc, #44]	@ (8016ae8 <xTimerGenericCommand+0x98>)
 8016aba:	6818      	ldr	r0, [r3, #0]
 8016abc:	f107 0110 	add.w	r1, r7, #16
 8016ac0:	2300      	movs	r3, #0
 8016ac2:	2200      	movs	r2, #0
 8016ac4:	f7fd fcd6 	bl	8014474 <xQueueGenericSend>
 8016ac8:	6278      	str	r0, [r7, #36]	@ 0x24
 8016aca:	e008      	b.n	8016ade <xTimerGenericCommand+0x8e>
			}
		}
		else
		{
			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
 8016acc:	4b06      	ldr	r3, [pc, #24]	@ (8016ae8 <xTimerGenericCommand+0x98>)
 8016ace:	6818      	ldr	r0, [r3, #0]
 8016ad0:	f107 0110 	add.w	r1, r7, #16
 8016ad4:	2300      	movs	r3, #0
 8016ad6:	683a      	ldr	r2, [r7, #0]
 8016ad8:	f7fd fdce 	bl	8014678 <xQueueGenericSendFromISR>
 8016adc:	6278      	str	r0, [r7, #36]	@ 0x24
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	return xReturn;
 8016ade:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
}
 8016ae0:	4618      	mov	r0, r3
 8016ae2:	3728      	adds	r7, #40	@ 0x28
 8016ae4:	46bd      	mov	sp, r7
 8016ae6:	bd80      	pop	{r7, pc}
 8016ae8:	24002b70 	.word	0x24002b70

08016aec <prvProcessExpiredTimer>:
	return pxTimer->pcTimerName;
}
/*-----------------------------------------------------------*/

static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
{
 8016aec:	b580      	push	{r7, lr}
 8016aee:	b088      	sub	sp, #32
 8016af0:	af02      	add	r7, sp, #8
 8016af2:	6078      	str	r0, [r7, #4]
 8016af4:	6039      	str	r1, [r7, #0]
BaseType_t xResult;
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8016af6:	4b23      	ldr	r3, [pc, #140]	@ (8016b84 <prvProcessExpiredTimer+0x98>)
 8016af8:	681b      	ldr	r3, [r3, #0]
 8016afa:	68db      	ldr	r3, [r3, #12]
 8016afc:	68db      	ldr	r3, [r3, #12]
 8016afe:	617b      	str	r3, [r7, #20]

	/* Remove the timer from the list of active timers.  A check has already
	been performed to ensure the list is not empty. */
	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 8016b00:	697b      	ldr	r3, [r7, #20]
 8016b02:	3304      	adds	r3, #4
 8016b04:	4618      	mov	r0, r3
 8016b06:	f7fd fa8d 	bl	8014024 <uxListRemove>
	traceTIMER_EXPIRED( pxTimer );

	/* If the timer is an auto-reload timer then calculate the next
	expiry time and re-insert the timer in the list of active timers. */
	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 8016b0a:	697b      	ldr	r3, [r7, #20]
 8016b0c:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8016b10:	f003 0304 	and.w	r3, r3, #4
 8016b14:	2b00      	cmp	r3, #0
 8016b16:	d023      	beq.n	8016b60 <prvProcessExpiredTimer+0x74>
	{
		/* The timer is inserted into a list using a time relative to anything
		other than the current time.  It will therefore be inserted into the
		correct list relative to the time this task thinks it is now. */
		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
 8016b18:	697b      	ldr	r3, [r7, #20]
 8016b1a:	699a      	ldr	r2, [r3, #24]
 8016b1c:	687b      	ldr	r3, [r7, #4]
 8016b1e:	18d1      	adds	r1, r2, r3
 8016b20:	687b      	ldr	r3, [r7, #4]
 8016b22:	683a      	ldr	r2, [r7, #0]
 8016b24:	6978      	ldr	r0, [r7, #20]
 8016b26:	f000 f8d5 	bl	8016cd4 <prvInsertTimerInActiveList>
 8016b2a:	4603      	mov	r3, r0
 8016b2c:	2b00      	cmp	r3, #0
 8016b2e:	d020      	beq.n	8016b72 <prvProcessExpiredTimer+0x86>
		{
			/* The timer expired before it was added to the active timer
			list.  Reload it now.  */
			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
 8016b30:	2300      	movs	r3, #0
 8016b32:	9300      	str	r3, [sp, #0]
 8016b34:	2300      	movs	r3, #0
 8016b36:	687a      	ldr	r2, [r7, #4]
 8016b38:	2100      	movs	r1, #0
 8016b3a:	6978      	ldr	r0, [r7, #20]
 8016b3c:	f7ff ff88 	bl	8016a50 <xTimerGenericCommand>
 8016b40:	6138      	str	r0, [r7, #16]
			configASSERT( xResult );
 8016b42:	693b      	ldr	r3, [r7, #16]
 8016b44:	2b00      	cmp	r3, #0
 8016b46:	d114      	bne.n	8016b72 <prvProcessExpiredTimer+0x86>
	__asm volatile
 8016b48:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8016b4c:	f383 8811 	msr	BASEPRI, r3
 8016b50:	f3bf 8f6f 	isb	sy
 8016b54:	f3bf 8f4f 	dsb	sy
 8016b58:	60fb      	str	r3, [r7, #12]
}
 8016b5a:	bf00      	nop
 8016b5c:	bf00      	nop
 8016b5e:	e7fd      	b.n	8016b5c <prvProcessExpiredTimer+0x70>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	else
	{
		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8016b60:	697b      	ldr	r3, [r7, #20]
 8016b62:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8016b66:	f023 0301 	bic.w	r3, r3, #1
 8016b6a:	b2da      	uxtb	r2, r3
 8016b6c:	697b      	ldr	r3, [r7, #20]
 8016b6e:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
		mtCOVERAGE_TEST_MARKER();
	}

	/* Call the timer callback. */
	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 8016b72:	697b      	ldr	r3, [r7, #20]
 8016b74:	6a1b      	ldr	r3, [r3, #32]
 8016b76:	6978      	ldr	r0, [r7, #20]
 8016b78:	4798      	blx	r3
}
 8016b7a:	bf00      	nop
 8016b7c:	3718      	adds	r7, #24
 8016b7e:	46bd      	mov	sp, r7
 8016b80:	bd80      	pop	{r7, pc}
 8016b82:	bf00      	nop
 8016b84:	24002b68 	.word	0x24002b68

08016b88 <prvTimerTask>:
/*-----------------------------------------------------------*/

static portTASK_FUNCTION( prvTimerTask, pvParameters )
{
 8016b88:	b580      	push	{r7, lr}
 8016b8a:	b084      	sub	sp, #16
 8016b8c:	af00      	add	r7, sp, #0
 8016b8e:	6078      	str	r0, [r7, #4]

	for( ;; )
	{
		/* Query the timers list to see if it contains any timers, and if so,
		obtain the time at which the next timer will expire. */
		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
 8016b90:	f107 0308 	add.w	r3, r7, #8
 8016b94:	4618      	mov	r0, r3
 8016b96:	f000 f859 	bl	8016c4c <prvGetNextExpireTime>
 8016b9a:	60f8      	str	r0, [r7, #12]

		/* If a timer has expired, process it.  Otherwise, block this task
		until either a timer does expire, or a command is received. */
		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
 8016b9c:	68bb      	ldr	r3, [r7, #8]
 8016b9e:	4619      	mov	r1, r3
 8016ba0:	68f8      	ldr	r0, [r7, #12]
 8016ba2:	f000 f805 	bl	8016bb0 <prvProcessTimerOrBlockTask>

		/* Empty the command queue. */
		prvProcessReceivedCommands();
 8016ba6:	f000 f8d7 	bl	8016d58 <prvProcessReceivedCommands>
		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
 8016baa:	bf00      	nop
 8016bac:	e7f0      	b.n	8016b90 <prvTimerTask+0x8>
	...

08016bb0 <prvProcessTimerOrBlockTask>:
	}
}
/*-----------------------------------------------------------*/

static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
{
 8016bb0:	b580      	push	{r7, lr}
 8016bb2:	b084      	sub	sp, #16
 8016bb4:	af00      	add	r7, sp, #0
 8016bb6:	6078      	str	r0, [r7, #4]
 8016bb8:	6039      	str	r1, [r7, #0]
TickType_t xTimeNow;
BaseType_t xTimerListsWereSwitched;

	vTaskSuspendAll();
 8016bba:	f7fe fe17 	bl	80157ec <vTaskSuspendAll>
		/* Obtain the time now to make an assessment as to whether the timer
		has expired or not.  If obtaining the time causes the lists to switch
		then don't process this timer as any timers that remained in the list
		when the lists were switched will have been processed within the
		prvSampleTimeNow() function. */
		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
 8016bbe:	f107 0308 	add.w	r3, r7, #8
 8016bc2:	4618      	mov	r0, r3
 8016bc4:	f000 f866 	bl	8016c94 <prvSampleTimeNow>
 8016bc8:	60f8      	str	r0, [r7, #12]
		if( xTimerListsWereSwitched == pdFALSE )
 8016bca:	68bb      	ldr	r3, [r7, #8]
 8016bcc:	2b00      	cmp	r3, #0
 8016bce:	d130      	bne.n	8016c32 <prvProcessTimerOrBlockTask+0x82>
		{
			/* The tick count has not overflowed, has the timer expired? */
			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
 8016bd0:	683b      	ldr	r3, [r7, #0]
 8016bd2:	2b00      	cmp	r3, #0
 8016bd4:	d10a      	bne.n	8016bec <prvProcessTimerOrBlockTask+0x3c>
 8016bd6:	687a      	ldr	r2, [r7, #4]
 8016bd8:	68fb      	ldr	r3, [r7, #12]
 8016bda:	429a      	cmp	r2, r3
 8016bdc:	d806      	bhi.n	8016bec <prvProcessTimerOrBlockTask+0x3c>
			{
				( void ) xTaskResumeAll();
 8016bde:	f7fe fe13 	bl	8015808 <xTaskResumeAll>
				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
 8016be2:	68f9      	ldr	r1, [r7, #12]
 8016be4:	6878      	ldr	r0, [r7, #4]
 8016be6:	f7ff ff81 	bl	8016aec <prvProcessExpiredTimer>
		else
		{
			( void ) xTaskResumeAll();
		}
	}
}
 8016bea:	e024      	b.n	8016c36 <prvProcessTimerOrBlockTask+0x86>
				if( xListWasEmpty != pdFALSE )
 8016bec:	683b      	ldr	r3, [r7, #0]
 8016bee:	2b00      	cmp	r3, #0
 8016bf0:	d008      	beq.n	8016c04 <prvProcessTimerOrBlockTask+0x54>
					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
 8016bf2:	4b13      	ldr	r3, [pc, #76]	@ (8016c40 <prvProcessTimerOrBlockTask+0x90>)
 8016bf4:	681b      	ldr	r3, [r3, #0]
 8016bf6:	681b      	ldr	r3, [r3, #0]
 8016bf8:	2b00      	cmp	r3, #0
 8016bfa:	d101      	bne.n	8016c00 <prvProcessTimerOrBlockTask+0x50>
 8016bfc:	2301      	movs	r3, #1
 8016bfe:	e000      	b.n	8016c02 <prvProcessTimerOrBlockTask+0x52>
 8016c00:	2300      	movs	r3, #0
 8016c02:	603b      	str	r3, [r7, #0]
				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
 8016c04:	4b0f      	ldr	r3, [pc, #60]	@ (8016c44 <prvProcessTimerOrBlockTask+0x94>)
 8016c06:	6818      	ldr	r0, [r3, #0]
 8016c08:	687a      	ldr	r2, [r7, #4]
 8016c0a:	68fb      	ldr	r3, [r7, #12]
 8016c0c:	1ad3      	subs	r3, r2, r3
 8016c0e:	683a      	ldr	r2, [r7, #0]
 8016c10:	4619      	mov	r1, r3
 8016c12:	f7fe f995 	bl	8014f40 <vQueueWaitForMessageRestricted>
				if( xTaskResumeAll() == pdFALSE )
 8016c16:	f7fe fdf7 	bl	8015808 <xTaskResumeAll>
 8016c1a:	4603      	mov	r3, r0
 8016c1c:	2b00      	cmp	r3, #0
 8016c1e:	d10a      	bne.n	8016c36 <prvProcessTimerOrBlockTask+0x86>
					portYIELD_WITHIN_API();
 8016c20:	4b09      	ldr	r3, [pc, #36]	@ (8016c48 <prvProcessTimerOrBlockTask+0x98>)
 8016c22:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 8016c26:	601a      	str	r2, [r3, #0]
 8016c28:	f3bf 8f4f 	dsb	sy
 8016c2c:	f3bf 8f6f 	isb	sy
}
 8016c30:	e001      	b.n	8016c36 <prvProcessTimerOrBlockTask+0x86>
			( void ) xTaskResumeAll();
 8016c32:	f7fe fde9 	bl	8015808 <xTaskResumeAll>
}
 8016c36:	bf00      	nop
 8016c38:	3710      	adds	r7, #16
 8016c3a:	46bd      	mov	sp, r7
 8016c3c:	bd80      	pop	{r7, pc}
 8016c3e:	bf00      	nop
 8016c40:	24002b6c 	.word	0x24002b6c
 8016c44:	24002b70 	.word	0x24002b70
 8016c48:	e000ed04 	.word	0xe000ed04

08016c4c <prvGetNextExpireTime>:
/*-----------------------------------------------------------*/

static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
{
 8016c4c:	b480      	push	{r7}
 8016c4e:	b085      	sub	sp, #20
 8016c50:	af00      	add	r7, sp, #0
 8016c52:	6078      	str	r0, [r7, #4]
	the timer with the nearest expiry time will expire.  If there are no
	active timers then just set the next expire time to 0.  That will cause
	this task to unblock when the tick count overflows, at which point the
	timer lists will be switched and the next expiry time can be
	re-assessed.  */
	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
 8016c54:	4b0e      	ldr	r3, [pc, #56]	@ (8016c90 <prvGetNextExpireTime+0x44>)
 8016c56:	681b      	ldr	r3, [r3, #0]
 8016c58:	681b      	ldr	r3, [r3, #0]
 8016c5a:	2b00      	cmp	r3, #0
 8016c5c:	d101      	bne.n	8016c62 <prvGetNextExpireTime+0x16>
 8016c5e:	2201      	movs	r2, #1
 8016c60:	e000      	b.n	8016c64 <prvGetNextExpireTime+0x18>
 8016c62:	2200      	movs	r2, #0
 8016c64:	687b      	ldr	r3, [r7, #4]
 8016c66:	601a      	str	r2, [r3, #0]
	if( *pxListWasEmpty == pdFALSE )
 8016c68:	687b      	ldr	r3, [r7, #4]
 8016c6a:	681b      	ldr	r3, [r3, #0]
 8016c6c:	2b00      	cmp	r3, #0
 8016c6e:	d105      	bne.n	8016c7c <prvGetNextExpireTime+0x30>
	{
		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 8016c70:	4b07      	ldr	r3, [pc, #28]	@ (8016c90 <prvGetNextExpireTime+0x44>)
 8016c72:	681b      	ldr	r3, [r3, #0]
 8016c74:	68db      	ldr	r3, [r3, #12]
 8016c76:	681b      	ldr	r3, [r3, #0]
 8016c78:	60fb      	str	r3, [r7, #12]
 8016c7a:	e001      	b.n	8016c80 <prvGetNextExpireTime+0x34>
	}
	else
	{
		/* Ensure the task unblocks when the tick count rolls over. */
		xNextExpireTime = ( TickType_t ) 0U;
 8016c7c:	2300      	movs	r3, #0
 8016c7e:	60fb      	str	r3, [r7, #12]
	}

	return xNextExpireTime;
 8016c80:	68fb      	ldr	r3, [r7, #12]
}
 8016c82:	4618      	mov	r0, r3
 8016c84:	3714      	adds	r7, #20
 8016c86:	46bd      	mov	sp, r7
 8016c88:	f85d 7b04 	ldr.w	r7, [sp], #4
 8016c8c:	4770      	bx	lr
 8016c8e:	bf00      	nop
 8016c90:	24002b68 	.word	0x24002b68

08016c94 <prvSampleTimeNow>:
/*-----------------------------------------------------------*/

static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
{
 8016c94:	b580      	push	{r7, lr}
 8016c96:	b084      	sub	sp, #16
 8016c98:	af00      	add	r7, sp, #0
 8016c9a:	6078      	str	r0, [r7, #4]
TickType_t xTimeNow;
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */

	xTimeNow = xTaskGetTickCount();
 8016c9c:	f7fe fe52 	bl	8015944 <xTaskGetTickCount>
 8016ca0:	60f8      	str	r0, [r7, #12]

	if( xTimeNow < xLastTime )
 8016ca2:	4b0b      	ldr	r3, [pc, #44]	@ (8016cd0 <prvSampleTimeNow+0x3c>)
 8016ca4:	681b      	ldr	r3, [r3, #0]
 8016ca6:	68fa      	ldr	r2, [r7, #12]
 8016ca8:	429a      	cmp	r2, r3
 8016caa:	d205      	bcs.n	8016cb8 <prvSampleTimeNow+0x24>
	{
		prvSwitchTimerLists();
 8016cac:	f000 f93a 	bl	8016f24 <prvSwitchTimerLists>
		*pxTimerListsWereSwitched = pdTRUE;
 8016cb0:	687b      	ldr	r3, [r7, #4]
 8016cb2:	2201      	movs	r2, #1
 8016cb4:	601a      	str	r2, [r3, #0]
 8016cb6:	e002      	b.n	8016cbe <prvSampleTimeNow+0x2a>
	}
	else
	{
		*pxTimerListsWereSwitched = pdFALSE;
 8016cb8:	687b      	ldr	r3, [r7, #4]
 8016cba:	2200      	movs	r2, #0
 8016cbc:	601a      	str	r2, [r3, #0]
	}

	xLastTime = xTimeNow;
 8016cbe:	4a04      	ldr	r2, [pc, #16]	@ (8016cd0 <prvSampleTimeNow+0x3c>)
 8016cc0:	68fb      	ldr	r3, [r7, #12]
 8016cc2:	6013      	str	r3, [r2, #0]

	return xTimeNow;
 8016cc4:	68fb      	ldr	r3, [r7, #12]
}
 8016cc6:	4618      	mov	r0, r3
 8016cc8:	3710      	adds	r7, #16
 8016cca:	46bd      	mov	sp, r7
 8016ccc:	bd80      	pop	{r7, pc}
 8016cce:	bf00      	nop
 8016cd0:	24002b78 	.word	0x24002b78

08016cd4 <prvInsertTimerInActiveList>:
/*-----------------------------------------------------------*/

static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
{
 8016cd4:	b580      	push	{r7, lr}
 8016cd6:	b086      	sub	sp, #24
 8016cd8:	af00      	add	r7, sp, #0
 8016cda:	60f8      	str	r0, [r7, #12]
 8016cdc:	60b9      	str	r1, [r7, #8]
 8016cde:	607a      	str	r2, [r7, #4]
 8016ce0:	603b      	str	r3, [r7, #0]
BaseType_t xProcessTimerNow = pdFALSE;
 8016ce2:	2300      	movs	r3, #0
 8016ce4:	617b      	str	r3, [r7, #20]

	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
 8016ce6:	68fb      	ldr	r3, [r7, #12]
 8016ce8:	68ba      	ldr	r2, [r7, #8]
 8016cea:	605a      	str	r2, [r3, #4]
	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
 8016cec:	68fb      	ldr	r3, [r7, #12]
 8016cee:	68fa      	ldr	r2, [r7, #12]
 8016cf0:	611a      	str	r2, [r3, #16]

	if( xNextExpiryTime <= xTimeNow )
 8016cf2:	68ba      	ldr	r2, [r7, #8]
 8016cf4:	687b      	ldr	r3, [r7, #4]
 8016cf6:	429a      	cmp	r2, r3
 8016cf8:	d812      	bhi.n	8016d20 <prvInsertTimerInActiveList+0x4c>
	{
		/* Has the expiry time elapsed between the command to start/reset a
		timer was issued, and the time the command was processed? */
		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8016cfa:	687a      	ldr	r2, [r7, #4]
 8016cfc:	683b      	ldr	r3, [r7, #0]
 8016cfe:	1ad2      	subs	r2, r2, r3
 8016d00:	68fb      	ldr	r3, [r7, #12]
 8016d02:	699b      	ldr	r3, [r3, #24]
 8016d04:	429a      	cmp	r2, r3
 8016d06:	d302      	bcc.n	8016d0e <prvInsertTimerInActiveList+0x3a>
		{
			/* The time between a command being issued and the command being
			processed actually exceeds the timers period.  */
			xProcessTimerNow = pdTRUE;
 8016d08:	2301      	movs	r3, #1
 8016d0a:	617b      	str	r3, [r7, #20]
 8016d0c:	e01b      	b.n	8016d46 <prvInsertTimerInActiveList+0x72>
		}
		else
		{
			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
 8016d0e:	4b10      	ldr	r3, [pc, #64]	@ (8016d50 <prvInsertTimerInActiveList+0x7c>)
 8016d10:	681a      	ldr	r2, [r3, #0]
 8016d12:	68fb      	ldr	r3, [r7, #12]
 8016d14:	3304      	adds	r3, #4
 8016d16:	4619      	mov	r1, r3
 8016d18:	4610      	mov	r0, r2
 8016d1a:	f7fd f94a 	bl	8013fb2 <vListInsert>
 8016d1e:	e012      	b.n	8016d46 <prvInsertTimerInActiveList+0x72>
		}
	}
	else
	{
		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
 8016d20:	687a      	ldr	r2, [r7, #4]
 8016d22:	683b      	ldr	r3, [r7, #0]
 8016d24:	429a      	cmp	r2, r3
 8016d26:	d206      	bcs.n	8016d36 <prvInsertTimerInActiveList+0x62>
 8016d28:	68ba      	ldr	r2, [r7, #8]
 8016d2a:	683b      	ldr	r3, [r7, #0]
 8016d2c:	429a      	cmp	r2, r3
 8016d2e:	d302      	bcc.n	8016d36 <prvInsertTimerInActiveList+0x62>
		{
			/* If, since the command was issued, the tick count has overflowed
			but the expiry time has not, then the timer must have already passed
			its expiry time and should be processed immediately. */
			xProcessTimerNow = pdTRUE;
 8016d30:	2301      	movs	r3, #1
 8016d32:	617b      	str	r3, [r7, #20]
 8016d34:	e007      	b.n	8016d46 <prvInsertTimerInActiveList+0x72>
		}
		else
		{
			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
 8016d36:	4b07      	ldr	r3, [pc, #28]	@ (8016d54 <prvInsertTimerInActiveList+0x80>)
 8016d38:	681a      	ldr	r2, [r3, #0]
 8016d3a:	68fb      	ldr	r3, [r7, #12]
 8016d3c:	3304      	adds	r3, #4
 8016d3e:	4619      	mov	r1, r3
 8016d40:	4610      	mov	r0, r2
 8016d42:	f7fd f936 	bl	8013fb2 <vListInsert>
		}
	}

	return xProcessTimerNow;
 8016d46:	697b      	ldr	r3, [r7, #20]
}
 8016d48:	4618      	mov	r0, r3
 8016d4a:	3718      	adds	r7, #24
 8016d4c:	46bd      	mov	sp, r7
 8016d4e:	bd80      	pop	{r7, pc}
 8016d50:	24002b6c 	.word	0x24002b6c
 8016d54:	24002b68 	.word	0x24002b68

08016d58 <prvProcessReceivedCommands>:
/*-----------------------------------------------------------*/

static void	prvProcessReceivedCommands( void )
{
 8016d58:	b580      	push	{r7, lr}
 8016d5a:	b08e      	sub	sp, #56	@ 0x38
 8016d5c:	af02      	add	r7, sp, #8
DaemonTaskMessage_t xMessage;
Timer_t *pxTimer;
BaseType_t xTimerListsWereSwitched, xResult;
TickType_t xTimeNow;

	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
 8016d5e:	e0ce      	b.n	8016efe <prvProcessReceivedCommands+0x1a6>
	{
		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
		{
			/* Negative commands are pended function calls rather than timer
			commands. */
			if( xMessage.xMessageID < ( BaseType_t ) 0 )
 8016d60:	687b      	ldr	r3, [r7, #4]
 8016d62:	2b00      	cmp	r3, #0
 8016d64:	da19      	bge.n	8016d9a <prvProcessReceivedCommands+0x42>
			{
				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
 8016d66:	1d3b      	adds	r3, r7, #4
 8016d68:	3304      	adds	r3, #4
 8016d6a:	62fb      	str	r3, [r7, #44]	@ 0x2c

				/* The timer uses the xCallbackParameters member to request a
				callback be executed.  Check the callback is not NULL. */
				configASSERT( pxCallback );
 8016d6c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8016d6e:	2b00      	cmp	r3, #0
 8016d70:	d10b      	bne.n	8016d8a <prvProcessReceivedCommands+0x32>
	__asm volatile
 8016d72:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8016d76:	f383 8811 	msr	BASEPRI, r3
 8016d7a:	f3bf 8f6f 	isb	sy
 8016d7e:	f3bf 8f4f 	dsb	sy
 8016d82:	61fb      	str	r3, [r7, #28]
}
 8016d84:	bf00      	nop
 8016d86:	bf00      	nop
 8016d88:	e7fd      	b.n	8016d86 <prvProcessReceivedCommands+0x2e>

				/* Call the function. */
				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
 8016d8a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8016d8c:	681b      	ldr	r3, [r3, #0]
 8016d8e:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8016d90:	6850      	ldr	r0, [r2, #4]
 8016d92:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8016d94:	6892      	ldr	r2, [r2, #8]
 8016d96:	4611      	mov	r1, r2
 8016d98:	4798      	blx	r3
		}
		#endif /* INCLUDE_xTimerPendFunctionCall */

		/* Commands that are positive are timer commands rather than pended
		function calls. */
		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
 8016d9a:	687b      	ldr	r3, [r7, #4]
 8016d9c:	2b00      	cmp	r3, #0
 8016d9e:	f2c0 80ae 	blt.w	8016efe <prvProcessReceivedCommands+0x1a6>
		{
			/* The messages uses the xTimerParameters member to work on a
			software timer. */
			pxTimer = xMessage.u.xTimerParameters.pxTimer;
 8016da2:	68fb      	ldr	r3, [r7, #12]
 8016da4:	62bb      	str	r3, [r7, #40]	@ 0x28

			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
 8016da6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016da8:	695b      	ldr	r3, [r3, #20]
 8016daa:	2b00      	cmp	r3, #0
 8016dac:	d004      	beq.n	8016db8 <prvProcessReceivedCommands+0x60>
			{
				/* The timer is in a list, remove it. */
				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 8016dae:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016db0:	3304      	adds	r3, #4
 8016db2:	4618      	mov	r0, r3
 8016db4:	f7fd f936 	bl	8014024 <uxListRemove>
			it must be present in the function call.  prvSampleTimeNow() must be
			called after the message is received from xTimerQueue so there is no
			possibility of a higher priority task adding a message to the message
			queue with a time that is ahead of the timer daemon task (because it
			pre-empted the timer daemon task after the xTimeNow value was set). */
			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
 8016db8:	463b      	mov	r3, r7
 8016dba:	4618      	mov	r0, r3
 8016dbc:	f7ff ff6a 	bl	8016c94 <prvSampleTimeNow>
 8016dc0:	6278      	str	r0, [r7, #36]	@ 0x24

			switch( xMessage.xMessageID )
 8016dc2:	687b      	ldr	r3, [r7, #4]
 8016dc4:	2b09      	cmp	r3, #9
 8016dc6:	f200 8097 	bhi.w	8016ef8 <prvProcessReceivedCommands+0x1a0>
 8016dca:	a201      	add	r2, pc, #4	@ (adr r2, 8016dd0 <prvProcessReceivedCommands+0x78>)
 8016dcc:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8016dd0:	08016df9 	.word	0x08016df9
 8016dd4:	08016df9 	.word	0x08016df9
 8016dd8:	08016df9 	.word	0x08016df9
 8016ddc:	08016e6f 	.word	0x08016e6f
 8016de0:	08016e83 	.word	0x08016e83
 8016de4:	08016ecf 	.word	0x08016ecf
 8016de8:	08016df9 	.word	0x08016df9
 8016dec:	08016df9 	.word	0x08016df9
 8016df0:	08016e6f 	.word	0x08016e6f
 8016df4:	08016e83 	.word	0x08016e83
				case tmrCOMMAND_START_FROM_ISR :
				case tmrCOMMAND_RESET :
				case tmrCOMMAND_RESET_FROM_ISR :
				case tmrCOMMAND_START_DONT_TRACE :
					/* Start or restart a timer. */
					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 8016df8:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016dfa:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8016dfe:	f043 0301 	orr.w	r3, r3, #1
 8016e02:	b2da      	uxtb	r2, r3
 8016e04:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016e06:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
 8016e0a:	68ba      	ldr	r2, [r7, #8]
 8016e0c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016e0e:	699b      	ldr	r3, [r3, #24]
 8016e10:	18d1      	adds	r1, r2, r3
 8016e12:	68bb      	ldr	r3, [r7, #8]
 8016e14:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8016e16:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8016e18:	f7ff ff5c 	bl	8016cd4 <prvInsertTimerInActiveList>
 8016e1c:	4603      	mov	r3, r0
 8016e1e:	2b00      	cmp	r3, #0
 8016e20:	d06c      	beq.n	8016efc <prvProcessReceivedCommands+0x1a4>
					{
						/* The timer expired before it was added to the active
						timer list.  Process it now. */
						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 8016e22:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016e24:	6a1b      	ldr	r3, [r3, #32]
 8016e26:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8016e28:	4798      	blx	r3
						traceTIMER_EXPIRED( pxTimer );

						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 8016e2a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016e2c:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8016e30:	f003 0304 	and.w	r3, r3, #4
 8016e34:	2b00      	cmp	r3, #0
 8016e36:	d061      	beq.n	8016efc <prvProcessReceivedCommands+0x1a4>
						{
							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
 8016e38:	68ba      	ldr	r2, [r7, #8]
 8016e3a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016e3c:	699b      	ldr	r3, [r3, #24]
 8016e3e:	441a      	add	r2, r3
 8016e40:	2300      	movs	r3, #0
 8016e42:	9300      	str	r3, [sp, #0]
 8016e44:	2300      	movs	r3, #0
 8016e46:	2100      	movs	r1, #0
 8016e48:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8016e4a:	f7ff fe01 	bl	8016a50 <xTimerGenericCommand>
 8016e4e:	6238      	str	r0, [r7, #32]
							configASSERT( xResult );
 8016e50:	6a3b      	ldr	r3, [r7, #32]
 8016e52:	2b00      	cmp	r3, #0
 8016e54:	d152      	bne.n	8016efc <prvProcessReceivedCommands+0x1a4>
	__asm volatile
 8016e56:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8016e5a:	f383 8811 	msr	BASEPRI, r3
 8016e5e:	f3bf 8f6f 	isb	sy
 8016e62:	f3bf 8f4f 	dsb	sy
 8016e66:	61bb      	str	r3, [r7, #24]
}
 8016e68:	bf00      	nop
 8016e6a:	bf00      	nop
 8016e6c:	e7fd      	b.n	8016e6a <prvProcessReceivedCommands+0x112>
					break;

				case tmrCOMMAND_STOP :
				case tmrCOMMAND_STOP_FROM_ISR :
					/* The timer has already been removed from the active list. */
					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8016e6e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016e70:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8016e74:	f023 0301 	bic.w	r3, r3, #1
 8016e78:	b2da      	uxtb	r2, r3
 8016e7a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016e7c:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					break;
 8016e80:	e03d      	b.n	8016efe <prvProcessReceivedCommands+0x1a6>

				case tmrCOMMAND_CHANGE_PERIOD :
				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 8016e82:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016e84:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8016e88:	f043 0301 	orr.w	r3, r3, #1
 8016e8c:	b2da      	uxtb	r2, r3
 8016e8e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016e90:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
 8016e94:	68ba      	ldr	r2, [r7, #8]
 8016e96:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016e98:	619a      	str	r2, [r3, #24]
					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
 8016e9a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016e9c:	699b      	ldr	r3, [r3, #24]
 8016e9e:	2b00      	cmp	r3, #0
 8016ea0:	d10b      	bne.n	8016eba <prvProcessReceivedCommands+0x162>
	__asm volatile
 8016ea2:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8016ea6:	f383 8811 	msr	BASEPRI, r3
 8016eaa:	f3bf 8f6f 	isb	sy
 8016eae:	f3bf 8f4f 	dsb	sy
 8016eb2:	617b      	str	r3, [r7, #20]
}
 8016eb4:	bf00      	nop
 8016eb6:	bf00      	nop
 8016eb8:	e7fd      	b.n	8016eb6 <prvProcessReceivedCommands+0x15e>
					be longer or shorter than the old one.  The command time is
					therefore set to the current time, and as the period cannot
					be zero the next expiry time can only be in the future,
					meaning (unlike for the xTimerStart() case above) there is
					no fail case that needs to be handled here. */
					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
 8016eba:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016ebc:	699a      	ldr	r2, [r3, #24]
 8016ebe:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8016ec0:	18d1      	adds	r1, r2, r3
 8016ec2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8016ec4:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8016ec6:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8016ec8:	f7ff ff04 	bl	8016cd4 <prvInsertTimerInActiveList>
					break;
 8016ecc:	e017      	b.n	8016efe <prvProcessReceivedCommands+0x1a6>
					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
					{
						/* The timer has already been removed from the active list,
						just free up the memory if the memory was dynamically
						allocated. */
						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
 8016ece:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016ed0:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8016ed4:	f003 0302 	and.w	r3, r3, #2
 8016ed8:	2b00      	cmp	r3, #0
 8016eda:	d103      	bne.n	8016ee4 <prvProcessReceivedCommands+0x18c>
						{
							vPortFree( pxTimer );
 8016edc:	6ab8      	ldr	r0, [r7, #40]	@ 0x28
 8016ede:	f000 fc33 	bl	8017748 <vPortFree>
						no need to free the memory - just mark the timer as
						"not active". */
						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
					}
					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
					break;
 8016ee2:	e00c      	b.n	8016efe <prvProcessReceivedCommands+0x1a6>
							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8016ee4:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016ee6:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8016eea:	f023 0301 	bic.w	r3, r3, #1
 8016eee:	b2da      	uxtb	r2, r3
 8016ef0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8016ef2:	f883 2028 	strb.w	r2, [r3, #40]	@ 0x28
					break;
 8016ef6:	e002      	b.n	8016efe <prvProcessReceivedCommands+0x1a6>

				default	:
					/* Don't expect to get here. */
					break;
 8016ef8:	bf00      	nop
 8016efa:	e000      	b.n	8016efe <prvProcessReceivedCommands+0x1a6>
					break;
 8016efc:	bf00      	nop
	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
 8016efe:	4b08      	ldr	r3, [pc, #32]	@ (8016f20 <prvProcessReceivedCommands+0x1c8>)
 8016f00:	681b      	ldr	r3, [r3, #0]
 8016f02:	1d39      	adds	r1, r7, #4
 8016f04:	2200      	movs	r2, #0
 8016f06:	4618      	mov	r0, r3
 8016f08:	f7fd fc54 	bl	80147b4 <xQueueReceive>
 8016f0c:	4603      	mov	r3, r0
 8016f0e:	2b00      	cmp	r3, #0
 8016f10:	f47f af26 	bne.w	8016d60 <prvProcessReceivedCommands+0x8>
			}
		}
	}
}
 8016f14:	bf00      	nop
 8016f16:	bf00      	nop
 8016f18:	3730      	adds	r7, #48	@ 0x30
 8016f1a:	46bd      	mov	sp, r7
 8016f1c:	bd80      	pop	{r7, pc}
 8016f1e:	bf00      	nop
 8016f20:	24002b70 	.word	0x24002b70

08016f24 <prvSwitchTimerLists>:
/*-----------------------------------------------------------*/

static void prvSwitchTimerLists( void )
{
 8016f24:	b580      	push	{r7, lr}
 8016f26:	b088      	sub	sp, #32
 8016f28:	af02      	add	r7, sp, #8

	/* The tick count has overflowed.  The timer lists must be switched.
	If there are any timers still referenced from the current timer list
	then they must have expired and should be processed before the lists
	are switched. */
	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
 8016f2a:	e049      	b.n	8016fc0 <prvSwitchTimerLists+0x9c>
	{
		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 8016f2c:	4b2e      	ldr	r3, [pc, #184]	@ (8016fe8 <prvSwitchTimerLists+0xc4>)
 8016f2e:	681b      	ldr	r3, [r3, #0]
 8016f30:	68db      	ldr	r3, [r3, #12]
 8016f32:	681b      	ldr	r3, [r3, #0]
 8016f34:	613b      	str	r3, [r7, #16]

		/* Remove the timer from the list. */
		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8016f36:	4b2c      	ldr	r3, [pc, #176]	@ (8016fe8 <prvSwitchTimerLists+0xc4>)
 8016f38:	681b      	ldr	r3, [r3, #0]
 8016f3a:	68db      	ldr	r3, [r3, #12]
 8016f3c:	68db      	ldr	r3, [r3, #12]
 8016f3e:	60fb      	str	r3, [r7, #12]
		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 8016f40:	68fb      	ldr	r3, [r7, #12]
 8016f42:	3304      	adds	r3, #4
 8016f44:	4618      	mov	r0, r3
 8016f46:	f7fd f86d 	bl	8014024 <uxListRemove>
		traceTIMER_EXPIRED( pxTimer );

		/* Execute its callback, then send a command to restart the timer if
		it is an auto-reload timer.  It cannot be restarted here as the lists
		have not yet been switched. */
		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 8016f4a:	68fb      	ldr	r3, [r7, #12]
 8016f4c:	6a1b      	ldr	r3, [r3, #32]
 8016f4e:	68f8      	ldr	r0, [r7, #12]
 8016f50:	4798      	blx	r3

		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 8016f52:	68fb      	ldr	r3, [r7, #12]
 8016f54:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 8016f58:	f003 0304 	and.w	r3, r3, #4
 8016f5c:	2b00      	cmp	r3, #0
 8016f5e:	d02f      	beq.n	8016fc0 <prvSwitchTimerLists+0x9c>
			the timer going into the same timer list then it has already expired
			and the timer should be re-inserted into the current list so it is
			processed again within this loop.  Otherwise a command should be sent
			to restart the timer to ensure it is only inserted into a list after
			the lists have been swapped. */
			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
 8016f60:	68fb      	ldr	r3, [r7, #12]
 8016f62:	699b      	ldr	r3, [r3, #24]
 8016f64:	693a      	ldr	r2, [r7, #16]
 8016f66:	4413      	add	r3, r2
 8016f68:	60bb      	str	r3, [r7, #8]
			if( xReloadTime > xNextExpireTime )
 8016f6a:	68ba      	ldr	r2, [r7, #8]
 8016f6c:	693b      	ldr	r3, [r7, #16]
 8016f6e:	429a      	cmp	r2, r3
 8016f70:	d90e      	bls.n	8016f90 <prvSwitchTimerLists+0x6c>
			{
				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
 8016f72:	68fb      	ldr	r3, [r7, #12]
 8016f74:	68ba      	ldr	r2, [r7, #8]
 8016f76:	605a      	str	r2, [r3, #4]
				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
 8016f78:	68fb      	ldr	r3, [r7, #12]
 8016f7a:	68fa      	ldr	r2, [r7, #12]
 8016f7c:	611a      	str	r2, [r3, #16]
				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
 8016f7e:	4b1a      	ldr	r3, [pc, #104]	@ (8016fe8 <prvSwitchTimerLists+0xc4>)
 8016f80:	681a      	ldr	r2, [r3, #0]
 8016f82:	68fb      	ldr	r3, [r7, #12]
 8016f84:	3304      	adds	r3, #4
 8016f86:	4619      	mov	r1, r3
 8016f88:	4610      	mov	r0, r2
 8016f8a:	f7fd f812 	bl	8013fb2 <vListInsert>
 8016f8e:	e017      	b.n	8016fc0 <prvSwitchTimerLists+0x9c>
			}
			else
			{
				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
 8016f90:	2300      	movs	r3, #0
 8016f92:	9300      	str	r3, [sp, #0]
 8016f94:	2300      	movs	r3, #0
 8016f96:	693a      	ldr	r2, [r7, #16]
 8016f98:	2100      	movs	r1, #0
 8016f9a:	68f8      	ldr	r0, [r7, #12]
 8016f9c:	f7ff fd58 	bl	8016a50 <xTimerGenericCommand>
 8016fa0:	6078      	str	r0, [r7, #4]
				configASSERT( xResult );
 8016fa2:	687b      	ldr	r3, [r7, #4]
 8016fa4:	2b00      	cmp	r3, #0
 8016fa6:	d10b      	bne.n	8016fc0 <prvSwitchTimerLists+0x9c>
	__asm volatile
 8016fa8:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8016fac:	f383 8811 	msr	BASEPRI, r3
 8016fb0:	f3bf 8f6f 	isb	sy
 8016fb4:	f3bf 8f4f 	dsb	sy
 8016fb8:	603b      	str	r3, [r7, #0]
}
 8016fba:	bf00      	nop
 8016fbc:	bf00      	nop
 8016fbe:	e7fd      	b.n	8016fbc <prvSwitchTimerLists+0x98>
	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
 8016fc0:	4b09      	ldr	r3, [pc, #36]	@ (8016fe8 <prvSwitchTimerLists+0xc4>)
 8016fc2:	681b      	ldr	r3, [r3, #0]
 8016fc4:	681b      	ldr	r3, [r3, #0]
 8016fc6:	2b00      	cmp	r3, #0
 8016fc8:	d1b0      	bne.n	8016f2c <prvSwitchTimerLists+0x8>
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}

	pxTemp = pxCurrentTimerList;
 8016fca:	4b07      	ldr	r3, [pc, #28]	@ (8016fe8 <prvSwitchTimerLists+0xc4>)
 8016fcc:	681b      	ldr	r3, [r3, #0]
 8016fce:	617b      	str	r3, [r7, #20]
	pxCurrentTimerList = pxOverflowTimerList;
 8016fd0:	4b06      	ldr	r3, [pc, #24]	@ (8016fec <prvSwitchTimerLists+0xc8>)
 8016fd2:	681b      	ldr	r3, [r3, #0]
 8016fd4:	4a04      	ldr	r2, [pc, #16]	@ (8016fe8 <prvSwitchTimerLists+0xc4>)
 8016fd6:	6013      	str	r3, [r2, #0]
	pxOverflowTimerList = pxTemp;
 8016fd8:	4a04      	ldr	r2, [pc, #16]	@ (8016fec <prvSwitchTimerLists+0xc8>)
 8016fda:	697b      	ldr	r3, [r7, #20]
 8016fdc:	6013      	str	r3, [r2, #0]
}
 8016fde:	bf00      	nop
 8016fe0:	3718      	adds	r7, #24
 8016fe2:	46bd      	mov	sp, r7
 8016fe4:	bd80      	pop	{r7, pc}
 8016fe6:	bf00      	nop
 8016fe8:	24002b68 	.word	0x24002b68
 8016fec:	24002b6c 	.word	0x24002b6c

08016ff0 <prvCheckForValidListAndQueue>:
/*-----------------------------------------------------------*/

static void prvCheckForValidListAndQueue( void )
{
 8016ff0:	b580      	push	{r7, lr}
 8016ff2:	b082      	sub	sp, #8
 8016ff4:	af02      	add	r7, sp, #8
	/* Check that the list from which active timers are referenced, and the
	queue used to communicate with the timer service, have been
	initialised. */
	taskENTER_CRITICAL();
 8016ff6:	f000 f9b7 	bl	8017368 <vPortEnterCritical>
	{
		if( xTimerQueue == NULL )
 8016ffa:	4b15      	ldr	r3, [pc, #84]	@ (8017050 <prvCheckForValidListAndQueue+0x60>)
 8016ffc:	681b      	ldr	r3, [r3, #0]
 8016ffe:	2b00      	cmp	r3, #0
 8017000:	d120      	bne.n	8017044 <prvCheckForValidListAndQueue+0x54>
		{
			vListInitialise( &xActiveTimerList1 );
 8017002:	4814      	ldr	r0, [pc, #80]	@ (8017054 <prvCheckForValidListAndQueue+0x64>)
 8017004:	f7fc ff84 	bl	8013f10 <vListInitialise>
			vListInitialise( &xActiveTimerList2 );
 8017008:	4813      	ldr	r0, [pc, #76]	@ (8017058 <prvCheckForValidListAndQueue+0x68>)
 801700a:	f7fc ff81 	bl	8013f10 <vListInitialise>
			pxCurrentTimerList = &xActiveTimerList1;
 801700e:	4b13      	ldr	r3, [pc, #76]	@ (801705c <prvCheckForValidListAndQueue+0x6c>)
 8017010:	4a10      	ldr	r2, [pc, #64]	@ (8017054 <prvCheckForValidListAndQueue+0x64>)
 8017012:	601a      	str	r2, [r3, #0]
			pxOverflowTimerList = &xActiveTimerList2;
 8017014:	4b12      	ldr	r3, [pc, #72]	@ (8017060 <prvCheckForValidListAndQueue+0x70>)
 8017016:	4a10      	ldr	r2, [pc, #64]	@ (8017058 <prvCheckForValidListAndQueue+0x68>)
 8017018:	601a      	str	r2, [r3, #0]
				/* The timer queue is allocated statically in case
				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */

				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
 801701a:	2300      	movs	r3, #0
 801701c:	9300      	str	r3, [sp, #0]
 801701e:	4b11      	ldr	r3, [pc, #68]	@ (8017064 <prvCheckForValidListAndQueue+0x74>)
 8017020:	4a11      	ldr	r2, [pc, #68]	@ (8017068 <prvCheckForValidListAndQueue+0x78>)
 8017022:	2110      	movs	r1, #16
 8017024:	200a      	movs	r0, #10
 8017026:	f7fd f891 	bl	801414c <xQueueGenericCreateStatic>
 801702a:	4603      	mov	r3, r0
 801702c:	4a08      	ldr	r2, [pc, #32]	@ (8017050 <prvCheckForValidListAndQueue+0x60>)
 801702e:	6013      	str	r3, [r2, #0]
			}
			#endif

			#if ( configQUEUE_REGISTRY_SIZE > 0 )
			{
				if( xTimerQueue != NULL )
 8017030:	4b07      	ldr	r3, [pc, #28]	@ (8017050 <prvCheckForValidListAndQueue+0x60>)
 8017032:	681b      	ldr	r3, [r3, #0]
 8017034:	2b00      	cmp	r3, #0
 8017036:	d005      	beq.n	8017044 <prvCheckForValidListAndQueue+0x54>
				{
					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
 8017038:	4b05      	ldr	r3, [pc, #20]	@ (8017050 <prvCheckForValidListAndQueue+0x60>)
 801703a:	681b      	ldr	r3, [r3, #0]
 801703c:	490b      	ldr	r1, [pc, #44]	@ (801706c <prvCheckForValidListAndQueue+0x7c>)
 801703e:	4618      	mov	r0, r3
 8017040:	f7fd ff54 	bl	8014eec <vQueueAddToRegistry>
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
	taskEXIT_CRITICAL();
 8017044:	f000 f9c2 	bl	80173cc <vPortExitCritical>
}
 8017048:	bf00      	nop
 801704a:	46bd      	mov	sp, r7
 801704c:	bd80      	pop	{r7, pc}
 801704e:	bf00      	nop
 8017050:	24002b70 	.word	0x24002b70
 8017054:	24002b40 	.word	0x24002b40
 8017058:	24002b54 	.word	0x24002b54
 801705c:	24002b68 	.word	0x24002b68
 8017060:	24002b6c 	.word	0x24002b6c
 8017064:	24002c1c 	.word	0x24002c1c
 8017068:	24002b7c 	.word	0x24002b7c
 801706c:	080189bc 	.word	0x080189bc

08017070 <xTimerIsTimerActive>:
/*-----------------------------------------------------------*/

BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
{
 8017070:	b580      	push	{r7, lr}
 8017072:	b086      	sub	sp, #24
 8017074:	af00      	add	r7, sp, #0
 8017076:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;
Timer_t *pxTimer = xTimer;
 8017078:	687b      	ldr	r3, [r7, #4]
 801707a:	613b      	str	r3, [r7, #16]

	configASSERT( xTimer );
 801707c:	687b      	ldr	r3, [r7, #4]
 801707e:	2b00      	cmp	r3, #0
 8017080:	d10b      	bne.n	801709a <xTimerIsTimerActive+0x2a>
	__asm volatile
 8017082:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8017086:	f383 8811 	msr	BASEPRI, r3
 801708a:	f3bf 8f6f 	isb	sy
 801708e:	f3bf 8f4f 	dsb	sy
 8017092:	60fb      	str	r3, [r7, #12]
}
 8017094:	bf00      	nop
 8017096:	bf00      	nop
 8017098:	e7fd      	b.n	8017096 <xTimerIsTimerActive+0x26>

	/* Is the timer in the list of active timers? */
	taskENTER_CRITICAL();
 801709a:	f000 f965 	bl	8017368 <vPortEnterCritical>
	{
		if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
 801709e:	693b      	ldr	r3, [r7, #16]
 80170a0:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
 80170a4:	f003 0301 	and.w	r3, r3, #1
 80170a8:	2b00      	cmp	r3, #0
 80170aa:	d102      	bne.n	80170b2 <xTimerIsTimerActive+0x42>
		{
			xReturn = pdFALSE;
 80170ac:	2300      	movs	r3, #0
 80170ae:	617b      	str	r3, [r7, #20]
 80170b0:	e001      	b.n	80170b6 <xTimerIsTimerActive+0x46>
		}
		else
		{
			xReturn = pdTRUE;
 80170b2:	2301      	movs	r3, #1
 80170b4:	617b      	str	r3, [r7, #20]
		}
	}
	taskEXIT_CRITICAL();
 80170b6:	f000 f989 	bl	80173cc <vPortExitCritical>

	return xReturn;
 80170ba:	697b      	ldr	r3, [r7, #20]
} /*lint !e818 Can't be pointer to const due to the typedef. */
 80170bc:	4618      	mov	r0, r3
 80170be:	3718      	adds	r7, #24
 80170c0:	46bd      	mov	sp, r7
 80170c2:	bd80      	pop	{r7, pc}

080170c4 <pvTimerGetTimerID>:
/*-----------------------------------------------------------*/

void *pvTimerGetTimerID( const TimerHandle_t xTimer )
{
 80170c4:	b580      	push	{r7, lr}
 80170c6:	b086      	sub	sp, #24
 80170c8:	af00      	add	r7, sp, #0
 80170ca:	6078      	str	r0, [r7, #4]
Timer_t * const pxTimer = xTimer;
 80170cc:	687b      	ldr	r3, [r7, #4]
 80170ce:	617b      	str	r3, [r7, #20]
void *pvReturn;

	configASSERT( xTimer );
 80170d0:	687b      	ldr	r3, [r7, #4]
 80170d2:	2b00      	cmp	r3, #0
 80170d4:	d10b      	bne.n	80170ee <pvTimerGetTimerID+0x2a>
	__asm volatile
 80170d6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80170da:	f383 8811 	msr	BASEPRI, r3
 80170de:	f3bf 8f6f 	isb	sy
 80170e2:	f3bf 8f4f 	dsb	sy
 80170e6:	60fb      	str	r3, [r7, #12]
}
 80170e8:	bf00      	nop
 80170ea:	bf00      	nop
 80170ec:	e7fd      	b.n	80170ea <pvTimerGetTimerID+0x26>

	taskENTER_CRITICAL();
 80170ee:	f000 f93b 	bl	8017368 <vPortEnterCritical>
	{
		pvReturn = pxTimer->pvTimerID;
 80170f2:	697b      	ldr	r3, [r7, #20]
 80170f4:	69db      	ldr	r3, [r3, #28]
 80170f6:	613b      	str	r3, [r7, #16]
	}
	taskEXIT_CRITICAL();
 80170f8:	f000 f968 	bl	80173cc <vPortExitCritical>

	return pvReturn;
 80170fc:	693b      	ldr	r3, [r7, #16]
}
 80170fe:	4618      	mov	r0, r3
 8017100:	3718      	adds	r7, #24
 8017102:	46bd      	mov	sp, r7
 8017104:	bd80      	pop	{r7, pc}
	...

08017108 <pxPortInitialiseStack>:

/*
 * See header file for description.
 */
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
 8017108:	b480      	push	{r7}
 801710a:	b085      	sub	sp, #20
 801710c:	af00      	add	r7, sp, #0
 801710e:	60f8      	str	r0, [r7, #12]
 8017110:	60b9      	str	r1, [r7, #8]
 8017112:	607a      	str	r2, [r7, #4]
	/* Simulate the stack frame as it would be created by a context switch
	interrupt. */

	/* Offset added to account for the way the MCU uses the stack on entry/exit
	of interrupts, and to ensure alignment. */
	pxTopOfStack--;
 8017114:	68fb      	ldr	r3, [r7, #12]
 8017116:	3b04      	subs	r3, #4
 8017118:	60fb      	str	r3, [r7, #12]

	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
 801711a:	68fb      	ldr	r3, [r7, #12]
 801711c:	f04f 7280 	mov.w	r2, #16777216	@ 0x1000000
 8017120:	601a      	str	r2, [r3, #0]
	pxTopOfStack--;
 8017122:	68fb      	ldr	r3, [r7, #12]
 8017124:	3b04      	subs	r3, #4
 8017126:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
 8017128:	68bb      	ldr	r3, [r7, #8]
 801712a:	f023 0201 	bic.w	r2, r3, #1
 801712e:	68fb      	ldr	r3, [r7, #12]
 8017130:	601a      	str	r2, [r3, #0]
	pxTopOfStack--;
 8017132:	68fb      	ldr	r3, [r7, #12]
 8017134:	3b04      	subs	r3, #4
 8017136:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
 8017138:	4a0c      	ldr	r2, [pc, #48]	@ (801716c <pxPortInitialiseStack+0x64>)
 801713a:	68fb      	ldr	r3, [r7, #12]
 801713c:	601a      	str	r2, [r3, #0]

	/* Save code space by skipping register initialisation. */
	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
 801713e:	68fb      	ldr	r3, [r7, #12]
 8017140:	3b14      	subs	r3, #20
 8017142:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
 8017144:	687a      	ldr	r2, [r7, #4]
 8017146:	68fb      	ldr	r3, [r7, #12]
 8017148:	601a      	str	r2, [r3, #0]

	/* A save method is being used that requires each task to maintain its
	own exec return value. */
	pxTopOfStack--;
 801714a:	68fb      	ldr	r3, [r7, #12]
 801714c:	3b04      	subs	r3, #4
 801714e:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = portINITIAL_EXC_RETURN;
 8017150:	68fb      	ldr	r3, [r7, #12]
 8017152:	f06f 0202 	mvn.w	r2, #2
 8017156:	601a      	str	r2, [r3, #0]

	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
 8017158:	68fb      	ldr	r3, [r7, #12]
 801715a:	3b20      	subs	r3, #32
 801715c:	60fb      	str	r3, [r7, #12]

	return pxTopOfStack;
 801715e:	68fb      	ldr	r3, [r7, #12]
}
 8017160:	4618      	mov	r0, r3
 8017162:	3714      	adds	r7, #20
 8017164:	46bd      	mov	sp, r7
 8017166:	f85d 7b04 	ldr.w	r7, [sp], #4
 801716a:	4770      	bx	lr
 801716c:	08017171 	.word	0x08017171

08017170 <prvTaskExitError>:
/*-----------------------------------------------------------*/

static void prvTaskExitError( void )
{
 8017170:	b480      	push	{r7}
 8017172:	b085      	sub	sp, #20
 8017174:	af00      	add	r7, sp, #0
volatile uint32_t ulDummy = 0;
 8017176:	2300      	movs	r3, #0
 8017178:	607b      	str	r3, [r7, #4]
	its caller as there is nothing to return to.  If a task wants to exit it
	should instead call vTaskDelete( NULL ).

	Artificially force an assert() to be triggered if configASSERT() is
	defined, then stop here so application writers can catch the error. */
	configASSERT( uxCriticalNesting == ~0UL );
 801717a:	4b13      	ldr	r3, [pc, #76]	@ (80171c8 <prvTaskExitError+0x58>)
 801717c:	681b      	ldr	r3, [r3, #0]
 801717e:	f1b3 3fff 	cmp.w	r3, #4294967295	@ 0xffffffff
 8017182:	d00b      	beq.n	801719c <prvTaskExitError+0x2c>
	__asm volatile
 8017184:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8017188:	f383 8811 	msr	BASEPRI, r3
 801718c:	f3bf 8f6f 	isb	sy
 8017190:	f3bf 8f4f 	dsb	sy
 8017194:	60fb      	str	r3, [r7, #12]
}
 8017196:	bf00      	nop
 8017198:	bf00      	nop
 801719a:	e7fd      	b.n	8017198 <prvTaskExitError+0x28>
	__asm volatile
 801719c:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80171a0:	f383 8811 	msr	BASEPRI, r3
 80171a4:	f3bf 8f6f 	isb	sy
 80171a8:	f3bf 8f4f 	dsb	sy
 80171ac:	60bb      	str	r3, [r7, #8]
}
 80171ae:	bf00      	nop
	portDISABLE_INTERRUPTS();
	while( ulDummy == 0 )
 80171b0:	bf00      	nop
 80171b2:	687b      	ldr	r3, [r7, #4]
 80171b4:	2b00      	cmp	r3, #0
 80171b6:	d0fc      	beq.n	80171b2 <prvTaskExitError+0x42>
		about code appearing after this function is called - making ulDummy
		volatile makes the compiler think the function could return and
		therefore not output an 'unreachable code' warning for code that appears
		after it. */
	}
}
 80171b8:	bf00      	nop
 80171ba:	bf00      	nop
 80171bc:	3714      	adds	r7, #20
 80171be:	46bd      	mov	sp, r7
 80171c0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80171c4:	4770      	bx	lr
 80171c6:	bf00      	nop
 80171c8:	24000044 	.word	0x24000044
 80171cc:	00000000 	.word	0x00000000

080171d0 <SVC_Handler>:
/*-----------------------------------------------------------*/

void vPortSVCHandler( void )
{
	__asm volatile (
 80171d0:	4b07      	ldr	r3, [pc, #28]	@ (80171f0 <pxCurrentTCBConst2>)
 80171d2:	6819      	ldr	r1, [r3, #0]
 80171d4:	6808      	ldr	r0, [r1, #0]
 80171d6:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 80171da:	f380 8809 	msr	PSP, r0
 80171de:	f3bf 8f6f 	isb	sy
 80171e2:	f04f 0000 	mov.w	r0, #0
 80171e6:	f380 8811 	msr	BASEPRI, r0
 80171ea:	4770      	bx	lr
 80171ec:	f3af 8000 	nop.w

080171f0 <pxCurrentTCBConst2>:
 80171f0:	24002640 	.word	0x24002640
					"	bx r14							\n"
					"									\n"
					"	.align 4						\n"
					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
				);
}
 80171f4:	bf00      	nop
 80171f6:	bf00      	nop

080171f8 <prvPortStartFirstTask>:
{
	/* Start the first task.  This also clears the bit that indicates the FPU is
	in use in case the FPU was used before the scheduler was started - which
	would otherwise result in the unnecessary leaving of space in the SVC stack
	for lazy saving of FPU registers. */
	__asm volatile(
 80171f8:	4808      	ldr	r0, [pc, #32]	@ (801721c <prvPortStartFirstTask+0x24>)
 80171fa:	6800      	ldr	r0, [r0, #0]
 80171fc:	6800      	ldr	r0, [r0, #0]
 80171fe:	f380 8808 	msr	MSP, r0
 8017202:	f04f 0000 	mov.w	r0, #0
 8017206:	f380 8814 	msr	CONTROL, r0
 801720a:	b662      	cpsie	i
 801720c:	b661      	cpsie	f
 801720e:	f3bf 8f4f 	dsb	sy
 8017212:	f3bf 8f6f 	isb	sy
 8017216:	df00      	svc	0
 8017218:	bf00      	nop
					" dsb					\n"
					" isb					\n"
					" svc 0					\n" /* System call to start first task. */
					" nop					\n"
				);
}
 801721a:	bf00      	nop
 801721c:	e000ed08 	.word	0xe000ed08

08017220 <xPortStartScheduler>:

/*
 * See header file for description.
 */
BaseType_t xPortStartScheduler( void )
{
 8017220:	b580      	push	{r7, lr}
 8017222:	b086      	sub	sp, #24
 8017224:	af00      	add	r7, sp, #0
	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );

	/* This port can be used on all revisions of the Cortex-M7 core other than
	the r0p1 parts.  r0p1 parts should use the port from the
	/source/portable/GCC/ARM_CM7/r0p1 directory. */
	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
 8017226:	4b47      	ldr	r3, [pc, #284]	@ (8017344 <xPortStartScheduler+0x124>)
 8017228:	681b      	ldr	r3, [r3, #0]
 801722a:	4a47      	ldr	r2, [pc, #284]	@ (8017348 <xPortStartScheduler+0x128>)
 801722c:	4293      	cmp	r3, r2
 801722e:	d10b      	bne.n	8017248 <xPortStartScheduler+0x28>
	__asm volatile
 8017230:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8017234:	f383 8811 	msr	BASEPRI, r3
 8017238:	f3bf 8f6f 	isb	sy
 801723c:	f3bf 8f4f 	dsb	sy
 8017240:	613b      	str	r3, [r7, #16]
}
 8017242:	bf00      	nop
 8017244:	bf00      	nop
 8017246:	e7fd      	b.n	8017244 <xPortStartScheduler+0x24>
	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
 8017248:	4b3e      	ldr	r3, [pc, #248]	@ (8017344 <xPortStartScheduler+0x124>)
 801724a:	681b      	ldr	r3, [r3, #0]
 801724c:	4a3f      	ldr	r2, [pc, #252]	@ (801734c <xPortStartScheduler+0x12c>)
 801724e:	4293      	cmp	r3, r2
 8017250:	d10b      	bne.n	801726a <xPortStartScheduler+0x4a>
	__asm volatile
 8017252:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8017256:	f383 8811 	msr	BASEPRI, r3
 801725a:	f3bf 8f6f 	isb	sy
 801725e:	f3bf 8f4f 	dsb	sy
 8017262:	60fb      	str	r3, [r7, #12]
}
 8017264:	bf00      	nop
 8017266:	bf00      	nop
 8017268:	e7fd      	b.n	8017266 <xPortStartScheduler+0x46>

	#if( configASSERT_DEFINED == 1 )
	{
		volatile uint32_t ulOriginalPriority;
		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
 801726a:	4b39      	ldr	r3, [pc, #228]	@ (8017350 <xPortStartScheduler+0x130>)
 801726c:	617b      	str	r3, [r7, #20]
		functions can be called.  ISR safe functions are those that end in
		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
		ensure interrupt entry is as fast and simple as possible.

		Save the interrupt priority value that is about to be clobbered. */
		ulOriginalPriority = *pucFirstUserPriorityRegister;
 801726e:	697b      	ldr	r3, [r7, #20]
 8017270:	781b      	ldrb	r3, [r3, #0]
 8017272:	b2db      	uxtb	r3, r3
 8017274:	607b      	str	r3, [r7, #4]

		/* Determine the number of priority bits available.  First write to all
		possible bits. */
		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
 8017276:	697b      	ldr	r3, [r7, #20]
 8017278:	22ff      	movs	r2, #255	@ 0xff
 801727a:	701a      	strb	r2, [r3, #0]

		/* Read the value back to see how many bits stuck. */
		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
 801727c:	697b      	ldr	r3, [r7, #20]
 801727e:	781b      	ldrb	r3, [r3, #0]
 8017280:	b2db      	uxtb	r3, r3
 8017282:	70fb      	strb	r3, [r7, #3]

		/* Use the same mask on the maximum system call priority. */
		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 8017284:	78fb      	ldrb	r3, [r7, #3]
 8017286:	b2db      	uxtb	r3, r3
 8017288:	f003 0350 	and.w	r3, r3, #80	@ 0x50
 801728c:	b2da      	uxtb	r2, r3
 801728e:	4b31      	ldr	r3, [pc, #196]	@ (8017354 <xPortStartScheduler+0x134>)
 8017290:	701a      	strb	r2, [r3, #0]

		/* Calculate the maximum acceptable priority group value for the number
		of bits read back. */
		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
 8017292:	4b31      	ldr	r3, [pc, #196]	@ (8017358 <xPortStartScheduler+0x138>)
 8017294:	2207      	movs	r2, #7
 8017296:	601a      	str	r2, [r3, #0]
		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
 8017298:	e009      	b.n	80172ae <xPortStartScheduler+0x8e>
		{
			ulMaxPRIGROUPValue--;
 801729a:	4b2f      	ldr	r3, [pc, #188]	@ (8017358 <xPortStartScheduler+0x138>)
 801729c:	681b      	ldr	r3, [r3, #0]
 801729e:	3b01      	subs	r3, #1
 80172a0:	4a2d      	ldr	r2, [pc, #180]	@ (8017358 <xPortStartScheduler+0x138>)
 80172a2:	6013      	str	r3, [r2, #0]
			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
 80172a4:	78fb      	ldrb	r3, [r7, #3]
 80172a6:	b2db      	uxtb	r3, r3
 80172a8:	005b      	lsls	r3, r3, #1
 80172aa:	b2db      	uxtb	r3, r3
 80172ac:	70fb      	strb	r3, [r7, #3]
		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
 80172ae:	78fb      	ldrb	r3, [r7, #3]
 80172b0:	b2db      	uxtb	r3, r3
 80172b2:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80172b6:	2b80      	cmp	r3, #128	@ 0x80
 80172b8:	d0ef      	beq.n	801729a <xPortStartScheduler+0x7a>
		#ifdef configPRIO_BITS
		{
			/* Check the FreeRTOS configuration that defines the number of
			priority bits matches the number of priority bits actually queried
			from the hardware. */
			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
 80172ba:	4b27      	ldr	r3, [pc, #156]	@ (8017358 <xPortStartScheduler+0x138>)
 80172bc:	681b      	ldr	r3, [r3, #0]
 80172be:	f1c3 0307 	rsb	r3, r3, #7
 80172c2:	2b04      	cmp	r3, #4
 80172c4:	d00b      	beq.n	80172de <xPortStartScheduler+0xbe>
	__asm volatile
 80172c6:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80172ca:	f383 8811 	msr	BASEPRI, r3
 80172ce:	f3bf 8f6f 	isb	sy
 80172d2:	f3bf 8f4f 	dsb	sy
 80172d6:	60bb      	str	r3, [r7, #8]
}
 80172d8:	bf00      	nop
 80172da:	bf00      	nop
 80172dc:	e7fd      	b.n	80172da <xPortStartScheduler+0xba>
		}
		#endif

		/* Shift the priority group value back to its position within the AIRCR
		register. */
		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
 80172de:	4b1e      	ldr	r3, [pc, #120]	@ (8017358 <xPortStartScheduler+0x138>)
 80172e0:	681b      	ldr	r3, [r3, #0]
 80172e2:	021b      	lsls	r3, r3, #8
 80172e4:	4a1c      	ldr	r2, [pc, #112]	@ (8017358 <xPortStartScheduler+0x138>)
 80172e6:	6013      	str	r3, [r2, #0]
		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
 80172e8:	4b1b      	ldr	r3, [pc, #108]	@ (8017358 <xPortStartScheduler+0x138>)
 80172ea:	681b      	ldr	r3, [r3, #0]
 80172ec:	f403 63e0 	and.w	r3, r3, #1792	@ 0x700
 80172f0:	4a19      	ldr	r2, [pc, #100]	@ (8017358 <xPortStartScheduler+0x138>)
 80172f2:	6013      	str	r3, [r2, #0]

		/* Restore the clobbered interrupt priority register to its original
		value. */
		*pucFirstUserPriorityRegister = ulOriginalPriority;
 80172f4:	687b      	ldr	r3, [r7, #4]
 80172f6:	b2da      	uxtb	r2, r3
 80172f8:	697b      	ldr	r3, [r7, #20]
 80172fa:	701a      	strb	r2, [r3, #0]
	}
	#endif /* conifgASSERT_DEFINED */

	/* Make PendSV and SysTick the lowest priority interrupts. */
	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
 80172fc:	4b17      	ldr	r3, [pc, #92]	@ (801735c <xPortStartScheduler+0x13c>)
 80172fe:	681b      	ldr	r3, [r3, #0]
 8017300:	4a16      	ldr	r2, [pc, #88]	@ (801735c <xPortStartScheduler+0x13c>)
 8017302:	f443 0370 	orr.w	r3, r3, #15728640	@ 0xf00000
 8017306:	6013      	str	r3, [r2, #0]
	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
 8017308:	4b14      	ldr	r3, [pc, #80]	@ (801735c <xPortStartScheduler+0x13c>)
 801730a:	681b      	ldr	r3, [r3, #0]
 801730c:	4a13      	ldr	r2, [pc, #76]	@ (801735c <xPortStartScheduler+0x13c>)
 801730e:	f043 4370 	orr.w	r3, r3, #4026531840	@ 0xf0000000
 8017312:	6013      	str	r3, [r2, #0]

	/* Start the timer that generates the tick ISR.  Interrupts are disabled
	here already. */
	vPortSetupTimerInterrupt();
 8017314:	f000 f8da 	bl	80174cc <vPortSetupTimerInterrupt>

	/* Initialise the critical nesting count ready for the first task. */
	uxCriticalNesting = 0;
 8017318:	4b11      	ldr	r3, [pc, #68]	@ (8017360 <xPortStartScheduler+0x140>)
 801731a:	2200      	movs	r2, #0
 801731c:	601a      	str	r2, [r3, #0]

	/* Ensure the VFP is enabled - it should be anyway. */
	vPortEnableVFP();
 801731e:	f000 f8f9 	bl	8017514 <vPortEnableVFP>

	/* Lazy save always. */
	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
 8017322:	4b10      	ldr	r3, [pc, #64]	@ (8017364 <xPortStartScheduler+0x144>)
 8017324:	681b      	ldr	r3, [r3, #0]
 8017326:	4a0f      	ldr	r2, [pc, #60]	@ (8017364 <xPortStartScheduler+0x144>)
 8017328:	f043 4340 	orr.w	r3, r3, #3221225472	@ 0xc0000000
 801732c:	6013      	str	r3, [r2, #0]

	/* Start the first task. */
	prvPortStartFirstTask();
 801732e:	f7ff ff63 	bl	80171f8 <prvPortStartFirstTask>
	exit error function to prevent compiler warnings about a static function
	not being called in the case that the application writer overrides this
	functionality by defining configTASK_RETURN_ADDRESS.  Call
	vTaskSwitchContext() so link time optimisation does not remove the
	symbol. */
	vTaskSwitchContext();
 8017332:	f7fe fbd1 	bl	8015ad8 <vTaskSwitchContext>
	prvTaskExitError();
 8017336:	f7ff ff1b 	bl	8017170 <prvTaskExitError>

	/* Should not get here! */
	return 0;
 801733a:	2300      	movs	r3, #0
}
 801733c:	4618      	mov	r0, r3
 801733e:	3718      	adds	r7, #24
 8017340:	46bd      	mov	sp, r7
 8017342:	bd80      	pop	{r7, pc}
 8017344:	e000ed00 	.word	0xe000ed00
 8017348:	410fc271 	.word	0x410fc271
 801734c:	410fc270 	.word	0x410fc270
 8017350:	e000e400 	.word	0xe000e400
 8017354:	24002c6c 	.word	0x24002c6c
 8017358:	24002c70 	.word	0x24002c70
 801735c:	e000ed20 	.word	0xe000ed20
 8017360:	24000044 	.word	0x24000044
 8017364:	e000ef34 	.word	0xe000ef34

08017368 <vPortEnterCritical>:
	configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/

void vPortEnterCritical( void )
{
 8017368:	b480      	push	{r7}
 801736a:	b083      	sub	sp, #12
 801736c:	af00      	add	r7, sp, #0
	__asm volatile
 801736e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8017372:	f383 8811 	msr	BASEPRI, r3
 8017376:	f3bf 8f6f 	isb	sy
 801737a:	f3bf 8f4f 	dsb	sy
 801737e:	607b      	str	r3, [r7, #4]
}
 8017380:	bf00      	nop
	portDISABLE_INTERRUPTS();
	uxCriticalNesting++;
 8017382:	4b10      	ldr	r3, [pc, #64]	@ (80173c4 <vPortEnterCritical+0x5c>)
 8017384:	681b      	ldr	r3, [r3, #0]
 8017386:	3301      	adds	r3, #1
 8017388:	4a0e      	ldr	r2, [pc, #56]	@ (80173c4 <vPortEnterCritical+0x5c>)
 801738a:	6013      	str	r3, [r2, #0]
	/* This is not the interrupt safe version of the enter critical function so
	assert() if it is being called from an interrupt context.  Only API
	functions that end in "FromISR" can be used in an interrupt.  Only assert if
	the critical nesting count is 1 to protect against recursive calls if the
	assert function also uses a critical section. */
	if( uxCriticalNesting == 1 )
 801738c:	4b0d      	ldr	r3, [pc, #52]	@ (80173c4 <vPortEnterCritical+0x5c>)
 801738e:	681b      	ldr	r3, [r3, #0]
 8017390:	2b01      	cmp	r3, #1
 8017392:	d110      	bne.n	80173b6 <vPortEnterCritical+0x4e>
	{
		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
 8017394:	4b0c      	ldr	r3, [pc, #48]	@ (80173c8 <vPortEnterCritical+0x60>)
 8017396:	681b      	ldr	r3, [r3, #0]
 8017398:	b2db      	uxtb	r3, r3
 801739a:	2b00      	cmp	r3, #0
 801739c:	d00b      	beq.n	80173b6 <vPortEnterCritical+0x4e>
	__asm volatile
 801739e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80173a2:	f383 8811 	msr	BASEPRI, r3
 80173a6:	f3bf 8f6f 	isb	sy
 80173aa:	f3bf 8f4f 	dsb	sy
 80173ae:	603b      	str	r3, [r7, #0]
}
 80173b0:	bf00      	nop
 80173b2:	bf00      	nop
 80173b4:	e7fd      	b.n	80173b2 <vPortEnterCritical+0x4a>
	}
}
 80173b6:	bf00      	nop
 80173b8:	370c      	adds	r7, #12
 80173ba:	46bd      	mov	sp, r7
 80173bc:	f85d 7b04 	ldr.w	r7, [sp], #4
 80173c0:	4770      	bx	lr
 80173c2:	bf00      	nop
 80173c4:	24000044 	.word	0x24000044
 80173c8:	e000ed04 	.word	0xe000ed04

080173cc <vPortExitCritical>:
/*-----------------------------------------------------------*/

void vPortExitCritical( void )
{
 80173cc:	b480      	push	{r7}
 80173ce:	b083      	sub	sp, #12
 80173d0:	af00      	add	r7, sp, #0
	configASSERT( uxCriticalNesting );
 80173d2:	4b12      	ldr	r3, [pc, #72]	@ (801741c <vPortExitCritical+0x50>)
 80173d4:	681b      	ldr	r3, [r3, #0]
 80173d6:	2b00      	cmp	r3, #0
 80173d8:	d10b      	bne.n	80173f2 <vPortExitCritical+0x26>
	__asm volatile
 80173da:	f04f 0350 	mov.w	r3, #80	@ 0x50
 80173de:	f383 8811 	msr	BASEPRI, r3
 80173e2:	f3bf 8f6f 	isb	sy
 80173e6:	f3bf 8f4f 	dsb	sy
 80173ea:	607b      	str	r3, [r7, #4]
}
 80173ec:	bf00      	nop
 80173ee:	bf00      	nop
 80173f0:	e7fd      	b.n	80173ee <vPortExitCritical+0x22>
	uxCriticalNesting--;
 80173f2:	4b0a      	ldr	r3, [pc, #40]	@ (801741c <vPortExitCritical+0x50>)
 80173f4:	681b      	ldr	r3, [r3, #0]
 80173f6:	3b01      	subs	r3, #1
 80173f8:	4a08      	ldr	r2, [pc, #32]	@ (801741c <vPortExitCritical+0x50>)
 80173fa:	6013      	str	r3, [r2, #0]
	if( uxCriticalNesting == 0 )
 80173fc:	4b07      	ldr	r3, [pc, #28]	@ (801741c <vPortExitCritical+0x50>)
 80173fe:	681b      	ldr	r3, [r3, #0]
 8017400:	2b00      	cmp	r3, #0
 8017402:	d105      	bne.n	8017410 <vPortExitCritical+0x44>
 8017404:	2300      	movs	r3, #0
 8017406:	603b      	str	r3, [r7, #0]
	__asm volatile
 8017408:	683b      	ldr	r3, [r7, #0]
 801740a:	f383 8811 	msr	BASEPRI, r3
}
 801740e:	bf00      	nop
	{
		portENABLE_INTERRUPTS();
	}
}
 8017410:	bf00      	nop
 8017412:	370c      	adds	r7, #12
 8017414:	46bd      	mov	sp, r7
 8017416:	f85d 7b04 	ldr.w	r7, [sp], #4
 801741a:	4770      	bx	lr
 801741c:	24000044 	.word	0x24000044

08017420 <PendSV_Handler>:

void xPortPendSVHandler( void )
{
	/* This is a naked function. */

	__asm volatile
 8017420:	f3ef 8009 	mrs	r0, PSP
 8017424:	f3bf 8f6f 	isb	sy
 8017428:	4b15      	ldr	r3, [pc, #84]	@ (8017480 <pxCurrentTCBConst>)
 801742a:	681a      	ldr	r2, [r3, #0]
 801742c:	f01e 0f10 	tst.w	lr, #16
 8017430:	bf08      	it	eq
 8017432:	ed20 8a10 	vstmdbeq	r0!, {s16-s31}
 8017436:	e920 4ff0 	stmdb	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 801743a:	6010      	str	r0, [r2, #0]
 801743c:	e92d 0009 	stmdb	sp!, {r0, r3}
 8017440:	f04f 0050 	mov.w	r0, #80	@ 0x50
 8017444:	f380 8811 	msr	BASEPRI, r0
 8017448:	f3bf 8f4f 	dsb	sy
 801744c:	f3bf 8f6f 	isb	sy
 8017450:	f7fe fb42 	bl	8015ad8 <vTaskSwitchContext>
 8017454:	f04f 0000 	mov.w	r0, #0
 8017458:	f380 8811 	msr	BASEPRI, r0
 801745c:	bc09      	pop	{r0, r3}
 801745e:	6819      	ldr	r1, [r3, #0]
 8017460:	6808      	ldr	r0, [r1, #0]
 8017462:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8017466:	f01e 0f10 	tst.w	lr, #16
 801746a:	bf08      	it	eq
 801746c:	ecb0 8a10 	vldmiaeq	r0!, {s16-s31}
 8017470:	f380 8809 	msr	PSP, r0
 8017474:	f3bf 8f6f 	isb	sy
 8017478:	4770      	bx	lr
 801747a:	bf00      	nop
 801747c:	f3af 8000 	nop.w

08017480 <pxCurrentTCBConst>:
 8017480:	24002640 	.word	0x24002640
	"										\n"
	"	.align 4							\n"
	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
	);
}
 8017484:	bf00      	nop
 8017486:	bf00      	nop

08017488 <xPortSysTickHandler>:
/*-----------------------------------------------------------*/

void xPortSysTickHandler( void )
{
 8017488:	b580      	push	{r7, lr}
 801748a:	b082      	sub	sp, #8
 801748c:	af00      	add	r7, sp, #0
	__asm volatile
 801748e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8017492:	f383 8811 	msr	BASEPRI, r3
 8017496:	f3bf 8f6f 	isb	sy
 801749a:	f3bf 8f4f 	dsb	sy
 801749e:	607b      	str	r3, [r7, #4]
}
 80174a0:	bf00      	nop
	save and then restore the interrupt mask value as its value is already
	known. */
	portDISABLE_INTERRUPTS();
	{
		/* Increment the RTOS tick. */
		if( xTaskIncrementTick() != pdFALSE )
 80174a2:	f7fe fa5f 	bl	8015964 <xTaskIncrementTick>
 80174a6:	4603      	mov	r3, r0
 80174a8:	2b00      	cmp	r3, #0
 80174aa:	d003      	beq.n	80174b4 <xPortSysTickHandler+0x2c>
		{
			/* A context switch is required.  Context switching is performed in
			the PendSV interrupt.  Pend the PendSV interrupt. */
			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
 80174ac:	4b06      	ldr	r3, [pc, #24]	@ (80174c8 <xPortSysTickHandler+0x40>)
 80174ae:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
 80174b2:	601a      	str	r2, [r3, #0]
 80174b4:	2300      	movs	r3, #0
 80174b6:	603b      	str	r3, [r7, #0]
	__asm volatile
 80174b8:	683b      	ldr	r3, [r7, #0]
 80174ba:	f383 8811 	msr	BASEPRI, r3
}
 80174be:	bf00      	nop
		}
	}
	portENABLE_INTERRUPTS();
}
 80174c0:	bf00      	nop
 80174c2:	3708      	adds	r7, #8
 80174c4:	46bd      	mov	sp, r7
 80174c6:	bd80      	pop	{r7, pc}
 80174c8:	e000ed04 	.word	0xe000ed04

080174cc <vPortSetupTimerInterrupt>:
/*
 * Setup the systick timer to generate the tick interrupts at the required
 * frequency.
 */
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
 80174cc:	b480      	push	{r7}
 80174ce:	af00      	add	r7, sp, #0
		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
	}
	#endif /* configUSE_TICKLESS_IDLE */

	/* Stop and clear the SysTick. */
	portNVIC_SYSTICK_CTRL_REG = 0UL;
 80174d0:	4b0b      	ldr	r3, [pc, #44]	@ (8017500 <vPortSetupTimerInterrupt+0x34>)
 80174d2:	2200      	movs	r2, #0
 80174d4:	601a      	str	r2, [r3, #0]
	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 80174d6:	4b0b      	ldr	r3, [pc, #44]	@ (8017504 <vPortSetupTimerInterrupt+0x38>)
 80174d8:	2200      	movs	r2, #0
 80174da:	601a      	str	r2, [r3, #0]

	/* Configure SysTick to interrupt at the requested rate. */
	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
 80174dc:	4b0a      	ldr	r3, [pc, #40]	@ (8017508 <vPortSetupTimerInterrupt+0x3c>)
 80174de:	681b      	ldr	r3, [r3, #0]
 80174e0:	4a0a      	ldr	r2, [pc, #40]	@ (801750c <vPortSetupTimerInterrupt+0x40>)
 80174e2:	fba2 2303 	umull	r2, r3, r2, r3
 80174e6:	099b      	lsrs	r3, r3, #6
 80174e8:	4a09      	ldr	r2, [pc, #36]	@ (8017510 <vPortSetupTimerInterrupt+0x44>)
 80174ea:	3b01      	subs	r3, #1
 80174ec:	6013      	str	r3, [r2, #0]
	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
 80174ee:	4b04      	ldr	r3, [pc, #16]	@ (8017500 <vPortSetupTimerInterrupt+0x34>)
 80174f0:	2207      	movs	r2, #7
 80174f2:	601a      	str	r2, [r3, #0]
}
 80174f4:	bf00      	nop
 80174f6:	46bd      	mov	sp, r7
 80174f8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80174fc:	4770      	bx	lr
 80174fe:	bf00      	nop
 8017500:	e000e010 	.word	0xe000e010
 8017504:	e000e018 	.word	0xe000e018
 8017508:	24000034 	.word	0x24000034
 801750c:	10624dd3 	.word	0x10624dd3
 8017510:	e000e014 	.word	0xe000e014

08017514 <vPortEnableVFP>:
/*-----------------------------------------------------------*/

/* This is a naked function. */
static void vPortEnableVFP( void )
{
	__asm volatile
 8017514:	f8df 000c 	ldr.w	r0, [pc, #12]	@ 8017524 <vPortEnableVFP+0x10>
 8017518:	6801      	ldr	r1, [r0, #0]
 801751a:	f441 0170 	orr.w	r1, r1, #15728640	@ 0xf00000
 801751e:	6001      	str	r1, [r0, #0]
 8017520:	4770      	bx	lr
		"								\n"
		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
		"	str r1, [r0]				\n"
		"	bx r14						"
	);
}
 8017522:	bf00      	nop
 8017524:	e000ed88 	.word	0xe000ed88

08017528 <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/

#if( configASSERT_DEFINED == 1 )

	void vPortValidateInterruptPriority( void )
	{
 8017528:	b480      	push	{r7}
 801752a:	b085      	sub	sp, #20
 801752c:	af00      	add	r7, sp, #0
	uint32_t ulCurrentInterrupt;
	uint8_t ucCurrentPriority;

		/* Obtain the number of the currently executing interrupt. */
		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
 801752e:	f3ef 8305 	mrs	r3, IPSR
 8017532:	60fb      	str	r3, [r7, #12]

		/* Is the interrupt number a user defined interrupt? */
		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
 8017534:	68fb      	ldr	r3, [r7, #12]
 8017536:	2b0f      	cmp	r3, #15
 8017538:	d915      	bls.n	8017566 <vPortValidateInterruptPriority+0x3e>
		{
			/* Look up the interrupt's priority. */
			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
 801753a:	4a18      	ldr	r2, [pc, #96]	@ (801759c <vPortValidateInterruptPriority+0x74>)
 801753c:	68fb      	ldr	r3, [r7, #12]
 801753e:	4413      	add	r3, r2
 8017540:	781b      	ldrb	r3, [r3, #0]
 8017542:	72fb      	strb	r3, [r7, #11]
			interrupt entry is as fast and simple as possible.

			The following links provide detailed information:
			http://www.freertos.org/RTOS-Cortex-M3-M4.html
			http://www.freertos.org/FAQHelp.html */
			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
 8017544:	4b16      	ldr	r3, [pc, #88]	@ (80175a0 <vPortValidateInterruptPriority+0x78>)
 8017546:	781b      	ldrb	r3, [r3, #0]
 8017548:	7afa      	ldrb	r2, [r7, #11]
 801754a:	429a      	cmp	r2, r3
 801754c:	d20b      	bcs.n	8017566 <vPortValidateInterruptPriority+0x3e>
	__asm volatile
 801754e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8017552:	f383 8811 	msr	BASEPRI, r3
 8017556:	f3bf 8f6f 	isb	sy
 801755a:	f3bf 8f4f 	dsb	sy
 801755e:	607b      	str	r3, [r7, #4]
}
 8017560:	bf00      	nop
 8017562:	bf00      	nop
 8017564:	e7fd      	b.n	8017562 <vPortValidateInterruptPriority+0x3a>
		configuration then the correct setting can be achieved on all Cortex-M
		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
		scheduler.  Note however that some vendor specific peripheral libraries
		assume a non-zero priority group setting, in which cases using a value
		of zero will result in unpredictable behaviour. */
		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
 8017566:	4b0f      	ldr	r3, [pc, #60]	@ (80175a4 <vPortValidateInterruptPriority+0x7c>)
 8017568:	681b      	ldr	r3, [r3, #0]
 801756a:	f403 62e0 	and.w	r2, r3, #1792	@ 0x700
 801756e:	4b0e      	ldr	r3, [pc, #56]	@ (80175a8 <vPortValidateInterruptPriority+0x80>)
 8017570:	681b      	ldr	r3, [r3, #0]
 8017572:	429a      	cmp	r2, r3
 8017574:	d90b      	bls.n	801758e <vPortValidateInterruptPriority+0x66>
	__asm volatile
 8017576:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801757a:	f383 8811 	msr	BASEPRI, r3
 801757e:	f3bf 8f6f 	isb	sy
 8017582:	f3bf 8f4f 	dsb	sy
 8017586:	603b      	str	r3, [r7, #0]
}
 8017588:	bf00      	nop
 801758a:	bf00      	nop
 801758c:	e7fd      	b.n	801758a <vPortValidateInterruptPriority+0x62>
	}
 801758e:	bf00      	nop
 8017590:	3714      	adds	r7, #20
 8017592:	46bd      	mov	sp, r7
 8017594:	f85d 7b04 	ldr.w	r7, [sp], #4
 8017598:	4770      	bx	lr
 801759a:	bf00      	nop
 801759c:	e000e3f0 	.word	0xe000e3f0
 80175a0:	24002c6c 	.word	0x24002c6c
 80175a4:	e000ed0c 	.word	0xe000ed0c
 80175a8:	24002c70 	.word	0x24002c70

080175ac <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;

/*-----------------------------------------------------------*/

void *pvPortMalloc( size_t xWantedSize )
{
 80175ac:	b580      	push	{r7, lr}
 80175ae:	b08a      	sub	sp, #40	@ 0x28
 80175b0:	af00      	add	r7, sp, #0
 80175b2:	6078      	str	r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
 80175b4:	2300      	movs	r3, #0
 80175b6:	61fb      	str	r3, [r7, #28]

	vTaskSuspendAll();
 80175b8:	f7fe f918 	bl	80157ec <vTaskSuspendAll>
	{
		/* If this is the first call to malloc then the heap will require
		initialisation to setup the list of free blocks. */
		if( pxEnd == NULL )
 80175bc:	4b5c      	ldr	r3, [pc, #368]	@ (8017730 <pvPortMalloc+0x184>)
 80175be:	681b      	ldr	r3, [r3, #0]
 80175c0:	2b00      	cmp	r3, #0
 80175c2:	d101      	bne.n	80175c8 <pvPortMalloc+0x1c>
		{
			prvHeapInit();
 80175c4:	f000 f924 	bl	8017810 <prvHeapInit>

		/* Check the requested block size is not so large that the top bit is
		set.  The top bit of the block size member of the BlockLink_t structure
		is used to determine who owns the block - the application or the
		kernel, so it must be free. */
		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
 80175c8:	4b5a      	ldr	r3, [pc, #360]	@ (8017734 <pvPortMalloc+0x188>)
 80175ca:	681a      	ldr	r2, [r3, #0]
 80175cc:	687b      	ldr	r3, [r7, #4]
 80175ce:	4013      	ands	r3, r2
 80175d0:	2b00      	cmp	r3, #0
 80175d2:	f040 8095 	bne.w	8017700 <pvPortMalloc+0x154>
		{
			/* The wanted size is increased so it can contain a BlockLink_t
			structure in addition to the requested amount of bytes. */
			if( xWantedSize > 0 )
 80175d6:	687b      	ldr	r3, [r7, #4]
 80175d8:	2b00      	cmp	r3, #0
 80175da:	d01e      	beq.n	801761a <pvPortMalloc+0x6e>
			{
				xWantedSize += xHeapStructSize;
 80175dc:	2208      	movs	r2, #8
 80175de:	687b      	ldr	r3, [r7, #4]
 80175e0:	4413      	add	r3, r2
 80175e2:	607b      	str	r3, [r7, #4]

				/* Ensure that blocks are always aligned to the required number
				of bytes. */
				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
 80175e4:	687b      	ldr	r3, [r7, #4]
 80175e6:	f003 0307 	and.w	r3, r3, #7
 80175ea:	2b00      	cmp	r3, #0
 80175ec:	d015      	beq.n	801761a <pvPortMalloc+0x6e>
				{
					/* Byte alignment required. */
					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
 80175ee:	687b      	ldr	r3, [r7, #4]
 80175f0:	f023 0307 	bic.w	r3, r3, #7
 80175f4:	3308      	adds	r3, #8
 80175f6:	607b      	str	r3, [r7, #4]
					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
 80175f8:	687b      	ldr	r3, [r7, #4]
 80175fa:	f003 0307 	and.w	r3, r3, #7
 80175fe:	2b00      	cmp	r3, #0
 8017600:	d00b      	beq.n	801761a <pvPortMalloc+0x6e>
	__asm volatile
 8017602:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8017606:	f383 8811 	msr	BASEPRI, r3
 801760a:	f3bf 8f6f 	isb	sy
 801760e:	f3bf 8f4f 	dsb	sy
 8017612:	617b      	str	r3, [r7, #20]
}
 8017614:	bf00      	nop
 8017616:	bf00      	nop
 8017618:	e7fd      	b.n	8017616 <pvPortMalloc+0x6a>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}

			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
 801761a:	687b      	ldr	r3, [r7, #4]
 801761c:	2b00      	cmp	r3, #0
 801761e:	d06f      	beq.n	8017700 <pvPortMalloc+0x154>
 8017620:	4b45      	ldr	r3, [pc, #276]	@ (8017738 <pvPortMalloc+0x18c>)
 8017622:	681b      	ldr	r3, [r3, #0]
 8017624:	687a      	ldr	r2, [r7, #4]
 8017626:	429a      	cmp	r2, r3
 8017628:	d86a      	bhi.n	8017700 <pvPortMalloc+0x154>
			{
				/* Traverse the list from the start	(lowest address) block until
				one	of adequate size is found. */
				pxPreviousBlock = &xStart;
 801762a:	4b44      	ldr	r3, [pc, #272]	@ (801773c <pvPortMalloc+0x190>)
 801762c:	623b      	str	r3, [r7, #32]
				pxBlock = xStart.pxNextFreeBlock;
 801762e:	4b43      	ldr	r3, [pc, #268]	@ (801773c <pvPortMalloc+0x190>)
 8017630:	681b      	ldr	r3, [r3, #0]
 8017632:	627b      	str	r3, [r7, #36]	@ 0x24
				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
 8017634:	e004      	b.n	8017640 <pvPortMalloc+0x94>
				{
					pxPreviousBlock = pxBlock;
 8017636:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8017638:	623b      	str	r3, [r7, #32]
					pxBlock = pxBlock->pxNextFreeBlock;
 801763a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 801763c:	681b      	ldr	r3, [r3, #0]
 801763e:	627b      	str	r3, [r7, #36]	@ 0x24
				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
 8017640:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8017642:	685b      	ldr	r3, [r3, #4]
 8017644:	687a      	ldr	r2, [r7, #4]
 8017646:	429a      	cmp	r2, r3
 8017648:	d903      	bls.n	8017652 <pvPortMalloc+0xa6>
 801764a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 801764c:	681b      	ldr	r3, [r3, #0]
 801764e:	2b00      	cmp	r3, #0
 8017650:	d1f1      	bne.n	8017636 <pvPortMalloc+0x8a>
				}

				/* If the end marker was reached then a block of adequate size
				was	not found. */
				if( pxBlock != pxEnd )
 8017652:	4b37      	ldr	r3, [pc, #220]	@ (8017730 <pvPortMalloc+0x184>)
 8017654:	681b      	ldr	r3, [r3, #0]
 8017656:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8017658:	429a      	cmp	r2, r3
 801765a:	d051      	beq.n	8017700 <pvPortMalloc+0x154>
				{
					/* Return the memory space pointed to - jumping over the
					BlockLink_t structure at its start. */
					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
 801765c:	6a3b      	ldr	r3, [r7, #32]
 801765e:	681b      	ldr	r3, [r3, #0]
 8017660:	2208      	movs	r2, #8
 8017662:	4413      	add	r3, r2
 8017664:	61fb      	str	r3, [r7, #28]

					/* This block is being returned for use so must be taken out
					of the list of free blocks. */
					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
 8017666:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8017668:	681a      	ldr	r2, [r3, #0]
 801766a:	6a3b      	ldr	r3, [r7, #32]
 801766c:	601a      	str	r2, [r3, #0]

					/* If the block is larger than required it can be split into
					two. */
					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
 801766e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 8017670:	685a      	ldr	r2, [r3, #4]
 8017672:	687b      	ldr	r3, [r7, #4]
 8017674:	1ad2      	subs	r2, r2, r3
 8017676:	2308      	movs	r3, #8
 8017678:	005b      	lsls	r3, r3, #1
 801767a:	429a      	cmp	r2, r3
 801767c:	d920      	bls.n	80176c0 <pvPortMalloc+0x114>
					{
						/* This block is to be split into two.  Create a new
						block following the number of bytes requested. The void
						cast is used to prevent byte alignment warnings from the
						compiler. */
						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
 801767e:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8017680:	687b      	ldr	r3, [r7, #4]
 8017682:	4413      	add	r3, r2
 8017684:	61bb      	str	r3, [r7, #24]
						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
 8017686:	69bb      	ldr	r3, [r7, #24]
 8017688:	f003 0307 	and.w	r3, r3, #7
 801768c:	2b00      	cmp	r3, #0
 801768e:	d00b      	beq.n	80176a8 <pvPortMalloc+0xfc>
	__asm volatile
 8017690:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8017694:	f383 8811 	msr	BASEPRI, r3
 8017698:	f3bf 8f6f 	isb	sy
 801769c:	f3bf 8f4f 	dsb	sy
 80176a0:	613b      	str	r3, [r7, #16]
}
 80176a2:	bf00      	nop
 80176a4:	bf00      	nop
 80176a6:	e7fd      	b.n	80176a4 <pvPortMalloc+0xf8>

						/* Calculate the sizes of two blocks split from the
						single block. */
						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
 80176a8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80176aa:	685a      	ldr	r2, [r3, #4]
 80176ac:	687b      	ldr	r3, [r7, #4]
 80176ae:	1ad2      	subs	r2, r2, r3
 80176b0:	69bb      	ldr	r3, [r7, #24]
 80176b2:	605a      	str	r2, [r3, #4]
						pxBlock->xBlockSize = xWantedSize;
 80176b4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80176b6:	687a      	ldr	r2, [r7, #4]
 80176b8:	605a      	str	r2, [r3, #4]

						/* Insert the new block into the list of free blocks. */
						prvInsertBlockIntoFreeList( pxNewBlockLink );
 80176ba:	69b8      	ldr	r0, [r7, #24]
 80176bc:	f000 f90a 	bl	80178d4 <prvInsertBlockIntoFreeList>
					else
					{
						mtCOVERAGE_TEST_MARKER();
					}

					xFreeBytesRemaining -= pxBlock->xBlockSize;
 80176c0:	4b1d      	ldr	r3, [pc, #116]	@ (8017738 <pvPortMalloc+0x18c>)
 80176c2:	681a      	ldr	r2, [r3, #0]
 80176c4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80176c6:	685b      	ldr	r3, [r3, #4]
 80176c8:	1ad3      	subs	r3, r2, r3
 80176ca:	4a1b      	ldr	r2, [pc, #108]	@ (8017738 <pvPortMalloc+0x18c>)
 80176cc:	6013      	str	r3, [r2, #0]

					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
 80176ce:	4b1a      	ldr	r3, [pc, #104]	@ (8017738 <pvPortMalloc+0x18c>)
 80176d0:	681a      	ldr	r2, [r3, #0]
 80176d2:	4b1b      	ldr	r3, [pc, #108]	@ (8017740 <pvPortMalloc+0x194>)
 80176d4:	681b      	ldr	r3, [r3, #0]
 80176d6:	429a      	cmp	r2, r3
 80176d8:	d203      	bcs.n	80176e2 <pvPortMalloc+0x136>
					{
						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
 80176da:	4b17      	ldr	r3, [pc, #92]	@ (8017738 <pvPortMalloc+0x18c>)
 80176dc:	681b      	ldr	r3, [r3, #0]
 80176de:	4a18      	ldr	r2, [pc, #96]	@ (8017740 <pvPortMalloc+0x194>)
 80176e0:	6013      	str	r3, [r2, #0]
						mtCOVERAGE_TEST_MARKER();
					}

					/* The block is being returned - it is allocated and owned
					by the application and has no "next" block. */
					pxBlock->xBlockSize |= xBlockAllocatedBit;
 80176e2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80176e4:	685a      	ldr	r2, [r3, #4]
 80176e6:	4b13      	ldr	r3, [pc, #76]	@ (8017734 <pvPortMalloc+0x188>)
 80176e8:	681b      	ldr	r3, [r3, #0]
 80176ea:	431a      	orrs	r2, r3
 80176ec:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80176ee:	605a      	str	r2, [r3, #4]
					pxBlock->pxNextFreeBlock = NULL;
 80176f0:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 80176f2:	2200      	movs	r2, #0
 80176f4:	601a      	str	r2, [r3, #0]
					xNumberOfSuccessfulAllocations++;
 80176f6:	4b13      	ldr	r3, [pc, #76]	@ (8017744 <pvPortMalloc+0x198>)
 80176f8:	681b      	ldr	r3, [r3, #0]
 80176fa:	3301      	adds	r3, #1
 80176fc:	4a11      	ldr	r2, [pc, #68]	@ (8017744 <pvPortMalloc+0x198>)
 80176fe:	6013      	str	r3, [r2, #0]
			mtCOVERAGE_TEST_MARKER();
		}

		traceMALLOC( pvReturn, xWantedSize );
	}
	( void ) xTaskResumeAll();
 8017700:	f7fe f882 	bl	8015808 <xTaskResumeAll>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	#endif

	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
 8017704:	69fb      	ldr	r3, [r7, #28]
 8017706:	f003 0307 	and.w	r3, r3, #7
 801770a:	2b00      	cmp	r3, #0
 801770c:	d00b      	beq.n	8017726 <pvPortMalloc+0x17a>
	__asm volatile
 801770e:	f04f 0350 	mov.w	r3, #80	@ 0x50
 8017712:	f383 8811 	msr	BASEPRI, r3
 8017716:	f3bf 8f6f 	isb	sy
 801771a:	f3bf 8f4f 	dsb	sy
 801771e:	60fb      	str	r3, [r7, #12]
}
 8017720:	bf00      	nop
 8017722:	bf00      	nop
 8017724:	e7fd      	b.n	8017722 <pvPortMalloc+0x176>
	return pvReturn;
 8017726:	69fb      	ldr	r3, [r7, #28]
}
 8017728:	4618      	mov	r0, r3
 801772a:	3728      	adds	r7, #40	@ 0x28
 801772c:	46bd      	mov	sp, r7
 801772e:	bd80      	pop	{r7, pc}
 8017730:	24012c7c 	.word	0x24012c7c
 8017734:	24012c90 	.word	0x24012c90
 8017738:	24012c80 	.word	0x24012c80
 801773c:	24012c74 	.word	0x24012c74
 8017740:	24012c84 	.word	0x24012c84
 8017744:	24012c88 	.word	0x24012c88

08017748 <vPortFree>:
/*-----------------------------------------------------------*/

void vPortFree( void *pv )
{
 8017748:	b580      	push	{r7, lr}
 801774a:	b086      	sub	sp, #24
 801774c:	af00      	add	r7, sp, #0
 801774e:	6078      	str	r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
 8017750:	687b      	ldr	r3, [r7, #4]
 8017752:	617b      	str	r3, [r7, #20]
BlockLink_t *pxLink;

	if( pv != NULL )
 8017754:	687b      	ldr	r3, [r7, #4]
 8017756:	2b00      	cmp	r3, #0
 8017758:	d04f      	beq.n	80177fa <vPortFree+0xb2>
	{
		/* The memory being freed will have an BlockLink_t structure immediately
		before it. */
		puc -= xHeapStructSize;
 801775a:	2308      	movs	r3, #8
 801775c:	425b      	negs	r3, r3
 801775e:	697a      	ldr	r2, [r7, #20]
 8017760:	4413      	add	r3, r2
 8017762:	617b      	str	r3, [r7, #20]

		/* This casting is to keep the compiler from issuing warnings. */
		pxLink = ( void * ) puc;
 8017764:	697b      	ldr	r3, [r7, #20]
 8017766:	613b      	str	r3, [r7, #16]

		/* Check the block is actually allocated. */
		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
 8017768:	693b      	ldr	r3, [r7, #16]
 801776a:	685a      	ldr	r2, [r3, #4]
 801776c:	4b25      	ldr	r3, [pc, #148]	@ (8017804 <vPortFree+0xbc>)
 801776e:	681b      	ldr	r3, [r3, #0]
 8017770:	4013      	ands	r3, r2
 8017772:	2b00      	cmp	r3, #0
 8017774:	d10b      	bne.n	801778e <vPortFree+0x46>
	__asm volatile
 8017776:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801777a:	f383 8811 	msr	BASEPRI, r3
 801777e:	f3bf 8f6f 	isb	sy
 8017782:	f3bf 8f4f 	dsb	sy
 8017786:	60fb      	str	r3, [r7, #12]
}
 8017788:	bf00      	nop
 801778a:	bf00      	nop
 801778c:	e7fd      	b.n	801778a <vPortFree+0x42>
		configASSERT( pxLink->pxNextFreeBlock == NULL );
 801778e:	693b      	ldr	r3, [r7, #16]
 8017790:	681b      	ldr	r3, [r3, #0]
 8017792:	2b00      	cmp	r3, #0
 8017794:	d00b      	beq.n	80177ae <vPortFree+0x66>
	__asm volatile
 8017796:	f04f 0350 	mov.w	r3, #80	@ 0x50
 801779a:	f383 8811 	msr	BASEPRI, r3
 801779e:	f3bf 8f6f 	isb	sy
 80177a2:	f3bf 8f4f 	dsb	sy
 80177a6:	60bb      	str	r3, [r7, #8]
}
 80177a8:	bf00      	nop
 80177aa:	bf00      	nop
 80177ac:	e7fd      	b.n	80177aa <vPortFree+0x62>

		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
 80177ae:	693b      	ldr	r3, [r7, #16]
 80177b0:	685a      	ldr	r2, [r3, #4]
 80177b2:	4b14      	ldr	r3, [pc, #80]	@ (8017804 <vPortFree+0xbc>)
 80177b4:	681b      	ldr	r3, [r3, #0]
 80177b6:	4013      	ands	r3, r2
 80177b8:	2b00      	cmp	r3, #0
 80177ba:	d01e      	beq.n	80177fa <vPortFree+0xb2>
		{
			if( pxLink->pxNextFreeBlock == NULL )
 80177bc:	693b      	ldr	r3, [r7, #16]
 80177be:	681b      	ldr	r3, [r3, #0]
 80177c0:	2b00      	cmp	r3, #0
 80177c2:	d11a      	bne.n	80177fa <vPortFree+0xb2>
			{
				/* The block is being returned to the heap - it is no longer
				allocated. */
				pxLink->xBlockSize &= ~xBlockAllocatedBit;
 80177c4:	693b      	ldr	r3, [r7, #16]
 80177c6:	685a      	ldr	r2, [r3, #4]
 80177c8:	4b0e      	ldr	r3, [pc, #56]	@ (8017804 <vPortFree+0xbc>)
 80177ca:	681b      	ldr	r3, [r3, #0]
 80177cc:	43db      	mvns	r3, r3
 80177ce:	401a      	ands	r2, r3
 80177d0:	693b      	ldr	r3, [r7, #16]
 80177d2:	605a      	str	r2, [r3, #4]

				vTaskSuspendAll();
 80177d4:	f7fe f80a 	bl	80157ec <vTaskSuspendAll>
				{
					/* Add this block to the list of free blocks. */
					xFreeBytesRemaining += pxLink->xBlockSize;
 80177d8:	693b      	ldr	r3, [r7, #16]
 80177da:	685a      	ldr	r2, [r3, #4]
 80177dc:	4b0a      	ldr	r3, [pc, #40]	@ (8017808 <vPortFree+0xc0>)
 80177de:	681b      	ldr	r3, [r3, #0]
 80177e0:	4413      	add	r3, r2
 80177e2:	4a09      	ldr	r2, [pc, #36]	@ (8017808 <vPortFree+0xc0>)
 80177e4:	6013      	str	r3, [r2, #0]
					traceFREE( pv, pxLink->xBlockSize );
					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
 80177e6:	6938      	ldr	r0, [r7, #16]
 80177e8:	f000 f874 	bl	80178d4 <prvInsertBlockIntoFreeList>
					xNumberOfSuccessfulFrees++;
 80177ec:	4b07      	ldr	r3, [pc, #28]	@ (801780c <vPortFree+0xc4>)
 80177ee:	681b      	ldr	r3, [r3, #0]
 80177f0:	3301      	adds	r3, #1
 80177f2:	4a06      	ldr	r2, [pc, #24]	@ (801780c <vPortFree+0xc4>)
 80177f4:	6013      	str	r3, [r2, #0]
				}
				( void ) xTaskResumeAll();
 80177f6:	f7fe f807 	bl	8015808 <xTaskResumeAll>
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
}
 80177fa:	bf00      	nop
 80177fc:	3718      	adds	r7, #24
 80177fe:	46bd      	mov	sp, r7
 8017800:	bd80      	pop	{r7, pc}
 8017802:	bf00      	nop
 8017804:	24012c90 	.word	0x24012c90
 8017808:	24012c80 	.word	0x24012c80
 801780c:	24012c8c 	.word	0x24012c8c

08017810 <prvHeapInit>:
	/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/

static void prvHeapInit( void )
{
 8017810:	b480      	push	{r7}
 8017812:	b085      	sub	sp, #20
 8017814:	af00      	add	r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
 8017816:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
 801781a:	60bb      	str	r3, [r7, #8]

	/* Ensure the heap starts on a correctly aligned boundary. */
	uxAddress = ( size_t ) ucHeap;
 801781c:	4b27      	ldr	r3, [pc, #156]	@ (80178bc <prvHeapInit+0xac>)
 801781e:	60fb      	str	r3, [r7, #12]

	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
 8017820:	68fb      	ldr	r3, [r7, #12]
 8017822:	f003 0307 	and.w	r3, r3, #7
 8017826:	2b00      	cmp	r3, #0
 8017828:	d00c      	beq.n	8017844 <prvHeapInit+0x34>
	{
		uxAddress += ( portBYTE_ALIGNMENT - 1 );
 801782a:	68fb      	ldr	r3, [r7, #12]
 801782c:	3307      	adds	r3, #7
 801782e:	60fb      	str	r3, [r7, #12]
		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
 8017830:	68fb      	ldr	r3, [r7, #12]
 8017832:	f023 0307 	bic.w	r3, r3, #7
 8017836:	60fb      	str	r3, [r7, #12]
		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
 8017838:	68ba      	ldr	r2, [r7, #8]
 801783a:	68fb      	ldr	r3, [r7, #12]
 801783c:	1ad3      	subs	r3, r2, r3
 801783e:	4a1f      	ldr	r2, [pc, #124]	@ (80178bc <prvHeapInit+0xac>)
 8017840:	4413      	add	r3, r2
 8017842:	60bb      	str	r3, [r7, #8]
	}

	pucAlignedHeap = ( uint8_t * ) uxAddress;
 8017844:	68fb      	ldr	r3, [r7, #12]
 8017846:	607b      	str	r3, [r7, #4]

	/* xStart is used to hold a pointer to the first item in the list of free
	blocks.  The void cast is used to prevent compiler warnings. */
	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
 8017848:	4a1d      	ldr	r2, [pc, #116]	@ (80178c0 <prvHeapInit+0xb0>)
 801784a:	687b      	ldr	r3, [r7, #4]
 801784c:	6013      	str	r3, [r2, #0]
	xStart.xBlockSize = ( size_t ) 0;
 801784e:	4b1c      	ldr	r3, [pc, #112]	@ (80178c0 <prvHeapInit+0xb0>)
 8017850:	2200      	movs	r2, #0
 8017852:	605a      	str	r2, [r3, #4]

	/* pxEnd is used to mark the end of the list of free blocks and is inserted
	at the end of the heap space. */
	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
 8017854:	687b      	ldr	r3, [r7, #4]
 8017856:	68ba      	ldr	r2, [r7, #8]
 8017858:	4413      	add	r3, r2
 801785a:	60fb      	str	r3, [r7, #12]
	uxAddress -= xHeapStructSize;
 801785c:	2208      	movs	r2, #8
 801785e:	68fb      	ldr	r3, [r7, #12]
 8017860:	1a9b      	subs	r3, r3, r2
 8017862:	60fb      	str	r3, [r7, #12]
	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
 8017864:	68fb      	ldr	r3, [r7, #12]
 8017866:	f023 0307 	bic.w	r3, r3, #7
 801786a:	60fb      	str	r3, [r7, #12]
	pxEnd = ( void * ) uxAddress;
 801786c:	68fb      	ldr	r3, [r7, #12]
 801786e:	4a15      	ldr	r2, [pc, #84]	@ (80178c4 <prvHeapInit+0xb4>)
 8017870:	6013      	str	r3, [r2, #0]
	pxEnd->xBlockSize = 0;
 8017872:	4b14      	ldr	r3, [pc, #80]	@ (80178c4 <prvHeapInit+0xb4>)
 8017874:	681b      	ldr	r3, [r3, #0]
 8017876:	2200      	movs	r2, #0
 8017878:	605a      	str	r2, [r3, #4]
	pxEnd->pxNextFreeBlock = NULL;
 801787a:	4b12      	ldr	r3, [pc, #72]	@ (80178c4 <prvHeapInit+0xb4>)
 801787c:	681b      	ldr	r3, [r3, #0]
 801787e:	2200      	movs	r2, #0
 8017880:	601a      	str	r2, [r3, #0]

	/* To start with there is a single free block that is sized to take up the
	entire heap space, minus the space taken by pxEnd. */
	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
 8017882:	687b      	ldr	r3, [r7, #4]
 8017884:	603b      	str	r3, [r7, #0]
	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
 8017886:	683b      	ldr	r3, [r7, #0]
 8017888:	68fa      	ldr	r2, [r7, #12]
 801788a:	1ad2      	subs	r2, r2, r3
 801788c:	683b      	ldr	r3, [r7, #0]
 801788e:	605a      	str	r2, [r3, #4]
	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
 8017890:	4b0c      	ldr	r3, [pc, #48]	@ (80178c4 <prvHeapInit+0xb4>)
 8017892:	681a      	ldr	r2, [r3, #0]
 8017894:	683b      	ldr	r3, [r7, #0]
 8017896:	601a      	str	r2, [r3, #0]

	/* Only one block exists - and it covers the entire usable heap space. */
	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
 8017898:	683b      	ldr	r3, [r7, #0]
 801789a:	685b      	ldr	r3, [r3, #4]
 801789c:	4a0a      	ldr	r2, [pc, #40]	@ (80178c8 <prvHeapInit+0xb8>)
 801789e:	6013      	str	r3, [r2, #0]
	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
 80178a0:	683b      	ldr	r3, [r7, #0]
 80178a2:	685b      	ldr	r3, [r3, #4]
 80178a4:	4a09      	ldr	r2, [pc, #36]	@ (80178cc <prvHeapInit+0xbc>)
 80178a6:	6013      	str	r3, [r2, #0]

	/* Work out the position of the top bit in a size_t variable. */
	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
 80178a8:	4b09      	ldr	r3, [pc, #36]	@ (80178d0 <prvHeapInit+0xc0>)
 80178aa:	f04f 4200 	mov.w	r2, #2147483648	@ 0x80000000
 80178ae:	601a      	str	r2, [r3, #0]
}
 80178b0:	bf00      	nop
 80178b2:	3714      	adds	r7, #20
 80178b4:	46bd      	mov	sp, r7
 80178b6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80178ba:	4770      	bx	lr
 80178bc:	24002c74 	.word	0x24002c74
 80178c0:	24012c74 	.word	0x24012c74
 80178c4:	24012c7c 	.word	0x24012c7c
 80178c8:	24012c84 	.word	0x24012c84
 80178cc:	24012c80 	.word	0x24012c80
 80178d0:	24012c90 	.word	0x24012c90

080178d4 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/

static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
 80178d4:	b480      	push	{r7}
 80178d6:	b085      	sub	sp, #20
 80178d8:	af00      	add	r7, sp, #0
 80178da:	6078      	str	r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;

	/* Iterate through the list until a block is found that has a higher address
	than the block being inserted. */
	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
 80178dc:	4b28      	ldr	r3, [pc, #160]	@ (8017980 <prvInsertBlockIntoFreeList+0xac>)
 80178de:	60fb      	str	r3, [r7, #12]
 80178e0:	e002      	b.n	80178e8 <prvInsertBlockIntoFreeList+0x14>
 80178e2:	68fb      	ldr	r3, [r7, #12]
 80178e4:	681b      	ldr	r3, [r3, #0]
 80178e6:	60fb      	str	r3, [r7, #12]
 80178e8:	68fb      	ldr	r3, [r7, #12]
 80178ea:	681b      	ldr	r3, [r3, #0]
 80178ec:	687a      	ldr	r2, [r7, #4]
 80178ee:	429a      	cmp	r2, r3
 80178f0:	d8f7      	bhi.n	80178e2 <prvInsertBlockIntoFreeList+0xe>
		/* Nothing to do here, just iterate to the right position. */
	}

	/* Do the block being inserted, and the block it is being inserted after
	make a contiguous block of memory? */
	puc = ( uint8_t * ) pxIterator;
 80178f2:	68fb      	ldr	r3, [r7, #12]
 80178f4:	60bb      	str	r3, [r7, #8]
	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
 80178f6:	68fb      	ldr	r3, [r7, #12]
 80178f8:	685b      	ldr	r3, [r3, #4]
 80178fa:	68ba      	ldr	r2, [r7, #8]
 80178fc:	4413      	add	r3, r2
 80178fe:	687a      	ldr	r2, [r7, #4]
 8017900:	429a      	cmp	r2, r3
 8017902:	d108      	bne.n	8017916 <prvInsertBlockIntoFreeList+0x42>
	{
		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
 8017904:	68fb      	ldr	r3, [r7, #12]
 8017906:	685a      	ldr	r2, [r3, #4]
 8017908:	687b      	ldr	r3, [r7, #4]
 801790a:	685b      	ldr	r3, [r3, #4]
 801790c:	441a      	add	r2, r3
 801790e:	68fb      	ldr	r3, [r7, #12]
 8017910:	605a      	str	r2, [r3, #4]
		pxBlockToInsert = pxIterator;
 8017912:	68fb      	ldr	r3, [r7, #12]
 8017914:	607b      	str	r3, [r7, #4]
		mtCOVERAGE_TEST_MARKER();
	}

	/* Do the block being inserted, and the block it is being inserted before
	make a contiguous block of memory? */
	puc = ( uint8_t * ) pxBlockToInsert;
 8017916:	687b      	ldr	r3, [r7, #4]
 8017918:	60bb      	str	r3, [r7, #8]
	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
 801791a:	687b      	ldr	r3, [r7, #4]
 801791c:	685b      	ldr	r3, [r3, #4]
 801791e:	68ba      	ldr	r2, [r7, #8]
 8017920:	441a      	add	r2, r3
 8017922:	68fb      	ldr	r3, [r7, #12]
 8017924:	681b      	ldr	r3, [r3, #0]
 8017926:	429a      	cmp	r2, r3
 8017928:	d118      	bne.n	801795c <prvInsertBlockIntoFreeList+0x88>
	{
		if( pxIterator->pxNextFreeBlock != pxEnd )
 801792a:	68fb      	ldr	r3, [r7, #12]
 801792c:	681a      	ldr	r2, [r3, #0]
 801792e:	4b15      	ldr	r3, [pc, #84]	@ (8017984 <prvInsertBlockIntoFreeList+0xb0>)
 8017930:	681b      	ldr	r3, [r3, #0]
 8017932:	429a      	cmp	r2, r3
 8017934:	d00d      	beq.n	8017952 <prvInsertBlockIntoFreeList+0x7e>
		{
			/* Form one big block from the two blocks. */
			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
 8017936:	687b      	ldr	r3, [r7, #4]
 8017938:	685a      	ldr	r2, [r3, #4]
 801793a:	68fb      	ldr	r3, [r7, #12]
 801793c:	681b      	ldr	r3, [r3, #0]
 801793e:	685b      	ldr	r3, [r3, #4]
 8017940:	441a      	add	r2, r3
 8017942:	687b      	ldr	r3, [r7, #4]
 8017944:	605a      	str	r2, [r3, #4]
			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
 8017946:	68fb      	ldr	r3, [r7, #12]
 8017948:	681b      	ldr	r3, [r3, #0]
 801794a:	681a      	ldr	r2, [r3, #0]
 801794c:	687b      	ldr	r3, [r7, #4]
 801794e:	601a      	str	r2, [r3, #0]
 8017950:	e008      	b.n	8017964 <prvInsertBlockIntoFreeList+0x90>
		}
		else
		{
			pxBlockToInsert->pxNextFreeBlock = pxEnd;
 8017952:	4b0c      	ldr	r3, [pc, #48]	@ (8017984 <prvInsertBlockIntoFreeList+0xb0>)
 8017954:	681a      	ldr	r2, [r3, #0]
 8017956:	687b      	ldr	r3, [r7, #4]
 8017958:	601a      	str	r2, [r3, #0]
 801795a:	e003      	b.n	8017964 <prvInsertBlockIntoFreeList+0x90>
		}
	}
	else
	{
		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
 801795c:	68fb      	ldr	r3, [r7, #12]
 801795e:	681a      	ldr	r2, [r3, #0]
 8017960:	687b      	ldr	r3, [r7, #4]
 8017962:	601a      	str	r2, [r3, #0]

	/* If the block being inserted plugged a gab, so was merged with the block
	before and the block after, then it's pxNextFreeBlock pointer will have
	already been set, and should not be set here as that would make it point
	to itself. */
	if( pxIterator != pxBlockToInsert )
 8017964:	68fa      	ldr	r2, [r7, #12]
 8017966:	687b      	ldr	r3, [r7, #4]
 8017968:	429a      	cmp	r2, r3
 801796a:	d002      	beq.n	8017972 <prvInsertBlockIntoFreeList+0x9e>
	{
		pxIterator->pxNextFreeBlock = pxBlockToInsert;
 801796c:	68fb      	ldr	r3, [r7, #12]
 801796e:	687a      	ldr	r2, [r7, #4]
 8017970:	601a      	str	r2, [r3, #0]
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 8017972:	bf00      	nop
 8017974:	3714      	adds	r7, #20
 8017976:	46bd      	mov	sp, r7
 8017978:	f85d 7b04 	ldr.w	r7, [sp], #4
 801797c:	4770      	bx	lr
 801797e:	bf00      	nop
 8017980:	24012c74 	.word	0x24012c74
 8017984:	24012c7c 	.word	0x24012c7c

08017988 <std>:
 8017988:	2300      	movs	r3, #0
 801798a:	b510      	push	{r4, lr}
 801798c:	4604      	mov	r4, r0
 801798e:	e9c0 3300 	strd	r3, r3, [r0]
 8017992:	e9c0 3304 	strd	r3, r3, [r0, #16]
 8017996:	6083      	str	r3, [r0, #8]
 8017998:	8181      	strh	r1, [r0, #12]
 801799a:	6643      	str	r3, [r0, #100]	@ 0x64
 801799c:	81c2      	strh	r2, [r0, #14]
 801799e:	6183      	str	r3, [r0, #24]
 80179a0:	4619      	mov	r1, r3
 80179a2:	2208      	movs	r2, #8
 80179a4:	305c      	adds	r0, #92	@ 0x5c
 80179a6:	f000 f906 	bl	8017bb6 <memset>
 80179aa:	4b0d      	ldr	r3, [pc, #52]	@ (80179e0 <std+0x58>)
 80179ac:	6263      	str	r3, [r4, #36]	@ 0x24
 80179ae:	4b0d      	ldr	r3, [pc, #52]	@ (80179e4 <std+0x5c>)
 80179b0:	62a3      	str	r3, [r4, #40]	@ 0x28
 80179b2:	4b0d      	ldr	r3, [pc, #52]	@ (80179e8 <std+0x60>)
 80179b4:	62e3      	str	r3, [r4, #44]	@ 0x2c
 80179b6:	4b0d      	ldr	r3, [pc, #52]	@ (80179ec <std+0x64>)
 80179b8:	6323      	str	r3, [r4, #48]	@ 0x30
 80179ba:	4b0d      	ldr	r3, [pc, #52]	@ (80179f0 <std+0x68>)
 80179bc:	6224      	str	r4, [r4, #32]
 80179be:	429c      	cmp	r4, r3
 80179c0:	d006      	beq.n	80179d0 <std+0x48>
 80179c2:	f103 0268 	add.w	r2, r3, #104	@ 0x68
 80179c6:	4294      	cmp	r4, r2
 80179c8:	d002      	beq.n	80179d0 <std+0x48>
 80179ca:	33d0      	adds	r3, #208	@ 0xd0
 80179cc:	429c      	cmp	r4, r3
 80179ce:	d105      	bne.n	80179dc <std+0x54>
 80179d0:	f104 0058 	add.w	r0, r4, #88	@ 0x58
 80179d4:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 80179d8:	f000 b9bc 	b.w	8017d54 <__retarget_lock_init_recursive>
 80179dc:	bd10      	pop	{r4, pc}
 80179de:	bf00      	nop
 80179e0:	08017b31 	.word	0x08017b31
 80179e4:	08017b53 	.word	0x08017b53
 80179e8:	08017b8b 	.word	0x08017b8b
 80179ec:	08017baf 	.word	0x08017baf
 80179f0:	24012c94 	.word	0x24012c94

080179f4 <stdio_exit_handler>:
 80179f4:	4a02      	ldr	r2, [pc, #8]	@ (8017a00 <stdio_exit_handler+0xc>)
 80179f6:	4903      	ldr	r1, [pc, #12]	@ (8017a04 <stdio_exit_handler+0x10>)
 80179f8:	4803      	ldr	r0, [pc, #12]	@ (8017a08 <stdio_exit_handler+0x14>)
 80179fa:	f000 b869 	b.w	8017ad0 <_fwalk_sglue>
 80179fe:	bf00      	nop
 8017a00:	24000048 	.word	0x24000048
 8017a04:	08018611 	.word	0x08018611
 8017a08:	24000058 	.word	0x24000058

08017a0c <cleanup_stdio>:
 8017a0c:	6841      	ldr	r1, [r0, #4]
 8017a0e:	4b0c      	ldr	r3, [pc, #48]	@ (8017a40 <cleanup_stdio+0x34>)
 8017a10:	4299      	cmp	r1, r3
 8017a12:	b510      	push	{r4, lr}
 8017a14:	4604      	mov	r4, r0
 8017a16:	d001      	beq.n	8017a1c <cleanup_stdio+0x10>
 8017a18:	f000 fdfa 	bl	8018610 <_fflush_r>
 8017a1c:	68a1      	ldr	r1, [r4, #8]
 8017a1e:	4b09      	ldr	r3, [pc, #36]	@ (8017a44 <cleanup_stdio+0x38>)
 8017a20:	4299      	cmp	r1, r3
 8017a22:	d002      	beq.n	8017a2a <cleanup_stdio+0x1e>
 8017a24:	4620      	mov	r0, r4
 8017a26:	f000 fdf3 	bl	8018610 <_fflush_r>
 8017a2a:	68e1      	ldr	r1, [r4, #12]
 8017a2c:	4b06      	ldr	r3, [pc, #24]	@ (8017a48 <cleanup_stdio+0x3c>)
 8017a2e:	4299      	cmp	r1, r3
 8017a30:	d004      	beq.n	8017a3c <cleanup_stdio+0x30>
 8017a32:	4620      	mov	r0, r4
 8017a34:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 8017a38:	f000 bdea 	b.w	8018610 <_fflush_r>
 8017a3c:	bd10      	pop	{r4, pc}
 8017a3e:	bf00      	nop
 8017a40:	24012c94 	.word	0x24012c94
 8017a44:	24012cfc 	.word	0x24012cfc
 8017a48:	24012d64 	.word	0x24012d64

08017a4c <global_stdio_init.part.0>:
 8017a4c:	b510      	push	{r4, lr}
 8017a4e:	4b0b      	ldr	r3, [pc, #44]	@ (8017a7c <global_stdio_init.part.0+0x30>)
 8017a50:	4c0b      	ldr	r4, [pc, #44]	@ (8017a80 <global_stdio_init.part.0+0x34>)
 8017a52:	4a0c      	ldr	r2, [pc, #48]	@ (8017a84 <global_stdio_init.part.0+0x38>)
 8017a54:	601a      	str	r2, [r3, #0]
 8017a56:	4620      	mov	r0, r4
 8017a58:	2200      	movs	r2, #0
 8017a5a:	2104      	movs	r1, #4
 8017a5c:	f7ff ff94 	bl	8017988 <std>
 8017a60:	f104 0068 	add.w	r0, r4, #104	@ 0x68
 8017a64:	2201      	movs	r2, #1
 8017a66:	2109      	movs	r1, #9
 8017a68:	f7ff ff8e 	bl	8017988 <std>
 8017a6c:	f104 00d0 	add.w	r0, r4, #208	@ 0xd0
 8017a70:	2202      	movs	r2, #2
 8017a72:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 8017a76:	2112      	movs	r1, #18
 8017a78:	f7ff bf86 	b.w	8017988 <std>
 8017a7c:	24012dcc 	.word	0x24012dcc
 8017a80:	24012c94 	.word	0x24012c94
 8017a84:	080179f5 	.word	0x080179f5

08017a88 <__sfp_lock_acquire>:
 8017a88:	4801      	ldr	r0, [pc, #4]	@ (8017a90 <__sfp_lock_acquire+0x8>)
 8017a8a:	f000 b964 	b.w	8017d56 <__retarget_lock_acquire_recursive>
 8017a8e:	bf00      	nop
 8017a90:	24012dd5 	.word	0x24012dd5

08017a94 <__sfp_lock_release>:
 8017a94:	4801      	ldr	r0, [pc, #4]	@ (8017a9c <__sfp_lock_release+0x8>)
 8017a96:	f000 b95f 	b.w	8017d58 <__retarget_lock_release_recursive>
 8017a9a:	bf00      	nop
 8017a9c:	24012dd5 	.word	0x24012dd5

08017aa0 <__sinit>:
 8017aa0:	b510      	push	{r4, lr}
 8017aa2:	4604      	mov	r4, r0
 8017aa4:	f7ff fff0 	bl	8017a88 <__sfp_lock_acquire>
 8017aa8:	6a23      	ldr	r3, [r4, #32]
 8017aaa:	b11b      	cbz	r3, 8017ab4 <__sinit+0x14>
 8017aac:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 8017ab0:	f7ff bff0 	b.w	8017a94 <__sfp_lock_release>
 8017ab4:	4b04      	ldr	r3, [pc, #16]	@ (8017ac8 <__sinit+0x28>)
 8017ab6:	6223      	str	r3, [r4, #32]
 8017ab8:	4b04      	ldr	r3, [pc, #16]	@ (8017acc <__sinit+0x2c>)
 8017aba:	681b      	ldr	r3, [r3, #0]
 8017abc:	2b00      	cmp	r3, #0
 8017abe:	d1f5      	bne.n	8017aac <__sinit+0xc>
 8017ac0:	f7ff ffc4 	bl	8017a4c <global_stdio_init.part.0>
 8017ac4:	e7f2      	b.n	8017aac <__sinit+0xc>
 8017ac6:	bf00      	nop
 8017ac8:	08017a0d 	.word	0x08017a0d
 8017acc:	24012dcc 	.word	0x24012dcc

08017ad0 <_fwalk_sglue>:
 8017ad0:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8017ad4:	4607      	mov	r7, r0
 8017ad6:	4688      	mov	r8, r1
 8017ad8:	4614      	mov	r4, r2
 8017ada:	2600      	movs	r6, #0
 8017adc:	e9d4 9501 	ldrd	r9, r5, [r4, #4]
 8017ae0:	f1b9 0901 	subs.w	r9, r9, #1
 8017ae4:	d505      	bpl.n	8017af2 <_fwalk_sglue+0x22>
 8017ae6:	6824      	ldr	r4, [r4, #0]
 8017ae8:	2c00      	cmp	r4, #0
 8017aea:	d1f7      	bne.n	8017adc <_fwalk_sglue+0xc>
 8017aec:	4630      	mov	r0, r6
 8017aee:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 8017af2:	89ab      	ldrh	r3, [r5, #12]
 8017af4:	2b01      	cmp	r3, #1
 8017af6:	d907      	bls.n	8017b08 <_fwalk_sglue+0x38>
 8017af8:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
 8017afc:	3301      	adds	r3, #1
 8017afe:	d003      	beq.n	8017b08 <_fwalk_sglue+0x38>
 8017b00:	4629      	mov	r1, r5
 8017b02:	4638      	mov	r0, r7
 8017b04:	47c0      	blx	r8
 8017b06:	4306      	orrs	r6, r0
 8017b08:	3568      	adds	r5, #104	@ 0x68
 8017b0a:	e7e9      	b.n	8017ae0 <_fwalk_sglue+0x10>

08017b0c <iprintf>:
 8017b0c:	b40f      	push	{r0, r1, r2, r3}
 8017b0e:	b507      	push	{r0, r1, r2, lr}
 8017b10:	4906      	ldr	r1, [pc, #24]	@ (8017b2c <iprintf+0x20>)
 8017b12:	ab04      	add	r3, sp, #16
 8017b14:	6808      	ldr	r0, [r1, #0]
 8017b16:	f853 2b04 	ldr.w	r2, [r3], #4
 8017b1a:	6881      	ldr	r1, [r0, #8]
 8017b1c:	9301      	str	r3, [sp, #4]
 8017b1e:	f000 fa4d 	bl	8017fbc <_vfiprintf_r>
 8017b22:	b003      	add	sp, #12
 8017b24:	f85d eb04 	ldr.w	lr, [sp], #4
 8017b28:	b004      	add	sp, #16
 8017b2a:	4770      	bx	lr
 8017b2c:	24000054 	.word	0x24000054

08017b30 <__sread>:
 8017b30:	b510      	push	{r4, lr}
 8017b32:	460c      	mov	r4, r1
 8017b34:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8017b38:	f000 f8be 	bl	8017cb8 <_read_r>
 8017b3c:	2800      	cmp	r0, #0
 8017b3e:	bfab      	itete	ge
 8017b40:	6d63      	ldrge	r3, [r4, #84]	@ 0x54
 8017b42:	89a3      	ldrhlt	r3, [r4, #12]
 8017b44:	181b      	addge	r3, r3, r0
 8017b46:	f423 5380 	biclt.w	r3, r3, #4096	@ 0x1000
 8017b4a:	bfac      	ite	ge
 8017b4c:	6563      	strge	r3, [r4, #84]	@ 0x54
 8017b4e:	81a3      	strhlt	r3, [r4, #12]
 8017b50:	bd10      	pop	{r4, pc}

08017b52 <__swrite>:
 8017b52:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8017b56:	461f      	mov	r7, r3
 8017b58:	898b      	ldrh	r3, [r1, #12]
 8017b5a:	05db      	lsls	r3, r3, #23
 8017b5c:	4605      	mov	r5, r0
 8017b5e:	460c      	mov	r4, r1
 8017b60:	4616      	mov	r6, r2
 8017b62:	d505      	bpl.n	8017b70 <__swrite+0x1e>
 8017b64:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8017b68:	2302      	movs	r3, #2
 8017b6a:	2200      	movs	r2, #0
 8017b6c:	f000 f892 	bl	8017c94 <_lseek_r>
 8017b70:	89a3      	ldrh	r3, [r4, #12]
 8017b72:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 8017b76:	f423 5380 	bic.w	r3, r3, #4096	@ 0x1000
 8017b7a:	81a3      	strh	r3, [r4, #12]
 8017b7c:	4632      	mov	r2, r6
 8017b7e:	463b      	mov	r3, r7
 8017b80:	4628      	mov	r0, r5
 8017b82:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
 8017b86:	f000 b8a9 	b.w	8017cdc <_write_r>

08017b8a <__sseek>:
 8017b8a:	b510      	push	{r4, lr}
 8017b8c:	460c      	mov	r4, r1
 8017b8e:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8017b92:	f000 f87f 	bl	8017c94 <_lseek_r>
 8017b96:	1c43      	adds	r3, r0, #1
 8017b98:	89a3      	ldrh	r3, [r4, #12]
 8017b9a:	bf15      	itete	ne
 8017b9c:	6560      	strne	r0, [r4, #84]	@ 0x54
 8017b9e:	f423 5380 	biceq.w	r3, r3, #4096	@ 0x1000
 8017ba2:	f443 5380 	orrne.w	r3, r3, #4096	@ 0x1000
 8017ba6:	81a3      	strheq	r3, [r4, #12]
 8017ba8:	bf18      	it	ne
 8017baa:	81a3      	strhne	r3, [r4, #12]
 8017bac:	bd10      	pop	{r4, pc}

08017bae <__sclose>:
 8017bae:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8017bb2:	f000 b809 	b.w	8017bc8 <_close_r>

08017bb6 <memset>:
 8017bb6:	4402      	add	r2, r0
 8017bb8:	4603      	mov	r3, r0
 8017bba:	4293      	cmp	r3, r2
 8017bbc:	d100      	bne.n	8017bc0 <memset+0xa>
 8017bbe:	4770      	bx	lr
 8017bc0:	f803 1b01 	strb.w	r1, [r3], #1
 8017bc4:	e7f9      	b.n	8017bba <memset+0x4>
	...

08017bc8 <_close_r>:
 8017bc8:	b538      	push	{r3, r4, r5, lr}
 8017bca:	4d06      	ldr	r5, [pc, #24]	@ (8017be4 <_close_r+0x1c>)
 8017bcc:	2300      	movs	r3, #0
 8017bce:	4604      	mov	r4, r0
 8017bd0:	4608      	mov	r0, r1
 8017bd2:	602b      	str	r3, [r5, #0]
 8017bd4:	f7ec fa2f 	bl	8004036 <_close>
 8017bd8:	1c43      	adds	r3, r0, #1
 8017bda:	d102      	bne.n	8017be2 <_close_r+0x1a>
 8017bdc:	682b      	ldr	r3, [r5, #0]
 8017bde:	b103      	cbz	r3, 8017be2 <_close_r+0x1a>
 8017be0:	6023      	str	r3, [r4, #0]
 8017be2:	bd38      	pop	{r3, r4, r5, pc}
 8017be4:	24012dd0 	.word	0x24012dd0

08017be8 <_reclaim_reent>:
 8017be8:	4b29      	ldr	r3, [pc, #164]	@ (8017c90 <_reclaim_reent+0xa8>)
 8017bea:	681b      	ldr	r3, [r3, #0]
 8017bec:	4283      	cmp	r3, r0
 8017bee:	b570      	push	{r4, r5, r6, lr}
 8017bf0:	4604      	mov	r4, r0
 8017bf2:	d04b      	beq.n	8017c8c <_reclaim_reent+0xa4>
 8017bf4:	69c3      	ldr	r3, [r0, #28]
 8017bf6:	b1ab      	cbz	r3, 8017c24 <_reclaim_reent+0x3c>
 8017bf8:	68db      	ldr	r3, [r3, #12]
 8017bfa:	b16b      	cbz	r3, 8017c18 <_reclaim_reent+0x30>
 8017bfc:	2500      	movs	r5, #0
 8017bfe:	69e3      	ldr	r3, [r4, #28]
 8017c00:	68db      	ldr	r3, [r3, #12]
 8017c02:	5959      	ldr	r1, [r3, r5]
 8017c04:	2900      	cmp	r1, #0
 8017c06:	d13b      	bne.n	8017c80 <_reclaim_reent+0x98>
 8017c08:	3504      	adds	r5, #4
 8017c0a:	2d80      	cmp	r5, #128	@ 0x80
 8017c0c:	d1f7      	bne.n	8017bfe <_reclaim_reent+0x16>
 8017c0e:	69e3      	ldr	r3, [r4, #28]
 8017c10:	4620      	mov	r0, r4
 8017c12:	68d9      	ldr	r1, [r3, #12]
 8017c14:	f000 f8b0 	bl	8017d78 <_free_r>
 8017c18:	69e3      	ldr	r3, [r4, #28]
 8017c1a:	6819      	ldr	r1, [r3, #0]
 8017c1c:	b111      	cbz	r1, 8017c24 <_reclaim_reent+0x3c>
 8017c1e:	4620      	mov	r0, r4
 8017c20:	f000 f8aa 	bl	8017d78 <_free_r>
 8017c24:	6961      	ldr	r1, [r4, #20]
 8017c26:	b111      	cbz	r1, 8017c2e <_reclaim_reent+0x46>
 8017c28:	4620      	mov	r0, r4
 8017c2a:	f000 f8a5 	bl	8017d78 <_free_r>
 8017c2e:	69e1      	ldr	r1, [r4, #28]
 8017c30:	b111      	cbz	r1, 8017c38 <_reclaim_reent+0x50>
 8017c32:	4620      	mov	r0, r4
 8017c34:	f000 f8a0 	bl	8017d78 <_free_r>
 8017c38:	6b21      	ldr	r1, [r4, #48]	@ 0x30
 8017c3a:	b111      	cbz	r1, 8017c42 <_reclaim_reent+0x5a>
 8017c3c:	4620      	mov	r0, r4
 8017c3e:	f000 f89b 	bl	8017d78 <_free_r>
 8017c42:	6b61      	ldr	r1, [r4, #52]	@ 0x34
 8017c44:	b111      	cbz	r1, 8017c4c <_reclaim_reent+0x64>
 8017c46:	4620      	mov	r0, r4
 8017c48:	f000 f896 	bl	8017d78 <_free_r>
 8017c4c:	6ba1      	ldr	r1, [r4, #56]	@ 0x38
 8017c4e:	b111      	cbz	r1, 8017c56 <_reclaim_reent+0x6e>
 8017c50:	4620      	mov	r0, r4
 8017c52:	f000 f891 	bl	8017d78 <_free_r>
 8017c56:	6ca1      	ldr	r1, [r4, #72]	@ 0x48
 8017c58:	b111      	cbz	r1, 8017c60 <_reclaim_reent+0x78>
 8017c5a:	4620      	mov	r0, r4
 8017c5c:	f000 f88c 	bl	8017d78 <_free_r>
 8017c60:	6c61      	ldr	r1, [r4, #68]	@ 0x44
 8017c62:	b111      	cbz	r1, 8017c6a <_reclaim_reent+0x82>
 8017c64:	4620      	mov	r0, r4
 8017c66:	f000 f887 	bl	8017d78 <_free_r>
 8017c6a:	6ae1      	ldr	r1, [r4, #44]	@ 0x2c
 8017c6c:	b111      	cbz	r1, 8017c74 <_reclaim_reent+0x8c>
 8017c6e:	4620      	mov	r0, r4
 8017c70:	f000 f882 	bl	8017d78 <_free_r>
 8017c74:	6a23      	ldr	r3, [r4, #32]
 8017c76:	b14b      	cbz	r3, 8017c8c <_reclaim_reent+0xa4>
 8017c78:	4620      	mov	r0, r4
 8017c7a:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
 8017c7e:	4718      	bx	r3
 8017c80:	680e      	ldr	r6, [r1, #0]
 8017c82:	4620      	mov	r0, r4
 8017c84:	f000 f878 	bl	8017d78 <_free_r>
 8017c88:	4631      	mov	r1, r6
 8017c8a:	e7bb      	b.n	8017c04 <_reclaim_reent+0x1c>
 8017c8c:	bd70      	pop	{r4, r5, r6, pc}
 8017c8e:	bf00      	nop
 8017c90:	24000054 	.word	0x24000054

08017c94 <_lseek_r>:
 8017c94:	b538      	push	{r3, r4, r5, lr}
 8017c96:	4d07      	ldr	r5, [pc, #28]	@ (8017cb4 <_lseek_r+0x20>)
 8017c98:	4604      	mov	r4, r0
 8017c9a:	4608      	mov	r0, r1
 8017c9c:	4611      	mov	r1, r2
 8017c9e:	2200      	movs	r2, #0
 8017ca0:	602a      	str	r2, [r5, #0]
 8017ca2:	461a      	mov	r2, r3
 8017ca4:	f7ec f9ee 	bl	8004084 <_lseek>
 8017ca8:	1c43      	adds	r3, r0, #1
 8017caa:	d102      	bne.n	8017cb2 <_lseek_r+0x1e>
 8017cac:	682b      	ldr	r3, [r5, #0]
 8017cae:	b103      	cbz	r3, 8017cb2 <_lseek_r+0x1e>
 8017cb0:	6023      	str	r3, [r4, #0]
 8017cb2:	bd38      	pop	{r3, r4, r5, pc}
 8017cb4:	24012dd0 	.word	0x24012dd0

08017cb8 <_read_r>:
 8017cb8:	b538      	push	{r3, r4, r5, lr}
 8017cba:	4d07      	ldr	r5, [pc, #28]	@ (8017cd8 <_read_r+0x20>)
 8017cbc:	4604      	mov	r4, r0
 8017cbe:	4608      	mov	r0, r1
 8017cc0:	4611      	mov	r1, r2
 8017cc2:	2200      	movs	r2, #0
 8017cc4:	602a      	str	r2, [r5, #0]
 8017cc6:	461a      	mov	r2, r3
 8017cc8:	f7ec f97c 	bl	8003fc4 <_read>
 8017ccc:	1c43      	adds	r3, r0, #1
 8017cce:	d102      	bne.n	8017cd6 <_read_r+0x1e>
 8017cd0:	682b      	ldr	r3, [r5, #0]
 8017cd2:	b103      	cbz	r3, 8017cd6 <_read_r+0x1e>
 8017cd4:	6023      	str	r3, [r4, #0]
 8017cd6:	bd38      	pop	{r3, r4, r5, pc}
 8017cd8:	24012dd0 	.word	0x24012dd0

08017cdc <_write_r>:
 8017cdc:	b538      	push	{r3, r4, r5, lr}
 8017cde:	4d07      	ldr	r5, [pc, #28]	@ (8017cfc <_write_r+0x20>)
 8017ce0:	4604      	mov	r4, r0
 8017ce2:	4608      	mov	r0, r1
 8017ce4:	4611      	mov	r1, r2
 8017ce6:	2200      	movs	r2, #0
 8017ce8:	602a      	str	r2, [r5, #0]
 8017cea:	461a      	mov	r2, r3
 8017cec:	f7ec f987 	bl	8003ffe <_write>
 8017cf0:	1c43      	adds	r3, r0, #1
 8017cf2:	d102      	bne.n	8017cfa <_write_r+0x1e>
 8017cf4:	682b      	ldr	r3, [r5, #0]
 8017cf6:	b103      	cbz	r3, 8017cfa <_write_r+0x1e>
 8017cf8:	6023      	str	r3, [r4, #0]
 8017cfa:	bd38      	pop	{r3, r4, r5, pc}
 8017cfc:	24012dd0 	.word	0x24012dd0

08017d00 <__errno>:
 8017d00:	4b01      	ldr	r3, [pc, #4]	@ (8017d08 <__errno+0x8>)
 8017d02:	6818      	ldr	r0, [r3, #0]
 8017d04:	4770      	bx	lr
 8017d06:	bf00      	nop
 8017d08:	24000054 	.word	0x24000054

08017d0c <__libc_init_array>:
 8017d0c:	b570      	push	{r4, r5, r6, lr}
 8017d0e:	4d0d      	ldr	r5, [pc, #52]	@ (8017d44 <__libc_init_array+0x38>)
 8017d10:	4c0d      	ldr	r4, [pc, #52]	@ (8017d48 <__libc_init_array+0x3c>)
 8017d12:	1b64      	subs	r4, r4, r5
 8017d14:	10a4      	asrs	r4, r4, #2
 8017d16:	2600      	movs	r6, #0
 8017d18:	42a6      	cmp	r6, r4
 8017d1a:	d109      	bne.n	8017d30 <__libc_init_array+0x24>
 8017d1c:	4d0b      	ldr	r5, [pc, #44]	@ (8017d4c <__libc_init_array+0x40>)
 8017d1e:	4c0c      	ldr	r4, [pc, #48]	@ (8017d50 <__libc_init_array+0x44>)
 8017d20:	f000 fdc6 	bl	80188b0 <_init>
 8017d24:	1b64      	subs	r4, r4, r5
 8017d26:	10a4      	asrs	r4, r4, #2
 8017d28:	2600      	movs	r6, #0
 8017d2a:	42a6      	cmp	r6, r4
 8017d2c:	d105      	bne.n	8017d3a <__libc_init_array+0x2e>
 8017d2e:	bd70      	pop	{r4, r5, r6, pc}
 8017d30:	f855 3b04 	ldr.w	r3, [r5], #4
 8017d34:	4798      	blx	r3
 8017d36:	3601      	adds	r6, #1
 8017d38:	e7ee      	b.n	8017d18 <__libc_init_array+0xc>
 8017d3a:	f855 3b04 	ldr.w	r3, [r5], #4
 8017d3e:	4798      	blx	r3
 8017d40:	3601      	adds	r6, #1
 8017d42:	e7f2      	b.n	8017d2a <__libc_init_array+0x1e>
 8017d44:	08018aa4 	.word	0x08018aa4
 8017d48:	08018aa4 	.word	0x08018aa4
 8017d4c:	08018aa4 	.word	0x08018aa4
 8017d50:	08018aa8 	.word	0x08018aa8

08017d54 <__retarget_lock_init_recursive>:
 8017d54:	4770      	bx	lr

08017d56 <__retarget_lock_acquire_recursive>:
 8017d56:	4770      	bx	lr

08017d58 <__retarget_lock_release_recursive>:
 8017d58:	4770      	bx	lr

08017d5a <memcpy>:
 8017d5a:	440a      	add	r2, r1
 8017d5c:	4291      	cmp	r1, r2
 8017d5e:	f100 33ff 	add.w	r3, r0, #4294967295	@ 0xffffffff
 8017d62:	d100      	bne.n	8017d66 <memcpy+0xc>
 8017d64:	4770      	bx	lr
 8017d66:	b510      	push	{r4, lr}
 8017d68:	f811 4b01 	ldrb.w	r4, [r1], #1
 8017d6c:	f803 4f01 	strb.w	r4, [r3, #1]!
 8017d70:	4291      	cmp	r1, r2
 8017d72:	d1f9      	bne.n	8017d68 <memcpy+0xe>
 8017d74:	bd10      	pop	{r4, pc}
	...

08017d78 <_free_r>:
 8017d78:	b538      	push	{r3, r4, r5, lr}
 8017d7a:	4605      	mov	r5, r0
 8017d7c:	2900      	cmp	r1, #0
 8017d7e:	d041      	beq.n	8017e04 <_free_r+0x8c>
 8017d80:	f851 3c04 	ldr.w	r3, [r1, #-4]
 8017d84:	1f0c      	subs	r4, r1, #4
 8017d86:	2b00      	cmp	r3, #0
 8017d88:	bfb8      	it	lt
 8017d8a:	18e4      	addlt	r4, r4, r3
 8017d8c:	f000 f8e0 	bl	8017f50 <__malloc_lock>
 8017d90:	4a1d      	ldr	r2, [pc, #116]	@ (8017e08 <_free_r+0x90>)
 8017d92:	6813      	ldr	r3, [r2, #0]
 8017d94:	b933      	cbnz	r3, 8017da4 <_free_r+0x2c>
 8017d96:	6063      	str	r3, [r4, #4]
 8017d98:	6014      	str	r4, [r2, #0]
 8017d9a:	4628      	mov	r0, r5
 8017d9c:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8017da0:	f000 b8dc 	b.w	8017f5c <__malloc_unlock>
 8017da4:	42a3      	cmp	r3, r4
 8017da6:	d908      	bls.n	8017dba <_free_r+0x42>
 8017da8:	6820      	ldr	r0, [r4, #0]
 8017daa:	1821      	adds	r1, r4, r0
 8017dac:	428b      	cmp	r3, r1
 8017dae:	bf01      	itttt	eq
 8017db0:	6819      	ldreq	r1, [r3, #0]
 8017db2:	685b      	ldreq	r3, [r3, #4]
 8017db4:	1809      	addeq	r1, r1, r0
 8017db6:	6021      	streq	r1, [r4, #0]
 8017db8:	e7ed      	b.n	8017d96 <_free_r+0x1e>
 8017dba:	461a      	mov	r2, r3
 8017dbc:	685b      	ldr	r3, [r3, #4]
 8017dbe:	b10b      	cbz	r3, 8017dc4 <_free_r+0x4c>
 8017dc0:	42a3      	cmp	r3, r4
 8017dc2:	d9fa      	bls.n	8017dba <_free_r+0x42>
 8017dc4:	6811      	ldr	r1, [r2, #0]
 8017dc6:	1850      	adds	r0, r2, r1
 8017dc8:	42a0      	cmp	r0, r4
 8017dca:	d10b      	bne.n	8017de4 <_free_r+0x6c>
 8017dcc:	6820      	ldr	r0, [r4, #0]
 8017dce:	4401      	add	r1, r0
 8017dd0:	1850      	adds	r0, r2, r1
 8017dd2:	4283      	cmp	r3, r0
 8017dd4:	6011      	str	r1, [r2, #0]
 8017dd6:	d1e0      	bne.n	8017d9a <_free_r+0x22>
 8017dd8:	6818      	ldr	r0, [r3, #0]
 8017dda:	685b      	ldr	r3, [r3, #4]
 8017ddc:	6053      	str	r3, [r2, #4]
 8017dde:	4408      	add	r0, r1
 8017de0:	6010      	str	r0, [r2, #0]
 8017de2:	e7da      	b.n	8017d9a <_free_r+0x22>
 8017de4:	d902      	bls.n	8017dec <_free_r+0x74>
 8017de6:	230c      	movs	r3, #12
 8017de8:	602b      	str	r3, [r5, #0]
 8017dea:	e7d6      	b.n	8017d9a <_free_r+0x22>
 8017dec:	6820      	ldr	r0, [r4, #0]
 8017dee:	1821      	adds	r1, r4, r0
 8017df0:	428b      	cmp	r3, r1
 8017df2:	bf04      	itt	eq
 8017df4:	6819      	ldreq	r1, [r3, #0]
 8017df6:	685b      	ldreq	r3, [r3, #4]
 8017df8:	6063      	str	r3, [r4, #4]
 8017dfa:	bf04      	itt	eq
 8017dfc:	1809      	addeq	r1, r1, r0
 8017dfe:	6021      	streq	r1, [r4, #0]
 8017e00:	6054      	str	r4, [r2, #4]
 8017e02:	e7ca      	b.n	8017d9a <_free_r+0x22>
 8017e04:	bd38      	pop	{r3, r4, r5, pc}
 8017e06:	bf00      	nop
 8017e08:	24012ddc 	.word	0x24012ddc

08017e0c <sbrk_aligned>:
 8017e0c:	b570      	push	{r4, r5, r6, lr}
 8017e0e:	4e0f      	ldr	r6, [pc, #60]	@ (8017e4c <sbrk_aligned+0x40>)
 8017e10:	460c      	mov	r4, r1
 8017e12:	6831      	ldr	r1, [r6, #0]
 8017e14:	4605      	mov	r5, r0
 8017e16:	b911      	cbnz	r1, 8017e1e <sbrk_aligned+0x12>
 8017e18:	f000 fcb6 	bl	8018788 <_sbrk_r>
 8017e1c:	6030      	str	r0, [r6, #0]
 8017e1e:	4621      	mov	r1, r4
 8017e20:	4628      	mov	r0, r5
 8017e22:	f000 fcb1 	bl	8018788 <_sbrk_r>
 8017e26:	1c43      	adds	r3, r0, #1
 8017e28:	d103      	bne.n	8017e32 <sbrk_aligned+0x26>
 8017e2a:	f04f 34ff 	mov.w	r4, #4294967295	@ 0xffffffff
 8017e2e:	4620      	mov	r0, r4
 8017e30:	bd70      	pop	{r4, r5, r6, pc}
 8017e32:	1cc4      	adds	r4, r0, #3
 8017e34:	f024 0403 	bic.w	r4, r4, #3
 8017e38:	42a0      	cmp	r0, r4
 8017e3a:	d0f8      	beq.n	8017e2e <sbrk_aligned+0x22>
 8017e3c:	1a21      	subs	r1, r4, r0
 8017e3e:	4628      	mov	r0, r5
 8017e40:	f000 fca2 	bl	8018788 <_sbrk_r>
 8017e44:	3001      	adds	r0, #1
 8017e46:	d1f2      	bne.n	8017e2e <sbrk_aligned+0x22>
 8017e48:	e7ef      	b.n	8017e2a <sbrk_aligned+0x1e>
 8017e4a:	bf00      	nop
 8017e4c:	24012dd8 	.word	0x24012dd8

08017e50 <_malloc_r>:
 8017e50:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8017e54:	1ccd      	adds	r5, r1, #3
 8017e56:	f025 0503 	bic.w	r5, r5, #3
 8017e5a:	3508      	adds	r5, #8
 8017e5c:	2d0c      	cmp	r5, #12
 8017e5e:	bf38      	it	cc
 8017e60:	250c      	movcc	r5, #12
 8017e62:	2d00      	cmp	r5, #0
 8017e64:	4606      	mov	r6, r0
 8017e66:	db01      	blt.n	8017e6c <_malloc_r+0x1c>
 8017e68:	42a9      	cmp	r1, r5
 8017e6a:	d904      	bls.n	8017e76 <_malloc_r+0x26>
 8017e6c:	230c      	movs	r3, #12
 8017e6e:	6033      	str	r3, [r6, #0]
 8017e70:	2000      	movs	r0, #0
 8017e72:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 8017e76:	f8df 80d4 	ldr.w	r8, [pc, #212]	@ 8017f4c <_malloc_r+0xfc>
 8017e7a:	f000 f869 	bl	8017f50 <__malloc_lock>
 8017e7e:	f8d8 3000 	ldr.w	r3, [r8]
 8017e82:	461c      	mov	r4, r3
 8017e84:	bb44      	cbnz	r4, 8017ed8 <_malloc_r+0x88>
 8017e86:	4629      	mov	r1, r5
 8017e88:	4630      	mov	r0, r6
 8017e8a:	f7ff ffbf 	bl	8017e0c <sbrk_aligned>
 8017e8e:	1c43      	adds	r3, r0, #1
 8017e90:	4604      	mov	r4, r0
 8017e92:	d158      	bne.n	8017f46 <_malloc_r+0xf6>
 8017e94:	f8d8 4000 	ldr.w	r4, [r8]
 8017e98:	4627      	mov	r7, r4
 8017e9a:	2f00      	cmp	r7, #0
 8017e9c:	d143      	bne.n	8017f26 <_malloc_r+0xd6>
 8017e9e:	2c00      	cmp	r4, #0
 8017ea0:	d04b      	beq.n	8017f3a <_malloc_r+0xea>
 8017ea2:	6823      	ldr	r3, [r4, #0]
 8017ea4:	4639      	mov	r1, r7
 8017ea6:	4630      	mov	r0, r6
 8017ea8:	eb04 0903 	add.w	r9, r4, r3
 8017eac:	f000 fc6c 	bl	8018788 <_sbrk_r>
 8017eb0:	4581      	cmp	r9, r0
 8017eb2:	d142      	bne.n	8017f3a <_malloc_r+0xea>
 8017eb4:	6821      	ldr	r1, [r4, #0]
 8017eb6:	1a6d      	subs	r5, r5, r1
 8017eb8:	4629      	mov	r1, r5
 8017eba:	4630      	mov	r0, r6
 8017ebc:	f7ff ffa6 	bl	8017e0c <sbrk_aligned>
 8017ec0:	3001      	adds	r0, #1
 8017ec2:	d03a      	beq.n	8017f3a <_malloc_r+0xea>
 8017ec4:	6823      	ldr	r3, [r4, #0]
 8017ec6:	442b      	add	r3, r5
 8017ec8:	6023      	str	r3, [r4, #0]
 8017eca:	f8d8 3000 	ldr.w	r3, [r8]
 8017ece:	685a      	ldr	r2, [r3, #4]
 8017ed0:	bb62      	cbnz	r2, 8017f2c <_malloc_r+0xdc>
 8017ed2:	f8c8 7000 	str.w	r7, [r8]
 8017ed6:	e00f      	b.n	8017ef8 <_malloc_r+0xa8>
 8017ed8:	6822      	ldr	r2, [r4, #0]
 8017eda:	1b52      	subs	r2, r2, r5
 8017edc:	d420      	bmi.n	8017f20 <_malloc_r+0xd0>
 8017ede:	2a0b      	cmp	r2, #11
 8017ee0:	d917      	bls.n	8017f12 <_malloc_r+0xc2>
 8017ee2:	1961      	adds	r1, r4, r5
 8017ee4:	42a3      	cmp	r3, r4
 8017ee6:	6025      	str	r5, [r4, #0]
 8017ee8:	bf18      	it	ne
 8017eea:	6059      	strne	r1, [r3, #4]
 8017eec:	6863      	ldr	r3, [r4, #4]
 8017eee:	bf08      	it	eq
 8017ef0:	f8c8 1000 	streq.w	r1, [r8]
 8017ef4:	5162      	str	r2, [r4, r5]
 8017ef6:	604b      	str	r3, [r1, #4]
 8017ef8:	4630      	mov	r0, r6
 8017efa:	f000 f82f 	bl	8017f5c <__malloc_unlock>
 8017efe:	f104 000b 	add.w	r0, r4, #11
 8017f02:	1d23      	adds	r3, r4, #4
 8017f04:	f020 0007 	bic.w	r0, r0, #7
 8017f08:	1ac2      	subs	r2, r0, r3
 8017f0a:	bf1c      	itt	ne
 8017f0c:	1a1b      	subne	r3, r3, r0
 8017f0e:	50a3      	strne	r3, [r4, r2]
 8017f10:	e7af      	b.n	8017e72 <_malloc_r+0x22>
 8017f12:	6862      	ldr	r2, [r4, #4]
 8017f14:	42a3      	cmp	r3, r4
 8017f16:	bf0c      	ite	eq
 8017f18:	f8c8 2000 	streq.w	r2, [r8]
 8017f1c:	605a      	strne	r2, [r3, #4]
 8017f1e:	e7eb      	b.n	8017ef8 <_malloc_r+0xa8>
 8017f20:	4623      	mov	r3, r4
 8017f22:	6864      	ldr	r4, [r4, #4]
 8017f24:	e7ae      	b.n	8017e84 <_malloc_r+0x34>
 8017f26:	463c      	mov	r4, r7
 8017f28:	687f      	ldr	r7, [r7, #4]
 8017f2a:	e7b6      	b.n	8017e9a <_malloc_r+0x4a>
 8017f2c:	461a      	mov	r2, r3
 8017f2e:	685b      	ldr	r3, [r3, #4]
 8017f30:	42a3      	cmp	r3, r4
 8017f32:	d1fb      	bne.n	8017f2c <_malloc_r+0xdc>
 8017f34:	2300      	movs	r3, #0
 8017f36:	6053      	str	r3, [r2, #4]
 8017f38:	e7de      	b.n	8017ef8 <_malloc_r+0xa8>
 8017f3a:	230c      	movs	r3, #12
 8017f3c:	6033      	str	r3, [r6, #0]
 8017f3e:	4630      	mov	r0, r6
 8017f40:	f000 f80c 	bl	8017f5c <__malloc_unlock>
 8017f44:	e794      	b.n	8017e70 <_malloc_r+0x20>
 8017f46:	6005      	str	r5, [r0, #0]
 8017f48:	e7d6      	b.n	8017ef8 <_malloc_r+0xa8>
 8017f4a:	bf00      	nop
 8017f4c:	24012ddc 	.word	0x24012ddc

08017f50 <__malloc_lock>:
 8017f50:	4801      	ldr	r0, [pc, #4]	@ (8017f58 <__malloc_lock+0x8>)
 8017f52:	f7ff bf00 	b.w	8017d56 <__retarget_lock_acquire_recursive>
 8017f56:	bf00      	nop
 8017f58:	24012dd4 	.word	0x24012dd4

08017f5c <__malloc_unlock>:
 8017f5c:	4801      	ldr	r0, [pc, #4]	@ (8017f64 <__malloc_unlock+0x8>)
 8017f5e:	f7ff befb 	b.w	8017d58 <__retarget_lock_release_recursive>
 8017f62:	bf00      	nop
 8017f64:	24012dd4 	.word	0x24012dd4

08017f68 <__sfputc_r>:
 8017f68:	6893      	ldr	r3, [r2, #8]
 8017f6a:	3b01      	subs	r3, #1
 8017f6c:	2b00      	cmp	r3, #0
 8017f6e:	b410      	push	{r4}
 8017f70:	6093      	str	r3, [r2, #8]
 8017f72:	da08      	bge.n	8017f86 <__sfputc_r+0x1e>
 8017f74:	6994      	ldr	r4, [r2, #24]
 8017f76:	42a3      	cmp	r3, r4
 8017f78:	db01      	blt.n	8017f7e <__sfputc_r+0x16>
 8017f7a:	290a      	cmp	r1, #10
 8017f7c:	d103      	bne.n	8017f86 <__sfputc_r+0x1e>
 8017f7e:	f85d 4b04 	ldr.w	r4, [sp], #4
 8017f82:	f000 bb6d 	b.w	8018660 <__swbuf_r>
 8017f86:	6813      	ldr	r3, [r2, #0]
 8017f88:	1c58      	adds	r0, r3, #1
 8017f8a:	6010      	str	r0, [r2, #0]
 8017f8c:	7019      	strb	r1, [r3, #0]
 8017f8e:	4608      	mov	r0, r1
 8017f90:	f85d 4b04 	ldr.w	r4, [sp], #4
 8017f94:	4770      	bx	lr

08017f96 <__sfputs_r>:
 8017f96:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8017f98:	4606      	mov	r6, r0
 8017f9a:	460f      	mov	r7, r1
 8017f9c:	4614      	mov	r4, r2
 8017f9e:	18d5      	adds	r5, r2, r3
 8017fa0:	42ac      	cmp	r4, r5
 8017fa2:	d101      	bne.n	8017fa8 <__sfputs_r+0x12>
 8017fa4:	2000      	movs	r0, #0
 8017fa6:	e007      	b.n	8017fb8 <__sfputs_r+0x22>
 8017fa8:	f814 1b01 	ldrb.w	r1, [r4], #1
 8017fac:	463a      	mov	r2, r7
 8017fae:	4630      	mov	r0, r6
 8017fb0:	f7ff ffda 	bl	8017f68 <__sfputc_r>
 8017fb4:	1c43      	adds	r3, r0, #1
 8017fb6:	d1f3      	bne.n	8017fa0 <__sfputs_r+0xa>
 8017fb8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	...

08017fbc <_vfiprintf_r>:
 8017fbc:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8017fc0:	460d      	mov	r5, r1
 8017fc2:	b09d      	sub	sp, #116	@ 0x74
 8017fc4:	4614      	mov	r4, r2
 8017fc6:	4698      	mov	r8, r3
 8017fc8:	4606      	mov	r6, r0
 8017fca:	b118      	cbz	r0, 8017fd4 <_vfiprintf_r+0x18>
 8017fcc:	6a03      	ldr	r3, [r0, #32]
 8017fce:	b90b      	cbnz	r3, 8017fd4 <_vfiprintf_r+0x18>
 8017fd0:	f7ff fd66 	bl	8017aa0 <__sinit>
 8017fd4:	6e6b      	ldr	r3, [r5, #100]	@ 0x64
 8017fd6:	07d9      	lsls	r1, r3, #31
 8017fd8:	d405      	bmi.n	8017fe6 <_vfiprintf_r+0x2a>
 8017fda:	89ab      	ldrh	r3, [r5, #12]
 8017fdc:	059a      	lsls	r2, r3, #22
 8017fde:	d402      	bmi.n	8017fe6 <_vfiprintf_r+0x2a>
 8017fe0:	6da8      	ldr	r0, [r5, #88]	@ 0x58
 8017fe2:	f7ff feb8 	bl	8017d56 <__retarget_lock_acquire_recursive>
 8017fe6:	89ab      	ldrh	r3, [r5, #12]
 8017fe8:	071b      	lsls	r3, r3, #28
 8017fea:	d501      	bpl.n	8017ff0 <_vfiprintf_r+0x34>
 8017fec:	692b      	ldr	r3, [r5, #16]
 8017fee:	b99b      	cbnz	r3, 8018018 <_vfiprintf_r+0x5c>
 8017ff0:	4629      	mov	r1, r5
 8017ff2:	4630      	mov	r0, r6
 8017ff4:	f000 fb72 	bl	80186dc <__swsetup_r>
 8017ff8:	b170      	cbz	r0, 8018018 <_vfiprintf_r+0x5c>
 8017ffa:	6e6b      	ldr	r3, [r5, #100]	@ 0x64
 8017ffc:	07dc      	lsls	r4, r3, #31
 8017ffe:	d504      	bpl.n	801800a <_vfiprintf_r+0x4e>
 8018000:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
 8018004:	b01d      	add	sp, #116	@ 0x74
 8018006:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 801800a:	89ab      	ldrh	r3, [r5, #12]
 801800c:	0598      	lsls	r0, r3, #22
 801800e:	d4f7      	bmi.n	8018000 <_vfiprintf_r+0x44>
 8018010:	6da8      	ldr	r0, [r5, #88]	@ 0x58
 8018012:	f7ff fea1 	bl	8017d58 <__retarget_lock_release_recursive>
 8018016:	e7f3      	b.n	8018000 <_vfiprintf_r+0x44>
 8018018:	2300      	movs	r3, #0
 801801a:	9309      	str	r3, [sp, #36]	@ 0x24
 801801c:	2320      	movs	r3, #32
 801801e:	f88d 3029 	strb.w	r3, [sp, #41]	@ 0x29
 8018022:	f8cd 800c 	str.w	r8, [sp, #12]
 8018026:	2330      	movs	r3, #48	@ 0x30
 8018028:	f8df 81ac 	ldr.w	r8, [pc, #428]	@ 80181d8 <_vfiprintf_r+0x21c>
 801802c:	f88d 302a 	strb.w	r3, [sp, #42]	@ 0x2a
 8018030:	f04f 0901 	mov.w	r9, #1
 8018034:	4623      	mov	r3, r4
 8018036:	469a      	mov	sl, r3
 8018038:	f813 2b01 	ldrb.w	r2, [r3], #1
 801803c:	b10a      	cbz	r2, 8018042 <_vfiprintf_r+0x86>
 801803e:	2a25      	cmp	r2, #37	@ 0x25
 8018040:	d1f9      	bne.n	8018036 <_vfiprintf_r+0x7a>
 8018042:	ebba 0b04 	subs.w	fp, sl, r4
 8018046:	d00b      	beq.n	8018060 <_vfiprintf_r+0xa4>
 8018048:	465b      	mov	r3, fp
 801804a:	4622      	mov	r2, r4
 801804c:	4629      	mov	r1, r5
 801804e:	4630      	mov	r0, r6
 8018050:	f7ff ffa1 	bl	8017f96 <__sfputs_r>
 8018054:	3001      	adds	r0, #1
 8018056:	f000 80a7 	beq.w	80181a8 <_vfiprintf_r+0x1ec>
 801805a:	9a09      	ldr	r2, [sp, #36]	@ 0x24
 801805c:	445a      	add	r2, fp
 801805e:	9209      	str	r2, [sp, #36]	@ 0x24
 8018060:	f89a 3000 	ldrb.w	r3, [sl]
 8018064:	2b00      	cmp	r3, #0
 8018066:	f000 809f 	beq.w	80181a8 <_vfiprintf_r+0x1ec>
 801806a:	2300      	movs	r3, #0
 801806c:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
 8018070:	e9cd 2305 	strd	r2, r3, [sp, #20]
 8018074:	f10a 0a01 	add.w	sl, sl, #1
 8018078:	9304      	str	r3, [sp, #16]
 801807a:	9307      	str	r3, [sp, #28]
 801807c:	f88d 3053 	strb.w	r3, [sp, #83]	@ 0x53
 8018080:	931a      	str	r3, [sp, #104]	@ 0x68
 8018082:	4654      	mov	r4, sl
 8018084:	2205      	movs	r2, #5
 8018086:	f814 1b01 	ldrb.w	r1, [r4], #1
 801808a:	4853      	ldr	r0, [pc, #332]	@ (80181d8 <_vfiprintf_r+0x21c>)
 801808c:	f7e8 f928 	bl	80002e0 <memchr>
 8018090:	9a04      	ldr	r2, [sp, #16]
 8018092:	b9d8      	cbnz	r0, 80180cc <_vfiprintf_r+0x110>
 8018094:	06d1      	lsls	r1, r2, #27
 8018096:	bf44      	itt	mi
 8018098:	2320      	movmi	r3, #32
 801809a:	f88d 3053 	strbmi.w	r3, [sp, #83]	@ 0x53
 801809e:	0713      	lsls	r3, r2, #28
 80180a0:	bf44      	itt	mi
 80180a2:	232b      	movmi	r3, #43	@ 0x2b
 80180a4:	f88d 3053 	strbmi.w	r3, [sp, #83]	@ 0x53
 80180a8:	f89a 3000 	ldrb.w	r3, [sl]
 80180ac:	2b2a      	cmp	r3, #42	@ 0x2a
 80180ae:	d015      	beq.n	80180dc <_vfiprintf_r+0x120>
 80180b0:	9a07      	ldr	r2, [sp, #28]
 80180b2:	4654      	mov	r4, sl
 80180b4:	2000      	movs	r0, #0
 80180b6:	f04f 0c0a 	mov.w	ip, #10
 80180ba:	4621      	mov	r1, r4
 80180bc:	f811 3b01 	ldrb.w	r3, [r1], #1
 80180c0:	3b30      	subs	r3, #48	@ 0x30
 80180c2:	2b09      	cmp	r3, #9
 80180c4:	d94b      	bls.n	801815e <_vfiprintf_r+0x1a2>
 80180c6:	b1b0      	cbz	r0, 80180f6 <_vfiprintf_r+0x13a>
 80180c8:	9207      	str	r2, [sp, #28]
 80180ca:	e014      	b.n	80180f6 <_vfiprintf_r+0x13a>
 80180cc:	eba0 0308 	sub.w	r3, r0, r8
 80180d0:	fa09 f303 	lsl.w	r3, r9, r3
 80180d4:	4313      	orrs	r3, r2
 80180d6:	9304      	str	r3, [sp, #16]
 80180d8:	46a2      	mov	sl, r4
 80180da:	e7d2      	b.n	8018082 <_vfiprintf_r+0xc6>
 80180dc:	9b03      	ldr	r3, [sp, #12]
 80180de:	1d19      	adds	r1, r3, #4
 80180e0:	681b      	ldr	r3, [r3, #0]
 80180e2:	9103      	str	r1, [sp, #12]
 80180e4:	2b00      	cmp	r3, #0
 80180e6:	bfbb      	ittet	lt
 80180e8:	425b      	neglt	r3, r3
 80180ea:	f042 0202 	orrlt.w	r2, r2, #2
 80180ee:	9307      	strge	r3, [sp, #28]
 80180f0:	9307      	strlt	r3, [sp, #28]
 80180f2:	bfb8      	it	lt
 80180f4:	9204      	strlt	r2, [sp, #16]
 80180f6:	7823      	ldrb	r3, [r4, #0]
 80180f8:	2b2e      	cmp	r3, #46	@ 0x2e
 80180fa:	d10a      	bne.n	8018112 <_vfiprintf_r+0x156>
 80180fc:	7863      	ldrb	r3, [r4, #1]
 80180fe:	2b2a      	cmp	r3, #42	@ 0x2a
 8018100:	d132      	bne.n	8018168 <_vfiprintf_r+0x1ac>
 8018102:	9b03      	ldr	r3, [sp, #12]
 8018104:	1d1a      	adds	r2, r3, #4
 8018106:	681b      	ldr	r3, [r3, #0]
 8018108:	9203      	str	r2, [sp, #12]
 801810a:	ea43 73e3 	orr.w	r3, r3, r3, asr #31
 801810e:	3402      	adds	r4, #2
 8018110:	9305      	str	r3, [sp, #20]
 8018112:	f8df a0d4 	ldr.w	sl, [pc, #212]	@ 80181e8 <_vfiprintf_r+0x22c>
 8018116:	7821      	ldrb	r1, [r4, #0]
 8018118:	2203      	movs	r2, #3
 801811a:	4650      	mov	r0, sl
 801811c:	f7e8 f8e0 	bl	80002e0 <memchr>
 8018120:	b138      	cbz	r0, 8018132 <_vfiprintf_r+0x176>
 8018122:	9b04      	ldr	r3, [sp, #16]
 8018124:	eba0 000a 	sub.w	r0, r0, sl
 8018128:	2240      	movs	r2, #64	@ 0x40
 801812a:	4082      	lsls	r2, r0
 801812c:	4313      	orrs	r3, r2
 801812e:	3401      	adds	r4, #1
 8018130:	9304      	str	r3, [sp, #16]
 8018132:	f814 1b01 	ldrb.w	r1, [r4], #1
 8018136:	4829      	ldr	r0, [pc, #164]	@ (80181dc <_vfiprintf_r+0x220>)
 8018138:	f88d 1028 	strb.w	r1, [sp, #40]	@ 0x28
 801813c:	2206      	movs	r2, #6
 801813e:	f7e8 f8cf 	bl	80002e0 <memchr>
 8018142:	2800      	cmp	r0, #0
 8018144:	d03f      	beq.n	80181c6 <_vfiprintf_r+0x20a>
 8018146:	4b26      	ldr	r3, [pc, #152]	@ (80181e0 <_vfiprintf_r+0x224>)
 8018148:	bb1b      	cbnz	r3, 8018192 <_vfiprintf_r+0x1d6>
 801814a:	9b03      	ldr	r3, [sp, #12]
 801814c:	3307      	adds	r3, #7
 801814e:	f023 0307 	bic.w	r3, r3, #7
 8018152:	3308      	adds	r3, #8
 8018154:	9303      	str	r3, [sp, #12]
 8018156:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 8018158:	443b      	add	r3, r7
 801815a:	9309      	str	r3, [sp, #36]	@ 0x24
 801815c:	e76a      	b.n	8018034 <_vfiprintf_r+0x78>
 801815e:	fb0c 3202 	mla	r2, ip, r2, r3
 8018162:	460c      	mov	r4, r1
 8018164:	2001      	movs	r0, #1
 8018166:	e7a8      	b.n	80180ba <_vfiprintf_r+0xfe>
 8018168:	2300      	movs	r3, #0
 801816a:	3401      	adds	r4, #1
 801816c:	9305      	str	r3, [sp, #20]
 801816e:	4619      	mov	r1, r3
 8018170:	f04f 0c0a 	mov.w	ip, #10
 8018174:	4620      	mov	r0, r4
 8018176:	f810 2b01 	ldrb.w	r2, [r0], #1
 801817a:	3a30      	subs	r2, #48	@ 0x30
 801817c:	2a09      	cmp	r2, #9
 801817e:	d903      	bls.n	8018188 <_vfiprintf_r+0x1cc>
 8018180:	2b00      	cmp	r3, #0
 8018182:	d0c6      	beq.n	8018112 <_vfiprintf_r+0x156>
 8018184:	9105      	str	r1, [sp, #20]
 8018186:	e7c4      	b.n	8018112 <_vfiprintf_r+0x156>
 8018188:	fb0c 2101 	mla	r1, ip, r1, r2
 801818c:	4604      	mov	r4, r0
 801818e:	2301      	movs	r3, #1
 8018190:	e7f0      	b.n	8018174 <_vfiprintf_r+0x1b8>
 8018192:	ab03      	add	r3, sp, #12
 8018194:	9300      	str	r3, [sp, #0]
 8018196:	462a      	mov	r2, r5
 8018198:	4b12      	ldr	r3, [pc, #72]	@ (80181e4 <_vfiprintf_r+0x228>)
 801819a:	a904      	add	r1, sp, #16
 801819c:	4630      	mov	r0, r6
 801819e:	f3af 8000 	nop.w
 80181a2:	4607      	mov	r7, r0
 80181a4:	1c78      	adds	r0, r7, #1
 80181a6:	d1d6      	bne.n	8018156 <_vfiprintf_r+0x19a>
 80181a8:	6e6b      	ldr	r3, [r5, #100]	@ 0x64
 80181aa:	07d9      	lsls	r1, r3, #31
 80181ac:	d405      	bmi.n	80181ba <_vfiprintf_r+0x1fe>
 80181ae:	89ab      	ldrh	r3, [r5, #12]
 80181b0:	059a      	lsls	r2, r3, #22
 80181b2:	d402      	bmi.n	80181ba <_vfiprintf_r+0x1fe>
 80181b4:	6da8      	ldr	r0, [r5, #88]	@ 0x58
 80181b6:	f7ff fdcf 	bl	8017d58 <__retarget_lock_release_recursive>
 80181ba:	89ab      	ldrh	r3, [r5, #12]
 80181bc:	065b      	lsls	r3, r3, #25
 80181be:	f53f af1f 	bmi.w	8018000 <_vfiprintf_r+0x44>
 80181c2:	9809      	ldr	r0, [sp, #36]	@ 0x24
 80181c4:	e71e      	b.n	8018004 <_vfiprintf_r+0x48>
 80181c6:	ab03      	add	r3, sp, #12
 80181c8:	9300      	str	r3, [sp, #0]
 80181ca:	462a      	mov	r2, r5
 80181cc:	4b05      	ldr	r3, [pc, #20]	@ (80181e4 <_vfiprintf_r+0x228>)
 80181ce:	a904      	add	r1, sp, #16
 80181d0:	4630      	mov	r0, r6
 80181d2:	f000 f879 	bl	80182c8 <_printf_i>
 80181d6:	e7e4      	b.n	80181a2 <_vfiprintf_r+0x1e6>
 80181d8:	08018a68 	.word	0x08018a68
 80181dc:	08018a72 	.word	0x08018a72
 80181e0:	00000000 	.word	0x00000000
 80181e4:	08017f97 	.word	0x08017f97
 80181e8:	08018a6e 	.word	0x08018a6e

080181ec <_printf_common>:
 80181ec:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 80181f0:	4616      	mov	r6, r2
 80181f2:	4698      	mov	r8, r3
 80181f4:	688a      	ldr	r2, [r1, #8]
 80181f6:	690b      	ldr	r3, [r1, #16]
 80181f8:	f8dd 9020 	ldr.w	r9, [sp, #32]
 80181fc:	4293      	cmp	r3, r2
 80181fe:	bfb8      	it	lt
 8018200:	4613      	movlt	r3, r2
 8018202:	6033      	str	r3, [r6, #0]
 8018204:	f891 2043 	ldrb.w	r2, [r1, #67]	@ 0x43
 8018208:	4607      	mov	r7, r0
 801820a:	460c      	mov	r4, r1
 801820c:	b10a      	cbz	r2, 8018212 <_printf_common+0x26>
 801820e:	3301      	adds	r3, #1
 8018210:	6033      	str	r3, [r6, #0]
 8018212:	6823      	ldr	r3, [r4, #0]
 8018214:	0699      	lsls	r1, r3, #26
 8018216:	bf42      	ittt	mi
 8018218:	6833      	ldrmi	r3, [r6, #0]
 801821a:	3302      	addmi	r3, #2
 801821c:	6033      	strmi	r3, [r6, #0]
 801821e:	6825      	ldr	r5, [r4, #0]
 8018220:	f015 0506 	ands.w	r5, r5, #6
 8018224:	d106      	bne.n	8018234 <_printf_common+0x48>
 8018226:	f104 0a19 	add.w	sl, r4, #25
 801822a:	68e3      	ldr	r3, [r4, #12]
 801822c:	6832      	ldr	r2, [r6, #0]
 801822e:	1a9b      	subs	r3, r3, r2
 8018230:	42ab      	cmp	r3, r5
 8018232:	dc26      	bgt.n	8018282 <_printf_common+0x96>
 8018234:	f894 3043 	ldrb.w	r3, [r4, #67]	@ 0x43
 8018238:	6822      	ldr	r2, [r4, #0]
 801823a:	3b00      	subs	r3, #0
 801823c:	bf18      	it	ne
 801823e:	2301      	movne	r3, #1
 8018240:	0692      	lsls	r2, r2, #26
 8018242:	d42b      	bmi.n	801829c <_printf_common+0xb0>
 8018244:	f104 0243 	add.w	r2, r4, #67	@ 0x43
 8018248:	4641      	mov	r1, r8
 801824a:	4638      	mov	r0, r7
 801824c:	47c8      	blx	r9
 801824e:	3001      	adds	r0, #1
 8018250:	d01e      	beq.n	8018290 <_printf_common+0xa4>
 8018252:	6823      	ldr	r3, [r4, #0]
 8018254:	6922      	ldr	r2, [r4, #16]
 8018256:	f003 0306 	and.w	r3, r3, #6
 801825a:	2b04      	cmp	r3, #4
 801825c:	bf02      	ittt	eq
 801825e:	68e5      	ldreq	r5, [r4, #12]
 8018260:	6833      	ldreq	r3, [r6, #0]
 8018262:	1aed      	subeq	r5, r5, r3
 8018264:	68a3      	ldr	r3, [r4, #8]
 8018266:	bf0c      	ite	eq
 8018268:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
 801826c:	2500      	movne	r5, #0
 801826e:	4293      	cmp	r3, r2
 8018270:	bfc4      	itt	gt
 8018272:	1a9b      	subgt	r3, r3, r2
 8018274:	18ed      	addgt	r5, r5, r3
 8018276:	2600      	movs	r6, #0
 8018278:	341a      	adds	r4, #26
 801827a:	42b5      	cmp	r5, r6
 801827c:	d11a      	bne.n	80182b4 <_printf_common+0xc8>
 801827e:	2000      	movs	r0, #0
 8018280:	e008      	b.n	8018294 <_printf_common+0xa8>
 8018282:	2301      	movs	r3, #1
 8018284:	4652      	mov	r2, sl
 8018286:	4641      	mov	r1, r8
 8018288:	4638      	mov	r0, r7
 801828a:	47c8      	blx	r9
 801828c:	3001      	adds	r0, #1
 801828e:	d103      	bne.n	8018298 <_printf_common+0xac>
 8018290:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
 8018294:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8018298:	3501      	adds	r5, #1
 801829a:	e7c6      	b.n	801822a <_printf_common+0x3e>
 801829c:	18e1      	adds	r1, r4, r3
 801829e:	1c5a      	adds	r2, r3, #1
 80182a0:	2030      	movs	r0, #48	@ 0x30
 80182a2:	f881 0043 	strb.w	r0, [r1, #67]	@ 0x43
 80182a6:	4422      	add	r2, r4
 80182a8:	f894 1045 	ldrb.w	r1, [r4, #69]	@ 0x45
 80182ac:	f882 1043 	strb.w	r1, [r2, #67]	@ 0x43
 80182b0:	3302      	adds	r3, #2
 80182b2:	e7c7      	b.n	8018244 <_printf_common+0x58>
 80182b4:	2301      	movs	r3, #1
 80182b6:	4622      	mov	r2, r4
 80182b8:	4641      	mov	r1, r8
 80182ba:	4638      	mov	r0, r7
 80182bc:	47c8      	blx	r9
 80182be:	3001      	adds	r0, #1
 80182c0:	d0e6      	beq.n	8018290 <_printf_common+0xa4>
 80182c2:	3601      	adds	r6, #1
 80182c4:	e7d9      	b.n	801827a <_printf_common+0x8e>
	...

080182c8 <_printf_i>:
 80182c8:	e92d 47ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
 80182cc:	7e0f      	ldrb	r7, [r1, #24]
 80182ce:	9e0c      	ldr	r6, [sp, #48]	@ 0x30
 80182d0:	2f78      	cmp	r7, #120	@ 0x78
 80182d2:	4691      	mov	r9, r2
 80182d4:	4680      	mov	r8, r0
 80182d6:	460c      	mov	r4, r1
 80182d8:	469a      	mov	sl, r3
 80182da:	f101 0243 	add.w	r2, r1, #67	@ 0x43
 80182de:	d807      	bhi.n	80182f0 <_printf_i+0x28>
 80182e0:	2f62      	cmp	r7, #98	@ 0x62
 80182e2:	d80a      	bhi.n	80182fa <_printf_i+0x32>
 80182e4:	2f00      	cmp	r7, #0
 80182e6:	f000 80d2 	beq.w	801848e <_printf_i+0x1c6>
 80182ea:	2f58      	cmp	r7, #88	@ 0x58
 80182ec:	f000 80b9 	beq.w	8018462 <_printf_i+0x19a>
 80182f0:	f104 0642 	add.w	r6, r4, #66	@ 0x42
 80182f4:	f884 7042 	strb.w	r7, [r4, #66]	@ 0x42
 80182f8:	e03a      	b.n	8018370 <_printf_i+0xa8>
 80182fa:	f1a7 0363 	sub.w	r3, r7, #99	@ 0x63
 80182fe:	2b15      	cmp	r3, #21
 8018300:	d8f6      	bhi.n	80182f0 <_printf_i+0x28>
 8018302:	a101      	add	r1, pc, #4	@ (adr r1, 8018308 <_printf_i+0x40>)
 8018304:	f851 f023 	ldr.w	pc, [r1, r3, lsl #2]
 8018308:	08018361 	.word	0x08018361
 801830c:	08018375 	.word	0x08018375
 8018310:	080182f1 	.word	0x080182f1
 8018314:	080182f1 	.word	0x080182f1
 8018318:	080182f1 	.word	0x080182f1
 801831c:	080182f1 	.word	0x080182f1
 8018320:	08018375 	.word	0x08018375
 8018324:	080182f1 	.word	0x080182f1
 8018328:	080182f1 	.word	0x080182f1
 801832c:	080182f1 	.word	0x080182f1
 8018330:	080182f1 	.word	0x080182f1
 8018334:	08018475 	.word	0x08018475
 8018338:	0801839f 	.word	0x0801839f
 801833c:	0801842f 	.word	0x0801842f
 8018340:	080182f1 	.word	0x080182f1
 8018344:	080182f1 	.word	0x080182f1
 8018348:	08018497 	.word	0x08018497
 801834c:	080182f1 	.word	0x080182f1
 8018350:	0801839f 	.word	0x0801839f
 8018354:	080182f1 	.word	0x080182f1
 8018358:	080182f1 	.word	0x080182f1
 801835c:	08018437 	.word	0x08018437
 8018360:	6833      	ldr	r3, [r6, #0]
 8018362:	1d1a      	adds	r2, r3, #4
 8018364:	681b      	ldr	r3, [r3, #0]
 8018366:	6032      	str	r2, [r6, #0]
 8018368:	f104 0642 	add.w	r6, r4, #66	@ 0x42
 801836c:	f884 3042 	strb.w	r3, [r4, #66]	@ 0x42
 8018370:	2301      	movs	r3, #1
 8018372:	e09d      	b.n	80184b0 <_printf_i+0x1e8>
 8018374:	6833      	ldr	r3, [r6, #0]
 8018376:	6820      	ldr	r0, [r4, #0]
 8018378:	1d19      	adds	r1, r3, #4
 801837a:	6031      	str	r1, [r6, #0]
 801837c:	0606      	lsls	r6, r0, #24
 801837e:	d501      	bpl.n	8018384 <_printf_i+0xbc>
 8018380:	681d      	ldr	r5, [r3, #0]
 8018382:	e003      	b.n	801838c <_printf_i+0xc4>
 8018384:	0645      	lsls	r5, r0, #25
 8018386:	d5fb      	bpl.n	8018380 <_printf_i+0xb8>
 8018388:	f9b3 5000 	ldrsh.w	r5, [r3]
 801838c:	2d00      	cmp	r5, #0
 801838e:	da03      	bge.n	8018398 <_printf_i+0xd0>
 8018390:	232d      	movs	r3, #45	@ 0x2d
 8018392:	426d      	negs	r5, r5
 8018394:	f884 3043 	strb.w	r3, [r4, #67]	@ 0x43
 8018398:	4859      	ldr	r0, [pc, #356]	@ (8018500 <_printf_i+0x238>)
 801839a:	230a      	movs	r3, #10
 801839c:	e011      	b.n	80183c2 <_printf_i+0xfa>
 801839e:	6821      	ldr	r1, [r4, #0]
 80183a0:	6833      	ldr	r3, [r6, #0]
 80183a2:	0608      	lsls	r0, r1, #24
 80183a4:	f853 5b04 	ldr.w	r5, [r3], #4
 80183a8:	d402      	bmi.n	80183b0 <_printf_i+0xe8>
 80183aa:	0649      	lsls	r1, r1, #25
 80183ac:	bf48      	it	mi
 80183ae:	b2ad      	uxthmi	r5, r5
 80183b0:	2f6f      	cmp	r7, #111	@ 0x6f
 80183b2:	4853      	ldr	r0, [pc, #332]	@ (8018500 <_printf_i+0x238>)
 80183b4:	6033      	str	r3, [r6, #0]
 80183b6:	bf14      	ite	ne
 80183b8:	230a      	movne	r3, #10
 80183ba:	2308      	moveq	r3, #8
 80183bc:	2100      	movs	r1, #0
 80183be:	f884 1043 	strb.w	r1, [r4, #67]	@ 0x43
 80183c2:	6866      	ldr	r6, [r4, #4]
 80183c4:	60a6      	str	r6, [r4, #8]
 80183c6:	2e00      	cmp	r6, #0
 80183c8:	bfa2      	ittt	ge
 80183ca:	6821      	ldrge	r1, [r4, #0]
 80183cc:	f021 0104 	bicge.w	r1, r1, #4
 80183d0:	6021      	strge	r1, [r4, #0]
 80183d2:	b90d      	cbnz	r5, 80183d8 <_printf_i+0x110>
 80183d4:	2e00      	cmp	r6, #0
 80183d6:	d04b      	beq.n	8018470 <_printf_i+0x1a8>
 80183d8:	4616      	mov	r6, r2
 80183da:	fbb5 f1f3 	udiv	r1, r5, r3
 80183de:	fb03 5711 	mls	r7, r3, r1, r5
 80183e2:	5dc7      	ldrb	r7, [r0, r7]
 80183e4:	f806 7d01 	strb.w	r7, [r6, #-1]!
 80183e8:	462f      	mov	r7, r5
 80183ea:	42bb      	cmp	r3, r7
 80183ec:	460d      	mov	r5, r1
 80183ee:	d9f4      	bls.n	80183da <_printf_i+0x112>
 80183f0:	2b08      	cmp	r3, #8
 80183f2:	d10b      	bne.n	801840c <_printf_i+0x144>
 80183f4:	6823      	ldr	r3, [r4, #0]
 80183f6:	07df      	lsls	r7, r3, #31
 80183f8:	d508      	bpl.n	801840c <_printf_i+0x144>
 80183fa:	6923      	ldr	r3, [r4, #16]
 80183fc:	6861      	ldr	r1, [r4, #4]
 80183fe:	4299      	cmp	r1, r3
 8018400:	bfde      	ittt	le
 8018402:	2330      	movle	r3, #48	@ 0x30
 8018404:	f806 3c01 	strble.w	r3, [r6, #-1]
 8018408:	f106 36ff 	addle.w	r6, r6, #4294967295	@ 0xffffffff
 801840c:	1b92      	subs	r2, r2, r6
 801840e:	6122      	str	r2, [r4, #16]
 8018410:	f8cd a000 	str.w	sl, [sp]
 8018414:	464b      	mov	r3, r9
 8018416:	aa03      	add	r2, sp, #12
 8018418:	4621      	mov	r1, r4
 801841a:	4640      	mov	r0, r8
 801841c:	f7ff fee6 	bl	80181ec <_printf_common>
 8018420:	3001      	adds	r0, #1
 8018422:	d14a      	bne.n	80184ba <_printf_i+0x1f2>
 8018424:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
 8018428:	b004      	add	sp, #16
 801842a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 801842e:	6823      	ldr	r3, [r4, #0]
 8018430:	f043 0320 	orr.w	r3, r3, #32
 8018434:	6023      	str	r3, [r4, #0]
 8018436:	4833      	ldr	r0, [pc, #204]	@ (8018504 <_printf_i+0x23c>)
 8018438:	2778      	movs	r7, #120	@ 0x78
 801843a:	f884 7045 	strb.w	r7, [r4, #69]	@ 0x45
 801843e:	6823      	ldr	r3, [r4, #0]
 8018440:	6831      	ldr	r1, [r6, #0]
 8018442:	061f      	lsls	r7, r3, #24
 8018444:	f851 5b04 	ldr.w	r5, [r1], #4
 8018448:	d402      	bmi.n	8018450 <_printf_i+0x188>
 801844a:	065f      	lsls	r7, r3, #25
 801844c:	bf48      	it	mi
 801844e:	b2ad      	uxthmi	r5, r5
 8018450:	6031      	str	r1, [r6, #0]
 8018452:	07d9      	lsls	r1, r3, #31
 8018454:	bf44      	itt	mi
 8018456:	f043 0320 	orrmi.w	r3, r3, #32
 801845a:	6023      	strmi	r3, [r4, #0]
 801845c:	b11d      	cbz	r5, 8018466 <_printf_i+0x19e>
 801845e:	2310      	movs	r3, #16
 8018460:	e7ac      	b.n	80183bc <_printf_i+0xf4>
 8018462:	4827      	ldr	r0, [pc, #156]	@ (8018500 <_printf_i+0x238>)
 8018464:	e7e9      	b.n	801843a <_printf_i+0x172>
 8018466:	6823      	ldr	r3, [r4, #0]
 8018468:	f023 0320 	bic.w	r3, r3, #32
 801846c:	6023      	str	r3, [r4, #0]
 801846e:	e7f6      	b.n	801845e <_printf_i+0x196>
 8018470:	4616      	mov	r6, r2
 8018472:	e7bd      	b.n	80183f0 <_printf_i+0x128>
 8018474:	6833      	ldr	r3, [r6, #0]
 8018476:	6825      	ldr	r5, [r4, #0]
 8018478:	6961      	ldr	r1, [r4, #20]
 801847a:	1d18      	adds	r0, r3, #4
 801847c:	6030      	str	r0, [r6, #0]
 801847e:	062e      	lsls	r6, r5, #24
 8018480:	681b      	ldr	r3, [r3, #0]
 8018482:	d501      	bpl.n	8018488 <_printf_i+0x1c0>
 8018484:	6019      	str	r1, [r3, #0]
 8018486:	e002      	b.n	801848e <_printf_i+0x1c6>
 8018488:	0668      	lsls	r0, r5, #25
 801848a:	d5fb      	bpl.n	8018484 <_printf_i+0x1bc>
 801848c:	8019      	strh	r1, [r3, #0]
 801848e:	2300      	movs	r3, #0
 8018490:	6123      	str	r3, [r4, #16]
 8018492:	4616      	mov	r6, r2
 8018494:	e7bc      	b.n	8018410 <_printf_i+0x148>
 8018496:	6833      	ldr	r3, [r6, #0]
 8018498:	1d1a      	adds	r2, r3, #4
 801849a:	6032      	str	r2, [r6, #0]
 801849c:	681e      	ldr	r6, [r3, #0]
 801849e:	6862      	ldr	r2, [r4, #4]
 80184a0:	2100      	movs	r1, #0
 80184a2:	4630      	mov	r0, r6
 80184a4:	f7e7 ff1c 	bl	80002e0 <memchr>
 80184a8:	b108      	cbz	r0, 80184ae <_printf_i+0x1e6>
 80184aa:	1b80      	subs	r0, r0, r6
 80184ac:	6060      	str	r0, [r4, #4]
 80184ae:	6863      	ldr	r3, [r4, #4]
 80184b0:	6123      	str	r3, [r4, #16]
 80184b2:	2300      	movs	r3, #0
 80184b4:	f884 3043 	strb.w	r3, [r4, #67]	@ 0x43
 80184b8:	e7aa      	b.n	8018410 <_printf_i+0x148>
 80184ba:	6923      	ldr	r3, [r4, #16]
 80184bc:	4632      	mov	r2, r6
 80184be:	4649      	mov	r1, r9
 80184c0:	4640      	mov	r0, r8
 80184c2:	47d0      	blx	sl
 80184c4:	3001      	adds	r0, #1
 80184c6:	d0ad      	beq.n	8018424 <_printf_i+0x15c>
 80184c8:	6823      	ldr	r3, [r4, #0]
 80184ca:	079b      	lsls	r3, r3, #30
 80184cc:	d413      	bmi.n	80184f6 <_printf_i+0x22e>
 80184ce:	68e0      	ldr	r0, [r4, #12]
 80184d0:	9b03      	ldr	r3, [sp, #12]
 80184d2:	4298      	cmp	r0, r3
 80184d4:	bfb8      	it	lt
 80184d6:	4618      	movlt	r0, r3
 80184d8:	e7a6      	b.n	8018428 <_printf_i+0x160>
 80184da:	2301      	movs	r3, #1
 80184dc:	4632      	mov	r2, r6
 80184de:	4649      	mov	r1, r9
 80184e0:	4640      	mov	r0, r8
 80184e2:	47d0      	blx	sl
 80184e4:	3001      	adds	r0, #1
 80184e6:	d09d      	beq.n	8018424 <_printf_i+0x15c>
 80184e8:	3501      	adds	r5, #1
 80184ea:	68e3      	ldr	r3, [r4, #12]
 80184ec:	9903      	ldr	r1, [sp, #12]
 80184ee:	1a5b      	subs	r3, r3, r1
 80184f0:	42ab      	cmp	r3, r5
 80184f2:	dcf2      	bgt.n	80184da <_printf_i+0x212>
 80184f4:	e7eb      	b.n	80184ce <_printf_i+0x206>
 80184f6:	2500      	movs	r5, #0
 80184f8:	f104 0619 	add.w	r6, r4, #25
 80184fc:	e7f5      	b.n	80184ea <_printf_i+0x222>
 80184fe:	bf00      	nop
 8018500:	08018a79 	.word	0x08018a79
 8018504:	08018a8a 	.word	0x08018a8a

08018508 <__sflush_r>:
 8018508:	f9b1 200c 	ldrsh.w	r2, [r1, #12]
 801850c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8018510:	0716      	lsls	r6, r2, #28
 8018512:	4605      	mov	r5, r0
 8018514:	460c      	mov	r4, r1
 8018516:	d454      	bmi.n	80185c2 <__sflush_r+0xba>
 8018518:	684b      	ldr	r3, [r1, #4]
 801851a:	2b00      	cmp	r3, #0
 801851c:	dc02      	bgt.n	8018524 <__sflush_r+0x1c>
 801851e:	6c0b      	ldr	r3, [r1, #64]	@ 0x40
 8018520:	2b00      	cmp	r3, #0
 8018522:	dd48      	ble.n	80185b6 <__sflush_r+0xae>
 8018524:	6ae6      	ldr	r6, [r4, #44]	@ 0x2c
 8018526:	2e00      	cmp	r6, #0
 8018528:	d045      	beq.n	80185b6 <__sflush_r+0xae>
 801852a:	2300      	movs	r3, #0
 801852c:	f412 5280 	ands.w	r2, r2, #4096	@ 0x1000
 8018530:	682f      	ldr	r7, [r5, #0]
 8018532:	6a21      	ldr	r1, [r4, #32]
 8018534:	602b      	str	r3, [r5, #0]
 8018536:	d030      	beq.n	801859a <__sflush_r+0x92>
 8018538:	6d62      	ldr	r2, [r4, #84]	@ 0x54
 801853a:	89a3      	ldrh	r3, [r4, #12]
 801853c:	0759      	lsls	r1, r3, #29
 801853e:	d505      	bpl.n	801854c <__sflush_r+0x44>
 8018540:	6863      	ldr	r3, [r4, #4]
 8018542:	1ad2      	subs	r2, r2, r3
 8018544:	6b63      	ldr	r3, [r4, #52]	@ 0x34
 8018546:	b10b      	cbz	r3, 801854c <__sflush_r+0x44>
 8018548:	6c23      	ldr	r3, [r4, #64]	@ 0x40
 801854a:	1ad2      	subs	r2, r2, r3
 801854c:	2300      	movs	r3, #0
 801854e:	6ae6      	ldr	r6, [r4, #44]	@ 0x2c
 8018550:	6a21      	ldr	r1, [r4, #32]
 8018552:	4628      	mov	r0, r5
 8018554:	47b0      	blx	r6
 8018556:	1c43      	adds	r3, r0, #1
 8018558:	89a3      	ldrh	r3, [r4, #12]
 801855a:	d106      	bne.n	801856a <__sflush_r+0x62>
 801855c:	6829      	ldr	r1, [r5, #0]
 801855e:	291d      	cmp	r1, #29
 8018560:	d82b      	bhi.n	80185ba <__sflush_r+0xb2>
 8018562:	4a2a      	ldr	r2, [pc, #168]	@ (801860c <__sflush_r+0x104>)
 8018564:	410a      	asrs	r2, r1
 8018566:	07d6      	lsls	r6, r2, #31
 8018568:	d427      	bmi.n	80185ba <__sflush_r+0xb2>
 801856a:	2200      	movs	r2, #0
 801856c:	6062      	str	r2, [r4, #4]
 801856e:	04d9      	lsls	r1, r3, #19
 8018570:	6922      	ldr	r2, [r4, #16]
 8018572:	6022      	str	r2, [r4, #0]
 8018574:	d504      	bpl.n	8018580 <__sflush_r+0x78>
 8018576:	1c42      	adds	r2, r0, #1
 8018578:	d101      	bne.n	801857e <__sflush_r+0x76>
 801857a:	682b      	ldr	r3, [r5, #0]
 801857c:	b903      	cbnz	r3, 8018580 <__sflush_r+0x78>
 801857e:	6560      	str	r0, [r4, #84]	@ 0x54
 8018580:	6b61      	ldr	r1, [r4, #52]	@ 0x34
 8018582:	602f      	str	r7, [r5, #0]
 8018584:	b1b9      	cbz	r1, 80185b6 <__sflush_r+0xae>
 8018586:	f104 0344 	add.w	r3, r4, #68	@ 0x44
 801858a:	4299      	cmp	r1, r3
 801858c:	d002      	beq.n	8018594 <__sflush_r+0x8c>
 801858e:	4628      	mov	r0, r5
 8018590:	f7ff fbf2 	bl	8017d78 <_free_r>
 8018594:	2300      	movs	r3, #0
 8018596:	6363      	str	r3, [r4, #52]	@ 0x34
 8018598:	e00d      	b.n	80185b6 <__sflush_r+0xae>
 801859a:	2301      	movs	r3, #1
 801859c:	4628      	mov	r0, r5
 801859e:	47b0      	blx	r6
 80185a0:	4602      	mov	r2, r0
 80185a2:	1c50      	adds	r0, r2, #1
 80185a4:	d1c9      	bne.n	801853a <__sflush_r+0x32>
 80185a6:	682b      	ldr	r3, [r5, #0]
 80185a8:	2b00      	cmp	r3, #0
 80185aa:	d0c6      	beq.n	801853a <__sflush_r+0x32>
 80185ac:	2b1d      	cmp	r3, #29
 80185ae:	d001      	beq.n	80185b4 <__sflush_r+0xac>
 80185b0:	2b16      	cmp	r3, #22
 80185b2:	d11e      	bne.n	80185f2 <__sflush_r+0xea>
 80185b4:	602f      	str	r7, [r5, #0]
 80185b6:	2000      	movs	r0, #0
 80185b8:	e022      	b.n	8018600 <__sflush_r+0xf8>
 80185ba:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 80185be:	b21b      	sxth	r3, r3
 80185c0:	e01b      	b.n	80185fa <__sflush_r+0xf2>
 80185c2:	690f      	ldr	r7, [r1, #16]
 80185c4:	2f00      	cmp	r7, #0
 80185c6:	d0f6      	beq.n	80185b6 <__sflush_r+0xae>
 80185c8:	0793      	lsls	r3, r2, #30
 80185ca:	680e      	ldr	r6, [r1, #0]
 80185cc:	bf08      	it	eq
 80185ce:	694b      	ldreq	r3, [r1, #20]
 80185d0:	600f      	str	r7, [r1, #0]
 80185d2:	bf18      	it	ne
 80185d4:	2300      	movne	r3, #0
 80185d6:	eba6 0807 	sub.w	r8, r6, r7
 80185da:	608b      	str	r3, [r1, #8]
 80185dc:	f1b8 0f00 	cmp.w	r8, #0
 80185e0:	dde9      	ble.n	80185b6 <__sflush_r+0xae>
 80185e2:	6a21      	ldr	r1, [r4, #32]
 80185e4:	6aa6      	ldr	r6, [r4, #40]	@ 0x28
 80185e6:	4643      	mov	r3, r8
 80185e8:	463a      	mov	r2, r7
 80185ea:	4628      	mov	r0, r5
 80185ec:	47b0      	blx	r6
 80185ee:	2800      	cmp	r0, #0
 80185f0:	dc08      	bgt.n	8018604 <__sflush_r+0xfc>
 80185f2:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 80185f6:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 80185fa:	81a3      	strh	r3, [r4, #12]
 80185fc:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
 8018600:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8018604:	4407      	add	r7, r0
 8018606:	eba8 0800 	sub.w	r8, r8, r0
 801860a:	e7e7      	b.n	80185dc <__sflush_r+0xd4>
 801860c:	dfbffffe 	.word	0xdfbffffe

08018610 <_fflush_r>:
 8018610:	b538      	push	{r3, r4, r5, lr}
 8018612:	690b      	ldr	r3, [r1, #16]
 8018614:	4605      	mov	r5, r0
 8018616:	460c      	mov	r4, r1
 8018618:	b913      	cbnz	r3, 8018620 <_fflush_r+0x10>
 801861a:	2500      	movs	r5, #0
 801861c:	4628      	mov	r0, r5
 801861e:	bd38      	pop	{r3, r4, r5, pc}
 8018620:	b118      	cbz	r0, 801862a <_fflush_r+0x1a>
 8018622:	6a03      	ldr	r3, [r0, #32]
 8018624:	b90b      	cbnz	r3, 801862a <_fflush_r+0x1a>
 8018626:	f7ff fa3b 	bl	8017aa0 <__sinit>
 801862a:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 801862e:	2b00      	cmp	r3, #0
 8018630:	d0f3      	beq.n	801861a <_fflush_r+0xa>
 8018632:	6e62      	ldr	r2, [r4, #100]	@ 0x64
 8018634:	07d0      	lsls	r0, r2, #31
 8018636:	d404      	bmi.n	8018642 <_fflush_r+0x32>
 8018638:	0599      	lsls	r1, r3, #22
 801863a:	d402      	bmi.n	8018642 <_fflush_r+0x32>
 801863c:	6da0      	ldr	r0, [r4, #88]	@ 0x58
 801863e:	f7ff fb8a 	bl	8017d56 <__retarget_lock_acquire_recursive>
 8018642:	4628      	mov	r0, r5
 8018644:	4621      	mov	r1, r4
 8018646:	f7ff ff5f 	bl	8018508 <__sflush_r>
 801864a:	6e63      	ldr	r3, [r4, #100]	@ 0x64
 801864c:	07da      	lsls	r2, r3, #31
 801864e:	4605      	mov	r5, r0
 8018650:	d4e4      	bmi.n	801861c <_fflush_r+0xc>
 8018652:	89a3      	ldrh	r3, [r4, #12]
 8018654:	059b      	lsls	r3, r3, #22
 8018656:	d4e1      	bmi.n	801861c <_fflush_r+0xc>
 8018658:	6da0      	ldr	r0, [r4, #88]	@ 0x58
 801865a:	f7ff fb7d 	bl	8017d58 <__retarget_lock_release_recursive>
 801865e:	e7dd      	b.n	801861c <_fflush_r+0xc>

08018660 <__swbuf_r>:
 8018660:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8018662:	460e      	mov	r6, r1
 8018664:	4614      	mov	r4, r2
 8018666:	4605      	mov	r5, r0
 8018668:	b118      	cbz	r0, 8018672 <__swbuf_r+0x12>
 801866a:	6a03      	ldr	r3, [r0, #32]
 801866c:	b90b      	cbnz	r3, 8018672 <__swbuf_r+0x12>
 801866e:	f7ff fa17 	bl	8017aa0 <__sinit>
 8018672:	69a3      	ldr	r3, [r4, #24]
 8018674:	60a3      	str	r3, [r4, #8]
 8018676:	89a3      	ldrh	r3, [r4, #12]
 8018678:	071a      	lsls	r2, r3, #28
 801867a:	d501      	bpl.n	8018680 <__swbuf_r+0x20>
 801867c:	6923      	ldr	r3, [r4, #16]
 801867e:	b943      	cbnz	r3, 8018692 <__swbuf_r+0x32>
 8018680:	4621      	mov	r1, r4
 8018682:	4628      	mov	r0, r5
 8018684:	f000 f82a 	bl	80186dc <__swsetup_r>
 8018688:	b118      	cbz	r0, 8018692 <__swbuf_r+0x32>
 801868a:	f04f 37ff 	mov.w	r7, #4294967295	@ 0xffffffff
 801868e:	4638      	mov	r0, r7
 8018690:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 8018692:	6823      	ldr	r3, [r4, #0]
 8018694:	6922      	ldr	r2, [r4, #16]
 8018696:	1a98      	subs	r0, r3, r2
 8018698:	6963      	ldr	r3, [r4, #20]
 801869a:	b2f6      	uxtb	r6, r6
 801869c:	4283      	cmp	r3, r0
 801869e:	4637      	mov	r7, r6
 80186a0:	dc05      	bgt.n	80186ae <__swbuf_r+0x4e>
 80186a2:	4621      	mov	r1, r4
 80186a4:	4628      	mov	r0, r5
 80186a6:	f7ff ffb3 	bl	8018610 <_fflush_r>
 80186aa:	2800      	cmp	r0, #0
 80186ac:	d1ed      	bne.n	801868a <__swbuf_r+0x2a>
 80186ae:	68a3      	ldr	r3, [r4, #8]
 80186b0:	3b01      	subs	r3, #1
 80186b2:	60a3      	str	r3, [r4, #8]
 80186b4:	6823      	ldr	r3, [r4, #0]
 80186b6:	1c5a      	adds	r2, r3, #1
 80186b8:	6022      	str	r2, [r4, #0]
 80186ba:	701e      	strb	r6, [r3, #0]
 80186bc:	6962      	ldr	r2, [r4, #20]
 80186be:	1c43      	adds	r3, r0, #1
 80186c0:	429a      	cmp	r2, r3
 80186c2:	d004      	beq.n	80186ce <__swbuf_r+0x6e>
 80186c4:	89a3      	ldrh	r3, [r4, #12]
 80186c6:	07db      	lsls	r3, r3, #31
 80186c8:	d5e1      	bpl.n	801868e <__swbuf_r+0x2e>
 80186ca:	2e0a      	cmp	r6, #10
 80186cc:	d1df      	bne.n	801868e <__swbuf_r+0x2e>
 80186ce:	4621      	mov	r1, r4
 80186d0:	4628      	mov	r0, r5
 80186d2:	f7ff ff9d 	bl	8018610 <_fflush_r>
 80186d6:	2800      	cmp	r0, #0
 80186d8:	d0d9      	beq.n	801868e <__swbuf_r+0x2e>
 80186da:	e7d6      	b.n	801868a <__swbuf_r+0x2a>

080186dc <__swsetup_r>:
 80186dc:	b538      	push	{r3, r4, r5, lr}
 80186de:	4b29      	ldr	r3, [pc, #164]	@ (8018784 <__swsetup_r+0xa8>)
 80186e0:	4605      	mov	r5, r0
 80186e2:	6818      	ldr	r0, [r3, #0]
 80186e4:	460c      	mov	r4, r1
 80186e6:	b118      	cbz	r0, 80186f0 <__swsetup_r+0x14>
 80186e8:	6a03      	ldr	r3, [r0, #32]
 80186ea:	b90b      	cbnz	r3, 80186f0 <__swsetup_r+0x14>
 80186ec:	f7ff f9d8 	bl	8017aa0 <__sinit>
 80186f0:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 80186f4:	0719      	lsls	r1, r3, #28
 80186f6:	d422      	bmi.n	801873e <__swsetup_r+0x62>
 80186f8:	06da      	lsls	r2, r3, #27
 80186fa:	d407      	bmi.n	801870c <__swsetup_r+0x30>
 80186fc:	2209      	movs	r2, #9
 80186fe:	602a      	str	r2, [r5, #0]
 8018700:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 8018704:	81a3      	strh	r3, [r4, #12]
 8018706:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
 801870a:	e033      	b.n	8018774 <__swsetup_r+0x98>
 801870c:	0758      	lsls	r0, r3, #29
 801870e:	d512      	bpl.n	8018736 <__swsetup_r+0x5a>
 8018710:	6b61      	ldr	r1, [r4, #52]	@ 0x34
 8018712:	b141      	cbz	r1, 8018726 <__swsetup_r+0x4a>
 8018714:	f104 0344 	add.w	r3, r4, #68	@ 0x44
 8018718:	4299      	cmp	r1, r3
 801871a:	d002      	beq.n	8018722 <__swsetup_r+0x46>
 801871c:	4628      	mov	r0, r5
 801871e:	f7ff fb2b 	bl	8017d78 <_free_r>
 8018722:	2300      	movs	r3, #0
 8018724:	6363      	str	r3, [r4, #52]	@ 0x34
 8018726:	89a3      	ldrh	r3, [r4, #12]
 8018728:	f023 0324 	bic.w	r3, r3, #36	@ 0x24
 801872c:	81a3      	strh	r3, [r4, #12]
 801872e:	2300      	movs	r3, #0
 8018730:	6063      	str	r3, [r4, #4]
 8018732:	6923      	ldr	r3, [r4, #16]
 8018734:	6023      	str	r3, [r4, #0]
 8018736:	89a3      	ldrh	r3, [r4, #12]
 8018738:	f043 0308 	orr.w	r3, r3, #8
 801873c:	81a3      	strh	r3, [r4, #12]
 801873e:	6923      	ldr	r3, [r4, #16]
 8018740:	b94b      	cbnz	r3, 8018756 <__swsetup_r+0x7a>
 8018742:	89a3      	ldrh	r3, [r4, #12]
 8018744:	f403 7320 	and.w	r3, r3, #640	@ 0x280
 8018748:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 801874c:	d003      	beq.n	8018756 <__swsetup_r+0x7a>
 801874e:	4621      	mov	r1, r4
 8018750:	4628      	mov	r0, r5
 8018752:	f000 f84f 	bl	80187f4 <__smakebuf_r>
 8018756:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 801875a:	f013 0201 	ands.w	r2, r3, #1
 801875e:	d00a      	beq.n	8018776 <__swsetup_r+0x9a>
 8018760:	2200      	movs	r2, #0
 8018762:	60a2      	str	r2, [r4, #8]
 8018764:	6962      	ldr	r2, [r4, #20]
 8018766:	4252      	negs	r2, r2
 8018768:	61a2      	str	r2, [r4, #24]
 801876a:	6922      	ldr	r2, [r4, #16]
 801876c:	b942      	cbnz	r2, 8018780 <__swsetup_r+0xa4>
 801876e:	f013 0080 	ands.w	r0, r3, #128	@ 0x80
 8018772:	d1c5      	bne.n	8018700 <__swsetup_r+0x24>
 8018774:	bd38      	pop	{r3, r4, r5, pc}
 8018776:	0799      	lsls	r1, r3, #30
 8018778:	bf58      	it	pl
 801877a:	6962      	ldrpl	r2, [r4, #20]
 801877c:	60a2      	str	r2, [r4, #8]
 801877e:	e7f4      	b.n	801876a <__swsetup_r+0x8e>
 8018780:	2000      	movs	r0, #0
 8018782:	e7f7      	b.n	8018774 <__swsetup_r+0x98>
 8018784:	24000054 	.word	0x24000054

08018788 <_sbrk_r>:
 8018788:	b538      	push	{r3, r4, r5, lr}
 801878a:	4d06      	ldr	r5, [pc, #24]	@ (80187a4 <_sbrk_r+0x1c>)
 801878c:	2300      	movs	r3, #0
 801878e:	4604      	mov	r4, r0
 8018790:	4608      	mov	r0, r1
 8018792:	602b      	str	r3, [r5, #0]
 8018794:	f7eb fc84 	bl	80040a0 <_sbrk>
 8018798:	1c43      	adds	r3, r0, #1
 801879a:	d102      	bne.n	80187a2 <_sbrk_r+0x1a>
 801879c:	682b      	ldr	r3, [r5, #0]
 801879e:	b103      	cbz	r3, 80187a2 <_sbrk_r+0x1a>
 80187a0:	6023      	str	r3, [r4, #0]
 80187a2:	bd38      	pop	{r3, r4, r5, pc}
 80187a4:	24012dd0 	.word	0x24012dd0

080187a8 <__swhatbuf_r>:
 80187a8:	b570      	push	{r4, r5, r6, lr}
 80187aa:	460c      	mov	r4, r1
 80187ac:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80187b0:	2900      	cmp	r1, #0
 80187b2:	b096      	sub	sp, #88	@ 0x58
 80187b4:	4615      	mov	r5, r2
 80187b6:	461e      	mov	r6, r3
 80187b8:	da0d      	bge.n	80187d6 <__swhatbuf_r+0x2e>
 80187ba:	89a3      	ldrh	r3, [r4, #12]
 80187bc:	f013 0f80 	tst.w	r3, #128	@ 0x80
 80187c0:	f04f 0100 	mov.w	r1, #0
 80187c4:	bf14      	ite	ne
 80187c6:	2340      	movne	r3, #64	@ 0x40
 80187c8:	f44f 6380 	moveq.w	r3, #1024	@ 0x400
 80187cc:	2000      	movs	r0, #0
 80187ce:	6031      	str	r1, [r6, #0]
 80187d0:	602b      	str	r3, [r5, #0]
 80187d2:	b016      	add	sp, #88	@ 0x58
 80187d4:	bd70      	pop	{r4, r5, r6, pc}
 80187d6:	466a      	mov	r2, sp
 80187d8:	f000 f848 	bl	801886c <_fstat_r>
 80187dc:	2800      	cmp	r0, #0
 80187de:	dbec      	blt.n	80187ba <__swhatbuf_r+0x12>
 80187e0:	9901      	ldr	r1, [sp, #4]
 80187e2:	f401 4170 	and.w	r1, r1, #61440	@ 0xf000
 80187e6:	f5a1 5300 	sub.w	r3, r1, #8192	@ 0x2000
 80187ea:	4259      	negs	r1, r3
 80187ec:	4159      	adcs	r1, r3
 80187ee:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 80187f2:	e7eb      	b.n	80187cc <__swhatbuf_r+0x24>

080187f4 <__smakebuf_r>:
 80187f4:	898b      	ldrh	r3, [r1, #12]
 80187f6:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
 80187f8:	079d      	lsls	r5, r3, #30
 80187fa:	4606      	mov	r6, r0
 80187fc:	460c      	mov	r4, r1
 80187fe:	d507      	bpl.n	8018810 <__smakebuf_r+0x1c>
 8018800:	f104 0347 	add.w	r3, r4, #71	@ 0x47
 8018804:	6023      	str	r3, [r4, #0]
 8018806:	6123      	str	r3, [r4, #16]
 8018808:	2301      	movs	r3, #1
 801880a:	6163      	str	r3, [r4, #20]
 801880c:	b003      	add	sp, #12
 801880e:	bdf0      	pop	{r4, r5, r6, r7, pc}
 8018810:	ab01      	add	r3, sp, #4
 8018812:	466a      	mov	r2, sp
 8018814:	f7ff ffc8 	bl	80187a8 <__swhatbuf_r>
 8018818:	9f00      	ldr	r7, [sp, #0]
 801881a:	4605      	mov	r5, r0
 801881c:	4639      	mov	r1, r7
 801881e:	4630      	mov	r0, r6
 8018820:	f7ff fb16 	bl	8017e50 <_malloc_r>
 8018824:	b948      	cbnz	r0, 801883a <__smakebuf_r+0x46>
 8018826:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 801882a:	059a      	lsls	r2, r3, #22
 801882c:	d4ee      	bmi.n	801880c <__smakebuf_r+0x18>
 801882e:	f023 0303 	bic.w	r3, r3, #3
 8018832:	f043 0302 	orr.w	r3, r3, #2
 8018836:	81a3      	strh	r3, [r4, #12]
 8018838:	e7e2      	b.n	8018800 <__smakebuf_r+0xc>
 801883a:	89a3      	ldrh	r3, [r4, #12]
 801883c:	6020      	str	r0, [r4, #0]
 801883e:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 8018842:	81a3      	strh	r3, [r4, #12]
 8018844:	9b01      	ldr	r3, [sp, #4]
 8018846:	e9c4 0704 	strd	r0, r7, [r4, #16]
 801884a:	b15b      	cbz	r3, 8018864 <__smakebuf_r+0x70>
 801884c:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 8018850:	4630      	mov	r0, r6
 8018852:	f000 f81d 	bl	8018890 <_isatty_r>
 8018856:	b128      	cbz	r0, 8018864 <__smakebuf_r+0x70>
 8018858:	89a3      	ldrh	r3, [r4, #12]
 801885a:	f023 0303 	bic.w	r3, r3, #3
 801885e:	f043 0301 	orr.w	r3, r3, #1
 8018862:	81a3      	strh	r3, [r4, #12]
 8018864:	89a3      	ldrh	r3, [r4, #12]
 8018866:	431d      	orrs	r5, r3
 8018868:	81a5      	strh	r5, [r4, #12]
 801886a:	e7cf      	b.n	801880c <__smakebuf_r+0x18>

0801886c <_fstat_r>:
 801886c:	b538      	push	{r3, r4, r5, lr}
 801886e:	4d07      	ldr	r5, [pc, #28]	@ (801888c <_fstat_r+0x20>)
 8018870:	2300      	movs	r3, #0
 8018872:	4604      	mov	r4, r0
 8018874:	4608      	mov	r0, r1
 8018876:	4611      	mov	r1, r2
 8018878:	602b      	str	r3, [r5, #0]
 801887a:	f7eb fbe8 	bl	800404e <_fstat>
 801887e:	1c43      	adds	r3, r0, #1
 8018880:	d102      	bne.n	8018888 <_fstat_r+0x1c>
 8018882:	682b      	ldr	r3, [r5, #0]
 8018884:	b103      	cbz	r3, 8018888 <_fstat_r+0x1c>
 8018886:	6023      	str	r3, [r4, #0]
 8018888:	bd38      	pop	{r3, r4, r5, pc}
 801888a:	bf00      	nop
 801888c:	24012dd0 	.word	0x24012dd0

08018890 <_isatty_r>:
 8018890:	b538      	push	{r3, r4, r5, lr}
 8018892:	4d06      	ldr	r5, [pc, #24]	@ (80188ac <_isatty_r+0x1c>)
 8018894:	2300      	movs	r3, #0
 8018896:	4604      	mov	r4, r0
 8018898:	4608      	mov	r0, r1
 801889a:	602b      	str	r3, [r5, #0]
 801889c:	f7eb fbe7 	bl	800406e <_isatty>
 80188a0:	1c43      	adds	r3, r0, #1
 80188a2:	d102      	bne.n	80188aa <_isatty_r+0x1a>
 80188a4:	682b      	ldr	r3, [r5, #0]
 80188a6:	b103      	cbz	r3, 80188aa <_isatty_r+0x1a>
 80188a8:	6023      	str	r3, [r4, #0]
 80188aa:	bd38      	pop	{r3, r4, r5, pc}
 80188ac:	24012dd0 	.word	0x24012dd0

080188b0 <_init>:
 80188b0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80188b2:	bf00      	nop
 80188b4:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80188b6:	bc08      	pop	{r3}
 80188b8:	469e      	mov	lr, r3
 80188ba:	4770      	bx	lr

080188bc <_fini>:
 80188bc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80188be:	bf00      	nop
 80188c0:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80188c2:	bc08      	pop	{r3}
 80188c4:	469e      	mov	lr, r3
 80188c6:	4770      	bx	lr