OZE_Sensor.list 1.7 MB

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  1. OZE_Sensor.elf: file format elf32-littlearm
  2. Sections:
  3. Idx Name Size VMA LMA File off Algn
  4. 0 .isr_vector 00000298 08000000 08000000 00001000 2**0
  5. CONTENTS, ALLOC, LOAD, READONLY, DATA
  6. 1 .text 000116ac 080002a0 080002a0 000012a0 2**4
  7. CONTENTS, ALLOC, LOAD, READONLY, CODE
  8. 2 .rodata 00000498 08011950 08011950 00012950 2**3
  9. CONTENTS, ALLOC, LOAD, READONLY, DATA
  10. 3 .ARM 00000008 08011de8 08011de8 00012de8 2**2
  11. CONTENTS, ALLOC, LOAD, READONLY, DATA
  12. 4 .init_array 00000004 08011df0 08011df0 00012df0 2**2
  13. CONTENTS, ALLOC, LOAD, READONLY, DATA
  14. 5 .fini_array 00000004 08011df4 08011df4 00012df4 2**2
  15. CONTENTS, ALLOC, LOAD, READONLY, DATA
  16. 6 .data 00000210 24000000 08011df8 00013000 2**2
  17. CONTENTS, ALLOC, LOAD, DATA
  18. 7 .bss 000130c4 24000220 08012008 00013220 2**5
  19. ALLOC
  20. 8 ._user_heap_stack 00000604 240132e4 08012008 000132e4 2**0
  21. ALLOC
  22. 9 .ARM.attributes 0000002e 00000000 00000000 00013210 2**0
  23. CONTENTS, READONLY
  24. 10 .debug_info 0004a7ba 00000000 00000000 0001323e 2**0
  25. CONTENTS, READONLY, DEBUGGING, OCTETS
  26. 11 .debug_abbrev 00007f45 00000000 00000000 0005d9f8 2**0
  27. CONTENTS, READONLY, DEBUGGING, OCTETS
  28. 12 .debug_aranges 00002078 00000000 00000000 00065940 2**3
  29. CONTENTS, READONLY, DEBUGGING, OCTETS
  30. 13 .debug_macro 0004021d 00000000 00000000 000679b8 2**0
  31. CONTENTS, READONLY, DEBUGGING, OCTETS
  32. 14 .debug_line 0004687b 00000000 00000000 000a7bd5 2**0
  33. CONTENTS, READONLY, DEBUGGING, OCTETS
  34. 15 .debug_str 0018947f 00000000 00000000 000ee450 2**0
  35. CONTENTS, READONLY, DEBUGGING, OCTETS
  36. 16 .comment 00000043 00000000 00000000 002778cf 2**0
  37. CONTENTS, READONLY
  38. 17 .debug_rnglists 00003ae7 00000000 00000000 00277912 2**0
  39. CONTENTS, READONLY, DEBUGGING, OCTETS
  40. 18 .debug_frame 00007014 00000000 00000000 0027b3fc 2**2
  41. CONTENTS, READONLY, DEBUGGING, OCTETS
  42. 19 .debug_loclists 0001fff2 00000000 00000000 00282410 2**0
  43. CONTENTS, READONLY, DEBUGGING, OCTETS
  44. 20 .debug_line_str 00000066 00000000 00000000 002a2402 2**0
  45. CONTENTS, READONLY, DEBUGGING, OCTETS
  46. Disassembly of section .text:
  47. 080002a0 <__do_global_dtors_aux>:
  48. 80002a0: b510 push {r4, lr}
  49. 80002a2: 4c05 ldr r4, [pc, #20] @ (80002b8 <__do_global_dtors_aux+0x18>)
  50. 80002a4: 7823 ldrb r3, [r4, #0]
  51. 80002a6: b933 cbnz r3, 80002b6 <__do_global_dtors_aux+0x16>
  52. 80002a8: 4b04 ldr r3, [pc, #16] @ (80002bc <__do_global_dtors_aux+0x1c>)
  53. 80002aa: b113 cbz r3, 80002b2 <__do_global_dtors_aux+0x12>
  54. 80002ac: 4804 ldr r0, [pc, #16] @ (80002c0 <__do_global_dtors_aux+0x20>)
  55. 80002ae: f3af 8000 nop.w
  56. 80002b2: 2301 movs r3, #1
  57. 80002b4: 7023 strb r3, [r4, #0]
  58. 80002b6: bd10 pop {r4, pc}
  59. 80002b8: 24000220 .word 0x24000220
  60. 80002bc: 00000000 .word 0x00000000
  61. 80002c0: 08011934 .word 0x08011934
  62. 080002c4 <frame_dummy>:
  63. 80002c4: b508 push {r3, lr}
  64. 80002c6: 4b03 ldr r3, [pc, #12] @ (80002d4 <frame_dummy+0x10>)
  65. 80002c8: b11b cbz r3, 80002d2 <frame_dummy+0xe>
  66. 80002ca: 4903 ldr r1, [pc, #12] @ (80002d8 <frame_dummy+0x14>)
  67. 80002cc: 4803 ldr r0, [pc, #12] @ (80002dc <frame_dummy+0x18>)
  68. 80002ce: f3af 8000 nop.w
  69. 80002d2: bd08 pop {r3, pc}
  70. 80002d4: 00000000 .word 0x00000000
  71. 80002d8: 24000224 .word 0x24000224
  72. 80002dc: 08011934 .word 0x08011934
  73. 080002e0 <memchr>:
  74. 80002e0: f001 01ff and.w r1, r1, #255 @ 0xff
  75. 80002e4: 2a10 cmp r2, #16
  76. 80002e6: db2b blt.n 8000340 <memchr+0x60>
  77. 80002e8: f010 0f07 tst.w r0, #7
  78. 80002ec: d008 beq.n 8000300 <memchr+0x20>
  79. 80002ee: f810 3b01 ldrb.w r3, [r0], #1
  80. 80002f2: 3a01 subs r2, #1
  81. 80002f4: 428b cmp r3, r1
  82. 80002f6: d02d beq.n 8000354 <memchr+0x74>
  83. 80002f8: f010 0f07 tst.w r0, #7
  84. 80002fc: b342 cbz r2, 8000350 <memchr+0x70>
  85. 80002fe: d1f6 bne.n 80002ee <memchr+0xe>
  86. 8000300: b4f0 push {r4, r5, r6, r7}
  87. 8000302: ea41 2101 orr.w r1, r1, r1, lsl #8
  88. 8000306: ea41 4101 orr.w r1, r1, r1, lsl #16
  89. 800030a: f022 0407 bic.w r4, r2, #7
  90. 800030e: f07f 0700 mvns.w r7, #0
  91. 8000312: 2300 movs r3, #0
  92. 8000314: e8f0 5602 ldrd r5, r6, [r0], #8
  93. 8000318: 3c08 subs r4, #8
  94. 800031a: ea85 0501 eor.w r5, r5, r1
  95. 800031e: ea86 0601 eor.w r6, r6, r1
  96. 8000322: fa85 f547 uadd8 r5, r5, r7
  97. 8000326: faa3 f587 sel r5, r3, r7
  98. 800032a: fa86 f647 uadd8 r6, r6, r7
  99. 800032e: faa5 f687 sel r6, r5, r7
  100. 8000332: b98e cbnz r6, 8000358 <memchr+0x78>
  101. 8000334: d1ee bne.n 8000314 <memchr+0x34>
  102. 8000336: bcf0 pop {r4, r5, r6, r7}
  103. 8000338: f001 01ff and.w r1, r1, #255 @ 0xff
  104. 800033c: f002 0207 and.w r2, r2, #7
  105. 8000340: b132 cbz r2, 8000350 <memchr+0x70>
  106. 8000342: f810 3b01 ldrb.w r3, [r0], #1
  107. 8000346: 3a01 subs r2, #1
  108. 8000348: ea83 0301 eor.w r3, r3, r1
  109. 800034c: b113 cbz r3, 8000354 <memchr+0x74>
  110. 800034e: d1f8 bne.n 8000342 <memchr+0x62>
  111. 8000350: 2000 movs r0, #0
  112. 8000352: 4770 bx lr
  113. 8000354: 3801 subs r0, #1
  114. 8000356: 4770 bx lr
  115. 8000358: 2d00 cmp r5, #0
  116. 800035a: bf06 itte eq
  117. 800035c: 4635 moveq r5, r6
  118. 800035e: 3803 subeq r0, #3
  119. 8000360: 3807 subne r0, #7
  120. 8000362: f015 0f01 tst.w r5, #1
  121. 8000366: d107 bne.n 8000378 <memchr+0x98>
  122. 8000368: 3001 adds r0, #1
  123. 800036a: f415 7f80 tst.w r5, #256 @ 0x100
  124. 800036e: bf02 ittt eq
  125. 8000370: 3001 addeq r0, #1
  126. 8000372: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
  127. 8000376: 3001 addeq r0, #1
  128. 8000378: bcf0 pop {r4, r5, r6, r7}
  129. 800037a: 3801 subs r0, #1
  130. 800037c: 4770 bx lr
  131. 800037e: bf00 nop
  132. 08000380 <strlen>:
  133. 8000380: 4603 mov r3, r0
  134. 8000382: f813 2b01 ldrb.w r2, [r3], #1
  135. 8000386: 2a00 cmp r2, #0
  136. 8000388: d1fb bne.n 8000382 <strlen+0x2>
  137. 800038a: 1a18 subs r0, r3, r0
  138. 800038c: 3801 subs r0, #1
  139. 800038e: 4770 bx lr
  140. 08000390 <__aeabi_uldivmod>:
  141. 8000390: b953 cbnz r3, 80003a8 <__aeabi_uldivmod+0x18>
  142. 8000392: b94a cbnz r2, 80003a8 <__aeabi_uldivmod+0x18>
  143. 8000394: 2900 cmp r1, #0
  144. 8000396: bf08 it eq
  145. 8000398: 2800 cmpeq r0, #0
  146. 800039a: bf1c itt ne
  147. 800039c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
  148. 80003a0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
  149. 80003a4: f000 b96a b.w 800067c <__aeabi_idiv0>
  150. 80003a8: f1ad 0c08 sub.w ip, sp, #8
  151. 80003ac: e96d ce04 strd ip, lr, [sp, #-16]!
  152. 80003b0: f000 f806 bl 80003c0 <__udivmoddi4>
  153. 80003b4: f8dd e004 ldr.w lr, [sp, #4]
  154. 80003b8: e9dd 2302 ldrd r2, r3, [sp, #8]
  155. 80003bc: b004 add sp, #16
  156. 80003be: 4770 bx lr
  157. 080003c0 <__udivmoddi4>:
  158. 80003c0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  159. 80003c4: 9d08 ldr r5, [sp, #32]
  160. 80003c6: 460c mov r4, r1
  161. 80003c8: 2b00 cmp r3, #0
  162. 80003ca: d14e bne.n 800046a <__udivmoddi4+0xaa>
  163. 80003cc: 4694 mov ip, r2
  164. 80003ce: 458c cmp ip, r1
  165. 80003d0: 4686 mov lr, r0
  166. 80003d2: fab2 f282 clz r2, r2
  167. 80003d6: d962 bls.n 800049e <__udivmoddi4+0xde>
  168. 80003d8: b14a cbz r2, 80003ee <__udivmoddi4+0x2e>
  169. 80003da: f1c2 0320 rsb r3, r2, #32
  170. 80003de: 4091 lsls r1, r2
  171. 80003e0: fa20 f303 lsr.w r3, r0, r3
  172. 80003e4: fa0c fc02 lsl.w ip, ip, r2
  173. 80003e8: 4319 orrs r1, r3
  174. 80003ea: fa00 fe02 lsl.w lr, r0, r2
  175. 80003ee: ea4f 471c mov.w r7, ip, lsr #16
  176. 80003f2: fa1f f68c uxth.w r6, ip
  177. 80003f6: fbb1 f4f7 udiv r4, r1, r7
  178. 80003fa: ea4f 431e mov.w r3, lr, lsr #16
  179. 80003fe: fb07 1114 mls r1, r7, r4, r1
  180. 8000402: ea43 4301 orr.w r3, r3, r1, lsl #16
  181. 8000406: fb04 f106 mul.w r1, r4, r6
  182. 800040a: 4299 cmp r1, r3
  183. 800040c: d90a bls.n 8000424 <__udivmoddi4+0x64>
  184. 800040e: eb1c 0303 adds.w r3, ip, r3
  185. 8000412: f104 30ff add.w r0, r4, #4294967295 @ 0xffffffff
  186. 8000416: f080 8112 bcs.w 800063e <__udivmoddi4+0x27e>
  187. 800041a: 4299 cmp r1, r3
  188. 800041c: f240 810f bls.w 800063e <__udivmoddi4+0x27e>
  189. 8000420: 3c02 subs r4, #2
  190. 8000422: 4463 add r3, ip
  191. 8000424: 1a59 subs r1, r3, r1
  192. 8000426: fa1f f38e uxth.w r3, lr
  193. 800042a: fbb1 f0f7 udiv r0, r1, r7
  194. 800042e: fb07 1110 mls r1, r7, r0, r1
  195. 8000432: ea43 4301 orr.w r3, r3, r1, lsl #16
  196. 8000436: fb00 f606 mul.w r6, r0, r6
  197. 800043a: 429e cmp r6, r3
  198. 800043c: d90a bls.n 8000454 <__udivmoddi4+0x94>
  199. 800043e: eb1c 0303 adds.w r3, ip, r3
  200. 8000442: f100 31ff add.w r1, r0, #4294967295 @ 0xffffffff
  201. 8000446: f080 80fc bcs.w 8000642 <__udivmoddi4+0x282>
  202. 800044a: 429e cmp r6, r3
  203. 800044c: f240 80f9 bls.w 8000642 <__udivmoddi4+0x282>
  204. 8000450: 4463 add r3, ip
  205. 8000452: 3802 subs r0, #2
  206. 8000454: 1b9b subs r3, r3, r6
  207. 8000456: ea40 4004 orr.w r0, r0, r4, lsl #16
  208. 800045a: 2100 movs r1, #0
  209. 800045c: b11d cbz r5, 8000466 <__udivmoddi4+0xa6>
  210. 800045e: 40d3 lsrs r3, r2
  211. 8000460: 2200 movs r2, #0
  212. 8000462: e9c5 3200 strd r3, r2, [r5]
  213. 8000466: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  214. 800046a: 428b cmp r3, r1
  215. 800046c: d905 bls.n 800047a <__udivmoddi4+0xba>
  216. 800046e: b10d cbz r5, 8000474 <__udivmoddi4+0xb4>
  217. 8000470: e9c5 0100 strd r0, r1, [r5]
  218. 8000474: 2100 movs r1, #0
  219. 8000476: 4608 mov r0, r1
  220. 8000478: e7f5 b.n 8000466 <__udivmoddi4+0xa6>
  221. 800047a: fab3 f183 clz r1, r3
  222. 800047e: 2900 cmp r1, #0
  223. 8000480: d146 bne.n 8000510 <__udivmoddi4+0x150>
  224. 8000482: 42a3 cmp r3, r4
  225. 8000484: d302 bcc.n 800048c <__udivmoddi4+0xcc>
  226. 8000486: 4290 cmp r0, r2
  227. 8000488: f0c0 80f0 bcc.w 800066c <__udivmoddi4+0x2ac>
  228. 800048c: 1a86 subs r6, r0, r2
  229. 800048e: eb64 0303 sbc.w r3, r4, r3
  230. 8000492: 2001 movs r0, #1
  231. 8000494: 2d00 cmp r5, #0
  232. 8000496: d0e6 beq.n 8000466 <__udivmoddi4+0xa6>
  233. 8000498: e9c5 6300 strd r6, r3, [r5]
  234. 800049c: e7e3 b.n 8000466 <__udivmoddi4+0xa6>
  235. 800049e: 2a00 cmp r2, #0
  236. 80004a0: f040 8090 bne.w 80005c4 <__udivmoddi4+0x204>
  237. 80004a4: eba1 040c sub.w r4, r1, ip
  238. 80004a8: ea4f 481c mov.w r8, ip, lsr #16
  239. 80004ac: fa1f f78c uxth.w r7, ip
  240. 80004b0: 2101 movs r1, #1
  241. 80004b2: fbb4 f6f8 udiv r6, r4, r8
  242. 80004b6: ea4f 431e mov.w r3, lr, lsr #16
  243. 80004ba: fb08 4416 mls r4, r8, r6, r4
  244. 80004be: ea43 4304 orr.w r3, r3, r4, lsl #16
  245. 80004c2: fb07 f006 mul.w r0, r7, r6
  246. 80004c6: 4298 cmp r0, r3
  247. 80004c8: d908 bls.n 80004dc <__udivmoddi4+0x11c>
  248. 80004ca: eb1c 0303 adds.w r3, ip, r3
  249. 80004ce: f106 34ff add.w r4, r6, #4294967295 @ 0xffffffff
  250. 80004d2: d202 bcs.n 80004da <__udivmoddi4+0x11a>
  251. 80004d4: 4298 cmp r0, r3
  252. 80004d6: f200 80cd bhi.w 8000674 <__udivmoddi4+0x2b4>
  253. 80004da: 4626 mov r6, r4
  254. 80004dc: 1a1c subs r4, r3, r0
  255. 80004de: fa1f f38e uxth.w r3, lr
  256. 80004e2: fbb4 f0f8 udiv r0, r4, r8
  257. 80004e6: fb08 4410 mls r4, r8, r0, r4
  258. 80004ea: ea43 4304 orr.w r3, r3, r4, lsl #16
  259. 80004ee: fb00 f707 mul.w r7, r0, r7
  260. 80004f2: 429f cmp r7, r3
  261. 80004f4: d908 bls.n 8000508 <__udivmoddi4+0x148>
  262. 80004f6: eb1c 0303 adds.w r3, ip, r3
  263. 80004fa: f100 34ff add.w r4, r0, #4294967295 @ 0xffffffff
  264. 80004fe: d202 bcs.n 8000506 <__udivmoddi4+0x146>
  265. 8000500: 429f cmp r7, r3
  266. 8000502: f200 80b0 bhi.w 8000666 <__udivmoddi4+0x2a6>
  267. 8000506: 4620 mov r0, r4
  268. 8000508: 1bdb subs r3, r3, r7
  269. 800050a: ea40 4006 orr.w r0, r0, r6, lsl #16
  270. 800050e: e7a5 b.n 800045c <__udivmoddi4+0x9c>
  271. 8000510: f1c1 0620 rsb r6, r1, #32
  272. 8000514: 408b lsls r3, r1
  273. 8000516: fa22 f706 lsr.w r7, r2, r6
  274. 800051a: 431f orrs r7, r3
  275. 800051c: fa20 fc06 lsr.w ip, r0, r6
  276. 8000520: fa04 f301 lsl.w r3, r4, r1
  277. 8000524: ea43 030c orr.w r3, r3, ip
  278. 8000528: 40f4 lsrs r4, r6
  279. 800052a: fa00 f801 lsl.w r8, r0, r1
  280. 800052e: 0c38 lsrs r0, r7, #16
  281. 8000530: ea4f 4913 mov.w r9, r3, lsr #16
  282. 8000534: fbb4 fef0 udiv lr, r4, r0
  283. 8000538: fa1f fc87 uxth.w ip, r7
  284. 800053c: fb00 441e mls r4, r0, lr, r4
  285. 8000540: ea49 4404 orr.w r4, r9, r4, lsl #16
  286. 8000544: fb0e f90c mul.w r9, lr, ip
  287. 8000548: 45a1 cmp r9, r4
  288. 800054a: fa02 f201 lsl.w r2, r2, r1
  289. 800054e: d90a bls.n 8000566 <__udivmoddi4+0x1a6>
  290. 8000550: 193c adds r4, r7, r4
  291. 8000552: f10e 3aff add.w sl, lr, #4294967295 @ 0xffffffff
  292. 8000556: f080 8084 bcs.w 8000662 <__udivmoddi4+0x2a2>
  293. 800055a: 45a1 cmp r9, r4
  294. 800055c: f240 8081 bls.w 8000662 <__udivmoddi4+0x2a2>
  295. 8000560: f1ae 0e02 sub.w lr, lr, #2
  296. 8000564: 443c add r4, r7
  297. 8000566: eba4 0409 sub.w r4, r4, r9
  298. 800056a: fa1f f983 uxth.w r9, r3
  299. 800056e: fbb4 f3f0 udiv r3, r4, r0
  300. 8000572: fb00 4413 mls r4, r0, r3, r4
  301. 8000576: ea49 4404 orr.w r4, r9, r4, lsl #16
  302. 800057a: fb03 fc0c mul.w ip, r3, ip
  303. 800057e: 45a4 cmp ip, r4
  304. 8000580: d907 bls.n 8000592 <__udivmoddi4+0x1d2>
  305. 8000582: 193c adds r4, r7, r4
  306. 8000584: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff
  307. 8000588: d267 bcs.n 800065a <__udivmoddi4+0x29a>
  308. 800058a: 45a4 cmp ip, r4
  309. 800058c: d965 bls.n 800065a <__udivmoddi4+0x29a>
  310. 800058e: 3b02 subs r3, #2
  311. 8000590: 443c add r4, r7
  312. 8000592: ea43 400e orr.w r0, r3, lr, lsl #16
  313. 8000596: fba0 9302 umull r9, r3, r0, r2
  314. 800059a: eba4 040c sub.w r4, r4, ip
  315. 800059e: 429c cmp r4, r3
  316. 80005a0: 46ce mov lr, r9
  317. 80005a2: 469c mov ip, r3
  318. 80005a4: d351 bcc.n 800064a <__udivmoddi4+0x28a>
  319. 80005a6: d04e beq.n 8000646 <__udivmoddi4+0x286>
  320. 80005a8: b155 cbz r5, 80005c0 <__udivmoddi4+0x200>
  321. 80005aa: ebb8 030e subs.w r3, r8, lr
  322. 80005ae: eb64 040c sbc.w r4, r4, ip
  323. 80005b2: fa04 f606 lsl.w r6, r4, r6
  324. 80005b6: 40cb lsrs r3, r1
  325. 80005b8: 431e orrs r6, r3
  326. 80005ba: 40cc lsrs r4, r1
  327. 80005bc: e9c5 6400 strd r6, r4, [r5]
  328. 80005c0: 2100 movs r1, #0
  329. 80005c2: e750 b.n 8000466 <__udivmoddi4+0xa6>
  330. 80005c4: f1c2 0320 rsb r3, r2, #32
  331. 80005c8: fa20 f103 lsr.w r1, r0, r3
  332. 80005cc: fa0c fc02 lsl.w ip, ip, r2
  333. 80005d0: fa24 f303 lsr.w r3, r4, r3
  334. 80005d4: 4094 lsls r4, r2
  335. 80005d6: 430c orrs r4, r1
  336. 80005d8: ea4f 481c mov.w r8, ip, lsr #16
  337. 80005dc: fa00 fe02 lsl.w lr, r0, r2
  338. 80005e0: fa1f f78c uxth.w r7, ip
  339. 80005e4: fbb3 f0f8 udiv r0, r3, r8
  340. 80005e8: fb08 3110 mls r1, r8, r0, r3
  341. 80005ec: 0c23 lsrs r3, r4, #16
  342. 80005ee: ea43 4301 orr.w r3, r3, r1, lsl #16
  343. 80005f2: fb00 f107 mul.w r1, r0, r7
  344. 80005f6: 4299 cmp r1, r3
  345. 80005f8: d908 bls.n 800060c <__udivmoddi4+0x24c>
  346. 80005fa: eb1c 0303 adds.w r3, ip, r3
  347. 80005fe: f100 36ff add.w r6, r0, #4294967295 @ 0xffffffff
  348. 8000602: d22c bcs.n 800065e <__udivmoddi4+0x29e>
  349. 8000604: 4299 cmp r1, r3
  350. 8000606: d92a bls.n 800065e <__udivmoddi4+0x29e>
  351. 8000608: 3802 subs r0, #2
  352. 800060a: 4463 add r3, ip
  353. 800060c: 1a5b subs r3, r3, r1
  354. 800060e: b2a4 uxth r4, r4
  355. 8000610: fbb3 f1f8 udiv r1, r3, r8
  356. 8000614: fb08 3311 mls r3, r8, r1, r3
  357. 8000618: ea44 4403 orr.w r4, r4, r3, lsl #16
  358. 800061c: fb01 f307 mul.w r3, r1, r7
  359. 8000620: 42a3 cmp r3, r4
  360. 8000622: d908 bls.n 8000636 <__udivmoddi4+0x276>
  361. 8000624: eb1c 0404 adds.w r4, ip, r4
  362. 8000628: f101 36ff add.w r6, r1, #4294967295 @ 0xffffffff
  363. 800062c: d213 bcs.n 8000656 <__udivmoddi4+0x296>
  364. 800062e: 42a3 cmp r3, r4
  365. 8000630: d911 bls.n 8000656 <__udivmoddi4+0x296>
  366. 8000632: 3902 subs r1, #2
  367. 8000634: 4464 add r4, ip
  368. 8000636: 1ae4 subs r4, r4, r3
  369. 8000638: ea41 4100 orr.w r1, r1, r0, lsl #16
  370. 800063c: e739 b.n 80004b2 <__udivmoddi4+0xf2>
  371. 800063e: 4604 mov r4, r0
  372. 8000640: e6f0 b.n 8000424 <__udivmoddi4+0x64>
  373. 8000642: 4608 mov r0, r1
  374. 8000644: e706 b.n 8000454 <__udivmoddi4+0x94>
  375. 8000646: 45c8 cmp r8, r9
  376. 8000648: d2ae bcs.n 80005a8 <__udivmoddi4+0x1e8>
  377. 800064a: ebb9 0e02 subs.w lr, r9, r2
  378. 800064e: eb63 0c07 sbc.w ip, r3, r7
  379. 8000652: 3801 subs r0, #1
  380. 8000654: e7a8 b.n 80005a8 <__udivmoddi4+0x1e8>
  381. 8000656: 4631 mov r1, r6
  382. 8000658: e7ed b.n 8000636 <__udivmoddi4+0x276>
  383. 800065a: 4603 mov r3, r0
  384. 800065c: e799 b.n 8000592 <__udivmoddi4+0x1d2>
  385. 800065e: 4630 mov r0, r6
  386. 8000660: e7d4 b.n 800060c <__udivmoddi4+0x24c>
  387. 8000662: 46d6 mov lr, sl
  388. 8000664: e77f b.n 8000566 <__udivmoddi4+0x1a6>
  389. 8000666: 4463 add r3, ip
  390. 8000668: 3802 subs r0, #2
  391. 800066a: e74d b.n 8000508 <__udivmoddi4+0x148>
  392. 800066c: 4606 mov r6, r0
  393. 800066e: 4623 mov r3, r4
  394. 8000670: 4608 mov r0, r1
  395. 8000672: e70f b.n 8000494 <__udivmoddi4+0xd4>
  396. 8000674: 3e02 subs r6, #2
  397. 8000676: 4463 add r3, ip
  398. 8000678: e730 b.n 80004dc <__udivmoddi4+0x11c>
  399. 800067a: bf00 nop
  400. 0800067c <__aeabi_idiv0>:
  401. 800067c: 4770 bx lr
  402. 800067e: bf00 nop
  403. 08000680 <vApplicationStackOverflowHook>:
  404. void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
  405. {
  406. /* Run time stack overflow checking is performed if
  407. configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
  408. called if a stack overflow is detected. */
  409. }
  410. 8000680: 4770 bx lr
  411. 8000682: bf00 nop
  412. 08000684 <debugLedTimerCallback>:
  413. /* debugLedTimerCallback function */
  414. void debugLedTimerCallback(void *argument)
  415. {
  416. /* USER CODE BEGIN debugLedTimerCallback */
  417. DbgLEDOff (DBG_LED1);
  418. 8000684: 2010 movs r0, #16
  419. 8000686: f001 bcb1 b.w 8001fec <DbgLEDOff>
  420. 800068a: bf00 nop
  421. 0800068c <fanTimerCallback>:
  422. /* fanTimerCallback function */
  423. void fanTimerCallback(void *argument)
  424. {
  425. /* USER CODE BEGIN fanTimerCallback */
  426. HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_2);
  427. 800068c: 2104 movs r1, #4
  428. 800068e: 4801 ldr r0, [pc, #4] @ (8000694 <fanTimerCallback+0x8>)
  429. 8000690: f009 bbe2 b.w 8009e58 <HAL_TIM_PWM_Stop>
  430. 8000694: 2400054c .word 0x2400054c
  431. 08000698 <motorXTimerCallback>:
  432. /* USER CODE END fanTimerCallback */
  433. }
  434. /* motorXTimerCallback function */
  435. void motorXTimerCallback(void *argument)
  436. {
  437. 8000698: b530 push {r4, r5, lr}
  438. /* USER CODE BEGIN motorXTimerCallback */
  439. MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0);
  440. 800069a: 2400 movs r4, #0
  441. {
  442. 800069c: b083 sub sp, #12
  443. MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0);
  444. 800069e: 4d0a ldr r5, [pc, #40] @ (80006c8 <motorXTimerCallback+0x30>)
  445. 80006a0: 2304 movs r3, #4
  446. 80006a2: 4622 mov r2, r4
  447. 80006a4: 4909 ldr r1, [pc, #36] @ (80006cc <motorXTimerCallback+0x34>)
  448. 80006a6: 4628 mov r0, r5
  449. 80006a8: e9cd 4400 strd r4, r4, [sp]
  450. 80006ac: f001 fe0c bl 80022c8 <MotorAction>
  451. HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1);
  452. 80006b0: 4621 mov r1, r4
  453. 80006b2: 4628 mov r0, r5
  454. 80006b4: f009 fbd0 bl 8009e58 <HAL_TIM_PWM_Stop>
  455. HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2);
  456. 80006b8: 2104 movs r1, #4
  457. 80006ba: 4628 mov r0, r5
  458. /* USER CODE END motorXTimerCallback */
  459. }
  460. 80006bc: b003 add sp, #12
  461. 80006be: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
  462. HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2);
  463. 80006c2: f009 bbc9 b.w 8009e58 <HAL_TIM_PWM_Stop>
  464. 80006c6: bf00 nop
  465. 80006c8: 24000500 .word 0x24000500
  466. 80006cc: 24000290 .word 0x24000290
  467. 080006d0 <motorYTimerCallback>:
  468. /* motorYTimerCallback function */
  469. void motorYTimerCallback(void *argument)
  470. {
  471. 80006d0: b510 push {r4, lr}
  472. /* USER CODE BEGIN motorYTimerCallback */
  473. MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0);
  474. 80006d2: 2000 movs r0, #0
  475. {
  476. 80006d4: b082 sub sp, #8
  477. MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0);
  478. 80006d6: 4c0a ldr r4, [pc, #40] @ (8000700 <motorYTimerCallback+0x30>)
  479. 80006d8: 230c movs r3, #12
  480. 80006da: 2208 movs r2, #8
  481. 80006dc: 4909 ldr r1, [pc, #36] @ (8000704 <motorYTimerCallback+0x34>)
  482. 80006de: e9cd 0000 strd r0, r0, [sp]
  483. 80006e2: 4620 mov r0, r4
  484. 80006e4: f001 fdf0 bl 80022c8 <MotorAction>
  485. HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_3);
  486. 80006e8: 2108 movs r1, #8
  487. 80006ea: 4620 mov r0, r4
  488. 80006ec: f009 fbb4 bl 8009e58 <HAL_TIM_PWM_Stop>
  489. HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4);
  490. 80006f0: 210c movs r1, #12
  491. 80006f2: 4620 mov r0, r4
  492. /* USER CODE END motorYTimerCallback */
  493. }
  494. 80006f4: b002 add sp, #8
  495. 80006f6: e8bd 4010 ldmia.w sp!, {r4, lr}
  496. HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4);
  497. 80006fa: f009 bbad b.w 8009e58 <HAL_TIM_PWM_Stop>
  498. 80006fe: bf00 nop
  499. 8000700: 24000500 .word 0x24000500
  500. 8000704: 24000290 .word 0x24000290
  501. 08000708 <__io_putchar>:
  502. \param [in] ch Character to transmit.
  503. \returns Character to transmit.
  504. */
  505. __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
  506. {
  507. if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
  508. 8000708: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000
  509. 800070c: f8d3 2e80 ldr.w r2, [r3, #3712] @ 0xe80
  510. 8000710: 07d1 lsls r1, r2, #31
  511. 8000712: d503 bpl.n 800071c <__io_putchar+0x14>
  512. ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
  513. 8000714: f8d3 2e00 ldr.w r2, [r3, #3584] @ 0xe00
  514. if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
  515. 8000718: 07d2 lsls r2, r2, #31
  516. 800071a: d401 bmi.n 8000720 <__io_putchar+0x18>
  517. }
  518. 800071c: 4770 bx lr
  519. {
  520. while (ITM->PORT[0U].u32 == 0UL)
  521. {
  522. __NOP();
  523. 800071e: bf00 nop
  524. while (ITM->PORT[0U].u32 == 0UL)
  525. 8000720: 681a ldr r2, [r3, #0]
  526. 8000722: 2a00 cmp r2, #0
  527. 8000724: d0fb beq.n 800071e <__io_putchar+0x16>
  528. }
  529. ITM->PORT[0U].u8 = (uint8_t)ch;
  530. 8000726: b2c3 uxtb r3, r0
  531. 8000728: f04f 4260 mov.w r2, #3758096384 @ 0xe0000000
  532. 800072c: 7013 strb r3, [r2, #0]
  533. 800072e: 4770 bx lr
  534. 08000730 <HAL_GPIO_EXTI_Callback>:
  535. if((GPIO_Pin == GPIO_PIN_14) || (GPIO_Pin == GPIO_PIN_15))
  536. 8000730: f5b0 4f80 cmp.w r0, #16384 @ 0x4000
  537. {
  538. 8000734: b510 push {r4, lr}
  539. 8000736: b082 sub sp, #8
  540. if((GPIO_Pin == GPIO_PIN_14) || (GPIO_Pin == GPIO_PIN_15))
  541. 8000738: d023 beq.n 8000782 <HAL_GPIO_EXTI_Callback+0x52>
  542. 800073a: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
  543. 800073e: d020 beq.n 8000782 <HAL_GPIO_EXTI_Callback+0x52>
  544. else if ((GPIO_Pin == GPIO_PIN_10) || (GPIO_Pin == GPIO_PIN_11))
  545. 8000740: f5b0 6f80 cmp.w r0, #1024 @ 0x400
  546. 8000744: d004 beq.n 8000750 <HAL_GPIO_EXTI_Callback+0x20>
  547. 8000746: f5b0 6f00 cmp.w r0, #2048 @ 0x800
  548. 800074a: d001 beq.n 8000750 <HAL_GPIO_EXTI_Callback+0x20>
  549. }
  550. 800074c: b002 add sp, #8
  551. 800074e: bd10 pop {r4, pc}
  552. uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3;
  553. 8000750: f44f 6100 mov.w r1, #2048 @ 0x800
  554. 8000754: 4811 ldr r0, [pc, #68] @ (800079c <HAL_GPIO_EXTI_Callback+0x6c>)
  555. 8000756: f006 fd2b bl 80071b0 <HAL_GPIO_ReadPin>
  556. 800075a: f44f 6180 mov.w r1, #1024 @ 0x400
  557. 800075e: 4604 mov r4, r0
  558. 8000760: 480e ldr r0, [pc, #56] @ (800079c <HAL_GPIO_EXTI_Callback+0x6c>)
  559. 8000762: f006 fd25 bl 80071b0 <HAL_GPIO_ReadPin>
  560. osMessageQueuePut(encoderYTaskArg.dataQueue, &pinStates, 0, 0);
  561. 8000766: 4a0e ldr r2, [pc, #56] @ (80007a0 <HAL_GPIO_EXTI_Callback+0x70>)
  562. 8000768: 2300 movs r3, #0
  563. uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3;
  564. 800076a: ea40 0444 orr.w r4, r0, r4, lsl #1
  565. osMessageQueuePut(encoderYTaskArg.dataQueue, &pinStates, 0, 0);
  566. 800076e: a901 add r1, sp, #4
  567. 8000770: 6910 ldr r0, [r2, #16]
  568. uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3;
  569. 8000772: f004 0403 and.w r4, r4, #3
  570. osMessageQueuePut(encoderYTaskArg.dataQueue, &pinStates, 0, 0);
  571. 8000776: 461a mov r2, r3
  572. uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3;
  573. 8000778: 9401 str r4, [sp, #4]
  574. osMessageQueuePut(encoderYTaskArg.dataQueue, &pinStates, 0, 0);
  575. 800077a: f00b fbc5 bl 800bf08 <osMessageQueuePut>
  576. }
  577. 800077e: b002 add sp, #8
  578. 8000780: bd10 pop {r4, pc}
  579. uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3;
  580. 8000782: f44f 4100 mov.w r1, #32768 @ 0x8000
  581. 8000786: 4807 ldr r0, [pc, #28] @ (80007a4 <HAL_GPIO_EXTI_Callback+0x74>)
  582. 8000788: f006 fd12 bl 80071b0 <HAL_GPIO_ReadPin>
  583. 800078c: f44f 4180 mov.w r1, #16384 @ 0x4000
  584. 8000790: 4604 mov r4, r0
  585. 8000792: 4804 ldr r0, [pc, #16] @ (80007a4 <HAL_GPIO_EXTI_Callback+0x74>)
  586. 8000794: f006 fd0c bl 80071b0 <HAL_GPIO_ReadPin>
  587. osMessageQueuePut(encoderXTaskArg.dataQueue, &pinStates, 0, 0);
  588. 8000798: 4a03 ldr r2, [pc, #12] @ (80007a8 <HAL_GPIO_EXTI_Callback+0x78>)
  589. 800079a: e7e5 b.n 8000768 <HAL_GPIO_EXTI_Callback+0x38>
  590. 800079c: 58020400 .word 0x58020400
  591. 80007a0: 240008c0 .word 0x240008c0
  592. 80007a4: 58020c00 .word 0x58020c00
  593. 80007a8: 240008e0 .word 0x240008e0
  594. 080007ac <HAL_TIM_PeriodElapsedCallback>:
  595. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
  596. {
  597. /* USER CODE BEGIN Callback 0 */
  598. /* USER CODE END Callback 0 */
  599. if (htim->Instance == TIM6) {
  600. 80007ac: 4a0c ldr r2, [pc, #48] @ (80007e0 <HAL_TIM_PeriodElapsedCallback+0x34>)
  601. 80007ae: 6803 ldr r3, [r0, #0]
  602. 80007b0: 4293 cmp r3, r2
  603. 80007b2: d012 beq.n 80007da <HAL_TIM_PeriodElapsedCallback+0x2e>
  604. HAL_IncTick();
  605. }
  606. /* USER CODE BEGIN Callback 1 */
  607. else if (htim->Instance == TIM4)
  608. 80007b4: 4a0b ldr r2, [pc, #44] @ (80007e4 <HAL_TIM_PeriodElapsedCallback+0x38>)
  609. 80007b6: 4293 cmp r3, r2
  610. 80007b8: d003 beq.n 80007c2 <HAL_TIM_PeriodElapsedCallback+0x16>
  611. {
  612. encoderXChannelA = 0;
  613. encoderXChannelB = 0;
  614. }
  615. else if (htim->Instance == TIM2)
  616. 80007ba: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
  617. 80007be: d006 beq.n 80007ce <HAL_TIM_PeriodElapsedCallback+0x22>
  618. {
  619. encoderYChannelA = 0;
  620. encoderYChannelB = 0;
  621. }
  622. /* USER CODE END Callback 1 */
  623. }
  624. 80007c0: 4770 bx lr
  625. encoderXChannelA = 0;
  626. 80007c2: 2300 movs r3, #0
  627. 80007c4: 4908 ldr r1, [pc, #32] @ (80007e8 <HAL_TIM_PeriodElapsedCallback+0x3c>)
  628. encoderXChannelB = 0;
  629. 80007c6: 4a09 ldr r2, [pc, #36] @ (80007ec <HAL_TIM_PeriodElapsedCallback+0x40>)
  630. encoderXChannelA = 0;
  631. 80007c8: 600b str r3, [r1, #0]
  632. encoderXChannelB = 0;
  633. 80007ca: 6013 str r3, [r2, #0]
  634. 80007cc: 4770 bx lr
  635. encoderYChannelA = 0;
  636. 80007ce: 2300 movs r3, #0
  637. 80007d0: 4907 ldr r1, [pc, #28] @ (80007f0 <HAL_TIM_PeriodElapsedCallback+0x44>)
  638. encoderYChannelB = 0;
  639. 80007d2: 4a08 ldr r2, [pc, #32] @ (80007f4 <HAL_TIM_PeriodElapsedCallback+0x48>)
  640. encoderYChannelA = 0;
  641. 80007d4: 600b str r3, [r1, #0]
  642. encoderYChannelB = 0;
  643. 80007d6: 6013 str r3, [r2, #0]
  644. }
  645. 80007d8: 4770 bx lr
  646. HAL_IncTick();
  647. 80007da: f003 bbed b.w 8003fb8 <HAL_IncTick>
  648. 80007de: bf00 nop
  649. 80007e0: 40001000 .word 0x40001000
  650. 80007e4: 40000800 .word 0x40000800
  651. 80007e8: 2400028c .word 0x2400028c
  652. 80007ec: 24000288 .word 0x24000288
  653. 80007f0: 24000284 .word 0x24000284
  654. 80007f4: 24000280 .word 0x24000280
  655. 080007f8 <Error_Handler>:
  656. \details Disables IRQ interrupts by setting the I-bit in the CPSR.
  657. Can only be executed in Privileged modes.
  658. */
  659. __STATIC_FORCEINLINE void __disable_irq(void)
  660. {
  661. __ASM volatile ("cpsid i" : : : "memory");
  662. 80007f8: b672 cpsid i
  663. \details Acts as a special kind of Data Memory Barrier.
  664. It completes when all explicit memory accesses before this instruction complete.
  665. */
  666. __STATIC_FORCEINLINE void __DSB(void)
  667. {
  668. __ASM volatile ("dsb 0xF":::"memory");
  669. 80007fa: f3bf 8f4f dsb sy
  670. (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
  671. 80007fe: 4905 ldr r1, [pc, #20] @ (8000814 <Error_Handler+0x1c>)
  672. SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  673. 8000800: 4b05 ldr r3, [pc, #20] @ (8000818 <Error_Handler+0x20>)
  674. (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
  675. 8000802: 68ca ldr r2, [r1, #12]
  676. 8000804: f402 62e0 and.w r2, r2, #1792 @ 0x700
  677. SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  678. 8000808: 4313 orrs r3, r2
  679. 800080a: 60cb str r3, [r1, #12]
  680. 800080c: f3bf 8f4f dsb sy
  681. __NOP();
  682. 8000810: bf00 nop
  683. for(;;) /* wait until reset */
  684. 8000812: e7fd b.n 8000810 <Error_Handler+0x18>
  685. 8000814: e000ed00 .word 0xe000ed00
  686. 8000818: 05fa0004 .word 0x05fa0004
  687. 0800081c <SystemClock_Config>:
  688. {
  689. 800081c: b530 push {r4, r5, lr}
  690. 800081e: b09f sub sp, #124 @ 0x7c
  691. RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  692. 8000820: 224c movs r2, #76 @ 0x4c
  693. 8000822: 2100 movs r1, #0
  694. 8000824: a80a add r0, sp, #40 @ 0x28
  695. 8000826: f00f f96f bl 800fb08 <memset>
  696. RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  697. 800082a: 2220 movs r2, #32
  698. 800082c: 2100 movs r1, #0
  699. 800082e: a802 add r0, sp, #8
  700. 8000830: f00f f96a bl 800fb08 <memset>
  701. HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
  702. 8000834: 2002 movs r0, #2
  703. 8000836: f006 fd65 bl 8007304 <HAL_PWREx_ConfigSupply>
  704. __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
  705. 800083a: 4b25 ldr r3, [pc, #148] @ (80008d0 <SystemClock_Config+0xb4>)
  706. 800083c: 2100 movs r1, #0
  707. 800083e: 4a25 ldr r2, [pc, #148] @ (80008d4 <SystemClock_Config+0xb8>)
  708. 8000840: 9101 str r1, [sp, #4]
  709. 8000842: 6ad9 ldr r1, [r3, #44] @ 0x2c
  710. 8000844: f021 0101 bic.w r1, r1, #1
  711. 8000848: 62d9 str r1, [r3, #44] @ 0x2c
  712. 800084a: 6adb ldr r3, [r3, #44] @ 0x2c
  713. 800084c: f003 0301 and.w r3, r3, #1
  714. 8000850: 9301 str r3, [sp, #4]
  715. 8000852: 6993 ldr r3, [r2, #24]
  716. 8000854: f443 4340 orr.w r3, r3, #49152 @ 0xc000
  717. 8000858: 6193 str r3, [r2, #24]
  718. 800085a: 6993 ldr r3, [r2, #24]
  719. 800085c: f403 4340 and.w r3, r3, #49152 @ 0xc000
  720. 8000860: 9301 str r3, [sp, #4]
  721. 8000862: 9b01 ldr r3, [sp, #4]
  722. while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
  723. 8000864: 6993 ldr r3, [r2, #24]
  724. 8000866: 049b lsls r3, r3, #18
  725. 8000868: d5fc bpl.n 8000864 <SystemClock_Config+0x48>
  726. RCC_OscInitStruct.LSIState = RCC_LSI_ON;
  727. 800086a: 2201 movs r2, #1
  728. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_LSI
  729. 800086c: 2029 movs r0, #41 @ 0x29
  730. 800086e: f44f 3180 mov.w r1, #65536 @ 0x10000
  731. RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  732. 8000872: 2402 movs r4, #2
  733. RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
  734. 8000874: 2300 movs r3, #0
  735. RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
  736. 8000876: 2508 movs r5, #8
  737. RCC_OscInitStruct.PLL.PLLP = 2;
  738. 8000878: 9417 str r4, [sp, #92] @ 0x5c
  739. RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
  740. 800087a: 951a str r5, [sp, #104] @ 0x68
  741. RCC_OscInitStruct.LSIState = RCC_LSI_ON;
  742. 800087c: e9cd 220f strd r2, r2, [sp, #60] @ 0x3c
  743. RCC_OscInitStruct.PLL.PLLM = 5;
  744. 8000880: 2205 movs r2, #5
  745. 8000882: 9215 str r2, [sp, #84] @ 0x54
  746. RCC_OscInitStruct.PLL.PLLN = 160;
  747. 8000884: 22a0 movs r2, #160 @ 0xa0
  748. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_LSI
  749. 8000886: e9cd 010a strd r0, r1, [sp, #40] @ 0x28
  750. if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  751. 800088a: a80a add r0, sp, #40 @ 0x28
  752. RCC_OscInitStruct.PLL.PLLN = 160;
  753. 800088c: 9216 str r2, [sp, #88] @ 0x58
  754. RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
  755. 800088e: e9cd 331b strd r3, r3, [sp, #108] @ 0x6c
  756. RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  757. 8000892: e9cd 4413 strd r4, r4, [sp, #76] @ 0x4c
  758. RCC_OscInitStruct.PLL.PLLR = 2;
  759. 8000896: e9cd 4418 strd r4, r4, [sp, #96] @ 0x60
  760. if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  761. 800089a: f006 fe17 bl 80074cc <HAL_RCC_OscConfig>
  762. 800089e: 4603 mov r3, r0
  763. 80008a0: b998 cbnz r0, 80008ca <SystemClock_Config+0xae>
  764. RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
  765. 80008a2: 223f movs r2, #63 @ 0x3f
  766. RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
  767. 80008a4: 9304 str r3, [sp, #16]
  768. RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
  769. 80008a6: 2340 movs r3, #64 @ 0x40
  770. if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
  771. 80008a8: 4621 mov r1, r4
  772. RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
  773. 80008aa: 9202 str r2, [sp, #8]
  774. RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  775. 80008ac: 2203 movs r2, #3
  776. RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
  777. 80008ae: 9307 str r3, [sp, #28]
  778. if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
  779. 80008b0: a802 add r0, sp, #8
  780. RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
  781. 80008b2: 9309 str r3, [sp, #36] @ 0x24
  782. RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  783. 80008b4: 9203 str r2, [sp, #12]
  784. RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
  785. 80008b6: e9cd 5305 strd r5, r3, [sp, #20]
  786. RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
  787. 80008ba: f44f 6380 mov.w r3, #1024 @ 0x400
  788. 80008be: 9308 str r3, [sp, #32]
  789. if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
  790. 80008c0: f007 f984 bl 8007bcc <HAL_RCC_ClockConfig>
  791. 80008c4: b908 cbnz r0, 80008ca <SystemClock_Config+0xae>
  792. }
  793. 80008c6: b01f add sp, #124 @ 0x7c
  794. 80008c8: bd30 pop {r4, r5, pc}
  795. Error_Handler();
  796. 80008ca: f7ff ff95 bl 80007f8 <Error_Handler>
  797. 80008ce: bf00 nop
  798. 80008d0: 58000400 .word 0x58000400
  799. 80008d4: 58024800 .word 0x58024800
  800. 080008d8 <PeriphCommonClock_Config>:
  801. {
  802. 80008d8: b510 push {r4, lr}
  803. 80008da: b0b0 sub sp, #192 @ 0xc0
  804. RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
  805. 80008dc: 22a0 movs r2, #160 @ 0xa0
  806. 80008de: 2100 movs r1, #0
  807. PeriphClkInitStruct.PLL2.PLL2P = 25;
  808. 80008e0: 2419 movs r4, #25
  809. RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
  810. 80008e2: a808 add r0, sp, #32
  811. 80008e4: f00f f910 bl 800fb08 <memset>
  812. PeriphClkInitStruct.PLL2.PLL2M = 5;
  813. 80008e8: 2305 movs r3, #5
  814. PeriphClkInitStruct.PLL2.PLL2N = 90;
  815. 80008ea: 205a movs r0, #90 @ 0x5a
  816. PeriphClkInitStruct.PLL2.PLL2Q = 3;
  817. 80008ec: 2103 movs r1, #3
  818. PeriphClkInitStruct.PLL2.PLL2R = 2;
  819. 80008ee: 2202 movs r2, #2
  820. PeriphClkInitStruct.PLL2.PLL2M = 5;
  821. 80008f0: 9302 str r3, [sp, #8]
  822. PeriphClkInitStruct.PLL2.PLL2R = 2;
  823. 80008f2: 2380 movs r3, #128 @ 0x80
  824. PeriphClkInitStruct.PLL2.PLL2N = 90;
  825. 80008f4: 9003 str r0, [sp, #12]
  826. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
  827. 80008f6: 4668 mov r0, sp
  828. PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  829. 80008f8: ed9f 7b07 vldr d7, [pc, #28] @ 8000918 <PeriphCommonClock_Config+0x40>
  830. PeriphClkInitStruct.PLL2.PLL2Q = 3;
  831. 80008fc: e9cd 4104 strd r4, r1, [sp, #16]
  832. PeriphClkInitStruct.PLL2.PLL2R = 2;
  833. 8000900: e9cd 2306 strd r2, r3, [sp, #24]
  834. PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  835. 8000904: ed8d 7b00 vstr d7, [sp]
  836. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
  837. 8000908: f007 fc6a bl 80081e0 <HAL_RCCEx_PeriphCLKConfig>
  838. 800090c: b908 cbnz r0, 8000912 <PeriphCommonClock_Config+0x3a>
  839. }
  840. 800090e: b030 add sp, #192 @ 0xc0
  841. 8000910: bd10 pop {r4, pc}
  842. Error_Handler();
  843. 8000912: f7ff ff71 bl 80007f8 <Error_Handler>
  844. 8000916: bf00 nop
  845. 8000918: 00080000 .word 0x00080000
  846. 800091c: 00000000 .word 0x00000000
  847. 08000920 <main>:
  848. {
  849. 8000920: e92d 4880 stmdb sp!, {r7, fp, lr}
  850. MPU_Region_InitTypeDef MPU_InitStruct = {0};
  851. 8000924: 2400 movs r4, #0
  852. {
  853. 8000926: b0cf sub sp, #316 @ 0x13c
  854. MPU_InitStruct.Enable = MPU_REGION_ENABLE;
  855. 8000928: 2501 movs r5, #1
  856. MPU_Region_InitTypeDef MPU_InitStruct = {0};
  857. 800092a: e9cd 4443 strd r4, r4, [sp, #268] @ 0x10c
  858. 800092e: e9cd 4445 strd r4, r4, [sp, #276] @ 0x114
  859. HAL_MPU_Disable();
  860. 8000932: f004 fb4b bl 8004fcc <HAL_MPU_Disable>
  861. MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
  862. 8000936: f248 721f movw r2, #34591 @ 0x871f
  863. 800093a: f240 1301 movw r3, #257 @ 0x101
  864. HAL_MPU_ConfigRegion(&MPU_InitStruct);
  865. 800093e: a843 add r0, sp, #268 @ 0x10c
  866. MPU_InitStruct.Enable = MPU_REGION_ENABLE;
  867. 8000940: f8ad 510c strh.w r5, [sp, #268] @ 0x10c
  868. MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
  869. 8000944: 9346 str r3, [sp, #280] @ 0x118
  870. 8000946: e9cd 4244 strd r4, r2, [sp, #272] @ 0x110
  871. HAL_MPU_ConfigRegion(&MPU_InitStruct);
  872. 800094a: f004 fb5d bl 8005008 <HAL_MPU_ConfigRegion>
  873. MPU_InitStruct.BaseAddress = 0x24020000;
  874. 800094e: 4acd ldr r2, [pc, #820] @ (8000c84 <main+0x364>)
  875. MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
  876. 8000950: 4bcd ldr r3, [pc, #820] @ (8000c88 <main+0x368>)
  877. HAL_MPU_ConfigRegion(&MPU_InitStruct);
  878. 8000952: a843 add r0, sp, #268 @ 0x10c
  879. MPU_InitStruct.BaseAddress = 0x24020000;
  880. 8000954: 9244 str r2, [sp, #272] @ 0x110
  881. MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
  882. 8000956: 9345 str r3, [sp, #276] @ 0x114
  883. MPU_InitStruct.Number = MPU_REGION_NUMBER1;
  884. 8000958: f88d 510d strb.w r5, [sp, #269] @ 0x10d
  885. MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
  886. 800095c: f88d 4119 strb.w r4, [sp, #281] @ 0x119
  887. HAL_MPU_ConfigRegion(&MPU_InitStruct);
  888. 8000960: f004 fb52 bl 8005008 <HAL_MPU_ConfigRegion>
  889. MPU_InitStruct.BaseAddress = 0x24040000;
  890. 8000964: 4bc9 ldr r3, [pc, #804] @ (8000c8c <main+0x36c>)
  891. MPU_InitStruct.Number = MPU_REGION_NUMBER2;
  892. 8000966: 2202 movs r2, #2
  893. HAL_MPU_ConfigRegion(&MPU_InitStruct);
  894. 8000968: a843 add r0, sp, #268 @ 0x10c
  895. MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
  896. 800096a: f88d 4116 strb.w r4, [sp, #278] @ 0x116
  897. MPU_InitStruct.BaseAddress = 0x24040000;
  898. 800096e: 9344 str r3, [sp, #272] @ 0x110
  899. MPU_InitStruct.Size = MPU_REGION_SIZE_512B;
  900. 8000970: 2308 movs r3, #8
  901. MPU_InitStruct.Number = MPU_REGION_NUMBER2;
  902. 8000972: f88d 210d strb.w r2, [sp, #269] @ 0x10d
  903. MPU_InitStruct.Size = MPU_REGION_SIZE_512B;
  904. 8000976: f88d 3114 strb.w r3, [sp, #276] @ 0x114
  905. MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
  906. 800097a: f88d 5119 strb.w r5, [sp, #281] @ 0x119
  907. MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
  908. 800097e: f88d 511b strb.w r5, [sp, #283] @ 0x11b
  909. HAL_MPU_ConfigRegion(&MPU_InitStruct);
  910. 8000982: f004 fb41 bl 8005008 <HAL_MPU_ConfigRegion>
  911. HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
  912. 8000986: 2004 movs r0, #4
  913. 8000988: f004 fb2e bl 8004fe8 <HAL_MPU_Enable>
  914. if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
  915. 800098c: 4ac0 ldr r2, [pc, #768] @ (8000c90 <main+0x370>)
  916. 800098e: 6953 ldr r3, [r2, #20]
  917. 8000990: f413 3300 ands.w r3, r3, #131072 @ 0x20000
  918. 8000994: d111 bne.n 80009ba <main+0x9a>
  919. 8000996: f3bf 8f4f dsb sy
  920. __ASM volatile ("isb 0xF":::"memory");
  921. 800099a: f3bf 8f6f isb sy
  922. SCB->ICIALLU = 0UL; /* invalidate I-Cache */
  923. 800099e: f8c2 3250 str.w r3, [r2, #592] @ 0x250
  924. __ASM volatile ("dsb 0xF":::"memory");
  925. 80009a2: f3bf 8f4f dsb sy
  926. __ASM volatile ("isb 0xF":::"memory");
  927. 80009a6: f3bf 8f6f isb sy
  928. SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
  929. 80009aa: 6953 ldr r3, [r2, #20]
  930. 80009ac: f443 3300 orr.w r3, r3, #131072 @ 0x20000
  931. 80009b0: 6153 str r3, [r2, #20]
  932. __ASM volatile ("dsb 0xF":::"memory");
  933. 80009b2: f3bf 8f4f dsb sy
  934. __ASM volatile ("isb 0xF":::"memory");
  935. 80009b6: f3bf 8f6f isb sy
  936. if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
  937. 80009ba: 48b5 ldr r0, [pc, #724] @ (8000c90 <main+0x370>)
  938. 80009bc: 6943 ldr r3, [r0, #20]
  939. 80009be: f413 3380 ands.w r3, r3, #65536 @ 0x10000
  940. 80009c2: d126 bne.n 8000a12 <main+0xf2>
  941. SCB->CSSELR = 0U; /* select Level 1 data cache */
  942. 80009c4: f8c0 3084 str.w r3, [r0, #132] @ 0x84
  943. __ASM volatile ("dsb 0xF":::"memory");
  944. 80009c8: f3bf 8f4f dsb sy
  945. ccsidr = SCB->CCSIDR;
  946. 80009cc: f8d0 4080 ldr.w r4, [r0, #128] @ 0x80
  947. SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
  948. 80009d0: f643 75e0 movw r5, #16352 @ 0x3fe0
  949. sets = (uint32_t)(CCSIDR_SETS(ccsidr));
  950. 80009d4: f3c4 3c4e ubfx ip, r4, #13, #15
  951. ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
  952. 80009d8: f3c4 04c9 ubfx r4, r4, #3, #10
  953. 80009dc: ea4f 1c4c mov.w ip, ip, lsl #5
  954. SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
  955. 80009e0: ea0c 0105 and.w r1, ip, r5
  956. ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
  957. 80009e4: 4623 mov r3, r4
  958. SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
  959. 80009e6: ea41 7283 orr.w r2, r1, r3, lsl #30
  960. } while (ways-- != 0U);
  961. 80009ea: 3b01 subs r3, #1
  962. SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
  963. 80009ec: f8c0 2260 str.w r2, [r0, #608] @ 0x260
  964. } while (ways-- != 0U);
  965. 80009f0: 1c5a adds r2, r3, #1
  966. 80009f2: d1f8 bne.n 80009e6 <main+0xc6>
  967. } while(sets-- != 0U);
  968. 80009f4: f1ac 0c20 sub.w ip, ip, #32
  969. 80009f8: f11c 0f20 cmn.w ip, #32
  970. 80009fc: d1f0 bne.n 80009e0 <main+0xc0>
  971. 80009fe: f3bf 8f4f dsb sy
  972. SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
  973. 8000a02: 6943 ldr r3, [r0, #20]
  974. 8000a04: f443 3380 orr.w r3, r3, #65536 @ 0x10000
  975. 8000a08: 6143 str r3, [r0, #20]
  976. 8000a0a: f3bf 8f4f dsb sy
  977. __ASM volatile ("isb 0xF":::"memory");
  978. 8000a0e: f3bf 8f6f isb sy
  979. __HAL_RCC_GPIOH_CLK_ENABLE();
  980. 8000a12: 4ca0 ldr r4, [pc, #640] @ (8000c94 <main+0x374>)
  981. GPIO_InitTypeDef GPIO_InitStruct = {0};
  982. 8000a14: 2500 movs r5, #0
  983. HAL_Init();
  984. 8000a16: f003 fa9f bl 8003f58 <HAL_Init>
  985. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  986. 8000a1a: 2601 movs r6, #1
  987. SystemClock_Config();
  988. 8000a1c: f7ff fefe bl 800081c <SystemClock_Config>
  989. GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
  990. 8000a20: f44f 1744 mov.w r7, #3211264 @ 0x310000
  991. PeriphCommonClock_Config();
  992. 8000a24: f7ff ff58 bl 80008d8 <PeriphCommonClock_Config>
  993. GPIO_InitTypeDef GPIO_InitStruct = {0};
  994. 8000a28: 9547 str r5, [sp, #284] @ 0x11c
  995. HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
  996. 8000a2a: 462a mov r2, r5
  997. 8000a2c: f24e 7180 movw r1, #59264 @ 0xe780
  998. 8000a30: 4899 ldr r0, [pc, #612] @ (8000c98 <main+0x378>)
  999. GPIO_InitTypeDef GPIO_InitStruct = {0};
  1000. 8000a32: e9cd 5543 strd r5, r5, [sp, #268] @ 0x10c
  1001. 8000a36: e9cd 5545 strd r5, r5, [sp, #276] @ 0x114
  1002. __HAL_RCC_GPIOH_CLK_ENABLE();
  1003. 8000a3a: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0
  1004. 8000a3e: f043 0380 orr.w r3, r3, #128 @ 0x80
  1005. 8000a42: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0
  1006. 8000a46: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0
  1007. 8000a4a: f003 0380 and.w r3, r3, #128 @ 0x80
  1008. 8000a4e: 9301 str r3, [sp, #4]
  1009. 8000a50: 9b01 ldr r3, [sp, #4]
  1010. __HAL_RCC_GPIOC_CLK_ENABLE();
  1011. 8000a52: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0
  1012. 8000a56: f043 0304 orr.w r3, r3, #4
  1013. 8000a5a: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0
  1014. 8000a5e: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0
  1015. 8000a62: f003 0304 and.w r3, r3, #4
  1016. 8000a66: 9302 str r3, [sp, #8]
  1017. 8000a68: 9b02 ldr r3, [sp, #8]
  1018. __HAL_RCC_GPIOA_CLK_ENABLE();
  1019. 8000a6a: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0
  1020. 8000a6e: f043 0301 orr.w r3, r3, #1
  1021. 8000a72: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0
  1022. 8000a76: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0
  1023. 8000a7a: f003 0301 and.w r3, r3, #1
  1024. 8000a7e: 9303 str r3, [sp, #12]
  1025. 8000a80: 9b03 ldr r3, [sp, #12]
  1026. __HAL_RCC_GPIOB_CLK_ENABLE();
  1027. 8000a82: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0
  1028. 8000a86: f043 0302 orr.w r3, r3, #2
  1029. 8000a8a: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0
  1030. 8000a8e: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0
  1031. 8000a92: f003 0302 and.w r3, r3, #2
  1032. 8000a96: 9304 str r3, [sp, #16]
  1033. 8000a98: 9b04 ldr r3, [sp, #16]
  1034. __HAL_RCC_GPIOE_CLK_ENABLE();
  1035. 8000a9a: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0
  1036. 8000a9e: f043 0310 orr.w r3, r3, #16
  1037. 8000aa2: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0
  1038. 8000aa6: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0
  1039. 8000aaa: f003 0310 and.w r3, r3, #16
  1040. 8000aae: 9305 str r3, [sp, #20]
  1041. 8000ab0: 9b05 ldr r3, [sp, #20]
  1042. __HAL_RCC_GPIOD_CLK_ENABLE();
  1043. 8000ab2: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0
  1044. 8000ab6: f043 0308 orr.w r3, r3, #8
  1045. 8000aba: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0
  1046. 8000abe: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0
  1047. 8000ac2: f003 0308 and.w r3, r3, #8
  1048. 8000ac6: 9306 str r3, [sp, #24]
  1049. 8000ac8: 9b06 ldr r3, [sp, #24]
  1050. HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
  1051. 8000aca: f006 fb77 bl 80071bc <HAL_GPIO_WritePin>
  1052. HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET);
  1053. 8000ace: 462a mov r2, r5
  1054. 8000ad0: 21f0 movs r1, #240 @ 0xf0
  1055. 8000ad2: 4872 ldr r0, [pc, #456] @ (8000c9c <main+0x37c>)
  1056. 8000ad4: f006 fb72 bl 80071bc <HAL_GPIO_WritePin>
  1057. GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
  1058. 8000ad8: f24e 7380 movw r3, #59264 @ 0xe780
  1059. HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
  1060. 8000adc: a943 add r1, sp, #268 @ 0x10c
  1061. 8000ade: 486e ldr r0, [pc, #440] @ (8000c98 <main+0x378>)
  1062. GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
  1063. 8000ae0: 9343 str r3, [sp, #268] @ 0x10c
  1064. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  1065. 8000ae2: 9546 str r5, [sp, #280] @ 0x118
  1066. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  1067. 8000ae4: e9cd 6544 strd r6, r5, [sp, #272] @ 0x110
  1068. HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
  1069. 8000ae8: f006 fa20 bl 8006f2c <HAL_GPIO_Init>
  1070. GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
  1071. 8000aec: f44f 6340 mov.w r3, #3072 @ 0xc00
  1072. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  1073. 8000af0: a943 add r1, sp, #268 @ 0x10c
  1074. 8000af2: 486b ldr r0, [pc, #428] @ (8000ca0 <main+0x380>)
  1075. GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
  1076. 8000af4: 9343 str r3, [sp, #268] @ 0x10c
  1077. GPIO_InitStruct.Pull = GPIO_NOPULL;
  1078. 8000af6: 9545 str r5, [sp, #276] @ 0x114
  1079. GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
  1080. 8000af8: 9744 str r7, [sp, #272] @ 0x110
  1081. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  1082. 8000afa: f006 fa17 bl 8006f2c <HAL_GPIO_Init>
  1083. GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
  1084. 8000afe: f643 7308 movw r3, #16136 @ 0x3f08
  1085. HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  1086. 8000b02: a943 add r1, sp, #268 @ 0x10c
  1087. 8000b04: 4865 ldr r0, [pc, #404] @ (8000c9c <main+0x37c>)
  1088. GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
  1089. 8000b06: 9343 str r3, [sp, #268] @ 0x10c
  1090. GPIO_InitStruct.Pull = GPIO_NOPULL;
  1091. 8000b08: e9cd 5544 strd r5, r5, [sp, #272] @ 0x110
  1092. HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  1093. 8000b0c: f006 fa0e bl 8006f2c <HAL_GPIO_Init>
  1094. GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
  1095. 8000b10: f44f 4340 mov.w r3, #49152 @ 0xc000
  1096. HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  1097. 8000b14: a943 add r1, sp, #268 @ 0x10c
  1098. 8000b16: 4861 ldr r0, [pc, #388] @ (8000c9c <main+0x37c>)
  1099. GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
  1100. 8000b18: 9343 str r3, [sp, #268] @ 0x10c
  1101. GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
  1102. 8000b1a: 9744 str r7, [sp, #272] @ 0x110
  1103. GPIO_InitStruct.Pull = GPIO_NOPULL;
  1104. 8000b1c: 9545 str r5, [sp, #276] @ 0x114
  1105. HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  1106. 8000b1e: f006 fa05 bl 8006f2c <HAL_GPIO_Init>
  1107. GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
  1108. 8000b22: 23f0 movs r3, #240 @ 0xf0
  1109. HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  1110. 8000b24: a943 add r1, sp, #268 @ 0x10c
  1111. 8000b26: 485d ldr r0, [pc, #372] @ (8000c9c <main+0x37c>)
  1112. GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
  1113. 8000b28: 9343 str r3, [sp, #268] @ 0x10c
  1114. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  1115. 8000b2a: 9546 str r5, [sp, #280] @ 0x118
  1116. GPIO_InitStruct.Pull = GPIO_NOPULL;
  1117. 8000b2c: e9cd 6544 strd r6, r5, [sp, #272] @ 0x110
  1118. HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  1119. 8000b30: f006 f9fc bl 8006f2c <HAL_GPIO_Init>
  1120. HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0);
  1121. 8000b34: 462a mov r2, r5
  1122. 8000b36: 2105 movs r1, #5
  1123. 8000b38: 2028 movs r0, #40 @ 0x28
  1124. 8000b3a: f004 f9fd bl 8004f38 <HAL_NVIC_SetPriority>
  1125. HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
  1126. 8000b3e: 2028 movs r0, #40 @ 0x28
  1127. 8000b40: f004 fa36 bl 8004fb0 <HAL_NVIC_EnableIRQ>
  1128. __HAL_RCC_DMA1_CLK_ENABLE();
  1129. 8000b44: f8d4 30d8 ldr.w r3, [r4, #216] @ 0xd8
  1130. HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
  1131. 8000b48: 462a mov r2, r5
  1132. 8000b4a: 2105 movs r1, #5
  1133. __HAL_RCC_DMA1_CLK_ENABLE();
  1134. 8000b4c: 4333 orrs r3, r6
  1135. HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
  1136. 8000b4e: 200b movs r0, #11
  1137. __HAL_RCC_DMA1_CLK_ENABLE();
  1138. 8000b50: f8c4 30d8 str.w r3, [r4, #216] @ 0xd8
  1139. 8000b54: f8d4 30d8 ldr.w r3, [r4, #216] @ 0xd8
  1140. 8000b58: 4033 ands r3, r6
  1141. 8000b5a: 9300 str r3, [sp, #0]
  1142. 8000b5c: 9b00 ldr r3, [sp, #0]
  1143. HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
  1144. 8000b5e: f004 f9eb bl 8004f38 <HAL_NVIC_SetPriority>
  1145. HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
  1146. 8000b62: 200b movs r0, #11
  1147. 8000b64: f004 fa24 bl 8004fb0 <HAL_NVIC_EnableIRQ>
  1148. HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0);
  1149. 8000b68: 462a mov r2, r5
  1150. 8000b6a: 2105 movs r1, #5
  1151. 8000b6c: 200c movs r0, #12
  1152. 8000b6e: f004 f9e3 bl 8004f38 <HAL_NVIC_SetPriority>
  1153. HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
  1154. 8000b72: 200c movs r0, #12
  1155. 8000b74: f004 fa1c bl 8004fb0 <HAL_NVIC_EnableIRQ>
  1156. HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0);
  1157. 8000b78: 462a mov r2, r5
  1158. 8000b7a: 2105 movs r1, #5
  1159. 8000b7c: 200d movs r0, #13
  1160. 8000b7e: f004 f9db bl 8004f38 <HAL_NVIC_SetPriority>
  1161. HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
  1162. 8000b82: 200d movs r0, #13
  1163. 8000b84: f004 fa14 bl 8004fb0 <HAL_NVIC_EnableIRQ>
  1164. hrng.Instance = RNG;
  1165. 8000b88: 4846 ldr r0, [pc, #280] @ (8000ca4 <main+0x384>)
  1166. 8000b8a: 4b47 ldr r3, [pc, #284] @ (8000ca8 <main+0x388>)
  1167. 8000b8c: e9c0 3500 strd r3, r5, [r0]
  1168. if (HAL_RNG_Init(&hrng) != HAL_OK)
  1169. 8000b90: f008 fe1c bl 80097cc <HAL_RNG_Init>
  1170. 8000b94: 2800 cmp r0, #0
  1171. 8000b96: f040 8399 bne.w 80012cc <main+0x9ac>
  1172. huart1.Instance = USART1;
  1173. 8000b9a: 4c44 ldr r4, [pc, #272] @ (8000cac <main+0x38c>)
  1174. huart1.Init.Mode = UART_MODE_TX_RX;
  1175. 8000b9c: 250c movs r5, #12
  1176. huart1.Instance = USART1;
  1177. 8000b9e: 4b44 ldr r3, [pc, #272] @ (8000cb0 <main+0x390>)
  1178. huart1.Init.WordLength = UART_WORDLENGTH_8B;
  1179. 8000ba0: 60a0 str r0, [r4, #8]
  1180. huart1.Instance = USART1;
  1181. 8000ba2: 6023 str r3, [r4, #0]
  1182. huart1.Init.BaudRate = 115200;
  1183. 8000ba4: f44f 33e1 mov.w r3, #115200 @ 0x1c200
  1184. huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  1185. 8000ba8: 61a0 str r0, [r4, #24]
  1186. huart1.Init.BaudRate = 115200;
  1187. 8000baa: 6063 str r3, [r4, #4]
  1188. huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE;
  1189. 8000bac: f44f 3300 mov.w r3, #131072 @ 0x20000
  1190. huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
  1191. 8000bb0: 6260 str r0, [r4, #36] @ 0x24
  1192. huart1.Init.Mode = UART_MODE_TX_RX;
  1193. 8000bb2: 6165 str r5, [r4, #20]
  1194. huart1.Init.Parity = UART_PARITY_NONE;
  1195. 8000bb4: e9c4 0003 strd r0, r0, [r4, #12]
  1196. huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
  1197. 8000bb8: e9c4 0007 strd r0, r0, [r4, #28]
  1198. if (HAL_UART_Init(&huart1) != HAL_OK)
  1199. 8000bbc: 4620 mov r0, r4
  1200. huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE;
  1201. 8000bbe: e9c4 630a strd r6, r3, [r4, #40] @ 0x28
  1202. if (HAL_UART_Init(&huart1) != HAL_OK)
  1203. 8000bc2: f00a fe31 bl 800b828 <HAL_UART_Init>
  1204. 8000bc6: 4601 mov r1, r0
  1205. 8000bc8: 2800 cmp r0, #0
  1206. 8000bca: f040 837f bne.w 80012cc <main+0x9ac>
  1207. if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
  1208. 8000bce: 4620 mov r0, r4
  1209. 8000bd0: f00a ff20 bl 800ba14 <HAL_UARTEx_SetTxFifoThreshold>
  1210. 8000bd4: 4601 mov r1, r0
  1211. 8000bd6: 2800 cmp r0, #0
  1212. 8000bd8: f040 8378 bne.w 80012cc <main+0x9ac>
  1213. if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
  1214. 8000bdc: 4620 mov r0, r4
  1215. 8000bde: f00a ff5b bl 800ba98 <HAL_UARTEx_SetRxFifoThreshold>
  1216. 8000be2: 2800 cmp r0, #0
  1217. 8000be4: f040 8372 bne.w 80012cc <main+0x9ac>
  1218. if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
  1219. 8000be8: 4620 mov r0, r4
  1220. 8000bea: f00a fef5 bl 800b9d8 <HAL_UARTEx_DisableFifoMode>
  1221. 8000bee: 2800 cmp r0, #0
  1222. 8000bf0: f040 836c bne.w 80012cc <main+0x9ac>
  1223. hadc1.Instance = ADC1;
  1224. 8000bf4: 4c2f ldr r4, [pc, #188] @ (8000cb4 <main+0x394>)
  1225. hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
  1226. 8000bf6: f44f 6b9c mov.w fp, #1248 @ 0x4e0
  1227. hadc1.Instance = ADC1;
  1228. 8000bfa: 4b2f ldr r3, [pc, #188] @ (8000cb8 <main+0x398>)
  1229. ADC_MultiModeTypeDef multimode = {0};
  1230. 8000bfc: 9010 str r0, [sp, #64] @ 0x40
  1231. hadc1.Instance = ADC1;
  1232. 8000bfe: 6023 str r3, [r4, #0]
  1233. hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
  1234. 8000c00: 2308 movs r3, #8
  1235. ADC_ChannelConfTypeDef sConfig = {0};
  1236. 8000c02: 9033 str r0, [sp, #204] @ 0xcc
  1237. hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
  1238. 8000c04: 6123 str r3, [r4, #16]
  1239. hadc1.Init.LowPowerAutoWait = DISABLE;
  1240. 8000c06: f44f 7380 mov.w r3, #256 @ 0x100
  1241. hadc1.Init.DiscontinuousConvMode = DISABLE;
  1242. 8000c0a: 7720 strb r0, [r4, #28]
  1243. hadc1.Init.LowPowerAutoWait = DISABLE;
  1244. 8000c0c: 82a3 strh r3, [r4, #20]
  1245. hadc1.Init.NbrOfConversion = 7;
  1246. 8000c0e: 2307 movs r3, #7
  1247. hadc1.Init.OversamplingMode = DISABLE;
  1248. 8000c10: f884 0038 strb.w r0, [r4, #56] @ 0x38
  1249. hadc1.Init.NbrOfConversion = 7;
  1250. 8000c14: 61a3 str r3, [r4, #24]
  1251. hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
  1252. 8000c16: f44f 6380 mov.w r3, #1024 @ 0x400
  1253. hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
  1254. 8000c1a: 60e6 str r6, [r4, #12]
  1255. hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT;
  1256. 8000c1c: 62e6 str r6, [r4, #44] @ 0x2c
  1257. ADC_MultiModeTypeDef multimode = {0};
  1258. 8000c1e: e9cd 0011 strd r0, r0, [sp, #68] @ 0x44
  1259. ADC_ChannelConfTypeDef sConfig = {0};
  1260. 8000c22: e9cd 0034 strd r0, r0, [sp, #208] @ 0xd0
  1261. 8000c26: e9cd 0036 strd r0, r0, [sp, #216] @ 0xd8
  1262. 8000c2a: e9cd 0038 strd r0, r0, [sp, #224] @ 0xe0
  1263. hadc1.Init.Resolution = ADC_RESOLUTION_16B;
  1264. 8000c2e: e9c4 0001 strd r0, r0, [r4, #4]
  1265. hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
  1266. 8000c32: e9c4 000c strd r0, r0, [r4, #48] @ 0x30
  1267. if (HAL_ADC_Init(&hadc1) != HAL_OK)
  1268. 8000c36: 4620 mov r0, r4
  1269. hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
  1270. 8000c38: e9c4 b309 strd fp, r3, [r4, #36] @ 0x24
  1271. if (HAL_ADC_Init(&hadc1) != HAL_OK)
  1272. 8000c3c: f003 fe32 bl 80048a4 <HAL_ADC_Init>
  1273. 8000c40: 2800 cmp r0, #0
  1274. 8000c42: f040 8343 bne.w 80012cc <main+0x9ac>
  1275. multimode.DualModeData = ADC_DUALMODEDATAFORMAT_32_10_BITS;
  1276. 8000c46: 2606 movs r6, #6
  1277. 8000c48: f44f 4300 mov.w r3, #32768 @ 0x8000
  1278. multimode.TwoSamplingDelay = ADC_TWOSAMPLINGDELAY_1CYCLE;
  1279. 8000c4c: 9012 str r0, [sp, #72] @ 0x48
  1280. if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
  1281. 8000c4e: a910 add r1, sp, #64 @ 0x40
  1282. 8000c50: 4620 mov r0, r4
  1283. multimode.DualModeData = ADC_DUALMODEDATAFORMAT_32_10_BITS;
  1284. 8000c52: e9cd 6310 strd r6, r3, [sp, #64] @ 0x40
  1285. if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
  1286. 8000c56: f004 f803 bl 8004c60 <HAL_ADCEx_MultiModeConfigChannel>
  1287. 8000c5a: 2800 cmp r0, #0
  1288. 8000c5c: f040 8336 bne.w 80012cc <main+0x9ac>
  1289. sConfig.Channel = ADC_CHANNEL_8;
  1290. 8000c60: 4b16 ldr r3, [pc, #88] @ (8000cbc <main+0x39c>)
  1291. sConfig.OffsetNumber = ADC_OFFSET_NONE;
  1292. 8000c62: f240 78ff movw r8, #2047 @ 0x7ff
  1293. sConfig.Offset = 0;
  1294. 8000c66: 9038 str r0, [sp, #224] @ 0xe0
  1295. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1296. 8000c68: a933 add r1, sp, #204 @ 0xcc
  1297. sConfig.Channel = ADC_CHANNEL_8;
  1298. 8000c6a: 9333 str r3, [sp, #204] @ 0xcc
  1299. sConfig.OffsetNumber = ADC_OFFSET_NONE;
  1300. 8000c6c: 2304 movs r3, #4
  1301. sConfig.OffsetSignedSaturation = DISABLE;
  1302. 8000c6e: f88d 00e5 strb.w r0, [sp, #229] @ 0xe5
  1303. sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
  1304. 8000c72: e9cd 6034 strd r6, r0, [sp, #208] @ 0xd0
  1305. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1306. 8000c76: 4620 mov r0, r4
  1307. sConfig.OffsetNumber = ADC_OFFSET_NONE;
  1308. 8000c78: e9cd 8336 strd r8, r3, [sp, #216] @ 0xd8
  1309. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1310. 8000c7c: f003 fa1e bl 80040bc <HAL_ADC_ConfigChannel>
  1311. 8000c80: e01e b.n 8000cc0 <main+0x3a0>
  1312. 8000c82: bf00 nop
  1313. 8000c84: 24020000 .word 0x24020000
  1314. 8000c88: 03010010 .word 0x03010010
  1315. 8000c8c: 24040000 .word 0x24040000
  1316. 8000c90: e000ed00 .word 0xe000ed00
  1317. 8000c94: 58024400 .word 0x58024400
  1318. 8000c98: 58021000 .word 0x58021000
  1319. 8000c9c: 58020c00 .word 0x58020c00
  1320. 8000ca0: 58020400 .word 0x58020400
  1321. 8000ca4: 24000598 .word 0x24000598
  1322. 8000ca8: 48021800 .word 0x48021800
  1323. 8000cac: 2400038c .word 0x2400038c
  1324. 8000cb0: 40011000 .word 0x40011000
  1325. 8000cb4: 24000850 .word 0x24000850
  1326. 8000cb8: 40022000 .word 0x40022000
  1327. 8000cbc: 21800100 .word 0x21800100
  1328. 8000cc0: 2800 cmp r0, #0
  1329. 8000cc2: f040 8303 bne.w 80012cc <main+0x9ac>
  1330. sConfig.Channel = ADC_CHANNEL_9;
  1331. 8000cc6: 4bcc ldr r3, [pc, #816] @ (8000ff8 <main+0x6d8>)
  1332. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1333. 8000cc8: a933 add r1, sp, #204 @ 0xcc
  1334. 8000cca: 4620 mov r0, r4
  1335. sConfig.Rank = ADC_REGULAR_RANK_2;
  1336. 8000ccc: 9534 str r5, [sp, #208] @ 0xd0
  1337. sConfig.Channel = ADC_CHANNEL_9;
  1338. 8000cce: 9333 str r3, [sp, #204] @ 0xcc
  1339. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1340. 8000cd0: f003 f9f4 bl 80040bc <HAL_ADC_ConfigChannel>
  1341. 8000cd4: 2800 cmp r0, #0
  1342. 8000cd6: f040 82f9 bne.w 80012cc <main+0x9ac>
  1343. sConfig.Channel = ADC_CHANNEL_7;
  1344. 8000cda: 4ac8 ldr r2, [pc, #800] @ (8000ffc <main+0x6dc>)
  1345. sConfig.Rank = ADC_REGULAR_RANK_3;
  1346. 8000cdc: 2312 movs r3, #18
  1347. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1348. 8000cde: 4620 mov r0, r4
  1349. 8000ce0: a933 add r1, sp, #204 @ 0xcc
  1350. sConfig.Rank = ADC_REGULAR_RANK_3;
  1351. 8000ce2: e9cd 2333 strd r2, r3, [sp, #204] @ 0xcc
  1352. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1353. 8000ce6: f003 f9e9 bl 80040bc <HAL_ADC_ConfigChannel>
  1354. 8000cea: 2800 cmp r0, #0
  1355. 8000cec: f040 82ee bne.w 80012cc <main+0x9ac>
  1356. sConfig.Channel = ADC_CHANNEL_16;
  1357. 8000cf0: 4ac3 ldr r2, [pc, #780] @ (8001000 <main+0x6e0>)
  1358. sConfig.Rank = ADC_REGULAR_RANK_4;
  1359. 8000cf2: 2318 movs r3, #24
  1360. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1361. 8000cf4: a933 add r1, sp, #204 @ 0xcc
  1362. 8000cf6: 4620 mov r0, r4
  1363. sConfig.Rank = ADC_REGULAR_RANK_4;
  1364. 8000cf8: e9cd 2333 strd r2, r3, [sp, #204] @ 0xcc
  1365. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1366. 8000cfc: f003 f9de bl 80040bc <HAL_ADC_ConfigChannel>
  1367. 8000d00: 2800 cmp r0, #0
  1368. 8000d02: f040 82e3 bne.w 80012cc <main+0x9ac>
  1369. sConfig.Channel = ADC_CHANNEL_17;
  1370. 8000d06: 4abf ldr r2, [pc, #764] @ (8001004 <main+0x6e4>)
  1371. sConfig.Rank = ADC_REGULAR_RANK_5;
  1372. 8000d08: f44f 7380 mov.w r3, #256 @ 0x100
  1373. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1374. 8000d0c: a933 add r1, sp, #204 @ 0xcc
  1375. 8000d0e: 4620 mov r0, r4
  1376. sConfig.Rank = ADC_REGULAR_RANK_5;
  1377. 8000d10: e9cd 2333 strd r2, r3, [sp, #204] @ 0xcc
  1378. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1379. 8000d14: f003 f9d2 bl 80040bc <HAL_ADC_ConfigChannel>
  1380. 8000d18: 2800 cmp r0, #0
  1381. 8000d1a: f040 82d7 bne.w 80012cc <main+0x9ac>
  1382. sConfig.Channel = ADC_CHANNEL_14;
  1383. 8000d1e: 4aba ldr r2, [pc, #744] @ (8001008 <main+0x6e8>)
  1384. sConfig.Rank = ADC_REGULAR_RANK_6;
  1385. 8000d20: f44f 7383 mov.w r3, #262 @ 0x106
  1386. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1387. 8000d24: a933 add r1, sp, #204 @ 0xcc
  1388. 8000d26: 4620 mov r0, r4
  1389. sConfig.Rank = ADC_REGULAR_RANK_6;
  1390. 8000d28: e9cd 2333 strd r2, r3, [sp, #204] @ 0xcc
  1391. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1392. 8000d2c: f003 f9c6 bl 80040bc <HAL_ADC_ConfigChannel>
  1393. 8000d30: 2800 cmp r0, #0
  1394. 8000d32: f040 82cb bne.w 80012cc <main+0x9ac>
  1395. sConfig.Channel = ADC_CHANNEL_15;
  1396. 8000d36: 4ab5 ldr r2, [pc, #724] @ (800100c <main+0x6ec>)
  1397. sConfig.Rank = ADC_REGULAR_RANK_7;
  1398. 8000d38: f44f 7386 mov.w r3, #268 @ 0x10c
  1399. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1400. 8000d3c: a933 add r1, sp, #204 @ 0xcc
  1401. 8000d3e: 4620 mov r0, r4
  1402. sConfig.Rank = ADC_REGULAR_RANK_7;
  1403. 8000d40: e9cd 2333 strd r2, r3, [sp, #204] @ 0xcc
  1404. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  1405. 8000d44: f003 f9ba bl 80040bc <HAL_ADC_ConfigChannel>
  1406. 8000d48: 2800 cmp r0, #0
  1407. 8000d4a: f040 82bf bne.w 80012cc <main+0x9ac>
  1408. if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK)
  1409. 8000d4e: f240 72ff movw r2, #2047 @ 0x7ff
  1410. 8000d52: f04f 1101 mov.w r1, #65537 @ 0x10001
  1411. 8000d56: 4620 mov r0, r4
  1412. 8000d58: f003 feb0 bl 8004abc <HAL_ADCEx_Calibration_Start>
  1413. 8000d5c: 4603 mov r3, r0
  1414. 8000d5e: 2800 cmp r0, #0
  1415. 8000d60: f040 82b4 bne.w 80012cc <main+0x9ac>
  1416. huart8.Instance = UART8;
  1417. 8000d64: 4caa ldr r4, [pc, #680] @ (8001010 <main+0x6f0>)
  1418. huart8.Init.BaudRate = 115200;
  1419. 8000d66: f44f 32e1 mov.w r2, #115200 @ 0x1c200
  1420. huart8.Instance = UART8;
  1421. 8000d6a: 49aa ldr r1, [pc, #680] @ (8001014 <main+0x6f4>)
  1422. if (HAL_UART_Init(&huart8) != HAL_OK)
  1423. 8000d6c: 4620 mov r0, r4
  1424. huart8.Init.BaudRate = 115200;
  1425. 8000d6e: e884 000e stmia.w r4, {r1, r2, r3}
  1426. huart8.Init.Parity = UART_PARITY_NONE;
  1427. 8000d72: e9c4 3303 strd r3, r3, [r4, #12]
  1428. huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  1429. 8000d76: e9c4 5305 strd r5, r3, [r4, #20]
  1430. huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
  1431. 8000d7a: e9c4 3307 strd r3, r3, [r4, #28]
  1432. huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
  1433. 8000d7e: e9c4 3309 strd r3, r3, [r4, #36] @ 0x24
  1434. if (HAL_UART_Init(&huart8) != HAL_OK)
  1435. 8000d82: f00a fd51 bl 800b828 <HAL_UART_Init>
  1436. 8000d86: 4601 mov r1, r0
  1437. 8000d88: 2800 cmp r0, #0
  1438. 8000d8a: f040 829f bne.w 80012cc <main+0x9ac>
  1439. if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
  1440. 8000d8e: 4620 mov r0, r4
  1441. 8000d90: f00a fe40 bl 800ba14 <HAL_UARTEx_SetTxFifoThreshold>
  1442. 8000d94: 4601 mov r1, r0
  1443. 8000d96: 2800 cmp r0, #0
  1444. 8000d98: f040 8298 bne.w 80012cc <main+0x9ac>
  1445. if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
  1446. 8000d9c: 4620 mov r0, r4
  1447. 8000d9e: f00a fe7b bl 800ba98 <HAL_UARTEx_SetRxFifoThreshold>
  1448. 8000da2: 2800 cmp r0, #0
  1449. 8000da4: f040 8292 bne.w 80012cc <main+0x9ac>
  1450. if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK)
  1451. 8000da8: 4620 mov r0, r4
  1452. 8000daa: f00a fe15 bl 800b9d8 <HAL_UARTEx_DisableFifoMode>
  1453. 8000dae: 4603 mov r3, r0
  1454. 8000db0: 2800 cmp r0, #0
  1455. 8000db2: f040 828b bne.w 80012cc <main+0x9ac>
  1456. hcrc.Instance = CRC;
  1457. 8000db6: 4898 ldr r0, [pc, #608] @ (8001018 <main+0x6f8>)
  1458. hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE;
  1459. 8000db8: 2201 movs r2, #1
  1460. hcrc.Instance = CRC;
  1461. 8000dba: 4998 ldr r1, [pc, #608] @ (800101c <main+0x6fc>)
  1462. hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE;
  1463. 8000dbc: 6143 str r3, [r0, #20]
  1464. hcrc.Instance = CRC;
  1465. 8000dbe: 6001 str r1, [r0, #0]
  1466. hcrc.Init.GeneratingPolynomial = 4129;
  1467. 8000dc0: f241 0121 movw r1, #4129 @ 0x1021
  1468. hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE;
  1469. 8000dc4: 6183 str r3, [r0, #24]
  1470. hcrc.Init.CRCLength = CRC_POLYLENGTH_16B;
  1471. 8000dc6: 2308 movs r3, #8
  1472. hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE;
  1473. 8000dc8: 8082 strh r2, [r0, #4]
  1474. hcrc.Init.GeneratingPolynomial = 4129;
  1475. 8000dca: 6081 str r1, [r0, #8]
  1476. hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
  1477. 8000dcc: 6202 str r2, [r0, #32]
  1478. hcrc.Init.CRCLength = CRC_POLYLENGTH_16B;
  1479. 8000dce: 60c3 str r3, [r0, #12]
  1480. if (HAL_CRC_Init(&hcrc) != HAL_OK)
  1481. 8000dd0: f004 f984 bl 80050dc <HAL_CRC_Init>
  1482. 8000dd4: 2800 cmp r0, #0
  1483. 8000dd6: f040 8279 bne.w 80012cc <main+0x9ac>
  1484. ADC_ChannelConfTypeDef sConfig = {0};
  1485. 8000dda: 2200 movs r2, #0
  1486. hadc2.Instance = ADC2;
  1487. 8000ddc: f8df 826c ldr.w r8, [pc, #620] @ 800104c <main+0x72c>
  1488. hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
  1489. 8000de0: 2401 movs r4, #1
  1490. hadc2.Instance = ADC2;
  1491. 8000de2: 498f ldr r1, [pc, #572] @ (8001020 <main+0x700>)
  1492. hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
  1493. 8000de4: f04f 0b08 mov.w fp, #8
  1494. hadc2.Init.LowPowerAutoWait = DISABLE;
  1495. 8000de8: f44f 7a80 mov.w sl, #256 @ 0x100
  1496. ADC_ChannelConfTypeDef sConfig = {0};
  1497. 8000dec: 922c str r2, [sp, #176] @ 0xb0
  1498. if (HAL_ADC_Init(&hadc2) != HAL_OK)
  1499. 8000dee: 4640 mov r0, r8
  1500. hadc2.Init.DiscontinuousConvMode = DISABLE;
  1501. 8000df0: f888 201c strb.w r2, [r8, #28]
  1502. hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
  1503. 8000df4: f8c8 2034 str.w r2, [r8, #52] @ 0x34
  1504. hadc2.Init.OversamplingMode = DISABLE;
  1505. 8000df8: f888 2038 strb.w r2, [r8, #56] @ 0x38
  1506. hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
  1507. 8000dfc: f8c8 b010 str.w fp, [r8, #16]
  1508. hadc2.Init.LowPowerAutoWait = DISABLE;
  1509. 8000e00: f8a8 a014 strh.w sl, [r8, #20]
  1510. hadc2.Instance = ADC2;
  1511. 8000e04: e9c8 1200 strd r1, r2, [r8]
  1512. hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
  1513. 8000e08: e9c8 2402 strd r2, r4, [r8, #8]
  1514. hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
  1515. 8000e0c: e9c8 420b strd r4, r2, [r8, #44] @ 0x2c
  1516. ADC_ChannelConfTypeDef sConfig = {0};
  1517. 8000e10: e9cd 222d strd r2, r2, [sp, #180] @ 0xb4
  1518. 8000e14: e9cd 222f strd r2, r2, [sp, #188] @ 0xbc
  1519. 8000e18: e9cd 2231 strd r2, r2, [sp, #196] @ 0xc4
  1520. hadc2.Init.NbrOfConversion = 3;
  1521. 8000e1c: 2203 movs r2, #3
  1522. 8000e1e: f8c8 2018 str.w r2, [r8, #24]
  1523. if (HAL_ADC_Init(&hadc2) != HAL_OK)
  1524. 8000e22: f003 fd3f bl 80048a4 <HAL_ADC_Init>
  1525. 8000e26: 2800 cmp r0, #0
  1526. 8000e28: f040 8250 bne.w 80012cc <main+0x9ac>
  1527. sConfig.Channel = ADC_CHANNEL_3;
  1528. 8000e2c: 4a7d ldr r2, [pc, #500] @ (8001024 <main+0x704>)
  1529. sConfig.Rank = ADC_REGULAR_RANK_1;
  1530. 8000e2e: 4635 mov r5, r6
  1531. sConfig.OffsetNumber = ADC_OFFSET_NONE;
  1532. 8000e30: f04f 0904 mov.w r9, #4
  1533. sConfig.Rank = ADC_REGULAR_RANK_1;
  1534. 8000e34: 962d str r6, [sp, #180] @ 0xb4
  1535. sConfig.OffsetNumber = ADC_OFFSET_NONE;
  1536. 8000e36: f240 76ff movw r6, #2047 @ 0x7ff
  1537. sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
  1538. 8000e3a: 902e str r0, [sp, #184] @ 0xb8
  1539. sConfig.Offset = 0;
  1540. 8000e3c: 9031 str r0, [sp, #196] @ 0xc4
  1541. if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
  1542. 8000e3e: a92c add r1, sp, #176 @ 0xb0
  1543. sConfig.OffsetSignedSaturation = DISABLE;
  1544. 8000e40: f88d 00c9 strb.w r0, [sp, #201] @ 0xc9
  1545. if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
  1546. 8000e44: 4640 mov r0, r8
  1547. sConfig.Channel = ADC_CHANNEL_3;
  1548. 8000e46: 922c str r2, [sp, #176] @ 0xb0
  1549. sConfig.OffsetNumber = ADC_OFFSET_NONE;
  1550. 8000e48: e9cd 692f strd r6, r9, [sp, #188] @ 0xbc
  1551. if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
  1552. 8000e4c: f003 f936 bl 80040bc <HAL_ADC_ConfigChannel>
  1553. 8000e50: 2800 cmp r0, #0
  1554. 8000e52: f040 823b bne.w 80012cc <main+0x9ac>
  1555. sConfig.Rank = ADC_REGULAR_RANK_2;
  1556. 8000e56: 4a74 ldr r2, [pc, #464] @ (8001028 <main+0x708>)
  1557. 8000e58: 230c movs r3, #12
  1558. if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
  1559. 8000e5a: a92c add r1, sp, #176 @ 0xb0
  1560. 8000e5c: 4640 mov r0, r8
  1561. sConfig.Rank = ADC_REGULAR_RANK_2;
  1562. 8000e5e: e9cd 232c strd r2, r3, [sp, #176] @ 0xb0
  1563. if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
  1564. 8000e62: f003 f92b bl 80040bc <HAL_ADC_ConfigChannel>
  1565. 8000e66: 2800 cmp r0, #0
  1566. 8000e68: f040 8230 bne.w 80012cc <main+0x9ac>
  1567. sConfig.Rank = ADC_REGULAR_RANK_3;
  1568. 8000e6c: 4a6f ldr r2, [pc, #444] @ (800102c <main+0x70c>)
  1569. 8000e6e: 2712 movs r7, #18
  1570. if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
  1571. 8000e70: a92c add r1, sp, #176 @ 0xb0
  1572. 8000e72: 4640 mov r0, r8
  1573. sConfig.Rank = ADC_REGULAR_RANK_3;
  1574. 8000e74: e9cd 272c strd r2, r7, [sp, #176] @ 0xb0
  1575. if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
  1576. 8000e78: f003 f920 bl 80040bc <HAL_ADC_ConfigChannel>
  1577. 8000e7c: 2800 cmp r0, #0
  1578. 8000e7e: f040 8225 bne.w 80012cc <main+0x9ac>
  1579. if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK)
  1580. 8000e82: 4640 mov r0, r8
  1581. 8000e84: 4632 mov r2, r6
  1582. 8000e86: f04f 1101 mov.w r1, #65537 @ 0x10001
  1583. 8000e8a: f003 fe17 bl 8004abc <HAL_ADCEx_Calibration_Start>
  1584. 8000e8e: 2800 cmp r0, #0
  1585. 8000e90: f040 821c bne.w 80012cc <main+0x9ac>
  1586. hadc3.Instance = ADC3;
  1587. 8000e94: f8df 81b8 ldr.w r8, [pc, #440] @ 8001050 <main+0x730>
  1588. hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
  1589. 8000e98: f44f 6c9c mov.w ip, #1248 @ 0x4e0
  1590. hadc3.Instance = ADC3;
  1591. 8000e9c: 4a64 ldr r2, [pc, #400] @ (8001030 <main+0x710>)
  1592. ADC_ChannelConfTypeDef sConfig = {0};
  1593. 8000e9e: 902b str r0, [sp, #172] @ 0xac
  1594. hadc3.Instance = ADC3;
  1595. 8000ea0: f8c8 2000 str.w r2, [r8]
  1596. hadc3.Init.NbrOfConversion = 5;
  1597. 8000ea4: 2205 movs r2, #5
  1598. hadc3.Init.DiscontinuousConvMode = DISABLE;
  1599. 8000ea6: f888 001c strb.w r0, [r8, #28]
  1600. hadc3.Init.NbrOfConversion = 5;
  1601. 8000eaa: f8c8 2018 str.w r2, [r8, #24]
  1602. hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
  1603. 8000eae: f44f 6280 mov.w r2, #1024 @ 0x400
  1604. hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
  1605. 8000eb2: f8c8 0034 str.w r0, [r8, #52] @ 0x34
  1606. hadc3.Init.OversamplingMode = DISABLE;
  1607. 8000eb6: f888 0038 strb.w r0, [r8, #56] @ 0x38
  1608. hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV;
  1609. 8000eba: f8c8 b010 str.w fp, [r8, #16]
  1610. hadc3.Init.LowPowerAutoWait = DISABLE;
  1611. 8000ebe: f8a8 a014 strh.w sl, [r8, #20]
  1612. hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE;
  1613. 8000ec2: f8c8 400c str.w r4, [r8, #12]
  1614. ADC_ChannelConfTypeDef sConfig = {0};
  1615. 8000ec6: e9cd 0025 strd r0, r0, [sp, #148] @ 0x94
  1616. 8000eca: e9cd 0027 strd r0, r0, [sp, #156] @ 0x9c
  1617. 8000ece: e9cd 0029 strd r0, r0, [sp, #164] @ 0xa4
  1618. hadc3.Init.Resolution = ADC_RESOLUTION_16B;
  1619. 8000ed2: e9c8 0001 strd r0, r0, [r8, #4]
  1620. hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED;
  1621. 8000ed6: e9c8 400b strd r4, r0, [r8, #44] @ 0x2c
  1622. if (HAL_ADC_Init(&hadc3) != HAL_OK)
  1623. 8000eda: 4640 mov r0, r8
  1624. hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
  1625. 8000edc: e9c8 c209 strd ip, r2, [r8, #36] @ 0x24
  1626. if (HAL_ADC_Init(&hadc3) != HAL_OK)
  1627. 8000ee0: f003 fce0 bl 80048a4 <HAL_ADC_Init>
  1628. 8000ee4: 2800 cmp r0, #0
  1629. 8000ee6: f040 81f1 bne.w 80012cc <main+0x9ac>
  1630. sConfig.Offset = 0;
  1631. 8000eea: 902a str r0, [sp, #168] @ 0xa8
  1632. if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
  1633. 8000eec: a925 add r1, sp, #148 @ 0x94
  1634. sConfig.OffsetSignedSaturation = DISABLE;
  1635. 8000eee: f88d 00ad strb.w r0, [sp, #173] @ 0xad
  1636. if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
  1637. 8000ef2: 4640 mov r0, r8
  1638. sConfig.Channel = ADC_CHANNEL_0;
  1639. 8000ef4: 9425 str r4, [sp, #148] @ 0x94
  1640. sConfig.OffsetNumber = ADC_OFFSET_NONE;
  1641. 8000ef6: e9cd 6928 strd r6, r9, [sp, #160] @ 0xa0
  1642. sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5;
  1643. 8000efa: e9cd 5526 strd r5, r5, [sp, #152] @ 0x98
  1644. if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
  1645. 8000efe: f003 f8dd bl 80040bc <HAL_ADC_ConfigChannel>
  1646. 8000f02: 2800 cmp r0, #0
  1647. 8000f04: f040 81e2 bne.w 80012cc <main+0x9ac>
  1648. sConfig.Rank = ADC_REGULAR_RANK_2;
  1649. 8000f08: 230c movs r3, #12
  1650. sConfig.Channel = ADC_CHANNEL_1;
  1651. 8000f0a: 4a4a ldr r2, [pc, #296] @ (8001034 <main+0x714>)
  1652. if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
  1653. 8000f0c: a925 add r1, sp, #148 @ 0x94
  1654. 8000f0e: 4640 mov r0, r8
  1655. sConfig.Rank = ADC_REGULAR_RANK_2;
  1656. 8000f10: 9326 str r3, [sp, #152] @ 0x98
  1657. sConfig.Channel = ADC_CHANNEL_1;
  1658. 8000f12: 9225 str r2, [sp, #148] @ 0x94
  1659. if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
  1660. 8000f14: f003 f8d2 bl 80040bc <HAL_ADC_ConfigChannel>
  1661. 8000f18: 2800 cmp r0, #0
  1662. 8000f1a: f040 81d7 bne.w 80012cc <main+0x9ac>
  1663. sConfig.Channel = ADC_CHANNEL_10;
  1664. 8000f1e: 4a46 ldr r2, [pc, #280] @ (8001038 <main+0x718>)
  1665. if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
  1666. 8000f20: a925 add r1, sp, #148 @ 0x94
  1667. 8000f22: 4640 mov r0, r8
  1668. sConfig.Rank = ADC_REGULAR_RANK_3;
  1669. 8000f24: 9726 str r7, [sp, #152] @ 0x98
  1670. sConfig.Channel = ADC_CHANNEL_10;
  1671. 8000f26: 9225 str r2, [sp, #148] @ 0x94
  1672. if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
  1673. 8000f28: f003 f8c8 bl 80040bc <HAL_ADC_ConfigChannel>
  1674. 8000f2c: 2800 cmp r0, #0
  1675. 8000f2e: f040 81cd bne.w 80012cc <main+0x9ac>
  1676. sConfig.Channel = ADC_CHANNEL_11;
  1677. 8000f32: 4942 ldr r1, [pc, #264] @ (800103c <main+0x71c>)
  1678. sConfig.Rank = ADC_REGULAR_RANK_4;
  1679. 8000f34: 2218 movs r2, #24
  1680. if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
  1681. 8000f36: 4640 mov r0, r8
  1682. sConfig.Rank = ADC_REGULAR_RANK_4;
  1683. 8000f38: e9cd 1225 strd r1, r2, [sp, #148] @ 0x94
  1684. if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
  1685. 8000f3c: a925 add r1, sp, #148 @ 0x94
  1686. 8000f3e: f003 f8bd bl 80040bc <HAL_ADC_ConfigChannel>
  1687. 8000f42: 2800 cmp r0, #0
  1688. 8000f44: f040 81c2 bne.w 80012cc <main+0x9ac>
  1689. sConfig.Channel = ADC_CHANNEL_VREFINT;
  1690. 8000f48: 4a3d ldr r2, [pc, #244] @ (8001040 <main+0x720>)
  1691. if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
  1692. 8000f4a: a925 add r1, sp, #148 @ 0x94
  1693. 8000f4c: 4640 mov r0, r8
  1694. sConfig.Rank = ADC_REGULAR_RANK_5;
  1695. 8000f4e: e9cd 2a25 strd r2, sl, [sp, #148] @ 0x94
  1696. if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
  1697. 8000f52: f003 f8b3 bl 80040bc <HAL_ADC_ConfigChannel>
  1698. 8000f56: 2800 cmp r0, #0
  1699. 8000f58: f040 81b8 bne.w 80012cc <main+0x9ac>
  1700. if (HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK)
  1701. 8000f5c: 4632 mov r2, r6
  1702. 8000f5e: f04f 1101 mov.w r1, #65537 @ 0x10001
  1703. 8000f62: 4640 mov r0, r8
  1704. 8000f64: f003 fdaa bl 8004abc <HAL_ADCEx_Calibration_Start>
  1705. 8000f68: 4604 mov r4, r0
  1706. 8000f6a: 2800 cmp r0, #0
  1707. 8000f6c: f040 81ae bne.w 80012cc <main+0x9ac>
  1708. htim1.Instance = TIM1;
  1709. 8000f70: 4e34 ldr r6, [pc, #208] @ (8001044 <main+0x724>)
  1710. TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
  1711. 8000f72: 4601 mov r1, r0
  1712. TIM_OC_InitTypeDef sConfigOC = {0};
  1713. 8000f74: 901e str r0, [sp, #120] @ 0x78
  1714. TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
  1715. 8000f76: 222c movs r2, #44 @ 0x2c
  1716. TIM_MasterConfigTypeDef sMasterConfig = {0};
  1717. 8000f78: 900f str r0, [sp, #60] @ 0x3c
  1718. htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
  1719. 8000f7a: f04f 0880 mov.w r8, #128 @ 0x80
  1720. htim1.Init.Prescaler = 199;
  1721. 8000f7e: f04f 0ac7 mov.w sl, #199 @ 0xc7
  1722. htim1.Init.Period = 999;
  1723. 8000f82: f240 39e7 movw r9, #999 @ 0x3e7
  1724. TIM_MasterConfigTypeDef sMasterConfig = {0};
  1725. 8000f86: e9cd 000d strd r0, r0, [sp, #52] @ 0x34
  1726. TIM_OC_InitTypeDef sConfigOC = {0};
  1727. 8000f8a: e9cd 001f strd r0, r0, [sp, #124] @ 0x7c
  1728. 8000f8e: e9cd 0021 strd r0, r0, [sp, #132] @ 0x84
  1729. 8000f92: e9cd 0023 strd r0, r0, [sp, #140] @ 0x8c
  1730. TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
  1731. 8000f96: a843 add r0, sp, #268 @ 0x10c
  1732. 8000f98: f00e fdb6 bl 800fb08 <memset>
  1733. htim1.Init.Prescaler = 199;
  1734. 8000f9c: 4b2a ldr r3, [pc, #168] @ (8001048 <main+0x728>)
  1735. if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
  1736. 8000f9e: 4630 mov r0, r6
  1737. htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
  1738. 8000fa0: 60b4 str r4, [r6, #8]
  1739. htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
  1740. 8000fa2: f8c6 8018 str.w r8, [r6, #24]
  1741. htim1.Init.Period = 999;
  1742. 8000fa6: f8c6 900c str.w r9, [r6, #12]
  1743. htim1.Init.RepetitionCounter = 0;
  1744. 8000faa: e9c6 4404 strd r4, r4, [r6, #16]
  1745. htim1.Init.Prescaler = 199;
  1746. 8000fae: e9c6 3a00 strd r3, sl, [r6]
  1747. if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
  1748. 8000fb2: f008 fe0b bl 8009bcc <HAL_TIM_PWM_Init>
  1749. 8000fb6: 2800 cmp r0, #0
  1750. 8000fb8: f040 8188 bne.w 80012cc <main+0x9ac>
  1751. sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  1752. 8000fbc: 900f str r0, [sp, #60] @ 0x3c
  1753. if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
  1754. 8000fbe: a90d add r1, sp, #52 @ 0x34
  1755. sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
  1756. 8000fc0: e9cd 000d strd r0, r0, [sp, #52] @ 0x34
  1757. if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
  1758. 8000fc4: 4630 mov r0, r6
  1759. 8000fc6: f009 fac3 bl 800a550 <HAL_TIMEx_MasterConfigSynchronization>
  1760. 8000fca: 2800 cmp r0, #0
  1761. 8000fcc: f040 817e bne.w 80012cc <main+0x9ac>
  1762. sConfigOC.Pulse = 99;
  1763. 8000fd0: f04f 0b60 mov.w fp, #96 @ 0x60
  1764. 8000fd4: 2363 movs r3, #99 @ 0x63
  1765. sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
  1766. 8000fd6: 9024 str r0, [sp, #144] @ 0x90
  1767. if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
  1768. 8000fd8: 2204 movs r2, #4
  1769. 8000fda: a91e add r1, sp, #120 @ 0x78
  1770. sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
  1771. 8000fdc: e9cd 0020 strd r0, r0, [sp, #128] @ 0x80
  1772. sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
  1773. 8000fe0: e9cd 0022 strd r0, r0, [sp, #136] @ 0x88
  1774. if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
  1775. 8000fe4: 4630 mov r0, r6
  1776. sConfigOC.Pulse = 99;
  1777. 8000fe6: e9cd b31e strd fp, r3, [sp, #120] @ 0x78
  1778. if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
  1779. 8000fea: f009 f997 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  1780. 8000fee: 2800 cmp r0, #0
  1781. 8000ff0: f040 816c bne.w 80012cc <main+0x9ac>
  1782. 8000ff4: e02e b.n 8001054 <main+0x734>
  1783. 8000ff6: bf00 nop
  1784. 8000ff8: 25b00200 .word 0x25b00200
  1785. 8000ffc: 1d500080 .word 0x1d500080
  1786. 8001000: 43210000 .word 0x43210000
  1787. 8001004: 47520000 .word 0x47520000
  1788. 8001008: 3ac04000 .word 0x3ac04000
  1789. 800100c: 3ef08000 .word 0x3ef08000
  1790. 8001010: 24000420 .word 0x24000420
  1791. 8001014: 40007c00 .word 0x40007c00
  1792. 8001018: 240005d0 .word 0x240005d0
  1793. 800101c: 58024c00 .word 0x58024c00
  1794. 8001020: 40022100 .word 0x40022100
  1795. 8001024: 0c900008 .word 0x0c900008
  1796. 8001028: 10c00010 .word 0x10c00010
  1797. 800102c: 14f00020 .word 0x14f00020
  1798. 8001030: 58026000 .word 0x58026000
  1799. 8001034: 04300002 .word 0x04300002
  1800. 8001038: 2a000400 .word 0x2a000400
  1801. 800103c: 2e300800 .word 0x2e300800
  1802. 8001040: cfb80000 .word 0xcfb80000
  1803. 8001044: 2400054c .word 0x2400054c
  1804. 8001048: 40010000 .word 0x40010000
  1805. 800104c: 240007ec .word 0x240007ec
  1806. 8001050: 24000788 .word 0x24000788
  1807. sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
  1808. 8001054: f44f 5300 mov.w r3, #8192 @ 0x2000
  1809. sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
  1810. 8001058: 9047 str r0, [sp, #284] @ 0x11c
  1811. if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
  1812. 800105a: a943 add r1, sp, #268 @ 0x10c
  1813. sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
  1814. 800105c: 9348 str r3, [sp, #288] @ 0x120
  1815. sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
  1816. 800105e: f04f 7300 mov.w r3, #33554432 @ 0x2000000
  1817. sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
  1818. 8001062: e9cd 0043 strd r0, r0, [sp, #268] @ 0x10c
  1819. sBreakDeadTimeConfig.DeadTime = 0;
  1820. 8001066: e9cd 0045 strd r0, r0, [sp, #276] @ 0x114
  1821. sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
  1822. 800106a: e9cd 0049 strd r0, r0, [sp, #292] @ 0x124
  1823. sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
  1824. 800106e: e9cd 004c strd r0, r0, [sp, #304] @ 0x130
  1825. if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
  1826. 8001072: 4630 mov r0, r6
  1827. sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
  1828. 8001074: 934b str r3, [sp, #300] @ 0x12c
  1829. if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
  1830. 8001076: f009 fac5 bl 800a604 <HAL_TIMEx_ConfigBreakDeadTime>
  1831. 800107a: 4604 mov r4, r0
  1832. 800107c: 2800 cmp r0, #0
  1833. 800107e: f040 8125 bne.w 80012cc <main+0x9ac>
  1834. memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef));
  1835. 8001082: af1e add r7, sp, #120 @ 0x78
  1836. 8001084: f8df c2b8 ldr.w ip, [pc, #696] @ 8001340 <main+0xa20>
  1837. htim3.Instance = TIM3;
  1838. 8001088: 4d91 ldr r5, [pc, #580] @ (80012d0 <main+0x9b0>)
  1839. memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef));
  1840. 800108a: cf0f ldmia r7!, {r0, r1, r2, r3}
  1841. 800108c: e8ac 000f stmia.w ip!, {r0, r1, r2, r3}
  1842. 8001090: e897 0007 ldmia.w r7, {r0, r1, r2}
  1843. 8001094: e88c 0007 stmia.w ip, {r0, r1, r2}
  1844. HAL_TIM_MspPostInit(&htim1);
  1845. 8001098: 4630 mov r0, r6
  1846. 800109a: f001 fe51 bl 8002d40 <HAL_TIM_MspPostInit>
  1847. htim3.Instance = TIM3;
  1848. 800109e: 4b8d ldr r3, [pc, #564] @ (80012d4 <main+0x9b4>)
  1849. if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
  1850. 80010a0: 4628 mov r0, r5
  1851. htim3.Init.Prescaler = 199;
  1852. 80010a2: f8c5 a004 str.w sl, [r5, #4]
  1853. htim3.Init.Period = 999;
  1854. 80010a6: f8c5 900c str.w r9, [r5, #12]
  1855. htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
  1856. 80010aa: f8c5 8018 str.w r8, [r5, #24]
  1857. TIM_MasterConfigTypeDef sMasterConfig = {0};
  1858. 80010ae: 940c str r4, [sp, #48] @ 0x30
  1859. TIM_OC_InitTypeDef sConfigOC = {0};
  1860. 80010b0: 941d str r4, [sp, #116] @ 0x74
  1861. htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
  1862. 80010b2: 60ac str r4, [r5, #8]
  1863. htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  1864. 80010b4: 612c str r4, [r5, #16]
  1865. htim3.Instance = TIM3;
  1866. 80010b6: 602b str r3, [r5, #0]
  1867. TIM_MasterConfigTypeDef sMasterConfig = {0};
  1868. 80010b8: e9cd 440a strd r4, r4, [sp, #40] @ 0x28
  1869. TIM_OC_InitTypeDef sConfigOC = {0};
  1870. 80010bc: e9cd 4417 strd r4, r4, [sp, #92] @ 0x5c
  1871. 80010c0: e9cd 4419 strd r4, r4, [sp, #100] @ 0x64
  1872. 80010c4: e9cd 441b strd r4, r4, [sp, #108] @ 0x6c
  1873. if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
  1874. 80010c8: f008 fd80 bl 8009bcc <HAL_TIM_PWM_Init>
  1875. 80010cc: 2800 cmp r0, #0
  1876. 80010ce: f040 80fd bne.w 80012cc <main+0x9ac>
  1877. sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
  1878. 80010d2: 900a str r0, [sp, #40] @ 0x28
  1879. if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
  1880. 80010d4: a90a add r1, sp, #40 @ 0x28
  1881. sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  1882. 80010d6: 900c str r0, [sp, #48] @ 0x30
  1883. if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
  1884. 80010d8: 4628 mov r0, r5
  1885. 80010da: f009 fa39 bl 800a550 <HAL_TIMEx_MasterConfigSynchronization>
  1886. 80010de: 4602 mov r2, r0
  1887. 80010e0: 2800 cmp r0, #0
  1888. 80010e2: f040 80f3 bne.w 80012cc <main+0x9ac>
  1889. sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1;
  1890. 80010e6: 4b7c ldr r3, [pc, #496] @ (80012d8 <main+0x9b8>)
  1891. if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
  1892. 80010e8: a917 add r1, sp, #92 @ 0x5c
  1893. sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
  1894. 80010ea: 9019 str r0, [sp, #100] @ 0x64
  1895. sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1;
  1896. 80010ec: 9317 str r3, [sp, #92] @ 0x5c
  1897. sConfigOC.Pulse = 500;
  1898. 80010ee: f44f 73fa mov.w r3, #500 @ 0x1f4
  1899. sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
  1900. 80010f2: 901b str r0, [sp, #108] @ 0x6c
  1901. if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
  1902. 80010f4: 4628 mov r0, r5
  1903. sConfigOC.Pulse = 500;
  1904. 80010f6: 9318 str r3, [sp, #96] @ 0x60
  1905. if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
  1906. 80010f8: f009 f910 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  1907. 80010fc: 2800 cmp r0, #0
  1908. 80010fe: f040 80e5 bne.w 80012cc <main+0x9ac>
  1909. __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1);
  1910. 8001102: 6828 ldr r0, [r5, #0]
  1911. if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
  1912. 8001104: 2204 movs r2, #4
  1913. 8001106: a917 add r1, sp, #92 @ 0x5c
  1914. sConfigOC.OCMode = TIM_OCMODE_PWM1;
  1915. 8001108: f8cd b05c str.w fp, [sp, #92] @ 0x5c
  1916. __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1);
  1917. 800110c: 6983 ldr r3, [r0, #24]
  1918. 800110e: f023 0308 bic.w r3, r3, #8
  1919. 8001112: 6183 str r3, [r0, #24]
  1920. if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
  1921. 8001114: 4628 mov r0, r5
  1922. 8001116: f009 f901 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  1923. 800111a: 2800 cmp r0, #0
  1924. 800111c: f040 80d6 bne.w 80012cc <main+0x9ac>
  1925. __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2);
  1926. 8001120: 6828 ldr r0, [r5, #0]
  1927. if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
  1928. 8001122: 2208 movs r2, #8
  1929. 8001124: a917 add r1, sp, #92 @ 0x5c
  1930. __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2);
  1931. 8001126: 6983 ldr r3, [r0, #24]
  1932. 8001128: f423 6300 bic.w r3, r3, #2048 @ 0x800
  1933. 800112c: 6183 str r3, [r0, #24]
  1934. if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
  1935. 800112e: 4628 mov r0, r5
  1936. 8001130: f009 f8f4 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  1937. 8001134: 2800 cmp r0, #0
  1938. 8001136: f040 80c9 bne.w 80012cc <main+0x9ac>
  1939. __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3);
  1940. 800113a: 6828 ldr r0, [r5, #0]
  1941. if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
  1942. 800113c: 220c movs r2, #12
  1943. 800113e: a917 add r1, sp, #92 @ 0x5c
  1944. __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3);
  1945. 8001140: 69c3 ldr r3, [r0, #28]
  1946. 8001142: f023 0308 bic.w r3, r3, #8
  1947. 8001146: 61c3 str r3, [r0, #28]
  1948. if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
  1949. 8001148: 4628 mov r0, r5
  1950. 800114a: f009 f8e7 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  1951. 800114e: 4607 mov r7, r0
  1952. 8001150: 2800 cmp r0, #0
  1953. 8001152: f040 80bb bne.w 80012cc <main+0x9ac>
  1954. __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4);
  1955. 8001156: 682a ldr r2, [r5, #0]
  1956. memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef));
  1957. 8001158: ac17 add r4, sp, #92 @ 0x5c
  1958. 800115a: 4d60 ldr r5, [pc, #384] @ (80012dc <main+0x9bc>)
  1959. __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4);
  1960. 800115c: 69d3 ldr r3, [r2, #28]
  1961. hdac1.Instance = DAC1;
  1962. 800115e: 4e60 ldr r6, [pc, #384] @ (80012e0 <main+0x9c0>)
  1963. __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4);
  1964. 8001160: f423 6300 bic.w r3, r3, #2048 @ 0x800
  1965. 8001164: 61d3 str r3, [r2, #28]
  1966. memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef));
  1967. 8001166: cc0f ldmia r4!, {r0, r1, r2, r3}
  1968. 8001168: c50f stmia r5!, {r0, r1, r2, r3}
  1969. 800116a: e894 0007 ldmia.w r4, {r0, r1, r2}
  1970. 800116e: e885 0007 stmia.w r5, {r0, r1, r2}
  1971. HAL_TIM_MspPostInit(&htim3);
  1972. 8001172: 4857 ldr r0, [pc, #348] @ (80012d0 <main+0x9b0>)
  1973. 8001174: f001 fde4 bl 8002d40 <HAL_TIM_MspPostInit>
  1974. DAC_ChannelConfTypeDef sConfig = {0};
  1975. 8001178: 2224 movs r2, #36 @ 0x24
  1976. 800117a: 4639 mov r1, r7
  1977. 800117c: a83a add r0, sp, #232 @ 0xe8
  1978. 800117e: f00e fcc3 bl 800fb08 <memset>
  1979. hdac1.Instance = DAC1;
  1980. 8001182: 4b58 ldr r3, [pc, #352] @ (80012e4 <main+0x9c4>)
  1981. if (HAL_DAC_Init(&hdac1) != HAL_OK)
  1982. 8001184: 4630 mov r0, r6
  1983. hdac1.Instance = DAC1;
  1984. 8001186: 6033 str r3, [r6, #0]
  1985. if (HAL_DAC_Init(&hdac1) != HAL_OK)
  1986. 8001188: f004 f85e bl 8005248 <HAL_DAC_Init>
  1987. 800118c: 4602 mov r2, r0
  1988. 800118e: 2800 cmp r0, #0
  1989. 8001190: f040 809c bne.w 80012cc <main+0x9ac>
  1990. sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE;
  1991. 8001194: 2301 movs r3, #1
  1992. sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
  1993. 8001196: 903e str r0, [sp, #248] @ 0xf8
  1994. if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK)
  1995. 8001198: a93a add r1, sp, #232 @ 0xe8
  1996. sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
  1997. 800119a: e9cd 003a strd r0, r0, [sp, #232] @ 0xe8
  1998. sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE;
  1999. 800119e: e9cd 033c strd r0, r3, [sp, #240] @ 0xf0
  2000. if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK)
  2001. 80011a2: 4630 mov r0, r6
  2002. 80011a4: f004 f8f0 bl 8005388 <HAL_DAC_ConfigChannel>
  2003. 80011a8: 2800 cmp r0, #0
  2004. 80011aa: f040 808f bne.w 80012cc <main+0x9ac>
  2005. if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK)
  2006. 80011ae: 2210 movs r2, #16
  2007. 80011b0: a93a add r1, sp, #232 @ 0xe8
  2008. 80011b2: 4630 mov r0, r6
  2009. 80011b4: f004 f8e8 bl 8005388 <HAL_DAC_ConfigChannel>
  2010. 80011b8: 4603 mov r3, r0
  2011. 80011ba: 2800 cmp r0, #0
  2012. 80011bc: f040 8086 bne.w 80012cc <main+0x9ac>
  2013. hcomp1.Instance = COMP1;
  2014. 80011c0: 4849 ldr r0, [pc, #292] @ (80012e8 <main+0x9c8>)
  2015. hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO2;
  2016. 80011c2: f44f 1280 mov.w r2, #1048576 @ 0x100000
  2017. hcomp1.Init.InvertingInput = COMP_INPUT_MINUS_3_4VREFINT;
  2018. 80011c6: 4949 ldr r1, [pc, #292] @ (80012ec <main+0x9cc>)
  2019. hcomp1.Instance = COMP1;
  2020. 80011c8: 4c49 ldr r4, [pc, #292] @ (80012f0 <main+0x9d0>)
  2021. hcomp1.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED;
  2022. 80011ca: 6183 str r3, [r0, #24]
  2023. hcomp1.Init.Hysteresis = COMP_HYSTERESIS_NONE;
  2024. 80011cc: 6143 str r3, [r0, #20]
  2025. hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE;
  2026. 80011ce: 61c3 str r3, [r0, #28]
  2027. hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_NONE;
  2028. 80011d0: 6203 str r3, [r0, #32]
  2029. hcomp1.Instance = COMP1;
  2030. 80011d2: 6004 str r4, [r0, #0]
  2031. hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE;
  2032. 80011d4: e9c0 3301 strd r3, r3, [r0, #4]
  2033. hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO2;
  2034. 80011d8: e9c0 2103 strd r2, r1, [r0, #12]
  2035. if (HAL_COMP_Init(&hcomp1) != HAL_OK)
  2036. 80011dc: f003 fda2 bl 8004d24 <HAL_COMP_Init>
  2037. 80011e0: 4603 mov r3, r0
  2038. 80011e2: 2800 cmp r0, #0
  2039. 80011e4: d172 bne.n 80012cc <main+0x9ac>
  2040. htim8.Instance = TIM8;
  2041. 80011e6: 4c43 ldr r4, [pc, #268] @ (80012f4 <main+0x9d4>)
  2042. htim8.Init.Period = 1999;
  2043. 80011e8: f240 72cf movw r2, #1999 @ 0x7cf
  2044. htim8.Instance = TIM8;
  2045. 80011ec: 4942 ldr r1, [pc, #264] @ (80012f8 <main+0x9d8>)
  2046. TIM_ClockConfigTypeDef sClockSourceConfig = {0};
  2047. 80011ee: 9013 str r0, [sp, #76] @ 0x4c
  2048. TIM_MasterConfigTypeDef sMasterConfig = {0};
  2049. 80011f0: 9009 str r0, [sp, #36] @ 0x24
  2050. htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
  2051. 80011f2: f8c4 8018 str.w r8, [r4, #24]
  2052. TIM_ClockConfigTypeDef sClockSourceConfig = {0};
  2053. 80011f6: 9316 str r3, [sp, #88] @ 0x58
  2054. TIM_MasterConfigTypeDef sMasterConfig = {0};
  2055. 80011f8: e9cd 0007 strd r0, r0, [sp, #28]
  2056. htim8.Init.Prescaler = 0;
  2057. 80011fc: e9c4 1000 strd r1, r0, [r4]
  2058. htim8.Init.Period = 1999;
  2059. 8001200: e9c4 0202 strd r0, r2, [r4, #8]
  2060. if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
  2061. 8001204: 4620 mov r0, r4
  2062. htim8.Init.RepetitionCounter = 0;
  2063. 8001206: e9c4 3304 strd r3, r3, [r4, #16]
  2064. TIM_ClockConfigTypeDef sClockSourceConfig = {0};
  2065. 800120a: e9cd 3314 strd r3, r3, [sp, #80] @ 0x50
  2066. if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
  2067. 800120e: f008 fb97 bl 8009940 <HAL_TIM_Base_Init>
  2068. 8001212: 2800 cmp r0, #0
  2069. 8001214: d15a bne.n 80012cc <main+0x9ac>
  2070. sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
  2071. 8001216: f44f 5380 mov.w r3, #4096 @ 0x1000
  2072. if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
  2073. 800121a: a913 add r1, sp, #76 @ 0x4c
  2074. 800121c: 4620 mov r0, r4
  2075. sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
  2076. 800121e: 9313 str r3, [sp, #76] @ 0x4c
  2077. if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
  2078. 8001220: f008 fe9a bl 8009f58 <HAL_TIM_ConfigClockSource>
  2079. 8001224: 4603 mov r3, r0
  2080. 8001226: 2800 cmp r0, #0
  2081. 8001228: d150 bne.n 80012cc <main+0x9ac>
  2082. sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
  2083. 800122a: 2220 movs r2, #32
  2084. if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
  2085. 800122c: 4620 mov r0, r4
  2086. 800122e: a907 add r1, sp, #28
  2087. sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
  2088. 8001230: 9308 str r3, [sp, #32]
  2089. sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
  2090. 8001232: 9207 str r2, [sp, #28]
  2091. sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE;
  2092. 8001234: f8cd 8024 str.w r8, [sp, #36] @ 0x24
  2093. if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
  2094. 8001238: f009 f98a bl 800a550 <HAL_TIMEx_MasterConfigSynchronization>
  2095. 800123c: 2800 cmp r0, #0
  2096. 800123e: d145 bne.n 80012cc <main+0x9ac>
  2097. hiwdg1.Instance = IWDG1;
  2098. 8001240: 482e ldr r0, [pc, #184] @ (80012fc <main+0x9dc>)
  2099. hiwdg1.Init.Window = 249;
  2100. 8001242: 23f9 movs r3, #249 @ 0xf9
  2101. hiwdg1.Instance = IWDG1;
  2102. 8001244: 492e ldr r1, [pc, #184] @ (8001300 <main+0x9e0>)
  2103. hiwdg1.Init.Prescaler = IWDG_PRESCALER_64;
  2104. 8001246: 2204 movs r2, #4
  2105. hiwdg1.Init.Window = 249;
  2106. 8001248: 60c3 str r3, [r0, #12]
  2107. hiwdg1.Init.Reload = 249;
  2108. 800124a: 6083 str r3, [r0, #8]
  2109. hiwdg1.Init.Prescaler = IWDG_PRESCALER_64;
  2110. 800124c: e9c0 1200 strd r1, r2, [r0]
  2111. if (HAL_IWDG_Init(&hiwdg1) != HAL_OK)
  2112. 8001250: f005 ffd0 bl 80071f4 <HAL_IWDG_Init>
  2113. 8001254: 2800 cmp r0, #0
  2114. 8001256: d139 bne.n 80012cc <main+0x9ac>
  2115. HAL_IWDG_Refresh(&hiwdg1);
  2116. 8001258: 4828 ldr r0, [pc, #160] @ (80012fc <main+0x9dc>)
  2117. 800125a: f005 fff9 bl 8007250 <HAL_IWDG_Refresh>
  2118. debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes);
  2119. 800125e: 4c29 ldr r4, [pc, #164] @ (8001304 <main+0x9e4>)
  2120. osKernelInitialize();
  2121. 8001260: f00a fc98 bl 800bb94 <osKernelInitialize>
  2122. debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes);
  2123. 8001264: 2200 movs r2, #0
  2124. 8001266: 4b28 ldr r3, [pc, #160] @ (8001308 <main+0x9e8>)
  2125. 8001268: 4611 mov r1, r2
  2126. 800126a: 4828 ldr r0, [pc, #160] @ (800130c <main+0x9ec>)
  2127. 800126c: f00a fd10 bl 800bc90 <osTimerNew>
  2128. fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes);
  2129. 8001270: 2200 movs r2, #0
  2130. debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes);
  2131. 8001272: 6020 str r0, [r4, #0]
  2132. fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes);
  2133. 8001274: 4c26 ldr r4, [pc, #152] @ (8001310 <main+0x9f0>)
  2134. 8001276: 4611 mov r1, r2
  2135. 8001278: 4b26 ldr r3, [pc, #152] @ (8001314 <main+0x9f4>)
  2136. 800127a: 4827 ldr r0, [pc, #156] @ (8001318 <main+0x9f8>)
  2137. 800127c: f00a fd08 bl 800bc90 <osTimerNew>
  2138. 8001280: 6020 str r0, [r4, #0]
  2139. motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes);
  2140. 8001282: 4c26 ldr r4, [pc, #152] @ (800131c <main+0x9fc>)
  2141. 8001284: 2200 movs r2, #0
  2142. 8001286: 4b26 ldr r3, [pc, #152] @ (8001320 <main+0xa00>)
  2143. 8001288: 2101 movs r1, #1
  2144. 800128a: 4826 ldr r0, [pc, #152] @ (8001324 <main+0xa04>)
  2145. 800128c: f00a fd00 bl 800bc90 <osTimerNew>
  2146. motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes);
  2147. 8001290: 4b25 ldr r3, [pc, #148] @ (8001328 <main+0xa08>)
  2148. motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes);
  2149. 8001292: 6020 str r0, [r4, #0]
  2150. motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes);
  2151. 8001294: 2200 movs r2, #0
  2152. 8001296: 2101 movs r1, #1
  2153. 8001298: 4824 ldr r0, [pc, #144] @ (800132c <main+0xa0c>)
  2154. 800129a: f00a fcf9 bl 800bc90 <osTimerNew>
  2155. 800129e: 4b24 ldr r3, [pc, #144] @ (8001330 <main+0xa10>)
  2156. 80012a0: 4604 mov r4, r0
  2157. defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
  2158. 80012a2: 2100 movs r1, #0
  2159. 80012a4: 4a23 ldr r2, [pc, #140] @ (8001334 <main+0xa14>)
  2160. 80012a6: 4824 ldr r0, [pc, #144] @ (8001338 <main+0xa18>)
  2161. motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes);
  2162. 80012a8: 601c str r4, [r3, #0]
  2163. defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
  2164. 80012aa: f00a fc9f bl 800bbec <osThreadNew>
  2165. 80012ae: 4b23 ldr r3, [pc, #140] @ (800133c <main+0xa1c>)
  2166. 80012b0: 4602 mov r2, r0
  2167. HAL_IWDG_Refresh(&hiwdg1);
  2168. 80012b2: 4812 ldr r0, [pc, #72] @ (80012fc <main+0x9dc>)
  2169. defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
  2170. 80012b4: 601a str r2, [r3, #0]
  2171. HAL_IWDG_Refresh(&hiwdg1);
  2172. 80012b6: f005 ffcb bl 8007250 <HAL_IWDG_Refresh>
  2173. UartTasksInit();
  2174. 80012ba: f002 fd7f bl 8003dbc <UartTasksInit>
  2175. MeasTasksInit();
  2176. 80012be: f000 fda1 bl 8001e04 <MeasTasksInit>
  2177. PositionControlTaskInit();
  2178. 80012c2: f001 f99b bl 80025fc <PositionControlTaskInit>
  2179. osKernelStart();
  2180. 80012c6: f00a fc77 bl 800bbb8 <osKernelStart>
  2181. while (1)
  2182. 80012ca: e7fe b.n 80012ca <main+0x9aa>
  2183. Error_Handler();
  2184. 80012cc: f7ff fa94 bl 80007f8 <Error_Handler>
  2185. 80012d0: 24000500 .word 0x24000500
  2186. 80012d4: 40000400 .word 0x40000400
  2187. 80012d8: 00010040 .word 0x00010040
  2188. 80012dc: 24000290 .word 0x24000290
  2189. 80012e0: 240005bc .word 0x240005bc
  2190. 80012e4: 40007400 .word 0x40007400
  2191. 80012e8: 240005f4 .word 0x240005f4
  2192. 80012ec: 00020006 .word 0x00020006
  2193. 80012f0: 5800380c .word 0x5800380c
  2194. 80012f4: 240004b4 .word 0x240004b4
  2195. 80012f8: 40010400 .word 0x40010400
  2196. 80012fc: 240005ac .word 0x240005ac
  2197. 8001300: 58004800 .word 0x58004800
  2198. 8001304: 24000384 .word 0x24000384
  2199. 8001308: 080119d0 .word 0x080119d0
  2200. 800130c: 08000685 .word 0x08000685
  2201. 8001310: 24000354 .word 0x24000354
  2202. 8001314: 080119c0 .word 0x080119c0
  2203. 8001318: 0800068d .word 0x0800068d
  2204. 800131c: 24000324 .word 0x24000324
  2205. 8001320: 080119b0 .word 0x080119b0
  2206. 8001324: 08000699 .word 0x08000699
  2207. 8001328: 080119a0 .word 0x080119a0
  2208. 800132c: 080006d1 .word 0x080006d1
  2209. 8001330: 240002f4 .word 0x240002f4
  2210. 8001334: 080119e0 .word 0x080119e0
  2211. 8001338: 08001401 .word 0x08001401
  2212. 800133c: 24000388 .word 0x24000388
  2213. 8001340: 240002ac .word 0x240002ac
  2214. 08001344 <HAL_ADC_ConvCpltCallback>:
  2215. if(hadc->Instance == ADC1)
  2216. 8001344: 4a24 ldr r2, [pc, #144] @ (80013d8 <HAL_ADC_ConvCpltCallback+0x94>)
  2217. 8001346: 6803 ldr r3, [r0, #0]
  2218. 8001348: 4293 cmp r3, r2
  2219. {
  2220. 800134a: b510 push {r4, lr}
  2221. if(hadc->Instance == ADC1)
  2222. 800134c: d024 beq.n 8001398 <HAL_ADC_ConvCpltCallback+0x54>
  2223. if(hadc->Instance == ADC3)
  2224. 800134e: 4a23 ldr r2, [pc, #140] @ (80013dc <HAL_ADC_ConvCpltCallback+0x98>)
  2225. 8001350: 4293 cmp r3, r2
  2226. 8001352: d005 beq.n 8001360 <HAL_ADC_ConvCpltCallback+0x1c>
  2227. osTimerStop (debugLedTimerHandle);
  2228. 8001354: 4b22 ldr r3, [pc, #136] @ (80013e0 <HAL_ADC_ConvCpltCallback+0x9c>)
  2229. }
  2230. 8001356: e8bd 4010 ldmia.w sp!, {r4, lr}
  2231. osTimerStop (debugLedTimerHandle);
  2232. 800135a: 6818 ldr r0, [r3, #0]
  2233. 800135c: f00a bcf0 b.w 800bd40 <osTimerStop>
  2234. SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc3Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE);
  2235. 8001360: 4920 ldr r1, [pc, #128] @ (80013e4 <HAL_ADC_ConvCpltCallback+0xa0>)
  2236. 8001362: f021 021f bic.w r2, r1, #31
  2237. __ASM volatile ("dsb 0xF":::"memory");
  2238. 8001366: f3bf 8f4f dsb sy
  2239. SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
  2240. 800136a: 4b1f ldr r3, [pc, #124] @ (80013e8 <HAL_ADC_ConvCpltCallback+0xa4>)
  2241. 800136c: f8c3 225c str.w r2, [r3, #604] @ 0x25c
  2242. 8001370: f3bf 8f4f dsb sy
  2243. __ASM volatile ("isb 0xF":::"memory");
  2244. 8001374: f3bf 8f6f isb sy
  2245. if(adc3MeasDataQueue != NULL)
  2246. 8001378: 4b1c ldr r3, [pc, #112] @ (80013ec <HAL_ADC_ConvCpltCallback+0xa8>)
  2247. 800137a: 6818 ldr r0, [r3, #0]
  2248. 800137c: b118 cbz r0, 8001386 <HAL_ADC_ConvCpltCallback+0x42>
  2249. osMessageQueuePut(adc3MeasDataQueue, &adc3Data, 0, 0);
  2250. 800137e: 2300 movs r3, #0
  2251. 8001380: 461a mov r2, r3
  2252. 8001382: f00a fdc1 bl 800bf08 <osMessageQueuePut>
  2253. if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData*sizeof(uint16_t)) != HAL_OK)
  2254. 8001386: 220a movs r2, #10
  2255. 8001388: 4916 ldr r1, [pc, #88] @ (80013e4 <HAL_ADC_ConvCpltCallback+0xa0>)
  2256. 800138a: 4819 ldr r0, [pc, #100] @ (80013f0 <HAL_ADC_ConvCpltCallback+0xac>)
  2257. 800138c: f003 f906 bl 800459c <HAL_ADC_Start_DMA>
  2258. 8001390: 2800 cmp r0, #0
  2259. 8001392: d0df beq.n 8001354 <HAL_ADC_ConvCpltCallback+0x10>
  2260. Error_Handler();
  2261. 8001394: f7ff fa30 bl 80007f8 <Error_Handler>
  2262. DbgLEDToggle(DBG_LED4);
  2263. 8001398: 4604 mov r4, r0
  2264. 800139a: 2080 movs r0, #128 @ 0x80
  2265. 800139c: f000 fe2e bl 8001ffc <DbgLEDToggle>
  2266. SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc1Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE);
  2267. 80013a0: 4914 ldr r1, [pc, #80] @ (80013f4 <HAL_ADC_ConvCpltCallback+0xb0>)
  2268. 80013a2: f021 021f bic.w r2, r1, #31
  2269. __ASM volatile ("dsb 0xF":::"memory");
  2270. 80013a6: f3bf 8f4f dsb sy
  2271. 80013aa: 4b0f ldr r3, [pc, #60] @ (80013e8 <HAL_ADC_ConvCpltCallback+0xa4>)
  2272. 80013ac: f8c3 225c str.w r2, [r3, #604] @ 0x25c
  2273. 80013b0: f3bf 8f4f dsb sy
  2274. __ASM volatile ("isb 0xF":::"memory");
  2275. 80013b4: f3bf 8f6f isb sy
  2276. if(adc1MeasDataQueue != NULL)
  2277. 80013b8: 4b0f ldr r3, [pc, #60] @ (80013f8 <HAL_ADC_ConvCpltCallback+0xb4>)
  2278. 80013ba: 6818 ldr r0, [r3, #0]
  2279. 80013bc: b118 cbz r0, 80013c6 <HAL_ADC_ConvCpltCallback+0x82>
  2280. osMessageQueuePut(adc1MeasDataQueue, &adc1Data, 0, 0);
  2281. 80013be: 2300 movs r3, #0
  2282. 80013c0: 461a mov r2, r3
  2283. 80013c2: f00a fda1 bl 800bf08 <osMessageQueuePut>
  2284. if(HAL_ADCEx_MultiModeStart_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData*sizeof(uint16_t)) != HAL_OK)
  2285. 80013c6: 2214 movs r2, #20
  2286. 80013c8: 490a ldr r1, [pc, #40] @ (80013f4 <HAL_ADC_ConvCpltCallback+0xb0>)
  2287. 80013ca: 480c ldr r0, [pc, #48] @ (80013fc <HAL_ADC_ConvCpltCallback+0xb8>)
  2288. 80013cc: f003 fbc8 bl 8004b60 <HAL_ADCEx_MultiModeStart_DMA>
  2289. 80013d0: 2800 cmp r0, #0
  2290. 80013d2: d1df bne.n 8001394 <HAL_ADC_ConvCpltCallback+0x50>
  2291. if(hadc->Instance == ADC3)
  2292. 80013d4: 6823 ldr r3, [r4, #0]
  2293. 80013d6: e7ba b.n 800134e <HAL_ADC_ConvCpltCallback+0xa>
  2294. 80013d8: 40022000 .word 0x40022000
  2295. 80013dc: 58026000 .word 0x58026000
  2296. 80013e0: 24000384 .word 0x24000384
  2297. 80013e4: 24000240 .word 0x24000240
  2298. 80013e8: e000ed00 .word 0xe000ed00
  2299. 80013ec: 2400098c .word 0x2400098c
  2300. 80013f0: 24000788 .word 0x24000788
  2301. 80013f4: 24000260 .word 0x24000260
  2302. 80013f8: 24000994 .word 0x24000994
  2303. 80013fc: 24000850 .word 0x24000850
  2304. 08001400 <StartDefaultTask>:
  2305. {
  2306. 8001400: b580 push {r7, lr}
  2307. HAL_IWDG_Refresh(&hiwdg1);
  2308. 8001402: 4839 ldr r0, [pc, #228] @ (80014e8 <StartDefaultTask+0xe8>)
  2309. 8001404: f005 ff24 bl 8007250 <HAL_IWDG_Refresh>
  2310. SelectCurrentSensorGain(CurrentSensorL1, csGain3);
  2311. 8001408: 2102 movs r1, #2
  2312. 800140a: 2000 movs r0, #0
  2313. 800140c: f000 fe04 bl 8002018 <SelectCurrentSensorGain>
  2314. SelectCurrentSensorGain(CurrentSensorL2, csGain3);
  2315. 8001410: 2102 movs r1, #2
  2316. 8001412: 2001 movs r0, #1
  2317. 8001414: f000 fe00 bl 8002018 <SelectCurrentSensorGain>
  2318. SelectCurrentSensorGain(CurrentSensorL3, csGain3);
  2319. 8001418: 2102 movs r1, #2
  2320. 800141a: 4608 mov r0, r1
  2321. 800141c: f000 fdfc bl 8002018 <SelectCurrentSensorGain>
  2322. EnableCurrentSensors();
  2323. 8001420: f000 fdf2 bl 8002008 <EnableCurrentSensors>
  2324. osDelay(pdMS_TO_TICKS(100));
  2325. 8001424: 2064 movs r0, #100 @ 0x64
  2326. 8001426: f00a fc25 bl 800bc74 <osDelay>
  2327. HAL_IWDG_Refresh(&hiwdg1);
  2328. 800142a: 482f ldr r0, [pc, #188] @ (80014e8 <StartDefaultTask+0xe8>)
  2329. 800142c: f005 ff10 bl 8007250 <HAL_IWDG_Refresh>
  2330. if(HAL_TIM_Base_Start(&htim8) != HAL_OK)
  2331. 8001430: 482e ldr r0, [pc, #184] @ (80014ec <StartDefaultTask+0xec>)
  2332. 8001432: f008 fb2b bl 8009a8c <HAL_TIM_Base_Start>
  2333. 8001436: b928 cbnz r0, 8001444 <StartDefaultTask+0x44>
  2334. if(HAL_ADCEx_MultiModeStart_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData*sizeof(uint16_t)) != HAL_OK)
  2335. 8001438: 2214 movs r2, #20
  2336. 800143a: 492d ldr r1, [pc, #180] @ (80014f0 <StartDefaultTask+0xf0>)
  2337. 800143c: 482d ldr r0, [pc, #180] @ (80014f4 <StartDefaultTask+0xf4>)
  2338. 800143e: f003 fb8f bl 8004b60 <HAL_ADCEx_MultiModeStart_DMA>
  2339. 8001442: b108 cbz r0, 8001448 <StartDefaultTask+0x48>
  2340. Error_Handler();
  2341. 8001444: f7ff f9d8 bl 80007f8 <Error_Handler>
  2342. if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData*sizeof(uint16_t)) != HAL_OK)
  2343. 8001448: 220a movs r2, #10
  2344. 800144a: 492b ldr r1, [pc, #172] @ (80014f8 <StartDefaultTask+0xf8>)
  2345. 800144c: 482b ldr r0, [pc, #172] @ (80014fc <StartDefaultTask+0xfc>)
  2346. 800144e: f003 f8a5 bl 800459c <HAL_ADC_Start_DMA>
  2347. 8001452: 2800 cmp r0, #0
  2348. 8001454: d1f6 bne.n 8001444 <StartDefaultTask+0x44>
  2349. HAL_IWDG_Refresh(&hiwdg1);
  2350. 8001456: 4d24 ldr r5, [pc, #144] @ (80014e8 <StartDefaultTask+0xe8>)
  2351. HAL_COMP_Start(&hcomp1);
  2352. 8001458: 4829 ldr r0, [pc, #164] @ (8001500 <StartDefaultTask+0x100>)
  2353. 800145a: f003 fd13 bl 8004e84 <HAL_COMP_Start>
  2354. HAL_IWDG_Refresh(&hiwdg1);
  2355. 800145e: 4628 mov r0, r5
  2356. 8001460: 4e28 ldr r6, [pc, #160] @ (8001504 <StartDefaultTask+0x104>)
  2357. 8001462: 4f29 ldr r7, [pc, #164] @ (8001508 <StartDefaultTask+0x108>)
  2358. if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY &&
  2359. 8001464: 4c29 ldr r4, [pc, #164] @ (800150c <StartDefaultTask+0x10c>)
  2360. HAL_IWDG_Refresh(&hiwdg1);
  2361. 8001466: f005 fef3 bl 8007250 <HAL_IWDG_Refresh>
  2362. 800146a: e005 b.n 8001478 <StartDefaultTask+0x78>
  2363. if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY &&
  2364. 800146c: 2108 movs r1, #8
  2365. 800146e: 4620 mov r0, r4
  2366. 8001470: f008 feec bl 800a24c <HAL_TIM_GetChannelState>
  2367. 8001474: 2801 cmp r0, #1
  2368. 8001476: d023 beq.n 80014c0 <StartDefaultTask+0xc0>
  2369. osDelay(pdMS_TO_TICKS(100));
  2370. 8001478: 2064 movs r0, #100 @ 0x64
  2371. 800147a: f00a fbfb bl 800bc74 <osDelay>
  2372. HAL_IWDG_Refresh(&hiwdg1);
  2373. 800147e: 4628 mov r0, r5
  2374. 8001480: f005 fee6 bl 8007250 <HAL_IWDG_Refresh>
  2375. if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY &&
  2376. 8001484: 2100 movs r1, #0
  2377. 8001486: 4620 mov r0, r4
  2378. 8001488: f008 fee0 bl 800a24c <HAL_TIM_GetChannelState>
  2379. 800148c: 2801 cmp r0, #1
  2380. 800148e: d1ed bne.n 800146c <StartDefaultTask+0x6c>
  2381. HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_2) == HAL_TIM_CHANNEL_STATE_READY)
  2382. 8001490: 2104 movs r1, #4
  2383. 8001492: 4620 mov r0, r4
  2384. 8001494: f008 feda bl 800a24c <HAL_TIM_GetChannelState>
  2385. if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY &&
  2386. 8001498: 2801 cmp r0, #1
  2387. 800149a: d1e7 bne.n 800146c <StartDefaultTask+0x6c>
  2388. if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK)
  2389. 800149c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  2390. 80014a0: 6830 ldr r0, [r6, #0]
  2391. 80014a2: f00a fcaf bl 800be04 <osMutexAcquire>
  2392. 80014a6: 4603 mov r3, r0
  2393. 80014a8: 2800 cmp r0, #0
  2394. 80014aa: d1df bne.n 800146c <StartDefaultTask+0x6c>
  2395. osMutexRelease(sensorsInfoMutex);
  2396. 80014ac: 6830 ldr r0, [r6, #0]
  2397. sensorsInfo.motorXStatus = 0;
  2398. 80014ae: 753b strb r3, [r7, #20]
  2399. osMutexRelease(sensorsInfoMutex);
  2400. 80014b0: f00a fccc bl 800be4c <osMutexRelease>
  2401. if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY &&
  2402. 80014b4: 2108 movs r1, #8
  2403. 80014b6: 4620 mov r0, r4
  2404. 80014b8: f008 fec8 bl 800a24c <HAL_TIM_GetChannelState>
  2405. 80014bc: 2801 cmp r0, #1
  2406. 80014be: d1db bne.n 8001478 <StartDefaultTask+0x78>
  2407. HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_4) == HAL_TIM_CHANNEL_STATE_READY)
  2408. 80014c0: 210c movs r1, #12
  2409. 80014c2: 4620 mov r0, r4
  2410. 80014c4: f008 fec2 bl 800a24c <HAL_TIM_GetChannelState>
  2411. if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY &&
  2412. 80014c8: 2801 cmp r0, #1
  2413. 80014ca: d1d5 bne.n 8001478 <StartDefaultTask+0x78>
  2414. if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK)
  2415. 80014cc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  2416. 80014d0: 6830 ldr r0, [r6, #0]
  2417. 80014d2: f00a fc97 bl 800be04 <osMutexAcquire>
  2418. 80014d6: 4603 mov r3, r0
  2419. 80014d8: 2800 cmp r0, #0
  2420. 80014da: d1cd bne.n 8001478 <StartDefaultTask+0x78>
  2421. osMutexRelease(sensorsInfoMutex);
  2422. 80014dc: 6830 ldr r0, [r6, #0]
  2423. sensorsInfo.motorYStatus = 0;
  2424. 80014de: 757b strb r3, [r7, #21]
  2425. osMutexRelease(sensorsInfoMutex);
  2426. 80014e0: f00a fcb4 bl 800be4c <osMutexRelease>
  2427. 80014e4: e7c8 b.n 8001478 <StartDefaultTask+0x78>
  2428. 80014e6: bf00 nop
  2429. 80014e8: 240005ac .word 0x240005ac
  2430. 80014ec: 240004b4 .word 0x240004b4
  2431. 80014f0: 24000260 .word 0x24000260
  2432. 80014f4: 24000850 .word 0x24000850
  2433. 80014f8: 24000240 .word 0x24000240
  2434. 80014fc: 24000788 .word 0x24000788
  2435. 8001500: 240005f4 .word 0x240005f4
  2436. 8001504: 24000980 .word 0x24000980
  2437. 8001508: 24000900 .word 0x24000900
  2438. 800150c: 24000500 .word 0x24000500
  2439. 08001510 <ADC3MeasTask>:
  2440. osMutexRelease (resMeasurementsMutex);
  2441. }
  2442. }
  2443. }
  2444. void ADC3MeasTask (void* arg) {
  2445. 8001510: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  2446. 8001514: ed2d 8b10 vpush {d8-d15}
  2447. 8001518: b0cb sub sp, #300 @ 0x12c
  2448. float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 };
  2449. 800151a: 2228 movs r2, #40 @ 0x28
  2450. 800151c: 2100 movs r1, #0
  2451. float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 };
  2452. #ifdef PV_BOARD
  2453. float pvT1CircBuffer[CIRC_BUFF_LEN] = { 0 };
  2454. float pvT2CircBuffer[CIRC_BUFF_LEN] = { 0 };
  2455. #endif
  2456. uint32_t circBuffPos = 0;
  2457. 800151e: 2400 movs r4, #0
  2458. float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 };
  2459. 8001520: a822 add r0, sp, #136 @ 0x88
  2460. 8001522: f8df b3a8 ldr.w fp, [pc, #936] @ 80018cc <ADC3MeasTask+0x3bc>
  2461. 8001526: f00e faef bl 800fb08 <memset>
  2462. float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 };
  2463. 800152a: 2228 movs r2, #40 @ 0x28
  2464. 800152c: 2100 movs r1, #0
  2465. 800152e: a82c add r0, sp, #176 @ 0xb0
  2466. 8001530: f00e faea bl 800fb08 <memset>
  2467. float pvT1CircBuffer[CIRC_BUFF_LEN] = { 0 };
  2468. 8001534: 2228 movs r2, #40 @ 0x28
  2469. 8001536: 2100 movs r1, #0
  2470. 8001538: a836 add r0, sp, #216 @ 0xd8
  2471. 800153a: f00e fae5 bl 800fb08 <memset>
  2472. float pvT2CircBuffer[CIRC_BUFF_LEN] = { 0 };
  2473. 800153e: 2228 movs r2, #40 @ 0x28
  2474. 8001540: 4621 mov r1, r4
  2475. 8001542: a840 add r0, sp, #256 @ 0x100
  2476. 8001544: f00e fae0 bl 800fb08 <memset>
  2477. ADC3_Data adcData = { 0 };
  2478. 8001548: 2220 movs r2, #32
  2479. 800154a: 4621 mov r1, r4
  2480. 800154c: a81a add r0, sp, #104 @ 0x68
  2481. 800154e: f8df 8380 ldr.w r8, [pc, #896] @ 80018d0 <ADC3MeasTask+0x3c0>
  2482. 8001552: f00e fad9 bl 800fb08 <memset>
  2483. 8001556: 4fd8 ldr r7, [pc, #864] @ (80018b8 <ADC3MeasTask+0x3a8>)
  2484. 8001558: 4dd8 ldr r5, [pc, #864] @ (80018bc <ADC3MeasTask+0x3ac>)
  2485. while (pdTRUE) {
  2486. osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever);
  2487. uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B);
  2488. 800155a: f8df a378 ldr.w sl, [pc, #888] @ 80018d4 <ADC3MeasTask+0x3c4>
  2489. 800155e: e17c b.n 800185a <ADC3MeasTask+0x34a>
  2490. float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333;
  2491. float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333;
  2492. motorXSensCircBuffer[circBuffPos] = motorXCurrentSense;
  2493. motorYSensCircBuffer[circBuffPos] = motorYCurrentSense;
  2494. #ifdef PV_BOARD
  2495. pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63;
  2496. 8001560: f8bd 3068 ldrh.w r3, [sp, #104] @ 0x68
  2497. }
  2498. motorXAveCurrent /= CIRC_BUFF_LEN;
  2499. motorYAveCurrent /= CIRC_BUFF_LEN;
  2500. pvT1AveTemp /= CIRC_BUFF_LEN;
  2501. pvT2AveTemp /= CIRC_BUFF_LEN;
  2502. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  2503. 8001564: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  2504. pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63;
  2505. 8001568: ee05 3a10 vmov s10, r3
  2506. pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63;
  2507. 800156c: f8bd 306a ldrh.w r3, [sp, #106] @ 0x6a
  2508. pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63;
  2509. 8001570: eeb8 5bc5 vcvt.f64.s32 d5, s10
  2510. pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63;
  2511. 8001574: ee03 3a10 vmov s6, r3
  2512. float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333;
  2513. 8001578: f8bd 306c ldrh.w r3, [sp, #108] @ 0x6c
  2514. pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63;
  2515. 800157c: eeb8 3bc3 vcvt.f64.s32 d3, s6
  2516. float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333;
  2517. 8001580: ee06 3a10 vmov s12, r3
  2518. float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333;
  2519. 8001584: f8bd 306e ldrh.w r3, [sp, #110] @ 0x6e
  2520. pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63;
  2521. 8001588: ed9f 2bc5 vldr d2, [pc, #788] @ 80018a0 <ADC3MeasTask+0x390>
  2522. 800158c: ed9f 4bc6 vldr d4, [pc, #792] @ 80018a8 <ADC3MeasTask+0x398>
  2523. float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333;
  2524. 8001590: ee07 3a10 vmov s14, r3
  2525. float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333;
  2526. 8001594: eeb8 6bc6 vcvt.f64.s32 d6, s12
  2527. motorXSensCircBuffer[circBuffPos] = motorXCurrentSense;
  2528. 8001598: ab4a add r3, sp, #296 @ 0x128
  2529. pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63;
  2530. 800159a: eea5 4b02 vfma.f64 d4, d5, d2
  2531. motorXSensCircBuffer[circBuffPos] = motorXCurrentSense;
  2532. 800159e: eb03 0384 add.w r3, r3, r4, lsl #2
  2533. float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333;
  2534. 80015a2: eeb8 7bc7 vcvt.f64.s32 d7, s14
  2535. pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63;
  2536. 80015a6: ed9f 5bc0 vldr d5, [pc, #768] @ 80018a8 <ADC3MeasTask+0x398>
  2537. 80015aa: eea3 5b02 vfma.f64 d5, d3, d2
  2538. pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63;
  2539. 80015ae: eeb7 4bc4 vcvt.f32.f64 s8, d4
  2540. float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333;
  2541. 80015b2: ed9f 3bbf vldr d3, [pc, #764] @ 80018b0 <ADC3MeasTask+0x3a0>
  2542. pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63;
  2543. 80015b6: ed03 4a14 vstr s8, [r3, #-80] @ 0xffffffb0
  2544. pvT1AveTemp += pvT1CircBuffer[i];
  2545. 80015ba: eddd fa38 vldr s31, [sp, #224] @ 0xe0
  2546. float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333;
  2547. 80015be: ee26 6b03 vmul.f64 d6, d6, d3
  2548. float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333;
  2549. 80015c2: ee27 7b03 vmul.f64 d7, d7, d3
  2550. float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333;
  2551. 80015c6: eef7 8bc6 vcvt.f32.f64 s17, d6
  2552. pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63;
  2553. 80015ca: eeb7 5bc5 vcvt.f32.f64 s10, d5
  2554. float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333;
  2555. 80015ce: eeb7 8bc7 vcvt.f32.f64 s16, d7
  2556. motorXSensCircBuffer[circBuffPos] = motorXCurrentSense;
  2557. 80015d2: ed43 8a28 vstr s17, [r3, #-160] @ 0xffffff60
  2558. motorXAveCurrent += motorXSensCircBuffer[i];
  2559. 80015d6: eddd 7a22 vldr s15, [sp, #136] @ 0x88
  2560. pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63;
  2561. 80015da: ed03 5a0a vstr s10, [r3, #-40] @ 0xffffffd8
  2562. motorYSensCircBuffer[circBuffPos] = motorYCurrentSense;
  2563. 80015de: ed03 8a1e vstr s16, [r3, #-120] @ 0xffffff88
  2564. motorXAveCurrent += motorXSensCircBuffer[i];
  2565. 80015e2: edcd 7a06 vstr s15, [sp, #24]
  2566. motorYAveCurrent += motorYSensCircBuffer[i];
  2567. 80015e6: eddd 7a2c vldr s15, [sp, #176] @ 0xb0
  2568. pvT2AveTemp += pvT2CircBuffer[i];
  2569. 80015ea: ed9d fa42 vldr s30, [sp, #264] @ 0x108
  2570. motorYAveCurrent += motorYSensCircBuffer[i];
  2571. 80015ee: edcd 7a07 vstr s15, [sp, #28]
  2572. pvT1AveTemp += pvT1CircBuffer[i];
  2573. 80015f2: eddd 7a36 vldr s15, [sp, #216] @ 0xd8
  2574. 80015f6: edcd 7a00 vstr s15, [sp]
  2575. pvT2AveTemp += pvT2CircBuffer[i];
  2576. 80015fa: eddd 7a40 vldr s15, [sp, #256] @ 0x100
  2577. 80015fe: edcd 7a01 vstr s15, [sp, #4]
  2578. motorXAveCurrent += motorXSensCircBuffer[i];
  2579. 8001602: eddd 7a23 vldr s15, [sp, #140] @ 0x8c
  2580. 8001606: edcd 7a08 vstr s15, [sp, #32]
  2581. motorYAveCurrent += motorYSensCircBuffer[i];
  2582. 800160a: eddd 7a2d vldr s15, [sp, #180] @ 0xb4
  2583. 800160e: edcd 7a09 vstr s15, [sp, #36] @ 0x24
  2584. pvT1AveTemp += pvT1CircBuffer[i];
  2585. 8001612: eddd 7a37 vldr s15, [sp, #220] @ 0xdc
  2586. 8001616: edcd 7a02 vstr s15, [sp, #8]
  2587. pvT2AveTemp += pvT2CircBuffer[i];
  2588. 800161a: eddd 7a41 vldr s15, [sp, #260] @ 0x104
  2589. 800161e: edcd 7a03 vstr s15, [sp, #12]
  2590. motorXAveCurrent += motorXSensCircBuffer[i];
  2591. 8001622: eddd 7a24 vldr s15, [sp, #144] @ 0x90
  2592. 8001626: edcd 7a0a vstr s15, [sp, #40] @ 0x28
  2593. motorYAveCurrent += motorYSensCircBuffer[i];
  2594. 800162a: eddd 7a2e vldr s15, [sp, #184] @ 0xb8
  2595. 800162e: edcd 7a0b vstr s15, [sp, #44] @ 0x2c
  2596. motorXAveCurrent += motorXSensCircBuffer[i];
  2597. 8001632: eddd 7a25 vldr s15, [sp, #148] @ 0x94
  2598. 8001636: edcd 7a0c vstr s15, [sp, #48] @ 0x30
  2599. motorYAveCurrent += motorYSensCircBuffer[i];
  2600. 800163a: eddd 7a2f vldr s15, [sp, #188] @ 0xbc
  2601. pvT1AveTemp += pvT1CircBuffer[i];
  2602. 800163e: eddd ea39 vldr s29, [sp, #228] @ 0xe4
  2603. motorYAveCurrent += motorYSensCircBuffer[i];
  2604. 8001642: edcd 7a0d vstr s15, [sp, #52] @ 0x34
  2605. motorXAveCurrent += motorXSensCircBuffer[i];
  2606. 8001646: eddd 7a26 vldr s15, [sp, #152] @ 0x98
  2607. pvT2AveTemp += pvT2CircBuffer[i];
  2608. 800164a: ed9d ea43 vldr s28, [sp, #268] @ 0x10c
  2609. motorXAveCurrent += motorXSensCircBuffer[i];
  2610. 800164e: edcd 7a0e vstr s15, [sp, #56] @ 0x38
  2611. motorYAveCurrent += motorYSensCircBuffer[i];
  2612. 8001652: eddd 7a30 vldr s15, [sp, #192] @ 0xc0
  2613. pvT1AveTemp += pvT1CircBuffer[i];
  2614. 8001656: eddd da3a vldr s27, [sp, #232] @ 0xe8
  2615. motorYAveCurrent += motorYSensCircBuffer[i];
  2616. 800165a: edcd 7a0f vstr s15, [sp, #60] @ 0x3c
  2617. motorXAveCurrent += motorXSensCircBuffer[i];
  2618. 800165e: eddd 7a27 vldr s15, [sp, #156] @ 0x9c
  2619. pvT2AveTemp += pvT2CircBuffer[i];
  2620. 8001662: ed9d da44 vldr s26, [sp, #272] @ 0x110
  2621. motorXAveCurrent += motorXSensCircBuffer[i];
  2622. 8001666: edcd 7a10 vstr s15, [sp, #64] @ 0x40
  2623. motorYAveCurrent += motorYSensCircBuffer[i];
  2624. 800166a: eddd 7a31 vldr s15, [sp, #196] @ 0xc4
  2625. pvT1AveTemp += pvT1CircBuffer[i];
  2626. 800166e: eddd ca3b vldr s25, [sp, #236] @ 0xec
  2627. motorYAveCurrent += motorYSensCircBuffer[i];
  2628. 8001672: edcd 7a11 vstr s15, [sp, #68] @ 0x44
  2629. motorXAveCurrent += motorXSensCircBuffer[i];
  2630. 8001676: eddd 7a28 vldr s15, [sp, #160] @ 0xa0
  2631. pvT2AveTemp += pvT2CircBuffer[i];
  2632. 800167a: ed9d ca45 vldr s24, [sp, #276] @ 0x114
  2633. motorXAveCurrent += motorXSensCircBuffer[i];
  2634. 800167e: edcd 7a12 vstr s15, [sp, #72] @ 0x48
  2635. motorYAveCurrent += motorYSensCircBuffer[i];
  2636. 8001682: eddd 7a32 vldr s15, [sp, #200] @ 0xc8
  2637. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  2638. 8001686: 6838 ldr r0, [r7, #0]
  2639. motorYAveCurrent += motorYSensCircBuffer[i];
  2640. 8001688: edcd 7a13 vstr s15, [sp, #76] @ 0x4c
  2641. pvT2AveTemp += pvT2CircBuffer[i];
  2642. 800168c: eddd 7a46 vldr s15, [sp, #280] @ 0x118
  2643. pvT1AveTemp += pvT1CircBuffer[i];
  2644. 8001690: eddd ba3c vldr s23, [sp, #240] @ 0xf0
  2645. pvT2AveTemp += pvT2CircBuffer[i];
  2646. 8001694: edcd 7a04 vstr s15, [sp, #16]
  2647. motorXAveCurrent += motorXSensCircBuffer[i];
  2648. 8001698: eddd 7a29 vldr s15, [sp, #164] @ 0xa4
  2649. pvT1AveTemp += pvT1CircBuffer[i];
  2650. 800169c: ed9d ba3d vldr s22, [sp, #244] @ 0xf4
  2651. motorXAveCurrent += motorXSensCircBuffer[i];
  2652. 80016a0: edcd 7a14 vstr s15, [sp, #80] @ 0x50
  2653. motorYAveCurrent += motorYSensCircBuffer[i];
  2654. 80016a4: eddd 7a33 vldr s15, [sp, #204] @ 0xcc
  2655. pvT2AveTemp += pvT2CircBuffer[i];
  2656. 80016a8: eddd aa47 vldr s21, [sp, #284] @ 0x11c
  2657. motorYAveCurrent += motorYSensCircBuffer[i];
  2658. 80016ac: edcd 7a15 vstr s15, [sp, #84] @ 0x54
  2659. motorXAveCurrent += motorXSensCircBuffer[i];
  2660. 80016b0: eddd 7a2a vldr s15, [sp, #168] @ 0xa8
  2661. 80016b4: edcd 7a16 vstr s15, [sp, #88] @ 0x58
  2662. motorYAveCurrent += motorYSensCircBuffer[i];
  2663. 80016b8: eddd 7a34 vldr s15, [sp, #208] @ 0xd0
  2664. pvT1AveTemp += pvT1CircBuffer[i];
  2665. 80016bc: ed9d aa3e vldr s20, [sp, #248] @ 0xf8
  2666. motorYAveCurrent += motorYSensCircBuffer[i];
  2667. 80016c0: edcd 7a17 vstr s15, [sp, #92] @ 0x5c
  2668. motorXAveCurrent += motorXSensCircBuffer[i];
  2669. 80016c4: eddd 7a2b vldr s15, [sp, #172] @ 0xac
  2670. pvT2AveTemp += pvT2CircBuffer[i];
  2671. 80016c8: eddd 9a48 vldr s19, [sp, #288] @ 0x120
  2672. motorXAveCurrent += motorXSensCircBuffer[i];
  2673. 80016cc: edcd 7a18 vstr s15, [sp, #96] @ 0x60
  2674. motorYAveCurrent += motorYSensCircBuffer[i];
  2675. 80016d0: eddd 7a35 vldr s15, [sp, #212] @ 0xd4
  2676. pvT1AveTemp += pvT1CircBuffer[i];
  2677. 80016d4: ed9d 9a3f vldr s18, [sp, #252] @ 0xfc
  2678. motorYAveCurrent += motorYSensCircBuffer[i];
  2679. 80016d8: edcd 7a19 vstr s15, [sp, #100] @ 0x64
  2680. pvT2AveTemp += pvT2CircBuffer[i];
  2681. 80016dc: eddd 7a49 vldr s15, [sp, #292] @ 0x124
  2682. 80016e0: edcd 7a05 vstr s15, [sp, #20]
  2683. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  2684. 80016e4: f00a fb8e bl 800be04 <osMutexAcquire>
  2685. 80016e8: 2800 cmp r0, #0
  2686. 80016ea: f040 80ad bne.w 8001848 <ADC3MeasTask+0x338>
  2687. if (sensorsInfo.motorXStatus == 1) {
  2688. 80016ee: 7d2b ldrb r3, [r5, #20]
  2689. 80016f0: 2b01 cmp r3, #1
  2690. 80016f2: d134 bne.n 800175e <ADC3MeasTask+0x24e>
  2691. motorXAveCurrent += motorXSensCircBuffer[i];
  2692. 80016f4: ed9d 7a08 vldr s14, [sp, #32]
  2693. 80016f8: eddd 7a06 vldr s15, [sp, #24]
  2694. 80016fc: ee77 7a87 vadd.f32 s15, s15, s14
  2695. 8001700: ed9d 7a0a vldr s14, [sp, #40] @ 0x28
  2696. 8001704: ee77 7a87 vadd.f32 s15, s15, s14
  2697. 8001708: ed9d 7a0c vldr s14, [sp, #48] @ 0x30
  2698. 800170c: ee77 7a87 vadd.f32 s15, s15, s14
  2699. 8001710: ed9d 7a0e vldr s14, [sp, #56] @ 0x38
  2700. 8001714: ee77 7a87 vadd.f32 s15, s15, s14
  2701. 8001718: ed9d 7a10 vldr s14, [sp, #64] @ 0x40
  2702. 800171c: ee77 7a87 vadd.f32 s15, s15, s14
  2703. 8001720: ed9d 7a12 vldr s14, [sp, #72] @ 0x48
  2704. 8001724: ee77 7a87 vadd.f32 s15, s15, s14
  2705. 8001728: ed9d 7a14 vldr s14, [sp, #80] @ 0x50
  2706. 800172c: ee77 7a87 vadd.f32 s15, s15, s14
  2707. 8001730: ed9d 7a16 vldr s14, [sp, #88] @ 0x58
  2708. 8001734: ee77 7a87 vadd.f32 s15, s15, s14
  2709. 8001738: ed9d 7a18 vldr s14, [sp, #96] @ 0x60
  2710. 800173c: ee77 7a87 vadd.f32 s15, s15, s14
  2711. motorXAveCurrent /= CIRC_BUFF_LEN;
  2712. 8001740: ed9f 7a5f vldr s14, [pc, #380] @ 80018c0 <ADC3MeasTask+0x3b0>
  2713. 8001744: ee67 7a87 vmul.f32 s15, s15, s14
  2714. sensorsInfo.motorXAveCurrent = motorXAveCurrent;
  2715. 8001748: edc5 7a06 vstr s15, [r5, #24]
  2716. if (sensorsInfo.motorXPeakCurrent < motorXCurrentSense) {
  2717. 800174c: edd5 7a08 vldr s15, [r5, #32]
  2718. 8001750: eef4 7ae8 vcmpe.f32 s15, s17
  2719. 8001754: eef1 fa10 vmrs APSR_nzcv, fpscr
  2720. sensorsInfo.motorXPeakCurrent = motorXCurrentSense;
  2721. 8001758: bf48 it mi
  2722. 800175a: edc5 8a08 vstrmi s17, [r5, #32]
  2723. }
  2724. }
  2725. if (sensorsInfo.motorYStatus == 1) {
  2726. 800175e: 7d6b ldrb r3, [r5, #21]
  2727. 8001760: 2b01 cmp r3, #1
  2728. 8001762: d134 bne.n 80017ce <ADC3MeasTask+0x2be>
  2729. motorYAveCurrent += motorYSensCircBuffer[i];
  2730. 8001764: ed9d 7a09 vldr s14, [sp, #36] @ 0x24
  2731. 8001768: eddd 7a07 vldr s15, [sp, #28]
  2732. sensorsInfo.motorYAveCurrent = motorYAveCurrent;
  2733. if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) {
  2734. 800176c: edd5 6a09 vldr s13, [r5, #36] @ 0x24
  2735. motorYAveCurrent += motorYSensCircBuffer[i];
  2736. 8001770: ee77 7a87 vadd.f32 s15, s15, s14
  2737. 8001774: ed9d 7a0b vldr s14, [sp, #44] @ 0x2c
  2738. if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) {
  2739. 8001778: eef4 6ac8 vcmpe.f32 s13, s16
  2740. motorYAveCurrent += motorYSensCircBuffer[i];
  2741. 800177c: ee77 7a87 vadd.f32 s15, s15, s14
  2742. 8001780: ed9d 7a0d vldr s14, [sp, #52] @ 0x34
  2743. if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) {
  2744. 8001784: eef1 fa10 vmrs APSR_nzcv, fpscr
  2745. motorYAveCurrent += motorYSensCircBuffer[i];
  2746. 8001788: ee77 7a87 vadd.f32 s15, s15, s14
  2747. 800178c: ed9d 7a0f vldr s14, [sp, #60] @ 0x3c
  2748. sensorsInfo.motorYPeakCurrent = motorYCurrentSense;
  2749. 8001790: bf48 it mi
  2750. 8001792: ed85 8a09 vstrmi s16, [r5, #36] @ 0x24
  2751. motorYAveCurrent += motorYSensCircBuffer[i];
  2752. 8001796: ee77 7a87 vadd.f32 s15, s15, s14
  2753. 800179a: ed9d 7a11 vldr s14, [sp, #68] @ 0x44
  2754. 800179e: ee77 7a87 vadd.f32 s15, s15, s14
  2755. 80017a2: ed9d 7a13 vldr s14, [sp, #76] @ 0x4c
  2756. 80017a6: ee77 7a87 vadd.f32 s15, s15, s14
  2757. 80017aa: ed9d 7a15 vldr s14, [sp, #84] @ 0x54
  2758. 80017ae: ee77 7a87 vadd.f32 s15, s15, s14
  2759. 80017b2: ed9d 7a17 vldr s14, [sp, #92] @ 0x5c
  2760. 80017b6: ee77 7a87 vadd.f32 s15, s15, s14
  2761. 80017ba: ed9d 7a19 vldr s14, [sp, #100] @ 0x64
  2762. 80017be: ee77 7a87 vadd.f32 s15, s15, s14
  2763. motorYAveCurrent /= CIRC_BUFF_LEN;
  2764. 80017c2: ed9f 7a3f vldr s14, [pc, #252] @ 80018c0 <ADC3MeasTask+0x3b0>
  2765. 80017c6: ee67 7a87 vmul.f32 s15, s15, s14
  2766. sensorsInfo.motorYAveCurrent = motorYAveCurrent;
  2767. 80017ca: edc5 7a07 vstr s15, [r5, #28]
  2768. pvT1AveTemp += pvT1CircBuffer[i];
  2769. 80017ce: eddd 7a00 vldr s15, [sp]
  2770. 80017d2: ed9d 7a02 vldr s14, [sp, #8]
  2771. pvT2AveTemp += pvT2CircBuffer[i];
  2772. 80017d6: eddd 6a03 vldr s13, [sp, #12]
  2773. pvT1AveTemp += pvT1CircBuffer[i];
  2774. 80017da: ee37 7a87 vadd.f32 s14, s15, s14
  2775. pvT2AveTemp += pvT2CircBuffer[i];
  2776. 80017de: eddd 7a01 vldr s15, [sp, #4]
  2777. }
  2778. }
  2779. sensorsInfo.pvTemperature[0] = pvT1AveTemp;
  2780. sensorsInfo.pvTemperature[1] = pvT2AveTemp;
  2781. osMutexRelease (sensorsInfoMutex);
  2782. 80017e2: 6838 ldr r0, [r7, #0]
  2783. pvT2AveTemp += pvT2CircBuffer[i];
  2784. 80017e4: ee77 7aa6 vadd.f32 s15, s15, s13
  2785. 80017e8: eddd 6a04 vldr s13, [sp, #16]
  2786. pvT1AveTemp += pvT1CircBuffer[i];
  2787. 80017ec: ee37 7a2f vadd.f32 s14, s14, s31
  2788. pvT2AveTemp += pvT2CircBuffer[i];
  2789. 80017f0: ee77 7a8f vadd.f32 s15, s15, s30
  2790. pvT1AveTemp += pvT1CircBuffer[i];
  2791. 80017f4: ee37 7a2e vadd.f32 s14, s14, s29
  2792. pvT2AveTemp += pvT2CircBuffer[i];
  2793. 80017f8: ee77 7a8e vadd.f32 s15, s15, s28
  2794. pvT1AveTemp += pvT1CircBuffer[i];
  2795. 80017fc: ee37 7a2d vadd.f32 s14, s14, s27
  2796. pvT2AveTemp += pvT2CircBuffer[i];
  2797. 8001800: ee77 7a8d vadd.f32 s15, s15, s26
  2798. pvT1AveTemp += pvT1CircBuffer[i];
  2799. 8001804: ee37 7a2c vadd.f32 s14, s14, s25
  2800. pvT2AveTemp += pvT2CircBuffer[i];
  2801. 8001808: ee77 7a8c vadd.f32 s15, s15, s24
  2802. pvT1AveTemp += pvT1CircBuffer[i];
  2803. 800180c: ee37 7a2b vadd.f32 s14, s14, s23
  2804. pvT2AveTemp += pvT2CircBuffer[i];
  2805. 8001810: ee77 7aa6 vadd.f32 s15, s15, s13
  2806. 8001814: eddd 6a05 vldr s13, [sp, #20]
  2807. pvT1AveTemp += pvT1CircBuffer[i];
  2808. 8001818: ee37 7a0b vadd.f32 s14, s14, s22
  2809. pvT2AveTemp += pvT2CircBuffer[i];
  2810. 800181c: ee77 7aaa vadd.f32 s15, s15, s21
  2811. pvT1AveTemp += pvT1CircBuffer[i];
  2812. 8001820: ee37 7a0a vadd.f32 s14, s14, s20
  2813. pvT2AveTemp += pvT2CircBuffer[i];
  2814. 8001824: ee77 7aa9 vadd.f32 s15, s15, s19
  2815. pvT1AveTemp += pvT1CircBuffer[i];
  2816. 8001828: ee37 7a09 vadd.f32 s14, s14, s18
  2817. pvT2AveTemp += pvT2CircBuffer[i];
  2818. 800182c: ee77 7aa6 vadd.f32 s15, s15, s13
  2819. pvT1AveTemp /= CIRC_BUFF_LEN;
  2820. 8001830: eddf 6a23 vldr s13, [pc, #140] @ 80018c0 <ADC3MeasTask+0x3b0>
  2821. 8001834: ee27 7a26 vmul.f32 s14, s14, s13
  2822. pvT2AveTemp /= CIRC_BUFF_LEN;
  2823. 8001838: ee67 7aa6 vmul.f32 s15, s15, s13
  2824. sensorsInfo.pvTemperature[0] = pvT1AveTemp;
  2825. 800183c: ed85 7a00 vstr s14, [r5]
  2826. sensorsInfo.pvTemperature[1] = pvT2AveTemp;
  2827. 8001840: edc5 7a01 vstr s15, [r5, #4]
  2828. osMutexRelease (sensorsInfoMutex);
  2829. 8001844: f00a fb02 bl 800be4c <osMutexRelease>
  2830. }
  2831. ++circBuffPos;
  2832. 8001848: 1c63 adds r3, r4, #1
  2833. circBuffPos = circBuffPos % CIRC_BUFF_LEN;
  2834. 800184a: 4c1e ldr r4, [pc, #120] @ (80018c4 <ADC3MeasTask+0x3b4>)
  2835. 800184c: fba4 2403 umull r2, r4, r4, r3
  2836. 8001850: 08e4 lsrs r4, r4, #3
  2837. 8001852: eb04 0484 add.w r4, r4, r4, lsl #2
  2838. 8001856: eba3 0444 sub.w r4, r3, r4, lsl #1
  2839. osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever);
  2840. 800185a: a91a add r1, sp, #104 @ 0x68
  2841. 800185c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
  2842. 8001860: 2200 movs r2, #0
  2843. 8001862: f8db 0000 ldr.w r0, [fp]
  2844. 8001866: f00a fb8b bl 800bf80 <osMessageQueueGet>
  2845. if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) {
  2846. 800186a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  2847. 800186e: f8d8 0000 ldr.w r0, [r8]
  2848. uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B);
  2849. 8001872: f8ba 6060 ldrh.w r6, [sl, #96] @ 0x60
  2850. 8001876: f8bd 9070 ldrh.w r9, [sp, #112] @ 0x70
  2851. if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) {
  2852. 800187a: f00a fac3 bl 800be04 <osMutexAcquire>
  2853. 800187e: 2800 cmp r0, #0
  2854. 8001880: f47f ae6e bne.w 8001560 <ADC3MeasTask+0x50>
  2855. uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B);
  2856. 8001884: f640 43e4 movw r3, #3300 @ 0xce4
  2857. osMutexRelease (vRefmVMutex);
  2858. 8001888: f8d8 0000 ldr.w r0, [r8]
  2859. uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B);
  2860. 800188c: fb03 f606 mul.w r6, r3, r6
  2861. vRefmV = vRef;
  2862. 8001890: 4b0d ldr r3, [pc, #52] @ (80018c8 <ADC3MeasTask+0x3b8>)
  2863. uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B);
  2864. 8001892: fbb6 f6f9 udiv r6, r6, r9
  2865. vRefmV = vRef;
  2866. 8001896: 601e str r6, [r3, #0]
  2867. osMutexRelease (vRefmVMutex);
  2868. 8001898: f00a fad8 bl 800be4c <osMutexRelease>
  2869. 800189c: e660 b.n 8001560 <ADC3MeasTask+0x50>
  2870. 800189e: bf00 nop
  2871. 80018a0: 000ba1a8 .word 0x000ba1a8
  2872. 80018a4: 3f610011 .word 0x3f610011
  2873. 80018a8: 00000000 .word 0x00000000
  2874. 80018ac: c04f8000 .word 0xc04f8000
  2875. 80018b0: 5afd32cf .word 0x5afd32cf
  2876. 80018b4: 3f0cccea .word 0x3f0cccea
  2877. 80018b8: 24000980 .word 0x24000980
  2878. 80018bc: 24000900 .word 0x24000900
  2879. 80018c0: 3dcccccd .word 0x3dcccccd
  2880. 80018c4: cccccccd .word 0xcccccccd
  2881. 80018c8: 24000030 .word 0x24000030
  2882. 80018cc: 2400098c .word 0x2400098c
  2883. 80018d0: 24000988 .word 0x24000988
  2884. 80018d4: 1ff1e800 .word 0x1ff1e800
  2885. 080018d8 <ADC1MeasTask>:
  2886. void ADC1MeasTask (void* arg) {
  2887. 80018d8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  2888. 80018dc: ed2d 8b0c vpush {d8-d13}
  2889. 80018e0: b089 sub sp, #36 @ 0x24
  2890. float powerAcc[CHANNELS_COUNT] = { 0 };
  2891. 80018e2: eddf aa73 vldr s21, [pc, #460] @ 8001ab0 <ADC1MeasTask+0x1d8>
  2892. ADC1_Data adcData = { 0 };
  2893. 80018e6: 2220 movs r2, #32
  2894. 80018e8: 2100 movs r1, #0
  2895. 80018ea: 4668 mov r0, sp
  2896. float gainCorrection = 1.0;
  2897. 80018ec: eeb7 ca00 vmov.f32 s24, #112 @ 0x3f800000 1.0
  2898. float currentAcc[CHANNELS_COUNT] = { 0 };
  2899. 80018f0: eef0 ba6a vmov.f32 s23, s21
  2900. 80018f4: f8df a1d4 ldr.w sl, [pc, #468] @ 8001acc <ADC1MeasTask+0x1f4>
  2901. float voltageAcc[CHANNELS_COUNT] = { 0 };
  2902. 80018f8: eeb0 ba6a vmov.f32 s22, s21
  2903. 80018fc: f8df 91d0 ldr.w r9, [pc, #464] @ 8001ad0 <ADC1MeasTask+0x1f8>
  2904. 8001900: f8df 81d0 ldr.w r8, [pc, #464] @ 8001ad4 <ADC1MeasTask+0x1fc>
  2905. 8001904: 2701 movs r7, #1
  2906. gainCorrection = gainCorrection / EXT_VREF_mV;
  2907. 8001906: ed9f aa6b vldr s20, [pc, #428] @ 8001ab4 <ADC1MeasTask+0x1dc>
  2908. 800190a: 4c6b ldr r4, [pc, #428] @ (8001ab8 <ADC1MeasTask+0x1e0>)
  2909. 800190c: 4e6b ldr r6, [pc, #428] @ (8001abc <ADC1MeasTask+0x1e4>)
  2910. 800190e: 4d6c ldr r5, [pc, #432] @ (8001ac0 <ADC1MeasTask+0x1e8>)
  2911. float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
  2912. 8001910: ed9f 9b61 vldr d9, [pc, #388] @ 8001a98 <ADC1MeasTask+0x1c0>
  2913. float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset;
  2914. 8001914: ed9f 8b62 vldr d8, [pc, #392] @ 8001aa0 <ADC1MeasTask+0x1c8>
  2915. float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12;
  2916. 8001918: ed9f db63 vldr d13, [pc, #396] @ 8001aa8 <ADC1MeasTask+0x1d0>
  2917. ADC1_Data adcData = { 0 };
  2918. 800191c: f00e f8f4 bl 800fb08 <memset>
  2919. osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever);
  2920. 8001920: 4669 mov r1, sp
  2921. 8001922: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
  2922. 8001926: 2200 movs r2, #0
  2923. 8001928: f8da 0000 ldr.w r0, [sl]
  2924. 800192c: f00a fb28 bl 800bf80 <osMessageQueueGet>
  2925. if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) {
  2926. 8001930: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  2927. 8001934: f8d9 0000 ldr.w r0, [r9]
  2928. 8001938: f00a fa64 bl 800be04 <osMutexAcquire>
  2929. 800193c: 2800 cmp r0, #0
  2930. 800193e: f000 80a0 beq.w 8001a82 <ADC1MeasTask+0x1aa>
  2931. if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
  2932. 8001942: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  2933. 8001946: f8d8 0000 ldr.w r0, [r8]
  2934. gainCorrection = gainCorrection / EXT_VREF_mV;
  2935. 800194a: ee2c ca0a vmul.f32 s24, s24, s20
  2936. samplesCounter += 1;
  2937. 800194e: 46bb mov fp, r7
  2938. if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
  2939. 8001950: f00a fa58 bl 800be04 <osMutexAcquire>
  2940. 8001954: 2800 cmp r0, #0
  2941. 8001956: d1e3 bne.n 8001920 <ADC1MeasTask+0x48>
  2942. float adcVal = (float)adcData.adcDataBuffer[IIL1 + i];
  2943. 8001958: f8bd 300e ldrh.w r3, [sp, #14]
  2944. float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
  2945. 800195c: eeb7 1acc vcvt.f64.f32 d1, s24
  2946. 8001960: ed96 3a00 vldr s6, [r6]
  2947. float adcVal = (float)adcData.adcDataBuffer[IIL1 + i];
  2948. 8001964: ee06 3a10 vmov s12, r3
  2949. float ref = (float)adcData.adcDataBuffer[IL1Ref + i];
  2950. 8001968: f8bd 3006 ldrh.w r3, [sp, #6]
  2951. float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
  2952. 800196c: eeb7 3ac3 vcvt.f64.f32 d3, s6
  2953. float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset;
  2954. 8001970: ed95 2a00 vldr s4, [r5]
  2955. float ref = (float)adcData.adcDataBuffer[IL1Ref + i];
  2956. 8001974: ee07 3a90 vmov s15, r3
  2957. float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
  2958. 8001978: f8bd 3000 ldrh.w r3, [sp]
  2959. float adcVal = (float)adcData.adcDataBuffer[IIL1 + i];
  2960. 800197c: eeb8 6a46 vcvt.f32.u32 s12, s12
  2961. float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
  2962. 8001980: ed96 5a01 vldr s10, [r6, #4]
  2963. float ref = (float)adcData.adcDataBuffer[IL1Ref + i];
  2964. 8001984: eef8 7a67 vcvt.f32.u32 s15, s15
  2965. float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
  2966. 8001988: ee04 3a10 vmov s8, r3
  2967. 800198c: ee23 3b09 vmul.f64 d3, d3, d9
  2968. float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset;
  2969. 8001990: ed95 7a01 vldr s14, [r5, #4]
  2970. if (fabs (resMeasurements.voltagePeak[i]) < fabs (voltage)) {
  2971. 8001994: edd4 0a03 vldr s1, [r4, #12]
  2972. float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset;
  2973. 8001998: eeb7 2ac2 vcvt.f64.f32 d2, s4
  2974. 800199c: ee36 6a67 vsub.f32 s12, s12, s15
  2975. float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
  2976. 80019a0: eeb8 4bc4 vcvt.f64.s32 d4, s8
  2977. float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset;
  2978. 80019a4: ee22 2b08 vmul.f64 d2, d2, d8
  2979. float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
  2980. 80019a8: ee24 4b03 vmul.f64 d4, d4, d3
  2981. float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset;
  2982. 80019ac: eeb7 6ac6 vcvt.f64.f32 d6, s12
  2983. float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
  2984. 80019b0: eeb7 5ac5 vcvt.f64.f32 d5, s10
  2985. float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset;
  2986. 80019b4: eeb7 7ac7 vcvt.f64.f32 d7, s14
  2987. 80019b8: ee26 6b02 vmul.f64 d6, d6, d2
  2988. float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
  2989. 80019bc: eea1 5b04 vfma.f64 d5, d1, d4
  2990. float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset;
  2991. 80019c0: eea1 7b06 vfma.f64 d7, d1, d6
  2992. if (fabs (resMeasurements.voltagePeak[i]) < fabs (voltage)) {
  2993. 80019c4: eef0 0ae0 vabs.f32 s1, s1
  2994. float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset;
  2995. 80019c8: eeb7 5bc5 vcvt.f32.f64 s10, d5
  2996. voltageAcc[i] += voltage * voltage;
  2997. 80019cc: eea5 ba05 vfma.f32 s22, s10, s10
  2998. float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset;
  2999. 80019d0: eeb7 7bc7 vcvt.f32.f64 s14, d7
  3000. if (fabs (resMeasurements.voltagePeak[i]) < fabs (voltage)) {
  3001. 80019d4: eef0 7ac5 vabs.f32 s15, s10
  3002. currentAcc[i] += current * current;
  3003. 80019d8: eee7 ba07 vfma.f32 s23, s14, s14
  3004. if (fabs (resMeasurements.voltagePeak[i]) < fabs (voltage)) {
  3005. 80019dc: eef4 0ae7 vcmpe.f32 s1, s15
  3006. powerAcc[i] += voltage * current;
  3007. 80019e0: eee5 aa07 vfma.f32 s21, s10, s14
  3008. if (fabs (resMeasurements.voltagePeak[i]) < fabs (voltage)) {
  3009. 80019e4: eef1 fa10 vmrs APSR_nzcv, fpscr
  3010. 80019e8: d501 bpl.n 80019ee <ADC1MeasTask+0x116>
  3011. resMeasurements.voltagePeak[i] = voltage;
  3012. 80019ea: ed84 5a03 vstr s10, [r4, #12]
  3013. if (fabs (resMeasurements.currentPeak[i]) < fabs (current)) {
  3014. 80019ee: edd4 6a09 vldr s13, [r4, #36] @ 0x24
  3015. 80019f2: eef0 7ac7 vabs.f32 s15, s14
  3016. if (samplesCounter > 33332)
  3017. 80019f6: f248 2334 movw r3, #33332 @ 0x8234
  3018. if (fabs (resMeasurements.currentPeak[i]) < fabs (current)) {
  3019. 80019fa: eef0 6ae6 vabs.f32 s13, s13
  3020. 80019fe: eef4 6ae7 vcmpe.f32 s13, s15
  3021. 8001a02: eef1 fa10 vmrs APSR_nzcv, fpscr
  3022. resMeasurements.currentPeak[i] = current;
  3023. 8001a06: bf48 it mi
  3024. 8001a08: ed84 7a09 vstrmi s14, [r4, #36] @ 0x24
  3025. if (samplesCounter > 33332)
  3026. 8001a0c: 429f cmp r7, r3
  3027. 8001a0e: d922 bls.n 8001a56 <ADC1MeasTask+0x17e>
  3028. resMeasurements.voltageRMS[i] = sqrtf(voltageAcc[i] / samplesCounter);
  3029. 8001a10: ee07 7a90 vmov s15, r7
  3030. 8001a14: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
  3031. DbgLEDToggle(DBG_LED3);
  3032. 8001a18: 2040 movs r0, #64 @ 0x40
  3033. samplesCounter = 0;
  3034. 8001a1a: f04f 0b00 mov.w fp, #0
  3035. resMeasurements.voltageRMS[i] = sqrtf(voltageAcc[i] / samplesCounter);
  3036. 8001a1e: eeb8 7a67 vcvt.f32.u32 s14, s15
  3037. 8001a22: eec6 7a87 vdiv.f32 s15, s13, s14
  3038. 8001a26: ee2b ba27 vmul.f32 s22, s22, s15
  3039. resMeasurements.currentRMS[i] = sqrtf(currentAcc[i] / samplesCounter);
  3040. 8001a2a: ee6b baa7 vmul.f32 s23, s23, s15
  3041. resMeasurements.power[i] = powerAcc[i] / samplesCounter;
  3042. 8001a2e: ee6a 7aa7 vmul.f32 s15, s21, s15
  3043. DbgLEDToggle(DBG_LED3);
  3044. 8001a32: eddf aa1f vldr s21, [pc, #124] @ 8001ab0 <ADC1MeasTask+0x1d8>
  3045. resMeasurements.voltageRMS[i] = sqrtf(voltageAcc[i] / samplesCounter);
  3046. 8001a36: eef1 6acb vsqrt.f32 s13, s22
  3047. resMeasurements.power[i] = powerAcc[i] / samplesCounter;
  3048. 8001a3a: edc4 7a0c vstr s15, [r4, #48] @ 0x30
  3049. resMeasurements.currentRMS[i] = sqrtf(currentAcc[i] / samplesCounter);
  3050. 8001a3e: eeb1 7aeb vsqrt.f32 s14, s23
  3051. DbgLEDToggle(DBG_LED3);
  3052. 8001a42: eeb0 ba6a vmov.f32 s22, s21
  3053. 8001a46: eef0 ba6a vmov.f32 s23, s21
  3054. resMeasurements.voltageRMS[i] = sqrtf(voltageAcc[i] / samplesCounter);
  3055. 8001a4a: edc4 6a00 vstr s13, [r4]
  3056. resMeasurements.currentRMS[i] = sqrtf(currentAcc[i] / samplesCounter);
  3057. 8001a4e: ed84 7a06 vstr s14, [r4, #24]
  3058. DbgLEDToggle(DBG_LED3);
  3059. 8001a52: f000 fad3 bl 8001ffc <DbgLEDToggle>
  3060. float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12;
  3061. 8001a56: f8bd 300c ldrh.w r3, [sp, #12]
  3062. 8001a5a: eeb2 7b08 vmov.f64 d7, #40 @ 0x41400000 12.0
  3063. osMutexRelease (resMeasurementsMutex);
  3064. 8001a5e: f8d8 0000 ldr.w r0, [r8]
  3065. 8001a62: f10b 0701 add.w r7, fp, #1
  3066. float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12;
  3067. 8001a66: ee06 3a10 vmov s12, r3
  3068. 8001a6a: 4b16 ldr r3, [pc, #88] @ (8001ac4 <ADC1MeasTask+0x1ec>)
  3069. 8001a6c: eeb8 6bc6 vcvt.f64.s32 d6, s12
  3070. 8001a70: eea6 7b0d vfma.f64 d7, d6, d13
  3071. 8001a74: eeb7 7bc7 vcvt.f32.f64 s14, d7
  3072. 8001a78: ed83 7a02 vstr s14, [r3, #8]
  3073. osMutexRelease (resMeasurementsMutex);
  3074. 8001a7c: f00a f9e6 bl 800be4c <osMutexRelease>
  3075. 8001a80: e74e b.n 8001920 <ADC1MeasTask+0x48>
  3076. gainCorrection = (float)vRefmV;
  3077. 8001a82: 4b11 ldr r3, [pc, #68] @ (8001ac8 <ADC1MeasTask+0x1f0>)
  3078. osMutexRelease (vRefmVMutex);
  3079. 8001a84: f8d9 0000 ldr.w r0, [r9]
  3080. gainCorrection = (float)vRefmV;
  3081. 8001a88: ed93 ca00 vldr s24, [r3]
  3082. 8001a8c: eeb8 ca4c vcvt.f32.u32 s24, s24
  3083. osMutexRelease (vRefmVMutex);
  3084. 8001a90: f00a f9dc bl 800be4c <osMutexRelease>
  3085. 8001a94: e755 b.n 8001942 <ADC1MeasTask+0x6a>
  3086. 8001a96: bf00 nop
  3087. 8001a98: 7d87690c .word 0x7d87690c
  3088. 8001a9c: 3f36c535 .word 0x3f36c535
  3089. 8001aa0: 9d38b97c .word 0x9d38b97c
  3090. 8001aa4: 3f36ba4d .word 0x3f36ba4d
  3091. 8001aa8: b34d4ce6 .word 0xb34d4ce6
  3092. 8001aac: bf2a19b3 .word 0xbf2a19b3
  3093. 8001ab0: 00000000 .word 0x00000000
  3094. 8001ab4: 39aec33e .word 0x39aec33e
  3095. 8001ab8: 24000940 .word 0x24000940
  3096. 8001abc: 24000018 .word 0x24000018
  3097. 8001ac0: 24000000 .word 0x24000000
  3098. 8001ac4: 24000900 .word 0x24000900
  3099. 8001ac8: 24000030 .word 0x24000030
  3100. 8001acc: 24000994 .word 0x24000994
  3101. 8001ad0: 24000988 .word 0x24000988
  3102. 8001ad4: 24000984 .word 0x24000984
  3103. 08001ad8 <LimiterSwitchTask>:
  3104. }
  3105. }
  3106. void LimiterSwitchTask (void* arg) {
  3107. 8001ad8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  3108. uint8_t limitYSwitchCenterPrevState = 0;
  3109. uint8_t limitYSwitchUpPrevState = 0;
  3110. uint8_t pinStates = 0;
  3111. uint8_t limiterXTriggered = 0;
  3112. uint8_t limiterYTriggered = 0;
  3113. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  3114. 8001adc: f8df a214 ldr.w sl, [pc, #532] @ 8001cf4 <LimiterSwitchTask+0x21c>
  3115. 8001ae0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  3116. sensorsInfo.positionXWeak = 1;
  3117. 8001ae4: 4f7a ldr r7, [pc, #488] @ (8001cd0 <LimiterSwitchTask+0x1f8>)
  3118. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  3119. 8001ae6: f8da 0000 ldr.w r0, [sl]
  3120. void LimiterSwitchTask (void* arg) {
  3121. 8001aea: ed2d 8b04 vpush {d8-d9}
  3122. 8001aee: b08d sub sp, #52 @ 0x34
  3123. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  3124. 8001af0: f00a f988 bl 800be04 <osMutexAcquire>
  3125. 8001af4: 2800 cmp r0, #0
  3126. 8001af6: f000 80e2 beq.w 8001cbe <LimiterSwitchTask+0x1e6>
  3127. void LimiterSwitchTask (void* arg) {
  3128. 8001afa: 2300 movs r3, #0
  3129. osMutexRelease (sensorsInfoMutex);
  3130. }
  3131. while (pdTRUE) {
  3132. osDelay (pdMS_TO_TICKS (100));
  3133. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  3134. sensorsInfo.limitXSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_13);
  3135. 8001afc: 4d75 ldr r5, [pc, #468] @ (8001cd4 <LimiterSwitchTask+0x1fc>)
  3136. pinStates = (limitXSwitchDownPrevState << 1) | sensorsInfo.limitXSwitchDown;
  3137. if ((pinStates & 0x3) == 0x1) {
  3138. limiterXTriggered = 1;
  3139. sensorsInfo.currentXPosition = 0;
  3140. 8001afe: ed9f 9a76 vldr s18, [pc, #472] @ 8001cd8 <LimiterSwitchTask+0x200>
  3141. void LimiterSwitchTask (void* arg) {
  3142. 8001b02: 461c mov r4, r3
  3143. 8001b04: 469b mov fp, r3
  3144. 8001b06: 4698 mov r8, r3
  3145. 8001b08: 4699 mov r9, r3
  3146. sensorsInfo.limitXSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_12);
  3147. pinStates = (limitXSwitchUpPrevState << 1) | sensorsInfo.limitXSwitchUp;
  3148. if ((pinStates & 0x3) == 0x1) {
  3149. limiterXTriggered = 1;
  3150. sensorsInfo.currentXPosition = 100;
  3151. 8001b0a: eddf 8a74 vldr s17, [pc, #464] @ 8001cdc <LimiterSwitchTask+0x204>
  3152. limitXSwitchUpPrevState = sensorsInfo.limitXSwitchUp;
  3153. sensorsInfo.limitXSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_10);
  3154. pinStates = (limitXSwitchCenterPrevState << 1) | sensorsInfo.limitXSwitchCenter;
  3155. if ((pinStates & 0x3) == 0x1) {
  3156. sensorsInfo.currentXPosition = AXE_X_MIDDLE_VALUE;
  3157. 8001b0e: ed9f 8a74 vldr s16, [pc, #464] @ 8001ce0 <LimiterSwitchTask+0x208>
  3158. void LimiterSwitchTask (void* arg) {
  3159. 8001b12: e9cd 3308 strd r3, r3, [sp, #32]
  3160. osDelay (pdMS_TO_TICKS (100));
  3161. 8001b16: 2064 movs r0, #100 @ 0x64
  3162. 8001b18: f00a f8ac bl 800bc74 <osDelay>
  3163. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  3164. 8001b1c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  3165. 8001b20: f8da 0000 ldr.w r0, [sl]
  3166. 8001b24: f00a f96e bl 800be04 <osMutexAcquire>
  3167. 8001b28: 4606 mov r6, r0
  3168. 8001b2a: 2800 cmp r0, #0
  3169. 8001b2c: d1f3 bne.n 8001b16 <LimiterSwitchTask+0x3e>
  3170. sensorsInfo.limitXSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_13);
  3171. 8001b2e: f44f 5100 mov.w r1, #8192 @ 0x2000
  3172. 8001b32: 4628 mov r0, r5
  3173. 8001b34: f005 fb3c bl 80071b0 <HAL_GPIO_ReadPin>
  3174. 8001b38: 900a str r0, [sp, #40] @ 0x28
  3175. pinStates = (limitXSwitchDownPrevState << 1) | sensorsInfo.limitXSwitchDown;
  3176. 8001b3a: ea40 0444 orr.w r4, r0, r4, lsl #1
  3177. sensorsInfo.limitXSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_13);
  3178. 8001b3e: f887 0029 strb.w r0, [r7, #41] @ 0x29
  3179. if ((pinStates & 0x3) == 0x1) {
  3180. 8001b42: f004 0303 and.w r3, r4, #3
  3181. 8001b46: 2b01 cmp r3, #1
  3182. 8001b48: 9307 str r3, [sp, #28]
  3183. 8001b4a: f000 80b3 beq.w 8001cb4 <LimiterSwitchTask+0x1dc>
  3184. 8001b4e: 9607 str r6, [sp, #28]
  3185. sensorsInfo.limitXSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_12);
  3186. 8001b50: f44f 5180 mov.w r1, #4096 @ 0x1000
  3187. 8001b54: 4628 mov r0, r5
  3188. 8001b56: f005 fb2b bl 80071b0 <HAL_GPIO_ReadPin>
  3189. 8001b5a: 900b str r0, [sp, #44] @ 0x2c
  3190. pinStates = (limitXSwitchUpPrevState << 1) | sensorsInfo.limitXSwitchUp;
  3191. 8001b5c: ea40 0848 orr.w r8, r0, r8, lsl #1
  3192. sensorsInfo.limitXSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_12);
  3193. 8001b60: f887 0028 strb.w r0, [r7, #40] @ 0x28
  3194. if ((pinStates & 0x3) == 0x1) {
  3195. 8001b64: f008 0803 and.w r8, r8, #3
  3196. 8001b68: f1b8 0f01 cmp.w r8, #1
  3197. 8001b6c: d106 bne.n 8001b7c <LimiterSwitchTask+0xa4>
  3198. sensorsInfo.positionXWeak = 0;
  3199. 8001b6e: 2300 movs r3, #0
  3200. limiterXTriggered = 1;
  3201. 8001b70: f8cd 801c str.w r8, [sp, #28]
  3202. sensorsInfo.currentXPosition = 100;
  3203. 8001b74: edc7 8a0c vstr s17, [r7, #48] @ 0x30
  3204. sensorsInfo.positionXWeak = 0;
  3205. 8001b78: f887 3038 strb.w r3, [r7, #56] @ 0x38
  3206. sensorsInfo.limitXSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_10);
  3207. 8001b7c: f44f 6180 mov.w r1, #1024 @ 0x400
  3208. 8001b80: 4628 mov r0, r5
  3209. 8001b82: f005 fb15 bl 80071b0 <HAL_GPIO_ReadPin>
  3210. 8001b86: 4604 mov r4, r0
  3211. pinStates = (limitXSwitchCenterPrevState << 1) | sensorsInfo.limitXSwitchCenter;
  3212. 8001b88: ea40 0949 orr.w r9, r0, r9, lsl #1
  3213. sensorsInfo.limitXSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_10);
  3214. 8001b8c: f887 002a strb.w r0, [r7, #42] @ 0x2a
  3215. if ((pinStates & 0x3) == 0x1) {
  3216. 8001b90: f009 0903 and.w r9, r9, #3
  3217. 8001b94: f1b9 0f01 cmp.w r9, #1
  3218. 8001b98: d104 bne.n 8001ba4 <LimiterSwitchTask+0xcc>
  3219. sensorsInfo.positionXWeak = 0;
  3220. 8001b9a: 2300 movs r3, #0
  3221. sensorsInfo.currentXPosition = AXE_X_MIDDLE_VALUE;
  3222. 8001b9c: ed87 8a0c vstr s16, [r7, #48] @ 0x30
  3223. sensorsInfo.positionXWeak = 0;
  3224. 8001ba0: f887 3038 strb.w r3, [r7, #56] @ 0x38
  3225. }
  3226. limitXSwitchCenterPrevState = sensorsInfo.limitXSwitchCenter;
  3227. sensorsInfo.limitYSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_9);
  3228. 8001ba4: f44f 7100 mov.w r1, #512 @ 0x200
  3229. 8001ba8: 4628 mov r0, r5
  3230. 8001baa: f005 fb01 bl 80071b0 <HAL_GPIO_ReadPin>
  3231. 8001bae: 4606 mov r6, r0
  3232. pinStates = (limitYSwitchDownPrevState << 1) | sensorsInfo.limitYSwitchDown;
  3233. 8001bb0: ea40 0b4b orr.w fp, r0, fp, lsl #1
  3234. sensorsInfo.limitYSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_9);
  3235. 8001bb4: f887 002c strb.w r0, [r7, #44] @ 0x2c
  3236. if ((pinStates & 0x3) == 0x1) {
  3237. 8001bb8: f00b 0b03 and.w fp, fp, #3
  3238. 8001bbc: f1bb 0f01 cmp.w fp, #1
  3239. 8001bc0: d072 beq.n 8001ca8 <LimiterSwitchTask+0x1d0>
  3240. 8001bc2: f04f 0b00 mov.w fp, #0
  3241. sensorsInfo.currentYPosition = 0;
  3242. sensorsInfo.positionYWeak = 0;
  3243. }
  3244. limitYSwitchDownPrevState = sensorsInfo.limitYSwitchDown;
  3245. sensorsInfo.limitYSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_11);
  3246. 8001bc6: f44f 6100 mov.w r1, #2048 @ 0x800
  3247. 8001bca: 4628 mov r0, r5
  3248. 8001bcc: f005 faf0 bl 80071b0 <HAL_GPIO_ReadPin>
  3249. pinStates = (limitYSwitchUpPrevState << 1) | sensorsInfo.limitYSwitchUp;
  3250. 8001bd0: 9b09 ldr r3, [sp, #36] @ 0x24
  3251. sensorsInfo.limitYSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_11);
  3252. 8001bd2: 4681 mov r9, r0
  3253. 8001bd4: f887 002b strb.w r0, [r7, #43] @ 0x2b
  3254. pinStates = (limitYSwitchUpPrevState << 1) | sensorsInfo.limitYSwitchUp;
  3255. 8001bd8: ea40 0343 orr.w r3, r0, r3, lsl #1
  3256. 8001bdc: f003 0303 and.w r3, r3, #3
  3257. if ((pinStates & 0x3) == 0x1) {
  3258. 8001be0: 2b01 cmp r3, #1
  3259. 8001be2: d105 bne.n 8001bf0 <LimiterSwitchTask+0x118>
  3260. limiterYTriggered = 1;
  3261. 8001be4: 469b mov fp, r3
  3262. sensorsInfo.currentYPosition = 100;
  3263. sensorsInfo.positionYWeak = 0;
  3264. 8001be6: 2300 movs r3, #0
  3265. sensorsInfo.currentYPosition = 100;
  3266. 8001be8: edc7 8a0d vstr s17, [r7, #52] @ 0x34
  3267. sensorsInfo.positionYWeak = 0;
  3268. 8001bec: f887 3039 strb.w r3, [r7, #57] @ 0x39
  3269. }
  3270. limitYSwitchUpPrevState = sensorsInfo.limitYSwitchUp;
  3271. sensorsInfo.limitYSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_8);
  3272. 8001bf0: f44f 7180 mov.w r1, #256 @ 0x100
  3273. 8001bf4: 4628 mov r0, r5
  3274. 8001bf6: f005 fadb bl 80071b0 <HAL_GPIO_ReadPin>
  3275. pinStates = (limitYSwitchCenterPrevState << 1) | sensorsInfo.limitYSwitchCenter;
  3276. 8001bfa: 9b08 ldr r3, [sp, #32]
  3277. sensorsInfo.limitYSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_8);
  3278. 8001bfc: 4680 mov r8, r0
  3279. 8001bfe: f887 002d strb.w r0, [r7, #45] @ 0x2d
  3280. pinStates = (limitYSwitchCenterPrevState << 1) | sensorsInfo.limitYSwitchCenter;
  3281. 8001c02: ea40 0343 orr.w r3, r0, r3, lsl #1
  3282. if ((pinStates & 0x3) == 0x1) {
  3283. 8001c06: f003 0303 and.w r3, r3, #3
  3284. 8001c0a: 2b01 cmp r3, #1
  3285. 8001c0c: d104 bne.n 8001c18 <LimiterSwitchTask+0x140>
  3286. sensorsInfo.currentYPosition = AXE_Y_MIDDLE_VALUE;
  3287. sensorsInfo.positionYWeak = 0;
  3288. 8001c0e: 2300 movs r3, #0
  3289. sensorsInfo.currentYPosition = AXE_Y_MIDDLE_VALUE;
  3290. 8001c10: ed87 8a0d vstr s16, [r7, #52] @ 0x34
  3291. sensorsInfo.positionYWeak = 0;
  3292. 8001c14: f887 3039 strb.w r3, [r7, #57] @ 0x39
  3293. }
  3294. limitYSwitchCenterPrevState = sensorsInfo.limitYSwitchCenter;
  3295. if (((sensorsInfo.limitXSwitchDown == 1) || (sensorsInfo.limitXSwitchUp == 1)) && (limiterXTriggered == 1)) {
  3296. 8001c18: f897 3029 ldrb.w r3, [r7, #41] @ 0x29
  3297. 8001c1c: 2b01 cmp r3, #1
  3298. 8001c1e: d017 beq.n 8001c50 <LimiterSwitchTask+0x178>
  3299. 8001c20: f897 2028 ldrb.w r2, [r7, #40] @ 0x28
  3300. 8001c24: 2a01 cmp r2, #1
  3301. 8001c26: d013 beq.n 8001c50 <LimiterSwitchTask+0x178>
  3302. sensorsInfo.motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown);
  3303. }
  3304. if (((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) && (limiterYTriggered == 1)) {
  3305. 8001c28: f897 302c ldrb.w r3, [r7, #44] @ 0x2c
  3306. 8001c2c: 2b01 cmp r3, #1
  3307. 8001c2e: d026 beq.n 8001c7e <LimiterSwitchTask+0x1a6>
  3308. 8001c30: f897 202b ldrb.w r2, [r7, #43] @ 0x2b
  3309. 8001c34: 2a01 cmp r2, #1
  3310. 8001c36: d022 beq.n 8001c7e <LimiterSwitchTask+0x1a6>
  3311. sensorsInfo.motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown);
  3312. }
  3313. limiterXTriggered = 0;
  3314. limiterYTriggered = 0;
  3315. osMutexRelease (sensorsInfoMutex);
  3316. 8001c38: f8da 0000 ldr.w r0, [sl]
  3317. limitYSwitchDownPrevState = sensorsInfo.limitYSwitchDown;
  3318. 8001c3c: 46b3 mov fp, r6
  3319. limitYSwitchCenterPrevState = sensorsInfo.limitYSwitchCenter;
  3320. 8001c3e: e9cd 8908 strd r8, r9, [sp, #32]
  3321. limitXSwitchCenterPrevState = sensorsInfo.limitXSwitchCenter;
  3322. 8001c42: 46a1 mov r9, r4
  3323. limitXSwitchUpPrevState = sensorsInfo.limitXSwitchUp;
  3324. 8001c44: f8dd 802c ldr.w r8, [sp, #44] @ 0x2c
  3325. limitXSwitchDownPrevState = sensorsInfo.limitXSwitchDown;
  3326. 8001c48: 9c0a ldr r4, [sp, #40] @ 0x28
  3327. osMutexRelease (sensorsInfoMutex);
  3328. 8001c4a: f00a f8ff bl 800be4c <osMutexRelease>
  3329. 8001c4e: e762 b.n 8001b16 <LimiterSwitchTask+0x3e>
  3330. if (((sensorsInfo.limitXSwitchDown == 1) || (sensorsInfo.limitXSwitchUp == 1)) && (limiterXTriggered == 1)) {
  3331. 8001c50: 9a07 ldr r2, [sp, #28]
  3332. 8001c52: 2a01 cmp r2, #1
  3333. 8001c54: d1e8 bne.n 8001c28 <LimiterSwitchTask+0x150>
  3334. sensorsInfo.motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown);
  3335. 8001c56: 9304 str r3, [sp, #16]
  3336. 8001c58: 2200 movs r2, #0
  3337. 8001c5a: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
  3338. 8001c5e: 4921 ldr r1, [pc, #132] @ (8001ce4 <LimiterSwitchTask+0x20c>)
  3339. 8001c60: 9303 str r3, [sp, #12]
  3340. 8001c62: 4b21 ldr r3, [pc, #132] @ (8001ce8 <LimiterSwitchTask+0x210>)
  3341. 8001c64: 4821 ldr r0, [pc, #132] @ (8001cec <LimiterSwitchTask+0x214>)
  3342. 8001c66: e9cd 2201 strd r2, r2, [sp, #4]
  3343. 8001c6a: 681b ldr r3, [r3, #0]
  3344. 8001c6c: 9300 str r3, [sp, #0]
  3345. 8001c6e: 2304 movs r3, #4
  3346. 8001c70: f000 f9f2 bl 8002058 <MotorControl>
  3347. if (((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) && (limiterYTriggered == 1)) {
  3348. 8001c74: f897 302c ldrb.w r3, [r7, #44] @ 0x2c
  3349. sensorsInfo.motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown);
  3350. 8001c78: 7538 strb r0, [r7, #20]
  3351. if (((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) && (limiterYTriggered == 1)) {
  3352. 8001c7a: 2b01 cmp r3, #1
  3353. 8001c7c: d1d8 bne.n 8001c30 <LimiterSwitchTask+0x158>
  3354. 8001c7e: f1bb 0f01 cmp.w fp, #1
  3355. 8001c82: d1d9 bne.n 8001c38 <LimiterSwitchTask+0x160>
  3356. sensorsInfo.motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown);
  3357. 8001c84: 9304 str r3, [sp, #16]
  3358. 8001c86: 2208 movs r2, #8
  3359. 8001c88: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
  3360. 8001c8c: 4915 ldr r1, [pc, #84] @ (8001ce4 <LimiterSwitchTask+0x20c>)
  3361. 8001c8e: 9303 str r3, [sp, #12]
  3362. 8001c90: 2300 movs r3, #0
  3363. 8001c92: 4816 ldr r0, [pc, #88] @ (8001cec <LimiterSwitchTask+0x214>)
  3364. 8001c94: e9cd 3301 strd r3, r3, [sp, #4]
  3365. 8001c98: 4b15 ldr r3, [pc, #84] @ (8001cf0 <LimiterSwitchTask+0x218>)
  3366. 8001c9a: 681b ldr r3, [r3, #0]
  3367. 8001c9c: 9300 str r3, [sp, #0]
  3368. 8001c9e: 230c movs r3, #12
  3369. 8001ca0: f000 f9da bl 8002058 <MotorControl>
  3370. 8001ca4: 7578 strb r0, [r7, #21]
  3371. 8001ca6: e7c7 b.n 8001c38 <LimiterSwitchTask+0x160>
  3372. sensorsInfo.positionYWeak = 0;
  3373. 8001ca8: 2300 movs r3, #0
  3374. sensorsInfo.currentYPosition = 0;
  3375. 8001caa: ed87 9a0d vstr s18, [r7, #52] @ 0x34
  3376. sensorsInfo.positionYWeak = 0;
  3377. 8001cae: f887 3039 strb.w r3, [r7, #57] @ 0x39
  3378. 8001cb2: e788 b.n 8001bc6 <LimiterSwitchTask+0xee>
  3379. sensorsInfo.positionXWeak = 0;
  3380. 8001cb4: f887 6038 strb.w r6, [r7, #56] @ 0x38
  3381. sensorsInfo.currentXPosition = 0;
  3382. 8001cb8: ed87 9a0c vstr s18, [r7, #48] @ 0x30
  3383. sensorsInfo.positionXWeak = 0;
  3384. 8001cbc: e748 b.n 8001b50 <LimiterSwitchTask+0x78>
  3385. sensorsInfo.positionXWeak = 1;
  3386. 8001cbe: f240 1301 movw r3, #257 @ 0x101
  3387. osMutexRelease (sensorsInfoMutex);
  3388. 8001cc2: f8da 0000 ldr.w r0, [sl]
  3389. sensorsInfo.positionXWeak = 1;
  3390. 8001cc6: 873b strh r3, [r7, #56] @ 0x38
  3391. osMutexRelease (sensorsInfoMutex);
  3392. 8001cc8: f00a f8c0 bl 800be4c <osMutexRelease>
  3393. 8001ccc: e715 b.n 8001afa <LimiterSwitchTask+0x22>
  3394. 8001cce: bf00 nop
  3395. 8001cd0: 24000900 .word 0x24000900
  3396. 8001cd4: 58020c00 .word 0x58020c00
  3397. 8001cd8: 00000000 .word 0x00000000
  3398. 8001cdc: 42c80000 .word 0x42c80000
  3399. 8001ce0: 42480000 .word 0x42480000
  3400. 8001ce4: 24000290 .word 0x24000290
  3401. 8001ce8: 24000324 .word 0x24000324
  3402. 8001cec: 24000500 .word 0x24000500
  3403. 8001cf0: 240002f4 .word 0x240002f4
  3404. 8001cf4: 24000980 .word 0x24000980
  3405. 08001cf8 <EncoderTask>:
  3406. }
  3407. }
  3408. }
  3409. void EncoderTask (void* arg) {
  3410. 8001cf8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  3411. // 01 11 10 00
  3412. const uint32_t encoderStates[4] = { 0x00, 0x01, 0x03, 0x02 };
  3413. 8001cfc: 4b3c ldr r3, [pc, #240] @ (8001df0 <EncoderTask+0xf8>)
  3414. void EncoderTask (void* arg) {
  3415. 8001cfe: 4604 mov r4, r0
  3416. 8001d00: ed2d 8b06 vpush {d8-d10}
  3417. 8001d04: b086 sub sp, #24
  3418. const uint32_t encoderStates[4] = { 0x00, 0x01, 0x03, 0x02 };
  3419. 8001d06: cb0f ldmia r3, {r0, r1, r2, r3}
  3420. 8001d08: ad06 add r5, sp, #24
  3421. 8001d0a: e905 000f stmdb r5, {r0, r1, r2, r3}
  3422. uint8_t step = 0;
  3423. EncoderTaskArg* encoderTaskArg = (EncoderTaskArg*)arg;
  3424. uint32_t pinStates = encoderTaskArg->initPinStates;
  3425. 8001d0e: 68e5 ldr r5, [r4, #12]
  3426. 8001d10: 9501 str r5, [sp, #4]
  3427. for (uint8_t i = 0; i < 4; i++) {
  3428. if (pinStates == encoderStates[i]) {
  3429. 8001d12: b13d cbz r5, 8001d24 <EncoderTask+0x2c>
  3430. 8001d14: 2d01 cmp r5, #1
  3431. 8001d16: d005 beq.n 8001d24 <EncoderTask+0x2c>
  3432. 8001d18: 2d03 cmp r5, #3
  3433. 8001d1a: d063 beq.n 8001de4 <EncoderTask+0xec>
  3434. for (uint8_t i = 0; i < 4; i++) {
  3435. 8001d1c: 2d02 cmp r5, #2
  3436. 8001d1e: bf14 ite ne
  3437. 8001d20: 2500 movne r5, #0
  3438. 8001d22: 2503 moveq r5, #3
  3439. 8001d24: 4e33 ldr r6, [pc, #204] @ (8001df4 <EncoderTask+0xfc>)
  3440. 8001d26: f105 0801 add.w r8, r5, #1
  3441. step--;
  3442. } else {
  3443. printf ("Forbidden\n");
  3444. }
  3445. step = step % 4;
  3446. *encoderTaskArg->pvEncoder = fmodf (encoderValue, 360.0);
  3447. 8001d2a: eddf 8a33 vldr s17, [pc, #204] @ 8001df8 <EncoderTask+0x100>
  3448. *encoderTaskArg->currentPosition = 100 * (*encoderTaskArg->pvEncoder) / MAX_X_AXE_ANGLE;
  3449. 8001d2e: ed9f aa33 vldr s20, [pc, #204] @ 8001dfc <EncoderTask+0x104>
  3450. encoderValue -= 360.0 / ENCODER_X_IMP_PER_TURN;
  3451. 8001d32: ed9f 9b2d vldr d9, [pc, #180] @ 8001de8 <EncoderTask+0xf0>
  3452. 8001d36: e029 b.n 8001d8c <EncoderTask+0x94>
  3453. } else if (encoderStates[(step - 1) % 4] == pinStates) {
  3454. 8001d38: f850 3c10 ldr.w r3, [r0, #-16]
  3455. encoderValue -= 360.0 / ENCODER_X_IMP_PER_TURN;
  3456. 8001d3c: eeb7 7ac8 vcvt.f64.f32 d7, s16
  3457. printf ("Forbidden\n");
  3458. 8001d40: 482f ldr r0, [pc, #188] @ (8001e00 <EncoderTask+0x108>)
  3459. } else if (encoderStates[(step - 1) % 4] == pinStates) {
  3460. 8001d42: 459c cmp ip, r3
  3461. encoderValue -= 360.0 / ENCODER_X_IMP_PER_TURN;
  3462. 8001d44: ee37 7b49 vsub.f64 d7, d7, d9
  3463. } else if (encoderStates[(step - 1) % 4] == pinStates) {
  3464. 8001d48: d149 bne.n 8001dde <EncoderTask+0xe6>
  3465. encoderValue -= 360.0 / ENCODER_X_IMP_PER_TURN;
  3466. 8001d4a: eeb7 8bc7 vcvt.f32.f64 s16, d7
  3467. step = step % 4;
  3468. 8001d4e: f001 0503 and.w r5, r1, #3
  3469. 8001d52: f105 0801 add.w r8, r5, #1
  3470. if (encoderValue < 0) {
  3471. 8001d56: eeb5 8ac0 vcmpe.f32 s16, #0.0
  3472. 8001d5a: eef1 fa10 vmrs APSR_nzcv, fpscr
  3473. 8001d5e: d501 bpl.n 8001d64 <EncoderTask+0x6c>
  3474. encoderValue = 360.0 + encoderValue;
  3475. 8001d60: ee38 8a28 vadd.f32 s16, s16, s17
  3476. *encoderTaskArg->pvEncoder = fmodf (encoderValue, 360.0);
  3477. 8001d64: eef0 0a68 vmov.f32 s1, s17
  3478. 8001d68: eeb0 0a48 vmov.f32 s0, s16
  3479. 8001d6c: f00f fd40 bl 80117f0 <fmodf>
  3480. *encoderTaskArg->currentPosition = 100 * (*encoderTaskArg->pvEncoder) / MAX_X_AXE_ANGLE;
  3481. 8001d70: ee60 7a0a vmul.f32 s15, s0, s20
  3482. osMutexRelease (sensorsInfoMutex);
  3483. 8001d74: 6830 ldr r0, [r6, #0]
  3484. *encoderTaskArg->currentPosition = 100 * (*encoderTaskArg->pvEncoder) / MAX_X_AXE_ANGLE;
  3485. 8001d76: e9d4 3201 ldrd r3, r2, [r4, #4]
  3486. *encoderTaskArg->pvEncoder = fmodf (encoderValue, 360.0);
  3487. 8001d7a: ed82 0a00 vstr s0, [r2]
  3488. *encoderTaskArg->currentPosition = 100 * (*encoderTaskArg->pvEncoder) / MAX_X_AXE_ANGLE;
  3489. 8001d7e: edc3 7a00 vstr s15, [r3]
  3490. osMutexRelease (sensorsInfoMutex);
  3491. 8001d82: f00a f863 bl 800be4c <osMutexRelease>
  3492. }
  3493. DbgLEDToggle (encoderTaskArg->dbgLed);
  3494. 8001d86: 7820 ldrb r0, [r4, #0]
  3495. 8001d88: f000 f938 bl 8001ffc <DbgLEDToggle>
  3496. float encoderValue = *encoderTaskArg->pvEncoder;
  3497. 8001d8c: 68a7 ldr r7, [r4, #8]
  3498. osMessageQueueGet (encoderTaskArg->dataQueue, &pinStates, 0, osWaitForever);
  3499. 8001d8e: 2200 movs r2, #0
  3500. 8001d90: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
  3501. 8001d94: a901 add r1, sp, #4
  3502. 8001d96: 6920 ldr r0, [r4, #16]
  3503. float encoderValue = *encoderTaskArg->pvEncoder;
  3504. 8001d98: ed97 8a00 vldr s16, [r7]
  3505. osMessageQueueGet (encoderTaskArg->dataQueue, &pinStates, 0, osWaitForever);
  3506. 8001d9c: f00a f8f0 bl 800bf80 <osMessageQueueGet>
  3507. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  3508. 8001da0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  3509. 8001da4: 6830 ldr r0, [r6, #0]
  3510. 8001da6: f00a f82d bl 800be04 <osMutexAcquire>
  3511. if (encoderStates[(step + 1) % 4] == pinStates) {
  3512. 8001daa: f008 0203 and.w r2, r8, #3
  3513. } else if (encoderStates[(step - 1) % 4] == pinStates) {
  3514. 8001dae: 1e69 subs r1, r5, #1
  3515. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  3516. 8001db0: 2800 cmp r0, #0
  3517. 8001db2: d1e8 bne.n 8001d86 <EncoderTask+0x8e>
  3518. } else if (encoderStates[(step - 1) % 4] == pinStates) {
  3519. 8001db4: ab06 add r3, sp, #24
  3520. if (encoderStates[(step + 1) % 4] == pinStates) {
  3521. 8001db6: f8dd c004 ldr.w ip, [sp, #4]
  3522. } else if (encoderStates[(step - 1) % 4] == pinStates) {
  3523. 8001dba: eb03 0081 add.w r0, r3, r1, lsl #2
  3524. if (encoderStates[(step + 1) % 4] == pinStates) {
  3525. 8001dbe: eb03 0382 add.w r3, r3, r2, lsl #2
  3526. 8001dc2: f853 3c10 ldr.w r3, [r3, #-16]
  3527. 8001dc6: 4563 cmp r3, ip
  3528. 8001dc8: d1b6 bne.n 8001d38 <EncoderTask+0x40>
  3529. encoderValue += 360.0 / ENCODER_X_IMP_PER_TURN;
  3530. 8001dca: eeb7 0ac8 vcvt.f64.f32 d0, s16
  3531. step = step % 4;
  3532. 8001dce: b2d5 uxtb r5, r2
  3533. 8001dd0: f102 0801 add.w r8, r2, #1
  3534. encoderValue += 360.0 / ENCODER_X_IMP_PER_TURN;
  3535. 8001dd4: ee30 0b09 vadd.f64 d0, d0, d9
  3536. 8001dd8: eeb7 8bc0 vcvt.f32.f64 s16, d0
  3537. 8001ddc: e7c2 b.n 8001d64 <EncoderTask+0x6c>
  3538. printf ("Forbidden\n");
  3539. 8001dde: f00d fdb3 bl 800f948 <puts>
  3540. 8001de2: e7bf b.n 8001d64 <EncoderTask+0x6c>
  3541. for (uint8_t i = 0; i < 4; i++) {
  3542. 8001de4: 2502 movs r5, #2
  3543. 8001de6: e79d b.n 8001d24 <EncoderTask+0x2c>
  3544. 8001de8: cccccccd .word 0xcccccccd
  3545. 8001dec: 3fdccccc .word 0x3fdccccc
  3546. 8001df0: 08011950 .word 0x08011950
  3547. 8001df4: 24000980 .word 0x24000980
  3548. 8001df8: 43b40000 .word 0x43b40000
  3549. 8001dfc: 3e8e38e4 .word 0x3e8e38e4
  3550. 8001e00: 08011a04 .word 0x08011a04
  3551. 08001e04 <MeasTasksInit>:
  3552. void MeasTasksInit (void) {
  3553. 8001e04: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  3554. vRefmVMutex = osMutexNew (NULL);
  3555. 8001e08: 2000 movs r0, #0
  3556. void MeasTasksInit (void) {
  3557. 8001e0a: b0ab sub sp, #172 @ 0xac
  3558. vRefmVMutex = osMutexNew (NULL);
  3559. 8001e0c: f009 ffb8 bl 800bd80 <osMutexNew>
  3560. 8001e10: 4b5e ldr r3, [pc, #376] @ (8001f8c <MeasTasksInit+0x188>)
  3561. 8001e12: 4602 mov r2, r0
  3562. resMeasurementsMutex = osMutexNew (NULL);
  3563. 8001e14: 2000 movs r0, #0
  3564. osThreadAttr_t osThreadAttradc1MeasTask = { 0 };
  3565. 8001e16: f04f 0a24 mov.w sl, #36 @ 0x24
  3566. osThreadAttradc3MeasTask.priority = (osPriority_t)osPriorityNormal;
  3567. 8001e1a: 2418 movs r4, #24
  3568. vRefmVMutex = osMutexNew (NULL);
  3569. 8001e1c: 601a str r2, [r3, #0]
  3570. resMeasurementsMutex = osMutexNew (NULL);
  3571. 8001e1e: f009 ffaf bl 800bd80 <osMutexNew>
  3572. 8001e22: 4b5b ldr r3, [pc, #364] @ (8001f90 <MeasTasksInit+0x18c>)
  3573. 8001e24: 4602 mov r2, r0
  3574. sensorsInfoMutex = osMutexNew (NULL);
  3575. 8001e26: 2000 movs r0, #0
  3576. osThreadAttradc1MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2;
  3577. 8001e28: f44f 6880 mov.w r8, #1024 @ 0x400
  3578. resMeasurementsMutex = osMutexNew (NULL);
  3579. 8001e2c: 601a str r2, [r3, #0]
  3580. sensorsInfoMutex = osMutexNew (NULL);
  3581. 8001e2e: f009 ffa7 bl 800bd80 <osMutexNew>
  3582. 8001e32: 4b58 ldr r3, [pc, #352] @ (8001f94 <MeasTasksInit+0x190>)
  3583. 8001e34: 4602 mov r2, r0
  3584. ILxRefMutex = osMutexNew (NULL);
  3585. 8001e36: 2000 movs r0, #0
  3586. osThreadAttradc1MeasTask.priority = (osPriority_t)osPriorityRealtime;
  3587. 8001e38: f04f 0930 mov.w r9, #48 @ 0x30
  3588. sensorsInfoMutex = osMutexNew (NULL);
  3589. 8001e3c: 601a str r2, [r3, #0]
  3590. ILxRefMutex = osMutexNew (NULL);
  3591. 8001e3e: f009 ff9f bl 800bd80 <osMutexNew>
  3592. 8001e42: 4b55 ldr r3, [pc, #340] @ (8001f98 <MeasTasksInit+0x194>)
  3593. adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL);
  3594. 8001e44: 2200 movs r2, #0
  3595. 8001e46: 2120 movs r1, #32
  3596. encoderXTaskArg.dbgLed = DBG_LED2;
  3597. 8001e48: 4e54 ldr r6, [pc, #336] @ (8001f9c <MeasTasksInit+0x198>)
  3598. ILxRefMutex = osMutexNew (NULL);
  3599. 8001e4a: 6018 str r0, [r3, #0]
  3600. adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL);
  3601. 8001e4c: 2008 movs r0, #8
  3602. 8001e4e: f00a f81f bl 800be90 <osMessageQueueNew>
  3603. 8001e52: 4b53 ldr r3, [pc, #332] @ (8001fa0 <MeasTasksInit+0x19c>)
  3604. adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL);
  3605. 8001e54: 2200 movs r2, #0
  3606. 8001e56: 2120 movs r1, #32
  3607. adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL);
  3608. 8001e58: 6018 str r0, [r3, #0]
  3609. adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL);
  3610. 8001e5a: 2008 movs r0, #8
  3611. 8001e5c: f00a f818 bl 800be90 <osMessageQueueNew>
  3612. 8001e60: 4b50 ldr r3, [pc, #320] @ (8001fa4 <MeasTasksInit+0x1a0>)
  3613. adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL);
  3614. 8001e62: 2200 movs r2, #0
  3615. 8001e64: 2120 movs r1, #32
  3616. adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL);
  3617. 8001e66: 6018 str r0, [r3, #0]
  3618. adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL);
  3619. 8001e68: 2008 movs r0, #8
  3620. 8001e6a: f00a f811 bl 800be90 <osMessageQueueNew>
  3621. 8001e6e: 4b4e ldr r3, [pc, #312] @ (8001fa8 <MeasTasksInit+0x1a4>)
  3622. osThreadAttr_t osThreadAttradc1MeasTask = { 0 };
  3623. 8001e70: 4652 mov r2, sl
  3624. 8001e72: 2100 movs r1, #0
  3625. adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL);
  3626. 8001e74: 6018 str r0, [r3, #0]
  3627. osThreadAttr_t osThreadAttradc1MeasTask = { 0 };
  3628. 8001e76: a806 add r0, sp, #24
  3629. 8001e78: f00d fe46 bl 800fb08 <memset>
  3630. osThreadAttr_t osThreadAttradc3MeasTask = { 0 };
  3631. 8001e7c: 4652 mov r2, sl
  3632. 8001e7e: 2100 movs r1, #0
  3633. 8001e80: a80f add r0, sp, #60 @ 0x3c
  3634. 8001e82: f00d fe41 bl 800fb08 <memset>
  3635. adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask);
  3636. 8001e86: eb0d 0204 add.w r2, sp, r4
  3637. 8001e8a: 2100 movs r1, #0
  3638. 8001e8c: 4847 ldr r0, [pc, #284] @ (8001fac <MeasTasksInit+0x1a8>)
  3639. encoderXTaskArg.pvEncoder = &(sensorsInfo.pvEncoderX);
  3640. 8001e8e: 4f48 ldr r7, [pc, #288] @ (8001fb0 <MeasTasksInit+0x1ac>)
  3641. encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3;
  3642. 8001e90: f8df b144 ldr.w fp, [pc, #324] @ 8001fd8 <MeasTasksInit+0x1d4>
  3643. osThreadAttradc3MeasTask.priority = (osPriority_t)osPriorityNormal;
  3644. 8001e94: e9cd 8414 strd r8, r4, [sp, #80] @ 0x50
  3645. osThreadAttradc1MeasTask.priority = (osPriority_t)osPriorityRealtime;
  3646. 8001e98: e9cd 890b strd r8, r9, [sp, #44] @ 0x2c
  3647. adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask);
  3648. 8001e9c: f009 fea6 bl 800bbec <osThreadNew>
  3649. 8001ea0: 4b44 ldr r3, [pc, #272] @ (8001fb4 <MeasTasksInit+0x1b0>)
  3650. adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask);
  3651. 8001ea2: aa0f add r2, sp, #60 @ 0x3c
  3652. 8001ea4: 2100 movs r1, #0
  3653. adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask);
  3654. 8001ea6: 6018 str r0, [r3, #0]
  3655. adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask);
  3656. 8001ea8: 4843 ldr r0, [pc, #268] @ (8001fb8 <MeasTasksInit+0x1b4>)
  3657. 8001eaa: f009 fe9f bl 800bbec <osThreadNew>
  3658. 8001eae: 4b43 ldr r3, [pc, #268] @ (8001fbc <MeasTasksInit+0x1b8>)
  3659. osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 };
  3660. 8001eb0: 4652 mov r2, sl
  3661. 8001eb2: 2100 movs r1, #0
  3662. adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask);
  3663. 8001eb4: 6018 str r0, [r3, #0]
  3664. osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 };
  3665. 8001eb6: a818 add r0, sp, #96 @ 0x60
  3666. 8001eb8: f00d fe26 bl 800fb08 <memset>
  3667. limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask);
  3668. 8001ebc: aa18 add r2, sp, #96 @ 0x60
  3669. 8001ebe: 2100 movs r1, #0
  3670. 8001ec0: 483f ldr r0, [pc, #252] @ (8001fc0 <MeasTasksInit+0x1bc>)
  3671. osThreadAttradc1LimiterSwitchTask.priority = (osPriority_t)osPriorityNormal;
  3672. 8001ec2: 941e str r4, [sp, #120] @ 0x78
  3673. osMessageQueueAttr_t encoderMsgQueueAttr = { 0 };
  3674. 8001ec4: 2400 movs r4, #0
  3675. osThreadAttradc1LimiterSwitchTask.stack_size = configMINIMAL_STACK_SIZE * 2;
  3676. 8001ec6: f8cd 8074 str.w r8, [sp, #116] @ 0x74
  3677. limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask);
  3678. 8001eca: f009 fe8f bl 800bbec <osThreadNew>
  3679. 8001ece: 4b3d ldr r3, [pc, #244] @ (8001fc4 <MeasTasksInit+0x1c0>)
  3680. encoderXTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr);
  3681. 8001ed0: 466a mov r2, sp
  3682. 8001ed2: 2104 movs r1, #4
  3683. encoderXTaskArg.pvEncoder = &(sensorsInfo.pvEncoderX);
  3684. 8001ed4: 60b7 str r7, [r6, #8]
  3685. limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask);
  3686. 8001ed6: 6018 str r0, [r3, #0]
  3687. encoderXTaskArg.dbgLed = DBG_LED2;
  3688. 8001ed8: 2320 movs r3, #32
  3689. encoderXTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr);
  3690. 8001eda: 2010 movs r0, #16
  3691. encoderXTaskArg.dbgLed = DBG_LED2;
  3692. 8001edc: 8033 strh r3, [r6, #0]
  3693. encoderXTaskArg.currentPosition = &(sensorsInfo.currentXPosition);
  3694. 8001ede: eb07 030a add.w r3, r7, sl
  3695. osMessageQueueAttr_t encoderMsgQueueAttr = { 0 };
  3696. 8001ee2: e9cd 4400 strd r4, r4, [sp]
  3697. encoderXTaskArg.currentPosition = &(sensorsInfo.currentXPosition);
  3698. 8001ee6: 6073 str r3, [r6, #4]
  3699. osMessageQueueAttr_t encoderMsgQueueAttr = { 0 };
  3700. 8001ee8: e9cd 4402 strd r4, r4, [sp, #8]
  3701. 8001eec: e9cd 4404 strd r4, r4, [sp, #16]
  3702. encoderXTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr);
  3703. 8001ef0: f009 ffce bl 800be90 <osMessageQueueNew>
  3704. encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3;
  3705. 8001ef4: f44f 4100 mov.w r1, #32768 @ 0x8000
  3706. encoderXTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr);
  3707. 8001ef8: 6130 str r0, [r6, #16]
  3708. encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3;
  3709. 8001efa: 4658 mov r0, fp
  3710. 8001efc: f005 f958 bl 80071b0 <HAL_GPIO_ReadPin>
  3711. 8001f00: 4605 mov r5, r0
  3712. 8001f02: f44f 4180 mov.w r1, #16384 @ 0x4000
  3713. 8001f06: 4658 mov r0, fp
  3714. 8001f08: f005 f952 bl 80071b0 <HAL_GPIO_ReadPin>
  3715. encoderYTaskArg.dbgLed = DBG_LED3;
  3716. 8001f0c: 2340 movs r3, #64 @ 0x40
  3717. encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3;
  3718. 8001f0e: ea40 0045 orr.w r0, r0, r5, lsl #1
  3719. encoderYTaskArg.dbgLed = DBG_LED3;
  3720. 8001f12: 4d2d ldr r5, [pc, #180] @ (8001fc8 <MeasTasksInit+0x1c4>)
  3721. encoderYTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3;
  3722. 8001f14: f5ab 6b00 sub.w fp, fp, #2048 @ 0x800
  3723. encoderYTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr);
  3724. 8001f18: 466a mov r2, sp
  3725. encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3;
  3726. 8001f1a: f000 0003 and.w r0, r0, #3
  3727. encoderYTaskArg.dbgLed = DBG_LED3;
  3728. 8001f1e: 802b strh r3, [r5, #0]
  3729. encoderYTaskArg.pvEncoder = &(sensorsInfo.pvEncoderY);
  3730. 8001f20: 1d3b adds r3, r7, #4
  3731. encoderYTaskArg.currentPosition = &(sensorsInfo.currentYPosition);
  3732. 8001f22: 3728 adds r7, #40 @ 0x28
  3733. encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3;
  3734. 8001f24: 60f0 str r0, [r6, #12]
  3735. encoderYTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr);
  3736. 8001f26: 2104 movs r1, #4
  3737. 8001f28: 2010 movs r0, #16
  3738. encoderYTaskArg.pvEncoder = &(sensorsInfo.pvEncoderY);
  3739. 8001f2a: 60ab str r3, [r5, #8]
  3740. encoderYTaskArg.currentPosition = &(sensorsInfo.currentYPosition);
  3741. 8001f2c: 606f str r7, [r5, #4]
  3742. encoderYTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr);
  3743. 8001f2e: f009 ffaf bl 800be90 <osMessageQueueNew>
  3744. encoderYTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3;
  3745. 8001f32: f44f 6100 mov.w r1, #2048 @ 0x800
  3746. encoderYTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr);
  3747. 8001f36: 6128 str r0, [r5, #16]
  3748. encoderYTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3;
  3749. 8001f38: 4658 mov r0, fp
  3750. 8001f3a: f005 f939 bl 80071b0 <HAL_GPIO_ReadPin>
  3751. 8001f3e: 4607 mov r7, r0
  3752. 8001f40: 4641 mov r1, r8
  3753. 8001f42: 4658 mov r0, fp
  3754. 8001f44: f005 f934 bl 80071b0 <HAL_GPIO_ReadPin>
  3755. osThreadAttr_t osThreadAttrEncoderTask = { 0 };
  3756. 8001f48: 4621 mov r1, r4
  3757. encoderYTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3;
  3758. 8001f4a: ea40 0047 orr.w r0, r0, r7, lsl #1
  3759. encoderXTaskHandle = osThreadNew (EncoderTask, &encoderXTaskArg, &osThreadAttrEncoderTask);
  3760. 8001f4e: 4c1f ldr r4, [pc, #124] @ (8001fcc <MeasTasksInit+0x1c8>)
  3761. osThreadAttr_t osThreadAttrEncoderTask = { 0 };
  3762. 8001f50: 4652 mov r2, sl
  3763. encoderYTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3;
  3764. 8001f52: f000 0003 and.w r0, r0, #3
  3765. 8001f56: 60e8 str r0, [r5, #12]
  3766. osThreadAttr_t osThreadAttrEncoderTask = { 0 };
  3767. 8001f58: a821 add r0, sp, #132 @ 0x84
  3768. 8001f5a: f00d fdd5 bl 800fb08 <memset>
  3769. encoderXTaskHandle = osThreadNew (EncoderTask, &encoderXTaskArg, &osThreadAttrEncoderTask);
  3770. 8001f5e: 4631 mov r1, r6
  3771. 8001f60: aa21 add r2, sp, #132 @ 0x84
  3772. 8001f62: 4620 mov r0, r4
  3773. osThreadAttrEncoderTask.stack_size = configMINIMAL_STACK_SIZE * 2;
  3774. 8001f64: f8cd 8098 str.w r8, [sp, #152] @ 0x98
  3775. osThreadAttrEncoderTask.priority = (osPriority_t)osPriorityRealtime;
  3776. 8001f68: f8cd 909c str.w r9, [sp, #156] @ 0x9c
  3777. encoderXTaskHandle = osThreadNew (EncoderTask, &encoderXTaskArg, &osThreadAttrEncoderTask);
  3778. 8001f6c: f009 fe3e bl 800bbec <osThreadNew>
  3779. 8001f70: 4b17 ldr r3, [pc, #92] @ (8001fd0 <MeasTasksInit+0x1cc>)
  3780. 8001f72: 4606 mov r6, r0
  3781. encoderYTaskHandle = osThreadNew (EncoderTask, &encoderYTaskArg, &osThreadAttrEncoderTask);
  3782. 8001f74: aa21 add r2, sp, #132 @ 0x84
  3783. 8001f76: 4629 mov r1, r5
  3784. 8001f78: 4620 mov r0, r4
  3785. encoderXTaskHandle = osThreadNew (EncoderTask, &encoderXTaskArg, &osThreadAttrEncoderTask);
  3786. 8001f7a: 601e str r6, [r3, #0]
  3787. encoderYTaskHandle = osThreadNew (EncoderTask, &encoderYTaskArg, &osThreadAttrEncoderTask);
  3788. 8001f7c: f009 fe36 bl 800bbec <osThreadNew>
  3789. 8001f80: 4b14 ldr r3, [pc, #80] @ (8001fd4 <MeasTasksInit+0x1d0>)
  3790. 8001f82: 6018 str r0, [r3, #0]
  3791. }
  3792. 8001f84: b02b add sp, #172 @ 0xac
  3793. 8001f86: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  3794. 8001f8a: bf00 nop
  3795. 8001f8c: 24000988 .word 0x24000988
  3796. 8001f90: 24000984 .word 0x24000984
  3797. 8001f94: 24000980 .word 0x24000980
  3798. 8001f98: 2400097c .word 0x2400097c
  3799. 8001f9c: 240008e0 .word 0x240008e0
  3800. 8001fa0: 24000994 .word 0x24000994
  3801. 8001fa4: 24000990 .word 0x24000990
  3802. 8001fa8: 2400098c .word 0x2400098c
  3803. 8001fac: 080018d9 .word 0x080018d9
  3804. 8001fb0: 2400090c .word 0x2400090c
  3805. 8001fb4: 240009a8 .word 0x240009a8
  3806. 8001fb8: 08001511 .word 0x08001511
  3807. 8001fbc: 240009a4 .word 0x240009a4
  3808. 8001fc0: 08001ad9 .word 0x08001ad9
  3809. 8001fc4: 240009a0 .word 0x240009a0
  3810. 8001fc8: 240008c0 .word 0x240008c0
  3811. 8001fcc: 08001cf9 .word 0x08001cf9
  3812. 8001fd0: 2400099c .word 0x2400099c
  3813. 8001fd4: 24000998 .word 0x24000998
  3814. 8001fd8: 58020c00 .word 0x58020c00
  3815. 08001fdc <DbgLEDOn>:
  3816. #include <stdlib.h>
  3817. #include "peripherial.h"
  3818. void DbgLEDOn (uint8_t ledNumber) {
  3819. 8001fdc: 4601 mov r1, r0
  3820. HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_SET);
  3821. 8001fde: 2201 movs r2, #1
  3822. 8001fe0: 4801 ldr r0, [pc, #4] @ (8001fe8 <DbgLEDOn+0xc>)
  3823. 8001fe2: f005 b8eb b.w 80071bc <HAL_GPIO_WritePin>
  3824. 8001fe6: bf00 nop
  3825. 8001fe8: 58020c00 .word 0x58020c00
  3826. 08001fec <DbgLEDOff>:
  3827. }
  3828. void DbgLEDOff (uint8_t ledNumber) {
  3829. 8001fec: 4601 mov r1, r0
  3830. HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_RESET);
  3831. 8001fee: 2200 movs r2, #0
  3832. 8001ff0: 4801 ldr r0, [pc, #4] @ (8001ff8 <DbgLEDOff+0xc>)
  3833. 8001ff2: f005 b8e3 b.w 80071bc <HAL_GPIO_WritePin>
  3834. 8001ff6: bf00 nop
  3835. 8001ff8: 58020c00 .word 0x58020c00
  3836. 08001ffc <DbgLEDToggle>:
  3837. }
  3838. void DbgLEDToggle (uint8_t ledNumber) {
  3839. 8001ffc: 4601 mov r1, r0
  3840. HAL_GPIO_TogglePin (GPIOD, ledNumber);
  3841. 8001ffe: 4801 ldr r0, [pc, #4] @ (8002004 <DbgLEDToggle+0x8>)
  3842. 8002000: f005 b8e0 b.w 80071c4 <HAL_GPIO_TogglePin>
  3843. 8002004: 58020c00 .word 0x58020c00
  3844. 08002008 <EnableCurrentSensors>:
  3845. }
  3846. void EnableCurrentSensors (void) {
  3847. HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_SET);
  3848. 8002008: 2201 movs r2, #1
  3849. 800200a: f44f 4100 mov.w r1, #32768 @ 0x8000
  3850. 800200e: 4801 ldr r0, [pc, #4] @ (8002014 <EnableCurrentSensors+0xc>)
  3851. 8002010: f005 b8d4 b.w 80071bc <HAL_GPIO_WritePin>
  3852. 8002014: 58021000 .word 0x58021000
  3853. 08002018 <SelectCurrentSensorGain>:
  3854. HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_RESET);
  3855. }
  3856. void SelectCurrentSensorGain (CurrentSensor sensor, CurrentSensorGain gain) {
  3857. uint8_t gpioOffset = 0;
  3858. switch (sensor) {
  3859. 8002018: 2802 cmp r0, #2
  3860. 800201a: d900 bls.n 800201e <SelectCurrentSensorGain+0x6>
  3861. 800201c: 4770 bx lr
  3862. case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break;
  3863. case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break;
  3864. default: break;
  3865. }
  3866. if (gpioOffset > 0) {
  3867. uint16_t gain0Gpio = 1 << gpioOffset;
  3868. 800201e: 4b0c ldr r3, [pc, #48] @ (8002050 <SelectCurrentSensorGain+0x38>)
  3869. void SelectCurrentSensorGain (CurrentSensor sensor, CurrentSensorGain gain) {
  3870. 8002020: b570 push {r4, r5, r6, lr}
  3871. uint16_t gain0Gpio = 1 << gpioOffset;
  3872. 8002022: 2501 movs r5, #1
  3873. 8002024: 5c1e ldrb r6, [r3, r0]
  3874. uint16_t gain1Gpio = 1 << (gpioOffset + 1);
  3875. uint16_t gpioState = ((uint16_t)gain) & 0x0001;
  3876. 8002026: 460c mov r4, r1
  3877. HAL_GPIO_WritePin (GPIOE, gain0Gpio, gpioState);
  3878. 8002028: 480a ldr r0, [pc, #40] @ (8002054 <SelectCurrentSensorGain+0x3c>)
  3879. uint16_t gain0Gpio = 1 << gpioOffset;
  3880. 800202a: fa05 f106 lsl.w r1, r5, r6
  3881. uint16_t gain1Gpio = 1 << (gpioOffset + 1);
  3882. 800202e: 442e add r6, r5
  3883. HAL_GPIO_WritePin (GPIOE, gain0Gpio, gpioState);
  3884. 8002030: ea04 0205 and.w r2, r4, r5
  3885. 8002034: b289 uxth r1, r1
  3886. 8002036: f005 f8c1 bl 80071bc <HAL_GPIO_WritePin>
  3887. uint16_t gain1Gpio = 1 << (gpioOffset + 1);
  3888. 800203a: fa05 f106 lsl.w r1, r5, r6
  3889. gpioState = (((uint16_t)gain) >> 1) & 0x0001;
  3890. HAL_GPIO_WritePin (GPIOE, gain1Gpio, gpioState);
  3891. 800203e: f3c4 0240 ubfx r2, r4, #1, #1
  3892. 8002042: 4804 ldr r0, [pc, #16] @ (8002054 <SelectCurrentSensorGain+0x3c>)
  3893. 8002044: b289 uxth r1, r1
  3894. }
  3895. }
  3896. 8002046: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  3897. HAL_GPIO_WritePin (GPIOE, gain1Gpio, gpioState);
  3898. 800204a: f005 b8b7 b.w 80071bc <HAL_GPIO_WritePin>
  3899. 800204e: bf00 nop
  3900. 8002050: 08011a10 .word 0x08011a10
  3901. 8002054: 58021000 .word 0x58021000
  3902. 08002058 <MotorControl>:
  3903. uint8_t
  3904. MotorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) {
  3905. 8002058: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  3906. 800205c: 461f mov r7, r3
  3907. 800205e: 4604 mov r4, r0
  3908. 8002060: f8dd 9030 ldr.w r9, [sp, #48] @ 0x30
  3909. 8002064: 460d mov r5, r1
  3910. uint32_t motorStatus = 0;
  3911. MotorDriverState setMotorState = HiZ;
  3912. HAL_TIM_PWM_Stop (htim, channel1);
  3913. 8002066: 4611 mov r1, r2
  3914. MotorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) {
  3915. 8002068: 4690 mov r8, r2
  3916. 800206a: 9e0b ldr r6, [sp, #44] @ 0x2c
  3917. 800206c: f89d a034 ldrb.w sl, [sp, #52] @ 0x34
  3918. 8002070: f89d b038 ldrb.w fp, [sp, #56] @ 0x38
  3919. HAL_TIM_PWM_Stop (htim, channel1);
  3920. 8002074: f007 fef0 bl 8009e58 <HAL_TIM_PWM_Stop>
  3921. HAL_TIM_PWM_Stop (htim, channel2);
  3922. 8002078: 4639 mov r1, r7
  3923. 800207a: 4620 mov r0, r4
  3924. 800207c: f007 feec bl 8009e58 <HAL_TIM_PWM_Stop>
  3925. if (motorTimerPeriod > 0) {
  3926. 8002080: f1b9 0f00 cmp.w r9, #0
  3927. 8002084: dd4a ble.n 800211c <MotorControl+0xc4>
  3928. if (motorPWMPulse > 0) {
  3929. 8002086: 2e00 cmp r6, #0
  3930. 8002088: dd20 ble.n 80020cc <MotorControl+0x74>
  3931. // Forward
  3932. if (switchLimiterUpStat == 0) {
  3933. 800208a: f1ba 0f00 cmp.w sl, #0
  3934. 800208e: d14f bne.n 8002130 <MotorControl+0xd8>
  3935. setMotorState = Forward;
  3936. MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10);
  3937. 8002090: eb06 0686 add.w r6, r6, r6, lsl #2
  3938. switch (setState) {
  3939. case Forward:
  3940. case Reverse:
  3941. case HiZ:
  3942. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  3943. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  3944. 8002094: 4642 mov r2, r8
  3945. 8002096: 4629 mov r1, r5
  3946. 8002098: 4620 mov r0, r4
  3947. MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10);
  3948. 800209a: 0076 lsls r6, r6, #1
  3949. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  3950. 800209c: f8c5 a008 str.w sl, [r5, #8]
  3951. timerConf->Pulse = pulse;
  3952. 80020a0: 606e str r6, [r5, #4]
  3953. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  3954. 80020a2: f008 f93b bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  3955. 80020a6: 2800 cmp r0, #0
  3956. 80020a8: f040 80ba bne.w 8002220 <MotorControl+0x1c8>
  3957. Error_Handler ();
  3958. }
  3959. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  3960. 80020ac: 2300 movs r3, #0
  3961. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  3962. 80020ae: 4629 mov r1, r5
  3963. 80020b0: 463a mov r2, r7
  3964. 80020b2: 4620 mov r0, r4
  3965. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  3966. 80020b4: 60ab str r3, [r5, #8]
  3967. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  3968. 80020b6: f008 f931 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  3969. 80020ba: 2800 cmp r0, #0
  3970. 80020bc: f040 80ad bne.w 800221a <MotorControl+0x1c2>
  3971. HAL_TIM_PWM_Start (htim, channel1);
  3972. 80020c0: 4641 mov r1, r8
  3973. 80020c2: 4620 mov r0, r4
  3974. 80020c4: 2501 movs r5, #1
  3975. 80020c6: f007 fe27 bl 8009d18 <HAL_TIM_PWM_Start>
  3976. motorStatus = 1;
  3977. 80020ca: e036 b.n 800213a <MotorControl+0xe2>
  3978. } else if (motorPWMPulse < 0) {
  3979. 80020cc: d066 beq.n 800219c <MotorControl+0x144>
  3980. if (switchLimiterDownStat == 0) {
  3981. 80020ce: f1bb 0f00 cmp.w fp, #0
  3982. 80020d2: f040 809c bne.w 800220e <MotorControl+0x1b6>
  3983. MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10);
  3984. 80020d6: f06f 0309 mvn.w r3, #9
  3985. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  3986. 80020da: 4642 mov r2, r8
  3987. 80020dc: 4629 mov r1, r5
  3988. 80020de: 4620 mov r0, r4
  3989. MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10);
  3990. 80020e0: fb06 f303 mul.w r3, r6, r3
  3991. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  3992. 80020e4: f8c5 b008 str.w fp, [r5, #8]
  3993. timerConf->Pulse = pulse;
  3994. 80020e8: 606b str r3, [r5, #4]
  3995. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  3996. 80020ea: f008 f917 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  3997. 80020ee: 2800 cmp r0, #0
  3998. 80020f0: f040 80ce bne.w 8002290 <MotorControl+0x238>
  3999. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4000. 80020f4: 2300 movs r3, #0
  4001. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4002. 80020f6: 4629 mov r1, r5
  4003. 80020f8: 463a mov r2, r7
  4004. 80020fa: 4620 mov r0, r4
  4005. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4006. 80020fc: 60ab str r3, [r5, #8]
  4007. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4008. 80020fe: f008 f90d bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4009. 8002102: 2800 cmp r0, #0
  4010. 8002104: f040 80c1 bne.w 800228a <MotorControl+0x232>
  4011. HAL_TIM_PWM_Start (htim, channel2);
  4012. 8002108: 2501 movs r5, #1
  4013. 800210a: 4639 mov r1, r7
  4014. 800210c: 4620 mov r0, r4
  4015. 800210e: f007 fe03 bl 8009d18 <HAL_TIM_PWM_Start>
  4016. HAL_TIM_PWM_Stop (htim, channel1);
  4017. 8002112: 4641 mov r1, r8
  4018. 8002114: 4620 mov r0, r4
  4019. 8002116: f007 fe9f bl 8009e58 <HAL_TIM_PWM_Stop>
  4020. 800211a: e012 b.n 8002142 <MotorControl+0xea>
  4021. } else if ((motorTimerPeriod == 0) && (motorPWMPulse == 0)) {
  4022. 800211c: ea59 0306 orrs.w r3, r9, r6
  4023. 8002120: d059 beq.n 80021d6 <MotorControl+0x17e>
  4024. } else if (motorTimerPeriod == -1) {
  4025. 8002122: f1b9 3fff cmp.w r9, #4294967295 @ 0xffffffff
  4026. 8002126: d016 beq.n 8002156 <MotorControl+0xfe>
  4027. HAL_TIM_PWM_Stop (htim, channel2);
  4028. 8002128: 2500 movs r5, #0
  4029. }
  4030. 800212a: 4628 mov r0, r5
  4031. 800212c: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
  4032. HAL_TIM_PWM_Stop (htim, channel1);
  4033. 8002130: 2500 movs r5, #0
  4034. 8002132: 4641 mov r1, r8
  4035. 8002134: 4620 mov r0, r4
  4036. 8002136: f007 fe8f bl 8009e58 <HAL_TIM_PWM_Stop>
  4037. HAL_TIM_PWM_Stop (htim, channel2);
  4038. 800213a: 4639 mov r1, r7
  4039. 800213c: 4620 mov r0, r4
  4040. 800213e: f007 fe8b bl 8009e58 <HAL_TIM_PWM_Stop>
  4041. osTimerStart (motorTimerHandle, motorTimerPeriod * 1000);
  4042. 8002142: f44f 717a mov.w r1, #1000 @ 0x3e8
  4043. 8002146: 980a ldr r0, [sp, #40] @ 0x28
  4044. 8002148: fb01 f109 mul.w r1, r1, r9
  4045. 800214c: f009 fde0 bl 800bd10 <osTimerStart>
  4046. }
  4047. 8002150: 4628 mov r0, r5
  4048. 8002152: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
  4049. if (motorPWMPulse > 0) {
  4050. 8002156: 2e00 cmp r6, #0
  4051. 8002158: dd75 ble.n 8002246 <MotorControl+0x1ee>
  4052. if (switchLimiterUpStat == 0) {
  4053. 800215a: f1ba 0f00 cmp.w sl, #0
  4054. 800215e: d162 bne.n 8002226 <MotorControl+0x1ce>
  4055. MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10);
  4056. 8002160: eb06 0686 add.w r6, r6, r6, lsl #2
  4057. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  4058. 8002164: 4642 mov r2, r8
  4059. 8002166: 4629 mov r1, r5
  4060. 8002168: 4620 mov r0, r4
  4061. MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10);
  4062. 800216a: 0076 lsls r6, r6, #1
  4063. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4064. 800216c: f8c5 a008 str.w sl, [r5, #8]
  4065. timerConf->Pulse = pulse;
  4066. 8002170: 606e str r6, [r5, #4]
  4067. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  4068. 8002172: f008 f8d3 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4069. 8002176: 2800 cmp r0, #0
  4070. 8002178: f040 809c bne.w 80022b4 <MotorControl+0x25c>
  4071. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4072. 800217c: 2300 movs r3, #0
  4073. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4074. 800217e: 463a mov r2, r7
  4075. 8002180: 4629 mov r1, r5
  4076. 8002182: 4620 mov r0, r4
  4077. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4078. 8002184: 60ab str r3, [r5, #8]
  4079. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4080. 8002186: f008 f8c9 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4081. 800218a: 2800 cmp r0, #0
  4082. 800218c: f040 808f bne.w 80022ae <MotorControl+0x256>
  4083. HAL_TIM_PWM_Start (htim, channel1);
  4084. 8002190: 4641 mov r1, r8
  4085. 8002192: 4620 mov r0, r4
  4086. 8002194: 2501 movs r5, #1
  4087. 8002196: f007 fdbf bl 8009d18 <HAL_TIM_PWM_Start>
  4088. motorStatus = 1;
  4089. 800219a: e049 b.n 8002230 <MotorControl+0x1d8>
  4090. timerConf->Pulse = pulse;
  4091. 800219c: 2302 movs r3, #2
  4092. Error_Handler ();
  4093. }
  4094. break;
  4095. case Brake:
  4096. timerConf->OCPolarity = TIM_OCPOLARITY_LOW;
  4097. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  4098. 800219e: 4642 mov r2, r8
  4099. 80021a0: 4629 mov r1, r5
  4100. 80021a2: 4620 mov r0, r4
  4101. timerConf->Pulse = pulse;
  4102. 80021a4: 606e str r6, [r5, #4]
  4103. 80021a6: 60ab str r3, [r5, #8]
  4104. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  4105. 80021a8: f008 f8b8 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4106. 80021ac: 2800 cmp r0, #0
  4107. 80021ae: d175 bne.n 800229c <MotorControl+0x244>
  4108. Error_Handler ();
  4109. }
  4110. timerConf->OCPolarity = TIM_OCPOLARITY_LOW;
  4111. 80021b0: 2302 movs r3, #2
  4112. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4113. 80021b2: 4629 mov r1, r5
  4114. 80021b4: 463a mov r2, r7
  4115. 80021b6: 4620 mov r0, r4
  4116. timerConf->OCPolarity = TIM_OCPOLARITY_LOW;
  4117. 80021b8: 60ab str r3, [r5, #8]
  4118. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4119. 80021ba: f008 f8af bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4120. 80021be: 2800 cmp r0, #0
  4121. 80021c0: d169 bne.n 8002296 <MotorControl+0x23e>
  4122. HAL_TIM_PWM_Start (htim, channel1);
  4123. 80021c2: 4641 mov r1, r8
  4124. 80021c4: 4620 mov r0, r4
  4125. 80021c6: f007 fda7 bl 8009d18 <HAL_TIM_PWM_Start>
  4126. HAL_TIM_PWM_Start (htim, channel2);
  4127. 80021ca: 4639 mov r1, r7
  4128. 80021cc: 4620 mov r0, r4
  4129. 80021ce: 2500 movs r5, #0
  4130. 80021d0: f007 fda2 bl 8009d18 <HAL_TIM_PWM_Start>
  4131. motorStatus = 0;
  4132. 80021d4: e7b5 b.n 8002142 <MotorControl+0xea>
  4133. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  4134. 80021d6: 4642 mov r2, r8
  4135. 80021d8: 4629 mov r1, r5
  4136. 80021da: 4620 mov r0, r4
  4137. timerConf->Pulse = pulse;
  4138. 80021dc: e9c5 3301 strd r3, r3, [r5, #4]
  4139. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  4140. 80021e0: f008 f89c bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4141. 80021e4: bb60 cbnz r0, 8002240 <MotorControl+0x1e8>
  4142. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4143. 80021e6: 2300 movs r3, #0
  4144. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4145. 80021e8: 463a mov r2, r7
  4146. 80021ea: 4629 mov r1, r5
  4147. 80021ec: 4620 mov r0, r4
  4148. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4149. 80021ee: 60ab str r3, [r5, #8]
  4150. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4151. 80021f0: f008 f894 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4152. 80021f4: bb08 cbnz r0, 800223a <MotorControl+0x1e2>
  4153. HAL_TIM_PWM_Stop (htim, channel1);
  4154. 80021f6: 4641 mov r1, r8
  4155. 80021f8: 4620 mov r0, r4
  4156. 80021fa: f007 fe2d bl 8009e58 <HAL_TIM_PWM_Stop>
  4157. HAL_TIM_PWM_Stop (htim, channel2);
  4158. 80021fe: 4639 mov r1, r7
  4159. 8002200: 4620 mov r0, r4
  4160. 8002202: f007 fe29 bl 8009e58 <HAL_TIM_PWM_Stop>
  4161. osTimerStop (motorTimerHandle);
  4162. 8002206: 980a ldr r0, [sp, #40] @ 0x28
  4163. 8002208: f009 fd9a bl 800bd40 <osTimerStop>
  4164. motorStatus = 0;
  4165. 800220c: e78c b.n 8002128 <MotorControl+0xd0>
  4166. HAL_TIM_PWM_Stop (htim, channel2);
  4167. 800220e: 4639 mov r1, r7
  4168. 8002210: 4620 mov r0, r4
  4169. 8002212: 2500 movs r5, #0
  4170. 8002214: f007 fe20 bl 8009e58 <HAL_TIM_PWM_Stop>
  4171. 8002218: e77b b.n 8002112 <MotorControl+0xba>
  4172. Error_Handler ();
  4173. 800221a: f7fe faed bl 80007f8 <Error_Handler>
  4174. 800221e: e74f b.n 80020c0 <MotorControl+0x68>
  4175. Error_Handler ();
  4176. 8002220: f7fe faea bl 80007f8 <Error_Handler>
  4177. 8002224: e742 b.n 80020ac <MotorControl+0x54>
  4178. HAL_TIM_PWM_Stop (htim, channel1);
  4179. 8002226: 4641 mov r1, r8
  4180. 8002228: 4620 mov r0, r4
  4181. 800222a: 2500 movs r5, #0
  4182. 800222c: f007 fe14 bl 8009e58 <HAL_TIM_PWM_Stop>
  4183. HAL_TIM_PWM_Stop (htim, channel2);
  4184. 8002230: 4639 mov r1, r7
  4185. 8002232: 4620 mov r0, r4
  4186. 8002234: f007 fe10 bl 8009e58 <HAL_TIM_PWM_Stop>
  4187. 8002238: e777 b.n 800212a <MotorControl+0xd2>
  4188. Error_Handler ();
  4189. 800223a: f7fe fadd bl 80007f8 <Error_Handler>
  4190. 800223e: e7da b.n 80021f6 <MotorControl+0x19e>
  4191. Error_Handler ();
  4192. 8002240: f7fe fada bl 80007f8 <Error_Handler>
  4193. 8002244: e7cf b.n 80021e6 <MotorControl+0x18e>
  4194. if (switchLimiterDownStat == 0) {
  4195. 8002246: f1bb 0f00 cmp.w fp, #0
  4196. 800224a: d12a bne.n 80022a2 <MotorControl+0x24a>
  4197. MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10);
  4198. 800224c: f06f 0309 mvn.w r3, #9
  4199. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  4200. 8002250: 4642 mov r2, r8
  4201. 8002252: 4629 mov r1, r5
  4202. 8002254: 4620 mov r0, r4
  4203. MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10);
  4204. 8002256: fb03 f606 mul.w r6, r3, r6
  4205. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4206. 800225a: f8c5 b008 str.w fp, [r5, #8]
  4207. timerConf->Pulse = pulse;
  4208. 800225e: 606e str r6, [r5, #4]
  4209. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  4210. 8002260: f008 f85c bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4211. 8002264: bb60 cbnz r0, 80022c0 <MotorControl+0x268>
  4212. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4213. 8002266: 2300 movs r3, #0
  4214. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4215. 8002268: 463a mov r2, r7
  4216. 800226a: 4629 mov r1, r5
  4217. 800226c: 4620 mov r0, r4
  4218. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4219. 800226e: 60ab str r3, [r5, #8]
  4220. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4221. 8002270: f008 f854 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4222. 8002274: bb08 cbnz r0, 80022ba <MotorControl+0x262>
  4223. HAL_TIM_PWM_Start (htim, channel2);
  4224. 8002276: 4639 mov r1, r7
  4225. 8002278: 4620 mov r0, r4
  4226. 800227a: 2501 movs r5, #1
  4227. 800227c: f007 fd4c bl 8009d18 <HAL_TIM_PWM_Start>
  4228. HAL_TIM_PWM_Stop (htim, channel1);
  4229. 8002280: 4641 mov r1, r8
  4230. 8002282: 4620 mov r0, r4
  4231. 8002284: f007 fde8 bl 8009e58 <HAL_TIM_PWM_Stop>
  4232. 8002288: e74f b.n 800212a <MotorControl+0xd2>
  4233. Error_Handler ();
  4234. 800228a: f7fe fab5 bl 80007f8 <Error_Handler>
  4235. 800228e: e73b b.n 8002108 <MotorControl+0xb0>
  4236. Error_Handler ();
  4237. 8002290: f7fe fab2 bl 80007f8 <Error_Handler>
  4238. 8002294: e72e b.n 80020f4 <MotorControl+0x9c>
  4239. Error_Handler ();
  4240. 8002296: f7fe faaf bl 80007f8 <Error_Handler>
  4241. 800229a: e792 b.n 80021c2 <MotorControl+0x16a>
  4242. Error_Handler ();
  4243. 800229c: f7fe faac bl 80007f8 <Error_Handler>
  4244. 80022a0: e786 b.n 80021b0 <MotorControl+0x158>
  4245. HAL_TIM_PWM_Stop (htim, channel2);
  4246. 80022a2: 4639 mov r1, r7
  4247. 80022a4: 4620 mov r0, r4
  4248. 80022a6: 2500 movs r5, #0
  4249. 80022a8: f007 fdd6 bl 8009e58 <HAL_TIM_PWM_Stop>
  4250. 80022ac: e7e8 b.n 8002280 <MotorControl+0x228>
  4251. Error_Handler ();
  4252. 80022ae: f7fe faa3 bl 80007f8 <Error_Handler>
  4253. 80022b2: e76d b.n 8002190 <MotorControl+0x138>
  4254. Error_Handler ();
  4255. 80022b4: f7fe faa0 bl 80007f8 <Error_Handler>
  4256. 80022b8: e760 b.n 800217c <MotorControl+0x124>
  4257. Error_Handler ();
  4258. 80022ba: f7fe fa9d bl 80007f8 <Error_Handler>
  4259. 80022be: e7da b.n 8002276 <MotorControl+0x21e>
  4260. Error_Handler ();
  4261. 80022c0: f7fe fa9a bl 80007f8 <Error_Handler>
  4262. 80022c4: e7cf b.n 8002266 <MotorControl+0x20e>
  4263. 80022c6: bf00 nop
  4264. 080022c8 <MotorAction>:
  4265. void MotorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) {
  4266. 80022c8: b570 push {r4, r5, r6, lr}
  4267. 80022ca: f89d c010 ldrb.w ip, [sp, #16]
  4268. 80022ce: 461d mov r5, r3
  4269. timerConf->Pulse = pulse;
  4270. 80022d0: 9b05 ldr r3, [sp, #20]
  4271. void MotorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) {
  4272. 80022d2: 4606 mov r6, r0
  4273. switch (setState) {
  4274. 80022d4: f1bc 0f02 cmp.w ip, #2
  4275. void MotorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) {
  4276. 80022d8: 460c mov r4, r1
  4277. timerConf->Pulse = pulse;
  4278. 80022da: 604b str r3, [r1, #4]
  4279. switch (setState) {
  4280. 80022dc: d913 bls.n 8002306 <MotorAction+0x3e>
  4281. 80022de: f1bc 0f03 cmp.w ip, #3
  4282. 80022e2: d110 bne.n 8002306 <MotorAction+0x3e>
  4283. timerConf->OCPolarity = TIM_OCPOLARITY_LOW;
  4284. 80022e4: 2302 movs r3, #2
  4285. 80022e6: 608b str r3, [r1, #8]
  4286. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  4287. 80022e8: f008 f818 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4288. 80022ec: b9e8 cbnz r0, 800232a <MotorAction+0x62>
  4289. timerConf->OCPolarity = TIM_OCPOLARITY_LOW;
  4290. 80022ee: 2302 movs r3, #2
  4291. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4292. 80022f0: 462a mov r2, r5
  4293. 80022f2: 4621 mov r1, r4
  4294. 80022f4: 4630 mov r0, r6
  4295. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4296. 80022f6: 60a3 str r3, [r4, #8]
  4297. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4298. 80022f8: f008 f810 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4299. 80022fc: b188 cbz r0, 8002322 <MotorAction+0x5a>
  4300. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4301. Error_Handler ();
  4302. }
  4303. break;
  4304. }
  4305. }
  4306. 80022fe: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  4307. Error_Handler ();
  4308. 8002302: f7fe ba79 b.w 80007f8 <Error_Handler>
  4309. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4310. 8002306: 2300 movs r3, #0
  4311. 8002308: 60a3 str r3, [r4, #8]
  4312. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) {
  4313. 800230a: f008 f807 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4314. 800230e: b948 cbnz r0, 8002324 <MotorAction+0x5c>
  4315. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4316. 8002310: 2300 movs r3, #0
  4317. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4318. 8002312: 462a mov r2, r5
  4319. 8002314: 4621 mov r1, r4
  4320. 8002316: 4630 mov r0, r6
  4321. timerConf->OCPolarity = TIM_OCPOLARITY_HIGH;
  4322. 8002318: 60a3 str r3, [r4, #8]
  4323. if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) {
  4324. 800231a: f007 ffff bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  4325. 800231e: 2800 cmp r0, #0
  4326. 8002320: d1ed bne.n 80022fe <MotorAction+0x36>
  4327. }
  4328. 8002322: bd70 pop {r4, r5, r6, pc}
  4329. Error_Handler ();
  4330. 8002324: f7fe fa68 bl 80007f8 <Error_Handler>
  4331. 8002328: e7f2 b.n 8002310 <MotorAction+0x48>
  4332. Error_Handler ();
  4333. 800232a: f7fe fa65 bl 80007f8 <Error_Handler>
  4334. timerConf->OCPolarity = TIM_OCPOLARITY_LOW;
  4335. 800232e: 2302 movs r3, #2
  4336. 8002330: e7de b.n 80022f0 <MotorAction+0x28>
  4337. 8002332: bf00 nop
  4338. 08002334 <PositionControlTask>:
  4339. positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask);
  4340. positionYControlTaskHandle = osThreadNew (PositionControlTask, &positionYControlTaskInitArg, &osThreadAttrPositionControlTask);
  4341. }
  4342. void PositionControlTask (void* argument) {
  4343. 8002334: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  4344. 8002338: ed2d 8b04 vpush {d8-d9}
  4345. 800233c: b091 sub sp, #68 @ 0x44
  4346. const int32_t PositionControlTaskTimeOut = 100;
  4347. PositionControlTaskInitArg* posCtrlTaskArg = (PositionControlTaskInitArg*)argument;
  4348. PositionControlTaskData posCtrlData __attribute__ ((aligned (32))) = { 0 };
  4349. 800233e: eddf 7aac vldr s15, [pc, #688] @ 80025f0 <PositionControlTask+0x2bc>
  4350. int32_t sign = 0;
  4351. MovementPhases movementPhase = idlePhase;
  4352. float startPosition = 0;
  4353. float prevPosition = 0;
  4354. int32_t timeLeftMS = 0;
  4355. int32_t moveCmdTimeoutCounter = 0;
  4356. 8002342: f04f 0800 mov.w r8, #0
  4357. int32_t pwmValue = MOTOR_START_STOP_PWM_VALUE;
  4358. 8002346: 233c movs r3, #60 @ 0x3c
  4359. void PositionControlTask (void* argument) {
  4360. 8002348: f10d 043f add.w r4, sp, #63 @ 0x3f
  4361. float prevPosition = 0;
  4362. 800234c: eeb0 9a67 vmov.f32 s18, s15
  4363. float startPosition = 0;
  4364. 8002350: eeb0 8a67 vmov.f32 s16, s15
  4365. int32_t timeLeftMS = 0;
  4366. 8002354: 46c2 mov sl, r8
  4367. void PositionControlTask (void* argument) {
  4368. 8002356: f024 041f bic.w r4, r4, #31
  4369. 800235a: 4605 mov r5, r0
  4370. MovementPhases movementPhase = idlePhase;
  4371. 800235c: 4647 mov r7, r8
  4372. int32_t sign = 0;
  4373. 800235e: 46c3 mov fp, r8
  4374. 8002360: 4ea4 ldr r6, [pc, #656] @ (80025f4 <PositionControlTask+0x2c0>)
  4375. 8002362: f8df 9294 ldr.w r9, [pc, #660] @ 80025f8 <PositionControlTask+0x2c4>
  4376. PositionControlTaskData posCtrlData __attribute__ ((aligned (32))) = { 0 };
  4377. 8002366: edc4 7a00 vstr s15, [r4]
  4378. int32_t pwmValue = MOTOR_START_STOP_PWM_VALUE;
  4379. 800236a: 9307 str r3, [sp, #28]
  4380. while (pdTRUE) {
  4381. queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut));
  4382. 800236c: 2364 movs r3, #100 @ 0x64
  4383. 800236e: 2200 movs r2, #0
  4384. 8002370: 4621 mov r1, r4
  4385. 8002372: 6928 ldr r0, [r5, #16]
  4386. 8002374: f009 fe04 bl 800bf80 <osMessageQueueGet>
  4387. if (queueSatus == osOK) {
  4388. 8002378: bb28 cbnz r0, 80023c6 <PositionControlTask+0x92>
  4389. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  4390. 800237a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  4391. 800237e: 6830 ldr r0, [r6, #0]
  4392. 8002380: f009 fd40 bl 800be04 <osMutexAcquire>
  4393. 8002384: 2800 cmp r0, #0
  4394. 8002386: d1f1 bne.n 800236c <PositionControlTask+0x38>
  4395. float posDiff = posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition;
  4396. 8002388: 6a2b ldr r3, [r5, #32]
  4397. 800238a: edd4 7a00 vldr s15, [r4]
  4398. 800238e: ed93 7a00 vldr s14, [r3]
  4399. 8002392: ee77 7ac7 vsub.f32 s15, s15, s14
  4400. if (posDiff != 0) {
  4401. 8002396: eef5 7a40 vcmp.f32 s15, #0.0
  4402. 800239a: eef1 fa10 vmrs APSR_nzcv, fpscr
  4403. 800239e: d00a beq.n 80023b6 <PositionControlTask+0x82>
  4404. sign = posDiff > 0 ? 1 : -1;
  4405. 80023a0: eef5 7ac0 vcmpe.f32 s15, #0.0
  4406. startPosition = *posCtrlTaskArg->currentPosition;
  4407. movementPhase = startPhase;
  4408. moveCmdTimeoutCounter = 0;
  4409. 80023a4: 4680 mov r8, r0
  4410. sign = posDiff > 0 ? 1 : -1;
  4411. 80023a6: eef1 fa10 vmrs APSR_nzcv, fpscr
  4412. 80023aa: dd4a ble.n 8002442 <PositionControlTask+0x10e>
  4413. movementPhase = startPhase;
  4414. 80023ac: 2701 movs r7, #1
  4415. startPosition = *posCtrlTaskArg->currentPosition;
  4416. 80023ae: eeb0 8a47 vmov.f32 s16, s14
  4417. timeLeftMS = 0;
  4418. 80023b2: 4682 mov sl, r0
  4419. sign = posDiff > 0 ? 1 : -1;
  4420. 80023b4: 46bb mov fp, r7
  4421. #ifdef DBG_POSITION
  4422. printf ("Axe %c start phase\n", posCtrlTaskArg->axe);
  4423. #endif
  4424. }
  4425. osMutexRelease (sensorsInfoMutex);
  4426. 80023b6: 6830 ldr r0, [r6, #0]
  4427. 80023b8: f009 fd48 bl 800be4c <osMutexRelease>
  4428. // if (osMutexAcquire (positionSettingMutex, osWaitForever) == osOK) {
  4429. *positionXControlTaskInitArg.positionSetting = posCtrlData.positionSettingValue;
  4430. 80023bc: 6822 ldr r2, [r4, #0]
  4431. 80023be: f8d9 3024 ldr.w r3, [r9, #36] @ 0x24
  4432. 80023c2: 601a str r2, [r3, #0]
  4433. 80023c4: e7d2 b.n 800236c <PositionControlTask+0x38>
  4434. // osMutexRelease (positionSettingMutex);
  4435. // }
  4436. }
  4437. } else if (queueSatus == osErrorTimeout) {
  4438. 80023c6: 3002 adds r0, #2
  4439. 80023c8: d1d0 bne.n 800236c <PositionControlTask+0x38>
  4440. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  4441. 80023ca: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  4442. 80023ce: 6830 ldr r0, [r6, #0]
  4443. 80023d0: f009 fd18 bl 800be04 <osMutexAcquire>
  4444. 80023d4: 2800 cmp r0, #0
  4445. 80023d6: d1c9 bne.n 800236c <PositionControlTask+0x38>
  4446. if (((*posCtrlTaskArg->motorStatus != 0) && (movementPhase != idlePhase)) || (movementPhase == startPhase) ) {
  4447. 80023d8: 6aab ldr r3, [r5, #40] @ 0x28
  4448. 80023da: 781b ldrb r3, [r3, #0]
  4449. 80023dc: 2b00 cmp r3, #0
  4450. 80023de: d037 beq.n 8002450 <PositionControlTask+0x11c>
  4451. 80023e0: b35f cbz r7, 800243a <PositionControlTask+0x106>
  4452. if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) ||
  4453. 80023e2: e9d5 1c05 ldrd r1, ip, [r5, #20]
  4454. 80023e6: f89c 2000 ldrb.w r2, [ip]
  4455. 80023ea: 780b ldrb r3, [r1, #0]
  4456. 80023ec: 2a01 cmp r2, #1
  4457. 80023ee: d03d beq.n 800246c <PositionControlTask+0x138>
  4458. 80023f0: 2b01 cmp r3, #1
  4459. 80023f2: d061 beq.n 80024b8 <PositionControlTask+0x184>
  4460. #endif
  4461. }
  4462. timeLeftMS += PositionControlTaskTimeOut;
  4463. if (prevPosition == *posCtrlTaskArg->currentPosition) {
  4464. 80023f4: 6a28 ldr r0, [r5, #32]
  4465. timeLeftMS += PositionControlTaskTimeOut;
  4466. 80023f6: f10a 0a64 add.w sl, sl, #100 @ 0x64
  4467. if (prevPosition == *posCtrlTaskArg->currentPosition) {
  4468. 80023fa: edd0 8a00 vldr s17, [r0]
  4469. 80023fe: eef4 8a49 vcmp.f32 s17, s18
  4470. 8002402: eef1 fa10 vmrs APSR_nzcv, fpscr
  4471. 8002406: d127 bne.n 8002458 <PositionControlTask+0x124>
  4472. moveCmdTimeoutCounter += PositionControlTaskTimeOut;
  4473. 8002408: f108 0864 add.w r8, r8, #100 @ 0x64
  4474. } else {
  4475. moveCmdTimeoutCounter = 0;
  4476. }
  4477. prevPosition = *posCtrlTaskArg->currentPosition;
  4478. if (moveCmdTimeoutCounter > NO_MOVE_TIMEOUT_MS) {
  4479. 800240c: f241 3088 movw r0, #5000 @ 0x1388
  4480. 8002410: 4580 cmp r8, r0
  4481. 8002412: f340 80dd ble.w 80025d0 <PositionControlTask+0x29c>
  4482. movementPhase = idlePhase;
  4483. motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0,
  4484. 8002416: f89c 3000 ldrb.w r3, [ip]
  4485. 800241a: 9304 str r3, [sp, #16]
  4486. 800241c: 780b ldrb r3, [r1, #0]
  4487. 800241e: 9303 str r3, [sp, #12]
  4488. #endif
  4489. break;
  4490. case stopPhase:
  4491. float posDiff = sign > 0 ? posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition : *posCtrlTaskArg->currentPosition - posCtrlData.positionSettingValue;
  4492. if ((posDiff <= 0) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) {
  4493. motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle,
  4494. 8002420: 2700 movs r7, #0
  4495. 8002422: e9cd 7701 strd r7, r7, [sp, #4]
  4496. 8002426: 68eb ldr r3, [r5, #12]
  4497. 8002428: 9300 str r3, [sp, #0]
  4498. 800242a: 7a6b ldrb r3, [r5, #9]
  4499. 800242c: 7a2a ldrb r2, [r5, #8]
  4500. 800242e: e9d5 0100 ldrd r0, r1, [r5]
  4501. 8002432: f7ff fe11 bl 8002058 <MotorControl>
  4502. 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat);
  4503. *posCtrlTaskArg->motorStatus = motorStatus;
  4504. 8002436: 6aab ldr r3, [r5, #40] @ 0x28
  4505. 8002438: 7018 strb r0, [r3, #0]
  4506. #ifdef DBG_POSITION
  4507. printf ("Axe %c idle phase\n", posCtrlTaskArg->axe);
  4508. #endif
  4509. }
  4510. }
  4511. osMutexRelease (sensorsInfoMutex);
  4512. 800243a: 6830 ldr r0, [r6, #0]
  4513. 800243c: f009 fd06 bl 800be4c <osMutexRelease>
  4514. 8002440: e794 b.n 800236c <PositionControlTask+0x38>
  4515. startPosition = *posCtrlTaskArg->currentPosition;
  4516. 8002442: eeb0 8a47 vmov.f32 s16, s14
  4517. movementPhase = startPhase;
  4518. 8002446: 2701 movs r7, #1
  4519. sign = posDiff > 0 ? 1 : -1;
  4520. 8002448: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff
  4521. timeLeftMS = 0;
  4522. 800244c: 4682 mov sl, r0
  4523. 800244e: e7b2 b.n 80023b6 <PositionControlTask+0x82>
  4524. if (((*posCtrlTaskArg->motorStatus != 0) && (movementPhase != idlePhase)) || (movementPhase == startPhase) ) {
  4525. 8002450: 2f01 cmp r7, #1
  4526. 8002452: d0c6 beq.n 80023e2 <PositionControlTask+0xae>
  4527. movementPhase = idlePhase;
  4528. 8002454: 2700 movs r7, #0
  4529. 8002456: e7f0 b.n 800243a <PositionControlTask+0x106>
  4530. moveCmdTimeoutCounter = 0;
  4531. 8002458: f04f 0800 mov.w r8, #0
  4532. switch (movementPhase) {
  4533. 800245c: 1e79 subs r1, r7, #1
  4534. 800245e: 2904 cmp r1, #4
  4535. 8002460: d842 bhi.n 80024e8 <PositionControlTask+0x1b4>
  4536. 8002462: e8df f001 tbb [pc, r1]
  4537. 8002466: 6e95 .short 0x6e95
  4538. 8002468: 445e .short 0x445e
  4539. 800246a: 2e .byte 0x2e
  4540. 800246b: 00 .byte 0x00
  4541. if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) ||
  4542. 800246c: 2b01 cmp r3, #1
  4543. 800246e: d1c1 bne.n 80023f4 <PositionControlTask+0xc0>
  4544. motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0,
  4545. 8002470: 2700 movs r7, #0
  4546. timeLeftMS += PositionControlTaskTimeOut;
  4547. 8002472: f10a 0a64 add.w sl, sl, #100 @ 0x64
  4548. motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0,
  4549. 8002476: e9cd 3203 strd r3, r2, [sp, #12]
  4550. 800247a: e9cd 7701 strd r7, r7, [sp, #4]
  4551. 800247e: 68eb ldr r3, [r5, #12]
  4552. 8002480: 9300 str r3, [sp, #0]
  4553. 8002482: 7a6b ldrb r3, [r5, #9]
  4554. 8002484: 7a2a ldrb r2, [r5, #8]
  4555. 8002486: e9d5 0100 ldrd r0, r1, [r5]
  4556. 800248a: f7ff fde5 bl 8002058 <MotorControl>
  4557. *posCtrlTaskArg->motorStatus = motorStatus;
  4558. 800248e: 6aab ldr r3, [r5, #40] @ 0x28
  4559. 8002490: 7018 strb r0, [r3, #0]
  4560. if (prevPosition == *posCtrlTaskArg->currentPosition) {
  4561. 8002492: 6a2b ldr r3, [r5, #32]
  4562. 8002494: edd3 7a00 vldr s15, [r3]
  4563. 8002498: eeb4 9a67 vcmp.f32 s18, s15
  4564. 800249c: eef1 fa10 vmrs APSR_nzcv, fpscr
  4565. 80024a0: f040 8099 bne.w 80025d6 <PositionControlTask+0x2a2>
  4566. moveCmdTimeoutCounter += PositionControlTaskTimeOut;
  4567. 80024a4: f108 0864 add.w r8, r8, #100 @ 0x64
  4568. if (moveCmdTimeoutCounter > NO_MOVE_TIMEOUT_MS) {
  4569. 80024a8: f241 3388 movw r3, #5000 @ 0x1388
  4570. 80024ac: 4598 cmp r8, r3
  4571. 80024ae: f340 8096 ble.w 80025de <PositionControlTask+0x2aa>
  4572. 80024b2: e9d5 1c05 ldrd r1, ip, [r5, #20]
  4573. 80024b6: e7ae b.n 8002416 <PositionControlTask+0xe2>
  4574. ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) {
  4575. 80024b8: 69e8 ldr r0, [r5, #28]
  4576. 80024ba: 7800 ldrb r0, [r0, #0]
  4577. 80024bc: 2801 cmp r0, #1
  4578. 80024be: d199 bne.n 80023f4 <PositionControlTask+0xc0>
  4579. 80024c0: e7d6 b.n 8002470 <PositionControlTask+0x13c>
  4580. float posDiff = sign > 0 ? posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition : *posCtrlTaskArg->currentPosition - posCtrlData.positionSettingValue;
  4581. 80024c2: edd4 7a00 vldr s15, [r4]
  4582. 80024c6: f1bb 0f01 cmp.w fp, #1
  4583. 80024ca: bf0c ite eq
  4584. 80024cc: ee77 7ae8 vsubeq.f32 s15, s15, s17
  4585. 80024d0: ee78 7ae7 vsubne.f32 s15, s17, s15
  4586. if ((posDiff <= 0) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) {
  4587. 80024d4: eef5 7ac0 vcmpe.f32 s15, #0.0
  4588. 80024d8: eef1 fa10 vmrs APSR_nzcv, fpscr
  4589. 80024dc: f240 8082 bls.w 80025e4 <PositionControlTask+0x2b0>
  4590. 80024e0: f241 3187 movw r1, #4999 @ 0x1387
  4591. 80024e4: 458a cmp sl, r1
  4592. 80024e6: dc7d bgt.n 80025e4 <PositionControlTask+0x2b0>
  4593. 80024e8: eeb0 9a68 vmov.f32 s18, s17
  4594. 80024ec: e7a5 b.n 800243a <PositionControlTask+0x106>
  4595. motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle,
  4596. 80024ee: e9cd 3203 strd r3, r2, [sp, #12]
  4597. 80024f2: 68ea ldr r2, [r5, #12]
  4598. 80024f4: 233c movs r3, #60 @ 0x3c
  4599. break;
  4600. 80024f6: eeb0 9a68 vmov.f32 s18, s17
  4601. timeLeftMS = 0;
  4602. 80024fa: f04f 0a00 mov.w sl, #0
  4603. motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle,
  4604. 80024fe: 9200 str r2, [sp, #0]
  4605. 8002500: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
  4606. pwmValue = MOTOR_START_STOP_PWM_VALUE;
  4607. 8002504: 9307 str r3, [sp, #28]
  4608. movementPhase = stopPhase;
  4609. 8002506: 2705 movs r7, #5
  4610. motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle,
  4611. 8002508: 9202 str r2, [sp, #8]
  4612. 800250a: fb03 f20b mul.w r2, r3, fp
  4613. 800250e: 9201 str r2, [sp, #4]
  4614. 8002510: 7a6b ldrb r3, [r5, #9]
  4615. 8002512: 7a2a ldrb r2, [r5, #8]
  4616. 8002514: e9d5 0100 ldrd r0, r1, [r5]
  4617. 8002518: f7ff fd9e bl 8002058 <MotorControl>
  4618. *posCtrlTaskArg->motorStatus = motorStatus;
  4619. 800251c: 6aab ldr r3, [r5, #40] @ 0x28
  4620. 800251e: 7018 strb r0, [r3, #0]
  4621. break;
  4622. 8002520: e78b b.n 800243a <PositionControlTask+0x106>
  4623. if (abs (*posCtrlTaskArg->currentPosition - *posCtrlTaskArg->positionSetting) <= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) {
  4624. 8002522: 6a6b ldr r3, [r5, #36] @ 0x24
  4625. 8002524: eeb0 9a68 vmov.f32 s18, s17
  4626. 8002528: edd3 7a00 vldr s15, [r3]
  4627. 800252c: ee78 8ae7 vsub.f32 s17, s17, s15
  4628. 8002530: eefd 8ae8 vcvt.s32.f32 s17, s17
  4629. 8002534: ee18 3a90 vmov r3, s17
  4630. 8002538: 3305 adds r3, #5
  4631. 800253a: 2b0b cmp r3, #11
  4632. 800253c: bf38 it cc
  4633. 800253e: 2704 movcc r7, #4
  4634. 8002540: e77b b.n 800243a <PositionControlTask+0x106>
  4635. if ((abs (*posCtrlTaskArg->currentPosition - startPosition) >= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) {
  4636. 8002542: ee78 7ac8 vsub.f32 s15, s17, s16
  4637. 8002546: eefd 7ae7 vcvt.s32.f32 s15, s15
  4638. 800254a: ee17 1a90 vmov r1, s15
  4639. 800254e: 2900 cmp r1, #0
  4640. 8002550: bfb8 it lt
  4641. 8002552: 4249 neglt r1, r1
  4642. 8002554: 2904 cmp r1, #4
  4643. 8002556: dc03 bgt.n 8002560 <PositionControlTask+0x22c>
  4644. 8002558: f241 3187 movw r1, #4999 @ 0x1387
  4645. 800255c: 458a cmp sl, r1
  4646. 800255e: ddc3 ble.n 80024e8 <PositionControlTask+0x1b4>
  4647. *posCtrlTaskArg->motorStatus = motorStatus;
  4648. 8002560: eeb0 9a68 vmov.f32 s18, s17
  4649. movementPhase = movePhase;
  4650. 8002564: 2703 movs r7, #3
  4651. motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle,
  4652. 8002566: e9cd 3203 strd r3, r2, [sp, #12]
  4653. 800256a: 68ea ldr r2, [r5, #12]
  4654. 800256c: 2364 movs r3, #100 @ 0x64
  4655. 800256e: 9200 str r2, [sp, #0]
  4656. 8002570: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
  4657. pwmValue = MOTOR_HIGH_SPEED_PWM_VALUE;
  4658. 8002574: 9307 str r3, [sp, #28]
  4659. motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle,
  4660. 8002576: 9202 str r2, [sp, #8]
  4661. 8002578: fb03 f20b mul.w r2, r3, fp
  4662. 800257c: 9201 str r2, [sp, #4]
  4663. 800257e: 7a6b ldrb r3, [r5, #9]
  4664. 8002580: 7a2a ldrb r2, [r5, #8]
  4665. 8002582: e9d5 0100 ldrd r0, r1, [r5]
  4666. 8002586: f7ff fd67 bl 8002058 <MotorControl>
  4667. *posCtrlTaskArg->motorStatus = motorStatus;
  4668. 800258a: 6aab ldr r3, [r5, #40] @ 0x28
  4669. 800258c: 7018 strb r0, [r3, #0]
  4670. movementPhase = movePhase;
  4671. 800258e: e754 b.n 800243a <PositionControlTask+0x106>
  4672. motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle,
  4673. 8002590: e9cd 3203 strd r3, r2, [sp, #12]
  4674. 8002594: 68eb ldr r3, [r5, #12]
  4675. 8002596: eeb0 9a68 vmov.f32 s18, s17
  4676. 800259a: 9300 str r3, [sp, #0]
  4677. 800259c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
  4678. 80025a0: 9302 str r3, [sp, #8]
  4679. 80025a2: 9b07 ldr r3, [sp, #28]
  4680. 80025a4: fb0b f303 mul.w r3, fp, r3
  4681. 80025a8: 9301 str r3, [sp, #4]
  4682. 80025aa: 7a6b ldrb r3, [r5, #9]
  4683. 80025ac: 7a2a ldrb r2, [r5, #8]
  4684. 80025ae: e9d5 0100 ldrd r0, r1, [r5]
  4685. 80025b2: f7ff fd51 bl 8002058 <MotorControl>
  4686. *posCtrlTaskArg->motorStatus = motorStatus;
  4687. 80025b6: 6aab ldr r3, [r5, #40] @ 0x28
  4688. if (motorStatus == 1) {
  4689. 80025b8: 2801 cmp r0, #1
  4690. *posCtrlTaskArg->motorStatus = motorStatus;
  4691. 80025ba: 7018 strb r0, [r3, #0]
  4692. if (motorStatus == 1) {
  4693. 80025bc: f47f af4a bne.w 8002454 <PositionControlTask+0x120>
  4694. *posCtrlTaskArg->motorPeakCurrent = 0.0;
  4695. 80025c0: 6aeb ldr r3, [r5, #44] @ 0x2c
  4696. 80025c2: 2200 movs r2, #0
  4697. moveCmdTimeoutCounter = 0;
  4698. 80025c4: f04f 0800 mov.w r8, #0
  4699. movementPhase = speedUpPhase;
  4700. 80025c8: 2702 movs r7, #2
  4701. *posCtrlTaskArg->motorPeakCurrent = 0.0;
  4702. 80025ca: 601a str r2, [r3, #0]
  4703. timeLeftMS = 0;
  4704. 80025cc: 46c2 mov sl, r8
  4705. 80025ce: e734 b.n 800243a <PositionControlTask+0x106>
  4706. 80025d0: eef0 8a49 vmov.f32 s17, s18
  4707. 80025d4: e742 b.n 800245c <PositionControlTask+0x128>
  4708. if (prevPosition == *posCtrlTaskArg->currentPosition) {
  4709. 80025d6: eeb0 9a67 vmov.f32 s18, s15
  4710. moveCmdTimeoutCounter = 0;
  4711. 80025da: 46b8 mov r8, r7
  4712. 80025dc: e72d b.n 800243a <PositionControlTask+0x106>
  4713. if (moveCmdTimeoutCounter > NO_MOVE_TIMEOUT_MS) {
  4714. 80025de: eeb0 9a67 vmov.f32 s18, s15
  4715. 80025e2: e72a b.n 800243a <PositionControlTask+0x106>
  4716. *posCtrlTaskArg->motorStatus = motorStatus;
  4717. 80025e4: eeb0 9a68 vmov.f32 s18, s17
  4718. motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle,
  4719. 80025e8: e9cd 3203 strd r3, r2, [sp, #12]
  4720. 80025ec: e718 b.n 8002420 <PositionControlTask+0xec>
  4721. 80025ee: bf00 nop
  4722. 80025f0: 00000000 .word 0x00000000
  4723. 80025f4: 24000980 .word 0x24000980
  4724. 80025f8: 24000a00 .word 0x24000a00
  4725. 080025fc <PositionControlTaskInit>:
  4726. void PositionControlTaskInit (void) {
  4727. 80025fc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  4728. 8002600: b08a sub sp, #40 @ 0x28
  4729. osThreadAttr_t osThreadAttrPositionControlTask = { 0 };
  4730. 8002602: 2224 movs r2, #36 @ 0x24
  4731. 8002604: 2100 movs r1, #0
  4732. positionXControlTaskInitArg.channel1 = TIM_CHANNEL_1;
  4733. 8002606: 4c30 ldr r4, [pc, #192] @ (80026c8 <PositionControlTaskInit+0xcc>)
  4734. osThreadAttr_t osThreadAttrPositionControlTask = { 0 };
  4735. 8002608: a801 add r0, sp, #4
  4736. positionXControlTaskInitArg.htim = &htim3;
  4737. 800260a: f8df 80e8 ldr.w r8, [pc, #232] @ 80026f4 <PositionControlTaskInit+0xf8>
  4738. osThreadAttr_t osThreadAttrPositionControlTask = { 0 };
  4739. 800260e: f00d fa7b bl 800fb08 <memset>
  4740. positionXControlTaskInitArg.motorTimerHandle = motorXTimerHandle;
  4741. 8002612: 4a2e ldr r2, [pc, #184] @ (80026cc <PositionControlTaskInit+0xd0>)
  4742. osThreadAttrPositionControlTask.stack_size = configMINIMAL_STACK_SIZE * 2;
  4743. 8002614: f44f 6380 mov.w r3, #1024 @ 0x400
  4744. positionXControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC;
  4745. 8002618: 4f2d ldr r7, [pc, #180] @ (80026d0 <PositionControlTaskInit+0xd4>)
  4746. positionXControlTaskInitArg.motorTimerHandle = motorXTimerHandle;
  4747. 800261a: 6812 ldr r2, [r2, #0]
  4748. positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL);
  4749. 800261c: 2104 movs r1, #4
  4750. osThreadAttrPositionControlTask.stack_size = configMINIMAL_STACK_SIZE * 2;
  4751. 800261e: 9306 str r3, [sp, #24]
  4752. positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL);
  4753. 8002620: 2010 movs r0, #16
  4754. positionXControlTaskInitArg.channel1 = TIM_CHANNEL_1;
  4755. 8002622: 8123 strh r3, [r4, #8]
  4756. osThreadAttrPositionControlTask.priority = (osPriority_t)osPriorityNormal;
  4757. 8002624: 2318 movs r3, #24
  4758. positionXControlTaskInitArg.motorTimerHandle = motorXTimerHandle;
  4759. 8002626: 60e2 str r2, [r4, #12]
  4760. positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL);
  4761. 8002628: 2200 movs r2, #0
  4762. positionXControlTaskInitArg.htim = &htim3;
  4763. 800262a: f8c4 8000 str.w r8, [r4]
  4764. positionXControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC;
  4765. 800262e: 6067 str r7, [r4, #4]
  4766. osThreadAttrPositionControlTask.priority = (osPriority_t)osPriorityNormal;
  4767. 8002630: 9307 str r3, [sp, #28]
  4768. positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL);
  4769. 8002632: f009 fc2d bl 800be90 <osMessageQueueNew>
  4770. positionYControlTaskInitArg.motorTimerHandle = motorYTimerHandle;
  4771. 8002636: 4b27 ldr r3, [pc, #156] @ (80026d4 <PositionControlTaskInit+0xd8>)
  4772. positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL);
  4773. 8002638: 2200 movs r2, #0
  4774. positionYControlTaskInitArg.channel1 = TIM_CHANNEL_3;
  4775. 800263a: 4e27 ldr r6, [pc, #156] @ (80026d8 <PositionControlTaskInit+0xdc>)
  4776. positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL);
  4777. 800263c: 2104 movs r1, #4
  4778. positionXControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitXSwitchCenter);
  4779. 800263e: 4d27 ldr r5, [pc, #156] @ (80026dc <PositionControlTaskInit+0xe0>)
  4780. positionYControlTaskInitArg.motorTimerHandle = motorYTimerHandle;
  4781. 8002640: 681b ldr r3, [r3, #0]
  4782. positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL);
  4783. 8002642: 6120 str r0, [r4, #16]
  4784. positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL);
  4785. 8002644: 2010 movs r0, #16
  4786. positionYControlTaskInitArg.motorTimerHandle = motorYTimerHandle;
  4787. 8002646: 60f3 str r3, [r6, #12]
  4788. positionXControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitXSwitchUp);
  4789. 8002648: 1eab subs r3, r5, #2
  4790. positionXControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitXSwitchCenter);
  4791. 800264a: 61e5 str r5, [r4, #28]
  4792. positionXControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitXSwitchUp);
  4793. 800264c: 6163 str r3, [r4, #20]
  4794. positionXControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitXSwitchDown);
  4795. 800264e: 1e6b subs r3, r5, #1
  4796. 8002650: 61a3 str r3, [r4, #24]
  4797. positionXControlTaskInitArg.currentPosition = &(sensorsInfo.currentXPosition);
  4798. 8002652: 1dab adds r3, r5, #6
  4799. 8002654: 6223 str r3, [r4, #32]
  4800. positionXControlTaskInitArg.motorStatus = &(sensorsInfo.motorXStatus);
  4801. 8002656: f1a5 0316 sub.w r3, r5, #22
  4802. 800265a: 62a3 str r3, [r4, #40] @ 0x28
  4803. positionXControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorXPeakCurrent);
  4804. 800265c: f1a5 030a sub.w r3, r5, #10
  4805. 8002660: 62e3 str r3, [r4, #44] @ 0x2c
  4806. positionXControlTaskInitArg.positionSetting = &positionXSetting;
  4807. 8002662: 4b1f ldr r3, [pc, #124] @ (80026e0 <PositionControlTaskInit+0xe4>)
  4808. 8002664: 6263 str r3, [r4, #36] @ 0x24
  4809. positionXControlTaskInitArg.axe = 'X';
  4810. 8002666: 2358 movs r3, #88 @ 0x58
  4811. 8002668: f884 3030 strb.w r3, [r4, #48] @ 0x30
  4812. positionYControlTaskInitArg.channel1 = TIM_CHANNEL_3;
  4813. 800266c: f640 4308 movw r3, #3080 @ 0xc08
  4814. positionYControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC;
  4815. 8002670: e9c6 8700 strd r8, r7, [r6]
  4816. positionYControlTaskInitArg.channel1 = TIM_CHANNEL_3;
  4817. 8002674: 8133 strh r3, [r6, #8]
  4818. positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL);
  4819. 8002676: f009 fc0b bl 800be90 <osMessageQueueNew>
  4820. positionYControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitYSwitchCenter);
  4821. 800267a: 1ceb adds r3, r5, #3
  4822. positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask);
  4823. 800267c: 4f19 ldr r7, [pc, #100] @ (80026e4 <PositionControlTaskInit+0xe8>)
  4824. 800267e: 4621 mov r1, r4
  4825. 8002680: aa01 add r2, sp, #4
  4826. positionYControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitYSwitchCenter);
  4827. 8002682: 61f3 str r3, [r6, #28]
  4828. positionYControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitYSwitchUp);
  4829. 8002684: 1c6b adds r3, r5, #1
  4830. positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL);
  4831. 8002686: 6130 str r0, [r6, #16]
  4832. positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask);
  4833. 8002688: 4638 mov r0, r7
  4834. positionYControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitYSwitchUp);
  4835. 800268a: 6173 str r3, [r6, #20]
  4836. positionYControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitYSwitchDown);
  4837. 800268c: 1cab adds r3, r5, #2
  4838. 800268e: 61b3 str r3, [r6, #24]
  4839. positionYControlTaskInitArg.currentPosition = &(sensorsInfo.currentYPosition);
  4840. 8002690: f105 030a add.w r3, r5, #10
  4841. 8002694: 6233 str r3, [r6, #32]
  4842. positionYControlTaskInitArg.motorStatus = &(sensorsInfo.motorYStatus);
  4843. 8002696: f1a5 0315 sub.w r3, r5, #21
  4844. positionYControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorYPeakCurrent);
  4845. 800269a: 3d06 subs r5, #6
  4846. positionYControlTaskInitArg.motorStatus = &(sensorsInfo.motorYStatus);
  4847. 800269c: 62b3 str r3, [r6, #40] @ 0x28
  4848. positionXControlTaskInitArg.positionSetting = &positionYSetting;
  4849. 800269e: 4b12 ldr r3, [pc, #72] @ (80026e8 <PositionControlTaskInit+0xec>)
  4850. positionYControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorYPeakCurrent);
  4851. 80026a0: 62f5 str r5, [r6, #44] @ 0x2c
  4852. positionXControlTaskInitArg.positionSetting = &positionYSetting;
  4853. 80026a2: 6263 str r3, [r4, #36] @ 0x24
  4854. positionYControlTaskInitArg.axe = 'Y';
  4855. 80026a4: 2359 movs r3, #89 @ 0x59
  4856. 80026a6: f886 3030 strb.w r3, [r6, #48] @ 0x30
  4857. positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask);
  4858. 80026aa: f009 fa9f bl 800bbec <osThreadNew>
  4859. 80026ae: 4b0f ldr r3, [pc, #60] @ (80026ec <PositionControlTaskInit+0xf0>)
  4860. 80026b0: 4604 mov r4, r0
  4861. positionYControlTaskHandle = osThreadNew (PositionControlTask, &positionYControlTaskInitArg, &osThreadAttrPositionControlTask);
  4862. 80026b2: aa01 add r2, sp, #4
  4863. 80026b4: 4631 mov r1, r6
  4864. 80026b6: 4638 mov r0, r7
  4865. positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask);
  4866. 80026b8: 601c str r4, [r3, #0]
  4867. positionYControlTaskHandle = osThreadNew (PositionControlTask, &positionYControlTaskInitArg, &osThreadAttrPositionControlTask);
  4868. 80026ba: f009 fa97 bl 800bbec <osThreadNew>
  4869. 80026be: 4b0c ldr r3, [pc, #48] @ (80026f0 <PositionControlTaskInit+0xf4>)
  4870. 80026c0: 6018 str r0, [r3, #0]
  4871. }
  4872. 80026c2: b00a add sp, #40 @ 0x28
  4873. 80026c4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  4874. 80026c8: 24000a00 .word 0x24000a00
  4875. 80026cc: 24000324 .word 0x24000324
  4876. 80026d0: 24000290 .word 0x24000290
  4877. 80026d4: 240002f4 .word 0x240002f4
  4878. 80026d8: 240009c0 .word 0x240009c0
  4879. 80026dc: 2400092a .word 0x2400092a
  4880. 80026e0: 24000a60 .word 0x24000a60
  4881. 80026e4: 08002335 .word 0x08002335
  4882. 80026e8: 24000a40 .word 0x24000a40
  4883. 80026ec: 24000a38 .word 0x24000a38
  4884. 80026f0: 24000a34 .word 0x24000a34
  4885. 80026f4: 24000500 .word 0x24000500
  4886. 080026f8 <WriteDataToBuffer>:
  4887. buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF);
  4888. }
  4889. *buffPos = newBuffPos;
  4890. }
  4891. void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) {
  4892. 80026f8: b570 push {r4, r5, r6, lr}
  4893. uint32_t* uDataPtr = data;
  4894. uint32_t uData = *uDataPtr;
  4895. 80026fa: 6816 ldr r6, [r2, #0]
  4896. uint8_t i = 0;
  4897. uint8_t newBuffPos = *buffPos;
  4898. 80026fc: 780a ldrb r2, [r1, #0]
  4899. for (i = 0; i < dataSize; i++) {
  4900. 80026fe: b18b cbz r3, 8002724 <WriteDataToBuffer+0x2c>
  4901. 8002700: 4413 add r3, r2
  4902. 8002702: f04f 0c00 mov.w ip, #0
  4903. 8002706: fa5f fe83 uxtb.w lr, r3
  4904. buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF);
  4905. 800270a: 1c55 adds r5, r2, #1
  4906. 800270c: 4614 mov r4, r2
  4907. 800270e: fa26 f30c lsr.w r3, r6, ip
  4908. 8002712: f10c 0c08 add.w ip, ip, #8
  4909. 8002716: b2ea uxtb r2, r5
  4910. 8002718: 5503 strb r3, [r0, r4]
  4911. for (i = 0; i < dataSize; i++) {
  4912. 800271a: 4572 cmp r2, lr
  4913. 800271c: d1f5 bne.n 800270a <WriteDataToBuffer+0x12>
  4914. }
  4915. *buffPos = newBuffPos;
  4916. 800271e: f8a1 e000 strh.w lr, [r1]
  4917. }
  4918. 8002722: bd70 pop {r4, r5, r6, pc}
  4919. uint8_t newBuffPos = *buffPos;
  4920. 8002724: 4696 mov lr, r2
  4921. *buffPos = newBuffPos;
  4922. 8002726: f8a1 e000 strh.w lr, [r1]
  4923. }
  4924. 800272a: bd70 pop {r4, r5, r6, pc}
  4925. 0800272c <ReadFloatFromBuffer>:
  4926. void ReadFloatFromBuffer(uint8_t* buff, uint16_t* buffPos, float* data)
  4927. {
  4928. uint32_t* word = (uint32_t *)data;
  4929. *word = CONVERT_BYTES_TO_WORD(&buff[*buffPos]);
  4930. 800272c: 880b ldrh r3, [r1, #0]
  4931. 800272e: eb00 0c03 add.w ip, r0, r3
  4932. {
  4933. 8002732: b510 push {r4, lr}
  4934. *word = CONVERT_BYTES_TO_WORD(&buff[*buffPos]);
  4935. 8002734: f810 e003 ldrb.w lr, [r0, r3]
  4936. *buffPos += sizeof(float);
  4937. 8002738: 1d18 adds r0, r3, #4
  4938. *word = CONVERT_BYTES_TO_WORD(&buff[*buffPos]);
  4939. 800273a: f89c 3002 ldrb.w r3, [ip, #2]
  4940. 800273e: f89c 4003 ldrb.w r4, [ip, #3]
  4941. 8002742: 041b lsls r3, r3, #16
  4942. 8002744: f89c c001 ldrb.w ip, [ip, #1]
  4943. 8002748: ea43 6304 orr.w r3, r3, r4, lsl #24
  4944. 800274c: ea43 030e orr.w r3, r3, lr
  4945. 8002750: ea43 230c orr.w r3, r3, ip, lsl #8
  4946. 8002754: 6013 str r3, [r2, #0]
  4947. *buffPos += sizeof(float);
  4948. 8002756: 8008 strh r0, [r1, #0]
  4949. }
  4950. 8002758: bd10 pop {r4, pc}
  4951. 800275a: bf00 nop
  4952. 0800275c <ReadWordFromBufer>:
  4953. {
  4954. *data = CONVERT_BYTES_TO_SHORT_WORD(&buff[*buffPos]);
  4955. *buffPos += sizeof(uint16_t);
  4956. }
  4957. void ReadWordFromBufer(uint8_t* buff, uint16_t* buffPos, uint32_t* data)
  4958. 800275c: 880b ldrh r3, [r1, #0]
  4959. 800275e: eb00 0c03 add.w ip, r0, r3
  4960. 8002762: b510 push {r4, lr}
  4961. 8002764: f810 e003 ldrb.w lr, [r0, r3]
  4962. 8002768: 1d18 adds r0, r3, #4
  4963. 800276a: f89c 3002 ldrb.w r3, [ip, #2]
  4964. 800276e: f89c 4003 ldrb.w r4, [ip, #3]
  4965. 8002772: 041b lsls r3, r3, #16
  4966. 8002774: f89c c001 ldrb.w ip, [ip, #1]
  4967. 8002778: ea43 6304 orr.w r3, r3, r4, lsl #24
  4968. 800277c: ea43 030e orr.w r3, r3, lr
  4969. 8002780: ea43 230c orr.w r3, r3, ip, lsl #8
  4970. 8002784: 6013 str r3, [r2, #0]
  4971. 8002786: 8008 strh r0, [r1, #0]
  4972. 8002788: bd10 pop {r4, pc}
  4973. 800278a: bf00 nop
  4974. 0800278c <PrepareRespFrame>:
  4975. txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc);
  4976. return txBufferPos;
  4977. }
  4978. uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) {
  4979. 800278c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  4980. 8002790: f8bd 501c ldrh.w r5, [sp, #28]
  4981. 8002794: 460e mov r6, r1
  4982. 8002796: 4690 mov r8, r2
  4983. uint16_t crc = 0;
  4984. uint16_t txBufferPos = 0;
  4985. uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response
  4986. memset (txBuffer, 0x00, dataLength);
  4987. 8002798: 2100 movs r1, #0
  4988. 800279a: 462a mov r2, r5
  4989. uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) {
  4990. 800279c: 4604 mov r4, r0
  4991. 800279e: 461f mov r7, r3
  4992. memset (txBuffer, 0x00, dataLength);
  4993. 80027a0: f00d f9b2 bl 800fb08 <memset>
  4994. txBuffer[txBufferPos++] = FRAME_INDICATOR;
  4995. txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId);
  4996. txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId);
  4997. txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd);
  4998. txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd);
  4999. 80027a4: 2380 movs r3, #128 @ 0x80
  5000. txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId);
  5001. 80027a6: 7066 strb r6, [r4, #1]
  5002. txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId);
  5003. 80027a8: 0a36 lsrs r6, r6, #8
  5004. txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd);
  5005. 80027aa: f884 8003 strb.w r8, [r4, #3]
  5006. txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd);
  5007. 80027ae: 7123 strb r3, [r4, #4]
  5008. txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength);
  5009. txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength);
  5010. 80027b0: 0a2b lsrs r3, r5, #8
  5011. txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId);
  5012. 80027b2: 70a6 strb r6, [r4, #2]
  5013. txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength);
  5014. 80027b4: 71a3 strb r3, [r4, #6]
  5015. txBuffer[txBufferPos++] = FRAME_INDICATOR;
  5016. 80027b6: 23aa movs r3, #170 @ 0xaa
  5017. txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength);
  5018. 80027b8: 7165 strb r5, [r4, #5]
  5019. txBuffer[txBufferPos++] = (uint8_t)respStatus;
  5020. 80027ba: 71e7 strb r7, [r4, #7]
  5021. txBuffer[txBufferPos++] = FRAME_INDICATOR;
  5022. 80027bc: 7023 strb r3, [r4, #0]
  5023. if (dataLength > 0) {
  5024. 80027be: b97d cbnz r5, 80027e0 <PrepareRespFrame+0x54>
  5025. 80027c0: 250a movs r5, #10
  5026. 80027c2: 2709 movs r7, #9
  5027. 80027c4: 2608 movs r6, #8
  5028. memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength);
  5029. txBufferPos += dataLength;
  5030. }
  5031. crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos);
  5032. 80027c6: 4632 mov r2, r6
  5033. 80027c8: 4621 mov r1, r4
  5034. 80027ca: 480d ldr r0, [pc, #52] @ (8002800 <PrepareRespFrame+0x74>)
  5035. 80027cc: f002 fcc4 bl 8005158 <HAL_CRC_Calculate>
  5036. 80027d0: 4603 mov r3, r0
  5037. txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc);
  5038. txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc);
  5039. return txBufferPos;
  5040. }
  5041. 80027d2: 4628 mov r0, r5
  5042. txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc);
  5043. 80027d4: 55a3 strb r3, [r4, r6]
  5044. txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc);
  5045. 80027d6: f3c3 2307 ubfx r3, r3, #8, #8
  5046. 80027da: 55e3 strb r3, [r4, r7]
  5047. }
  5048. 80027dc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  5049. memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength);
  5050. 80027e0: 462a mov r2, r5
  5051. txBufferPos += dataLength;
  5052. 80027e2: f105 0608 add.w r6, r5, #8
  5053. txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc);
  5054. 80027e6: f105 0709 add.w r7, r5, #9
  5055. txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc);
  5056. 80027ea: 350a adds r5, #10
  5057. memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength);
  5058. 80027ec: 9906 ldr r1, [sp, #24]
  5059. 80027ee: f104 0008 add.w r0, r4, #8
  5060. crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos);
  5061. 80027f2: b2b6 uxth r6, r6
  5062. txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc);
  5063. 80027f4: b2bf uxth r7, r7
  5064. 80027f6: b2ad uxth r5, r5
  5065. memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength);
  5066. 80027f8: f00d fa5b bl 800fcb2 <memcpy>
  5067. txBufferPos += dataLength;
  5068. 80027fc: e7e3 b.n 80027c6 <PrepareRespFrame+0x3a>
  5069. 80027fe: bf00 nop
  5070. 8002800: 240005d0 .word 0x240005d0
  5071. 08002804 <HAL_MspInit>:
  5072. void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
  5073. /**
  5074. * Initializes the Global MSP.
  5075. */
  5076. void HAL_MspInit(void)
  5077. {
  5078. 8002804: b530 push {r4, r5, lr}
  5079. /* USER CODE END MspInit 0 */
  5080. PWREx_AVDTypeDef sConfigAVD = {0};
  5081. PWR_PVDTypeDef sConfigPVD = {0};
  5082. __HAL_RCC_SYSCFG_CLK_ENABLE();
  5083. 8002806: 4c23 ldr r4, [pc, #140] @ (8002894 <HAL_MspInit+0x90>)
  5084. {
  5085. 8002808: b087 sub sp, #28
  5086. PWREx_AVDTypeDef sConfigAVD = {0};
  5087. 800280a: 2500 movs r5, #0
  5088. /* System interrupt init*/
  5089. /* PendSV_IRQn interrupt configuration */
  5090. HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
  5091. 800280c: 210f movs r1, #15
  5092. 800280e: f06f 0001 mvn.w r0, #1
  5093. PWREx_AVDTypeDef sConfigAVD = {0};
  5094. 8002812: 9502 str r5, [sp, #8]
  5095. HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
  5096. 8002814: 462a mov r2, r5
  5097. PWR_PVDTypeDef sConfigPVD = {0};
  5098. 8002816: 9505 str r5, [sp, #20]
  5099. PWREx_AVDTypeDef sConfigAVD = {0};
  5100. 8002818: e9cd 5503 strd r5, r5, [sp, #12]
  5101. __HAL_RCC_SYSCFG_CLK_ENABLE();
  5102. 800281c: f8d4 30f4 ldr.w r3, [r4, #244] @ 0xf4
  5103. 8002820: f043 0302 orr.w r3, r3, #2
  5104. 8002824: f8c4 30f4 str.w r3, [r4, #244] @ 0xf4
  5105. 8002828: f8d4 30f4 ldr.w r3, [r4, #244] @ 0xf4
  5106. 800282c: f003 0302 and.w r3, r3, #2
  5107. 8002830: 9300 str r3, [sp, #0]
  5108. 8002832: 9b00 ldr r3, [sp, #0]
  5109. HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
  5110. 8002834: f002 fb80 bl 8004f38 <HAL_NVIC_SetPriority>
  5111. /* Peripheral interrupt init */
  5112. /* RCC_IRQn interrupt configuration */
  5113. HAL_NVIC_SetPriority(RCC_IRQn, 5, 0);
  5114. 8002838: 2105 movs r1, #5
  5115. 800283a: 462a mov r2, r5
  5116. 800283c: 4608 mov r0, r1
  5117. 800283e: f002 fb7b bl 8004f38 <HAL_NVIC_SetPriority>
  5118. HAL_NVIC_EnableIRQ(RCC_IRQn);
  5119. 8002842: 2005 movs r0, #5
  5120. 8002844: f002 fbb4 bl 8004fb0 <HAL_NVIC_EnableIRQ>
  5121. /** AVD Configuration
  5122. */
  5123. sConfigAVD.AVDLevel = PWR_AVDLEVEL_3;
  5124. 8002848: f44f 22c0 mov.w r2, #393216 @ 0x60000
  5125. 800284c: 2300 movs r3, #0
  5126. sConfigAVD.Mode = PWR_AVD_MODE_NORMAL;
  5127. HAL_PWREx_ConfigAVD(&sConfigAVD);
  5128. 800284e: a802 add r0, sp, #8
  5129. sConfigAVD.AVDLevel = PWR_AVDLEVEL_3;
  5130. 8002850: e9cd 2302 strd r2, r3, [sp, #8]
  5131. HAL_PWREx_ConfigAVD(&sConfigAVD);
  5132. 8002854: f004 fd7a bl 800734c <HAL_PWREx_ConfigAVD>
  5133. /** Enable the AVD Output
  5134. */
  5135. HAL_PWREx_EnableAVD();
  5136. 8002858: f004 fdbe bl 80073d8 <HAL_PWREx_EnableAVD>
  5137. /** PVD Configuration
  5138. */
  5139. sConfigPVD.PVDLevel = PWR_PVDLEVEL_6;
  5140. 800285c: 22c0 movs r2, #192 @ 0xc0
  5141. 800285e: 2300 movs r3, #0
  5142. sConfigPVD.Mode = PWR_PVD_MODE_NORMAL;
  5143. HAL_PWR_ConfigPVD(&sConfigPVD);
  5144. 8002860: a804 add r0, sp, #16
  5145. sConfigPVD.PVDLevel = PWR_PVDLEVEL_6;
  5146. 8002862: e9cd 2304 strd r2, r3, [sp, #16]
  5147. HAL_PWR_ConfigPVD(&sConfigPVD);
  5148. 8002866: f004 fcfb bl 8007260 <HAL_PWR_ConfigPVD>
  5149. /** Enable the PVD Output
  5150. */
  5151. HAL_PWR_EnablePVD();
  5152. 800286a: f004 fd43 bl 80072f4 <HAL_PWR_EnablePVD>
  5153. /** Enable the VREF clock
  5154. */
  5155. __HAL_RCC_VREF_CLK_ENABLE();
  5156. 800286e: f8d4 30f4 ldr.w r3, [r4, #244] @ 0xf4
  5157. 8002872: f443 4300 orr.w r3, r3, #32768 @ 0x8000
  5158. 8002876: f8c4 30f4 str.w r3, [r4, #244] @ 0xf4
  5159. 800287a: f8d4 30f4 ldr.w r3, [r4, #244] @ 0xf4
  5160. 800287e: f403 4300 and.w r3, r3, #32768 @ 0x8000
  5161. 8002882: 9301 str r3, [sp, #4]
  5162. 8002884: 9b01 ldr r3, [sp, #4]
  5163. /** Disable the Internal Voltage Reference buffer
  5164. */
  5165. HAL_SYSCFG_DisableVREFBUF();
  5166. 8002886: f001 fbb9 bl 8003ffc <HAL_SYSCFG_DisableVREFBUF>
  5167. /** Configure the internal voltage reference buffer high impedance mode
  5168. */
  5169. HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE);
  5170. 800288a: 2002 movs r0, #2
  5171. 800288c: f001 fbac bl 8003fe8 <HAL_SYSCFG_VREFBUF_HighImpedanceConfig>
  5172. /* USER CODE BEGIN MspInit 1 */
  5173. /* USER CODE END MspInit 1 */
  5174. }
  5175. 8002890: b007 add sp, #28
  5176. 8002892: bd30 pop {r4, r5, pc}
  5177. 8002894: 58024400 .word 0x58024400
  5178. 08002898 <HAL_ADC_MspInit>:
  5179. * @retval None
  5180. */
  5181. void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
  5182. {
  5183. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5184. if(hadc->Instance==ADC1)
  5185. 8002898: 4a95 ldr r2, [pc, #596] @ (8002af0 <HAL_ADC_MspInit+0x258>)
  5186. 800289a: 6803 ldr r3, [r0, #0]
  5187. {
  5188. 800289c: b570 push {r4, r5, r6, lr}
  5189. if(hadc->Instance==ADC1)
  5190. 800289e: 4293 cmp r3, r2
  5191. {
  5192. 80028a0: b090 sub sp, #64 @ 0x40
  5193. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5194. 80028a2: f04f 0400 mov.w r4, #0
  5195. {
  5196. 80028a6: 4605 mov r5, r0
  5197. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5198. 80028a8: e9cd 440a strd r4, r4, [sp, #40] @ 0x28
  5199. 80028ac: 940c str r4, [sp, #48] @ 0x30
  5200. 80028ae: e9cd 440d strd r4, r4, [sp, #52] @ 0x34
  5201. if(hadc->Instance==ADC1)
  5202. 80028b2: d06b beq.n 800298c <HAL_ADC_MspInit+0xf4>
  5203. /* USER CODE BEGIN ADC1_MspInit 1 */
  5204. /* USER CODE END ADC1_MspInit 1 */
  5205. }
  5206. else if(hadc->Instance==ADC2)
  5207. 80028b4: 4a8f ldr r2, [pc, #572] @ (8002af4 <HAL_ADC_MspInit+0x25c>)
  5208. 80028b6: 4293 cmp r3, r2
  5209. 80028b8: d005 beq.n 80028c6 <HAL_ADC_MspInit+0x2e>
  5210. /* USER CODE BEGIN ADC2_MspInit 1 */
  5211. /* USER CODE END ADC2_MspInit 1 */
  5212. }
  5213. else if(hadc->Instance==ADC3)
  5214. 80028ba: 4a8f ldr r2, [pc, #572] @ (8002af8 <HAL_ADC_MspInit+0x260>)
  5215. 80028bc: 4293 cmp r3, r2
  5216. 80028be: f000 80ce beq.w 8002a5e <HAL_ADC_MspInit+0x1c6>
  5217. /* USER CODE BEGIN ADC3_MspInit 1 */
  5218. /* USER CODE END ADC3_MspInit 1 */
  5219. }
  5220. }
  5221. 80028c2: b010 add sp, #64 @ 0x40
  5222. 80028c4: bd70 pop {r4, r5, r6, pc}
  5223. HAL_RCC_ADC12_CLK_ENABLED++;
  5224. 80028c6: 4a8d ldr r2, [pc, #564] @ (8002afc <HAL_ADC_MspInit+0x264>)
  5225. 80028c8: 6813 ldr r3, [r2, #0]
  5226. 80028ca: 3301 adds r3, #1
  5227. if(HAL_RCC_ADC12_CLK_ENABLED==1){
  5228. 80028cc: 2b01 cmp r3, #1
  5229. HAL_RCC_ADC12_CLK_ENABLED++;
  5230. 80028ce: 6013 str r3, [r2, #0]
  5231. if(HAL_RCC_ADC12_CLK_ENABLED==1){
  5232. 80028d0: f000 80b4 beq.w 8002a3c <HAL_ADC_MspInit+0x1a4>
  5233. __HAL_RCC_GPIOA_CLK_ENABLE();
  5234. 80028d4: 4b8a ldr r3, [pc, #552] @ (8002b00 <HAL_ADC_MspInit+0x268>)
  5235. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  5236. 80028d6: a90a add r1, sp, #40 @ 0x28
  5237. GPIO_InitStruct.Pull = GPIO_NOPULL;
  5238. 80028d8: 2600 movs r6, #0
  5239. hdma_adc2.Instance = DMA1_Stream1;
  5240. 80028da: 4c8a ldr r4, [pc, #552] @ (8002b04 <HAL_ADC_MspInit+0x26c>)
  5241. __HAL_RCC_GPIOA_CLK_ENABLE();
  5242. 80028dc: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5243. 80028e0: f042 0201 orr.w r2, r2, #1
  5244. 80028e4: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5245. 80028e8: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5246. 80028ec: f002 0201 and.w r2, r2, #1
  5247. 80028f0: 9205 str r2, [sp, #20]
  5248. 80028f2: 9a05 ldr r2, [sp, #20]
  5249. __HAL_RCC_GPIOC_CLK_ENABLE();
  5250. 80028f4: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5251. 80028f8: f042 0204 orr.w r2, r2, #4
  5252. 80028fc: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5253. 8002900: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5254. 8002904: f002 0204 and.w r2, r2, #4
  5255. 8002908: 9206 str r2, [sp, #24]
  5256. 800290a: 9a06 ldr r2, [sp, #24]
  5257. __HAL_RCC_GPIOB_CLK_ENABLE();
  5258. 800290c: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5259. 8002910: f042 0202 orr.w r2, r2, #2
  5260. 8002914: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5261. GPIO_InitStruct.Pin = GPIO_PIN_6;
  5262. 8002918: 2240 movs r2, #64 @ 0x40
  5263. __HAL_RCC_GPIOB_CLK_ENABLE();
  5264. 800291a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
  5265. 800291e: f003 0302 and.w r3, r3, #2
  5266. 8002922: 9307 str r3, [sp, #28]
  5267. GPIO_InitStruct.Pin = GPIO_PIN_6;
  5268. 8002924: 2303 movs r3, #3
  5269. __HAL_RCC_GPIOB_CLK_ENABLE();
  5270. 8002926: 9807 ldr r0, [sp, #28]
  5271. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  5272. 8002928: 4877 ldr r0, [pc, #476] @ (8002b08 <HAL_ADC_MspInit+0x270>)
  5273. GPIO_InitStruct.Pin = GPIO_PIN_6;
  5274. 800292a: e9cd 230a strd r2, r3, [sp, #40] @ 0x28
  5275. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  5276. 800292e: f004 fafd bl 8006f2c <HAL_GPIO_Init>
  5277. GPIO_InitStruct.Pin = GPIO_PIN_4;
  5278. 8002932: 2210 movs r2, #16
  5279. 8002934: 2303 movs r3, #3
  5280. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  5281. 8002936: a90a add r1, sp, #40 @ 0x28
  5282. 8002938: 4874 ldr r0, [pc, #464] @ (8002b0c <HAL_ADC_MspInit+0x274>)
  5283. GPIO_InitStruct.Pull = GPIO_NOPULL;
  5284. 800293a: 960c str r6, [sp, #48] @ 0x30
  5285. GPIO_InitStruct.Pin = GPIO_PIN_4;
  5286. 800293c: e9cd 230a strd r2, r3, [sp, #40] @ 0x28
  5287. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  5288. 8002940: f004 faf4 bl 8006f2c <HAL_GPIO_Init>
  5289. GPIO_InitStruct.Pin = GPIO_PIN_1;
  5290. 8002944: 2202 movs r2, #2
  5291. 8002946: 2303 movs r3, #3
  5292. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  5293. 8002948: a90a add r1, sp, #40 @ 0x28
  5294. 800294a: 4871 ldr r0, [pc, #452] @ (8002b10 <HAL_ADC_MspInit+0x278>)
  5295. GPIO_InitStruct.Pull = GPIO_NOPULL;
  5296. 800294c: 960c str r6, [sp, #48] @ 0x30
  5297. GPIO_InitStruct.Pin = GPIO_PIN_1;
  5298. 800294e: e9cd 230a strd r2, r3, [sp, #40] @ 0x28
  5299. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  5300. 8002952: f004 faeb bl 8006f2c <HAL_GPIO_Init>
  5301. hdma_adc2.Instance = DMA1_Stream1;
  5302. 8002956: 4a6f ldr r2, [pc, #444] @ (8002b14 <HAL_ADC_MspInit+0x27c>)
  5303. hdma_adc2.Init.Request = DMA_REQUEST_ADC2;
  5304. 8002958: 230a movs r3, #10
  5305. 800295a: 6063 str r3, [r4, #4]
  5306. hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
  5307. 800295c: f44f 6300 mov.w r3, #2048 @ 0x800
  5308. hdma_adc2.Instance = DMA1_Stream1;
  5309. 8002960: 6022 str r2, [r4, #0]
  5310. hdma_adc2.Init.MemInc = DMA_MINC_ENABLE;
  5311. 8002962: f44f 6280 mov.w r2, #1024 @ 0x400
  5312. hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
  5313. 8002966: 6163 str r3, [r4, #20]
  5314. hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
  5315. 8002968: f44f 5300 mov.w r3, #8192 @ 0x2000
  5316. if (HAL_DMA_Init(&hdma_adc2) != HAL_OK)
  5317. 800296c: 4620 mov r0, r4
  5318. hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY;
  5319. 800296e: 60a6 str r6, [r4, #8]
  5320. hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE;
  5321. 8002970: 60e6 str r6, [r4, #12]
  5322. hdma_adc2.Init.Mode = DMA_NORMAL;
  5323. 8002972: 61e6 str r6, [r4, #28]
  5324. hdma_adc2.Init.MemInc = DMA_MINC_ENABLE;
  5325. 8002974: 6122 str r2, [r4, #16]
  5326. hdma_adc2.Init.Priority = DMA_PRIORITY_LOW;
  5327. 8002976: 6226 str r6, [r4, #32]
  5328. hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  5329. 8002978: 6266 str r6, [r4, #36] @ 0x24
  5330. hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
  5331. 800297a: 61a3 str r3, [r4, #24]
  5332. if (HAL_DMA_Init(&hdma_adc2) != HAL_OK)
  5333. 800297c: f002 fe98 bl 80056b0 <HAL_DMA_Init>
  5334. 8002980: 2800 cmp r0, #0
  5335. 8002982: d169 bne.n 8002a58 <HAL_ADC_MspInit+0x1c0>
  5336. __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2);
  5337. 8002984: 64ec str r4, [r5, #76] @ 0x4c
  5338. 8002986: 63a5 str r5, [r4, #56] @ 0x38
  5339. }
  5340. 8002988: b010 add sp, #64 @ 0x40
  5341. 800298a: bd70 pop {r4, r5, r6, pc}
  5342. HAL_RCC_ADC12_CLK_ENABLED++;
  5343. 800298c: 4a5b ldr r2, [pc, #364] @ (8002afc <HAL_ADC_MspInit+0x264>)
  5344. 800298e: 6813 ldr r3, [r2, #0]
  5345. 8002990: 3301 adds r3, #1
  5346. if(HAL_RCC_ADC12_CLK_ENABLED==1){
  5347. 8002992: 2b01 cmp r3, #1
  5348. HAL_RCC_ADC12_CLK_ENABLED++;
  5349. 8002994: 6013 str r3, [r2, #0]
  5350. if(HAL_RCC_ADC12_CLK_ENABLED==1){
  5351. 8002996: d043 beq.n 8002a20 <HAL_ADC_MspInit+0x188>
  5352. __HAL_RCC_GPIOA_CLK_ENABLE();
  5353. 8002998: 4b59 ldr r3, [pc, #356] @ (8002b00 <HAL_ADC_MspInit+0x268>)
  5354. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  5355. 800299a: a90a add r1, sp, #40 @ 0x28
  5356. GPIO_InitStruct.Pull = GPIO_NOPULL;
  5357. 800299c: 2600 movs r6, #0
  5358. hdma_adc1.Instance = DMA1_Stream0;
  5359. 800299e: 4c5e ldr r4, [pc, #376] @ (8002b18 <HAL_ADC_MspInit+0x280>)
  5360. __HAL_RCC_GPIOA_CLK_ENABLE();
  5361. 80029a0: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5362. 80029a4: f042 0201 orr.w r2, r2, #1
  5363. 80029a8: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5364. 80029ac: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5365. 80029b0: f002 0201 and.w r2, r2, #1
  5366. 80029b4: 9201 str r2, [sp, #4]
  5367. 80029b6: 9a01 ldr r2, [sp, #4]
  5368. __HAL_RCC_GPIOC_CLK_ENABLE();
  5369. 80029b8: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5370. 80029bc: f042 0204 orr.w r2, r2, #4
  5371. 80029c0: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5372. 80029c4: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5373. 80029c8: f002 0204 and.w r2, r2, #4
  5374. 80029cc: 9202 str r2, [sp, #8]
  5375. 80029ce: 9a02 ldr r2, [sp, #8]
  5376. __HAL_RCC_GPIOB_CLK_ENABLE();
  5377. 80029d0: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5378. 80029d4: f042 0202 orr.w r2, r2, #2
  5379. 80029d8: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5380. GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
  5381. 80029dc: 228f movs r2, #143 @ 0x8f
  5382. __HAL_RCC_GPIOB_CLK_ENABLE();
  5383. 80029de: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
  5384. 80029e2: f003 0302 and.w r3, r3, #2
  5385. 80029e6: 9303 str r3, [sp, #12]
  5386. GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
  5387. 80029e8: 2303 movs r3, #3
  5388. __HAL_RCC_GPIOB_CLK_ENABLE();
  5389. 80029ea: 9803 ldr r0, [sp, #12]
  5390. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  5391. 80029ec: 4846 ldr r0, [pc, #280] @ (8002b08 <HAL_ADC_MspInit+0x270>)
  5392. GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
  5393. 80029ee: e9cd 230a strd r2, r3, [sp, #40] @ 0x28
  5394. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  5395. 80029f2: f004 fa9b bl 8006f2c <HAL_GPIO_Init>
  5396. GPIO_InitStruct.Pin = GPIO_PIN_5;
  5397. 80029f6: 2220 movs r2, #32
  5398. 80029f8: 2303 movs r3, #3
  5399. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  5400. 80029fa: a90a add r1, sp, #40 @ 0x28
  5401. 80029fc: 4843 ldr r0, [pc, #268] @ (8002b0c <HAL_ADC_MspInit+0x274>)
  5402. GPIO_InitStruct.Pull = GPIO_NOPULL;
  5403. 80029fe: 960c str r6, [sp, #48] @ 0x30
  5404. GPIO_InitStruct.Pin = GPIO_PIN_5;
  5405. 8002a00: e9cd 230a strd r2, r3, [sp, #40] @ 0x28
  5406. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  5407. 8002a04: f004 fa92 bl 8006f2c <HAL_GPIO_Init>
  5408. GPIO_InitStruct.Pin = GPIO_PIN_0;
  5409. 8002a08: 2201 movs r2, #1
  5410. 8002a0a: 2303 movs r3, #3
  5411. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  5412. 8002a0c: a90a add r1, sp, #40 @ 0x28
  5413. 8002a0e: 4840 ldr r0, [pc, #256] @ (8002b10 <HAL_ADC_MspInit+0x278>)
  5414. GPIO_InitStruct.Pull = GPIO_NOPULL;
  5415. 8002a10: 960c str r6, [sp, #48] @ 0x30
  5416. GPIO_InitStruct.Pin = GPIO_PIN_0;
  5417. 8002a12: e9cd 230a strd r2, r3, [sp, #40] @ 0x28
  5418. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  5419. 8002a16: f004 fa89 bl 8006f2c <HAL_GPIO_Init>
  5420. hdma_adc1.Instance = DMA1_Stream0;
  5421. 8002a1a: 4a40 ldr r2, [pc, #256] @ (8002b1c <HAL_ADC_MspInit+0x284>)
  5422. hdma_adc1.Init.Request = DMA_REQUEST_ADC1;
  5423. 8002a1c: 2309 movs r3, #9
  5424. 8002a1e: e79c b.n 800295a <HAL_ADC_MspInit+0xc2>
  5425. __HAL_RCC_ADC12_CLK_ENABLE();
  5426. 8002a20: 4b37 ldr r3, [pc, #220] @ (8002b00 <HAL_ADC_MspInit+0x268>)
  5427. 8002a22: f8d3 20d8 ldr.w r2, [r3, #216] @ 0xd8
  5428. 8002a26: f042 0220 orr.w r2, r2, #32
  5429. 8002a2a: f8c3 20d8 str.w r2, [r3, #216] @ 0xd8
  5430. 8002a2e: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8
  5431. 8002a32: f003 0320 and.w r3, r3, #32
  5432. 8002a36: 9300 str r3, [sp, #0]
  5433. 8002a38: 9b00 ldr r3, [sp, #0]
  5434. 8002a3a: e7ad b.n 8002998 <HAL_ADC_MspInit+0x100>
  5435. __HAL_RCC_ADC12_CLK_ENABLE();
  5436. 8002a3c: 4b30 ldr r3, [pc, #192] @ (8002b00 <HAL_ADC_MspInit+0x268>)
  5437. 8002a3e: f8d3 20d8 ldr.w r2, [r3, #216] @ 0xd8
  5438. 8002a42: f042 0220 orr.w r2, r2, #32
  5439. 8002a46: f8c3 20d8 str.w r2, [r3, #216] @ 0xd8
  5440. 8002a4a: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8
  5441. 8002a4e: f003 0320 and.w r3, r3, #32
  5442. 8002a52: 9304 str r3, [sp, #16]
  5443. 8002a54: 9b04 ldr r3, [sp, #16]
  5444. 8002a56: e73d b.n 80028d4 <HAL_ADC_MspInit+0x3c>
  5445. Error_Handler();
  5446. 8002a58: f7fd fece bl 80007f8 <Error_Handler>
  5447. 8002a5c: e792 b.n 8002984 <HAL_ADC_MspInit+0xec>
  5448. __HAL_RCC_ADC3_CLK_ENABLE();
  5449. 8002a5e: 4b28 ldr r3, [pc, #160] @ (8002b00 <HAL_ADC_MspInit+0x268>)
  5450. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  5451. 8002a60: a90a add r1, sp, #40 @ 0x28
  5452. hdma_adc3.Instance = DMA1_Stream2;
  5453. 8002a62: 4e2f ldr r6, [pc, #188] @ (8002b20 <HAL_ADC_MspInit+0x288>)
  5454. __HAL_RCC_ADC3_CLK_ENABLE();
  5455. 8002a64: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5456. 8002a68: f042 7280 orr.w r2, r2, #16777216 @ 0x1000000
  5457. 8002a6c: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5458. 8002a70: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5459. 8002a74: f002 7280 and.w r2, r2, #16777216 @ 0x1000000
  5460. 8002a78: 9208 str r2, [sp, #32]
  5461. 8002a7a: 9a08 ldr r2, [sp, #32]
  5462. __HAL_RCC_GPIOC_CLK_ENABLE();
  5463. 8002a7c: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5464. 8002a80: f042 0204 orr.w r2, r2, #4
  5465. 8002a84: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5466. GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
  5467. 8002a88: 2203 movs r2, #3
  5468. __HAL_RCC_GPIOC_CLK_ENABLE();
  5469. 8002a8a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
  5470. 8002a8e: f003 0304 and.w r3, r3, #4
  5471. 8002a92: 9309 str r3, [sp, #36] @ 0x24
  5472. GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
  5473. 8002a94: 2303 movs r3, #3
  5474. __HAL_RCC_GPIOC_CLK_ENABLE();
  5475. 8002a96: 9809 ldr r0, [sp, #36] @ 0x24
  5476. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  5477. 8002a98: 481c ldr r0, [pc, #112] @ (8002b0c <HAL_ADC_MspInit+0x274>)
  5478. GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
  5479. 8002a9a: e9cd 230a strd r2, r3, [sp, #40] @ 0x28
  5480. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  5481. 8002a9e: f004 fa45 bl 8006f2c <HAL_GPIO_Init>
  5482. HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN);
  5483. 8002aa2: f04f 6180 mov.w r1, #67108864 @ 0x4000000
  5484. 8002aa6: 4608 mov r0, r1
  5485. 8002aa8: f001 fab0 bl 800400c <HAL_SYSCFG_AnalogSwitchConfig>
  5486. HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN);
  5487. 8002aac: f04f 6100 mov.w r1, #134217728 @ 0x8000000
  5488. 8002ab0: 4608 mov r0, r1
  5489. 8002ab2: f001 faab bl 800400c <HAL_SYSCFG_AnalogSwitchConfig>
  5490. hdma_adc3.Init.Request = DMA_REQUEST_ADC3;
  5491. 8002ab6: 2373 movs r3, #115 @ 0x73
  5492. hdma_adc3.Instance = DMA1_Stream2;
  5493. 8002ab8: 4a1a ldr r2, [pc, #104] @ (8002b24 <HAL_ADC_MspInit+0x28c>)
  5494. if (HAL_DMA_Init(&hdma_adc3) != HAL_OK)
  5495. 8002aba: 4630 mov r0, r6
  5496. hdma_adc3.Init.Request = DMA_REQUEST_ADC3;
  5497. 8002abc: 6073 str r3, [r6, #4]
  5498. hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
  5499. 8002abe: f44f 6300 mov.w r3, #2048 @ 0x800
  5500. hdma_adc3.Instance = DMA1_Stream2;
  5501. 8002ac2: 6032 str r2, [r6, #0]
  5502. hdma_adc3.Init.MemInc = DMA_MINC_ENABLE;
  5503. 8002ac4: f44f 6280 mov.w r2, #1024 @ 0x400
  5504. hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
  5505. 8002ac8: 6173 str r3, [r6, #20]
  5506. hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
  5507. 8002aca: f44f 5300 mov.w r3, #8192 @ 0x2000
  5508. hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY;
  5509. 8002ace: 60b4 str r4, [r6, #8]
  5510. hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE;
  5511. 8002ad0: 60f4 str r4, [r6, #12]
  5512. hdma_adc3.Init.Mode = DMA_NORMAL;
  5513. 8002ad2: 61f4 str r4, [r6, #28]
  5514. hdma_adc3.Init.MemInc = DMA_MINC_ENABLE;
  5515. 8002ad4: 6132 str r2, [r6, #16]
  5516. hdma_adc3.Init.Priority = DMA_PRIORITY_LOW;
  5517. 8002ad6: 6234 str r4, [r6, #32]
  5518. hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  5519. 8002ad8: 6274 str r4, [r6, #36] @ 0x24
  5520. hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
  5521. 8002ada: 61b3 str r3, [r6, #24]
  5522. if (HAL_DMA_Init(&hdma_adc3) != HAL_OK)
  5523. 8002adc: f002 fde8 bl 80056b0 <HAL_DMA_Init>
  5524. 8002ae0: b910 cbnz r0, 8002ae8 <HAL_ADC_MspInit+0x250>
  5525. __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3);
  5526. 8002ae2: 64ee str r6, [r5, #76] @ 0x4c
  5527. 8002ae4: 63b5 str r5, [r6, #56] @ 0x38
  5528. }
  5529. 8002ae6: e6ec b.n 80028c2 <HAL_ADC_MspInit+0x2a>
  5530. Error_Handler();
  5531. 8002ae8: f7fd fe86 bl 80007f8 <Error_Handler>
  5532. 8002aec: e7f9 b.n 8002ae2 <HAL_ADC_MspInit+0x24a>
  5533. 8002aee: bf00 nop
  5534. 8002af0: 40022000 .word 0x40022000
  5535. 8002af4: 40022100 .word 0x40022100
  5536. 8002af8: 58026000 .word 0x58026000
  5537. 8002afc: 24000a64 .word 0x24000a64
  5538. 8002b00: 58024400 .word 0x58024400
  5539. 8002b04: 24000698 .word 0x24000698
  5540. 8002b08: 58020000 .word 0x58020000
  5541. 8002b0c: 58020800 .word 0x58020800
  5542. 8002b10: 58020400 .word 0x58020400
  5543. 8002b14: 40020028 .word 0x40020028
  5544. 8002b18: 24000710 .word 0x24000710
  5545. 8002b1c: 40020010 .word 0x40020010
  5546. 8002b20: 24000620 .word 0x24000620
  5547. 8002b24: 40020040 .word 0x40020040
  5548. 08002b28 <HAL_COMP_MspInit>:
  5549. * @retval None
  5550. */
  5551. void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp)
  5552. {
  5553. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5554. if(hcomp->Instance==COMP1)
  5555. 8002b28: 4a1b ldr r2, [pc, #108] @ (8002b98 <HAL_COMP_MspInit+0x70>)
  5556. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5557. 8002b2a: 2300 movs r3, #0
  5558. if(hcomp->Instance==COMP1)
  5559. 8002b2c: 6801 ldr r1, [r0, #0]
  5560. {
  5561. 8002b2e: b500 push {lr}
  5562. if(hcomp->Instance==COMP1)
  5563. 8002b30: 4291 cmp r1, r2
  5564. {
  5565. 8002b32: b089 sub sp, #36 @ 0x24
  5566. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5567. 8002b34: e9cd 3302 strd r3, r3, [sp, #8]
  5568. 8002b38: e9cd 3304 strd r3, r3, [sp, #16]
  5569. 8002b3c: 9306 str r3, [sp, #24]
  5570. if(hcomp->Instance==COMP1)
  5571. 8002b3e: d002 beq.n 8002b46 <HAL_COMP_MspInit+0x1e>
  5572. /* USER CODE BEGIN COMP1_MspInit 1 */
  5573. /* USER CODE END COMP1_MspInit 1 */
  5574. }
  5575. }
  5576. 8002b40: b009 add sp, #36 @ 0x24
  5577. 8002b42: f85d fb04 ldr.w pc, [sp], #4
  5578. __HAL_RCC_COMP12_CLK_ENABLE();
  5579. 8002b46: 4b15 ldr r3, [pc, #84] @ (8002b9c <HAL_COMP_MspInit+0x74>)
  5580. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  5581. 8002b48: a902 add r1, sp, #8
  5582. 8002b4a: 4815 ldr r0, [pc, #84] @ (8002ba0 <HAL_COMP_MspInit+0x78>)
  5583. __HAL_RCC_COMP12_CLK_ENABLE();
  5584. 8002b4c: f8d3 20f4 ldr.w r2, [r3, #244] @ 0xf4
  5585. 8002b50: f442 4280 orr.w r2, r2, #16384 @ 0x4000
  5586. 8002b54: f8c3 20f4 str.w r2, [r3, #244] @ 0xf4
  5587. 8002b58: f8d3 20f4 ldr.w r2, [r3, #244] @ 0xf4
  5588. 8002b5c: f402 4280 and.w r2, r2, #16384 @ 0x4000
  5589. 8002b60: 9200 str r2, [sp, #0]
  5590. 8002b62: 9a00 ldr r2, [sp, #0]
  5591. __HAL_RCC_GPIOB_CLK_ENABLE();
  5592. 8002b64: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5593. 8002b68: f042 0202 orr.w r2, r2, #2
  5594. 8002b6c: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5595. 8002b70: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
  5596. 8002b74: f003 0302 and.w r3, r3, #2
  5597. GPIO_InitStruct.Pin = GPIO_PIN_2;
  5598. 8002b78: ed9f 7b05 vldr d7, [pc, #20] @ 8002b90 <HAL_COMP_MspInit+0x68>
  5599. __HAL_RCC_GPIOB_CLK_ENABLE();
  5600. 8002b7c: 9301 str r3, [sp, #4]
  5601. 8002b7e: 9b01 ldr r3, [sp, #4]
  5602. GPIO_InitStruct.Pin = GPIO_PIN_2;
  5603. 8002b80: ed8d 7b02 vstr d7, [sp, #8]
  5604. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  5605. 8002b84: f004 f9d2 bl 8006f2c <HAL_GPIO_Init>
  5606. }
  5607. 8002b88: b009 add sp, #36 @ 0x24
  5608. 8002b8a: f85d fb04 ldr.w pc, [sp], #4
  5609. 8002b8e: bf00 nop
  5610. 8002b90: 00000004 .word 0x00000004
  5611. 8002b94: 00000003 .word 0x00000003
  5612. 8002b98: 5800380c .word 0x5800380c
  5613. 8002b9c: 58024400 .word 0x58024400
  5614. 8002ba0: 58020400 .word 0x58020400
  5615. 08002ba4 <HAL_CRC_MspInit>:
  5616. * @param hcrc: CRC handle pointer
  5617. * @retval None
  5618. */
  5619. void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
  5620. {
  5621. if(hcrc->Instance==CRC)
  5622. 8002ba4: 4b0a ldr r3, [pc, #40] @ (8002bd0 <HAL_CRC_MspInit+0x2c>)
  5623. 8002ba6: 6802 ldr r2, [r0, #0]
  5624. 8002ba8: 429a cmp r2, r3
  5625. 8002baa: d000 beq.n 8002bae <HAL_CRC_MspInit+0xa>
  5626. 8002bac: 4770 bx lr
  5627. {
  5628. /* USER CODE BEGIN CRC_MspInit 0 */
  5629. /* USER CODE END CRC_MspInit 0 */
  5630. /* Peripheral clock enable */
  5631. __HAL_RCC_CRC_CLK_ENABLE();
  5632. 8002bae: f5a3 6300 sub.w r3, r3, #2048 @ 0x800
  5633. {
  5634. 8002bb2: b082 sub sp, #8
  5635. __HAL_RCC_CRC_CLK_ENABLE();
  5636. 8002bb4: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5637. 8002bb8: f442 2200 orr.w r2, r2, #524288 @ 0x80000
  5638. 8002bbc: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5639. 8002bc0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
  5640. 8002bc4: f403 2300 and.w r3, r3, #524288 @ 0x80000
  5641. 8002bc8: 9301 str r3, [sp, #4]
  5642. 8002bca: 9b01 ldr r3, [sp, #4]
  5643. /* USER CODE BEGIN CRC_MspInit 1 */
  5644. /* USER CODE END CRC_MspInit 1 */
  5645. }
  5646. }
  5647. 8002bcc: b002 add sp, #8
  5648. 8002bce: 4770 bx lr
  5649. 8002bd0: 58024c00 .word 0x58024c00
  5650. 08002bd4 <HAL_DAC_MspInit>:
  5651. * @retval None
  5652. */
  5653. void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
  5654. {
  5655. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5656. if(hdac->Instance==DAC1)
  5657. 8002bd4: 4b1c ldr r3, [pc, #112] @ (8002c48 <HAL_DAC_MspInit+0x74>)
  5658. 8002bd6: 6802 ldr r2, [r0, #0]
  5659. {
  5660. 8002bd8: b530 push {r4, r5, lr}
  5661. if(hdac->Instance==DAC1)
  5662. 8002bda: 429a cmp r2, r3
  5663. {
  5664. 8002bdc: b089 sub sp, #36 @ 0x24
  5665. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5666. 8002bde: f04f 0400 mov.w r4, #0
  5667. 8002be2: e9cd 4402 strd r4, r4, [sp, #8]
  5668. 8002be6: e9cd 4404 strd r4, r4, [sp, #16]
  5669. 8002bea: 9406 str r4, [sp, #24]
  5670. if(hdac->Instance==DAC1)
  5671. 8002bec: d001 beq.n 8002bf2 <HAL_DAC_MspInit+0x1e>
  5672. /* USER CODE BEGIN DAC1_MspInit 1 */
  5673. /* USER CODE END DAC1_MspInit 1 */
  5674. }
  5675. }
  5676. 8002bee: b009 add sp, #36 @ 0x24
  5677. 8002bf0: bd30 pop {r4, r5, pc}
  5678. __HAL_RCC_DAC12_CLK_ENABLE();
  5679. 8002bf2: 4b16 ldr r3, [pc, #88] @ (8002c4c <HAL_DAC_MspInit+0x78>)
  5680. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  5681. 8002bf4: a902 add r1, sp, #8
  5682. 8002bf6: 4816 ldr r0, [pc, #88] @ (8002c50 <HAL_DAC_MspInit+0x7c>)
  5683. __HAL_RCC_DAC12_CLK_ENABLE();
  5684. 8002bf8: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8
  5685. 8002bfc: f042 5200 orr.w r2, r2, #536870912 @ 0x20000000
  5686. 8002c00: f8c3 20e8 str.w r2, [r3, #232] @ 0xe8
  5687. 8002c04: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8
  5688. 8002c08: f002 5200 and.w r2, r2, #536870912 @ 0x20000000
  5689. 8002c0c: 9200 str r2, [sp, #0]
  5690. 8002c0e: 9a00 ldr r2, [sp, #0]
  5691. __HAL_RCC_GPIOA_CLK_ENABLE();
  5692. 8002c10: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5693. 8002c14: f042 0201 orr.w r2, r2, #1
  5694. 8002c18: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5695. GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
  5696. 8002c1c: 2230 movs r2, #48 @ 0x30
  5697. __HAL_RCC_GPIOA_CLK_ENABLE();
  5698. 8002c1e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
  5699. 8002c22: f003 0301 and.w r3, r3, #1
  5700. 8002c26: 9301 str r3, [sp, #4]
  5701. GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
  5702. 8002c28: 2303 movs r3, #3
  5703. __HAL_RCC_GPIOA_CLK_ENABLE();
  5704. 8002c2a: 9d01 ldr r5, [sp, #4]
  5705. GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
  5706. 8002c2c: e9cd 2302 strd r2, r3, [sp, #8]
  5707. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  5708. 8002c30: f004 f97c bl 8006f2c <HAL_GPIO_Init>
  5709. HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0);
  5710. 8002c34: 4622 mov r2, r4
  5711. 8002c36: 2105 movs r1, #5
  5712. 8002c38: 2036 movs r0, #54 @ 0x36
  5713. 8002c3a: f002 f97d bl 8004f38 <HAL_NVIC_SetPriority>
  5714. HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
  5715. 8002c3e: 2036 movs r0, #54 @ 0x36
  5716. 8002c40: f002 f9b6 bl 8004fb0 <HAL_NVIC_EnableIRQ>
  5717. }
  5718. 8002c44: b009 add sp, #36 @ 0x24
  5719. 8002c46: bd30 pop {r4, r5, pc}
  5720. 8002c48: 40007400 .word 0x40007400
  5721. 8002c4c: 58024400 .word 0x58024400
  5722. 8002c50: 58020000 .word 0x58020000
  5723. 08002c54 <HAL_RNG_MspInit>:
  5724. * This function configures the hardware resources used in this example
  5725. * @param hrng: RNG handle pointer
  5726. * @retval None
  5727. */
  5728. void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng)
  5729. {
  5730. 8002c54: b510 push {r4, lr}
  5731. 8002c56: b0b2 sub sp, #200 @ 0xc8
  5732. 8002c58: 4604 mov r4, r0
  5733. RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
  5734. 8002c5a: 22c0 movs r2, #192 @ 0xc0
  5735. 8002c5c: 2100 movs r1, #0
  5736. 8002c5e: a802 add r0, sp, #8
  5737. 8002c60: f00c ff52 bl 800fb08 <memset>
  5738. if(hrng->Instance==RNG)
  5739. 8002c64: 4b10 ldr r3, [pc, #64] @ (8002ca8 <HAL_RNG_MspInit+0x54>)
  5740. 8002c66: 6822 ldr r2, [r4, #0]
  5741. 8002c68: 429a cmp r2, r3
  5742. 8002c6a: d001 beq.n 8002c70 <HAL_RNG_MspInit+0x1c>
  5743. /* USER CODE BEGIN RNG_MspInit 1 */
  5744. /* USER CODE END RNG_MspInit 1 */
  5745. }
  5746. }
  5747. 8002c6c: b032 add sp, #200 @ 0xc8
  5748. 8002c6e: bd10 pop {r4, pc}
  5749. PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
  5750. 8002c70: f44f 3200 mov.w r2, #131072 @ 0x20000
  5751. 8002c74: 2300 movs r3, #0
  5752. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
  5753. 8002c76: a802 add r0, sp, #8
  5754. PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
  5755. 8002c78: e9cd 2302 strd r2, r3, [sp, #8]
  5756. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
  5757. 8002c7c: f005 fab0 bl 80081e0 <HAL_RCCEx_PeriphCLKConfig>
  5758. 8002c80: b970 cbnz r0, 8002ca0 <HAL_RNG_MspInit+0x4c>
  5759. __HAL_RCC_RNG_CLK_ENABLE();
  5760. 8002c82: 4b0a ldr r3, [pc, #40] @ (8002cac <HAL_RNG_MspInit+0x58>)
  5761. 8002c84: f8d3 20dc ldr.w r2, [r3, #220] @ 0xdc
  5762. 8002c88: f042 0240 orr.w r2, r2, #64 @ 0x40
  5763. 8002c8c: f8c3 20dc str.w r2, [r3, #220] @ 0xdc
  5764. 8002c90: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc
  5765. 8002c94: f003 0340 and.w r3, r3, #64 @ 0x40
  5766. 8002c98: 9301 str r3, [sp, #4]
  5767. 8002c9a: 9b01 ldr r3, [sp, #4]
  5768. }
  5769. 8002c9c: b032 add sp, #200 @ 0xc8
  5770. 8002c9e: bd10 pop {r4, pc}
  5771. Error_Handler();
  5772. 8002ca0: f7fd fdaa bl 80007f8 <Error_Handler>
  5773. 8002ca4: e7ed b.n 8002c82 <HAL_RNG_MspInit+0x2e>
  5774. 8002ca6: bf00 nop
  5775. 8002ca8: 48021800 .word 0x48021800
  5776. 8002cac: 58024400 .word 0x58024400
  5777. 08002cb0 <HAL_TIM_PWM_MspInit>:
  5778. * @param htim_pwm: TIM_PWM handle pointer
  5779. * @retval None
  5780. */
  5781. void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
  5782. {
  5783. if(htim_pwm->Instance==TIM1)
  5784. 8002cb0: 4a13 ldr r2, [pc, #76] @ (8002d00 <HAL_TIM_PWM_MspInit+0x50>)
  5785. {
  5786. 8002cb2: b082 sub sp, #8
  5787. if(htim_pwm->Instance==TIM1)
  5788. 8002cb4: 6803 ldr r3, [r0, #0]
  5789. 8002cb6: 4293 cmp r3, r2
  5790. 8002cb8: d013 beq.n 8002ce2 <HAL_TIM_PWM_MspInit+0x32>
  5791. __HAL_RCC_TIM1_CLK_ENABLE();
  5792. /* USER CODE BEGIN TIM1_MspInit 1 */
  5793. /* USER CODE END TIM1_MspInit 1 */
  5794. }
  5795. else if(htim_pwm->Instance==TIM3)
  5796. 8002cba: 4a12 ldr r2, [pc, #72] @ (8002d04 <HAL_TIM_PWM_MspInit+0x54>)
  5797. 8002cbc: 4293 cmp r3, r2
  5798. 8002cbe: d001 beq.n 8002cc4 <HAL_TIM_PWM_MspInit+0x14>
  5799. /* USER CODE BEGIN TIM3_MspInit 1 */
  5800. /* USER CODE END TIM3_MspInit 1 */
  5801. }
  5802. }
  5803. 8002cc0: b002 add sp, #8
  5804. 8002cc2: 4770 bx lr
  5805. __HAL_RCC_TIM3_CLK_ENABLE();
  5806. 8002cc4: 4b10 ldr r3, [pc, #64] @ (8002d08 <HAL_TIM_PWM_MspInit+0x58>)
  5807. 8002cc6: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8
  5808. 8002cca: f042 0202 orr.w r2, r2, #2
  5809. 8002cce: f8c3 20e8 str.w r2, [r3, #232] @ 0xe8
  5810. 8002cd2: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8
  5811. 8002cd6: f003 0302 and.w r3, r3, #2
  5812. 8002cda: 9301 str r3, [sp, #4]
  5813. 8002cdc: 9b01 ldr r3, [sp, #4]
  5814. }
  5815. 8002cde: b002 add sp, #8
  5816. 8002ce0: 4770 bx lr
  5817. __HAL_RCC_TIM1_CLK_ENABLE();
  5818. 8002ce2: 4b09 ldr r3, [pc, #36] @ (8002d08 <HAL_TIM_PWM_MspInit+0x58>)
  5819. 8002ce4: f8d3 20f0 ldr.w r2, [r3, #240] @ 0xf0
  5820. 8002ce8: f042 0201 orr.w r2, r2, #1
  5821. 8002cec: f8c3 20f0 str.w r2, [r3, #240] @ 0xf0
  5822. 8002cf0: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0
  5823. 8002cf4: f003 0301 and.w r3, r3, #1
  5824. 8002cf8: 9300 str r3, [sp, #0]
  5825. 8002cfa: 9b00 ldr r3, [sp, #0]
  5826. }
  5827. 8002cfc: b002 add sp, #8
  5828. 8002cfe: 4770 bx lr
  5829. 8002d00: 40010000 .word 0x40010000
  5830. 8002d04: 40000400 .word 0x40000400
  5831. 8002d08: 58024400 .word 0x58024400
  5832. 08002d0c <HAL_TIM_Base_MspInit>:
  5833. * @param htim_base: TIM_Base handle pointer
  5834. * @retval None
  5835. */
  5836. void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
  5837. {
  5838. if(htim_base->Instance==TIM8)
  5839. 8002d0c: 4b0a ldr r3, [pc, #40] @ (8002d38 <HAL_TIM_Base_MspInit+0x2c>)
  5840. 8002d0e: 6802 ldr r2, [r0, #0]
  5841. 8002d10: 429a cmp r2, r3
  5842. 8002d12: d000 beq.n 8002d16 <HAL_TIM_Base_MspInit+0xa>
  5843. 8002d14: 4770 bx lr
  5844. {
  5845. /* USER CODE BEGIN TIM8_MspInit 0 */
  5846. /* USER CODE END TIM8_MspInit 0 */
  5847. /* Peripheral clock enable */
  5848. __HAL_RCC_TIM8_CLK_ENABLE();
  5849. 8002d16: 4b09 ldr r3, [pc, #36] @ (8002d3c <HAL_TIM_Base_MspInit+0x30>)
  5850. {
  5851. 8002d18: b082 sub sp, #8
  5852. __HAL_RCC_TIM8_CLK_ENABLE();
  5853. 8002d1a: f8d3 20f0 ldr.w r2, [r3, #240] @ 0xf0
  5854. 8002d1e: f042 0202 orr.w r2, r2, #2
  5855. 8002d22: f8c3 20f0 str.w r2, [r3, #240] @ 0xf0
  5856. 8002d26: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0
  5857. 8002d2a: f003 0302 and.w r3, r3, #2
  5858. 8002d2e: 9301 str r3, [sp, #4]
  5859. 8002d30: 9b01 ldr r3, [sp, #4]
  5860. /* USER CODE BEGIN TIM8_MspInit 1 */
  5861. /* USER CODE END TIM8_MspInit 1 */
  5862. }
  5863. }
  5864. 8002d32: b002 add sp, #8
  5865. 8002d34: 4770 bx lr
  5866. 8002d36: bf00 nop
  5867. 8002d38: 40010400 .word 0x40010400
  5868. 8002d3c: 58024400 .word 0x58024400
  5869. 08002d40 <HAL_TIM_MspPostInit>:
  5870. void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
  5871. {
  5872. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5873. if(htim->Instance==TIM1)
  5874. 8002d40: 4925 ldr r1, [pc, #148] @ (8002dd8 <HAL_TIM_MspPostInit+0x98>)
  5875. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5876. 8002d42: 2300 movs r3, #0
  5877. if(htim->Instance==TIM1)
  5878. 8002d44: 6802 ldr r2, [r0, #0]
  5879. {
  5880. 8002d46: b510 push {r4, lr}
  5881. if(htim->Instance==TIM1)
  5882. 8002d48: 428a cmp r2, r1
  5883. {
  5884. 8002d4a: b088 sub sp, #32
  5885. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5886. 8002d4c: e9cd 3302 strd r3, r3, [sp, #8]
  5887. 8002d50: e9cd 3304 strd r3, r3, [sp, #16]
  5888. 8002d54: 9306 str r3, [sp, #24]
  5889. if(htim->Instance==TIM1)
  5890. 8002d56: d004 beq.n 8002d62 <HAL_TIM_MspPostInit+0x22>
  5891. /* USER CODE BEGIN TIM1_MspPostInit 1 */
  5892. /* USER CODE END TIM1_MspPostInit 1 */
  5893. }
  5894. else if(htim->Instance==TIM3)
  5895. 8002d58: 4b20 ldr r3, [pc, #128] @ (8002ddc <HAL_TIM_MspPostInit+0x9c>)
  5896. 8002d5a: 429a cmp r2, r3
  5897. 8002d5c: d018 beq.n 8002d90 <HAL_TIM_MspPostInit+0x50>
  5898. /* USER CODE BEGIN TIM3_MspPostInit 1 */
  5899. /* USER CODE END TIM3_MspPostInit 1 */
  5900. }
  5901. }
  5902. 8002d5e: b008 add sp, #32
  5903. 8002d60: bd10 pop {r4, pc}
  5904. __HAL_RCC_GPIOA_CLK_ENABLE();
  5905. 8002d62: 4b1f ldr r3, [pc, #124] @ (8002de0 <HAL_TIM_MspPostInit+0xa0>)
  5906. GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
  5907. 8002d64: 2401 movs r4, #1
  5908. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  5909. 8002d66: a902 add r1, sp, #8
  5910. 8002d68: 481e ldr r0, [pc, #120] @ (8002de4 <HAL_TIM_MspPostInit+0xa4>)
  5911. __HAL_RCC_GPIOA_CLK_ENABLE();
  5912. 8002d6a: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5913. 8002d6e: 4322 orrs r2, r4
  5914. 8002d70: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5915. 8002d74: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
  5916. GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
  5917. 8002d78: 9406 str r4, [sp, #24]
  5918. __HAL_RCC_GPIOA_CLK_ENABLE();
  5919. 8002d7a: 4023 ands r3, r4
  5920. GPIO_InitStruct.Pin = GPIO_PIN_9;
  5921. 8002d7c: ed9f 7b12 vldr d7, [pc, #72] @ 8002dc8 <HAL_TIM_MspPostInit+0x88>
  5922. __HAL_RCC_GPIOA_CLK_ENABLE();
  5923. 8002d80: 9300 str r3, [sp, #0]
  5924. 8002d82: 9b00 ldr r3, [sp, #0]
  5925. GPIO_InitStruct.Pin = GPIO_PIN_9;
  5926. 8002d84: ed8d 7b02 vstr d7, [sp, #8]
  5927. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  5928. 8002d88: f004 f8d0 bl 8006f2c <HAL_GPIO_Init>
  5929. }
  5930. 8002d8c: b008 add sp, #32
  5931. 8002d8e: bd10 pop {r4, pc}
  5932. __HAL_RCC_GPIOC_CLK_ENABLE();
  5933. 8002d90: 4b13 ldr r3, [pc, #76] @ (8002de0 <HAL_TIM_MspPostInit+0xa0>)
  5934. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
  5935. 8002d92: 2001 movs r0, #1
  5936. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  5937. 8002d94: a902 add r1, sp, #8
  5938. __HAL_RCC_GPIOC_CLK_ENABLE();
  5939. 8002d96: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  5940. 8002d9a: f042 0204 orr.w r2, r2, #4
  5941. 8002d9e: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  5942. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
  5943. 8002da2: 2202 movs r2, #2
  5944. __HAL_RCC_GPIOC_CLK_ENABLE();
  5945. 8002da4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
  5946. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
  5947. 8002da8: 9005 str r0, [sp, #20]
  5948. __HAL_RCC_GPIOC_CLK_ENABLE();
  5949. 8002daa: f003 0304 and.w r3, r3, #4
  5950. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  5951. 8002dae: 480e ldr r0, [pc, #56] @ (8002de8 <HAL_TIM_MspPostInit+0xa8>)
  5952. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
  5953. 8002db0: 9206 str r2, [sp, #24]
  5954. __HAL_RCC_GPIOC_CLK_ENABLE();
  5955. 8002db2: 9301 str r3, [sp, #4]
  5956. 8002db4: 9b01 ldr r3, [sp, #4]
  5957. GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9;
  5958. 8002db6: ed9f 7b06 vldr d7, [pc, #24] @ 8002dd0 <HAL_TIM_MspPostInit+0x90>
  5959. 8002dba: ed8d 7b02 vstr d7, [sp, #8]
  5960. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  5961. 8002dbe: f004 f8b5 bl 8006f2c <HAL_GPIO_Init>
  5962. }
  5963. 8002dc2: b008 add sp, #32
  5964. 8002dc4: bd10 pop {r4, pc}
  5965. 8002dc6: bf00 nop
  5966. 8002dc8: 00000200 .word 0x00000200
  5967. 8002dcc: 00000002 .word 0x00000002
  5968. 8002dd0: 000003c0 .word 0x000003c0
  5969. 8002dd4: 00000002 .word 0x00000002
  5970. 8002dd8: 40010000 .word 0x40010000
  5971. 8002ddc: 40000400 .word 0x40000400
  5972. 8002de0: 58024400 .word 0x58024400
  5973. 8002de4: 58020000 .word 0x58020000
  5974. 8002de8: 58020800 .word 0x58020800
  5975. 8002dec: 00000000 .word 0x00000000
  5976. 08002df0 <HAL_UART_MspInit>:
  5977. * This function configures the hardware resources used in this example
  5978. * @param huart: UART handle pointer
  5979. * @retval None
  5980. */
  5981. void HAL_UART_MspInit(UART_HandleTypeDef* huart)
  5982. {
  5983. 8002df0: b510 push {r4, lr}
  5984. 8002df2: b0ba sub sp, #232 @ 0xe8
  5985. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5986. 8002df4: 2100 movs r1, #0
  5987. {
  5988. 8002df6: 4604 mov r4, r0
  5989. RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
  5990. 8002df8: 22c0 movs r2, #192 @ 0xc0
  5991. 8002dfa: a80a add r0, sp, #40 @ 0x28
  5992. GPIO_InitTypeDef GPIO_InitStruct = {0};
  5993. 8002dfc: 9108 str r1, [sp, #32]
  5994. 8002dfe: e9cd 1104 strd r1, r1, [sp, #16]
  5995. 8002e02: e9cd 1106 strd r1, r1, [sp, #24]
  5996. RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
  5997. 8002e06: f00c fe7f bl 800fb08 <memset>
  5998. if(huart->Instance==UART8)
  5999. 8002e0a: 6823 ldr r3, [r4, #0]
  6000. 8002e0c: 4a46 ldr r2, [pc, #280] @ (8002f28 <HAL_UART_MspInit+0x138>)
  6001. 8002e0e: 4293 cmp r3, r2
  6002. 8002e10: d004 beq.n 8002e1c <HAL_UART_MspInit+0x2c>
  6003. HAL_NVIC_EnableIRQ(UART8_IRQn);
  6004. /* USER CODE BEGIN UART8_MspInit 1 */
  6005. /* USER CODE END UART8_MspInit 1 */
  6006. }
  6007. else if(huart->Instance==USART1)
  6008. 8002e12: 4a46 ldr r2, [pc, #280] @ (8002f2c <HAL_UART_MspInit+0x13c>)
  6009. 8002e14: 4293 cmp r3, r2
  6010. 8002e16: d03b beq.n 8002e90 <HAL_UART_MspInit+0xa0>
  6011. /* USER CODE BEGIN USART1_MspInit 1 */
  6012. /* USER CODE END USART1_MspInit 1 */
  6013. }
  6014. }
  6015. 8002e18: b03a add sp, #232 @ 0xe8
  6016. 8002e1a: bd10 pop {r4, pc}
  6017. PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8;
  6018. 8002e1c: 2202 movs r2, #2
  6019. 8002e1e: 2300 movs r3, #0
  6020. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
  6021. 8002e20: a80a add r0, sp, #40 @ 0x28
  6022. PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8;
  6023. 8002e22: e9cd 230a strd r2, r3, [sp, #40] @ 0x28
  6024. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
  6025. 8002e26: f005 f9db bl 80081e0 <HAL_RCCEx_PeriphCLKConfig>
  6026. 8002e2a: 2800 cmp r0, #0
  6027. 8002e2c: d169 bne.n 8002f02 <HAL_UART_MspInit+0x112>
  6028. __HAL_RCC_UART8_CLK_ENABLE();
  6029. 8002e2e: 4b40 ldr r3, [pc, #256] @ (8002f30 <HAL_UART_MspInit+0x140>)
  6030. GPIO_InitStruct.Alternate = GPIO_AF8_UART8;
  6031. 8002e30: 2408 movs r4, #8
  6032. HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
  6033. 8002e32: a904 add r1, sp, #16
  6034. 8002e34: 483f ldr r0, [pc, #252] @ (8002f34 <HAL_UART_MspInit+0x144>)
  6035. __HAL_RCC_UART8_CLK_ENABLE();
  6036. 8002e36: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8
  6037. 8002e3a: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000
  6038. 8002e3e: f8c3 20e8 str.w r2, [r3, #232] @ 0xe8
  6039. 8002e42: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8
  6040. 8002e46: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000
  6041. 8002e4a: 9200 str r2, [sp, #0]
  6042. 8002e4c: 9a00 ldr r2, [sp, #0]
  6043. __HAL_RCC_GPIOE_CLK_ENABLE();
  6044. 8002e4e: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  6045. 8002e52: f042 0210 orr.w r2, r2, #16
  6046. GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
  6047. 8002e56: ed9f 7b2e vldr d7, [pc, #184] @ 8002f10 <HAL_UART_MspInit+0x120>
  6048. __HAL_RCC_GPIOE_CLK_ENABLE();
  6049. 8002e5a: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  6050. 8002e5e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
  6051. GPIO_InitStruct.Alternate = GPIO_AF8_UART8;
  6052. 8002e62: 9408 str r4, [sp, #32]
  6053. __HAL_RCC_GPIOE_CLK_ENABLE();
  6054. 8002e64: f003 0310 and.w r3, r3, #16
  6055. GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
  6056. 8002e68: ed8d 7b04 vstr d7, [sp, #16]
  6057. 8002e6c: ed9f 7b2a vldr d7, [pc, #168] @ 8002f18 <HAL_UART_MspInit+0x128>
  6058. __HAL_RCC_GPIOE_CLK_ENABLE();
  6059. 8002e70: 9301 str r3, [sp, #4]
  6060. 8002e72: 9b01 ldr r3, [sp, #4]
  6061. GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
  6062. 8002e74: ed8d 7b06 vstr d7, [sp, #24]
  6063. HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
  6064. 8002e78: f004 f858 bl 8006f2c <HAL_GPIO_Init>
  6065. HAL_NVIC_SetPriority(UART8_IRQn, 5, 0);
  6066. 8002e7c: 2200 movs r2, #0
  6067. 8002e7e: 2105 movs r1, #5
  6068. 8002e80: 2053 movs r0, #83 @ 0x53
  6069. 8002e82: f002 f859 bl 8004f38 <HAL_NVIC_SetPriority>
  6070. HAL_NVIC_EnableIRQ(UART8_IRQn);
  6071. 8002e86: 2053 movs r0, #83 @ 0x53
  6072. 8002e88: f002 f892 bl 8004fb0 <HAL_NVIC_EnableIRQ>
  6073. }
  6074. 8002e8c: b03a add sp, #232 @ 0xe8
  6075. 8002e8e: bd10 pop {r4, pc}
  6076. PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
  6077. 8002e90: 2201 movs r2, #1
  6078. 8002e92: 2300 movs r3, #0
  6079. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
  6080. 8002e94: a80a add r0, sp, #40 @ 0x28
  6081. PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
  6082. 8002e96: e9cd 230a strd r2, r3, [sp, #40] @ 0x28
  6083. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
  6084. 8002e9a: f005 f9a1 bl 80081e0 <HAL_RCCEx_PeriphCLKConfig>
  6085. 8002e9e: bb98 cbnz r0, 8002f08 <HAL_UART_MspInit+0x118>
  6086. __HAL_RCC_USART1_CLK_ENABLE();
  6087. 8002ea0: 4b23 ldr r3, [pc, #140] @ (8002f30 <HAL_UART_MspInit+0x140>)
  6088. GPIO_InitStruct.Alternate = GPIO_AF4_USART1;
  6089. 8002ea2: 2404 movs r4, #4
  6090. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  6091. 8002ea4: a904 add r1, sp, #16
  6092. 8002ea6: 4824 ldr r0, [pc, #144] @ (8002f38 <HAL_UART_MspInit+0x148>)
  6093. __HAL_RCC_USART1_CLK_ENABLE();
  6094. 8002ea8: f8d3 20f0 ldr.w r2, [r3, #240] @ 0xf0
  6095. 8002eac: f042 0210 orr.w r2, r2, #16
  6096. 8002eb0: f8c3 20f0 str.w r2, [r3, #240] @ 0xf0
  6097. 8002eb4: f8d3 20f0 ldr.w r2, [r3, #240] @ 0xf0
  6098. 8002eb8: f002 0210 and.w r2, r2, #16
  6099. 8002ebc: 9202 str r2, [sp, #8]
  6100. 8002ebe: 9a02 ldr r2, [sp, #8]
  6101. __HAL_RCC_GPIOB_CLK_ENABLE();
  6102. 8002ec0: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
  6103. 8002ec4: f042 0202 orr.w r2, r2, #2
  6104. GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
  6105. 8002ec8: ed9f 7b15 vldr d7, [pc, #84] @ 8002f20 <HAL_UART_MspInit+0x130>
  6106. __HAL_RCC_GPIOB_CLK_ENABLE();
  6107. 8002ecc: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
  6108. 8002ed0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
  6109. GPIO_InitStruct.Alternate = GPIO_AF4_USART1;
  6110. 8002ed4: 9408 str r4, [sp, #32]
  6111. __HAL_RCC_GPIOB_CLK_ENABLE();
  6112. 8002ed6: f003 0302 and.w r3, r3, #2
  6113. GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
  6114. 8002eda: ed8d 7b04 vstr d7, [sp, #16]
  6115. 8002ede: ed9f 7b0e vldr d7, [pc, #56] @ 8002f18 <HAL_UART_MspInit+0x128>
  6116. __HAL_RCC_GPIOB_CLK_ENABLE();
  6117. 8002ee2: 9303 str r3, [sp, #12]
  6118. 8002ee4: 9b03 ldr r3, [sp, #12]
  6119. GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
  6120. 8002ee6: ed8d 7b06 vstr d7, [sp, #24]
  6121. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  6122. 8002eea: f004 f81f bl 8006f2c <HAL_GPIO_Init>
  6123. HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
  6124. 8002eee: 2200 movs r2, #0
  6125. 8002ef0: 2105 movs r1, #5
  6126. 8002ef2: 2025 movs r0, #37 @ 0x25
  6127. 8002ef4: f002 f820 bl 8004f38 <HAL_NVIC_SetPriority>
  6128. HAL_NVIC_EnableIRQ(USART1_IRQn);
  6129. 8002ef8: 2025 movs r0, #37 @ 0x25
  6130. 8002efa: f002 f859 bl 8004fb0 <HAL_NVIC_EnableIRQ>
  6131. }
  6132. 8002efe: b03a add sp, #232 @ 0xe8
  6133. 8002f00: bd10 pop {r4, pc}
  6134. Error_Handler();
  6135. 8002f02: f7fd fc79 bl 80007f8 <Error_Handler>
  6136. 8002f06: e792 b.n 8002e2e <HAL_UART_MspInit+0x3e>
  6137. Error_Handler();
  6138. 8002f08: f7fd fc76 bl 80007f8 <Error_Handler>
  6139. 8002f0c: e7c8 b.n 8002ea0 <HAL_UART_MspInit+0xb0>
  6140. 8002f0e: bf00 nop
  6141. 8002f10: 00000003 .word 0x00000003
  6142. 8002f14: 00000002 .word 0x00000002
  6143. ...
  6144. 8002f20: 0000c000 .word 0x0000c000
  6145. 8002f24: 00000002 .word 0x00000002
  6146. 8002f28: 40007c00 .word 0x40007c00
  6147. 8002f2c: 40011000 .word 0x40011000
  6148. 8002f30: 58024400 .word 0x58024400
  6149. 8002f34: 58021000 .word 0x58021000
  6150. 8002f38: 58020400 .word 0x58020400
  6151. 08002f3c <HAL_InitTick>:
  6152. uint32_t uwTimclock, uwAPB1Prescaler;
  6153. uint32_t uwPrescalerValue;
  6154. uint32_t pFLatency;
  6155. /*Configure the TIM6 IRQ priority */
  6156. if (TickPriority < (1UL << __NVIC_PRIO_BITS))
  6157. 8002f3c: 280f cmp r0, #15
  6158. 8002f3e: d901 bls.n 8002f44 <HAL_InitTick+0x8>
  6159. HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
  6160. uwTickPrio = TickPriority;
  6161. }
  6162. else
  6163. {
  6164. return HAL_ERROR;
  6165. 8002f40: 2001 movs r0, #1
  6166. return HAL_TIM_Base_Start_IT(&htim6);
  6167. }
  6168. /* Return function status */
  6169. return HAL_ERROR;
  6170. }
  6171. 8002f42: 4770 bx lr
  6172. {
  6173. 8002f44: b530 push {r4, r5, lr}
  6174. HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
  6175. 8002f46: 4601 mov r1, r0
  6176. {
  6177. 8002f48: b08b sub sp, #44 @ 0x2c
  6178. HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
  6179. 8002f4a: 2200 movs r2, #0
  6180. 8002f4c: 4604 mov r4, r0
  6181. 8002f4e: 2036 movs r0, #54 @ 0x36
  6182. 8002f50: f001 fff2 bl 8004f38 <HAL_NVIC_SetPriority>
  6183. HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
  6184. 8002f54: 2036 movs r0, #54 @ 0x36
  6185. 8002f56: f002 f82b bl 8004fb0 <HAL_NVIC_EnableIRQ>
  6186. __HAL_RCC_TIM6_CLK_ENABLE();
  6187. 8002f5a: 4b1b ldr r3, [pc, #108] @ (8002fc8 <HAL_InitTick+0x8c>)
  6188. uwTickPrio = TickPriority;
  6189. 8002f5c: 4a1b ldr r2, [pc, #108] @ (8002fcc <HAL_InitTick+0x90>)
  6190. HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
  6191. 8002f5e: 4669 mov r1, sp
  6192. 8002f60: a802 add r0, sp, #8
  6193. uwTickPrio = TickPriority;
  6194. 8002f62: 6014 str r4, [r2, #0]
  6195. __HAL_RCC_TIM6_CLK_ENABLE();
  6196. 8002f64: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8
  6197. 8002f68: f042 0210 orr.w r2, r2, #16
  6198. 8002f6c: f8c3 20e8 str.w r2, [r3, #232] @ 0xe8
  6199. 8002f70: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8
  6200. 8002f74: f003 0310 and.w r3, r3, #16
  6201. 8002f78: 9301 str r3, [sp, #4]
  6202. 8002f7a: 9b01 ldr r3, [sp, #4]
  6203. HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
  6204. 8002f7c: f005 f820 bl 8007fc0 <HAL_RCC_GetClockConfig>
  6205. if (uwAPB1Prescaler == RCC_HCLK_DIV1)
  6206. 8002f80: 9b07 ldr r3, [sp, #28]
  6207. 8002f82: b9c3 cbnz r3, 8002fb6 <HAL_InitTick+0x7a>
  6208. uwTimclock = HAL_RCC_GetPCLK1Freq();
  6209. 8002f84: f004 ff8c bl 8007ea0 <HAL_RCC_GetPCLK1Freq>
  6210. 8002f88: 4603 mov r3, r0
  6211. uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
  6212. 8002f8a: 4911 ldr r1, [pc, #68] @ (8002fd0 <HAL_InitTick+0x94>)
  6213. htim6.Init.ClockDivision = 0;
  6214. 8002f8c: 2200 movs r2, #0
  6215. htim6.Instance = TIM6;
  6216. 8002f8e: 4c11 ldr r4, [pc, #68] @ (8002fd4 <HAL_InitTick+0x98>)
  6217. uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
  6218. 8002f90: fba1 1303 umull r1, r3, r1, r3
  6219. htim6.Instance = TIM6;
  6220. 8002f94: 4d10 ldr r5, [pc, #64] @ (8002fd8 <HAL_InitTick+0x9c>)
  6221. htim6.Init.Period = (1000000U / 1000U) - 1U;
  6222. 8002f96: f240 31e7 movw r1, #999 @ 0x3e7
  6223. if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
  6224. 8002f9a: 4620 mov r0, r4
  6225. uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
  6226. 8002f9c: 0c9b lsrs r3, r3, #18
  6227. htim6.Instance = TIM6;
  6228. 8002f9e: 6025 str r5, [r4, #0]
  6229. htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
  6230. 8002fa0: 60a2 str r2, [r4, #8]
  6231. uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
  6232. 8002fa2: 3b01 subs r3, #1
  6233. htim6.Init.Period = (1000000U / 1000U) - 1U;
  6234. 8002fa4: e9c4 1203 strd r1, r2, [r4, #12]
  6235. htim6.Init.Prescaler = uwPrescalerValue;
  6236. 8002fa8: 6063 str r3, [r4, #4]
  6237. if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
  6238. 8002faa: f006 fcc9 bl 8009940 <HAL_TIM_Base_Init>
  6239. 8002fae: b130 cbz r0, 8002fbe <HAL_InitTick+0x82>
  6240. return HAL_ERROR;
  6241. 8002fb0: 2001 movs r0, #1
  6242. }
  6243. 8002fb2: b00b add sp, #44 @ 0x2c
  6244. 8002fb4: bd30 pop {r4, r5, pc}
  6245. uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
  6246. 8002fb6: f004 ff73 bl 8007ea0 <HAL_RCC_GetPCLK1Freq>
  6247. 8002fba: 0043 lsls r3, r0, #1
  6248. 8002fbc: e7e5 b.n 8002f8a <HAL_InitTick+0x4e>
  6249. return HAL_TIM_Base_Start_IT(&htim6);
  6250. 8002fbe: 4620 mov r0, r4
  6251. 8002fc0: f006 fdb2 bl 8009b28 <HAL_TIM_Base_Start_IT>
  6252. 8002fc4: e7f5 b.n 8002fb2 <HAL_InitTick+0x76>
  6253. 8002fc6: bf00 nop
  6254. 8002fc8: 58024400 .word 0x58024400
  6255. 8002fcc: 24000040 .word 0x24000040
  6256. 8002fd0: 431bde83 .word 0x431bde83
  6257. 8002fd4: 24000a68 .word 0x24000a68
  6258. 8002fd8: 40001000 .word 0x40001000
  6259. 08002fdc <NMI_Handler>:
  6260. {
  6261. /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
  6262. /* USER CODE END NonMaskableInt_IRQn 0 */
  6263. /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  6264. while (1)
  6265. 8002fdc: e7fe b.n 8002fdc <NMI_Handler>
  6266. 8002fde: bf00 nop
  6267. 08002fe0 <HardFault_Handler>:
  6268. void HardFault_Handler(void)
  6269. {
  6270. /* USER CODE BEGIN HardFault_IRQn 0 */
  6271. /* USER CODE END HardFault_IRQn 0 */
  6272. while (1)
  6273. 8002fe0: e7fe b.n 8002fe0 <HardFault_Handler>
  6274. 8002fe2: bf00 nop
  6275. 08002fe4 <MemManage_Handler>:
  6276. void MemManage_Handler(void)
  6277. {
  6278. /* USER CODE BEGIN MemoryManagement_IRQn 0 */
  6279. /* USER CODE END MemoryManagement_IRQn 0 */
  6280. while (1)
  6281. 8002fe4: e7fe b.n 8002fe4 <MemManage_Handler>
  6282. 8002fe6: bf00 nop
  6283. 08002fe8 <BusFault_Handler>:
  6284. void BusFault_Handler(void)
  6285. {
  6286. /* USER CODE BEGIN BusFault_IRQn 0 */
  6287. /* USER CODE END BusFault_IRQn 0 */
  6288. while (1)
  6289. 8002fe8: e7fe b.n 8002fe8 <BusFault_Handler>
  6290. 8002fea: bf00 nop
  6291. 08002fec <UsageFault_Handler>:
  6292. void UsageFault_Handler(void)
  6293. {
  6294. /* USER CODE BEGIN UsageFault_IRQn 0 */
  6295. /* USER CODE END UsageFault_IRQn 0 */
  6296. while (1)
  6297. 8002fec: e7fe b.n 8002fec <UsageFault_Handler>
  6298. 8002fee: bf00 nop
  6299. 08002ff0 <DebugMon_Handler>:
  6300. /* USER CODE END DebugMonitor_IRQn 0 */
  6301. /* USER CODE BEGIN DebugMonitor_IRQn 1 */
  6302. /* USER CODE END DebugMonitor_IRQn 1 */
  6303. }
  6304. 8002ff0: 4770 bx lr
  6305. 8002ff2: bf00 nop
  6306. 08002ff4 <RCC_IRQHandler>:
  6307. /******************************************************************************/
  6308. /**
  6309. * @brief This function handles RCC global interrupt.
  6310. */
  6311. void RCC_IRQHandler(void)
  6312. 8002ff4: 4770 bx lr
  6313. 8002ff6: bf00 nop
  6314. 08002ff8 <DMA1_Stream0_IRQHandler>:
  6315. void DMA1_Stream0_IRQHandler(void)
  6316. {
  6317. /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
  6318. /* USER CODE END DMA1_Stream0_IRQn 0 */
  6319. HAL_DMA_IRQHandler(&hdma_adc1);
  6320. 8002ff8: 4801 ldr r0, [pc, #4] @ (8003000 <DMA1_Stream0_IRQHandler+0x8>)
  6321. 8002ffa: f003 bc43 b.w 8006884 <HAL_DMA_IRQHandler>
  6322. 8002ffe: bf00 nop
  6323. 8003000: 24000710 .word 0x24000710
  6324. 08003004 <DMA1_Stream1_IRQHandler>:
  6325. void DMA1_Stream1_IRQHandler(void)
  6326. {
  6327. /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
  6328. /* USER CODE END DMA1_Stream1_IRQn 0 */
  6329. HAL_DMA_IRQHandler(&hdma_adc2);
  6330. 8003004: 4801 ldr r0, [pc, #4] @ (800300c <DMA1_Stream1_IRQHandler+0x8>)
  6331. 8003006: f003 bc3d b.w 8006884 <HAL_DMA_IRQHandler>
  6332. 800300a: bf00 nop
  6333. 800300c: 24000698 .word 0x24000698
  6334. 08003010 <DMA1_Stream2_IRQHandler>:
  6335. void DMA1_Stream2_IRQHandler(void)
  6336. {
  6337. /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */
  6338. /* USER CODE END DMA1_Stream2_IRQn 0 */
  6339. HAL_DMA_IRQHandler(&hdma_adc3);
  6340. 8003010: 4801 ldr r0, [pc, #4] @ (8003018 <DMA1_Stream2_IRQHandler+0x8>)
  6341. 8003012: f003 bc37 b.w 8006884 <HAL_DMA_IRQHandler>
  6342. 8003016: bf00 nop
  6343. 8003018: 24000620 .word 0x24000620
  6344. 0800301c <USART1_IRQHandler>:
  6345. void USART1_IRQHandler(void)
  6346. {
  6347. /* USER CODE BEGIN USART1_IRQn 0 */
  6348. /* USER CODE END USART1_IRQn 0 */
  6349. HAL_UART_IRQHandler(&huart1);
  6350. 800301c: 4801 ldr r0, [pc, #4] @ (8003024 <USART1_IRQHandler+0x8>)
  6351. 800301e: f007 bc7d b.w 800a91c <HAL_UART_IRQHandler>
  6352. 8003022: bf00 nop
  6353. 8003024: 2400038c .word 0x2400038c
  6354. 08003028 <EXTI15_10_IRQHandler>:
  6355. /**
  6356. * @brief This function handles EXTI line[15:10] interrupts.
  6357. */
  6358. void EXTI15_10_IRQHandler(void)
  6359. {
  6360. 8003028: b508 push {r3, lr}
  6361. /* USER CODE BEGIN EXTI15_10_IRQn 0 */
  6362. /* USER CODE END EXTI15_10_IRQn 0 */
  6363. HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
  6364. 800302a: f44f 6080 mov.w r0, #1024 @ 0x400
  6365. 800302e: f004 f8d3 bl 80071d8 <HAL_GPIO_EXTI_IRQHandler>
  6366. HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
  6367. 8003032: f44f 6000 mov.w r0, #2048 @ 0x800
  6368. 8003036: f004 f8cf bl 80071d8 <HAL_GPIO_EXTI_IRQHandler>
  6369. HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
  6370. 800303a: f44f 4080 mov.w r0, #16384 @ 0x4000
  6371. 800303e: f004 f8cb bl 80071d8 <HAL_GPIO_EXTI_IRQHandler>
  6372. HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
  6373. 8003042: f44f 4000 mov.w r0, #32768 @ 0x8000
  6374. /* USER CODE BEGIN EXTI15_10_IRQn 1 */
  6375. /* USER CODE END EXTI15_10_IRQn 1 */
  6376. }
  6377. 8003046: e8bd 4008 ldmia.w sp!, {r3, lr}
  6378. HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
  6379. 800304a: f004 b8c5 b.w 80071d8 <HAL_GPIO_EXTI_IRQHandler>
  6380. 800304e: bf00 nop
  6381. 08003050 <TIM6_DAC_IRQHandler>:
  6382. void TIM6_DAC_IRQHandler(void)
  6383. {
  6384. /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
  6385. /* USER CODE END TIM6_DAC_IRQn 0 */
  6386. if (hdac1.State != HAL_DAC_STATE_RESET) {
  6387. 8003050: 4807 ldr r0, [pc, #28] @ (8003070 <TIM6_DAC_IRQHandler+0x20>)
  6388. {
  6389. 8003052: b508 push {r3, lr}
  6390. if (hdac1.State != HAL_DAC_STATE_RESET) {
  6391. 8003054: 7903 ldrb r3, [r0, #4]
  6392. 8003056: b923 cbnz r3, 8003062 <TIM6_DAC_IRQHandler+0x12>
  6393. HAL_DAC_IRQHandler(&hdac1);
  6394. }
  6395. HAL_TIM_IRQHandler(&htim6);
  6396. 8003058: 4806 ldr r0, [pc, #24] @ (8003074 <TIM6_DAC_IRQHandler+0x24>)
  6397. /* USER CODE BEGIN TIM6_DAC_IRQn 1 */
  6398. /* USER CODE END TIM6_DAC_IRQn 1 */
  6399. }
  6400. 800305a: e8bd 4008 ldmia.w sp!, {r3, lr}
  6401. HAL_TIM_IRQHandler(&htim6);
  6402. 800305e: f007 b849 b.w 800a0f4 <HAL_TIM_IRQHandler>
  6403. HAL_DAC_IRQHandler(&hdac1);
  6404. 8003062: f002 f95f bl 8005324 <HAL_DAC_IRQHandler>
  6405. HAL_TIM_IRQHandler(&htim6);
  6406. 8003066: 4803 ldr r0, [pc, #12] @ (8003074 <TIM6_DAC_IRQHandler+0x24>)
  6407. }
  6408. 8003068: e8bd 4008 ldmia.w sp!, {r3, lr}
  6409. HAL_TIM_IRQHandler(&htim6);
  6410. 800306c: f007 b842 b.w 800a0f4 <HAL_TIM_IRQHandler>
  6411. 8003070: 240005bc .word 0x240005bc
  6412. 8003074: 24000a68 .word 0x24000a68
  6413. 08003078 <UART8_IRQHandler>:
  6414. void UART8_IRQHandler(void)
  6415. {
  6416. /* USER CODE BEGIN UART8_IRQn 0 */
  6417. /* USER CODE END UART8_IRQn 0 */
  6418. HAL_UART_IRQHandler(&huart8);
  6419. 8003078: 4801 ldr r0, [pc, #4] @ (8003080 <UART8_IRQHandler+0x8>)
  6420. 800307a: f007 bc4f b.w 800a91c <HAL_UART_IRQHandler>
  6421. 800307e: bf00 nop
  6422. 8003080: 24000420 .word 0x24000420
  6423. 08003084 <_getpid>:
  6424. }
  6425. int _getpid(void)
  6426. {
  6427. return 1;
  6428. }
  6429. 8003084: 2001 movs r0, #1
  6430. 8003086: 4770 bx lr
  6431. 08003088 <_kill>:
  6432. int _kill(int pid, int sig)
  6433. {
  6434. 8003088: b508 push {r3, lr}
  6435. (void)pid;
  6436. (void)sig;
  6437. errno = EINVAL;
  6438. 800308a: f00c fde5 bl 800fc58 <__errno>
  6439. 800308e: 2216 movs r2, #22
  6440. 8003090: 4603 mov r3, r0
  6441. return -1;
  6442. }
  6443. 8003092: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  6444. errno = EINVAL;
  6445. 8003096: 601a str r2, [r3, #0]
  6446. }
  6447. 8003098: bd08 pop {r3, pc}
  6448. 800309a: bf00 nop
  6449. 0800309c <_exit>:
  6450. void _exit (int status)
  6451. {
  6452. 800309c: b508 push {r3, lr}
  6453. errno = EINVAL;
  6454. 800309e: f00c fddb bl 800fc58 <__errno>
  6455. 80030a2: 2316 movs r3, #22
  6456. 80030a4: 6003 str r3, [r0, #0]
  6457. _kill(status, -1);
  6458. while (1) {} /* Make sure we hang here */
  6459. 80030a6: e7fe b.n 80030a6 <_exit+0xa>
  6460. 080030a8 <_read>:
  6461. }
  6462. __attribute__((weak)) int _read(int file, char *ptr, int len)
  6463. {
  6464. 80030a8: b570 push {r4, r5, r6, lr}
  6465. (void)file;
  6466. int DataIdx;
  6467. for (DataIdx = 0; DataIdx < len; DataIdx++)
  6468. 80030aa: 1e16 subs r6, r2, #0
  6469. 80030ac: dd07 ble.n 80030be <_read+0x16>
  6470. 80030ae: 460c mov r4, r1
  6471. 80030b0: 198d adds r5, r1, r6
  6472. {
  6473. *ptr++ = __io_getchar();
  6474. 80030b2: f3af 8000 nop.w
  6475. 80030b6: f804 0b01 strb.w r0, [r4], #1
  6476. for (DataIdx = 0; DataIdx < len; DataIdx++)
  6477. 80030ba: 42a5 cmp r5, r4
  6478. 80030bc: d1f9 bne.n 80030b2 <_read+0xa>
  6479. }
  6480. return len;
  6481. }
  6482. 80030be: 4630 mov r0, r6
  6483. 80030c0: bd70 pop {r4, r5, r6, pc}
  6484. 80030c2: bf00 nop
  6485. 080030c4 <_write>:
  6486. __attribute__((weak)) int _write(int file, char *ptr, int len)
  6487. {
  6488. 80030c4: b570 push {r4, r5, r6, lr}
  6489. (void)file;
  6490. int DataIdx;
  6491. for (DataIdx = 0; DataIdx < len; DataIdx++)
  6492. 80030c6: 1e16 subs r6, r2, #0
  6493. 80030c8: dd07 ble.n 80030da <_write+0x16>
  6494. 80030ca: 460c mov r4, r1
  6495. 80030cc: 198d adds r5, r1, r6
  6496. {
  6497. __io_putchar(*ptr++);
  6498. 80030ce: f814 0b01 ldrb.w r0, [r4], #1
  6499. 80030d2: f7fd fb19 bl 8000708 <__io_putchar>
  6500. for (DataIdx = 0; DataIdx < len; DataIdx++)
  6501. 80030d6: 42ac cmp r4, r5
  6502. 80030d8: d1f9 bne.n 80030ce <_write+0xa>
  6503. }
  6504. return len;
  6505. }
  6506. 80030da: 4630 mov r0, r6
  6507. 80030dc: bd70 pop {r4, r5, r6, pc}
  6508. 80030de: bf00 nop
  6509. 080030e0 <_close>:
  6510. int _close(int file)
  6511. {
  6512. (void)file;
  6513. return -1;
  6514. }
  6515. 80030e0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  6516. 80030e4: 4770 bx lr
  6517. 80030e6: bf00 nop
  6518. 080030e8 <_fstat>:
  6519. int _fstat(int file, struct stat *st)
  6520. {
  6521. (void)file;
  6522. st->st_mode = S_IFCHR;
  6523. 80030e8: f44f 5300 mov.w r3, #8192 @ 0x2000
  6524. return 0;
  6525. }
  6526. 80030ec: 2000 movs r0, #0
  6527. st->st_mode = S_IFCHR;
  6528. 80030ee: 604b str r3, [r1, #4]
  6529. }
  6530. 80030f0: 4770 bx lr
  6531. 80030f2: bf00 nop
  6532. 080030f4 <_isatty>:
  6533. int _isatty(int file)
  6534. {
  6535. (void)file;
  6536. return 1;
  6537. }
  6538. 80030f4: 2001 movs r0, #1
  6539. 80030f6: 4770 bx lr
  6540. 080030f8 <_lseek>:
  6541. {
  6542. (void)file;
  6543. (void)ptr;
  6544. (void)dir;
  6545. return 0;
  6546. }
  6547. 80030f8: 2000 movs r0, #0
  6548. 80030fa: 4770 bx lr
  6549. 080030fc <_sbrk>:
  6550. const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
  6551. const uint8_t *max_heap = (uint8_t *)stack_limit;
  6552. uint8_t *prev_heap_end;
  6553. /* Initialize heap end at first call */
  6554. if (NULL == __sbrk_heap_end)
  6555. 80030fc: 490d ldr r1, [pc, #52] @ (8003134 <_sbrk+0x38>)
  6556. {
  6557. 80030fe: 4603 mov r3, r0
  6558. const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
  6559. 8003100: 4a0d ldr r2, [pc, #52] @ (8003138 <_sbrk+0x3c>)
  6560. if (NULL == __sbrk_heap_end)
  6561. 8003102: 6808 ldr r0, [r1, #0]
  6562. {
  6563. 8003104: b510 push {r4, lr}
  6564. const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
  6565. 8003106: 4c0d ldr r4, [pc, #52] @ (800313c <_sbrk+0x40>)
  6566. 8003108: 1b12 subs r2, r2, r4
  6567. if (NULL == __sbrk_heap_end)
  6568. 800310a: b120 cbz r0, 8003116 <_sbrk+0x1a>
  6569. {
  6570. __sbrk_heap_end = &_end;
  6571. }
  6572. /* Protect heap from growing into the reserved MSP stack */
  6573. if (__sbrk_heap_end + incr > max_heap)
  6574. 800310c: 4403 add r3, r0
  6575. 800310e: 4293 cmp r3, r2
  6576. 8003110: d807 bhi.n 8003122 <_sbrk+0x26>
  6577. errno = ENOMEM;
  6578. return (void *)-1;
  6579. }
  6580. prev_heap_end = __sbrk_heap_end;
  6581. __sbrk_heap_end += incr;
  6582. 8003112: 600b str r3, [r1, #0]
  6583. return (void *)prev_heap_end;
  6584. }
  6585. 8003114: bd10 pop {r4, pc}
  6586. __sbrk_heap_end = &_end;
  6587. 8003116: 4c0a ldr r4, [pc, #40] @ (8003140 <_sbrk+0x44>)
  6588. 8003118: 4620 mov r0, r4
  6589. 800311a: 600c str r4, [r1, #0]
  6590. if (__sbrk_heap_end + incr > max_heap)
  6591. 800311c: 4403 add r3, r0
  6592. 800311e: 4293 cmp r3, r2
  6593. 8003120: d9f7 bls.n 8003112 <_sbrk+0x16>
  6594. errno = ENOMEM;
  6595. 8003122: f00c fd99 bl 800fc58 <__errno>
  6596. 8003126: 220c movs r2, #12
  6597. 8003128: 4603 mov r3, r0
  6598. return (void *)-1;
  6599. 800312a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  6600. errno = ENOMEM;
  6601. 800312e: 601a str r2, [r3, #0]
  6602. }
  6603. 8003130: bd10 pop {r4, pc}
  6604. 8003132: bf00 nop
  6605. 8003134: 24000ab4 .word 0x24000ab4
  6606. 8003138: 24060000 .word 0x24060000
  6607. 800313c: 00000400 .word 0x00000400
  6608. 8003140: 240132e8 .word 0x240132e8
  6609. 08003144 <SystemInit>:
  6610. __IO uint32_t tmpreg;
  6611. #endif /* DATA_IN_D2_SRAM */
  6612. /* FPU settings ------------------------------------------------------------*/
  6613. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  6614. SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
  6615. 8003144: 4927 ldr r1, [pc, #156] @ (80031e4 <SystemInit+0xa0>)
  6616. #endif
  6617. /* Reset the RCC clock configuration to the default reset state ------------*/
  6618. /* Increasing the CPU frequency */
  6619. if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
  6620. 8003146: 4a28 ldr r2, [pc, #160] @ (80031e8 <SystemInit+0xa4>)
  6621. SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
  6622. 8003148: f8d1 3088 ldr.w r3, [r1, #136] @ 0x88
  6623. 800314c: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
  6624. {
  6625. 8003150: b410 push {r4}
  6626. SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
  6627. 8003152: f8c1 3088 str.w r3, [r1, #136] @ 0x88
  6628. if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
  6629. 8003156: 6813 ldr r3, [r2, #0]
  6630. 8003158: f003 030f and.w r3, r3, #15
  6631. 800315c: 2b06 cmp r3, #6
  6632. 800315e: d805 bhi.n 800316c <SystemInit+0x28>
  6633. {
  6634. /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  6635. MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
  6636. 8003160: 6813 ldr r3, [r2, #0]
  6637. 8003162: f023 030f bic.w r3, r3, #15
  6638. 8003166: f043 0307 orr.w r3, r3, #7
  6639. 800316a: 6013 str r3, [r2, #0]
  6640. }
  6641. /* Set HSION bit */
  6642. RCC->CR |= RCC_CR_HSION;
  6643. 800316c: 4b1f ldr r3, [pc, #124] @ (80031ec <SystemInit+0xa8>)
  6644. /* Reset CFGR register */
  6645. RCC->CFGR = 0x00000000;
  6646. 800316e: 2400 movs r4, #0
  6647. /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
  6648. RCC->CR &= 0xEAF6ED7FU;
  6649. 8003170: 4a1f ldr r2, [pc, #124] @ (80031f0 <SystemInit+0xac>)
  6650. RCC->CR |= RCC_CR_HSION;
  6651. 8003172: 6819 ldr r1, [r3, #0]
  6652. /* Decreasing the number of wait states because of lower CPU frequency */
  6653. if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
  6654. 8003174: 481c ldr r0, [pc, #112] @ (80031e8 <SystemInit+0xa4>)
  6655. RCC->CR |= RCC_CR_HSION;
  6656. 8003176: f041 0101 orr.w r1, r1, #1
  6657. 800317a: 6019 str r1, [r3, #0]
  6658. RCC->CFGR = 0x00000000;
  6659. 800317c: 611c str r4, [r3, #16]
  6660. RCC->CR &= 0xEAF6ED7FU;
  6661. 800317e: 6819 ldr r1, [r3, #0]
  6662. 8003180: 400a ands r2, r1
  6663. 8003182: 601a str r2, [r3, #0]
  6664. if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
  6665. 8003184: 6803 ldr r3, [r0, #0]
  6666. 8003186: 071b lsls r3, r3, #28
  6667. 8003188: d505 bpl.n 8003196 <SystemInit+0x52>
  6668. {
  6669. /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  6670. MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
  6671. 800318a: 6803 ldr r3, [r0, #0]
  6672. 800318c: f023 030f bic.w r3, r3, #15
  6673. 8003190: f043 0307 orr.w r3, r3, #7
  6674. 8003194: 6003 str r3, [r0, #0]
  6675. }
  6676. #if defined(D3_SRAM_BASE)
  6677. /* Reset D1CFGR register */
  6678. RCC->D1CFGR = 0x00000000;
  6679. 8003196: 4b15 ldr r3, [pc, #84] @ (80031ec <SystemInit+0xa8>)
  6680. 8003198: 2200 movs r2, #0
  6681. RCC->PLLCKSELR = 0x02020200;
  6682. /* Reset PLLCFGR register */
  6683. RCC->PLLCFGR = 0x01FF0000;
  6684. /* Reset PLL1DIVR register */
  6685. RCC->PLL1DIVR = 0x01010280;
  6686. 800319a: 4916 ldr r1, [pc, #88] @ (80031f4 <SystemInit+0xb0>)
  6687. RCC->PLLCKSELR = 0x02020200;
  6688. 800319c: 4c16 ldr r4, [pc, #88] @ (80031f8 <SystemInit+0xb4>)
  6689. RCC->PLLCFGR = 0x01FF0000;
  6690. 800319e: 4817 ldr r0, [pc, #92] @ (80031fc <SystemInit+0xb8>)
  6691. RCC->D1CFGR = 0x00000000;
  6692. 80031a0: 619a str r2, [r3, #24]
  6693. RCC->D2CFGR = 0x00000000;
  6694. 80031a2: 61da str r2, [r3, #28]
  6695. RCC->D3CFGR = 0x00000000;
  6696. 80031a4: 621a str r2, [r3, #32]
  6697. RCC->PLLCKSELR = 0x02020200;
  6698. 80031a6: 629c str r4, [r3, #40] @ 0x28
  6699. RCC->PLLCFGR = 0x01FF0000;
  6700. 80031a8: 62d8 str r0, [r3, #44] @ 0x2c
  6701. RCC->PLL1DIVR = 0x01010280;
  6702. 80031aa: 6319 str r1, [r3, #48] @ 0x30
  6703. /* Reset PLL1FRACR register */
  6704. RCC->PLL1FRACR = 0x00000000;
  6705. 80031ac: 635a str r2, [r3, #52] @ 0x34
  6706. /* Reset PLL2DIVR register */
  6707. RCC->PLL2DIVR = 0x01010280;
  6708. 80031ae: 6399 str r1, [r3, #56] @ 0x38
  6709. /* Reset PLL2FRACR register */
  6710. RCC->PLL2FRACR = 0x00000000;
  6711. 80031b0: 63da str r2, [r3, #60] @ 0x3c
  6712. /* Reset PLL3DIVR register */
  6713. RCC->PLL3DIVR = 0x01010280;
  6714. 80031b2: 6419 str r1, [r3, #64] @ 0x40
  6715. /* Reset PLL3FRACR register */
  6716. RCC->PLL3FRACR = 0x00000000;
  6717. 80031b4: 645a str r2, [r3, #68] @ 0x44
  6718. /* Reset HSEBYP bit */
  6719. RCC->CR &= 0xFFFBFFFFU;
  6720. 80031b6: 6818 ldr r0, [r3, #0]
  6721. /* Disable all interrupts */
  6722. RCC->CIER = 0x00000000;
  6723. #if (STM32H7_DEV_ID == 0x450UL)
  6724. /* dual core CM7 or single core line */
  6725. if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
  6726. 80031b8: 4c11 ldr r4, [pc, #68] @ (8003200 <SystemInit+0xbc>)
  6727. RCC->CR &= 0xFFFBFFFFU;
  6728. 80031ba: f420 2080 bic.w r0, r0, #262144 @ 0x40000
  6729. if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
  6730. 80031be: 4911 ldr r1, [pc, #68] @ (8003204 <SystemInit+0xc0>)
  6731. RCC->CR &= 0xFFFBFFFFU;
  6732. 80031c0: 6018 str r0, [r3, #0]
  6733. RCC->CIER = 0x00000000;
  6734. 80031c2: 661a str r2, [r3, #96] @ 0x60
  6735. if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
  6736. 80031c4: 6823 ldr r3, [r4, #0]
  6737. 80031c6: 4019 ands r1, r3
  6738. 80031c8: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000
  6739. 80031cc: d203 bcs.n 80031d6 <SystemInit+0x92>
  6740. {
  6741. /* if stm32h7 revY*/
  6742. /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
  6743. *((__IO uint32_t*)0x51008108) = 0x000000001U;
  6744. 80031ce: 4b0e ldr r3, [pc, #56] @ (8003208 <SystemInit+0xc4>)
  6745. 80031d0: 2201 movs r2, #1
  6746. 80031d2: f8c3 2108 str.w r2, [r3, #264] @ 0x108
  6747. /*
  6748. * Disable the FMC bank1 (enabled after reset).
  6749. * This, prevents CPU speculation access on this bank which blocks the use of FMC during
  6750. * 24us. During this time the others FMC master (such as LTDC) cannot use it!
  6751. */
  6752. FMC_Bank1_R->BTCR[0] = 0x000030D2;
  6753. 80031d6: 4b0d ldr r3, [pc, #52] @ (800320c <SystemInit+0xc8>)
  6754. 80031d8: f243 02d2 movw r2, #12498 @ 0x30d2
  6755. #if defined(USER_VECT_TAB_ADDRESS)
  6756. SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
  6757. #endif /* USER_VECT_TAB_ADDRESS */
  6758. #endif /*DUAL_CORE && CORE_CM4*/
  6759. }
  6760. 80031dc: f85d 4b04 ldr.w r4, [sp], #4
  6761. FMC_Bank1_R->BTCR[0] = 0x000030D2;
  6762. 80031e0: 601a str r2, [r3, #0]
  6763. }
  6764. 80031e2: 4770 bx lr
  6765. 80031e4: e000ed00 .word 0xe000ed00
  6766. 80031e8: 52002000 .word 0x52002000
  6767. 80031ec: 58024400 .word 0x58024400
  6768. 80031f0: eaf6ed7f .word 0xeaf6ed7f
  6769. 80031f4: 01010280 .word 0x01010280
  6770. 80031f8: 02020200 .word 0x02020200
  6771. 80031fc: 01ff0000 .word 0x01ff0000
  6772. 8003200: 5c001000 .word 0x5c001000
  6773. 8003204: ffff0000 .word 0xffff0000
  6774. 8003208: 51008000 .word 0x51008000
  6775. 800320c: 52004000 .word 0x52004000
  6776. 08003210 <UartRxTask>:
  6777. xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken);
  6778. HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
  6779. portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken);
  6780. }
  6781. void UartRxTask (void* argument) {
  6782. 8003210: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  6783. 8003214: b0c9 sub sp, #292 @ 0x124
  6784. 8003216: 4604 mov r4, r0
  6785. UartTaskData* uartTaskData = (UartTaskData*)argument;
  6786. SerialProtocolFrameData spFrameData = { 0 };
  6787. 8003218: f44f 7286 mov.w r2, #268 @ 0x10c
  6788. 800321c: 2100 movs r1, #0
  6789. 800321e: a805 add r0, sp, #20
  6790. 8003220: f8df a2a4 ldr.w sl, [pc, #676] @ 80034c8 <UartRxTask+0x2b8>
  6791. 8003224: f00c fc70 bl 800fb08 <memset>
  6792. uint32_t bytesRec = 0;
  6793. 8003228: 2000 movs r0, #0
  6794. uint16_t frameTotalLength = 0;
  6795. uint16_t dataToSend = 0;
  6796. portBASE_TYPE crcPass = pdFAIL;
  6797. portBASE_TYPE proceed = pdFALSE;
  6798. portBASE_TYPE frameTimeout = pdFAIL;
  6799. enum SerialReceiverStates receverState = srWaitForHeader;
  6800. 800322a: 4607 mov r7, r0
  6801. uint32_t bytesRec = 0;
  6802. 800322c: 9004 str r0, [sp, #16]
  6803. uartTaskData->rxDataBufferMutex = osMutexNew (NULL);
  6804. 800322e: f008 fda7 bl 800bd80 <osMutexNew>
  6805. HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
  6806. 8003232: 88a2 ldrh r2, [r4, #4]
  6807. uartTaskData->rxDataBufferMutex = osMutexNew (NULL);
  6808. 8003234: 6220 str r0, [r4, #32]
  6809. uint16_t frameTotalLength = 0;
  6810. 8003236: 46b8 mov r8, r7
  6811. HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
  6812. 8003238: 6821 ldr r1, [r4, #0]
  6813. while (pdTRUE) {
  6814. frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
  6815. 800323a: 46b9 mov r9, r7
  6816. HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
  6817. 800323c: 6b20 ldr r0, [r4, #48] @ 0x30
  6818. portBASE_TYPE crcPass = pdFAIL;
  6819. 800323e: 9703 str r7, [sp, #12]
  6820. HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
  6821. 8003240: f008 fc6c bl 800bb1c <HAL_UARTEx_ReceiveToIdle_IT>
  6822. frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
  6823. 8003244: 2100 movs r1, #0
  6824. 8003246: f44f 63fa mov.w r3, #2000 @ 0x7d0
  6825. 800324a: aa04 add r2, sp, #16
  6826. 800324c: 4608 mov r0, r1
  6827. 800324e: f00a fe5f bl 800df10 <xTaskNotifyWait>
  6828. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  6829. 8003252: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  6830. frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
  6831. 8003256: 4683 mov fp, r0
  6832. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  6833. 8003258: 6a20 ldr r0, [r4, #32]
  6834. 800325a: f008 fdd3 bl 800be04 <osMutexAcquire>
  6835. frameBytesCount = uartTaskData->frameBytesCount;
  6836. 800325e: 8ae5 ldrh r5, [r4, #22]
  6837. osMutexRelease (uartTaskData->rxDataBufferMutex);
  6838. 8003260: 6a20 ldr r0, [r4, #32]
  6839. 8003262: f008 fdf3 bl 800be4c <osMutexRelease>
  6840. if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) {
  6841. 8003266: 1e2e subs r6, r5, #0
  6842. 8003268: bf18 it ne
  6843. 800326a: 2601 movne r6, #1
  6844. 800326c: f1bb 0f00 cmp.w fp, #0
  6845. 8003270: d14d bne.n 800330e <UartRxTask+0xfe>
  6846. 8003272: 2e00 cmp r6, #0
  6847. 8003274: d048 beq.n 8003308 <UartRxTask+0xf8>
  6848. }
  6849. receverState = srFinish;
  6850. break;
  6851. case srFail:
  6852. dataToSend = 0;
  6853. if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) {
  6854. 8003276: 2d02 cmp r5, #2
  6855. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0);
  6856. 8003278: 68a0 ldr r0, [r4, #8]
  6857. 800327a: f8bd 1014 ldrh.w r1, [sp, #20]
  6858. 800327e: f89d 2016 ldrb.w r2, [sp, #22]
  6859. if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) {
  6860. 8003282: f200 80f7 bhi.w 8003474 <UartRxTask+0x264>
  6861. #ifdef SERIAL_PROTOCOL_DBG
  6862. printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber);
  6863. #endif
  6864. } else if (!crcPass) {
  6865. 8003286: 9b03 ldr r3, [sp, #12]
  6866. 8003288: 2b00 cmp r3, #0
  6867. 800328a: f000 8098 beq.w 80033be <UartRxTask+0x1ae>
  6868. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0);
  6869. #ifdef SERIAL_PROTOCOL_DBG
  6870. printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber);
  6871. #endif
  6872. } else {
  6873. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0);
  6874. 800328e: f06f 0303 mvn.w r3, #3
  6875. 8003292: e9cd 9900 strd r9, r9, [sp]
  6876. 8003296: f7ff fa79 bl 800278c <PrepareRespFrame>
  6877. }
  6878. if (dataToSend > 0) {
  6879. 800329a: 2800 cmp r0, #0
  6880. 800329c: f040 809a bne.w 80033d4 <UartRxTask+0x1c4>
  6881. #endif
  6882. receverState = srFinish;
  6883. break;
  6884. case srFinish:
  6885. default:
  6886. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  6887. 80032a0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  6888. 80032a4: 6a20 ldr r0, [r4, #32]
  6889. 80032a6: f008 fdad bl 800be04 <osMutexAcquire>
  6890. uartTaskData->frameBytesCount = 0;
  6891. osMutexRelease (uartTaskData->rxDataBufferMutex);
  6892. 80032aa: 6a20 ldr r0, [r4, #32]
  6893. uartTaskData->frameBytesCount = 0;
  6894. 80032ac: f8a4 9016 strh.w r9, [r4, #22]
  6895. spFrameData.frameHeader.frameCommand = spUnknown;
  6896. 80032b0: 2512 movs r5, #18
  6897. osMutexRelease (uartTaskData->rxDataBufferMutex);
  6898. 80032b2: f008 fdcb bl 800be4c <osMutexRelease>
  6899. frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
  6900. 80032b6: 2100 movs r1, #0
  6901. 80032b8: f44f 63fa mov.w r3, #2000 @ 0x7d0
  6902. 80032bc: aa04 add r2, sp, #16
  6903. 80032be: 4608 mov r0, r1
  6904. spFrameData.frameHeader.frameCommand = spUnknown;
  6905. 80032c0: f88d 5016 strb.w r5, [sp, #22]
  6906. frameTotalLength = 0;
  6907. outputDataBufferPos = 0;
  6908. 80032c4: f8aa 9000 strh.w r9, [sl]
  6909. frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
  6910. 80032c8: f00a fe22 bl 800df10 <xTaskNotifyWait>
  6911. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  6912. 80032cc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  6913. frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
  6914. 80032d0: 4607 mov r7, r0
  6915. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  6916. 80032d2: 6a20 ldr r0, [r4, #32]
  6917. 80032d4: f008 fd96 bl 800be04 <osMutexAcquire>
  6918. frameBytesCount = uartTaskData->frameBytesCount;
  6919. 80032d8: 8ae5 ldrh r5, [r4, #22]
  6920. osMutexRelease (uartTaskData->rxDataBufferMutex);
  6921. 80032da: 6a20 ldr r0, [r4, #32]
  6922. 80032dc: f008 fdb6 bl 800be4c <osMutexRelease>
  6923. if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) {
  6924. 80032e0: 1e2e subs r6, r5, #0
  6925. 80032e2: bf18 it ne
  6926. 80032e4: 2601 movne r6, #1
  6927. 80032e6: 2f00 cmp r7, #0
  6928. 80032e8: d17a bne.n 80033e0 <UartRxTask+0x1d0>
  6929. 80032ea: 2e00 cmp r6, #0
  6930. 80032ec: d1c3 bne.n 8003276 <UartRxTask+0x66>
  6931. if (frameTimeout == pdFALSE) {
  6932. 80032ee: 2f00 cmp r7, #0
  6933. 80032f0: d176 bne.n 80033e0 <UartRxTask+0x1d0>
  6934. frameTotalLength = 0;
  6935. 80032f2: 46b8 mov r8, r7
  6936. if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) {
  6937. 80032f4: 6b20 ldr r0, [r4, #48] @ 0x30
  6938. 80032f6: f8d0 308c ldr.w r3, [r0, #140] @ 0x8c
  6939. 80032fa: 2b20 cmp r3, #32
  6940. 80032fc: d1a2 bne.n 8003244 <UartRxTask+0x34>
  6941. HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
  6942. 80032fe: 88a2 ldrh r2, [r4, #4]
  6943. 8003300: 6821 ldr r1, [r4, #0]
  6944. 8003302: f008 fc0b bl 800bb1c <HAL_UARTEx_ReceiveToIdle_IT>
  6945. while (proceed) {
  6946. 8003306: e79d b.n 8003244 <UartRxTask+0x34>
  6947. if (frameTimeout == pdFALSE) {
  6948. 8003308: f1bb 0f00 cmp.w fp, #0
  6949. 800330c: d0f2 beq.n 80032f4 <UartRxTask+0xe4>
  6950. switch (receverState) {
  6951. 800330e: 2f04 cmp r7, #4
  6952. 8003310: d8c6 bhi.n 80032a0 <UartRxTask+0x90>
  6953. 8003312: e8df f007 tbb [pc, r7]
  6954. 8003316: 3867 .short 0x3867
  6955. 8003318: 130d .short 0x130d
  6956. 800331a: 32 .byte 0x32
  6957. 800331b: 00 .byte 0x00
  6958. spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH]));
  6959. 800331c: f8b3 3005 ldrh.w r3, [r3, #5]
  6960. osMutexRelease (uartTaskData->rxDataBufferMutex);
  6961. 8003320: 6a20 ldr r0, [r4, #32]
  6962. spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH]));
  6963. 8003322: f8ad 3018 strh.w r3, [sp, #24]
  6964. frameTotalLength = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH;
  6965. 8003326: 330a adds r3, #10
  6966. 8003328: fa1f f883 uxth.w r8, r3
  6967. osMutexRelease (uartTaskData->rxDataBufferMutex);
  6968. 800332c: f008 fd8e bl 800be4c <osMutexRelease>
  6969. if (frameBytesCount >= frameTotalLength) {
  6970. 8003330: 45a8 cmp r8, r5
  6971. 8003332: d928 bls.n 8003386 <UartRxTask+0x176>
  6972. 8003334: 2702 movs r7, #2
  6973. 8003336: e785 b.n 8003244 <UartRxTask+0x34>
  6974. crcPass = frameCrc == crc;
  6975. 8003338: 2301 movs r3, #1
  6976. 800333a: 9303 str r3, [sp, #12]
  6977. if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) {
  6978. 800333c: 6aa3 ldr r3, [r4, #40] @ 0x28
  6979. 800333e: 2b00 cmp r3, #0
  6980. 8003340: f000 8083 beq.w 800344a <UartRxTask+0x23a>
  6981. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  6982. 8003344: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  6983. 8003348: 6a20 ldr r0, [r4, #32]
  6984. 800334a: f008 fd5b bl 800be04 <osMutexAcquire>
  6985. memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength);
  6986. 800334e: 6921 ldr r1, [r4, #16]
  6987. 8003350: f8bd 2018 ldrh.w r2, [sp, #24]
  6988. 8003354: a808 add r0, sp, #32
  6989. 8003356: 3108 adds r1, #8
  6990. 8003358: f00c fcab bl 800fcb2 <memcpy>
  6991. osMutexRelease (uartTaskData->rxDataBufferMutex);
  6992. 800335c: 6a20 ldr r0, [r4, #32]
  6993. 800335e: f008 fd75 bl 800be4c <osMutexRelease>
  6994. if (uartTaskData->processRxDataMsgBuffer != NULL) {
  6995. 8003362: 6a60 ldr r0, [r4, #36] @ 0x24
  6996. 8003364: 2800 cmp r0, #0
  6997. 8003366: d068 beq.n 800343a <UartRxTask+0x22a>
  6998. if (xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE) {
  6999. 8003368: f8bd 2018 ldrh.w r2, [sp, #24]
  7000. 800336c: 23c8 movs r3, #200 @ 0xc8
  7001. 800336e: a905 add r1, sp, #20
  7002. 8003370: 320c adds r2, #12
  7003. 8003372: f009 fe73 bl 800d05c <xStreamBufferSend>
  7004. 8003376: 2800 cmp r0, #0
  7005. 8003378: d15f bne.n 800343a <UartRxTask+0x22a>
  7006. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0);
  7007. 800337a: 68a0 ldr r0, [r4, #8]
  7008. 800337c: f8bd 1014 ldrh.w r1, [sp, #20]
  7009. 8003380: f89d 2016 ldrb.w r2, [sp, #22]
  7010. 8003384: e77f b.n 8003286 <UartRxTask+0x76>
  7011. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  7012. 8003386: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7013. 800338a: 6a20 ldr r0, [r4, #32]
  7014. 800338c: f008 fd3a bl 800be04 <osMutexAcquire>
  7015. frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH]));
  7016. 8003390: 6921 ldr r1, [r4, #16]
  7017. 8003392: f1a8 0202 sub.w r2, r8, #2
  7018. crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH);
  7019. 8003396: 484b ldr r0, [pc, #300] @ (80034c4 <UartRxTask+0x2b4>)
  7020. frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH]));
  7021. 8003398: 4488 add r8, r1
  7022. 800339a: 5c8e ldrb r6, [r1, r2]
  7023. 800339c: f818 3c01 ldrb.w r3, [r8, #-1]
  7024. 80033a0: ea46 2603 orr.w r6, r6, r3, lsl #8
  7025. crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH);
  7026. 80033a4: f001 fed8 bl 8005158 <HAL_CRC_Calculate>
  7027. 80033a8: 4605 mov r5, r0
  7028. osMutexRelease (uartTaskData->rxDataBufferMutex);
  7029. 80033aa: 6a20 ldr r0, [r4, #32]
  7030. 80033ac: f008 fd4e bl 800be4c <osMutexRelease>
  7031. if (crcPass) {
  7032. 80033b0: 42ae cmp r6, r5
  7033. 80033b2: d0c1 beq.n 8003338 <UartRxTask+0x128>
  7034. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0);
  7035. 80033b4: 68a0 ldr r0, [r4, #8]
  7036. 80033b6: f8bd 1014 ldrh.w r1, [sp, #20]
  7037. 80033ba: f89d 2016 ldrb.w r2, [sp, #22]
  7038. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0);
  7039. 80033be: f06f 0301 mvn.w r3, #1
  7040. 80033c2: e9cd 9900 strd r9, r9, [sp]
  7041. 80033c6: f7ff f9e1 bl 800278c <PrepareRespFrame>
  7042. 80033ca: 2300 movs r3, #0
  7043. 80033cc: 9303 str r3, [sp, #12]
  7044. if (dataToSend > 0) {
  7045. 80033ce: 2800 cmp r0, #0
  7046. 80033d0: f43f af66 beq.w 80032a0 <UartRxTask+0x90>
  7047. HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend);
  7048. 80033d4: 4602 mov r2, r0
  7049. 80033d6: 68a1 ldr r1, [r4, #8]
  7050. 80033d8: 6b20 ldr r0, [r4, #48] @ 0x30
  7051. 80033da: f007 fa37 bl 800a84c <HAL_UART_Transmit_IT>
  7052. 80033de: e75f b.n 80032a0 <UartRxTask+0x90>
  7053. frameTotalLength = 0;
  7054. 80033e0: f04f 0800 mov.w r8, #0
  7055. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  7056. 80033e4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7057. 80033e8: 6a20 ldr r0, [r4, #32]
  7058. 80033ea: f008 fd0b bl 800be04 <osMutexAcquire>
  7059. if (uartTaskData->frameData[0] == FRAME_INDICATOR) {
  7060. 80033ee: 6923 ldr r3, [r4, #16]
  7061. 80033f0: 781a ldrb r2, [r3, #0]
  7062. 80033f2: 2aaa cmp r2, #170 @ 0xaa
  7063. 80033f4: d02e beq.n 8003454 <UartRxTask+0x244>
  7064. osMutexRelease (uartTaskData->rxDataBufferMutex);
  7065. 80033f6: 6a20 ldr r0, [r4, #32]
  7066. if (frameBytesCount > 0) {
  7067. 80033f8: 2e00 cmp r6, #0
  7068. 80033fa: d142 bne.n 8003482 <UartRxTask+0x272>
  7069. osMutexRelease (uartTaskData->rxDataBufferMutex);
  7070. 80033fc: f008 fd26 bl 800be4c <osMutexRelease>
  7071. frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
  7072. 8003400: f44f 63fa mov.w r3, #2000 @ 0x7d0
  7073. 8003404: aa04 add r2, sp, #16
  7074. 8003406: 4631 mov r1, r6
  7075. 8003408: 4608 mov r0, r1
  7076. 800340a: f00a fd81 bl 800df10 <xTaskNotifyWait>
  7077. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  7078. 800340e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7079. frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
  7080. 8003412: 4607 mov r7, r0
  7081. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  7082. 8003414: 6a20 ldr r0, [r4, #32]
  7083. 8003416: f008 fcf5 bl 800be04 <osMutexAcquire>
  7084. frameBytesCount = uartTaskData->frameBytesCount;
  7085. 800341a: 8ae5 ldrh r5, [r4, #22]
  7086. osMutexRelease (uartTaskData->rxDataBufferMutex);
  7087. 800341c: 6a20 ldr r0, [r4, #32]
  7088. 800341e: f008 fd15 bl 800be4c <osMutexRelease>
  7089. if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) {
  7090. 8003422: 1e2e subs r6, r5, #0
  7091. 8003424: bf18 it ne
  7092. 8003426: 2601 movne r6, #1
  7093. 8003428: 2f00 cmp r7, #0
  7094. 800342a: d1db bne.n 80033e4 <UartRxTask+0x1d4>
  7095. 800342c: 2e00 cmp r6, #0
  7096. 800342e: f47f af22 bne.w 8003276 <UartRxTask+0x66>
  7097. if (frameTimeout == pdFALSE) {
  7098. 8003432: 2f00 cmp r7, #0
  7099. 8003434: d1d6 bne.n 80033e4 <UartRxTask+0x1d4>
  7100. uint16_t frameTotalLength = 0;
  7101. 8003436: 2700 movs r7, #0
  7102. 8003438: e75c b.n 80032f4 <UartRxTask+0xe4>
  7103. if (uartTaskData->processDataCb != NULL) {
  7104. 800343a: 6aa3 ldr r3, [r4, #40] @ 0x28
  7105. 800343c: 2b00 cmp r3, #0
  7106. 800343e: f43f af2f beq.w 80032a0 <UartRxTask+0x90>
  7107. uartTaskData->processDataCb (uartTaskData, &spFrameData);
  7108. 8003442: a905 add r1, sp, #20
  7109. 8003444: 4620 mov r0, r4
  7110. 8003446: 4798 blx r3
  7111. switch (receverState) {
  7112. 8003448: e72a b.n 80032a0 <UartRxTask+0x90>
  7113. if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) {
  7114. 800344a: 6a63 ldr r3, [r4, #36] @ 0x24
  7115. 800344c: 2b00 cmp r3, #0
  7116. 800344e: f47f af79 bne.w 8003344 <UartRxTask+0x134>
  7117. 8003452: e725 b.n 80032a0 <UartRxTask+0x90>
  7118. if (frameBytesCount > FRAME_ID_LENGTH) {
  7119. 8003454: 2d02 cmp r5, #2
  7120. 8003456: d81c bhi.n 8003492 <UartRxTask+0x282>
  7121. osMutexRelease (uartTaskData->rxDataBufferMutex);
  7122. 8003458: 6a20 ldr r0, [r4, #32]
  7123. 800345a: f008 fcf7 bl 800be4c <osMutexRelease>
  7124. frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
  7125. 800345e: 2100 movs r1, #0
  7126. 8003460: f44f 63fa mov.w r3, #2000 @ 0x7d0
  7127. 8003464: aa04 add r2, sp, #16
  7128. 8003466: 4608 mov r0, r1
  7129. 8003468: f00a fd52 bl 800df10 <xTaskNotifyWait>
  7130. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  7131. 800346c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7132. frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
  7133. 8003470: 4607 mov r7, r0
  7134. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  7135. 8003472: e7cf b.n 8003414 <UartRxTask+0x204>
  7136. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0);
  7137. 8003474: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
  7138. 8003478: e9cd 9900 strd r9, r9, [sp]
  7139. 800347c: f7ff f986 bl 800278c <PrepareRespFrame>
  7140. 8003480: e70b b.n 800329a <UartRxTask+0x8a>
  7141. osMutexRelease (uartTaskData->rxDataBufferMutex);
  7142. 8003482: f008 fce3 bl 800be4c <osMutexRelease>
  7143. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0);
  7144. 8003486: 68a0 ldr r0, [r4, #8]
  7145. 8003488: f8bd 1014 ldrh.w r1, [sp, #20]
  7146. 800348c: f89d 2016 ldrb.w r2, [sp, #22]
  7147. 8003490: e6f9 b.n 8003286 <UartRxTask+0x76>
  7148. spFrameData.frameHeader.frameId =
  7149. 8003492: f8b3 2001 ldrh.w r2, [r3, #1]
  7150. if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) {
  7151. 8003496: 2d04 cmp r5, #4
  7152. spFrameData.frameHeader.frameId =
  7153. 8003498: f8ad 2014 strh.w r2, [sp, #20]
  7154. if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) {
  7155. 800349c: d909 bls.n 80034b2 <UartRxTask+0x2a2>
  7156. frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH]));
  7157. 800349e: f8b3 2003 ldrh.w r2, [r3, #3]
  7158. if (frameBytesCount >= FRAME_HEADER_LENGTH) {
  7159. 80034a2: 2d07 cmp r5, #7
  7160. spFrameData.frameHeader.frameCommand = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF);
  7161. 80034a4: f88d 2016 strb.w r2, [sp, #22]
  7162. spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE;
  7163. 80034a8: ea4f 32d2 mov.w r2, r2, lsr #15
  7164. 80034ac: 9207 str r2, [sp, #28]
  7165. if (frameBytesCount >= FRAME_HEADER_LENGTH) {
  7166. 80034ae: f63f af35 bhi.w 800331c <UartRxTask+0x10c>
  7167. osMutexRelease (uartTaskData->rxDataBufferMutex);
  7168. 80034b2: 6a20 ldr r0, [r4, #32]
  7169. 80034b4: f008 fcca bl 800be4c <osMutexRelease>
  7170. frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS)));
  7171. 80034b8: 2100 movs r1, #0
  7172. 80034ba: f44f 63fa mov.w r3, #2000 @ 0x7d0
  7173. 80034be: aa04 add r2, sp, #16
  7174. 80034c0: e7a2 b.n 8003408 <UartRxTask+0x1f8>
  7175. 80034c2: bf00 nop
  7176. 80034c4: 240005d0 .word 0x240005d0
  7177. 80034c8: 24000ab8 .word 0x24000ab8
  7178. 80034cc: 00000000 .word 0x00000000
  7179. 080034d0 <Uart1ReceivedDataProcessCallback>:
  7180. void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) {
  7181. Uart1ReceivedDataProcessCallback (arg, spFrameData);
  7182. }
  7183. void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) {
  7184. 80034d0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  7185. 80034d4: b093 sub sp, #76 @ 0x4c
  7186. UartTaskData* uartTaskData = (UartTaskData*)arg;
  7187. uint16_t dataToSend = 0;
  7188. outputDataBufferPos = 0;
  7189. 80034d6: 2300 movs r3, #0
  7190. 80034d8: 4eb9 ldr r6, [pc, #740] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7191. void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) {
  7192. 80034da: 460c mov r4, r1
  7193. 80034dc: f10d 0247 add.w r2, sp, #71 @ 0x47
  7194. 80034e0: 4605 mov r5, r0
  7195. outputDataBufferPos = 0;
  7196. 80034e2: 8033 strh r3, [r6, #0]
  7197. void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) {
  7198. 80034e4: f022 071f bic.w r7, r2, #31
  7199. uint16_t inputDataBufferPos = 0;
  7200. SerialProtocolRespStatus respStatus = spUnknownCommand;
  7201. switch (spFrameData->frameHeader.frameCommand) {
  7202. 80034e8: 788a ldrb r2, [r1, #2]
  7203. uint16_t inputDataBufferPos = 0;
  7204. 80034ea: f8ad 301e strh.w r3, [sp, #30]
  7205. switch (spFrameData->frameHeader.frameCommand) {
  7206. 80034ee: 2a11 cmp r2, #17
  7207. 80034f0: f200 8443 bhi.w 8003d7a <Uart1ReceivedDataProcessCallback+0x8aa>
  7208. 80034f4: e8df f012 tbh [pc, r2, lsl #1]
  7209. 80034f8: 02e8003a .word 0x02e8003a
  7210. 80034fc: 02870251 .word 0x02870251
  7211. 8003500: 00e800c8 .word 0x00e800c8
  7212. 8003504: 03a6011a .word 0x03a6011a
  7213. 8003508: 020d00a5 .word 0x020d00a5
  7214. 800350c: 022801ec .word 0x022801ec
  7215. 8003510: 01920141 .word 0x01920141
  7216. 8003514: 03d201b2 .word 0x03d201b2
  7217. 8003518: 001201d2 .word 0x001201d2
  7218. ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posXData.positionSettingValue);
  7219. osMessageQueuePut(positionXControlTaskInitArg.positionSettingQueue, &posXData, 0, 0);
  7220. }
  7221. break;
  7222. case spSetPositonY:
  7223. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  7224. 800351c: f8df 82d8 ldr.w r8, [pc, #728] @ 80037f8 <Uart1ReceivedDataProcessCallback+0x328>
  7225. 8003520: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7226. 8003524: f8d8 0000 ldr.w r0, [r8]
  7227. 8003528: f008 fc6c bl 800be04 <osMutexAcquire>
  7228. 800352c: 2800 cmp r0, #0
  7229. 800352e: f000 83fe beq.w 8003d2e <Uart1ReceivedDataProcessCallback+0x85e>
  7230. sensorsInfo.positionYWeak = 1;
  7231. osMutexRelease (sensorsInfoMutex);
  7232. }
  7233. PositionControlTaskData posYData __attribute__ ((aligned (32))) = { 0 };
  7234. 8003532: 2300 movs r3, #0
  7235. if (positionYControlTaskInitArg.positionSettingQueue != NULL)
  7236. 8003534: f8df 82d8 ldr.w r8, [pc, #728] @ 8003810 <Uart1ReceivedDataProcessCallback+0x340>
  7237. PositionControlTaskData posYData __attribute__ ((aligned (32))) = { 0 };
  7238. 8003538: 603b str r3, [r7, #0]
  7239. if (positionYControlTaskInitArg.positionSettingQueue != NULL)
  7240. 800353a: f8d8 3010 ldr.w r3, [r8, #16]
  7241. 800353e: 2b00 cmp r3, #0
  7242. 8003540: f000 81c0 beq.w 80038c4 <Uart1ReceivedDataProcessCallback+0x3f4>
  7243. {
  7244. ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posYData.positionSettingValue);
  7245. 8003544: 463a mov r2, r7
  7246. 8003546: f10d 011e add.w r1, sp, #30
  7247. 800354a: f104 000c add.w r0, r4, #12
  7248. 800354e: f7ff f8ed bl 800272c <ReadFloatFromBuffer>
  7249. osMessageQueuePut(positionYControlTaskInitArg.positionSettingQueue, &posYData, 0, 0);
  7250. 8003552: 2300 movs r3, #0
  7251. 8003554: 4639 mov r1, r7
  7252. 8003556: f8d8 0010 ldr.w r0, [r8, #16]
  7253. 800355a: 461a mov r2, r3
  7254. 800355c: 4f99 ldr r7, [pc, #612] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7255. 800355e: f008 fcd3 bl 800bf08 <osMessageQueuePut>
  7256. }
  7257. break;
  7258. default: respStatus = spUnknownCommand; break;
  7259. }
  7260. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7261. 8003562: 78a2 ldrb r2, [r4, #2]
  7262. 8003564: 8836 ldrh r6, [r6, #0]
  7263. SerialProtocolRespStatus respStatus = spUnknownCommand;
  7264. 8003566: f06f 0302 mvn.w r3, #2
  7265. 800356a: e0d3 b.n 8003714 <Uart1ReceivedDataProcessCallback+0x244>
  7266. if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
  7267. 800356c: f8df 92a4 ldr.w r9, [pc, #676] @ 8003814 <Uart1ReceivedDataProcessCallback+0x344>
  7268. 8003570: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7269. 8003574: f8d9 0000 ldr.w r0, [r9]
  7270. 8003578: f008 fc44 bl 800be04 <osMutexAcquire>
  7271. 800357c: 2800 cmp r0, #0
  7272. 800357e: f040 809d bne.w 80036bc <Uart1ReceivedDataProcessCallback+0x1ec>
  7273. 8003582: f8df 8294 ldr.w r8, [pc, #660] @ 8003818 <Uart1ReceivedDataProcessCallback+0x348>
  7274. 8003586: 4f8f ldr r7, [pc, #572] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7275. 8003588: f108 0a0c add.w sl, r8, #12
  7276. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float));
  7277. 800358c: 46bb mov fp, r7
  7278. 800358e: 4642 mov r2, r8
  7279. for (int i = 0; i < 3; i++) {
  7280. 8003590: f108 0804 add.w r8, r8, #4
  7281. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float));
  7282. 8003594: 2304 movs r3, #4
  7283. 8003596: 498a ldr r1, [pc, #552] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7284. 8003598: 4658 mov r0, fp
  7285. 800359a: f7ff f8ad bl 80026f8 <WriteDataToBuffer>
  7286. for (int i = 0; i < 3; i++) {
  7287. 800359e: 45d0 cmp r8, sl
  7288. 80035a0: d1f5 bne.n 800358e <Uart1ReceivedDataProcessCallback+0xbe>
  7289. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof (float));
  7290. 80035a2: 2304 movs r3, #4
  7291. 80035a4: 4a88 ldr r2, [pc, #544] @ (80037c8 <Uart1ReceivedDataProcessCallback+0x2f8>)
  7292. 80035a6: 4986 ldr r1, [pc, #536] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7293. 80035a8: 4886 ldr r0, [pc, #536] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7294. 80035aa: f7ff f8a5 bl 80026f8 <WriteDataToBuffer>
  7295. 80035ae: 2304 movs r3, #4
  7296. 80035b0: 4a86 ldr r2, [pc, #536] @ (80037cc <Uart1ReceivedDataProcessCallback+0x2fc>)
  7297. 80035b2: 4983 ldr r1, [pc, #524] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7298. 80035b4: 4883 ldr r0, [pc, #524] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7299. 80035b6: f7ff f89f bl 80026f8 <WriteDataToBuffer>
  7300. 80035ba: 2304 movs r3, #4
  7301. 80035bc: 4a84 ldr r2, [pc, #528] @ (80037d0 <Uart1ReceivedDataProcessCallback+0x300>)
  7302. 80035be: 4980 ldr r1, [pc, #512] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7303. 80035c0: 4880 ldr r0, [pc, #512] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7304. 80035c2: f7ff f899 bl 80026f8 <WriteDataToBuffer>
  7305. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof (float));
  7306. 80035c6: 2304 movs r3, #4
  7307. 80035c8: 4a82 ldr r2, [pc, #520] @ (80037d4 <Uart1ReceivedDataProcessCallback+0x304>)
  7308. 80035ca: 497d ldr r1, [pc, #500] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7309. 80035cc: 487d ldr r0, [pc, #500] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7310. 80035ce: f7ff f893 bl 80026f8 <WriteDataToBuffer>
  7311. 80035d2: 2304 movs r3, #4
  7312. 80035d4: 4a80 ldr r2, [pc, #512] @ (80037d8 <Uart1ReceivedDataProcessCallback+0x308>)
  7313. 80035d6: 497a ldr r1, [pc, #488] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7314. 80035d8: 487a ldr r0, [pc, #488] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7315. 80035da: f7ff f88d bl 80026f8 <WriteDataToBuffer>
  7316. 80035de: 2304 movs r3, #4
  7317. 80035e0: 4a7e ldr r2, [pc, #504] @ (80037dc <Uart1ReceivedDataProcessCallback+0x30c>)
  7318. 80035e2: 4977 ldr r1, [pc, #476] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7319. 80035e4: 4877 ldr r0, [pc, #476] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7320. 80035e6: f7ff f887 bl 80026f8 <WriteDataToBuffer>
  7321. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof (float));
  7322. 80035ea: 2304 movs r3, #4
  7323. 80035ec: 4a7c ldr r2, [pc, #496] @ (80037e0 <Uart1ReceivedDataProcessCallback+0x310>)
  7324. 80035ee: 4974 ldr r1, [pc, #464] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7325. 80035f0: 4874 ldr r0, [pc, #464] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7326. 80035f2: f7ff f881 bl 80026f8 <WriteDataToBuffer>
  7327. 80035f6: 2304 movs r3, #4
  7328. 80035f8: 4a7a ldr r2, [pc, #488] @ (80037e4 <Uart1ReceivedDataProcessCallback+0x314>)
  7329. 80035fa: 4971 ldr r1, [pc, #452] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7330. 80035fc: 4871 ldr r0, [pc, #452] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7331. 80035fe: f7ff f87b bl 80026f8 <WriteDataToBuffer>
  7332. 8003602: 2304 movs r3, #4
  7333. 8003604: 4a78 ldr r2, [pc, #480] @ (80037e8 <Uart1ReceivedDataProcessCallback+0x318>)
  7334. 8003606: 496e ldr r1, [pc, #440] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7335. 8003608: 486e ldr r0, [pc, #440] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7336. 800360a: f7ff f875 bl 80026f8 <WriteDataToBuffer>
  7337. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof (float));
  7338. 800360e: 2304 movs r3, #4
  7339. 8003610: 4a76 ldr r2, [pc, #472] @ (80037ec <Uart1ReceivedDataProcessCallback+0x31c>)
  7340. 8003612: 496b ldr r1, [pc, #428] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7341. 8003614: 486b ldr r0, [pc, #428] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7342. 8003616: f7ff f86f bl 80026f8 <WriteDataToBuffer>
  7343. 800361a: 2304 movs r3, #4
  7344. 800361c: 4a74 ldr r2, [pc, #464] @ (80037f0 <Uart1ReceivedDataProcessCallback+0x320>)
  7345. 800361e: 4968 ldr r1, [pc, #416] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7346. 8003620: 4868 ldr r0, [pc, #416] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7347. 8003622: f7ff f869 bl 80026f8 <WriteDataToBuffer>
  7348. 8003626: 2304 movs r3, #4
  7349. 8003628: 4a72 ldr r2, [pc, #456] @ (80037f4 <Uart1ReceivedDataProcessCallback+0x324>)
  7350. 800362a: 4965 ldr r1, [pc, #404] @ (80037c0 <Uart1ReceivedDataProcessCallback+0x2f0>)
  7351. 800362c: 4865 ldr r0, [pc, #404] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7352. 800362e: f7ff f863 bl 80026f8 <WriteDataToBuffer>
  7353. osMutexRelease (resMeasurementsMutex);
  7354. 8003632: f8d9 0000 ldr.w r0, [r9]
  7355. 8003636: f008 fc09 bl 800be4c <osMutexRelease>
  7356. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7357. 800363a: 78a2 ldrb r2, [r4, #2]
  7358. 800363c: 8836 ldrh r6, [r6, #0]
  7359. respStatus = spOK;
  7360. 800363e: 2300 movs r3, #0
  7361. 8003640: e068 b.n 8003714 <Uart1ReceivedDataProcessCallback+0x244>
  7362. if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
  7363. 8003642: f8df 91d0 ldr.w r9, [pc, #464] @ 8003814 <Uart1ReceivedDataProcessCallback+0x344>
  7364. 8003646: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7365. 800364a: f8d9 0000 ldr.w r0, [r9]
  7366. 800364e: f008 fbd9 bl 800be04 <osMutexAcquire>
  7367. 8003652: 4680 mov r8, r0
  7368. 8003654: bb90 cbnz r0, 80036bc <Uart1ReceivedDataProcessCallback+0x1ec>
  7369. resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i];
  7370. 8003656: f8df c170 ldr.w ip, [pc, #368] @ 80037c8 <Uart1ReceivedDataProcessCallback+0x2f8>
  7371. 800365a: 4f5a ldr r7, [pc, #360] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7372. 800365c: f1ac 030c sub.w r3, ip, #12
  7373. resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i];
  7374. 8003660: f10c 0a0c add.w sl, ip, #12
  7375. 8003664: f10c 0e18 add.w lr, ip, #24
  7376. resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i];
  7377. 8003668: e893 0007 ldmia.w r3, {r0, r1, r2}
  7378. 800366c: e88c 0007 stmia.w ip, {r0, r1, r2}
  7379. resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i];
  7380. 8003670: e89a 0007 ldmia.w sl, {r0, r1, r2}
  7381. 8003674: e88e 0007 stmia.w lr, {r0, r1, r2}
  7382. osMutexRelease (resMeasurementsMutex);
  7383. 8003678: f8d9 0000 ldr.w r0, [r9]
  7384. 800367c: f008 fbe6 bl 800be4c <osMutexRelease>
  7385. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7386. 8003680: 8836 ldrh r6, [r6, #0]
  7387. respStatus = spOK;
  7388. 8003682: 4643 mov r3, r8
  7389. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7390. 8003684: 78a2 ldrb r2, [r4, #2]
  7391. 8003686: e045 b.n 8003714 <Uart1ReceivedDataProcessCallback+0x244>
  7392. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse);
  7393. 8003688: f101 070c add.w r7, r1, #12
  7394. int32_t motorYPWMPulse = 0;
  7395. 800368c: 2300 movs r3, #0
  7396. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse);
  7397. 800368e: aa08 add r2, sp, #32
  7398. 8003690: f10d 011e add.w r1, sp, #30
  7399. 8003694: 4638 mov r0, r7
  7400. int32_t motorYTimerPeriod = 0;
  7401. 8003696: e9cd 3308 strd r3, r3, [sp, #32]
  7402. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse);
  7403. 800369a: f7ff f85f bl 800275c <ReadWordFromBufer>
  7404. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod);
  7405. 800369e: 4638 mov r0, r7
  7406. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  7407. 80036a0: 4f55 ldr r7, [pc, #340] @ (80037f8 <Uart1ReceivedDataProcessCallback+0x328>)
  7408. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod);
  7409. 80036a2: f10d 011e add.w r1, sp, #30
  7410. 80036a6: aa09 add r2, sp, #36 @ 0x24
  7411. 80036a8: f7ff f858 bl 800275c <ReadWordFromBufer>
  7412. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  7413. 80036ac: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7414. 80036b0: 6838 ldr r0, [r7, #0]
  7415. 80036b2: f008 fba7 bl 800be04 <osMutexAcquire>
  7416. 80036b6: 2800 cmp r0, #0
  7417. 80036b8: f000 8310 beq.w 8003cdc <Uart1ReceivedDataProcessCallback+0x80c>
  7418. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7419. 80036bc: 78a2 ldrb r2, [r4, #2]
  7420. respStatus = spInternalError;
  7421. 80036be: f06f 0303 mvn.w r3, #3
  7422. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7423. 80036c2: 8836 ldrh r6, [r6, #0]
  7424. 80036c4: 4f3f ldr r7, [pc, #252] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7425. 80036c6: e025 b.n 8003714 <Uart1ReceivedDataProcessCallback+0x244>
  7426. float motorXMaxCurrent = 0;
  7427. 80036c8: 2300 movs r3, #0
  7428. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent);
  7429. 80036ca: aa09 add r2, sp, #36 @ 0x24
  7430. 80036cc: f10d 011e add.w r1, sp, #30
  7431. 80036d0: f104 000c add.w r0, r4, #12
  7432. float motorXMaxCurrent = 0;
  7433. 80036d4: 9309 str r3, [sp, #36] @ 0x24
  7434. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent);
  7435. 80036d6: f7ff f841 bl 800275c <ReadWordFromBufer>
  7436. uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001));
  7437. 80036da: ed9d 7a09 vldr s14, [sp, #36] @ 0x24
  7438. HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1);
  7439. 80036de: 2200 movs r2, #0
  7440. uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001));
  7441. 80036e0: eddf 7a46 vldr s15, [pc, #280] @ 80037fc <Uart1ReceivedDataProcessCallback+0x32c>
  7442. HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1);
  7443. 80036e4: 4611 mov r1, r2
  7444. 80036e6: 4846 ldr r0, [pc, #280] @ (8003800 <Uart1ReceivedDataProcessCallback+0x330>)
  7445. uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001));
  7446. 80036e8: ee27 7a27 vmul.f32 s14, s14, s15
  7447. 80036ec: ed9f 6b32 vldr d6, [pc, #200] @ 80037b8 <Uart1ReceivedDataProcessCallback+0x2e8>
  7448. 80036f0: eeb7 7ac7 vcvt.f64.f32 d7, s14
  7449. 80036f4: ee27 7b06 vmul.f64 d7, d7, d6
  7450. HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1);
  7451. 80036f8: eefc 7bc7 vcvt.u32.f64 s15, d7
  7452. 80036fc: ee17 3a90 vmov r3, s15
  7453. 8003700: f001 fdf0 bl 80052e4 <HAL_DAC_SetValue>
  7454. HAL_DAC_Start (&hdac1, DAC_CHANNEL_1);
  7455. 8003704: 2100 movs r1, #0
  7456. 8003706: 483e ldr r0, [pc, #248] @ (8003800 <Uart1ReceivedDataProcessCallback+0x330>)
  7457. 8003708: f001 fdb4 bl 8005274 <HAL_DAC_Start>
  7458. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7459. 800370c: 78a2 ldrb r2, [r4, #2]
  7460. respStatus = spOK;
  7461. 800370e: 2300 movs r3, #0
  7462. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7463. 8003710: 8836 ldrh r6, [r6, #0]
  7464. 8003712: 4f2c ldr r7, [pc, #176] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7465. 8003714: 9601 str r6, [sp, #4]
  7466. 8003716: 8821 ldrh r1, [r4, #0]
  7467. 8003718: 9700 str r7, [sp, #0]
  7468. 800371a: 68a8 ldr r0, [r5, #8]
  7469. 800371c: f7ff f836 bl 800278c <PrepareRespFrame>
  7470. if (dataToSend > 0) {
  7471. 8003720: 2800 cmp r0, #0
  7472. 8003722: f040 82b3 bne.w 8003c8c <Uart1ReceivedDataProcessCallback+0x7bc>
  7473. HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend);
  7474. }
  7475. #ifdef SERIAL_PROTOCOL_DBG
  7476. printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend);
  7477. #endif
  7478. }
  7479. 8003726: b013 add sp, #76 @ 0x4c
  7480. 8003728: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  7481. float motorYMaxCurrent = 0;
  7482. 800372c: 2300 movs r3, #0
  7483. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent);
  7484. 800372e: aa09 add r2, sp, #36 @ 0x24
  7485. 8003730: f10d 011e add.w r1, sp, #30
  7486. 8003734: f104 000c add.w r0, r4, #12
  7487. float motorYMaxCurrent = 0;
  7488. 8003738: 9309 str r3, [sp, #36] @ 0x24
  7489. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent);
  7490. 800373a: f7ff f80f bl 800275c <ReadWordFromBufer>
  7491. uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001));
  7492. 800373e: ed9d 7a09 vldr s14, [sp, #36] @ 0x24
  7493. HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2);
  7494. 8003742: 2200 movs r2, #0
  7495. uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001));
  7496. 8003744: eddf 7a2d vldr s15, [pc, #180] @ 80037fc <Uart1ReceivedDataProcessCallback+0x32c>
  7497. HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2);
  7498. 8003748: 2110 movs r1, #16
  7499. 800374a: 482d ldr r0, [pc, #180] @ (8003800 <Uart1ReceivedDataProcessCallback+0x330>)
  7500. uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001));
  7501. 800374c: ee27 7a27 vmul.f32 s14, s14, s15
  7502. 8003750: 4f1c ldr r7, [pc, #112] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7503. 8003752: ed9f 6b19 vldr d6, [pc, #100] @ 80037b8 <Uart1ReceivedDataProcessCallback+0x2e8>
  7504. 8003756: eeb7 7ac7 vcvt.f64.f32 d7, s14
  7505. 800375a: ee27 7b06 vmul.f64 d7, d7, d6
  7506. HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2);
  7507. 800375e: eefc 7bc7 vcvt.u32.f64 s15, d7
  7508. 8003762: ee17 3a90 vmov r3, s15
  7509. 8003766: f001 fdbd bl 80052e4 <HAL_DAC_SetValue>
  7510. HAL_DAC_Start (&hdac1, DAC_CHANNEL_2);
  7511. 800376a: 2110 movs r1, #16
  7512. 800376c: 4824 ldr r0, [pc, #144] @ (8003800 <Uart1ReceivedDataProcessCallback+0x330>)
  7513. 800376e: f001 fd81 bl 8005274 <HAL_DAC_Start>
  7514. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7515. 8003772: 78a2 ldrb r2, [r4, #2]
  7516. 8003774: 8836 ldrh r6, [r6, #0]
  7517. respStatus = spOK;
  7518. 8003776: 2300 movs r3, #0
  7519. break;
  7520. 8003778: e7cc b.n 8003714 <Uart1ReceivedDataProcessCallback+0x244>
  7521. if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
  7522. 800377a: f8df a098 ldr.w sl, [pc, #152] @ 8003814 <Uart1ReceivedDataProcessCallback+0x344>
  7523. 800377e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7524. 8003782: f8da 0000 ldr.w r0, [sl]
  7525. 8003786: f008 fb3d bl 800be04 <osMutexAcquire>
  7526. 800378a: 4680 mov r8, r0
  7527. 800378c: 2800 cmp r0, #0
  7528. 800378e: d195 bne.n 80036bc <Uart1ReceivedDataProcessCallback+0x1ec>
  7529. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse);
  7530. 8003790: f104 090c add.w r9, r4, #12
  7531. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].offset);
  7532. 8003794: 4a1b ldr r2, [pc, #108] @ (8003804 <Uart1ReceivedDataProcessCallback+0x334>)
  7533. 8003796: f10d 011e add.w r1, sp, #30
  7534. 800379a: 4f0a ldr r7, [pc, #40] @ (80037c4 <Uart1ReceivedDataProcessCallback+0x2f4>)
  7535. 800379c: 4648 mov r0, r9
  7536. 800379e: f7fe ffdd bl 800275c <ReadWordFromBufer>
  7537. 80037a2: 4a19 ldr r2, [pc, #100] @ (8003808 <Uart1ReceivedDataProcessCallback+0x338>)
  7538. 80037a4: f10d 011e add.w r1, sp, #30
  7539. 80037a8: 4648 mov r0, r9
  7540. 80037aa: f7fe ffd7 bl 800275c <ReadWordFromBufer>
  7541. 80037ae: f10d 011e add.w r1, sp, #30
  7542. 80037b2: 4648 mov r0, r9
  7543. 80037b4: 4a15 ldr r2, [pc, #84] @ (800380c <Uart1ReceivedDataProcessCallback+0x33c>)
  7544. 80037b6: e0e6 b.n 8003986 <Uart1ReceivedDataProcessCallback+0x4b6>
  7545. 80037b8: 55555555 .word 0x55555555
  7546. 80037bc: 3fd55555 .word 0x3fd55555
  7547. 80037c0: 24000ab8 .word 0x24000ab8
  7548. 80037c4: 24000abc .word 0x24000abc
  7549. 80037c8: 2400094c .word 0x2400094c
  7550. 80037cc: 24000950 .word 0x24000950
  7551. 80037d0: 24000954 .word 0x24000954
  7552. 80037d4: 24000958 .word 0x24000958
  7553. 80037d8: 2400095c .word 0x2400095c
  7554. 80037dc: 24000960 .word 0x24000960
  7555. 80037e0: 24000964 .word 0x24000964
  7556. 80037e4: 24000968 .word 0x24000968
  7557. 80037e8: 2400096c .word 0x2400096c
  7558. 80037ec: 24000970 .word 0x24000970
  7559. 80037f0: 24000974 .word 0x24000974
  7560. 80037f4: 24000978 .word 0x24000978
  7561. 80037f8: 24000980 .word 0x24000980
  7562. 80037fc: 457ff000 .word 0x457ff000
  7563. 8003800: 240005bc .word 0x240005bc
  7564. 8003804: 2400001c .word 0x2400001c
  7565. 8003808: 24000024 .word 0x24000024
  7566. 800380c: 2400002c .word 0x2400002c
  7567. 8003810: 240009c0 .word 0x240009c0
  7568. 8003814: 24000984 .word 0x24000984
  7569. 8003818: 24000940 .word 0x24000940
  7570. if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
  7571. 800381c: f8df a29c ldr.w sl, [pc, #668] @ 8003abc <Uart1ReceivedDataProcessCallback+0x5ec>
  7572. 8003820: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7573. 8003824: f8da 0000 ldr.w r0, [sl]
  7574. 8003828: f008 faec bl 800be04 <osMutexAcquire>
  7575. 800382c: 4680 mov r8, r0
  7576. 800382e: 2800 cmp r0, #0
  7577. 8003830: f47f af44 bne.w 80036bc <Uart1ReceivedDataProcessCallback+0x1ec>
  7578. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse);
  7579. 8003834: f104 090c add.w r9, r4, #12
  7580. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].gain);
  7581. 8003838: 4a8f ldr r2, [pc, #572] @ (8003a78 <Uart1ReceivedDataProcessCallback+0x5a8>)
  7582. 800383a: f10d 011e add.w r1, sp, #30
  7583. 800383e: 4f8f ldr r7, [pc, #572] @ (8003a7c <Uart1ReceivedDataProcessCallback+0x5ac>)
  7584. 8003840: 4648 mov r0, r9
  7585. 8003842: f7fe ff8b bl 800275c <ReadWordFromBufer>
  7586. 8003846: 4a8e ldr r2, [pc, #568] @ (8003a80 <Uart1ReceivedDataProcessCallback+0x5b0>)
  7587. 8003848: f10d 011e add.w r1, sp, #30
  7588. 800384c: 4648 mov r0, r9
  7589. 800384e: f7fe ff85 bl 800275c <ReadWordFromBufer>
  7590. 8003852: f10d 011e add.w r1, sp, #30
  7591. 8003856: 4648 mov r0, r9
  7592. 8003858: 4a8a ldr r2, [pc, #552] @ (8003a84 <Uart1ReceivedDataProcessCallback+0x5b4>)
  7593. 800385a: e094 b.n 8003986 <Uart1ReceivedDataProcessCallback+0x4b6>
  7594. if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
  7595. 800385c: f8df a25c ldr.w sl, [pc, #604] @ 8003abc <Uart1ReceivedDataProcessCallback+0x5ec>
  7596. 8003860: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7597. 8003864: f8da 0000 ldr.w r0, [sl]
  7598. 8003868: f008 facc bl 800be04 <osMutexAcquire>
  7599. 800386c: 4680 mov r8, r0
  7600. 800386e: 2800 cmp r0, #0
  7601. 8003870: f47f af24 bne.w 80036bc <Uart1ReceivedDataProcessCallback+0x1ec>
  7602. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse);
  7603. 8003874: f104 090c add.w r9, r4, #12
  7604. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].offset);
  7605. 8003878: 4a83 ldr r2, [pc, #524] @ (8003a88 <Uart1ReceivedDataProcessCallback+0x5b8>)
  7606. 800387a: f10d 011e add.w r1, sp, #30
  7607. 800387e: 4f7f ldr r7, [pc, #508] @ (8003a7c <Uart1ReceivedDataProcessCallback+0x5ac>)
  7608. 8003880: 4648 mov r0, r9
  7609. 8003882: f7fe ff6b bl 800275c <ReadWordFromBufer>
  7610. 8003886: 4a81 ldr r2, [pc, #516] @ (8003a8c <Uart1ReceivedDataProcessCallback+0x5bc>)
  7611. 8003888: f10d 011e add.w r1, sp, #30
  7612. 800388c: 4648 mov r0, r9
  7613. 800388e: f7fe ff65 bl 800275c <ReadWordFromBufer>
  7614. 8003892: f10d 011e add.w r1, sp, #30
  7615. 8003896: 4648 mov r0, r9
  7616. 8003898: 4a7d ldr r2, [pc, #500] @ (8003a90 <Uart1ReceivedDataProcessCallback+0x5c0>)
  7617. 800389a: e074 b.n 8003986 <Uart1ReceivedDataProcessCallback+0x4b6>
  7618. PositionControlTaskData posXData __attribute__ ((aligned (32))) = { 0 };
  7619. 800389c: 2300 movs r3, #0
  7620. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  7621. 800389e: f8df 820c ldr.w r8, [pc, #524] @ 8003aac <Uart1ReceivedDataProcessCallback+0x5dc>
  7622. 80038a2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7623. 80038a6: f8d8 0000 ldr.w r0, [r8]
  7624. PositionControlTaskData posXData __attribute__ ((aligned (32))) = { 0 };
  7625. 80038aa: 603b str r3, [r7, #0]
  7626. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  7627. 80038ac: f008 faaa bl 800be04 <osMutexAcquire>
  7628. 80038b0: 2800 cmp r0, #0
  7629. 80038b2: f000 8233 beq.w 8003d1c <Uart1ReceivedDataProcessCallback+0x84c>
  7630. if (positionXControlTaskInitArg.positionSettingQueue != NULL)
  7631. 80038b6: f8df 8208 ldr.w r8, [pc, #520] @ 8003ac0 <Uart1ReceivedDataProcessCallback+0x5f0>
  7632. 80038ba: f8d8 3010 ldr.w r3, [r8, #16]
  7633. 80038be: 2b00 cmp r3, #0
  7634. 80038c0: f47f ae40 bne.w 8003544 <Uart1ReceivedDataProcessCallback+0x74>
  7635. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7636. 80038c4: 78a2 ldrb r2, [r4, #2]
  7637. SerialProtocolRespStatus respStatus = spUnknownCommand;
  7638. 80038c6: f06f 0302 mvn.w r3, #2
  7639. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7640. 80038ca: 8836 ldrh r6, [r6, #0]
  7641. 80038cc: 4f6b ldr r7, [pc, #428] @ (8003a7c <Uart1ReceivedDataProcessCallback+0x5ac>)
  7642. 80038ce: e721 b.n 8003714 <Uart1ReceivedDataProcessCallback+0x244>
  7643. float enocoderYValue = 0;
  7644. 80038d0: 2300 movs r3, #0
  7645. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  7646. 80038d2: f8df 81d8 ldr.w r8, [pc, #472] @ 8003aac <Uart1ReceivedDataProcessCallback+0x5dc>
  7647. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderYValue);
  7648. 80038d6: aa09 add r2, sp, #36 @ 0x24
  7649. 80038d8: f10d 011e add.w r1, sp, #30
  7650. 80038dc: f104 000c add.w r0, r4, #12
  7651. float enocoderYValue = 0;
  7652. 80038e0: 9309 str r3, [sp, #36] @ 0x24
  7653. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderYValue);
  7654. 80038e2: f7fe ff3b bl 800275c <ReadWordFromBufer>
  7655. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  7656. 80038e6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7657. 80038ea: f8d8 0000 ldr.w r0, [r8]
  7658. 80038ee: f008 fa89 bl 800be04 <osMutexAcquire>
  7659. 80038f2: 4607 mov r7, r0
  7660. 80038f4: 2800 cmp r0, #0
  7661. 80038f6: f47f aee1 bne.w 80036bc <Uart1ReceivedDataProcessCallback+0x1ec>
  7662. sensorsInfo.pvEncoderY = enocoderYValue;
  7663. 80038fa: 9a09 ldr r2, [sp, #36] @ 0x24
  7664. 80038fc: 4b65 ldr r3, [pc, #404] @ (8003a94 <Uart1ReceivedDataProcessCallback+0x5c4>)
  7665. osMutexRelease (sensorsInfoMutex);
  7666. 80038fe: f8d8 0000 ldr.w r0, [r8]
  7667. sensorsInfo.pvEncoderY = enocoderYValue;
  7668. 8003902: 611a str r2, [r3, #16]
  7669. osMutexRelease (sensorsInfoMutex);
  7670. 8003904: f008 faa2 bl 800be4c <osMutexRelease>
  7671. respStatus = spOK;
  7672. 8003908: 463b mov r3, r7
  7673. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7674. 800390a: 78a2 ldrb r2, [r4, #2]
  7675. 800390c: 8836 ldrh r6, [r6, #0]
  7676. 800390e: 4f5b ldr r7, [pc, #364] @ (8003a7c <Uart1ReceivedDataProcessCallback+0x5ac>)
  7677. 8003910: e700 b.n 8003714 <Uart1ReceivedDataProcessCallback+0x244>
  7678. float enocoderXValue = 0;
  7679. 8003912: 2300 movs r3, #0
  7680. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  7681. 8003914: f8df 8194 ldr.w r8, [pc, #404] @ 8003aac <Uart1ReceivedDataProcessCallback+0x5dc>
  7682. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderXValue);
  7683. 8003918: aa09 add r2, sp, #36 @ 0x24
  7684. 800391a: f10d 011e add.w r1, sp, #30
  7685. 800391e: f104 000c add.w r0, r4, #12
  7686. float enocoderXValue = 0;
  7687. 8003922: 9309 str r3, [sp, #36] @ 0x24
  7688. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderXValue);
  7689. 8003924: f7fe ff1a bl 800275c <ReadWordFromBufer>
  7690. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  7691. 8003928: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7692. 800392c: f8d8 0000 ldr.w r0, [r8]
  7693. 8003930: f008 fa68 bl 800be04 <osMutexAcquire>
  7694. 8003934: 4607 mov r7, r0
  7695. 8003936: 2800 cmp r0, #0
  7696. 8003938: f47f aec0 bne.w 80036bc <Uart1ReceivedDataProcessCallback+0x1ec>
  7697. sensorsInfo.pvEncoderX = enocoderXValue;
  7698. 800393c: 9a09 ldr r2, [sp, #36] @ 0x24
  7699. 800393e: 4b55 ldr r3, [pc, #340] @ (8003a94 <Uart1ReceivedDataProcessCallback+0x5c4>)
  7700. osMutexRelease (sensorsInfoMutex);
  7701. 8003940: f8d8 0000 ldr.w r0, [r8]
  7702. sensorsInfo.pvEncoderX = enocoderXValue;
  7703. 8003944: 60da str r2, [r3, #12]
  7704. osMutexRelease (sensorsInfoMutex);
  7705. 8003946: e7dd b.n 8003904 <Uart1ReceivedDataProcessCallback+0x434>
  7706. if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) {
  7707. 8003948: f8df a170 ldr.w sl, [pc, #368] @ 8003abc <Uart1ReceivedDataProcessCallback+0x5ec>
  7708. 800394c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7709. 8003950: f8da 0000 ldr.w r0, [sl]
  7710. 8003954: f008 fa56 bl 800be04 <osMutexAcquire>
  7711. 8003958: 4680 mov r8, r0
  7712. 800395a: 2800 cmp r0, #0
  7713. 800395c: f47f aeae bne.w 80036bc <Uart1ReceivedDataProcessCallback+0x1ec>
  7714. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse);
  7715. 8003960: f104 090c add.w r9, r4, #12
  7716. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].gain);
  7717. 8003964: 4a4c ldr r2, [pc, #304] @ (8003a98 <Uart1ReceivedDataProcessCallback+0x5c8>)
  7718. 8003966: f10d 011e add.w r1, sp, #30
  7719. 800396a: 4f44 ldr r7, [pc, #272] @ (8003a7c <Uart1ReceivedDataProcessCallback+0x5ac>)
  7720. 800396c: 4648 mov r0, r9
  7721. 800396e: f7fe fef5 bl 800275c <ReadWordFromBufer>
  7722. 8003972: 4a4a ldr r2, [pc, #296] @ (8003a9c <Uart1ReceivedDataProcessCallback+0x5cc>)
  7723. 8003974: f10d 011e add.w r1, sp, #30
  7724. 8003978: 4648 mov r0, r9
  7725. 800397a: f7fe feef bl 800275c <ReadWordFromBufer>
  7726. 800397e: f10d 011e add.w r1, sp, #30
  7727. 8003982: 4648 mov r0, r9
  7728. 8003984: 4a46 ldr r2, [pc, #280] @ (8003aa0 <Uart1ReceivedDataProcessCallback+0x5d0>)
  7729. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].offset);
  7730. 8003986: f7fe fee9 bl 800275c <ReadWordFromBufer>
  7731. osMutexRelease (resMeasurementsMutex);
  7732. 800398a: f8da 0000 ldr.w r0, [sl]
  7733. 800398e: f008 fa5d bl 800be4c <osMutexRelease>
  7734. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7735. 8003992: 8836 ldrh r6, [r6, #0]
  7736. respStatus = spOK;
  7737. 8003994: 4643 mov r3, r8
  7738. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  7739. 8003996: 78a2 ldrb r2, [r4, #2]
  7740. 8003998: e6bc b.n 8003714 <Uart1ReceivedDataProcessCallback+0x244>
  7741. osTimerStop (fanTimerHandle);
  7742. 800399a: f8df 8128 ldr.w r8, [pc, #296] @ 8003ac4 <Uart1ReceivedDataProcessCallback+0x5f4>
  7743. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse);
  7744. 800399e: f104 070c add.w r7, r4, #12
  7745. osTimerStop (fanTimerHandle);
  7746. 80039a2: f8d8 0000 ldr.w r0, [r8]
  7747. 80039a6: f008 f9cb bl 800bd40 <osTimerStop>
  7748. int32_t fanTimerPeriod = 0;
  7749. 80039aa: 2300 movs r3, #0
  7750. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse);
  7751. 80039ac: aa09 add r2, sp, #36 @ 0x24
  7752. 80039ae: f10d 011e add.w r1, sp, #30
  7753. 80039b2: 4638 mov r0, r7
  7754. uint32_t pulse = 0;
  7755. 80039b4: e9cd 3308 strd r3, r3, [sp, #32]
  7756. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse);
  7757. 80039b8: f7fe fed0 bl 800275c <ReadWordFromBufer>
  7758. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&fanTimerPeriod);
  7759. 80039bc: f10d 011e add.w r1, sp, #30
  7760. 80039c0: 4638 mov r0, r7
  7761. 80039c2: aa08 add r2, sp, #32
  7762. 80039c4: f7fe feca bl 800275c <ReadWordFromBufer>
  7763. fanTimerConfigOC.Pulse = pulse * 10;
  7764. 80039c8: 9b09 ldr r3, [sp, #36] @ 0x24
  7765. 80039ca: 4936 ldr r1, [pc, #216] @ (8003aa4 <Uart1ReceivedDataProcessCallback+0x5d4>)
  7766. if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) {
  7767. 80039cc: 2204 movs r2, #4
  7768. fanTimerConfigOC.Pulse = pulse * 10;
  7769. 80039ce: eb03 0383 add.w r3, r3, r3, lsl #2
  7770. if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) {
  7771. 80039d2: 4835 ldr r0, [pc, #212] @ (8003aa8 <Uart1ReceivedDataProcessCallback+0x5d8>)
  7772. fanTimerConfigOC.Pulse = pulse * 10;
  7773. 80039d4: 005b lsls r3, r3, #1
  7774. 80039d6: 604b str r3, [r1, #4]
  7775. if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) {
  7776. 80039d8: f006 fca0 bl 800a31c <HAL_TIM_PWM_ConfigChannel>
  7777. 80039dc: 2800 cmp r0, #0
  7778. 80039de: f040 81b0 bne.w 8003d42 <Uart1ReceivedDataProcessCallback+0x872>
  7779. if (fanTimerPeriod > 0) {
  7780. 80039e2: 9f08 ldr r7, [sp, #32]
  7781. 80039e4: 2f00 cmp r7, #0
  7782. 80039e6: f300 8170 bgt.w 8003cca <Uart1ReceivedDataProcessCallback+0x7fa>
  7783. } else if (fanTimerPeriod == 0) {
  7784. 80039ea: f000 81ad beq.w 8003d48 <Uart1ReceivedDataProcessCallback+0x878>
  7785. } else if (fanTimerPeriod == -1) {
  7786. 80039ee: 3701 adds r7, #1
  7787. 80039f0: f47f ae8c bne.w 800370c <Uart1ReceivedDataProcessCallback+0x23c>
  7788. osTimerStop (fanTimerHandle);
  7789. 80039f4: f8d8 0000 ldr.w r0, [r8]
  7790. 80039f8: f008 f9a2 bl 800bd40 <osTimerStop>
  7791. HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2);
  7792. 80039fc: 2104 movs r1, #4
  7793. 80039fe: 482a ldr r0, [pc, #168] @ (8003aa8 <Uart1ReceivedDataProcessCallback+0x5d8>)
  7794. 8003a00: f006 f98a bl 8009d18 <HAL_TIM_PWM_Start>
  7795. 8003a04: e682 b.n 800370c <Uart1ReceivedDataProcessCallback+0x23c>
  7796. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse);
  7797. 8003a06: f101 070c add.w r7, r1, #12
  7798. int32_t motorXPWMPulse = 0;
  7799. 8003a0a: 2300 movs r3, #0
  7800. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse);
  7801. 8003a0c: aa08 add r2, sp, #32
  7802. 8003a0e: f10d 011e add.w r1, sp, #30
  7803. 8003a12: 4638 mov r0, r7
  7804. int32_t motorXTimerPeriod = 0;
  7805. 8003a14: e9cd 3308 strd r3, r3, [sp, #32]
  7806. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse);
  7807. 8003a18: f7fe fea0 bl 800275c <ReadWordFromBufer>
  7808. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod);
  7809. 8003a1c: 4638 mov r0, r7
  7810. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  7811. 8003a1e: 4f23 ldr r7, [pc, #140] @ (8003aac <Uart1ReceivedDataProcessCallback+0x5dc>)
  7812. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod);
  7813. 8003a20: f10d 011e add.w r1, sp, #30
  7814. 8003a24: aa09 add r2, sp, #36 @ 0x24
  7815. 8003a26: f7fe fe99 bl 800275c <ReadWordFromBufer>
  7816. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  7817. 8003a2a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7818. 8003a2e: 6838 ldr r0, [r7, #0]
  7819. 8003a30: f008 f9e8 bl 800be04 <osMutexAcquire>
  7820. 8003a34: 2800 cmp r0, #0
  7821. 8003a36: f47f ae41 bne.w 80036bc <Uart1ReceivedDataProcessCallback+0x1ec>
  7822. MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, motorXPWMPulse, motorXTimerPeriod, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown);
  7823. 8003a3a: 4b1d ldr r3, [pc, #116] @ (8003ab0 <Uart1ReceivedDataProcessCallback+0x5e0>)
  7824. 8003a3c: 4602 mov r2, r0
  7825. 8003a3e: f8df 8054 ldr.w r8, [pc, #84] @ 8003a94 <Uart1ReceivedDataProcessCallback+0x5c4>
  7826. 8003a42: 681b ldr r3, [r3, #0]
  7827. 8003a44: 491b ldr r1, [pc, #108] @ (8003ab4 <Uart1ReceivedDataProcessCallback+0x5e4>)
  7828. 8003a46: 9300 str r3, [sp, #0]
  7829. 8003a48: f898 3029 ldrb.w r3, [r8, #41] @ 0x29
  7830. 8003a4c: 481a ldr r0, [pc, #104] @ (8003ab8 <Uart1ReceivedDataProcessCallback+0x5e8>)
  7831. 8003a4e: 9304 str r3, [sp, #16]
  7832. 8003a50: f898 3028 ldrb.w r3, [r8, #40] @ 0x28
  7833. 8003a54: 9303 str r3, [sp, #12]
  7834. 8003a56: 9b09 ldr r3, [sp, #36] @ 0x24
  7835. 8003a58: 9302 str r3, [sp, #8]
  7836. 8003a5a: 9b08 ldr r3, [sp, #32]
  7837. 8003a5c: 9301 str r3, [sp, #4]
  7838. 8003a5e: 2304 movs r3, #4
  7839. 8003a60: f7fe fafa bl 8002058 <MotorControl>
  7840. if (motorXStatus == 1) {
  7841. 8003a64: 2801 cmp r0, #1
  7842. sensorsInfo.motorXStatus = motorXStatus;
  7843. 8003a66: f888 0014 strb.w r0, [r8, #20]
  7844. if (motorXStatus == 1) {
  7845. 8003a6a: f040 8153 bne.w 8003d14 <Uart1ReceivedDataProcessCallback+0x844>
  7846. sensorsInfo.motorXPeakCurrent = 0.0;
  7847. 8003a6e: 2300 movs r3, #0
  7848. 8003a70: f8c8 3020 str.w r3, [r8, #32]
  7849. 8003a74: e14e b.n 8003d14 <Uart1ReceivedDataProcessCallback+0x844>
  7850. 8003a76: bf00 nop
  7851. 8003a78: 24000000 .word 0x24000000
  7852. 8003a7c: 24000abc .word 0x24000abc
  7853. 8003a80: 24000008 .word 0x24000008
  7854. 8003a84: 24000010 .word 0x24000010
  7855. 8003a88: 24000004 .word 0x24000004
  7856. 8003a8c: 2400000c .word 0x2400000c
  7857. 8003a90: 24000014 .word 0x24000014
  7858. 8003a94: 24000900 .word 0x24000900
  7859. 8003a98: 24000018 .word 0x24000018
  7860. 8003a9c: 24000020 .word 0x24000020
  7861. 8003aa0: 24000028 .word 0x24000028
  7862. 8003aa4: 240002ac .word 0x240002ac
  7863. 8003aa8: 2400054c .word 0x2400054c
  7864. 8003aac: 24000980 .word 0x24000980
  7865. 8003ab0: 24000324 .word 0x24000324
  7866. 8003ab4: 24000290 .word 0x24000290
  7867. 8003ab8: 24000500 .word 0x24000500
  7868. 8003abc: 24000984 .word 0x24000984
  7869. 8003ac0: 24000a00 .word 0x24000a00
  7870. 8003ac4: 24000354 .word 0x24000354
  7871. if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) {
  7872. 8003ac8: f8df 92e4 ldr.w r9, [pc, #740] @ 8003db0 <Uart1ReceivedDataProcessCallback+0x8e0>
  7873. 8003acc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  7874. 8003ad0: f8d9 0000 ldr.w r0, [r9]
  7875. 8003ad4: f008 f996 bl 800be04 <osMutexAcquire>
  7876. 8003ad8: 4607 mov r7, r0
  7877. 8003ada: 2800 cmp r0, #0
  7878. 8003adc: f47f adee bne.w 80036bc <Uart1ReceivedDataProcessCallback+0x1ec>
  7879. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof (float));
  7880. 8003ae0: f8df 82c4 ldr.w r8, [pc, #708] @ 8003da8 <Uart1ReceivedDataProcessCallback+0x8d8>
  7881. 8003ae4: 2304 movs r3, #4
  7882. 8003ae6: 49a7 ldr r1, [pc, #668] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7883. 8003ae8: 48a7 ldr r0, [pc, #668] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7884. 8003aea: 4642 mov r2, r8
  7885. 8003aec: f7fe fe04 bl 80026f8 <WriteDataToBuffer>
  7886. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof (float));
  7887. 8003af0: 2304 movs r3, #4
  7888. 8003af2: 49a4 ldr r1, [pc, #656] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7889. 8003af4: eb08 0203 add.w r2, r8, r3
  7890. 8003af8: 48a3 ldr r0, [pc, #652] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7891. 8003afa: f7fe fdfd bl 80026f8 <WriteDataToBuffer>
  7892. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof (float));
  7893. 8003afe: 2304 movs r3, #4
  7894. 8003b00: f108 0208 add.w r2, r8, #8
  7895. 8003b04: 499f ldr r1, [pc, #636] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7896. 8003b06: 48a0 ldr r0, [pc, #640] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7897. 8003b08: f7fe fdf6 bl 80026f8 <WriteDataToBuffer>
  7898. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderX, sizeof (float));
  7899. 8003b0c: 2304 movs r3, #4
  7900. 8003b0e: f108 020c add.w r2, r8, #12
  7901. 8003b12: 499c ldr r1, [pc, #624] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7902. 8003b14: 489c ldr r0, [pc, #624] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7903. 8003b16: f7fe fdef bl 80026f8 <WriteDataToBuffer>
  7904. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderY, sizeof (float));
  7905. 8003b1a: 2304 movs r3, #4
  7906. 8003b1c: f108 0210 add.w r2, r8, #16
  7907. 8003b20: 4998 ldr r1, [pc, #608] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7908. 8003b22: 4899 ldr r0, [pc, #612] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7909. 8003b24: f7fe fde8 bl 80026f8 <WriteDataToBuffer>
  7910. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof (uint8_t));
  7911. 8003b28: 2301 movs r3, #1
  7912. 8003b2a: f108 0214 add.w r2, r8, #20
  7913. 8003b2e: 4995 ldr r1, [pc, #596] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7914. 8003b30: 4895 ldr r0, [pc, #596] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7915. 8003b32: f7fe fde1 bl 80026f8 <WriteDataToBuffer>
  7916. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof (uint8_t));
  7917. 8003b36: 2301 movs r3, #1
  7918. 8003b38: f108 0215 add.w r2, r8, #21
  7919. 8003b3c: 4991 ldr r1, [pc, #580] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7920. 8003b3e: 4892 ldr r0, [pc, #584] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7921. 8003b40: f7fe fdda bl 80026f8 <WriteDataToBuffer>
  7922. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof (float));
  7923. 8003b44: 2304 movs r3, #4
  7924. 8003b46: f108 0218 add.w r2, r8, #24
  7925. 8003b4a: 498e ldr r1, [pc, #568] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7926. 8003b4c: 488e ldr r0, [pc, #568] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7927. 8003b4e: f7fe fdd3 bl 80026f8 <WriteDataToBuffer>
  7928. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof (float));
  7929. 8003b52: 2304 movs r3, #4
  7930. 8003b54: f108 021c add.w r2, r8, #28
  7931. 8003b58: 498a ldr r1, [pc, #552] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7932. 8003b5a: 488b ldr r0, [pc, #556] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7933. 8003b5c: f7fe fdcc bl 80026f8 <WriteDataToBuffer>
  7934. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof (float));
  7935. 8003b60: 2304 movs r3, #4
  7936. 8003b62: f108 0220 add.w r2, r8, #32
  7937. 8003b66: 4987 ldr r1, [pc, #540] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7938. 8003b68: 4887 ldr r0, [pc, #540] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7939. 8003b6a: f7fe fdc5 bl 80026f8 <WriteDataToBuffer>
  7940. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof (float));
  7941. 8003b6e: 2304 movs r3, #4
  7942. 8003b70: f108 0224 add.w r2, r8, #36 @ 0x24
  7943. 8003b74: 4983 ldr r1, [pc, #524] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7944. 8003b76: 4884 ldr r0, [pc, #528] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7945. 8003b78: f7fe fdbe bl 80026f8 <WriteDataToBuffer>
  7946. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchUp, sizeof (uint8_t));
  7947. 8003b7c: 2301 movs r3, #1
  7948. 8003b7e: f108 0228 add.w r2, r8, #40 @ 0x28
  7949. 8003b82: 4980 ldr r1, [pc, #512] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7950. 8003b84: 4880 ldr r0, [pc, #512] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7951. 8003b86: f7fe fdb7 bl 80026f8 <WriteDataToBuffer>
  7952. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchDown, sizeof (uint8_t));
  7953. 8003b8a: 2301 movs r3, #1
  7954. 8003b8c: f108 0229 add.w r2, r8, #41 @ 0x29
  7955. 8003b90: 497c ldr r1, [pc, #496] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7956. 8003b92: 487d ldr r0, [pc, #500] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7957. 8003b94: f7fe fdb0 bl 80026f8 <WriteDataToBuffer>
  7958. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchCenter, sizeof (uint8_t));
  7959. 8003b98: 2301 movs r3, #1
  7960. 8003b9a: f108 022a add.w r2, r8, #42 @ 0x2a
  7961. 8003b9e: 4979 ldr r1, [pc, #484] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7962. 8003ba0: 4879 ldr r0, [pc, #484] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7963. 8003ba2: f7fe fda9 bl 80026f8 <WriteDataToBuffer>
  7964. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchUp, sizeof (uint8_t));
  7965. 8003ba6: 2301 movs r3, #1
  7966. 8003ba8: f108 022b add.w r2, r8, #43 @ 0x2b
  7967. 8003bac: 4975 ldr r1, [pc, #468] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7968. 8003bae: 4876 ldr r0, [pc, #472] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7969. 8003bb0: f7fe fda2 bl 80026f8 <WriteDataToBuffer>
  7970. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchDown, sizeof (uint8_t));
  7971. 8003bb4: 2301 movs r3, #1
  7972. 8003bb6: f108 022c add.w r2, r8, #44 @ 0x2c
  7973. 8003bba: 4972 ldr r1, [pc, #456] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7974. 8003bbc: 4872 ldr r0, [pc, #456] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7975. 8003bbe: f7fe fd9b bl 80026f8 <WriteDataToBuffer>
  7976. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchCenter, sizeof (uint8_t));
  7977. 8003bc2: 2301 movs r3, #1
  7978. 8003bc4: f108 022d add.w r2, r8, #45 @ 0x2d
  7979. 8003bc8: 496e ldr r1, [pc, #440] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7980. 8003bca: 486f ldr r0, [pc, #444] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  7981. 8003bcc: f7fe fd94 bl 80026f8 <WriteDataToBuffer>
  7982. uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0;
  7983. 8003bd0: 486e ldr r0, [pc, #440] @ (8003d8c <Uart1ReceivedDataProcessCallback+0x8bc>)
  7984. 8003bd2: f001 f98d bl 8004ef0 <HAL_COMP_GetOutputLevel>
  7985. 8003bd6: 4682 mov sl, r0
  7986. sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01;
  7987. 8003bd8: 2108 movs r1, #8
  7988. 8003bda: 486d ldr r0, [pc, #436] @ (8003d90 <Uart1ReceivedDataProcessCallback+0x8c0>)
  7989. uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0;
  7990. 8003bdc: f1aa 0a01 sub.w sl, sl, #1
  7991. sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01;
  7992. 8003be0: f003 fae6 bl 80071b0 <HAL_GPIO_ReadPin>
  7993. 8003be4: 4642 mov r2, r8
  7994. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t));
  7995. 8003be6: 4967 ldr r1, [pc, #412] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  7996. uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0;
  7997. 8003be8: faba fa8a clz sl, sl
  7998. 8003bec: ea4f 1a5a mov.w sl, sl, lsr #5
  7999. sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01;
  8000. 8003bf0: ea40 034a orr.w r3, r0, sl, lsl #1
  8001. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t));
  8002. 8003bf4: 4864 ldr r0, [pc, #400] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  8003. sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01;
  8004. 8003bf6: 43db mvns r3, r3
  8005. 8003bf8: f003 0301 and.w r3, r3, #1
  8006. 8003bfc: f802 3f2e strb.w r3, [r2, #46]!
  8007. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t));
  8008. 8003c00: 2301 movs r3, #1
  8009. 8003c02: f7fe fd79 bl 80026f8 <WriteDataToBuffer>
  8010. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentXPosition, sizeof (float));
  8011. 8003c06: 2304 movs r3, #4
  8012. 8003c08: f108 0230 add.w r2, r8, #48 @ 0x30
  8013. 8003c0c: 495d ldr r1, [pc, #372] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  8014. 8003c0e: 485e ldr r0, [pc, #376] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  8015. 8003c10: f7fe fd72 bl 80026f8 <WriteDataToBuffer>
  8016. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentYPosition, sizeof (float));
  8017. 8003c14: 2304 movs r3, #4
  8018. 8003c16: f108 0234 add.w r2, r8, #52 @ 0x34
  8019. 8003c1a: 495a ldr r1, [pc, #360] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  8020. 8003c1c: 485a ldr r0, [pc, #360] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  8021. 8003c1e: f7fe fd6b bl 80026f8 <WriteDataToBuffer>
  8022. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionXWeak, sizeof (uint8_t));
  8023. 8003c22: 2301 movs r3, #1
  8024. 8003c24: f108 0238 add.w r2, r8, #56 @ 0x38
  8025. 8003c28: 4956 ldr r1, [pc, #344] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  8026. 8003c2a: 4857 ldr r0, [pc, #348] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  8027. 8003c2c: f7fe fd64 bl 80026f8 <WriteDataToBuffer>
  8028. WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionYWeak, sizeof (uint8_t));
  8029. 8003c30: 4855 ldr r0, [pc, #340] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  8030. 8003c32: f108 0239 add.w r2, r8, #57 @ 0x39
  8031. 8003c36: 2301 movs r3, #1
  8032. 8003c38: 4952 ldr r1, [pc, #328] @ (8003d84 <Uart1ReceivedDataProcessCallback+0x8b4>)
  8033. 8003c3a: f7fe fd5d bl 80026f8 <WriteDataToBuffer>
  8034. osMutexRelease (sensorsInfoMutex);
  8035. 8003c3e: f8d9 0000 ldr.w r0, [r9]
  8036. 8003c42: e65f b.n 8003904 <Uart1ReceivedDataProcessCallback+0x434>
  8037. osTimerStop (debugLedTimerHandle);
  8038. 8003c44: f8df 916c ldr.w r9, [pc, #364] @ 8003db4 <Uart1ReceivedDataProcessCallback+0x8e4>
  8039. int32_t dbgLedTimerPeriod = 0;
  8040. 8003c48: 2700 movs r7, #0
  8041. osTimerStop (debugLedTimerHandle);
  8042. 8003c4a: f8d9 0000 ldr.w r0, [r9]
  8043. 8003c4e: f008 f877 bl 800bd40 <osTimerStop>
  8044. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod);
  8045. 8003c52: aa09 add r2, sp, #36 @ 0x24
  8046. 8003c54: f10d 011e add.w r1, sp, #30
  8047. 8003c58: f104 000c add.w r0, r4, #12
  8048. int32_t dbgLedTimerPeriod = 0;
  8049. 8003c5c: 9709 str r7, [sp, #36] @ 0x24
  8050. ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod);
  8051. 8003c5e: f7fe fd7d bl 800275c <ReadWordFromBufer>
  8052. if (dbgLedTimerPeriod > 0) {
  8053. 8003c62: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24
  8054. 8003c66: 45b8 cmp r8, r7
  8055. 8003c68: dc26 bgt.n 8003cb8 <Uart1ReceivedDataProcessCallback+0x7e8>
  8056. } else if (dbgLedTimerPeriod == 0) {
  8057. 8003c6a: d07a beq.n 8003d62 <Uart1ReceivedDataProcessCallback+0x892>
  8058. } else if (dbgLedTimerPeriod == -1) {
  8059. 8003c6c: f1b8 3fff cmp.w r8, #4294967295 @ 0xffffffff
  8060. 8003c70: f47f ad4c bne.w 800370c <Uart1ReceivedDataProcessCallback+0x23c>
  8061. osTimerStop (debugLedTimerHandle);
  8062. 8003c74: f8d9 0000 ldr.w r0, [r9]
  8063. 8003c78: f008 f862 bl 800bd40 <osTimerStop>
  8064. DbgLEDOn (DBG_LED1);
  8065. 8003c7c: 2010 movs r0, #16
  8066. 8003c7e: f7fe f9ad bl 8001fdc <DbgLEDOn>
  8067. respStatus = spOK;
  8068. 8003c82: 463b mov r3, r7
  8069. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  8070. 8003c84: 78a2 ldrb r2, [r4, #2]
  8071. 8003c86: 8836 ldrh r6, [r6, #0]
  8072. 8003c88: 4f3f ldr r7, [pc, #252] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  8073. 8003c8a: e543 b.n 8003714 <Uart1ReceivedDataProcessCallback+0x244>
  8074. HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend);
  8075. 8003c8c: 4602 mov r2, r0
  8076. 8003c8e: 68a9 ldr r1, [r5, #8]
  8077. 8003c90: 6b28 ldr r0, [r5, #48] @ 0x30
  8078. 8003c92: f006 fddb bl 800a84c <HAL_UART_Transmit_IT>
  8079. }
  8080. 8003c96: b013 add sp, #76 @ 0x4c
  8081. 8003c98: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  8082. __ASM volatile ("cpsid i" : : : "memory");
  8083. 8003c9c: b672 cpsid i
  8084. __ASM volatile ("dsb 0xF":::"memory");
  8085. 8003c9e: f3bf 8f4f dsb sy
  8086. (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
  8087. 8003ca2: 493c ldr r1, [pc, #240] @ (8003d94 <Uart1ReceivedDataProcessCallback+0x8c4>)
  8088. SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  8089. 8003ca4: 4b3c ldr r3, [pc, #240] @ (8003d98 <Uart1ReceivedDataProcessCallback+0x8c8>)
  8090. (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
  8091. 8003ca6: 68ca ldr r2, [r1, #12]
  8092. 8003ca8: f402 62e0 and.w r2, r2, #1792 @ 0x700
  8093. SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  8094. 8003cac: 4313 orrs r3, r2
  8095. 8003cae: 60cb str r3, [r1, #12]
  8096. 8003cb0: f3bf 8f4f dsb sy
  8097. __NOP();
  8098. 8003cb4: bf00 nop
  8099. for(;;) /* wait until reset */
  8100. 8003cb6: e7fd b.n 8003cb4 <Uart1ReceivedDataProcessCallback+0x7e4>
  8101. osTimerStart (debugLedTimerHandle, dbgLedTimerPeriod * 1000);
  8102. 8003cb8: f44f 717a mov.w r1, #1000 @ 0x3e8
  8103. 8003cbc: f8d9 0000 ldr.w r0, [r9]
  8104. 8003cc0: fb01 f108 mul.w r1, r1, r8
  8105. 8003cc4: f008 f824 bl 800bd10 <osTimerStart>
  8106. DbgLEDOn (DBG_LED1);
  8107. 8003cc8: e7d8 b.n 8003c7c <Uart1ReceivedDataProcessCallback+0x7ac>
  8108. osTimerStart (fanTimerHandle, fanTimerPeriod * 1000);
  8109. 8003cca: f44f 717a mov.w r1, #1000 @ 0x3e8
  8110. 8003cce: f8d8 0000 ldr.w r0, [r8]
  8111. 8003cd2: fb07 f101 mul.w r1, r7, r1
  8112. 8003cd6: f008 f81b bl 800bd10 <osTimerStart>
  8113. HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2);
  8114. 8003cda: e68f b.n 80039fc <Uart1ReceivedDataProcessCallback+0x52c>
  8115. MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, motorYPWMPulse, motorYTimerPeriod, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown);
  8116. 8003cdc: 4b2f ldr r3, [pc, #188] @ (8003d9c <Uart1ReceivedDataProcessCallback+0x8cc>)
  8117. 8003cde: 2208 movs r2, #8
  8118. 8003ce0: f8df 80c4 ldr.w r8, [pc, #196] @ 8003da8 <Uart1ReceivedDataProcessCallback+0x8d8>
  8119. 8003ce4: 681b ldr r3, [r3, #0]
  8120. 8003ce6: 492e ldr r1, [pc, #184] @ (8003da0 <Uart1ReceivedDataProcessCallback+0x8d0>)
  8121. 8003ce8: 9300 str r3, [sp, #0]
  8122. 8003cea: f898 302c ldrb.w r3, [r8, #44] @ 0x2c
  8123. 8003cee: 482d ldr r0, [pc, #180] @ (8003da4 <Uart1ReceivedDataProcessCallback+0x8d4>)
  8124. 8003cf0: 9304 str r3, [sp, #16]
  8125. 8003cf2: f898 302b ldrb.w r3, [r8, #43] @ 0x2b
  8126. 8003cf6: 9303 str r3, [sp, #12]
  8127. 8003cf8: 9b09 ldr r3, [sp, #36] @ 0x24
  8128. 8003cfa: 9302 str r3, [sp, #8]
  8129. 8003cfc: 9b08 ldr r3, [sp, #32]
  8130. 8003cfe: 9301 str r3, [sp, #4]
  8131. 8003d00: 230c movs r3, #12
  8132. 8003d02: f7fe f9a9 bl 8002058 <MotorControl>
  8133. if (motorYStatus == 1) {
  8134. 8003d06: 2801 cmp r0, #1
  8135. sensorsInfo.motorYStatus = motorYStatus;
  8136. 8003d08: f888 0015 strb.w r0, [r8, #21]
  8137. if (motorYStatus == 1) {
  8138. 8003d0c: d102 bne.n 8003d14 <Uart1ReceivedDataProcessCallback+0x844>
  8139. sensorsInfo.motorYPeakCurrent = 0.0;
  8140. 8003d0e: 2300 movs r3, #0
  8141. 8003d10: f8c8 3024 str.w r3, [r8, #36] @ 0x24
  8142. osMutexRelease (sensorsInfoMutex);
  8143. 8003d14: 6838 ldr r0, [r7, #0]
  8144. 8003d16: f008 f899 bl 800be4c <osMutexRelease>
  8145. respStatus = spOK;
  8146. 8003d1a: e4f7 b.n 800370c <Uart1ReceivedDataProcessCallback+0x23c>
  8147. sensorsInfo.positionXWeak = 1;
  8148. 8003d1c: 4b22 ldr r3, [pc, #136] @ (8003da8 <Uart1ReceivedDataProcessCallback+0x8d8>)
  8149. 8003d1e: 2201 movs r2, #1
  8150. osMutexRelease (sensorsInfoMutex);
  8151. 8003d20: f8d8 0000 ldr.w r0, [r8]
  8152. sensorsInfo.positionXWeak = 1;
  8153. 8003d24: f883 2038 strb.w r2, [r3, #56] @ 0x38
  8154. osMutexRelease (sensorsInfoMutex);
  8155. 8003d28: f008 f890 bl 800be4c <osMutexRelease>
  8156. 8003d2c: e5c3 b.n 80038b6 <Uart1ReceivedDataProcessCallback+0x3e6>
  8157. sensorsInfo.positionYWeak = 1;
  8158. 8003d2e: 4b1e ldr r3, [pc, #120] @ (8003da8 <Uart1ReceivedDataProcessCallback+0x8d8>)
  8159. 8003d30: 2201 movs r2, #1
  8160. osMutexRelease (sensorsInfoMutex);
  8161. 8003d32: f8d8 0000 ldr.w r0, [r8]
  8162. sensorsInfo.positionYWeak = 1;
  8163. 8003d36: f883 2039 strb.w r2, [r3, #57] @ 0x39
  8164. osMutexRelease (sensorsInfoMutex);
  8165. 8003d3a: f008 f887 bl 800be4c <osMutexRelease>
  8166. 8003d3e: f7ff bbf8 b.w 8003532 <Uart1ReceivedDataProcessCallback+0x62>
  8167. Error_Handler ();
  8168. 8003d42: f7fc fd59 bl 80007f8 <Error_Handler>
  8169. 8003d46: e64c b.n 80039e2 <Uart1ReceivedDataProcessCallback+0x512>
  8170. osTimerStop (fanTimerHandle);
  8171. 8003d48: f8d8 0000 ldr.w r0, [r8]
  8172. 8003d4c: f007 fff8 bl 800bd40 <osTimerStop>
  8173. HAL_TIM_PWM_Stop (&htim1, TIM_CHANNEL_2);
  8174. 8003d50: 2104 movs r1, #4
  8175. 8003d52: 4816 ldr r0, [pc, #88] @ (8003dac <Uart1ReceivedDataProcessCallback+0x8dc>)
  8176. 8003d54: f006 f880 bl 8009e58 <HAL_TIM_PWM_Stop>
  8177. respStatus = spOK;
  8178. 8003d58: 463b mov r3, r7
  8179. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  8180. 8003d5a: 78a2 ldrb r2, [r4, #2]
  8181. 8003d5c: 8836 ldrh r6, [r6, #0]
  8182. 8003d5e: 4f0a ldr r7, [pc, #40] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  8183. 8003d60: e4d8 b.n 8003714 <Uart1ReceivedDataProcessCallback+0x244>
  8184. osTimerStop (debugLedTimerHandle);
  8185. 8003d62: f8d9 0000 ldr.w r0, [r9]
  8186. 8003d66: f007 ffeb bl 800bd40 <osTimerStop>
  8187. DbgLEDOff (DBG_LED1);
  8188. 8003d6a: 2010 movs r0, #16
  8189. 8003d6c: f7fe f93e bl 8001fec <DbgLEDOff>
  8190. 8003d70: 4f05 ldr r7, [pc, #20] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  8191. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  8192. 8003d72: 78a2 ldrb r2, [r4, #2]
  8193. respStatus = spOK;
  8194. 8003d74: 4643 mov r3, r8
  8195. dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos);
  8196. 8003d76: 8836 ldrh r6, [r6, #0]
  8197. 8003d78: e4cc b.n 8003714 <Uart1ReceivedDataProcessCallback+0x244>
  8198. switch (spFrameData->frameHeader.frameCommand) {
  8199. 8003d7a: 2600 movs r6, #0
  8200. 8003d7c: f06f 0302 mvn.w r3, #2
  8201. 8003d80: 4f01 ldr r7, [pc, #4] @ (8003d88 <Uart1ReceivedDataProcessCallback+0x8b8>)
  8202. 8003d82: e4c7 b.n 8003714 <Uart1ReceivedDataProcessCallback+0x244>
  8203. 8003d84: 24000ab8 .word 0x24000ab8
  8204. 8003d88: 24000abc .word 0x24000abc
  8205. 8003d8c: 240005f4 .word 0x240005f4
  8206. 8003d90: 58020c00 .word 0x58020c00
  8207. 8003d94: e000ed00 .word 0xe000ed00
  8208. 8003d98: 05fa0004 .word 0x05fa0004
  8209. 8003d9c: 240002f4 .word 0x240002f4
  8210. 8003da0: 24000290 .word 0x24000290
  8211. 8003da4: 24000500 .word 0x24000500
  8212. 8003da8: 24000900 .word 0x24000900
  8213. 8003dac: 2400054c .word 0x2400054c
  8214. 8003db0: 24000980 .word 0x24000980
  8215. 8003db4: 24000384 .word 0x24000384
  8216. 08003db8 <Uart8ReceivedDataProcessCallback>:
  8217. Uart1ReceivedDataProcessCallback (arg, spFrameData);
  8218. 8003db8: f7ff bb8a b.w 80034d0 <Uart1ReceivedDataProcessCallback>
  8219. 08003dbc <UartTasksInit>:
  8220. void UartTasksInit (void) {
  8221. 8003dbc: b510 push {r4, lr}
  8222. uart1TaskData.uartRxBuffer = uart1RxBuffer;
  8223. 8003dbe: 4b1b ldr r3, [pc, #108] @ (8003e2c <UartTasksInit+0x70>)
  8224. uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE;
  8225. 8003dc0: f44f 7280 mov.w r2, #256 @ 0x100
  8226. uart1TaskData.uartRxBuffer = uart1RxBuffer;
  8227. 8003dc4: 4c1a ldr r4, [pc, #104] @ (8003e30 <UartTasksInit+0x74>)
  8228. void UartTasksInit (void) {
  8229. 8003dc6: b08a sub sp, #40 @ 0x28
  8230. uart8TaskData.uartRxBuffer = uart8RxBuffer;
  8231. 8003dc8: 481a ldr r0, [pc, #104] @ (8003e34 <UartTasksInit+0x78>)
  8232. uart1TaskData.processRxDataMsgBuffer = NULL;
  8233. 8003dca: 2100 movs r1, #0
  8234. uart1TaskData.uartRxBuffer = uart1RxBuffer;
  8235. 8003dcc: 6023 str r3, [r4, #0]
  8236. uart1TaskData.uartTxBuffer = uart1TxBuffer;
  8237. 8003dce: 4b1a ldr r3, [pc, #104] @ (8003e38 <UartTasksInit+0x7c>)
  8238. uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE;
  8239. 8003dd0: 80a2 strh r2, [r4, #4]
  8240. uart1TaskData.uartTxBuffer = uart1TxBuffer;
  8241. 8003dd2: 60a3 str r3, [r4, #8]
  8242. uart1TaskData.frameData = uart1TaskFrameData;
  8243. 8003dd4: 4b19 ldr r3, [pc, #100] @ (8003e3c <UartTasksInit+0x80>)
  8244. uart1TaskData.frameDataLen = UART1_RX_BUFF_SIZE;
  8245. 8003dd6: 82a2 strh r2, [r4, #20]
  8246. uart1TaskData.frameData = uart1TaskFrameData;
  8247. 8003dd8: 6123 str r3, [r4, #16]
  8248. uart1TaskData.huart = &huart1;
  8249. 8003dda: 4b19 ldr r3, [pc, #100] @ (8003e40 <UartTasksInit+0x84>)
  8250. uart1TaskData.processRxDataMsgBuffer = NULL;
  8251. 8003ddc: 6261 str r1, [r4, #36] @ 0x24
  8252. uart1TaskData.huart = &huart1;
  8253. 8003dde: 6323 str r3, [r4, #48] @ 0x30
  8254. uart1TaskData.uartNumber = 1;
  8255. 8003de0: 2301 movs r3, #1
  8256. 8003de2: f884 3034 strb.w r3, [r4, #52] @ 0x34
  8257. uart1TaskData.processDataCb = Uart1ReceivedDataProcessCallback;
  8258. 8003de6: 4b17 ldr r3, [pc, #92] @ (8003e44 <UartTasksInit+0x88>)
  8259. 8003de8: 62a3 str r3, [r4, #40] @ 0x28
  8260. uart8TaskData.uartRxBuffer = uart8RxBuffer;
  8261. 8003dea: 4b17 ldr r3, [pc, #92] @ (8003e48 <UartTasksInit+0x8c>)
  8262. uart8TaskData.uartRxBufferLen = UART8_RX_BUFF_SIZE;
  8263. 8003dec: 809a strh r2, [r3, #4]
  8264. uart8TaskData.frameDataLen = UART8_RX_BUFF_SIZE;
  8265. 8003dee: 829a strh r2, [r3, #20]
  8266. uart8TaskData.huart = &huart8;
  8267. 8003df0: 4a16 ldr r2, [pc, #88] @ (8003e4c <UartTasksInit+0x90>)
  8268. uart8TaskData.uartRxBuffer = uart8RxBuffer;
  8269. 8003df2: 6018 str r0, [r3, #0]
  8270. uart8TaskData.huart = &huart8;
  8271. 8003df4: 631a str r2, [r3, #48] @ 0x30
  8272. uart8TaskData.uartNumber = 8;
  8273. 8003df6: 2208 movs r2, #8
  8274. uart8TaskData.uartTxBuffer = uart8TxBuffer;
  8275. 8003df8: 4815 ldr r0, [pc, #84] @ (8003e50 <UartTasksInit+0x94>)
  8276. uart8TaskData.uartNumber = 8;
  8277. 8003dfa: f883 2034 strb.w r2, [r3, #52] @ 0x34
  8278. uart8TaskData.uartTxBuffer = uart8TxBuffer;
  8279. 8003dfe: 6098 str r0, [r3, #8]
  8280. uart8TaskData.processDataCb = Uart8ReceivedDataProcessCallback;
  8281. 8003e00: 4a14 ldr r2, [pc, #80] @ (8003e54 <UartTasksInit+0x98>)
  8282. uart8TaskData.frameData = uart8TaskFrameData;
  8283. 8003e02: 4815 ldr r0, [pc, #84] @ (8003e58 <UartTasksInit+0x9c>)
  8284. uart8TaskData.processDataCb = Uart8ReceivedDataProcessCallback;
  8285. 8003e04: 629a str r2, [r3, #40] @ 0x28
  8286. osThreadAttr_t osThreadAttrRxUart = { 0 };
  8287. 8003e06: 2224 movs r2, #36 @ 0x24
  8288. uart8TaskData.frameData = uart8TaskFrameData;
  8289. 8003e08: 6118 str r0, [r3, #16]
  8290. osThreadAttr_t osThreadAttrRxUart = { 0 };
  8291. 8003e0a: a801 add r0, sp, #4
  8292. uart8TaskData.processRxDataMsgBuffer = NULL;
  8293. 8003e0c: 6259 str r1, [r3, #36] @ 0x24
  8294. osThreadAttr_t osThreadAttrRxUart = { 0 };
  8295. 8003e0e: f00b fe7b bl 800fb08 <memset>
  8296. osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh;
  8297. 8003e12: 2328 movs r3, #40 @ 0x28
  8298. osThreadAttrRxUart.stack_size = configMINIMAL_STACK_SIZE * 2;
  8299. 8003e14: f44f 6080 mov.w r0, #1024 @ 0x400
  8300. uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart);
  8301. 8003e18: aa01 add r2, sp, #4
  8302. 8003e1a: 4621 mov r1, r4
  8303. osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh;
  8304. 8003e1c: e9cd 0306 strd r0, r3, [sp, #24]
  8305. uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart);
  8306. 8003e20: 480e ldr r0, [pc, #56] @ (8003e5c <UartTasksInit+0xa0>)
  8307. 8003e22: f007 fee3 bl 800bbec <osThreadNew>
  8308. 8003e26: 61a0 str r0, [r4, #24]
  8309. }
  8310. 8003e28: b00a add sp, #40 @ 0x28
  8311. 8003e2a: bd10 pop {r4, pc}
  8312. 8003e2c: 240010ac .word 0x240010ac
  8313. 8003e30: 24000b74 .word 0x24000b74
  8314. 8003e34: 24000dac .word 0x24000dac
  8315. 8003e38: 24000fac .word 0x24000fac
  8316. 8003e3c: 24000eac .word 0x24000eac
  8317. 8003e40: 2400038c .word 0x2400038c
  8318. 8003e44: 080034d1 .word 0x080034d1
  8319. 8003e48: 24000b3c .word 0x24000b3c
  8320. 8003e4c: 24000420 .word 0x24000420
  8321. 8003e50: 24000cac .word 0x24000cac
  8322. 8003e54: 08003db9 .word 0x08003db9
  8323. 8003e58: 24000bac .word 0x24000bac
  8324. 8003e5c: 08003211 .word 0x08003211
  8325. 08003e60 <HAL_UART_RxCpltCallback>:
  8326. void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) {
  8327. 8003e60: 4770 bx lr
  8328. 8003e62: bf00 nop
  8329. 08003e64 <HAL_UART_TxCpltCallback>:
  8330. }
  8331. 8003e64: 4770 bx lr
  8332. 8003e66: bf00 nop
  8333. 08003e68 <HandleUartRxCallback>:
  8334. void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) {
  8335. 8003e68: b570 push {r4, r5, r6, lr}
  8336. 8003e6a: 4604 mov r4, r0
  8337. 8003e6c: b084 sub sp, #16
  8338. BaseType_t pxHigherPriorityTaskWoken = pdFALSE;
  8339. 8003e6e: 2600 movs r6, #0
  8340. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  8341. 8003e70: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  8342. 8003e74: 6a00 ldr r0, [r0, #32]
  8343. void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) {
  8344. 8003e76: 4615 mov r5, r2
  8345. BaseType_t pxHigherPriorityTaskWoken = pdFALSE;
  8346. 8003e78: 9603 str r6, [sp, #12]
  8347. osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever);
  8348. 8003e7a: f007 ffc3 bl 800be04 <osMutexAcquire>
  8349. memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size);
  8350. 8003e7e: 8ae3 ldrh r3, [r4, #22]
  8351. 8003e80: 462a mov r2, r5
  8352. 8003e82: 6920 ldr r0, [r4, #16]
  8353. 8003e84: 6821 ldr r1, [r4, #0]
  8354. 8003e86: 4418 add r0, r3
  8355. 8003e88: f00b ff13 bl 800fcb2 <memcpy>
  8356. uartTaskData->frameBytesCount += Size;
  8357. 8003e8c: 8ae2 ldrh r2, [r4, #22]
  8358. osMutexRelease (uartTaskData->rxDataBufferMutex);
  8359. 8003e8e: 6a20 ldr r0, [r4, #32]
  8360. uartTaskData->frameBytesCount += Size;
  8361. 8003e90: 442a add r2, r5
  8362. 8003e92: 82e2 strh r2, [r4, #22]
  8363. osMutexRelease (uartTaskData->rxDataBufferMutex);
  8364. 8003e94: f007 ffda bl 800be4c <osMutexRelease>
  8365. xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken);
  8366. 8003e98: a803 add r0, sp, #12
  8367. 8003e9a: 4633 mov r3, r6
  8368. 8003e9c: 2203 movs r2, #3
  8369. 8003e9e: 4629 mov r1, r5
  8370. 8003ea0: 9000 str r0, [sp, #0]
  8371. 8003ea2: 69a0 ldr r0, [r4, #24]
  8372. 8003ea4: f00a f928 bl 800e0f8 <xTaskGenericNotifyFromISR>
  8373. HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen);
  8374. 8003ea8: 88a2 ldrh r2, [r4, #4]
  8375. 8003eaa: 6821 ldr r1, [r4, #0]
  8376. 8003eac: 6b20 ldr r0, [r4, #48] @ 0x30
  8377. 8003eae: f007 fe35 bl 800bb1c <HAL_UARTEx_ReceiveToIdle_IT>
  8378. portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken);
  8379. 8003eb2: 9b03 ldr r3, [sp, #12]
  8380. 8003eb4: b14b cbz r3, 8003eca <HandleUartRxCallback+0x62>
  8381. 8003eb6: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  8382. 8003eba: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  8383. 8003ebe: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  8384. 8003ec2: f3bf 8f4f dsb sy
  8385. 8003ec6: f3bf 8f6f isb sy
  8386. }
  8387. 8003eca: b004 add sp, #16
  8388. 8003ecc: bd70 pop {r4, r5, r6, pc}
  8389. 8003ece: bf00 nop
  8390. 08003ed0 <HAL_UARTEx_RxEventCallback>:
  8391. if (huart->Instance == USART1) {
  8392. 8003ed0: 4a08 ldr r2, [pc, #32] @ (8003ef4 <HAL_UARTEx_RxEventCallback+0x24>)
  8393. 8003ed2: 6803 ldr r3, [r0, #0]
  8394. 8003ed4: 4293 cmp r3, r2
  8395. 8003ed6: d003 beq.n 8003ee0 <HAL_UARTEx_RxEventCallback+0x10>
  8396. } else if (huart->Instance == UART8) {
  8397. 8003ed8: 4a07 ldr r2, [pc, #28] @ (8003ef8 <HAL_UARTEx_RxEventCallback+0x28>)
  8398. 8003eda: 4293 cmp r3, r2
  8399. 8003edc: d005 beq.n 8003eea <HAL_UARTEx_RxEventCallback+0x1a>
  8400. }
  8401. 8003ede: 4770 bx lr
  8402. HandleUartRxCallback (&uart1TaskData, huart, Size);
  8403. 8003ee0: 460a mov r2, r1
  8404. 8003ee2: 4601 mov r1, r0
  8405. 8003ee4: 4805 ldr r0, [pc, #20] @ (8003efc <HAL_UARTEx_RxEventCallback+0x2c>)
  8406. 8003ee6: f7ff bfbf b.w 8003e68 <HandleUartRxCallback>
  8407. HandleUartRxCallback (&uart8TaskData, huart, Size);
  8408. 8003eea: 460a mov r2, r1
  8409. 8003eec: 4601 mov r1, r0
  8410. 8003eee: 4804 ldr r0, [pc, #16] @ (8003f00 <HAL_UARTEx_RxEventCallback+0x30>)
  8411. 8003ef0: f7ff bfba b.w 8003e68 <HandleUartRxCallback>
  8412. 8003ef4: 40011000 .word 0x40011000
  8413. 8003ef8: 40007c00 .word 0x40007c00
  8414. 8003efc: 24000b74 .word 0x24000b74
  8415. 8003f00: 24000b3c .word 0x24000b3c
  8416. 08003f04 <Reset_Handler>:
  8417. .section .text.Reset_Handler
  8418. .weak Reset_Handler
  8419. .type Reset_Handler, %function
  8420. Reset_Handler:
  8421. ldr sp, =_estack /* set stack pointer */
  8422. 8003f04: f8df d034 ldr.w sp, [pc, #52] @ 8003f3c <LoopFillZerobss+0xe>
  8423. /* Call the clock system initialization function.*/
  8424. bl SystemInit
  8425. 8003f08: f7ff f91c bl 8003144 <SystemInit>
  8426. /* Copy the data segment initializers from flash to SRAM */
  8427. ldr r0, =_sdata
  8428. 8003f0c: 480c ldr r0, [pc, #48] @ (8003f40 <LoopFillZerobss+0x12>)
  8429. ldr r1, =_edata
  8430. 8003f0e: 490d ldr r1, [pc, #52] @ (8003f44 <LoopFillZerobss+0x16>)
  8431. ldr r2, =_sidata
  8432. 8003f10: 4a0d ldr r2, [pc, #52] @ (8003f48 <LoopFillZerobss+0x1a>)
  8433. movs r3, #0
  8434. 8003f12: 2300 movs r3, #0
  8435. b LoopCopyDataInit
  8436. 8003f14: e002 b.n 8003f1c <LoopCopyDataInit>
  8437. 08003f16 <CopyDataInit>:
  8438. CopyDataInit:
  8439. ldr r4, [r2, r3]
  8440. 8003f16: 58d4 ldr r4, [r2, r3]
  8441. str r4, [r0, r3]
  8442. 8003f18: 50c4 str r4, [r0, r3]
  8443. adds r3, r3, #4
  8444. 8003f1a: 3304 adds r3, #4
  8445. 08003f1c <LoopCopyDataInit>:
  8446. LoopCopyDataInit:
  8447. adds r4, r0, r3
  8448. 8003f1c: 18c4 adds r4, r0, r3
  8449. cmp r4, r1
  8450. 8003f1e: 428c cmp r4, r1
  8451. bcc CopyDataInit
  8452. 8003f20: d3f9 bcc.n 8003f16 <CopyDataInit>
  8453. /* Zero fill the bss segment. */
  8454. ldr r2, =_sbss
  8455. 8003f22: 4a0a ldr r2, [pc, #40] @ (8003f4c <LoopFillZerobss+0x1e>)
  8456. ldr r4, =_ebss
  8457. 8003f24: 4c0a ldr r4, [pc, #40] @ (8003f50 <LoopFillZerobss+0x22>)
  8458. movs r3, #0
  8459. 8003f26: 2300 movs r3, #0
  8460. b LoopFillZerobss
  8461. 8003f28: e001 b.n 8003f2e <LoopFillZerobss>
  8462. 08003f2a <FillZerobss>:
  8463. FillZerobss:
  8464. str r3, [r2]
  8465. 8003f2a: 6013 str r3, [r2, #0]
  8466. adds r2, r2, #4
  8467. 8003f2c: 3204 adds r2, #4
  8468. 08003f2e <LoopFillZerobss>:
  8469. LoopFillZerobss:
  8470. cmp r2, r4
  8471. 8003f2e: 42a2 cmp r2, r4
  8472. bcc FillZerobss
  8473. 8003f30: d3fb bcc.n 8003f2a <FillZerobss>
  8474. /* Call static constructors */
  8475. bl __libc_init_array
  8476. 8003f32: f00b fe97 bl 800fc64 <__libc_init_array>
  8477. /* Call the application's entry point.*/
  8478. bl main
  8479. 8003f36: f7fc fcf3 bl 8000920 <main>
  8480. bx lr
  8481. 8003f3a: 4770 bx lr
  8482. ldr sp, =_estack /* set stack pointer */
  8483. 8003f3c: 24060000 .word 0x24060000
  8484. ldr r0, =_sdata
  8485. 8003f40: 24000000 .word 0x24000000
  8486. ldr r1, =_edata
  8487. 8003f44: 24000210 .word 0x24000210
  8488. ldr r2, =_sidata
  8489. 8003f48: 08011df8 .word 0x08011df8
  8490. ldr r2, =_sbss
  8491. 8003f4c: 24000220 .word 0x24000220
  8492. ldr r4, =_ebss
  8493. 8003f50: 240132e4 .word 0x240132e4
  8494. 08003f54 <ADC3_IRQHandler>:
  8495. * @retval None
  8496. */
  8497. .section .text.Default_Handler,"ax",%progbits
  8498. Default_Handler:
  8499. Infinite_Loop:
  8500. b Infinite_Loop
  8501. 8003f54: e7fe b.n 8003f54 <ADC3_IRQHandler>
  8502. ...
  8503. 08003f58 <HAL_Init>:
  8504. * need to ensure that the SysTick time base is always set to 1 millisecond
  8505. * to have correct HAL operation.
  8506. * @retval HAL status
  8507. */
  8508. HAL_StatusTypeDef HAL_Init(void)
  8509. {
  8510. 8003f58: b510 push {r4, lr}
  8511. __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
  8512. __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */
  8513. #endif /* DUAL_CORE && CORE_CM4 */
  8514. /* Set Interrupt Group Priority */
  8515. HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
  8516. 8003f5a: 2003 movs r0, #3
  8517. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
  8518. #endif
  8519. /* Update the SystemD2Clock global variable */
  8520. #if defined(RCC_D1CFGR_HPRE)
  8521. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  8522. 8003f5c: 4c12 ldr r4, [pc, #72] @ (8003fa8 <HAL_Init+0x50>)
  8523. HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
  8524. 8003f5e: f000 ffd9 bl 8004f14 <HAL_NVIC_SetPriorityGrouping>
  8525. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
  8526. 8003f62: f003 fda5 bl 8007ab0 <HAL_RCC_GetSysClockFreq>
  8527. 8003f66: 4b11 ldr r3, [pc, #68] @ (8003fac <HAL_Init+0x54>)
  8528. 8003f68: 4911 ldr r1, [pc, #68] @ (8003fb0 <HAL_Init+0x58>)
  8529. 8003f6a: 699a ldr r2, [r3, #24]
  8530. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  8531. 8003f6c: 699b ldr r3, [r3, #24]
  8532. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
  8533. 8003f6e: f3c2 2203 ubfx r2, r2, #8, #4
  8534. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  8535. 8003f72: f003 030f and.w r3, r3, #15
  8536. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
  8537. 8003f76: 5c8a ldrb r2, [r1, r2]
  8538. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  8539. 8003f78: 5ccb ldrb r3, [r1, r3]
  8540. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
  8541. 8003f7a: f002 021f and.w r2, r2, #31
  8542. #endif
  8543. #if defined(DUAL_CORE) && defined(CORE_CM4)
  8544. SystemCoreClock = SystemD2Clock;
  8545. #else
  8546. SystemCoreClock = common_system_clock;
  8547. 8003f7e: 490d ldr r1, [pc, #52] @ (8003fb4 <HAL_Init+0x5c>)
  8548. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  8549. 8003f80: f003 031f and.w r3, r3, #31
  8550. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
  8551. 8003f84: 40d0 lsrs r0, r2
  8552. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  8553. 8003f86: fa20 f303 lsr.w r3, r0, r3
  8554. SystemCoreClock = common_system_clock;
  8555. 8003f8a: 6008 str r0, [r1, #0]
  8556. #endif /* DUAL_CORE && CORE_CM4 */
  8557. /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  8558. if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
  8559. 8003f8c: 2005 movs r0, #5
  8560. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  8561. 8003f8e: 6023 str r3, [r4, #0]
  8562. if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
  8563. 8003f90: f7fe ffd4 bl 8002f3c <HAL_InitTick>
  8564. 8003f94: b110 cbz r0, 8003f9c <HAL_Init+0x44>
  8565. {
  8566. return HAL_ERROR;
  8567. 8003f96: 2401 movs r4, #1
  8568. /* Init the low level hardware */
  8569. HAL_MspInit();
  8570. /* Return function status */
  8571. return HAL_OK;
  8572. }
  8573. 8003f98: 4620 mov r0, r4
  8574. 8003f9a: bd10 pop {r4, pc}
  8575. 8003f9c: 4604 mov r4, r0
  8576. HAL_MspInit();
  8577. 8003f9e: f7fe fc31 bl 8002804 <HAL_MspInit>
  8578. }
  8579. 8003fa2: 4620 mov r0, r4
  8580. 8003fa4: bd10 pop {r4, pc}
  8581. 8003fa6: bf00 nop
  8582. 8003fa8: 24000034 .word 0x24000034
  8583. 8003fac: 58024400 .word 0x58024400
  8584. 8003fb0: 08011a14 .word 0x08011a14
  8585. 8003fb4: 24000038 .word 0x24000038
  8586. 08003fb8 <HAL_IncTick>:
  8587. * implementations in user file.
  8588. * @retval None
  8589. */
  8590. __weak void HAL_IncTick(void)
  8591. {
  8592. uwTick += (uint32_t)uwTickFreq;
  8593. 8003fb8: 4a03 ldr r2, [pc, #12] @ (8003fc8 <HAL_IncTick+0x10>)
  8594. 8003fba: 4b04 ldr r3, [pc, #16] @ (8003fcc <HAL_IncTick+0x14>)
  8595. 8003fbc: 6811 ldr r1, [r2, #0]
  8596. 8003fbe: 781b ldrb r3, [r3, #0]
  8597. 8003fc0: 440b add r3, r1
  8598. 8003fc2: 6013 str r3, [r2, #0]
  8599. }
  8600. 8003fc4: 4770 bx lr
  8601. 8003fc6: bf00 nop
  8602. 8003fc8: 240011ac .word 0x240011ac
  8603. 8003fcc: 2400003c .word 0x2400003c
  8604. 08003fd0 <HAL_GetTick>:
  8605. * implementations in user file.
  8606. * @retval tick value
  8607. */
  8608. __weak uint32_t HAL_GetTick(void)
  8609. {
  8610. return uwTick;
  8611. 8003fd0: 4b01 ldr r3, [pc, #4] @ (8003fd8 <HAL_GetTick+0x8>)
  8612. 8003fd2: 6818 ldr r0, [r3, #0]
  8613. }
  8614. 8003fd4: 4770 bx lr
  8615. 8003fd6: bf00 nop
  8616. 8003fd8: 240011ac .word 0x240011ac
  8617. 08003fdc <HAL_GetREVID>:
  8618. * @brief Returns the device revision identifier.
  8619. * @retval Device revision identifier
  8620. */
  8621. uint32_t HAL_GetREVID(void)
  8622. {
  8623. return((DBGMCU->IDCODE) >> 16);
  8624. 8003fdc: 4b01 ldr r3, [pc, #4] @ (8003fe4 <HAL_GetREVID+0x8>)
  8625. 8003fde: 6818 ldr r0, [r3, #0]
  8626. }
  8627. 8003fe0: 0c00 lsrs r0, r0, #16
  8628. 8003fe2: 4770 bx lr
  8629. 8003fe4: 5c001000 .word 0x5c001000
  8630. 08003fe8 <HAL_SYSCFG_VREFBUF_HighImpedanceConfig>:
  8631. void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
  8632. {
  8633. /* Check the parameters */
  8634. assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
  8635. MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
  8636. 8003fe8: 4a03 ldr r2, [pc, #12] @ (8003ff8 <HAL_SYSCFG_VREFBUF_HighImpedanceConfig+0x10>)
  8637. 8003fea: 6813 ldr r3, [r2, #0]
  8638. 8003fec: f023 0302 bic.w r3, r3, #2
  8639. 8003ff0: 4303 orrs r3, r0
  8640. 8003ff2: 6013 str r3, [r2, #0]
  8641. }
  8642. 8003ff4: 4770 bx lr
  8643. 8003ff6: bf00 nop
  8644. 8003ff8: 58003c00 .word 0x58003c00
  8645. 08003ffc <HAL_SYSCFG_DisableVREFBUF>:
  8646. *
  8647. * @retval None
  8648. */
  8649. void HAL_SYSCFG_DisableVREFBUF(void)
  8650. {
  8651. CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
  8652. 8003ffc: 4a02 ldr r2, [pc, #8] @ (8004008 <HAL_SYSCFG_DisableVREFBUF+0xc>)
  8653. 8003ffe: 6813 ldr r3, [r2, #0]
  8654. 8004000: f023 0301 bic.w r3, r3, #1
  8655. 8004004: 6013 str r3, [r2, #0]
  8656. }
  8657. 8004006: 4770 bx lr
  8658. 8004008: 58003c00 .word 0x58003c00
  8659. 0800400c <HAL_SYSCFG_AnalogSwitchConfig>:
  8660. {
  8661. /* Check the parameter */
  8662. assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
  8663. assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
  8664. MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
  8665. 800400c: 4a03 ldr r2, [pc, #12] @ (800401c <HAL_SYSCFG_AnalogSwitchConfig+0x10>)
  8666. 800400e: 6853 ldr r3, [r2, #4]
  8667. 8004010: ea23 0300 bic.w r3, r3, r0
  8668. 8004014: 430b orrs r3, r1
  8669. 8004016: 6053 str r3, [r2, #4]
  8670. }
  8671. 8004018: 4770 bx lr
  8672. 800401a: bf00 nop
  8673. 800401c: 58000400 .word 0x58000400
  8674. 08004020 <HAL_ADC_ConvHalfCpltCallback>:
  8675. /**
  8676. * @brief Conversion DMA half-transfer callback in non-blocking mode.
  8677. * @param hadc ADC handle
  8678. * @retval None
  8679. */
  8680. __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
  8681. 8004020: 4770 bx lr
  8682. 8004022: bf00 nop
  8683. 08004024 <ADC_DMAHalfConvCplt>:
  8684. /* Half conversion callback */
  8685. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  8686. hadc->ConvHalfCpltCallback(hadc);
  8687. #else
  8688. HAL_ADC_ConvHalfCpltCallback(hadc);
  8689. 8004024: 6b80 ldr r0, [r0, #56] @ 0x38
  8690. {
  8691. 8004026: b508 push {r3, lr}
  8692. HAL_ADC_ConvHalfCpltCallback(hadc);
  8693. 8004028: f7ff fffa bl 8004020 <HAL_ADC_ConvHalfCpltCallback>
  8694. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  8695. }
  8696. 800402c: bd08 pop {r3, pc}
  8697. 800402e: bf00 nop
  8698. 08004030 <HAL_ADC_ErrorCallback>:
  8699. __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
  8700. 8004030: 4770 bx lr
  8701. 8004032: bf00 nop
  8702. 08004034 <ADC_DMAConvCplt>:
  8703. ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  8704. 8004034: 6b83 ldr r3, [r0, #56] @ 0x38
  8705. if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
  8706. 8004036: 6d5a ldr r2, [r3, #84] @ 0x54
  8707. 8004038: f012 0f50 tst.w r2, #80 @ 0x50
  8708. SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
  8709. 800403c: 6d5a ldr r2, [r3, #84] @ 0x54
  8710. {
  8711. 800403e: b510 push {r4, lr}
  8712. if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
  8713. 8004040: d11d bne.n 800407e <ADC_DMAConvCplt+0x4a>
  8714. if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
  8715. 8004042: 6819 ldr r1, [r3, #0]
  8716. SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
  8717. 8004044: f442 7200 orr.w r2, r2, #512 @ 0x200
  8718. 8004048: 655a str r2, [r3, #84] @ 0x54
  8719. if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
  8720. 800404a: 680a ldr r2, [r1, #0]
  8721. 800404c: f012 0f08 tst.w r2, #8
  8722. * @retval Value "0" if trigger source external trigger
  8723. * Value "1" if trigger source SW start.
  8724. */
  8725. __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
  8726. {
  8727. return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
  8728. 8004050: 68ca ldr r2, [r1, #12]
  8729. 8004052: d01b beq.n 800408c <ADC_DMAConvCplt+0x58>
  8730. 8004054: f412 6f40 tst.w r2, #3072 @ 0xc00
  8731. 8004058: d10d bne.n 8004076 <ADC_DMAConvCplt+0x42>
  8732. if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
  8733. 800405a: 68ca ldr r2, [r1, #12]
  8734. 800405c: 0494 lsls r4, r2, #18
  8735. 800405e: d40a bmi.n 8004076 <ADC_DMAConvCplt+0x42>
  8736. CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
  8737. 8004060: 6d5a ldr r2, [r3, #84] @ 0x54
  8738. 8004062: f422 7280 bic.w r2, r2, #256 @ 0x100
  8739. 8004066: 655a str r2, [r3, #84] @ 0x54
  8740. if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
  8741. 8004068: 6d5a ldr r2, [r3, #84] @ 0x54
  8742. 800406a: 04d1 lsls r1, r2, #19
  8743. 800406c: d403 bmi.n 8004076 <ADC_DMAConvCplt+0x42>
  8744. SET_BIT(hadc->State, HAL_ADC_STATE_READY);
  8745. 800406e: 6d5a ldr r2, [r3, #84] @ 0x54
  8746. 8004070: f042 0201 orr.w r2, r2, #1
  8747. 8004074: 655a str r2, [r3, #84] @ 0x54
  8748. HAL_ADC_ConvCpltCallback(hadc);
  8749. 8004076: 4618 mov r0, r3
  8750. 8004078: f7fd f964 bl 8001344 <HAL_ADC_ConvCpltCallback>
  8751. }
  8752. 800407c: bd10 pop {r4, pc}
  8753. if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
  8754. 800407e: 06d2 lsls r2, r2, #27
  8755. 8004080: d40a bmi.n 8004098 <ADC_DMAConvCplt+0x64>
  8756. hadc->DMA_Handle->XferErrorCallback(hdma);
  8757. 8004082: 6cdb ldr r3, [r3, #76] @ 0x4c
  8758. }
  8759. 8004084: e8bd 4010 ldmia.w sp!, {r4, lr}
  8760. hadc->DMA_Handle->XferErrorCallback(hdma);
  8761. 8004088: 6cdb ldr r3, [r3, #76] @ 0x4c
  8762. 800408a: 4718 bx r3
  8763. if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL)
  8764. 800408c: 0790 lsls r0, r2, #30
  8765. 800408e: d0e7 beq.n 8004060 <ADC_DMAConvCplt+0x2c>
  8766. HAL_ADC_ConvCpltCallback(hadc);
  8767. 8004090: 4618 mov r0, r3
  8768. 8004092: f7fd f957 bl 8001344 <HAL_ADC_ConvCpltCallback>
  8769. 8004096: e7f1 b.n 800407c <ADC_DMAConvCplt+0x48>
  8770. HAL_ADC_ErrorCallback(hadc);
  8771. 8004098: 4618 mov r0, r3
  8772. 800409a: f7ff ffc9 bl 8004030 <HAL_ADC_ErrorCallback>
  8773. }
  8774. 800409e: bd10 pop {r4, pc}
  8775. 080040a0 <ADC_DMAError>:
  8776. * @retval None
  8777. */
  8778. void ADC_DMAError(DMA_HandleTypeDef *hdma)
  8779. {
  8780. /* Retrieve ADC handle corresponding to current DMA handle */
  8781. ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  8782. 80040a0: 6b80 ldr r0, [r0, #56] @ 0x38
  8783. {
  8784. 80040a2: b508 push {r3, lr}
  8785. /* Set ADC state */
  8786. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
  8787. 80040a4: 6d43 ldr r3, [r0, #84] @ 0x54
  8788. 80040a6: f043 0340 orr.w r3, r3, #64 @ 0x40
  8789. 80040aa: 6543 str r3, [r0, #84] @ 0x54
  8790. /* Set ADC error code to DMA error */
  8791. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
  8792. 80040ac: 6d83 ldr r3, [r0, #88] @ 0x58
  8793. 80040ae: f043 0304 orr.w r3, r3, #4
  8794. 80040b2: 6583 str r3, [r0, #88] @ 0x58
  8795. /* Error callback */
  8796. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  8797. hadc->ErrorCallback(hadc);
  8798. #else
  8799. HAL_ADC_ErrorCallback(hadc);
  8800. 80040b4: f7ff ffbc bl 8004030 <HAL_ADC_ErrorCallback>
  8801. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  8802. }
  8803. 80040b8: bd08 pop {r3, pc}
  8804. 80040ba: bf00 nop
  8805. 080040bc <HAL_ADC_ConfigChannel>:
  8806. {
  8807. 80040bc: b5f0 push {r4, r5, r6, r7, lr}
  8808. __IO uint32_t wait_loop_index = 0;
  8809. 80040be: 2200 movs r2, #0
  8810. {
  8811. 80040c0: b083 sub sp, #12
  8812. __IO uint32_t wait_loop_index = 0;
  8813. 80040c2: 9201 str r2, [sp, #4]
  8814. __HAL_LOCK(hadc);
  8815. 80040c4: f890 2050 ldrb.w r2, [r0, #80] @ 0x50
  8816. 80040c8: 2a01 cmp r2, #1
  8817. 80040ca: f000 8138 beq.w 800433e <HAL_ADC_ConfigChannel+0x282>
  8818. 80040ce: 2401 movs r4, #1
  8819. if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
  8820. 80040d0: 6802 ldr r2, [r0, #0]
  8821. 80040d2: 4603 mov r3, r0
  8822. __HAL_LOCK(hadc);
  8823. 80040d4: f880 4050 strb.w r4, [r0, #80] @ 0x50
  8824. * @param ADCx ADC instance
  8825. * @retval 0: no conversion is on going on ADC group regular.
  8826. */
  8827. __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
  8828. {
  8829. return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
  8830. 80040d8: 6890 ldr r0, [r2, #8]
  8831. 80040da: 0745 lsls r5, r0, #29
  8832. 80040dc: d509 bpl.n 80040f2 <HAL_ADC_ConfigChannel+0x36>
  8833. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  8834. 80040de: 6d5a ldr r2, [r3, #84] @ 0x54
  8835. tmp_hal_status = HAL_ERROR;
  8836. 80040e0: 2001 movs r0, #1
  8837. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  8838. 80040e2: f042 0220 orr.w r2, r2, #32
  8839. 80040e6: 655a str r2, [r3, #84] @ 0x54
  8840. __HAL_UNLOCK(hadc);
  8841. 80040e8: 2200 movs r2, #0
  8842. 80040ea: f883 2050 strb.w r2, [r3, #80] @ 0x50
  8843. }
  8844. 80040ee: b003 add sp, #12
  8845. 80040f0: bdf0 pop {r4, r5, r6, r7, pc}
  8846. if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)))
  8847. 80040f2: 680d ldr r5, [r1, #0]
  8848. 80040f4: 2d00 cmp r5, #0
  8849. hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
  8850. 80040f6: ea4f 6095 mov.w r0, r5, lsr #26
  8851. if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)))
  8852. 80040fa: db0d blt.n 8004118 <HAL_ADC_ConfigChannel+0x5c>
  8853. hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
  8854. 80040fc: f3c5 0613 ubfx r6, r5, #0, #20
  8855. 8004100: 2e00 cmp r6, #0
  8856. 8004102: f000 809a beq.w 800423a <HAL_ADC_ConfigChannel+0x17e>
  8857. uint32_t result;
  8858. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  8859. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  8860. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  8861. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  8862. 8004106: fa95 f5a5 rbit r5, r5
  8863. optimisations using the logic "value was passed to __builtin_clz, so it
  8864. is non-zero".
  8865. ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
  8866. single CLZ instruction.
  8867. */
  8868. if (value == 0U)
  8869. 800410a: b115 cbz r5, 8004112 <HAL_ADC_ConfigChannel+0x56>
  8870. {
  8871. return 32U;
  8872. }
  8873. return __builtin_clz(value);
  8874. 800410c: fab5 f585 clz r5, r5
  8875. 8004110: 40ac lsls r4, r5
  8876. 8004112: 69d5 ldr r5, [r2, #28]
  8877. 8004114: 432c orrs r4, r5
  8878. 8004116: 61d4 str r4, [r2, #28]
  8879. LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
  8880. 8004118: 684c ldr r4, [r1, #4]
  8881. MODIFY_REG(*preg,
  8882. 800411a: f04f 0c1f mov.w ip, #31
  8883. __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
  8884. 800411e: f102 0e30 add.w lr, r2, #48 @ 0x30
  8885. MODIFY_REG(*preg,
  8886. 8004122: f000 001f and.w r0, r0, #31
  8887. __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
  8888. 8004126: 09a5 lsrs r5, r4, #6
  8889. MODIFY_REG(*preg,
  8890. 8004128: ea04 040c and.w r4, r4, ip
  8891. __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
  8892. 800412c: f005 050c and.w r5, r5, #12
  8893. MODIFY_REG(*preg,
  8894. 8004130: fa0c fc04 lsl.w ip, ip, r4
  8895. 8004134: 40a0 lsls r0, r4
  8896. 8004136: f85e 4005 ldr.w r4, [lr, r5]
  8897. 800413a: ea24 0c0c bic.w ip, r4, ip
  8898. 800413e: ea4c 0000 orr.w r0, ip, r0
  8899. 8004142: f84e 0005 str.w r0, [lr, r5]
  8900. return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
  8901. 8004146: 6890 ldr r0, [r2, #8]
  8902. 8004148: f010 0f04 tst.w r0, #4
  8903. * @param ADCx ADC instance
  8904. * @retval 0: no conversion is on going on ADC group injected.
  8905. */
  8906. __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
  8907. {
  8908. return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
  8909. 800414c: 6890 ldr r0, [r2, #8]
  8910. return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
  8911. 800414e: d101 bne.n 8004154 <HAL_ADC_ConfigChannel+0x98>
  8912. return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
  8913. 8004150: 0700 lsls r0, r0, #28
  8914. 8004152: d51a bpl.n 800418a <HAL_ADC_ConfigChannel+0xce>
  8915. return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
  8916. 8004154: 6890 ldr r0, [r2, #8]
  8917. 8004156: 07c7 lsls r7, r0, #31
  8918. 8004158: d415 bmi.n 8004186 <HAL_ADC_ConfigChannel+0xca>
  8919. LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
  8920. 800415a: 68ce ldr r6, [r1, #12]
  8921. 800415c: 680c ldr r4, [r1, #0]
  8922. MODIFY_REG(ADCx->DIFSEL,
  8923. 800415e: f006 0718 and.w r7, r6, #24
  8924. 8004162: 48bd ldr r0, [pc, #756] @ (8004458 <HAL_ADC_ConfigChannel+0x39c>)
  8925. 8004164: f8d2 50c0 ldr.w r5, [r2, #192] @ 0xc0
  8926. 8004168: 40f8 lsrs r0, r7
  8927. 800416a: f3c4 0713 ubfx r7, r4, #0, #20
  8928. 800416e: 4020 ands r0, r4
  8929. 8004170: ea25 0507 bic.w r5, r5, r7
  8930. 8004174: 4328 orrs r0, r5
  8931. 8004176: f8c2 00c0 str.w r0, [r2, #192] @ 0xc0
  8932. if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
  8933. 800417a: 48b8 ldr r0, [pc, #736] @ (800445c <HAL_ADC_ConfigChannel+0x3a0>)
  8934. 800417c: 4286 cmp r6, r0
  8935. 800417e: f000 8091 beq.w 80042a4 <HAL_ADC_ConfigChannel+0x1e8>
  8936. if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
  8937. 8004182: 2c00 cmp r4, #0
  8938. 8004184: db5b blt.n 800423e <HAL_ADC_ConfigChannel+0x182>
  8939. HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  8940. 8004186: 2000 movs r0, #0
  8941. 8004188: e7ae b.n 80040e8 <HAL_ADC_ConfigChannel+0x2c>
  8942. LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
  8943. 800418a: 680c ldr r4, [r1, #0]
  8944. __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
  8945. 800418c: f102 0c14 add.w ip, r2, #20
  8946. MODIFY_REG(*preg,
  8947. 8004190: f04f 0e07 mov.w lr, #7
  8948. 8004194: 688e ldr r6, [r1, #8]
  8949. __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
  8950. 8004196: 0de5 lsrs r5, r4, #23
  8951. MODIFY_REG(*preg,
  8952. 8004198: f3c4 5404 ubfx r4, r4, #20, #5
  8953. __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
  8954. 800419c: f005 0504 and.w r5, r5, #4
  8955. MODIFY_REG(*preg,
  8956. 80041a0: fa0e fe04 lsl.w lr, lr, r4
  8957. 80041a4: fa06 f404 lsl.w r4, r6, r4
  8958. 80041a8: f85c 0005 ldr.w r0, [ip, r5]
  8959. 80041ac: ea20 000e bic.w r0, r0, lr
  8960. 80041b0: 4320 orrs r0, r4
  8961. 80041b2: f84c 0005 str.w r0, [ip, r5]
  8962. tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
  8963. 80041b6: 48aa ldr r0, [pc, #680] @ (8004460 <HAL_ADC_ConfigChannel+0x3a4>)
  8964. 80041b8: 694d ldr r5, [r1, #20]
  8965. 80041ba: 6800 ldr r0, [r0, #0]
  8966. 80041bc: f000 4070 and.w r0, r0, #4026531840 @ 0xf0000000
  8967. 80041c0: f1b0 5f80 cmp.w r0, #268435456 @ 0x10000000
  8968. 80041c4: 68d0 ldr r0, [r2, #12]
  8969. 80041c6: d068 beq.n 800429a <HAL_ADC_ConfigChannel+0x1de>
  8970. 80041c8: f010 0f10 tst.w r0, #16
  8971. 80041cc: 68d0 ldr r0, [r2, #12]
  8972. 80041ce: d064 beq.n 800429a <HAL_ADC_ConfigChannel+0x1de>
  8973. 80041d0: 0840 lsrs r0, r0, #1
  8974. 80041d2: f000 0008 and.w r0, r0, #8
  8975. 80041d6: 4085 lsls r5, r0
  8976. if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
  8977. 80041d8: 690e ldr r6, [r1, #16]
  8978. LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
  8979. 80041da: 6808 ldr r0, [r1, #0]
  8980. if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
  8981. 80041dc: 2e04 cmp r6, #4
  8982. 80041de: f000 80b1 beq.w 8004344 <HAL_ADC_ConfigChannel+0x288>
  8983. __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
  8984. 80041e2: f102 0c60 add.w ip, r2, #96 @ 0x60
  8985. MODIFY_REG(*preg,
  8986. 80041e6: f000 44f8 and.w r4, r0, #2080374784 @ 0x7c000000
  8987. 80041ea: f85c 0026 ldr.w r0, [ip, r6, lsl #2]
  8988. 80041ee: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
  8989. 80041f2: 4320 orrs r0, r4
  8990. 80041f4: 4328 orrs r0, r5
  8991. 80041f6: f84c 0026 str.w r0, [ip, r6, lsl #2]
  8992. LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
  8993. 80041fa: 7e4c ldrb r4, [r1, #25]
  8994. __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
  8995. 80041fc: 690d ldr r5, [r1, #16]
  8996. 80041fe: f1a4 0401 sub.w r4, r4, #1
  8997. MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
  8998. 8004202: f85c 0025 ldr.w r0, [ip, r5, lsl #2]
  8999. 8004206: fab4 f484 clz r4, r4
  9000. 800420a: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000
  9001. 800420e: 0964 lsrs r4, r4, #5
  9002. 8004210: ea40 70c4 orr.w r0, r0, r4, lsl #31
  9003. 8004214: f84c 0025 str.w r0, [ip, r5, lsl #2]
  9004. LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
  9005. 8004218: 7e08 ldrb r0, [r1, #24]
  9006. MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
  9007. 800421a: 690d ldr r5, [r1, #16]
  9008. 800421c: f1a0 0001 sub.w r0, r0, #1
  9009. 8004220: 6914 ldr r4, [r2, #16]
  9010. 8004222: f005 051f and.w r5, r5, #31
  9011. 8004226: fab0 f080 clz r0, r0
  9012. 800422a: f424 44f0 bic.w r4, r4, #30720 @ 0x7800
  9013. 800422e: 0940 lsrs r0, r0, #5
  9014. 8004230: 02c0 lsls r0, r0, #11
  9015. 8004232: 40a8 lsls r0, r5
  9016. 8004234: 4320 orrs r0, r4
  9017. 8004236: 6110 str r0, [r2, #16]
  9018. }
  9019. 8004238: e78c b.n 8004154 <HAL_ADC_ConfigChannel+0x98>
  9020. hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
  9021. 800423a: 4084 lsls r4, r0
  9022. 800423c: e769 b.n 8004112 <HAL_ADC_ConfigChannel+0x56>
  9023. tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  9024. 800423e: 4989 ldr r1, [pc, #548] @ (8004464 <HAL_ADC_ConfigChannel+0x3a8>)
  9025. 8004240: 428a cmp r2, r1
  9026. 8004242: f000 80be beq.w 80043c2 <HAL_ADC_ConfigChannel+0x306>
  9027. 8004246: f501 7180 add.w r1, r1, #256 @ 0x100
  9028. 800424a: 428a cmp r2, r1
  9029. 800424c: f000 80b9 beq.w 80043c2 <HAL_ADC_ConfigChannel+0x306>
  9030. return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
  9031. 8004250: f101 51c0 add.w r1, r1, #402653184 @ 0x18000000
  9032. return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
  9033. 8004254: 4d84 ldr r5, [pc, #528] @ (8004468 <HAL_ADC_ConfigChannel+0x3ac>)
  9034. return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
  9035. 8004256: f501 4184 add.w r1, r1, #16896 @ 0x4200
  9036. 800425a: 6888 ldr r0, [r1, #8]
  9037. return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
  9038. 800425c: 68ae ldr r6, [r5, #8]
  9039. 800425e: 07f6 lsls r6, r6, #31
  9040. 8004260: f53f af3d bmi.w 80040de <HAL_ADC_ConfigChannel+0x22>
  9041. if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
  9042. 8004264: 4e81 ldr r6, [pc, #516] @ (800446c <HAL_ADC_ConfigChannel+0x3b0>)
  9043. return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
  9044. 8004266: f000 77e0 and.w r7, r0, #29360128 @ 0x1c00000
  9045. 800426a: 42b4 cmp r4, r6
  9046. 800426c: f000 8106 beq.w 800447c <HAL_ADC_ConfigChannel+0x3c0>
  9047. else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
  9048. 8004270: 4e7f ldr r6, [pc, #508] @ (8004470 <HAL_ADC_ConfigChannel+0x3b4>)
  9049. 8004272: 42b4 cmp r4, r6
  9050. 8004274: f000 80e2 beq.w 800443c <HAL_ADC_ConfigChannel+0x380>
  9051. else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
  9052. 8004278: 4d7e ldr r5, [pc, #504] @ (8004474 <HAL_ADC_ConfigChannel+0x3b8>)
  9053. 800427a: 42ac cmp r4, r5
  9054. 800427c: d183 bne.n 8004186 <HAL_ADC_ConfigChannel+0xca>
  9055. if (ADC_VREFINT_INSTANCE(hadc))
  9056. 800427e: 0240 lsls r0, r0, #9
  9057. 8004280: d481 bmi.n 8004186 <HAL_ADC_ConfigChannel+0xca>
  9058. 8004282: 4879 ldr r0, [pc, #484] @ (8004468 <HAL_ADC_ConfigChannel+0x3ac>)
  9059. 8004284: 4282 cmp r2, r0
  9060. 8004286: f47f af7e bne.w 8004186 <HAL_ADC_ConfigChannel+0xca>
  9061. MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
  9062. 800428a: 688a ldr r2, [r1, #8]
  9063. 800428c: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000
  9064. 8004290: 433a orrs r2, r7
  9065. 8004292: f442 0280 orr.w r2, r2, #4194304 @ 0x400000
  9066. 8004296: 608a str r2, [r1, #8]
  9067. }
  9068. 8004298: e775 b.n 8004186 <HAL_ADC_ConfigChannel+0xca>
  9069. tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
  9070. 800429a: f3c0 0082 ubfx r0, r0, #2, #3
  9071. 800429e: 0040 lsls r0, r0, #1
  9072. 80042a0: 4085 lsls r5, r0
  9073. 80042a2: e799 b.n 80041d8 <HAL_ADC_ConfigChannel+0x11c>
  9074. (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
  9075. 80042a4: 2f00 cmp r7, #0
  9076. 80042a6: d069 beq.n 800437c <HAL_ADC_ConfigChannel+0x2c0>
  9077. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  9078. 80042a8: fa94 f0a4 rbit r0, r4
  9079. if (value == 0U)
  9080. 80042ac: 2800 cmp r0, #0
  9081. 80042ae: f000 80a1 beq.w 80043f4 <HAL_ADC_ConfigChannel+0x338>
  9082. return __builtin_clz(value);
  9083. 80042b2: fab0 f080 clz r0, r0
  9084. LL_ADC_SetChannelSamplingTime(hadc->Instance,
  9085. 80042b6: 3001 adds r0, #1
  9086. 80042b8: f000 001f and.w r0, r0, #31
  9087. 80042bc: 2809 cmp r0, #9
  9088. 80042be: f240 8099 bls.w 80043f4 <HAL_ADC_ConfigChannel+0x338>
  9089. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  9090. 80042c2: fa94 f0a4 rbit r0, r4
  9091. if (value == 0U)
  9092. 80042c6: 2800 cmp r0, #0
  9093. 80042c8: f000 80fe beq.w 80044c8 <HAL_ADC_ConfigChannel+0x40c>
  9094. return __builtin_clz(value);
  9095. 80042cc: fab0 f080 clz r0, r0
  9096. (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
  9097. 80042d0: 3001 adds r0, #1
  9098. 80042d2: 0680 lsls r0, r0, #26
  9099. 80042d4: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000
  9100. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  9101. 80042d8: fa94 f5a4 rbit r5, r4
  9102. if (value == 0U)
  9103. 80042dc: 2d00 cmp r5, #0
  9104. 80042de: f000 80f1 beq.w 80044c4 <HAL_ADC_ConfigChannel+0x408>
  9105. return __builtin_clz(value);
  9106. 80042e2: fab5 f585 clz r5, r5
  9107. 80042e6: 2601 movs r6, #1
  9108. 80042e8: 3501 adds r5, #1
  9109. 80042ea: f005 051f and.w r5, r5, #31
  9110. 80042ee: fa06 f505 lsl.w r5, r6, r5
  9111. 80042f2: 4328 orrs r0, r5
  9112. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  9113. 80042f4: fa94 f4a4 rbit r4, r4
  9114. if (value == 0U)
  9115. 80042f8: 2c00 cmp r4, #0
  9116. 80042fa: f000 80e1 beq.w 80044c0 <HAL_ADC_ConfigChannel+0x404>
  9117. return __builtin_clz(value);
  9118. 80042fe: fab4 f484 clz r4, r4
  9119. 8004302: f06f 061d mvn.w r6, #29
  9120. 8004306: 1c65 adds r5, r4, #1
  9121. 8004308: 2403 movs r4, #3
  9122. 800430a: f005 051f and.w r5, r5, #31
  9123. 800430e: fb14 6405 smlabb r4, r4, r5, r6
  9124. 8004312: 0524 lsls r4, r4, #20
  9125. 8004314: f044 7400 orr.w r4, r4, #33554432 @ 0x2000000
  9126. LL_ADC_SetChannelSamplingTime(hadc->Instance,
  9127. 8004318: 4320 orrs r0, r4
  9128. __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
  9129. 800431a: f102 0614 add.w r6, r2, #20
  9130. MODIFY_REG(*preg,
  9131. 800431e: 2707 movs r7, #7
  9132. __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
  9133. 8004320: 0dc5 lsrs r5, r0, #23
  9134. MODIFY_REG(*preg,
  9135. 8004322: f3c0 5004 ubfx r0, r0, #20, #5
  9136. __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
  9137. 8004326: f005 0504 and.w r5, r5, #4
  9138. MODIFY_REG(*preg,
  9139. 800432a: 4087 lsls r7, r0
  9140. 800432c: 5974 ldr r4, [r6, r5]
  9141. 800432e: ea24 0407 bic.w r4, r4, r7
  9142. 8004332: 688f ldr r7, [r1, #8]
  9143. 8004334: 4087 lsls r7, r0
  9144. 8004336: 433c orrs r4, r7
  9145. 8004338: 5174 str r4, [r6, r5]
  9146. if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
  9147. 800433a: 680c ldr r4, [r1, #0]
  9148. }
  9149. 800433c: e721 b.n 8004182 <HAL_ADC_ConfigChannel+0xc6>
  9150. __HAL_LOCK(hadc);
  9151. 800433e: 2002 movs r0, #2
  9152. }
  9153. 8004340: b003 add sp, #12
  9154. 8004342: bdf0 pop {r4, r5, r6, r7, pc}
  9155. if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
  9156. 8004344: 6e15 ldr r5, [r2, #96] @ 0x60
  9157. 8004346: 0684 lsls r4, r0, #26
  9158. 8004348: f005 45f8 and.w r5, r5, #2080374784 @ 0x7c000000
  9159. 800434c: ebb5 6f80 cmp.w r5, r0, lsl #26
  9160. 8004350: d032 beq.n 80043b8 <HAL_ADC_ConfigChannel+0x2fc>
  9161. if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
  9162. 8004352: 6e50 ldr r0, [r2, #100] @ 0x64
  9163. 8004354: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000
  9164. 8004358: 4284 cmp r4, r0
  9165. 800435a: d028 beq.n 80043ae <HAL_ADC_ConfigChannel+0x2f2>
  9166. if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
  9167. 800435c: 6e90 ldr r0, [r2, #104] @ 0x68
  9168. 800435e: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000
  9169. 8004362: 4284 cmp r4, r0
  9170. 8004364: d01e beq.n 80043a4 <HAL_ADC_ConfigChannel+0x2e8>
  9171. if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
  9172. 8004366: 6ed0 ldr r0, [r2, #108] @ 0x6c
  9173. 8004368: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000
  9174. 800436c: 4284 cmp r4, r0
  9175. 800436e: f47f aef1 bne.w 8004154 <HAL_ADC_ConfigChannel+0x98>
  9176. CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
  9177. 8004372: 6ed0 ldr r0, [r2, #108] @ 0x6c
  9178. 8004374: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000
  9179. 8004378: 66d0 str r0, [r2, #108] @ 0x6c
  9180. 800437a: e6eb b.n 8004154 <HAL_ADC_ConfigChannel+0x98>
  9181. (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
  9182. 800437c: 0ea4 lsrs r4, r4, #26
  9183. 800437e: 2001 movs r0, #1
  9184. 8004380: 3401 adds r4, #1
  9185. 8004382: f004 051f and.w r5, r4, #31
  9186. 8004386: 06a4 lsls r4, r4, #26
  9187. 8004388: 40a8 lsls r0, r5
  9188. 800438a: f004 44f8 and.w r4, r4, #2080374784 @ 0x7c000000
  9189. LL_ADC_SetChannelSamplingTime(hadc->Instance,
  9190. 800438e: 2d09 cmp r5, #9
  9191. (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
  9192. 8004390: ea40 0004 orr.w r0, r0, r4
  9193. 8004394: eb05 0445 add.w r4, r5, r5, lsl #1
  9194. LL_ADC_SetChannelSamplingTime(hadc->Instance,
  9195. 8004398: d94e bls.n 8004438 <HAL_ADC_ConfigChannel+0x37c>
  9196. (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
  9197. 800439a: 3c1e subs r4, #30
  9198. 800439c: 0524 lsls r4, r4, #20
  9199. 800439e: f044 7400 orr.w r4, r4, #33554432 @ 0x2000000
  9200. 80043a2: e7b9 b.n 8004318 <HAL_ADC_ConfigChannel+0x25c>
  9201. CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
  9202. 80043a4: 6e90 ldr r0, [r2, #104] @ 0x68
  9203. 80043a6: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000
  9204. 80043aa: 6690 str r0, [r2, #104] @ 0x68
  9205. 80043ac: e7db b.n 8004366 <HAL_ADC_ConfigChannel+0x2aa>
  9206. CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
  9207. 80043ae: 6e50 ldr r0, [r2, #100] @ 0x64
  9208. 80043b0: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000
  9209. 80043b4: 6650 str r0, [r2, #100] @ 0x64
  9210. 80043b6: e7d1 b.n 800435c <HAL_ADC_ConfigChannel+0x2a0>
  9211. CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
  9212. 80043b8: 6e10 ldr r0, [r2, #96] @ 0x60
  9213. 80043ba: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000
  9214. 80043be: 6610 str r0, [r2, #96] @ 0x60
  9215. 80043c0: e7c7 b.n 8004352 <HAL_ADC_ConfigChannel+0x296>
  9216. return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
  9217. 80043c2: 4d28 ldr r5, [pc, #160] @ (8004464 <HAL_ADC_ConfigChannel+0x3a8>)
  9218. return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
  9219. 80043c4: 492c ldr r1, [pc, #176] @ (8004478 <HAL_ADC_ConfigChannel+0x3bc>)
  9220. return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
  9221. 80043c6: f505 7580 add.w r5, r5, #256 @ 0x100
  9222. return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
  9223. 80043ca: 6888 ldr r0, [r1, #8]
  9224. return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
  9225. 80043cc: f855 6cf8 ldr.w r6, [r5, #-248]
  9226. 80043d0: 68ad ldr r5, [r5, #8]
  9227. 80043d2: 07ed lsls r5, r5, #31
  9228. 80043d4: f53f ae83 bmi.w 80040de <HAL_ADC_ConfigChannel+0x22>
  9229. if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
  9230. 80043d8: 07f7 lsls r7, r6, #31
  9231. 80043da: f53f ae80 bmi.w 80040de <HAL_ADC_ConfigChannel+0x22>
  9232. if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
  9233. 80043de: 4d23 ldr r5, [pc, #140] @ (800446c <HAL_ADC_ConfigChannel+0x3b0>)
  9234. 80043e0: 42ac cmp r4, r5
  9235. 80043e2: f43f aed0 beq.w 8004186 <HAL_ADC_ConfigChannel+0xca>
  9236. else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
  9237. 80043e6: 4d22 ldr r5, [pc, #136] @ (8004470 <HAL_ADC_ConfigChannel+0x3b4>)
  9238. 80043e8: 42ac cmp r4, r5
  9239. 80043ea: f43f aecc beq.w 8004186 <HAL_ADC_ConfigChannel+0xca>
  9240. return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
  9241. 80043ee: f000 77e0 and.w r7, r0, #29360128 @ 0x1c00000
  9242. 80043f2: e741 b.n 8004278 <HAL_ADC_ConfigChannel+0x1bc>
  9243. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  9244. 80043f4: fa94 f0a4 rbit r0, r4
  9245. if (value == 0U)
  9246. 80043f8: 2800 cmp r0, #0
  9247. 80043fa: d06d beq.n 80044d8 <HAL_ADC_ConfigChannel+0x41c>
  9248. return __builtin_clz(value);
  9249. 80043fc: fab0 f080 clz r0, r0
  9250. (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
  9251. 8004400: 3001 adds r0, #1
  9252. 8004402: 0680 lsls r0, r0, #26
  9253. 8004404: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000
  9254. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  9255. 8004408: fa94 f5a4 rbit r5, r4
  9256. if (value == 0U)
  9257. 800440c: 2d00 cmp r5, #0
  9258. 800440e: d061 beq.n 80044d4 <HAL_ADC_ConfigChannel+0x418>
  9259. return __builtin_clz(value);
  9260. 8004410: fab5 f585 clz r5, r5
  9261. 8004414: 2601 movs r6, #1
  9262. 8004416: 3501 adds r5, #1
  9263. 8004418: f005 051f and.w r5, r5, #31
  9264. 800441c: fa06 f505 lsl.w r5, r6, r5
  9265. 8004420: 4328 orrs r0, r5
  9266. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  9267. 8004422: fa94 f4a4 rbit r4, r4
  9268. if (value == 0U)
  9269. 8004426: 2c00 cmp r4, #0
  9270. 8004428: d051 beq.n 80044ce <HAL_ADC_ConfigChannel+0x412>
  9271. return __builtin_clz(value);
  9272. 800442a: fab4 f484 clz r4, r4
  9273. 800442e: 3401 adds r4, #1
  9274. 8004430: f004 041f and.w r4, r4, #31
  9275. 8004434: eb04 0444 add.w r4, r4, r4, lsl #1
  9276. 8004438: 0524 lsls r4, r4, #20
  9277. 800443a: e76d b.n 8004318 <HAL_ADC_ConfigChannel+0x25c>
  9278. if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
  9279. 800443c: 01c4 lsls r4, r0, #7
  9280. 800443e: f53f aea2 bmi.w 8004186 <HAL_ADC_ConfigChannel+0xca>
  9281. 8004442: 42aa cmp r2, r5
  9282. 8004444: f47f ae9f bne.w 8004186 <HAL_ADC_ConfigChannel+0xca>
  9283. MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
  9284. 8004448: 688a ldr r2, [r1, #8]
  9285. 800444a: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000
  9286. 800444e: 433a orrs r2, r7
  9287. 8004450: f042 7280 orr.w r2, r2, #16777216 @ 0x1000000
  9288. 8004454: 608a str r2, [r1, #8]
  9289. }
  9290. 8004456: e696 b.n 8004186 <HAL_ADC_ConfigChannel+0xca>
  9291. 8004458: 000fffff .word 0x000fffff
  9292. 800445c: 47ff0000 .word 0x47ff0000
  9293. 8004460: 5c001000 .word 0x5c001000
  9294. 8004464: 40022000 .word 0x40022000
  9295. 8004468: 58026000 .word 0x58026000
  9296. 800446c: cb840000 .word 0xcb840000
  9297. 8004470: c7520000 .word 0xc7520000
  9298. 8004474: cfb80000 .word 0xcfb80000
  9299. 8004478: 40022300 .word 0x40022300
  9300. if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
  9301. 800447c: 0206 lsls r6, r0, #8
  9302. 800447e: f53f ae82 bmi.w 8004186 <HAL_ADC_ConfigChannel+0xca>
  9303. if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
  9304. 8004482: 42aa cmp r2, r5
  9305. 8004484: f47f ae7f bne.w 8004186 <HAL_ADC_ConfigChannel+0xca>
  9306. MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
  9307. 8004488: 688a ldr r2, [r1, #8]
  9308. wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
  9309. 800448a: 4815 ldr r0, [pc, #84] @ (80044e0 <HAL_ADC_ConfigChannel+0x424>)
  9310. 800448c: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000
  9311. 8004490: 433a orrs r2, r7
  9312. 8004492: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
  9313. 8004496: 608a str r2, [r1, #8]
  9314. 8004498: 6802 ldr r2, [r0, #0]
  9315. 800449a: 4912 ldr r1, [pc, #72] @ (80044e4 <HAL_ADC_ConfigChannel+0x428>)
  9316. 800449c: 0992 lsrs r2, r2, #6
  9317. 800449e: fba1 1202 umull r1, r2, r1, r2
  9318. 80044a2: 0992 lsrs r2, r2, #6
  9319. 80044a4: 3201 adds r2, #1
  9320. 80044a6: 0052 lsls r2, r2, #1
  9321. 80044a8: 9201 str r2, [sp, #4]
  9322. while (wait_loop_index != 0UL)
  9323. 80044aa: 9a01 ldr r2, [sp, #4]
  9324. 80044ac: 2a00 cmp r2, #0
  9325. 80044ae: f43f ae6a beq.w 8004186 <HAL_ADC_ConfigChannel+0xca>
  9326. wait_loop_index--;
  9327. 80044b2: 9a01 ldr r2, [sp, #4]
  9328. 80044b4: 3a01 subs r2, #1
  9329. 80044b6: 9201 str r2, [sp, #4]
  9330. while (wait_loop_index != 0UL)
  9331. 80044b8: 9a01 ldr r2, [sp, #4]
  9332. 80044ba: 2a00 cmp r2, #0
  9333. 80044bc: d1f9 bne.n 80044b2 <HAL_ADC_ConfigChannel+0x3f6>
  9334. 80044be: e662 b.n 8004186 <HAL_ADC_ConfigChannel+0xca>
  9335. 80044c0: 4c09 ldr r4, [pc, #36] @ (80044e8 <HAL_ADC_ConfigChannel+0x42c>)
  9336. 80044c2: e729 b.n 8004318 <HAL_ADC_ConfigChannel+0x25c>
  9337. 80044c4: 2502 movs r5, #2
  9338. 80044c6: e714 b.n 80042f2 <HAL_ADC_ConfigChannel+0x236>
  9339. 80044c8: f04f 6080 mov.w r0, #67108864 @ 0x4000000
  9340. 80044cc: e704 b.n 80042d8 <HAL_ADC_ConfigChannel+0x21c>
  9341. 80044ce: f44f 1440 mov.w r4, #3145728 @ 0x300000
  9342. 80044d2: e721 b.n 8004318 <HAL_ADC_ConfigChannel+0x25c>
  9343. 80044d4: 2502 movs r5, #2
  9344. 80044d6: e7a3 b.n 8004420 <HAL_ADC_ConfigChannel+0x364>
  9345. 80044d8: f04f 6080 mov.w r0, #67108864 @ 0x4000000
  9346. 80044dc: e794 b.n 8004408 <HAL_ADC_ConfigChannel+0x34c>
  9347. 80044de: bf00 nop
  9348. 80044e0: 24000038 .word 0x24000038
  9349. 80044e4: 053e2d63 .word 0x053e2d63
  9350. 80044e8: fe500000 .word 0xfe500000
  9351. 080044ec <ADC_Enable>:
  9352. if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
  9353. 80044ec: 6803 ldr r3, [r0, #0]
  9354. return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
  9355. 80044ee: 689a ldr r2, [r3, #8]
  9356. 80044f0: 07d1 lsls r1, r2, #31
  9357. 80044f2: d501 bpl.n 80044f8 <ADC_Enable+0xc>
  9358. return HAL_OK;
  9359. 80044f4: 2000 movs r0, #0
  9360. }
  9361. 80044f6: 4770 bx lr
  9362. if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
  9363. 80044f8: 6899 ldr r1, [r3, #8]
  9364. 80044fa: 4a23 ldr r2, [pc, #140] @ (8004588 <ADC_Enable+0x9c>)
  9365. 80044fc: 4211 tst r1, r2
  9366. {
  9367. 80044fe: b570 push {r4, r5, r6, lr}
  9368. 8004500: 4604 mov r4, r0
  9369. if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
  9370. 8004502: d12f bne.n 8004564 <ADC_Enable+0x78>
  9371. MODIFY_REG(ADCx->CR,
  9372. 8004504: 6899 ldr r1, [r3, #8]
  9373. 8004506: 4a21 ldr r2, [pc, #132] @ (800458c <ADC_Enable+0xa0>)
  9374. 8004508: 400a ands r2, r1
  9375. 800450a: f042 0201 orr.w r2, r2, #1
  9376. 800450e: 609a str r2, [r3, #8]
  9377. tickstart = HAL_GetTick();
  9378. 8004510: f7ff fd5e bl 8003fd0 <HAL_GetTick>
  9379. uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  9380. 8004514: 6823 ldr r3, [r4, #0]
  9381. 8004516: 4a1e ldr r2, [pc, #120] @ (8004590 <ADC_Enable+0xa4>)
  9382. tickstart = HAL_GetTick();
  9383. 8004518: 4605 mov r5, r0
  9384. uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  9385. 800451a: 4293 cmp r3, r2
  9386. 800451c: d02c beq.n 8004578 <ADC_Enable+0x8c>
  9387. 800451e: f502 7280 add.w r2, r2, #256 @ 0x100
  9388. 8004522: 4293 cmp r3, r2
  9389. 8004524: d028 beq.n 8004578 <ADC_Enable+0x8c>
  9390. return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
  9391. 8004526: f102 52c0 add.w r2, r2, #402653184 @ 0x18000000
  9392. 800452a: f502 4284 add.w r2, r2, #16896 @ 0x4200
  9393. 800452e: 6892 ldr r2, [r2, #8]
  9394. while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
  9395. 8004530: 681a ldr r2, [r3, #0]
  9396. 8004532: 07d2 lsls r2, r2, #31
  9397. 8004534: d414 bmi.n 8004560 <ADC_Enable+0x74>
  9398. MODIFY_REG(ADCx->CR,
  9399. 8004536: 4e15 ldr r6, [pc, #84] @ (800458c <ADC_Enable+0xa0>)
  9400. return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
  9401. 8004538: 689a ldr r2, [r3, #8]
  9402. 800453a: 07d0 lsls r0, r2, #31
  9403. 800453c: d404 bmi.n 8004548 <ADC_Enable+0x5c>
  9404. MODIFY_REG(ADCx->CR,
  9405. 800453e: 689a ldr r2, [r3, #8]
  9406. 8004540: 4032 ands r2, r6
  9407. 8004542: f042 0201 orr.w r2, r2, #1
  9408. 8004546: 609a str r2, [r3, #8]
  9409. if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
  9410. 8004548: f7ff fd42 bl 8003fd0 <HAL_GetTick>
  9411. 800454c: 1b43 subs r3, r0, r5
  9412. 800454e: 2b02 cmp r3, #2
  9413. if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
  9414. 8004550: 6823 ldr r3, [r4, #0]
  9415. if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
  9416. 8004552: d902 bls.n 800455a <ADC_Enable+0x6e>
  9417. if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
  9418. 8004554: 681a ldr r2, [r3, #0]
  9419. 8004556: 07d1 lsls r1, r2, #31
  9420. 8004558: d504 bpl.n 8004564 <ADC_Enable+0x78>
  9421. while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
  9422. 800455a: 681a ldr r2, [r3, #0]
  9423. 800455c: 07d2 lsls r2, r2, #31
  9424. 800455e: d5eb bpl.n 8004538 <ADC_Enable+0x4c>
  9425. return HAL_OK;
  9426. 8004560: 2000 movs r0, #0
  9427. }
  9428. 8004562: bd70 pop {r4, r5, r6, pc}
  9429. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  9430. 8004564: 6d63 ldr r3, [r4, #84] @ 0x54
  9431. return HAL_ERROR;
  9432. 8004566: 2001 movs r0, #1
  9433. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  9434. 8004568: f043 0310 orr.w r3, r3, #16
  9435. 800456c: 6563 str r3, [r4, #84] @ 0x54
  9436. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  9437. 800456e: 6da3 ldr r3, [r4, #88] @ 0x58
  9438. 8004570: f043 0301 orr.w r3, r3, #1
  9439. 8004574: 65a3 str r3, [r4, #88] @ 0x58
  9440. }
  9441. 8004576: bd70 pop {r4, r5, r6, pc}
  9442. return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
  9443. 8004578: 4a06 ldr r2, [pc, #24] @ (8004594 <ADC_Enable+0xa8>)
  9444. 800457a: 6892 ldr r2, [r2, #8]
  9445. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  9446. 800457c: 06d6 lsls r6, r2, #27
  9447. 800457e: d0d7 beq.n 8004530 <ADC_Enable+0x44>
  9448. if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
  9449. 8004580: 4a05 ldr r2, [pc, #20] @ (8004598 <ADC_Enable+0xac>)
  9450. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  9451. 8004582: 4293 cmp r3, r2
  9452. 8004584: d1d4 bne.n 8004530 <ADC_Enable+0x44>
  9453. 8004586: e7eb b.n 8004560 <ADC_Enable+0x74>
  9454. 8004588: 8000003f .word 0x8000003f
  9455. 800458c: 7fffffc0 .word 0x7fffffc0
  9456. 8004590: 40022000 .word 0x40022000
  9457. 8004594: 40022300 .word 0x40022300
  9458. 8004598: 40022100 .word 0x40022100
  9459. 0800459c <HAL_ADC_Start_DMA>:
  9460. {
  9461. 800459c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  9462. uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  9463. 80045a0: 4b3c ldr r3, [pc, #240] @ (8004694 <HAL_ADC_Start_DMA+0xf8>)
  9464. {
  9465. 80045a2: 4604 mov r4, r0
  9466. uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  9467. 80045a4: 6800 ldr r0, [r0, #0]
  9468. {
  9469. 80045a6: 460e mov r6, r1
  9470. 80045a8: 4617 mov r7, r2
  9471. uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  9472. 80045aa: 4298 cmp r0, r3
  9473. 80045ac: d05f beq.n 800466e <HAL_ADC_Start_DMA+0xd2>
  9474. 80045ae: f503 7380 add.w r3, r3, #256 @ 0x100
  9475. 80045b2: 4298 cmp r0, r3
  9476. 80045b4: d05b beq.n 800466e <HAL_ADC_Start_DMA+0xd2>
  9477. 80045b6: 4b38 ldr r3, [pc, #224] @ (8004698 <HAL_ADC_Start_DMA+0xfc>)
  9478. 80045b8: 689b ldr r3, [r3, #8]
  9479. return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
  9480. 80045ba: 6885 ldr r5, [r0, #8]
  9481. 80045bc: f015 0504 ands.w r5, r5, #4
  9482. 80045c0: d15b bne.n 800467a <HAL_ADC_Start_DMA+0xde>
  9483. __HAL_LOCK(hadc);
  9484. 80045c2: f894 2050 ldrb.w r2, [r4, #80] @ 0x50
  9485. 80045c6: 2a01 cmp r2, #1
  9486. 80045c8: d057 beq.n 800467a <HAL_ADC_Start_DMA+0xde>
  9487. return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
  9488. 80045ca: f003 081f and.w r8, r3, #31
  9489. if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  9490. 80045ce: f240 2321 movw r3, #545 @ 0x221
  9491. __HAL_LOCK(hadc);
  9492. 80045d2: 2001 movs r0, #1
  9493. if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  9494. 80045d4: fa23 f308 lsr.w r3, r3, r8
  9495. __HAL_LOCK(hadc);
  9496. 80045d8: f884 0050 strb.w r0, [r4, #80] @ 0x50
  9497. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
  9498. 80045dc: 4003 ands r3, r0
  9499. 80045de: d053 beq.n 8004688 <HAL_ADC_Start_DMA+0xec>
  9500. tmp_hal_status = ADC_Enable(hadc);
  9501. 80045e0: 4620 mov r0, r4
  9502. 80045e2: f7ff ff83 bl 80044ec <ADC_Enable>
  9503. if (tmp_hal_status == HAL_OK)
  9504. 80045e6: 2800 cmp r0, #0
  9505. 80045e8: d14a bne.n 8004680 <HAL_ADC_Start_DMA+0xe4>
  9506. ADC_STATE_CLR_SET(hadc->State,
  9507. 80045ea: 6d62 ldr r2, [r4, #84] @ 0x54
  9508. 80045ec: 4b2b ldr r3, [pc, #172] @ (800469c <HAL_ADC_Start_DMA+0x100>)
  9509. if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
  9510. 80045ee: 6821 ldr r1, [r4, #0]
  9511. ADC_STATE_CLR_SET(hadc->State,
  9512. 80045f0: 4013 ands r3, r2
  9513. 80045f2: f443 7380 orr.w r3, r3, #256 @ 0x100
  9514. 80045f6: 6563 str r3, [r4, #84] @ 0x54
  9515. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  9516. 80045f8: f1b8 0f00 cmp.w r8, #0
  9517. 80045fc: d002 beq.n 8004604 <HAL_ADC_Start_DMA+0x68>
  9518. if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
  9519. 80045fe: 4b28 ldr r3, [pc, #160] @ (80046a0 <HAL_ADC_Start_DMA+0x104>)
  9520. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  9521. 8004600: 4299 cmp r1, r3
  9522. 8004602: d003 beq.n 800460c <HAL_ADC_Start_DMA+0x70>
  9523. CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  9524. 8004604: 6d63 ldr r3, [r4, #84] @ 0x54
  9525. 8004606: f423 1380 bic.w r3, r3, #1048576 @ 0x100000
  9526. 800460a: 6563 str r3, [r4, #84] @ 0x54
  9527. if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
  9528. 800460c: 6d63 ldr r3, [r4, #84] @ 0x54
  9529. 800460e: f413 5380 ands.w r3, r3, #4096 @ 0x1000
  9530. 8004612: d03d beq.n 8004690 <HAL_ADC_Start_DMA+0xf4>
  9531. CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
  9532. 8004614: 6da3 ldr r3, [r4, #88] @ 0x58
  9533. 8004616: f023 0306 bic.w r3, r3, #6
  9534. 800461a: 65a3 str r3, [r4, #88] @ 0x58
  9535. hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
  9536. 800461c: 6ce0 ldr r0, [r4, #76] @ 0x4c
  9537. tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
  9538. 800461e: 4632 mov r2, r6
  9539. hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
  9540. 8004620: 4d20 ldr r5, [pc, #128] @ (80046a4 <HAL_ADC_Start_DMA+0x108>)
  9541. tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
  9542. 8004622: 463b mov r3, r7
  9543. MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);
  9544. 8004624: 6ae6 ldr r6, [r4, #44] @ 0x2c
  9545. 8004626: 3140 adds r1, #64 @ 0x40
  9546. hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
  9547. 8004628: 63c5 str r5, [r0, #60] @ 0x3c
  9548. hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
  9549. 800462a: 4d1f ldr r5, [pc, #124] @ (80046a8 <HAL_ADC_Start_DMA+0x10c>)
  9550. 800462c: 6405 str r5, [r0, #64] @ 0x40
  9551. hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
  9552. 800462e: 4d1f ldr r5, [pc, #124] @ (80046ac <HAL_ADC_Start_DMA+0x110>)
  9553. 8004630: 64c5 str r5, [r0, #76] @ 0x4c
  9554. __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
  9555. 8004632: 251c movs r5, #28
  9556. 8004634: f841 5c40 str.w r5, [r1, #-64]
  9557. __HAL_UNLOCK(hadc);
  9558. 8004638: 2500 movs r5, #0
  9559. 800463a: f884 5050 strb.w r5, [r4, #80] @ 0x50
  9560. __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
  9561. 800463e: f851 5c3c ldr.w r5, [r1, #-60]
  9562. 8004642: f045 0510 orr.w r5, r5, #16
  9563. 8004646: f841 5c3c str.w r5, [r1, #-60]
  9564. 800464a: f851 5c34 ldr.w r5, [r1, #-52]
  9565. 800464e: f025 0503 bic.w r5, r5, #3
  9566. 8004652: 4335 orrs r5, r6
  9567. 8004654: f841 5c34 str.w r5, [r1, #-52]
  9568. tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
  9569. 8004658: f001 fab0 bl 8005bbc <HAL_DMA_Start_IT>
  9570. LL_ADC_REG_StartConversion(hadc->Instance);
  9571. 800465c: 6822 ldr r2, [r4, #0]
  9572. MODIFY_REG(ADCx->CR,
  9573. 800465e: 4b14 ldr r3, [pc, #80] @ (80046b0 <HAL_ADC_Start_DMA+0x114>)
  9574. 8004660: 6891 ldr r1, [r2, #8]
  9575. 8004662: 400b ands r3, r1
  9576. 8004664: f043 0304 orr.w r3, r3, #4
  9577. 8004668: 6093 str r3, [r2, #8]
  9578. }
  9579. 800466a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  9580. uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  9581. 800466e: 4b11 ldr r3, [pc, #68] @ (80046b4 <HAL_ADC_Start_DMA+0x118>)
  9582. return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
  9583. 8004670: 689b ldr r3, [r3, #8]
  9584. return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
  9585. 8004672: 6885 ldr r5, [r0, #8]
  9586. 8004674: f015 0504 ands.w r5, r5, #4
  9587. 8004678: d0a3 beq.n 80045c2 <HAL_ADC_Start_DMA+0x26>
  9588. __HAL_LOCK(hadc);
  9589. 800467a: 2002 movs r0, #2
  9590. }
  9591. 800467c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  9592. __HAL_UNLOCK(hadc);
  9593. 8004680: f884 5050 strb.w r5, [r4, #80] @ 0x50
  9594. }
  9595. 8004684: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  9596. __HAL_UNLOCK(hadc);
  9597. 8004688: f884 3050 strb.w r3, [r4, #80] @ 0x50
  9598. }
  9599. 800468c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  9600. ADC_CLEAR_ERRORCODE(hadc);
  9601. 8004690: 65a3 str r3, [r4, #88] @ 0x58
  9602. 8004692: e7c3 b.n 800461c <HAL_ADC_Start_DMA+0x80>
  9603. 8004694: 40022000 .word 0x40022000
  9604. 8004698: 58026300 .word 0x58026300
  9605. 800469c: fffff0fe .word 0xfffff0fe
  9606. 80046a0: 40022100 .word 0x40022100
  9607. 80046a4: 08004035 .word 0x08004035
  9608. 80046a8: 08004025 .word 0x08004025
  9609. 80046ac: 080040a1 .word 0x080040a1
  9610. 80046b0: 7fffffc0 .word 0x7fffffc0
  9611. 80046b4: 40022300 .word 0x40022300
  9612. 080046b8 <ADC_Disable>:
  9613. {
  9614. 80046b8: b538 push {r3, r4, r5, lr}
  9615. const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
  9616. 80046ba: 6803 ldr r3, [r0, #0]
  9617. return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
  9618. 80046bc: 689a ldr r2, [r3, #8]
  9619. 80046be: 0795 lsls r5, r2, #30
  9620. 80046c0: d502 bpl.n 80046c8 <ADC_Disable+0x10>
  9621. return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
  9622. 80046c2: 689b ldr r3, [r3, #8]
  9623. return HAL_OK;
  9624. 80046c4: 2000 movs r0, #0
  9625. }
  9626. 80046c6: bd38 pop {r3, r4, r5, pc}
  9627. 80046c8: 689a ldr r2, [r3, #8]
  9628. 80046ca: 07d4 lsls r4, r2, #31
  9629. 80046cc: d5fa bpl.n 80046c4 <ADC_Disable+0xc>
  9630. if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
  9631. 80046ce: 689a ldr r2, [r3, #8]
  9632. 80046d0: 4604 mov r4, r0
  9633. 80046d2: f002 020d and.w r2, r2, #13
  9634. 80046d6: 2a01 cmp r2, #1
  9635. 80046d8: d009 beq.n 80046ee <ADC_Disable+0x36>
  9636. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  9637. 80046da: 6d63 ldr r3, [r4, #84] @ 0x54
  9638. return HAL_ERROR;
  9639. 80046dc: 2001 movs r0, #1
  9640. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  9641. 80046de: f043 0310 orr.w r3, r3, #16
  9642. 80046e2: 6563 str r3, [r4, #84] @ 0x54
  9643. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  9644. 80046e4: 6da3 ldr r3, [r4, #88] @ 0x58
  9645. 80046e6: f043 0301 orr.w r3, r3, #1
  9646. 80046ea: 65a3 str r3, [r4, #88] @ 0x58
  9647. }
  9648. 80046ec: bd38 pop {r3, r4, r5, pc}
  9649. MODIFY_REG(ADCx->CR,
  9650. 80046ee: 6898 ldr r0, [r3, #8]
  9651. __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
  9652. 80046f0: 2103 movs r1, #3
  9653. 80046f2: 4a0d ldr r2, [pc, #52] @ (8004728 <ADC_Disable+0x70>)
  9654. 80046f4: 4002 ands r2, r0
  9655. 80046f6: f042 0202 orr.w r2, r2, #2
  9656. 80046fa: 609a str r2, [r3, #8]
  9657. 80046fc: 6019 str r1, [r3, #0]
  9658. tickstart = HAL_GetTick();
  9659. 80046fe: f7ff fc67 bl 8003fd0 <HAL_GetTick>
  9660. while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
  9661. 8004702: 6823 ldr r3, [r4, #0]
  9662. tickstart = HAL_GetTick();
  9663. 8004704: 4605 mov r5, r0
  9664. while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
  9665. 8004706: 689b ldr r3, [r3, #8]
  9666. 8004708: 07d9 lsls r1, r3, #31
  9667. 800470a: d403 bmi.n 8004714 <ADC_Disable+0x5c>
  9668. 800470c: e7da b.n 80046c4 <ADC_Disable+0xc>
  9669. 800470e: 689b ldr r3, [r3, #8]
  9670. 8004710: 07db lsls r3, r3, #31
  9671. 8004712: d5d7 bpl.n 80046c4 <ADC_Disable+0xc>
  9672. if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
  9673. 8004714: f7ff fc5c bl 8003fd0 <HAL_GetTick>
  9674. 8004718: 1b40 subs r0, r0, r5
  9675. if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
  9676. 800471a: 6823 ldr r3, [r4, #0]
  9677. if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
  9678. 800471c: 2802 cmp r0, #2
  9679. 800471e: d9f6 bls.n 800470e <ADC_Disable+0x56>
  9680. if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
  9681. 8004720: 689a ldr r2, [r3, #8]
  9682. 8004722: 07d2 lsls r2, r2, #31
  9683. 8004724: d5f3 bpl.n 800470e <ADC_Disable+0x56>
  9684. 8004726: e7d8 b.n 80046da <ADC_Disable+0x22>
  9685. 8004728: 7fffffc0 .word 0x7fffffc0
  9686. 0800472c <ADC_ConfigureBoostMode>:
  9687. * stopped.
  9688. * @param hadc ADC handle
  9689. * @retval None.
  9690. */
  9691. void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc)
  9692. {
  9693. 800472c: b538 push {r3, r4, r5, lr}
  9694. uint32_t freq;
  9695. if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
  9696. 800472e: 4a56 ldr r2, [pc, #344] @ (8004888 <ADC_ConfigureBoostMode+0x15c>)
  9697. {
  9698. 8004730: 4604 mov r4, r0
  9699. if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
  9700. 8004732: 6803 ldr r3, [r0, #0]
  9701. 8004734: 4293 cmp r3, r2
  9702. 8004736: d025 beq.n 8004784 <ADC_ConfigureBoostMode+0x58>
  9703. 8004738: f502 7280 add.w r2, r2, #256 @ 0x100
  9704. 800473c: 4293 cmp r3, r2
  9705. 800473e: d021 beq.n 8004784 <ADC_ConfigureBoostMode+0x58>
  9706. 8004740: 4b52 ldr r3, [pc, #328] @ (800488c <ADC_ConfigureBoostMode+0x160>)
  9707. 8004742: 689b ldr r3, [r3, #8]
  9708. 8004744: f413 3f40 tst.w r3, #196608 @ 0x30000
  9709. 8004748: d021 beq.n 800478e <ADC_ConfigureBoostMode+0x62>
  9710. {
  9711. freq = HAL_RCC_GetHCLKFreq();
  9712. 800474a: f003 fb69 bl 8007e20 <HAL_RCC_GetHCLKFreq>
  9713. switch (hadc->Init.ClockPrescaler)
  9714. 800474e: 6863 ldr r3, [r4, #4]
  9715. freq = HAL_RCC_GetHCLKFreq();
  9716. 8004750: 4605 mov r5, r0
  9717. switch (hadc->Init.ClockPrescaler)
  9718. 8004752: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
  9719. 8004756: f000 8086 beq.w 8004866 <ADC_ConfigureBoostMode+0x13a>
  9720. 800475a: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
  9721. 800475e: d06f beq.n 8004840 <ADC_ConfigureBoostMode+0x114>
  9722. 8004760: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
  9723. 8004764: d07f beq.n 8004866 <ADC_ConfigureBoostMode+0x13a>
  9724. else /* if(freq > 25000000UL) */
  9725. {
  9726. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
  9727. }
  9728. #else
  9729. if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
  9730. 8004766: f7ff fc39 bl 8003fdc <HAL_GetREVID>
  9731. 800476a: f241 0303 movw r3, #4099 @ 0x1003
  9732. 800476e: 4298 cmp r0, r3
  9733. 8004770: d84b bhi.n 800480a <ADC_ConfigureBoostMode+0xde>
  9734. {
  9735. if (freq > 20000000UL)
  9736. 8004772: 4a47 ldr r2, [pc, #284] @ (8004890 <ADC_ConfigureBoostMode+0x164>)
  9737. {
  9738. SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
  9739. 8004774: 6823 ldr r3, [r4, #0]
  9740. if (freq > 20000000UL)
  9741. 8004776: 4295 cmp r5, r2
  9742. 8004778: d92a bls.n 80047d0 <ADC_ConfigureBoostMode+0xa4>
  9743. SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
  9744. 800477a: 689a ldr r2, [r3, #8]
  9745. 800477c: f442 7280 orr.w r2, r2, #256 @ 0x100
  9746. 8004780: 609a str r2, [r3, #8]
  9747. {
  9748. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
  9749. }
  9750. }
  9751. #endif /* ADC_VER_V5_3 */
  9752. }
  9753. 8004782: bd38 pop {r3, r4, r5, pc}
  9754. if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
  9755. 8004784: 4b43 ldr r3, [pc, #268] @ (8004894 <ADC_ConfigureBoostMode+0x168>)
  9756. 8004786: 689b ldr r3, [r3, #8]
  9757. 8004788: f413 3f40 tst.w r3, #196608 @ 0x30000
  9758. 800478c: d1dd bne.n 800474a <ADC_ConfigureBoostMode+0x1e>
  9759. freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
  9760. 800478e: f44f 2000 mov.w r0, #524288 @ 0x80000
  9761. 8004792: 2100 movs r1, #0
  9762. 8004794: f004 fe52 bl 800943c <HAL_RCCEx_GetPeriphCLKFreq>
  9763. switch (hadc->Init.ClockPrescaler)
  9764. 8004798: 6863 ldr r3, [r4, #4]
  9765. freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
  9766. 800479a: 4605 mov r5, r0
  9767. switch (hadc->Init.ClockPrescaler)
  9768. 800479c: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000
  9769. 80047a0: d06b beq.n 800487a <ADC_ConfigureBoostMode+0x14e>
  9770. 80047a2: d808 bhi.n 80047b6 <ADC_ConfigureBoostMode+0x8a>
  9771. 80047a4: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000
  9772. 80047a8: d054 beq.n 8004854 <ADC_ConfigureBoostMode+0x128>
  9773. 80047aa: d916 bls.n 80047da <ADC_ConfigureBoostMode+0xae>
  9774. 80047ac: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
  9775. 80047b0: d1d9 bne.n 8004766 <ADC_ConfigureBoostMode+0x3a>
  9776. freq /= 32UL;
  9777. 80047b2: 0945 lsrs r5, r0, #5
  9778. break;
  9779. 80047b4: e7d7 b.n 8004766 <ADC_ConfigureBoostMode+0x3a>
  9780. switch (hadc->Init.ClockPrescaler)
  9781. 80047b6: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000
  9782. 80047ba: d049 beq.n 8004850 <ADC_ConfigureBoostMode+0x124>
  9783. 80047bc: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000
  9784. 80047c0: d1d1 bne.n 8004766 <ADC_ConfigureBoostMode+0x3a>
  9785. if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
  9786. 80047c2: f7ff fc0b bl 8003fdc <HAL_GetREVID>
  9787. 80047c6: f241 0303 movw r3, #4099 @ 0x1003
  9788. 80047ca: 4298 cmp r0, r3
  9789. 80047cc: d82e bhi.n 800482c <ADC_ConfigureBoostMode+0x100>
  9790. 80047ce: 6823 ldr r3, [r4, #0]
  9791. CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
  9792. 80047d0: 689a ldr r2, [r3, #8]
  9793. 80047d2: f422 7280 bic.w r2, r2, #256 @ 0x100
  9794. 80047d6: 609a str r2, [r3, #8]
  9795. }
  9796. 80047d8: bd38 pop {r3, r4, r5, pc}
  9797. switch (hadc->Init.ClockPrescaler)
  9798. 80047da: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
  9799. 80047de: d006 beq.n 80047ee <ADC_ConfigureBoostMode+0xc2>
  9800. 80047e0: d90a bls.n 80047f8 <ADC_ConfigureBoostMode+0xcc>
  9801. 80047e2: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000
  9802. 80047e6: d002 beq.n 80047ee <ADC_ConfigureBoostMode+0xc2>
  9803. 80047e8: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000
  9804. 80047ec: d1bb bne.n 8004766 <ADC_ConfigureBoostMode+0x3a>
  9805. freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL);
  9806. 80047ee: 0c9b lsrs r3, r3, #18
  9807. 80047f0: 005b lsls r3, r3, #1
  9808. 80047f2: fbb5 f5f3 udiv r5, r5, r3
  9809. break;
  9810. 80047f6: e7b6 b.n 8004766 <ADC_ConfigureBoostMode+0x3a>
  9811. switch (hadc->Init.ClockPrescaler)
  9812. 80047f8: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
  9813. 80047fc: d0f7 beq.n 80047ee <ADC_ConfigureBoostMode+0xc2>
  9814. 80047fe: f423 2200 bic.w r2, r3, #524288 @ 0x80000
  9815. 8004802: f5b2 2f80 cmp.w r2, #262144 @ 0x40000
  9816. 8004806: d0f2 beq.n 80047ee <ADC_ConfigureBoostMode+0xc2>
  9817. 8004808: e7ad b.n 8004766 <ADC_ConfigureBoostMode+0x3a>
  9818. if (freq <= 6250000UL)
  9819. 800480a: 4a23 ldr r2, [pc, #140] @ (8004898 <ADC_ConfigureBoostMode+0x16c>)
  9820. SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
  9821. 800480c: 6823 ldr r3, [r4, #0]
  9822. if (freq <= 6250000UL)
  9823. 800480e: 4295 cmp r5, r2
  9824. 8004810: d911 bls.n 8004836 <ADC_ConfigureBoostMode+0x10a>
  9825. else if (freq <= 12500000UL)
  9826. 8004812: 4a22 ldr r2, [pc, #136] @ (800489c <ADC_ConfigureBoostMode+0x170>)
  9827. 8004814: 4295 cmp r5, r2
  9828. 8004816: d91f bls.n 8004858 <ADC_ConfigureBoostMode+0x12c>
  9829. else if (freq <= 25000000UL)
  9830. 8004818: 4a21 ldr r2, [pc, #132] @ (80048a0 <ADC_ConfigureBoostMode+0x174>)
  9831. 800481a: 4295 cmp r5, r2
  9832. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
  9833. 800481c: 689a ldr r2, [r3, #8]
  9834. else if (freq <= 25000000UL)
  9835. 800481e: d82e bhi.n 800487e <ADC_ConfigureBoostMode+0x152>
  9836. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
  9837. 8004820: f422 7240 bic.w r2, r2, #768 @ 0x300
  9838. 8004824: f442 7200 orr.w r2, r2, #512 @ 0x200
  9839. 8004828: 609a str r2, [r3, #8]
  9840. }
  9841. 800482a: bd38 pop {r3, r4, r5, pc}
  9842. if (freq <= 6250000UL)
  9843. 800482c: 4b1a ldr r3, [pc, #104] @ (8004898 <ADC_ConfigureBoostMode+0x16c>)
  9844. 800482e: ebb3 2f15 cmp.w r3, r5, lsr #8
  9845. 8004832: 6823 ldr r3, [r4, #0]
  9846. 8004834: d310 bcc.n 8004858 <ADC_ConfigureBoostMode+0x12c>
  9847. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
  9848. 8004836: 689a ldr r2, [r3, #8]
  9849. 8004838: f422 7240 bic.w r2, r2, #768 @ 0x300
  9850. 800483c: 609a str r2, [r3, #8]
  9851. }
  9852. 800483e: bd38 pop {r3, r4, r5, pc}
  9853. freq /= 4UL;
  9854. 8004840: 0885 lsrs r5, r0, #2
  9855. if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
  9856. 8004842: f7ff fbcb bl 8003fdc <HAL_GetREVID>
  9857. 8004846: f241 0303 movw r3, #4099 @ 0x1003
  9858. 800484a: 4298 cmp r0, r3
  9859. 800484c: d8dd bhi.n 800480a <ADC_ConfigureBoostMode+0xde>
  9860. 800484e: e790 b.n 8004772 <ADC_ConfigureBoostMode+0x46>
  9861. freq /= 128UL;
  9862. 8004850: 09c5 lsrs r5, r0, #7
  9863. break;
  9864. 8004852: e788 b.n 8004766 <ADC_ConfigureBoostMode+0x3a>
  9865. freq /= 16UL;
  9866. 8004854: 0905 lsrs r5, r0, #4
  9867. break;
  9868. 8004856: e786 b.n 8004766 <ADC_ConfigureBoostMode+0x3a>
  9869. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
  9870. 8004858: 689a ldr r2, [r3, #8]
  9871. 800485a: f422 7240 bic.w r2, r2, #768 @ 0x300
  9872. 800485e: f442 7280 orr.w r2, r2, #256 @ 0x100
  9873. 8004862: 609a str r2, [r3, #8]
  9874. }
  9875. 8004864: bd38 pop {r3, r4, r5, pc}
  9876. freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos);
  9877. 8004866: 0c1b lsrs r3, r3, #16
  9878. 8004868: fbb5 f5f3 udiv r5, r5, r3
  9879. if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
  9880. 800486c: f7ff fbb6 bl 8003fdc <HAL_GetREVID>
  9881. 8004870: f241 0303 movw r3, #4099 @ 0x1003
  9882. 8004874: 4298 cmp r0, r3
  9883. 8004876: d8c8 bhi.n 800480a <ADC_ConfigureBoostMode+0xde>
  9884. 8004878: e77b b.n 8004772 <ADC_ConfigureBoostMode+0x46>
  9885. freq /= 64UL;
  9886. 800487a: 0985 lsrs r5, r0, #6
  9887. break;
  9888. 800487c: e773 b.n 8004766 <ADC_ConfigureBoostMode+0x3a>
  9889. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
  9890. 800487e: f442 7240 orr.w r2, r2, #768 @ 0x300
  9891. 8004882: 609a str r2, [r3, #8]
  9892. }
  9893. 8004884: bd38 pop {r3, r4, r5, pc}
  9894. 8004886: bf00 nop
  9895. 8004888: 40022000 .word 0x40022000
  9896. 800488c: 58026300 .word 0x58026300
  9897. 8004890: 01312d00 .word 0x01312d00
  9898. 8004894: 40022300 .word 0x40022300
  9899. 8004898: 00bebc21 .word 0x00bebc21
  9900. 800489c: 017d7841 .word 0x017d7841
  9901. 80048a0: 02faf081 .word 0x02faf081
  9902. 080048a4 <HAL_ADC_Init>:
  9903. {
  9904. 80048a4: b570 push {r4, r5, r6, lr}
  9905. __IO uint32_t wait_loop_index = 0UL;
  9906. 80048a6: 2300 movs r3, #0
  9907. {
  9908. 80048a8: b082 sub sp, #8
  9909. __IO uint32_t wait_loop_index = 0UL;
  9910. 80048aa: 9301 str r3, [sp, #4]
  9911. if (hadc == NULL)
  9912. 80048ac: 2800 cmp r0, #0
  9913. 80048ae: f000 80a9 beq.w 8004a04 <HAL_ADC_Init+0x160>
  9914. if (hadc->State == HAL_ADC_STATE_RESET)
  9915. 80048b2: 6d45 ldr r5, [r0, #84] @ 0x54
  9916. 80048b4: 4604 mov r4, r0
  9917. 80048b6: 2d00 cmp r5, #0
  9918. 80048b8: f000 80aa beq.w 8004a10 <HAL_ADC_Init+0x16c>
  9919. if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
  9920. 80048bc: 6822 ldr r2, [r4, #0]
  9921. return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
  9922. 80048be: 6893 ldr r3, [r2, #8]
  9923. 80048c0: 009e lsls r6, r3, #2
  9924. 80048c2: d503 bpl.n 80048cc <HAL_ADC_Init+0x28>
  9925. CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
  9926. 80048c4: 6891 ldr r1, [r2, #8]
  9927. 80048c6: 4b71 ldr r3, [pc, #452] @ (8004a8c <HAL_ADC_Init+0x1e8>)
  9928. 80048c8: 400b ands r3, r1
  9929. 80048ca: 6093 str r3, [r2, #8]
  9930. return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
  9931. 80048cc: 6893 ldr r3, [r2, #8]
  9932. 80048ce: 00dd lsls r5, r3, #3
  9933. 80048d0: d416 bmi.n 8004900 <HAL_ADC_Init+0x5c>
  9934. wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
  9935. 80048d2: 4b6f ldr r3, [pc, #444] @ (8004a90 <HAL_ADC_Init+0x1ec>)
  9936. 80048d4: 496f ldr r1, [pc, #444] @ (8004a94 <HAL_ADC_Init+0x1f0>)
  9937. 80048d6: 681b ldr r3, [r3, #0]
  9938. MODIFY_REG(ADCx->CR,
  9939. 80048d8: 6890 ldr r0, [r2, #8]
  9940. 80048da: 099b lsrs r3, r3, #6
  9941. 80048dc: fba1 1303 umull r1, r3, r1, r3
  9942. 80048e0: 496d ldr r1, [pc, #436] @ (8004a98 <HAL_ADC_Init+0x1f4>)
  9943. 80048e2: 099b lsrs r3, r3, #6
  9944. 80048e4: 4001 ands r1, r0
  9945. 80048e6: 3301 adds r3, #1
  9946. 80048e8: f041 5180 orr.w r1, r1, #268435456 @ 0x10000000
  9947. 80048ec: 6091 str r1, [r2, #8]
  9948. 80048ee: 9301 str r3, [sp, #4]
  9949. while (wait_loop_index != 0UL)
  9950. 80048f0: 9b01 ldr r3, [sp, #4]
  9951. 80048f2: b12b cbz r3, 8004900 <HAL_ADC_Init+0x5c>
  9952. wait_loop_index--;
  9953. 80048f4: 9b01 ldr r3, [sp, #4]
  9954. 80048f6: 3b01 subs r3, #1
  9955. 80048f8: 9301 str r3, [sp, #4]
  9956. while (wait_loop_index != 0UL)
  9957. 80048fa: 9b01 ldr r3, [sp, #4]
  9958. 80048fc: 2b00 cmp r3, #0
  9959. 80048fe: d1f9 bne.n 80048f4 <HAL_ADC_Init+0x50>
  9960. return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
  9961. 8004900: 6893 ldr r3, [r2, #8]
  9962. 8004902: 00d8 lsls r0, r3, #3
  9963. 8004904: f100 8082 bmi.w 8004a0c <HAL_ADC_Init+0x168>
  9964. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  9965. 8004908: 6d63 ldr r3, [r4, #84] @ 0x54
  9966. tmp_hal_status = HAL_ERROR;
  9967. 800490a: 2501 movs r5, #1
  9968. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  9969. 800490c: f043 0310 orr.w r3, r3, #16
  9970. 8004910: 6563 str r3, [r4, #84] @ 0x54
  9971. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  9972. 8004912: 6da3 ldr r3, [r4, #88] @ 0x58
  9973. 8004914: 432b orrs r3, r5
  9974. 8004916: 65a3 str r3, [r4, #88] @ 0x58
  9975. return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
  9976. 8004918: 6893 ldr r3, [r2, #8]
  9977. 800491a: f013 0f04 tst.w r3, #4
  9978. if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
  9979. 800491e: 6d63 ldr r3, [r4, #84] @ 0x54
  9980. 8004920: d16c bne.n 80049fc <HAL_ADC_Init+0x158>
  9981. 8004922: 06d9 lsls r1, r3, #27
  9982. 8004924: d46a bmi.n 80049fc <HAL_ADC_Init+0x158>
  9983. ADC_STATE_CLR_SET(hadc->State,
  9984. 8004926: 6d63 ldr r3, [r4, #84] @ 0x54
  9985. 8004928: f423 7381 bic.w r3, r3, #258 @ 0x102
  9986. 800492c: f043 0302 orr.w r3, r3, #2
  9987. 8004930: 6563 str r3, [r4, #84] @ 0x54
  9988. return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
  9989. 8004932: 6893 ldr r3, [r2, #8]
  9990. 8004934: 07db lsls r3, r3, #31
  9991. 8004936: d40c bmi.n 8004952 <HAL_ADC_Init+0xae>
  9992. if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
  9993. 8004938: 4b58 ldr r3, [pc, #352] @ (8004a9c <HAL_ADC_Init+0x1f8>)
  9994. 800493a: 429a cmp r2, r3
  9995. 800493c: f000 8081 beq.w 8004a42 <HAL_ADC_Init+0x19e>
  9996. 8004940: f503 7380 add.w r3, r3, #256 @ 0x100
  9997. 8004944: 429a cmp r2, r3
  9998. 8004946: d07c beq.n 8004a42 <HAL_ADC_Init+0x19e>
  9999. 8004948: 4b55 ldr r3, [pc, #340] @ (8004aa0 <HAL_ADC_Init+0x1fc>)
  10000. 800494a: 689b ldr r3, [r3, #8]
  10001. 800494c: 07d9 lsls r1, r3, #31
  10002. 800494e: f140 8089 bpl.w 8004a64 <HAL_ADC_Init+0x1c0>
  10003. if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
  10004. 8004952: f7ff fb43 bl 8003fdc <HAL_GetREVID>
  10005. 8004956: f241 0303 movw r3, #4099 @ 0x1003
  10006. 800495a: 68a1 ldr r1, [r4, #8]
  10007. 800495c: 4298 cmp r0, r3
  10008. ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
  10009. 800495e: 7f23 ldrb r3, [r4, #28]
  10010. if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
  10011. 8004960: d85c bhi.n 8004a1c <HAL_ADC_Init+0x178>
  10012. tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
  10013. 8004962: f894 c015 ldrb.w ip, [r4, #21]
  10014. ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
  10015. 8004966: 041a lsls r2, r3, #16
  10016. tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
  10017. 8004968: 6b20 ldr r0, [r4, #48] @ 0x30
  10018. 800496a: ea42 324c orr.w r2, r2, ip, lsl #13
  10019. 800496e: 4302 orrs r2, r0
  10020. 8004970: 430a orrs r2, r1
  10021. if (hadc->Init.DiscontinuousConvMode == ENABLE)
  10022. 8004972: 2b01 cmp r3, #1
  10023. 8004974: d103 bne.n 800497e <HAL_ADC_Init+0xda>
  10024. tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
  10025. 8004976: 6a23 ldr r3, [r4, #32]
  10026. 8004978: 3b01 subs r3, #1
  10027. 800497a: ea42 4243 orr.w r2, r2, r3, lsl #17
  10028. if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
  10029. 800497e: 6a63 ldr r3, [r4, #36] @ 0x24
  10030. 8004980: b123 cbz r3, 800498c <HAL_ADC_Init+0xe8>
  10031. tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
  10032. 8004982: f403 7378 and.w r3, r3, #992 @ 0x3e0
  10033. | hadc->Init.ExternalTrigConvEdge
  10034. 8004986: 6aa1 ldr r1, [r4, #40] @ 0x28
  10035. 8004988: 430b orrs r3, r1
  10036. tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
  10037. 800498a: 431a orrs r2, r3
  10038. MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
  10039. 800498c: 6823 ldr r3, [r4, #0]
  10040. 800498e: 4945 ldr r1, [pc, #276] @ (8004aa4 <HAL_ADC_Init+0x200>)
  10041. 8004990: 68d8 ldr r0, [r3, #12]
  10042. 8004992: 4001 ands r1, r0
  10043. 8004994: 4311 orrs r1, r2
  10044. 8004996: 60d9 str r1, [r3, #12]
  10045. return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
  10046. 8004998: 689a ldr r2, [r3, #8]
  10047. 800499a: f012 0f04 tst.w r2, #4
  10048. return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
  10049. 800499e: 689a ldr r2, [r3, #8]
  10050. return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
  10051. 80049a0: d11c bne.n 80049dc <HAL_ADC_Init+0x138>
  10052. return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
  10053. 80049a2: 0712 lsls r2, r2, #28
  10054. 80049a4: d41a bmi.n 80049dc <HAL_ADC_Init+0x138>
  10055. MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
  10056. 80049a6: 68d8 ldr r0, [r3, #12]
  10057. 80049a8: 4a3f ldr r2, [pc, #252] @ (8004aa8 <HAL_ADC_Init+0x204>)
  10058. ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
  10059. 80049aa: 7d21 ldrb r1, [r4, #20]
  10060. MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
  10061. 80049ac: 4002 ands r2, r0
  10062. 80049ae: ea42 3281 orr.w r2, r2, r1, lsl #14
  10063. 80049b2: 6ae1 ldr r1, [r4, #44] @ 0x2c
  10064. 80049b4: 430a orrs r2, r1
  10065. 80049b6: 60da str r2, [r3, #12]
  10066. if (hadc->Init.OversamplingMode == ENABLE)
  10067. 80049b8: f894 2038 ldrb.w r2, [r4, #56] @ 0x38
  10068. 80049bc: 2a01 cmp r2, #1
  10069. 80049be: d053 beq.n 8004a68 <HAL_ADC_Init+0x1c4>
  10070. CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
  10071. 80049c0: 691a ldr r2, [r3, #16]
  10072. 80049c2: f022 0201 bic.w r2, r2, #1
  10073. 80049c6: 611a str r2, [r3, #16]
  10074. MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
  10075. 80049c8: 691a ldr r2, [r3, #16]
  10076. ADC_ConfigureBoostMode(hadc);
  10077. 80049ca: 4620 mov r0, r4
  10078. MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
  10079. 80049cc: 6b61 ldr r1, [r4, #52] @ 0x34
  10080. 80049ce: f022 4270 bic.w r2, r2, #4026531840 @ 0xf0000000
  10081. 80049d2: 430a orrs r2, r1
  10082. 80049d4: 611a str r2, [r3, #16]
  10083. ADC_ConfigureBoostMode(hadc);
  10084. 80049d6: f7ff fea9 bl 800472c <ADC_ConfigureBoostMode>
  10085. MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
  10086. 80049da: 6823 ldr r3, [r4, #0]
  10087. if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
  10088. 80049dc: 68e2 ldr r2, [r4, #12]
  10089. 80049de: 2a01 cmp r2, #1
  10090. 80049e0: d027 beq.n 8004a32 <HAL_ADC_Init+0x18e>
  10091. CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
  10092. 80049e2: 6b1a ldr r2, [r3, #48] @ 0x30
  10093. 80049e4: f022 020f bic.w r2, r2, #15
  10094. 80049e8: 631a str r2, [r3, #48] @ 0x30
  10095. ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
  10096. 80049ea: 6d63 ldr r3, [r4, #84] @ 0x54
  10097. }
  10098. 80049ec: 4628 mov r0, r5
  10099. ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
  10100. 80049ee: f023 0303 bic.w r3, r3, #3
  10101. 80049f2: f043 0301 orr.w r3, r3, #1
  10102. 80049f6: 6563 str r3, [r4, #84] @ 0x54
  10103. }
  10104. 80049f8: b002 add sp, #8
  10105. 80049fa: bd70 pop {r4, r5, r6, pc}
  10106. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  10107. 80049fc: 6d63 ldr r3, [r4, #84] @ 0x54
  10108. 80049fe: f043 0310 orr.w r3, r3, #16
  10109. 8004a02: 6563 str r3, [r4, #84] @ 0x54
  10110. return HAL_ERROR;
  10111. 8004a04: 2501 movs r5, #1
  10112. }
  10113. 8004a06: 4628 mov r0, r5
  10114. 8004a08: b002 add sp, #8
  10115. 8004a0a: bd70 pop {r4, r5, r6, pc}
  10116. HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  10117. 8004a0c: 2500 movs r5, #0
  10118. 8004a0e: e783 b.n 8004918 <HAL_ADC_Init+0x74>
  10119. HAL_ADC_MspInit(hadc);
  10120. 8004a10: f7fd ff42 bl 8002898 <HAL_ADC_MspInit>
  10121. ADC_CLEAR_ERRORCODE(hadc);
  10122. 8004a14: 65a5 str r5, [r4, #88] @ 0x58
  10123. hadc->Lock = HAL_UNLOCKED;
  10124. 8004a16: f884 5050 strb.w r5, [r4, #80] @ 0x50
  10125. 8004a1a: e74f b.n 80048bc <HAL_ADC_Init+0x18>
  10126. if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
  10127. 8004a1c: 2910 cmp r1, #16
  10128. 8004a1e: d1a0 bne.n 8004962 <HAL_ADC_Init+0xbe>
  10129. tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
  10130. 8004a20: 7d61 ldrb r1, [r4, #21]
  10131. ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
  10132. 8004a22: 041a lsls r2, r3, #16
  10133. tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
  10134. 8004a24: ea42 3241 orr.w r2, r2, r1, lsl #13
  10135. 8004a28: 6b21 ldr r1, [r4, #48] @ 0x30
  10136. 8004a2a: 430a orrs r2, r1
  10137. 8004a2c: f042 021c orr.w r2, r2, #28
  10138. 8004a30: e79f b.n 8004972 <HAL_ADC_Init+0xce>
  10139. MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
  10140. 8004a32: 6b19 ldr r1, [r3, #48] @ 0x30
  10141. 8004a34: 69a2 ldr r2, [r4, #24]
  10142. 8004a36: f021 010f bic.w r1, r1, #15
  10143. 8004a3a: 3a01 subs r2, #1
  10144. 8004a3c: 430a orrs r2, r1
  10145. 8004a3e: 631a str r2, [r3, #48] @ 0x30
  10146. 8004a40: e7d3 b.n 80049ea <HAL_ADC_Init+0x146>
  10147. return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
  10148. 8004a42: 4a16 ldr r2, [pc, #88] @ (8004a9c <HAL_ADC_Init+0x1f8>)
  10149. 8004a44: 4b19 ldr r3, [pc, #100] @ (8004aac <HAL_ADC_Init+0x208>)
  10150. 8004a46: 6892 ldr r2, [r2, #8]
  10151. 8004a48: 689b ldr r3, [r3, #8]
  10152. 8004a4a: 07de lsls r6, r3, #31
  10153. 8004a4c: d481 bmi.n 8004952 <HAL_ADC_Init+0xae>
  10154. if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
  10155. 8004a4e: 07d0 lsls r0, r2, #31
  10156. 8004a50: f53f af7f bmi.w 8004952 <HAL_ADC_Init+0xae>
  10157. LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
  10158. 8004a54: 4a16 ldr r2, [pc, #88] @ (8004ab0 <HAL_ADC_Init+0x20c>)
  10159. MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
  10160. 8004a56: 6893 ldr r3, [r2, #8]
  10161. 8004a58: 6861 ldr r1, [r4, #4]
  10162. 8004a5a: f423 137c bic.w r3, r3, #4128768 @ 0x3f0000
  10163. 8004a5e: 430b orrs r3, r1
  10164. 8004a60: 6093 str r3, [r2, #8]
  10165. }
  10166. 8004a62: e776 b.n 8004952 <HAL_ADC_Init+0xae>
  10167. 8004a64: 4a13 ldr r2, [pc, #76] @ (8004ab4 <HAL_ADC_Init+0x210>)
  10168. 8004a66: e7f6 b.n 8004a56 <HAL_ADC_Init+0x1b2>
  10169. MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
  10170. 8004a68: e9d4 120f ldrd r1, r2, [r4, #60] @ 0x3c
  10171. 8004a6c: 6c66 ldr r6, [r4, #68] @ 0x44
  10172. 8004a6e: 3901 subs r1, #1
  10173. 8004a70: 6918 ldr r0, [r3, #16]
  10174. 8004a72: 4332 orrs r2, r6
  10175. 8004a74: ea42 4201 orr.w r2, r2, r1, lsl #16
  10176. 8004a78: 6ca1 ldr r1, [r4, #72] @ 0x48
  10177. 8004a7a: 430a orrs r2, r1
  10178. 8004a7c: 490e ldr r1, [pc, #56] @ (8004ab8 <HAL_ADC_Init+0x214>)
  10179. 8004a7e: 4001 ands r1, r0
  10180. 8004a80: 430a orrs r2, r1
  10181. 8004a82: f042 0201 orr.w r2, r2, #1
  10182. 8004a86: 611a str r2, [r3, #16]
  10183. 8004a88: e79e b.n 80049c8 <HAL_ADC_Init+0x124>
  10184. 8004a8a: bf00 nop
  10185. 8004a8c: 5fffffc0 .word 0x5fffffc0
  10186. 8004a90: 24000038 .word 0x24000038
  10187. 8004a94: 053e2d63 .word 0x053e2d63
  10188. 8004a98: 6fffffc0 .word 0x6fffffc0
  10189. 8004a9c: 40022000 .word 0x40022000
  10190. 8004aa0: 58026000 .word 0x58026000
  10191. 8004aa4: fff0c003 .word 0xfff0c003
  10192. 8004aa8: ffffbffc .word 0xffffbffc
  10193. 8004aac: 40022100 .word 0x40022100
  10194. 8004ab0: 40022300 .word 0x40022300
  10195. 8004ab4: 58026300 .word 0x58026300
  10196. 8004ab8: fc00f81e .word 0xfc00f81e
  10197. 08004abc <HAL_ADCEx_Calibration_Start>:
  10198. * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
  10199. * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
  10200. * @retval HAL status
  10201. */
  10202. HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
  10203. {
  10204. 8004abc: b5f0 push {r4, r5, r6, r7, lr}
  10205. HAL_StatusTypeDef tmp_hal_status;
  10206. __IO uint32_t wait_loop_index = 0UL;
  10207. 8004abe: 2300 movs r3, #0
  10208. {
  10209. 8004ac0: b083 sub sp, #12
  10210. __IO uint32_t wait_loop_index = 0UL;
  10211. 8004ac2: 9301 str r3, [sp, #4]
  10212. /* Check the parameters */
  10213. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  10214. assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
  10215. /* Process locked */
  10216. __HAL_LOCK(hadc);
  10217. 8004ac4: f890 3050 ldrb.w r3, [r0, #80] @ 0x50
  10218. 8004ac8: 2b01 cmp r3, #1
  10219. 8004aca: d040 beq.n 8004b4e <HAL_ADCEx_Calibration_Start+0x92>
  10220. 8004acc: 2301 movs r3, #1
  10221. 8004ace: 4604 mov r4, r0
  10222. 8004ad0: 460e mov r6, r1
  10223. 8004ad2: 4615 mov r5, r2
  10224. 8004ad4: f880 3050 strb.w r3, [r0, #80] @ 0x50
  10225. /* Calibration prerequisite: ADC must be disabled. */
  10226. /* Disable the ADC (if not already disabled) */
  10227. tmp_hal_status = ADC_Disable(hadc);
  10228. 8004ad8: f7ff fdee bl 80046b8 <ADC_Disable>
  10229. /* Check if ADC is effectively disabled */
  10230. if (tmp_hal_status == HAL_OK)
  10231. 8004adc: b9e8 cbnz r0, 8004b1a <HAL_ADCEx_Calibration_Start+0x5e>
  10232. {
  10233. /* Set ADC state */
  10234. ADC_STATE_CLR_SET(hadc->State,
  10235. 8004ade: 6d67 ldr r7, [r4, #84] @ 0x54
  10236. MODIFY_REG(ADCx->CR,
  10237. 8004ae0: f005 4280 and.w r2, r5, #1073741824 @ 0x40000000
  10238. 8004ae4: 4b1b ldr r3, [pc, #108] @ (8004b54 <HAL_ADCEx_Calibration_Start+0x98>)
  10239. 8004ae6: f406 3180 and.w r1, r6, #65536 @ 0x10000
  10240. HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
  10241. HAL_ADC_STATE_BUSY_INTERNAL);
  10242. /* Start ADC calibration in mode single-ended or differential */
  10243. LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff);
  10244. 8004aea: 6825 ldr r5, [r4, #0]
  10245. ADC_STATE_CLR_SET(hadc->State,
  10246. 8004aec: 403b ands r3, r7
  10247. 8004aee: f043 0302 orr.w r3, r3, #2
  10248. 8004af2: 6563 str r3, [r4, #84] @ 0x54
  10249. 8004af4: 4b18 ldr r3, [pc, #96] @ (8004b58 <HAL_ADCEx_Calibration_Start+0x9c>)
  10250. 8004af6: 68ae ldr r6, [r5, #8]
  10251. 8004af8: 4033 ands r3, r6
  10252. 8004afa: 4313 orrs r3, r2
  10253. 8004afc: 430b orrs r3, r1
  10254. 8004afe: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
  10255. 8004b02: 60ab str r3, [r5, #8]
  10256. return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
  10257. 8004b04: 68ab ldr r3, [r5, #8]
  10258. /* Wait for calibration completion */
  10259. while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
  10260. {
  10261. wait_loop_index++;
  10262. if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
  10263. 8004b06: 4a15 ldr r2, [pc, #84] @ (8004b5c <HAL_ADCEx_Calibration_Start+0xa0>)
  10264. 8004b08: 2b00 cmp r3, #0
  10265. 8004b0a: db0f blt.n 8004b2c <HAL_ADCEx_Calibration_Start+0x70>
  10266. return HAL_ERROR;
  10267. }
  10268. }
  10269. /* Set ADC state */
  10270. ADC_STATE_CLR_SET(hadc->State,
  10271. 8004b0c: 6d63 ldr r3, [r4, #84] @ 0x54
  10272. 8004b0e: f023 0303 bic.w r3, r3, #3
  10273. 8004b12: f043 0301 orr.w r3, r3, #1
  10274. 8004b16: 6563 str r3, [r4, #84] @ 0x54
  10275. 8004b18: e003 b.n 8004b22 <HAL_ADCEx_Calibration_Start+0x66>
  10276. HAL_ADC_STATE_BUSY_INTERNAL,
  10277. HAL_ADC_STATE_READY);
  10278. }
  10279. else
  10280. {
  10281. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  10282. 8004b1a: 6d63 ldr r3, [r4, #84] @ 0x54
  10283. 8004b1c: f043 0310 orr.w r3, r3, #16
  10284. 8004b20: 6563 str r3, [r4, #84] @ 0x54
  10285. /* Note: No need to update variable "tmp_hal_status" here: already set */
  10286. /* to state "HAL_ERROR" by function disabling the ADC. */
  10287. }
  10288. /* Process unlocked */
  10289. __HAL_UNLOCK(hadc);
  10290. 8004b22: 2300 movs r3, #0
  10291. 8004b24: f884 3050 strb.w r3, [r4, #80] @ 0x50
  10292. /* Return function status */
  10293. return tmp_hal_status;
  10294. }
  10295. 8004b28: b003 add sp, #12
  10296. 8004b2a: bdf0 pop {r4, r5, r6, r7, pc}
  10297. wait_loop_index++;
  10298. 8004b2c: 9b01 ldr r3, [sp, #4]
  10299. 8004b2e: 3301 adds r3, #1
  10300. 8004b30: 9301 str r3, [sp, #4]
  10301. if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
  10302. 8004b32: 9b01 ldr r3, [sp, #4]
  10303. 8004b34: 4293 cmp r3, r2
  10304. 8004b36: d3e5 bcc.n 8004b04 <HAL_ADCEx_Calibration_Start+0x48>
  10305. ADC_STATE_CLR_SET(hadc->State,
  10306. 8004b38: 6d63 ldr r3, [r4, #84] @ 0x54
  10307. __HAL_UNLOCK(hadc);
  10308. 8004b3a: 2200 movs r2, #0
  10309. return HAL_ERROR;
  10310. 8004b3c: 2001 movs r0, #1
  10311. ADC_STATE_CLR_SET(hadc->State,
  10312. 8004b3e: f023 0312 bic.w r3, r3, #18
  10313. __HAL_UNLOCK(hadc);
  10314. 8004b42: f884 2050 strb.w r2, [r4, #80] @ 0x50
  10315. ADC_STATE_CLR_SET(hadc->State,
  10316. 8004b46: f043 0310 orr.w r3, r3, #16
  10317. 8004b4a: 6563 str r3, [r4, #84] @ 0x54
  10318. return HAL_ERROR;
  10319. 8004b4c: e7ec b.n 8004b28 <HAL_ADCEx_Calibration_Start+0x6c>
  10320. __HAL_LOCK(hadc);
  10321. 8004b4e: 2002 movs r0, #2
  10322. }
  10323. 8004b50: b003 add sp, #12
  10324. 8004b52: bdf0 pop {r4, r5, r6, r7, pc}
  10325. 8004b54: ffffeefd .word 0xffffeefd
  10326. 8004b58: 3ffeffc0 .word 0x3ffeffc0
  10327. 8004b5c: 25c3f800 .word 0x25c3f800
  10328. 08004b60 <HAL_ADCEx_MultiModeStart_DMA>:
  10329. * @param pData Destination Buffer address.
  10330. * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
  10331. * @retval HAL status
  10332. */
  10333. HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
  10334. {
  10335. 8004b60: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  10336. /* Check the parameters */
  10337. assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
  10338. assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  10339. assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
  10340. if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
  10341. 8004b64: 6806 ldr r6, [r0, #0]
  10342. {
  10343. 8004b66: b09a sub sp, #104 @ 0x68
  10344. return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
  10345. 8004b68: 68b5 ldr r5, [r6, #8]
  10346. 8004b6a: f015 0504 ands.w r5, r5, #4
  10347. 8004b6e: d11c bne.n 8004baa <HAL_ADCEx_MultiModeStart_DMA+0x4a>
  10348. return HAL_BUSY;
  10349. }
  10350. else
  10351. {
  10352. /* Process locked */
  10353. __HAL_LOCK(hadc);
  10354. 8004b70: f890 3050 ldrb.w r3, [r0, #80] @ 0x50
  10355. 8004b74: 4604 mov r4, r0
  10356. 8004b76: 2b01 cmp r3, #1
  10357. 8004b78: d017 beq.n 8004baa <HAL_ADCEx_MultiModeStart_DMA+0x4a>
  10358. /* Case of ADC slave using its own DMA channel: check whether handle selected
  10359. corresponds to ADC master or slave instance */
  10360. if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance)
  10361. 8004b7a: 4b2f ldr r3, [pc, #188] @ (8004c38 <HAL_ADCEx_MultiModeStart_DMA+0xd8>)
  10362. __HAL_LOCK(hadc);
  10363. 8004b7c: f04f 0c01 mov.w ip, #1
  10364. 8004b80: 460f mov r7, r1
  10365. 8004b82: 4690 mov r8, r2
  10366. if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance)
  10367. 8004b84: 429e cmp r6, r3
  10368. __HAL_LOCK(hadc);
  10369. 8004b86: f880 c050 strb.w ip, [r0, #80] @ 0x50
  10370. if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance)
  10371. 8004b8a: d018 beq.n 8004bbe <HAL_ADCEx_MultiModeStart_DMA+0x5e>
  10372. else
  10373. {
  10374. tmphadcSlave.State = HAL_ADC_STATE_RESET;
  10375. tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
  10376. /* Set a temporary handle of the ADC slave associated to the ADC master */
  10377. ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  10378. 8004b8c: 4a2b ldr r2, [pc, #172] @ (8004c3c <HAL_ADCEx_MultiModeStart_DMA+0xdc>)
  10379. tmphadcSlave.State = HAL_ADC_STATE_RESET;
  10380. 8004b8e: 9516 str r5, [sp, #88] @ 0x58
  10381. ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  10382. 8004b90: 4296 cmp r6, r2
  10383. tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
  10384. 8004b92: 9517 str r5, [sp, #92] @ 0x5c
  10385. ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  10386. 8004b94: d00d beq.n 8004bb2 <HAL_ADCEx_MultiModeStart_DMA+0x52>
  10387. if (tmphadcSlave.Instance == NULL)
  10388. {
  10389. /* Set ADC state */
  10390. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  10391. 8004b96: 6d43 ldr r3, [r0, #84] @ 0x54
  10392. /* Process unlocked */
  10393. __HAL_UNLOCK(hadc);
  10394. return HAL_ERROR;
  10395. 8004b98: 4660 mov r0, ip
  10396. __HAL_UNLOCK(hadc);
  10397. 8004b9a: f884 5050 strb.w r5, [r4, #80] @ 0x50
  10398. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  10399. 8004b9e: f043 0320 orr.w r3, r3, #32
  10400. 8004ba2: 6563 str r3, [r4, #84] @ 0x54
  10401. }
  10402. /* Return function status */
  10403. return tmp_hal_status;
  10404. }
  10405. }
  10406. 8004ba4: b01a add sp, #104 @ 0x68
  10407. 8004ba6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  10408. return HAL_BUSY;
  10409. 8004baa: 2002 movs r0, #2
  10410. }
  10411. 8004bac: b01a add sp, #104 @ 0x68
  10412. 8004bae: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  10413. 8004bb2: 9301 str r3, [sp, #4]
  10414. tmp_hal_status = ADC_Enable(hadc);
  10415. 8004bb4: f7ff fc9a bl 80044ec <ADC_Enable>
  10416. if (tmp_hal_status == HAL_OK)
  10417. 8004bb8: 2800 cmp r0, #0
  10418. 8004bba: d132 bne.n 8004c22 <HAL_ADCEx_MultiModeStart_DMA+0xc2>
  10419. tmp_hal_status = ADC_Enable(&tmphadcSlave);
  10420. 8004bbc: a801 add r0, sp, #4
  10421. 8004bbe: f7ff fc95 bl 80044ec <ADC_Enable>
  10422. if (tmp_hal_status == HAL_OK)
  10423. 8004bc2: 2800 cmp r0, #0
  10424. 8004bc4: d12d bne.n 8004c22 <HAL_ADCEx_MultiModeStart_DMA+0xc2>
  10425. ADC_STATE_CLR_SET(hadc->State,
  10426. 8004bc6: 6d62 ldr r2, [r4, #84] @ 0x54
  10427. 8004bc8: 4b1d ldr r3, [pc, #116] @ (8004c40 <HAL_ADCEx_MultiModeStart_DMA+0xe0>)
  10428. hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
  10429. 8004bca: 6ce6 ldr r6, [r4, #76] @ 0x4c
  10430. ADC_STATE_CLR_SET(hadc->State,
  10431. 8004bcc: 4013 ands r3, r2
  10432. __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
  10433. 8004bce: 6825 ldr r5, [r4, #0]
  10434. tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
  10435. 8004bd0: 463a mov r2, r7
  10436. ADC_STATE_CLR_SET(hadc->State,
  10437. 8004bd2: f443 7380 orr.w r3, r3, #256 @ 0x100
  10438. 8004bd6: 6563 str r3, [r4, #84] @ 0x54
  10439. hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
  10440. 8004bd8: 4b1a ldr r3, [pc, #104] @ (8004c44 <HAL_ADCEx_MultiModeStart_DMA+0xe4>)
  10441. ADC_CLEAR_ERRORCODE(hadc);
  10442. 8004bda: 65a0 str r0, [r4, #88] @ 0x58
  10443. hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
  10444. 8004bdc: 63f3 str r3, [r6, #60] @ 0x3c
  10445. hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
  10446. 8004bde: 4b1a ldr r3, [pc, #104] @ (8004c48 <HAL_ADCEx_MultiModeStart_DMA+0xe8>)
  10447. 8004be0: 6433 str r3, [r6, #64] @ 0x40
  10448. hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
  10449. 8004be2: 4b1a ldr r3, [pc, #104] @ (8004c4c <HAL_ADCEx_MultiModeStart_DMA+0xec>)
  10450. 8004be4: 64f3 str r3, [r6, #76] @ 0x4c
  10451. __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
  10452. 8004be6: 231c movs r3, #28
  10453. 8004be8: 602b str r3, [r5, #0]
  10454. __HAL_UNLOCK(hadc);
  10455. 8004bea: f884 0050 strb.w r0, [r4, #80] @ 0x50
  10456. __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
  10457. 8004bee: 686b ldr r3, [r5, #4]
  10458. 8004bf0: f043 0310 orr.w r3, r3, #16
  10459. 8004bf4: 606b str r3, [r5, #4]
  10460. if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance)
  10461. 8004bf6: 4b10 ldr r3, [pc, #64] @ (8004c38 <HAL_ADCEx_MultiModeStart_DMA+0xd8>)
  10462. 8004bf8: 429d cmp r5, r3
  10463. tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
  10464. 8004bfa: 4643 mov r3, r8
  10465. if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance)
  10466. 8004bfc: d017 beq.n 8004c2e <HAL_ADCEx_MultiModeStart_DMA+0xce>
  10467. tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
  10468. 8004bfe: 4630 mov r0, r6
  10469. tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
  10470. 8004c00: 4f0e ldr r7, [pc, #56] @ (8004c3c <HAL_ADCEx_MultiModeStart_DMA+0xdc>)
  10471. 8004c02: 4913 ldr r1, [pc, #76] @ (8004c50 <HAL_ADCEx_MultiModeStart_DMA+0xf0>)
  10472. 8004c04: 4e13 ldr r6, [pc, #76] @ (8004c54 <HAL_ADCEx_MultiModeStart_DMA+0xf4>)
  10473. 8004c06: 42bd cmp r5, r7
  10474. 8004c08: bf08 it eq
  10475. 8004c0a: 4631 moveq r1, r6
  10476. tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
  10477. 8004c0c: 310c adds r1, #12
  10478. 8004c0e: f000 ffd5 bl 8005bbc <HAL_DMA_Start_IT>
  10479. LL_ADC_REG_StartConversion(hadc->Instance);
  10480. 8004c12: 6822 ldr r2, [r4, #0]
  10481. MODIFY_REG(ADCx->CR,
  10482. 8004c14: 4b10 ldr r3, [pc, #64] @ (8004c58 <HAL_ADCEx_MultiModeStart_DMA+0xf8>)
  10483. 8004c16: 6891 ldr r1, [r2, #8]
  10484. 8004c18: 400b ands r3, r1
  10485. 8004c1a: f043 0304 orr.w r3, r3, #4
  10486. 8004c1e: 6093 str r3, [r2, #8]
  10487. }
  10488. 8004c20: e7c4 b.n 8004bac <HAL_ADCEx_MultiModeStart_DMA+0x4c>
  10489. __HAL_UNLOCK(hadc);
  10490. 8004c22: 2300 movs r3, #0
  10491. 8004c24: f884 3050 strb.w r3, [r4, #80] @ 0x50
  10492. }
  10493. 8004c28: b01a add sp, #104 @ 0x68
  10494. 8004c2a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  10495. tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
  10496. 8004c2e: 490b ldr r1, [pc, #44] @ (8004c5c <HAL_ADCEx_MultiModeStart_DMA+0xfc>)
  10497. 8004c30: 4630 mov r0, r6
  10498. 8004c32: f000 ffc3 bl 8005bbc <HAL_DMA_Start_IT>
  10499. 8004c36: e7b9 b.n 8004bac <HAL_ADCEx_MultiModeStart_DMA+0x4c>
  10500. 8004c38: 40022100 .word 0x40022100
  10501. 8004c3c: 40022000 .word 0x40022000
  10502. 8004c40: fffff0fe .word 0xfffff0fe
  10503. 8004c44: 08004035 .word 0x08004035
  10504. 8004c48: 08004025 .word 0x08004025
  10505. 8004c4c: 080040a1 .word 0x080040a1
  10506. 8004c50: 58026300 .word 0x58026300
  10507. 8004c54: 40022300 .word 0x40022300
  10508. 8004c58: 7fffffc0 .word 0x7fffffc0
  10509. 8004c5c: 40022140 .word 0x40022140
  10510. 08004c60 <HAL_ADCEx_MultiModeConfigChannel>:
  10511. * @param hadc Master ADC handle
  10512. * @param multimode Structure of ADC multimode configuration
  10513. * @retval HAL status
  10514. */
  10515. HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
  10516. {
  10517. 8004c60: b4f0 push {r4, r5, r6, r7}
  10518. assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData));
  10519. assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
  10520. }
  10521. /* Process locked */
  10522. __HAL_LOCK(hadc);
  10523. 8004c62: f890 2050 ldrb.w r2, [r0, #80] @ 0x50
  10524. {
  10525. 8004c66: b09a sub sp, #104 @ 0x68
  10526. if (multimode->Mode != ADC_MODE_INDEPENDENT)
  10527. 8004c68: 680e ldr r6, [r1, #0]
  10528. __HAL_LOCK(hadc);
  10529. 8004c6a: 2a01 cmp r2, #1
  10530. 8004c6c: d038 beq.n 8004ce0 <HAL_ADCEx_MultiModeConfigChannel+0x80>
  10531. 8004c6e: 4603 mov r3, r0
  10532. tmphadcSlave.State = HAL_ADC_STATE_RESET;
  10533. tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
  10534. ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  10535. 8004c70: 4d28 ldr r5, [pc, #160] @ (8004d14 <HAL_ADCEx_MultiModeConfigChannel+0xb4>)
  10536. tmphadcSlave.State = HAL_ADC_STATE_RESET;
  10537. 8004c72: 2200 movs r2, #0
  10538. __HAL_LOCK(hadc);
  10539. 8004c74: 2001 movs r0, #1
  10540. ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  10541. 8004c76: 681c ldr r4, [r3, #0]
  10542. tmphadcSlave.State = HAL_ADC_STATE_RESET;
  10543. 8004c78: 9216 str r2, [sp, #88] @ 0x58
  10544. ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  10545. 8004c7a: 42ac cmp r4, r5
  10546. __HAL_LOCK(hadc);
  10547. 8004c7c: f883 0050 strb.w r0, [r3, #80] @ 0x50
  10548. tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
  10549. 8004c80: 9217 str r2, [sp, #92] @ 0x5c
  10550. ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  10551. 8004c82: d008 beq.n 8004c96 <HAL_ADCEx_MultiModeConfigChannel+0x36>
  10552. if (tmphadcSlave.Instance == NULL)
  10553. {
  10554. /* Update ADC state machine to error */
  10555. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  10556. 8004c84: 6d59 ldr r1, [r3, #84] @ 0x54
  10557. /* Process unlocked */
  10558. __HAL_UNLOCK(hadc);
  10559. 8004c86: f883 2050 strb.w r2, [r3, #80] @ 0x50
  10560. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  10561. 8004c8a: f041 0120 orr.w r1, r1, #32
  10562. 8004c8e: 6559 str r1, [r3, #84] @ 0x54
  10563. /* Process unlocked */
  10564. __HAL_UNLOCK(hadc);
  10565. /* Return function status */
  10566. return tmp_hal_status;
  10567. }
  10568. 8004c90: b01a add sp, #104 @ 0x68
  10569. 8004c92: bcf0 pop {r4, r5, r6, r7}
  10570. 8004c94: 4770 bx lr
  10571. return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
  10572. 8004c96: 4a20 ldr r2, [pc, #128] @ (8004d18 <HAL_ADCEx_MultiModeConfigChannel+0xb8>)
  10573. 8004c98: 6890 ldr r0, [r2, #8]
  10574. 8004c9a: 0740 lsls r0, r0, #29
  10575. 8004c9c: d50b bpl.n 8004cb6 <HAL_ADCEx_MultiModeConfigChannel+0x56>
  10576. 8004c9e: 68a2 ldr r2, [r4, #8]
  10577. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  10578. 8004ca0: 6d5a ldr r2, [r3, #84] @ 0x54
  10579. tmp_hal_status = HAL_ERROR;
  10580. 8004ca2: 2001 movs r0, #1
  10581. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  10582. 8004ca4: f042 0220 orr.w r2, r2, #32
  10583. 8004ca8: 655a str r2, [r3, #84] @ 0x54
  10584. __HAL_UNLOCK(hadc);
  10585. 8004caa: 2200 movs r2, #0
  10586. 8004cac: f883 2050 strb.w r2, [r3, #80] @ 0x50
  10587. }
  10588. 8004cb0: b01a add sp, #104 @ 0x68
  10589. 8004cb2: bcf0 pop {r4, r5, r6, r7}
  10590. 8004cb4: 4770 bx lr
  10591. 8004cb6: 68a0 ldr r0, [r4, #8]
  10592. 8004cb8: 0745 lsls r5, r0, #29
  10593. 8004cba: d4f1 bmi.n 8004ca0 <HAL_ADCEx_MultiModeConfigChannel+0x40>
  10594. if (multimode->Mode != ADC_MODE_INDEPENDENT)
  10595. 8004cbc: b9a6 cbnz r6, 8004ce8 <HAL_ADCEx_MultiModeConfigChannel+0x88>
  10596. CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
  10597. 8004cbe: 4917 ldr r1, [pc, #92] @ (8004d1c <HAL_ADCEx_MultiModeConfigChannel+0xbc>)
  10598. 8004cc0: 6888 ldr r0, [r1, #8]
  10599. 8004cc2: f420 4040 bic.w r0, r0, #49152 @ 0xc000
  10600. 8004cc6: 6088 str r0, [r1, #8]
  10601. return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
  10602. 8004cc8: 68a0 ldr r0, [r4, #8]
  10603. 8004cca: 6892 ldr r2, [r2, #8]
  10604. 8004ccc: 07d4 lsls r4, r2, #31
  10605. 8004cce: d405 bmi.n 8004cdc <HAL_ADCEx_MultiModeConfigChannel+0x7c>
  10606. if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
  10607. 8004cd0: 07c5 lsls r5, r0, #31
  10608. 8004cd2: d403 bmi.n 8004cdc <HAL_ADCEx_MultiModeConfigChannel+0x7c>
  10609. CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
  10610. 8004cd4: 6888 ldr r0, [r1, #8]
  10611. 8004cd6: 4a12 ldr r2, [pc, #72] @ (8004d20 <HAL_ADCEx_MultiModeConfigChannel+0xc0>)
  10612. 8004cd8: 4002 ands r2, r0
  10613. 8004cda: 608a str r2, [r1, #8]
  10614. HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  10615. 8004cdc: 2000 movs r0, #0
  10616. 8004cde: e7e4 b.n 8004caa <HAL_ADCEx_MultiModeConfigChannel+0x4a>
  10617. __HAL_LOCK(hadc);
  10618. 8004ce0: 2002 movs r0, #2
  10619. }
  10620. 8004ce2: b01a add sp, #104 @ 0x68
  10621. 8004ce4: bcf0 pop {r4, r5, r6, r7}
  10622. 8004ce6: 4770 bx lr
  10623. MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
  10624. 8004ce8: 4f0c ldr r7, [pc, #48] @ (8004d1c <HAL_ADCEx_MultiModeConfigChannel+0xbc>)
  10625. 8004cea: 684d ldr r5, [r1, #4]
  10626. 8004cec: 68b8 ldr r0, [r7, #8]
  10627. 8004cee: f420 4040 bic.w r0, r0, #49152 @ 0xc000
  10628. 8004cf2: 4328 orrs r0, r5
  10629. 8004cf4: 60b8 str r0, [r7, #8]
  10630. 8004cf6: 68a0 ldr r0, [r4, #8]
  10631. 8004cf8: 6892 ldr r2, [r2, #8]
  10632. 8004cfa: 07d4 lsls r4, r2, #31
  10633. 8004cfc: d4ee bmi.n 8004cdc <HAL_ADCEx_MultiModeConfigChannel+0x7c>
  10634. if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
  10635. 8004cfe: 07c2 lsls r2, r0, #31
  10636. 8004d00: d4ec bmi.n 8004cdc <HAL_ADCEx_MultiModeConfigChannel+0x7c>
  10637. MODIFY_REG(tmpADC_Common->CCR,
  10638. 8004d02: 688a ldr r2, [r1, #8]
  10639. 8004d04: 68b8 ldr r0, [r7, #8]
  10640. 8004d06: 4906 ldr r1, [pc, #24] @ (8004d20 <HAL_ADCEx_MultiModeConfigChannel+0xc0>)
  10641. 8004d08: 4332 orrs r2, r6
  10642. 8004d0a: 4001 ands r1, r0
  10643. 8004d0c: 430a orrs r2, r1
  10644. 8004d0e: 60ba str r2, [r7, #8]
  10645. 8004d10: e7e4 b.n 8004cdc <HAL_ADCEx_MultiModeConfigChannel+0x7c>
  10646. 8004d12: bf00 nop
  10647. 8004d14: 40022000 .word 0x40022000
  10648. 8004d18: 40022100 .word 0x40022100
  10649. 8004d1c: 40022300 .word 0x40022300
  10650. 8004d20: fffff0e0 .word 0xfffff0e0
  10651. 08004d24 <HAL_COMP_Init>:
  10652. * To unlock the configuration, perform a system reset.
  10653. * @param hcomp COMP handle
  10654. * @retval HAL status
  10655. */
  10656. HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
  10657. {
  10658. 8004d24: b530 push {r4, r5, lr}
  10659. uint32_t tmp_csr ;
  10660. uint32_t exti_line ;
  10661. uint32_t comp_voltage_scaler_initialized; /* Value "0" is comparator voltage scaler is not initialized */
  10662. __IO uint32_t wait_loop_index = 0UL;
  10663. 8004d26: 2300 movs r3, #0
  10664. {
  10665. 8004d28: b083 sub sp, #12
  10666. __IO uint32_t wait_loop_index = 0UL;
  10667. 8004d2a: 9301 str r3, [sp, #4]
  10668. HAL_StatusTypeDef status = HAL_OK;
  10669. /* Check the COMP handle allocation and lock status */
  10670. if(hcomp == NULL)
  10671. 8004d2c: 2800 cmp r0, #0
  10672. 8004d2e: d063 beq.n 8004df8 <HAL_COMP_Init+0xd4>
  10673. {
  10674. status = HAL_ERROR;
  10675. }
  10676. else if(__HAL_COMP_IS_LOCKED(hcomp))
  10677. 8004d30: 6802 ldr r2, [r0, #0]
  10678. 8004d32: 4604 mov r4, r0
  10679. 8004d34: 6813 ldr r3, [r2, #0]
  10680. 8004d36: 2b00 cmp r3, #0
  10681. 8004d38: db5e blt.n 8004df8 <HAL_COMP_Init+0xd4>
  10682. assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
  10683. assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
  10684. assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
  10685. assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
  10686. if(hcomp->State == HAL_COMP_STATE_RESET)
  10687. 8004d3a: f890 3025 ldrb.w r3, [r0, #37] @ 0x25
  10688. 8004d3e: f003 01ff and.w r1, r3, #255 @ 0xff
  10689. 8004d42: 2b00 cmp r3, #0
  10690. 8004d44: f000 808e beq.w 8004e64 <HAL_COMP_Init+0x140>
  10691. /* Set HYST bits according to hcomp->Init.Hysteresis value */
  10692. /* Set POLARITY bit according to hcomp->Init.OutputPol value */
  10693. /* Set POWERMODE bits according to hcomp->Init.Mode value */
  10694. tmp_csr = (hcomp->Init.InvertingInput | \
  10695. hcomp->Init.NonInvertingInput | \
  10696. 8004d48: 69e1 ldr r1, [r4, #28]
  10697. comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN);
  10698. 8004d4a: 6810 ldr r0, [r2, #0]
  10699. tmp_csr = (hcomp->Init.InvertingInput | \
  10700. 8004d4c: e9d4 5303 ldrd r5, r3, [r4, #12]
  10701. comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN);
  10702. 8004d50: f000 0004 and.w r0, r0, #4
  10703. tmp_csr = (hcomp->Init.InvertingInput | \
  10704. 8004d54: 432b orrs r3, r5
  10705. COMP_CFGRx_INP2SEL | COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST |
  10706. COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN | COMP_CFGRx_SCALEN,
  10707. tmp_csr
  10708. );
  10709. #else
  10710. MODIFY_REG(hcomp->Instance->CFGR,
  10711. 8004d56: 6815 ldr r5, [r2, #0]
  10712. hcomp->Init.NonInvertingInput | \
  10713. 8004d58: 430b orrs r3, r1
  10714. hcomp->Init.BlankingSrce | \
  10715. 8004d5a: 6961 ldr r1, [r4, #20]
  10716. 8004d5c: 430b orrs r3, r1
  10717. hcomp->Init.Hysteresis | \
  10718. 8004d5e: 69a1 ldr r1, [r4, #24]
  10719. 8004d60: 430b orrs r3, r1
  10720. tmp_csr = (hcomp->Init.InvertingInput | \
  10721. 8004d62: 68a1 ldr r1, [r4, #8]
  10722. 8004d64: 430b orrs r3, r1
  10723. MODIFY_REG(hcomp->Instance->CFGR,
  10724. 8004d66: 4943 ldr r1, [pc, #268] @ (8004e74 <HAL_COMP_Init+0x150>)
  10725. 8004d68: 4029 ands r1, r5
  10726. 8004d6a: 430b orrs r3, r1
  10727. #endif
  10728. /* Set window mode */
  10729. /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */
  10730. /* instances. Therefore, this function can update another COMP */
  10731. /* instance that the one currently selected. */
  10732. if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
  10733. 8004d6c: 6861 ldr r1, [r4, #4]
  10734. MODIFY_REG(hcomp->Instance->CFGR,
  10735. 8004d6e: 6013 str r3, [r2, #0]
  10736. if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
  10737. 8004d70: 2910 cmp r1, #16
  10738. {
  10739. SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE);
  10740. 8004d72: 6813 ldr r3, [r2, #0]
  10741. 8004d74: bf0c ite eq
  10742. 8004d76: f043 0310 orreq.w r3, r3, #16
  10743. }
  10744. else
  10745. {
  10746. CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE);
  10747. 8004d7a: f023 0310 bicne.w r3, r3, #16
  10748. 8004d7e: 6013 str r3, [r2, #0]
  10749. }
  10750. /* Delay for COMP scaler bridge voltage stabilization */
  10751. /* Apply the delay if voltage scaler bridge is enabled for the first time */
  10752. if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0UL) &&
  10753. 8004d80: 6813 ldr r3, [r2, #0]
  10754. 8004d82: 075d lsls r5, r3, #29
  10755. 8004d84: d501 bpl.n 8004d8a <HAL_COMP_Init+0x66>
  10756. 8004d86: 2800 cmp r0, #0
  10757. 8004d88: d156 bne.n 8004e38 <HAL_COMP_Init+0x114>
  10758. wait_loop_index --;
  10759. }
  10760. }
  10761. /* Get the EXTI line corresponding to the selected COMP instance */
  10762. exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
  10763. 8004d8a: 493b ldr r1, [pc, #236] @ (8004e78 <HAL_COMP_Init+0x154>)
  10764. /* Manage EXTI settings */
  10765. if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
  10766. 8004d8c: 6a23 ldr r3, [r4, #32]
  10767. exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
  10768. 8004d8e: 428a cmp r2, r1
  10769. 8004d90: bf15 itete ne
  10770. 8004d92: f46f 1200 mvnne.w r2, #2097152 @ 0x200000
  10771. 8004d96: f46f 1280 mvneq.w r2, #1048576 @ 0x100000
  10772. 8004d9a: f44f 1100 movne.w r1, #2097152 @ 0x200000
  10773. 8004d9e: f44f 1180 moveq.w r1, #1048576 @ 0x100000
  10774. if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
  10775. 8004da2: 0798 lsls r0, r3, #30
  10776. 8004da4: d02b beq.n 8004dfe <HAL_COMP_Init+0xda>
  10777. {
  10778. /* Configure EXTI rising edge */
  10779. if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
  10780. {
  10781. SET_BIT(EXTI->RTSR1, exti_line);
  10782. 8004da6: f04f 45b0 mov.w r5, #1476395008 @ 0x58000000
  10783. if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
  10784. 8004daa: f013 0f10 tst.w r3, #16
  10785. SET_BIT(EXTI->RTSR1, exti_line);
  10786. 8004dae: 6828 ldr r0, [r5, #0]
  10787. 8004db0: bf14 ite ne
  10788. 8004db2: 4308 orrne r0, r1
  10789. }
  10790. else
  10791. {
  10792. CLEAR_BIT(EXTI->RTSR1, exti_line);
  10793. 8004db4: 4010 andeq r0, r2
  10794. }
  10795. /* Configure EXTI falling edge */
  10796. if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
  10797. 8004db6: f013 0f20 tst.w r3, #32
  10798. CLEAR_BIT(EXTI->RTSR1, exti_line);
  10799. 8004dba: 6028 str r0, [r5, #0]
  10800. {
  10801. SET_BIT(EXTI->FTSR1, exti_line);
  10802. 8004dbc: f04f 45b0 mov.w r5, #1476395008 @ 0x58000000
  10803. 8004dc0: 6868 ldr r0, [r5, #4]
  10804. 8004dc2: bf14 ite ne
  10805. 8004dc4: 4308 orrne r0, r1
  10806. }
  10807. else
  10808. {
  10809. CLEAR_BIT(EXTI->FTSR1, exti_line);
  10810. 8004dc6: 4010 andeq r0, r2
  10811. #if !defined (CORE_CM4)
  10812. /* Clear COMP EXTI pending bit (if any) */
  10813. WRITE_REG(EXTI->PR1, exti_line);
  10814. /* Configure EXTI event mode */
  10815. if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
  10816. 8004dc8: f013 0f02 tst.w r3, #2
  10817. CLEAR_BIT(EXTI->FTSR1, exti_line);
  10818. 8004dcc: 6068 str r0, [r5, #4]
  10819. WRITE_REG(EXTI->PR1, exti_line);
  10820. 8004dce: f04f 40b0 mov.w r0, #1476395008 @ 0x58000000
  10821. 8004dd2: f8c0 1088 str.w r1, [r0, #136] @ 0x88
  10822. {
  10823. SET_BIT(EXTI->EMR1, exti_line);
  10824. 8004dd6: f8d0 5084 ldr.w r5, [r0, #132] @ 0x84
  10825. 8004dda: bf14 ite ne
  10826. 8004ddc: 430d orrne r5, r1
  10827. }
  10828. else
  10829. {
  10830. CLEAR_BIT(EXTI->EMR1, exti_line);
  10831. 8004dde: 4015 andeq r5, r2
  10832. }
  10833. /* Configure EXTI interrupt mode */
  10834. if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
  10835. 8004de0: 07db lsls r3, r3, #31
  10836. CLEAR_BIT(EXTI->EMR1, exti_line);
  10837. 8004de2: f8c0 5084 str.w r5, [r0, #132] @ 0x84
  10838. if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
  10839. 8004de6: d51f bpl.n 8004e28 <HAL_COMP_Init+0x104>
  10840. {
  10841. SET_BIT(EXTI->IMR1, exti_line);
  10842. 8004de8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
  10843. 8004dec: f8d2 3080 ldr.w r3, [r2, #128] @ 0x80
  10844. 8004df0: 430b orrs r3, r1
  10845. 8004df2: f8c2 3080 str.w r3, [r2, #128] @ 0x80
  10846. 8004df6: e00e b.n 8004e16 <HAL_COMP_Init+0xf2>
  10847. status = HAL_ERROR;
  10848. 8004df8: 2001 movs r0, #1
  10849. }
  10850. }
  10851. return status;
  10852. }
  10853. 8004dfa: b003 add sp, #12
  10854. 8004dfc: bd30 pop {r4, r5, pc}
  10855. CLEAR_BIT(EXTI->EMR1, exti_line);
  10856. 8004dfe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
  10857. 8004e02: f8d3 1084 ldr.w r1, [r3, #132] @ 0x84
  10858. 8004e06: 4011 ands r1, r2
  10859. 8004e08: f8c3 1084 str.w r1, [r3, #132] @ 0x84
  10860. CLEAR_BIT(EXTI->IMR1, exti_line);
  10861. 8004e0c: f8d3 1080 ldr.w r1, [r3, #128] @ 0x80
  10862. 8004e10: 400a ands r2, r1
  10863. 8004e12: f8c3 2080 str.w r2, [r3, #128] @ 0x80
  10864. if (hcomp->State == HAL_COMP_STATE_RESET)
  10865. 8004e16: f894 3025 ldrb.w r3, [r4, #37] @ 0x25
  10866. 8004e1a: b913 cbnz r3, 8004e22 <HAL_COMP_Init+0xfe>
  10867. hcomp->State = HAL_COMP_STATE_READY;
  10868. 8004e1c: 2301 movs r3, #1
  10869. 8004e1e: f884 3025 strb.w r3, [r4, #37] @ 0x25
  10870. HAL_StatusTypeDef status = HAL_OK;
  10871. 8004e22: 2000 movs r0, #0
  10872. }
  10873. 8004e24: b003 add sp, #12
  10874. 8004e26: bd30 pop {r4, r5, pc}
  10875. CLEAR_BIT(EXTI->IMR1, exti_line);
  10876. 8004e28: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
  10877. 8004e2c: f8d1 3080 ldr.w r3, [r1, #128] @ 0x80
  10878. 8004e30: 4013 ands r3, r2
  10879. 8004e32: f8c1 3080 str.w r3, [r1, #128] @ 0x80
  10880. 8004e36: e7ee b.n 8004e16 <HAL_COMP_Init+0xf2>
  10881. wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
  10882. 8004e38: 4b10 ldr r3, [pc, #64] @ (8004e7c <HAL_COMP_Init+0x158>)
  10883. 8004e3a: 4911 ldr r1, [pc, #68] @ (8004e80 <HAL_COMP_Init+0x15c>)
  10884. 8004e3c: 681b ldr r3, [r3, #0]
  10885. 8004e3e: 099b lsrs r3, r3, #6
  10886. 8004e40: fba1 1303 umull r1, r3, r1, r3
  10887. 8004e44: 099b lsrs r3, r3, #6
  10888. 8004e46: 3301 adds r3, #1
  10889. 8004e48: eb03 0383 add.w r3, r3, r3, lsl #2
  10890. 8004e4c: 009b lsls r3, r3, #2
  10891. 8004e4e: 9301 str r3, [sp, #4]
  10892. while(wait_loop_index != 0UL)
  10893. 8004e50: 9b01 ldr r3, [sp, #4]
  10894. 8004e52: 2b00 cmp r3, #0
  10895. 8004e54: d099 beq.n 8004d8a <HAL_COMP_Init+0x66>
  10896. wait_loop_index --;
  10897. 8004e56: 9b01 ldr r3, [sp, #4]
  10898. 8004e58: 3b01 subs r3, #1
  10899. 8004e5a: 9301 str r3, [sp, #4]
  10900. while(wait_loop_index != 0UL)
  10901. 8004e5c: 9b01 ldr r3, [sp, #4]
  10902. 8004e5e: 2b00 cmp r3, #0
  10903. 8004e60: d1f9 bne.n 8004e56 <HAL_COMP_Init+0x132>
  10904. 8004e62: e792 b.n 8004d8a <HAL_COMP_Init+0x66>
  10905. hcomp->Lock = HAL_UNLOCKED;
  10906. 8004e64: f880 1024 strb.w r1, [r0, #36] @ 0x24
  10907. COMP_CLEAR_ERRORCODE(hcomp);
  10908. 8004e68: 6281 str r1, [r0, #40] @ 0x28
  10909. HAL_COMP_MspInit(hcomp);
  10910. 8004e6a: f7fd fe5d bl 8002b28 <HAL_COMP_MspInit>
  10911. comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN);
  10912. 8004e6e: 6822 ldr r2, [r4, #0]
  10913. 8004e70: e76a b.n 8004d48 <HAL_COMP_Init+0x24>
  10914. 8004e72: bf00 nop
  10915. 8004e74: f0e8cce1 .word 0xf0e8cce1
  10916. 8004e78: 5800380c .word 0x5800380c
  10917. 8004e7c: 24000038 .word 0x24000038
  10918. 8004e80: 053e2d63 .word 0x053e2d63
  10919. 08004e84 <HAL_COMP_Start>:
  10920. * @brief Start the comparator.
  10921. * @param hcomp COMP handle
  10922. * @retval HAL status
  10923. */
  10924. HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
  10925. {
  10926. 8004e84: b410 push {r4}
  10927. __IO uint32_t wait_loop_index = 0UL;
  10928. 8004e86: 2300 movs r3, #0
  10929. {
  10930. 8004e88: b083 sub sp, #12
  10931. __IO uint32_t wait_loop_index = 0UL;
  10932. 8004e8a: 9301 str r3, [sp, #4]
  10933. HAL_StatusTypeDef status = HAL_OK;
  10934. /* Check the COMP handle allocation and lock status */
  10935. if(hcomp == NULL)
  10936. 8004e8c: b138 cbz r0, 8004e9e <HAL_COMP_Start+0x1a>
  10937. {
  10938. status = HAL_ERROR;
  10939. }
  10940. else if(__HAL_COMP_IS_LOCKED(hcomp))
  10941. 8004e8e: 6803 ldr r3, [r0, #0]
  10942. 8004e90: 681a ldr r2, [r3, #0]
  10943. 8004e92: 2a00 cmp r2, #0
  10944. 8004e94: db03 blt.n 8004e9e <HAL_COMP_Start+0x1a>
  10945. else
  10946. {
  10947. /* Check the parameter */
  10948. assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
  10949. if(hcomp->State == HAL_COMP_STATE_READY)
  10950. 8004e96: f890 2025 ldrb.w r2, [r0, #37] @ 0x25
  10951. 8004e9a: 2a01 cmp r2, #1
  10952. 8004e9c: d004 beq.n 8004ea8 <HAL_COMP_Start+0x24>
  10953. status = HAL_ERROR;
  10954. 8004e9e: 2001 movs r0, #1
  10955. status = HAL_ERROR;
  10956. }
  10957. }
  10958. return status;
  10959. }
  10960. 8004ea0: b003 add sp, #12
  10961. 8004ea2: f85d 4b04 ldr.w r4, [sp], #4
  10962. 8004ea6: 4770 bx lr
  10963. SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
  10964. 8004ea8: 681a ldr r2, [r3, #0]
  10965. hcomp->State = HAL_COMP_STATE_BUSY;
  10966. 8004eaa: f04f 0c02 mov.w ip, #2
  10967. wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
  10968. 8004eae: 4c0e ldr r4, [pc, #56] @ (8004ee8 <HAL_COMP_Start+0x64>)
  10969. SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
  10970. 8004eb0: f042 0201 orr.w r2, r2, #1
  10971. wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
  10972. 8004eb4: 490d ldr r1, [pc, #52] @ (8004eec <HAL_COMP_Start+0x68>)
  10973. SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
  10974. 8004eb6: 601a str r2, [r3, #0]
  10975. wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
  10976. 8004eb8: 6823 ldr r3, [r4, #0]
  10977. hcomp->State = HAL_COMP_STATE_BUSY;
  10978. 8004eba: f880 c025 strb.w ip, [r0, #37] @ 0x25
  10979. wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
  10980. 8004ebe: 099b lsrs r3, r3, #6
  10981. 8004ec0: fba1 1303 umull r1, r3, r1, r3
  10982. 8004ec4: 099b lsrs r3, r3, #6
  10983. 8004ec6: 3301 adds r3, #1
  10984. 8004ec8: 00db lsls r3, r3, #3
  10985. 8004eca: 9301 str r3, [sp, #4]
  10986. while(wait_loop_index != 0UL)
  10987. 8004ecc: 9b01 ldr r3, [sp, #4]
  10988. 8004ece: b12b cbz r3, 8004edc <HAL_COMP_Start+0x58>
  10989. wait_loop_index--;
  10990. 8004ed0: 9b01 ldr r3, [sp, #4]
  10991. 8004ed2: 3b01 subs r3, #1
  10992. 8004ed4: 9301 str r3, [sp, #4]
  10993. while(wait_loop_index != 0UL)
  10994. 8004ed6: 9b01 ldr r3, [sp, #4]
  10995. 8004ed8: 2b00 cmp r3, #0
  10996. 8004eda: d1f9 bne.n 8004ed0 <HAL_COMP_Start+0x4c>
  10997. HAL_StatusTypeDef status = HAL_OK;
  10998. 8004edc: 2000 movs r0, #0
  10999. }
  11000. 8004ede: b003 add sp, #12
  11001. 8004ee0: f85d 4b04 ldr.w r4, [sp], #4
  11002. 8004ee4: 4770 bx lr
  11003. 8004ee6: bf00 nop
  11004. 8004ee8: 24000038 .word 0x24000038
  11005. 8004eec: 053e2d63 .word 0x053e2d63
  11006. 08004ef0 <HAL_COMP_GetOutputLevel>:
  11007. uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
  11008. {
  11009. /* Check the parameter */
  11010. assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
  11011. if (hcomp->Instance == COMP1)
  11012. 8004ef0: 4b06 ldr r3, [pc, #24] @ (8004f0c <HAL_COMP_GetOutputLevel+0x1c>)
  11013. 8004ef2: 6802 ldr r2, [r0, #0]
  11014. 8004ef4: 429a cmp r2, r3
  11015. 8004ef6: d004 beq.n 8004f02 <HAL_COMP_GetOutputLevel+0x12>
  11016. {
  11017. return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL));
  11018. }
  11019. else
  11020. {
  11021. return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1UL);
  11022. 8004ef8: 4b05 ldr r3, [pc, #20] @ (8004f10 <HAL_COMP_GetOutputLevel+0x20>)
  11023. 8004efa: 6818 ldr r0, [r3, #0]
  11024. 8004efc: f3c0 0040 ubfx r0, r0, #1, #1
  11025. }
  11026. }
  11027. 8004f00: 4770 bx lr
  11028. return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL));
  11029. 8004f02: f853 0c0c ldr.w r0, [r3, #-12]
  11030. 8004f06: f000 0001 and.w r0, r0, #1
  11031. 8004f0a: 4770 bx lr
  11032. 8004f0c: 5800380c .word 0x5800380c
  11033. 8004f10: 58003800 .word 0x58003800
  11034. 08004f14 <HAL_NVIC_SetPriorityGrouping>:
  11035. reg_value = SCB->AIRCR; /* read old register configuration */
  11036. 8004f14: 4906 ldr r1, [pc, #24] @ (8004f30 <HAL_NVIC_SetPriorityGrouping+0x1c>)
  11037. reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
  11038. 8004f16: f64f 0cff movw ip, #63743 @ 0xf8ff
  11039. (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
  11040. 8004f1a: 0200 lsls r0, r0, #8
  11041. reg_value = (reg_value |
  11042. 8004f1c: 4b05 ldr r3, [pc, #20] @ (8004f34 <HAL_NVIC_SetPriorityGrouping+0x20>)
  11043. reg_value = SCB->AIRCR; /* read old register configuration */
  11044. 8004f1e: 68ca ldr r2, [r1, #12]
  11045. (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
  11046. 8004f20: f400 60e0 and.w r0, r0, #1792 @ 0x700
  11047. reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
  11048. 8004f24: ea02 020c and.w r2, r2, ip
  11049. ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  11050. 8004f28: 4310 orrs r0, r2
  11051. reg_value = (reg_value |
  11052. 8004f2a: 4303 orrs r3, r0
  11053. SCB->AIRCR = reg_value;
  11054. 8004f2c: 60cb str r3, [r1, #12]
  11055. /* Check the parameters */
  11056. assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  11057. /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  11058. NVIC_SetPriorityGrouping(PriorityGroup);
  11059. }
  11060. 8004f2e: 4770 bx lr
  11061. 8004f30: e000ed00 .word 0xe000ed00
  11062. 8004f34: 05fa0000 .word 0x05fa0000
  11063. 08004f38 <HAL_NVIC_SetPriority>:
  11064. return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
  11065. 8004f38: 4b1a ldr r3, [pc, #104] @ (8004fa4 <HAL_NVIC_SetPriority+0x6c>)
  11066. 8004f3a: 68db ldr r3, [r3, #12]
  11067. 8004f3c: f3c3 2302 ubfx r3, r3, #8, #3
  11068. * This parameter can be a value between 0 and 15
  11069. * A lower priority value indicates a higher priority.
  11070. * @retval None
  11071. */
  11072. void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
  11073. {
  11074. 8004f40: b500 push {lr}
  11075. PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  11076. 8004f42: f1c3 0e07 rsb lr, r3, #7
  11077. SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  11078. 8004f46: f103 0c04 add.w ip, r3, #4
  11079. PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  11080. 8004f4a: f1be 0f04 cmp.w lr, #4
  11081. 8004f4e: bf28 it cs
  11082. 8004f50: f04f 0e04 movcs.w lr, #4
  11083. SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  11084. 8004f54: f1bc 0f06 cmp.w ip, #6
  11085. 8004f58: d91a bls.n 8004f90 <HAL_NVIC_SetPriority+0x58>
  11086. 8004f5a: f1a3 0c03 sub.w ip, r3, #3
  11087. ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
  11088. 8004f5e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
  11089. 8004f62: fa03 f30c lsl.w r3, r3, ip
  11090. 8004f66: ea22 0203 bic.w r2, r2, r3
  11091. ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
  11092. 8004f6a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
  11093. if ((int32_t)(IRQn) >= 0)
  11094. 8004f6e: 2800 cmp r0, #0
  11095. ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
  11096. 8004f70: fa03 f30e lsl.w r3, r3, lr
  11097. 8004f74: ea21 0303 bic.w r3, r1, r3
  11098. 8004f78: fa03 f30c lsl.w r3, r3, ip
  11099. 8004f7c: ea43 0302 orr.w r3, r3, r2
  11100. NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  11101. 8004f80: ea4f 1303 mov.w r3, r3, lsl #4
  11102. 8004f84: b2db uxtb r3, r3
  11103. if ((int32_t)(IRQn) >= 0)
  11104. 8004f86: db06 blt.n 8004f96 <HAL_NVIC_SetPriority+0x5e>
  11105. NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  11106. 8004f88: 4a07 ldr r2, [pc, #28] @ (8004fa8 <HAL_NVIC_SetPriority+0x70>)
  11107. 8004f8a: 5413 strb r3, [r2, r0]
  11108. assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  11109. prioritygroup = NVIC_GetPriorityGrouping();
  11110. NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
  11111. }
  11112. 8004f8c: f85d fb04 ldr.w pc, [sp], #4
  11113. 8004f90: 2200 movs r2, #0
  11114. SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  11115. 8004f92: 4694 mov ip, r2
  11116. 8004f94: e7e9 b.n 8004f6a <HAL_NVIC_SetPriority+0x32>
  11117. SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  11118. 8004f96: f000 000f and.w r0, r0, #15
  11119. 8004f9a: 4a04 ldr r2, [pc, #16] @ (8004fac <HAL_NVIC_SetPriority+0x74>)
  11120. 8004f9c: 5413 strb r3, [r2, r0]
  11121. 8004f9e: f85d fb04 ldr.w pc, [sp], #4
  11122. 8004fa2: bf00 nop
  11123. 8004fa4: e000ed00 .word 0xe000ed00
  11124. 8004fa8: e000e400 .word 0xe000e400
  11125. 8004fac: e000ed14 .word 0xe000ed14
  11126. 08004fb0 <HAL_NVIC_EnableIRQ>:
  11127. if ((int32_t)(IRQn) >= 0)
  11128. 8004fb0: 2800 cmp r0, #0
  11129. 8004fb2: db07 blt.n 8004fc4 <HAL_NVIC_EnableIRQ+0x14>
  11130. NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  11131. 8004fb4: 2301 movs r3, #1
  11132. 8004fb6: f000 011f and.w r1, r0, #31
  11133. 8004fba: 4a03 ldr r2, [pc, #12] @ (8004fc8 <HAL_NVIC_EnableIRQ+0x18>)
  11134. 8004fbc: 0940 lsrs r0, r0, #5
  11135. 8004fbe: 408b lsls r3, r1
  11136. 8004fc0: f842 3020 str.w r3, [r2, r0, lsl #2]
  11137. /* Check the parameters */
  11138. assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  11139. /* Enable interrupt */
  11140. NVIC_EnableIRQ(IRQn);
  11141. }
  11142. 8004fc4: 4770 bx lr
  11143. 8004fc6: bf00 nop
  11144. 8004fc8: e000e100 .word 0xe000e100
  11145. 08004fcc <HAL_MPU_Disable>:
  11146. __ASM volatile ("dmb 0xF":::"memory");
  11147. 8004fcc: f3bf 8f5f dmb sy
  11148. {
  11149. /* Make sure outstanding transfers are done */
  11150. __DMB();
  11151. /* Disable fault exceptions */
  11152. SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
  11153. 8004fd0: 4b04 ldr r3, [pc, #16] @ (8004fe4 <HAL_MPU_Disable+0x18>)
  11154. /* Disable the MPU and clear the control register*/
  11155. MPU->CTRL = 0;
  11156. 8004fd2: 2100 movs r1, #0
  11157. SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
  11158. 8004fd4: 6a5a ldr r2, [r3, #36] @ 0x24
  11159. 8004fd6: f422 3280 bic.w r2, r2, #65536 @ 0x10000
  11160. 8004fda: 625a str r2, [r3, #36] @ 0x24
  11161. MPU->CTRL = 0;
  11162. 8004fdc: f8c3 1094 str.w r1, [r3, #148] @ 0x94
  11163. }
  11164. 8004fe0: 4770 bx lr
  11165. 8004fe2: bf00 nop
  11166. 8004fe4: e000ed00 .word 0xe000ed00
  11167. 08004fe8 <HAL_MPU_Enable>:
  11168. * @retval None
  11169. */
  11170. void HAL_MPU_Enable(uint32_t MPU_Control)
  11171. {
  11172. /* Enable the MPU */
  11173. MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
  11174. 8004fe8: 4b06 ldr r3, [pc, #24] @ (8005004 <HAL_MPU_Enable+0x1c>)
  11175. 8004fea: f040 0001 orr.w r0, r0, #1
  11176. 8004fee: f8c3 0094 str.w r0, [r3, #148] @ 0x94
  11177. /* Enable fault exceptions */
  11178. SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
  11179. 8004ff2: 6a5a ldr r2, [r3, #36] @ 0x24
  11180. 8004ff4: f442 3280 orr.w r2, r2, #65536 @ 0x10000
  11181. 8004ff8: 625a str r2, [r3, #36] @ 0x24
  11182. __ASM volatile ("dsb 0xF":::"memory");
  11183. 8004ffa: f3bf 8f4f dsb sy
  11184. __ASM volatile ("isb 0xF":::"memory");
  11185. 8004ffe: f3bf 8f6f isb sy
  11186. /* Ensure MPU setting take effects */
  11187. __DSB();
  11188. __ISB();
  11189. }
  11190. 8005002: 4770 bx lr
  11191. 8005004: e000ed00 .word 0xe000ed00
  11192. 08005008 <HAL_MPU_ConfigRegion>:
  11193. assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
  11194. assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
  11195. assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
  11196. /* Set the Region number */
  11197. MPU->RNR = MPU_Init->Number;
  11198. 8005008: 4a16 ldr r2, [pc, #88] @ (8005064 <HAL_MPU_ConfigRegion+0x5c>)
  11199. 800500a: 7843 ldrb r3, [r0, #1]
  11200. 800500c: f8c2 3098 str.w r3, [r2, #152] @ 0x98
  11201. /* Disable the Region */
  11202. CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
  11203. 8005010: f8d2 30a0 ldr.w r3, [r2, #160] @ 0xa0
  11204. 8005014: f023 0301 bic.w r3, r3, #1
  11205. 8005018: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0
  11206. /* Apply configuration */
  11207. MPU->RBAR = MPU_Init->BaseAddress;
  11208. 800501c: 6843 ldr r3, [r0, #4]
  11209. 800501e: f8c2 309c str.w r3, [r2, #156] @ 0x9c
  11210. MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
  11211. ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
  11212. 8005022: 7ac3 ldrb r3, [r0, #11]
  11213. MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
  11214. 8005024: f890 c00c ldrb.w ip, [r0, #12]
  11215. ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
  11216. 8005028: 061b lsls r3, r3, #24
  11217. ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
  11218. ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
  11219. ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
  11220. ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
  11221. ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
  11222. ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
  11223. 800502a: 7801 ldrb r1, [r0, #0]
  11224. MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
  11225. 800502c: ea43 730c orr.w r3, r3, ip, lsl #28
  11226. ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
  11227. 8005030: f890 c00a ldrb.w ip, [r0, #10]
  11228. ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
  11229. 8005034: 430b orrs r3, r1
  11230. ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
  11231. 8005036: 7b41 ldrb r1, [r0, #13]
  11232. ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
  11233. 8005038: ea43 43cc orr.w r3, r3, ip, lsl #19
  11234. ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
  11235. 800503c: f890 c00e ldrb.w ip, [r0, #14]
  11236. ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
  11237. 8005040: ea43 4381 orr.w r3, r3, r1, lsl #18
  11238. ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
  11239. 8005044: 7bc1 ldrb r1, [r0, #15]
  11240. ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
  11241. 8005046: ea43 434c orr.w r3, r3, ip, lsl #17
  11242. ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
  11243. 800504a: f890 c009 ldrb.w ip, [r0, #9]
  11244. ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
  11245. 800504e: ea43 4301 orr.w r3, r3, r1, lsl #16
  11246. 8005052: 7a01 ldrb r1, [r0, #8]
  11247. 8005054: ea43 230c orr.w r3, r3, ip, lsl #8
  11248. 8005058: ea43 0341 orr.w r3, r3, r1, lsl #1
  11249. MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
  11250. 800505c: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0
  11251. }
  11252. 8005060: 4770 bx lr
  11253. 8005062: bf00 nop
  11254. 8005064: e000ed00 .word 0xe000ed00
  11255. 08005068 <CRC_Handle_8>:
  11256. * @param pBuffer pointer to the input data buffer
  11257. * @param BufferLength input data buffer length
  11258. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
  11259. */
  11260. static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
  11261. {
  11262. 8005068: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  11263. __IO uint16_t *pReg;
  11264. /* Processing time optimization: 4 bytes are entered in a row with a single word write,
  11265. * last bytes must be carefully fed to the CRC calculator to ensure a correct type
  11266. * handling by the peripheral */
  11267. for (i = 0U; i < (BufferLength / 4U); i++)
  11268. 800506c: 0897 lsrs r7, r2, #2
  11269. /* last bytes specific handling */
  11270. if ((BufferLength % 4U) != 0U)
  11271. {
  11272. if ((BufferLength % 4U) == 1U)
  11273. {
  11274. *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
  11275. 800506e: 6805 ldr r5, [r0, #0]
  11276. for (i = 0U; i < (BufferLength / 4U); i++)
  11277. 8005070: d016 beq.n 80050a0 <CRC_Handle_8+0x38>
  11278. 8005072: 468c mov ip, r1
  11279. 8005074: eb01 0687 add.w r6, r1, r7, lsl #2
  11280. ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
  11281. 8005078: f89c 3001 ldrb.w r3, [ip, #1]
  11282. for (i = 0U; i < (BufferLength / 4U); i++)
  11283. 800507c: f10c 0c04 add.w ip, ip, #4
  11284. hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
  11285. 8005080: f81c 8c04 ldrb.w r8, [ip, #-4]
  11286. ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
  11287. 8005084: 041b lsls r3, r3, #16
  11288. (uint32_t)pBuffer[(4U * i) + 3U];
  11289. 8005086: f81c 4c01 ldrb.w r4, [ip, #-1]
  11290. ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
  11291. 800508a: f81c ec02 ldrb.w lr, [ip, #-2]
  11292. for (i = 0U; i < (BufferLength / 4U); i++)
  11293. 800508e: 45b4 cmp ip, r6
  11294. ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
  11295. 8005090: ea43 6308 orr.w r3, r3, r8, lsl #24
  11296. 8005094: ea43 0304 orr.w r3, r3, r4
  11297. 8005098: ea43 230e orr.w r3, r3, lr, lsl #8
  11298. hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
  11299. 800509c: 602b str r3, [r5, #0]
  11300. for (i = 0U; i < (BufferLength / 4U); i++)
  11301. 800509e: d1eb bne.n 8005078 <CRC_Handle_8+0x10>
  11302. if ((BufferLength % 4U) != 0U)
  11303. 80050a0: f012 0203 ands.w r2, r2, #3
  11304. 80050a4: d00c beq.n 80050c0 <CRC_Handle_8+0x58>
  11305. if ((BufferLength % 4U) == 1U)
  11306. 80050a6: 2a01 cmp r2, #1
  11307. *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
  11308. 80050a8: ea4f 0387 mov.w r3, r7, lsl #2
  11309. 80050ac: f811 4027 ldrb.w r4, [r1, r7, lsl #2]
  11310. if ((BufferLength % 4U) == 1U)
  11311. 80050b0: d009 beq.n 80050c6 <CRC_Handle_8+0x5e>
  11312. pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
  11313. *pReg = data;
  11314. }
  11315. if ((BufferLength % 4U) == 3U)
  11316. {
  11317. data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
  11318. 80050b2: 4419 add r1, r3
  11319. if ((BufferLength % 4U) == 2U)
  11320. 80050b4: 2a02 cmp r2, #2
  11321. data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
  11322. 80050b6: 784b ldrb r3, [r1, #1]
  11323. 80050b8: ea43 2304 orr.w r3, r3, r4, lsl #8
  11324. *pReg = data;
  11325. 80050bc: 802b strh r3, [r5, #0]
  11326. if ((BufferLength % 4U) == 2U)
  11327. 80050be: d107 bne.n 80050d0 <CRC_Handle_8+0x68>
  11328. *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
  11329. }
  11330. }
  11331. /* Return the CRC computed value */
  11332. return hcrc->Instance->DR;
  11333. 80050c0: 6828 ldr r0, [r5, #0]
  11334. }
  11335. 80050c2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  11336. *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
  11337. 80050c6: 702c strb r4, [r5, #0]
  11338. return hcrc->Instance->DR;
  11339. 80050c8: 6805 ldr r5, [r0, #0]
  11340. 80050ca: 6828 ldr r0, [r5, #0]
  11341. }
  11342. 80050cc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  11343. *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
  11344. 80050d0: 788b ldrb r3, [r1, #2]
  11345. 80050d2: 702b strb r3, [r5, #0]
  11346. return hcrc->Instance->DR;
  11347. 80050d4: 6805 ldr r5, [r0, #0]
  11348. 80050d6: 6828 ldr r0, [r5, #0]
  11349. }
  11350. 80050d8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  11351. 080050dc <HAL_CRC_Init>:
  11352. if (hcrc == NULL)
  11353. 80050dc: 2800 cmp r0, #0
  11354. 80050de: d036 beq.n 800514e <HAL_CRC_Init+0x72>
  11355. {
  11356. 80050e0: b510 push {r4, lr}
  11357. if (hcrc->State == HAL_CRC_STATE_RESET)
  11358. 80050e2: 7f43 ldrb r3, [r0, #29]
  11359. 80050e4: 4604 mov r4, r0
  11360. 80050e6: f003 02ff and.w r2, r3, #255 @ 0xff
  11361. 80050ea: b363 cbz r3, 8005146 <HAL_CRC_Init+0x6a>
  11362. hcrc->State = HAL_CRC_STATE_BUSY;
  11363. 80050ec: 2202 movs r2, #2
  11364. if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
  11365. 80050ee: 7923 ldrb r3, [r4, #4]
  11366. hcrc->State = HAL_CRC_STATE_BUSY;
  11367. 80050f0: 7762 strb r2, [r4, #29]
  11368. if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
  11369. 80050f2: b9f3 cbnz r3, 8005132 <HAL_CRC_Init+0x56>
  11370. WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
  11371. 80050f4: 6823 ldr r3, [r4, #0]
  11372. 80050f6: 4a17 ldr r2, [pc, #92] @ (8005154 <HAL_CRC_Init+0x78>)
  11373. 80050f8: 615a str r2, [r3, #20]
  11374. MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
  11375. 80050fa: 689a ldr r2, [r3, #8]
  11376. 80050fc: f022 0218 bic.w r2, r2, #24
  11377. 8005100: 609a str r2, [r3, #8]
  11378. if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
  11379. 8005102: 7962 ldrb r2, [r4, #5]
  11380. 8005104: b18a cbz r2, 800512a <HAL_CRC_Init+0x4e>
  11381. WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
  11382. 8005106: 6922 ldr r2, [r4, #16]
  11383. 8005108: 611a str r2, [r3, #16]
  11384. MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
  11385. 800510a: 689a ldr r2, [r3, #8]
  11386. MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
  11387. 800510c: e9d4 0105 ldrd r0, r1, [r4, #20]
  11388. MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
  11389. 8005110: f022 0260 bic.w r2, r2, #96 @ 0x60
  11390. 8005114: 4302 orrs r2, r0
  11391. return HAL_OK;
  11392. 8005116: 2000 movs r0, #0
  11393. MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
  11394. 8005118: 609a str r2, [r3, #8]
  11395. MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
  11396. 800511a: 689a ldr r2, [r3, #8]
  11397. 800511c: f022 0280 bic.w r2, r2, #128 @ 0x80
  11398. 8005120: 430a orrs r2, r1
  11399. hcrc->State = HAL_CRC_STATE_READY;
  11400. 8005122: 2101 movs r1, #1
  11401. MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
  11402. 8005124: 609a str r2, [r3, #8]
  11403. hcrc->State = HAL_CRC_STATE_READY;
  11404. 8005126: 7761 strb r1, [r4, #29]
  11405. }
  11406. 8005128: bd10 pop {r4, pc}
  11407. WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
  11408. 800512a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
  11409. 800512e: 611a str r2, [r3, #16]
  11410. 8005130: e7eb b.n 800510a <HAL_CRC_Init+0x2e>
  11411. if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
  11412. 8005132: e9d4 1202 ldrd r1, r2, [r4, #8]
  11413. 8005136: 4620 mov r0, r4
  11414. 8005138: f000 f84e bl 80051d8 <HAL_CRCEx_Polynomial_Set>
  11415. 800513c: b908 cbnz r0, 8005142 <HAL_CRC_Init+0x66>
  11416. WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
  11417. 800513e: 6823 ldr r3, [r4, #0]
  11418. 8005140: e7df b.n 8005102 <HAL_CRC_Init+0x26>
  11419. return HAL_ERROR;
  11420. 8005142: 2001 movs r0, #1
  11421. }
  11422. 8005144: bd10 pop {r4, pc}
  11423. hcrc->Lock = HAL_UNLOCKED;
  11424. 8005146: 7702 strb r2, [r0, #28]
  11425. HAL_CRC_MspInit(hcrc);
  11426. 8005148: f7fd fd2c bl 8002ba4 <HAL_CRC_MspInit>
  11427. 800514c: e7ce b.n 80050ec <HAL_CRC_Init+0x10>
  11428. return HAL_ERROR;
  11429. 800514e: 2001 movs r0, #1
  11430. }
  11431. 8005150: 4770 bx lr
  11432. 8005152: bf00 nop
  11433. 8005154: 04c11db7 .word 0x04c11db7
  11434. 08005158 <HAL_CRC_Calculate>:
  11435. {
  11436. 8005158: b5f8 push {r3, r4, r5, r6, r7, lr}
  11437. hcrc->State = HAL_CRC_STATE_BUSY;
  11438. 800515a: 2302 movs r3, #2
  11439. __HAL_CRC_DR_RESET(hcrc);
  11440. 800515c: 6805 ldr r5, [r0, #0]
  11441. {
  11442. 800515e: 4606 mov r6, r0
  11443. 8005160: 468c mov ip, r1
  11444. hcrc->State = HAL_CRC_STATE_BUSY;
  11445. 8005162: 7743 strb r3, [r0, #29]
  11446. {
  11447. 8005164: 4617 mov r7, r2
  11448. __HAL_CRC_DR_RESET(hcrc);
  11449. 8005166: 68ab ldr r3, [r5, #8]
  11450. 8005168: f043 0301 orr.w r3, r3, #1
  11451. 800516c: 60ab str r3, [r5, #8]
  11452. switch (hcrc->InputDataFormat)
  11453. 800516e: 6a03 ldr r3, [r0, #32]
  11454. 8005170: 2b02 cmp r3, #2
  11455. 8005172: d007 beq.n 8005184 <HAL_CRC_Calculate+0x2c>
  11456. 8005174: 2b03 cmp r3, #3
  11457. 8005176: d022 beq.n 80051be <HAL_CRC_Calculate+0x66>
  11458. 8005178: 2b01 cmp r3, #1
  11459. 800517a: d01b beq.n 80051b4 <HAL_CRC_Calculate+0x5c>
  11460. hcrc->State = HAL_CRC_STATE_READY;
  11461. 800517c: 2301 movs r3, #1
  11462. switch (hcrc->InputDataFormat)
  11463. 800517e: 2000 movs r0, #0
  11464. hcrc->State = HAL_CRC_STATE_READY;
  11465. 8005180: 7773 strb r3, [r6, #29]
  11466. }
  11467. 8005182: bdf8 pop {r3, r4, r5, r6, r7, pc}
  11468. __IO uint16_t *pReg;
  11469. /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
  11470. * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
  11471. * a correct type handling by the peripheral */
  11472. for (i = 0U; i < (BufferLength / 2U); i++)
  11473. 8005184: 0851 lsrs r1, r2, #1
  11474. 8005186: d00c beq.n 80051a2 <HAL_CRC_Calculate+0x4a>
  11475. 8005188: 2300 movs r3, #0
  11476. 800518a: f10c 0002 add.w r0, ip, #2
  11477. {
  11478. hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
  11479. 800518e: f83c 2023 ldrh.w r2, [ip, r3, lsl #2]
  11480. 8005192: f830 4023 ldrh.w r4, [r0, r3, lsl #2]
  11481. for (i = 0U; i < (BufferLength / 2U); i++)
  11482. 8005196: 3301 adds r3, #1
  11483. hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
  11484. 8005198: ea44 4402 orr.w r4, r4, r2, lsl #16
  11485. for (i = 0U; i < (BufferLength / 2U); i++)
  11486. 800519c: 428b cmp r3, r1
  11487. hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
  11488. 800519e: 602c str r4, [r5, #0]
  11489. for (i = 0U; i < (BufferLength / 2U); i++)
  11490. 80051a0: d1f5 bne.n 800518e <HAL_CRC_Calculate+0x36>
  11491. }
  11492. if ((BufferLength % 2U) != 0U)
  11493. 80051a2: 07fb lsls r3, r7, #31
  11494. 80051a4: d502 bpl.n 80051ac <HAL_CRC_Calculate+0x54>
  11495. {
  11496. pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
  11497. *pReg = pBuffer[2U * i];
  11498. 80051a6: f83c 3021 ldrh.w r3, [ip, r1, lsl #2]
  11499. 80051aa: 802b strh r3, [r5, #0]
  11500. }
  11501. /* Return the CRC computed value */
  11502. return hcrc->Instance->DR;
  11503. 80051ac: 6828 ldr r0, [r5, #0]
  11504. hcrc->State = HAL_CRC_STATE_READY;
  11505. 80051ae: 2301 movs r3, #1
  11506. 80051b0: 7773 strb r3, [r6, #29]
  11507. }
  11508. 80051b2: bdf8 pop {r3, r4, r5, r6, r7, pc}
  11509. temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
  11510. 80051b4: f7ff ff58 bl 8005068 <CRC_Handle_8>
  11511. hcrc->State = HAL_CRC_STATE_READY;
  11512. 80051b8: 2301 movs r3, #1
  11513. 80051ba: 7773 strb r3, [r6, #29]
  11514. }
  11515. 80051bc: bdf8 pop {r3, r4, r5, r6, r7, pc}
  11516. for (index = 0U; index < BufferLength; index++)
  11517. 80051be: 2a00 cmp r2, #0
  11518. 80051c0: d0f4 beq.n 80051ac <HAL_CRC_Calculate+0x54>
  11519. 80051c2: 3904 subs r1, #4
  11520. 80051c4: eb01 0782 add.w r7, r1, r2, lsl #2
  11521. hcrc->Instance->DR = pBuffer[index];
  11522. 80051c8: f851 3f04 ldr.w r3, [r1, #4]!
  11523. for (index = 0U; index < BufferLength; index++)
  11524. 80051cc: 42b9 cmp r1, r7
  11525. hcrc->Instance->DR = pBuffer[index];
  11526. 80051ce: 602b str r3, [r5, #0]
  11527. for (index = 0U; index < BufferLength; index++)
  11528. 80051d0: d1fa bne.n 80051c8 <HAL_CRC_Calculate+0x70>
  11529. return hcrc->Instance->DR;
  11530. 80051d2: 6828 ldr r0, [r5, #0]
  11531. break;
  11532. 80051d4: e7eb b.n 80051ae <HAL_CRC_Calculate+0x56>
  11533. 80051d6: bf00 nop
  11534. 080051d8 <HAL_CRCEx_Polynomial_Set>:
  11535. /* Check the parameters */
  11536. assert_param(IS_CRC_POL_LENGTH(PolyLength));
  11537. /* Ensure that the generating polynomial is odd */
  11538. if ((Pol & (uint32_t)(0x1U)) == 0U)
  11539. 80051d8: 07cb lsls r3, r1, #31
  11540. 80051da: d51a bpl.n 8005212 <HAL_CRCEx_Polynomial_Set+0x3a>
  11541. uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
  11542. 80051dc: 231f movs r3, #31
  11543. {
  11544. 80051de: b410 push {r4}
  11545. * definition. HAL_ERROR is reported if Pol degree is
  11546. * larger than that indicated by PolyLength.
  11547. * Look for MSB position: msb will contain the degree of
  11548. * the second to the largest polynomial member. E.g., for
  11549. * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
  11550. while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
  11551. 80051e0: 3b01 subs r3, #1
  11552. 80051e2: 1c5c adds r4, r3, #1
  11553. 80051e4: fa21 fc03 lsr.w ip, r1, r3
  11554. 80051e8: d015 beq.n 8005216 <HAL_CRCEx_Polynomial_Set+0x3e>
  11555. 80051ea: f01c 0f01 tst.w ip, #1
  11556. 80051ee: d0f7 beq.n 80051e0 <HAL_CRCEx_Polynomial_Set+0x8>
  11557. {
  11558. }
  11559. switch (PolyLength)
  11560. 80051f0: 2a18 cmp r2, #24
  11561. 80051f2: d811 bhi.n 8005218 <HAL_CRCEx_Polynomial_Set+0x40>
  11562. 80051f4: e8df f002 tbb [pc, r2]
  11563. 80051f8: 10101016 .word 0x10101016
  11564. 80051fc: 10101010 .word 0x10101010
  11565. 8005200: 10101024 .word 0x10101024
  11566. 8005204: 10101010 .word 0x10101010
  11567. 8005208: 10101021 .word 0x10101021
  11568. 800520c: 10101010 .word 0x10101010
  11569. 8005210: 14 .byte 0x14
  11570. 8005211: 00 .byte 0x00
  11571. 8005212: 2001 movs r0, #1
  11572. /* set generating polynomial size */
  11573. MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
  11574. }
  11575. /* Return function status */
  11576. return status;
  11577. }
  11578. 8005214: 4770 bx lr
  11579. switch (PolyLength)
  11580. 8005216: b12a cbz r2, 8005224 <HAL_CRCEx_Polynomial_Set+0x4c>
  11581. 8005218: 2001 movs r0, #1
  11582. }
  11583. 800521a: f85d 4b04 ldr.w r4, [sp], #4
  11584. 800521e: 4770 bx lr
  11585. if (msb >= HAL_CRC_LENGTH_7B)
  11586. 8005220: 2b06 cmp r3, #6
  11587. 8005222: d8f9 bhi.n 8005218 <HAL_CRCEx_Polynomial_Set+0x40>
  11588. WRITE_REG(hcrc->Instance->POL, Pol);
  11589. 8005224: 6804 ldr r4, [r0, #0]
  11590. MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
  11591. 8005226: 2000 movs r0, #0
  11592. WRITE_REG(hcrc->Instance->POL, Pol);
  11593. 8005228: 6161 str r1, [r4, #20]
  11594. MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
  11595. 800522a: 68a3 ldr r3, [r4, #8]
  11596. 800522c: f023 0318 bic.w r3, r3, #24
  11597. 8005230: 4313 orrs r3, r2
  11598. 8005232: 60a3 str r3, [r4, #8]
  11599. }
  11600. 8005234: f85d 4b04 ldr.w r4, [sp], #4
  11601. 8005238: 4770 bx lr
  11602. if (msb >= HAL_CRC_LENGTH_8B)
  11603. 800523a: 2b07 cmp r3, #7
  11604. 800523c: d9f2 bls.n 8005224 <HAL_CRCEx_Polynomial_Set+0x4c>
  11605. 800523e: e7eb b.n 8005218 <HAL_CRCEx_Polynomial_Set+0x40>
  11606. if (msb >= HAL_CRC_LENGTH_16B)
  11607. 8005240: 2b0f cmp r3, #15
  11608. 8005242: d9ef bls.n 8005224 <HAL_CRCEx_Polynomial_Set+0x4c>
  11609. 8005244: e7e8 b.n 8005218 <HAL_CRCEx_Polynomial_Set+0x40>
  11610. 8005246: bf00 nop
  11611. 08005248 <HAL_DAC_Init>:
  11612. * @retval HAL status
  11613. */
  11614. HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
  11615. {
  11616. /* Check the DAC peripheral handle */
  11617. if (hdac == NULL)
  11618. 8005248: b188 cbz r0, 800526e <HAL_DAC_Init+0x26>
  11619. {
  11620. 800524a: b510 push {r4, lr}
  11621. return HAL_ERROR;
  11622. }
  11623. /* Check the parameters */
  11624. assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
  11625. if (hdac->State == HAL_DAC_STATE_RESET)
  11626. 800524c: 7903 ldrb r3, [r0, #4]
  11627. 800524e: 4604 mov r4, r0
  11628. 8005250: f003 02ff and.w r2, r3, #255 @ 0xff
  11629. 8005254: b13b cbz r3, 8005266 <HAL_DAC_Init+0x1e>
  11630. /* Initialize the DAC state*/
  11631. hdac->State = HAL_DAC_STATE_BUSY;
  11632. /* Set DAC error code to none */
  11633. hdac->ErrorCode = HAL_DAC_ERROR_NONE;
  11634. 8005256: 2300 movs r3, #0
  11635. hdac->State = HAL_DAC_STATE_BUSY;
  11636. 8005258: 2102 movs r1, #2
  11637. /* Initialize the DAC state*/
  11638. hdac->State = HAL_DAC_STATE_READY;
  11639. 800525a: 2201 movs r2, #1
  11640. hdac->State = HAL_DAC_STATE_BUSY;
  11641. 800525c: 7121 strb r1, [r4, #4]
  11642. /* Return function status */
  11643. return HAL_OK;
  11644. 800525e: 4618 mov r0, r3
  11645. hdac->ErrorCode = HAL_DAC_ERROR_NONE;
  11646. 8005260: 6123 str r3, [r4, #16]
  11647. hdac->State = HAL_DAC_STATE_READY;
  11648. 8005262: 7122 strb r2, [r4, #4]
  11649. }
  11650. 8005264: bd10 pop {r4, pc}
  11651. hdac->Lock = HAL_UNLOCKED;
  11652. 8005266: 7142 strb r2, [r0, #5]
  11653. HAL_DAC_MspInit(hdac);
  11654. 8005268: f7fd fcb4 bl 8002bd4 <HAL_DAC_MspInit>
  11655. 800526c: e7f3 b.n 8005256 <HAL_DAC_Init+0xe>
  11656. return HAL_ERROR;
  11657. 800526e: 2001 movs r0, #1
  11658. }
  11659. 8005270: 4770 bx lr
  11660. 8005272: bf00 nop
  11661. 08005274 <HAL_DAC_Start>:
  11662. * @retval HAL status
  11663. */
  11664. HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
  11665. {
  11666. /* Check the DAC peripheral handle */
  11667. if (hdac == NULL)
  11668. 8005274: b388 cbz r0, 80052da <HAL_DAC_Start+0x66>
  11669. /* Check the parameters */
  11670. assert_param(IS_DAC_CHANNEL(Channel));
  11671. /* Process locked */
  11672. __HAL_LOCK(hdac);
  11673. 8005276: 7942 ldrb r2, [r0, #5]
  11674. 8005278: 4603 mov r3, r0
  11675. 800527a: 2a01 cmp r2, #1
  11676. 800527c: d02f beq.n 80052de <HAL_DAC_Start+0x6a>
  11677. /* Change DAC state */
  11678. hdac->State = HAL_DAC_STATE_BUSY;
  11679. /* Enable the Peripheral */
  11680. __HAL_DAC_ENABLE(hdac, Channel);
  11681. 800527e: 6800 ldr r0, [r0, #0]
  11682. hdac->State = HAL_DAC_STATE_BUSY;
  11683. 8005280: f04f 0c02 mov.w ip, #2
  11684. __HAL_DAC_ENABLE(hdac, Channel);
  11685. 8005284: 2201 movs r2, #1
  11686. {
  11687. 8005286: b510 push {r4, lr}
  11688. __HAL_DAC_ENABLE(hdac, Channel);
  11689. 8005288: f001 0e10 and.w lr, r1, #16
  11690. hdac->State = HAL_DAC_STATE_BUSY;
  11691. 800528c: f883 c004 strb.w ip, [r3, #4]
  11692. __HAL_DAC_ENABLE(hdac, Channel);
  11693. 8005290: 6804 ldr r4, [r0, #0]
  11694. 8005292: fa02 f20e lsl.w r2, r2, lr
  11695. 8005296: 4322 orrs r2, r4
  11696. 8005298: 6002 str r2, [r0, #0]
  11697. if (Channel == DAC_CHANNEL_1)
  11698. {
  11699. /* Check if software trigger enabled */
  11700. if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
  11701. 800529a: 6802 ldr r2, [r0, #0]
  11702. if (Channel == DAC_CHANNEL_1)
  11703. 800529c: b969 cbnz r1, 80052ba <HAL_DAC_Start+0x46>
  11704. if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
  11705. 800529e: f002 023e and.w r2, r2, #62 @ 0x3e
  11706. 80052a2: 4562 cmp r2, ip
  11707. 80052a4: d103 bne.n 80052ae <HAL_DAC_Start+0x3a>
  11708. {
  11709. /* Enable the selected DAC software conversion */
  11710. SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
  11711. 80052a6: 6842 ldr r2, [r0, #4]
  11712. 80052a8: f042 0201 orr.w r2, r2, #1
  11713. 80052ac: 6042 str r2, [r0, #4]
  11714. /* Change DAC state */
  11715. hdac->State = HAL_DAC_STATE_READY;
  11716. /* Process unlocked */
  11717. __HAL_UNLOCK(hdac);
  11718. 80052ae: 2200 movs r2, #0
  11719. hdac->State = HAL_DAC_STATE_READY;
  11720. 80052b0: 2101 movs r1, #1
  11721. /* Return function status */
  11722. return HAL_OK;
  11723. 80052b2: 4610 mov r0, r2
  11724. hdac->State = HAL_DAC_STATE_READY;
  11725. 80052b4: 7119 strb r1, [r3, #4]
  11726. __HAL_UNLOCK(hdac);
  11727. 80052b6: 715a strb r2, [r3, #5]
  11728. }
  11729. 80052b8: bd10 pop {r4, pc}
  11730. if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
  11731. 80052ba: fa0c fc0e lsl.w ip, ip, lr
  11732. 80052be: f402 1278 and.w r2, r2, #4063232 @ 0x3e0000
  11733. 80052c2: 4562 cmp r2, ip
  11734. 80052c4: d1f3 bne.n 80052ae <HAL_DAC_Start+0x3a>
  11735. SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
  11736. 80052c6: 6842 ldr r2, [r0, #4]
  11737. hdac->State = HAL_DAC_STATE_READY;
  11738. 80052c8: 2101 movs r1, #1
  11739. SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
  11740. 80052ca: f042 0202 orr.w r2, r2, #2
  11741. 80052ce: 6042 str r2, [r0, #4]
  11742. __HAL_UNLOCK(hdac);
  11743. 80052d0: 2200 movs r2, #0
  11744. hdac->State = HAL_DAC_STATE_READY;
  11745. 80052d2: 7119 strb r1, [r3, #4]
  11746. return HAL_OK;
  11747. 80052d4: 4610 mov r0, r2
  11748. __HAL_UNLOCK(hdac);
  11749. 80052d6: 715a strb r2, [r3, #5]
  11750. }
  11751. 80052d8: bd10 pop {r4, pc}
  11752. return HAL_ERROR;
  11753. 80052da: 2001 movs r0, #1
  11754. 80052dc: 4770 bx lr
  11755. __HAL_LOCK(hdac);
  11756. 80052de: 2002 movs r0, #2
  11757. }
  11758. 80052e0: 4770 bx lr
  11759. 80052e2: bf00 nop
  11760. 080052e4 <HAL_DAC_SetValue>:
  11761. * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
  11762. * @param Data Data to be loaded in the selected data holding register.
  11763. * @retval HAL status
  11764. */
  11765. HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
  11766. {
  11767. 80052e4: b410 push {r4}
  11768. __IO uint32_t tmp = 0UL;
  11769. 80052e6: 2400 movs r4, #0
  11770. {
  11771. 80052e8: b083 sub sp, #12
  11772. __IO uint32_t tmp = 0UL;
  11773. 80052ea: 9401 str r4, [sp, #4]
  11774. /* Check the DAC peripheral handle */
  11775. if (hdac == NULL)
  11776. 80052ec: b190 cbz r0, 8005314 <HAL_DAC_SetValue+0x30>
  11777. /* Check the parameters */
  11778. assert_param(IS_DAC_CHANNEL(Channel));
  11779. assert_param(IS_DAC_ALIGN(Alignment));
  11780. assert_param(IS_DAC_DATA(Data));
  11781. tmp = (uint32_t)hdac->Instance;
  11782. 80052ee: 6800 ldr r0, [r0, #0]
  11783. 80052f0: 9001 str r0, [sp, #4]
  11784. if (Channel == DAC_CHANNEL_1)
  11785. 80052f2: b151 cbz r1, 800530a <HAL_DAC_SetValue+0x26>
  11786. tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
  11787. }
  11788. else
  11789. {
  11790. tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
  11791. 80052f4: 9901 ldr r1, [sp, #4]
  11792. 80052f6: 3114 adds r1, #20
  11793. 80052f8: 440a add r2, r1
  11794. 80052fa: 9201 str r2, [sp, #4]
  11795. }
  11796. /* Set the DAC channel selected data holding register */
  11797. *(__IO uint32_t *) tmp = Data;
  11798. 80052fc: 9a01 ldr r2, [sp, #4]
  11799. /* Return function status */
  11800. return HAL_OK;
  11801. 80052fe: 2000 movs r0, #0
  11802. *(__IO uint32_t *) tmp = Data;
  11803. 8005300: 6013 str r3, [r2, #0]
  11804. }
  11805. 8005302: b003 add sp, #12
  11806. 8005304: f85d 4b04 ldr.w r4, [sp], #4
  11807. 8005308: 4770 bx lr
  11808. tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
  11809. 800530a: 9901 ldr r1, [sp, #4]
  11810. 800530c: 3108 adds r1, #8
  11811. 800530e: 440a add r2, r1
  11812. 8005310: 9201 str r2, [sp, #4]
  11813. 8005312: e7f3 b.n 80052fc <HAL_DAC_SetValue+0x18>
  11814. return HAL_ERROR;
  11815. 8005314: 2001 movs r0, #1
  11816. }
  11817. 8005316: b003 add sp, #12
  11818. 8005318: f85d 4b04 ldr.w r4, [sp], #4
  11819. 800531c: 4770 bx lr
  11820. 800531e: bf00 nop
  11821. 08005320 <HAL_DAC_DMAUnderrunCallbackCh1>:
  11822. * @brief DMA underrun DAC callback for channel1.
  11823. * @param hdac pointer to a DAC_HandleTypeDef structure that contains
  11824. * the configuration information for the specified DAC.
  11825. * @retval None
  11826. */
  11827. __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
  11828. 8005320: 4770 bx lr
  11829. 8005322: bf00 nop
  11830. 08005324 <HAL_DAC_IRQHandler>:
  11831. uint32_t itsource = hdac->Instance->CR;
  11832. 8005324: 6803 ldr r3, [r0, #0]
  11833. {
  11834. 8005326: b570 push {r4, r5, r6, lr}
  11835. uint32_t itsource = hdac->Instance->CR;
  11836. 8005328: 681d ldr r5, [r3, #0]
  11837. {
  11838. 800532a: 4604 mov r4, r0
  11839. uint32_t itflag = hdac->Instance->SR;
  11840. 800532c: 6b5e ldr r6, [r3, #52] @ 0x34
  11841. if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
  11842. 800532e: 04aa lsls r2, r5, #18
  11843. 8005330: d501 bpl.n 8005336 <HAL_DAC_IRQHandler+0x12>
  11844. if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
  11845. 8005332: 04b1 lsls r1, r6, #18
  11846. 8005334: d417 bmi.n 8005366 <HAL_DAC_IRQHandler+0x42>
  11847. if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
  11848. 8005336: 00aa lsls r2, r5, #2
  11849. 8005338: d501 bpl.n 800533e <HAL_DAC_IRQHandler+0x1a>
  11850. if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
  11851. 800533a: 00b3 lsls r3, r6, #2
  11852. 800533c: d400 bmi.n 8005340 <HAL_DAC_IRQHandler+0x1c>
  11853. }
  11854. 800533e: bd70 pop {r4, r5, r6, pc}
  11855. hdac->State = HAL_DAC_STATE_ERROR;
  11856. 8005340: 2204 movs r2, #4
  11857. __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
  11858. 8005342: 6823 ldr r3, [r4, #0]
  11859. 8005344: f04f 5100 mov.w r1, #536870912 @ 0x20000000
  11860. HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
  11861. 8005348: 4620 mov r0, r4
  11862. hdac->State = HAL_DAC_STATE_ERROR;
  11863. 800534a: 7122 strb r2, [r4, #4]
  11864. SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
  11865. 800534c: 6922 ldr r2, [r4, #16]
  11866. 800534e: f042 0202 orr.w r2, r2, #2
  11867. 8005352: 6122 str r2, [r4, #16]
  11868. __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
  11869. 8005354: 6359 str r1, [r3, #52] @ 0x34
  11870. __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
  11871. 8005356: 681a ldr r2, [r3, #0]
  11872. 8005358: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000
  11873. }
  11874. 800535c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  11875. __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
  11876. 8005360: 601a str r2, [r3, #0]
  11877. HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
  11878. 8005362: f000 b8bb b.w 80054dc <HAL_DACEx_DMAUnderrunCallbackCh2>
  11879. hdac->State = HAL_DAC_STATE_ERROR;
  11880. 8005366: 2204 movs r2, #4
  11881. 8005368: 7102 strb r2, [r0, #4]
  11882. SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
  11883. 800536a: 6902 ldr r2, [r0, #16]
  11884. 800536c: f042 0201 orr.w r2, r2, #1
  11885. 8005370: 6102 str r2, [r0, #16]
  11886. __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
  11887. 8005372: f44f 5200 mov.w r2, #8192 @ 0x2000
  11888. 8005376: 635a str r2, [r3, #52] @ 0x34
  11889. __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
  11890. 8005378: 681a ldr r2, [r3, #0]
  11891. 800537a: f422 5280 bic.w r2, r2, #4096 @ 0x1000
  11892. 800537e: 601a str r2, [r3, #0]
  11893. HAL_DAC_DMAUnderrunCallbackCh1(hdac);
  11894. 8005380: f7ff ffce bl 8005320 <HAL_DAC_DMAUnderrunCallbackCh1>
  11895. 8005384: e7d7 b.n 8005336 <HAL_DAC_IRQHandler+0x12>
  11896. 8005386: bf00 nop
  11897. 08005388 <HAL_DAC_ConfigChannel>:
  11898. uint32_t tmpreg2;
  11899. uint32_t tickstart;
  11900. uint32_t connectOnChip;
  11901. /* Check the DAC peripheral handle and channel configuration struct */
  11902. if ((hdac == NULL) || (sConfig == NULL))
  11903. 8005388: 2800 cmp r0, #0
  11904. 800538a: f000 8086 beq.w 800549a <HAL_DAC_ConfigChannel+0x112>
  11905. {
  11906. 800538e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  11907. 8005392: 460d mov r5, r1
  11908. if ((hdac == NULL) || (sConfig == NULL))
  11909. 8005394: 2900 cmp r1, #0
  11910. 8005396: d04d beq.n 8005434 <HAL_DAC_ConfigChannel+0xac>
  11911. assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
  11912. }
  11913. assert_param(IS_DAC_CHANNEL(Channel));
  11914. /* Process locked */
  11915. __HAL_LOCK(hdac);
  11916. 8005398: 7943 ldrb r3, [r0, #5]
  11917. 800539a: 4604 mov r4, r0
  11918. if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
  11919. 800539c: 6809 ldr r1, [r1, #0]
  11920. __HAL_LOCK(hdac);
  11921. 800539e: 2b01 cmp r3, #1
  11922. 80053a0: d079 beq.n 8005496 <HAL_DAC_ConfigChannel+0x10e>
  11923. 80053a2: 2301 movs r3, #1
  11924. /* Change DAC state */
  11925. hdac->State = HAL_DAC_STATE_BUSY;
  11926. /* Sample and hold configuration */
  11927. if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
  11928. 80053a4: 2904 cmp r1, #4
  11929. 80053a6: 4616 mov r6, r2
  11930. __HAL_LOCK(hdac);
  11931. 80053a8: 7143 strb r3, [r0, #5]
  11932. hdac->State = HAL_DAC_STATE_BUSY;
  11933. 80053aa: f04f 0302 mov.w r3, #2
  11934. 80053ae: 7103 strb r3, [r0, #4]
  11935. if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
  11936. 80053b0: d043 beq.n 800543a <HAL_DAC_ConfigChannel+0xb2>
  11937. hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
  11938. }
  11939. /* HoldTime */
  11940. MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
  11941. 80053b2: f002 0210 and.w r2, r2, #16
  11942. if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
  11943. /* USER TRIMMING */
  11944. {
  11945. /* Get the DAC CCR value */
  11946. tmpreg1 = hdac->Instance->CCR;
  11947. 80053b6: 6803 ldr r3, [r0, #0]
  11948. if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
  11949. 80053b8: 6928 ldr r0, [r5, #16]
  11950. 80053ba: 2801 cmp r0, #1
  11951. 80053bc: d108 bne.n 80053d0 <HAL_DAC_ConfigChannel+0x48>
  11952. /* Clear trimming value */
  11953. tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
  11954. 80053be: 201f movs r0, #31
  11955. tmpreg1 = hdac->Instance->CCR;
  11956. 80053c0: 6b9e ldr r6, [r3, #56] @ 0x38
  11957. tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
  11958. 80053c2: 4090 lsls r0, r2
  11959. 80053c4: ea26 0600 bic.w r6, r6, r0
  11960. /* Configure for the selected trimming offset */
  11961. tmpreg2 = sConfig->DAC_TrimmingValue;
  11962. /* Calculate CCR register value depending on DAC_Channel */
  11963. tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
  11964. 80053c8: 6968 ldr r0, [r5, #20]
  11965. 80053ca: 4090 lsls r0, r2
  11966. 80053cc: 4330 orrs r0, r6
  11967. /* Write to DAC CCR */
  11968. hdac->Instance->CCR = tmpreg1;
  11969. 80053ce: 6398 str r0, [r3, #56] @ 0x38
  11970. /* SW Nothing has nothing to do */
  11971. /* Get the DAC MCR value */
  11972. tmpreg1 = hdac->Instance->MCR;
  11973. /* Clear DAC_MCR_MODEx bits */
  11974. tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
  11975. 80053d0: 2007 movs r0, #7
  11976. tmpreg1 = hdac->Instance->MCR;
  11977. 80053d2: 6bde ldr r6, [r3, #60] @ 0x3c
  11978. tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
  11979. 80053d4: 4090 lsls r0, r2
  11980. 80053d6: ea26 0600 bic.w r6, r6, r0
  11981. {
  11982. connectOnChip = DAC_MCR_MODE1_0;
  11983. }
  11984. else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
  11985. {
  11986. if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
  11987. 80053da: e9d5 7002 ldrd r7, r0, [r5, #8]
  11988. if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
  11989. 80053de: 2801 cmp r0, #1
  11990. 80053e0: d055 beq.n 800548e <HAL_DAC_ConfigChannel+0x106>
  11991. else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
  11992. 80053e2: 2802 cmp r0, #2
  11993. 80053e4: d055 beq.n 8005492 <HAL_DAC_ConfigChannel+0x10a>
  11994. if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
  11995. 80053e6: fab7 f087 clz r0, r7
  11996. 80053ea: 0940 lsrs r0, r0, #5
  11997. else
  11998. {
  11999. connectOnChip = 0x00000000UL;
  12000. }
  12001. }
  12002. tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
  12003. 80053ec: 4339 orrs r1, r7
  12004. 80053ee: 4301 orrs r1, r0
  12005. tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
  12006. /* Configure for the selected DAC channel: trigger */
  12007. /* Set TSELx and TENx bits according to DAC_Trigger value */
  12008. tmpreg2 = sConfig->DAC_Trigger;
  12009. /* Calculate CR register value depending on DAC_Channel */
  12010. tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
  12011. 80053f0: 6868 ldr r0, [r5, #4]
  12012. CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
  12013. 80053f2: f44f 4580 mov.w r5, #16384 @ 0x4000
  12014. tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
  12015. 80053f6: 4091 lsls r1, r2
  12016. tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
  12017. 80053f8: 4090 lsls r0, r2
  12018. CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
  12019. 80053fa: 4095 lsls r5, r2
  12020. tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
  12021. 80053fc: 4331 orrs r1, r6
  12022. hdac->Instance->CR = tmpreg1;
  12023. /* Disable wave generation */
  12024. CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
  12025. /* Change DAC state */
  12026. hdac->State = HAL_DAC_STATE_READY;
  12027. 80053fe: 2601 movs r6, #1
  12028. hdac->Instance->MCR = tmpreg1;
  12029. 8005400: 63d9 str r1, [r3, #60] @ 0x3c
  12030. CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
  12031. 8005402: 6819 ldr r1, [r3, #0]
  12032. 8005404: ea21 0105 bic.w r1, r1, r5
  12033. tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
  12034. 8005408: f640 75fe movw r5, #4094 @ 0xffe
  12035. CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
  12036. 800540c: 6019 str r1, [r3, #0]
  12037. tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
  12038. 800540e: 4095 lsls r5, r2
  12039. tmpreg1 = hdac->Instance->CR;
  12040. 8005410: 6819 ldr r1, [r3, #0]
  12041. tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
  12042. 8005412: ea21 0105 bic.w r1, r1, r5
  12043. /* Process unlocked */
  12044. __HAL_UNLOCK(hdac);
  12045. 8005416: 2500 movs r5, #0
  12046. tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
  12047. 8005418: 4301 orrs r1, r0
  12048. CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
  12049. 800541a: 20c0 movs r0, #192 @ 0xc0
  12050. hdac->Instance->CR = tmpreg1;
  12051. 800541c: 6019 str r1, [r3, #0]
  12052. CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
  12053. 800541e: fa00 f102 lsl.w r1, r0, r2
  12054. 8005422: 681a ldr r2, [r3, #0]
  12055. /* Return function status */
  12056. return status;
  12057. 8005424: 4628 mov r0, r5
  12058. CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
  12059. 8005426: ea22 0201 bic.w r2, r2, r1
  12060. 800542a: 601a str r2, [r3, #0]
  12061. hdac->State = HAL_DAC_STATE_READY;
  12062. 800542c: 7126 strb r6, [r4, #4]
  12063. __HAL_UNLOCK(hdac);
  12064. 800542e: 7165 strb r5, [r4, #5]
  12065. }
  12066. 8005430: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  12067. return HAL_ERROR;
  12068. 8005434: 2001 movs r0, #1
  12069. }
  12070. 8005436: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  12071. tickstart = HAL_GetTick();
  12072. 800543a: f7fe fdc9 bl 8003fd0 <HAL_GetTick>
  12073. while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
  12074. 800543e: 6823 ldr r3, [r4, #0]
  12075. tickstart = HAL_GetTick();
  12076. 8005440: 4607 mov r7, r0
  12077. if (Channel == DAC_CHANNEL_1)
  12078. 8005442: b9be cbnz r6, 8005474 <HAL_DAC_ConfigChannel+0xec>
  12079. while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
  12080. 8005444: f8df 8090 ldr.w r8, [pc, #144] @ 80054d8 <HAL_DAC_ConfigChannel+0x150>
  12081. 8005448: 6b5a ldr r2, [r3, #52] @ 0x34
  12082. 800544a: ea12 0f08 tst.w r2, r8
  12083. 800544e: d026 beq.n 800549e <HAL_DAC_ConfigChannel+0x116>
  12084. if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
  12085. 8005450: f7fe fdbe bl 8003fd0 <HAL_GetTick>
  12086. 8005454: 1bc0 subs r0, r0, r7
  12087. if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
  12088. 8005456: 6823 ldr r3, [r4, #0]
  12089. if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
  12090. 8005458: 2801 cmp r0, #1
  12091. 800545a: d9f5 bls.n 8005448 <HAL_DAC_ConfigChannel+0xc0>
  12092. if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
  12093. 800545c: 6b5a ldr r2, [r3, #52] @ 0x34
  12094. 800545e: ea12 0f08 tst.w r2, r8
  12095. 8005462: d0f1 beq.n 8005448 <HAL_DAC_ConfigChannel+0xc0>
  12096. SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
  12097. 8005464: 6923 ldr r3, [r4, #16]
  12098. hdac->State = HAL_DAC_STATE_TIMEOUT;
  12099. 8005466: 2203 movs r2, #3
  12100. return HAL_TIMEOUT;
  12101. 8005468: 2003 movs r0, #3
  12102. SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
  12103. 800546a: f043 0308 orr.w r3, r3, #8
  12104. 800546e: 6123 str r3, [r4, #16]
  12105. hdac->State = HAL_DAC_STATE_TIMEOUT;
  12106. 8005470: 7122 strb r2, [r4, #4]
  12107. return HAL_TIMEOUT;
  12108. 8005472: e7dd b.n 8005430 <HAL_DAC_ConfigChannel+0xa8>
  12109. while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
  12110. 8005474: 6b5a ldr r2, [r3, #52] @ 0x34
  12111. 8005476: 2a00 cmp r2, #0
  12112. 8005478: da2a bge.n 80054d0 <HAL_DAC_ConfigChannel+0x148>
  12113. if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
  12114. 800547a: f7fe fda9 bl 8003fd0 <HAL_GetTick>
  12115. 800547e: 1bc0 subs r0, r0, r7
  12116. if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
  12117. 8005480: 6823 ldr r3, [r4, #0]
  12118. if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
  12119. 8005482: 2801 cmp r0, #1
  12120. 8005484: d9f6 bls.n 8005474 <HAL_DAC_ConfigChannel+0xec>
  12121. if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
  12122. 8005486: 6b5a ldr r2, [r3, #52] @ 0x34
  12123. 8005488: 2a00 cmp r2, #0
  12124. 800548a: daf3 bge.n 8005474 <HAL_DAC_ConfigChannel+0xec>
  12125. 800548c: e7ea b.n 8005464 <HAL_DAC_ConfigChannel+0xdc>
  12126. connectOnChip = 0x00000000UL;
  12127. 800548e: 2000 movs r0, #0
  12128. 8005490: e7ac b.n 80053ec <HAL_DAC_ConfigChannel+0x64>
  12129. connectOnChip = DAC_MCR_MODE1_0;
  12130. 8005492: 2001 movs r0, #1
  12131. 8005494: e7aa b.n 80053ec <HAL_DAC_ConfigChannel+0x64>
  12132. __HAL_LOCK(hdac);
  12133. 8005496: 2002 movs r0, #2
  12134. 8005498: e7ca b.n 8005430 <HAL_DAC_ConfigChannel+0xa8>
  12135. return HAL_ERROR;
  12136. 800549a: 2001 movs r0, #1
  12137. }
  12138. 800549c: 4770 bx lr
  12139. hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
  12140. 800549e: 69aa ldr r2, [r5, #24]
  12141. 80054a0: 641a str r2, [r3, #64] @ 0x40
  12142. MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
  12143. 80054a2: f006 0210 and.w r2, r6, #16
  12144. 80054a6: f240 30ff movw r0, #1023 @ 0x3ff
  12145. 80054aa: 6c99 ldr r1, [r3, #72] @ 0x48
  12146. 80054ac: 4090 lsls r0, r2
  12147. 80054ae: ea21 0100 bic.w r1, r1, r0
  12148. 80054b2: 69e8 ldr r0, [r5, #28]
  12149. 80054b4: 4090 lsls r0, r2
  12150. 80054b6: 4301 orrs r1, r0
  12151. MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
  12152. 80054b8: 20ff movs r0, #255 @ 0xff
  12153. MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
  12154. 80054ba: 6499 str r1, [r3, #72] @ 0x48
  12155. MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
  12156. 80054bc: 4090 lsls r0, r2
  12157. 80054be: 6cd9 ldr r1, [r3, #76] @ 0x4c
  12158. 80054c0: ea21 0100 bic.w r1, r1, r0
  12159. 80054c4: 6a28 ldr r0, [r5, #32]
  12160. 80054c6: 4090 lsls r0, r2
  12161. 80054c8: 4301 orrs r1, r0
  12162. 80054ca: 64d9 str r1, [r3, #76] @ 0x4c
  12163. tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
  12164. 80054cc: 6829 ldr r1, [r5, #0]
  12165. 80054ce: e773 b.n 80053b8 <HAL_DAC_ConfigChannel+0x30>
  12166. hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
  12167. 80054d0: 69aa ldr r2, [r5, #24]
  12168. 80054d2: 645a str r2, [r3, #68] @ 0x44
  12169. 80054d4: e7e5 b.n 80054a2 <HAL_DAC_ConfigChannel+0x11a>
  12170. 80054d6: bf00 nop
  12171. 80054d8: 20008000 .word 0x20008000
  12172. 080054dc <HAL_DACEx_DMAUnderrunCallbackCh2>:
  12173. * @brief DMA underrun DAC callback for Channel2.
  12174. * @param hdac pointer to a DAC_HandleTypeDef structure that contains
  12175. * the configuration information for the specified DAC.
  12176. * @retval None
  12177. */
  12178. __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
  12179. 80054dc: 4770 bx lr
  12180. 80054de: bf00 nop
  12181. 080054e0 <DMA_CalcBaseAndBitshift>:
  12182. * the configuration information for the specified DMA Stream.
  12183. * @retval Stream base address
  12184. */
  12185. static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
  12186. {
  12187. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  12188. 80054e0: 4936 ldr r1, [pc, #216] @ (80055bc <DMA_CalcBaseAndBitshift+0xdc>)
  12189. {
  12190. 80054e2: 4602 mov r2, r0
  12191. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  12192. 80054e4: 6803 ldr r3, [r0, #0]
  12193. 80054e6: 428b cmp r3, r1
  12194. 80054e8: d033 beq.n 8005552 <DMA_CalcBaseAndBitshift+0x72>
  12195. 80054ea: 3118 adds r1, #24
  12196. 80054ec: 1a59 subs r1, r3, r1
  12197. 80054ee: fab1 f181 clz r1, r1
  12198. 80054f2: 0949 lsrs r1, r1, #5
  12199. 80054f4: bb69 cbnz r1, 8005552 <DMA_CalcBaseAndBitshift+0x72>
  12200. 80054f6: 4832 ldr r0, [pc, #200] @ (80055c0 <DMA_CalcBaseAndBitshift+0xe0>)
  12201. 80054f8: 4283 cmp r3, r0
  12202. 80054fa: d03e beq.n 800557a <DMA_CalcBaseAndBitshift+0x9a>
  12203. 80054fc: 3018 adds r0, #24
  12204. 80054fe: 4283 cmp r3, r0
  12205. 8005500: d03e beq.n 8005580 <DMA_CalcBaseAndBitshift+0xa0>
  12206. 8005502: 3018 adds r0, #24
  12207. 8005504: 4283 cmp r3, r0
  12208. 8005506: d034 beq.n 8005572 <DMA_CalcBaseAndBitshift+0x92>
  12209. 8005508: 3018 adds r0, #24
  12210. 800550a: 4283 cmp r3, r0
  12211. 800550c: d03b beq.n 8005586 <DMA_CalcBaseAndBitshift+0xa6>
  12212. 800550e: 3018 adds r0, #24
  12213. 8005510: 4283 cmp r3, r0
  12214. 8005512: d03e beq.n 8005592 <DMA_CalcBaseAndBitshift+0xb2>
  12215. 8005514: 3018 adds r0, #24
  12216. 8005516: 4283 cmp r3, r0
  12217. 8005518: d02a beq.n 8005570 <DMA_CalcBaseAndBitshift+0x90>
  12218. 800551a: f500 7056 add.w r0, r0, #856 @ 0x358
  12219. 800551e: 4283 cmp r3, r0
  12220. 8005520: d035 beq.n 800558e <DMA_CalcBaseAndBitshift+0xae>
  12221. 8005522: 4928 ldr r1, [pc, #160] @ (80055c4 <DMA_CalcBaseAndBitshift+0xe4>)
  12222. 8005524: 428b cmp r3, r1
  12223. 8005526: d031 beq.n 800558c <DMA_CalcBaseAndBitshift+0xac>
  12224. 8005528: 3118 adds r1, #24
  12225. 800552a: 428b cmp r3, r1
  12226. 800552c: d034 beq.n 8005598 <DMA_CalcBaseAndBitshift+0xb8>
  12227. 800552e: 3118 adds r1, #24
  12228. 8005530: 428b cmp r3, r1
  12229. 8005532: d034 beq.n 800559e <DMA_CalcBaseAndBitshift+0xbe>
  12230. 8005534: 3118 adds r1, #24
  12231. 8005536: 428b cmp r3, r1
  12232. 8005538: d034 beq.n 80055a4 <DMA_CalcBaseAndBitshift+0xc4>
  12233. 800553a: 3118 adds r1, #24
  12234. 800553c: 428b cmp r3, r1
  12235. 800553e: d034 beq.n 80055aa <DMA_CalcBaseAndBitshift+0xca>
  12236. 8005540: 3118 adds r1, #24
  12237. 8005542: 428b cmp r3, r1
  12238. 8005544: d034 beq.n 80055b0 <DMA_CalcBaseAndBitshift+0xd0>
  12239. 8005546: 3118 adds r1, #24
  12240. 8005548: 428b cmp r3, r1
  12241. 800554a: d034 beq.n 80055b6 <DMA_CalcBaseAndBitshift+0xd6>
  12242. }
  12243. }
  12244. else /* BDMA instance(s) */
  12245. {
  12246. /* return pointer to ISR and IFCR */
  12247. hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU));
  12248. 800554c: f023 00ff bic.w r0, r3, #255 @ 0xff
  12249. 8005550: e011 b.n 8005576 <DMA_CalcBaseAndBitshift+0x96>
  12250. uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
  12251. 8005552: b2db uxtb r3, r3
  12252. 8005554: 491c ldr r1, [pc, #112] @ (80055c8 <DMA_CalcBaseAndBitshift+0xe8>)
  12253. hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
  12254. 8005556: 481d ldr r0, [pc, #116] @ (80055cc <DMA_CalcBaseAndBitshift+0xec>)
  12255. uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
  12256. 8005558: 3b10 subs r3, #16
  12257. 800555a: fba1 1303 umull r1, r3, r1, r3
  12258. {
  12259. 800555e: b410 push {r4}
  12260. uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
  12261. 8005560: 091b lsrs r3, r3, #4
  12262. hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
  12263. 8005562: 4c1b ldr r4, [pc, #108] @ (80055d0 <DMA_CalcBaseAndBitshift+0xf0>)
  12264. 8005564: 5ce1 ldrb r1, [r4, r3]
  12265. }
  12266. return hdma->StreamBaseAddress;
  12267. }
  12268. 8005566: f85d 4b04 ldr.w r4, [sp], #4
  12269. hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU));
  12270. 800556a: e9c2 0116 strd r0, r1, [r2, #88] @ 0x58
  12271. }
  12272. 800556e: 4770 bx lr
  12273. 8005570: 2116 movs r1, #22
  12274. 8005572: 4818 ldr r0, [pc, #96] @ (80055d4 <DMA_CalcBaseAndBitshift+0xf4>)
  12275. hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
  12276. 8005574: 65d1 str r1, [r2, #92] @ 0x5c
  12277. hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU));
  12278. 8005576: 6590 str r0, [r2, #88] @ 0x58
  12279. }
  12280. 8005578: 4770 bx lr
  12281. 800557a: 2110 movs r1, #16
  12282. 800557c: 4813 ldr r0, [pc, #76] @ (80055cc <DMA_CalcBaseAndBitshift+0xec>)
  12283. 800557e: e7f9 b.n 8005574 <DMA_CalcBaseAndBitshift+0x94>
  12284. 8005580: 2116 movs r1, #22
  12285. 8005582: 4812 ldr r0, [pc, #72] @ (80055cc <DMA_CalcBaseAndBitshift+0xec>)
  12286. 8005584: e7f6 b.n 8005574 <DMA_CalcBaseAndBitshift+0x94>
  12287. 8005586: 2106 movs r1, #6
  12288. 8005588: 4812 ldr r0, [pc, #72] @ (80055d4 <DMA_CalcBaseAndBitshift+0xf4>)
  12289. 800558a: e7f3 b.n 8005574 <DMA_CalcBaseAndBitshift+0x94>
  12290. 800558c: 2106 movs r1, #6
  12291. 800558e: 4812 ldr r0, [pc, #72] @ (80055d8 <DMA_CalcBaseAndBitshift+0xf8>)
  12292. 8005590: e7f0 b.n 8005574 <DMA_CalcBaseAndBitshift+0x94>
  12293. 8005592: 2110 movs r1, #16
  12294. 8005594: 480f ldr r0, [pc, #60] @ (80055d4 <DMA_CalcBaseAndBitshift+0xf4>)
  12295. 8005596: e7ed b.n 8005574 <DMA_CalcBaseAndBitshift+0x94>
  12296. 8005598: 2110 movs r1, #16
  12297. 800559a: 480f ldr r0, [pc, #60] @ (80055d8 <DMA_CalcBaseAndBitshift+0xf8>)
  12298. 800559c: e7ea b.n 8005574 <DMA_CalcBaseAndBitshift+0x94>
  12299. 800559e: 2116 movs r1, #22
  12300. 80055a0: 480d ldr r0, [pc, #52] @ (80055d8 <DMA_CalcBaseAndBitshift+0xf8>)
  12301. 80055a2: e7e7 b.n 8005574 <DMA_CalcBaseAndBitshift+0x94>
  12302. 80055a4: 2100 movs r1, #0
  12303. 80055a6: 480d ldr r0, [pc, #52] @ (80055dc <DMA_CalcBaseAndBitshift+0xfc>)
  12304. 80055a8: e7e4 b.n 8005574 <DMA_CalcBaseAndBitshift+0x94>
  12305. 80055aa: 2106 movs r1, #6
  12306. 80055ac: 480b ldr r0, [pc, #44] @ (80055dc <DMA_CalcBaseAndBitshift+0xfc>)
  12307. 80055ae: e7e1 b.n 8005574 <DMA_CalcBaseAndBitshift+0x94>
  12308. 80055b0: 2110 movs r1, #16
  12309. 80055b2: 480a ldr r0, [pc, #40] @ (80055dc <DMA_CalcBaseAndBitshift+0xfc>)
  12310. 80055b4: e7de b.n 8005574 <DMA_CalcBaseAndBitshift+0x94>
  12311. 80055b6: 2116 movs r1, #22
  12312. 80055b8: 4808 ldr r0, [pc, #32] @ (80055dc <DMA_CalcBaseAndBitshift+0xfc>)
  12313. 80055ba: e7db b.n 8005574 <DMA_CalcBaseAndBitshift+0x94>
  12314. 80055bc: 40020010 .word 0x40020010
  12315. 80055c0: 40020040 .word 0x40020040
  12316. 80055c4: 40020428 .word 0x40020428
  12317. 80055c8: aaaaaaab .word 0xaaaaaaab
  12318. 80055cc: 40020000 .word 0x40020000
  12319. 80055d0: 08011a24 .word 0x08011a24
  12320. 80055d4: 40020004 .word 0x40020004
  12321. 80055d8: 40020400 .word 0x40020400
  12322. 80055dc: 40020404 .word 0x40020404
  12323. 080055e0 <DMA_CalcDMAMUXChannelBaseAndMask>:
  12324. * @retval HAL status
  12325. */
  12326. static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
  12327. {
  12328. uint32_t stream_number;
  12329. uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance);
  12330. 80055e0: 6802 ldr r2, [r0, #0]
  12331. if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
  12332. 80055e2: 4b27 ldr r3, [pc, #156] @ (8005680 <DMA_CalcDMAMUXChannelBaseAndMask+0xa0>)
  12333. 80055e4: 4927 ldr r1, [pc, #156] @ (8005684 <DMA_CalcDMAMUXChannelBaseAndMask+0xa4>)
  12334. {
  12335. 80055e6: b430 push {r4, r5}
  12336. if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
  12337. 80055e8: 4d27 ldr r5, [pc, #156] @ (8005688 <DMA_CalcDMAMUXChannelBaseAndMask+0xa8>)
  12338. 80055ea: 4c28 ldr r4, [pc, #160] @ (800568c <DMA_CalcDMAMUXChannelBaseAndMask+0xac>)
  12339. 80055ec: 42aa cmp r2, r5
  12340. 80055ee: bf18 it ne
  12341. 80055f0: 429a cmpne r2, r3
  12342. 80055f2: bf0c ite eq
  12343. 80055f4: 2301 moveq r3, #1
  12344. 80055f6: 2300 movne r3, #0
  12345. 80055f8: 428a cmp r2, r1
  12346. 80055fa: bf08 it eq
  12347. 80055fc: f043 0301 orreq.w r3, r3, #1
  12348. 8005600: 3128 adds r1, #40 @ 0x28
  12349. 8005602: 42a2 cmp r2, r4
  12350. 8005604: bf08 it eq
  12351. 8005606: f043 0301 orreq.w r3, r3, #1
  12352. 800560a: 3428 adds r4, #40 @ 0x28
  12353. 800560c: 428a cmp r2, r1
  12354. 800560e: bf08 it eq
  12355. 8005610: f043 0301 orreq.w r3, r3, #1
  12356. 8005614: 3128 adds r1, #40 @ 0x28
  12357. 8005616: 42a2 cmp r2, r4
  12358. 8005618: bf08 it eq
  12359. 800561a: f043 0301 orreq.w r3, r3, #1
  12360. 800561e: 428a cmp r2, r1
  12361. 8005620: bf08 it eq
  12362. 8005622: f043 0301 orreq.w r3, r3, #1
  12363. hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
  12364. }
  12365. else
  12366. {
  12367. /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */
  12368. stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
  12369. 8005626: b2d1 uxtb r1, r2
  12370. if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
  12371. 8005628: b913 cbnz r3, 8005630 <DMA_CalcDMAMUXChannelBaseAndMask+0x50>
  12372. 800562a: 4b19 ldr r3, [pc, #100] @ (8005690 <DMA_CalcDMAMUXChannelBaseAndMask+0xb0>)
  12373. 800562c: 429a cmp r2, r3
  12374. 800562e: d112 bne.n 8005656 <DMA_CalcDMAMUXChannelBaseAndMask+0x76>
  12375. stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U;
  12376. 8005630: f1a1 0308 sub.w r3, r1, #8
  12377. 8005634: 4917 ldr r1, [pc, #92] @ (8005694 <DMA_CalcDMAMUXChannelBaseAndMask+0xb4>)
  12378. hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
  12379. 8005636: 4a18 ldr r2, [pc, #96] @ (8005698 <DMA_CalcDMAMUXChannelBaseAndMask+0xb8>)
  12380. stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U;
  12381. 8005638: fba1 1303 umull r1, r3, r1, r3
  12382. hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
  12383. 800563c: 2101 movs r1, #1
  12384. 800563e: 4c17 ldr r4, [pc, #92] @ (800569c <DMA_CalcDMAMUXChannelBaseAndMask+0xbc>)
  12385. hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
  12386. 8005640: eb02 1213 add.w r2, r2, r3, lsr #4
  12387. hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
  12388. 8005644: f3c3 1304 ubfx r3, r3, #4, #5
  12389. hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
  12390. 8005648: 0092 lsls r2, r2, #2
  12391. hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
  12392. 800564a: 4099 lsls r1, r3
  12393. 800564c: 6681 str r1, [r0, #104] @ 0x68
  12394. hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;
  12395. 800564e: e9c0 2418 strd r2, r4, [r0, #96] @ 0x60
  12396. }
  12397. hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
  12398. hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
  12399. hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
  12400. }
  12401. }
  12402. 8005652: bc30 pop {r4, r5}
  12403. 8005654: 4770 bx lr
  12404. stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
  12405. 8005656: f1a1 0310 sub.w r3, r1, #16
  12406. if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
  12407. 800565a: 4911 ldr r1, [pc, #68] @ (80056a0 <DMA_CalcDMAMUXChannelBaseAndMask+0xc0>)
  12408. stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
  12409. 800565c: 4c11 ldr r4, [pc, #68] @ (80056a4 <DMA_CalcDMAMUXChannelBaseAndMask+0xc4>)
  12410. if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
  12411. 800565e: 4411 add r1, r2
  12412. stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
  12413. 8005660: fba4 4303 umull r4, r3, r4, r3
  12414. if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
  12415. 8005664: 29a8 cmp r1, #168 @ 0xa8
  12416. stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
  12417. 8005666: ea4f 1313 mov.w r3, r3, lsr #4
  12418. if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
  12419. 800566a: d800 bhi.n 800566e <DMA_CalcDMAMUXChannelBaseAndMask+0x8e>
  12420. stream_number += 8U;
  12421. 800566c: 3308 adds r3, #8
  12422. hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
  12423. 800566e: 4a0e ldr r2, [pc, #56] @ (80056a8 <DMA_CalcDMAMUXChannelBaseAndMask+0xc8>)
  12424. hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
  12425. 8005670: f003 041f and.w r4, r3, #31
  12426. 8005674: 2101 movs r1, #1
  12427. hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
  12428. 8005676: 441a add r2, r3
  12429. hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
  12430. 8005678: 40a1 lsls r1, r4
  12431. 800567a: 4c0c ldr r4, [pc, #48] @ (80056ac <DMA_CalcDMAMUXChannelBaseAndMask+0xcc>)
  12432. hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
  12433. 800567c: 0092 lsls r2, r2, #2
  12434. hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
  12435. 800567e: e7e5 b.n 800564c <DMA_CalcDMAMUXChannelBaseAndMask+0x6c>
  12436. 8005680: 58025408 .word 0x58025408
  12437. 8005684: 58025430 .word 0x58025430
  12438. 8005688: 5802541c .word 0x5802541c
  12439. 800568c: 58025444 .word 0x58025444
  12440. 8005690: 58025494 .word 0x58025494
  12441. 8005694: cccccccd .word 0xcccccccd
  12442. 8005698: 16009600 .word 0x16009600
  12443. 800569c: 58025880 .word 0x58025880
  12444. 80056a0: bffdfbf0 .word 0xbffdfbf0
  12445. 80056a4: aaaaaaab .word 0xaaaaaaab
  12446. 80056a8: 10008200 .word 0x10008200
  12447. 80056ac: 40020880 .word 0x40020880
  12448. 080056b0 <HAL_DMA_Init>:
  12449. {
  12450. 80056b0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  12451. 80056b4: 4605 mov r5, r0
  12452. 80056b6: b083 sub sp, #12
  12453. uint32_t tickstart = HAL_GetTick();
  12454. 80056b8: f7fe fc8a bl 8003fd0 <HAL_GetTick>
  12455. if(hdma == NULL)
  12456. 80056bc: 2d00 cmp r5, #0
  12457. 80056be: f000 8203 beq.w 8005ac8 <HAL_DMA_Init+0x418>
  12458. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  12459. 80056c2: 682c ldr r4, [r5, #0]
  12460. 80056c4: 4606 mov r6, r0
  12461. 80056c6: 4b65 ldr r3, [pc, #404] @ (800585c <HAL_DMA_Init+0x1ac>)
  12462. 80056c8: 429c cmp r4, r3
  12463. 80056ca: f000 80bc beq.w 8005846 <HAL_DMA_Init+0x196>
  12464. 80056ce: 3318 adds r3, #24
  12465. 80056d0: 429c cmp r4, r3
  12466. 80056d2: f000 80b8 beq.w 8005846 <HAL_DMA_Init+0x196>
  12467. 80056d6: 3318 adds r3, #24
  12468. 80056d8: 429c cmp r4, r3
  12469. 80056da: f000 80b4 beq.w 8005846 <HAL_DMA_Init+0x196>
  12470. 80056de: 3318 adds r3, #24
  12471. 80056e0: 429c cmp r4, r3
  12472. 80056e2: f000 80b0 beq.w 8005846 <HAL_DMA_Init+0x196>
  12473. 80056e6: 3318 adds r3, #24
  12474. 80056e8: 429c cmp r4, r3
  12475. 80056ea: f000 80ac beq.w 8005846 <HAL_DMA_Init+0x196>
  12476. 80056ee: 3318 adds r3, #24
  12477. 80056f0: 429c cmp r4, r3
  12478. 80056f2: f000 80a8 beq.w 8005846 <HAL_DMA_Init+0x196>
  12479. 80056f6: 3318 adds r3, #24
  12480. 80056f8: 429c cmp r4, r3
  12481. 80056fa: f000 80a4 beq.w 8005846 <HAL_DMA_Init+0x196>
  12482. 80056fe: 3318 adds r3, #24
  12483. 8005700: 429c cmp r4, r3
  12484. 8005702: f000 80a0 beq.w 8005846 <HAL_DMA_Init+0x196>
  12485. 8005706: f503 7356 add.w r3, r3, #856 @ 0x358
  12486. 800570a: 429c cmp r4, r3
  12487. 800570c: f000 809b beq.w 8005846 <HAL_DMA_Init+0x196>
  12488. 8005710: 3318 adds r3, #24
  12489. 8005712: 429c cmp r4, r3
  12490. 8005714: f000 8097 beq.w 8005846 <HAL_DMA_Init+0x196>
  12491. 8005718: 3318 adds r3, #24
  12492. 800571a: 429c cmp r4, r3
  12493. 800571c: f000 8093 beq.w 8005846 <HAL_DMA_Init+0x196>
  12494. 8005720: 3318 adds r3, #24
  12495. 8005722: 429c cmp r4, r3
  12496. 8005724: f000 808f beq.w 8005846 <HAL_DMA_Init+0x196>
  12497. 8005728: 3318 adds r3, #24
  12498. 800572a: 429c cmp r4, r3
  12499. 800572c: f000 808b beq.w 8005846 <HAL_DMA_Init+0x196>
  12500. 8005730: 3318 adds r3, #24
  12501. 8005732: 429c cmp r4, r3
  12502. 8005734: f000 8087 beq.w 8005846 <HAL_DMA_Init+0x196>
  12503. 8005738: 3318 adds r3, #24
  12504. 800573a: 429c cmp r4, r3
  12505. 800573c: f000 8083 beq.w 8005846 <HAL_DMA_Init+0x196>
  12506. 8005740: 3318 adds r3, #24
  12507. 8005742: 429c cmp r4, r3
  12508. 8005744: d07f beq.n 8005846 <HAL_DMA_Init+0x196>
  12509. else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
  12510. 8005746: 4946 ldr r1, [pc, #280] @ (8005860 <HAL_DMA_Init+0x1b0>)
  12511. 8005748: 4a46 ldr r2, [pc, #280] @ (8005864 <HAL_DMA_Init+0x1b4>)
  12512. 800574a: 4b47 ldr r3, [pc, #284] @ (8005868 <HAL_DMA_Init+0x1b8>)
  12513. 800574c: eba4 0901 sub.w r9, r4, r1
  12514. 8005750: 1aa2 subs r2, r4, r2
  12515. 8005752: 4f46 ldr r7, [pc, #280] @ (800586c <HAL_DMA_Init+0x1bc>)
  12516. 8005754: eba4 0803 sub.w r8, r4, r3
  12517. 8005758: fab9 f989 clz r9, r9
  12518. 800575c: 3314 adds r3, #20
  12519. 800575e: fab2 f282 clz r2, r2
  12520. 8005762: ea4f 1959 mov.w r9, r9, lsr #5
  12521. 8005766: fab8 f888 clz r8, r8
  12522. 800576a: eba4 0a03 sub.w sl, r4, r3
  12523. 800576e: 0952 lsrs r2, r2, #5
  12524. 8005770: ea4f 1858 mov.w r8, r8, lsr #5
  12525. 8005774: 1be7 subs r7, r4, r7
  12526. 8005776: faba fa8a clz sl, sl
  12527. 800577a: ea49 0102 orr.w r1, r9, r2
  12528. 800577e: 4e3c ldr r6, [pc, #240] @ (8005870 <HAL_DMA_Init+0x1c0>)
  12529. 8005780: fab7 f787 clz r7, r7
  12530. 8005784: 483b ldr r0, [pc, #236] @ (8005874 <HAL_DMA_Init+0x1c4>)
  12531. 8005786: ea4f 1a5a mov.w sl, sl, lsr #5
  12532. 800578a: ea48 0101 orr.w r1, r8, r1
  12533. 800578e: 1ba6 subs r6, r4, r6
  12534. 8005790: eba4 0b00 sub.w fp, r4, r0
  12535. 8005794: 097f lsrs r7, r7, #5
  12536. 8005796: ea4a 0101 orr.w r1, sl, r1
  12537. 800579a: fab6 f686 clz r6, r6
  12538. 800579e: 3014 adds r0, #20
  12539. 80057a0: fabb fb8b clz fp, fp
  12540. 80057a4: 4339 orrs r1, r7
  12541. 80057a6: 0976 lsrs r6, r6, #5
  12542. 80057a8: 1a23 subs r3, r4, r0
  12543. 80057aa: ea4f 1b5b mov.w fp, fp, lsr #5
  12544. 80057ae: 4331 orrs r1, r6
  12545. 80057b0: fab3 f383 clz r3, r3
  12546. 80057b4: ea5b 0101 orrs.w r1, fp, r1
  12547. 80057b8: ea4f 1353 mov.w r3, r3, lsr #5
  12548. 80057bc: 9301 str r3, [sp, #4]
  12549. 80057be: d102 bne.n 80057c6 <HAL_DMA_Init+0x116>
  12550. 80057c0: 2b00 cmp r3, #0
  12551. 80057c2: f000 81d4 beq.w 8005b6e <HAL_DMA_Init+0x4be>
  12552. hdma->State = HAL_DMA_STATE_BUSY;
  12553. 80057c6: 2102 movs r1, #2
  12554. registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \
  12555. 80057c8: f8df c0b4 ldr.w ip, [pc, #180] @ 8005880 <HAL_DMA_Init+0x1d0>
  12556. hdma->State = HAL_DMA_STATE_BUSY;
  12557. 80057cc: f885 1035 strb.w r1, [r5, #53] @ 0x35
  12558. __HAL_UNLOCK(hdma);
  12559. 80057d0: 2100 movs r1, #0
  12560. 80057d2: f885 1034 strb.w r1, [r5, #52] @ 0x34
  12561. registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
  12562. 80057d6: 6821 ldr r1, [r4, #0]
  12563. registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \
  12564. 80057d8: ea01 0c0c and.w ip, r1, ip
  12565. registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) |
  12566. 80057dc: 68a9 ldr r1, [r5, #8]
  12567. 80057de: 2940 cmp r1, #64 @ 0x40
  12568. 80057e0: f000 81c2 beq.w 8005b68 <HAL_DMA_Init+0x4b8>
  12569. 80057e4: f1a1 0180 sub.w r1, r1, #128 @ 0x80
  12570. 80057e8: fab1 f181 clz r1, r1
  12571. 80057ec: 0949 lsrs r1, r1, #5
  12572. 80057ee: ea4f 3e81 mov.w lr, r1, lsl #14
  12573. DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) |
  12574. 80057f2: 6929 ldr r1, [r5, #16]
  12575. DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) |
  12576. 80057f4: 68e8 ldr r0, [r5, #12]
  12577. DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) |
  12578. 80057f6: 08c9 lsrs r1, r1, #3
  12579. hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
  12580. 80057f8: 4b1f ldr r3, [pc, #124] @ (8005878 <HAL_DMA_Init+0x1c8>)
  12581. 80057fa: 9200 str r2, [sp, #0]
  12582. 80057fc: ea41 00d0 orr.w r0, r1, r0, lsr #3
  12583. DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
  12584. 8005800: 6969 ldr r1, [r5, #20]
  12585. hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
  12586. 8005802: 4423 add r3, r4
  12587. 8005804: ea40 00d1 orr.w r0, r0, r1, lsr #3
  12588. DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) |
  12589. 8005808: 69a9 ldr r1, [r5, #24]
  12590. 800580a: ea40 00d1 orr.w r0, r0, r1, lsr #3
  12591. DMA_TO_BDMA_MODE(hdma->Init.Mode) |
  12592. 800580e: 69e9 ldr r1, [r5, #28]
  12593. 8005810: ea40 00d1 orr.w r0, r0, r1, lsr #3
  12594. DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);
  12595. 8005814: 6a29 ldr r1, [r5, #32]
  12596. 8005816: ea40 1111 orr.w r1, r0, r1, lsr #4
  12597. 800581a: ea41 010c orr.w r1, r1, ip
  12598. registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) |
  12599. 800581e: ea4e 0101 orr.w r1, lr, r1
  12600. ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;
  12601. 8005822: 6021 str r1, [r4, #0]
  12602. hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
  12603. 8005824: 4915 ldr r1, [pc, #84] @ (800587c <HAL_DMA_Init+0x1cc>)
  12604. 8005826: fba1 0103 umull r0, r1, r1, r3
  12605. regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
  12606. 800582a: 4628 mov r0, r5
  12607. hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
  12608. 800582c: 0909 lsrs r1, r1, #4
  12609. 800582e: 0089 lsls r1, r1, #2
  12610. 8005830: 65e9 str r1, [r5, #92] @ 0x5c
  12611. regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
  12612. 8005832: f7ff fe55 bl 80054e0 <DMA_CalcBaseAndBitshift>
  12613. regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
  12614. 8005836: 6de9 ldr r1, [r5, #92] @ 0x5c
  12615. 8005838: 9a00 ldr r2, [sp, #0]
  12616. 800583a: f001 041f and.w r4, r1, #31
  12617. 800583e: 2101 movs r1, #1
  12618. 8005840: 40a1 lsls r1, r4
  12619. 8005842: 6041 str r1, [r0, #4]
  12620. 8005844: e0e2 b.n 8005a0c <HAL_DMA_Init+0x35c>
  12621. hdma->State = HAL_DMA_STATE_BUSY;
  12622. 8005846: 2302 movs r3, #2
  12623. 8005848: f885 3035 strb.w r3, [r5, #53] @ 0x35
  12624. __HAL_UNLOCK(hdma);
  12625. 800584c: 2300 movs r3, #0
  12626. 800584e: f885 3034 strb.w r3, [r5, #52] @ 0x34
  12627. __HAL_DMA_DISABLE(hdma);
  12628. 8005852: 6823 ldr r3, [r4, #0]
  12629. 8005854: f023 0301 bic.w r3, r3, #1
  12630. 8005858: 6023 str r3, [r4, #0]
  12631. 800585a: e01a b.n 8005892 <HAL_DMA_Init+0x1e2>
  12632. 800585c: 40020010 .word 0x40020010
  12633. 8005860: 58025408 .word 0x58025408
  12634. 8005864: 5802541c .word 0x5802541c
  12635. 8005868: 58025430 .word 0x58025430
  12636. 800586c: 58025458 .word 0x58025458
  12637. 8005870: 5802546c .word 0x5802546c
  12638. 8005874: 58025480 .word 0x58025480
  12639. 8005878: a7fdabf8 .word 0xa7fdabf8
  12640. 800587c: cccccccd .word 0xcccccccd
  12641. 8005880: fffe000f .word 0xfffe000f
  12642. if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
  12643. 8005884: f7fe fba4 bl 8003fd0 <HAL_GetTick>
  12644. 8005888: 1b80 subs r0, r0, r6
  12645. 800588a: 2805 cmp r0, #5
  12646. 800588c: f200 8117 bhi.w 8005abe <HAL_DMA_Init+0x40e>
  12647. while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
  12648. 8005890: 682c ldr r4, [r5, #0]
  12649. 8005892: 6823 ldr r3, [r4, #0]
  12650. 8005894: 07df lsls r7, r3, #31
  12651. 8005896: d4f5 bmi.n 8005884 <HAL_DMA_Init+0x1d4>
  12652. registerValue |= hdma->Init.Direction |
  12653. 8005898: e9d5 3002 ldrd r3, r0, [r5, #8]
  12654. hdma->Init.PeriphInc | hdma->Init.MemInc |
  12655. 800589c: 6929 ldr r1, [r5, #16]
  12656. registerValue |= hdma->Init.Direction |
  12657. 800589e: 4303 orrs r3, r0
  12658. hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
  12659. 80058a0: 69aa ldr r2, [r5, #24]
  12660. registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR;
  12661. 80058a2: 6820 ldr r0, [r4, #0]
  12662. hdma->Init.PeriphInc | hdma->Init.MemInc |
  12663. 80058a4: 430b orrs r3, r1
  12664. 80058a6: 6969 ldr r1, [r5, #20]
  12665. 80058a8: 430b orrs r3, r1
  12666. hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
  12667. 80058aa: 69e9 ldr r1, [r5, #28]
  12668. 80058ac: 4313 orrs r3, r2
  12669. 80058ae: 430b orrs r3, r1
  12670. registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
  12671. 80058b0: 49b2 ldr r1, [pc, #712] @ (8005b7c <HAL_DMA_Init+0x4cc>)
  12672. 80058b2: 4001 ands r1, r0
  12673. hdma->Init.Mode | hdma->Init.Priority;
  12674. 80058b4: 6a28 ldr r0, [r5, #32]
  12675. 80058b6: 4303 orrs r3, r0
  12676. if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
  12677. 80058b8: 48b1 ldr r0, [pc, #708] @ (8005b80 <HAL_DMA_Init+0x4d0>)
  12678. registerValue |= hdma->Init.Direction |
  12679. 80058ba: 430b orrs r3, r1
  12680. if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
  12681. 80058bc: 6a69 ldr r1, [r5, #36] @ 0x24
  12682. 80058be: 2904 cmp r1, #4
  12683. 80058c0: f000 8117 beq.w 8005af2 <HAL_DMA_Init+0x442>
  12684. if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
  12685. 80058c4: 6806 ldr r6, [r0, #0]
  12686. 80058c6: 48af ldr r0, [pc, #700] @ (8005b84 <HAL_DMA_Init+0x4d4>)
  12687. 80058c8: 4030 ands r0, r6
  12688. 80058ca: f1b0 5f00 cmp.w r0, #536870912 @ 0x20000000
  12689. 80058ce: f080 80d5 bcs.w 8005a7c <HAL_DMA_Init+0x3cc>
  12690. ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue;
  12691. 80058d2: 6023 str r3, [r4, #0]
  12692. registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR;
  12693. 80058d4: 6963 ldr r3, [r4, #20]
  12694. registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
  12695. 80058d6: f023 0307 bic.w r3, r3, #7
  12696. registerValue |= hdma->Init.FIFOMode;
  12697. 80058da: 430b orrs r3, r1
  12698. ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue;
  12699. 80058dc: 6163 str r3, [r4, #20]
  12700. regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
  12701. 80058de: 4628 mov r0, r5
  12702. 80058e0: f7ff fdfe bl 80054e0 <DMA_CalcBaseAndBitshift>
  12703. regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
  12704. 80058e4: 6dea ldr r2, [r5, #92] @ 0x5c
  12705. 80058e6: 233f movs r3, #63 @ 0x3f
  12706. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  12707. 80058e8: 49a7 ldr r1, [pc, #668] @ (8005b88 <HAL_DMA_Init+0x4d8>)
  12708. regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
  12709. 80058ea: f002 021f and.w r2, r2, #31
  12710. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  12711. 80058ee: 4fa7 ldr r7, [pc, #668] @ (8005b8c <HAL_DMA_Init+0x4dc>)
  12712. 80058f0: 4ea7 ldr r6, [pc, #668] @ (8005b90 <HAL_DMA_Init+0x4e0>)
  12713. regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
  12714. 80058f2: 4093 lsls r3, r2
  12715. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  12716. 80058f4: 4aa7 ldr r2, [pc, #668] @ (8005b94 <HAL_DMA_Init+0x4e4>)
  12717. 80058f6: 1be7 subs r7, r4, r7
  12718. 80058f8: 1ba6 subs r6, r4, r6
  12719. regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
  12720. 80058fa: 6083 str r3, [r0, #8]
  12721. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  12722. 80058fc: eba4 0902 sub.w r9, r4, r2
  12723. 8005900: 4ba5 ldr r3, [pc, #660] @ (8005b98 <HAL_DMA_Init+0x4e8>)
  12724. 8005902: 3214 adds r2, #20
  12725. 8005904: fab9 f989 clz r9, r9
  12726. 8005908: 48a4 ldr r0, [pc, #656] @ (8005b9c <HAL_DMA_Init+0x4ec>)
  12727. 800590a: eba4 0803 sub.w r8, r4, r3
  12728. 800590e: 4ba4 ldr r3, [pc, #656] @ (8005ba0 <HAL_DMA_Init+0x4f0>)
  12729. 8005910: 1aa2 subs r2, r4, r2
  12730. 8005912: ea4f 1959 mov.w r9, r9, lsr #5
  12731. 8005916: 429c cmp r4, r3
  12732. 8005918: bf18 it ne
  12733. 800591a: 428c cmpne r4, r1
  12734. 800591c: f103 0318 add.w r3, r3, #24
  12735. 8005920: fab2 f282 clz r2, r2
  12736. 8005924: fab8 f888 clz r8, r8
  12737. 8005928: bf0c ite eq
  12738. 800592a: 2101 moveq r1, #1
  12739. 800592c: 2100 movne r1, #0
  12740. 800592e: 0952 lsrs r2, r2, #5
  12741. 8005930: fab7 f787 clz r7, r7
  12742. 8005934: 429c cmp r4, r3
  12743. 8005936: bf08 it eq
  12744. 8005938: f041 0101 orreq.w r1, r1, #1
  12745. 800593c: 3318 adds r3, #24
  12746. 800593e: ea4f 1858 mov.w r8, r8, lsr #5
  12747. 8005942: eba4 0b00 sub.w fp, r4, r0
  12748. 8005946: 429c cmp r4, r3
  12749. 8005948: bf08 it eq
  12750. 800594a: f041 0101 orreq.w r1, r1, #1
  12751. 800594e: 3318 adds r3, #24
  12752. 8005950: 097f lsrs r7, r7, #5
  12753. 8005952: fab6 f686 clz r6, r6
  12754. 8005956: 429c cmp r4, r3
  12755. 8005958: bf08 it eq
  12756. 800595a: f041 0101 orreq.w r1, r1, #1
  12757. 800595e: 3318 adds r3, #24
  12758. 8005960: 3014 adds r0, #20
  12759. 8005962: 0976 lsrs r6, r6, #5
  12760. 8005964: 429c cmp r4, r3
  12761. 8005966: bf08 it eq
  12762. 8005968: f041 0101 orreq.w r1, r1, #1
  12763. 800596c: 3318 adds r3, #24
  12764. 800596e: fabb fb8b clz fp, fp
  12765. 8005972: 429c cmp r4, r3
  12766. 8005974: bf08 it eq
  12767. 8005976: f041 0101 orreq.w r1, r1, #1
  12768. 800597a: 3318 adds r3, #24
  12769. 800597c: ea4f 1b5b mov.w fp, fp, lsr #5
  12770. 8005980: 429c cmp r4, r3
  12771. 8005982: bf08 it eq
  12772. 8005984: f041 0101 orreq.w r1, r1, #1
  12773. 8005988: f503 7356 add.w r3, r3, #856 @ 0x358
  12774. 800598c: 429c cmp r4, r3
  12775. 800598e: bf08 it eq
  12776. 8005990: f041 0101 orreq.w r1, r1, #1
  12777. 8005994: 3318 adds r3, #24
  12778. 8005996: 429c cmp r4, r3
  12779. 8005998: bf08 it eq
  12780. 800599a: f041 0101 orreq.w r1, r1, #1
  12781. 800599e: 3318 adds r3, #24
  12782. 80059a0: 429c cmp r4, r3
  12783. 80059a2: bf08 it eq
  12784. 80059a4: f041 0101 orreq.w r1, r1, #1
  12785. 80059a8: 3318 adds r3, #24
  12786. 80059aa: 429c cmp r4, r3
  12787. 80059ac: bf08 it eq
  12788. 80059ae: f041 0101 orreq.w r1, r1, #1
  12789. 80059b2: 3318 adds r3, #24
  12790. 80059b4: 429c cmp r4, r3
  12791. 80059b6: bf08 it eq
  12792. 80059b8: f041 0101 orreq.w r1, r1, #1
  12793. 80059bc: 3318 adds r3, #24
  12794. 80059be: 429c cmp r4, r3
  12795. 80059c0: bf08 it eq
  12796. 80059c2: f041 0101 orreq.w r1, r1, #1
  12797. 80059c6: 3318 adds r3, #24
  12798. 80059c8: 429c cmp r4, r3
  12799. 80059ca: bf08 it eq
  12800. 80059cc: f041 0101 orreq.w r1, r1, #1
  12801. 80059d0: 3318 adds r3, #24
  12802. 80059d2: 429c cmp r4, r3
  12803. 80059d4: bf08 it eq
  12804. 80059d6: f041 0101 orreq.w r1, r1, #1
  12805. 80059da: 4b72 ldr r3, [pc, #456] @ (8005ba4 <HAL_DMA_Init+0x4f4>)
  12806. 80059dc: ea49 0101 orr.w r1, r9, r1
  12807. 80059e0: eba4 0a03 sub.w sl, r4, r3
  12808. 80059e4: 1a23 subs r3, r4, r0
  12809. 80059e6: 4311 orrs r1, r2
  12810. 80059e8: faba fa8a clz sl, sl
  12811. 80059ec: fab3 f383 clz r3, r3
  12812. 80059f0: ea48 0101 orr.w r1, r8, r1
  12813. 80059f4: ea4f 1a5a mov.w sl, sl, lsr #5
  12814. 80059f8: 095b lsrs r3, r3, #5
  12815. 80059fa: ea4a 0101 orr.w r1, sl, r1
  12816. 80059fe: 9301 str r3, [sp, #4]
  12817. 8005a00: 4339 orrs r1, r7
  12818. 8005a02: 4331 orrs r1, r6
  12819. 8005a04: ea5b 0101 orrs.w r1, fp, r1
  12820. 8005a08: d100 bne.n 8005a0c <HAL_DMA_Init+0x35c>
  12821. 8005a0a: b37b cbz r3, 8005a6c <HAL_DMA_Init+0x3bc>
  12822. DMA_CalcDMAMUXChannelBaseAndMask(hdma);
  12823. 8005a0c: 4628 mov r0, r5
  12824. 8005a0e: 9200 str r2, [sp, #0]
  12825. 8005a10: f7ff fde6 bl 80055e0 <DMA_CalcDMAMUXChannelBaseAndMask>
  12826. if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
  12827. 8005a14: 68a9 ldr r1, [r5, #8]
  12828. 8005a16: 9a00 ldr r2, [sp, #0]
  12829. 8005a18: 2980 cmp r1, #128 @ 0x80
  12830. 8005a1a: d05e beq.n 8005ada <HAL_DMA_Init+0x42a>
  12831. hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
  12832. 8005a1c: 6868 ldr r0, [r5, #4]
  12833. 8005a1e: 6e2b ldr r3, [r5, #96] @ 0x60
  12834. 8005a20: b2c4 uxtb r4, r0
  12835. if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
  12836. 8005a22: 3801 subs r0, #1
  12837. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  12838. 8005a24: e9d5 c119 ldrd ip, r1, [r5, #100] @ 0x64
  12839. if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
  12840. 8005a28: 2807 cmp r0, #7
  12841. hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
  12842. 8005a2a: 601c str r4, [r3, #0]
  12843. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  12844. 8005a2c: f8cc 1004 str.w r1, [ip, #4]
  12845. if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
  12846. 8005a30: d85a bhi.n 8005ae8 <HAL_DMA_Init+0x438>
  12847. {
  12848. uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
  12849. if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
  12850. {
  12851. if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
  12852. 8005a32: ea49 090a orr.w r9, r9, sl
  12853. 8005a36: 9b01 ldr r3, [sp, #4]
  12854. if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
  12855. 8005a38: 1e60 subs r0, r4, #1
  12856. if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
  12857. 8005a3a: ea48 0809 orr.w r8, r8, r9
  12858. 8005a3e: ea47 0708 orr.w r7, r7, r8
  12859. 8005a42: 433e orrs r6, r7
  12860. 8005a44: ea43 0a06 orr.w sl, r3, r6
  12861. 8005a48: ea5b 0a0a orrs.w sl, fp, sl
  12862. 8005a4c: d102 bne.n 8005a54 <HAL_DMA_Init+0x3a4>
  12863. 8005a4e: 2a00 cmp r2, #0
  12864. 8005a50: f000 8085 beq.w 8005b5e <HAL_DMA_Init+0x4ae>
  12865. {
  12866. /* BDMA Channels are connected to DMAMUX2 request generator blocks */
  12867. hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
  12868. 8005a54: 4a54 ldr r2, [pc, #336] @ (8005ba8 <HAL_DMA_Init+0x4f8>)
  12869. hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;
  12870. 8005a56: 4955 ldr r1, [pc, #340] @ (8005bac <HAL_DMA_Init+0x4fc>)
  12871. hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
  12872. 8005a58: 4422 add r2, r4
  12873. 8005a5a: 0092 lsls r2, r2, #2
  12874. hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
  12875. hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
  12876. }
  12877. hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);
  12878. 8005a5c: 2301 movs r3, #1
  12879. 8005a5e: 4083 lsls r3, r0
  12880. hdma->DMAmuxRequestGen->RGCR = 0U;
  12881. 8005a60: 2000 movs r0, #0
  12882. 8005a62: e9c5 211b strd r2, r1, [r5, #108] @ 0x6c
  12883. hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);
  12884. 8005a66: 676b str r3, [r5, #116] @ 0x74
  12885. hdma->DMAmuxRequestGen->RGCR = 0U;
  12886. 8005a68: 6010 str r0, [r2, #0]
  12887. hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
  12888. 8005a6a: 604b str r3, [r1, #4]
  12889. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  12890. 8005a6c: 2000 movs r0, #0
  12891. hdma->State = HAL_DMA_STATE_READY;
  12892. 8005a6e: 2301 movs r3, #1
  12893. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  12894. 8005a70: 6568 str r0, [r5, #84] @ 0x54
  12895. hdma->State = HAL_DMA_STATE_READY;
  12896. 8005a72: f885 3035 strb.w r3, [r5, #53] @ 0x35
  12897. }
  12898. 8005a76: b003 add sp, #12
  12899. 8005a78: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  12900. if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
  12901. 8005a7c: 6868 ldr r0, [r5, #4]
  12902. 8005a7e: f1a0 0629 sub.w r6, r0, #41 @ 0x29
  12903. 8005a82: 2e1f cmp r6, #31
  12904. 8005a84: d924 bls.n 8005ad0 <HAL_DMA_Init+0x420>
  12905. 8005a86: 384f subs r0, #79 @ 0x4f
  12906. 8005a88: 2803 cmp r0, #3
  12907. 8005a8a: d801 bhi.n 8005a90 <HAL_DMA_Init+0x3e0>
  12908. registerValue |= DMA_SxCR_TRBUFF;
  12909. 8005a8c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
  12910. ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue;
  12911. 8005a90: 6023 str r3, [r4, #0]
  12912. if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
  12913. 8005a92: 2904 cmp r1, #4
  12914. registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR;
  12915. 8005a94: 6963 ldr r3, [r4, #20]
  12916. registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
  12917. 8005a96: f023 0307 bic.w r3, r3, #7
  12918. registerValue |= hdma->Init.FIFOMode;
  12919. 8005a9a: ea43 0301 orr.w r3, r3, r1
  12920. if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
  12921. 8005a9e: f47f af1d bne.w 80058dc <HAL_DMA_Init+0x22c>
  12922. 8005aa2: 6ae8 ldr r0, [r5, #44] @ 0x2c
  12923. registerValue |= hdma->Init.FIFOThreshold;
  12924. 8005aa4: 6aa9 ldr r1, [r5, #40] @ 0x28
  12925. 8005aa6: 430b orrs r3, r1
  12926. if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)
  12927. 8005aa8: 2800 cmp r0, #0
  12928. 8005aaa: f43f af17 beq.w 80058dc <HAL_DMA_Init+0x22c>
  12929. if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
  12930. 8005aae: bb8a cbnz r2, 8005b14 <HAL_DMA_Init+0x464>
  12931. switch (hdma->Init.FIFOThreshold)
  12932. 8005ab0: 2901 cmp r1, #1
  12933. 8005ab2: d04f beq.n 8005b54 <HAL_DMA_Init+0x4a4>
  12934. 8005ab4: f031 0202 bics.w r2, r1, #2
  12935. 8005ab8: f47f af10 bne.w 80058dc <HAL_DMA_Init+0x22c>
  12936. 8005abc: e032 b.n 8005b24 <HAL_DMA_Init+0x474>
  12937. hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
  12938. 8005abe: 2220 movs r2, #32
  12939. hdma->State = HAL_DMA_STATE_ERROR;
  12940. 8005ac0: 2303 movs r3, #3
  12941. hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
  12942. 8005ac2: 656a str r2, [r5, #84] @ 0x54
  12943. hdma->State = HAL_DMA_STATE_ERROR;
  12944. 8005ac4: f885 3035 strb.w r3, [r5, #53] @ 0x35
  12945. return HAL_ERROR;
  12946. 8005ac8: 2001 movs r0, #1
  12947. }
  12948. 8005aca: b003 add sp, #12
  12949. 8005acc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  12950. if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
  12951. 8005ad0: 4837 ldr r0, [pc, #220] @ (8005bb0 <HAL_DMA_Init+0x500>)
  12952. 8005ad2: 40f0 lsrs r0, r6
  12953. 8005ad4: 07c0 lsls r0, r0, #31
  12954. 8005ad6: d5db bpl.n 8005a90 <HAL_DMA_Init+0x3e0>
  12955. 8005ad8: e7d8 b.n 8005a8c <HAL_DMA_Init+0x3dc>
  12956. hdma->Init.Request = DMA_REQUEST_MEM2MEM;
  12957. 8005ada: 2300 movs r3, #0
  12958. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  12959. 8005adc: 6ea9 ldr r1, [r5, #104] @ 0x68
  12960. 8005ade: e9d5 0218 ldrd r0, r2, [r5, #96] @ 0x60
  12961. hdma->Init.Request = DMA_REQUEST_MEM2MEM;
  12962. 8005ae2: 606b str r3, [r5, #4]
  12963. hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
  12964. 8005ae4: 6003 str r3, [r0, #0]
  12965. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  12966. 8005ae6: 6051 str r1, [r2, #4]
  12967. hdma->DMAmuxRequestGen = 0U;
  12968. 8005ae8: 2300 movs r3, #0
  12969. 8005aea: e9c5 331b strd r3, r3, [r5, #108] @ 0x6c
  12970. hdma->DMAmuxRequestGenStatusMask = 0U;
  12971. 8005aee: 676b str r3, [r5, #116] @ 0x74
  12972. 8005af0: e7bc b.n 8005a6c <HAL_DMA_Init+0x3bc>
  12973. if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
  12974. 8005af2: 6807 ldr r7, [r0, #0]
  12975. registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
  12976. 8005af4: e9d5 060b ldrd r0, r6, [r5, #44] @ 0x2c
  12977. 8005af8: 4306 orrs r6, r0
  12978. 8005afa: 4333 orrs r3, r6
  12979. if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
  12980. 8005afc: 4e21 ldr r6, [pc, #132] @ (8005b84 <HAL_DMA_Init+0x4d4>)
  12981. 8005afe: 403e ands r6, r7
  12982. 8005b00: f1b6 5f00 cmp.w r6, #536870912 @ 0x20000000
  12983. 8005b04: d2ba bcs.n 8005a7c <HAL_DMA_Init+0x3cc>
  12984. ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue;
  12985. 8005b06: 6023 str r3, [r4, #0]
  12986. registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR;
  12987. 8005b08: 6963 ldr r3, [r4, #20]
  12988. registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
  12989. 8005b0a: f023 0307 bic.w r3, r3, #7
  12990. registerValue |= hdma->Init.FIFOMode;
  12991. 8005b0e: f043 0304 orr.w r3, r3, #4
  12992. if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
  12993. 8005b12: e7c7 b.n 8005aa4 <HAL_DMA_Init+0x3f4>
  12994. else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
  12995. 8005b14: f5b2 5f00 cmp.w r2, #8192 @ 0x2000
  12996. 8005b18: d00d beq.n 8005b36 <HAL_DMA_Init+0x486>
  12997. switch (hdma->Init.FIFOThreshold)
  12998. 8005b1a: 2902 cmp r1, #2
  12999. 8005b1c: d905 bls.n 8005b2a <HAL_DMA_Init+0x47a>
  13000. 8005b1e: 2903 cmp r1, #3
  13001. 8005b20: f47f aedc bne.w 80058dc <HAL_DMA_Init+0x22c>
  13002. if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
  13003. 8005b24: 01c2 lsls r2, r0, #7
  13004. 8005b26: f57f aed9 bpl.w 80058dc <HAL_DMA_Init+0x22c>
  13005. hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
  13006. 8005b2a: 2240 movs r2, #64 @ 0x40
  13007. hdma->State = HAL_DMA_STATE_READY;
  13008. 8005b2c: 2301 movs r3, #1
  13009. hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
  13010. 8005b2e: 656a str r2, [r5, #84] @ 0x54
  13011. hdma->State = HAL_DMA_STATE_READY;
  13012. 8005b30: f885 3035 strb.w r3, [r5, #53] @ 0x35
  13013. return HAL_ERROR;
  13014. 8005b34: e7c8 b.n 8005ac8 <HAL_DMA_Init+0x418>
  13015. switch (hdma->Init.FIFOThreshold)
  13016. 8005b36: 2903 cmp r1, #3
  13017. 8005b38: f63f aed0 bhi.w 80058dc <HAL_DMA_Init+0x22c>
  13018. 8005b3c: a201 add r2, pc, #4 @ (adr r2, 8005b44 <HAL_DMA_Init+0x494>)
  13019. 8005b3e: f852 f021 ldr.w pc, [r2, r1, lsl #2]
  13020. 8005b42: bf00 nop
  13021. 8005b44: 08005b2b .word 0x08005b2b
  13022. 8005b48: 08005b25 .word 0x08005b25
  13023. 8005b4c: 08005b2b .word 0x08005b2b
  13024. 8005b50: 08005b55 .word 0x08005b55
  13025. if (hdma->Init.MemBurst == DMA_MBURST_INC16)
  13026. 8005b54: f1b0 7fc0 cmp.w r0, #25165824 @ 0x1800000
  13027. 8005b58: f47f aec0 bne.w 80058dc <HAL_DMA_Init+0x22c>
  13028. 8005b5c: e7e5 b.n 8005b2a <HAL_DMA_Init+0x47a>
  13029. hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
  13030. 8005b5e: 4a15 ldr r2, [pc, #84] @ (8005bb4 <HAL_DMA_Init+0x504>)
  13031. hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
  13032. 8005b60: 4915 ldr r1, [pc, #84] @ (8005bb8 <HAL_DMA_Init+0x508>)
  13033. hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
  13034. 8005b62: 4422 add r2, r4
  13035. 8005b64: 0092 lsls r2, r2, #2
  13036. hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
  13037. 8005b66: e779 b.n 8005a5c <HAL_DMA_Init+0x3ac>
  13038. registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) |
  13039. 8005b68: f04f 0e10 mov.w lr, #16
  13040. 8005b6c: e641 b.n 80057f2 <HAL_DMA_Init+0x142>
  13041. hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
  13042. 8005b6e: 2240 movs r2, #64 @ 0x40
  13043. hdma->State = HAL_DMA_STATE_ERROR;
  13044. 8005b70: 2303 movs r3, #3
  13045. hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
  13046. 8005b72: 656a str r2, [r5, #84] @ 0x54
  13047. hdma->State = HAL_DMA_STATE_ERROR;
  13048. 8005b74: f885 3035 strb.w r3, [r5, #53] @ 0x35
  13049. return HAL_ERROR;
  13050. 8005b78: e7a6 b.n 8005ac8 <HAL_DMA_Init+0x418>
  13051. 8005b7a: bf00 nop
  13052. 8005b7c: fe10803f .word 0xfe10803f
  13053. 8005b80: 5c001000 .word 0x5c001000
  13054. 8005b84: ffff0000 .word 0xffff0000
  13055. 8005b88: 40020010 .word 0x40020010
  13056. 8005b8c: 58025458 .word 0x58025458
  13057. 8005b90: 5802546c .word 0x5802546c
  13058. 8005b94: 58025408 .word 0x58025408
  13059. 8005b98: 58025430 .word 0x58025430
  13060. 8005b9c: 58025480 .word 0x58025480
  13061. 8005ba0: 40020028 .word 0x40020028
  13062. 8005ba4: 58025444 .word 0x58025444
  13063. 8005ba8: 1600963f .word 0x1600963f
  13064. 8005bac: 58025940 .word 0x58025940
  13065. 8005bb0: c3c0003f .word 0xc3c0003f
  13066. 8005bb4: 1000823f .word 0x1000823f
  13067. 8005bb8: 40020940 .word 0x40020940
  13068. 08005bbc <HAL_DMA_Start_IT>:
  13069. if(hdma == NULL)
  13070. 8005bbc: 2800 cmp r0, #0
  13071. 8005bbe: f000 8232 beq.w 8006026 <HAL_DMA_Start_IT+0x46a>
  13072. {
  13073. 8005bc2: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  13074. __HAL_LOCK(hdma);
  13075. 8005bc6: f890 4034 ldrb.w r4, [r0, #52] @ 0x34
  13076. {
  13077. 8005bca: b083 sub sp, #12
  13078. __HAL_LOCK(hdma);
  13079. 8005bcc: 2c01 cmp r4, #1
  13080. 8005bce: f000 8226 beq.w 800601e <HAL_DMA_Start_IT+0x462>
  13081. 8005bd2: 2401 movs r4, #1
  13082. 8005bd4: f880 4034 strb.w r4, [r0, #52] @ 0x34
  13083. if(HAL_DMA_STATE_READY == hdma->State)
  13084. 8005bd8: f890 4035 ldrb.w r4, [r0, #53] @ 0x35
  13085. 8005bdc: 2c01 cmp r4, #1
  13086. 8005bde: d009 beq.n 8005bf4 <HAL_DMA_Start_IT+0x38>
  13087. hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
  13088. 8005be0: f44f 6200 mov.w r2, #2048 @ 0x800
  13089. __HAL_UNLOCK(hdma);
  13090. 8005be4: 2300 movs r3, #0
  13091. hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
  13092. 8005be6: 6542 str r2, [r0, #84] @ 0x54
  13093. __HAL_UNLOCK(hdma);
  13094. 8005be8: f880 3034 strb.w r3, [r0, #52] @ 0x34
  13095. return HAL_ERROR;
  13096. 8005bec: 2001 movs r0, #1
  13097. }
  13098. 8005bee: b003 add sp, #12
  13099. 8005bf0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  13100. hdma->State = HAL_DMA_STATE_BUSY;
  13101. 8005bf4: 2402 movs r4, #2
  13102. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  13103. 8005bf6: 4e7d ldr r6, [pc, #500] @ (8005dec <HAL_DMA_Start_IT+0x230>)
  13104. 8005bf8: f8df 81f8 ldr.w r8, [pc, #504] @ 8005df4 <HAL_DMA_Start_IT+0x238>
  13105. hdma->State = HAL_DMA_STATE_BUSY;
  13106. 8005bfc: f880 4035 strb.w r4, [r0, #53] @ 0x35
  13107. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  13108. 8005c00: 2400 movs r4, #0
  13109. __HAL_DMA_DISABLE(hdma);
  13110. 8005c02: 4d7b ldr r5, [pc, #492] @ (8005df0 <HAL_DMA_Start_IT+0x234>)
  13111. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  13112. 8005c04: 6544 str r4, [r0, #84] @ 0x54
  13113. __HAL_DMA_DISABLE(hdma);
  13114. 8005c06: 6804 ldr r4, [r0, #0]
  13115. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  13116. 8005c08: f8df 91ec ldr.w r9, [pc, #492] @ 8005df8 <HAL_DMA_Start_IT+0x23c>
  13117. 8005c0c: 4544 cmp r4, r8
  13118. 8005c0e: bf18 it ne
  13119. 8005c10: 42b4 cmpne r4, r6
  13120. __HAL_DMA_DISABLE(hdma);
  13121. 8005c12: f8df c1f8 ldr.w ip, [pc, #504] @ 8005e0c <HAL_DMA_Start_IT+0x250>
  13122. DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
  13123. 8005c16: 6d86 ldr r6, [r0, #88] @ 0x58
  13124. 8005c18: bf0c ite eq
  13125. 8005c1a: f04f 0b01 moveq.w fp, #1
  13126. 8005c1e: f04f 0b00 movne.w fp, #0
  13127. 8005c22: 9601 str r6, [sp, #4]
  13128. 8005c24: 454c cmp r4, r9
  13129. 8005c26: bf14 ite ne
  13130. 8005c28: 46de movne lr, fp
  13131. 8005c2a: f04b 0e01 orreq.w lr, fp, #1
  13132. __HAL_DMA_DISABLE(hdma);
  13133. 8005c2e: 42ac cmp r4, r5
  13134. 8005c30: bf18 it ne
  13135. 8005c32: 4564 cmpne r4, ip
  13136. 8005c34: bf0c ite eq
  13137. 8005c36: 2501 moveq r5, #1
  13138. 8005c38: 2500 movne r5, #0
  13139. 8005c3a: f040 80e9 bne.w 8005e10 <HAL_DMA_Start_IT+0x254>
  13140. 8005c3e: f8d4 c000 ldr.w ip, [r4]
  13141. 8005c42: f02c 0c01 bic.w ip, ip, #1
  13142. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13143. 8005c46: e9d0 7619 ldrd r7, r6, [r0, #100] @ 0x64
  13144. __HAL_DMA_DISABLE(hdma);
  13145. 8005c4a: f8c4 c000 str.w ip, [r4]
  13146. if(hdma->DMAmuxRequestGen != 0U)
  13147. 8005c4e: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c
  13148. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13149. 8005c52: 607e str r6, [r7, #4]
  13150. if(hdma->DMAmuxRequestGen != 0U)
  13151. 8005c54: f1bc 0f00 cmp.w ip, #0
  13152. 8005c58: d002 beq.n 8005c60 <HAL_DMA_Start_IT+0xa4>
  13153. hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
  13154. 8005c5a: e9d0 671c ldrd r6, r7, [r0, #112] @ 0x70
  13155. 8005c5e: 6077 str r7, [r6, #4]
  13156. regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
  13157. 8005c60: 6dc7 ldr r7, [r0, #92] @ 0x5c
  13158. 8005c62: f04f 083f mov.w r8, #63 @ 0x3f
  13159. 8005c66: 9e01 ldr r6, [sp, #4]
  13160. 8005c68: f007 091f and.w r9, r7, #31
  13161. 8005c6c: fa08 f809 lsl.w r8, r8, r9
  13162. 8005c70: f8c6 8008 str.w r8, [r6, #8]
  13163. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);
  13164. 8005c74: 6827 ldr r7, [r4, #0]
  13165. 8005c76: f427 2780 bic.w r7, r7, #262144 @ 0x40000
  13166. 8005c7a: 6027 str r7, [r4, #0]
  13167. ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
  13168. 8005c7c: 6063 str r3, [r4, #4]
  13169. if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
  13170. 8005c7e: 6883 ldr r3, [r0, #8]
  13171. 8005c80: 2b40 cmp r3, #64 @ 0x40
  13172. 8005c82: f000 81d2 beq.w 800602a <HAL_DMA_Start_IT+0x46e>
  13173. ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
  13174. 8005c86: 60a1 str r1, [r4, #8]
  13175. ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
  13176. 8005c88: 60e2 str r2, [r4, #12]
  13177. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  13178. 8005c8a: 2d00 cmp r5, #0
  13179. 8005c8c: f040 81a2 bne.w 8005fd4 <HAL_DMA_Start_IT+0x418>
  13180. 8005c90: 4a58 ldr r2, [pc, #352] @ (8005df4 <HAL_DMA_Start_IT+0x238>)
  13181. if(hdma->XferHalfCpltCallback != NULL)
  13182. 8005c92: 6c03 ldr r3, [r0, #64] @ 0x40
  13183. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  13184. 8005c94: 4294 cmp r4, r2
  13185. 8005c96: f000 8201 beq.w 800609c <HAL_DMA_Start_IT+0x4e0>
  13186. 8005c9a: 4a57 ldr r2, [pc, #348] @ (8005df8 <HAL_DMA_Start_IT+0x23c>)
  13187. 8005c9c: 4294 cmp r4, r2
  13188. 8005c9e: f000 8207 beq.w 80060b0 <HAL_DMA_Start_IT+0x4f4>
  13189. 8005ca2: f1bb 0f00 cmp.w fp, #0
  13190. 8005ca6: f040 81d7 bne.w 8006058 <HAL_DMA_Start_IT+0x49c>
  13191. 8005caa: 4a54 ldr r2, [pc, #336] @ (8005dfc <HAL_DMA_Start_IT+0x240>)
  13192. if(hdma->XferHalfCpltCallback != NULL)
  13193. 8005cac: 4619 mov r1, r3
  13194. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  13195. 8005cae: 4294 cmp r4, r2
  13196. 8005cb0: f000 821c beq.w 80060ec <HAL_DMA_Start_IT+0x530>
  13197. 8005cb4: 4a52 ldr r2, [pc, #328] @ (8005e00 <HAL_DMA_Start_IT+0x244>)
  13198. 8005cb6: 4294 cmp r4, r2
  13199. 8005cb8: f000 824c beq.w 8006154 <HAL_DMA_Start_IT+0x598>
  13200. 8005cbc: 3218 adds r2, #24
  13201. 8005cbe: 4294 cmp r4, r2
  13202. 8005cc0: f000 8269 beq.w 8006196 <HAL_DMA_Start_IT+0x5da>
  13203. 8005cc4: f502 7256 add.w r2, r2, #856 @ 0x358
  13204. 8005cc8: 4294 cmp r4, r2
  13205. 8005cca: f000 8271 beq.w 80061b0 <HAL_DMA_Start_IT+0x5f4>
  13206. 8005cce: 4b4d ldr r3, [pc, #308] @ (8005e04 <HAL_DMA_Start_IT+0x248>)
  13207. 8005cd0: 429c cmp r4, r3
  13208. 8005cd2: f000 82ce beq.w 8006272 <HAL_DMA_Start_IT+0x6b6>
  13209. 8005cd6: 3318 adds r3, #24
  13210. 8005cd8: 429c cmp r4, r3
  13211. 8005cda: f000 82d5 beq.w 8006288 <HAL_DMA_Start_IT+0x6cc>
  13212. 8005cde: 3318 adds r3, #24
  13213. 8005ce0: 429c cmp r4, r3
  13214. 8005ce2: f000 82e5 beq.w 80062b0 <HAL_DMA_Start_IT+0x6f4>
  13215. 8005ce6: 3318 adds r3, #24
  13216. 8005ce8: 429c cmp r4, r3
  13217. 8005cea: f000 82fe beq.w 80062ea <HAL_DMA_Start_IT+0x72e>
  13218. 8005cee: 3318 adds r3, #24
  13219. 8005cf0: 429c cmp r4, r3
  13220. 8005cf2: f000 830f beq.w 8006314 <HAL_DMA_Start_IT+0x758>
  13221. 8005cf6: 3318 adds r3, #24
  13222. 8005cf8: 429c cmp r4, r3
  13223. 8005cfa: f000 8321 beq.w 8006340 <HAL_DMA_Start_IT+0x784>
  13224. 8005cfe: 3318 adds r3, #24
  13225. 8005d00: 429c cmp r4, r3
  13226. 8005d02: f000 8349 beq.w 8006398 <HAL_DMA_Start_IT+0x7dc>
  13227. MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
  13228. 8005d06: 6823 ldr r3, [r4, #0]
  13229. 8005d08: f023 030e bic.w r3, r3, #14
  13230. 8005d0c: f043 030a orr.w r3, r3, #10
  13231. 8005d10: 6023 str r3, [r4, #0]
  13232. if(hdma->XferHalfCpltCallback != NULL)
  13233. 8005d12: b119 cbz r1, 8005d1c <HAL_DMA_Start_IT+0x160>
  13234. ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE;
  13235. 8005d14: 6823 ldr r3, [r4, #0]
  13236. 8005d16: f043 0304 orr.w r3, r3, #4
  13237. 8005d1a: 6023 str r3, [r4, #0]
  13238. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13239. 8005d1c: 4b38 ldr r3, [pc, #224] @ (8005e00 <HAL_DMA_Start_IT+0x244>)
  13240. 8005d1e: 4a37 ldr r2, [pc, #220] @ (8005dfc <HAL_DMA_Start_IT+0x240>)
  13241. 8005d20: 4294 cmp r4, r2
  13242. 8005d22: bf18 it ne
  13243. 8005d24: 429c cmpne r4, r3
  13244. 8005d26: f102 0230 add.w r2, r2, #48 @ 0x30
  13245. 8005d2a: bf0c ite eq
  13246. 8005d2c: 2301 moveq r3, #1
  13247. 8005d2e: 2300 movne r3, #0
  13248. 8005d30: 4294 cmp r4, r2
  13249. 8005d32: bf08 it eq
  13250. 8005d34: f043 0301 orreq.w r3, r3, #1
  13251. 8005d38: f502 7256 add.w r2, r2, #856 @ 0x358
  13252. 8005d3c: 4294 cmp r4, r2
  13253. 8005d3e: bf08 it eq
  13254. 8005d40: f043 0301 orreq.w r3, r3, #1
  13255. 8005d44: 3218 adds r2, #24
  13256. 8005d46: 4294 cmp r4, r2
  13257. 8005d48: bf08 it eq
  13258. 8005d4a: f043 0301 orreq.w r3, r3, #1
  13259. 8005d4e: 3218 adds r2, #24
  13260. 8005d50: 4294 cmp r4, r2
  13261. 8005d52: bf08 it eq
  13262. 8005d54: f043 0301 orreq.w r3, r3, #1
  13263. 8005d58: 3218 adds r2, #24
  13264. 8005d5a: 4294 cmp r4, r2
  13265. 8005d5c: bf08 it eq
  13266. 8005d5e: f043 0301 orreq.w r3, r3, #1
  13267. 8005d62: 3218 adds r2, #24
  13268. 8005d64: 4294 cmp r4, r2
  13269. 8005d66: bf08 it eq
  13270. 8005d68: f043 0301 orreq.w r3, r3, #1
  13271. 8005d6c: 3218 adds r2, #24
  13272. 8005d6e: 4294 cmp r4, r2
  13273. 8005d70: bf08 it eq
  13274. 8005d72: f043 0301 orreq.w r3, r3, #1
  13275. 8005d76: 3218 adds r2, #24
  13276. 8005d78: 4294 cmp r4, r2
  13277. 8005d7a: bf08 it eq
  13278. 8005d7c: f043 0301 orreq.w r3, r3, #1
  13279. 8005d80: 3218 adds r2, #24
  13280. 8005d82: 4294 cmp r4, r2
  13281. 8005d84: bf08 it eq
  13282. 8005d86: f043 0301 orreq.w r3, r3, #1
  13283. 8005d8a: 4a1f ldr r2, [pc, #124] @ (8005e08 <HAL_DMA_Start_IT+0x24c>)
  13284. 8005d8c: 4294 cmp r4, r2
  13285. 8005d8e: bf08 it eq
  13286. 8005d90: f043 0301 orreq.w r3, r3, #1
  13287. 8005d94: 3214 adds r2, #20
  13288. 8005d96: 4294 cmp r4, r2
  13289. 8005d98: bf08 it eq
  13290. 8005d9a: f043 0301 orreq.w r3, r3, #1
  13291. 8005d9e: 3214 adds r2, #20
  13292. 8005da0: 4294 cmp r4, r2
  13293. 8005da2: bf08 it eq
  13294. 8005da4: f043 0301 orreq.w r3, r3, #1
  13295. 8005da8: 3214 adds r2, #20
  13296. 8005daa: 4294 cmp r4, r2
  13297. 8005dac: bf08 it eq
  13298. 8005dae: f043 0301 orreq.w r3, r3, #1
  13299. 8005db2: 3214 adds r2, #20
  13300. 8005db4: 4294 cmp r4, r2
  13301. 8005db6: bf08 it eq
  13302. 8005db8: f043 0301 orreq.w r3, r3, #1
  13303. 8005dbc: 3214 adds r2, #20
  13304. 8005dbe: 4294 cmp r4, r2
  13305. 8005dc0: bf08 it eq
  13306. 8005dc2: f043 0301 orreq.w r3, r3, #1
  13307. 8005dc6: 3214 adds r2, #20
  13308. 8005dc8: 4294 cmp r4, r2
  13309. 8005dca: bf08 it eq
  13310. 8005dcc: f043 0301 orreq.w r3, r3, #1
  13311. 8005dd0: 3214 adds r2, #20
  13312. 8005dd2: 4294 cmp r4, r2
  13313. 8005dd4: bf08 it eq
  13314. 8005dd6: f043 0301 orreq.w r3, r3, #1
  13315. 8005dda: b91b cbnz r3, 8005de4 <HAL_DMA_Start_IT+0x228>
  13316. 8005ddc: f1be 0f00 cmp.w lr, #0
  13317. 8005de0: f000 8115 beq.w 800600e <HAL_DMA_Start_IT+0x452>
  13318. 8005de4: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c
  13319. 8005de8: e100 b.n 8005fec <HAL_DMA_Start_IT+0x430>
  13320. 8005dea: bf00 nop
  13321. 8005dec: 40020070 .word 0x40020070
  13322. 8005df0: 40020028 .word 0x40020028
  13323. 8005df4: 40020040 .word 0x40020040
  13324. 8005df8: 40020058 .word 0x40020058
  13325. 8005dfc: 40020088 .word 0x40020088
  13326. 8005e00: 400200a0 .word 0x400200a0
  13327. 8005e04: 40020428 .word 0x40020428
  13328. 8005e08: 58025408 .word 0x58025408
  13329. 8005e0c: 40020010 .word 0x40020010
  13330. __HAL_DMA_DISABLE(hdma);
  13331. 8005e10: 4544 cmp r4, r8
  13332. 8005e12: f000 812f beq.w 8006074 <HAL_DMA_Start_IT+0x4b8>
  13333. 8005e16: 454c cmp r4, r9
  13334. 8005e18: f000 8154 beq.w 80060c4 <HAL_DMA_Start_IT+0x508>
  13335. 8005e1c: f1bb 0f00 cmp.w fp, #0
  13336. 8005e20: f040 8106 bne.w 8006030 <HAL_DMA_Start_IT+0x474>
  13337. 8005e24: f8df c54c ldr.w ip, [pc, #1356] @ 8006374 <HAL_DMA_Start_IT+0x7b8>
  13338. 8005e28: 4564 cmp r4, ip
  13339. 8005e2a: f000 816b beq.w 8006104 <HAL_DMA_Start_IT+0x548>
  13340. 8005e2e: f10c 0c18 add.w ip, ip, #24
  13341. 8005e32: 4564 cmp r4, ip
  13342. 8005e34: f000 817a beq.w 800612c <HAL_DMA_Start_IT+0x570>
  13343. 8005e38: f10c 0c18 add.w ip, ip, #24
  13344. 8005e3c: 4564 cmp r4, ip
  13345. 8005e3e: f000 8196 beq.w 800616e <HAL_DMA_Start_IT+0x5b2>
  13346. 8005e42: f50c 7c56 add.w ip, ip, #856 @ 0x358
  13347. 8005e46: 4564 cmp r4, ip
  13348. 8005e48: f000 81bd beq.w 80061c6 <HAL_DMA_Start_IT+0x60a>
  13349. 8005e4c: f10c 0c18 add.w ip, ip, #24
  13350. 8005e50: 4564 cmp r4, ip
  13351. 8005e52: f000 8205 beq.w 8006260 <HAL_DMA_Start_IT+0x6a4>
  13352. 8005e56: f10c 0c18 add.w ip, ip, #24
  13353. 8005e5a: 4564 cmp r4, ip
  13354. 8005e5c: f000 821f beq.w 800629e <HAL_DMA_Start_IT+0x6e2>
  13355. 8005e60: f10c 0c18 add.w ip, ip, #24
  13356. 8005e64: 4564 cmp r4, ip
  13357. 8005e66: f000 822e beq.w 80062c6 <HAL_DMA_Start_IT+0x70a>
  13358. 8005e6a: f10c 0c18 add.w ip, ip, #24
  13359. 8005e6e: 4564 cmp r4, ip
  13360. 8005e70: f000 8232 beq.w 80062d8 <HAL_DMA_Start_IT+0x71c>
  13361. 8005e74: f10c 0c18 add.w ip, ip, #24
  13362. 8005e78: 4564 cmp r4, ip
  13363. 8005e7a: f000 8258 beq.w 800632e <HAL_DMA_Start_IT+0x772>
  13364. 8005e7e: f10c 0c18 add.w ip, ip, #24
  13365. 8005e82: 4564 cmp r4, ip
  13366. 8005e84: f000 8269 beq.w 800635a <HAL_DMA_Start_IT+0x79e>
  13367. 8005e88: f10c 0c18 add.w ip, ip, #24
  13368. 8005e8c: 4564 cmp r4, ip
  13369. 8005e8e: f000 8290 beq.w 80063b2 <HAL_DMA_Start_IT+0x7f6>
  13370. 8005e92: f8d4 c000 ldr.w ip, [r4]
  13371. 8005e96: f02c 0c01 bic.w ip, ip, #1
  13372. 8005e9a: f8c4 c000 str.w ip, [r4]
  13373. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13374. 8005e9e: f8df c4d8 ldr.w ip, [pc, #1240] @ 8006378 <HAL_DMA_Start_IT+0x7bc>
  13375. 8005ea2: 4564 cmp r4, ip
  13376. 8005ea4: f040 81a6 bne.w 80061f4 <HAL_DMA_Start_IT+0x638>
  13377. if(hdma->DMAmuxRequestGen != 0U)
  13378. 8005ea8: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c
  13379. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13380. 8005eac: e9d0 6719 ldrd r6, r7, [r0, #100] @ 0x64
  13381. 8005eb0: 6077 str r7, [r6, #4]
  13382. if(hdma->DMAmuxRequestGen != 0U)
  13383. 8005eb2: f1bc 0f00 cmp.w ip, #0
  13384. 8005eb6: f43f aed3 beq.w 8005c60 <HAL_DMA_Start_IT+0xa4>
  13385. hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
  13386. 8005eba: e9d0 671c ldrd r6, r7, [r0, #112] @ 0x70
  13387. 8005ebe: 6077 str r7, [r6, #4]
  13388. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  13389. 8005ec0: f8df 84b0 ldr.w r8, [pc, #1200] @ 8006374 <HAL_DMA_Start_IT+0x7b8>
  13390. 8005ec4: f8df 94b4 ldr.w r9, [pc, #1204] @ 800637c <HAL_DMA_Start_IT+0x7c0>
  13391. 8005ec8: 454c cmp r4, r9
  13392. 8005eca: bf18 it ne
  13393. 8005ecc: 4544 cmpne r4, r8
  13394. 8005ece: f109 0918 add.w r9, r9, #24
  13395. 8005ed2: bf0c ite eq
  13396. 8005ed4: f04f 0801 moveq.w r8, #1
  13397. 8005ed8: f04f 0800 movne.w r8, #0
  13398. 8005edc: 454c cmp r4, r9
  13399. 8005ede: bf08 it eq
  13400. 8005ee0: f048 0801 orreq.w r8, r8, #1
  13401. 8005ee4: f509 7956 add.w r9, r9, #856 @ 0x358
  13402. 8005ee8: 454c cmp r4, r9
  13403. 8005eea: bf08 it eq
  13404. 8005eec: f048 0801 orreq.w r8, r8, #1
  13405. 8005ef0: f109 0918 add.w r9, r9, #24
  13406. 8005ef4: 454c cmp r4, r9
  13407. 8005ef6: bf08 it eq
  13408. 8005ef8: f048 0801 orreq.w r8, r8, #1
  13409. 8005efc: f109 0918 add.w r9, r9, #24
  13410. 8005f00: 454c cmp r4, r9
  13411. 8005f02: bf08 it eq
  13412. 8005f04: f048 0801 orreq.w r8, r8, #1
  13413. 8005f08: f109 0918 add.w r9, r9, #24
  13414. 8005f0c: 454c cmp r4, r9
  13415. 8005f0e: bf08 it eq
  13416. 8005f10: f048 0801 orreq.w r8, r8, #1
  13417. 8005f14: f109 0918 add.w r9, r9, #24
  13418. 8005f18: 454c cmp r4, r9
  13419. 8005f1a: bf08 it eq
  13420. 8005f1c: f048 0801 orreq.w r8, r8, #1
  13421. 8005f20: f109 0918 add.w r9, r9, #24
  13422. 8005f24: 454c cmp r4, r9
  13423. 8005f26: bf08 it eq
  13424. 8005f28: f048 0801 orreq.w r8, r8, #1
  13425. 8005f2c: f109 0918 add.w r9, r9, #24
  13426. 8005f30: 454c cmp r4, r9
  13427. 8005f32: bf08 it eq
  13428. 8005f34: f048 0801 orreq.w r8, r8, #1
  13429. 8005f38: f1b8 0f00 cmp.w r8, #0
  13430. 8005f3c: f47f ae90 bne.w 8005c60 <HAL_DMA_Start_IT+0xa4>
  13431. 8005f40: f8df 843c ldr.w r8, [pc, #1084] @ 8006380 <HAL_DMA_Start_IT+0x7c4>
  13432. 8005f44: 4544 cmp r4, r8
  13433. 8005f46: f43f ae8b beq.w 8005c60 <HAL_DMA_Start_IT+0xa4>
  13434. else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
  13435. 8005f4a: f8df 8438 ldr.w r8, [pc, #1080] @ 8006384 <HAL_DMA_Start_IT+0x7c8>
  13436. 8005f4e: f8df 9438 ldr.w r9, [pc, #1080] @ 8006388 <HAL_DMA_Start_IT+0x7cc>
  13437. 8005f52: 454c cmp r4, r9
  13438. 8005f54: bf18 it ne
  13439. 8005f56: 4544 cmpne r4, r8
  13440. 8005f58: f109 0914 add.w r9, r9, #20
  13441. 8005f5c: bf0c ite eq
  13442. 8005f5e: f04f 0801 moveq.w r8, #1
  13443. 8005f62: f04f 0800 movne.w r8, #0
  13444. 8005f66: 454c cmp r4, r9
  13445. 8005f68: bf08 it eq
  13446. 8005f6a: f048 0801 orreq.w r8, r8, #1
  13447. 8005f6e: f109 0914 add.w r9, r9, #20
  13448. 8005f72: 454c cmp r4, r9
  13449. 8005f74: bf08 it eq
  13450. 8005f76: f048 0801 orreq.w r8, r8, #1
  13451. 8005f7a: f109 0914 add.w r9, r9, #20
  13452. 8005f7e: 454c cmp r4, r9
  13453. 8005f80: bf08 it eq
  13454. 8005f82: f048 0801 orreq.w r8, r8, #1
  13455. 8005f86: f109 0914 add.w r9, r9, #20
  13456. 8005f8a: 454c cmp r4, r9
  13457. 8005f8c: bf08 it eq
  13458. 8005f8e: f048 0801 orreq.w r8, r8, #1
  13459. 8005f92: f109 0914 add.w r9, r9, #20
  13460. 8005f96: 454c cmp r4, r9
  13461. 8005f98: bf08 it eq
  13462. 8005f9a: f048 0801 orreq.w r8, r8, #1
  13463. 8005f9e: f1b8 0f00 cmp.w r8, #0
  13464. 8005fa2: d104 bne.n 8005fae <HAL_DMA_Start_IT+0x3f2>
  13465. 8005fa4: f8df 83e4 ldr.w r8, [pc, #996] @ 800638c <HAL_DMA_Start_IT+0x7d0>
  13466. 8005fa8: 4544 cmp r4, r8
  13467. 8005faa: f040 820d bne.w 80063c8 <HAL_DMA_Start_IT+0x80c>
  13468. regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
  13469. 8005fae: 6dc6 ldr r6, [r0, #92] @ 0x5c
  13470. 8005fb0: f04f 0801 mov.w r8, #1
  13471. 8005fb4: f006 091f and.w r9, r6, #31
  13472. 8005fb8: 9e01 ldr r6, [sp, #4]
  13473. 8005fba: fa08 f809 lsl.w r8, r8, r9
  13474. 8005fbe: f8c6 8004 str.w r8, [r6, #4]
  13475. ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
  13476. 8005fc2: 6063 str r3, [r4, #4]
  13477. if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
  13478. 8005fc4: 6883 ldr r3, [r0, #8]
  13479. 8005fc6: 2b40 cmp r3, #64 @ 0x40
  13480. 8005fc8: f000 81fc beq.w 80063c4 <HAL_DMA_Start_IT+0x808>
  13481. ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
  13482. 8005fcc: 60a1 str r1, [r4, #8]
  13483. if(hdma->XferHalfCpltCallback != NULL)
  13484. 8005fce: 6c03 ldr r3, [r0, #64] @ 0x40
  13485. ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
  13486. 8005fd0: 60e2 str r2, [r4, #12]
  13487. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  13488. 8005fd2: e662 b.n 8005c9a <HAL_DMA_Start_IT+0xde>
  13489. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13490. 8005fd4: 6823 ldr r3, [r4, #0]
  13491. 8005fd6: f023 031e bic.w r3, r3, #30
  13492. 8005fda: f043 0316 orr.w r3, r3, #22
  13493. 8005fde: 6023 str r3, [r4, #0]
  13494. if(hdma->XferHalfCpltCallback != NULL)
  13495. 8005fe0: 6c03 ldr r3, [r0, #64] @ 0x40
  13496. 8005fe2: b11b cbz r3, 8005fec <HAL_DMA_Start_IT+0x430>
  13497. ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;
  13498. 8005fe4: 6823 ldr r3, [r4, #0]
  13499. 8005fe6: f043 0308 orr.w r3, r3, #8
  13500. 8005fea: 6023 str r3, [r4, #0]
  13501. if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
  13502. 8005fec: 6e03 ldr r3, [r0, #96] @ 0x60
  13503. 8005fee: 681a ldr r2, [r3, #0]
  13504. 8005ff0: 03d2 lsls r2, r2, #15
  13505. 8005ff2: d503 bpl.n 8005ffc <HAL_DMA_Start_IT+0x440>
  13506. hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
  13507. 8005ff4: 681a ldr r2, [r3, #0]
  13508. 8005ff6: f442 7280 orr.w r2, r2, #256 @ 0x100
  13509. 8005ffa: 601a str r2, [r3, #0]
  13510. if(hdma->DMAmuxRequestGen != 0U)
  13511. 8005ffc: f1bc 0f00 cmp.w ip, #0
  13512. 8006000: d005 beq.n 800600e <HAL_DMA_Start_IT+0x452>
  13513. hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
  13514. 8006002: f8dc 3000 ldr.w r3, [ip]
  13515. 8006006: f443 7380 orr.w r3, r3, #256 @ 0x100
  13516. 800600a: f8cc 3000 str.w r3, [ip]
  13517. __HAL_DMA_ENABLE(hdma);
  13518. 800600e: 6823 ldr r3, [r4, #0]
  13519. HAL_StatusTypeDef status = HAL_OK;
  13520. 8006010: 2000 movs r0, #0
  13521. __HAL_DMA_ENABLE(hdma);
  13522. 8006012: f043 0301 orr.w r3, r3, #1
  13523. 8006016: 6023 str r3, [r4, #0]
  13524. }
  13525. 8006018: b003 add sp, #12
  13526. 800601a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  13527. __HAL_LOCK(hdma);
  13528. 800601e: 2002 movs r0, #2
  13529. }
  13530. 8006020: b003 add sp, #12
  13531. 8006022: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  13532. return HAL_ERROR;
  13533. 8006026: 2001 movs r0, #1
  13534. }
  13535. 8006028: 4770 bx lr
  13536. ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
  13537. 800602a: 60a2 str r2, [r4, #8]
  13538. ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
  13539. 800602c: 60e1 str r1, [r4, #12]
  13540. 800602e: e62c b.n 8005c8a <HAL_DMA_Start_IT+0xce>
  13541. __HAL_DMA_DISABLE(hdma);
  13542. 8006030: f8df a338 ldr.w sl, [pc, #824] @ 800636c <HAL_DMA_Start_IT+0x7b0>
  13543. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13544. 8006034: f8d0 9064 ldr.w r9, [r0, #100] @ 0x64
  13545. __HAL_DMA_DISABLE(hdma);
  13546. 8006038: f8da 8070 ldr.w r8, [sl, #112] @ 0x70
  13547. if(hdma->DMAmuxRequestGen != 0U)
  13548. 800603c: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c
  13549. __HAL_DMA_DISABLE(hdma);
  13550. 8006040: f028 0801 bic.w r8, r8, #1
  13551. 8006044: f8ca 8070 str.w r8, [sl, #112] @ 0x70
  13552. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13553. 8006048: 6e86 ldr r6, [r0, #104] @ 0x68
  13554. 800604a: f8c9 6004 str.w r6, [r9, #4]
  13555. if(hdma->DMAmuxRequestGen != 0U)
  13556. 800604e: f1bc 0f00 cmp.w ip, #0
  13557. 8006052: f47f ae02 bne.w 8005c5a <HAL_DMA_Start_IT+0x9e>
  13558. 8006056: e603 b.n 8005c60 <HAL_DMA_Start_IT+0xa4>
  13559. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13560. 8006058: 49c4 ldr r1, [pc, #784] @ (800636c <HAL_DMA_Start_IT+0x7b0>)
  13561. 800605a: 6f0a ldr r2, [r1, #112] @ 0x70
  13562. 800605c: f022 021e bic.w r2, r2, #30
  13563. 8006060: f042 0216 orr.w r2, r2, #22
  13564. 8006064: 670a str r2, [r1, #112] @ 0x70
  13565. if(hdma->XferHalfCpltCallback != NULL)
  13566. 8006066: 2b00 cmp r3, #0
  13567. 8006068: d0c0 beq.n 8005fec <HAL_DMA_Start_IT+0x430>
  13568. ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;
  13569. 800606a: 6823 ldr r3, [r4, #0]
  13570. 800606c: f043 0308 orr.w r3, r3, #8
  13571. 8006070: 6023 str r3, [r4, #0]
  13572. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13573. 8006072: e653 b.n 8005d1c <HAL_DMA_Start_IT+0x160>
  13574. __HAL_DMA_DISABLE(hdma);
  13575. 8006074: f8df a2f4 ldr.w sl, [pc, #756] @ 800636c <HAL_DMA_Start_IT+0x7b0>
  13576. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13577. 8006078: f8d0 9064 ldr.w r9, [r0, #100] @ 0x64
  13578. __HAL_DMA_DISABLE(hdma);
  13579. 800607c: f8da 8040 ldr.w r8, [sl, #64] @ 0x40
  13580. if(hdma->DMAmuxRequestGen != 0U)
  13581. 8006080: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c
  13582. __HAL_DMA_DISABLE(hdma);
  13583. 8006084: f028 0801 bic.w r8, r8, #1
  13584. 8006088: f8ca 8040 str.w r8, [sl, #64] @ 0x40
  13585. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13586. 800608c: 6e86 ldr r6, [r0, #104] @ 0x68
  13587. 800608e: f8c9 6004 str.w r6, [r9, #4]
  13588. if(hdma->DMAmuxRequestGen != 0U)
  13589. 8006092: f1bc 0f00 cmp.w ip, #0
  13590. 8006096: f47f ade0 bne.w 8005c5a <HAL_DMA_Start_IT+0x9e>
  13591. 800609a: e5e1 b.n 8005c60 <HAL_DMA_Start_IT+0xa4>
  13592. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13593. 800609c: 49b3 ldr r1, [pc, #716] @ (800636c <HAL_DMA_Start_IT+0x7b0>)
  13594. 800609e: 6c0a ldr r2, [r1, #64] @ 0x40
  13595. 80060a0: f022 021e bic.w r2, r2, #30
  13596. 80060a4: f042 0216 orr.w r2, r2, #22
  13597. 80060a8: 640a str r2, [r1, #64] @ 0x40
  13598. if(hdma->XferHalfCpltCallback != NULL)
  13599. 80060aa: 2b00 cmp r3, #0
  13600. 80060ac: d1dd bne.n 800606a <HAL_DMA_Start_IT+0x4ae>
  13601. 80060ae: e79d b.n 8005fec <HAL_DMA_Start_IT+0x430>
  13602. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13603. 80060b0: 49ae ldr r1, [pc, #696] @ (800636c <HAL_DMA_Start_IT+0x7b0>)
  13604. 80060b2: 6d8a ldr r2, [r1, #88] @ 0x58
  13605. 80060b4: f022 021e bic.w r2, r2, #30
  13606. 80060b8: f042 0216 orr.w r2, r2, #22
  13607. 80060bc: 658a str r2, [r1, #88] @ 0x58
  13608. if(hdma->XferHalfCpltCallback != NULL)
  13609. 80060be: 2b00 cmp r3, #0
  13610. 80060c0: d1d3 bne.n 800606a <HAL_DMA_Start_IT+0x4ae>
  13611. 80060c2: e793 b.n 8005fec <HAL_DMA_Start_IT+0x430>
  13612. __HAL_DMA_DISABLE(hdma);
  13613. 80060c4: f8df a2a4 ldr.w sl, [pc, #676] @ 800636c <HAL_DMA_Start_IT+0x7b0>
  13614. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13615. 80060c8: f8d0 9064 ldr.w r9, [r0, #100] @ 0x64
  13616. __HAL_DMA_DISABLE(hdma);
  13617. 80060cc: f8da 8058 ldr.w r8, [sl, #88] @ 0x58
  13618. if(hdma->DMAmuxRequestGen != 0U)
  13619. 80060d0: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c
  13620. __HAL_DMA_DISABLE(hdma);
  13621. 80060d4: f028 0801 bic.w r8, r8, #1
  13622. 80060d8: f8ca 8058 str.w r8, [sl, #88] @ 0x58
  13623. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13624. 80060dc: 6e86 ldr r6, [r0, #104] @ 0x68
  13625. 80060de: f8c9 6004 str.w r6, [r9, #4]
  13626. if(hdma->DMAmuxRequestGen != 0U)
  13627. 80060e2: f1bc 0f00 cmp.w ip, #0
  13628. 80060e6: f47f adb8 bne.w 8005c5a <HAL_DMA_Start_IT+0x9e>
  13629. 80060ea: e5b9 b.n 8005c60 <HAL_DMA_Start_IT+0xa4>
  13630. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13631. 80060ec: 499f ldr r1, [pc, #636] @ (800636c <HAL_DMA_Start_IT+0x7b0>)
  13632. 80060ee: f8d1 2088 ldr.w r2, [r1, #136] @ 0x88
  13633. 80060f2: f022 021e bic.w r2, r2, #30
  13634. 80060f6: f042 0216 orr.w r2, r2, #22
  13635. 80060fa: f8c1 2088 str.w r2, [r1, #136] @ 0x88
  13636. if(hdma->XferHalfCpltCallback != NULL)
  13637. 80060fe: 2b00 cmp r3, #0
  13638. 8006100: d1b3 bne.n 800606a <HAL_DMA_Start_IT+0x4ae>
  13639. 8006102: e773 b.n 8005fec <HAL_DMA_Start_IT+0x430>
  13640. __HAL_DMA_DISABLE(hdma);
  13641. 8006104: f8df a264 ldr.w sl, [pc, #612] @ 800636c <HAL_DMA_Start_IT+0x7b0>
  13642. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13643. 8006108: f8d0 9064 ldr.w r9, [r0, #100] @ 0x64
  13644. __HAL_DMA_DISABLE(hdma);
  13645. 800610c: f8da 8088 ldr.w r8, [sl, #136] @ 0x88
  13646. if(hdma->DMAmuxRequestGen != 0U)
  13647. 8006110: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c
  13648. __HAL_DMA_DISABLE(hdma);
  13649. 8006114: f028 0801 bic.w r8, r8, #1
  13650. 8006118: f8ca 8088 str.w r8, [sl, #136] @ 0x88
  13651. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13652. 800611c: 6e86 ldr r6, [r0, #104] @ 0x68
  13653. 800611e: f8c9 6004 str.w r6, [r9, #4]
  13654. if(hdma->DMAmuxRequestGen != 0U)
  13655. 8006122: f1bc 0f00 cmp.w ip, #0
  13656. 8006126: f47f aec8 bne.w 8005eba <HAL_DMA_Start_IT+0x2fe>
  13657. 800612a: e6c9 b.n 8005ec0 <HAL_DMA_Start_IT+0x304>
  13658. __HAL_DMA_DISABLE(hdma);
  13659. 800612c: f8df a23c ldr.w sl, [pc, #572] @ 800636c <HAL_DMA_Start_IT+0x7b0>
  13660. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13661. 8006130: f8d0 9064 ldr.w r9, [r0, #100] @ 0x64
  13662. __HAL_DMA_DISABLE(hdma);
  13663. 8006134: f8da 80a0 ldr.w r8, [sl, #160] @ 0xa0
  13664. if(hdma->DMAmuxRequestGen != 0U)
  13665. 8006138: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c
  13666. __HAL_DMA_DISABLE(hdma);
  13667. 800613c: f028 0801 bic.w r8, r8, #1
  13668. 8006140: f8ca 80a0 str.w r8, [sl, #160] @ 0xa0
  13669. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13670. 8006144: 6e86 ldr r6, [r0, #104] @ 0x68
  13671. 8006146: f8c9 6004 str.w r6, [r9, #4]
  13672. if(hdma->DMAmuxRequestGen != 0U)
  13673. 800614a: f1bc 0f00 cmp.w ip, #0
  13674. 800614e: f47f aeb4 bne.w 8005eba <HAL_DMA_Start_IT+0x2fe>
  13675. 8006152: e6b5 b.n 8005ec0 <HAL_DMA_Start_IT+0x304>
  13676. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13677. 8006154: 4985 ldr r1, [pc, #532] @ (800636c <HAL_DMA_Start_IT+0x7b0>)
  13678. 8006156: f8d1 20a0 ldr.w r2, [r1, #160] @ 0xa0
  13679. 800615a: f022 021e bic.w r2, r2, #30
  13680. 800615e: f042 0216 orr.w r2, r2, #22
  13681. 8006162: f8c1 20a0 str.w r2, [r1, #160] @ 0xa0
  13682. if(hdma->XferHalfCpltCallback != NULL)
  13683. 8006166: 2b00 cmp r3, #0
  13684. 8006168: f47f af7f bne.w 800606a <HAL_DMA_Start_IT+0x4ae>
  13685. 800616c: e73e b.n 8005fec <HAL_DMA_Start_IT+0x430>
  13686. __HAL_DMA_DISABLE(hdma);
  13687. 800616e: f8df a1fc ldr.w sl, [pc, #508] @ 800636c <HAL_DMA_Start_IT+0x7b0>
  13688. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13689. 8006172: f8d0 9064 ldr.w r9, [r0, #100] @ 0x64
  13690. __HAL_DMA_DISABLE(hdma);
  13691. 8006176: f8da 80b8 ldr.w r8, [sl, #184] @ 0xb8
  13692. if(hdma->DMAmuxRequestGen != 0U)
  13693. 800617a: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c
  13694. __HAL_DMA_DISABLE(hdma);
  13695. 800617e: f028 0801 bic.w r8, r8, #1
  13696. 8006182: f8ca 80b8 str.w r8, [sl, #184] @ 0xb8
  13697. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13698. 8006186: 6e86 ldr r6, [r0, #104] @ 0x68
  13699. 8006188: f8c9 6004 str.w r6, [r9, #4]
  13700. if(hdma->DMAmuxRequestGen != 0U)
  13701. 800618c: f1bc 0f00 cmp.w ip, #0
  13702. 8006190: f47f ae93 bne.w 8005eba <HAL_DMA_Start_IT+0x2fe>
  13703. 8006194: e694 b.n 8005ec0 <HAL_DMA_Start_IT+0x304>
  13704. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13705. 8006196: 4975 ldr r1, [pc, #468] @ (800636c <HAL_DMA_Start_IT+0x7b0>)
  13706. 8006198: f8d1 20b8 ldr.w r2, [r1, #184] @ 0xb8
  13707. 800619c: f022 021e bic.w r2, r2, #30
  13708. 80061a0: f042 0216 orr.w r2, r2, #22
  13709. 80061a4: f8c1 20b8 str.w r2, [r1, #184] @ 0xb8
  13710. if(hdma->XferHalfCpltCallback != NULL)
  13711. 80061a8: 2b00 cmp r3, #0
  13712. 80061aa: f47f af5e bne.w 800606a <HAL_DMA_Start_IT+0x4ae>
  13713. 80061ae: e71d b.n 8005fec <HAL_DMA_Start_IT+0x430>
  13714. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13715. 80061b0: 496f ldr r1, [pc, #444] @ (8006370 <HAL_DMA_Start_IT+0x7b4>)
  13716. 80061b2: 690a ldr r2, [r1, #16]
  13717. 80061b4: f022 021e bic.w r2, r2, #30
  13718. 80061b8: f042 0216 orr.w r2, r2, #22
  13719. 80061bc: 610a str r2, [r1, #16]
  13720. if(hdma->XferHalfCpltCallback != NULL)
  13721. 80061be: 2b00 cmp r3, #0
  13722. 80061c0: f47f af53 bne.w 800606a <HAL_DMA_Start_IT+0x4ae>
  13723. 80061c4: e712 b.n 8005fec <HAL_DMA_Start_IT+0x430>
  13724. __HAL_DMA_DISABLE(hdma);
  13725. 80061c6: f8df 81a8 ldr.w r8, [pc, #424] @ 8006370 <HAL_DMA_Start_IT+0x7b4>
  13726. 80061ca: f8d8 c010 ldr.w ip, [r8, #16]
  13727. 80061ce: f02c 0c01 bic.w ip, ip, #1
  13728. 80061d2: f8c8 c010 str.w ip, [r8, #16]
  13729. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13730. 80061d6: f8df c1b8 ldr.w ip, [pc, #440] @ 8006390 <HAL_DMA_Start_IT+0x7d4>
  13731. 80061da: 4564 cmp r4, ip
  13732. 80061dc: f43f ae64 beq.w 8005ea8 <HAL_DMA_Start_IT+0x2ec>
  13733. 80061e0: f10c 0c18 add.w ip, ip, #24
  13734. 80061e4: 4564 cmp r4, ip
  13735. 80061e6: f43f ae5f beq.w 8005ea8 <HAL_DMA_Start_IT+0x2ec>
  13736. 80061ea: f10c 0c18 add.w ip, ip, #24
  13737. 80061ee: 4564 cmp r4, ip
  13738. 80061f0: f43f ae5a beq.w 8005ea8 <HAL_DMA_Start_IT+0x2ec>
  13739. 80061f4: f8df c19c ldr.w ip, [pc, #412] @ 8006394 <HAL_DMA_Start_IT+0x7d8>
  13740. 80061f8: 4564 cmp r4, ip
  13741. 80061fa: f43f ae55 beq.w 8005ea8 <HAL_DMA_Start_IT+0x2ec>
  13742. 80061fe: f10c 0c18 add.w ip, ip, #24
  13743. 8006202: 4564 cmp r4, ip
  13744. 8006204: f43f ae50 beq.w 8005ea8 <HAL_DMA_Start_IT+0x2ec>
  13745. 8006208: f10c 0c18 add.w ip, ip, #24
  13746. 800620c: 4564 cmp r4, ip
  13747. 800620e: f43f ae4b beq.w 8005ea8 <HAL_DMA_Start_IT+0x2ec>
  13748. 8006212: f10c 0c18 add.w ip, ip, #24
  13749. 8006216: 4564 cmp r4, ip
  13750. 8006218: f43f ae46 beq.w 8005ea8 <HAL_DMA_Start_IT+0x2ec>
  13751. 800621c: f8df c164 ldr.w ip, [pc, #356] @ 8006384 <HAL_DMA_Start_IT+0x7c8>
  13752. 8006220: 4564 cmp r4, ip
  13753. 8006222: d06d beq.n 8006300 <HAL_DMA_Start_IT+0x744>
  13754. 8006224: f10c 0c14 add.w ip, ip, #20
  13755. 8006228: 4564 cmp r4, ip
  13756. 800622a: d069 beq.n 8006300 <HAL_DMA_Start_IT+0x744>
  13757. 800622c: f10c 0c14 add.w ip, ip, #20
  13758. 8006230: 4564 cmp r4, ip
  13759. 8006232: d065 beq.n 8006300 <HAL_DMA_Start_IT+0x744>
  13760. 8006234: f10c 0c14 add.w ip, ip, #20
  13761. 8006238: 4564 cmp r4, ip
  13762. 800623a: d061 beq.n 8006300 <HAL_DMA_Start_IT+0x744>
  13763. 800623c: f10c 0c14 add.w ip, ip, #20
  13764. 8006240: 4564 cmp r4, ip
  13765. 8006242: d05d beq.n 8006300 <HAL_DMA_Start_IT+0x744>
  13766. 8006244: f10c 0c14 add.w ip, ip, #20
  13767. 8006248: 4564 cmp r4, ip
  13768. 800624a: d059 beq.n 8006300 <HAL_DMA_Start_IT+0x744>
  13769. 800624c: f10c 0c14 add.w ip, ip, #20
  13770. 8006250: 4564 cmp r4, ip
  13771. 8006252: d055 beq.n 8006300 <HAL_DMA_Start_IT+0x744>
  13772. 8006254: f10c 0c14 add.w ip, ip, #20
  13773. 8006258: 4564 cmp r4, ip
  13774. 800625a: d051 beq.n 8006300 <HAL_DMA_Start_IT+0x744>
  13775. if(hdma->XferHalfCpltCallback != NULL)
  13776. 800625c: 6c01 ldr r1, [r0, #64] @ 0x40
  13777. 800625e: e536 b.n 8005cce <HAL_DMA_Start_IT+0x112>
  13778. __HAL_DMA_DISABLE(hdma);
  13779. 8006260: f8df 810c ldr.w r8, [pc, #268] @ 8006370 <HAL_DMA_Start_IT+0x7b4>
  13780. 8006264: f8d8 c028 ldr.w ip, [r8, #40] @ 0x28
  13781. 8006268: f02c 0c01 bic.w ip, ip, #1
  13782. 800626c: f8c8 c028 str.w ip, [r8, #40] @ 0x28
  13783. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13784. 8006270: e61a b.n 8005ea8 <HAL_DMA_Start_IT+0x2ec>
  13785. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13786. 8006272: 4a3f ldr r2, [pc, #252] @ (8006370 <HAL_DMA_Start_IT+0x7b4>)
  13787. 8006274: 6a93 ldr r3, [r2, #40] @ 0x28
  13788. 8006276: f023 031e bic.w r3, r3, #30
  13789. 800627a: f043 0316 orr.w r3, r3, #22
  13790. 800627e: 6293 str r3, [r2, #40] @ 0x28
  13791. if(hdma->XferHalfCpltCallback != NULL)
  13792. 8006280: 2900 cmp r1, #0
  13793. 8006282: f47f aef2 bne.w 800606a <HAL_DMA_Start_IT+0x4ae>
  13794. 8006286: e5ad b.n 8005de4 <HAL_DMA_Start_IT+0x228>
  13795. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13796. 8006288: 4a39 ldr r2, [pc, #228] @ (8006370 <HAL_DMA_Start_IT+0x7b4>)
  13797. 800628a: 6c13 ldr r3, [r2, #64] @ 0x40
  13798. 800628c: f023 031e bic.w r3, r3, #30
  13799. 8006290: f043 0316 orr.w r3, r3, #22
  13800. 8006294: 6413 str r3, [r2, #64] @ 0x40
  13801. if(hdma->XferHalfCpltCallback != NULL)
  13802. 8006296: 2900 cmp r1, #0
  13803. 8006298: f47f aee7 bne.w 800606a <HAL_DMA_Start_IT+0x4ae>
  13804. 800629c: e5a2 b.n 8005de4 <HAL_DMA_Start_IT+0x228>
  13805. __HAL_DMA_DISABLE(hdma);
  13806. 800629e: f8df 80d0 ldr.w r8, [pc, #208] @ 8006370 <HAL_DMA_Start_IT+0x7b4>
  13807. 80062a2: f8d8 c040 ldr.w ip, [r8, #64] @ 0x40
  13808. 80062a6: f02c 0c01 bic.w ip, ip, #1
  13809. 80062aa: f8c8 c040 str.w ip, [r8, #64] @ 0x40
  13810. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13811. 80062ae: e5fb b.n 8005ea8 <HAL_DMA_Start_IT+0x2ec>
  13812. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13813. 80062b0: 4a2f ldr r2, [pc, #188] @ (8006370 <HAL_DMA_Start_IT+0x7b4>)
  13814. 80062b2: 6d93 ldr r3, [r2, #88] @ 0x58
  13815. 80062b4: f023 031e bic.w r3, r3, #30
  13816. 80062b8: f043 0316 orr.w r3, r3, #22
  13817. 80062bc: 6593 str r3, [r2, #88] @ 0x58
  13818. if(hdma->XferHalfCpltCallback != NULL)
  13819. 80062be: 2900 cmp r1, #0
  13820. 80062c0: f47f aed3 bne.w 800606a <HAL_DMA_Start_IT+0x4ae>
  13821. 80062c4: e58e b.n 8005de4 <HAL_DMA_Start_IT+0x228>
  13822. __HAL_DMA_DISABLE(hdma);
  13823. 80062c6: f8df 80a8 ldr.w r8, [pc, #168] @ 8006370 <HAL_DMA_Start_IT+0x7b4>
  13824. 80062ca: f8d8 c058 ldr.w ip, [r8, #88] @ 0x58
  13825. 80062ce: f02c 0c01 bic.w ip, ip, #1
  13826. 80062d2: f8c8 c058 str.w ip, [r8, #88] @ 0x58
  13827. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13828. 80062d6: e5e2 b.n 8005e9e <HAL_DMA_Start_IT+0x2e2>
  13829. __HAL_DMA_DISABLE(hdma);
  13830. 80062d8: f8df 8094 ldr.w r8, [pc, #148] @ 8006370 <HAL_DMA_Start_IT+0x7b4>
  13831. 80062dc: f8d8 c070 ldr.w ip, [r8, #112] @ 0x70
  13832. 80062e0: f02c 0c01 bic.w ip, ip, #1
  13833. 80062e4: f8c8 c070 str.w ip, [r8, #112] @ 0x70
  13834. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13835. 80062e8: e784 b.n 80061f4 <HAL_DMA_Start_IT+0x638>
  13836. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13837. 80062ea: 4a21 ldr r2, [pc, #132] @ (8006370 <HAL_DMA_Start_IT+0x7b4>)
  13838. 80062ec: 6f13 ldr r3, [r2, #112] @ 0x70
  13839. 80062ee: f023 031e bic.w r3, r3, #30
  13840. 80062f2: f043 0316 orr.w r3, r3, #22
  13841. 80062f6: 6713 str r3, [r2, #112] @ 0x70
  13842. if(hdma->XferHalfCpltCallback != NULL)
  13843. 80062f8: 2900 cmp r1, #0
  13844. 80062fa: f47f aeb6 bne.w 800606a <HAL_DMA_Start_IT+0x4ae>
  13845. 80062fe: e571 b.n 8005de4 <HAL_DMA_Start_IT+0x228>
  13846. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13847. 8006300: e9d0 6719 ldrd r6, r7, [r0, #100] @ 0x64
  13848. if(hdma->DMAmuxRequestGen != 0U)
  13849. 8006304: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c
  13850. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  13851. 8006308: 6077 str r7, [r6, #4]
  13852. if(hdma->DMAmuxRequestGen != 0U)
  13853. 800630a: f1bc 0f00 cmp.w ip, #0
  13854. 800630e: f47f add4 bne.w 8005eba <HAL_DMA_Start_IT+0x2fe>
  13855. 8006312: e61a b.n 8005f4a <HAL_DMA_Start_IT+0x38e>
  13856. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13857. 8006314: 4a16 ldr r2, [pc, #88] @ (8006370 <HAL_DMA_Start_IT+0x7b4>)
  13858. 8006316: f8d2 3088 ldr.w r3, [r2, #136] @ 0x88
  13859. 800631a: f023 031e bic.w r3, r3, #30
  13860. 800631e: f043 0316 orr.w r3, r3, #22
  13861. 8006322: f8c2 3088 str.w r3, [r2, #136] @ 0x88
  13862. if(hdma->XferHalfCpltCallback != NULL)
  13863. 8006326: 2900 cmp r1, #0
  13864. 8006328: f47f ae9f bne.w 800606a <HAL_DMA_Start_IT+0x4ae>
  13865. 800632c: e55a b.n 8005de4 <HAL_DMA_Start_IT+0x228>
  13866. __HAL_DMA_DISABLE(hdma);
  13867. 800632e: f8df 8040 ldr.w r8, [pc, #64] @ 8006370 <HAL_DMA_Start_IT+0x7b4>
  13868. 8006332: f8d8 c088 ldr.w ip, [r8, #136] @ 0x88
  13869. 8006336: f02c 0c01 bic.w ip, ip, #1
  13870. 800633a: f8c8 c088 str.w ip, [r8, #136] @ 0x88
  13871. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13872. 800633e: e5ae b.n 8005e9e <HAL_DMA_Start_IT+0x2e2>
  13873. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13874. 8006340: 4a0b ldr r2, [pc, #44] @ (8006370 <HAL_DMA_Start_IT+0x7b4>)
  13875. 8006342: f8d2 30a0 ldr.w r3, [r2, #160] @ 0xa0
  13876. 8006346: f023 031e bic.w r3, r3, #30
  13877. 800634a: f043 0316 orr.w r3, r3, #22
  13878. 800634e: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0
  13879. if(hdma->XferHalfCpltCallback != NULL)
  13880. 8006352: 2900 cmp r1, #0
  13881. 8006354: f47f ae89 bne.w 800606a <HAL_DMA_Start_IT+0x4ae>
  13882. 8006358: e544 b.n 8005de4 <HAL_DMA_Start_IT+0x228>
  13883. __HAL_DMA_DISABLE(hdma);
  13884. 800635a: f8df 8014 ldr.w r8, [pc, #20] @ 8006370 <HAL_DMA_Start_IT+0x7b4>
  13885. 800635e: f8d8 c0a0 ldr.w ip, [r8, #160] @ 0xa0
  13886. 8006362: f02c 0c01 bic.w ip, ip, #1
  13887. 8006366: f8c8 c0a0 str.w ip, [r8, #160] @ 0xa0
  13888. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13889. 800636a: e734 b.n 80061d6 <HAL_DMA_Start_IT+0x61a>
  13890. 800636c: 40020000 .word 0x40020000
  13891. 8006370: 40020400 .word 0x40020400
  13892. 8006374: 40020088 .word 0x40020088
  13893. 8006378: 40020458 .word 0x40020458
  13894. 800637c: 400200a0 .word 0x400200a0
  13895. 8006380: 400204b8 .word 0x400204b8
  13896. 8006384: 58025408 .word 0x58025408
  13897. 8006388: 5802541c .word 0x5802541c
  13898. 800638c: 58025494 .word 0x58025494
  13899. 8006390: 40020410 .word 0x40020410
  13900. 8006394: 40020470 .word 0x40020470
  13901. MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
  13902. 8006398: 4a0c ldr r2, [pc, #48] @ (80063cc <HAL_DMA_Start_IT+0x810>)
  13903. 800639a: f8d2 30b8 ldr.w r3, [r2, #184] @ 0xb8
  13904. 800639e: f023 031e bic.w r3, r3, #30
  13905. 80063a2: f043 0316 orr.w r3, r3, #22
  13906. 80063a6: f8c2 30b8 str.w r3, [r2, #184] @ 0xb8
  13907. if(hdma->XferHalfCpltCallback != NULL)
  13908. 80063aa: 2900 cmp r1, #0
  13909. 80063ac: f47f ae5d bne.w 800606a <HAL_DMA_Start_IT+0x4ae>
  13910. 80063b0: e518 b.n 8005de4 <HAL_DMA_Start_IT+0x228>
  13911. __HAL_DMA_DISABLE(hdma);
  13912. 80063b2: f8df 8018 ldr.w r8, [pc, #24] @ 80063cc <HAL_DMA_Start_IT+0x810>
  13913. 80063b6: f8d8 c0b8 ldr.w ip, [r8, #184] @ 0xb8
  13914. 80063ba: f02c 0c01 bic.w ip, ip, #1
  13915. 80063be: f8c8 c0b8 str.w ip, [r8, #184] @ 0xb8
  13916. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13917. 80063c2: e708 b.n 80061d6 <HAL_DMA_Start_IT+0x61a>
  13918. ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
  13919. 80063c4: 60a2 str r2, [r4, #8]
  13920. ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
  13921. 80063c6: 60e1 str r1, [r4, #12]
  13922. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  13923. 80063c8: 6c03 ldr r3, [r0, #64] @ 0x40
  13924. 80063ca: e46e b.n 8005caa <HAL_DMA_Start_IT+0xee>
  13925. 80063cc: 40020400 .word 0x40020400
  13926. 080063d0 <HAL_DMA_Abort>:
  13927. {
  13928. 80063d0: b570 push {r4, r5, r6, lr}
  13929. 80063d2: 4604 mov r4, r0
  13930. uint32_t tickstart = HAL_GetTick();
  13931. 80063d4: f7fd fdfc bl 8003fd0 <HAL_GetTick>
  13932. if(hdma == NULL)
  13933. 80063d8: 2c00 cmp r4, #0
  13934. 80063da: d06b beq.n 80064b4 <HAL_DMA_Abort+0xe4>
  13935. if(hdma->State != HAL_DMA_STATE_BUSY)
  13936. 80063dc: f894 3035 ldrb.w r3, [r4, #53] @ 0x35
  13937. 80063e0: 2b02 cmp r3, #2
  13938. 80063e2: d162 bne.n 80064aa <HAL_DMA_Abort+0xda>
  13939. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  13940. 80063e4: 6825 ldr r5, [r4, #0]
  13941. 80063e6: 4606 mov r6, r0
  13942. 80063e8: 4ba2 ldr r3, [pc, #648] @ (8006674 <HAL_DMA_Abort+0x2a4>)
  13943. 80063ea: 429d cmp r5, r3
  13944. 80063ec: d064 beq.n 80064b8 <HAL_DMA_Abort+0xe8>
  13945. 80063ee: 3318 adds r3, #24
  13946. 80063f0: 429d cmp r5, r3
  13947. 80063f2: d061 beq.n 80064b8 <HAL_DMA_Abort+0xe8>
  13948. 80063f4: 3318 adds r3, #24
  13949. 80063f6: 429d cmp r5, r3
  13950. 80063f8: f000 80f1 beq.w 80065de <HAL_DMA_Abort+0x20e>
  13951. 80063fc: 3318 adds r3, #24
  13952. 80063fe: 429d cmp r5, r3
  13953. 8006400: f000 8118 beq.w 8006634 <HAL_DMA_Abort+0x264>
  13954. 8006404: 3318 adds r3, #24
  13955. 8006406: 429d cmp r5, r3
  13956. 8006408: f000 8123 beq.w 8006652 <HAL_DMA_Abort+0x282>
  13957. 800640c: 3318 adds r3, #24
  13958. 800640e: 429d cmp r5, r3
  13959. 8006410: f000 80fd beq.w 800660e <HAL_DMA_Abort+0x23e>
  13960. 8006414: 3318 adds r3, #24
  13961. 8006416: 429d cmp r5, r3
  13962. 8006418: f000 8138 beq.w 800668c <HAL_DMA_Abort+0x2bc>
  13963. 800641c: 3318 adds r3, #24
  13964. 800641e: 429d cmp r5, r3
  13965. 8006420: f000 8147 beq.w 80066b2 <HAL_DMA_Abort+0x2e2>
  13966. 8006424: f503 7356 add.w r3, r3, #856 @ 0x358
  13967. 8006428: 429d cmp r5, r3
  13968. 800642a: f000 8155 beq.w 80066d8 <HAL_DMA_Abort+0x308>
  13969. 800642e: 3318 adds r3, #24
  13970. 8006430: 429d cmp r5, r3
  13971. 8006432: f000 8160 beq.w 80066f6 <HAL_DMA_Abort+0x326>
  13972. 8006436: 3318 adds r3, #24
  13973. 8006438: 429d cmp r5, r3
  13974. 800643a: f000 816b beq.w 8006714 <HAL_DMA_Abort+0x344>
  13975. 800643e: 3318 adds r3, #24
  13976. 8006440: 429d cmp r5, r3
  13977. 8006442: f000 8169 beq.w 8006718 <HAL_DMA_Abort+0x348>
  13978. 8006446: 3318 adds r3, #24
  13979. 8006448: 429d cmp r5, r3
  13980. 800644a: f000 8167 beq.w 800671c <HAL_DMA_Abort+0x34c>
  13981. 800644e: 3318 adds r3, #24
  13982. 8006450: 429d cmp r5, r3
  13983. 8006452: f000 8165 beq.w 8006720 <HAL_DMA_Abort+0x350>
  13984. 8006456: 3318 adds r3, #24
  13985. 8006458: 429d cmp r5, r3
  13986. 800645a: f000 8165 beq.w 8006728 <HAL_DMA_Abort+0x358>
  13987. 800645e: 3318 adds r3, #24
  13988. 8006460: 429d cmp r5, r3
  13989. 8006462: f000 815f beq.w 8006724 <HAL_DMA_Abort+0x354>
  13990. ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
  13991. 8006466: 682b ldr r3, [r5, #0]
  13992. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13993. 8006468: 4a83 ldr r2, [pc, #524] @ (8006678 <HAL_DMA_Abort+0x2a8>)
  13994. ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
  13995. 800646a: f023 030e bic.w r3, r3, #14
  13996. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  13997. 800646e: 4295 cmp r5, r2
  13998. ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
  13999. 8006470: 602b str r3, [r5, #0]
  14000. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  14001. 8006472: d014 beq.n 800649e <HAL_DMA_Abort+0xce>
  14002. 8006474: 4b81 ldr r3, [pc, #516] @ (800667c <HAL_DMA_Abort+0x2ac>)
  14003. 8006476: 429d cmp r5, r3
  14004. 8006478: d011 beq.n 800649e <HAL_DMA_Abort+0xce>
  14005. 800647a: 3314 adds r3, #20
  14006. 800647c: 429d cmp r5, r3
  14007. 800647e: d00e beq.n 800649e <HAL_DMA_Abort+0xce>
  14008. 8006480: 3314 adds r3, #20
  14009. 8006482: 429d cmp r5, r3
  14010. 8006484: d00b beq.n 800649e <HAL_DMA_Abort+0xce>
  14011. 8006486: 3314 adds r3, #20
  14012. 8006488: 429d cmp r5, r3
  14013. 800648a: d008 beq.n 800649e <HAL_DMA_Abort+0xce>
  14014. 800648c: 3314 adds r3, #20
  14015. 800648e: 429d cmp r5, r3
  14016. 8006490: d005 beq.n 800649e <HAL_DMA_Abort+0xce>
  14017. 8006492: 3314 adds r3, #20
  14018. 8006494: 429d cmp r5, r3
  14019. 8006496: d002 beq.n 800649e <HAL_DMA_Abort+0xce>
  14020. 8006498: 3314 adds r3, #20
  14021. 800649a: 429d cmp r5, r3
  14022. 800649c: d119 bne.n 80064d2 <HAL_DMA_Abort+0x102>
  14023. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14024. 800649e: 6e22 ldr r2, [r4, #96] @ 0x60
  14025. 80064a0: 6813 ldr r3, [r2, #0]
  14026. 80064a2: f423 7380 bic.w r3, r3, #256 @ 0x100
  14027. 80064a6: 6013 str r3, [r2, #0]
  14028. __HAL_DMA_DISABLE(hdma);
  14029. 80064a8: e013 b.n 80064d2 <HAL_DMA_Abort+0x102>
  14030. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  14031. 80064aa: 2280 movs r2, #128 @ 0x80
  14032. __HAL_UNLOCK(hdma);
  14033. 80064ac: 2300 movs r3, #0
  14034. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  14035. 80064ae: 6562 str r2, [r4, #84] @ 0x54
  14036. __HAL_UNLOCK(hdma);
  14037. 80064b0: f884 3034 strb.w r3, [r4, #52] @ 0x34
  14038. return HAL_ERROR;
  14039. 80064b4: 2001 movs r0, #1
  14040. }
  14041. 80064b6: bd70 pop {r4, r5, r6, pc}
  14042. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
  14043. 80064b8: 682b ldr r3, [r5, #0]
  14044. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14045. 80064ba: 6e22 ldr r2, [r4, #96] @ 0x60
  14046. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
  14047. 80064bc: f023 031e bic.w r3, r3, #30
  14048. 80064c0: 602b str r3, [r5, #0]
  14049. ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
  14050. 80064c2: 696b ldr r3, [r5, #20]
  14051. 80064c4: f023 0380 bic.w r3, r3, #128 @ 0x80
  14052. 80064c8: 616b str r3, [r5, #20]
  14053. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14054. 80064ca: 6813 ldr r3, [r2, #0]
  14055. 80064cc: f423 7380 bic.w r3, r3, #256 @ 0x100
  14056. 80064d0: 6013 str r3, [r2, #0]
  14057. __HAL_DMA_DISABLE(hdma);
  14058. 80064d2: 682b ldr r3, [r5, #0]
  14059. 80064d4: f023 0301 bic.w r3, r3, #1
  14060. 80064d8: 602b str r3, [r5, #0]
  14061. 80064da: e005 b.n 80064e8 <HAL_DMA_Abort+0x118>
  14062. if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
  14063. 80064dc: f7fd fd78 bl 8003fd0 <HAL_GetTick>
  14064. 80064e0: 1b83 subs r3, r0, r6
  14065. 80064e2: 2b05 cmp r3, #5
  14066. 80064e4: f200 808a bhi.w 80065fc <HAL_DMA_Abort+0x22c>
  14067. while(((*enableRegister) & DMA_SxCR_EN) != 0U)
  14068. 80064e8: 682b ldr r3, [r5, #0]
  14069. 80064ea: 07db lsls r3, r3, #31
  14070. 80064ec: d4f6 bmi.n 80064dc <HAL_DMA_Abort+0x10c>
  14071. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  14072. 80064ee: 6823 ldr r3, [r4, #0]
  14073. 80064f0: 4960 ldr r1, [pc, #384] @ (8006674 <HAL_DMA_Abort+0x2a4>)
  14074. regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
  14075. 80064f2: 6de2 ldr r2, [r4, #92] @ 0x5c
  14076. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  14077. 80064f4: 428b cmp r3, r1
  14078. regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
  14079. 80064f6: 6da0 ldr r0, [r4, #88] @ 0x58
  14080. regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
  14081. 80064f8: f002 021f and.w r2, r2, #31
  14082. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  14083. 80064fc: d05e beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14084. 80064fe: 3118 adds r1, #24
  14085. 8006500: 428b cmp r3, r1
  14086. 8006502: d05b beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14087. 8006504: 3118 adds r1, #24
  14088. 8006506: 428b cmp r3, r1
  14089. 8006508: d058 beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14090. 800650a: 3118 adds r1, #24
  14091. 800650c: 428b cmp r3, r1
  14092. 800650e: d055 beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14093. 8006510: 3118 adds r1, #24
  14094. 8006512: 428b cmp r3, r1
  14095. 8006514: d052 beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14096. 8006516: 3118 adds r1, #24
  14097. 8006518: 428b cmp r3, r1
  14098. 800651a: d04f beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14099. 800651c: 3118 adds r1, #24
  14100. 800651e: 428b cmp r3, r1
  14101. 8006520: d04c beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14102. 8006522: 3118 adds r1, #24
  14103. 8006524: 428b cmp r3, r1
  14104. 8006526: d049 beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14105. 8006528: f501 7156 add.w r1, r1, #856 @ 0x358
  14106. 800652c: 428b cmp r3, r1
  14107. 800652e: d045 beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14108. 8006530: 3118 adds r1, #24
  14109. 8006532: 428b cmp r3, r1
  14110. 8006534: d042 beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14111. 8006536: 3118 adds r1, #24
  14112. 8006538: 428b cmp r3, r1
  14113. 800653a: d03f beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14114. 800653c: 3118 adds r1, #24
  14115. 800653e: 428b cmp r3, r1
  14116. 8006540: d03c beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14117. 8006542: 3118 adds r1, #24
  14118. 8006544: 428b cmp r3, r1
  14119. 8006546: d039 beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14120. 8006548: 3118 adds r1, #24
  14121. 800654a: 428b cmp r3, r1
  14122. 800654c: d036 beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14123. 800654e: 3118 adds r1, #24
  14124. 8006550: 428b cmp r3, r1
  14125. 8006552: d033 beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14126. 8006554: 3118 adds r1, #24
  14127. 8006556: 428b cmp r3, r1
  14128. 8006558: d030 beq.n 80065bc <HAL_DMA_Abort+0x1ec>
  14129. regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
  14130. 800655a: 2101 movs r1, #1
  14131. 800655c: 4091 lsls r1, r2
  14132. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  14133. 800655e: 4a47 ldr r2, [pc, #284] @ (800667c <HAL_DMA_Abort+0x2ac>)
  14134. regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
  14135. 8006560: 6041 str r1, [r0, #4]
  14136. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  14137. 8006562: 4845 ldr r0, [pc, #276] @ (8006678 <HAL_DMA_Abort+0x2a8>)
  14138. 8006564: 4946 ldr r1, [pc, #280] @ (8006680 <HAL_DMA_Abort+0x2b0>)
  14139. 8006566: 4283 cmp r3, r0
  14140. 8006568: bf18 it ne
  14141. 800656a: 4293 cmpne r3, r2
  14142. 800656c: f100 003c add.w r0, r0, #60 @ 0x3c
  14143. 8006570: bf0c ite eq
  14144. 8006572: 2201 moveq r2, #1
  14145. 8006574: 2200 movne r2, #0
  14146. 8006576: 428b cmp r3, r1
  14147. 8006578: bf08 it eq
  14148. 800657a: f042 0201 orreq.w r2, r2, #1
  14149. 800657e: 3128 adds r1, #40 @ 0x28
  14150. 8006580: 4283 cmp r3, r0
  14151. 8006582: bf08 it eq
  14152. 8006584: f042 0201 orreq.w r2, r2, #1
  14153. 8006588: 3028 adds r0, #40 @ 0x28
  14154. 800658a: 428b cmp r3, r1
  14155. 800658c: bf08 it eq
  14156. 800658e: f042 0201 orreq.w r2, r2, #1
  14157. 8006592: 3128 adds r1, #40 @ 0x28
  14158. 8006594: 4283 cmp r3, r0
  14159. 8006596: bf08 it eq
  14160. 8006598: f042 0201 orreq.w r2, r2, #1
  14161. 800659c: 428b cmp r3, r1
  14162. 800659e: bf08 it eq
  14163. 80065a0: f042 0201 orreq.w r2, r2, #1
  14164. 80065a4: b96a cbnz r2, 80065c2 <HAL_DMA_Abort+0x1f2>
  14165. 80065a6: 4a37 ldr r2, [pc, #220] @ (8006684 <HAL_DMA_Abort+0x2b4>)
  14166. 80065a8: 4293 cmp r3, r2
  14167. 80065aa: d00a beq.n 80065c2 <HAL_DMA_Abort+0x1f2>
  14168. __HAL_UNLOCK(hdma);
  14169. 80065ac: 2300 movs r3, #0
  14170. hdma->State = HAL_DMA_STATE_READY;
  14171. 80065ae: 2201 movs r2, #1
  14172. return HAL_OK;
  14173. 80065b0: 4618 mov r0, r3
  14174. hdma->State = HAL_DMA_STATE_READY;
  14175. 80065b2: f884 2035 strb.w r2, [r4, #53] @ 0x35
  14176. __HAL_UNLOCK(hdma);
  14177. 80065b6: f884 3034 strb.w r3, [r4, #52] @ 0x34
  14178. }
  14179. 80065ba: bd70 pop {r4, r5, r6, pc}
  14180. regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
  14181. 80065bc: 233f movs r3, #63 @ 0x3f
  14182. 80065be: 4093 lsls r3, r2
  14183. 80065c0: 6083 str r3, [r0, #8]
  14184. if(hdma->DMAmuxRequestGen != 0U)
  14185. 80065c2: 6ee3 ldr r3, [r4, #108] @ 0x6c
  14186. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  14187. 80065c4: e9d4 2119 ldrd r2, r1, [r4, #100] @ 0x64
  14188. 80065c8: 6051 str r1, [r2, #4]
  14189. if(hdma->DMAmuxRequestGen != 0U)
  14190. 80065ca: 2b00 cmp r3, #0
  14191. 80065cc: d0ee beq.n 80065ac <HAL_DMA_Abort+0x1dc>
  14192. hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
  14193. 80065ce: 681a ldr r2, [r3, #0]
  14194. hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
  14195. 80065d0: e9d4 101c ldrd r1, r0, [r4, #112] @ 0x70
  14196. hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
  14197. 80065d4: f422 7280 bic.w r2, r2, #256 @ 0x100
  14198. 80065d8: 601a str r2, [r3, #0]
  14199. hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
  14200. 80065da: 6048 str r0, [r1, #4]
  14201. 80065dc: e7e6 b.n 80065ac <HAL_DMA_Abort+0x1dc>
  14202. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
  14203. 80065de: 4b2a ldr r3, [pc, #168] @ (8006688 <HAL_DMA_Abort+0x2b8>)
  14204. 80065e0: 6c1a ldr r2, [r3, #64] @ 0x40
  14205. 80065e2: f022 021e bic.w r2, r2, #30
  14206. 80065e6: 641a str r2, [r3, #64] @ 0x40
  14207. ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
  14208. 80065e8: 6d5a ldr r2, [r3, #84] @ 0x54
  14209. 80065ea: f022 0280 bic.w r2, r2, #128 @ 0x80
  14210. 80065ee: 655a str r2, [r3, #84] @ 0x54
  14211. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14212. 80065f0: 6e22 ldr r2, [r4, #96] @ 0x60
  14213. 80065f2: 6813 ldr r3, [r2, #0]
  14214. 80065f4: f423 7380 bic.w r3, r3, #256 @ 0x100
  14215. 80065f8: 6013 str r3, [r2, #0]
  14216. __HAL_DMA_DISABLE(hdma);
  14217. 80065fa: e76a b.n 80064d2 <HAL_DMA_Abort+0x102>
  14218. hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
  14219. 80065fc: 2120 movs r1, #32
  14220. hdma->State = HAL_DMA_STATE_ERROR;
  14221. 80065fe: 2203 movs r2, #3
  14222. __HAL_UNLOCK(hdma);
  14223. 8006600: 2300 movs r3, #0
  14224. hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
  14225. 8006602: 6561 str r1, [r4, #84] @ 0x54
  14226. __HAL_UNLOCK(hdma);
  14227. 8006604: f884 3034 strb.w r3, [r4, #52] @ 0x34
  14228. hdma->State = HAL_DMA_STATE_ERROR;
  14229. 8006608: f884 2035 strb.w r2, [r4, #53] @ 0x35
  14230. return HAL_ERROR;
  14231. 800660c: e752 b.n 80064b4 <HAL_DMA_Abort+0xe4>
  14232. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
  14233. 800660e: 4b1e ldr r3, [pc, #120] @ (8006688 <HAL_DMA_Abort+0x2b8>)
  14234. 8006610: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88
  14235. 8006614: f022 021e bic.w r2, r2, #30
  14236. 8006618: f8c3 2088 str.w r2, [r3, #136] @ 0x88
  14237. ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
  14238. 800661c: f8d3 209c ldr.w r2, [r3, #156] @ 0x9c
  14239. 8006620: f022 0280 bic.w r2, r2, #128 @ 0x80
  14240. 8006624: f8c3 209c str.w r2, [r3, #156] @ 0x9c
  14241. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14242. 8006628: 6e22 ldr r2, [r4, #96] @ 0x60
  14243. 800662a: 6813 ldr r3, [r2, #0]
  14244. 800662c: f423 7380 bic.w r3, r3, #256 @ 0x100
  14245. 8006630: 6013 str r3, [r2, #0]
  14246. __HAL_DMA_DISABLE(hdma);
  14247. 8006632: e74e b.n 80064d2 <HAL_DMA_Abort+0x102>
  14248. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
  14249. 8006634: 4b14 ldr r3, [pc, #80] @ (8006688 <HAL_DMA_Abort+0x2b8>)
  14250. 8006636: 6d9a ldr r2, [r3, #88] @ 0x58
  14251. 8006638: f022 021e bic.w r2, r2, #30
  14252. 800663c: 659a str r2, [r3, #88] @ 0x58
  14253. ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
  14254. 800663e: 6eda ldr r2, [r3, #108] @ 0x6c
  14255. 8006640: f022 0280 bic.w r2, r2, #128 @ 0x80
  14256. 8006644: 66da str r2, [r3, #108] @ 0x6c
  14257. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14258. 8006646: 6e22 ldr r2, [r4, #96] @ 0x60
  14259. 8006648: 6813 ldr r3, [r2, #0]
  14260. 800664a: f423 7380 bic.w r3, r3, #256 @ 0x100
  14261. 800664e: 6013 str r3, [r2, #0]
  14262. __HAL_DMA_DISABLE(hdma);
  14263. 8006650: e73f b.n 80064d2 <HAL_DMA_Abort+0x102>
  14264. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
  14265. 8006652: 4b0d ldr r3, [pc, #52] @ (8006688 <HAL_DMA_Abort+0x2b8>)
  14266. 8006654: 6f1a ldr r2, [r3, #112] @ 0x70
  14267. 8006656: f022 021e bic.w r2, r2, #30
  14268. 800665a: 671a str r2, [r3, #112] @ 0x70
  14269. ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
  14270. 800665c: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84
  14271. 8006660: f022 0280 bic.w r2, r2, #128 @ 0x80
  14272. 8006664: f8c3 2084 str.w r2, [r3, #132] @ 0x84
  14273. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14274. 8006668: 6e22 ldr r2, [r4, #96] @ 0x60
  14275. 800666a: 6813 ldr r3, [r2, #0]
  14276. 800666c: f423 7380 bic.w r3, r3, #256 @ 0x100
  14277. 8006670: 6013 str r3, [r2, #0]
  14278. __HAL_DMA_DISABLE(hdma);
  14279. 8006672: e72e b.n 80064d2 <HAL_DMA_Abort+0x102>
  14280. 8006674: 40020010 .word 0x40020010
  14281. 8006678: 58025408 .word 0x58025408
  14282. 800667c: 5802541c .word 0x5802541c
  14283. 8006680: 58025430 .word 0x58025430
  14284. 8006684: 58025494 .word 0x58025494
  14285. 8006688: 40020000 .word 0x40020000
  14286. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
  14287. 800668c: 4b27 ldr r3, [pc, #156] @ (800672c <HAL_DMA_Abort+0x35c>)
  14288. 800668e: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0
  14289. 8006692: f022 021e bic.w r2, r2, #30
  14290. 8006696: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0
  14291. ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
  14292. 800669a: f8d3 20b4 ldr.w r2, [r3, #180] @ 0xb4
  14293. 800669e: f022 0280 bic.w r2, r2, #128 @ 0x80
  14294. 80066a2: f8c3 20b4 str.w r2, [r3, #180] @ 0xb4
  14295. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14296. 80066a6: 6e22 ldr r2, [r4, #96] @ 0x60
  14297. 80066a8: 6813 ldr r3, [r2, #0]
  14298. 80066aa: f423 7380 bic.w r3, r3, #256 @ 0x100
  14299. 80066ae: 6013 str r3, [r2, #0]
  14300. __HAL_DMA_DISABLE(hdma);
  14301. 80066b0: e70f b.n 80064d2 <HAL_DMA_Abort+0x102>
  14302. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
  14303. 80066b2: 4b1e ldr r3, [pc, #120] @ (800672c <HAL_DMA_Abort+0x35c>)
  14304. 80066b4: f8d3 20b8 ldr.w r2, [r3, #184] @ 0xb8
  14305. 80066b8: f022 021e bic.w r2, r2, #30
  14306. 80066bc: f8c3 20b8 str.w r2, [r3, #184] @ 0xb8
  14307. ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
  14308. 80066c0: f8d3 20cc ldr.w r2, [r3, #204] @ 0xcc
  14309. 80066c4: f022 0280 bic.w r2, r2, #128 @ 0x80
  14310. 80066c8: f8c3 20cc str.w r2, [r3, #204] @ 0xcc
  14311. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14312. 80066cc: 6e22 ldr r2, [r4, #96] @ 0x60
  14313. 80066ce: 6813 ldr r3, [r2, #0]
  14314. 80066d0: f423 7380 bic.w r3, r3, #256 @ 0x100
  14315. 80066d4: 6013 str r3, [r2, #0]
  14316. __HAL_DMA_DISABLE(hdma);
  14317. 80066d6: e6fc b.n 80064d2 <HAL_DMA_Abort+0x102>
  14318. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
  14319. 80066d8: 4b15 ldr r3, [pc, #84] @ (8006730 <HAL_DMA_Abort+0x360>)
  14320. 80066da: 691a ldr r2, [r3, #16]
  14321. 80066dc: f022 021e bic.w r2, r2, #30
  14322. 80066e0: 611a str r2, [r3, #16]
  14323. ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
  14324. 80066e2: 6a5a ldr r2, [r3, #36] @ 0x24
  14325. 80066e4: f022 0280 bic.w r2, r2, #128 @ 0x80
  14326. 80066e8: 625a str r2, [r3, #36] @ 0x24
  14327. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14328. 80066ea: 6e22 ldr r2, [r4, #96] @ 0x60
  14329. 80066ec: 6813 ldr r3, [r2, #0]
  14330. 80066ee: f423 7380 bic.w r3, r3, #256 @ 0x100
  14331. 80066f2: 6013 str r3, [r2, #0]
  14332. __HAL_DMA_DISABLE(hdma);
  14333. 80066f4: e6ed b.n 80064d2 <HAL_DMA_Abort+0x102>
  14334. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
  14335. 80066f6: 4b0e ldr r3, [pc, #56] @ (8006730 <HAL_DMA_Abort+0x360>)
  14336. 80066f8: 6a9a ldr r2, [r3, #40] @ 0x28
  14337. 80066fa: f022 021e bic.w r2, r2, #30
  14338. 80066fe: 629a str r2, [r3, #40] @ 0x28
  14339. ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
  14340. 8006700: 6bda ldr r2, [r3, #60] @ 0x3c
  14341. 8006702: f022 0280 bic.w r2, r2, #128 @ 0x80
  14342. 8006706: 63da str r2, [r3, #60] @ 0x3c
  14343. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14344. 8006708: 6e22 ldr r2, [r4, #96] @ 0x60
  14345. 800670a: 6813 ldr r3, [r2, #0]
  14346. 800670c: f423 7380 bic.w r3, r3, #256 @ 0x100
  14347. 8006710: 6013 str r3, [r2, #0]
  14348. __HAL_DMA_DISABLE(hdma);
  14349. 8006712: e6de b.n 80064d2 <HAL_DMA_Abort+0x102>
  14350. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
  14351. 8006714: 4b06 ldr r3, [pc, #24] @ (8006730 <HAL_DMA_Abort+0x360>)
  14352. 8006716: e763 b.n 80065e0 <HAL_DMA_Abort+0x210>
  14353. 8006718: 4b05 ldr r3, [pc, #20] @ (8006730 <HAL_DMA_Abort+0x360>)
  14354. 800671a: e78c b.n 8006636 <HAL_DMA_Abort+0x266>
  14355. 800671c: 4b04 ldr r3, [pc, #16] @ (8006730 <HAL_DMA_Abort+0x360>)
  14356. 800671e: e799 b.n 8006654 <HAL_DMA_Abort+0x284>
  14357. 8006720: 4b03 ldr r3, [pc, #12] @ (8006730 <HAL_DMA_Abort+0x360>)
  14358. 8006722: e775 b.n 8006610 <HAL_DMA_Abort+0x240>
  14359. 8006724: 4b02 ldr r3, [pc, #8] @ (8006730 <HAL_DMA_Abort+0x360>)
  14360. 8006726: e7c5 b.n 80066b4 <HAL_DMA_Abort+0x2e4>
  14361. 8006728: 4b01 ldr r3, [pc, #4] @ (8006730 <HAL_DMA_Abort+0x360>)
  14362. 800672a: e7b0 b.n 800668e <HAL_DMA_Abort+0x2be>
  14363. 800672c: 40020000 .word 0x40020000
  14364. 8006730: 40020400 .word 0x40020400
  14365. 08006734 <HAL_DMA_Abort_IT>:
  14366. if(hdma == NULL)
  14367. 8006734: 2800 cmp r0, #0
  14368. 8006736: f000 8096 beq.w 8006866 <HAL_DMA_Abort_IT+0x132>
  14369. {
  14370. 800673a: b538 push {r3, r4, r5, lr}
  14371. if(hdma->State != HAL_DMA_STATE_BUSY)
  14372. 800673c: f890 3035 ldrb.w r3, [r0, #53] @ 0x35
  14373. 8006740: 2b02 cmp r3, #2
  14374. 8006742: f040 8083 bne.w 800684c <HAL_DMA_Abort_IT+0x118>
  14375. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  14376. 8006746: 6803 ldr r3, [r0, #0]
  14377. 8006748: 4a48 ldr r2, [pc, #288] @ (800686c <HAL_DMA_Abort_IT+0x138>)
  14378. 800674a: 4293 cmp r3, r2
  14379. 800674c: f000 8082 beq.w 8006854 <HAL_DMA_Abort_IT+0x120>
  14380. 8006750: 3218 adds r2, #24
  14381. 8006752: 4293 cmp r3, r2
  14382. 8006754: d07e beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14383. 8006756: 3218 adds r2, #24
  14384. 8006758: 4293 cmp r3, r2
  14385. 800675a: d07b beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14386. 800675c: 3218 adds r2, #24
  14387. 800675e: 4293 cmp r3, r2
  14388. 8006760: d078 beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14389. 8006762: 3218 adds r2, #24
  14390. 8006764: 4293 cmp r3, r2
  14391. 8006766: d075 beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14392. 8006768: 3218 adds r2, #24
  14393. 800676a: 4293 cmp r3, r2
  14394. 800676c: d072 beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14395. 800676e: 3218 adds r2, #24
  14396. 8006770: 4293 cmp r3, r2
  14397. 8006772: d06f beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14398. 8006774: 3218 adds r2, #24
  14399. 8006776: 4293 cmp r3, r2
  14400. 8006778: d06c beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14401. 800677a: f502 7256 add.w r2, r2, #856 @ 0x358
  14402. 800677e: 4293 cmp r3, r2
  14403. 8006780: d068 beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14404. 8006782: 3218 adds r2, #24
  14405. 8006784: 4293 cmp r3, r2
  14406. 8006786: d065 beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14407. 8006788: 3218 adds r2, #24
  14408. 800678a: 4293 cmp r3, r2
  14409. 800678c: d062 beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14410. 800678e: 3218 adds r2, #24
  14411. 8006790: 4293 cmp r3, r2
  14412. 8006792: d05f beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14413. 8006794: 3218 adds r2, #24
  14414. 8006796: 4293 cmp r3, r2
  14415. 8006798: d05c beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14416. 800679a: 3218 adds r2, #24
  14417. 800679c: 4293 cmp r3, r2
  14418. 800679e: d059 beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14419. 80067a0: 3218 adds r2, #24
  14420. 80067a2: 4293 cmp r3, r2
  14421. 80067a4: d056 beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14422. 80067a6: 3218 adds r2, #24
  14423. 80067a8: 4293 cmp r3, r2
  14424. 80067aa: d053 beq.n 8006854 <HAL_DMA_Abort_IT+0x120>
  14425. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  14426. 80067ac: 4a30 ldr r2, [pc, #192] @ (8006870 <HAL_DMA_Abort_IT+0x13c>)
  14427. 80067ae: 4d31 ldr r5, [pc, #196] @ (8006874 <HAL_DMA_Abort_IT+0x140>)
  14428. ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
  14429. 80067b0: 6819 ldr r1, [r3, #0]
  14430. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  14431. 80067b2: 42ab cmp r3, r5
  14432. 80067b4: bf18 it ne
  14433. 80067b6: 4293 cmpne r3, r2
  14434. 80067b8: 4c2f ldr r4, [pc, #188] @ (8006878 <HAL_DMA_Abort_IT+0x144>)
  14435. ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
  14436. 80067ba: f021 010e bic.w r1, r1, #14
  14437. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  14438. 80067be: f105 053c add.w r5, r5, #60 @ 0x3c
  14439. 80067c2: bf0c ite eq
  14440. 80067c4: 2201 moveq r2, #1
  14441. 80067c6: 2200 movne r2, #0
  14442. ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
  14443. 80067c8: 6019 str r1, [r3, #0]
  14444. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  14445. 80067ca: 42a3 cmp r3, r4
  14446. 80067cc: bf08 it eq
  14447. 80067ce: f042 0201 orreq.w r2, r2, #1
  14448. __HAL_DMA_DISABLE(hdma);
  14449. 80067d2: 6819 ldr r1, [r3, #0]
  14450. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  14451. 80067d4: 3428 adds r4, #40 @ 0x28
  14452. 80067d6: 42ab cmp r3, r5
  14453. 80067d8: bf08 it eq
  14454. 80067da: f042 0201 orreq.w r2, r2, #1
  14455. __HAL_DMA_DISABLE(hdma);
  14456. 80067de: f021 0101 bic.w r1, r1, #1
  14457. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  14458. 80067e2: 42a3 cmp r3, r4
  14459. 80067e4: bf08 it eq
  14460. 80067e6: f042 0201 orreq.w r2, r2, #1
  14461. 80067ea: 3414 adds r4, #20
  14462. __HAL_DMA_DISABLE(hdma);
  14463. 80067ec: 6019 str r1, [r3, #0]
  14464. if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
  14465. 80067ee: 42a3 cmp r3, r4
  14466. 80067f0: bf08 it eq
  14467. 80067f2: f042 0201 orreq.w r2, r2, #1
  14468. 80067f6: 4921 ldr r1, [pc, #132] @ (800687c <HAL_DMA_Abort_IT+0x148>)
  14469. 80067f8: 428b cmp r3, r1
  14470. 80067fa: bf08 it eq
  14471. 80067fc: f042 0201 orreq.w r2, r2, #1
  14472. 8006800: b912 cbnz r2, 8006808 <HAL_DMA_Abort_IT+0xd4>
  14473. 8006802: 4a1f ldr r2, [pc, #124] @ (8006880 <HAL_DMA_Abort_IT+0x14c>)
  14474. 8006804: 4293 cmp r3, r2
  14475. 8006806: d117 bne.n 8006838 <HAL_DMA_Abort_IT+0x104>
  14476. regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
  14477. 8006808: 2301 movs r3, #1
  14478. regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
  14479. 800680a: 6d84 ldr r4, [r0, #88] @ 0x58
  14480. regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
  14481. 800680c: e9d0 1517 ldrd r1, r5, [r0, #92] @ 0x5c
  14482. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14483. 8006810: 682a ldr r2, [r5, #0]
  14484. regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
  14485. 8006812: f001 011f and.w r1, r1, #31
  14486. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14487. 8006816: f422 7280 bic.w r2, r2, #256 @ 0x100
  14488. regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
  14489. 800681a: 408b lsls r3, r1
  14490. hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
  14491. 800681c: 602a str r2, [r5, #0]
  14492. regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
  14493. 800681e: 6063 str r3, [r4, #4]
  14494. if(hdma->DMAmuxRequestGen != 0U)
  14495. 8006820: 6ec3 ldr r3, [r0, #108] @ 0x6c
  14496. hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
  14497. 8006822: e9d0 2119 ldrd r2, r1, [r0, #100] @ 0x64
  14498. 8006826: 6051 str r1, [r2, #4]
  14499. if(hdma->DMAmuxRequestGen != 0U)
  14500. 8006828: b133 cbz r3, 8006838 <HAL_DMA_Abort_IT+0x104>
  14501. hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
  14502. 800682a: 681a ldr r2, [r3, #0]
  14503. hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
  14504. 800682c: e9d0 141c ldrd r1, r4, [r0, #112] @ 0x70
  14505. hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
  14506. 8006830: f422 7280 bic.w r2, r2, #256 @ 0x100
  14507. 8006834: 601a str r2, [r3, #0]
  14508. hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
  14509. 8006836: 604c str r4, [r1, #4]
  14510. hdma->State = HAL_DMA_STATE_READY;
  14511. 8006838: 2101 movs r1, #1
  14512. __HAL_UNLOCK(hdma);
  14513. 800683a: 2200 movs r2, #0
  14514. if(hdma->XferAbortCallback != NULL)
  14515. 800683c: 6d03 ldr r3, [r0, #80] @ 0x50
  14516. hdma->State = HAL_DMA_STATE_READY;
  14517. 800683e: f880 1035 strb.w r1, [r0, #53] @ 0x35
  14518. __HAL_UNLOCK(hdma);
  14519. 8006842: f880 2034 strb.w r2, [r0, #52] @ 0x34
  14520. if(hdma->XferAbortCallback != NULL)
  14521. 8006846: b163 cbz r3, 8006862 <HAL_DMA_Abort_IT+0x12e>
  14522. hdma->XferAbortCallback(hdma);
  14523. 8006848: 4798 blx r3
  14524. 800684a: e00a b.n 8006862 <HAL_DMA_Abort_IT+0x12e>
  14525. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  14526. 800684c: 2380 movs r3, #128 @ 0x80
  14527. 800684e: 6543 str r3, [r0, #84] @ 0x54
  14528. return HAL_ERROR;
  14529. 8006850: 2001 movs r0, #1
  14530. }
  14531. 8006852: bd38 pop {r3, r4, r5, pc}
  14532. hdma->State = HAL_DMA_STATE_ABORT;
  14533. 8006854: 2204 movs r2, #4
  14534. 8006856: f880 2035 strb.w r2, [r0, #53] @ 0x35
  14535. __HAL_DMA_DISABLE(hdma);
  14536. 800685a: 681a ldr r2, [r3, #0]
  14537. 800685c: f022 0201 bic.w r2, r2, #1
  14538. 8006860: 601a str r2, [r3, #0]
  14539. return HAL_OK;
  14540. 8006862: 2000 movs r0, #0
  14541. }
  14542. 8006864: bd38 pop {r3, r4, r5, pc}
  14543. return HAL_ERROR;
  14544. 8006866: 2001 movs r0, #1
  14545. }
  14546. 8006868: 4770 bx lr
  14547. 800686a: bf00 nop
  14548. 800686c: 40020010 .word 0x40020010
  14549. 8006870: 5802541c .word 0x5802541c
  14550. 8006874: 58025408 .word 0x58025408
  14551. 8006878: 58025430 .word 0x58025430
  14552. 800687c: 58025480 .word 0x58025480
  14553. 8006880: 58025494 .word 0x58025494
  14554. 08006884 <HAL_DMA_IRQHandler>:
  14555. {
  14556. 8006884: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  14557. __IO uint32_t count = 0U;
  14558. 8006888: 2200 movs r2, #0
  14559. uint32_t timeout = SystemCoreClock / 9600U;
  14560. 800688a: 4b46 ldr r3, [pc, #280] @ (80069a4 <HAL_DMA_IRQHandler+0x120>)
  14561. {
  14562. 800688c: b082 sub sp, #8
  14563. DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
  14564. 800688e: 6d84 ldr r4, [r0, #88] @ 0x58
  14565. {
  14566. 8006890: 4606 mov r6, r0
  14567. uint32_t timeout = SystemCoreClock / 9600U;
  14568. 8006892: 681d ldr r5, [r3, #0]
  14569. __IO uint32_t count = 0U;
  14570. 8006894: 9201 str r2, [sp, #4]
  14571. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  14572. 8006896: 6803 ldr r3, [r0, #0]
  14573. 8006898: 4a43 ldr r2, [pc, #268] @ (80069a8 <HAL_DMA_IRQHandler+0x124>)
  14574. 800689a: 4844 ldr r0, [pc, #272] @ (80069ac <HAL_DMA_IRQHandler+0x128>)
  14575. tmpisr_dma = regs_dma->ISR;
  14576. 800689c: 6827 ldr r7, [r4, #0]
  14577. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  14578. 800689e: 4293 cmp r3, r2
  14579. 80068a0: bf18 it ne
  14580. 80068a2: 4283 cmpne r3, r0
  14581. tmpisr_bdma = regs_bdma->ISR;
  14582. 80068a4: 6821 ldr r1, [r4, #0]
  14583. if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
  14584. 80068a6: bf0c ite eq
  14585. 80068a8: 2001 moveq r0, #1
  14586. 80068aa: 2000 movne r0, #0
  14587. 80068ac: f000 8086 beq.w 80069bc <HAL_DMA_IRQHandler+0x138>
  14588. 80068b0: 3218 adds r2, #24
  14589. 80068b2: 4293 cmp r3, r2
  14590. 80068b4: f000 827c beq.w 8006db0 <HAL_DMA_IRQHandler+0x52c>
  14591. 80068b8: 3218 adds r2, #24
  14592. 80068ba: 4293 cmp r3, r2
  14593. 80068bc: f000 8278 beq.w 8006db0 <HAL_DMA_IRQHandler+0x52c>
  14594. 80068c0: 3218 adds r2, #24
  14595. 80068c2: 4293 cmp r3, r2
  14596. 80068c4: f000 8285 beq.w 8006dd2 <HAL_DMA_IRQHandler+0x54e>
  14597. 80068c8: 3218 adds r2, #24
  14598. 80068ca: 4293 cmp r3, r2
  14599. 80068cc: f000 8281 beq.w 8006dd2 <HAL_DMA_IRQHandler+0x54e>
  14600. 80068d0: 3218 adds r2, #24
  14601. 80068d2: 4293 cmp r3, r2
  14602. 80068d4: f000 827d beq.w 8006dd2 <HAL_DMA_IRQHandler+0x54e>
  14603. 80068d8: 3218 adds r2, #24
  14604. 80068da: 4293 cmp r3, r2
  14605. 80068dc: f000 8279 beq.w 8006dd2 <HAL_DMA_IRQHandler+0x54e>
  14606. 80068e0: f502 7256 add.w r2, r2, #856 @ 0x358
  14607. 80068e4: 4293 cmp r3, r2
  14608. 80068e6: f000 8274 beq.w 8006dd2 <HAL_DMA_IRQHandler+0x54e>
  14609. 80068ea: 3218 adds r2, #24
  14610. 80068ec: 4293 cmp r3, r2
  14611. 80068ee: f000 8270 beq.w 8006dd2 <HAL_DMA_IRQHandler+0x54e>
  14612. 80068f2: 3218 adds r2, #24
  14613. 80068f4: 4293 cmp r3, r2
  14614. 80068f6: f000 826c beq.w 8006dd2 <HAL_DMA_IRQHandler+0x54e>
  14615. 80068fa: 3218 adds r2, #24
  14616. 80068fc: 4293 cmp r3, r2
  14617. 80068fe: f000 8268 beq.w 8006dd2 <HAL_DMA_IRQHandler+0x54e>
  14618. 8006902: 3218 adds r2, #24
  14619. 8006904: 4293 cmp r3, r2
  14620. 8006906: f000 8264 beq.w 8006dd2 <HAL_DMA_IRQHandler+0x54e>
  14621. 800690a: 3218 adds r2, #24
  14622. 800690c: 4293 cmp r3, r2
  14623. 800690e: f000 8260 beq.w 8006dd2 <HAL_DMA_IRQHandler+0x54e>
  14624. 8006912: 3218 adds r2, #24
  14625. 8006914: 4293 cmp r3, r2
  14626. 8006916: f000 825c beq.w 8006dd2 <HAL_DMA_IRQHandler+0x54e>
  14627. 800691a: 3218 adds r2, #24
  14628. 800691c: 4293 cmp r3, r2
  14629. 800691e: f000 8258 beq.w 8006dd2 <HAL_DMA_IRQHandler+0x54e>
  14630. else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
  14631. 8006922: 4a23 ldr r2, [pc, #140] @ (80069b0 <HAL_DMA_IRQHandler+0x12c>)
  14632. 8006924: 4823 ldr r0, [pc, #140] @ (80069b4 <HAL_DMA_IRQHandler+0x130>)
  14633. 8006926: 4283 cmp r3, r0
  14634. 8006928: bf18 it ne
  14635. 800692a: 4293 cmpne r3, r2
  14636. 800692c: f100 0014 add.w r0, r0, #20
  14637. 8006930: bf0c ite eq
  14638. 8006932: 2201 moveq r2, #1
  14639. 8006934: 2200 movne r2, #0
  14640. 8006936: 4283 cmp r3, r0
  14641. 8006938: bf08 it eq
  14642. 800693a: f042 0201 orreq.w r2, r2, #1
  14643. 800693e: 3014 adds r0, #20
  14644. 8006940: 4283 cmp r3, r0
  14645. 8006942: bf08 it eq
  14646. 8006944: f042 0201 orreq.w r2, r2, #1
  14647. 8006948: 3014 adds r0, #20
  14648. 800694a: 4283 cmp r3, r0
  14649. 800694c: bf08 it eq
  14650. 800694e: f042 0201 orreq.w r2, r2, #1
  14651. 8006952: 3014 adds r0, #20
  14652. 8006954: 4283 cmp r3, r0
  14653. 8006956: bf08 it eq
  14654. 8006958: f042 0201 orreq.w r2, r2, #1
  14655. 800695c: 3014 adds r0, #20
  14656. 800695e: 4283 cmp r3, r0
  14657. 8006960: bf08 it eq
  14658. 8006962: f042 0201 orreq.w r2, r2, #1
  14659. 8006966: b912 cbnz r2, 800696e <HAL_DMA_IRQHandler+0xea>
  14660. 8006968: 4a13 ldr r2, [pc, #76] @ (80069b8 <HAL_DMA_IRQHandler+0x134>)
  14661. 800696a: 4293 cmp r3, r2
  14662. 800696c: d116 bne.n 800699c <HAL_DMA_IRQHandler+0x118>
  14663. if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U))
  14664. 800696e: 6df0 ldr r0, [r6, #92] @ 0x5c
  14665. 8006970: 2504 movs r5, #4
  14666. ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR);
  14667. 8006972: 681a ldr r2, [r3, #0]
  14668. if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U))
  14669. 8006974: f000 001f and.w r0, r0, #31
  14670. 8006978: 4085 lsls r5, r0
  14671. 800697a: 420d tst r5, r1
  14672. 800697c: f000 8283 beq.w 8006e86 <HAL_DMA_IRQHandler+0x602>
  14673. 8006980: 0757 lsls r7, r2, #29
  14674. 8006982: f140 8280 bpl.w 8006e86 <HAL_DMA_IRQHandler+0x602>
  14675. if((ccr_reg & BDMA_CCR_DBM) != 0U)
  14676. 8006986: 0410 lsls r0, r2, #16
  14677. regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU));
  14678. 8006988: 6065 str r5, [r4, #4]
  14679. if((ccr_reg & BDMA_CCR_DBM) != 0U)
  14680. 800698a: f140 82af bpl.w 8006eec <HAL_DMA_IRQHandler+0x668>
  14681. if((ccr_reg & BDMA_CCR_CT) == 0U)
  14682. 800698e: 03d1 lsls r1, r2, #15
  14683. 8006990: f100 82b2 bmi.w 8006ef8 <HAL_DMA_IRQHandler+0x674>
  14684. if(hdma->XferM1HalfCpltCallback != NULL)
  14685. 8006994: 6cb3 ldr r3, [r6, #72] @ 0x48
  14686. 8006996: 2b00 cmp r3, #0
  14687. 8006998: f040 81f4 bne.w 8006d84 <HAL_DMA_IRQHandler+0x500>
  14688. }
  14689. 800699c: b002 add sp, #8
  14690. 800699e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  14691. 80069a2: bf00 nop
  14692. 80069a4: 24000038 .word 0x24000038
  14693. 80069a8: 40020028 .word 0x40020028
  14694. 80069ac: 40020010 .word 0x40020010
  14695. 80069b0: 58025408 .word 0x58025408
  14696. 80069b4: 5802541c .word 0x5802541c
  14697. 80069b8: 58025494 .word 0x58025494
  14698. if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  14699. 80069bc: f8d6 e05c ldr.w lr, [r6, #92] @ 0x5c
  14700. 80069c0: f04f 0c08 mov.w ip, #8
  14701. 80069c4: f00e 021f and.w r2, lr, #31
  14702. 80069c8: fa0c f102 lsl.w r1, ip, r2
  14703. 80069cc: 420f tst r7, r1
  14704. 80069ce: f000 81de beq.w 8006d8e <HAL_DMA_IRQHandler+0x50a>
  14705. if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U)
  14706. 80069d2: f8d3 c000 ldr.w ip, [r3]
  14707. 80069d6: f01c 0f04 tst.w ip, #4
  14708. 80069da: d00a beq.n 80069f2 <HAL_DMA_IRQHandler+0x16e>
  14709. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE);
  14710. 80069dc: f8d3 c000 ldr.w ip, [r3]
  14711. 80069e0: f02c 0c04 bic.w ip, ip, #4
  14712. 80069e4: f8c3 c000 str.w ip, [r3]
  14713. regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
  14714. 80069e8: 60a1 str r1, [r4, #8]
  14715. hdma->ErrorCode |= HAL_DMA_ERROR_TE;
  14716. 80069ea: 6d71 ldr r1, [r6, #84] @ 0x54
  14717. 80069ec: f041 0101 orr.w r1, r1, #1
  14718. 80069f0: 6571 str r1, [r6, #84] @ 0x54
  14719. if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  14720. 80069f2: fa27 f102 lsr.w r1, r7, r2
  14721. 80069f6: 07c9 lsls r1, r1, #31
  14722. 80069f8: d55b bpl.n 8006ab2 <HAL_DMA_IRQHandler+0x22e>
  14723. if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
  14724. 80069fa: 2800 cmp r0, #0
  14725. 80069fc: d14f bne.n 8006a9e <HAL_DMA_IRQHandler+0x21a>
  14726. 80069fe: 49a2 ldr r1, [pc, #648] @ (8006c88 <HAL_DMA_IRQHandler+0x404>)
  14727. 8006a00: f8df c298 ldr.w ip, [pc, #664] @ 8006c9c <HAL_DMA_IRQHandler+0x418>
  14728. 8006a04: 4563 cmp r3, ip
  14729. 8006a06: bf18 it ne
  14730. 8006a08: 428b cmpne r3, r1
  14731. 8006a0a: f10c 0c18 add.w ip, ip, #24
  14732. 8006a0e: bf0c ite eq
  14733. 8006a10: 2101 moveq r1, #1
  14734. 8006a12: 2100 movne r1, #0
  14735. 8006a14: 4563 cmp r3, ip
  14736. 8006a16: bf08 it eq
  14737. 8006a18: f041 0101 orreq.w r1, r1, #1
  14738. 8006a1c: f10c 0c18 add.w ip, ip, #24
  14739. 8006a20: 4563 cmp r3, ip
  14740. 8006a22: bf08 it eq
  14741. 8006a24: f041 0101 orreq.w r1, r1, #1
  14742. 8006a28: f10c 0c18 add.w ip, ip, #24
  14743. 8006a2c: 4563 cmp r3, ip
  14744. 8006a2e: bf08 it eq
  14745. 8006a30: f041 0101 orreq.w r1, r1, #1
  14746. 8006a34: f10c 0c18 add.w ip, ip, #24
  14747. 8006a38: 4563 cmp r3, ip
  14748. 8006a3a: bf08 it eq
  14749. 8006a3c: f041 0101 orreq.w r1, r1, #1
  14750. 8006a40: f50c 7c56 add.w ip, ip, #856 @ 0x358
  14751. 8006a44: 4563 cmp r3, ip
  14752. 8006a46: bf08 it eq
  14753. 8006a48: f041 0101 orreq.w r1, r1, #1
  14754. 8006a4c: f10c 0c18 add.w ip, ip, #24
  14755. 8006a50: 4563 cmp r3, ip
  14756. 8006a52: bf08 it eq
  14757. 8006a54: f041 0101 orreq.w r1, r1, #1
  14758. 8006a58: f10c 0c18 add.w ip, ip, #24
  14759. 8006a5c: 4563 cmp r3, ip
  14760. 8006a5e: bf08 it eq
  14761. 8006a60: f041 0101 orreq.w r1, r1, #1
  14762. 8006a64: f10c 0c18 add.w ip, ip, #24
  14763. 8006a68: 4563 cmp r3, ip
  14764. 8006a6a: bf08 it eq
  14765. 8006a6c: f041 0101 orreq.w r1, r1, #1
  14766. 8006a70: f10c 0c18 add.w ip, ip, #24
  14767. 8006a74: 4563 cmp r3, ip
  14768. 8006a76: bf08 it eq
  14769. 8006a78: f041 0101 orreq.w r1, r1, #1
  14770. 8006a7c: f10c 0c18 add.w ip, ip, #24
  14771. 8006a80: 4563 cmp r3, ip
  14772. 8006a82: bf08 it eq
  14773. 8006a84: f041 0101 orreq.w r1, r1, #1
  14774. 8006a88: f10c 0c18 add.w ip, ip, #24
  14775. 8006a8c: 4563 cmp r3, ip
  14776. 8006a8e: bf08 it eq
  14777. 8006a90: f041 0101 orreq.w r1, r1, #1
  14778. 8006a94: b919 cbnz r1, 8006a9e <HAL_DMA_IRQHandler+0x21a>
  14779. 8006a96: 497d ldr r1, [pc, #500] @ (8006c8c <HAL_DMA_IRQHandler+0x408>)
  14780. 8006a98: 428b cmp r3, r1
  14781. 8006a9a: f040 81e3 bne.w 8006e64 <HAL_DMA_IRQHandler+0x5e0>
  14782. 8006a9e: 6959 ldr r1, [r3, #20]
  14783. 8006aa0: 0609 lsls r1, r1, #24
  14784. 8006aa2: d506 bpl.n 8006ab2 <HAL_DMA_IRQHandler+0x22e>
  14785. regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
  14786. 8006aa4: 2101 movs r1, #1
  14787. 8006aa6: 4091 lsls r1, r2
  14788. 8006aa8: 60a1 str r1, [r4, #8]
  14789. hdma->ErrorCode |= HAL_DMA_ERROR_FE;
  14790. 8006aaa: 6d71 ldr r1, [r6, #84] @ 0x54
  14791. 8006aac: f041 0102 orr.w r1, r1, #2
  14792. 8006ab0: 6571 str r1, [r6, #84] @ 0x54
  14793. if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  14794. 8006ab2: 2104 movs r1, #4
  14795. 8006ab4: 4091 lsls r1, r2
  14796. 8006ab6: 4239 tst r1, r7
  14797. 8006ab8: d05f beq.n 8006b7a <HAL_DMA_IRQHandler+0x2f6>
  14798. if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)
  14799. 8006aba: f8df c1cc ldr.w ip, [pc, #460] @ 8006c88 <HAL_DMA_IRQHandler+0x404>
  14800. 8006abe: 4563 cmp r3, ip
  14801. 8006ac0: d051 beq.n 8006b66 <HAL_DMA_IRQHandler+0x2e2>
  14802. 8006ac2: 2800 cmp r0, #0
  14803. 8006ac4: d14f bne.n 8006b66 <HAL_DMA_IRQHandler+0x2e2>
  14804. 8006ac6: f10c 0c30 add.w ip, ip, #48 @ 0x30
  14805. 8006aca: f8df 81d0 ldr.w r8, [pc, #464] @ 8006c9c <HAL_DMA_IRQHandler+0x418>
  14806. 8006ace: 4543 cmp r3, r8
  14807. 8006ad0: bf18 it ne
  14808. 8006ad2: 4563 cmpne r3, ip
  14809. 8006ad4: f108 0830 add.w r8, r8, #48 @ 0x30
  14810. 8006ad8: bf0c ite eq
  14811. 8006ada: f04f 0c01 moveq.w ip, #1
  14812. 8006ade: f04f 0c00 movne.w ip, #0
  14813. 8006ae2: 4543 cmp r3, r8
  14814. 8006ae4: bf08 it eq
  14815. 8006ae6: f04c 0c01 orreq.w ip, ip, #1
  14816. 8006aea: f108 0818 add.w r8, r8, #24
  14817. 8006aee: 4543 cmp r3, r8
  14818. 8006af0: bf08 it eq
  14819. 8006af2: f04c 0c01 orreq.w ip, ip, #1
  14820. 8006af6: f108 0818 add.w r8, r8, #24
  14821. 8006afa: 4543 cmp r3, r8
  14822. 8006afc: bf08 it eq
  14823. 8006afe: f04c 0c01 orreq.w ip, ip, #1
  14824. 8006b02: f508 7856 add.w r8, r8, #856 @ 0x358
  14825. 8006b06: 4543 cmp r3, r8
  14826. 8006b08: bf08 it eq
  14827. 8006b0a: f04c 0c01 orreq.w ip, ip, #1
  14828. 8006b0e: f108 0818 add.w r8, r8, #24
  14829. 8006b12: 4543 cmp r3, r8
  14830. 8006b14: bf08 it eq
  14831. 8006b16: f04c 0c01 orreq.w ip, ip, #1
  14832. 8006b1a: f108 0818 add.w r8, r8, #24
  14833. 8006b1e: 4543 cmp r3, r8
  14834. 8006b20: bf08 it eq
  14835. 8006b22: f04c 0c01 orreq.w ip, ip, #1
  14836. 8006b26: f108 0818 add.w r8, r8, #24
  14837. 8006b2a: 4543 cmp r3, r8
  14838. 8006b2c: bf08 it eq
  14839. 8006b2e: f04c 0c01 orreq.w ip, ip, #1
  14840. 8006b32: f108 0818 add.w r8, r8, #24
  14841. 8006b36: 4543 cmp r3, r8
  14842. 8006b38: bf08 it eq
  14843. 8006b3a: f04c 0c01 orreq.w ip, ip, #1
  14844. 8006b3e: f108 0818 add.w r8, r8, #24
  14845. 8006b42: 4543 cmp r3, r8
  14846. 8006b44: bf08 it eq
  14847. 8006b46: f04c 0c01 orreq.w ip, ip, #1
  14848. 8006b4a: f108 0818 add.w r8, r8, #24
  14849. 8006b4e: 4543 cmp r3, r8
  14850. 8006b50: bf08 it eq
  14851. 8006b52: f04c 0c01 orreq.w ip, ip, #1
  14852. 8006b56: f1bc 0f00 cmp.w ip, #0
  14853. 8006b5a: d104 bne.n 8006b66 <HAL_DMA_IRQHandler+0x2e2>
  14854. 8006b5c: f8df c12c ldr.w ip, [pc, #300] @ 8006c8c <HAL_DMA_IRQHandler+0x408>
  14855. 8006b60: 4563 cmp r3, ip
  14856. 8006b62: f040 8185 bne.w 8006e70 <HAL_DMA_IRQHandler+0x5ec>
  14857. 8006b66: f8d3 c000 ldr.w ip, [r3]
  14858. 8006b6a: f01c 0f02 tst.w ip, #2
  14859. 8006b6e: d004 beq.n 8006b7a <HAL_DMA_IRQHandler+0x2f6>
  14860. regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
  14861. 8006b70: 60a1 str r1, [r4, #8]
  14862. hdma->ErrorCode |= HAL_DMA_ERROR_DME;
  14863. 8006b72: 6d71 ldr r1, [r6, #84] @ 0x54
  14864. 8006b74: f041 0104 orr.w r1, r1, #4
  14865. 8006b78: 6571 str r1, [r6, #84] @ 0x54
  14866. if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  14867. 8006b7a: 2110 movs r1, #16
  14868. 8006b7c: fa01 f202 lsl.w r2, r1, r2
  14869. 8006b80: 423a tst r2, r7
  14870. 8006b82: d05b beq.n 8006c3c <HAL_DMA_IRQHandler+0x3b8>
  14871. if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
  14872. 8006b84: 4940 ldr r1, [pc, #256] @ (8006c88 <HAL_DMA_IRQHandler+0x404>)
  14873. 8006b86: 428b cmp r3, r1
  14874. 8006b88: d042 beq.n 8006c10 <HAL_DMA_IRQHandler+0x38c>
  14875. 8006b8a: 2800 cmp r0, #0
  14876. 8006b8c: d140 bne.n 8006c10 <HAL_DMA_IRQHandler+0x38c>
  14877. 8006b8e: 3118 adds r1, #24
  14878. 8006b90: 483f ldr r0, [pc, #252] @ (8006c90 <HAL_DMA_IRQHandler+0x40c>)
  14879. 8006b92: 4283 cmp r3, r0
  14880. 8006b94: bf18 it ne
  14881. 8006b96: 428b cmpne r3, r1
  14882. 8006b98: f100 0018 add.w r0, r0, #24
  14883. 8006b9c: bf0c ite eq
  14884. 8006b9e: 2101 moveq r1, #1
  14885. 8006ba0: 2100 movne r1, #0
  14886. 8006ba2: 4283 cmp r3, r0
  14887. 8006ba4: bf08 it eq
  14888. 8006ba6: f041 0101 orreq.w r1, r1, #1
  14889. 8006baa: 3018 adds r0, #24
  14890. 8006bac: 4283 cmp r3, r0
  14891. 8006bae: bf08 it eq
  14892. 8006bb0: f041 0101 orreq.w r1, r1, #1
  14893. 8006bb4: 3018 adds r0, #24
  14894. 8006bb6: 4283 cmp r3, r0
  14895. 8006bb8: bf08 it eq
  14896. 8006bba: f041 0101 orreq.w r1, r1, #1
  14897. 8006bbe: f500 7056 add.w r0, r0, #856 @ 0x358
  14898. 8006bc2: 4283 cmp r3, r0
  14899. 8006bc4: bf08 it eq
  14900. 8006bc6: f041 0101 orreq.w r1, r1, #1
  14901. 8006bca: 3018 adds r0, #24
  14902. 8006bcc: 4283 cmp r3, r0
  14903. 8006bce: bf08 it eq
  14904. 8006bd0: f041 0101 orreq.w r1, r1, #1
  14905. 8006bd4: 3018 adds r0, #24
  14906. 8006bd6: 4283 cmp r3, r0
  14907. 8006bd8: bf08 it eq
  14908. 8006bda: f041 0101 orreq.w r1, r1, #1
  14909. 8006bde: 3018 adds r0, #24
  14910. 8006be0: 4283 cmp r3, r0
  14911. 8006be2: bf08 it eq
  14912. 8006be4: f041 0101 orreq.w r1, r1, #1
  14913. 8006be8: 3018 adds r0, #24
  14914. 8006bea: 4283 cmp r3, r0
  14915. 8006bec: bf08 it eq
  14916. 8006bee: f041 0101 orreq.w r1, r1, #1
  14917. 8006bf2: 3018 adds r0, #24
  14918. 8006bf4: 4283 cmp r3, r0
  14919. 8006bf6: bf08 it eq
  14920. 8006bf8: f041 0101 orreq.w r1, r1, #1
  14921. 8006bfc: 3018 adds r0, #24
  14922. 8006bfe: 4283 cmp r3, r0
  14923. 8006c00: bf08 it eq
  14924. 8006c02: f041 0101 orreq.w r1, r1, #1
  14925. 8006c06: b919 cbnz r1, 8006c10 <HAL_DMA_IRQHandler+0x38c>
  14926. 8006c08: 4920 ldr r1, [pc, #128] @ (8006c8c <HAL_DMA_IRQHandler+0x408>)
  14927. 8006c0a: 428b cmp r3, r1
  14928. 8006c0c: f040 8137 bne.w 8006e7e <HAL_DMA_IRQHandler+0x5fa>
  14929. 8006c10: 6819 ldr r1, [r3, #0]
  14930. 8006c12: f3c1 01c0 ubfx r1, r1, #3, #1
  14931. 8006c16: b189 cbz r1, 8006c3c <HAL_DMA_IRQHandler+0x3b8>
  14932. regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
  14933. 8006c18: 60a2 str r2, [r4, #8]
  14934. if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
  14935. 8006c1a: 681a ldr r2, [r3, #0]
  14936. 8006c1c: 0350 lsls r0, r2, #13
  14937. 8006c1e: f100 80e7 bmi.w 8006df0 <HAL_DMA_IRQHandler+0x56c>
  14938. if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
  14939. 8006c22: 681a ldr r2, [r3, #0]
  14940. 8006c24: 05d2 lsls r2, r2, #23
  14941. 8006c26: d403 bmi.n 8006c30 <HAL_DMA_IRQHandler+0x3ac>
  14942. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT);
  14943. 8006c28: 681a ldr r2, [r3, #0]
  14944. 8006c2a: f022 0208 bic.w r2, r2, #8
  14945. 8006c2e: 601a str r2, [r3, #0]
  14946. if(hdma->XferHalfCpltCallback != NULL)
  14947. 8006c30: 6c33 ldr r3, [r6, #64] @ 0x40
  14948. 8006c32: b11b cbz r3, 8006c3c <HAL_DMA_IRQHandler+0x3b8>
  14949. hdma->XferHalfCpltCallback(hdma);
  14950. 8006c34: 4630 mov r0, r6
  14951. 8006c36: 4798 blx r3
  14952. 8006c38: f8d6 e05c ldr.w lr, [r6, #92] @ 0x5c
  14953. if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  14954. 8006c3c: f00e 011f and.w r1, lr, #31
  14955. 8006c40: 2020 movs r0, #32
  14956. 8006c42: 4088 lsls r0, r1
  14957. 8006c44: 4238 tst r0, r7
  14958. 8006c46: d073 beq.n 8006d30 <HAL_DMA_IRQHandler+0x4ac>
  14959. if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
  14960. 8006c48: 6832 ldr r2, [r6, #0]
  14961. 8006c4a: 4b12 ldr r3, [pc, #72] @ (8006c94 <HAL_DMA_IRQHandler+0x410>)
  14962. 8006c4c: 4f12 ldr r7, [pc, #72] @ (8006c98 <HAL_DMA_IRQHandler+0x414>)
  14963. 8006c4e: 42ba cmp r2, r7
  14964. 8006c50: bf18 it ne
  14965. 8006c52: 429a cmpne r2, r3
  14966. 8006c54: f107 0718 add.w r7, r7, #24
  14967. 8006c58: bf0c ite eq
  14968. 8006c5a: 2301 moveq r3, #1
  14969. 8006c5c: 2300 movne r3, #0
  14970. 8006c5e: 42ba cmp r2, r7
  14971. 8006c60: bf08 it eq
  14972. 8006c62: f043 0301 orreq.w r3, r3, #1
  14973. 8006c66: 3718 adds r7, #24
  14974. 8006c68: 42ba cmp r2, r7
  14975. 8006c6a: bf08 it eq
  14976. 8006c6c: f043 0301 orreq.w r3, r3, #1
  14977. 8006c70: 3718 adds r7, #24
  14978. 8006c72: 42ba cmp r2, r7
  14979. 8006c74: bf08 it eq
  14980. 8006c76: f043 0301 orreq.w r3, r3, #1
  14981. 8006c7a: 3718 adds r7, #24
  14982. 8006c7c: 42ba cmp r2, r7
  14983. 8006c7e: bf08 it eq
  14984. 8006c80: f043 0301 orreq.w r3, r3, #1
  14985. 8006c84: 3718 adds r7, #24
  14986. 8006c86: e00b b.n 8006ca0 <HAL_DMA_IRQHandler+0x41c>
  14987. 8006c88: 40020040 .word 0x40020040
  14988. 8006c8c: 400204b8 .word 0x400204b8
  14989. 8006c90: 40020070 .word 0x40020070
  14990. 8006c94: 40020010 .word 0x40020010
  14991. 8006c98: 40020028 .word 0x40020028
  14992. 8006c9c: 40020058 .word 0x40020058
  14993. 8006ca0: 42ba cmp r2, r7
  14994. 8006ca2: bf08 it eq
  14995. 8006ca4: f043 0301 orreq.w r3, r3, #1
  14996. 8006ca8: 3718 adds r7, #24
  14997. 8006caa: 42ba cmp r2, r7
  14998. 8006cac: bf08 it eq
  14999. 8006cae: f043 0301 orreq.w r3, r3, #1
  15000. 8006cb2: f507 7756 add.w r7, r7, #856 @ 0x358
  15001. 8006cb6: 42ba cmp r2, r7
  15002. 8006cb8: bf08 it eq
  15003. 8006cba: f043 0301 orreq.w r3, r3, #1
  15004. 8006cbe: 3718 adds r7, #24
  15005. 8006cc0: 42ba cmp r2, r7
  15006. 8006cc2: bf08 it eq
  15007. 8006cc4: f043 0301 orreq.w r3, r3, #1
  15008. 8006cc8: 3718 adds r7, #24
  15009. 8006cca: 42ba cmp r2, r7
  15010. 8006ccc: bf08 it eq
  15011. 8006cce: f043 0301 orreq.w r3, r3, #1
  15012. 8006cd2: 3718 adds r7, #24
  15013. 8006cd4: 42ba cmp r2, r7
  15014. 8006cd6: bf08 it eq
  15015. 8006cd8: f043 0301 orreq.w r3, r3, #1
  15016. 8006cdc: 3718 adds r7, #24
  15017. 8006cde: 42ba cmp r2, r7
  15018. 8006ce0: bf08 it eq
  15019. 8006ce2: f043 0301 orreq.w r3, r3, #1
  15020. 8006ce6: 3718 adds r7, #24
  15021. 8006ce8: 42ba cmp r2, r7
  15022. 8006cea: bf08 it eq
  15023. 8006cec: f043 0301 orreq.w r3, r3, #1
  15024. 8006cf0: 3718 adds r7, #24
  15025. 8006cf2: 42ba cmp r2, r7
  15026. 8006cf4: bf08 it eq
  15027. 8006cf6: f043 0301 orreq.w r3, r3, #1
  15028. 8006cfa: b91b cbnz r3, 8006d04 <HAL_DMA_IRQHandler+0x480>
  15029. 8006cfc: 4b89 ldr r3, [pc, #548] @ (8006f24 <HAL_DMA_IRQHandler+0x6a0>)
  15030. 8006cfe: 429a cmp r2, r3
  15031. 8006d00: f040 80d1 bne.w 8006ea6 <HAL_DMA_IRQHandler+0x622>
  15032. 8006d04: 6813 ldr r3, [r2, #0]
  15033. 8006d06: f3c3 1300 ubfx r3, r3, #4, #1
  15034. 8006d0a: b18b cbz r3, 8006d30 <HAL_DMA_IRQHandler+0x4ac>
  15035. regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
  15036. 8006d0c: 60a0 str r0, [r4, #8]
  15037. if(HAL_DMA_STATE_ABORT == hdma->State)
  15038. 8006d0e: f896 3035 ldrb.w r3, [r6, #53] @ 0x35
  15039. 8006d12: 2b04 cmp r3, #4
  15040. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
  15041. 8006d14: 6813 ldr r3, [r2, #0]
  15042. if(HAL_DMA_STATE_ABORT == hdma->State)
  15043. 8006d16: d074 beq.n 8006e02 <HAL_DMA_IRQHandler+0x57e>
  15044. if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
  15045. 8006d18: f413 2f80 tst.w r3, #262144 @ 0x40000
  15046. if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
  15047. 8006d1c: 6813 ldr r3, [r2, #0]
  15048. if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
  15049. 8006d1e: f000 808a beq.w 8006e36 <HAL_DMA_IRQHandler+0x5b2>
  15050. if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
  15051. 8006d22: 031f lsls r7, r3, #12
  15052. 8006d24: f140 8095 bpl.w 8006e52 <HAL_DMA_IRQHandler+0x5ce>
  15053. if(hdma->XferCpltCallback != NULL)
  15054. 8006d28: 6bf3 ldr r3, [r6, #60] @ 0x3c
  15055. 8006d2a: b10b cbz r3, 8006d30 <HAL_DMA_IRQHandler+0x4ac>
  15056. hdma->XferCpltCallback(hdma);
  15057. 8006d2c: 4630 mov r0, r6
  15058. 8006d2e: 4798 blx r3
  15059. if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
  15060. 8006d30: 6d73 ldr r3, [r6, #84] @ 0x54
  15061. 8006d32: 2b00 cmp r3, #0
  15062. 8006d34: f43f ae32 beq.w 800699c <HAL_DMA_IRQHandler+0x118>
  15063. if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)
  15064. 8006d38: 6d73 ldr r3, [r6, #84] @ 0x54
  15065. 8006d3a: 07dc lsls r4, r3, #31
  15066. 8006d3c: d51e bpl.n 8006d7c <HAL_DMA_IRQHandler+0x4f8>
  15067. __HAL_DMA_DISABLE(hdma);
  15068. 8006d3e: 6832 ldr r2, [r6, #0]
  15069. hdma->State = HAL_DMA_STATE_ABORT;
  15070. 8006d40: 2104 movs r1, #4
  15071. 8006d42: f886 1035 strb.w r1, [r6, #53] @ 0x35
  15072. uint32_t timeout = SystemCoreClock / 9600U;
  15073. 8006d46: 4978 ldr r1, [pc, #480] @ (8006f28 <HAL_DMA_IRQHandler+0x6a4>)
  15074. __HAL_DMA_DISABLE(hdma);
  15075. 8006d48: 6813 ldr r3, [r2, #0]
  15076. uint32_t timeout = SystemCoreClock / 9600U;
  15077. 8006d4a: fba1 5105 umull r5, r1, r1, r5
  15078. __HAL_DMA_DISABLE(hdma);
  15079. 8006d4e: f023 0301 bic.w r3, r3, #1
  15080. uint32_t timeout = SystemCoreClock / 9600U;
  15081. 8006d52: 0a89 lsrs r1, r1, #10
  15082. __HAL_DMA_DISABLE(hdma);
  15083. 8006d54: 6013 str r3, [r2, #0]
  15084. 8006d56: e002 b.n 8006d5e <HAL_DMA_IRQHandler+0x4da>
  15085. while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
  15086. 8006d58: 6813 ldr r3, [r2, #0]
  15087. 8006d5a: 07d8 lsls r0, r3, #31
  15088. 8006d5c: d504 bpl.n 8006d68 <HAL_DMA_IRQHandler+0x4e4>
  15089. if (++count > timeout)
  15090. 8006d5e: 9b01 ldr r3, [sp, #4]
  15091. 8006d60: 3301 adds r3, #1
  15092. 8006d62: 428b cmp r3, r1
  15093. 8006d64: 9301 str r3, [sp, #4]
  15094. 8006d66: d9f7 bls.n 8006d58 <HAL_DMA_IRQHandler+0x4d4>
  15095. if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
  15096. 8006d68: 6813 ldr r3, [r2, #0]
  15097. 8006d6a: 07db lsls r3, r3, #31
  15098. hdma->State = HAL_DMA_STATE_ERROR;
  15099. 8006d6c: bf4c ite mi
  15100. 8006d6e: 2303 movmi r3, #3
  15101. hdma->State = HAL_DMA_STATE_READY;
  15102. 8006d70: 2301 movpl r3, #1
  15103. 8006d72: f886 3035 strb.w r3, [r6, #53] @ 0x35
  15104. __HAL_UNLOCK(hdma);
  15105. 8006d76: 2300 movs r3, #0
  15106. 8006d78: f886 3034 strb.w r3, [r6, #52] @ 0x34
  15107. if(hdma->XferErrorCallback != NULL)
  15108. 8006d7c: 6cf3 ldr r3, [r6, #76] @ 0x4c
  15109. 8006d7e: 2b00 cmp r3, #0
  15110. 8006d80: f43f ae0c beq.w 800699c <HAL_DMA_IRQHandler+0x118>
  15111. hdma->XferCpltCallback(hdma);
  15112. 8006d84: 4630 mov r0, r6
  15113. }
  15114. 8006d86: b002 add sp, #8
  15115. 8006d88: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
  15116. hdma->XferCpltCallback(hdma);
  15117. 8006d8c: 4718 bx r3
  15118. if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  15119. 8006d8e: fa27 f102 lsr.w r1, r7, r2
  15120. 8006d92: 07c9 lsls r1, r1, #31
  15121. 8006d94: f53f ae83 bmi.w 8006a9e <HAL_DMA_IRQHandler+0x21a>
  15122. if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  15123. 8006d98: 2104 movs r1, #4
  15124. 8006d9a: 4091 lsls r1, r2
  15125. 8006d9c: 420f tst r7, r1
  15126. 8006d9e: f47f aee2 bne.w 8006b66 <HAL_DMA_IRQHandler+0x2e2>
  15127. if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  15128. 8006da2: 2110 movs r1, #16
  15129. 8006da4: fa01 f202 lsl.w r2, r1, r2
  15130. 8006da8: 4217 tst r7, r2
  15131. 8006daa: f47f af31 bne.w 8006c10 <HAL_DMA_IRQHandler+0x38c>
  15132. 8006dae: e745 b.n 8006c3c <HAL_DMA_IRQHandler+0x3b8>
  15133. if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  15134. 8006db0: f8d6 e05c ldr.w lr, [r6, #92] @ 0x5c
  15135. 8006db4: f04f 0c08 mov.w ip, #8
  15136. 8006db8: f00e 021f and.w r2, lr, #31
  15137. 8006dbc: fa0c f102 lsl.w r1, ip, r2
  15138. 8006dc0: 420f tst r7, r1
  15139. 8006dc2: f47f ae06 bne.w 80069d2 <HAL_DMA_IRQHandler+0x14e>
  15140. if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  15141. 8006dc6: fa27 f102 lsr.w r1, r7, r2
  15142. 8006dca: 07c9 lsls r1, r1, #31
  15143. 8006dcc: f53f ae67 bmi.w 8006a9e <HAL_DMA_IRQHandler+0x21a>
  15144. 8006dd0: e66f b.n 8006ab2 <HAL_DMA_IRQHandler+0x22e>
  15145. if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  15146. 8006dd2: f8d6 e05c ldr.w lr, [r6, #92] @ 0x5c
  15147. 8006dd6: 2108 movs r1, #8
  15148. 8006dd8: f00e 021f and.w r2, lr, #31
  15149. 8006ddc: 4091 lsls r1, r2
  15150. 8006dde: 420f tst r7, r1
  15151. 8006de0: f47f adf7 bne.w 80069d2 <HAL_DMA_IRQHandler+0x14e>
  15152. if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  15153. 8006de4: fa27 f102 lsr.w r1, r7, r2
  15154. 8006de8: 07c9 lsls r1, r1, #31
  15155. 8006dea: f53f ae58 bmi.w 8006a9e <HAL_DMA_IRQHandler+0x21a>
  15156. 8006dee: e660 b.n 8006ab2 <HAL_DMA_IRQHandler+0x22e>
  15157. if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
  15158. 8006df0: 681b ldr r3, [r3, #0]
  15159. 8006df2: 0319 lsls r1, r3, #12
  15160. 8006df4: f57f af1c bpl.w 8006c30 <HAL_DMA_IRQHandler+0x3ac>
  15161. if(hdma->XferM1HalfCpltCallback != NULL)
  15162. 8006df8: 6cb3 ldr r3, [r6, #72] @ 0x48
  15163. 8006dfa: 2b00 cmp r3, #0
  15164. 8006dfc: f47f af1a bne.w 8006c34 <HAL_DMA_IRQHandler+0x3b0>
  15165. 8006e00: e71c b.n 8006c3c <HAL_DMA_IRQHandler+0x3b8>
  15166. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
  15167. 8006e02: f023 0316 bic.w r3, r3, #22
  15168. 8006e06: 6013 str r3, [r2, #0]
  15169. ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
  15170. 8006e08: 6953 ldr r3, [r2, #20]
  15171. 8006e0a: f023 0380 bic.w r3, r3, #128 @ 0x80
  15172. 8006e0e: 6153 str r3, [r2, #20]
  15173. if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
  15174. 8006e10: 6c33 ldr r3, [r6, #64] @ 0x40
  15175. 8006e12: b31b cbz r3, 8006e5c <HAL_DMA_IRQHandler+0x5d8>
  15176. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT);
  15177. 8006e14: 6813 ldr r3, [r2, #0]
  15178. 8006e16: f023 0308 bic.w r3, r3, #8
  15179. 8006e1a: 6013 str r3, [r2, #0]
  15180. regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
  15181. 8006e1c: 233f movs r3, #63 @ 0x3f
  15182. hdma->State = HAL_DMA_STATE_READY;
  15183. 8006e1e: 2001 movs r0, #1
  15184. __HAL_UNLOCK(hdma);
  15185. 8006e20: 2200 movs r2, #0
  15186. regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
  15187. 8006e22: 408b lsls r3, r1
  15188. 8006e24: 60a3 str r3, [r4, #8]
  15189. if(hdma->XferAbortCallback != NULL)
  15190. 8006e26: 6d33 ldr r3, [r6, #80] @ 0x50
  15191. hdma->State = HAL_DMA_STATE_READY;
  15192. 8006e28: f886 0035 strb.w r0, [r6, #53] @ 0x35
  15193. __HAL_UNLOCK(hdma);
  15194. 8006e2c: f886 2034 strb.w r2, [r6, #52] @ 0x34
  15195. if(hdma->XferAbortCallback != NULL)
  15196. 8006e30: 2b00 cmp r3, #0
  15197. 8006e32: d1a7 bne.n 8006d84 <HAL_DMA_IRQHandler+0x500>
  15198. 8006e34: e5b2 b.n 800699c <HAL_DMA_IRQHandler+0x118>
  15199. if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
  15200. 8006e36: f413 7380 ands.w r3, r3, #256 @ 0x100
  15201. 8006e3a: f47f af75 bne.w 8006d28 <HAL_DMA_IRQHandler+0x4a4>
  15202. ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC);
  15203. 8006e3e: 6811 ldr r1, [r2, #0]
  15204. 8006e40: f021 0110 bic.w r1, r1, #16
  15205. 8006e44: 6011 str r1, [r2, #0]
  15206. hdma->State = HAL_DMA_STATE_READY;
  15207. 8006e46: 2201 movs r2, #1
  15208. __HAL_UNLOCK(hdma);
  15209. 8006e48: f886 3034 strb.w r3, [r6, #52] @ 0x34
  15210. hdma->State = HAL_DMA_STATE_READY;
  15211. 8006e4c: f886 2035 strb.w r2, [r6, #53] @ 0x35
  15212. __HAL_UNLOCK(hdma);
  15213. 8006e50: e76a b.n 8006d28 <HAL_DMA_IRQHandler+0x4a4>
  15214. if(hdma->XferM1CpltCallback != NULL)
  15215. 8006e52: 6c73 ldr r3, [r6, #68] @ 0x44
  15216. 8006e54: 2b00 cmp r3, #0
  15217. 8006e56: f47f af69 bne.w 8006d2c <HAL_DMA_IRQHandler+0x4a8>
  15218. 8006e5a: e769 b.n 8006d30 <HAL_DMA_IRQHandler+0x4ac>
  15219. if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
  15220. 8006e5c: 6cb3 ldr r3, [r6, #72] @ 0x48
  15221. 8006e5e: 2b00 cmp r3, #0
  15222. 8006e60: d1d8 bne.n 8006e14 <HAL_DMA_IRQHandler+0x590>
  15223. 8006e62: e7db b.n 8006e1c <HAL_DMA_IRQHandler+0x598>
  15224. if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
  15225. 8006e64: 6819 ldr r1, [r3, #0]
  15226. if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  15227. 8006e66: 2104 movs r1, #4
  15228. 8006e68: 4091 lsls r1, r2
  15229. 8006e6a: 4239 tst r1, r7
  15230. 8006e6c: f43f ae85 beq.w 8006b7a <HAL_DMA_IRQHandler+0x2f6>
  15231. if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)
  15232. 8006e70: 6819 ldr r1, [r3, #0]
  15233. if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
  15234. 8006e72: 2110 movs r1, #16
  15235. 8006e74: fa01 f202 lsl.w r2, r1, r2
  15236. 8006e78: 4217 tst r7, r2
  15237. 8006e7a: f43f aedf beq.w 8006c3c <HAL_DMA_IRQHandler+0x3b8>
  15238. if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
  15239. 8006e7e: 6819 ldr r1, [r3, #0]
  15240. 8006e80: f3c1 0180 ubfx r1, r1, #2, #1
  15241. 8006e84: e6c7 b.n 8006c16 <HAL_DMA_IRQHandler+0x392>
  15242. else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U))
  15243. 8006e86: 2502 movs r5, #2
  15244. 8006e88: 4085 lsls r5, r0
  15245. 8006e8a: 420d tst r5, r1
  15246. 8006e8c: d00f beq.n 8006eae <HAL_DMA_IRQHandler+0x62a>
  15247. 8006e8e: 0797 lsls r7, r2, #30
  15248. 8006e90: d50d bpl.n 8006eae <HAL_DMA_IRQHandler+0x62a>
  15249. if((ccr_reg & BDMA_CCR_DBM) != 0U)
  15250. 8006e92: 0411 lsls r1, r2, #16
  15251. regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU);
  15252. 8006e94: 6065 str r5, [r4, #4]
  15253. if((ccr_reg & BDMA_CCR_DBM) != 0U)
  15254. 8006e96: d534 bpl.n 8006f02 <HAL_DMA_IRQHandler+0x67e>
  15255. if((ccr_reg & BDMA_CCR_CT) == 0U)
  15256. 8006e98: 03d7 lsls r7, r2, #15
  15257. 8006e9a: d43e bmi.n 8006f1a <HAL_DMA_IRQHandler+0x696>
  15258. if(hdma->XferM1CpltCallback != NULL)
  15259. 8006e9c: 6c73 ldr r3, [r6, #68] @ 0x44
  15260. 8006e9e: 2b00 cmp r3, #0
  15261. 8006ea0: f47f af70 bne.w 8006d84 <HAL_DMA_IRQHandler+0x500>
  15262. 8006ea4: e57a b.n 800699c <HAL_DMA_IRQHandler+0x118>
  15263. if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
  15264. 8006ea6: 6813 ldr r3, [r2, #0]
  15265. 8006ea8: f3c3 0340 ubfx r3, r3, #1, #1
  15266. 8006eac: e72d b.n 8006d0a <HAL_DMA_IRQHandler+0x486>
  15267. else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))
  15268. 8006eae: 2508 movs r5, #8
  15269. 8006eb0: 4085 lsls r5, r0
  15270. 8006eb2: 420d tst r5, r1
  15271. 8006eb4: f43f ad72 beq.w 800699c <HAL_DMA_IRQHandler+0x118>
  15272. 8006eb8: 0715 lsls r5, r2, #28
  15273. 8006eba: f57f ad6f bpl.w 800699c <HAL_DMA_IRQHandler+0x118>
  15274. __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
  15275. 8006ebe: 681a ldr r2, [r3, #0]
  15276. __HAL_UNLOCK(hdma);
  15277. 8006ec0: 2100 movs r1, #0
  15278. __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
  15279. 8006ec2: f022 020e bic.w r2, r2, #14
  15280. 8006ec6: 601a str r2, [r3, #0]
  15281. regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
  15282. 8006ec8: 2301 movs r3, #1
  15283. if (hdma->XferErrorCallback != NULL)
  15284. 8006eca: 6cf2 ldr r2, [r6, #76] @ 0x4c
  15285. regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
  15286. 8006ecc: fa03 f000 lsl.w r0, r3, r0
  15287. 8006ed0: 6060 str r0, [r4, #4]
  15288. hdma->ErrorCode = HAL_DMA_ERROR_TE;
  15289. 8006ed2: 6573 str r3, [r6, #84] @ 0x54
  15290. __HAL_UNLOCK(hdma);
  15291. 8006ed4: f886 1034 strb.w r1, [r6, #52] @ 0x34
  15292. hdma->State = HAL_DMA_STATE_READY;
  15293. 8006ed8: f886 3035 strb.w r3, [r6, #53] @ 0x35
  15294. if (hdma->XferErrorCallback != NULL)
  15295. 8006edc: 2a00 cmp r2, #0
  15296. 8006ede: f43f ad5d beq.w 800699c <HAL_DMA_IRQHandler+0x118>
  15297. hdma->XferErrorCallback(hdma);
  15298. 8006ee2: 4630 mov r0, r6
  15299. }
  15300. 8006ee4: b002 add sp, #8
  15301. 8006ee6: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
  15302. hdma->XferErrorCallback(hdma);
  15303. 8006eea: 4710 bx r2
  15304. if((ccr_reg & BDMA_CCR_CIRC) == 0U)
  15305. 8006eec: 0692 lsls r2, r2, #26
  15306. 8006eee: d403 bmi.n 8006ef8 <HAL_DMA_IRQHandler+0x674>
  15307. __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
  15308. 8006ef0: 681a ldr r2, [r3, #0]
  15309. 8006ef2: f022 0204 bic.w r2, r2, #4
  15310. 8006ef6: 601a str r2, [r3, #0]
  15311. if(hdma->XferHalfCpltCallback != NULL)
  15312. 8006ef8: 6c33 ldr r3, [r6, #64] @ 0x40
  15313. 8006efa: 2b00 cmp r3, #0
  15314. 8006efc: f47f af42 bne.w 8006d84 <HAL_DMA_IRQHandler+0x500>
  15315. 8006f00: e54c b.n 800699c <HAL_DMA_IRQHandler+0x118>
  15316. if((ccr_reg & BDMA_CCR_CIRC) == 0U)
  15317. 8006f02: f012 0220 ands.w r2, r2, #32
  15318. 8006f06: d108 bne.n 8006f1a <HAL_DMA_IRQHandler+0x696>
  15319. __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
  15320. 8006f08: 6819 ldr r1, [r3, #0]
  15321. hdma->State = HAL_DMA_STATE_READY;
  15322. 8006f0a: 2001 movs r0, #1
  15323. __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
  15324. 8006f0c: f021 010a bic.w r1, r1, #10
  15325. 8006f10: 6019 str r1, [r3, #0]
  15326. hdma->State = HAL_DMA_STATE_READY;
  15327. 8006f12: f886 0035 strb.w r0, [r6, #53] @ 0x35
  15328. __HAL_UNLOCK(hdma);
  15329. 8006f16: f886 2034 strb.w r2, [r6, #52] @ 0x34
  15330. if(hdma->XferCpltCallback != NULL)
  15331. 8006f1a: 6bf3 ldr r3, [r6, #60] @ 0x3c
  15332. 8006f1c: 2b00 cmp r3, #0
  15333. 8006f1e: f47f af31 bne.w 8006d84 <HAL_DMA_IRQHandler+0x500>
  15334. 8006f22: e53b b.n 800699c <HAL_DMA_IRQHandler+0x118>
  15335. 8006f24: 400204b8 .word 0x400204b8
  15336. 8006f28: 1b4e81b5 .word 0x1b4e81b5
  15337. 08006f2c <HAL_GPIO_Init>:
  15338. * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  15339. * the configuration information for the specified GPIO peripheral.
  15340. * @retval None
  15341. */
  15342. void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
  15343. {
  15344. 8006f2c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  15345. assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  15346. assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  15347. assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
  15348. /* Configure the port pins */
  15349. while (((GPIO_Init->Pin) >> position) != 0x00U)
  15350. 8006f30: 680c ldr r4, [r1, #0]
  15351. {
  15352. 8006f32: b085 sub sp, #20
  15353. while (((GPIO_Init->Pin) >> position) != 0x00U)
  15354. 8006f34: 2c00 cmp r4, #0
  15355. 8006f36: f000 80a5 beq.w 8007084 <HAL_GPIO_Init+0x158>
  15356. uint32_t position = 0x00U;
  15357. 8006f3a: 2300 movs r3, #0
  15358. {
  15359. /* Get current io position */
  15360. iocurrent = (GPIO_Init->Pin) & (1UL << position);
  15361. 8006f3c: f04f 0b01 mov.w fp, #1
  15362. temp &= ~(0x0FUL << (4U * (position & 0x03U)));
  15363. temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
  15364. SYSCFG->EXTICR[position >> 2U] = temp;
  15365. /* Clear Rising Falling edge configuration */
  15366. temp = EXTI->RTSR1;
  15367. 8006f40: f04f 4eb0 mov.w lr, #1476395008 @ 0x58000000
  15368. temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
  15369. 8006f44: 9100 str r1, [sp, #0]
  15370. iocurrent = (GPIO_Init->Pin) & (1UL << position);
  15371. 8006f46: fa0b fc03 lsl.w ip, fp, r3
  15372. if (iocurrent != 0x00U)
  15373. 8006f4a: ea1c 0a04 ands.w sl, ip, r4
  15374. 8006f4e: f000 8094 beq.w 800707a <HAL_GPIO_Init+0x14e>
  15375. if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
  15376. 8006f52: 9900 ldr r1, [sp, #0]
  15377. 8006f54: 005f lsls r7, r3, #1
  15378. 8006f56: 684d ldr r5, [r1, #4]
  15379. temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
  15380. 8006f58: 2103 movs r1, #3
  15381. if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
  15382. 8006f5a: f005 0203 and.w r2, r5, #3
  15383. temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
  15384. 8006f5e: fa01 f607 lsl.w r6, r1, r7
  15385. if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
  15386. 8006f62: f102 38ff add.w r8, r2, #4294967295 @ 0xffffffff
  15387. temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
  15388. 8006f66: 43f6 mvns r6, r6
  15389. if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
  15390. 8006f68: f1b8 0f01 cmp.w r8, #1
  15391. 8006f6c: f240 808d bls.w 800708a <HAL_GPIO_Init+0x15e>
  15392. if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
  15393. 8006f70: 2a03 cmp r2, #3
  15394. 8006f72: f040 80cb bne.w 800710c <HAL_GPIO_Init+0x1e0>
  15395. temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
  15396. 8006f76: 40ba lsls r2, r7
  15397. temp = GPIOx->MODER;
  15398. 8006f78: 6807 ldr r7, [r0, #0]
  15399. if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
  15400. 8006f7a: f415 3f40 tst.w r5, #196608 @ 0x30000
  15401. temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
  15402. 8006f7e: ea06 0607 and.w r6, r6, r7
  15403. temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
  15404. 8006f82: ea42 0206 orr.w r2, r2, r6
  15405. GPIOx->MODER = temp;
  15406. 8006f86: 6002 str r2, [r0, #0]
  15407. if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
  15408. 8006f88: d077 beq.n 800707a <HAL_GPIO_Init+0x14e>
  15409. __HAL_RCC_SYSCFG_CLK_ENABLE();
  15410. 8006f8a: 4e7f ldr r6, [pc, #508] @ (8007188 <HAL_GPIO_Init+0x25c>)
  15411. temp &= ~(0x0FUL << (4U * (position & 0x03U)));
  15412. 8006f8c: f003 0703 and.w r7, r3, #3
  15413. 8006f90: 210f movs r1, #15
  15414. __HAL_RCC_SYSCFG_CLK_ENABLE();
  15415. 8006f92: f8d6 20f4 ldr.w r2, [r6, #244] @ 0xf4
  15416. temp &= ~(0x0FUL << (4U * (position & 0x03U)));
  15417. 8006f96: 00bf lsls r7, r7, #2
  15418. __HAL_RCC_SYSCFG_CLK_ENABLE();
  15419. 8006f98: f042 0202 orr.w r2, r2, #2
  15420. temp &= ~(0x0FUL << (4U * (position & 0x03U)));
  15421. 8006f9c: fa01 fc07 lsl.w ip, r1, r7
  15422. temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
  15423. 8006fa0: 497a ldr r1, [pc, #488] @ (800718c <HAL_GPIO_Init+0x260>)
  15424. __HAL_RCC_SYSCFG_CLK_ENABLE();
  15425. 8006fa2: f8c6 20f4 str.w r2, [r6, #244] @ 0xf4
  15426. 8006fa6: f8d6 20f4 ldr.w r2, [r6, #244] @ 0xf4
  15427. 8006faa: f023 0603 bic.w r6, r3, #3
  15428. temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
  15429. 8006fae: 4288 cmp r0, r1
  15430. 8006fb0: f106 46b0 add.w r6, r6, #1476395008 @ 0x58000000
  15431. __HAL_RCC_SYSCFG_CLK_ENABLE();
  15432. 8006fb4: f002 0202 and.w r2, r2, #2
  15433. 8006fb8: f506 6680 add.w r6, r6, #1024 @ 0x400
  15434. 8006fbc: 9203 str r2, [sp, #12]
  15435. 8006fbe: 9a03 ldr r2, [sp, #12]
  15436. temp = SYSCFG->EXTICR[position >> 2U];
  15437. 8006fc0: 68b2 ldr r2, [r6, #8]
  15438. temp &= ~(0x0FUL << (4U * (position & 0x03U)));
  15439. 8006fc2: ea22 020c bic.w r2, r2, ip
  15440. temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
  15441. 8006fc6: d031 beq.n 800702c <HAL_GPIO_Init+0x100>
  15442. 8006fc8: f501 6180 add.w r1, r1, #1024 @ 0x400
  15443. 8006fcc: 4288 cmp r0, r1
  15444. 8006fce: f000 80b0 beq.w 8007132 <HAL_GPIO_Init+0x206>
  15445. 8006fd2: 496f ldr r1, [pc, #444] @ (8007190 <HAL_GPIO_Init+0x264>)
  15446. 8006fd4: 4288 cmp r0, r1
  15447. 8006fd6: f000 80b2 beq.w 800713e <HAL_GPIO_Init+0x212>
  15448. 8006fda: f8df c1b8 ldr.w ip, [pc, #440] @ 8007194 <HAL_GPIO_Init+0x268>
  15449. 8006fde: 4560 cmp r0, ip
  15450. 8006fe0: f000 80a1 beq.w 8007126 <HAL_GPIO_Init+0x1fa>
  15451. 8006fe4: f8df c1b0 ldr.w ip, [pc, #432] @ 8007198 <HAL_GPIO_Init+0x26c>
  15452. 8006fe8: 4560 cmp r0, ip
  15453. 8006fea: f000 80b4 beq.w 8007156 <HAL_GPIO_Init+0x22a>
  15454. 8006fee: f8df c1ac ldr.w ip, [pc, #428] @ 800719c <HAL_GPIO_Init+0x270>
  15455. 8006ff2: 4560 cmp r0, ip
  15456. 8006ff4: f000 80b5 beq.w 8007162 <HAL_GPIO_Init+0x236>
  15457. 8006ff8: f8df c1a4 ldr.w ip, [pc, #420] @ 80071a0 <HAL_GPIO_Init+0x274>
  15458. 8006ffc: 4560 cmp r0, ip
  15459. 8006ffe: f000 80a4 beq.w 800714a <HAL_GPIO_Init+0x21e>
  15460. 8007002: f8df c1a0 ldr.w ip, [pc, #416] @ 80071a4 <HAL_GPIO_Init+0x278>
  15461. 8007006: 4560 cmp r0, ip
  15462. 8007008: f000 80b1 beq.w 800716e <HAL_GPIO_Init+0x242>
  15463. 800700c: f8df c198 ldr.w ip, [pc, #408] @ 80071a8 <HAL_GPIO_Init+0x27c>
  15464. 8007010: 4560 cmp r0, ip
  15465. 8007012: f000 80b2 beq.w 800717a <HAL_GPIO_Init+0x24e>
  15466. 8007016: f8df c194 ldr.w ip, [pc, #404] @ 80071ac <HAL_GPIO_Init+0x280>
  15467. 800701a: 4560 cmp r0, ip
  15468. 800701c: bf0c ite eq
  15469. 800701e: f04f 0c09 moveq.w ip, #9
  15470. 8007022: f04f 0c0a movne.w ip, #10
  15471. 8007026: fa0c f707 lsl.w r7, ip, r7
  15472. 800702a: 433a orrs r2, r7
  15473. SYSCFG->EXTICR[position >> 2U] = temp;
  15474. 800702c: 60b2 str r2, [r6, #8]
  15475. temp &= ~(iocurrent);
  15476. if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
  15477. 800702e: 02ef lsls r7, r5, #11
  15478. temp = EXTI->RTSR1;
  15479. 8007030: f8de 2000 ldr.w r2, [lr]
  15480. temp &= ~(iocurrent);
  15481. 8007034: ea6f 060a mvn.w r6, sl
  15482. {
  15483. temp |= iocurrent;
  15484. 8007038: bf4c ite mi
  15485. 800703a: ea4a 0202 orrmi.w r2, sl, r2
  15486. temp &= ~(iocurrent);
  15487. 800703e: 4032 andpl r2, r6
  15488. }
  15489. EXTI->RTSR1 = temp;
  15490. temp = EXTI->FTSR1;
  15491. temp &= ~(iocurrent);
  15492. if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
  15493. 8007040: 02a9 lsls r1, r5, #10
  15494. EXTI->RTSR1 = temp;
  15495. 8007042: f8ce 2000 str.w r2, [lr]
  15496. temp = EXTI->FTSR1;
  15497. 8007046: f8de 2004 ldr.w r2, [lr, #4]
  15498. temp &= ~(iocurrent);
  15499. 800704a: bf54 ite pl
  15500. 800704c: 4032 andpl r2, r6
  15501. {
  15502. temp |= iocurrent;
  15503. 800704e: ea4a 0202 orrmi.w r2, sl, r2
  15504. }
  15505. EXTI->FTSR1 = temp;
  15506. temp = EXTI_CurrentCPU->EMR1;
  15507. temp &= ~(iocurrent);
  15508. if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
  15509. 8007052: 03af lsls r7, r5, #14
  15510. EXTI->FTSR1 = temp;
  15511. 8007054: f8ce 2004 str.w r2, [lr, #4]
  15512. temp = EXTI_CurrentCPU->EMR1;
  15513. 8007058: f8de 2084 ldr.w r2, [lr, #132] @ 0x84
  15514. temp &= ~(iocurrent);
  15515. 800705c: bf54 ite pl
  15516. 800705e: 4032 andpl r2, r6
  15517. {
  15518. temp |= iocurrent;
  15519. 8007060: ea4a 0202 orrmi.w r2, sl, r2
  15520. EXTI_CurrentCPU->EMR1 = temp;
  15521. /* Clear EXTI line configuration */
  15522. temp = EXTI_CurrentCPU->IMR1;
  15523. temp &= ~(iocurrent);
  15524. if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
  15525. 8007064: 03e9 lsls r1, r5, #15
  15526. EXTI_CurrentCPU->EMR1 = temp;
  15527. 8007066: f8ce 2084 str.w r2, [lr, #132] @ 0x84
  15528. temp = EXTI_CurrentCPU->IMR1;
  15529. 800706a: f8de 2080 ldr.w r2, [lr, #128] @ 0x80
  15530. temp &= ~(iocurrent);
  15531. 800706e: bf54 ite pl
  15532. 8007070: 4032 andpl r2, r6
  15533. {
  15534. temp |= iocurrent;
  15535. 8007072: ea4a 0202 orrmi.w r2, sl, r2
  15536. }
  15537. EXTI_CurrentCPU->IMR1 = temp;
  15538. 8007076: f8ce 2080 str.w r2, [lr, #128] @ 0x80
  15539. }
  15540. }
  15541. position++;
  15542. 800707a: 3301 adds r3, #1
  15543. while (((GPIO_Init->Pin) >> position) != 0x00U)
  15544. 800707c: fa34 f203 lsrs.w r2, r4, r3
  15545. 8007080: f47f af61 bne.w 8006f46 <HAL_GPIO_Init+0x1a>
  15546. }
  15547. }
  15548. 8007084: b005 add sp, #20
  15549. 8007086: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  15550. temp |= (GPIO_Init->Speed << (position * 2U));
  15551. 800708a: 9900 ldr r1, [sp, #0]
  15552. if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
  15553. 800708c: 2a02 cmp r2, #2
  15554. temp = GPIOx->OSPEEDR;
  15555. 800708e: f8d0 9008 ldr.w r9, [r0, #8]
  15556. temp |= (GPIO_Init->Speed << (position * 2U));
  15557. 8007092: 68c9 ldr r1, [r1, #12]
  15558. temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
  15559. 8007094: ea09 0906 and.w r9, r9, r6
  15560. temp |= (GPIO_Init->Speed << (position * 2U));
  15561. 8007098: fa01 f807 lsl.w r8, r1, r7
  15562. temp |= ((GPIO_Init->Pull) << (position * 2U));
  15563. 800709c: 9900 ldr r1, [sp, #0]
  15564. temp |= (GPIO_Init->Speed << (position * 2U));
  15565. 800709e: ea48 0809 orr.w r8, r8, r9
  15566. temp |= ((GPIO_Init->Pull) << (position * 2U));
  15567. 80070a2: 6889 ldr r1, [r1, #8]
  15568. GPIOx->OSPEEDR = temp;
  15569. 80070a4: f8c0 8008 str.w r8, [r0, #8]
  15570. temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
  15571. 80070a8: f3c5 1800 ubfx r8, r5, #4, #1
  15572. temp = GPIOx->OTYPER;
  15573. 80070ac: f8d0 9004 ldr.w r9, [r0, #4]
  15574. temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
  15575. 80070b0: fa08 f803 lsl.w r8, r8, r3
  15576. temp &= ~(GPIO_OTYPER_OT0 << position) ;
  15577. 80070b4: ea29 0c0c bic.w ip, r9, ip
  15578. temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
  15579. 80070b8: ea48 0c0c orr.w ip, r8, ip
  15580. GPIOx->OTYPER = temp;
  15581. 80070bc: f8c0 c004 str.w ip, [r0, #4]
  15582. temp |= ((GPIO_Init->Pull) << (position * 2U));
  15583. 80070c0: fa01 fc07 lsl.w ip, r1, r7
  15584. temp = GPIOx->PUPDR;
  15585. 80070c4: f8d0 800c ldr.w r8, [r0, #12]
  15586. temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
  15587. 80070c8: ea08 0806 and.w r8, r8, r6
  15588. temp |= ((GPIO_Init->Pull) << (position * 2U));
  15589. 80070cc: ea4c 0c08 orr.w ip, ip, r8
  15590. GPIOx->PUPDR = temp;
  15591. 80070d0: f8c0 c00c str.w ip, [r0, #12]
  15592. if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
  15593. 80070d4: f47f af4f bne.w 8006f76 <HAL_GPIO_Init+0x4a>
  15594. temp &= ~(0xFU << ((position & 0x07U) * 4U));
  15595. 80070d8: f003 0c07 and.w ip, r3, #7
  15596. temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
  15597. 80070dc: 9900 ldr r1, [sp, #0]
  15598. temp = GPIOx->AFR[position >> 3U];
  15599. 80070de: ea4f 08d3 mov.w r8, r3, lsr #3
  15600. temp &= ~(0xFU << ((position & 0x07U) * 4U));
  15601. 80070e2: ea4f 0c8c mov.w ip, ip, lsl #2
  15602. temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
  15603. 80070e6: 6909 ldr r1, [r1, #16]
  15604. 80070e8: eb00 0888 add.w r8, r0, r8, lsl #2
  15605. 80070ec: fa01 f10c lsl.w r1, r1, ip
  15606. temp = GPIOx->AFR[position >> 3U];
  15607. 80070f0: f8d8 9020 ldr.w r9, [r8, #32]
  15608. temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
  15609. 80070f4: 9101 str r1, [sp, #4]
  15610. temp &= ~(0xFU << ((position & 0x07U) * 4U));
  15611. 80070f6: 210f movs r1, #15
  15612. 80070f8: fa01 fc0c lsl.w ip, r1, ip
  15613. temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
  15614. 80070fc: 9901 ldr r1, [sp, #4]
  15615. temp &= ~(0xFU << ((position & 0x07U) * 4U));
  15616. 80070fe: ea29 090c bic.w r9, r9, ip
  15617. temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
  15618. 8007102: ea41 0c09 orr.w ip, r1, r9
  15619. GPIOx->AFR[position >> 3U] = temp;
  15620. 8007106: f8c8 c020 str.w ip, [r8, #32]
  15621. 800710a: e734 b.n 8006f76 <HAL_GPIO_Init+0x4a>
  15622. temp |= ((GPIO_Init->Pull) << (position * 2U));
  15623. 800710c: 9900 ldr r1, [sp, #0]
  15624. temp = GPIOx->PUPDR;
  15625. 800710e: f8d0 800c ldr.w r8, [r0, #12]
  15626. temp |= ((GPIO_Init->Pull) << (position * 2U));
  15627. 8007112: 6889 ldr r1, [r1, #8]
  15628. temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
  15629. 8007114: ea08 0806 and.w r8, r8, r6
  15630. temp |= ((GPIO_Init->Pull) << (position * 2U));
  15631. 8007118: fa01 fc07 lsl.w ip, r1, r7
  15632. 800711c: ea4c 0c08 orr.w ip, ip, r8
  15633. GPIOx->PUPDR = temp;
  15634. 8007120: f8c0 c00c str.w ip, [r0, #12]
  15635. if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
  15636. 8007124: e727 b.n 8006f76 <HAL_GPIO_Init+0x4a>
  15637. temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
  15638. 8007126: f04f 0c03 mov.w ip, #3
  15639. 800712a: fa0c f707 lsl.w r7, ip, r7
  15640. 800712e: 433a orrs r2, r7
  15641. 8007130: e77c b.n 800702c <HAL_GPIO_Init+0x100>
  15642. 8007132: f04f 0c01 mov.w ip, #1
  15643. 8007136: fa0c f707 lsl.w r7, ip, r7
  15644. 800713a: 433a orrs r2, r7
  15645. 800713c: e776 b.n 800702c <HAL_GPIO_Init+0x100>
  15646. 800713e: f04f 0c02 mov.w ip, #2
  15647. 8007142: fa0c f707 lsl.w r7, ip, r7
  15648. 8007146: 433a orrs r2, r7
  15649. 8007148: e770 b.n 800702c <HAL_GPIO_Init+0x100>
  15650. 800714a: f04f 0c06 mov.w ip, #6
  15651. 800714e: fa0c f707 lsl.w r7, ip, r7
  15652. 8007152: 433a orrs r2, r7
  15653. 8007154: e76a b.n 800702c <HAL_GPIO_Init+0x100>
  15654. 8007156: f04f 0c04 mov.w ip, #4
  15655. 800715a: fa0c f707 lsl.w r7, ip, r7
  15656. 800715e: 433a orrs r2, r7
  15657. 8007160: e764 b.n 800702c <HAL_GPIO_Init+0x100>
  15658. 8007162: f04f 0c05 mov.w ip, #5
  15659. 8007166: fa0c f707 lsl.w r7, ip, r7
  15660. 800716a: 433a orrs r2, r7
  15661. 800716c: e75e b.n 800702c <HAL_GPIO_Init+0x100>
  15662. 800716e: f04f 0c07 mov.w ip, #7
  15663. 8007172: fa0c f707 lsl.w r7, ip, r7
  15664. 8007176: 433a orrs r2, r7
  15665. 8007178: e758 b.n 800702c <HAL_GPIO_Init+0x100>
  15666. 800717a: f04f 0c08 mov.w ip, #8
  15667. 800717e: fa0c f707 lsl.w r7, ip, r7
  15668. 8007182: 433a orrs r2, r7
  15669. 8007184: e752 b.n 800702c <HAL_GPIO_Init+0x100>
  15670. 8007186: bf00 nop
  15671. 8007188: 58024400 .word 0x58024400
  15672. 800718c: 58020000 .word 0x58020000
  15673. 8007190: 58020800 .word 0x58020800
  15674. 8007194: 58020c00 .word 0x58020c00
  15675. 8007198: 58021000 .word 0x58021000
  15676. 800719c: 58021400 .word 0x58021400
  15677. 80071a0: 58021800 .word 0x58021800
  15678. 80071a4: 58021c00 .word 0x58021c00
  15679. 80071a8: 58022000 .word 0x58022000
  15680. 80071ac: 58022400 .word 0x58022400
  15681. 080071b0 <HAL_GPIO_ReadPin>:
  15682. GPIO_PinState bitstatus;
  15683. /* Check the parameters */
  15684. assert_param(IS_GPIO_PIN(GPIO_Pin));
  15685. if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
  15686. 80071b0: 6903 ldr r3, [r0, #16]
  15687. 80071b2: 4219 tst r1, r3
  15688. else
  15689. {
  15690. bitstatus = GPIO_PIN_RESET;
  15691. }
  15692. return bitstatus;
  15693. }
  15694. 80071b4: bf14 ite ne
  15695. 80071b6: 2001 movne r0, #1
  15696. 80071b8: 2000 moveq r0, #0
  15697. 80071ba: 4770 bx lr
  15698. 080071bc <HAL_GPIO_WritePin>:
  15699. {
  15700. /* Check the parameters */
  15701. assert_param(IS_GPIO_PIN(GPIO_Pin));
  15702. assert_param(IS_GPIO_PIN_ACTION(PinState));
  15703. if (PinState != GPIO_PIN_RESET)
  15704. 80071bc: b902 cbnz r2, 80071c0 <HAL_GPIO_WritePin+0x4>
  15705. {
  15706. GPIOx->BSRR = GPIO_Pin;
  15707. }
  15708. else
  15709. {
  15710. GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
  15711. 80071be: 0409 lsls r1, r1, #16
  15712. 80071c0: 6181 str r1, [r0, #24]
  15713. }
  15714. }
  15715. 80071c2: 4770 bx lr
  15716. 080071c4 <HAL_GPIO_TogglePin>:
  15717. /* Check the parameters */
  15718. assert_param(IS_GPIO_PIN(GPIO_Pin));
  15719. /* get current Output Data Register value */
  15720. odr = GPIOx->ODR;
  15721. 80071c4: 6943 ldr r3, [r0, #20]
  15722. /* Set selected pins that were at low level, and reset ones that were high */
  15723. GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
  15724. 80071c6: ea01 0203 and.w r2, r1, r3
  15725. 80071ca: ea21 0103 bic.w r1, r1, r3
  15726. 80071ce: ea41 4102 orr.w r1, r1, r2, lsl #16
  15727. 80071d2: 6181 str r1, [r0, #24]
  15728. }
  15729. 80071d4: 4770 bx lr
  15730. 80071d6: bf00 nop
  15731. 080071d8 <HAL_GPIO_EXTI_IRQHandler>:
  15732. __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);
  15733. HAL_GPIO_EXTI_Callback(GPIO_Pin);
  15734. }
  15735. #else
  15736. /* EXTI line interrupt detected */
  15737. if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U)
  15738. 80071d8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
  15739. 80071dc: f8d2 1088 ldr.w r1, [r2, #136] @ 0x88
  15740. 80071e0: 4201 tst r1, r0
  15741. 80071e2: d100 bne.n 80071e6 <HAL_GPIO_EXTI_IRQHandler+0xe>
  15742. 80071e4: 4770 bx lr
  15743. {
  15744. 80071e6: b508 push {r3, lr}
  15745. {
  15746. __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
  15747. 80071e8: f8c2 0088 str.w r0, [r2, #136] @ 0x88
  15748. HAL_GPIO_EXTI_Callback(GPIO_Pin);
  15749. 80071ec: f7f9 faa0 bl 8000730 <HAL_GPIO_EXTI_Callback>
  15750. }
  15751. #endif
  15752. }
  15753. 80071f0: bd08 pop {r3, pc}
  15754. 80071f2: bf00 nop
  15755. 080071f4 <HAL_IWDG_Init>:
  15756. HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
  15757. {
  15758. uint32_t tickstart;
  15759. /* Check the IWDG handle allocation */
  15760. if (hiwdg == NULL)
  15761. 80071f4: b328 cbz r0, 8007242 <HAL_IWDG_Init+0x4e>
  15762. 0x5555 in KR */
  15763. IWDG_ENABLE_WRITE_ACCESS(hiwdg);
  15764. /* Write to IWDG registers the Prescaler & Reload values to work with */
  15765. hiwdg->Instance->PR = hiwdg->Init.Prescaler;
  15766. hiwdg->Instance->RLR = hiwdg->Init.Reload;
  15767. 80071f6: 6882 ldr r2, [r0, #8]
  15768. {
  15769. 80071f8: b538 push {r3, r4, r5, lr}
  15770. hiwdg->Instance->PR = hiwdg->Init.Prescaler;
  15771. 80071fa: e9d0 3100 ldrd r3, r1, [r0]
  15772. 80071fe: 4604 mov r4, r0
  15773. __HAL_IWDG_START(hiwdg);
  15774. 8007200: f64c 40cc movw r0, #52428 @ 0xcccc
  15775. 8007204: 6018 str r0, [r3, #0]
  15776. IWDG_ENABLE_WRITE_ACCESS(hiwdg);
  15777. 8007206: f245 5055 movw r0, #21845 @ 0x5555
  15778. 800720a: 6018 str r0, [r3, #0]
  15779. hiwdg->Instance->PR = hiwdg->Init.Prescaler;
  15780. 800720c: 6059 str r1, [r3, #4]
  15781. hiwdg->Instance->RLR = hiwdg->Init.Reload;
  15782. 800720e: 609a str r2, [r3, #8]
  15783. /* Check pending flag, if previous update not done, return timeout */
  15784. tickstart = HAL_GetTick();
  15785. 8007210: f7fc fede bl 8003fd0 <HAL_GetTick>
  15786. /* Wait for register to be updated */
  15787. while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
  15788. 8007214: 6823 ldr r3, [r4, #0]
  15789. tickstart = HAL_GetTick();
  15790. 8007216: 4605 mov r5, r0
  15791. while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
  15792. 8007218: 68da ldr r2, [r3, #12]
  15793. 800721a: 0751 lsls r1, r2, #29
  15794. 800721c: d00a beq.n 8007234 <HAL_IWDG_Init+0x40>
  15795. {
  15796. if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
  15797. 800721e: f7fc fed7 bl 8003fd0 <HAL_GetTick>
  15798. 8007222: 1b40 subs r0, r0, r5
  15799. {
  15800. if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
  15801. 8007224: 6823 ldr r3, [r4, #0]
  15802. if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
  15803. 8007226: 2831 cmp r0, #49 @ 0x31
  15804. 8007228: d9f6 bls.n 8007218 <HAL_IWDG_Init+0x24>
  15805. if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
  15806. 800722a: 68da ldr r2, [r3, #12]
  15807. 800722c: 0752 lsls r2, r2, #29
  15808. 800722e: d0f3 beq.n 8007218 <HAL_IWDG_Init+0x24>
  15809. {
  15810. return HAL_TIMEOUT;
  15811. 8007230: 2003 movs r0, #3
  15812. __HAL_IWDG_RELOAD_COUNTER(hiwdg);
  15813. }
  15814. /* Return function status */
  15815. return HAL_OK;
  15816. }
  15817. 8007232: bd38 pop {r3, r4, r5, pc}
  15818. if (hiwdg->Instance->WINR != hiwdg->Init.Window)
  15819. 8007234: 6919 ldr r1, [r3, #16]
  15820. 8007236: 68e2 ldr r2, [r4, #12]
  15821. 8007238: 4291 cmp r1, r2
  15822. 800723a: d004 beq.n 8007246 <HAL_IWDG_Init+0x52>
  15823. hiwdg->Instance->WINR = hiwdg->Init.Window;
  15824. 800723c: 611a str r2, [r3, #16]
  15825. return HAL_OK;
  15826. 800723e: 2000 movs r0, #0
  15827. }
  15828. 8007240: bd38 pop {r3, r4, r5, pc}
  15829. return HAL_ERROR;
  15830. 8007242: 2001 movs r0, #1
  15831. }
  15832. 8007244: 4770 bx lr
  15833. __HAL_IWDG_RELOAD_COUNTER(hiwdg);
  15834. 8007246: f64a 22aa movw r2, #43690 @ 0xaaaa
  15835. 800724a: 601a str r2, [r3, #0]
  15836. 800724c: e7f7 b.n 800723e <HAL_IWDG_Init+0x4a>
  15837. 800724e: bf00 nop
  15838. 08007250 <HAL_IWDG_Refresh>:
  15839. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
  15840. * the configuration information for the specified IWDG module.
  15841. * @retval HAL status
  15842. */
  15843. HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
  15844. {
  15845. 8007250: 4603 mov r3, r0
  15846. /* Reload IWDG counter with value defined in the reload register */
  15847. __HAL_IWDG_RELOAD_COUNTER(hiwdg);
  15848. 8007252: f64a 22aa movw r2, #43690 @ 0xaaaa
  15849. /* Return function status */
  15850. return HAL_OK;
  15851. }
  15852. 8007256: 2000 movs r0, #0
  15853. __HAL_IWDG_RELOAD_COUNTER(hiwdg);
  15854. 8007258: 681b ldr r3, [r3, #0]
  15855. 800725a: 601a str r2, [r3, #0]
  15856. }
  15857. 800725c: 4770 bx lr
  15858. 800725e: bf00 nop
  15859. 08007260 <HAL_PWR_ConfigPVD>:
  15860. * @retval None.
  15861. */
  15862. void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
  15863. {
  15864. /* Check the PVD configuration parameter */
  15865. if (sConfigPVD == NULL)
  15866. 8007260: 2800 cmp r0, #0
  15867. 8007262: d043 beq.n 80072ec <HAL_PWR_ConfigPVD+0x8c>
  15868. /* Check the parameters */
  15869. assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
  15870. assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
  15871. /* Set PLS[7:5] bits according to PVDLevel value */
  15872. MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
  15873. 8007264: 4922 ldr r1, [pc, #136] @ (80072f0 <HAL_PWR_ConfigPVD+0x90>)
  15874. /* Clear previous config */
  15875. #if !defined (DUAL_CORE)
  15876. __HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
  15877. 8007266: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
  15878. MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
  15879. 800726a: 680a ldr r2, [r1, #0]
  15880. {
  15881. 800726c: b410 push {r4}
  15882. MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
  15883. 800726e: f022 02e0 bic.w r2, r2, #224 @ 0xe0
  15884. 8007272: 6804 ldr r4, [r0, #0]
  15885. 8007274: 4322 orrs r2, r4
  15886. 8007276: 600a str r2, [r1, #0]
  15887. __HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
  15888. 8007278: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84
  15889. 800727c: f422 3280 bic.w r2, r2, #65536 @ 0x10000
  15890. 8007280: f8c3 2084 str.w r2, [r3, #132] @ 0x84
  15891. __HAL_PWR_PVD_EXTI_DISABLE_IT ();
  15892. 8007284: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80
  15893. 8007288: f422 3280 bic.w r2, r2, #65536 @ 0x10000
  15894. 800728c: f8c3 2080 str.w r2, [r3, #128] @ 0x80
  15895. #endif /* !defined (DUAL_CORE) */
  15896. __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
  15897. 8007290: 681a ldr r2, [r3, #0]
  15898. 8007292: f422 3280 bic.w r2, r2, #65536 @ 0x10000
  15899. 8007296: 601a str r2, [r3, #0]
  15900. __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
  15901. 8007298: 685a ldr r2, [r3, #4]
  15902. 800729a: f422 3280 bic.w r2, r2, #65536 @ 0x10000
  15903. 800729e: 605a str r2, [r3, #4]
  15904. #if !defined (DUAL_CORE)
  15905. /* Interrupt mode configuration */
  15906. if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
  15907. 80072a0: 6842 ldr r2, [r0, #4]
  15908. 80072a2: 03d4 lsls r4, r2, #15
  15909. 80072a4: d505 bpl.n 80072b2 <HAL_PWR_ConfigPVD+0x52>
  15910. {
  15911. __HAL_PWR_PVD_EXTI_ENABLE_IT ();
  15912. 80072a6: f8d3 1080 ldr.w r1, [r3, #128] @ 0x80
  15913. 80072aa: f441 3180 orr.w r1, r1, #65536 @ 0x10000
  15914. 80072ae: f8c3 1080 str.w r1, [r3, #128] @ 0x80
  15915. }
  15916. /* Event mode configuration */
  15917. if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
  15918. 80072b2: 0390 lsls r0, r2, #14
  15919. 80072b4: d507 bpl.n 80072c6 <HAL_PWR_ConfigPVD+0x66>
  15920. {
  15921. __HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
  15922. 80072b6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
  15923. 80072ba: f8d1 3084 ldr.w r3, [r1, #132] @ 0x84
  15924. 80072be: f443 3380 orr.w r3, r3, #65536 @ 0x10000
  15925. 80072c2: f8c1 3084 str.w r3, [r1, #132] @ 0x84
  15926. }
  15927. #endif /* !defined (DUAL_CORE) */
  15928. /* Rising edge configuration */
  15929. if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
  15930. 80072c6: 07d1 lsls r1, r2, #31
  15931. 80072c8: d505 bpl.n 80072d6 <HAL_PWR_ConfigPVD+0x76>
  15932. {
  15933. __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
  15934. 80072ca: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
  15935. 80072ce: 680b ldr r3, [r1, #0]
  15936. 80072d0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
  15937. 80072d4: 600b str r3, [r1, #0]
  15938. }
  15939. /* Falling edge configuration */
  15940. if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
  15941. 80072d6: 0793 lsls r3, r2, #30
  15942. 80072d8: d505 bpl.n 80072e6 <HAL_PWR_ConfigPVD+0x86>
  15943. {
  15944. __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
  15945. 80072da: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
  15946. 80072de: 6853 ldr r3, [r2, #4]
  15947. 80072e0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
  15948. 80072e4: 6053 str r3, [r2, #4]
  15949. }
  15950. }
  15951. 80072e6: f85d 4b04 ldr.w r4, [sp], #4
  15952. 80072ea: 4770 bx lr
  15953. 80072ec: 4770 bx lr
  15954. 80072ee: bf00 nop
  15955. 80072f0: 58024800 .word 0x58024800
  15956. 080072f4 <HAL_PWR_EnablePVD>:
  15957. * @retval None.
  15958. */
  15959. void HAL_PWR_EnablePVD (void)
  15960. {
  15961. /* Enable the power voltage detector */
  15962. SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
  15963. 80072f4: 4a02 ldr r2, [pc, #8] @ (8007300 <HAL_PWR_EnablePVD+0xc>)
  15964. 80072f6: 6813 ldr r3, [r2, #0]
  15965. 80072f8: f043 0310 orr.w r3, r3, #16
  15966. 80072fc: 6013 str r3, [r2, #0]
  15967. }
  15968. 80072fe: 4770 bx lr
  15969. 8007300: 58024800 .word 0x58024800
  15970. 08007304 <HAL_PWREx_ConfigSupply>:
  15971. * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
  15972. * regulator.
  15973. * @retval HAL status.
  15974. */
  15975. HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
  15976. {
  15977. 8007304: b538 push {r3, r4, r5, lr}
  15978. /* Check the parameters */
  15979. assert_param (IS_PWR_SUPPLY (SupplySource));
  15980. /* Check if supply source was configured */
  15981. #if defined (PWR_FLAG_SCUEN)
  15982. if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
  15983. 8007306: 4c10 ldr r4, [pc, #64] @ (8007348 <HAL_PWREx_ConfigSupply+0x44>)
  15984. 8007308: 68e3 ldr r3, [r4, #12]
  15985. 800730a: f013 0f04 tst.w r3, #4
  15986. #else
  15987. if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
  15988. #endif /* defined (PWR_FLAG_SCUEN) */
  15989. {
  15990. /* Check supply configuration */
  15991. if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
  15992. 800730e: 68e3 ldr r3, [r4, #12]
  15993. if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
  15994. 8007310: d105 bne.n 800731e <HAL_PWREx_ConfigSupply+0x1a>
  15995. if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
  15996. 8007312: f003 0307 and.w r3, r3, #7
  15997. 8007316: 1a18 subs r0, r3, r0
  15998. 8007318: bf18 it ne
  15999. 800731a: 2001 movne r0, #1
  16000. }
  16001. }
  16002. #endif /* defined (SMPS) */
  16003. return HAL_OK;
  16004. }
  16005. 800731c: bd38 pop {r3, r4, r5, pc}
  16006. MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
  16007. 800731e: f023 0307 bic.w r3, r3, #7
  16008. 8007322: 4303 orrs r3, r0
  16009. 8007324: 60e3 str r3, [r4, #12]
  16010. tickstart = HAL_GetTick ();
  16011. 8007326: f7fc fe53 bl 8003fd0 <HAL_GetTick>
  16012. 800732a: 4605 mov r5, r0
  16013. while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
  16014. 800732c: e005 b.n 800733a <HAL_PWREx_ConfigSupply+0x36>
  16015. if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
  16016. 800732e: f7fc fe4f bl 8003fd0 <HAL_GetTick>
  16017. 8007332: 1b40 subs r0, r0, r5
  16018. 8007334: f5b0 7f7a cmp.w r0, #1000 @ 0x3e8
  16019. 8007338: d804 bhi.n 8007344 <HAL_PWREx_ConfigSupply+0x40>
  16020. while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
  16021. 800733a: 6863 ldr r3, [r4, #4]
  16022. 800733c: 049b lsls r3, r3, #18
  16023. 800733e: d5f6 bpl.n 800732e <HAL_PWREx_ConfigSupply+0x2a>
  16024. return HAL_OK;
  16025. 8007340: 2000 movs r0, #0
  16026. }
  16027. 8007342: bd38 pop {r3, r4, r5, pc}
  16028. return HAL_ERROR;
  16029. 8007344: 2001 movs r0, #1
  16030. }
  16031. 8007346: bd38 pop {r3, r4, r5, pc}
  16032. 8007348: 58024800 .word 0x58024800
  16033. 0800734c <HAL_PWREx_ConfigAVD>:
  16034. /* Check the parameters */
  16035. assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel));
  16036. assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode));
  16037. /* Set the ALS[18:17] bits according to AVDLevel value */
  16038. MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
  16039. 800734c: 4921 ldr r1, [pc, #132] @ (80073d4 <HAL_PWREx_ConfigAVD+0x88>)
  16040. /* Clear any previous config */
  16041. #if !defined (DUAL_CORE)
  16042. __HAL_PWR_AVD_EXTI_DISABLE_EVENT ();
  16043. 800734e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
  16044. MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
  16045. 8007352: 680a ldr r2, [r1, #0]
  16046. {
  16047. 8007354: b410 push {r4}
  16048. MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
  16049. 8007356: f422 22c0 bic.w r2, r2, #393216 @ 0x60000
  16050. 800735a: 6804 ldr r4, [r0, #0]
  16051. 800735c: 4322 orrs r2, r4
  16052. 800735e: 600a str r2, [r1, #0]
  16053. __HAL_PWR_AVD_EXTI_DISABLE_EVENT ();
  16054. 8007360: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84
  16055. 8007364: f422 3280 bic.w r2, r2, #65536 @ 0x10000
  16056. 8007368: f8c3 2084 str.w r2, [r3, #132] @ 0x84
  16057. __HAL_PWR_AVD_EXTI_DISABLE_IT ();
  16058. 800736c: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80
  16059. 8007370: f422 3280 bic.w r2, r2, #65536 @ 0x10000
  16060. 8007374: f8c3 2080 str.w r2, [r3, #128] @ 0x80
  16061. #endif /* !defined (DUAL_CORE) */
  16062. __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE ();
  16063. 8007378: 681a ldr r2, [r3, #0]
  16064. 800737a: f422 3280 bic.w r2, r2, #65536 @ 0x10000
  16065. 800737e: 601a str r2, [r3, #0]
  16066. __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE ();
  16067. 8007380: 685a ldr r2, [r3, #4]
  16068. 8007382: f422 3280 bic.w r2, r2, #65536 @ 0x10000
  16069. 8007386: 605a str r2, [r3, #4]
  16070. #if !defined (DUAL_CORE)
  16071. /* Configure the interrupt mode */
  16072. if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT)
  16073. 8007388: 6842 ldr r2, [r0, #4]
  16074. 800738a: 03d4 lsls r4, r2, #15
  16075. 800738c: d505 bpl.n 800739a <HAL_PWREx_ConfigAVD+0x4e>
  16076. {
  16077. __HAL_PWR_AVD_EXTI_ENABLE_IT ();
  16078. 800738e: f8d3 1080 ldr.w r1, [r3, #128] @ 0x80
  16079. 8007392: f441 3180 orr.w r1, r1, #65536 @ 0x10000
  16080. 8007396: f8c3 1080 str.w r1, [r3, #128] @ 0x80
  16081. }
  16082. /* Configure the event mode */
  16083. if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT)
  16084. 800739a: 0390 lsls r0, r2, #14
  16085. 800739c: d507 bpl.n 80073ae <HAL_PWREx_ConfigAVD+0x62>
  16086. {
  16087. __HAL_PWR_AVD_EXTI_ENABLE_EVENT ();
  16088. 800739e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
  16089. 80073a2: f8d1 3084 ldr.w r3, [r1, #132] @ 0x84
  16090. 80073a6: f443 3380 orr.w r3, r3, #65536 @ 0x10000
  16091. 80073aa: f8c1 3084 str.w r3, [r1, #132] @ 0x84
  16092. }
  16093. #endif /* !defined (DUAL_CORE) */
  16094. /* Rising edge configuration */
  16095. if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE)
  16096. 80073ae: 07d1 lsls r1, r2, #31
  16097. 80073b0: d505 bpl.n 80073be <HAL_PWREx_ConfigAVD+0x72>
  16098. {
  16099. __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE ();
  16100. 80073b2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
  16101. 80073b6: 680b ldr r3, [r1, #0]
  16102. 80073b8: f443 3380 orr.w r3, r3, #65536 @ 0x10000
  16103. 80073bc: 600b str r3, [r1, #0]
  16104. }
  16105. /* Falling edge configuration */
  16106. if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE)
  16107. 80073be: 0793 lsls r3, r2, #30
  16108. 80073c0: d505 bpl.n 80073ce <HAL_PWREx_ConfigAVD+0x82>
  16109. {
  16110. __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE ();
  16111. 80073c2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
  16112. 80073c6: 6853 ldr r3, [r2, #4]
  16113. 80073c8: f443 3380 orr.w r3, r3, #65536 @ 0x10000
  16114. 80073cc: 6053 str r3, [r2, #4]
  16115. }
  16116. }
  16117. 80073ce: f85d 4b04 ldr.w r4, [sp], #4
  16118. 80073d2: 4770 bx lr
  16119. 80073d4: 58024800 .word 0x58024800
  16120. 080073d8 <HAL_PWREx_EnableAVD>:
  16121. * @retval None.
  16122. */
  16123. void HAL_PWREx_EnableAVD (void)
  16124. {
  16125. /* Enable the Analog Voltage Detector */
  16126. SET_BIT (PWR->CR1, PWR_CR1_AVDEN);
  16127. 80073d8: 4a02 ldr r2, [pc, #8] @ (80073e4 <HAL_PWREx_EnableAVD+0xc>)
  16128. 80073da: 6813 ldr r3, [r2, #0]
  16129. 80073dc: f443 3380 orr.w r3, r3, #65536 @ 0x10000
  16130. 80073e0: 6013 str r3, [r2, #0]
  16131. }
  16132. 80073e2: 4770 bx lr
  16133. 80073e4: 58024800 .word 0x58024800
  16134. 080073e8 <HAL_RCC_GetSysClockFreq.part.0>:
  16135. case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
  16136. /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
  16137. SYSCLK = PLL_VCO / PLLR
  16138. */
  16139. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  16140. 80073e8: 4b33 ldr r3, [pc, #204] @ (80074b8 <HAL_RCC_GetSysClockFreq.part.0+0xd0>)
  16141. uint32_t HAL_RCC_GetSysClockFreq(void)
  16142. 80073ea: b430 push {r4, r5}
  16143. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  16144. 80073ec: 6a9a ldr r2, [r3, #40] @ 0x28
  16145. pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ;
  16146. 80073ee: 6a9c ldr r4, [r3, #40] @ 0x28
  16147. pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
  16148. 80073f0: 6add ldr r5, [r3, #44] @ 0x2c
  16149. fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
  16150. if (pllm != 0U)
  16151. 80073f2: f414 7f7c tst.w r4, #1008 @ 0x3f0
  16152. fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
  16153. 80073f6: 6b59 ldr r1, [r3, #52] @ 0x34
  16154. pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ;
  16155. 80073f8: f3c4 1005 ubfx r0, r4, #4, #6
  16156. if (pllm != 0U)
  16157. 80073fc: d036 beq.n 800746c <HAL_RCC_GetSysClockFreq.part.0+0x84>
  16158. fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
  16159. 80073fe: f3c1 01cc ubfx r1, r1, #3, #13
  16160. pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
  16161. 8007402: f005 0501 and.w r5, r5, #1
  16162. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  16163. 8007406: f002 0203 and.w r2, r2, #3
  16164. case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
  16165. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  16166. {
  16167. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  16168. pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  16169. 800740a: ee07 0a90 vmov s15, r0
  16170. fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
  16171. 800740e: fb05 f101 mul.w r1, r5, r1
  16172. 8007412: 2a01 cmp r2, #1
  16173. pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  16174. 8007414: eeb8 7ae7 vcvt.f32.s32 s14, s15
  16175. 8007418: ee06 1a90 vmov s13, r1
  16176. 800741c: eefa 6ae9 vcvt.f32.s32 s13, s13, #13
  16177. 8007420: d002 beq.n 8007428 <HAL_RCC_GetSysClockFreq.part.0+0x40>
  16178. 8007422: 2a02 cmp r2, #2
  16179. 8007424: d042 beq.n 80074ac <HAL_RCC_GetSysClockFreq.part.0+0xc4>
  16180. 8007426: b31a cbz r2, 8007470 <HAL_RCC_GetSysClockFreq.part.0+0x88>
  16181. case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
  16182. pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  16183. break;
  16184. default:
  16185. pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  16186. 8007428: eddf 7a24 vldr s15, [pc, #144] @ 80074bc <HAL_RCC_GetSysClockFreq.part.0+0xd4>
  16187. 800742c: ee87 6a87 vdiv.f32 s12, s15, s14
  16188. 8007430: 6b1b ldr r3, [r3, #48] @ 0x30
  16189. 8007432: f3c3 0308 ubfx r3, r3, #0, #9
  16190. 8007436: ee07 3a90 vmov s15, r3
  16191. 800743a: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
  16192. 800743e: eef8 7ae7 vcvt.f32.s32 s15, s15
  16193. 8007442: ee77 7aa5 vadd.f32 s15, s15, s11
  16194. 8007446: ee77 7aa6 vadd.f32 s15, s15, s13
  16195. 800744a: ee67 7a86 vmul.f32 s15, s15, s12
  16196. break;
  16197. }
  16198. pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
  16199. 800744e: 4b1a ldr r3, [pc, #104] @ (80074b8 <HAL_RCC_GetSysClockFreq.part.0+0xd0>)
  16200. 8007450: 6b1b ldr r3, [r3, #48] @ 0x30
  16201. 8007452: f3c3 2346 ubfx r3, r3, #9, #7
  16202. 8007456: 3301 adds r3, #1
  16203. sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
  16204. 8007458: ee07 3a10 vmov s14, r3
  16205. 800745c: eef8 6ac7 vcvt.f32.s32 s13, s14
  16206. 8007460: ee87 7aa6 vdiv.f32 s14, s15, s13
  16207. 8007464: eefc 7ac7 vcvt.u32.f32 s15, s14
  16208. 8007468: ee17 0a90 vmov r0, s15
  16209. sysclockfreq = CSI_VALUE;
  16210. break;
  16211. }
  16212. return sysclockfreq;
  16213. }
  16214. 800746c: bc30 pop {r4, r5}
  16215. 800746e: 4770 bx lr
  16216. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  16217. 8007470: 681a ldr r2, [r3, #0]
  16218. 8007472: 0692 lsls r2, r2, #26
  16219. 8007474: d51d bpl.n 80074b2 <HAL_RCC_GetSysClockFreq.part.0+0xca>
  16220. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  16221. 8007476: 6819 ldr r1, [r3, #0]
  16222. pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  16223. 8007478: eef7 7a00 vmov.f32 s15, #112 @ 0x3f800000 1.0
  16224. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  16225. 800747c: 4a10 ldr r2, [pc, #64] @ (80074c0 <HAL_RCC_GetSysClockFreq.part.0+0xd8>)
  16226. pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  16227. 800747e: 6b1b ldr r3, [r3, #48] @ 0x30
  16228. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  16229. 8007480: f3c1 01c1 ubfx r1, r1, #3, #2
  16230. pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  16231. 8007484: f3c3 0308 ubfx r3, r3, #0, #9
  16232. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  16233. 8007488: 40ca lsrs r2, r1
  16234. pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  16235. 800748a: ee06 3a10 vmov s12, r3
  16236. 800748e: ee05 2a90 vmov s11, r2
  16237. 8007492: eeb8 6ac6 vcvt.f32.s32 s12, s12
  16238. 8007496: eef8 5ae5 vcvt.f32.s32 s11, s11
  16239. 800749a: ee36 6a27 vadd.f32 s12, s12, s15
  16240. 800749e: eec5 7a87 vdiv.f32 s15, s11, s14
  16241. 80074a2: ee36 7a26 vadd.f32 s14, s12, s13
  16242. 80074a6: ee67 7a87 vmul.f32 s15, s15, s14
  16243. 80074aa: e7d0 b.n 800744e <HAL_RCC_GetSysClockFreq.part.0+0x66>
  16244. pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  16245. 80074ac: eddf 7a05 vldr s15, [pc, #20] @ 80074c4 <HAL_RCC_GetSysClockFreq.part.0+0xdc>
  16246. 80074b0: e7bc b.n 800742c <HAL_RCC_GetSysClockFreq.part.0+0x44>
  16247. pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  16248. 80074b2: eddf 7a05 vldr s15, [pc, #20] @ 80074c8 <HAL_RCC_GetSysClockFreq.part.0+0xe0>
  16249. 80074b6: e7b9 b.n 800742c <HAL_RCC_GetSysClockFreq.part.0+0x44>
  16250. 80074b8: 58024400 .word 0x58024400
  16251. 80074bc: 4a742400 .word 0x4a742400
  16252. 80074c0: 03d09000 .word 0x03d09000
  16253. 80074c4: 4bbebc20 .word 0x4bbebc20
  16254. 80074c8: 4c742400 .word 0x4c742400
  16255. 080074cc <HAL_RCC_OscConfig>:
  16256. if (RCC_OscInitStruct == NULL)
  16257. 80074cc: 2800 cmp r0, #0
  16258. 80074ce: f000 82e9 beq.w 8007aa4 <HAL_RCC_OscConfig+0x5d8>
  16259. {
  16260. 80074d2: b5f8 push {r3, r4, r5, r6, r7, lr}
  16261. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
  16262. 80074d4: 6803 ldr r3, [r0, #0]
  16263. 80074d6: 4604 mov r4, r0
  16264. 80074d8: 07d9 lsls r1, r3, #31
  16265. 80074da: d52e bpl.n 800753a <HAL_RCC_OscConfig+0x6e>
  16266. const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
  16267. 80074dc: 4997 ldr r1, [pc, #604] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16268. 80074de: 690a ldr r2, [r1, #16]
  16269. const uint32_t temp_pllckselr = RCC->PLLCKSELR;
  16270. 80074e0: 6a89 ldr r1, [r1, #40] @ 0x28
  16271. const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
  16272. 80074e2: f002 0238 and.w r2, r2, #56 @ 0x38
  16273. if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
  16274. 80074e6: 2a10 cmp r2, #16
  16275. 80074e8: f000 80ee beq.w 80076c8 <HAL_RCC_OscConfig+0x1fc>
  16276. 80074ec: 2a18 cmp r2, #24
  16277. 80074ee: f000 80e6 beq.w 80076be <HAL_RCC_OscConfig+0x1f2>
  16278. __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
  16279. 80074f2: 6863 ldr r3, [r4, #4]
  16280. 80074f4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
  16281. 80074f8: f000 8111 beq.w 800771e <HAL_RCC_OscConfig+0x252>
  16282. 80074fc: 2b00 cmp r3, #0
  16283. 80074fe: f000 8167 beq.w 80077d0 <HAL_RCC_OscConfig+0x304>
  16284. 8007502: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
  16285. 8007506: 4b8d ldr r3, [pc, #564] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16286. 8007508: 681a ldr r2, [r3, #0]
  16287. 800750a: f000 828a beq.w 8007a22 <HAL_RCC_OscConfig+0x556>
  16288. 800750e: f422 3280 bic.w r2, r2, #65536 @ 0x10000
  16289. 8007512: 601a str r2, [r3, #0]
  16290. 8007514: 681a ldr r2, [r3, #0]
  16291. 8007516: f422 2280 bic.w r2, r2, #262144 @ 0x40000
  16292. 800751a: 601a str r2, [r3, #0]
  16293. tickstart = HAL_GetTick();
  16294. 800751c: f7fc fd58 bl 8003fd0 <HAL_GetTick>
  16295. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
  16296. 8007520: 4e86 ldr r6, [pc, #536] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16297. tickstart = HAL_GetTick();
  16298. 8007522: 4605 mov r5, r0
  16299. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
  16300. 8007524: e005 b.n 8007532 <HAL_RCC_OscConfig+0x66>
  16301. if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
  16302. 8007526: f7fc fd53 bl 8003fd0 <HAL_GetTick>
  16303. 800752a: 1b40 subs r0, r0, r5
  16304. 800752c: 2864 cmp r0, #100 @ 0x64
  16305. 800752e: f200 814d bhi.w 80077cc <HAL_RCC_OscConfig+0x300>
  16306. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
  16307. 8007532: 6833 ldr r3, [r6, #0]
  16308. 8007534: 039b lsls r3, r3, #14
  16309. 8007536: d5f6 bpl.n 8007526 <HAL_RCC_OscConfig+0x5a>
  16310. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
  16311. 8007538: 6823 ldr r3, [r4, #0]
  16312. 800753a: 079d lsls r5, r3, #30
  16313. 800753c: d470 bmi.n 8007620 <HAL_RCC_OscConfig+0x154>
  16314. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
  16315. 800753e: 06d9 lsls r1, r3, #27
  16316. 8007540: d533 bpl.n 80075aa <HAL_RCC_OscConfig+0xde>
  16317. const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
  16318. 8007542: 4a7e ldr r2, [pc, #504] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16319. 8007544: 6913 ldr r3, [r2, #16]
  16320. const uint32_t temp_pllckselr = RCC->PLLCKSELR;
  16321. 8007546: 6a92 ldr r2, [r2, #40] @ 0x28
  16322. const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
  16323. 8007548: f003 0338 and.w r3, r3, #56 @ 0x38
  16324. if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
  16325. 800754c: 2b08 cmp r3, #8
  16326. 800754e: f000 80cb beq.w 80076e8 <HAL_RCC_OscConfig+0x21c>
  16327. 8007552: 2b18 cmp r3, #24
  16328. 8007554: f000 80c3 beq.w 80076de <HAL_RCC_OscConfig+0x212>
  16329. if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
  16330. 8007558: 69e3 ldr r3, [r4, #28]
  16331. __HAL_RCC_CSI_ENABLE();
  16332. 800755a: 4d78 ldr r5, [pc, #480] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16333. if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
  16334. 800755c: 2b00 cmp r3, #0
  16335. 800755e: f000 816f beq.w 8007840 <HAL_RCC_OscConfig+0x374>
  16336. __HAL_RCC_CSI_ENABLE();
  16337. 8007562: 682b ldr r3, [r5, #0]
  16338. 8007564: f043 0380 orr.w r3, r3, #128 @ 0x80
  16339. 8007568: 602b str r3, [r5, #0]
  16340. tickstart = HAL_GetTick();
  16341. 800756a: f7fc fd31 bl 8003fd0 <HAL_GetTick>
  16342. 800756e: 4606 mov r6, r0
  16343. while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
  16344. 8007570: e005 b.n 800757e <HAL_RCC_OscConfig+0xb2>
  16345. if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
  16346. 8007572: f7fc fd2d bl 8003fd0 <HAL_GetTick>
  16347. 8007576: 1b80 subs r0, r0, r6
  16348. 8007578: 2802 cmp r0, #2
  16349. 800757a: f200 8127 bhi.w 80077cc <HAL_RCC_OscConfig+0x300>
  16350. while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
  16351. 800757e: 682b ldr r3, [r5, #0]
  16352. 8007580: 05db lsls r3, r3, #23
  16353. 8007582: d5f6 bpl.n 8007572 <HAL_RCC_OscConfig+0xa6>
  16354. __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
  16355. 8007584: f7fc fd2a bl 8003fdc <HAL_GetREVID>
  16356. 8007588: f241 0303 movw r3, #4099 @ 0x1003
  16357. 800758c: 4298 cmp r0, r3
  16358. 800758e: f200 8269 bhi.w 8007a64 <HAL_RCC_OscConfig+0x598>
  16359. 8007592: 6a22 ldr r2, [r4, #32]
  16360. 8007594: 686b ldr r3, [r5, #4]
  16361. 8007596: 2a20 cmp r2, #32
  16362. 8007598: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000
  16363. 800759c: bf0c ite eq
  16364. 800759e: f043 4380 orreq.w r3, r3, #1073741824 @ 0x40000000
  16365. 80075a2: ea43 6382 orrne.w r3, r3, r2, lsl #26
  16366. 80075a6: 606b str r3, [r5, #4]
  16367. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
  16368. 80075a8: 6823 ldr r3, [r4, #0]
  16369. 80075aa: 071d lsls r5, r3, #28
  16370. 80075ac: d516 bpl.n 80075dc <HAL_RCC_OscConfig+0x110>
  16371. if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
  16372. 80075ae: 6963 ldr r3, [r4, #20]
  16373. __HAL_RCC_LSI_ENABLE();
  16374. 80075b0: 4d62 ldr r5, [pc, #392] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16375. if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
  16376. 80075b2: 2b00 cmp r3, #0
  16377. 80075b4: f000 8122 beq.w 80077fc <HAL_RCC_OscConfig+0x330>
  16378. __HAL_RCC_LSI_ENABLE();
  16379. 80075b8: 6f6b ldr r3, [r5, #116] @ 0x74
  16380. 80075ba: f043 0301 orr.w r3, r3, #1
  16381. 80075be: 676b str r3, [r5, #116] @ 0x74
  16382. tickstart = HAL_GetTick();
  16383. 80075c0: f7fc fd06 bl 8003fd0 <HAL_GetTick>
  16384. 80075c4: 4606 mov r6, r0
  16385. while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
  16386. 80075c6: e005 b.n 80075d4 <HAL_RCC_OscConfig+0x108>
  16387. if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
  16388. 80075c8: f7fc fd02 bl 8003fd0 <HAL_GetTick>
  16389. 80075cc: 1b80 subs r0, r0, r6
  16390. 80075ce: 2802 cmp r0, #2
  16391. 80075d0: f200 80fc bhi.w 80077cc <HAL_RCC_OscConfig+0x300>
  16392. while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
  16393. 80075d4: 6f6b ldr r3, [r5, #116] @ 0x74
  16394. 80075d6: 0798 lsls r0, r3, #30
  16395. 80075d8: d5f6 bpl.n 80075c8 <HAL_RCC_OscConfig+0xfc>
  16396. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
  16397. 80075da: 6823 ldr r3, [r4, #0]
  16398. 80075dc: 069a lsls r2, r3, #26
  16399. 80075de: d516 bpl.n 800760e <HAL_RCC_OscConfig+0x142>
  16400. if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
  16401. 80075e0: 69a3 ldr r3, [r4, #24]
  16402. __HAL_RCC_HSI48_ENABLE();
  16403. 80075e2: 4d56 ldr r5, [pc, #344] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16404. if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
  16405. 80075e4: 2b00 cmp r3, #0
  16406. 80075e6: f000 811a beq.w 800781e <HAL_RCC_OscConfig+0x352>
  16407. __HAL_RCC_HSI48_ENABLE();
  16408. 80075ea: 682b ldr r3, [r5, #0]
  16409. 80075ec: f443 5380 orr.w r3, r3, #4096 @ 0x1000
  16410. 80075f0: 602b str r3, [r5, #0]
  16411. tickstart = HAL_GetTick();
  16412. 80075f2: f7fc fced bl 8003fd0 <HAL_GetTick>
  16413. 80075f6: 4606 mov r6, r0
  16414. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
  16415. 80075f8: e005 b.n 8007606 <HAL_RCC_OscConfig+0x13a>
  16416. if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
  16417. 80075fa: f7fc fce9 bl 8003fd0 <HAL_GetTick>
  16418. 80075fe: 1b80 subs r0, r0, r6
  16419. 8007600: 2802 cmp r0, #2
  16420. 8007602: f200 80e3 bhi.w 80077cc <HAL_RCC_OscConfig+0x300>
  16421. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
  16422. 8007606: 682b ldr r3, [r5, #0]
  16423. 8007608: 049f lsls r7, r3, #18
  16424. 800760a: d5f6 bpl.n 80075fa <HAL_RCC_OscConfig+0x12e>
  16425. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
  16426. 800760c: 6823 ldr r3, [r4, #0]
  16427. 800760e: 0759 lsls r1, r3, #29
  16428. 8007610: f100 808b bmi.w 800772a <HAL_RCC_OscConfig+0x25e>
  16429. if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
  16430. 8007614: 6a63 ldr r3, [r4, #36] @ 0x24
  16431. 8007616: 2b00 cmp r3, #0
  16432. 8007618: f040 80bf bne.w 800779a <HAL_RCC_OscConfig+0x2ce>
  16433. return HAL_OK;
  16434. 800761c: 2000 movs r0, #0
  16435. }
  16436. 800761e: bdf8 pop {r3, r4, r5, r6, r7, pc}
  16437. const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
  16438. 8007620: 4a46 ldr r2, [pc, #280] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16439. 8007622: 6913 ldr r3, [r2, #16]
  16440. const uint32_t temp_pllckselr = RCC->PLLCKSELR;
  16441. 8007624: 6a92 ldr r2, [r2, #40] @ 0x28
  16442. if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
  16443. 8007626: f013 0338 ands.w r3, r3, #56 @ 0x38
  16444. 800762a: d12d bne.n 8007688 <HAL_RCC_OscConfig+0x1bc>
  16445. if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
  16446. 800762c: 4b43 ldr r3, [pc, #268] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16447. if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
  16448. 800762e: 68e2 ldr r2, [r4, #12]
  16449. if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
  16450. 8007630: 681b ldr r3, [r3, #0]
  16451. 8007632: 0759 lsls r1, r3, #29
  16452. 8007634: d501 bpl.n 800763a <HAL_RCC_OscConfig+0x16e>
  16453. 8007636: 2a00 cmp r2, #0
  16454. 8007638: d04f beq.n 80076da <HAL_RCC_OscConfig+0x20e>
  16455. __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
  16456. 800763a: 4d40 ldr r5, [pc, #256] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16457. 800763c: 682b ldr r3, [r5, #0]
  16458. 800763e: f023 0319 bic.w r3, r3, #25
  16459. 8007642: 4313 orrs r3, r2
  16460. 8007644: 602b str r3, [r5, #0]
  16461. tickstart = HAL_GetTick();
  16462. 8007646: f7fc fcc3 bl 8003fd0 <HAL_GetTick>
  16463. 800764a: 4606 mov r6, r0
  16464. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  16465. 800764c: e005 b.n 800765a <HAL_RCC_OscConfig+0x18e>
  16466. if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
  16467. 800764e: f7fc fcbf bl 8003fd0 <HAL_GetTick>
  16468. 8007652: 1b80 subs r0, r0, r6
  16469. 8007654: 2802 cmp r0, #2
  16470. 8007656: f200 80b9 bhi.w 80077cc <HAL_RCC_OscConfig+0x300>
  16471. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  16472. 800765a: 682b ldr r3, [r5, #0]
  16473. 800765c: 075b lsls r3, r3, #29
  16474. 800765e: d5f6 bpl.n 800764e <HAL_RCC_OscConfig+0x182>
  16475. __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  16476. 8007660: f7fc fcbc bl 8003fdc <HAL_GetREVID>
  16477. 8007664: f241 0303 movw r3, #4099 @ 0x1003
  16478. 8007668: 4298 cmp r0, r3
  16479. 800766a: f200 8110 bhi.w 800788e <HAL_RCC_OscConfig+0x3c2>
  16480. 800766e: 6922 ldr r2, [r4, #16]
  16481. 8007670: 686b ldr r3, [r5, #4]
  16482. 8007672: 2a40 cmp r2, #64 @ 0x40
  16483. 8007674: f423 337c bic.w r3, r3, #258048 @ 0x3f000
  16484. 8007678: bf0c ite eq
  16485. 800767a: f443 3300 orreq.w r3, r3, #131072 @ 0x20000
  16486. 800767e: ea43 3302 orrne.w r3, r3, r2, lsl #12
  16487. 8007682: 606b str r3, [r5, #4]
  16488. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
  16489. 8007684: 6823 ldr r3, [r4, #0]
  16490. 8007686: e75a b.n 800753e <HAL_RCC_OscConfig+0x72>
  16491. if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
  16492. 8007688: 2b18 cmp r3, #24
  16493. 800768a: f000 80fc beq.w 8007886 <HAL_RCC_OscConfig+0x3ba>
  16494. __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
  16495. 800768e: 4d2b ldr r5, [pc, #172] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16496. if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
  16497. 8007690: 68e2 ldr r2, [r4, #12]
  16498. __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
  16499. 8007692: 682b ldr r3, [r5, #0]
  16500. if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
  16501. 8007694: 2a00 cmp r2, #0
  16502. 8007696: f000 80e5 beq.w 8007864 <HAL_RCC_OscConfig+0x398>
  16503. __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
  16504. 800769a: f023 0319 bic.w r3, r3, #25
  16505. 800769e: 4313 orrs r3, r2
  16506. 80076a0: 602b str r3, [r5, #0]
  16507. tickstart = HAL_GetTick();
  16508. 80076a2: f7fc fc95 bl 8003fd0 <HAL_GetTick>
  16509. 80076a6: 4606 mov r6, r0
  16510. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  16511. 80076a8: e005 b.n 80076b6 <HAL_RCC_OscConfig+0x1ea>
  16512. if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
  16513. 80076aa: f7fc fc91 bl 8003fd0 <HAL_GetTick>
  16514. 80076ae: 1b80 subs r0, r0, r6
  16515. 80076b0: 2802 cmp r0, #2
  16516. 80076b2: f200 808b bhi.w 80077cc <HAL_RCC_OscConfig+0x300>
  16517. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  16518. 80076b6: 682b ldr r3, [r5, #0]
  16519. 80076b8: 075f lsls r7, r3, #29
  16520. 80076ba: d5f6 bpl.n 80076aa <HAL_RCC_OscConfig+0x1de>
  16521. 80076bc: e7d0 b.n 8007660 <HAL_RCC_OscConfig+0x194>
  16522. if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
  16523. 80076be: f001 0103 and.w r1, r1, #3
  16524. 80076c2: 2902 cmp r1, #2
  16525. 80076c4: f47f af15 bne.w 80074f2 <HAL_RCC_OscConfig+0x26>
  16526. if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
  16527. 80076c8: 4a1c ldr r2, [pc, #112] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16528. 80076ca: 6812 ldr r2, [r2, #0]
  16529. 80076cc: 0392 lsls r2, r2, #14
  16530. 80076ce: f57f af34 bpl.w 800753a <HAL_RCC_OscConfig+0x6e>
  16531. 80076d2: 6862 ldr r2, [r4, #4]
  16532. 80076d4: 2a00 cmp r2, #0
  16533. 80076d6: f47f af30 bne.w 800753a <HAL_RCC_OscConfig+0x6e>
  16534. return HAL_ERROR;
  16535. 80076da: 2001 movs r0, #1
  16536. }
  16537. 80076dc: bdf8 pop {r3, r4, r5, r6, r7, pc}
  16538. if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
  16539. 80076de: f002 0203 and.w r2, r2, #3
  16540. 80076e2: 2a01 cmp r2, #1
  16541. 80076e4: f47f af38 bne.w 8007558 <HAL_RCC_OscConfig+0x8c>
  16542. if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
  16543. 80076e8: 4b14 ldr r3, [pc, #80] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16544. 80076ea: 681b ldr r3, [r3, #0]
  16545. 80076ec: 05da lsls r2, r3, #23
  16546. 80076ee: d502 bpl.n 80076f6 <HAL_RCC_OscConfig+0x22a>
  16547. 80076f0: 69e3 ldr r3, [r4, #28]
  16548. 80076f2: 2b80 cmp r3, #128 @ 0x80
  16549. 80076f4: d1f1 bne.n 80076da <HAL_RCC_OscConfig+0x20e>
  16550. __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
  16551. 80076f6: f7fc fc71 bl 8003fdc <HAL_GetREVID>
  16552. 80076fa: f241 0303 movw r3, #4099 @ 0x1003
  16553. 80076fe: 4298 cmp r0, r3
  16554. 8007700: f200 80ce bhi.w 80078a0 <HAL_RCC_OscConfig+0x3d4>
  16555. 8007704: 6a22 ldr r2, [r4, #32]
  16556. 8007706: 2a20 cmp r2, #32
  16557. 8007708: f000 81bb beq.w 8007a82 <HAL_RCC_OscConfig+0x5b6>
  16558. 800770c: 490b ldr r1, [pc, #44] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16559. 800770e: 684b ldr r3, [r1, #4]
  16560. 8007710: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000
  16561. 8007714: ea43 6382 orr.w r3, r3, r2, lsl #26
  16562. 8007718: 604b str r3, [r1, #4]
  16563. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
  16564. 800771a: 6823 ldr r3, [r4, #0]
  16565. 800771c: e745 b.n 80075aa <HAL_RCC_OscConfig+0xde>
  16566. __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
  16567. 800771e: 4a07 ldr r2, [pc, #28] @ (800773c <HAL_RCC_OscConfig+0x270>)
  16568. 8007720: 6813 ldr r3, [r2, #0]
  16569. 8007722: f443 3380 orr.w r3, r3, #65536 @ 0x10000
  16570. 8007726: 6013 str r3, [r2, #0]
  16571. if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
  16572. 8007728: e6f8 b.n 800751c <HAL_RCC_OscConfig+0x50>
  16573. PWR->CR1 |= PWR_CR1_DBP;
  16574. 800772a: 4d05 ldr r5, [pc, #20] @ (8007740 <HAL_RCC_OscConfig+0x274>)
  16575. 800772c: 682b ldr r3, [r5, #0]
  16576. 800772e: f443 7380 orr.w r3, r3, #256 @ 0x100
  16577. 8007732: 602b str r3, [r5, #0]
  16578. tickstart = HAL_GetTick();
  16579. 8007734: f7fc fc4c bl 8003fd0 <HAL_GetTick>
  16580. 8007738: 4606 mov r6, r0
  16581. while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
  16582. 800773a: e008 b.n 800774e <HAL_RCC_OscConfig+0x282>
  16583. 800773c: 58024400 .word 0x58024400
  16584. 8007740: 58024800 .word 0x58024800
  16585. if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
  16586. 8007744: f7fc fc44 bl 8003fd0 <HAL_GetTick>
  16587. 8007748: 1b80 subs r0, r0, r6
  16588. 800774a: 2864 cmp r0, #100 @ 0x64
  16589. 800774c: d83e bhi.n 80077cc <HAL_RCC_OscConfig+0x300>
  16590. while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
  16591. 800774e: 682b ldr r3, [r5, #0]
  16592. 8007750: 05da lsls r2, r3, #23
  16593. 8007752: d5f7 bpl.n 8007744 <HAL_RCC_OscConfig+0x278>
  16594. __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  16595. 8007754: 68a3 ldr r3, [r4, #8]
  16596. 8007756: 2b01 cmp r3, #1
  16597. 8007758: f000 818d beq.w 8007a76 <HAL_RCC_OscConfig+0x5aa>
  16598. 800775c: 2b00 cmp r3, #0
  16599. 800775e: f000 8168 beq.w 8007a32 <HAL_RCC_OscConfig+0x566>
  16600. 8007762: 2b05 cmp r3, #5
  16601. 8007764: 4b85 ldr r3, [pc, #532] @ (800797c <HAL_RCC_OscConfig+0x4b0>)
  16602. 8007766: 6f1a ldr r2, [r3, #112] @ 0x70
  16603. 8007768: f000 8194 beq.w 8007a94 <HAL_RCC_OscConfig+0x5c8>
  16604. 800776c: f022 0201 bic.w r2, r2, #1
  16605. 8007770: 671a str r2, [r3, #112] @ 0x70
  16606. 8007772: 6f1a ldr r2, [r3, #112] @ 0x70
  16607. 8007774: f022 0204 bic.w r2, r2, #4
  16608. 8007778: 671a str r2, [r3, #112] @ 0x70
  16609. tickstart = HAL_GetTick();
  16610. 800777a: f7fc fc29 bl 8003fd0 <HAL_GetTick>
  16611. while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
  16612. 800777e: 4e7f ldr r6, [pc, #508] @ (800797c <HAL_RCC_OscConfig+0x4b0>)
  16613. if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
  16614. 8007780: f241 3788 movw r7, #5000 @ 0x1388
  16615. tickstart = HAL_GetTick();
  16616. 8007784: 4605 mov r5, r0
  16617. while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
  16618. 8007786: e004 b.n 8007792 <HAL_RCC_OscConfig+0x2c6>
  16619. if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
  16620. 8007788: f7fc fc22 bl 8003fd0 <HAL_GetTick>
  16621. 800778c: 1b40 subs r0, r0, r5
  16622. 800778e: 42b8 cmp r0, r7
  16623. 8007790: d81c bhi.n 80077cc <HAL_RCC_OscConfig+0x300>
  16624. while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
  16625. 8007792: 6f33 ldr r3, [r6, #112] @ 0x70
  16626. 8007794: 079b lsls r3, r3, #30
  16627. 8007796: d5f7 bpl.n 8007788 <HAL_RCC_OscConfig+0x2bc>
  16628. 8007798: e73c b.n 8007614 <HAL_RCC_OscConfig+0x148>
  16629. if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
  16630. 800779a: 4d78 ldr r5, [pc, #480] @ (800797c <HAL_RCC_OscConfig+0x4b0>)
  16631. 800779c: 692a ldr r2, [r5, #16]
  16632. 800779e: f002 0238 and.w r2, r2, #56 @ 0x38
  16633. 80077a2: 2a18 cmp r2, #24
  16634. 80077a4: f000 80f0 beq.w 8007988 <HAL_RCC_OscConfig+0x4bc>
  16635. if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
  16636. 80077a8: 2b02 cmp r3, #2
  16637. __HAL_RCC_PLL_DISABLE();
  16638. 80077aa: 682b ldr r3, [r5, #0]
  16639. 80077ac: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
  16640. 80077b0: 602b str r3, [r5, #0]
  16641. if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
  16642. 80077b2: d07f beq.n 80078b4 <HAL_RCC_OscConfig+0x3e8>
  16643. tickstart = HAL_GetTick();
  16644. 80077b4: f7fc fc0c bl 8003fd0 <HAL_GetTick>
  16645. 80077b8: 4604 mov r4, r0
  16646. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
  16647. 80077ba: 682b ldr r3, [r5, #0]
  16648. 80077bc: 019b lsls r3, r3, #6
  16649. 80077be: f57f af2d bpl.w 800761c <HAL_RCC_OscConfig+0x150>
  16650. if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
  16651. 80077c2: f7fc fc05 bl 8003fd0 <HAL_GetTick>
  16652. 80077c6: 1b00 subs r0, r0, r4
  16653. 80077c8: 2802 cmp r0, #2
  16654. 80077ca: d9f6 bls.n 80077ba <HAL_RCC_OscConfig+0x2ee>
  16655. return HAL_TIMEOUT;
  16656. 80077cc: 2003 movs r0, #3
  16657. }
  16658. 80077ce: bdf8 pop {r3, r4, r5, r6, r7, pc}
  16659. __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
  16660. 80077d0: 4d6a ldr r5, [pc, #424] @ (800797c <HAL_RCC_OscConfig+0x4b0>)
  16661. 80077d2: 682b ldr r3, [r5, #0]
  16662. 80077d4: f423 3380 bic.w r3, r3, #65536 @ 0x10000
  16663. 80077d8: 602b str r3, [r5, #0]
  16664. 80077da: 682b ldr r3, [r5, #0]
  16665. 80077dc: f423 2380 bic.w r3, r3, #262144 @ 0x40000
  16666. 80077e0: 602b str r3, [r5, #0]
  16667. tickstart = HAL_GetTick();
  16668. 80077e2: f7fc fbf5 bl 8003fd0 <HAL_GetTick>
  16669. 80077e6: 4606 mov r6, r0
  16670. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
  16671. 80077e8: e004 b.n 80077f4 <HAL_RCC_OscConfig+0x328>
  16672. if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
  16673. 80077ea: f7fc fbf1 bl 8003fd0 <HAL_GetTick>
  16674. 80077ee: 1b80 subs r0, r0, r6
  16675. 80077f0: 2864 cmp r0, #100 @ 0x64
  16676. 80077f2: d8eb bhi.n 80077cc <HAL_RCC_OscConfig+0x300>
  16677. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
  16678. 80077f4: 682b ldr r3, [r5, #0]
  16679. 80077f6: 039f lsls r7, r3, #14
  16680. 80077f8: d4f7 bmi.n 80077ea <HAL_RCC_OscConfig+0x31e>
  16681. 80077fa: e69d b.n 8007538 <HAL_RCC_OscConfig+0x6c>
  16682. __HAL_RCC_LSI_DISABLE();
  16683. 80077fc: 6f6b ldr r3, [r5, #116] @ 0x74
  16684. 80077fe: f023 0301 bic.w r3, r3, #1
  16685. 8007802: 676b str r3, [r5, #116] @ 0x74
  16686. tickstart = HAL_GetTick();
  16687. 8007804: f7fc fbe4 bl 8003fd0 <HAL_GetTick>
  16688. 8007808: 4606 mov r6, r0
  16689. while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
  16690. 800780a: e004 b.n 8007816 <HAL_RCC_OscConfig+0x34a>
  16691. if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
  16692. 800780c: f7fc fbe0 bl 8003fd0 <HAL_GetTick>
  16693. 8007810: 1b80 subs r0, r0, r6
  16694. 8007812: 2802 cmp r0, #2
  16695. 8007814: d8da bhi.n 80077cc <HAL_RCC_OscConfig+0x300>
  16696. while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
  16697. 8007816: 6f6b ldr r3, [r5, #116] @ 0x74
  16698. 8007818: 0799 lsls r1, r3, #30
  16699. 800781a: d4f7 bmi.n 800780c <HAL_RCC_OscConfig+0x340>
  16700. 800781c: e6dd b.n 80075da <HAL_RCC_OscConfig+0x10e>
  16701. __HAL_RCC_HSI48_DISABLE();
  16702. 800781e: 682b ldr r3, [r5, #0]
  16703. 8007820: f423 5380 bic.w r3, r3, #4096 @ 0x1000
  16704. 8007824: 602b str r3, [r5, #0]
  16705. tickstart = HAL_GetTick();
  16706. 8007826: f7fc fbd3 bl 8003fd0 <HAL_GetTick>
  16707. 800782a: 4606 mov r6, r0
  16708. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
  16709. 800782c: e004 b.n 8007838 <HAL_RCC_OscConfig+0x36c>
  16710. if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
  16711. 800782e: f7fc fbcf bl 8003fd0 <HAL_GetTick>
  16712. 8007832: 1b80 subs r0, r0, r6
  16713. 8007834: 2802 cmp r0, #2
  16714. 8007836: d8c9 bhi.n 80077cc <HAL_RCC_OscConfig+0x300>
  16715. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
  16716. 8007838: 682b ldr r3, [r5, #0]
  16717. 800783a: 0498 lsls r0, r3, #18
  16718. 800783c: d4f7 bmi.n 800782e <HAL_RCC_OscConfig+0x362>
  16719. 800783e: e6e5 b.n 800760c <HAL_RCC_OscConfig+0x140>
  16720. __HAL_RCC_CSI_DISABLE();
  16721. 8007840: 682b ldr r3, [r5, #0]
  16722. 8007842: f023 0380 bic.w r3, r3, #128 @ 0x80
  16723. 8007846: 602b str r3, [r5, #0]
  16724. tickstart = HAL_GetTick();
  16725. 8007848: f7fc fbc2 bl 8003fd0 <HAL_GetTick>
  16726. 800784c: 4606 mov r6, r0
  16727. while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
  16728. 800784e: e004 b.n 800785a <HAL_RCC_OscConfig+0x38e>
  16729. if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
  16730. 8007850: f7fc fbbe bl 8003fd0 <HAL_GetTick>
  16731. 8007854: 1b80 subs r0, r0, r6
  16732. 8007856: 2802 cmp r0, #2
  16733. 8007858: d8b8 bhi.n 80077cc <HAL_RCC_OscConfig+0x300>
  16734. while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
  16735. 800785a: 682b ldr r3, [r5, #0]
  16736. 800785c: 05df lsls r7, r3, #23
  16737. 800785e: d4f7 bmi.n 8007850 <HAL_RCC_OscConfig+0x384>
  16738. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
  16739. 8007860: 6823 ldr r3, [r4, #0]
  16740. 8007862: e6a2 b.n 80075aa <HAL_RCC_OscConfig+0xde>
  16741. __HAL_RCC_HSI_DISABLE();
  16742. 8007864: f023 0301 bic.w r3, r3, #1
  16743. 8007868: 602b str r3, [r5, #0]
  16744. tickstart = HAL_GetTick();
  16745. 800786a: f7fc fbb1 bl 8003fd0 <HAL_GetTick>
  16746. 800786e: 4606 mov r6, r0
  16747. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
  16748. 8007870: e004 b.n 800787c <HAL_RCC_OscConfig+0x3b0>
  16749. if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
  16750. 8007872: f7fc fbad bl 8003fd0 <HAL_GetTick>
  16751. 8007876: 1b80 subs r0, r0, r6
  16752. 8007878: 2802 cmp r0, #2
  16753. 800787a: d8a7 bhi.n 80077cc <HAL_RCC_OscConfig+0x300>
  16754. while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
  16755. 800787c: 682b ldr r3, [r5, #0]
  16756. 800787e: 0758 lsls r0, r3, #29
  16757. 8007880: d4f7 bmi.n 8007872 <HAL_RCC_OscConfig+0x3a6>
  16758. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
  16759. 8007882: 6823 ldr r3, [r4, #0]
  16760. 8007884: e65b b.n 800753e <HAL_RCC_OscConfig+0x72>
  16761. if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
  16762. 8007886: 0790 lsls r0, r2, #30
  16763. 8007888: f47f af01 bne.w 800768e <HAL_RCC_OscConfig+0x1c2>
  16764. 800788c: e6ce b.n 800762c <HAL_RCC_OscConfig+0x160>
  16765. __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  16766. 800788e: 686b ldr r3, [r5, #4]
  16767. 8007890: 6922 ldr r2, [r4, #16]
  16768. 8007892: f023 43fe bic.w r3, r3, #2130706432 @ 0x7f000000
  16769. 8007896: ea43 6302 orr.w r3, r3, r2, lsl #24
  16770. 800789a: 606b str r3, [r5, #4]
  16771. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
  16772. 800789c: 6823 ldr r3, [r4, #0]
  16773. 800789e: e64e b.n 800753e <HAL_RCC_OscConfig+0x72>
  16774. __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
  16775. 80078a0: 4a36 ldr r2, [pc, #216] @ (800797c <HAL_RCC_OscConfig+0x4b0>)
  16776. 80078a2: 6a21 ldr r1, [r4, #32]
  16777. 80078a4: 68d3 ldr r3, [r2, #12]
  16778. 80078a6: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000
  16779. 80078aa: ea43 6301 orr.w r3, r3, r1, lsl #24
  16780. 80078ae: 60d3 str r3, [r2, #12]
  16781. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
  16782. 80078b0: 6823 ldr r3, [r4, #0]
  16783. 80078b2: e67a b.n 80075aa <HAL_RCC_OscConfig+0xde>
  16784. tickstart = HAL_GetTick();
  16785. 80078b4: f7fc fb8c bl 8003fd0 <HAL_GetTick>
  16786. 80078b8: 4606 mov r6, r0
  16787. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
  16788. 80078ba: e004 b.n 80078c6 <HAL_RCC_OscConfig+0x3fa>
  16789. if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
  16790. 80078bc: f7fc fb88 bl 8003fd0 <HAL_GetTick>
  16791. 80078c0: 1b80 subs r0, r0, r6
  16792. 80078c2: 2802 cmp r0, #2
  16793. 80078c4: d882 bhi.n 80077cc <HAL_RCC_OscConfig+0x300>
  16794. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
  16795. 80078c6: 682b ldr r3, [r5, #0]
  16796. 80078c8: 0199 lsls r1, r3, #6
  16797. 80078ca: d4f7 bmi.n 80078bc <HAL_RCC_OscConfig+0x3f0>
  16798. __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
  16799. 80078cc: 6aa9 ldr r1, [r5, #40] @ 0x28
  16800. 80078ce: 4b2c ldr r3, [pc, #176] @ (8007980 <HAL_RCC_OscConfig+0x4b4>)
  16801. 80078d0: 6aa2 ldr r2, [r4, #40] @ 0x28
  16802. 80078d2: 400b ands r3, r1
  16803. __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
  16804. 80078d4: 492b ldr r1, [pc, #172] @ (8007984 <HAL_RCC_OscConfig+0x4b8>)
  16805. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
  16806. 80078d6: 4e29 ldr r6, [pc, #164] @ (800797c <HAL_RCC_OscConfig+0x4b0>)
  16807. __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
  16808. 80078d8: 4313 orrs r3, r2
  16809. 80078da: 6ae2 ldr r2, [r4, #44] @ 0x2c
  16810. 80078dc: ea43 1302 orr.w r3, r3, r2, lsl #4
  16811. 80078e0: 62ab str r3, [r5, #40] @ 0x28
  16812. 80078e2: e9d4 320d ldrd r3, r2, [r4, #52] @ 0x34
  16813. 80078e6: 3b01 subs r3, #1
  16814. 80078e8: 3a01 subs r2, #1
  16815. 80078ea: 025b lsls r3, r3, #9
  16816. 80078ec: 0412 lsls r2, r2, #16
  16817. 80078ee: b29b uxth r3, r3
  16818. 80078f0: f402 02fe and.w r2, r2, #8323072 @ 0x7f0000
  16819. 80078f4: 4313 orrs r3, r2
  16820. 80078f6: 6b22 ldr r2, [r4, #48] @ 0x30
  16821. 80078f8: 3a01 subs r2, #1
  16822. 80078fa: f3c2 0208 ubfx r2, r2, #0, #9
  16823. 80078fe: 4313 orrs r3, r2
  16824. 8007900: 6be2 ldr r2, [r4, #60] @ 0x3c
  16825. 8007902: 3a01 subs r2, #1
  16826. 8007904: 0612 lsls r2, r2, #24
  16827. 8007906: f002 42fe and.w r2, r2, #2130706432 @ 0x7f000000
  16828. 800790a: 4313 orrs r3, r2
  16829. 800790c: 632b str r3, [r5, #48] @ 0x30
  16830. __HAL_RCC_PLLFRACN_DISABLE();
  16831. 800790e: 6aeb ldr r3, [r5, #44] @ 0x2c
  16832. 8007910: f023 0301 bic.w r3, r3, #1
  16833. 8007914: 62eb str r3, [r5, #44] @ 0x2c
  16834. __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
  16835. 8007916: 6b6a ldr r2, [r5, #52] @ 0x34
  16836. 8007918: 6ca3 ldr r3, [r4, #72] @ 0x48
  16837. 800791a: 4011 ands r1, r2
  16838. 800791c: ea41 01c3 orr.w r1, r1, r3, lsl #3
  16839. 8007920: 6369 str r1, [r5, #52] @ 0x34
  16840. __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
  16841. 8007922: 6aeb ldr r3, [r5, #44] @ 0x2c
  16842. 8007924: 6c22 ldr r2, [r4, #64] @ 0x40
  16843. 8007926: f023 030c bic.w r3, r3, #12
  16844. 800792a: 4313 orrs r3, r2
  16845. 800792c: 62eb str r3, [r5, #44] @ 0x2c
  16846. __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
  16847. 800792e: 6aeb ldr r3, [r5, #44] @ 0x2c
  16848. 8007930: 6c62 ldr r2, [r4, #68] @ 0x44
  16849. 8007932: f023 0302 bic.w r3, r3, #2
  16850. 8007936: 4313 orrs r3, r2
  16851. 8007938: 62eb str r3, [r5, #44] @ 0x2c
  16852. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
  16853. 800793a: 6aeb ldr r3, [r5, #44] @ 0x2c
  16854. 800793c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
  16855. 8007940: 62eb str r3, [r5, #44] @ 0x2c
  16856. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  16857. 8007942: 6aeb ldr r3, [r5, #44] @ 0x2c
  16858. 8007944: f443 3300 orr.w r3, r3, #131072 @ 0x20000
  16859. 8007948: 62eb str r3, [r5, #44] @ 0x2c
  16860. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
  16861. 800794a: 6aeb ldr r3, [r5, #44] @ 0x2c
  16862. 800794c: f443 2380 orr.w r3, r3, #262144 @ 0x40000
  16863. 8007950: 62eb str r3, [r5, #44] @ 0x2c
  16864. __HAL_RCC_PLLFRACN_ENABLE();
  16865. 8007952: 6aeb ldr r3, [r5, #44] @ 0x2c
  16866. 8007954: f043 0301 orr.w r3, r3, #1
  16867. 8007958: 62eb str r3, [r5, #44] @ 0x2c
  16868. __HAL_RCC_PLL_ENABLE();
  16869. 800795a: 682b ldr r3, [r5, #0]
  16870. 800795c: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
  16871. 8007960: 602b str r3, [r5, #0]
  16872. tickstart = HAL_GetTick();
  16873. 8007962: f7fc fb35 bl 8003fd0 <HAL_GetTick>
  16874. 8007966: 4604 mov r4, r0
  16875. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
  16876. 8007968: 6833 ldr r3, [r6, #0]
  16877. 800796a: 019a lsls r2, r3, #6
  16878. 800796c: f53f ae56 bmi.w 800761c <HAL_RCC_OscConfig+0x150>
  16879. if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
  16880. 8007970: f7fc fb2e bl 8003fd0 <HAL_GetTick>
  16881. 8007974: 1b00 subs r0, r0, r4
  16882. 8007976: 2802 cmp r0, #2
  16883. 8007978: d9f6 bls.n 8007968 <HAL_RCC_OscConfig+0x49c>
  16884. 800797a: e727 b.n 80077cc <HAL_RCC_OscConfig+0x300>
  16885. 800797c: 58024400 .word 0x58024400
  16886. 8007980: fffffc0c .word 0xfffffc0c
  16887. 8007984: ffff0007 .word 0xffff0007
  16888. if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
  16889. 8007988: 2b01 cmp r3, #1
  16890. temp1_pllckcfg = RCC->PLLCKSELR;
  16891. 800798a: 6aaa ldr r2, [r5, #40] @ 0x28
  16892. temp2_pllckcfg = RCC->PLL1DIVR;
  16893. 800798c: 6b28 ldr r0, [r5, #48] @ 0x30
  16894. if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
  16895. 800798e: f43f aea4 beq.w 80076da <HAL_RCC_OscConfig+0x20e>
  16896. (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
  16897. 8007992: f002 0303 and.w r3, r2, #3
  16898. if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
  16899. 8007996: 6aa1 ldr r1, [r4, #40] @ 0x28
  16900. 8007998: 428b cmp r3, r1
  16901. 800799a: f47f ae9e bne.w 80076da <HAL_RCC_OscConfig+0x20e>
  16902. ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
  16903. 800799e: f3c2 1205 ubfx r2, r2, #4, #6
  16904. (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
  16905. 80079a2: 6ae3 ldr r3, [r4, #44] @ 0x2c
  16906. 80079a4: 429a cmp r2, r3
  16907. 80079a6: f47f ae98 bne.w 80076da <HAL_RCC_OscConfig+0x20e>
  16908. (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
  16909. 80079aa: 6b23 ldr r3, [r4, #48] @ 0x30
  16910. 80079ac: f3c0 0208 ubfx r2, r0, #0, #9
  16911. 80079b0: 3b01 subs r3, #1
  16912. ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
  16913. 80079b2: 429a cmp r2, r3
  16914. 80079b4: f47f ae91 bne.w 80076da <HAL_RCC_OscConfig+0x20e>
  16915. ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
  16916. 80079b8: 6b63 ldr r3, [r4, #52] @ 0x34
  16917. 80079ba: f3c0 2246 ubfx r2, r0, #9, #7
  16918. 80079be: 3b01 subs r3, #1
  16919. (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
  16920. 80079c0: 429a cmp r2, r3
  16921. 80079c2: f47f ae8a bne.w 80076da <HAL_RCC_OscConfig+0x20e>
  16922. ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
  16923. 80079c6: 6ba3 ldr r3, [r4, #56] @ 0x38
  16924. 80079c8: f3c0 4206 ubfx r2, r0, #16, #7
  16925. 80079cc: 3b01 subs r3, #1
  16926. ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
  16927. 80079ce: 429a cmp r2, r3
  16928. 80079d0: f47f ae83 bne.w 80076da <HAL_RCC_OscConfig+0x20e>
  16929. ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
  16930. 80079d4: 6be3 ldr r3, [r4, #60] @ 0x3c
  16931. 80079d6: f3c0 6006 ubfx r0, r0, #24, #7
  16932. 80079da: 3b01 subs r3, #1
  16933. ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
  16934. 80079dc: 4298 cmp r0, r3
  16935. 80079de: f47f ae7c bne.w 80076da <HAL_RCC_OscConfig+0x20e>
  16936. temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
  16937. 80079e2: 6b6b ldr r3, [r5, #52] @ 0x34
  16938. if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
  16939. 80079e4: 6ca2 ldr r2, [r4, #72] @ 0x48
  16940. temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
  16941. 80079e6: f3c3 03cc ubfx r3, r3, #3, #13
  16942. if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
  16943. 80079ea: 429a cmp r2, r3
  16944. 80079ec: f43f ae16 beq.w 800761c <HAL_RCC_OscConfig+0x150>
  16945. __HAL_RCC_PLLFRACN_DISABLE();
  16946. 80079f0: 4a2d ldr r2, [pc, #180] @ (8007aa8 <HAL_RCC_OscConfig+0x5dc>)
  16947. 80079f2: 6ad3 ldr r3, [r2, #44] @ 0x2c
  16948. 80079f4: f023 0301 bic.w r3, r3, #1
  16949. 80079f8: 62d3 str r3, [r2, #44] @ 0x2c
  16950. tickstart = HAL_GetTick();
  16951. 80079fa: f7fc fae9 bl 8003fd0 <HAL_GetTick>
  16952. 80079fe: 4605 mov r5, r0
  16953. while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE)
  16954. 8007a00: f7fc fae6 bl 8003fd0 <HAL_GetTick>
  16955. 8007a04: 42a8 cmp r0, r5
  16956. 8007a06: d0fb beq.n 8007a00 <HAL_RCC_OscConfig+0x534>
  16957. __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
  16958. 8007a08: 4a27 ldr r2, [pc, #156] @ (8007aa8 <HAL_RCC_OscConfig+0x5dc>)
  16959. 8007a0a: 4b28 ldr r3, [pc, #160] @ (8007aac <HAL_RCC_OscConfig+0x5e0>)
  16960. 8007a0c: 6b50 ldr r0, [r2, #52] @ 0x34
  16961. 8007a0e: 6ca1 ldr r1, [r4, #72] @ 0x48
  16962. 8007a10: 4003 ands r3, r0
  16963. 8007a12: ea43 03c1 orr.w r3, r3, r1, lsl #3
  16964. 8007a16: 6353 str r3, [r2, #52] @ 0x34
  16965. __HAL_RCC_PLLFRACN_ENABLE();
  16966. 8007a18: 6ad3 ldr r3, [r2, #44] @ 0x2c
  16967. 8007a1a: f043 0301 orr.w r3, r3, #1
  16968. 8007a1e: 62d3 str r3, [r2, #44] @ 0x2c
  16969. 8007a20: e5fc b.n 800761c <HAL_RCC_OscConfig+0x150>
  16970. __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
  16971. 8007a22: f442 2280 orr.w r2, r2, #262144 @ 0x40000
  16972. 8007a26: 601a str r2, [r3, #0]
  16973. 8007a28: 681a ldr r2, [r3, #0]
  16974. 8007a2a: f442 3280 orr.w r2, r2, #65536 @ 0x10000
  16975. 8007a2e: 601a str r2, [r3, #0]
  16976. if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
  16977. 8007a30: e574 b.n 800751c <HAL_RCC_OscConfig+0x50>
  16978. __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  16979. 8007a32: 4d1d ldr r5, [pc, #116] @ (8007aa8 <HAL_RCC_OscConfig+0x5dc>)
  16980. if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
  16981. 8007a34: f241 3788 movw r7, #5000 @ 0x1388
  16982. __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  16983. 8007a38: 6f2b ldr r3, [r5, #112] @ 0x70
  16984. 8007a3a: f023 0301 bic.w r3, r3, #1
  16985. 8007a3e: 672b str r3, [r5, #112] @ 0x70
  16986. 8007a40: 6f2b ldr r3, [r5, #112] @ 0x70
  16987. 8007a42: f023 0304 bic.w r3, r3, #4
  16988. 8007a46: 672b str r3, [r5, #112] @ 0x70
  16989. tickstart = HAL_GetTick();
  16990. 8007a48: f7fc fac2 bl 8003fd0 <HAL_GetTick>
  16991. 8007a4c: 4606 mov r6, r0
  16992. while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
  16993. 8007a4e: e005 b.n 8007a5c <HAL_RCC_OscConfig+0x590>
  16994. if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
  16995. 8007a50: f7fc fabe bl 8003fd0 <HAL_GetTick>
  16996. 8007a54: 1b80 subs r0, r0, r6
  16997. 8007a56: 42b8 cmp r0, r7
  16998. 8007a58: f63f aeb8 bhi.w 80077cc <HAL_RCC_OscConfig+0x300>
  16999. while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
  17000. 8007a5c: 6f2b ldr r3, [r5, #112] @ 0x70
  17001. 8007a5e: 0798 lsls r0, r3, #30
  17002. 8007a60: d4f6 bmi.n 8007a50 <HAL_RCC_OscConfig+0x584>
  17003. 8007a62: e5d7 b.n 8007614 <HAL_RCC_OscConfig+0x148>
  17004. __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
  17005. 8007a64: 68eb ldr r3, [r5, #12]
  17006. 8007a66: 6a22 ldr r2, [r4, #32]
  17007. 8007a68: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000
  17008. 8007a6c: ea43 6302 orr.w r3, r3, r2, lsl #24
  17009. 8007a70: 60eb str r3, [r5, #12]
  17010. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
  17011. 8007a72: 6823 ldr r3, [r4, #0]
  17012. 8007a74: e599 b.n 80075aa <HAL_RCC_OscConfig+0xde>
  17013. __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  17014. 8007a76: 4a0c ldr r2, [pc, #48] @ (8007aa8 <HAL_RCC_OscConfig+0x5dc>)
  17015. 8007a78: 6f13 ldr r3, [r2, #112] @ 0x70
  17016. 8007a7a: f043 0301 orr.w r3, r3, #1
  17017. 8007a7e: 6713 str r3, [r2, #112] @ 0x70
  17018. if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
  17019. 8007a80: e67b b.n 800777a <HAL_RCC_OscConfig+0x2ae>
  17020. __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
  17021. 8007a82: 4a09 ldr r2, [pc, #36] @ (8007aa8 <HAL_RCC_OscConfig+0x5dc>)
  17022. 8007a84: 6853 ldr r3, [r2, #4]
  17023. 8007a86: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000
  17024. 8007a8a: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
  17025. 8007a8e: 6053 str r3, [r2, #4]
  17026. if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
  17027. 8007a90: 6823 ldr r3, [r4, #0]
  17028. 8007a92: e58a b.n 80075aa <HAL_RCC_OscConfig+0xde>
  17029. __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  17030. 8007a94: f042 0204 orr.w r2, r2, #4
  17031. 8007a98: 671a str r2, [r3, #112] @ 0x70
  17032. 8007a9a: 6f1a ldr r2, [r3, #112] @ 0x70
  17033. 8007a9c: f042 0201 orr.w r2, r2, #1
  17034. 8007aa0: 671a str r2, [r3, #112] @ 0x70
  17035. if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
  17036. 8007aa2: e66a b.n 800777a <HAL_RCC_OscConfig+0x2ae>
  17037. return HAL_ERROR;
  17038. 8007aa4: 2001 movs r0, #1
  17039. }
  17040. 8007aa6: 4770 bx lr
  17041. 8007aa8: 58024400 .word 0x58024400
  17042. 8007aac: ffff0007 .word 0xffff0007
  17043. 08007ab0 <HAL_RCC_GetSysClockFreq>:
  17044. switch (RCC->CFGR & RCC_CFGR_SWS)
  17045. 8007ab0: 4a3f ldr r2, [pc, #252] @ (8007bb0 <HAL_RCC_GetSysClockFreq+0x100>)
  17046. 8007ab2: 6913 ldr r3, [r2, #16]
  17047. 8007ab4: f003 0338 and.w r3, r3, #56 @ 0x38
  17048. 8007ab8: 2b10 cmp r3, #16
  17049. 8007aba: d004 beq.n 8007ac6 <HAL_RCC_GetSysClockFreq+0x16>
  17050. 8007abc: 2b18 cmp r3, #24
  17051. 8007abe: d00d beq.n 8007adc <HAL_RCC_GetSysClockFreq+0x2c>
  17052. 8007ac0: b11b cbz r3, 8007aca <HAL_RCC_GetSysClockFreq+0x1a>
  17053. sysclockfreq = CSI_VALUE;
  17054. 8007ac2: 483c ldr r0, [pc, #240] @ (8007bb4 <HAL_RCC_GetSysClockFreq+0x104>)
  17055. 8007ac4: 4770 bx lr
  17056. switch (RCC->CFGR & RCC_CFGR_SWS)
  17057. 8007ac6: 483c ldr r0, [pc, #240] @ (8007bb8 <HAL_RCC_GetSysClockFreq+0x108>)
  17058. 8007ac8: 4770 bx lr
  17059. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  17060. 8007aca: 6813 ldr r3, [r2, #0]
  17061. 8007acc: 0699 lsls r1, r3, #26
  17062. 8007ace: d548 bpl.n 8007b62 <HAL_RCC_GetSysClockFreq+0xb2>
  17063. sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  17064. 8007ad0: 6813 ldr r3, [r2, #0]
  17065. 8007ad2: 483a ldr r0, [pc, #232] @ (8007bbc <HAL_RCC_GetSysClockFreq+0x10c>)
  17066. 8007ad4: f3c3 03c1 ubfx r3, r3, #3, #2
  17067. 8007ad8: 40d8 lsrs r0, r3
  17068. 8007ada: 4770 bx lr
  17069. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  17070. 8007adc: 6a93 ldr r3, [r2, #40] @ 0x28
  17071. {
  17072. 8007ade: b430 push {r4, r5}
  17073. pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ;
  17074. 8007ae0: 6a94 ldr r4, [r2, #40] @ 0x28
  17075. pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
  17076. 8007ae2: 6ad5 ldr r5, [r2, #44] @ 0x2c
  17077. if (pllm != 0U)
  17078. 8007ae4: f414 7f7c tst.w r4, #1008 @ 0x3f0
  17079. fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
  17080. 8007ae8: 6b51 ldr r1, [r2, #52] @ 0x34
  17081. pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ;
  17082. 8007aea: f3c4 1005 ubfx r0, r4, #4, #6
  17083. if (pllm != 0U)
  17084. 8007aee: d036 beq.n 8007b5e <HAL_RCC_GetSysClockFreq+0xae>
  17085. fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
  17086. 8007af0: f3c1 01cc ubfx r1, r1, #3, #13
  17087. pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
  17088. 8007af4: f005 0501 and.w r5, r5, #1
  17089. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  17090. 8007af8: f003 0303 and.w r3, r3, #3
  17091. pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  17092. 8007afc: ee07 0a90 vmov s15, r0
  17093. fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
  17094. 8007b00: fb05 f101 mul.w r1, r5, r1
  17095. 8007b04: 2b01 cmp r3, #1
  17096. pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  17097. 8007b06: eef8 7ae7 vcvt.f32.s32 s15, s15
  17098. 8007b0a: ee06 1a90 vmov s13, r1
  17099. 8007b0e: eefa 6ae9 vcvt.f32.s32 s13, s13, #13
  17100. 8007b12: d002 beq.n 8007b1a <HAL_RCC_GetSysClockFreq+0x6a>
  17101. 8007b14: 2b02 cmp r3, #2
  17102. 8007b16: d026 beq.n 8007b66 <HAL_RCC_GetSysClockFreq+0xb6>
  17103. 8007b18: b343 cbz r3, 8007b6c <HAL_RCC_GetSysClockFreq+0xbc>
  17104. pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  17105. 8007b1a: ed9f 7a29 vldr s14, [pc, #164] @ 8007bc0 <HAL_RCC_GetSysClockFreq+0x110>
  17106. 8007b1e: ee87 6a27 vdiv.f32 s12, s14, s15
  17107. 8007b22: 6b13 ldr r3, [r2, #48] @ 0x30
  17108. 8007b24: f3c3 0308 ubfx r3, r3, #0, #9
  17109. 8007b28: ee07 3a10 vmov s14, r3
  17110. 8007b2c: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
  17111. 8007b30: eeb8 7ac7 vcvt.f32.s32 s14, s14
  17112. 8007b34: ee37 7a25 vadd.f32 s14, s14, s11
  17113. 8007b38: ee37 7a26 vadd.f32 s14, s14, s13
  17114. 8007b3c: ee27 7a06 vmul.f32 s14, s14, s12
  17115. pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
  17116. 8007b40: 4b1b ldr r3, [pc, #108] @ (8007bb0 <HAL_RCC_GetSysClockFreq+0x100>)
  17117. 8007b42: 6b1b ldr r3, [r3, #48] @ 0x30
  17118. 8007b44: f3c3 2346 ubfx r3, r3, #9, #7
  17119. 8007b48: 3301 adds r3, #1
  17120. sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
  17121. 8007b4a: ee07 3a90 vmov s15, r3
  17122. 8007b4e: eef8 6ae7 vcvt.f32.s32 s13, s15
  17123. 8007b52: eec7 7a26 vdiv.f32 s15, s14, s13
  17124. 8007b56: eefc 7ae7 vcvt.u32.f32 s15, s15
  17125. 8007b5a: ee17 0a90 vmov r0, s15
  17126. }
  17127. 8007b5e: bc30 pop {r4, r5}
  17128. 8007b60: 4770 bx lr
  17129. sysclockfreq = (uint32_t) HSI_VALUE;
  17130. 8007b62: 4816 ldr r0, [pc, #88] @ (8007bbc <HAL_RCC_GetSysClockFreq+0x10c>)
  17131. }
  17132. 8007b64: 4770 bx lr
  17133. pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  17134. 8007b66: ed9f 7a17 vldr s14, [pc, #92] @ 8007bc4 <HAL_RCC_GetSysClockFreq+0x114>
  17135. 8007b6a: e7d8 b.n 8007b1e <HAL_RCC_GetSysClockFreq+0x6e>
  17136. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  17137. 8007b6c: 6813 ldr r3, [r2, #0]
  17138. 8007b6e: 069b lsls r3, r3, #26
  17139. 8007b70: d51a bpl.n 8007ba8 <HAL_RCC_GetSysClockFreq+0xf8>
  17140. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  17141. 8007b72: 6810 ldr r0, [r2, #0]
  17142. pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  17143. 8007b74: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0
  17144. 8007b78: 6b13 ldr r3, [r2, #48] @ 0x30
  17145. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  17146. 8007b7a: 4910 ldr r1, [pc, #64] @ (8007bbc <HAL_RCC_GetSysClockFreq+0x10c>)
  17147. 8007b7c: f3c0 02c1 ubfx r2, r0, #3, #2
  17148. pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  17149. 8007b80: f3c3 0308 ubfx r3, r3, #0, #9
  17150. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  17151. 8007b84: 40d1 lsrs r1, r2
  17152. pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  17153. 8007b86: ee06 3a10 vmov s12, r3
  17154. 8007b8a: ee05 1a90 vmov s11, r1
  17155. 8007b8e: eeb8 6ac6 vcvt.f32.s32 s12, s12
  17156. 8007b92: eef8 5ae5 vcvt.f32.s32 s11, s11
  17157. 8007b96: ee36 6a07 vadd.f32 s12, s12, s14
  17158. 8007b9a: ee85 7aa7 vdiv.f32 s14, s11, s15
  17159. 8007b9e: ee76 7a26 vadd.f32 s15, s12, s13
  17160. 8007ba2: ee27 7a27 vmul.f32 s14, s14, s15
  17161. 8007ba6: e7cb b.n 8007b40 <HAL_RCC_GetSysClockFreq+0x90>
  17162. pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  17163. 8007ba8: ed9f 7a07 vldr s14, [pc, #28] @ 8007bc8 <HAL_RCC_GetSysClockFreq+0x118>
  17164. 8007bac: e7b7 b.n 8007b1e <HAL_RCC_GetSysClockFreq+0x6e>
  17165. 8007bae: bf00 nop
  17166. 8007bb0: 58024400 .word 0x58024400
  17167. 8007bb4: 003d0900 .word 0x003d0900
  17168. 8007bb8: 017d7840 .word 0x017d7840
  17169. 8007bbc: 03d09000 .word 0x03d09000
  17170. 8007bc0: 4a742400 .word 0x4a742400
  17171. 8007bc4: 4bbebc20 .word 0x4bbebc20
  17172. 8007bc8: 4c742400 .word 0x4c742400
  17173. 08007bcc <HAL_RCC_ClockConfig>:
  17174. if (RCC_ClkInitStruct == NULL)
  17175. 8007bcc: 2800 cmp r0, #0
  17176. 8007bce: f000 810e beq.w 8007dee <HAL_RCC_ClockConfig+0x222>
  17177. if (FLatency > __HAL_FLASH_GET_LATENCY())
  17178. 8007bd2: 4a8d ldr r2, [pc, #564] @ (8007e08 <HAL_RCC_ClockConfig+0x23c>)
  17179. 8007bd4: 6813 ldr r3, [r2, #0]
  17180. 8007bd6: f003 030f and.w r3, r3, #15
  17181. 8007bda: 428b cmp r3, r1
  17182. {
  17183. 8007bdc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  17184. 8007be0: 4604 mov r4, r0
  17185. 8007be2: 460d mov r5, r1
  17186. if (FLatency > __HAL_FLASH_GET_LATENCY())
  17187. 8007be4: d20c bcs.n 8007c00 <HAL_RCC_ClockConfig+0x34>
  17188. __HAL_FLASH_SET_LATENCY(FLatency);
  17189. 8007be6: 6813 ldr r3, [r2, #0]
  17190. 8007be8: f023 030f bic.w r3, r3, #15
  17191. 8007bec: 430b orrs r3, r1
  17192. 8007bee: 6013 str r3, [r2, #0]
  17193. if (__HAL_FLASH_GET_LATENCY() != FLatency)
  17194. 8007bf0: 6813 ldr r3, [r2, #0]
  17195. 8007bf2: f003 030f and.w r3, r3, #15
  17196. 8007bf6: 428b cmp r3, r1
  17197. 8007bf8: d002 beq.n 8007c00 <HAL_RCC_ClockConfig+0x34>
  17198. return HAL_ERROR;
  17199. 8007bfa: 2001 movs r0, #1
  17200. }
  17201. 8007bfc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  17202. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
  17203. 8007c00: 6823 ldr r3, [r4, #0]
  17204. 8007c02: 0758 lsls r0, r3, #29
  17205. 8007c04: d50b bpl.n 8007c1e <HAL_RCC_ClockConfig+0x52>
  17206. if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
  17207. 8007c06: 4981 ldr r1, [pc, #516] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17208. 8007c08: 6920 ldr r0, [r4, #16]
  17209. 8007c0a: 698a ldr r2, [r1, #24]
  17210. 8007c0c: f002 0270 and.w r2, r2, #112 @ 0x70
  17211. 8007c10: 4290 cmp r0, r2
  17212. 8007c12: d904 bls.n 8007c1e <HAL_RCC_ClockConfig+0x52>
  17213. MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
  17214. 8007c14: 698a ldr r2, [r1, #24]
  17215. 8007c16: f022 0270 bic.w r2, r2, #112 @ 0x70
  17216. 8007c1a: 4302 orrs r2, r0
  17217. 8007c1c: 618a str r2, [r1, #24]
  17218. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
  17219. 8007c1e: 0719 lsls r1, r3, #28
  17220. 8007c20: d50b bpl.n 8007c3a <HAL_RCC_ClockConfig+0x6e>
  17221. if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
  17222. 8007c22: 497a ldr r1, [pc, #488] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17223. 8007c24: 6960 ldr r0, [r4, #20]
  17224. 8007c26: 69ca ldr r2, [r1, #28]
  17225. 8007c28: f002 0270 and.w r2, r2, #112 @ 0x70
  17226. 8007c2c: 4290 cmp r0, r2
  17227. 8007c2e: d904 bls.n 8007c3a <HAL_RCC_ClockConfig+0x6e>
  17228. MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
  17229. 8007c30: 69ca ldr r2, [r1, #28]
  17230. 8007c32: f022 0270 bic.w r2, r2, #112 @ 0x70
  17231. 8007c36: 4302 orrs r2, r0
  17232. 8007c38: 61ca str r2, [r1, #28]
  17233. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
  17234. 8007c3a: 06da lsls r2, r3, #27
  17235. 8007c3c: d50b bpl.n 8007c56 <HAL_RCC_ClockConfig+0x8a>
  17236. if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
  17237. 8007c3e: 4973 ldr r1, [pc, #460] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17238. 8007c40: 69a0 ldr r0, [r4, #24]
  17239. 8007c42: 69ca ldr r2, [r1, #28]
  17240. 8007c44: f402 62e0 and.w r2, r2, #1792 @ 0x700
  17241. 8007c48: 4290 cmp r0, r2
  17242. 8007c4a: d904 bls.n 8007c56 <HAL_RCC_ClockConfig+0x8a>
  17243. MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
  17244. 8007c4c: 69ca ldr r2, [r1, #28]
  17245. 8007c4e: f422 62e0 bic.w r2, r2, #1792 @ 0x700
  17246. 8007c52: 4302 orrs r2, r0
  17247. 8007c54: 61ca str r2, [r1, #28]
  17248. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
  17249. 8007c56: 069f lsls r7, r3, #26
  17250. 8007c58: d50b bpl.n 8007c72 <HAL_RCC_ClockConfig+0xa6>
  17251. if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
  17252. 8007c5a: 496c ldr r1, [pc, #432] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17253. 8007c5c: 69e0 ldr r0, [r4, #28]
  17254. 8007c5e: 6a0a ldr r2, [r1, #32]
  17255. 8007c60: f002 0270 and.w r2, r2, #112 @ 0x70
  17256. 8007c64: 4290 cmp r0, r2
  17257. 8007c66: d904 bls.n 8007c72 <HAL_RCC_ClockConfig+0xa6>
  17258. MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
  17259. 8007c68: 6a0a ldr r2, [r1, #32]
  17260. 8007c6a: f022 0270 bic.w r2, r2, #112 @ 0x70
  17261. 8007c6e: 4302 orrs r2, r0
  17262. 8007c70: 620a str r2, [r1, #32]
  17263. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
  17264. 8007c72: 079e lsls r6, r3, #30
  17265. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
  17266. 8007c74: f003 0201 and.w r2, r3, #1
  17267. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
  17268. 8007c78: f140 80ab bpl.w 8007dd2 <HAL_RCC_ClockConfig+0x206>
  17269. if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
  17270. 8007c7c: 4e63 ldr r6, [pc, #396] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17271. 8007c7e: 68e0 ldr r0, [r4, #12]
  17272. 8007c80: 69b1 ldr r1, [r6, #24]
  17273. 8007c82: f001 010f and.w r1, r1, #15
  17274. 8007c86: 4288 cmp r0, r1
  17275. 8007c88: d904 bls.n 8007c94 <HAL_RCC_ClockConfig+0xc8>
  17276. MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
  17277. 8007c8a: 69b1 ldr r1, [r6, #24]
  17278. 8007c8c: f021 010f bic.w r1, r1, #15
  17279. 8007c90: 4301 orrs r1, r0
  17280. 8007c92: 61b1 str r1, [r6, #24]
  17281. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
  17282. 8007c94: 2a00 cmp r2, #0
  17283. 8007c96: d030 beq.n 8007cfa <HAL_RCC_ClockConfig+0x12e>
  17284. MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
  17285. 8007c98: 4a5c ldr r2, [pc, #368] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17286. 8007c9a: 68a1 ldr r1, [r4, #8]
  17287. 8007c9c: 6993 ldr r3, [r2, #24]
  17288. 8007c9e: f423 6370 bic.w r3, r3, #3840 @ 0xf00
  17289. 8007ca2: 430b orrs r3, r1
  17290. 8007ca4: 6193 str r3, [r2, #24]
  17291. if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  17292. 8007ca6: 6861 ldr r1, [r4, #4]
  17293. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
  17294. 8007ca8: 6813 ldr r3, [r2, #0]
  17295. if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  17296. 8007caa: 2902 cmp r1, #2
  17297. 8007cac: f000 80a1 beq.w 8007df2 <HAL_RCC_ClockConfig+0x226>
  17298. else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  17299. 8007cb0: 2903 cmp r1, #3
  17300. 8007cb2: f000 8098 beq.w 8007de6 <HAL_RCC_ClockConfig+0x21a>
  17301. else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
  17302. 8007cb6: 2901 cmp r1, #1
  17303. 8007cb8: f000 80a1 beq.w 8007dfe <HAL_RCC_ClockConfig+0x232>
  17304. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  17305. 8007cbc: 075f lsls r7, r3, #29
  17306. 8007cbe: d59c bpl.n 8007bfa <HAL_RCC_ClockConfig+0x2e>
  17307. MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
  17308. 8007cc0: 4e52 ldr r6, [pc, #328] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17309. if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
  17310. 8007cc2: f241 3888 movw r8, #5000 @ 0x1388
  17311. MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
  17312. 8007cc6: 6933 ldr r3, [r6, #16]
  17313. 8007cc8: f023 0307 bic.w r3, r3, #7
  17314. 8007ccc: 430b orrs r3, r1
  17315. 8007cce: 6133 str r3, [r6, #16]
  17316. tickstart = HAL_GetTick();
  17317. 8007cd0: f7fc f97e bl 8003fd0 <HAL_GetTick>
  17318. 8007cd4: 4607 mov r7, r0
  17319. while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
  17320. 8007cd6: e005 b.n 8007ce4 <HAL_RCC_ClockConfig+0x118>
  17321. if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
  17322. 8007cd8: f7fc f97a bl 8003fd0 <HAL_GetTick>
  17323. 8007cdc: 1bc0 subs r0, r0, r7
  17324. 8007cde: 4540 cmp r0, r8
  17325. 8007ce0: f200 808b bhi.w 8007dfa <HAL_RCC_ClockConfig+0x22e>
  17326. while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
  17327. 8007ce4: 6933 ldr r3, [r6, #16]
  17328. 8007ce6: 6862 ldr r2, [r4, #4]
  17329. 8007ce8: f003 0338 and.w r3, r3, #56 @ 0x38
  17330. 8007cec: ebb3 0fc2 cmp.w r3, r2, lsl #3
  17331. 8007cf0: d1f2 bne.n 8007cd8 <HAL_RCC_ClockConfig+0x10c>
  17332. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
  17333. 8007cf2: 6823 ldr r3, [r4, #0]
  17334. 8007cf4: 079e lsls r6, r3, #30
  17335. 8007cf6: d506 bpl.n 8007d06 <HAL_RCC_ClockConfig+0x13a>
  17336. if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
  17337. 8007cf8: 68e0 ldr r0, [r4, #12]
  17338. 8007cfa: 4944 ldr r1, [pc, #272] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17339. 8007cfc: 698a ldr r2, [r1, #24]
  17340. 8007cfe: f002 020f and.w r2, r2, #15
  17341. 8007d02: 4282 cmp r2, r0
  17342. 8007d04: d869 bhi.n 8007dda <HAL_RCC_ClockConfig+0x20e>
  17343. if (FLatency < __HAL_FLASH_GET_LATENCY())
  17344. 8007d06: 4940 ldr r1, [pc, #256] @ (8007e08 <HAL_RCC_ClockConfig+0x23c>)
  17345. 8007d08: 680a ldr r2, [r1, #0]
  17346. 8007d0a: f002 020f and.w r2, r2, #15
  17347. 8007d0e: 42aa cmp r2, r5
  17348. 8007d10: d90a bls.n 8007d28 <HAL_RCC_ClockConfig+0x15c>
  17349. __HAL_FLASH_SET_LATENCY(FLatency);
  17350. 8007d12: 680a ldr r2, [r1, #0]
  17351. 8007d14: f022 020f bic.w r2, r2, #15
  17352. 8007d18: 432a orrs r2, r5
  17353. 8007d1a: 600a str r2, [r1, #0]
  17354. if (__HAL_FLASH_GET_LATENCY() != FLatency)
  17355. 8007d1c: 680a ldr r2, [r1, #0]
  17356. 8007d1e: f002 020f and.w r2, r2, #15
  17357. 8007d22: 42aa cmp r2, r5
  17358. 8007d24: f47f af69 bne.w 8007bfa <HAL_RCC_ClockConfig+0x2e>
  17359. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
  17360. 8007d28: 0758 lsls r0, r3, #29
  17361. 8007d2a: d50b bpl.n 8007d44 <HAL_RCC_ClockConfig+0x178>
  17362. if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
  17363. 8007d2c: 4937 ldr r1, [pc, #220] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17364. 8007d2e: 6920 ldr r0, [r4, #16]
  17365. 8007d30: 698a ldr r2, [r1, #24]
  17366. 8007d32: f002 0270 and.w r2, r2, #112 @ 0x70
  17367. 8007d36: 4290 cmp r0, r2
  17368. 8007d38: d204 bcs.n 8007d44 <HAL_RCC_ClockConfig+0x178>
  17369. MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
  17370. 8007d3a: 698a ldr r2, [r1, #24]
  17371. 8007d3c: f022 0270 bic.w r2, r2, #112 @ 0x70
  17372. 8007d40: 4302 orrs r2, r0
  17373. 8007d42: 618a str r2, [r1, #24]
  17374. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
  17375. 8007d44: 0719 lsls r1, r3, #28
  17376. 8007d46: d50b bpl.n 8007d60 <HAL_RCC_ClockConfig+0x194>
  17377. if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
  17378. 8007d48: 4930 ldr r1, [pc, #192] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17379. 8007d4a: 6960 ldr r0, [r4, #20]
  17380. 8007d4c: 69ca ldr r2, [r1, #28]
  17381. 8007d4e: f002 0270 and.w r2, r2, #112 @ 0x70
  17382. 8007d52: 4290 cmp r0, r2
  17383. 8007d54: d204 bcs.n 8007d60 <HAL_RCC_ClockConfig+0x194>
  17384. MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
  17385. 8007d56: 69ca ldr r2, [r1, #28]
  17386. 8007d58: f022 0270 bic.w r2, r2, #112 @ 0x70
  17387. 8007d5c: 4302 orrs r2, r0
  17388. 8007d5e: 61ca str r2, [r1, #28]
  17389. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
  17390. 8007d60: 06da lsls r2, r3, #27
  17391. 8007d62: d50b bpl.n 8007d7c <HAL_RCC_ClockConfig+0x1b0>
  17392. if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
  17393. 8007d64: 4929 ldr r1, [pc, #164] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17394. 8007d66: 69a0 ldr r0, [r4, #24]
  17395. 8007d68: 69ca ldr r2, [r1, #28]
  17396. 8007d6a: f402 62e0 and.w r2, r2, #1792 @ 0x700
  17397. 8007d6e: 4290 cmp r0, r2
  17398. 8007d70: d204 bcs.n 8007d7c <HAL_RCC_ClockConfig+0x1b0>
  17399. MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
  17400. 8007d72: 69ca ldr r2, [r1, #28]
  17401. 8007d74: f422 62e0 bic.w r2, r2, #1792 @ 0x700
  17402. 8007d78: 4302 orrs r2, r0
  17403. 8007d7a: 61ca str r2, [r1, #28]
  17404. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
  17405. 8007d7c: 069b lsls r3, r3, #26
  17406. 8007d7e: d50b bpl.n 8007d98 <HAL_RCC_ClockConfig+0x1cc>
  17407. if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
  17408. 8007d80: 4a22 ldr r2, [pc, #136] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17409. 8007d82: 69e1 ldr r1, [r4, #28]
  17410. 8007d84: 6a13 ldr r3, [r2, #32]
  17411. 8007d86: f003 0370 and.w r3, r3, #112 @ 0x70
  17412. 8007d8a: 4299 cmp r1, r3
  17413. 8007d8c: d204 bcs.n 8007d98 <HAL_RCC_ClockConfig+0x1cc>
  17414. MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
  17415. 8007d8e: 6a13 ldr r3, [r2, #32]
  17416. 8007d90: f023 0370 bic.w r3, r3, #112 @ 0x70
  17417. 8007d94: 430b orrs r3, r1
  17418. 8007d96: 6213 str r3, [r2, #32]
  17419. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
  17420. 8007d98: f7ff fe8a bl 8007ab0 <HAL_RCC_GetSysClockFreq>
  17421. 8007d9c: 4a1b ldr r2, [pc, #108] @ (8007e0c <HAL_RCC_ClockConfig+0x240>)
  17422. 8007d9e: 4603 mov r3, r0
  17423. 8007da0: 481b ldr r0, [pc, #108] @ (8007e10 <HAL_RCC_ClockConfig+0x244>)
  17424. 8007da2: 6991 ldr r1, [r2, #24]
  17425. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17426. 8007da4: 6992 ldr r2, [r2, #24]
  17427. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
  17428. 8007da6: f3c1 2103 ubfx r1, r1, #8, #4
  17429. SystemCoreClock = common_system_clock;
  17430. 8007daa: 4d1a ldr r5, [pc, #104] @ (8007e14 <HAL_RCC_ClockConfig+0x248>)
  17431. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17432. 8007dac: f002 020f and.w r2, r2, #15
  17433. 8007db0: 4c19 ldr r4, [pc, #100] @ (8007e18 <HAL_RCC_ClockConfig+0x24c>)
  17434. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
  17435. 8007db2: 5c41 ldrb r1, [r0, r1]
  17436. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17437. 8007db4: 5c82 ldrb r2, [r0, r2]
  17438. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
  17439. 8007db6: f001 011f and.w r1, r1, #31
  17440. halstatus = HAL_InitTick(uwTickPrio);
  17441. 8007dba: 4818 ldr r0, [pc, #96] @ (8007e1c <HAL_RCC_ClockConfig+0x250>)
  17442. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17443. 8007dbc: f002 021f and.w r2, r2, #31
  17444. common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
  17445. 8007dc0: 40cb lsrs r3, r1
  17446. halstatus = HAL_InitTick(uwTickPrio);
  17447. 8007dc2: 6800 ldr r0, [r0, #0]
  17448. SystemCoreClock = common_system_clock;
  17449. 8007dc4: 602b str r3, [r5, #0]
  17450. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17451. 8007dc6: 40d3 lsrs r3, r2
  17452. 8007dc8: 6023 str r3, [r4, #0]
  17453. }
  17454. 8007dca: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
  17455. halstatus = HAL_InitTick(uwTickPrio);
  17456. 8007dce: f7fb b8b5 b.w 8002f3c <HAL_InitTick>
  17457. if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
  17458. 8007dd2: 2a00 cmp r2, #0
  17459. 8007dd4: f47f af60 bne.w 8007c98 <HAL_RCC_ClockConfig+0xcc>
  17460. 8007dd8: e795 b.n 8007d06 <HAL_RCC_ClockConfig+0x13a>
  17461. MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
  17462. 8007dda: 698a ldr r2, [r1, #24]
  17463. 8007ddc: f022 020f bic.w r2, r2, #15
  17464. 8007de0: 4302 orrs r2, r0
  17465. 8007de2: 618a str r2, [r1, #24]
  17466. 8007de4: e78f b.n 8007d06 <HAL_RCC_ClockConfig+0x13a>
  17467. if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
  17468. 8007de6: 019a lsls r2, r3, #6
  17469. 8007de8: f53f af6a bmi.w 8007cc0 <HAL_RCC_ClockConfig+0xf4>
  17470. 8007dec: e705 b.n 8007bfa <HAL_RCC_ClockConfig+0x2e>
  17471. return HAL_ERROR;
  17472. 8007dee: 2001 movs r0, #1
  17473. }
  17474. 8007df0: 4770 bx lr
  17475. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
  17476. 8007df2: 0398 lsls r0, r3, #14
  17477. 8007df4: f53f af64 bmi.w 8007cc0 <HAL_RCC_ClockConfig+0xf4>
  17478. 8007df8: e6ff b.n 8007bfa <HAL_RCC_ClockConfig+0x2e>
  17479. return HAL_TIMEOUT;
  17480. 8007dfa: 2003 movs r0, #3
  17481. 8007dfc: e6fe b.n 8007bfc <HAL_RCC_ClockConfig+0x30>
  17482. if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
  17483. 8007dfe: 05db lsls r3, r3, #23
  17484. 8007e00: f53f af5e bmi.w 8007cc0 <HAL_RCC_ClockConfig+0xf4>
  17485. 8007e04: e6f9 b.n 8007bfa <HAL_RCC_ClockConfig+0x2e>
  17486. 8007e06: bf00 nop
  17487. 8007e08: 52002000 .word 0x52002000
  17488. 8007e0c: 58024400 .word 0x58024400
  17489. 8007e10: 08011a14 .word 0x08011a14
  17490. 8007e14: 24000038 .word 0x24000038
  17491. 8007e18: 24000034 .word 0x24000034
  17492. 8007e1c: 24000040 .word 0x24000040
  17493. 08007e20 <HAL_RCC_GetHCLKFreq>:
  17494. switch (RCC->CFGR & RCC_CFGR_SWS)
  17495. 8007e20: 4a18 ldr r2, [pc, #96] @ (8007e84 <HAL_RCC_GetHCLKFreq+0x64>)
  17496. * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
  17497. * and updated within this function
  17498. * @retval HCLK frequency
  17499. */
  17500. uint32_t HAL_RCC_GetHCLKFreq(void)
  17501. {
  17502. 8007e22: b538 push {r3, r4, r5, lr}
  17503. switch (RCC->CFGR & RCC_CFGR_SWS)
  17504. 8007e24: 6913 ldr r3, [r2, #16]
  17505. 8007e26: f003 0338 and.w r3, r3, #56 @ 0x38
  17506. 8007e2a: 2b10 cmp r3, #16
  17507. 8007e2c: d019 beq.n 8007e62 <HAL_RCC_GetHCLKFreq+0x42>
  17508. 8007e2e: 2b18 cmp r3, #24
  17509. 8007e30: d022 beq.n 8007e78 <HAL_RCC_GetHCLKFreq+0x58>
  17510. 8007e32: b1c3 cbz r3, 8007e66 <HAL_RCC_GetHCLKFreq+0x46>
  17511. sysclockfreq = CSI_VALUE;
  17512. 8007e34: 4b14 ldr r3, [pc, #80] @ (8007e88 <HAL_RCC_GetHCLKFreq+0x68>)
  17513. uint32_t common_system_clock;
  17514. #if defined(RCC_D1CFGR_D1CPRE)
  17515. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
  17516. 8007e36: 4913 ldr r1, [pc, #76] @ (8007e84 <HAL_RCC_GetHCLKFreq+0x64>)
  17517. 8007e38: 4814 ldr r0, [pc, #80] @ (8007e8c <HAL_RCC_GetHCLKFreq+0x6c>)
  17518. 8007e3a: 698a ldr r2, [r1, #24]
  17519. #else
  17520. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
  17521. #endif
  17522. #if defined(RCC_D1CFGR_HPRE)
  17523. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17524. 8007e3c: 6989 ldr r1, [r1, #24]
  17525. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
  17526. 8007e3e: f3c2 2203 ubfx r2, r2, #8, #4
  17527. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17528. 8007e42: 4c13 ldr r4, [pc, #76] @ (8007e90 <HAL_RCC_GetHCLKFreq+0x70>)
  17529. 8007e44: f001 010f and.w r1, r1, #15
  17530. #endif
  17531. #if defined(DUAL_CORE) && defined(CORE_CM4)
  17532. SystemCoreClock = SystemD2Clock;
  17533. #else
  17534. SystemCoreClock = common_system_clock;
  17535. 8007e48: 4d12 ldr r5, [pc, #72] @ (8007e94 <HAL_RCC_GetHCLKFreq+0x74>)
  17536. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
  17537. 8007e4a: 5c82 ldrb r2, [r0, r2]
  17538. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17539. 8007e4c: 5c40 ldrb r0, [r0, r1]
  17540. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
  17541. 8007e4e: f002 021f and.w r2, r2, #31
  17542. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17543. 8007e52: f000 001f and.w r0, r0, #31
  17544. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
  17545. 8007e56: 40d3 lsrs r3, r2
  17546. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17547. 8007e58: fa23 f000 lsr.w r0, r3, r0
  17548. SystemCoreClock = common_system_clock;
  17549. 8007e5c: 602b str r3, [r5, #0]
  17550. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17551. 8007e5e: 6020 str r0, [r4, #0]
  17552. #endif /* DUAL_CORE && CORE_CM4 */
  17553. return SystemD2Clock;
  17554. }
  17555. 8007e60: bd38 pop {r3, r4, r5, pc}
  17556. switch (RCC->CFGR & RCC_CFGR_SWS)
  17557. 8007e62: 4b0d ldr r3, [pc, #52] @ (8007e98 <HAL_RCC_GetHCLKFreq+0x78>)
  17558. 8007e64: e7e7 b.n 8007e36 <HAL_RCC_GetHCLKFreq+0x16>
  17559. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  17560. 8007e66: 6813 ldr r3, [r2, #0]
  17561. 8007e68: 069b lsls r3, r3, #26
  17562. 8007e6a: d509 bpl.n 8007e80 <HAL_RCC_GetHCLKFreq+0x60>
  17563. sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  17564. 8007e6c: 6812 ldr r2, [r2, #0]
  17565. 8007e6e: 4b0b ldr r3, [pc, #44] @ (8007e9c <HAL_RCC_GetHCLKFreq+0x7c>)
  17566. 8007e70: f3c2 02c1 ubfx r2, r2, #3, #2
  17567. 8007e74: 40d3 lsrs r3, r2
  17568. 8007e76: e7de b.n 8007e36 <HAL_RCC_GetHCLKFreq+0x16>
  17569. 8007e78: f7ff fab6 bl 80073e8 <HAL_RCC_GetSysClockFreq.part.0>
  17570. 8007e7c: 4603 mov r3, r0
  17571. 8007e7e: e7da b.n 8007e36 <HAL_RCC_GetHCLKFreq+0x16>
  17572. sysclockfreq = (uint32_t) HSI_VALUE;
  17573. 8007e80: 4b06 ldr r3, [pc, #24] @ (8007e9c <HAL_RCC_GetHCLKFreq+0x7c>)
  17574. 8007e82: e7d8 b.n 8007e36 <HAL_RCC_GetHCLKFreq+0x16>
  17575. 8007e84: 58024400 .word 0x58024400
  17576. 8007e88: 003d0900 .word 0x003d0900
  17577. 8007e8c: 08011a14 .word 0x08011a14
  17578. 8007e90: 24000034 .word 0x24000034
  17579. 8007e94: 24000038 .word 0x24000038
  17580. 8007e98: 017d7840 .word 0x017d7840
  17581. 8007e9c: 03d09000 .word 0x03d09000
  17582. 08007ea0 <HAL_RCC_GetPCLK1Freq>:
  17583. switch (RCC->CFGR & RCC_CFGR_SWS)
  17584. 8007ea0: 4a1c ldr r2, [pc, #112] @ (8007f14 <HAL_RCC_GetPCLK1Freq+0x74>)
  17585. * @note Each time PCLK1 changes, this function must be called to update the
  17586. * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  17587. * @retval PCLK1 frequency
  17588. */
  17589. uint32_t HAL_RCC_GetPCLK1Freq(void)
  17590. {
  17591. 8007ea2: b538 push {r3, r4, r5, lr}
  17592. switch (RCC->CFGR & RCC_CFGR_SWS)
  17593. 8007ea4: 6913 ldr r3, [r2, #16]
  17594. 8007ea6: f003 0338 and.w r3, r3, #56 @ 0x38
  17595. 8007eaa: 2b10 cmp r3, #16
  17596. 8007eac: d020 beq.n 8007ef0 <HAL_RCC_GetPCLK1Freq+0x50>
  17597. 8007eae: 2b18 cmp r3, #24
  17598. 8007eb0: d029 beq.n 8007f06 <HAL_RCC_GetPCLK1Freq+0x66>
  17599. 8007eb2: b1fb cbz r3, 8007ef4 <HAL_RCC_GetPCLK1Freq+0x54>
  17600. sysclockfreq = CSI_VALUE;
  17601. 8007eb4: 4b18 ldr r3, [pc, #96] @ (8007f18 <HAL_RCC_GetPCLK1Freq+0x78>)
  17602. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
  17603. 8007eb6: 4a17 ldr r2, [pc, #92] @ (8007f14 <HAL_RCC_GetPCLK1Freq+0x74>)
  17604. 8007eb8: 4918 ldr r1, [pc, #96] @ (8007f1c <HAL_RCC_GetPCLK1Freq+0x7c>)
  17605. 8007eba: 6990 ldr r0, [r2, #24]
  17606. SystemCoreClock = common_system_clock;
  17607. 8007ebc: 4d18 ldr r5, [pc, #96] @ (8007f20 <HAL_RCC_GetPCLK1Freq+0x80>)
  17608. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
  17609. 8007ebe: f3c0 2003 ubfx r0, r0, #8, #4
  17610. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17611. 8007ec2: 4c18 ldr r4, [pc, #96] @ (8007f24 <HAL_RCC_GetPCLK1Freq+0x84>)
  17612. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
  17613. 8007ec4: 5c08 ldrb r0, [r1, r0]
  17614. 8007ec6: f000 001f and.w r0, r0, #31
  17615. 8007eca: 40c3 lsrs r3, r0
  17616. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17617. 8007ecc: 6990 ldr r0, [r2, #24]
  17618. 8007ece: f000 000f and.w r0, r0, #15
  17619. SystemCoreClock = common_system_clock;
  17620. 8007ed2: 602b str r3, [r5, #0]
  17621. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17622. 8007ed4: 5c08 ldrb r0, [r1, r0]
  17623. 8007ed6: f000 001f and.w r0, r0, #31
  17624. 8007eda: 40c3 lsrs r3, r0
  17625. 8007edc: 6023 str r3, [r4, #0]
  17626. #if defined (RCC_D2CFGR_D2PPRE1)
  17627. /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  17628. return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
  17629. 8007ede: 69d2 ldr r2, [r2, #28]
  17630. 8007ee0: f3c2 1202 ubfx r2, r2, #4, #3
  17631. 8007ee4: 5c88 ldrb r0, [r1, r2]
  17632. 8007ee6: f000 001f and.w r0, r0, #31
  17633. #else
  17634. /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  17635. return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
  17636. #endif
  17637. }
  17638. 8007eea: fa23 f000 lsr.w r0, r3, r0
  17639. 8007eee: bd38 pop {r3, r4, r5, pc}
  17640. switch (RCC->CFGR & RCC_CFGR_SWS)
  17641. 8007ef0: 4b0d ldr r3, [pc, #52] @ (8007f28 <HAL_RCC_GetPCLK1Freq+0x88>)
  17642. 8007ef2: e7e0 b.n 8007eb6 <HAL_RCC_GetPCLK1Freq+0x16>
  17643. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  17644. 8007ef4: 6813 ldr r3, [r2, #0]
  17645. 8007ef6: 069b lsls r3, r3, #26
  17646. 8007ef8: d509 bpl.n 8007f0e <HAL_RCC_GetPCLK1Freq+0x6e>
  17647. sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  17648. 8007efa: 6812 ldr r2, [r2, #0]
  17649. 8007efc: 4b0b ldr r3, [pc, #44] @ (8007f2c <HAL_RCC_GetPCLK1Freq+0x8c>)
  17650. 8007efe: f3c2 02c1 ubfx r2, r2, #3, #2
  17651. 8007f02: 40d3 lsrs r3, r2
  17652. 8007f04: e7d7 b.n 8007eb6 <HAL_RCC_GetPCLK1Freq+0x16>
  17653. 8007f06: f7ff fa6f bl 80073e8 <HAL_RCC_GetSysClockFreq.part.0>
  17654. 8007f0a: 4603 mov r3, r0
  17655. 8007f0c: e7d3 b.n 8007eb6 <HAL_RCC_GetPCLK1Freq+0x16>
  17656. sysclockfreq = (uint32_t) HSI_VALUE;
  17657. 8007f0e: 4b07 ldr r3, [pc, #28] @ (8007f2c <HAL_RCC_GetPCLK1Freq+0x8c>)
  17658. 8007f10: e7d1 b.n 8007eb6 <HAL_RCC_GetPCLK1Freq+0x16>
  17659. 8007f12: bf00 nop
  17660. 8007f14: 58024400 .word 0x58024400
  17661. 8007f18: 003d0900 .word 0x003d0900
  17662. 8007f1c: 08011a14 .word 0x08011a14
  17663. 8007f20: 24000038 .word 0x24000038
  17664. 8007f24: 24000034 .word 0x24000034
  17665. 8007f28: 017d7840 .word 0x017d7840
  17666. 8007f2c: 03d09000 .word 0x03d09000
  17667. 08007f30 <HAL_RCC_GetPCLK2Freq>:
  17668. switch (RCC->CFGR & RCC_CFGR_SWS)
  17669. 8007f30: 4a1c ldr r2, [pc, #112] @ (8007fa4 <HAL_RCC_GetPCLK2Freq+0x74>)
  17670. * @note Each time PCLK2 changes, this function must be called to update the
  17671. * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  17672. * @retval PCLK1 frequency
  17673. */
  17674. uint32_t HAL_RCC_GetPCLK2Freq(void)
  17675. {
  17676. 8007f32: b538 push {r3, r4, r5, lr}
  17677. switch (RCC->CFGR & RCC_CFGR_SWS)
  17678. 8007f34: 6913 ldr r3, [r2, #16]
  17679. 8007f36: f003 0338 and.w r3, r3, #56 @ 0x38
  17680. 8007f3a: 2b10 cmp r3, #16
  17681. 8007f3c: d020 beq.n 8007f80 <HAL_RCC_GetPCLK2Freq+0x50>
  17682. 8007f3e: 2b18 cmp r3, #24
  17683. 8007f40: d029 beq.n 8007f96 <HAL_RCC_GetPCLK2Freq+0x66>
  17684. 8007f42: b1fb cbz r3, 8007f84 <HAL_RCC_GetPCLK2Freq+0x54>
  17685. sysclockfreq = CSI_VALUE;
  17686. 8007f44: 4b18 ldr r3, [pc, #96] @ (8007fa8 <HAL_RCC_GetPCLK2Freq+0x78>)
  17687. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
  17688. 8007f46: 4a17 ldr r2, [pc, #92] @ (8007fa4 <HAL_RCC_GetPCLK2Freq+0x74>)
  17689. 8007f48: 4918 ldr r1, [pc, #96] @ (8007fac <HAL_RCC_GetPCLK2Freq+0x7c>)
  17690. 8007f4a: 6990 ldr r0, [r2, #24]
  17691. SystemCoreClock = common_system_clock;
  17692. 8007f4c: 4d18 ldr r5, [pc, #96] @ (8007fb0 <HAL_RCC_GetPCLK2Freq+0x80>)
  17693. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
  17694. 8007f4e: f3c0 2003 ubfx r0, r0, #8, #4
  17695. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17696. 8007f52: 4c18 ldr r4, [pc, #96] @ (8007fb4 <HAL_RCC_GetPCLK2Freq+0x84>)
  17697. common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
  17698. 8007f54: 5c08 ldrb r0, [r1, r0]
  17699. 8007f56: f000 001f and.w r0, r0, #31
  17700. 8007f5a: 40c3 lsrs r3, r0
  17701. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17702. 8007f5c: 6990 ldr r0, [r2, #24]
  17703. 8007f5e: f000 000f and.w r0, r0, #15
  17704. SystemCoreClock = common_system_clock;
  17705. 8007f62: 602b str r3, [r5, #0]
  17706. SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
  17707. 8007f64: 5c08 ldrb r0, [r1, r0]
  17708. 8007f66: f000 001f and.w r0, r0, #31
  17709. 8007f6a: 40c3 lsrs r3, r0
  17710. 8007f6c: 6023 str r3, [r4, #0]
  17711. /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  17712. #if defined(RCC_D2CFGR_D2PPRE2)
  17713. return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
  17714. 8007f6e: 69d2 ldr r2, [r2, #28]
  17715. 8007f70: f3c2 2202 ubfx r2, r2, #8, #3
  17716. 8007f74: 5c88 ldrb r0, [r1, r2]
  17717. 8007f76: f000 001f and.w r0, r0, #31
  17718. #else
  17719. return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
  17720. #endif
  17721. }
  17722. 8007f7a: fa23 f000 lsr.w r0, r3, r0
  17723. 8007f7e: bd38 pop {r3, r4, r5, pc}
  17724. switch (RCC->CFGR & RCC_CFGR_SWS)
  17725. 8007f80: 4b0d ldr r3, [pc, #52] @ (8007fb8 <HAL_RCC_GetPCLK2Freq+0x88>)
  17726. 8007f82: e7e0 b.n 8007f46 <HAL_RCC_GetPCLK2Freq+0x16>
  17727. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  17728. 8007f84: 6813 ldr r3, [r2, #0]
  17729. 8007f86: 069b lsls r3, r3, #26
  17730. 8007f88: d509 bpl.n 8007f9e <HAL_RCC_GetPCLK2Freq+0x6e>
  17731. sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  17732. 8007f8a: 6812 ldr r2, [r2, #0]
  17733. 8007f8c: 4b0b ldr r3, [pc, #44] @ (8007fbc <HAL_RCC_GetPCLK2Freq+0x8c>)
  17734. 8007f8e: f3c2 02c1 ubfx r2, r2, #3, #2
  17735. 8007f92: 40d3 lsrs r3, r2
  17736. 8007f94: e7d7 b.n 8007f46 <HAL_RCC_GetPCLK2Freq+0x16>
  17737. 8007f96: f7ff fa27 bl 80073e8 <HAL_RCC_GetSysClockFreq.part.0>
  17738. 8007f9a: 4603 mov r3, r0
  17739. 8007f9c: e7d3 b.n 8007f46 <HAL_RCC_GetPCLK2Freq+0x16>
  17740. sysclockfreq = (uint32_t) HSI_VALUE;
  17741. 8007f9e: 4b07 ldr r3, [pc, #28] @ (8007fbc <HAL_RCC_GetPCLK2Freq+0x8c>)
  17742. 8007fa0: e7d1 b.n 8007f46 <HAL_RCC_GetPCLK2Freq+0x16>
  17743. 8007fa2: bf00 nop
  17744. 8007fa4: 58024400 .word 0x58024400
  17745. 8007fa8: 003d0900 .word 0x003d0900
  17746. 8007fac: 08011a14 .word 0x08011a14
  17747. 8007fb0: 24000038 .word 0x24000038
  17748. 8007fb4: 24000034 .word 0x24000034
  17749. 8007fb8: 017d7840 .word 0x017d7840
  17750. 8007fbc: 03d09000 .word 0x03d09000
  17751. 08007fc0 <HAL_RCC_GetClockConfig>:
  17752. /* Set all possible values for the Clock type parameter --------------------*/
  17753. RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
  17754. RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ;
  17755. /* Get the SYSCLK configuration --------------------------------------------*/
  17756. RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
  17757. 8007fc0: 4b13 ldr r3, [pc, #76] @ (8008010 <HAL_RCC_GetClockConfig+0x50>)
  17758. RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
  17759. 8007fc2: 223f movs r2, #63 @ 0x3f
  17760. 8007fc4: 6002 str r2, [r0, #0]
  17761. RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
  17762. 8007fc6: 691a ldr r2, [r3, #16]
  17763. 8007fc8: f002 0207 and.w r2, r2, #7
  17764. 8007fcc: 6042 str r2, [r0, #4]
  17765. #if defined(RCC_D1CFGR_D1CPRE)
  17766. /* Get the SYSCLK configuration ----------------------------------------------*/
  17767. RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
  17768. 8007fce: 699a ldr r2, [r3, #24]
  17769. 8007fd0: f402 6270 and.w r2, r2, #3840 @ 0xf00
  17770. 8007fd4: 6082 str r2, [r0, #8]
  17771. /* Get the D1HCLK configuration ----------------------------------------------*/
  17772. RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
  17773. 8007fd6: 699a ldr r2, [r3, #24]
  17774. 8007fd8: f002 020f and.w r2, r2, #15
  17775. 8007fdc: 60c2 str r2, [r0, #12]
  17776. /* Get the APB3 configuration ----------------------------------------------*/
  17777. RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
  17778. 8007fde: 699a ldr r2, [r3, #24]
  17779. 8007fe0: f002 0270 and.w r2, r2, #112 @ 0x70
  17780. 8007fe4: 6102 str r2, [r0, #16]
  17781. /* Get the APB1 configuration ----------------------------------------------*/
  17782. RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
  17783. 8007fe6: 69da ldr r2, [r3, #28]
  17784. 8007fe8: f002 0270 and.w r2, r2, #112 @ 0x70
  17785. 8007fec: 6142 str r2, [r0, #20]
  17786. /* Get the APB2 configuration ----------------------------------------------*/
  17787. RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
  17788. 8007fee: 69da ldr r2, [r3, #28]
  17789. 8007ff0: f402 62e0 and.w r2, r2, #1792 @ 0x700
  17790. 8007ff4: 6182 str r2, [r0, #24]
  17791. /* Get the APB4 configuration ----------------------------------------------*/
  17792. RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
  17793. 8007ff6: 6a1b ldr r3, [r3, #32]
  17794. {
  17795. 8007ff8: b410 push {r4}
  17796. RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
  17797. 8007ffa: f003 0370 and.w r3, r3, #112 @ 0x70
  17798. /* Get the APB4 configuration ----------------------------------------------*/
  17799. RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE);
  17800. #endif
  17801. /* Get the Flash Wait State (Latency) configuration ------------------------*/
  17802. *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
  17803. 8007ffe: 4c05 ldr r4, [pc, #20] @ (8008014 <HAL_RCC_GetClockConfig+0x54>)
  17804. RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
  17805. 8008000: 61c3 str r3, [r0, #28]
  17806. *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
  17807. 8008002: 6823 ldr r3, [r4, #0]
  17808. }
  17809. 8008004: f85d 4b04 ldr.w r4, [sp], #4
  17810. *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
  17811. 8008008: f003 030f and.w r3, r3, #15
  17812. 800800c: 600b str r3, [r1, #0]
  17813. }
  17814. 800800e: 4770 bx lr
  17815. 8008010: 58024400 .word 0x58024400
  17816. 8008014: 52002000 .word 0x52002000
  17817. 08008018 <RCCEx_PLL2_Config.part.0>:
  17818. * @param Divider divider parameter to be updated
  17819. * @note PLL2 is temporary disabled to apply new parameters
  17820. *
  17821. * @retval HAL status
  17822. */
  17823. static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
  17824. 8008018: b5f8 push {r3, r4, r5, r6, r7, lr}
  17825. else
  17826. {
  17827. /* Disable PLL2. */
  17828. __HAL_RCC_PLL2_DISABLE();
  17829. 800801a: 4c36 ldr r4, [pc, #216] @ (80080f4 <RCCEx_PLL2_Config.part.0+0xdc>)
  17830. static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
  17831. 800801c: 4606 mov r6, r0
  17832. 800801e: 460f mov r7, r1
  17833. __HAL_RCC_PLL2_DISABLE();
  17834. 8008020: 6823 ldr r3, [r4, #0]
  17835. 8008022: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
  17836. 8008026: 6023 str r3, [r4, #0]
  17837. /* Get Start Tick*/
  17838. tickstart = HAL_GetTick();
  17839. 8008028: f7fb ffd2 bl 8003fd0 <HAL_GetTick>
  17840. 800802c: 4605 mov r5, r0
  17841. /* Wait till PLL is disabled */
  17842. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
  17843. 800802e: e004 b.n 800803a <RCCEx_PLL2_Config.part.0+0x22>
  17844. {
  17845. if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
  17846. 8008030: f7fb ffce bl 8003fd0 <HAL_GetTick>
  17847. 8008034: 1b40 subs r0, r0, r5
  17848. 8008036: 2802 cmp r0, #2
  17849. 8008038: d856 bhi.n 80080e8 <RCCEx_PLL2_Config.part.0+0xd0>
  17850. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
  17851. 800803a: 6823 ldr r3, [r4, #0]
  17852. 800803c: 011a lsls r2, r3, #4
  17853. 800803e: d4f7 bmi.n 8008030 <RCCEx_PLL2_Config.part.0+0x18>
  17854. return HAL_TIMEOUT;
  17855. }
  17856. }
  17857. /* Configure PLL2 multiplication and division factors. */
  17858. __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
  17859. 8008040: 6aa3 ldr r3, [r4, #40] @ 0x28
  17860. 8008042: 6832 ldr r2, [r6, #0]
  17861. 8008044: f423 337c bic.w r3, r3, #258048 @ 0x3f000
  17862. 8008048: ea43 3302 orr.w r3, r3, r2, lsl #12
  17863. 800804c: 62a3 str r3, [r4, #40] @ 0x28
  17864. 800804e: e9d6 3202 ldrd r3, r2, [r6, #8]
  17865. 8008052: 3b01 subs r3, #1
  17866. 8008054: 3a01 subs r2, #1
  17867. 8008056: 025b lsls r3, r3, #9
  17868. 8008058: 0412 lsls r2, r2, #16
  17869. 800805a: b29b uxth r3, r3
  17870. 800805c: f402 02fe and.w r2, r2, #8323072 @ 0x7f0000
  17871. 8008060: 4313 orrs r3, r2
  17872. 8008062: 6872 ldr r2, [r6, #4]
  17873. 8008064: 3a01 subs r2, #1
  17874. 8008066: f3c2 0208 ubfx r2, r2, #0, #9
  17875. 800806a: 4313 orrs r3, r2
  17876. 800806c: 6932 ldr r2, [r6, #16]
  17877. 800806e: 3a01 subs r2, #1
  17878. 8008070: 0612 lsls r2, r2, #24
  17879. 8008072: f002 42fe and.w r2, r2, #2130706432 @ 0x7f000000
  17880. 8008076: 4313 orrs r3, r2
  17881. 8008078: 63a3 str r3, [r4, #56] @ 0x38
  17882. pll2->PLL2P,
  17883. pll2->PLL2Q,
  17884. pll2->PLL2R);
  17885. /* Select PLL2 input reference frequency range: VCI */
  17886. __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
  17887. 800807a: 6ae3 ldr r3, [r4, #44] @ 0x2c
  17888. 800807c: 6972 ldr r2, [r6, #20]
  17889. 800807e: f023 03c0 bic.w r3, r3, #192 @ 0xc0
  17890. 8008082: 4313 orrs r3, r2
  17891. 8008084: 62e3 str r3, [r4, #44] @ 0x2c
  17892. /* Select PLL2 output frequency range : VCO */
  17893. __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
  17894. 8008086: 6ae2 ldr r2, [r4, #44] @ 0x2c
  17895. 8008088: 69b3 ldr r3, [r6, #24]
  17896. 800808a: f022 0220 bic.w r2, r2, #32
  17897. 800808e: 431a orrs r2, r3
  17898. /* Disable PLL2FRACN . */
  17899. __HAL_RCC_PLL2FRACN_DISABLE();
  17900. /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
  17901. __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
  17902. 8008090: 4b19 ldr r3, [pc, #100] @ (80080f8 <RCCEx_PLL2_Config.part.0+0xe0>)
  17903. __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
  17904. 8008092: 62e2 str r2, [r4, #44] @ 0x2c
  17905. __HAL_RCC_PLL2FRACN_DISABLE();
  17906. 8008094: 6ae2 ldr r2, [r4, #44] @ 0x2c
  17907. 8008096: f022 0210 bic.w r2, r2, #16
  17908. 800809a: 62e2 str r2, [r4, #44] @ 0x2c
  17909. __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
  17910. 800809c: 6be1 ldr r1, [r4, #60] @ 0x3c
  17911. 800809e: 69f2 ldr r2, [r6, #28]
  17912. 80080a0: 400b ands r3, r1
  17913. 80080a2: ea43 03c2 orr.w r3, r3, r2, lsl #3
  17914. 80080a6: 63e3 str r3, [r4, #60] @ 0x3c
  17915. /* Enable PLL2FRACN . */
  17916. __HAL_RCC_PLL2FRACN_ENABLE();
  17917. 80080a8: 6ae3 ldr r3, [r4, #44] @ 0x2c
  17918. 80080aa: f043 0310 orr.w r3, r3, #16
  17919. 80080ae: 62e3 str r3, [r4, #44] @ 0x2c
  17920. /* Enable the PLL2 clock output */
  17921. if (Divider == DIVIDER_P_UPDATE)
  17922. {
  17923. __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
  17924. 80080b0: 6ae3 ldr r3, [r4, #44] @ 0x2c
  17925. if (Divider == DIVIDER_P_UPDATE)
  17926. 80080b2: b1df cbz r7, 80080ec <RCCEx_PLL2_Config.part.0+0xd4>
  17927. }
  17928. else if (Divider == DIVIDER_Q_UPDATE)
  17929. 80080b4: 2f01 cmp r7, #1
  17930. {
  17931. __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
  17932. 80080b6: bf0c ite eq
  17933. 80080b8: f443 1380 orreq.w r3, r3, #1048576 @ 0x100000
  17934. }
  17935. else
  17936. {
  17937. __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
  17938. 80080bc: f443 1300 orrne.w r3, r3, #2097152 @ 0x200000
  17939. 80080c0: 62e3 str r3, [r4, #44] @ 0x2c
  17940. }
  17941. /* Enable PLL2. */
  17942. __HAL_RCC_PLL2_ENABLE();
  17943. 80080c2: 4c0c ldr r4, [pc, #48] @ (80080f4 <RCCEx_PLL2_Config.part.0+0xdc>)
  17944. 80080c4: 6823 ldr r3, [r4, #0]
  17945. 80080c6: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
  17946. 80080ca: 6023 str r3, [r4, #0]
  17947. /* Get Start Tick*/
  17948. tickstart = HAL_GetTick();
  17949. 80080cc: f7fb ff80 bl 8003fd0 <HAL_GetTick>
  17950. 80080d0: 4605 mov r5, r0
  17951. /* Wait till PLL2 is ready */
  17952. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
  17953. 80080d2: e004 b.n 80080de <RCCEx_PLL2_Config.part.0+0xc6>
  17954. {
  17955. if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
  17956. 80080d4: f7fb ff7c bl 8003fd0 <HAL_GetTick>
  17957. 80080d8: 1b40 subs r0, r0, r5
  17958. 80080da: 2802 cmp r0, #2
  17959. 80080dc: d804 bhi.n 80080e8 <RCCEx_PLL2_Config.part.0+0xd0>
  17960. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
  17961. 80080de: 6823 ldr r3, [r4, #0]
  17962. 80080e0: 011b lsls r3, r3, #4
  17963. 80080e2: d5f7 bpl.n 80080d4 <RCCEx_PLL2_Config.part.0+0xbc>
  17964. }
  17965. }
  17966. return status;
  17967. 80080e4: 2000 movs r0, #0
  17968. }
  17969. 80080e6: bdf8 pop {r3, r4, r5, r6, r7, pc}
  17970. return HAL_TIMEOUT;
  17971. 80080e8: 2003 movs r0, #3
  17972. }
  17973. 80080ea: bdf8 pop {r3, r4, r5, r6, r7, pc}
  17974. __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
  17975. 80080ec: f443 2300 orr.w r3, r3, #524288 @ 0x80000
  17976. 80080f0: 62e3 str r3, [r4, #44] @ 0x2c
  17977. 80080f2: e7e6 b.n 80080c2 <RCCEx_PLL2_Config.part.0+0xaa>
  17978. 80080f4: 58024400 .word 0x58024400
  17979. 80080f8: ffff0007 .word 0xffff0007
  17980. 080080fc <RCCEx_PLL3_Config.part.0>:
  17981. * @param Divider divider parameter to be updated
  17982. * @note PLL3 is temporary disabled to apply new parameters
  17983. *
  17984. * @retval HAL status
  17985. */
  17986. static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
  17987. 80080fc: b5f8 push {r3, r4, r5, r6, r7, lr}
  17988. else
  17989. {
  17990. /* Disable PLL3. */
  17991. __HAL_RCC_PLL3_DISABLE();
  17992. 80080fe: 4c36 ldr r4, [pc, #216] @ (80081d8 <RCCEx_PLL3_Config.part.0+0xdc>)
  17993. static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
  17994. 8008100: 4606 mov r6, r0
  17995. 8008102: 460f mov r7, r1
  17996. __HAL_RCC_PLL3_DISABLE();
  17997. 8008104: 6823 ldr r3, [r4, #0]
  17998. 8008106: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
  17999. 800810a: 6023 str r3, [r4, #0]
  18000. /* Get Start Tick*/
  18001. tickstart = HAL_GetTick();
  18002. 800810c: f7fb ff60 bl 8003fd0 <HAL_GetTick>
  18003. 8008110: 4605 mov r5, r0
  18004. /* Wait till PLL3 is ready */
  18005. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
  18006. 8008112: e004 b.n 800811e <RCCEx_PLL3_Config.part.0+0x22>
  18007. {
  18008. if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
  18009. 8008114: f7fb ff5c bl 8003fd0 <HAL_GetTick>
  18010. 8008118: 1b40 subs r0, r0, r5
  18011. 800811a: 2802 cmp r0, #2
  18012. 800811c: d856 bhi.n 80081cc <RCCEx_PLL3_Config.part.0+0xd0>
  18013. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
  18014. 800811e: 6823 ldr r3, [r4, #0]
  18015. 8008120: 009a lsls r2, r3, #2
  18016. 8008122: d4f7 bmi.n 8008114 <RCCEx_PLL3_Config.part.0+0x18>
  18017. return HAL_TIMEOUT;
  18018. }
  18019. }
  18020. /* Configure the PLL3 multiplication and division factors. */
  18021. __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
  18022. 8008124: 6aa3 ldr r3, [r4, #40] @ 0x28
  18023. 8008126: 6832 ldr r2, [r6, #0]
  18024. 8008128: f023 737c bic.w r3, r3, #66060288 @ 0x3f00000
  18025. 800812c: ea43 5302 orr.w r3, r3, r2, lsl #20
  18026. 8008130: 62a3 str r3, [r4, #40] @ 0x28
  18027. 8008132: e9d6 3202 ldrd r3, r2, [r6, #8]
  18028. 8008136: 3b01 subs r3, #1
  18029. 8008138: 3a01 subs r2, #1
  18030. 800813a: 025b lsls r3, r3, #9
  18031. 800813c: 0412 lsls r2, r2, #16
  18032. 800813e: b29b uxth r3, r3
  18033. 8008140: f402 02fe and.w r2, r2, #8323072 @ 0x7f0000
  18034. 8008144: 4313 orrs r3, r2
  18035. 8008146: 6872 ldr r2, [r6, #4]
  18036. 8008148: 3a01 subs r2, #1
  18037. 800814a: f3c2 0208 ubfx r2, r2, #0, #9
  18038. 800814e: 4313 orrs r3, r2
  18039. 8008150: 6932 ldr r2, [r6, #16]
  18040. 8008152: 3a01 subs r2, #1
  18041. 8008154: 0612 lsls r2, r2, #24
  18042. 8008156: f002 42fe and.w r2, r2, #2130706432 @ 0x7f000000
  18043. 800815a: 4313 orrs r3, r2
  18044. 800815c: 6423 str r3, [r4, #64] @ 0x40
  18045. pll3->PLL3P,
  18046. pll3->PLL3Q,
  18047. pll3->PLL3R);
  18048. /* Select PLL3 input reference frequency range: VCI */
  18049. __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
  18050. 800815e: 6ae3 ldr r3, [r4, #44] @ 0x2c
  18051. 8008160: 6972 ldr r2, [r6, #20]
  18052. 8008162: f423 6340 bic.w r3, r3, #3072 @ 0xc00
  18053. 8008166: 4313 orrs r3, r2
  18054. 8008168: 62e3 str r3, [r4, #44] @ 0x2c
  18055. /* Select PLL3 output frequency range : VCO */
  18056. __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
  18057. 800816a: 6ae2 ldr r2, [r4, #44] @ 0x2c
  18058. 800816c: 69b3 ldr r3, [r6, #24]
  18059. 800816e: f422 7200 bic.w r2, r2, #512 @ 0x200
  18060. 8008172: 431a orrs r2, r3
  18061. /* Disable PLL3FRACN . */
  18062. __HAL_RCC_PLL3FRACN_DISABLE();
  18063. /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
  18064. __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
  18065. 8008174: 4b19 ldr r3, [pc, #100] @ (80081dc <RCCEx_PLL3_Config.part.0+0xe0>)
  18066. __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
  18067. 8008176: 62e2 str r2, [r4, #44] @ 0x2c
  18068. __HAL_RCC_PLL3FRACN_DISABLE();
  18069. 8008178: 6ae2 ldr r2, [r4, #44] @ 0x2c
  18070. 800817a: f422 7280 bic.w r2, r2, #256 @ 0x100
  18071. 800817e: 62e2 str r2, [r4, #44] @ 0x2c
  18072. __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
  18073. 8008180: 6c61 ldr r1, [r4, #68] @ 0x44
  18074. 8008182: 69f2 ldr r2, [r6, #28]
  18075. 8008184: 400b ands r3, r1
  18076. 8008186: ea43 03c2 orr.w r3, r3, r2, lsl #3
  18077. 800818a: 6463 str r3, [r4, #68] @ 0x44
  18078. /* Enable PLL3FRACN . */
  18079. __HAL_RCC_PLL3FRACN_ENABLE();
  18080. 800818c: 6ae3 ldr r3, [r4, #44] @ 0x2c
  18081. 800818e: f443 7380 orr.w r3, r3, #256 @ 0x100
  18082. 8008192: 62e3 str r3, [r4, #44] @ 0x2c
  18083. /* Enable the PLL3 clock output */
  18084. if (Divider == DIVIDER_P_UPDATE)
  18085. {
  18086. __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
  18087. 8008194: 6ae3 ldr r3, [r4, #44] @ 0x2c
  18088. if (Divider == DIVIDER_P_UPDATE)
  18089. 8008196: b1df cbz r7, 80081d0 <RCCEx_PLL3_Config.part.0+0xd4>
  18090. }
  18091. else if (Divider == DIVIDER_Q_UPDATE)
  18092. 8008198: 2f01 cmp r7, #1
  18093. {
  18094. __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
  18095. 800819a: bf0c ite eq
  18096. 800819c: f443 0300 orreq.w r3, r3, #8388608 @ 0x800000
  18097. }
  18098. else
  18099. {
  18100. __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
  18101. 80081a0: f043 7380 orrne.w r3, r3, #16777216 @ 0x1000000
  18102. 80081a4: 62e3 str r3, [r4, #44] @ 0x2c
  18103. }
  18104. /* Enable PLL3. */
  18105. __HAL_RCC_PLL3_ENABLE();
  18106. 80081a6: 4c0c ldr r4, [pc, #48] @ (80081d8 <RCCEx_PLL3_Config.part.0+0xdc>)
  18107. 80081a8: 6823 ldr r3, [r4, #0]
  18108. 80081aa: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
  18109. 80081ae: 6023 str r3, [r4, #0]
  18110. /* Get Start Tick*/
  18111. tickstart = HAL_GetTick();
  18112. 80081b0: f7fb ff0e bl 8003fd0 <HAL_GetTick>
  18113. 80081b4: 4605 mov r5, r0
  18114. /* Wait till PLL3 is ready */
  18115. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
  18116. 80081b6: e004 b.n 80081c2 <RCCEx_PLL3_Config.part.0+0xc6>
  18117. {
  18118. if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
  18119. 80081b8: f7fb ff0a bl 8003fd0 <HAL_GetTick>
  18120. 80081bc: 1b40 subs r0, r0, r5
  18121. 80081be: 2802 cmp r0, #2
  18122. 80081c0: d804 bhi.n 80081cc <RCCEx_PLL3_Config.part.0+0xd0>
  18123. while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
  18124. 80081c2: 6823 ldr r3, [r4, #0]
  18125. 80081c4: 009b lsls r3, r3, #2
  18126. 80081c6: d5f7 bpl.n 80081b8 <RCCEx_PLL3_Config.part.0+0xbc>
  18127. }
  18128. }
  18129. return status;
  18130. 80081c8: 2000 movs r0, #0
  18131. }
  18132. 80081ca: bdf8 pop {r3, r4, r5, r6, r7, pc}
  18133. return HAL_TIMEOUT;
  18134. 80081cc: 2003 movs r0, #3
  18135. }
  18136. 80081ce: bdf8 pop {r3, r4, r5, r6, r7, pc}
  18137. __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
  18138. 80081d0: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
  18139. 80081d4: 62e3 str r3, [r4, #44] @ 0x2c
  18140. 80081d6: e7e6 b.n 80081a6 <RCCEx_PLL3_Config.part.0+0xaa>
  18141. 80081d8: 58024400 .word 0x58024400
  18142. 80081dc: ffff0007 .word 0xffff0007
  18143. 080081e0 <HAL_RCCEx_PeriphCLKConfig>:
  18144. {
  18145. 80081e0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  18146. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
  18147. 80081e4: e9d0 3200 ldrd r3, r2, [r0]
  18148. {
  18149. 80081e8: 4604 mov r4, r0
  18150. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
  18151. 80081ea: 011d lsls r5, r3, #4
  18152. 80081ec: f003 6600 and.w r6, r3, #134217728 @ 0x8000000
  18153. 80081f0: d525 bpl.n 800823e <HAL_RCCEx_PeriphCLKConfig+0x5e>
  18154. switch (PeriphClkInit->SpdifrxClockSelection)
  18155. 80081f2: 6e81 ldr r1, [r0, #104] @ 0x68
  18156. 80081f4: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
  18157. 80081f8: f000 8652 beq.w 8008ea0 <HAL_RCCEx_PeriphCLKConfig+0xcc0>
  18158. 80081fc: d814 bhi.n 8008228 <HAL_RCCEx_PeriphCLKConfig+0x48>
  18159. 80081fe: 2900 cmp r1, #0
  18160. 8008200: f000 86ee beq.w 8008fe0 <HAL_RCCEx_PeriphCLKConfig+0xe00>
  18161. 8008204: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
  18162. 8008208: f040 8456 bne.w 8008ab8 <HAL_RCCEx_PeriphCLKConfig+0x8d8>
  18163. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18164. 800820c: 49ad ldr r1, [pc, #692] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18165. 800820e: 6a89 ldr r1, [r1, #40] @ 0x28
  18166. 8008210: f001 0103 and.w r1, r1, #3
  18167. 8008214: 2903 cmp r1, #3
  18168. 8008216: f000 844f beq.w 8008ab8 <HAL_RCCEx_PeriphCLKConfig+0x8d8>
  18169. 800821a: 2102 movs r1, #2
  18170. 800821c: 3008 adds r0, #8
  18171. 800821e: f7ff fefb bl 8008018 <RCCEx_PLL2_Config.part.0>
  18172. 8008222: 4606 mov r6, r0
  18173. break;
  18174. 8008224: f000 be48 b.w 8008eb8 <HAL_RCCEx_PeriphCLKConfig+0xcd8>
  18175. switch (PeriphClkInit->SpdifrxClockSelection)
  18176. 8008228: f5b1 1f40 cmp.w r1, #3145728 @ 0x300000
  18177. 800822c: f040 8444 bne.w 8008ab8 <HAL_RCCEx_PeriphCLKConfig+0x8d8>
  18178. __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
  18179. 8008230: 4da4 ldr r5, [pc, #656] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18180. HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
  18181. 8008232: 2600 movs r6, #0
  18182. __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
  18183. 8008234: 6d28 ldr r0, [r5, #80] @ 0x50
  18184. 8008236: f420 1040 bic.w r0, r0, #3145728 @ 0x300000
  18185. 800823a: 4301 orrs r1, r0
  18186. 800823c: 6529 str r1, [r5, #80] @ 0x50
  18187. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
  18188. 800823e: 05d8 lsls r0, r3, #23
  18189. 8008240: d50a bpl.n 8008258 <HAL_RCCEx_PeriphCLKConfig+0x78>
  18190. switch (PeriphClkInit->Sai1ClockSelection)
  18191. 8008242: 6da1 ldr r1, [r4, #88] @ 0x58
  18192. 8008244: 2904 cmp r1, #4
  18193. 8008246: d806 bhi.n 8008256 <HAL_RCCEx_PeriphCLKConfig+0x76>
  18194. 8008248: e8df f011 tbh [pc, r1, lsl #1]
  18195. 800824c: 06680484 .word 0x06680484
  18196. 8008250: 0489067d .word 0x0489067d
  18197. 8008254: 0489 .short 0x0489
  18198. 8008256: 2601 movs r6, #1
  18199. 8008258: 4635 mov r5, r6
  18200. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
  18201. 800825a: 0599 lsls r1, r3, #22
  18202. 800825c: d524 bpl.n 80082a8 <HAL_RCCEx_PeriphCLKConfig+0xc8>
  18203. switch (PeriphClkInit->Sai23ClockSelection)
  18204. 800825e: 6de1 ldr r1, [r4, #92] @ 0x5c
  18205. 8008260: 2980 cmp r1, #128 @ 0x80
  18206. 8008262: f000 8647 beq.w 8008ef4 <HAL_RCCEx_PeriphCLKConfig+0xd14>
  18207. 8008266: f200 8122 bhi.w 80084ae <HAL_RCCEx_PeriphCLKConfig+0x2ce>
  18208. 800826a: 2900 cmp r1, #0
  18209. 800826c: f000 8484 beq.w 8008b78 <HAL_RCCEx_PeriphCLKConfig+0x998>
  18210. 8008270: 2940 cmp r1, #64 @ 0x40
  18211. 8008272: f040 8123 bne.w 80084bc <HAL_RCCEx_PeriphCLKConfig+0x2dc>
  18212. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18213. 8008276: 4993 ldr r1, [pc, #588] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18214. 8008278: 6a89 ldr r1, [r1, #40] @ 0x28
  18215. 800827a: f001 0103 and.w r1, r1, #3
  18216. 800827e: 2903 cmp r1, #3
  18217. 8008280: f000 811c beq.w 80084bc <HAL_RCCEx_PeriphCLKConfig+0x2dc>
  18218. 8008284: 2100 movs r1, #0
  18219. 8008286: f104 0008 add.w r0, r4, #8
  18220. 800828a: f7ff fec5 bl 8008018 <RCCEx_PLL2_Config.part.0>
  18221. 800828e: 4605 mov r5, r0
  18222. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
  18223. 8008290: e9d4 3200 ldrd r3, r2, [r4]
  18224. if (ret == HAL_OK)
  18225. 8008294: 2d00 cmp r5, #0
  18226. 8008296: f040 850f bne.w 8008cb8 <HAL_RCCEx_PeriphCLKConfig+0xad8>
  18227. __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
  18228. 800829a: 4f8a ldr r7, [pc, #552] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18229. 800829c: 6de0 ldr r0, [r4, #92] @ 0x5c
  18230. 800829e: 6d39 ldr r1, [r7, #80] @ 0x50
  18231. 80082a0: f421 71e0 bic.w r1, r1, #448 @ 0x1c0
  18232. 80082a4: 4301 orrs r1, r0
  18233. 80082a6: 6539 str r1, [r7, #80] @ 0x50
  18234. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
  18235. 80082a8: 055f lsls r7, r3, #21
  18236. 80082aa: d528 bpl.n 80082fe <HAL_RCCEx_PeriphCLKConfig+0x11e>
  18237. switch (PeriphClkInit->Sai4AClockSelection)
  18238. 80082ac: f8d4 10a8 ldr.w r1, [r4, #168] @ 0xa8
  18239. 80082b0: f5b1 0f80 cmp.w r1, #4194304 @ 0x400000
  18240. 80082b4: f000 85e0 beq.w 8008e78 <HAL_RCCEx_PeriphCLKConfig+0xc98>
  18241. 80082b8: f200 8106 bhi.w 80084c8 <HAL_RCCEx_PeriphCLKConfig+0x2e8>
  18242. 80082bc: 2900 cmp r1, #0
  18243. 80082be: f000 8465 beq.w 8008b8c <HAL_RCCEx_PeriphCLKConfig+0x9ac>
  18244. 80082c2: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
  18245. 80082c6: f040 8107 bne.w 80084d8 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
  18246. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18247. 80082ca: 497e ldr r1, [pc, #504] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18248. 80082cc: 6a89 ldr r1, [r1, #40] @ 0x28
  18249. 80082ce: f001 0103 and.w r1, r1, #3
  18250. 80082d2: 2903 cmp r1, #3
  18251. 80082d4: f000 8100 beq.w 80084d8 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
  18252. 80082d8: 2100 movs r1, #0
  18253. 80082da: f104 0008 add.w r0, r4, #8
  18254. 80082de: f7ff fe9b bl 8008018 <RCCEx_PLL2_Config.part.0>
  18255. 80082e2: 4605 mov r5, r0
  18256. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
  18257. 80082e4: e9d4 3200 ldrd r3, r2, [r4]
  18258. if (ret == HAL_OK)
  18259. 80082e8: 2d00 cmp r5, #0
  18260. 80082ea: f040 84e8 bne.w 8008cbe <HAL_RCCEx_PeriphCLKConfig+0xade>
  18261. __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
  18262. 80082ee: 4f75 ldr r7, [pc, #468] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18263. 80082f0: f8d4 00a8 ldr.w r0, [r4, #168] @ 0xa8
  18264. 80082f4: 6db9 ldr r1, [r7, #88] @ 0x58
  18265. 80082f6: f421 0160 bic.w r1, r1, #14680064 @ 0xe00000
  18266. 80082fa: 4301 orrs r1, r0
  18267. 80082fc: 65b9 str r1, [r7, #88] @ 0x58
  18268. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
  18269. 80082fe: 0518 lsls r0, r3, #20
  18270. 8008300: d528 bpl.n 8008354 <HAL_RCCEx_PeriphCLKConfig+0x174>
  18271. switch (PeriphClkInit->Sai4BClockSelection)
  18272. 8008302: f8d4 10ac ldr.w r1, [r4, #172] @ 0xac
  18273. 8008306: f1b1 7f00 cmp.w r1, #33554432 @ 0x2000000
  18274. 800830a: f000 85df beq.w 8008ecc <HAL_RCCEx_PeriphCLKConfig+0xcec>
  18275. 800830e: f200 80e6 bhi.w 80084de <HAL_RCCEx_PeriphCLKConfig+0x2fe>
  18276. 8008312: 2900 cmp r1, #0
  18277. 8008314: f000 8444 beq.w 8008ba0 <HAL_RCCEx_PeriphCLKConfig+0x9c0>
  18278. 8008318: f1b1 7f80 cmp.w r1, #16777216 @ 0x1000000
  18279. 800831c: f040 80e7 bne.w 80084ee <HAL_RCCEx_PeriphCLKConfig+0x30e>
  18280. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18281. 8008320: 4968 ldr r1, [pc, #416] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18282. 8008322: 6a89 ldr r1, [r1, #40] @ 0x28
  18283. 8008324: f001 0103 and.w r1, r1, #3
  18284. 8008328: 2903 cmp r1, #3
  18285. 800832a: f000 80e0 beq.w 80084ee <HAL_RCCEx_PeriphCLKConfig+0x30e>
  18286. 800832e: 2100 movs r1, #0
  18287. 8008330: f104 0008 add.w r0, r4, #8
  18288. 8008334: f7ff fe70 bl 8008018 <RCCEx_PLL2_Config.part.0>
  18289. 8008338: 4605 mov r5, r0
  18290. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
  18291. 800833a: e9d4 3200 ldrd r3, r2, [r4]
  18292. if (ret == HAL_OK)
  18293. 800833e: 2d00 cmp r5, #0
  18294. 8008340: f040 84c0 bne.w 8008cc4 <HAL_RCCEx_PeriphCLKConfig+0xae4>
  18295. __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
  18296. 8008344: 4f5f ldr r7, [pc, #380] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18297. 8008346: f8d4 00ac ldr.w r0, [r4, #172] @ 0xac
  18298. 800834a: 6db9 ldr r1, [r7, #88] @ 0x58
  18299. 800834c: f021 61e0 bic.w r1, r1, #117440512 @ 0x7000000
  18300. 8008350: 4301 orrs r1, r0
  18301. 8008352: 65b9 str r1, [r7, #88] @ 0x58
  18302. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
  18303. 8008354: 0199 lsls r1, r3, #6
  18304. 8008356: d518 bpl.n 800838a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
  18305. switch (PeriphClkInit->QspiClockSelection)
  18306. 8008358: 6ce1 ldr r1, [r4, #76] @ 0x4c
  18307. 800835a: 2920 cmp r1, #32
  18308. 800835c: f000 84e1 beq.w 8008d22 <HAL_RCCEx_PeriphCLKConfig+0xb42>
  18309. 8008360: f200 80c8 bhi.w 80084f4 <HAL_RCCEx_PeriphCLKConfig+0x314>
  18310. 8008364: b139 cbz r1, 8008376 <HAL_RCCEx_PeriphCLKConfig+0x196>
  18311. 8008366: 2910 cmp r1, #16
  18312. 8008368: f040 80c7 bne.w 80084fa <HAL_RCCEx_PeriphCLKConfig+0x31a>
  18313. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  18314. 800836c: 4855 ldr r0, [pc, #340] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18315. 800836e: 6ac1 ldr r1, [r0, #44] @ 0x2c
  18316. 8008370: f441 3100 orr.w r1, r1, #131072 @ 0x20000
  18317. 8008374: 62c1 str r1, [r0, #44] @ 0x2c
  18318. if (ret == HAL_OK)
  18319. 8008376: 2d00 cmp r5, #0
  18320. 8008378: f040 849b bne.w 8008cb2 <HAL_RCCEx_PeriphCLKConfig+0xad2>
  18321. __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
  18322. 800837c: 4f51 ldr r7, [pc, #324] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18323. 800837e: 6ce0 ldr r0, [r4, #76] @ 0x4c
  18324. 8008380: 6cf9 ldr r1, [r7, #76] @ 0x4c
  18325. 8008382: f021 0130 bic.w r1, r1, #48 @ 0x30
  18326. 8008386: 4301 orrs r1, r0
  18327. 8008388: 64f9 str r1, [r7, #76] @ 0x4c
  18328. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
  18329. 800838a: 04df lsls r7, r3, #19
  18330. 800838c: d526 bpl.n 80083dc <HAL_RCCEx_PeriphCLKConfig+0x1fc>
  18331. switch (PeriphClkInit->Spi123ClockSelection)
  18332. 800838e: 6e21 ldr r1, [r4, #96] @ 0x60
  18333. 8008390: f5b1 5f00 cmp.w r1, #8192 @ 0x2000
  18334. 8008394: f000 855c beq.w 8008e50 <HAL_RCCEx_PeriphCLKConfig+0xc70>
  18335. 8008398: f200 80b2 bhi.w 8008500 <HAL_RCCEx_PeriphCLKConfig+0x320>
  18336. 800839c: 2900 cmp r1, #0
  18337. 800839e: f000 83d0 beq.w 8008b42 <HAL_RCCEx_PeriphCLKConfig+0x962>
  18338. 80083a2: f5b1 5f80 cmp.w r1, #4096 @ 0x1000
  18339. 80083a6: f040 80b3 bne.w 8008510 <HAL_RCCEx_PeriphCLKConfig+0x330>
  18340. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18341. 80083aa: 4946 ldr r1, [pc, #280] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18342. 80083ac: 6a89 ldr r1, [r1, #40] @ 0x28
  18343. 80083ae: f001 0103 and.w r1, r1, #3
  18344. 80083b2: 2903 cmp r1, #3
  18345. 80083b4: f000 80ac beq.w 8008510 <HAL_RCCEx_PeriphCLKConfig+0x330>
  18346. 80083b8: 2100 movs r1, #0
  18347. 80083ba: f104 0008 add.w r0, r4, #8
  18348. 80083be: f7ff fe2b bl 8008018 <RCCEx_PLL2_Config.part.0>
  18349. 80083c2: 4605 mov r5, r0
  18350. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
  18351. 80083c4: e9d4 3200 ldrd r3, r2, [r4]
  18352. if (ret == HAL_OK)
  18353. 80083c8: 2d00 cmp r5, #0
  18354. 80083ca: f040 847e bne.w 8008cca <HAL_RCCEx_PeriphCLKConfig+0xaea>
  18355. __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
  18356. 80083ce: 4f3d ldr r7, [pc, #244] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18357. 80083d0: 6e20 ldr r0, [r4, #96] @ 0x60
  18358. 80083d2: 6d39 ldr r1, [r7, #80] @ 0x50
  18359. 80083d4: f421 41e0 bic.w r1, r1, #28672 @ 0x7000
  18360. 80083d8: 4301 orrs r1, r0
  18361. 80083da: 6539 str r1, [r7, #80] @ 0x50
  18362. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
  18363. 80083dc: 0498 lsls r0, r3, #18
  18364. 80083de: d524 bpl.n 800842a <HAL_RCCEx_PeriphCLKConfig+0x24a>
  18365. switch (PeriphClkInit->Spi45ClockSelection)
  18366. 80083e0: 6e61 ldr r1, [r4, #100] @ 0x64
  18367. 80083e2: f5b1 3f00 cmp.w r1, #131072 @ 0x20000
  18368. 80083e6: f000 850c beq.w 8008e02 <HAL_RCCEx_PeriphCLKConfig+0xc22>
  18369. 80083ea: f200 8094 bhi.w 8008516 <HAL_RCCEx_PeriphCLKConfig+0x336>
  18370. 80083ee: b191 cbz r1, 8008416 <HAL_RCCEx_PeriphCLKConfig+0x236>
  18371. 80083f0: f5b1 3f80 cmp.w r1, #65536 @ 0x10000
  18372. 80083f4: f040 8099 bne.w 800852a <HAL_RCCEx_PeriphCLKConfig+0x34a>
  18373. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18374. 80083f8: 4932 ldr r1, [pc, #200] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18375. 80083fa: 6a89 ldr r1, [r1, #40] @ 0x28
  18376. 80083fc: f001 0103 and.w r1, r1, #3
  18377. 8008400: 2903 cmp r1, #3
  18378. 8008402: f000 8092 beq.w 800852a <HAL_RCCEx_PeriphCLKConfig+0x34a>
  18379. 8008406: 2101 movs r1, #1
  18380. 8008408: f104 0008 add.w r0, r4, #8
  18381. 800840c: f7ff fe04 bl 8008018 <RCCEx_PLL2_Config.part.0>
  18382. 8008410: 4605 mov r5, r0
  18383. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
  18384. 8008412: e9d4 3200 ldrd r3, r2, [r4]
  18385. if (ret == HAL_OK)
  18386. 8008416: 2d00 cmp r5, #0
  18387. 8008418: f040 846c bne.w 8008cf4 <HAL_RCCEx_PeriphCLKConfig+0xb14>
  18388. __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
  18389. 800841c: 4f29 ldr r7, [pc, #164] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18390. 800841e: 6e60 ldr r0, [r4, #100] @ 0x64
  18391. 8008420: 6d39 ldr r1, [r7, #80] @ 0x50
  18392. 8008422: f421 21e0 bic.w r1, r1, #458752 @ 0x70000
  18393. 8008426: 4301 orrs r1, r0
  18394. 8008428: 6539 str r1, [r7, #80] @ 0x50
  18395. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
  18396. 800842a: 0459 lsls r1, r3, #17
  18397. 800842c: d523 bpl.n 8008476 <HAL_RCCEx_PeriphCLKConfig+0x296>
  18398. switch (PeriphClkInit->Spi6ClockSelection)
  18399. 800842e: f8d4 10b0 ldr.w r1, [r4, #176] @ 0xb0
  18400. 8008432: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000
  18401. 8008436: f000 84ac beq.w 8008d92 <HAL_RCCEx_PeriphCLKConfig+0xbb2>
  18402. 800843a: d879 bhi.n 8008530 <HAL_RCCEx_PeriphCLKConfig+0x350>
  18403. 800843c: b181 cbz r1, 8008460 <HAL_RCCEx_PeriphCLKConfig+0x280>
  18404. 800843e: f1b1 5f80 cmp.w r1, #268435456 @ 0x10000000
  18405. 8008442: d17d bne.n 8008540 <HAL_RCCEx_PeriphCLKConfig+0x360>
  18406. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18407. 8008444: 491f ldr r1, [pc, #124] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18408. 8008446: 6a89 ldr r1, [r1, #40] @ 0x28
  18409. 8008448: f001 0103 and.w r1, r1, #3
  18410. 800844c: 2903 cmp r1, #3
  18411. 800844e: d077 beq.n 8008540 <HAL_RCCEx_PeriphCLKConfig+0x360>
  18412. 8008450: 2101 movs r1, #1
  18413. 8008452: f104 0008 add.w r0, r4, #8
  18414. 8008456: f7ff fddf bl 8008018 <RCCEx_PLL2_Config.part.0>
  18415. 800845a: 4605 mov r5, r0
  18416. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
  18417. 800845c: e9d4 3200 ldrd r3, r2, [r4]
  18418. if (ret == HAL_OK)
  18419. 8008460: 2d00 cmp r5, #0
  18420. 8008462: f040 8455 bne.w 8008d10 <HAL_RCCEx_PeriphCLKConfig+0xb30>
  18421. __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
  18422. 8008466: 4f17 ldr r7, [pc, #92] @ (80084c4 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
  18423. 8008468: f8d4 00b0 ldr.w r0, [r4, #176] @ 0xb0
  18424. 800846c: 6db9 ldr r1, [r7, #88] @ 0x58
  18425. 800846e: f021 41e0 bic.w r1, r1, #1879048192 @ 0x70000000
  18426. 8008472: 4301 orrs r1, r0
  18427. 8008474: 65b9 str r1, [r7, #88] @ 0x58
  18428. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
  18429. 8008476: 041f lsls r7, r3, #16
  18430. 8008478: d50d bpl.n 8008496 <HAL_RCCEx_PeriphCLKConfig+0x2b6>
  18431. switch (PeriphClkInit->FdcanClockSelection)
  18432. 800847a: 6f21 ldr r1, [r4, #112] @ 0x70
  18433. 800847c: f1b1 5f80 cmp.w r1, #268435456 @ 0x10000000
  18434. 8008480: f000 82d2 beq.w 8008a28 <HAL_RCCEx_PeriphCLKConfig+0x848>
  18435. 8008484: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000
  18436. 8008488: f000 83e4 beq.w 8008c54 <HAL_RCCEx_PeriphCLKConfig+0xa74>
  18437. 800848c: 2900 cmp r1, #0
  18438. 800848e: f000 82d0 beq.w 8008a32 <HAL_RCCEx_PeriphCLKConfig+0x852>
  18439. 8008492: 2601 movs r6, #1
  18440. 8008494: 4635 mov r5, r6
  18441. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
  18442. 8008496: 01d8 lsls r0, r3, #7
  18443. 8008498: d55e bpl.n 8008558 <HAL_RCCEx_PeriphCLKConfig+0x378>
  18444. switch (PeriphClkInit->FmcClockSelection)
  18445. 800849a: 6ca1 ldr r1, [r4, #72] @ 0x48
  18446. 800849c: 2903 cmp r1, #3
  18447. 800849e: f200 85c1 bhi.w 8009024 <HAL_RCCEx_PeriphCLKConfig+0xe44>
  18448. 80084a2: e8df f011 tbh [pc, r1, lsl #1]
  18449. 80084a6: 0055 .short 0x0055
  18450. 80084a8: 04630050 .word 0x04630050
  18451. 80084ac: 0055 .short 0x0055
  18452. switch (PeriphClkInit->Sai23ClockSelection)
  18453. 80084ae: 29c0 cmp r1, #192 @ 0xc0
  18454. 80084b0: f43f aef0 beq.w 8008294 <HAL_RCCEx_PeriphCLKConfig+0xb4>
  18455. 80084b4: f5b1 7f80 cmp.w r1, #256 @ 0x100
  18456. 80084b8: f43f aeec beq.w 8008294 <HAL_RCCEx_PeriphCLKConfig+0xb4>
  18457. 80084bc: 2601 movs r6, #1
  18458. 80084be: 4635 mov r5, r6
  18459. 80084c0: e6f2 b.n 80082a8 <HAL_RCCEx_PeriphCLKConfig+0xc8>
  18460. 80084c2: bf00 nop
  18461. 80084c4: 58024400 .word 0x58024400
  18462. switch (PeriphClkInit->Sai4AClockSelection)
  18463. 80084c8: f5b1 0fc0 cmp.w r1, #6291456 @ 0x600000
  18464. 80084cc: f43f af0c beq.w 80082e8 <HAL_RCCEx_PeriphCLKConfig+0x108>
  18465. 80084d0: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000
  18466. 80084d4: f43f af08 beq.w 80082e8 <HAL_RCCEx_PeriphCLKConfig+0x108>
  18467. 80084d8: 2601 movs r6, #1
  18468. 80084da: 4635 mov r5, r6
  18469. 80084dc: e70f b.n 80082fe <HAL_RCCEx_PeriphCLKConfig+0x11e>
  18470. switch (PeriphClkInit->Sai4BClockSelection)
  18471. 80084de: f1b1 7f40 cmp.w r1, #50331648 @ 0x3000000
  18472. 80084e2: f43f af2c beq.w 800833e <HAL_RCCEx_PeriphCLKConfig+0x15e>
  18473. 80084e6: f1b1 6f80 cmp.w r1, #67108864 @ 0x4000000
  18474. 80084ea: f43f af28 beq.w 800833e <HAL_RCCEx_PeriphCLKConfig+0x15e>
  18475. 80084ee: 2601 movs r6, #1
  18476. 80084f0: 4635 mov r5, r6
  18477. 80084f2: e72f b.n 8008354 <HAL_RCCEx_PeriphCLKConfig+0x174>
  18478. switch (PeriphClkInit->QspiClockSelection)
  18479. 80084f4: 2930 cmp r1, #48 @ 0x30
  18480. 80084f6: f43f af3e beq.w 8008376 <HAL_RCCEx_PeriphCLKConfig+0x196>
  18481. 80084fa: 2601 movs r6, #1
  18482. 80084fc: 4635 mov r5, r6
  18483. 80084fe: e744 b.n 800838a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
  18484. switch (PeriphClkInit->Spi123ClockSelection)
  18485. 8008500: f5b1 5f40 cmp.w r1, #12288 @ 0x3000
  18486. 8008504: f43f af60 beq.w 80083c8 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
  18487. 8008508: f5b1 4f80 cmp.w r1, #16384 @ 0x4000
  18488. 800850c: f43f af5c beq.w 80083c8 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
  18489. 8008510: 2601 movs r6, #1
  18490. 8008512: 4635 mov r5, r6
  18491. 8008514: e762 b.n 80083dc <HAL_RCCEx_PeriphCLKConfig+0x1fc>
  18492. switch (PeriphClkInit->Spi45ClockSelection)
  18493. 8008516: f421 3080 bic.w r0, r1, #65536 @ 0x10000
  18494. 800851a: f5b0 2f80 cmp.w r0, #262144 @ 0x40000
  18495. 800851e: f43f af7a beq.w 8008416 <HAL_RCCEx_PeriphCLKConfig+0x236>
  18496. 8008522: f5b1 3f40 cmp.w r1, #196608 @ 0x30000
  18497. 8008526: f43f af76 beq.w 8008416 <HAL_RCCEx_PeriphCLKConfig+0x236>
  18498. 800852a: 2601 movs r6, #1
  18499. 800852c: 4635 mov r5, r6
  18500. 800852e: e77c b.n 800842a <HAL_RCCEx_PeriphCLKConfig+0x24a>
  18501. switch (PeriphClkInit->Spi6ClockSelection)
  18502. 8008530: f021 5080 bic.w r0, r1, #268435456 @ 0x10000000
  18503. 8008534: f1b0 4f80 cmp.w r0, #1073741824 @ 0x40000000
  18504. 8008538: d092 beq.n 8008460 <HAL_RCCEx_PeriphCLKConfig+0x280>
  18505. 800853a: f1b1 5f40 cmp.w r1, #805306368 @ 0x30000000
  18506. 800853e: d08f beq.n 8008460 <HAL_RCCEx_PeriphCLKConfig+0x280>
  18507. 8008540: 2601 movs r6, #1
  18508. 8008542: 4635 mov r5, r6
  18509. 8008544: e797 b.n 8008476 <HAL_RCCEx_PeriphCLKConfig+0x296>
  18510. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  18511. 8008546: 4837 ldr r0, [pc, #220] @ (8008624 <HAL_RCCEx_PeriphCLKConfig+0x444>)
  18512. 8008548: 6ac1 ldr r1, [r0, #44] @ 0x2c
  18513. 800854a: f441 3100 orr.w r1, r1, #131072 @ 0x20000
  18514. 800854e: 62c1 str r1, [r0, #44] @ 0x2c
  18515. if (ret == HAL_OK)
  18516. 8008550: 2d00 cmp r5, #0
  18517. 8008552: f000 83a6 beq.w 8008ca2 <HAL_RCCEx_PeriphCLKConfig+0xac2>
  18518. 8008556: 462e mov r6, r5
  18519. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
  18520. 8008558: 0259 lsls r1, r3, #9
  18521. 800855a: f100 82b0 bmi.w 8008abe <HAL_RCCEx_PeriphCLKConfig+0x8de>
  18522. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
  18523. 800855e: 07d8 lsls r0, r3, #31
  18524. 8008560: d52f bpl.n 80085c2 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
  18525. switch (PeriphClkInit->Usart16ClockSelection)
  18526. 8008562: 6fe1 ldr r1, [r4, #124] @ 0x7c
  18527. 8008564: 2928 cmp r1, #40 @ 0x28
  18528. 8008566: d82a bhi.n 80085be <HAL_RCCEx_PeriphCLKConfig+0x3de>
  18529. 8008568: e8df f011 tbh [pc, r1, lsl #1]
  18530. 800856c: 0029029b .word 0x0029029b
  18531. 8008570: 00290029 .word 0x00290029
  18532. 8008574: 00290029 .word 0x00290029
  18533. 8008578: 00290029 .word 0x00290029
  18534. 800857c: 0029028c .word 0x0029028c
  18535. 8008580: 00290029 .word 0x00290029
  18536. 8008584: 00290029 .word 0x00290029
  18537. 8008588: 00290029 .word 0x00290029
  18538. 800858c: 00290521 .word 0x00290521
  18539. 8008590: 00290029 .word 0x00290029
  18540. 8008594: 00290029 .word 0x00290029
  18541. 8008598: 00290029 .word 0x00290029
  18542. 800859c: 0029029b .word 0x0029029b
  18543. 80085a0: 00290029 .word 0x00290029
  18544. 80085a4: 00290029 .word 0x00290029
  18545. 80085a8: 00290029 .word 0x00290029
  18546. 80085ac: 0029029b .word 0x0029029b
  18547. 80085b0: 00290029 .word 0x00290029
  18548. 80085b4: 00290029 .word 0x00290029
  18549. 80085b8: 00290029 .word 0x00290029
  18550. 80085bc: 029b .short 0x029b
  18551. 80085be: 2601 movs r6, #1
  18552. 80085c0: 4635 mov r5, r6
  18553. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
  18554. 80085c2: 0799 lsls r1, r3, #30
  18555. 80085c4: d51e bpl.n 8008604 <HAL_RCCEx_PeriphCLKConfig+0x424>
  18556. switch (PeriphClkInit->Usart234578ClockSelection)
  18557. 80085c6: 6fa1 ldr r1, [r4, #120] @ 0x78
  18558. 80085c8: 2905 cmp r1, #5
  18559. 80085ca: f200 8510 bhi.w 8008fee <HAL_RCCEx_PeriphCLKConfig+0xe0e>
  18560. 80085ce: e8df f011 tbh [pc, r1, lsl #1]
  18561. 80085d2: 0015 .short 0x0015
  18562. 80085d4: 04ca0006 .word 0x04ca0006
  18563. 80085d8: 00150015 .word 0x00150015
  18564. 80085dc: 0015 .short 0x0015
  18565. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18566. 80085de: 4911 ldr r1, [pc, #68] @ (8008624 <HAL_RCCEx_PeriphCLKConfig+0x444>)
  18567. 80085e0: 6a89 ldr r1, [r1, #40] @ 0x28
  18568. 80085e2: f001 0103 and.w r1, r1, #3
  18569. 80085e6: 2903 cmp r1, #3
  18570. 80085e8: f000 8501 beq.w 8008fee <HAL_RCCEx_PeriphCLKConfig+0xe0e>
  18571. 80085ec: 2101 movs r1, #1
  18572. 80085ee: f104 0008 add.w r0, r4, #8
  18573. 80085f2: f7ff fd11 bl 8008018 <RCCEx_PLL2_Config.part.0>
  18574. 80085f6: 4605 mov r5, r0
  18575. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
  18576. 80085f8: e9d4 3200 ldrd r3, r2, [r4]
  18577. if (ret == HAL_OK)
  18578. 80085fc: 2d00 cmp r5, #0
  18579. 80085fe: f000 836f beq.w 8008ce0 <HAL_RCCEx_PeriphCLKConfig+0xb00>
  18580. 8008602: 462e mov r6, r5
  18581. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
  18582. 8008604: 075f lsls r7, r3, #29
  18583. 8008606: d522 bpl.n 800864e <HAL_RCCEx_PeriphCLKConfig+0x46e>
  18584. switch (PeriphClkInit->Lpuart1ClockSelection)
  18585. 8008608: f8d4 1094 ldr.w r1, [r4, #148] @ 0x94
  18586. 800860c: 2905 cmp r1, #5
  18587. 800860e: f200 84f2 bhi.w 8008ff6 <HAL_RCCEx_PeriphCLKConfig+0xe16>
  18588. 8008612: e8df f011 tbh [pc, r1, lsl #1]
  18589. 8008616: 0018 .short 0x0018
  18590. 8008618: 04ba0009 .word 0x04ba0009
  18591. 800861c: 00180018 .word 0x00180018
  18592. 8008620: 0018 .short 0x0018
  18593. 8008622: bf00 nop
  18594. 8008624: 58024400 .word 0x58024400
  18595. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18596. 8008628: 49b0 ldr r1, [pc, #704] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18597. 800862a: 6a89 ldr r1, [r1, #40] @ 0x28
  18598. 800862c: f001 0103 and.w r1, r1, #3
  18599. 8008630: 2903 cmp r1, #3
  18600. 8008632: f000 84e0 beq.w 8008ff6 <HAL_RCCEx_PeriphCLKConfig+0xe16>
  18601. 8008636: 2101 movs r1, #1
  18602. 8008638: f104 0008 add.w r0, r4, #8
  18603. 800863c: f7ff fcec bl 8008018 <RCCEx_PLL2_Config.part.0>
  18604. 8008640: 4605 mov r5, r0
  18605. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
  18606. 8008642: e9d4 3200 ldrd r3, r2, [r4]
  18607. if (ret == HAL_OK)
  18608. 8008646: 2d00 cmp r5, #0
  18609. 8008648: f000 8357 beq.w 8008cfa <HAL_RCCEx_PeriphCLKConfig+0xb1a>
  18610. 800864c: 462e mov r6, r5
  18611. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
  18612. 800864e: 0698 lsls r0, r3, #26
  18613. 8008650: d526 bpl.n 80086a0 <HAL_RCCEx_PeriphCLKConfig+0x4c0>
  18614. switch (PeriphClkInit->Lptim1ClockSelection)
  18615. 8008652: f8d4 1090 ldr.w r1, [r4, #144] @ 0x90
  18616. 8008656: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000
  18617. 800865a: f000 83ad beq.w 8008db8 <HAL_RCCEx_PeriphCLKConfig+0xbd8>
  18618. 800865e: f200 8182 bhi.w 8008966 <HAL_RCCEx_PeriphCLKConfig+0x786>
  18619. 8008662: b191 cbz r1, 800868a <HAL_RCCEx_PeriphCLKConfig+0x4aa>
  18620. 8008664: f1b1 5f80 cmp.w r1, #268435456 @ 0x10000000
  18621. 8008668: f040 8187 bne.w 800897a <HAL_RCCEx_PeriphCLKConfig+0x79a>
  18622. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18623. 800866c: 499f ldr r1, [pc, #636] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18624. 800866e: 6a89 ldr r1, [r1, #40] @ 0x28
  18625. 8008670: f001 0103 and.w r1, r1, #3
  18626. 8008674: 2903 cmp r1, #3
  18627. 8008676: f000 8180 beq.w 800897a <HAL_RCCEx_PeriphCLKConfig+0x79a>
  18628. 800867a: 2100 movs r1, #0
  18629. 800867c: f104 0008 add.w r0, r4, #8
  18630. 8008680: f7ff fcca bl 8008018 <RCCEx_PLL2_Config.part.0>
  18631. 8008684: 4605 mov r5, r0
  18632. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
  18633. 8008686: e9d4 3200 ldrd r3, r2, [r4]
  18634. if (ret == HAL_OK)
  18635. 800868a: 2d00 cmp r5, #0
  18636. 800868c: f040 8345 bne.w 8008d1a <HAL_RCCEx_PeriphCLKConfig+0xb3a>
  18637. __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
  18638. 8008690: 4f96 ldr r7, [pc, #600] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18639. 8008692: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90
  18640. 8008696: 6d79 ldr r1, [r7, #84] @ 0x54
  18641. 8008698: f021 41e0 bic.w r1, r1, #1879048192 @ 0x70000000
  18642. 800869c: 4301 orrs r1, r0
  18643. 800869e: 6579 str r1, [r7, #84] @ 0x54
  18644. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
  18645. 80086a0: 0659 lsls r1, r3, #25
  18646. 80086a2: d526 bpl.n 80086f2 <HAL_RCCEx_PeriphCLKConfig+0x512>
  18647. switch (PeriphClkInit->Lptim2ClockSelection)
  18648. 80086a4: f8d4 109c ldr.w r1, [r4, #156] @ 0x9c
  18649. 80086a8: f5b1 6f00 cmp.w r1, #2048 @ 0x800
  18650. 80086ac: f000 8396 beq.w 8008ddc <HAL_RCCEx_PeriphCLKConfig+0xbfc>
  18651. 80086b0: f200 8166 bhi.w 8008980 <HAL_RCCEx_PeriphCLKConfig+0x7a0>
  18652. 80086b4: b191 cbz r1, 80086dc <HAL_RCCEx_PeriphCLKConfig+0x4fc>
  18653. 80086b6: f5b1 6f80 cmp.w r1, #1024 @ 0x400
  18654. 80086ba: f040 816b bne.w 8008994 <HAL_RCCEx_PeriphCLKConfig+0x7b4>
  18655. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18656. 80086be: 498b ldr r1, [pc, #556] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18657. 80086c0: 6a89 ldr r1, [r1, #40] @ 0x28
  18658. 80086c2: f001 0103 and.w r1, r1, #3
  18659. 80086c6: 2903 cmp r1, #3
  18660. 80086c8: f000 8164 beq.w 8008994 <HAL_RCCEx_PeriphCLKConfig+0x7b4>
  18661. 80086cc: 2100 movs r1, #0
  18662. 80086ce: f104 0008 add.w r0, r4, #8
  18663. 80086d2: f7ff fca1 bl 8008018 <RCCEx_PLL2_Config.part.0>
  18664. 80086d6: 4605 mov r5, r0
  18665. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
  18666. 80086d8: e9d4 3200 ldrd r3, r2, [r4]
  18667. if (ret == HAL_OK)
  18668. 80086dc: 2d00 cmp r5, #0
  18669. 80086de: f040 8307 bne.w 8008cf0 <HAL_RCCEx_PeriphCLKConfig+0xb10>
  18670. __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
  18671. 80086e2: 4f82 ldr r7, [pc, #520] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18672. 80086e4: f8d4 009c ldr.w r0, [r4, #156] @ 0x9c
  18673. 80086e8: 6db9 ldr r1, [r7, #88] @ 0x58
  18674. 80086ea: f421 51e0 bic.w r1, r1, #7168 @ 0x1c00
  18675. 80086ee: 4301 orrs r1, r0
  18676. 80086f0: 65b9 str r1, [r7, #88] @ 0x58
  18677. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
  18678. 80086f2: 061f lsls r7, r3, #24
  18679. 80086f4: d526 bpl.n 8008744 <HAL_RCCEx_PeriphCLKConfig+0x564>
  18680. switch (PeriphClkInit->Lptim345ClockSelection)
  18681. 80086f6: f8d4 10a0 ldr.w r1, [r4, #160] @ 0xa0
  18682. 80086fa: f5b1 4f80 cmp.w r1, #16384 @ 0x4000
  18683. 80086fe: f000 8394 beq.w 8008e2a <HAL_RCCEx_PeriphCLKConfig+0xc4a>
  18684. 8008702: f200 814a bhi.w 800899a <HAL_RCCEx_PeriphCLKConfig+0x7ba>
  18685. 8008706: b191 cbz r1, 800872e <HAL_RCCEx_PeriphCLKConfig+0x54e>
  18686. 8008708: f5b1 5f00 cmp.w r1, #8192 @ 0x2000
  18687. 800870c: f040 814f bne.w 80089ae <HAL_RCCEx_PeriphCLKConfig+0x7ce>
  18688. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18689. 8008710: 4976 ldr r1, [pc, #472] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18690. 8008712: 6a89 ldr r1, [r1, #40] @ 0x28
  18691. 8008714: f001 0103 and.w r1, r1, #3
  18692. 8008718: 2903 cmp r1, #3
  18693. 800871a: f000 8148 beq.w 80089ae <HAL_RCCEx_PeriphCLKConfig+0x7ce>
  18694. 800871e: 2100 movs r1, #0
  18695. 8008720: f104 0008 add.w r0, r4, #8
  18696. 8008724: f7ff fc78 bl 8008018 <RCCEx_PLL2_Config.part.0>
  18697. 8008728: 4605 mov r5, r0
  18698. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
  18699. 800872a: e9d4 3200 ldrd r3, r2, [r4]
  18700. if (ret == HAL_OK)
  18701. 800872e: 2d00 cmp r5, #0
  18702. 8008730: f040 82ec bne.w 8008d0c <HAL_RCCEx_PeriphCLKConfig+0xb2c>
  18703. __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
  18704. 8008734: 4f6d ldr r7, [pc, #436] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18705. 8008736: f8d4 00a0 ldr.w r0, [r4, #160] @ 0xa0
  18706. 800873a: 6db9 ldr r1, [r7, #88] @ 0x58
  18707. 800873c: f421 4160 bic.w r1, r1, #57344 @ 0xe000
  18708. 8008740: 4301 orrs r1, r0
  18709. 8008742: 65b9 str r1, [r7, #88] @ 0x58
  18710. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
  18711. 8008744: 0718 lsls r0, r3, #28
  18712. 8008746: d50b bpl.n 8008760 <HAL_RCCEx_PeriphCLKConfig+0x580>
  18713. if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3)
  18714. 8008748: f8d4 0084 ldr.w r0, [r4, #132] @ 0x84
  18715. 800874c: f5b0 5f80 cmp.w r0, #4096 @ 0x1000
  18716. 8008750: f000 8255 beq.w 8008bfe <HAL_RCCEx_PeriphCLKConfig+0xa1e>
  18717. __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
  18718. 8008754: 4f65 ldr r7, [pc, #404] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18719. 8008756: 6d79 ldr r1, [r7, #84] @ 0x54
  18720. 8008758: f421 5140 bic.w r1, r1, #12288 @ 0x3000
  18721. 800875c: 4301 orrs r1, r0
  18722. 800875e: 6579 str r1, [r7, #84] @ 0x54
  18723. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
  18724. 8008760: 06d9 lsls r1, r3, #27
  18725. 8008762: d50b bpl.n 800877c <HAL_RCCEx_PeriphCLKConfig+0x59c>
  18726. if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3)
  18727. 8008764: f8d4 0098 ldr.w r0, [r4, #152] @ 0x98
  18728. 8008768: f5b0 7f80 cmp.w r0, #256 @ 0x100
  18729. 800876c: f000 8233 beq.w 8008bd6 <HAL_RCCEx_PeriphCLKConfig+0x9f6>
  18730. __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
  18731. 8008770: 4f5e ldr r7, [pc, #376] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18732. 8008772: 6db9 ldr r1, [r7, #88] @ 0x58
  18733. 8008774: f421 7140 bic.w r1, r1, #768 @ 0x300
  18734. 8008778: 4301 orrs r1, r0
  18735. 800877a: 65b9 str r1, [r7, #88] @ 0x58
  18736. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
  18737. 800877c: 031f lsls r7, r3, #12
  18738. 800877e: d50e bpl.n 800879e <HAL_RCCEx_PeriphCLKConfig+0x5be>
  18739. switch (PeriphClkInit->AdcClockSelection)
  18740. 8008780: f8d4 10a4 ldr.w r1, [r4, #164] @ 0xa4
  18741. 8008784: f5b1 3f80 cmp.w r1, #65536 @ 0x10000
  18742. 8008788: f000 815e beq.w 8008a48 <HAL_RCCEx_PeriphCLKConfig+0x868>
  18743. 800878c: f5b1 3f00 cmp.w r1, #131072 @ 0x20000
  18744. 8008790: f000 8169 beq.w 8008a66 <HAL_RCCEx_PeriphCLKConfig+0x886>
  18745. 8008794: 2900 cmp r1, #0
  18746. 8008796: f000 826e beq.w 8008c76 <HAL_RCCEx_PeriphCLKConfig+0xa96>
  18747. 800879a: 2601 movs r6, #1
  18748. 800879c: 4635 mov r5, r6
  18749. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
  18750. 800879e: 0358 lsls r0, r3, #13
  18751. 80087a0: d50f bpl.n 80087c2 <HAL_RCCEx_PeriphCLKConfig+0x5e2>
  18752. switch (PeriphClkInit->UsbClockSelection)
  18753. 80087a2: f8d4 1088 ldr.w r1, [r4, #136] @ 0x88
  18754. 80087a6: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
  18755. 80087aa: f000 82cd beq.w 8008d48 <HAL_RCCEx_PeriphCLKConfig+0xb68>
  18756. 80087ae: f5b1 1f40 cmp.w r1, #3145728 @ 0x300000
  18757. 80087b2: f000 812d beq.w 8008a10 <HAL_RCCEx_PeriphCLKConfig+0x830>
  18758. 80087b6: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
  18759. 80087ba: f000 8124 beq.w 8008a06 <HAL_RCCEx_PeriphCLKConfig+0x826>
  18760. 80087be: 2601 movs r6, #1
  18761. 80087c0: 4635 mov r5, r6
  18762. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
  18763. 80087c2: 03d9 lsls r1, r3, #15
  18764. 80087c4: d520 bpl.n 8008808 <HAL_RCCEx_PeriphCLKConfig+0x628>
  18765. switch (PeriphClkInit->SdmmcClockSelection)
  18766. 80087c6: 6d21 ldr r1, [r4, #80] @ 0x50
  18767. 80087c8: 2900 cmp r1, #0
  18768. 80087ca: f000 8236 beq.w 8008c3a <HAL_RCCEx_PeriphCLKConfig+0xa5a>
  18769. 80087ce: f5b1 3f80 cmp.w r1, #65536 @ 0x10000
  18770. 80087d2: f040 8113 bne.w 80089fc <HAL_RCCEx_PeriphCLKConfig+0x81c>
  18771. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18772. 80087d6: 4945 ldr r1, [pc, #276] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18773. 80087d8: 6a89 ldr r1, [r1, #40] @ 0x28
  18774. 80087da: f001 0103 and.w r1, r1, #3
  18775. 80087de: 2903 cmp r1, #3
  18776. 80087e0: f000 810c beq.w 80089fc <HAL_RCCEx_PeriphCLKConfig+0x81c>
  18777. 80087e4: 2102 movs r1, #2
  18778. 80087e6: f104 0008 add.w r0, r4, #8
  18779. 80087ea: f7ff fc15 bl 8008018 <RCCEx_PLL2_Config.part.0>
  18780. 80087ee: 4605 mov r5, r0
  18781. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
  18782. 80087f0: e9d4 3200 ldrd r3, r2, [r4]
  18783. if (ret == HAL_OK)
  18784. 80087f4: 2d00 cmp r5, #0
  18785. 80087f6: f040 8228 bne.w 8008c4a <HAL_RCCEx_PeriphCLKConfig+0xa6a>
  18786. __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
  18787. 80087fa: 4f3c ldr r7, [pc, #240] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18788. 80087fc: 6d20 ldr r0, [r4, #80] @ 0x50
  18789. 80087fe: 6cf9 ldr r1, [r7, #76] @ 0x4c
  18790. 8008800: f421 3180 bic.w r1, r1, #65536 @ 0x10000
  18791. 8008804: 4301 orrs r1, r0
  18792. 8008806: 64f9 str r1, [r7, #76] @ 0x4c
  18793. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
  18794. 8008808: 039f lsls r7, r3, #14
  18795. 800880a: f140 80df bpl.w 80089cc <HAL_RCCEx_PeriphCLKConfig+0x7ec>
  18796. switch (PeriphClkInit->RngClockSelection)
  18797. 800880e: f8d4 1080 ldr.w r1, [r4, #128] @ 0x80
  18798. 8008812: f5b1 7f80 cmp.w r1, #256 @ 0x100
  18799. 8008816: f000 8207 beq.w 8008c28 <HAL_RCCEx_PeriphCLKConfig+0xa48>
  18800. 800881a: f240 80cb bls.w 80089b4 <HAL_RCCEx_PeriphCLKConfig+0x7d4>
  18801. 800881e: f421 7080 bic.w r0, r1, #256 @ 0x100
  18802. 8008822: f5b0 7f00 cmp.w r0, #512 @ 0x200
  18803. 8008826: f000 80c8 beq.w 80089ba <HAL_RCCEx_PeriphCLKConfig+0x7da>
  18804. 800882a: 2501 movs r5, #1
  18805. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
  18806. 800882c: 02d8 lsls r0, r3, #11
  18807. 800882e: d506 bpl.n 800883e <HAL_RCCEx_PeriphCLKConfig+0x65e>
  18808. __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
  18809. 8008830: 482e ldr r0, [pc, #184] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18810. 8008832: 6f66 ldr r6, [r4, #116] @ 0x74
  18811. 8008834: 6d01 ldr r1, [r0, #80] @ 0x50
  18812. 8008836: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
  18813. 800883a: 4331 orrs r1, r6
  18814. 800883c: 6501 str r1, [r0, #80] @ 0x50
  18815. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
  18816. 800883e: 00d9 lsls r1, r3, #3
  18817. 8008840: d507 bpl.n 8008852 <HAL_RCCEx_PeriphCLKConfig+0x672>
  18818. __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
  18819. 8008842: 482a ldr r0, [pc, #168] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18820. 8008844: f8d4 60b8 ldr.w r6, [r4, #184] @ 0xb8
  18821. 8008848: 6901 ldr r1, [r0, #16]
  18822. 800884a: f421 4180 bic.w r1, r1, #16384 @ 0x4000
  18823. 800884e: 4331 orrs r1, r6
  18824. 8008850: 6101 str r1, [r0, #16]
  18825. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
  18826. 8008852: 029f lsls r7, r3, #10
  18827. 8008854: d506 bpl.n 8008864 <HAL_RCCEx_PeriphCLKConfig+0x684>
  18828. __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
  18829. 8008856: 4825 ldr r0, [pc, #148] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18830. 8008858: 6ee6 ldr r6, [r4, #108] @ 0x6c
  18831. 800885a: 6d01 ldr r1, [r0, #80] @ 0x50
  18832. 800885c: f021 7180 bic.w r1, r1, #16777216 @ 0x1000000
  18833. 8008860: 4331 orrs r1, r6
  18834. 8008862: 6501 str r1, [r0, #80] @ 0x50
  18835. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
  18836. 8008864: 005e lsls r6, r3, #1
  18837. 8008866: d509 bpl.n 800887c <HAL_RCCEx_PeriphCLKConfig+0x69c>
  18838. __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
  18839. 8008868: 4920 ldr r1, [pc, #128] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18840. 800886a: 6908 ldr r0, [r1, #16]
  18841. 800886c: f420 4000 bic.w r0, r0, #32768 @ 0x8000
  18842. 8008870: 6108 str r0, [r1, #16]
  18843. 8008872: 6908 ldr r0, [r1, #16]
  18844. 8008874: f8d4 60bc ldr.w r6, [r4, #188] @ 0xbc
  18845. 8008878: 4330 orrs r0, r6
  18846. 800887a: 6108 str r0, [r1, #16]
  18847. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
  18848. 800887c: 2b00 cmp r3, #0
  18849. 800887e: da06 bge.n 800888e <HAL_RCCEx_PeriphCLKConfig+0x6ae>
  18850. __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
  18851. 8008880: 481a ldr r0, [pc, #104] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18852. 8008882: 6d66 ldr r6, [r4, #84] @ 0x54
  18853. 8008884: 6cc1 ldr r1, [r0, #76] @ 0x4c
  18854. 8008886: f021 5140 bic.w r1, r1, #805306368 @ 0x30000000
  18855. 800888a: 4331 orrs r1, r6
  18856. 800888c: 64c1 str r1, [r0, #76] @ 0x4c
  18857. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
  18858. 800888e: 0218 lsls r0, r3, #8
  18859. 8008890: d507 bpl.n 80088a2 <HAL_RCCEx_PeriphCLKConfig+0x6c2>
  18860. __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
  18861. 8008892: 4916 ldr r1, [pc, #88] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18862. 8008894: f8d4 008c ldr.w r0, [r4, #140] @ 0x8c
  18863. 8008898: 6d4b ldr r3, [r1, #84] @ 0x54
  18864. 800889a: f423 0340 bic.w r3, r3, #12582912 @ 0xc00000
  18865. 800889e: 4303 orrs r3, r0
  18866. 80088a0: 654b str r3, [r1, #84] @ 0x54
  18867. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP)
  18868. 80088a2: 07d1 lsls r1, r2, #31
  18869. 80088a4: d50f bpl.n 80088c6 <HAL_RCCEx_PeriphCLKConfig+0x6e6>
  18870. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18871. 80088a6: 4b11 ldr r3, [pc, #68] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18872. 80088a8: 6a9b ldr r3, [r3, #40] @ 0x28
  18873. 80088aa: f003 0303 and.w r3, r3, #3
  18874. 80088ae: 2b03 cmp r3, #3
  18875. 80088b0: f000 8184 beq.w 8008bbc <HAL_RCCEx_PeriphCLKConfig+0x9dc>
  18876. 80088b4: 2100 movs r1, #0
  18877. 80088b6: f104 0008 add.w r0, r4, #8
  18878. 80088ba: f7ff fbad bl 8008018 <RCCEx_PLL2_Config.part.0>
  18879. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
  18880. 80088be: 6862 ldr r2, [r4, #4]
  18881. if (ret == HAL_OK)
  18882. 80088c0: 2800 cmp r0, #0
  18883. 80088c2: f040 8205 bne.w 8008cd0 <HAL_RCCEx_PeriphCLKConfig+0xaf0>
  18884. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
  18885. 80088c6: 0793 lsls r3, r2, #30
  18886. 80088c8: d512 bpl.n 80088f0 <HAL_RCCEx_PeriphCLKConfig+0x710>
  18887. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18888. 80088ca: 4b08 ldr r3, [pc, #32] @ (80088ec <HAL_RCCEx_PeriphCLKConfig+0x70c>)
  18889. 80088cc: 6a9b ldr r3, [r3, #40] @ 0x28
  18890. 80088ce: f003 0303 and.w r3, r3, #3
  18891. 80088d2: 2b03 cmp r3, #3
  18892. 80088d4: f000 8170 beq.w 8008bb8 <HAL_RCCEx_PeriphCLKConfig+0x9d8>
  18893. 80088d8: 2101 movs r1, #1
  18894. 80088da: f104 0008 add.w r0, r4, #8
  18895. 80088de: f7ff fb9b bl 8008018 <RCCEx_PLL2_Config.part.0>
  18896. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
  18897. 80088e2: 6862 ldr r2, [r4, #4]
  18898. if (ret == HAL_OK)
  18899. 80088e4: 2800 cmp r0, #0
  18900. 80088e6: f040 81f5 bne.w 8008cd4 <HAL_RCCEx_PeriphCLKConfig+0xaf4>
  18901. 80088ea: e001 b.n 80088f0 <HAL_RCCEx_PeriphCLKConfig+0x710>
  18902. 80088ec: 58024400 .word 0x58024400
  18903. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
  18904. 80088f0: 0757 lsls r7, r2, #29
  18905. 80088f2: d50f bpl.n 8008914 <HAL_RCCEx_PeriphCLKConfig+0x734>
  18906. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18907. 80088f4: 4bb2 ldr r3, [pc, #712] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  18908. 80088f6: 6a9b ldr r3, [r3, #40] @ 0x28
  18909. 80088f8: f003 0303 and.w r3, r3, #3
  18910. 80088fc: 2b03 cmp r3, #3
  18911. 80088fe: f000 8168 beq.w 8008bd2 <HAL_RCCEx_PeriphCLKConfig+0x9f2>
  18912. 8008902: 2102 movs r1, #2
  18913. 8008904: f104 0008 add.w r0, r4, #8
  18914. 8008908: f7ff fb86 bl 8008018 <RCCEx_PLL2_Config.part.0>
  18915. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
  18916. 800890c: 6862 ldr r2, [r4, #4]
  18917. if (ret == HAL_OK)
  18918. 800890e: 2800 cmp r0, #0
  18919. 8008910: f040 81e2 bne.w 8008cd8 <HAL_RCCEx_PeriphCLKConfig+0xaf8>
  18920. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
  18921. 8008914: 0716 lsls r6, r2, #28
  18922. 8008916: d50f bpl.n 8008938 <HAL_RCCEx_PeriphCLKConfig+0x758>
  18923. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18924. 8008918: 4ba9 ldr r3, [pc, #676] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  18925. 800891a: 6a9b ldr r3, [r3, #40] @ 0x28
  18926. 800891c: f003 0303 and.w r3, r3, #3
  18927. 8008920: 2b03 cmp r3, #3
  18928. 8008922: f000 8147 beq.w 8008bb4 <HAL_RCCEx_PeriphCLKConfig+0x9d4>
  18929. 8008926: 2100 movs r1, #0
  18930. 8008928: f104 0028 add.w r0, r4, #40 @ 0x28
  18931. 800892c: f7ff fbe6 bl 80080fc <RCCEx_PLL3_Config.part.0>
  18932. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
  18933. 8008930: 6862 ldr r2, [r4, #4]
  18934. if (ret == HAL_OK)
  18935. 8008932: 2800 cmp r0, #0
  18936. 8008934: f040 81d2 bne.w 8008cdc <HAL_RCCEx_PeriphCLKConfig+0xafc>
  18937. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
  18938. 8008938: 06d0 lsls r0, r2, #27
  18939. 800893a: d54a bpl.n 80089d2 <HAL_RCCEx_PeriphCLKConfig+0x7f2>
  18940. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18941. 800893c: 4ba0 ldr r3, [pc, #640] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  18942. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
  18943. 800893e: f104 0628 add.w r6, r4, #40 @ 0x28
  18944. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  18945. 8008942: 6a9b ldr r3, [r3, #40] @ 0x28
  18946. 8008944: f003 0303 and.w r3, r3, #3
  18947. 8008948: 2b03 cmp r3, #3
  18948. 800894a: f000 813d beq.w 8008bc8 <HAL_RCCEx_PeriphCLKConfig+0x9e8>
  18949. 800894e: 2101 movs r1, #1
  18950. 8008950: 4630 mov r0, r6
  18951. 8008952: f7ff fbd3 bl 80080fc <RCCEx_PLL3_Config.part.0>
  18952. if (ret == HAL_OK)
  18953. 8008956: 2800 cmp r0, #0
  18954. 8008958: d03a beq.n 80089d0 <HAL_RCCEx_PeriphCLKConfig+0x7f0>
  18955. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
  18956. 800895a: 6863 ldr r3, [r4, #4]
  18957. 800895c: 069a lsls r2, r3, #26
  18958. 800895e: f140 808e bpl.w 8008a7e <HAL_RCCEx_PeriphCLKConfig+0x89e>
  18959. 8008962: 4605 mov r5, r0
  18960. 8008964: e039 b.n 80089da <HAL_RCCEx_PeriphCLKConfig+0x7fa>
  18961. switch (PeriphClkInit->Lptim1ClockSelection)
  18962. 8008966: f021 5080 bic.w r0, r1, #268435456 @ 0x10000000
  18963. 800896a: f1b0 4f80 cmp.w r0, #1073741824 @ 0x40000000
  18964. 800896e: f43f ae8c beq.w 800868a <HAL_RCCEx_PeriphCLKConfig+0x4aa>
  18965. 8008972: f1b1 5f40 cmp.w r1, #805306368 @ 0x30000000
  18966. 8008976: f43f ae88 beq.w 800868a <HAL_RCCEx_PeriphCLKConfig+0x4aa>
  18967. 800897a: 2601 movs r6, #1
  18968. 800897c: 4635 mov r5, r6
  18969. 800897e: e68f b.n 80086a0 <HAL_RCCEx_PeriphCLKConfig+0x4c0>
  18970. switch (PeriphClkInit->Lptim2ClockSelection)
  18971. 8008980: f421 6080 bic.w r0, r1, #1024 @ 0x400
  18972. 8008984: f5b0 5f80 cmp.w r0, #4096 @ 0x1000
  18973. 8008988: f43f aea8 beq.w 80086dc <HAL_RCCEx_PeriphCLKConfig+0x4fc>
  18974. 800898c: f5b1 6f40 cmp.w r1, #3072 @ 0xc00
  18975. 8008990: f43f aea4 beq.w 80086dc <HAL_RCCEx_PeriphCLKConfig+0x4fc>
  18976. 8008994: 2601 movs r6, #1
  18977. 8008996: 4635 mov r5, r6
  18978. 8008998: e6ab b.n 80086f2 <HAL_RCCEx_PeriphCLKConfig+0x512>
  18979. switch (PeriphClkInit->Lptim345ClockSelection)
  18980. 800899a: f421 5000 bic.w r0, r1, #8192 @ 0x2000
  18981. 800899e: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
  18982. 80089a2: f43f aec4 beq.w 800872e <HAL_RCCEx_PeriphCLKConfig+0x54e>
  18983. 80089a6: f5b1 4fc0 cmp.w r1, #24576 @ 0x6000
  18984. 80089aa: f43f aec0 beq.w 800872e <HAL_RCCEx_PeriphCLKConfig+0x54e>
  18985. 80089ae: 2601 movs r6, #1
  18986. 80089b0: 4635 mov r5, r6
  18987. 80089b2: e6c7 b.n 8008744 <HAL_RCCEx_PeriphCLKConfig+0x564>
  18988. switch (PeriphClkInit->RngClockSelection)
  18989. 80089b4: 2900 cmp r1, #0
  18990. 80089b6: f47f af38 bne.w 800882a <HAL_RCCEx_PeriphCLKConfig+0x64a>
  18991. if (ret == HAL_OK)
  18992. 80089ba: 2d00 cmp r5, #0
  18993. 80089bc: f47f af36 bne.w 800882c <HAL_RCCEx_PeriphCLKConfig+0x64c>
  18994. __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
  18995. 80089c0: 4d7f ldr r5, [pc, #508] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  18996. 80089c2: 6d68 ldr r0, [r5, #84] @ 0x54
  18997. 80089c4: f420 7040 bic.w r0, r0, #768 @ 0x300
  18998. 80089c8: 4301 orrs r1, r0
  18999. 80089ca: 6569 str r1, [r5, #84] @ 0x54
  19000. switch (PeriphClkInit->SdmmcClockSelection)
  19001. 80089cc: 4635 mov r5, r6
  19002. 80089ce: e72d b.n 800882c <HAL_RCCEx_PeriphCLKConfig+0x64c>
  19003. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
  19004. 80089d0: 6862 ldr r2, [r4, #4]
  19005. 80089d2: 0693 lsls r3, r2, #26
  19006. 80089d4: d50d bpl.n 80089f2 <HAL_RCCEx_PeriphCLKConfig+0x812>
  19007. ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
  19008. 80089d6: f104 0628 add.w r6, r4, #40 @ 0x28
  19009. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19010. 80089da: 4b79 ldr r3, [pc, #484] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19011. 80089dc: 6a9b ldr r3, [r3, #40] @ 0x28
  19012. 80089de: f003 0303 and.w r3, r3, #3
  19013. 80089e2: 2b03 cmp r3, #3
  19014. 80089e4: d04b beq.n 8008a7e <HAL_RCCEx_PeriphCLKConfig+0x89e>
  19015. 80089e6: 2102 movs r1, #2
  19016. 80089e8: 4630 mov r0, r6
  19017. 80089ea: f7ff fb87 bl 80080fc <RCCEx_PLL3_Config.part.0>
  19018. if (ret == HAL_OK)
  19019. 80089ee: 2800 cmp r0, #0
  19020. 80089f0: d145 bne.n 8008a7e <HAL_RCCEx_PeriphCLKConfig+0x89e>
  19021. if (status == HAL_OK)
  19022. 80089f2: 1e28 subs r0, r5, #0
  19023. 80089f4: bf18 it ne
  19024. 80089f6: 2001 movne r0, #1
  19025. }
  19026. 80089f8: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  19027. 80089fc: 2601 movs r6, #1
  19028. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
  19029. 80089fe: 039f lsls r7, r3, #14
  19030. 8008a00: 4635 mov r5, r6
  19031. 8008a02: d5e3 bpl.n 80089cc <HAL_RCCEx_PeriphCLKConfig+0x7ec>
  19032. 8008a04: e703 b.n 800880e <HAL_RCCEx_PeriphCLKConfig+0x62e>
  19033. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  19034. 8008a06: 486e ldr r0, [pc, #440] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19035. 8008a08: 6ac1 ldr r1, [r0, #44] @ 0x2c
  19036. 8008a0a: f441 3100 orr.w r1, r1, #131072 @ 0x20000
  19037. 8008a0e: 62c1 str r1, [r0, #44] @ 0x2c
  19038. if (ret == HAL_OK)
  19039. 8008a10: 2d00 cmp r5, #0
  19040. 8008a12: f040 8144 bne.w 8008c9e <HAL_RCCEx_PeriphCLKConfig+0xabe>
  19041. __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
  19042. 8008a16: 4f6a ldr r7, [pc, #424] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19043. 8008a18: f8d4 0088 ldr.w r0, [r4, #136] @ 0x88
  19044. 8008a1c: 6d79 ldr r1, [r7, #84] @ 0x54
  19045. 8008a1e: f421 1140 bic.w r1, r1, #3145728 @ 0x300000
  19046. 8008a22: 4301 orrs r1, r0
  19047. 8008a24: 6579 str r1, [r7, #84] @ 0x54
  19048. 8008a26: e6cc b.n 80087c2 <HAL_RCCEx_PeriphCLKConfig+0x5e2>
  19049. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  19050. 8008a28: 4865 ldr r0, [pc, #404] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19051. 8008a2a: 6ac1 ldr r1, [r0, #44] @ 0x2c
  19052. 8008a2c: f441 3100 orr.w r1, r1, #131072 @ 0x20000
  19053. 8008a30: 62c1 str r1, [r0, #44] @ 0x2c
  19054. if (ret == HAL_OK)
  19055. 8008a32: 2d00 cmp r5, #0
  19056. 8008a34: f040 8130 bne.w 8008c98 <HAL_RCCEx_PeriphCLKConfig+0xab8>
  19057. __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
  19058. 8008a38: 4f61 ldr r7, [pc, #388] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19059. 8008a3a: 6f20 ldr r0, [r4, #112] @ 0x70
  19060. 8008a3c: 6d39 ldr r1, [r7, #80] @ 0x50
  19061. 8008a3e: f021 5140 bic.w r1, r1, #805306368 @ 0x30000000
  19062. 8008a42: 4301 orrs r1, r0
  19063. 8008a44: 6539 str r1, [r7, #80] @ 0x50
  19064. 8008a46: e526 b.n 8008496 <HAL_RCCEx_PeriphCLKConfig+0x2b6>
  19065. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19066. 8008a48: 495d ldr r1, [pc, #372] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19067. 8008a4a: 6a89 ldr r1, [r1, #40] @ 0x28
  19068. 8008a4c: f001 0103 and.w r1, r1, #3
  19069. 8008a50: 2903 cmp r1, #3
  19070. 8008a52: f43f aea2 beq.w 800879a <HAL_RCCEx_PeriphCLKConfig+0x5ba>
  19071. 8008a56: 2102 movs r1, #2
  19072. 8008a58: f104 0028 add.w r0, r4, #40 @ 0x28
  19073. 8008a5c: f7ff fb4e bl 80080fc <RCCEx_PLL3_Config.part.0>
  19074. 8008a60: 4605 mov r5, r0
  19075. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
  19076. 8008a62: e9d4 3200 ldrd r3, r2, [r4]
  19077. if (ret == HAL_OK)
  19078. 8008a66: 2d00 cmp r5, #0
  19079. 8008a68: f040 8155 bne.w 8008d16 <HAL_RCCEx_PeriphCLKConfig+0xb36>
  19080. __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
  19081. 8008a6c: 4f54 ldr r7, [pc, #336] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19082. 8008a6e: f8d4 00a4 ldr.w r0, [r4, #164] @ 0xa4
  19083. 8008a72: 6db9 ldr r1, [r7, #88] @ 0x58
  19084. 8008a74: f421 3140 bic.w r1, r1, #196608 @ 0x30000
  19085. 8008a78: 4301 orrs r1, r0
  19086. 8008a7a: 65b9 str r1, [r7, #88] @ 0x58
  19087. 8008a7c: e68f b.n 800879e <HAL_RCCEx_PeriphCLKConfig+0x5be>
  19088. return HAL_ERROR;
  19089. 8008a7e: 2001 movs r0, #1
  19090. }
  19091. 8008a80: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  19092. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19093. 8008a84: 494e ldr r1, [pc, #312] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19094. 8008a86: 6a89 ldr r1, [r1, #40] @ 0x28
  19095. 8008a88: f001 0103 and.w r1, r1, #3
  19096. 8008a8c: 2903 cmp r1, #3
  19097. 8008a8e: f43f ad96 beq.w 80085be <HAL_RCCEx_PeriphCLKConfig+0x3de>
  19098. 8008a92: 2101 movs r1, #1
  19099. 8008a94: f104 0008 add.w r0, r4, #8
  19100. 8008a98: f7ff fabe bl 8008018 <RCCEx_PLL2_Config.part.0>
  19101. 8008a9c: 4605 mov r5, r0
  19102. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
  19103. 8008a9e: e9d4 3200 ldrd r3, r2, [r4]
  19104. if (ret == HAL_OK)
  19105. 8008aa2: 2d00 cmp r5, #0
  19106. 8008aa4: f040 813b bne.w 8008d1e <HAL_RCCEx_PeriphCLKConfig+0xb3e>
  19107. __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
  19108. 8008aa8: 4f45 ldr r7, [pc, #276] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19109. 8008aaa: 6fe0 ldr r0, [r4, #124] @ 0x7c
  19110. 8008aac: 6d79 ldr r1, [r7, #84] @ 0x54
  19111. 8008aae: f021 0138 bic.w r1, r1, #56 @ 0x38
  19112. 8008ab2: 4301 orrs r1, r0
  19113. 8008ab4: 6579 str r1, [r7, #84] @ 0x54
  19114. 8008ab6: e584 b.n 80085c2 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
  19115. 8008ab8: 2601 movs r6, #1
  19116. 8008aba: f7ff bbc0 b.w 800823e <HAL_RCCEx_PeriphCLKConfig+0x5e>
  19117. SET_BIT(PWR->CR1, PWR_CR1_DBP);
  19118. 8008abe: 4f41 ldr r7, [pc, #260] @ (8008bc4 <HAL_RCCEx_PeriphCLKConfig+0x9e4>)
  19119. 8008ac0: 683b ldr r3, [r7, #0]
  19120. 8008ac2: f443 7380 orr.w r3, r3, #256 @ 0x100
  19121. 8008ac6: 603b str r3, [r7, #0]
  19122. tickstart = HAL_GetTick();
  19123. 8008ac8: f7fb fa82 bl 8003fd0 <HAL_GetTick>
  19124. 8008acc: 4680 mov r8, r0
  19125. while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
  19126. 8008ace: e006 b.n 8008ade <HAL_RCCEx_PeriphCLKConfig+0x8fe>
  19127. if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
  19128. 8008ad0: f7fb fa7e bl 8003fd0 <HAL_GetTick>
  19129. 8008ad4: eba0 0008 sub.w r0, r0, r8
  19130. 8008ad8: 2864 cmp r0, #100 @ 0x64
  19131. 8008ada: f200 827b bhi.w 8008fd4 <HAL_RCCEx_PeriphCLKConfig+0xdf4>
  19132. while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
  19133. 8008ade: 683b ldr r3, [r7, #0]
  19134. 8008ae0: 05da lsls r2, r3, #23
  19135. 8008ae2: d5f5 bpl.n 8008ad0 <HAL_RCCEx_PeriphCLKConfig+0x8f0>
  19136. if (ret == HAL_OK)
  19137. 8008ae4: 2d00 cmp r5, #0
  19138. 8008ae6: f040 8276 bne.w 8008fd6 <HAL_RCCEx_PeriphCLKConfig+0xdf6>
  19139. if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
  19140. 8008aea: 4a35 ldr r2, [pc, #212] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19141. 8008aec: f8d4 30b4 ldr.w r3, [r4, #180] @ 0xb4
  19142. 8008af0: 6f11 ldr r1, [r2, #112] @ 0x70
  19143. 8008af2: 4059 eors r1, r3
  19144. 8008af4: f411 7f40 tst.w r1, #768 @ 0x300
  19145. 8008af8: d00b beq.n 8008b12 <HAL_RCCEx_PeriphCLKConfig+0x932>
  19146. tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
  19147. 8008afa: 6f11 ldr r1, [r2, #112] @ 0x70
  19148. __HAL_RCC_BACKUPRESET_FORCE();
  19149. 8008afc: 6f10 ldr r0, [r2, #112] @ 0x70
  19150. tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
  19151. 8008afe: f421 7140 bic.w r1, r1, #768 @ 0x300
  19152. __HAL_RCC_BACKUPRESET_FORCE();
  19153. 8008b02: f440 3080 orr.w r0, r0, #65536 @ 0x10000
  19154. 8008b06: 6710 str r0, [r2, #112] @ 0x70
  19155. __HAL_RCC_BACKUPRESET_RELEASE();
  19156. 8008b08: 6f10 ldr r0, [r2, #112] @ 0x70
  19157. 8008b0a: f420 3080 bic.w r0, r0, #65536 @ 0x10000
  19158. 8008b0e: 6710 str r0, [r2, #112] @ 0x70
  19159. RCC->BDCR = tmpreg;
  19160. 8008b10: 6711 str r1, [r2, #112] @ 0x70
  19161. if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
  19162. 8008b12: f5b3 7f80 cmp.w r3, #256 @ 0x100
  19163. 8008b16: f000 8289 beq.w 800902c <HAL_RCCEx_PeriphCLKConfig+0xe4c>
  19164. __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
  19165. 8008b1a: f403 7240 and.w r2, r3, #768 @ 0x300
  19166. 8008b1e: f5b2 7f40 cmp.w r2, #768 @ 0x300
  19167. 8008b22: f000 8297 beq.w 8009054 <HAL_RCCEx_PeriphCLKConfig+0xe74>
  19168. 8008b26: 4926 ldr r1, [pc, #152] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19169. 8008b28: 690a ldr r2, [r1, #16]
  19170. 8008b2a: f422 527c bic.w r2, r2, #16128 @ 0x3f00
  19171. 8008b2e: 610a str r2, [r1, #16]
  19172. 8008b30: 4823 ldr r0, [pc, #140] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19173. 8008b32: f3c3 010b ubfx r1, r3, #0, #12
  19174. 8008b36: 6f07 ldr r7, [r0, #112] @ 0x70
  19175. 8008b38: 4339 orrs r1, r7
  19176. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
  19177. 8008b3a: e9d4 3200 ldrd r3, r2, [r4]
  19178. __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
  19179. 8008b3e: 6701 str r1, [r0, #112] @ 0x70
  19180. 8008b40: e50d b.n 800855e <HAL_RCCEx_PeriphCLKConfig+0x37e>
  19181. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  19182. 8008b42: 481f ldr r0, [pc, #124] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19183. 8008b44: 6ac1 ldr r1, [r0, #44] @ 0x2c
  19184. 8008b46: f441 3100 orr.w r1, r1, #131072 @ 0x20000
  19185. 8008b4a: 62c1 str r1, [r0, #44] @ 0x2c
  19186. if (ret == HAL_OK)
  19187. 8008b4c: 2d00 cmp r5, #0
  19188. 8008b4e: f040 80bc bne.w 8008cca <HAL_RCCEx_PeriphCLKConfig+0xaea>
  19189. 8008b52: e43c b.n 80083ce <HAL_RCCEx_PeriphCLKConfig+0x1ee>
  19190. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  19191. 8008b54: 481a ldr r0, [pc, #104] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19192. 8008b56: 6ac1 ldr r1, [r0, #44] @ 0x2c
  19193. 8008b58: f441 3100 orr.w r1, r1, #131072 @ 0x20000
  19194. 8008b5c: 62c1 str r1, [r0, #44] @ 0x2c
  19195. break;
  19196. 8008b5e: 4635 mov r5, r6
  19197. if (ret == HAL_OK)
  19198. 8008b60: 2d00 cmp r5, #0
  19199. 8008b62: f040 81ed bne.w 8008f40 <HAL_RCCEx_PeriphCLKConfig+0xd60>
  19200. __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
  19201. 8008b66: 4f16 ldr r7, [pc, #88] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19202. 8008b68: 6da0 ldr r0, [r4, #88] @ 0x58
  19203. 8008b6a: 6d39 ldr r1, [r7, #80] @ 0x50
  19204. 8008b6c: f021 0107 bic.w r1, r1, #7
  19205. 8008b70: 4301 orrs r1, r0
  19206. 8008b72: 6539 str r1, [r7, #80] @ 0x50
  19207. 8008b74: f7ff bb71 b.w 800825a <HAL_RCCEx_PeriphCLKConfig+0x7a>
  19208. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  19209. 8008b78: 4811 ldr r0, [pc, #68] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19210. 8008b7a: 6ac1 ldr r1, [r0, #44] @ 0x2c
  19211. 8008b7c: f441 3100 orr.w r1, r1, #131072 @ 0x20000
  19212. 8008b80: 62c1 str r1, [r0, #44] @ 0x2c
  19213. if (ret == HAL_OK)
  19214. 8008b82: 2d00 cmp r5, #0
  19215. 8008b84: f040 8098 bne.w 8008cb8 <HAL_RCCEx_PeriphCLKConfig+0xad8>
  19216. 8008b88: f7ff bb87 b.w 800829a <HAL_RCCEx_PeriphCLKConfig+0xba>
  19217. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  19218. 8008b8c: 480c ldr r0, [pc, #48] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19219. 8008b8e: 6ac1 ldr r1, [r0, #44] @ 0x2c
  19220. 8008b90: f441 3100 orr.w r1, r1, #131072 @ 0x20000
  19221. 8008b94: 62c1 str r1, [r0, #44] @ 0x2c
  19222. if (ret == HAL_OK)
  19223. 8008b96: 2d00 cmp r5, #0
  19224. 8008b98: f040 8091 bne.w 8008cbe <HAL_RCCEx_PeriphCLKConfig+0xade>
  19225. 8008b9c: f7ff bba7 b.w 80082ee <HAL_RCCEx_PeriphCLKConfig+0x10e>
  19226. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  19227. 8008ba0: 4807 ldr r0, [pc, #28] @ (8008bc0 <HAL_RCCEx_PeriphCLKConfig+0x9e0>)
  19228. 8008ba2: 6ac1 ldr r1, [r0, #44] @ 0x2c
  19229. 8008ba4: f441 3100 orr.w r1, r1, #131072 @ 0x20000
  19230. 8008ba8: 62c1 str r1, [r0, #44] @ 0x2c
  19231. if (ret == HAL_OK)
  19232. 8008baa: 2d00 cmp r5, #0
  19233. 8008bac: f040 808a bne.w 8008cc4 <HAL_RCCEx_PeriphCLKConfig+0xae4>
  19234. 8008bb0: f7ff bbc8 b.w 8008344 <HAL_RCCEx_PeriphCLKConfig+0x164>
  19235. return HAL_ERROR;
  19236. 8008bb4: 2501 movs r5, #1
  19237. 8008bb6: e6bf b.n 8008938 <HAL_RCCEx_PeriphCLKConfig+0x758>
  19238. return HAL_ERROR;
  19239. 8008bb8: 2501 movs r5, #1
  19240. 8008bba: e699 b.n 80088f0 <HAL_RCCEx_PeriphCLKConfig+0x710>
  19241. 8008bbc: 2501 movs r5, #1
  19242. 8008bbe: e682 b.n 80088c6 <HAL_RCCEx_PeriphCLKConfig+0x6e6>
  19243. 8008bc0: 58024400 .word 0x58024400
  19244. 8008bc4: 58024800 .word 0x58024800
  19245. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
  19246. 8008bc8: 0691 lsls r1, r2, #26
  19247. 8008bca: f57f af58 bpl.w 8008a7e <HAL_RCCEx_PeriphCLKConfig+0x89e>
  19248. return HAL_ERROR;
  19249. 8008bce: 2501 movs r5, #1
  19250. 8008bd0: e703 b.n 80089da <HAL_RCCEx_PeriphCLKConfig+0x7fa>
  19251. return HAL_ERROR;
  19252. 8008bd2: 2501 movs r5, #1
  19253. 8008bd4: e69e b.n 8008914 <HAL_RCCEx_PeriphCLKConfig+0x734>
  19254. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19255. 8008bd6: 49bc ldr r1, [pc, #752] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19256. 8008bd8: 6a89 ldr r1, [r1, #40] @ 0x28
  19257. 8008bda: f001 0103 and.w r1, r1, #3
  19258. 8008bde: 2903 cmp r1, #3
  19259. 8008be0: f000 820d beq.w 8008ffe <HAL_RCCEx_PeriphCLKConfig+0xe1e>
  19260. 8008be4: 2102 movs r1, #2
  19261. 8008be6: f104 0028 add.w r0, r4, #40 @ 0x28
  19262. 8008bea: f7ff fa87 bl 80080fc <RCCEx_PLL3_Config.part.0>
  19263. if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
  19264. 8008bee: 2800 cmp r0, #0
  19265. 8008bf0: f040 8211 bne.w 8009016 <HAL_RCCEx_PeriphCLKConfig+0xe36>
  19266. __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
  19267. 8008bf4: f8d4 0098 ldr.w r0, [r4, #152] @ 0x98
  19268. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
  19269. 8008bf8: e9d4 3200 ldrd r3, r2, [r4]
  19270. 8008bfc: e5b8 b.n 8008770 <HAL_RCCEx_PeriphCLKConfig+0x590>
  19271. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19272. 8008bfe: 49b2 ldr r1, [pc, #712] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19273. 8008c00: 6a89 ldr r1, [r1, #40] @ 0x28
  19274. 8008c02: f001 0103 and.w r1, r1, #3
  19275. 8008c06: 2903 cmp r1, #3
  19276. 8008c08: f000 81fc beq.w 8009004 <HAL_RCCEx_PeriphCLKConfig+0xe24>
  19277. 8008c0c: 2102 movs r1, #2
  19278. 8008c0e: f104 0028 add.w r0, r4, #40 @ 0x28
  19279. 8008c12: f7ff fa73 bl 80080fc <RCCEx_PLL3_Config.part.0>
  19280. if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
  19281. 8008c16: 2800 cmp r0, #0
  19282. 8008c18: f000 81f7 beq.w 800900a <HAL_RCCEx_PeriphCLKConfig+0xe2a>
  19283. __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
  19284. 8008c1c: f8d4 0084 ldr.w r0, [r4, #132] @ 0x84
  19285. status = HAL_ERROR;
  19286. 8008c20: 2601 movs r6, #1
  19287. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
  19288. 8008c22: e9d4 3200 ldrd r3, r2, [r4]
  19289. 8008c26: e595 b.n 8008754 <HAL_RCCEx_PeriphCLKConfig+0x574>
  19290. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  19291. 8008c28: 4fa7 ldr r7, [pc, #668] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19292. 8008c2a: 6af8 ldr r0, [r7, #44] @ 0x2c
  19293. 8008c2c: f440 3000 orr.w r0, r0, #131072 @ 0x20000
  19294. 8008c30: 62f8 str r0, [r7, #44] @ 0x2c
  19295. if (ret == HAL_OK)
  19296. 8008c32: 2d00 cmp r5, #0
  19297. 8008c34: f47f adfa bne.w 800882c <HAL_RCCEx_PeriphCLKConfig+0x64c>
  19298. 8008c38: e6c2 b.n 80089c0 <HAL_RCCEx_PeriphCLKConfig+0x7e0>
  19299. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  19300. 8008c3a: 48a3 ldr r0, [pc, #652] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19301. 8008c3c: 6ac1 ldr r1, [r0, #44] @ 0x2c
  19302. 8008c3e: f441 3100 orr.w r1, r1, #131072 @ 0x20000
  19303. 8008c42: 62c1 str r1, [r0, #44] @ 0x2c
  19304. if (ret == HAL_OK)
  19305. 8008c44: 2d00 cmp r5, #0
  19306. 8008c46: f43f add8 beq.w 80087fa <HAL_RCCEx_PeriphCLKConfig+0x61a>
  19307. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
  19308. 8008c4a: 039f lsls r7, r3, #14
  19309. 8008c4c: 462e mov r6, r5
  19310. 8008c4e: f57f aebd bpl.w 80089cc <HAL_RCCEx_PeriphCLKConfig+0x7ec>
  19311. 8008c52: e5dc b.n 800880e <HAL_RCCEx_PeriphCLKConfig+0x62e>
  19312. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19313. 8008c54: 499c ldr r1, [pc, #624] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19314. 8008c56: 6a89 ldr r1, [r1, #40] @ 0x28
  19315. 8008c58: f001 0103 and.w r1, r1, #3
  19316. 8008c5c: 2903 cmp r1, #3
  19317. 8008c5e: f43f ac18 beq.w 8008492 <HAL_RCCEx_PeriphCLKConfig+0x2b2>
  19318. 8008c62: 2101 movs r1, #1
  19319. 8008c64: f104 0008 add.w r0, r4, #8
  19320. 8008c68: f7ff f9d6 bl 8008018 <RCCEx_PLL2_Config.part.0>
  19321. 8008c6c: 4605 mov r5, r0
  19322. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
  19323. 8008c6e: e9d4 3200 ldrd r3, r2, [r4]
  19324. if (ret == HAL_OK)
  19325. 8008c72: b98d cbnz r5, 8008c98 <HAL_RCCEx_PeriphCLKConfig+0xab8>
  19326. 8008c74: e6e0 b.n 8008a38 <HAL_RCCEx_PeriphCLKConfig+0x858>
  19327. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19328. 8008c76: 4894 ldr r0, [pc, #592] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19329. 8008c78: 6a80 ldr r0, [r0, #40] @ 0x28
  19330. 8008c7a: f000 0003 and.w r0, r0, #3
  19331. 8008c7e: 2803 cmp r0, #3
  19332. 8008c80: f43f ad8b beq.w 800879a <HAL_RCCEx_PeriphCLKConfig+0x5ba>
  19333. 8008c84: f104 0008 add.w r0, r4, #8
  19334. 8008c88: f7ff f9c6 bl 8008018 <RCCEx_PLL2_Config.part.0>
  19335. 8008c8c: 4605 mov r5, r0
  19336. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
  19337. 8008c8e: e9d4 3200 ldrd r3, r2, [r4]
  19338. if (ret == HAL_OK)
  19339. 8008c92: 2d00 cmp r5, #0
  19340. 8008c94: d13f bne.n 8008d16 <HAL_RCCEx_PeriphCLKConfig+0xb36>
  19341. 8008c96: e6e9 b.n 8008a6c <HAL_RCCEx_PeriphCLKConfig+0x88c>
  19342. 8008c98: 462e mov r6, r5
  19343. 8008c9a: f7ff bbfc b.w 8008496 <HAL_RCCEx_PeriphCLKConfig+0x2b6>
  19344. 8008c9e: 462e mov r6, r5
  19345. 8008ca0: e58f b.n 80087c2 <HAL_RCCEx_PeriphCLKConfig+0x5e2>
  19346. __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
  19347. 8008ca2: 4f89 ldr r7, [pc, #548] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19348. 8008ca4: 6ca0 ldr r0, [r4, #72] @ 0x48
  19349. 8008ca6: 6cf9 ldr r1, [r7, #76] @ 0x4c
  19350. 8008ca8: f021 0103 bic.w r1, r1, #3
  19351. 8008cac: 4301 orrs r1, r0
  19352. 8008cae: 64f9 str r1, [r7, #76] @ 0x4c
  19353. 8008cb0: e452 b.n 8008558 <HAL_RCCEx_PeriphCLKConfig+0x378>
  19354. 8008cb2: 462e mov r6, r5
  19355. 8008cb4: f7ff bb69 b.w 800838a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
  19356. 8008cb8: 462e mov r6, r5
  19357. 8008cba: f7ff baf5 b.w 80082a8 <HAL_RCCEx_PeriphCLKConfig+0xc8>
  19358. 8008cbe: 462e mov r6, r5
  19359. 8008cc0: f7ff bb1d b.w 80082fe <HAL_RCCEx_PeriphCLKConfig+0x11e>
  19360. 8008cc4: 462e mov r6, r5
  19361. 8008cc6: f7ff bb45 b.w 8008354 <HAL_RCCEx_PeriphCLKConfig+0x174>
  19362. 8008cca: 462e mov r6, r5
  19363. 8008ccc: f7ff bb86 b.w 80083dc <HAL_RCCEx_PeriphCLKConfig+0x1fc>
  19364. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
  19365. 8008cd0: 4605 mov r5, r0
  19366. 8008cd2: e5f8 b.n 80088c6 <HAL_RCCEx_PeriphCLKConfig+0x6e6>
  19367. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
  19368. 8008cd4: 4605 mov r5, r0
  19369. 8008cd6: e60b b.n 80088f0 <HAL_RCCEx_PeriphCLKConfig+0x710>
  19370. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
  19371. 8008cd8: 4605 mov r5, r0
  19372. 8008cda: e61b b.n 8008914 <HAL_RCCEx_PeriphCLKConfig+0x734>
  19373. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
  19374. 8008cdc: 4605 mov r5, r0
  19375. 8008cde: e62b b.n 8008938 <HAL_RCCEx_PeriphCLKConfig+0x758>
  19376. __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
  19377. 8008ce0: 4f79 ldr r7, [pc, #484] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19378. 8008ce2: 6fa0 ldr r0, [r4, #120] @ 0x78
  19379. 8008ce4: 6d79 ldr r1, [r7, #84] @ 0x54
  19380. 8008ce6: f021 0107 bic.w r1, r1, #7
  19381. 8008cea: 4301 orrs r1, r0
  19382. 8008cec: 6579 str r1, [r7, #84] @ 0x54
  19383. 8008cee: e489 b.n 8008604 <HAL_RCCEx_PeriphCLKConfig+0x424>
  19384. 8008cf0: 462e mov r6, r5
  19385. 8008cf2: e4fe b.n 80086f2 <HAL_RCCEx_PeriphCLKConfig+0x512>
  19386. 8008cf4: 462e mov r6, r5
  19387. 8008cf6: f7ff bb98 b.w 800842a <HAL_RCCEx_PeriphCLKConfig+0x24a>
  19388. __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
  19389. 8008cfa: 4f73 ldr r7, [pc, #460] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19390. 8008cfc: f8d4 0094 ldr.w r0, [r4, #148] @ 0x94
  19391. 8008d00: 6db9 ldr r1, [r7, #88] @ 0x58
  19392. 8008d02: f021 0107 bic.w r1, r1, #7
  19393. 8008d06: 4301 orrs r1, r0
  19394. 8008d08: 65b9 str r1, [r7, #88] @ 0x58
  19395. 8008d0a: e4a0 b.n 800864e <HAL_RCCEx_PeriphCLKConfig+0x46e>
  19396. 8008d0c: 462e mov r6, r5
  19397. 8008d0e: e519 b.n 8008744 <HAL_RCCEx_PeriphCLKConfig+0x564>
  19398. 8008d10: 462e mov r6, r5
  19399. 8008d12: f7ff bbb0 b.w 8008476 <HAL_RCCEx_PeriphCLKConfig+0x296>
  19400. 8008d16: 462e mov r6, r5
  19401. 8008d18: e541 b.n 800879e <HAL_RCCEx_PeriphCLKConfig+0x5be>
  19402. 8008d1a: 462e mov r6, r5
  19403. 8008d1c: e4c0 b.n 80086a0 <HAL_RCCEx_PeriphCLKConfig+0x4c0>
  19404. 8008d1e: 462e mov r6, r5
  19405. 8008d20: e44f b.n 80085c2 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
  19406. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19407. 8008d22: 4969 ldr r1, [pc, #420] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19408. 8008d24: 6a89 ldr r1, [r1, #40] @ 0x28
  19409. 8008d26: f001 0103 and.w r1, r1, #3
  19410. 8008d2a: 2903 cmp r1, #3
  19411. 8008d2c: f43f abe5 beq.w 80084fa <HAL_RCCEx_PeriphCLKConfig+0x31a>
  19412. 8008d30: 2102 movs r1, #2
  19413. 8008d32: f104 0008 add.w r0, r4, #8
  19414. 8008d36: f7ff f96f bl 8008018 <RCCEx_PLL2_Config.part.0>
  19415. 8008d3a: 4605 mov r5, r0
  19416. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
  19417. 8008d3c: e9d4 3200 ldrd r3, r2, [r4]
  19418. if (ret == HAL_OK)
  19419. 8008d40: 2d00 cmp r5, #0
  19420. 8008d42: d1b6 bne.n 8008cb2 <HAL_RCCEx_PeriphCLKConfig+0xad2>
  19421. 8008d44: f7ff bb1a b.w 800837c <HAL_RCCEx_PeriphCLKConfig+0x19c>
  19422. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19423. 8008d48: 495f ldr r1, [pc, #380] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19424. 8008d4a: 6a89 ldr r1, [r1, #40] @ 0x28
  19425. 8008d4c: f001 0103 and.w r1, r1, #3
  19426. 8008d50: 2903 cmp r1, #3
  19427. 8008d52: f43f ad34 beq.w 80087be <HAL_RCCEx_PeriphCLKConfig+0x5de>
  19428. 8008d56: 2101 movs r1, #1
  19429. 8008d58: f104 0028 add.w r0, r4, #40 @ 0x28
  19430. 8008d5c: f7ff f9ce bl 80080fc <RCCEx_PLL3_Config.part.0>
  19431. 8008d60: 4605 mov r5, r0
  19432. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
  19433. 8008d62: e9d4 3200 ldrd r3, r2, [r4]
  19434. if (ret == HAL_OK)
  19435. 8008d66: 2d00 cmp r5, #0
  19436. 8008d68: d199 bne.n 8008c9e <HAL_RCCEx_PeriphCLKConfig+0xabe>
  19437. 8008d6a: e654 b.n 8008a16 <HAL_RCCEx_PeriphCLKConfig+0x836>
  19438. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19439. 8008d6c: 4956 ldr r1, [pc, #344] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19440. 8008d6e: 6a89 ldr r1, [r1, #40] @ 0x28
  19441. 8008d70: f001 0103 and.w r1, r1, #3
  19442. 8008d74: 2903 cmp r1, #3
  19443. 8008d76: f000 8155 beq.w 8009024 <HAL_RCCEx_PeriphCLKConfig+0xe44>
  19444. 8008d7a: 2102 movs r1, #2
  19445. 8008d7c: f104 0008 add.w r0, r4, #8
  19446. 8008d80: f7ff f94a bl 8008018 <RCCEx_PLL2_Config.part.0>
  19447. 8008d84: 4605 mov r5, r0
  19448. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
  19449. 8008d86: e9d4 3200 ldrd r3, r2, [r4]
  19450. if (ret == HAL_OK)
  19451. 8008d8a: 2d00 cmp r5, #0
  19452. 8008d8c: f47f abe3 bne.w 8008556 <HAL_RCCEx_PeriphCLKConfig+0x376>
  19453. 8008d90: e787 b.n 8008ca2 <HAL_RCCEx_PeriphCLKConfig+0xac2>
  19454. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19455. 8008d92: 494d ldr r1, [pc, #308] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19456. 8008d94: 6a89 ldr r1, [r1, #40] @ 0x28
  19457. 8008d96: f001 0103 and.w r1, r1, #3
  19458. 8008d9a: 2903 cmp r1, #3
  19459. 8008d9c: f43f abd0 beq.w 8008540 <HAL_RCCEx_PeriphCLKConfig+0x360>
  19460. 8008da0: 2101 movs r1, #1
  19461. 8008da2: f104 0028 add.w r0, r4, #40 @ 0x28
  19462. 8008da6: f7ff f9a9 bl 80080fc <RCCEx_PLL3_Config.part.0>
  19463. 8008daa: 4605 mov r5, r0
  19464. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
  19465. 8008dac: e9d4 3200 ldrd r3, r2, [r4]
  19466. if (ret == HAL_OK)
  19467. 8008db0: 2d00 cmp r5, #0
  19468. 8008db2: d1ad bne.n 8008d10 <HAL_RCCEx_PeriphCLKConfig+0xb30>
  19469. 8008db4: f7ff bb57 b.w 8008466 <HAL_RCCEx_PeriphCLKConfig+0x286>
  19470. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19471. 8008db8: 4943 ldr r1, [pc, #268] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19472. 8008dba: 6a89 ldr r1, [r1, #40] @ 0x28
  19473. 8008dbc: f001 0103 and.w r1, r1, #3
  19474. 8008dc0: 2903 cmp r1, #3
  19475. 8008dc2: f43f adda beq.w 800897a <HAL_RCCEx_PeriphCLKConfig+0x79a>
  19476. 8008dc6: 2102 movs r1, #2
  19477. 8008dc8: f104 0028 add.w r0, r4, #40 @ 0x28
  19478. 8008dcc: f7ff f996 bl 80080fc <RCCEx_PLL3_Config.part.0>
  19479. 8008dd0: 4605 mov r5, r0
  19480. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
  19481. 8008dd2: e9d4 3200 ldrd r3, r2, [r4]
  19482. if (ret == HAL_OK)
  19483. 8008dd6: 2d00 cmp r5, #0
  19484. 8008dd8: d19f bne.n 8008d1a <HAL_RCCEx_PeriphCLKConfig+0xb3a>
  19485. 8008dda: e459 b.n 8008690 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
  19486. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19487. 8008ddc: 493a ldr r1, [pc, #232] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19488. 8008dde: 6a89 ldr r1, [r1, #40] @ 0x28
  19489. 8008de0: f001 0103 and.w r1, r1, #3
  19490. 8008de4: 2903 cmp r1, #3
  19491. 8008de6: f43f add5 beq.w 8008994 <HAL_RCCEx_PeriphCLKConfig+0x7b4>
  19492. 8008dea: 2102 movs r1, #2
  19493. 8008dec: f104 0028 add.w r0, r4, #40 @ 0x28
  19494. 8008df0: f7ff f984 bl 80080fc <RCCEx_PLL3_Config.part.0>
  19495. 8008df4: 4605 mov r5, r0
  19496. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
  19497. 8008df6: e9d4 3200 ldrd r3, r2, [r4]
  19498. if (ret == HAL_OK)
  19499. 8008dfa: 2d00 cmp r5, #0
  19500. 8008dfc: f47f af78 bne.w 8008cf0 <HAL_RCCEx_PeriphCLKConfig+0xb10>
  19501. 8008e00: e46f b.n 80086e2 <HAL_RCCEx_PeriphCLKConfig+0x502>
  19502. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19503. 8008e02: 4931 ldr r1, [pc, #196] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19504. 8008e04: 6a89 ldr r1, [r1, #40] @ 0x28
  19505. 8008e06: f001 0103 and.w r1, r1, #3
  19506. 8008e0a: 2903 cmp r1, #3
  19507. 8008e0c: f43f ab8d beq.w 800852a <HAL_RCCEx_PeriphCLKConfig+0x34a>
  19508. 8008e10: 2101 movs r1, #1
  19509. 8008e12: f104 0028 add.w r0, r4, #40 @ 0x28
  19510. 8008e16: f7ff f971 bl 80080fc <RCCEx_PLL3_Config.part.0>
  19511. 8008e1a: 4605 mov r5, r0
  19512. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
  19513. 8008e1c: e9d4 3200 ldrd r3, r2, [r4]
  19514. if (ret == HAL_OK)
  19515. 8008e20: 2d00 cmp r5, #0
  19516. 8008e22: f47f af67 bne.w 8008cf4 <HAL_RCCEx_PeriphCLKConfig+0xb14>
  19517. 8008e26: f7ff baf9 b.w 800841c <HAL_RCCEx_PeriphCLKConfig+0x23c>
  19518. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19519. 8008e2a: 4927 ldr r1, [pc, #156] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19520. 8008e2c: 6a89 ldr r1, [r1, #40] @ 0x28
  19521. 8008e2e: f001 0103 and.w r1, r1, #3
  19522. 8008e32: 2903 cmp r1, #3
  19523. 8008e34: f43f adbb beq.w 80089ae <HAL_RCCEx_PeriphCLKConfig+0x7ce>
  19524. 8008e38: 2102 movs r1, #2
  19525. 8008e3a: f104 0028 add.w r0, r4, #40 @ 0x28
  19526. 8008e3e: f7ff f95d bl 80080fc <RCCEx_PLL3_Config.part.0>
  19527. 8008e42: 4605 mov r5, r0
  19528. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
  19529. 8008e44: e9d4 3200 ldrd r3, r2, [r4]
  19530. if (ret == HAL_OK)
  19531. 8008e48: 2d00 cmp r5, #0
  19532. 8008e4a: f47f af5f bne.w 8008d0c <HAL_RCCEx_PeriphCLKConfig+0xb2c>
  19533. 8008e4e: e471 b.n 8008734 <HAL_RCCEx_PeriphCLKConfig+0x554>
  19534. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19535. 8008e50: 491d ldr r1, [pc, #116] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19536. 8008e52: 6a89 ldr r1, [r1, #40] @ 0x28
  19537. 8008e54: f001 0103 and.w r1, r1, #3
  19538. 8008e58: 2903 cmp r1, #3
  19539. 8008e5a: f43f ab59 beq.w 8008510 <HAL_RCCEx_PeriphCLKConfig+0x330>
  19540. 8008e5e: 2100 movs r1, #0
  19541. 8008e60: f104 0028 add.w r0, r4, #40 @ 0x28
  19542. 8008e64: f7ff f94a bl 80080fc <RCCEx_PLL3_Config.part.0>
  19543. 8008e68: 4605 mov r5, r0
  19544. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
  19545. 8008e6a: e9d4 3200 ldrd r3, r2, [r4]
  19546. if (ret == HAL_OK)
  19547. 8008e6e: 2d00 cmp r5, #0
  19548. 8008e70: f47f af2b bne.w 8008cca <HAL_RCCEx_PeriphCLKConfig+0xaea>
  19549. 8008e74: f7ff baab b.w 80083ce <HAL_RCCEx_PeriphCLKConfig+0x1ee>
  19550. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19551. 8008e78: 4913 ldr r1, [pc, #76] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19552. 8008e7a: 6a89 ldr r1, [r1, #40] @ 0x28
  19553. 8008e7c: f001 0103 and.w r1, r1, #3
  19554. 8008e80: 2903 cmp r1, #3
  19555. 8008e82: f43f ab29 beq.w 80084d8 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
  19556. 8008e86: 2100 movs r1, #0
  19557. 8008e88: f104 0028 add.w r0, r4, #40 @ 0x28
  19558. 8008e8c: f7ff f936 bl 80080fc <RCCEx_PLL3_Config.part.0>
  19559. 8008e90: 4605 mov r5, r0
  19560. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
  19561. 8008e92: e9d4 3200 ldrd r3, r2, [r4]
  19562. if (ret == HAL_OK)
  19563. 8008e96: 2d00 cmp r5, #0
  19564. 8008e98: f47f af11 bne.w 8008cbe <HAL_RCCEx_PeriphCLKConfig+0xade>
  19565. 8008e9c: f7ff ba27 b.w 80082ee <HAL_RCCEx_PeriphCLKConfig+0x10e>
  19566. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19567. 8008ea0: 4909 ldr r1, [pc, #36] @ (8008ec8 <HAL_RCCEx_PeriphCLKConfig+0xce8>)
  19568. 8008ea2: 6a89 ldr r1, [r1, #40] @ 0x28
  19569. 8008ea4: f001 0103 and.w r1, r1, #3
  19570. 8008ea8: 2903 cmp r1, #3
  19571. 8008eaa: f43f ae05 beq.w 8008ab8 <HAL_RCCEx_PeriphCLKConfig+0x8d8>
  19572. 8008eae: 2102 movs r1, #2
  19573. 8008eb0: 3028 adds r0, #40 @ 0x28
  19574. 8008eb2: f7ff f923 bl 80080fc <RCCEx_PLL3_Config.part.0>
  19575. 8008eb6: 4606 mov r6, r0
  19576. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
  19577. 8008eb8: e9d4 3200 ldrd r3, r2, [r4]
  19578. if (ret == HAL_OK)
  19579. 8008ebc: 2e00 cmp r6, #0
  19580. 8008ebe: f47f a9be bne.w 800823e <HAL_RCCEx_PeriphCLKConfig+0x5e>
  19581. __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
  19582. 8008ec2: 6ea1 ldr r1, [r4, #104] @ 0x68
  19583. 8008ec4: f7ff b9b4 b.w 8008230 <HAL_RCCEx_PeriphCLKConfig+0x50>
  19584. 8008ec8: 58024400 .word 0x58024400
  19585. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19586. 8008ecc: 4969 ldr r1, [pc, #420] @ (8009074 <HAL_RCCEx_PeriphCLKConfig+0xe94>)
  19587. 8008ece: 6a89 ldr r1, [r1, #40] @ 0x28
  19588. 8008ed0: f001 0103 and.w r1, r1, #3
  19589. 8008ed4: 2903 cmp r1, #3
  19590. 8008ed6: f43f ab0a beq.w 80084ee <HAL_RCCEx_PeriphCLKConfig+0x30e>
  19591. 8008eda: 2100 movs r1, #0
  19592. 8008edc: f104 0028 add.w r0, r4, #40 @ 0x28
  19593. 8008ee0: f7ff f90c bl 80080fc <RCCEx_PLL3_Config.part.0>
  19594. 8008ee4: 4605 mov r5, r0
  19595. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
  19596. 8008ee6: e9d4 3200 ldrd r3, r2, [r4]
  19597. if (ret == HAL_OK)
  19598. 8008eea: 2d00 cmp r5, #0
  19599. 8008eec: f47f aeea bne.w 8008cc4 <HAL_RCCEx_PeriphCLKConfig+0xae4>
  19600. 8008ef0: f7ff ba28 b.w 8008344 <HAL_RCCEx_PeriphCLKConfig+0x164>
  19601. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19602. 8008ef4: 495f ldr r1, [pc, #380] @ (8009074 <HAL_RCCEx_PeriphCLKConfig+0xe94>)
  19603. 8008ef6: 6a89 ldr r1, [r1, #40] @ 0x28
  19604. 8008ef8: f001 0103 and.w r1, r1, #3
  19605. 8008efc: 2903 cmp r1, #3
  19606. 8008efe: f43f aadd beq.w 80084bc <HAL_RCCEx_PeriphCLKConfig+0x2dc>
  19607. 8008f02: 2100 movs r1, #0
  19608. 8008f04: f104 0028 add.w r0, r4, #40 @ 0x28
  19609. 8008f08: f7ff f8f8 bl 80080fc <RCCEx_PLL3_Config.part.0>
  19610. 8008f0c: 4605 mov r5, r0
  19611. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
  19612. 8008f0e: e9d4 3200 ldrd r3, r2, [r4]
  19613. if (ret == HAL_OK)
  19614. 8008f12: 2d00 cmp r5, #0
  19615. 8008f14: f47f aed0 bne.w 8008cb8 <HAL_RCCEx_PeriphCLKConfig+0xad8>
  19616. 8008f18: f7ff b9bf b.w 800829a <HAL_RCCEx_PeriphCLKConfig+0xba>
  19617. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19618. 8008f1c: 4955 ldr r1, [pc, #340] @ (8009074 <HAL_RCCEx_PeriphCLKConfig+0xe94>)
  19619. 8008f1e: 6a89 ldr r1, [r1, #40] @ 0x28
  19620. 8008f20: f001 0103 and.w r1, r1, #3
  19621. 8008f24: 2903 cmp r1, #3
  19622. 8008f26: f43f a996 beq.w 8008256 <HAL_RCCEx_PeriphCLKConfig+0x76>
  19623. 8008f2a: 2100 movs r1, #0
  19624. 8008f2c: f104 0008 add.w r0, r4, #8
  19625. 8008f30: f7ff f872 bl 8008018 <RCCEx_PLL2_Config.part.0>
  19626. 8008f34: 4605 mov r5, r0
  19627. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
  19628. 8008f36: e9d4 3200 ldrd r3, r2, [r4]
  19629. if (ret == HAL_OK)
  19630. 8008f3a: 2d00 cmp r5, #0
  19631. 8008f3c: f43f ae13 beq.w 8008b66 <HAL_RCCEx_PeriphCLKConfig+0x986>
  19632. 8008f40: 462e mov r6, r5
  19633. 8008f42: f7ff b98a b.w 800825a <HAL_RCCEx_PeriphCLKConfig+0x7a>
  19634. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19635. 8008f46: 494b ldr r1, [pc, #300] @ (8009074 <HAL_RCCEx_PeriphCLKConfig+0xe94>)
  19636. 8008f48: 6a89 ldr r1, [r1, #40] @ 0x28
  19637. 8008f4a: f001 0103 and.w r1, r1, #3
  19638. 8008f4e: 2903 cmp r1, #3
  19639. 8008f50: f43f a981 beq.w 8008256 <HAL_RCCEx_PeriphCLKConfig+0x76>
  19640. 8008f54: 2100 movs r1, #0
  19641. 8008f56: f104 0028 add.w r0, r4, #40 @ 0x28
  19642. 8008f5a: f7ff f8cf bl 80080fc <RCCEx_PLL3_Config.part.0>
  19643. 8008f5e: 4605 mov r5, r0
  19644. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
  19645. 8008f60: e9d4 3200 ldrd r3, r2, [r4]
  19646. break;
  19647. 8008f64: e5fc b.n 8008b60 <HAL_RCCEx_PeriphCLKConfig+0x980>
  19648. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19649. 8008f66: 4943 ldr r1, [pc, #268] @ (8009074 <HAL_RCCEx_PeriphCLKConfig+0xe94>)
  19650. 8008f68: 6a89 ldr r1, [r1, #40] @ 0x28
  19651. 8008f6a: f001 0103 and.w r1, r1, #3
  19652. 8008f6e: 2903 cmp r1, #3
  19653. 8008f70: d03d beq.n 8008fee <HAL_RCCEx_PeriphCLKConfig+0xe0e>
  19654. 8008f72: 2101 movs r1, #1
  19655. 8008f74: f104 0028 add.w r0, r4, #40 @ 0x28
  19656. 8008f78: f7ff f8c0 bl 80080fc <RCCEx_PLL3_Config.part.0>
  19657. 8008f7c: 4605 mov r5, r0
  19658. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
  19659. 8008f7e: e9d4 3200 ldrd r3, r2, [r4]
  19660. if (ret == HAL_OK)
  19661. 8008f82: 2d00 cmp r5, #0
  19662. 8008f84: f47f ab3d bne.w 8008602 <HAL_RCCEx_PeriphCLKConfig+0x422>
  19663. 8008f88: e6aa b.n 8008ce0 <HAL_RCCEx_PeriphCLKConfig+0xb00>
  19664. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19665. 8008f8a: 493a ldr r1, [pc, #232] @ (8009074 <HAL_RCCEx_PeriphCLKConfig+0xe94>)
  19666. 8008f8c: 6a89 ldr r1, [r1, #40] @ 0x28
  19667. 8008f8e: f001 0103 and.w r1, r1, #3
  19668. 8008f92: 2903 cmp r1, #3
  19669. 8008f94: d02f beq.n 8008ff6 <HAL_RCCEx_PeriphCLKConfig+0xe16>
  19670. 8008f96: 2101 movs r1, #1
  19671. 8008f98: f104 0028 add.w r0, r4, #40 @ 0x28
  19672. 8008f9c: f7ff f8ae bl 80080fc <RCCEx_PLL3_Config.part.0>
  19673. 8008fa0: 4605 mov r5, r0
  19674. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
  19675. 8008fa2: e9d4 3200 ldrd r3, r2, [r4]
  19676. if (ret == HAL_OK)
  19677. 8008fa6: 2d00 cmp r5, #0
  19678. 8008fa8: f47f ab50 bne.w 800864c <HAL_RCCEx_PeriphCLKConfig+0x46c>
  19679. 8008fac: e6a5 b.n 8008cfa <HAL_RCCEx_PeriphCLKConfig+0xb1a>
  19680. if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
  19681. 8008fae: 4931 ldr r1, [pc, #196] @ (8009074 <HAL_RCCEx_PeriphCLKConfig+0xe94>)
  19682. 8008fb0: 6a89 ldr r1, [r1, #40] @ 0x28
  19683. 8008fb2: f001 0103 and.w r1, r1, #3
  19684. 8008fb6: 2903 cmp r1, #3
  19685. 8008fb8: f43f ab01 beq.w 80085be <HAL_RCCEx_PeriphCLKConfig+0x3de>
  19686. 8008fbc: 2101 movs r1, #1
  19687. 8008fbe: f104 0028 add.w r0, r4, #40 @ 0x28
  19688. 8008fc2: f7ff f89b bl 80080fc <RCCEx_PLL3_Config.part.0>
  19689. 8008fc6: 4605 mov r5, r0
  19690. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
  19691. 8008fc8: e9d4 3200 ldrd r3, r2, [r4]
  19692. if (ret == HAL_OK)
  19693. 8008fcc: 2d00 cmp r5, #0
  19694. 8008fce: f47f aea6 bne.w 8008d1e <HAL_RCCEx_PeriphCLKConfig+0xb3e>
  19695. 8008fd2: e569 b.n 8008aa8 <HAL_RCCEx_PeriphCLKConfig+0x8c8>
  19696. ret = HAL_TIMEOUT;
  19697. 8008fd4: 2503 movs r5, #3
  19698. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
  19699. 8008fd6: 462e mov r6, r5
  19700. 8008fd8: e9d4 3200 ldrd r3, r2, [r4]
  19701. 8008fdc: f7ff babf b.w 800855e <HAL_RCCEx_PeriphCLKConfig+0x37e>
  19702. __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
  19703. 8008fe0: 4d24 ldr r5, [pc, #144] @ (8009074 <HAL_RCCEx_PeriphCLKConfig+0xe94>)
  19704. 8008fe2: 6ae8 ldr r0, [r5, #44] @ 0x2c
  19705. 8008fe4: f440 3000 orr.w r0, r0, #131072 @ 0x20000
  19706. 8008fe8: 62e8 str r0, [r5, #44] @ 0x2c
  19707. if (ret == HAL_OK)
  19708. 8008fea: f7ff b921 b.w 8008230 <HAL_RCCEx_PeriphCLKConfig+0x50>
  19709. 8008fee: 2601 movs r6, #1
  19710. 8008ff0: 4635 mov r5, r6
  19711. 8008ff2: f7ff bb07 b.w 8008604 <HAL_RCCEx_PeriphCLKConfig+0x424>
  19712. 8008ff6: 2601 movs r6, #1
  19713. 8008ff8: 4635 mov r5, r6
  19714. 8008ffa: f7ff bb28 b.w 800864e <HAL_RCCEx_PeriphCLKConfig+0x46e>
  19715. status = HAL_ERROR;
  19716. 8008ffe: 2601 movs r6, #1
  19717. 8009000: f7ff bbb6 b.w 8008770 <HAL_RCCEx_PeriphCLKConfig+0x590>
  19718. status = HAL_ERROR;
  19719. 8009004: 2601 movs r6, #1
  19720. 8009006: f7ff bba5 b.w 8008754 <HAL_RCCEx_PeriphCLKConfig+0x574>
  19721. __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
  19722. 800900a: f8d4 0084 ldr.w r0, [r4, #132] @ 0x84
  19723. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
  19724. 800900e: e9d4 3200 ldrd r3, r2, [r4]
  19725. 8009012: f7ff bb9f b.w 8008754 <HAL_RCCEx_PeriphCLKConfig+0x574>
  19726. __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
  19727. 8009016: f8d4 0098 ldr.w r0, [r4, #152] @ 0x98
  19728. status = HAL_ERROR;
  19729. 800901a: 2601 movs r6, #1
  19730. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
  19731. 800901c: e9d4 3200 ldrd r3, r2, [r4]
  19732. 8009020: f7ff bba6 b.w 8008770 <HAL_RCCEx_PeriphCLKConfig+0x590>
  19733. 8009024: 2601 movs r6, #1
  19734. 8009026: 4635 mov r5, r6
  19735. 8009028: f7ff ba96 b.w 8008558 <HAL_RCCEx_PeriphCLKConfig+0x378>
  19736. tickstart = HAL_GetTick();
  19737. 800902c: f7fa ffd0 bl 8003fd0 <HAL_GetTick>
  19738. while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
  19739. 8009030: f8df 8040 ldr.w r8, [pc, #64] @ 8009074 <HAL_RCCEx_PeriphCLKConfig+0xe94>
  19740. tickstart = HAL_GetTick();
  19741. 8009034: 4607 mov r7, r0
  19742. if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
  19743. 8009036: f241 3988 movw r9, #5000 @ 0x1388
  19744. while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
  19745. 800903a: e004 b.n 8009046 <HAL_RCCEx_PeriphCLKConfig+0xe66>
  19746. if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
  19747. 800903c: f7fa ffc8 bl 8003fd0 <HAL_GetTick>
  19748. 8009040: 1bc0 subs r0, r0, r7
  19749. 8009042: 4548 cmp r0, r9
  19750. 8009044: d810 bhi.n 8009068 <HAL_RCCEx_PeriphCLKConfig+0xe88>
  19751. while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
  19752. 8009046: f8d8 3070 ldr.w r3, [r8, #112] @ 0x70
  19753. 800904a: 079b lsls r3, r3, #30
  19754. 800904c: d5f6 bpl.n 800903c <HAL_RCCEx_PeriphCLKConfig+0xe5c>
  19755. __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
  19756. 800904e: f8d4 30b4 ldr.w r3, [r4, #180] @ 0xb4
  19757. 8009052: e562 b.n 8008b1a <HAL_RCCEx_PeriphCLKConfig+0x93a>
  19758. 8009054: 4807 ldr r0, [pc, #28] @ (8009074 <HAL_RCCEx_PeriphCLKConfig+0xe94>)
  19759. 8009056: 4a08 ldr r2, [pc, #32] @ (8009078 <HAL_RCCEx_PeriphCLKConfig+0xe98>)
  19760. 8009058: 6901 ldr r1, [r0, #16]
  19761. 800905a: ea02 1213 and.w r2, r2, r3, lsr #4
  19762. 800905e: f421 517c bic.w r1, r1, #16128 @ 0x3f00
  19763. 8009062: 430a orrs r2, r1
  19764. 8009064: 6102 str r2, [r0, #16]
  19765. 8009066: e563 b.n 8008b30 <HAL_RCCEx_PeriphCLKConfig+0x950>
  19766. status = ret;
  19767. 8009068: 2603 movs r6, #3
  19768. if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
  19769. 800906a: e9d4 3200 ldrd r3, r2, [r4]
  19770. 800906e: 4635 mov r5, r6
  19771. 8009070: f7ff ba75 b.w 800855e <HAL_RCCEx_PeriphCLKConfig+0x37e>
  19772. 8009074: 58024400 .word 0x58024400
  19773. 8009078: 00ffffcf .word 0x00ffffcf
  19774. 0800907c <HAL_RCCEx_GetD3PCLK1Freq>:
  19775. {
  19776. 800907c: b508 push {r3, lr}
  19777. return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
  19778. 800907e: f7fe fecf bl 8007e20 <HAL_RCC_GetHCLKFreq>
  19779. 8009082: 4b05 ldr r3, [pc, #20] @ (8009098 <HAL_RCCEx_GetD3PCLK1Freq+0x1c>)
  19780. 8009084: 4a05 ldr r2, [pc, #20] @ (800909c <HAL_RCCEx_GetD3PCLK1Freq+0x20>)
  19781. 8009086: 6a1b ldr r3, [r3, #32]
  19782. 8009088: f3c3 1302 ubfx r3, r3, #4, #3
  19783. 800908c: 5cd3 ldrb r3, [r2, r3]
  19784. 800908e: f003 031f and.w r3, r3, #31
  19785. }
  19786. 8009092: 40d8 lsrs r0, r3
  19787. 8009094: bd08 pop {r3, pc}
  19788. 8009096: bf00 nop
  19789. 8009098: 58024400 .word 0x58024400
  19790. 800909c: 08011a14 .word 0x08011a14
  19791. 080090a0 <HAL_RCCEx_GetPLL2ClockFreq>:
  19792. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  19793. 80090a0: 4a47 ldr r2, [pc, #284] @ (80091c0 <HAL_RCCEx_GetPLL2ClockFreq+0x120>)
  19794. {
  19795. 80090a2: b470 push {r4, r5, r6}
  19796. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  19797. 80090a4: 6a91 ldr r1, [r2, #40] @ 0x28
  19798. pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12);
  19799. 80090a6: 6a95 ldr r5, [r2, #40] @ 0x28
  19800. pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
  19801. 80090a8: 6ad6 ldr r6, [r2, #44] @ 0x2c
  19802. if (pll2m != 0U)
  19803. 80090aa: f415 3f7c tst.w r5, #258048 @ 0x3f000
  19804. pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12);
  19805. 80090ae: f3c5 3305 ubfx r3, r5, #12, #6
  19806. fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
  19807. 80090b2: 6bd4 ldr r4, [r2, #60] @ 0x3c
  19808. if (pll2m != 0U)
  19809. 80090b4: d05b beq.n 800916e <HAL_RCCEx_GetPLL2ClockFreq+0xce>
  19810. fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
  19811. 80090b6: f3c4 04cc ubfx r4, r4, #3, #13
  19812. pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
  19813. 80090ba: f3c6 1600 ubfx r6, r6, #4, #1
  19814. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  19815. 80090be: f001 0103 and.w r1, r1, #3
  19816. pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
  19817. 80090c2: ee07 3a90 vmov s15, r3
  19818. fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
  19819. 80090c6: fb06 f404 mul.w r4, r6, r4
  19820. switch (pllsource)
  19821. 80090ca: 2901 cmp r1, #1
  19822. pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
  19823. 80090cc: eeb8 7ae7 vcvt.f32.s32 s14, s15
  19824. 80090d0: ee06 4a90 vmov s13, r4
  19825. 80090d4: eefa 6ae9 vcvt.f32.s32 s13, s13, #13
  19826. switch (pllsource)
  19827. 80090d8: d003 beq.n 80090e2 <HAL_RCCEx_GetPLL2ClockFreq+0x42>
  19828. 80090da: 2902 cmp r1, #2
  19829. 80090dc: d06a beq.n 80091b4 <HAL_RCCEx_GetPLL2ClockFreq+0x114>
  19830. 80090de: 2900 cmp r1, #0
  19831. 80090e0: d04a beq.n 8009178 <HAL_RCCEx_GetPLL2ClockFreq+0xd8>
  19832. pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
  19833. 80090e2: eddf 7a38 vldr s15, [pc, #224] @ 80091c4 <HAL_RCCEx_GetPLL2ClockFreq+0x124>
  19834. 80090e6: ee87 6a87 vdiv.f32 s12, s15, s14
  19835. 80090ea: 6b93 ldr r3, [r2, #56] @ 0x38
  19836. 80090ec: f3c3 0308 ubfx r3, r3, #0, #9
  19837. 80090f0: ee07 3a90 vmov s15, r3
  19838. 80090f4: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
  19839. 80090f8: eef8 7ae7 vcvt.f32.s32 s15, s15
  19840. 80090fc: ee77 7aa5 vadd.f32 s15, s15, s11
  19841. 8009100: ee77 7aa6 vadd.f32 s15, s15, s13
  19842. 8009104: ee67 7a86 vmul.f32 s15, s15, s12
  19843. PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ;
  19844. 8009108: 4a2d ldr r2, [pc, #180] @ (80091c0 <HAL_RCCEx_GetPLL2ClockFreq+0x120>)
  19845. 800910a: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0
  19846. 800910e: 6b93 ldr r3, [r2, #56] @ 0x38
  19847. 8009110: f3c3 2346 ubfx r3, r3, #9, #7
  19848. 8009114: ee07 3a10 vmov s14, r3
  19849. 8009118: eeb8 7ac7 vcvt.f32.s32 s14, s14
  19850. }
  19851. 800911c: bc70 pop {r4, r5, r6}
  19852. PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ;
  19853. 800911e: ee37 7a06 vadd.f32 s14, s14, s12
  19854. 8009122: eec7 6a87 vdiv.f32 s13, s15, s14
  19855. 8009126: eefc 6ae6 vcvt.u32.f32 s13, s13
  19856. 800912a: edc0 6a00 vstr s13, [r0]
  19857. PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ;
  19858. 800912e: 6b93 ldr r3, [r2, #56] @ 0x38
  19859. 8009130: f3c3 4306 ubfx r3, r3, #16, #7
  19860. 8009134: ee07 3a10 vmov s14, r3
  19861. 8009138: eeb8 7ac7 vcvt.f32.s32 s14, s14
  19862. 800913c: ee37 7a06 vadd.f32 s14, s14, s12
  19863. 8009140: eec7 6a87 vdiv.f32 s13, s15, s14
  19864. 8009144: eefc 6ae6 vcvt.u32.f32 s13, s13
  19865. 8009148: edc0 6a01 vstr s13, [r0, #4]
  19866. PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ;
  19867. 800914c: 6b93 ldr r3, [r2, #56] @ 0x38
  19868. 800914e: f3c3 6306 ubfx r3, r3, #24, #7
  19869. 8009152: ee06 3a90 vmov s13, r3
  19870. 8009156: eef8 6ae6 vcvt.f32.s32 s13, s13
  19871. 800915a: ee76 6a86 vadd.f32 s13, s13, s12
  19872. 800915e: ee87 7aa6 vdiv.f32 s14, s15, s13
  19873. 8009162: eefc 7ac7 vcvt.u32.f32 s15, s14
  19874. 8009166: ee17 3a90 vmov r3, s15
  19875. 800916a: 6083 str r3, [r0, #8]
  19876. }
  19877. 800916c: 4770 bx lr
  19878. 800916e: bc70 pop {r4, r5, r6}
  19879. PLL2_Clocks->PLL2_P_Frequency = 0U;
  19880. 8009170: e9c0 3300 strd r3, r3, [r0]
  19881. PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ;
  19882. 8009174: 6083 str r3, [r0, #8]
  19883. }
  19884. 8009176: 4770 bx lr
  19885. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  19886. 8009178: 6813 ldr r3, [r2, #0]
  19887. 800917a: 069b lsls r3, r3, #26
  19888. 800917c: d51d bpl.n 80091ba <HAL_RCCEx_GetPLL2ClockFreq+0x11a>
  19889. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  19890. 800917e: 6814 ldr r4, [r2, #0]
  19891. pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
  19892. 8009180: eef7 7a00 vmov.f32 s15, #112 @ 0x3f800000 1.0
  19893. 8009184: 6b93 ldr r3, [r2, #56] @ 0x38
  19894. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  19895. 8009186: 4910 ldr r1, [pc, #64] @ (80091c8 <HAL_RCCEx_GetPLL2ClockFreq+0x128>)
  19896. 8009188: f3c4 02c1 ubfx r2, r4, #3, #2
  19897. pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
  19898. 800918c: f3c3 0308 ubfx r3, r3, #0, #9
  19899. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  19900. 8009190: 40d1 lsrs r1, r2
  19901. pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
  19902. 8009192: ee06 3a10 vmov s12, r3
  19903. 8009196: ee05 1a90 vmov s11, r1
  19904. 800919a: eeb8 6ac6 vcvt.f32.s32 s12, s12
  19905. 800919e: eef8 5ae5 vcvt.f32.s32 s11, s11
  19906. 80091a2: ee36 6a27 vadd.f32 s12, s12, s15
  19907. 80091a6: eec5 7a87 vdiv.f32 s15, s11, s14
  19908. 80091aa: ee36 7a26 vadd.f32 s14, s12, s13
  19909. 80091ae: ee67 7a87 vmul.f32 s15, s15, s14
  19910. 80091b2: e7a9 b.n 8009108 <HAL_RCCEx_GetPLL2ClockFreq+0x68>
  19911. pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
  19912. 80091b4: eddf 7a05 vldr s15, [pc, #20] @ 80091cc <HAL_RCCEx_GetPLL2ClockFreq+0x12c>
  19913. 80091b8: e795 b.n 80090e6 <HAL_RCCEx_GetPLL2ClockFreq+0x46>
  19914. pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
  19915. 80091ba: eddf 7a05 vldr s15, [pc, #20] @ 80091d0 <HAL_RCCEx_GetPLL2ClockFreq+0x130>
  19916. 80091be: e792 b.n 80090e6 <HAL_RCCEx_GetPLL2ClockFreq+0x46>
  19917. 80091c0: 58024400 .word 0x58024400
  19918. 80091c4: 4a742400 .word 0x4a742400
  19919. 80091c8: 03d09000 .word 0x03d09000
  19920. 80091cc: 4bbebc20 .word 0x4bbebc20
  19921. 80091d0: 4c742400 .word 0x4c742400
  19922. 080091d4 <HAL_RCCEx_GetPLL3ClockFreq>:
  19923. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  19924. 80091d4: 4a47 ldr r2, [pc, #284] @ (80092f4 <HAL_RCCEx_GetPLL3ClockFreq+0x120>)
  19925. {
  19926. 80091d6: b470 push {r4, r5, r6}
  19927. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  19928. 80091d8: 6a91 ldr r1, [r2, #40] @ 0x28
  19929. pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ;
  19930. 80091da: 6a95 ldr r5, [r2, #40] @ 0x28
  19931. pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
  19932. 80091dc: 6ad6 ldr r6, [r2, #44] @ 0x2c
  19933. if (pll3m != 0U)
  19934. 80091de: f015 7f7c tst.w r5, #66060288 @ 0x3f00000
  19935. pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ;
  19936. 80091e2: f3c5 5305 ubfx r3, r5, #20, #6
  19937. fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
  19938. 80091e6: 6c54 ldr r4, [r2, #68] @ 0x44
  19939. if (pll3m != 0U)
  19940. 80091e8: d05b beq.n 80092a2 <HAL_RCCEx_GetPLL3ClockFreq+0xce>
  19941. fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
  19942. 80091ea: f3c4 04cc ubfx r4, r4, #3, #13
  19943. pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
  19944. 80091ee: f3c6 2600 ubfx r6, r6, #8, #1
  19945. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  19946. 80091f2: f001 0103 and.w r1, r1, #3
  19947. pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
  19948. 80091f6: ee07 3a90 vmov s15, r3
  19949. fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
  19950. 80091fa: fb06 f404 mul.w r4, r6, r4
  19951. switch (pllsource)
  19952. 80091fe: 2901 cmp r1, #1
  19953. pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
  19954. 8009200: eeb8 7ae7 vcvt.f32.s32 s14, s15
  19955. 8009204: ee06 4a90 vmov s13, r4
  19956. 8009208: eefa 6ae9 vcvt.f32.s32 s13, s13, #13
  19957. switch (pllsource)
  19958. 800920c: d003 beq.n 8009216 <HAL_RCCEx_GetPLL3ClockFreq+0x42>
  19959. 800920e: 2902 cmp r1, #2
  19960. 8009210: d06a beq.n 80092e8 <HAL_RCCEx_GetPLL3ClockFreq+0x114>
  19961. 8009212: 2900 cmp r1, #0
  19962. 8009214: d04a beq.n 80092ac <HAL_RCCEx_GetPLL3ClockFreq+0xd8>
  19963. pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
  19964. 8009216: eddf 7a38 vldr s15, [pc, #224] @ 80092f8 <HAL_RCCEx_GetPLL3ClockFreq+0x124>
  19965. 800921a: ee87 6a87 vdiv.f32 s12, s15, s14
  19966. 800921e: 6c13 ldr r3, [r2, #64] @ 0x40
  19967. 8009220: f3c3 0308 ubfx r3, r3, #0, #9
  19968. 8009224: ee07 3a90 vmov s15, r3
  19969. 8009228: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
  19970. 800922c: eef8 7ae7 vcvt.f32.s32 s15, s15
  19971. 8009230: ee77 7aa5 vadd.f32 s15, s15, s11
  19972. 8009234: ee77 7aa6 vadd.f32 s15, s15, s13
  19973. 8009238: ee67 7a86 vmul.f32 s15, s15, s12
  19974. PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ;
  19975. 800923c: 4a2d ldr r2, [pc, #180] @ (80092f4 <HAL_RCCEx_GetPLL3ClockFreq+0x120>)
  19976. 800923e: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0
  19977. 8009242: 6c13 ldr r3, [r2, #64] @ 0x40
  19978. 8009244: f3c3 2346 ubfx r3, r3, #9, #7
  19979. 8009248: ee07 3a10 vmov s14, r3
  19980. 800924c: eeb8 7ac7 vcvt.f32.s32 s14, s14
  19981. }
  19982. 8009250: bc70 pop {r4, r5, r6}
  19983. PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ;
  19984. 8009252: ee37 7a06 vadd.f32 s14, s14, s12
  19985. 8009256: eec7 6a87 vdiv.f32 s13, s15, s14
  19986. 800925a: eefc 6ae6 vcvt.u32.f32 s13, s13
  19987. 800925e: edc0 6a00 vstr s13, [r0]
  19988. PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ;
  19989. 8009262: 6c13 ldr r3, [r2, #64] @ 0x40
  19990. 8009264: f3c3 4306 ubfx r3, r3, #16, #7
  19991. 8009268: ee07 3a10 vmov s14, r3
  19992. 800926c: eeb8 7ac7 vcvt.f32.s32 s14, s14
  19993. 8009270: ee37 7a06 vadd.f32 s14, s14, s12
  19994. 8009274: eec7 6a87 vdiv.f32 s13, s15, s14
  19995. 8009278: eefc 6ae6 vcvt.u32.f32 s13, s13
  19996. 800927c: edc0 6a01 vstr s13, [r0, #4]
  19997. PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ;
  19998. 8009280: 6c13 ldr r3, [r2, #64] @ 0x40
  19999. 8009282: f3c3 6306 ubfx r3, r3, #24, #7
  20000. 8009286: ee06 3a90 vmov s13, r3
  20001. 800928a: eef8 6ae6 vcvt.f32.s32 s13, s13
  20002. 800928e: ee76 6a86 vadd.f32 s13, s13, s12
  20003. 8009292: ee87 7aa6 vdiv.f32 s14, s15, s13
  20004. 8009296: eefc 7ac7 vcvt.u32.f32 s15, s14
  20005. 800929a: ee17 3a90 vmov r3, s15
  20006. 800929e: 6083 str r3, [r0, #8]
  20007. }
  20008. 80092a0: 4770 bx lr
  20009. 80092a2: bc70 pop {r4, r5, r6}
  20010. PLL3_Clocks->PLL3_P_Frequency = 0U;
  20011. 80092a4: e9c0 3300 strd r3, r3, [r0]
  20012. PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ;
  20013. 80092a8: 6083 str r3, [r0, #8]
  20014. }
  20015. 80092aa: 4770 bx lr
  20016. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  20017. 80092ac: 6813 ldr r3, [r2, #0]
  20018. 80092ae: 069b lsls r3, r3, #26
  20019. 80092b0: d51d bpl.n 80092ee <HAL_RCCEx_GetPLL3ClockFreq+0x11a>
  20020. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  20021. 80092b2: 6814 ldr r4, [r2, #0]
  20022. pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
  20023. 80092b4: eef7 7a00 vmov.f32 s15, #112 @ 0x3f800000 1.0
  20024. 80092b8: 6c13 ldr r3, [r2, #64] @ 0x40
  20025. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  20026. 80092ba: 4910 ldr r1, [pc, #64] @ (80092fc <HAL_RCCEx_GetPLL3ClockFreq+0x128>)
  20027. 80092bc: f3c4 02c1 ubfx r2, r4, #3, #2
  20028. pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
  20029. 80092c0: f3c3 0308 ubfx r3, r3, #0, #9
  20030. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  20031. 80092c4: 40d1 lsrs r1, r2
  20032. pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
  20033. 80092c6: ee06 3a10 vmov s12, r3
  20034. 80092ca: ee05 1a90 vmov s11, r1
  20035. 80092ce: eeb8 6ac6 vcvt.f32.s32 s12, s12
  20036. 80092d2: eef8 5ae5 vcvt.f32.s32 s11, s11
  20037. 80092d6: ee36 6a27 vadd.f32 s12, s12, s15
  20038. 80092da: eec5 7a87 vdiv.f32 s15, s11, s14
  20039. 80092de: ee36 7a26 vadd.f32 s14, s12, s13
  20040. 80092e2: ee67 7a87 vmul.f32 s15, s15, s14
  20041. 80092e6: e7a9 b.n 800923c <HAL_RCCEx_GetPLL3ClockFreq+0x68>
  20042. pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
  20043. 80092e8: eddf 7a05 vldr s15, [pc, #20] @ 8009300 <HAL_RCCEx_GetPLL3ClockFreq+0x12c>
  20044. 80092ec: e795 b.n 800921a <HAL_RCCEx_GetPLL3ClockFreq+0x46>
  20045. pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
  20046. 80092ee: eddf 7a05 vldr s15, [pc, #20] @ 8009304 <HAL_RCCEx_GetPLL3ClockFreq+0x130>
  20047. 80092f2: e792 b.n 800921a <HAL_RCCEx_GetPLL3ClockFreq+0x46>
  20048. 80092f4: 58024400 .word 0x58024400
  20049. 80092f8: 4a742400 .word 0x4a742400
  20050. 80092fc: 03d09000 .word 0x03d09000
  20051. 8009300: 4bbebc20 .word 0x4bbebc20
  20052. 8009304: 4c742400 .word 0x4c742400
  20053. 08009308 <HAL_RCCEx_GetPLL1ClockFreq>:
  20054. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  20055. 8009308: 4a47 ldr r2, [pc, #284] @ (8009428 <HAL_RCCEx_GetPLL1ClockFreq+0x120>)
  20056. {
  20057. 800930a: b470 push {r4, r5, r6}
  20058. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  20059. 800930c: 6a91 ldr r1, [r2, #40] @ 0x28
  20060. pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
  20061. 800930e: 6a95 ldr r5, [r2, #40] @ 0x28
  20062. pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
  20063. 8009310: 6ad6 ldr r6, [r2, #44] @ 0x2c
  20064. if (pll1m != 0U)
  20065. 8009312: f415 7f7c tst.w r5, #1008 @ 0x3f0
  20066. pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
  20067. 8009316: f3c5 1305 ubfx r3, r5, #4, #6
  20068. fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
  20069. 800931a: 6b54 ldr r4, [r2, #52] @ 0x34
  20070. if (pll1m != 0U)
  20071. 800931c: d05b beq.n 80093d6 <HAL_RCCEx_GetPLL1ClockFreq+0xce>
  20072. fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
  20073. 800931e: f3c4 04cc ubfx r4, r4, #3, #13
  20074. pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
  20075. 8009322: f006 0601 and.w r6, r6, #1
  20076. pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
  20077. 8009326: f001 0103 and.w r1, r1, #3
  20078. pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  20079. 800932a: ee07 3a90 vmov s15, r3
  20080. fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
  20081. 800932e: fb06 f404 mul.w r4, r6, r4
  20082. switch (pllsource)
  20083. 8009332: 2901 cmp r1, #1
  20084. pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  20085. 8009334: eeb8 7ae7 vcvt.f32.s32 s14, s15
  20086. 8009338: ee06 4a90 vmov s13, r4
  20087. 800933c: eefa 6ae9 vcvt.f32.s32 s13, s13, #13
  20088. switch (pllsource)
  20089. 8009340: d06f beq.n 8009422 <HAL_RCCEx_GetPLL1ClockFreq+0x11a>
  20090. 8009342: 2902 cmp r1, #2
  20091. 8009344: d06a beq.n 800941c <HAL_RCCEx_GetPLL1ClockFreq+0x114>
  20092. 8009346: 2900 cmp r1, #0
  20093. 8009348: d04a beq.n 80093e0 <HAL_RCCEx_GetPLL1ClockFreq+0xd8>
  20094. pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  20095. 800934a: eddf 7a38 vldr s15, [pc, #224] @ 800942c <HAL_RCCEx_GetPLL1ClockFreq+0x124>
  20096. 800934e: ee87 6a87 vdiv.f32 s12, s15, s14
  20097. 8009352: 6b13 ldr r3, [r2, #48] @ 0x30
  20098. 8009354: f3c3 0308 ubfx r3, r3, #0, #9
  20099. 8009358: ee07 3a90 vmov s15, r3
  20100. 800935c: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
  20101. 8009360: eef8 7ae7 vcvt.f32.s32 s15, s15
  20102. 8009364: ee77 7aa5 vadd.f32 s15, s15, s11
  20103. 8009368: ee77 7aa6 vadd.f32 s15, s15, s13
  20104. 800936c: ee67 7a86 vmul.f32 s15, s15, s12
  20105. PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ;
  20106. 8009370: 4a2d ldr r2, [pc, #180] @ (8009428 <HAL_RCCEx_GetPLL1ClockFreq+0x120>)
  20107. 8009372: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0
  20108. 8009376: 6b13 ldr r3, [r2, #48] @ 0x30
  20109. 8009378: f3c3 2346 ubfx r3, r3, #9, #7
  20110. 800937c: ee07 3a10 vmov s14, r3
  20111. 8009380: eeb8 7ac7 vcvt.f32.s32 s14, s14
  20112. }
  20113. 8009384: bc70 pop {r4, r5, r6}
  20114. PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ;
  20115. 8009386: ee37 7a06 vadd.f32 s14, s14, s12
  20116. 800938a: eec7 6a87 vdiv.f32 s13, s15, s14
  20117. 800938e: eefc 6ae6 vcvt.u32.f32 s13, s13
  20118. 8009392: edc0 6a00 vstr s13, [r0]
  20119. PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ;
  20120. 8009396: 6b13 ldr r3, [r2, #48] @ 0x30
  20121. 8009398: f3c3 4306 ubfx r3, r3, #16, #7
  20122. 800939c: ee07 3a10 vmov s14, r3
  20123. 80093a0: eeb8 7ac7 vcvt.f32.s32 s14, s14
  20124. 80093a4: ee37 7a06 vadd.f32 s14, s14, s12
  20125. 80093a8: eec7 6a87 vdiv.f32 s13, s15, s14
  20126. 80093ac: eefc 6ae6 vcvt.u32.f32 s13, s13
  20127. 80093b0: edc0 6a01 vstr s13, [r0, #4]
  20128. PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ;
  20129. 80093b4: 6b13 ldr r3, [r2, #48] @ 0x30
  20130. 80093b6: f3c3 6306 ubfx r3, r3, #24, #7
  20131. 80093ba: ee06 3a90 vmov s13, r3
  20132. 80093be: eef8 6ae6 vcvt.f32.s32 s13, s13
  20133. 80093c2: ee76 6a86 vadd.f32 s13, s13, s12
  20134. 80093c6: ee87 7aa6 vdiv.f32 s14, s15, s13
  20135. 80093ca: eefc 7ac7 vcvt.u32.f32 s15, s14
  20136. 80093ce: ee17 3a90 vmov r3, s15
  20137. 80093d2: 6083 str r3, [r0, #8]
  20138. }
  20139. 80093d4: 4770 bx lr
  20140. 80093d6: bc70 pop {r4, r5, r6}
  20141. PLL1_Clocks->PLL1_P_Frequency = 0U;
  20142. 80093d8: e9c0 3300 strd r3, r3, [r0]
  20143. PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ;
  20144. 80093dc: 6083 str r3, [r0, #8]
  20145. }
  20146. 80093de: 4770 bx lr
  20147. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  20148. 80093e0: 6813 ldr r3, [r2, #0]
  20149. 80093e2: 069b lsls r3, r3, #26
  20150. 80093e4: d5b1 bpl.n 800934a <HAL_RCCEx_GetPLL1ClockFreq+0x42>
  20151. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  20152. 80093e6: 6814 ldr r4, [r2, #0]
  20153. pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  20154. 80093e8: eef7 7a00 vmov.f32 s15, #112 @ 0x3f800000 1.0
  20155. 80093ec: 6b13 ldr r3, [r2, #48] @ 0x30
  20156. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  20157. 80093ee: 4910 ldr r1, [pc, #64] @ (8009430 <HAL_RCCEx_GetPLL1ClockFreq+0x128>)
  20158. 80093f0: f3c4 02c1 ubfx r2, r4, #3, #2
  20159. pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  20160. 80093f4: f3c3 0308 ubfx r3, r3, #0, #9
  20161. hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  20162. 80093f8: 40d1 lsrs r1, r2
  20163. pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  20164. 80093fa: ee06 3a10 vmov s12, r3
  20165. 80093fe: ee05 1a90 vmov s11, r1
  20166. 8009402: eeb8 6ac6 vcvt.f32.s32 s12, s12
  20167. 8009406: eef8 5ae5 vcvt.f32.s32 s11, s11
  20168. 800940a: ee36 6a27 vadd.f32 s12, s12, s15
  20169. 800940e: eec5 7a87 vdiv.f32 s15, s11, s14
  20170. 8009412: ee36 7a26 vadd.f32 s14, s12, s13
  20171. 8009416: ee67 7a87 vmul.f32 s15, s15, s14
  20172. 800941a: e7a9 b.n 8009370 <HAL_RCCEx_GetPLL1ClockFreq+0x68>
  20173. pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  20174. 800941c: eddf 7a05 vldr s15, [pc, #20] @ 8009434 <HAL_RCCEx_GetPLL1ClockFreq+0x12c>
  20175. 8009420: e795 b.n 800934e <HAL_RCCEx_GetPLL1ClockFreq+0x46>
  20176. pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
  20177. 8009422: eddf 7a05 vldr s15, [pc, #20] @ 8009438 <HAL_RCCEx_GetPLL1ClockFreq+0x130>
  20178. 8009426: e792 b.n 800934e <HAL_RCCEx_GetPLL1ClockFreq+0x46>
  20179. 8009428: 58024400 .word 0x58024400
  20180. 800942c: 4c742400 .word 0x4c742400
  20181. 8009430: 03d09000 .word 0x03d09000
  20182. 8009434: 4bbebc20 .word 0x4bbebc20
  20183. 8009438: 4a742400 .word 0x4a742400
  20184. 0800943c <HAL_RCCEx_GetPeriphCLKFreq>:
  20185. if (PeriphClk == RCC_PERIPHCLK_SAI1)
  20186. 800943c: f5a0 7380 sub.w r3, r0, #256 @ 0x100
  20187. 8009440: 430b orrs r3, r1
  20188. {
  20189. 8009442: b500 push {lr}
  20190. 8009444: b085 sub sp, #20
  20191. if (PeriphClk == RCC_PERIPHCLK_SAI1)
  20192. 8009446: f000 8083 beq.w 8009550 <HAL_RCCEx_GetPeriphCLKFreq+0x114>
  20193. else if (PeriphClk == RCC_PERIPHCLK_SAI23)
  20194. 800944a: f5a0 7300 sub.w r3, r0, #512 @ 0x200
  20195. 800944e: 430b orrs r3, r1
  20196. 8009450: d038 beq.n 80094c4 <HAL_RCCEx_GetPeriphCLKFreq+0x88>
  20197. else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
  20198. 8009452: f5a0 6380 sub.w r3, r0, #1024 @ 0x400
  20199. 8009456: 430b orrs r3, r1
  20200. 8009458: f000 80e6 beq.w 8009628 <HAL_RCCEx_GetPeriphCLKFreq+0x1ec>
  20201. else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
  20202. 800945c: f5a0 6300 sub.w r3, r0, #2048 @ 0x800
  20203. 8009460: 430b orrs r3, r1
  20204. 8009462: f000 8089 beq.w 8009578 <HAL_RCCEx_GetPeriphCLKFreq+0x13c>
  20205. else if (PeriphClk == RCC_PERIPHCLK_SPI123)
  20206. 8009466: f5a0 5380 sub.w r3, r0, #4096 @ 0x1000
  20207. 800946a: 430b orrs r3, r1
  20208. 800946c: d060 beq.n 8009530 <HAL_RCCEx_GetPeriphCLKFreq+0xf4>
  20209. else if (PeriphClk == RCC_PERIPHCLK_SPI45)
  20210. 800946e: f5a0 5300 sub.w r3, r0, #8192 @ 0x2000
  20211. 8009472: 430b orrs r3, r1
  20212. 8009474: f000 8112 beq.w 800969c <HAL_RCCEx_GetPeriphCLKFreq+0x260>
  20213. else if (PeriphClk == RCC_PERIPHCLK_ADC)
  20214. 8009478: f5a0 2300 sub.w r3, r0, #524288 @ 0x80000
  20215. 800947c: 430b orrs r3, r1
  20216. 800947e: f000 80a3 beq.w 80095c8 <HAL_RCCEx_GetPeriphCLKFreq+0x18c>
  20217. else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
  20218. 8009482: f5a0 3380 sub.w r3, r0, #65536 @ 0x10000
  20219. 8009486: 430b orrs r3, r1
  20220. 8009488: f000 80fa beq.w 8009680 <HAL_RCCEx_GetPeriphCLKFreq+0x244>
  20221. else if (PeriphClk == RCC_PERIPHCLK_SPI6)
  20222. 800948c: f5a0 4380 sub.w r3, r0, #16384 @ 0x4000
  20223. 8009490: 430b orrs r3, r1
  20224. 8009492: f000 8143 beq.w 800971c <HAL_RCCEx_GetPeriphCLKFreq+0x2e0>
  20225. else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
  20226. 8009496: f5a0 4000 sub.w r0, r0, #32768 @ 0x8000
  20227. 800949a: 4308 orrs r0, r1
  20228. 800949c: d137 bne.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20229. srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
  20230. 800949e: 4a9a ldr r2, [pc, #616] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20231. 80094a0: 6d13 ldr r3, [r2, #80] @ 0x50
  20232. 80094a2: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
  20233. switch (srcclk)
  20234. 80094a6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
  20235. 80094aa: f000 8084 beq.w 80095b6 <HAL_RCCEx_GetPeriphCLKFreq+0x17a>
  20236. 80094ae: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
  20237. 80094b2: f000 8157 beq.w 8009764 <HAL_RCCEx_GetPeriphCLKFreq+0x328>
  20238. 80094b6: bb53 cbnz r3, 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20239. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
  20240. 80094b8: 6810 ldr r0, [r2, #0]
  20241. 80094ba: f410 3000 ands.w r0, r0, #131072 @ 0x20000
  20242. 80094be: d044 beq.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20243. frequency = HSE_VALUE;
  20244. 80094c0: 4892 ldr r0, [pc, #584] @ (800970c <HAL_RCCEx_GetPeriphCLKFreq+0x2d0>)
  20245. 80094c2: e042 b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20246. saiclocksource = __HAL_RCC_GET_SAI23_SOURCE();
  20247. 80094c4: 4a90 ldr r2, [pc, #576] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20248. 80094c6: 6d13 ldr r3, [r2, #80] @ 0x50
  20249. 80094c8: f403 73e0 and.w r3, r3, #448 @ 0x1c0
  20250. switch (saiclocksource)
  20251. 80094cc: 2b80 cmp r3, #128 @ 0x80
  20252. 80094ce: f000 80a6 beq.w 800961e <HAL_RCCEx_GetPeriphCLKFreq+0x1e2>
  20253. 80094d2: d920 bls.n 8009516 <HAL_RCCEx_GetPeriphCLKFreq+0xda>
  20254. 80094d4: 2bc0 cmp r3, #192 @ 0xc0
  20255. 80094d6: d037 beq.n 8009548 <HAL_RCCEx_GetPeriphCLKFreq+0x10c>
  20256. 80094d8: f5b3 7f80 cmp.w r3, #256 @ 0x100
  20257. 80094dc: d117 bne.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20258. ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
  20259. 80094de: 6cd3 ldr r3, [r2, #76] @ 0x4c
  20260. if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
  20261. 80094e0: 6811 ldr r1, [r2, #0]
  20262. ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
  20263. 80094e2: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
  20264. if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
  20265. 80094e6: 0749 lsls r1, r1, #29
  20266. 80094e8: d502 bpl.n 80094f0 <HAL_RCCEx_GetPeriphCLKFreq+0xb4>
  20267. 80094ea: 2b00 cmp r3, #0
  20268. 80094ec: f000 80c2 beq.w 8009674 <HAL_RCCEx_GetPeriphCLKFreq+0x238>
  20269. else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
  20270. 80094f0: 4a85 ldr r2, [pc, #532] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20271. 80094f2: 6812 ldr r2, [r2, #0]
  20272. 80094f4: 05d0 lsls r0, r2, #23
  20273. 80094f6: d503 bpl.n 8009500 <HAL_RCCEx_GetPeriphCLKFreq+0xc4>
  20274. 80094f8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
  20275. 80094fc: f000 8102 beq.w 8009704 <HAL_RCCEx_GetPeriphCLKFreq+0x2c8>
  20276. else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
  20277. 8009500: 4a81 ldr r2, [pc, #516] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20278. 8009502: 6812 ldr r2, [r2, #0]
  20279. 8009504: 0391 lsls r1, r2, #14
  20280. 8009506: d502 bpl.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20281. 8009508: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
  20282. 800950c: d0d8 beq.n 80094c0 <HAL_RCCEx_GetPeriphCLKFreq+0x84>
  20283. frequency = 0;
  20284. 800950e: 2000 movs r0, #0
  20285. }
  20286. 8009510: b005 add sp, #20
  20287. 8009512: f85d fb04 ldr.w pc, [sp], #4
  20288. switch (saiclocksource)
  20289. 8009516: 2b00 cmp r3, #0
  20290. 8009518: d04d beq.n 80095b6 <HAL_RCCEx_GetPeriphCLKFreq+0x17a>
  20291. 800951a: 2b40 cmp r3, #64 @ 0x40
  20292. 800951c: d1f7 bne.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20293. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
  20294. 800951e: 6810 ldr r0, [r2, #0]
  20295. 8009520: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
  20296. 8009524: d011 beq.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20297. HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
  20298. 8009526: a801 add r0, sp, #4
  20299. 8009528: f7ff fdba bl 80090a0 <HAL_RCCEx_GetPLL2ClockFreq>
  20300. frequency = pll2_clocks.PLL2_P_Frequency;
  20301. 800952c: 9801 ldr r0, [sp, #4]
  20302. 800952e: e00c b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20303. srcclk = __HAL_RCC_GET_SPI123_SOURCE();
  20304. 8009530: 4a75 ldr r2, [pc, #468] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20305. 8009532: 6d13 ldr r3, [r2, #80] @ 0x50
  20306. 8009534: f403 43e0 and.w r3, r3, #28672 @ 0x7000
  20307. switch (srcclk)
  20308. 8009538: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
  20309. 800953c: d06f beq.n 800961e <HAL_RCCEx_GetPeriphCLKFreq+0x1e2>
  20310. 800953e: d938 bls.n 80095b2 <HAL_RCCEx_GetPeriphCLKFreq+0x176>
  20311. 8009540: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
  20312. 8009544: f040 8088 bne.w 8009658 <HAL_RCCEx_GetPeriphCLKFreq+0x21c>
  20313. frequency = EXTERNAL_CLOCK_VALUE;
  20314. 8009548: 4871 ldr r0, [pc, #452] @ (8009710 <HAL_RCCEx_GetPeriphCLKFreq+0x2d4>)
  20315. }
  20316. 800954a: b005 add sp, #20
  20317. 800954c: f85d fb04 ldr.w pc, [sp], #4
  20318. saiclocksource = __HAL_RCC_GET_SAI1_SOURCE();
  20319. 8009550: 4b6d ldr r3, [pc, #436] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20320. 8009552: 6d1b ldr r3, [r3, #80] @ 0x50
  20321. 8009554: f003 0307 and.w r3, r3, #7
  20322. switch (saiclocksource)
  20323. 8009558: 2b04 cmp r3, #4
  20324. 800955a: d8d8 bhi.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20325. 800955c: a201 add r2, pc, #4 @ (adr r2, 8009564 <HAL_RCCEx_GetPeriphCLKFreq+0x128>)
  20326. 800955e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  20327. 8009562: bf00 nop
  20328. 8009564: 08009607 .word 0x08009607
  20329. 8009568: 080095e3 .word 0x080095e3
  20330. 800956c: 080095f3 .word 0x080095f3
  20331. 8009570: 08009549 .word 0x08009549
  20332. 8009574: 080095ef .word 0x080095ef
  20333. saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE();
  20334. 8009578: 4a63 ldr r2, [pc, #396] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20335. 800957a: 6d93 ldr r3, [r2, #88] @ 0x58
  20336. 800957c: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000
  20337. switch (saiclocksource)
  20338. 8009580: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
  20339. 8009584: d04b beq.n 800961e <HAL_RCCEx_GetPeriphCLKFreq+0x1e2>
  20340. 8009586: d944 bls.n 8009612 <HAL_RCCEx_GetPeriphCLKFreq+0x1d6>
  20341. 8009588: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
  20342. 800958c: d0dc beq.n 8009548 <HAL_RCCEx_GetPeriphCLKFreq+0x10c>
  20343. 800958e: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
  20344. 8009592: d1bc bne.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20345. ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
  20346. 8009594: 6cd3 ldr r3, [r2, #76] @ 0x4c
  20347. if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
  20348. 8009596: 6812 ldr r2, [r2, #0]
  20349. ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
  20350. 8009598: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
  20351. if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
  20352. 800959c: 0752 lsls r2, r2, #29
  20353. 800959e: d5a7 bpl.n 80094f0 <HAL_RCCEx_GetPeriphCLKFreq+0xb4>
  20354. 80095a0: 2b00 cmp r3, #0
  20355. 80095a2: d1a5 bne.n 80094f0 <HAL_RCCEx_GetPeriphCLKFreq+0xb4>
  20356. frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  20357. 80095a4: 4b58 ldr r3, [pc, #352] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20358. 80095a6: 485b ldr r0, [pc, #364] @ (8009714 <HAL_RCCEx_GetPeriphCLKFreq+0x2d8>)
  20359. 80095a8: 681b ldr r3, [r3, #0]
  20360. 80095aa: f3c3 03c1 ubfx r3, r3, #3, #2
  20361. 80095ae: 40d8 lsrs r0, r3
  20362. 80095b0: e7cb b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20363. switch (srcclk)
  20364. 80095b2: 2b00 cmp r3, #0
  20365. 80095b4: d154 bne.n 8009660 <HAL_RCCEx_GetPeriphCLKFreq+0x224>
  20366. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
  20367. 80095b6: 6810 ldr r0, [r2, #0]
  20368. 80095b8: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000
  20369. 80095bc: d0c5 beq.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20370. HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
  20371. 80095be: a801 add r0, sp, #4
  20372. 80095c0: f7ff fea2 bl 8009308 <HAL_RCCEx_GetPLL1ClockFreq>
  20373. frequency = pll1_clocks.PLL1_Q_Frequency;
  20374. 80095c4: 9802 ldr r0, [sp, #8]
  20375. 80095c6: e7c0 b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20376. srcclk = __HAL_RCC_GET_ADC_SOURCE();
  20377. 80095c8: 4a4f ldr r2, [pc, #316] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20378. 80095ca: 6d93 ldr r3, [r2, #88] @ 0x58
  20379. 80095cc: f403 3340 and.w r3, r3, #196608 @ 0x30000
  20380. switch (srcclk)
  20381. 80095d0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
  20382. 80095d4: f000 80d0 beq.w 8009778 <HAL_RCCEx_GetPeriphCLKFreq+0x33c>
  20383. 80095d8: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
  20384. 80095dc: d0da beq.n 8009594 <HAL_RCCEx_GetPeriphCLKFreq+0x158>
  20385. 80095de: 2b00 cmp r3, #0
  20386. 80095e0: d195 bne.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20387. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
  20388. 80095e2: 4b49 ldr r3, [pc, #292] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20389. 80095e4: 6818 ldr r0, [r3, #0]
  20390. 80095e6: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
  20391. 80095ea: d0ae beq.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20392. 80095ec: e79b b.n 8009526 <HAL_RCCEx_GetPeriphCLKFreq+0xea>
  20393. ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
  20394. 80095ee: 4a46 ldr r2, [pc, #280] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20395. 80095f0: e775 b.n 80094de <HAL_RCCEx_GetPeriphCLKFreq+0xa2>
  20396. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
  20397. 80095f2: 4b45 ldr r3, [pc, #276] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20398. 80095f4: 6818 ldr r0, [r3, #0]
  20399. 80095f6: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
  20400. 80095fa: d0a6 beq.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20401. HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
  20402. 80095fc: a801 add r0, sp, #4
  20403. 80095fe: f7ff fde9 bl 80091d4 <HAL_RCCEx_GetPLL3ClockFreq>
  20404. frequency = pll3_clocks.PLL3_P_Frequency;
  20405. 8009602: 9801 ldr r0, [sp, #4]
  20406. 8009604: e7a1 b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20407. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
  20408. 8009606: 4b40 ldr r3, [pc, #256] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20409. 8009608: 6818 ldr r0, [r3, #0]
  20410. 800960a: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000
  20411. 800960e: d09c beq.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20412. 8009610: e7d5 b.n 80095be <HAL_RCCEx_GetPeriphCLKFreq+0x182>
  20413. switch (saiclocksource)
  20414. 8009612: 2b00 cmp r3, #0
  20415. 8009614: d0cf beq.n 80095b6 <HAL_RCCEx_GetPeriphCLKFreq+0x17a>
  20416. 8009616: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
  20417. 800961a: d080 beq.n 800951e <HAL_RCCEx_GetPeriphCLKFreq+0xe2>
  20418. 800961c: e777 b.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20419. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
  20420. 800961e: 6810 ldr r0, [r2, #0]
  20421. 8009620: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
  20422. 8009624: d091 beq.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20423. 8009626: e7e9 b.n 80095fc <HAL_RCCEx_GetPeriphCLKFreq+0x1c0>
  20424. saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE();
  20425. 8009628: 4a37 ldr r2, [pc, #220] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20426. 800962a: 6d93 ldr r3, [r2, #88] @ 0x58
  20427. 800962c: f403 0360 and.w r3, r3, #14680064 @ 0xe00000
  20428. switch (saiclocksource)
  20429. 8009630: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
  20430. 8009634: d0f3 beq.n 800961e <HAL_RCCEx_GetPeriphCLKFreq+0x1e2>
  20431. 8009636: d806 bhi.n 8009646 <HAL_RCCEx_GetPeriphCLKFreq+0x20a>
  20432. 8009638: 2b00 cmp r3, #0
  20433. 800963a: d0bc beq.n 80095b6 <HAL_RCCEx_GetPeriphCLKFreq+0x17a>
  20434. 800963c: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
  20435. 8009640: f43f af6d beq.w 800951e <HAL_RCCEx_GetPeriphCLKFreq+0xe2>
  20436. 8009644: e763 b.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20437. 8009646: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000
  20438. 800964a: f43f af7d beq.w 8009548 <HAL_RCCEx_GetPeriphCLKFreq+0x10c>
  20439. 800964e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
  20440. 8009652: f43f af44 beq.w 80094de <HAL_RCCEx_GetPeriphCLKFreq+0xa2>
  20441. 8009656: e75a b.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20442. switch (srcclk)
  20443. 8009658: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
  20444. 800965c: d09a beq.n 8009594 <HAL_RCCEx_GetPeriphCLKFreq+0x158>
  20445. 800965e: e756 b.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20446. 8009660: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
  20447. 8009664: f43f af5b beq.w 800951e <HAL_RCCEx_GetPeriphCLKFreq+0xe2>
  20448. 8009668: e751 b.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20449. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
  20450. 800966a: 6810 ldr r0, [r2, #0]
  20451. 800966c: f010 0004 ands.w r0, r0, #4
  20452. 8009670: f43f af6b beq.w 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20453. frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  20454. 8009674: 6813 ldr r3, [r2, #0]
  20455. 8009676: 4827 ldr r0, [pc, #156] @ (8009714 <HAL_RCCEx_GetPeriphCLKFreq+0x2d8>)
  20456. 8009678: f3c3 03c1 ubfx r3, r3, #3, #2
  20457. 800967c: 40d8 lsrs r0, r3
  20458. 800967e: e764 b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20459. srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
  20460. 8009680: 4b21 ldr r3, [pc, #132] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20461. 8009682: 6cda ldr r2, [r3, #76] @ 0x4c
  20462. switch (srcclk)
  20463. 8009684: 03d2 lsls r2, r2, #15
  20464. 8009686: d5bf bpl.n 8009608 <HAL_RCCEx_GetPeriphCLKFreq+0x1cc>
  20465. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
  20466. 8009688: 6818 ldr r0, [r3, #0]
  20467. 800968a: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
  20468. 800968e: f43f af5c beq.w 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20469. HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
  20470. 8009692: a801 add r0, sp, #4
  20471. 8009694: f7ff fd04 bl 80090a0 <HAL_RCCEx_GetPLL2ClockFreq>
  20472. frequency = pll2_clocks.PLL2_R_Frequency;
  20473. 8009698: 9803 ldr r0, [sp, #12]
  20474. 800969a: e756 b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20475. srcclk = __HAL_RCC_GET_SPI45_SOURCE();
  20476. 800969c: 4a1a ldr r2, [pc, #104] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20477. 800969e: 6d13 ldr r3, [r2, #80] @ 0x50
  20478. 80096a0: f403 23e0 and.w r3, r3, #458752 @ 0x70000
  20479. switch (srcclk)
  20480. 80096a4: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
  20481. 80096a8: d0df beq.n 800966a <HAL_RCCEx_GetPeriphCLKFreq+0x22e>
  20482. 80096aa: d810 bhi.n 80096ce <HAL_RCCEx_GetPeriphCLKFreq+0x292>
  20483. 80096ac: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
  20484. 80096b0: d058 beq.n 8009764 <HAL_RCCEx_GetPeriphCLKFreq+0x328>
  20485. 80096b2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
  20486. 80096b6: d118 bne.n 80096ea <HAL_RCCEx_GetPeriphCLKFreq+0x2ae>
  20487. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
  20488. 80096b8: 4b13 ldr r3, [pc, #76] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20489. 80096ba: 6818 ldr r0, [r3, #0]
  20490. 80096bc: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
  20491. 80096c0: f43f af43 beq.w 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20492. HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
  20493. 80096c4: a801 add r0, sp, #4
  20494. 80096c6: f7ff fd85 bl 80091d4 <HAL_RCCEx_GetPLL3ClockFreq>
  20495. frequency = pll3_clocks.PLL3_Q_Frequency;
  20496. 80096ca: 9802 ldr r0, [sp, #8]
  20497. 80096cc: e73d b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20498. switch (srcclk)
  20499. 80096ce: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
  20500. 80096d2: d012 beq.n 80096fa <HAL_RCCEx_GetPeriphCLKFreq+0x2be>
  20501. 80096d4: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
  20502. 80096d8: f47f af19 bne.w 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20503. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
  20504. 80096dc: 4b0a ldr r3, [pc, #40] @ (8009708 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>)
  20505. 80096de: 6818 ldr r0, [r3, #0]
  20506. 80096e0: f410 3000 ands.w r0, r0, #131072 @ 0x20000
  20507. 80096e4: f43f af31 beq.w 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20508. 80096e8: e6ea b.n 80094c0 <HAL_RCCEx_GetPeriphCLKFreq+0x84>
  20509. switch (srcclk)
  20510. 80096ea: 2b00 cmp r3, #0
  20511. 80096ec: f47f af0f bne.w 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20512. }
  20513. 80096f0: b005 add sp, #20
  20514. 80096f2: f85d eb04 ldr.w lr, [sp], #4
  20515. frequency = HAL_RCC_GetPCLK1Freq();
  20516. 80096f6: f7fe bbd3 b.w 8007ea0 <HAL_RCC_GetPCLK1Freq>
  20517. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
  20518. 80096fa: 6810 ldr r0, [r2, #0]
  20519. 80096fc: f410 7080 ands.w r0, r0, #256 @ 0x100
  20520. 8009700: f43f af23 beq.w 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20521. frequency = CSI_VALUE;
  20522. 8009704: 4804 ldr r0, [pc, #16] @ (8009718 <HAL_RCCEx_GetPeriphCLKFreq+0x2dc>)
  20523. 8009706: e720 b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20524. 8009708: 58024400 .word 0x58024400
  20525. 800970c: 017d7840 .word 0x017d7840
  20526. 8009710: 00bb8000 .word 0x00bb8000
  20527. 8009714: 03d09000 .word 0x03d09000
  20528. 8009718: 003d0900 .word 0x003d0900
  20529. srcclk = __HAL_RCC_GET_SPI6_SOURCE();
  20530. 800971c: 4b28 ldr r3, [pc, #160] @ (80097c0 <HAL_RCCEx_GetPeriphCLKFreq+0x384>)
  20531. 800971e: 6d9b ldr r3, [r3, #88] @ 0x58
  20532. 8009720: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000
  20533. switch (srcclk)
  20534. 8009724: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000
  20535. 8009728: d037 beq.n 800979a <HAL_RCCEx_GetPeriphCLKFreq+0x35e>
  20536. 800972a: d814 bhi.n 8009756 <HAL_RCCEx_GetPeriphCLKFreq+0x31a>
  20537. 800972c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
  20538. 8009730: d03f beq.n 80097b2 <HAL_RCCEx_GetPeriphCLKFreq+0x376>
  20539. 8009732: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
  20540. 8009736: d0bf beq.n 80096b8 <HAL_RCCEx_GetPeriphCLKFreq+0x27c>
  20541. 8009738: 2b00 cmp r3, #0
  20542. 800973a: f47f aee8 bne.w 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20543. return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
  20544. 800973e: f7fe fb6f bl 8007e20 <HAL_RCC_GetHCLKFreq>
  20545. 8009742: 4b1f ldr r3, [pc, #124] @ (80097c0 <HAL_RCCEx_GetPeriphCLKFreq+0x384>)
  20546. 8009744: 4a1f ldr r2, [pc, #124] @ (80097c4 <HAL_RCCEx_GetPeriphCLKFreq+0x388>)
  20547. 8009746: 6a1b ldr r3, [r3, #32]
  20548. 8009748: f3c3 1302 ubfx r3, r3, #4, #3
  20549. 800974c: 5cd3 ldrb r3, [r2, r3]
  20550. 800974e: f003 031f and.w r3, r3, #31
  20551. 8009752: 40d8 lsrs r0, r3
  20552. break;
  20553. 8009754: e6f9 b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20554. switch (srcclk)
  20555. 8009756: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
  20556. 800975a: d017 beq.n 800978c <HAL_RCCEx_GetPeriphCLKFreq+0x350>
  20557. 800975c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
  20558. 8009760: d0bc beq.n 80096dc <HAL_RCCEx_GetPeriphCLKFreq+0x2a0>
  20559. 8009762: e6d4 b.n 800950e <HAL_RCCEx_GetPeriphCLKFreq+0xd2>
  20560. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
  20561. 8009764: 6810 ldr r0, [r2, #0]
  20562. 8009766: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
  20563. 800976a: f43f aeee beq.w 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20564. HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
  20565. 800976e: a801 add r0, sp, #4
  20566. 8009770: f7ff fc96 bl 80090a0 <HAL_RCCEx_GetPLL2ClockFreq>
  20567. frequency = pll2_clocks.PLL2_Q_Frequency;
  20568. 8009774: 9802 ldr r0, [sp, #8]
  20569. 8009776: e6e8 b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20570. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
  20571. 8009778: 6810 ldr r0, [r2, #0]
  20572. 800977a: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
  20573. 800977e: f43f aee4 beq.w 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20574. HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
  20575. 8009782: a801 add r0, sp, #4
  20576. 8009784: f7ff fd26 bl 80091d4 <HAL_RCCEx_GetPLL3ClockFreq>
  20577. frequency = pll3_clocks.PLL3_R_Frequency;
  20578. 8009788: 9803 ldr r0, [sp, #12]
  20579. 800978a: e6de b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20580. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
  20581. 800978c: 4b0c ldr r3, [pc, #48] @ (80097c0 <HAL_RCCEx_GetPeriphCLKFreq+0x384>)
  20582. 800978e: 6818 ldr r0, [r3, #0]
  20583. 8009790: f410 7080 ands.w r0, r0, #256 @ 0x100
  20584. 8009794: f43f aed9 beq.w 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20585. 8009798: e7b4 b.n 8009704 <HAL_RCCEx_GetPeriphCLKFreq+0x2c8>
  20586. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
  20587. 800979a: 4b09 ldr r3, [pc, #36] @ (80097c0 <HAL_RCCEx_GetPeriphCLKFreq+0x384>)
  20588. 800979c: 6818 ldr r0, [r3, #0]
  20589. 800979e: f010 0004 ands.w r0, r0, #4
  20590. 80097a2: f43f aed2 beq.w 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20591. frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
  20592. 80097a6: 681b ldr r3, [r3, #0]
  20593. 80097a8: 4807 ldr r0, [pc, #28] @ (80097c8 <HAL_RCCEx_GetPeriphCLKFreq+0x38c>)
  20594. 80097aa: f3c3 03c1 ubfx r3, r3, #3, #2
  20595. 80097ae: 40d8 lsrs r0, r3
  20596. 80097b0: e6cb b.n 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20597. if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
  20598. 80097b2: 4b03 ldr r3, [pc, #12] @ (80097c0 <HAL_RCCEx_GetPeriphCLKFreq+0x384>)
  20599. 80097b4: 6818 ldr r0, [r3, #0]
  20600. 80097b6: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
  20601. 80097ba: f43f aec6 beq.w 800954a <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
  20602. 80097be: e7d6 b.n 800976e <HAL_RCCEx_GetPeriphCLKFreq+0x332>
  20603. 80097c0: 58024400 .word 0x58024400
  20604. 80097c4: 08011a14 .word 0x08011a14
  20605. 80097c8: 03d09000 .word 0x03d09000
  20606. 080097cc <HAL_RNG_Init>:
  20607. */
  20608. HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
  20609. {
  20610. uint32_t tickstart;
  20611. /* Check the RNG handle allocation */
  20612. if (hrng == NULL)
  20613. 80097cc: 2800 cmp r0, #0
  20614. 80097ce: d038 beq.n 8009842 <HAL_RNG_Init+0x76>
  20615. {
  20616. 80097d0: b538 push {r3, r4, r5, lr}
  20617. /* Init the low level hardware */
  20618. hrng->MspInitCallback(hrng);
  20619. }
  20620. #else
  20621. if (hrng->State == HAL_RNG_STATE_RESET)
  20622. 80097d2: 7a43 ldrb r3, [r0, #9]
  20623. 80097d4: 4604 mov r4, r0
  20624. 80097d6: f003 02ff and.w r2, r3, #255 @ 0xff
  20625. 80097da: b373 cbz r3, 800983a <HAL_RNG_Init+0x6e>
  20626. }
  20627. }
  20628. }
  20629. #else
  20630. /* Clock Error Detection Configuration */
  20631. MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
  20632. 80097dc: 6823 ldr r3, [r4, #0]
  20633. hrng->State = HAL_RNG_STATE_BUSY;
  20634. 80097de: 2202 movs r2, #2
  20635. MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
  20636. 80097e0: 6861 ldr r1, [r4, #4]
  20637. hrng->State = HAL_RNG_STATE_BUSY;
  20638. 80097e2: 7262 strb r2, [r4, #9]
  20639. MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
  20640. 80097e4: 681a ldr r2, [r3, #0]
  20641. 80097e6: f022 0220 bic.w r2, r2, #32
  20642. 80097ea: 430a orrs r2, r1
  20643. 80097ec: 601a str r2, [r3, #0]
  20644. #endif /* RNG_CR_CONDRST */
  20645. /* Enable the RNG Peripheral */
  20646. __HAL_RNG_ENABLE(hrng);
  20647. 80097ee: 681a ldr r2, [r3, #0]
  20648. 80097f0: f042 0204 orr.w r2, r2, #4
  20649. 80097f4: 601a str r2, [r3, #0]
  20650. /* verify that no seed error */
  20651. if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
  20652. 80097f6: 685b ldr r3, [r3, #4]
  20653. 80097f8: 0658 lsls r0, r3, #25
  20654. 80097fa: d503 bpl.n 8009804 <HAL_RNG_Init+0x38>
  20655. {
  20656. hrng->State = HAL_RNG_STATE_ERROR;
  20657. 80097fc: 2304 movs r3, #4
  20658. 80097fe: 7263 strb r3, [r4, #9]
  20659. return HAL_ERROR;
  20660. 8009800: 2001 movs r0, #1
  20661. /* Initialise the error code */
  20662. hrng->ErrorCode = HAL_RNG_ERROR_NONE;
  20663. /* Return function status */
  20664. return HAL_OK;
  20665. }
  20666. 8009802: bd38 pop {r3, r4, r5, pc}
  20667. tickstart = HAL_GetTick();
  20668. 8009804: f7fa fbe4 bl 8003fd0 <HAL_GetTick>
  20669. while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
  20670. 8009808: 6823 ldr r3, [r4, #0]
  20671. tickstart = HAL_GetTick();
  20672. 800980a: 4605 mov r5, r0
  20673. while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
  20674. 800980c: 685b ldr r3, [r3, #4]
  20675. 800980e: 0759 lsls r1, r3, #29
  20676. 8009810: d50d bpl.n 800982e <HAL_RNG_Init+0x62>
  20677. if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
  20678. 8009812: f7fa fbdd bl 8003fd0 <HAL_GetTick>
  20679. 8009816: 1b40 subs r0, r0, r5
  20680. if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
  20681. 8009818: 6823 ldr r3, [r4, #0]
  20682. if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
  20683. 800981a: 2802 cmp r0, #2
  20684. 800981c: d9f6 bls.n 800980c <HAL_RNG_Init+0x40>
  20685. if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
  20686. 800981e: 685a ldr r2, [r3, #4]
  20687. 8009820: 0752 lsls r2, r2, #29
  20688. 8009822: d5f3 bpl.n 800980c <HAL_RNG_Init+0x40>
  20689. hrng->State = HAL_RNG_STATE_ERROR;
  20690. 8009824: 2204 movs r2, #4
  20691. hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
  20692. 8009826: 2302 movs r3, #2
  20693. hrng->State = HAL_RNG_STATE_ERROR;
  20694. 8009828: 7262 strb r2, [r4, #9]
  20695. hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
  20696. 800982a: 60e3 str r3, [r4, #12]
  20697. return HAL_ERROR;
  20698. 800982c: e7e8 b.n 8009800 <HAL_RNG_Init+0x34>
  20699. hrng->ErrorCode = HAL_RNG_ERROR_NONE;
  20700. 800982e: 2300 movs r3, #0
  20701. hrng->State = HAL_RNG_STATE_READY;
  20702. 8009830: 2201 movs r2, #1
  20703. return HAL_OK;
  20704. 8009832: 4618 mov r0, r3
  20705. hrng->State = HAL_RNG_STATE_READY;
  20706. 8009834: 7262 strb r2, [r4, #9]
  20707. hrng->ErrorCode = HAL_RNG_ERROR_NONE;
  20708. 8009836: 60e3 str r3, [r4, #12]
  20709. }
  20710. 8009838: bd38 pop {r3, r4, r5, pc}
  20711. hrng->Lock = HAL_UNLOCKED;
  20712. 800983a: 7202 strb r2, [r0, #8]
  20713. HAL_RNG_MspInit(hrng);
  20714. 800983c: f7f9 fa0a bl 8002c54 <HAL_RNG_MspInit>
  20715. 8009840: e7cc b.n 80097dc <HAL_RNG_Init+0x10>
  20716. return HAL_ERROR;
  20717. 8009842: 2001 movs r0, #1
  20718. }
  20719. 8009844: 4770 bx lr
  20720. 8009846: bf00 nop
  20721. 08009848 <TIM_OC1_SetConfig>:
  20722. uint32_t tmpccmrx;
  20723. uint32_t tmpccer;
  20724. uint32_t tmpcr2;
  20725. /* Get the TIMx CCER register value */
  20726. tmpccer = TIMx->CCER;
  20727. 8009848: 6a03 ldr r3, [r0, #32]
  20728. /* Disable the Channel 1: Reset the CC1E Bit */
  20729. TIMx->CCER &= ~TIM_CCER_CC1E;
  20730. 800984a: 6a02 ldr r2, [r0, #32]
  20731. tmpccmrx &= ~TIM_CCMR1_CC1S;
  20732. /* Select the Output Compare Mode */
  20733. tmpccmrx |= OC_Config->OCMode;
  20734. /* Reset the Output Polarity level */
  20735. tmpccer &= ~TIM_CCER_CC1P;
  20736. 800984c: f023 0302 bic.w r3, r3, #2
  20737. TIMx->CCER &= ~TIM_CCER_CC1E;
  20738. 8009850: f022 0201 bic.w r2, r2, #1
  20739. {
  20740. 8009854: b470 push {r4, r5, r6}
  20741. TIMx->CCER &= ~TIM_CCER_CC1E;
  20742. 8009856: 6202 str r2, [r0, #32]
  20743. tmpccmrx &= ~TIM_CCMR1_CC1S;
  20744. 8009858: 4a17 ldr r2, [pc, #92] @ (80098b8 <TIM_OC1_SetConfig+0x70>)
  20745. tmpcr2 = TIMx->CR2;
  20746. 800985a: 6844 ldr r4, [r0, #4]
  20747. tmpccmrx = TIMx->CCMR1;
  20748. 800985c: 6985 ldr r5, [r0, #24]
  20749. tmpccmrx &= ~TIM_CCMR1_CC1S;
  20750. 800985e: 402a ands r2, r5
  20751. tmpccmrx |= OC_Config->OCMode;
  20752. 8009860: 680d ldr r5, [r1, #0]
  20753. 8009862: 432a orrs r2, r5
  20754. /* Set the Output Compare Polarity */
  20755. tmpccer |= OC_Config->OCPolarity;
  20756. 8009864: 688d ldr r5, [r1, #8]
  20757. 8009866: 432b orrs r3, r5
  20758. if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
  20759. 8009868: 4d14 ldr r5, [pc, #80] @ (80098bc <TIM_OC1_SetConfig+0x74>)
  20760. 800986a: 42a8 cmp r0, r5
  20761. 800986c: d00f beq.n 800988e <TIM_OC1_SetConfig+0x46>
  20762. 800986e: f505 6580 add.w r5, r5, #1024 @ 0x400
  20763. 8009872: 42a8 cmp r0, r5
  20764. 8009874: d00b beq.n 800988e <TIM_OC1_SetConfig+0x46>
  20765. 8009876: f505 5570 add.w r5, r5, #15360 @ 0x3c00
  20766. 800987a: 42a8 cmp r0, r5
  20767. 800987c: d007 beq.n 800988e <TIM_OC1_SetConfig+0x46>
  20768. 800987e: f505 6580 add.w r5, r5, #1024 @ 0x400
  20769. 8009882: 42a8 cmp r0, r5
  20770. 8009884: d003 beq.n 800988e <TIM_OC1_SetConfig+0x46>
  20771. 8009886: f505 6580 add.w r5, r5, #1024 @ 0x400
  20772. 800988a: 42a8 cmp r0, r5
  20773. 800988c: d10d bne.n 80098aa <TIM_OC1_SetConfig+0x62>
  20774. assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
  20775. /* Reset the Output N Polarity level */
  20776. tmpccer &= ~TIM_CCER_CC1NP;
  20777. /* Set the Output N Polarity */
  20778. tmpccer |= OC_Config->OCNPolarity;
  20779. 800988e: 68cd ldr r5, [r1, #12]
  20780. tmpccer &= ~TIM_CCER_CC1NP;
  20781. 8009890: f023 0308 bic.w r3, r3, #8
  20782. assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
  20783. assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  20784. /* Reset the Output Compare and Output Compare N IDLE State */
  20785. tmpcr2 &= ~TIM_CR2_OIS1;
  20786. tmpcr2 &= ~TIM_CR2_OIS1N;
  20787. 8009894: f424 7440 bic.w r4, r4, #768 @ 0x300
  20788. tmpccer |= OC_Config->OCNPolarity;
  20789. 8009898: 432b orrs r3, r5
  20790. /* Set the Output Idle state */
  20791. tmpcr2 |= OC_Config->OCIdleState;
  20792. /* Set the Output N Idle state */
  20793. tmpcr2 |= OC_Config->OCNIdleState;
  20794. 800989a: e9d1 6505 ldrd r6, r5, [r1, #20]
  20795. tmpccer &= ~TIM_CCER_CC1NE;
  20796. 800989e: f023 0304 bic.w r3, r3, #4
  20797. tmpcr2 |= OC_Config->OCNIdleState;
  20798. 80098a2: ea46 0c05 orr.w ip, r6, r5
  20799. 80098a6: ea4c 0404 orr.w r4, ip, r4
  20800. /* Write to TIMx CCMR1 */
  20801. TIMx->CCMR1 = tmpccmrx;
  20802. /* Set the Capture Compare Register value */
  20803. TIMx->CCR1 = OC_Config->Pulse;
  20804. 80098aa: 6849 ldr r1, [r1, #4]
  20805. TIMx->CR2 = tmpcr2;
  20806. 80098ac: 6044 str r4, [r0, #4]
  20807. TIMx->CCMR1 = tmpccmrx;
  20808. 80098ae: 6182 str r2, [r0, #24]
  20809. TIMx->CCR1 = OC_Config->Pulse;
  20810. 80098b0: 6341 str r1, [r0, #52] @ 0x34
  20811. /* Write to TIMx CCER */
  20812. TIMx->CCER = tmpccer;
  20813. 80098b2: 6203 str r3, [r0, #32]
  20814. }
  20815. 80098b4: bc70 pop {r4, r5, r6}
  20816. 80098b6: 4770 bx lr
  20817. 80098b8: fffeff8c .word 0xfffeff8c
  20818. 80098bc: 40010000 .word 0x40010000
  20819. 080098c0 <TIM_OC3_SetConfig>:
  20820. uint32_t tmpccmrx;
  20821. uint32_t tmpccer;
  20822. uint32_t tmpcr2;
  20823. /* Get the TIMx CCER register value */
  20824. tmpccer = TIMx->CCER;
  20825. 80098c0: 6a03 ldr r3, [r0, #32]
  20826. /* Disable the Channel 3: Reset the CC2E Bit */
  20827. TIMx->CCER &= ~TIM_CCER_CC3E;
  20828. 80098c2: 6a02 ldr r2, [r0, #32]
  20829. tmpccmrx &= ~TIM_CCMR2_CC3S;
  20830. /* Select the Output Compare Mode */
  20831. tmpccmrx |= OC_Config->OCMode;
  20832. /* Reset the Output Polarity level */
  20833. tmpccer &= ~TIM_CCER_CC3P;
  20834. 80098c4: f423 7300 bic.w r3, r3, #512 @ 0x200
  20835. TIMx->CCER &= ~TIM_CCER_CC3E;
  20836. 80098c8: f422 7280 bic.w r2, r2, #256 @ 0x100
  20837. {
  20838. 80098cc: b470 push {r4, r5, r6}
  20839. TIMx->CCER &= ~TIM_CCER_CC3E;
  20840. 80098ce: 6202 str r2, [r0, #32]
  20841. tmpccmrx &= ~TIM_CCMR2_CC3S;
  20842. 80098d0: 4a18 ldr r2, [pc, #96] @ (8009934 <TIM_OC3_SetConfig+0x74>)
  20843. tmpcr2 = TIMx->CR2;
  20844. 80098d2: 6844 ldr r4, [r0, #4]
  20845. tmpccmrx = TIMx->CCMR2;
  20846. 80098d4: 69c5 ldr r5, [r0, #28]
  20847. tmpccmrx &= ~TIM_CCMR2_CC3S;
  20848. 80098d6: 402a ands r2, r5
  20849. tmpccmrx |= OC_Config->OCMode;
  20850. 80098d8: 680d ldr r5, [r1, #0]
  20851. 80098da: 432a orrs r2, r5
  20852. /* Set the Output Compare Polarity */
  20853. tmpccer |= (OC_Config->OCPolarity << 8U);
  20854. 80098dc: 688d ldr r5, [r1, #8]
  20855. 80098de: ea43 2305 orr.w r3, r3, r5, lsl #8
  20856. if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
  20857. 80098e2: 4d15 ldr r5, [pc, #84] @ (8009938 <TIM_OC3_SetConfig+0x78>)
  20858. 80098e4: 42a8 cmp r0, r5
  20859. 80098e6: d00f beq.n 8009908 <TIM_OC3_SetConfig+0x48>
  20860. 80098e8: f505 6580 add.w r5, r5, #1024 @ 0x400
  20861. 80098ec: 42a8 cmp r0, r5
  20862. 80098ee: d00b beq.n 8009908 <TIM_OC3_SetConfig+0x48>
  20863. tmpccer |= (OC_Config->OCNPolarity << 8U);
  20864. /* Reset the Output N State */
  20865. tmpccer &= ~TIM_CCER_CC3NE;
  20866. }
  20867. if (IS_TIM_BREAK_INSTANCE(TIMx))
  20868. 80098f0: 4e12 ldr r6, [pc, #72] @ (800993c <TIM_OC3_SetConfig+0x7c>)
  20869. 80098f2: f505 4580 add.w r5, r5, #16384 @ 0x4000
  20870. 80098f6: 42a8 cmp r0, r5
  20871. 80098f8: bf18 it ne
  20872. 80098fa: 42b0 cmpne r0, r6
  20873. 80098fc: d00b beq.n 8009916 <TIM_OC3_SetConfig+0x56>
  20874. 80098fe: f505 6580 add.w r5, r5, #1024 @ 0x400
  20875. 8009902: 42a8 cmp r0, r5
  20876. 8009904: d10f bne.n 8009926 <TIM_OC3_SetConfig+0x66>
  20877. 8009906: e006 b.n 8009916 <TIM_OC3_SetConfig+0x56>
  20878. tmpccer &= ~TIM_CCER_CC3NP;
  20879. 8009908: f423 6300 bic.w r3, r3, #2048 @ 0x800
  20880. tmpccer |= (OC_Config->OCNPolarity << 8U);
  20881. 800990c: 68cd ldr r5, [r1, #12]
  20882. 800990e: ea43 2305 orr.w r3, r3, r5, lsl #8
  20883. tmpccer &= ~TIM_CCER_CC3NE;
  20884. 8009912: f423 6380 bic.w r3, r3, #1024 @ 0x400
  20885. assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
  20886. assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  20887. /* Reset the Output Compare and Output Compare N IDLE State */
  20888. tmpcr2 &= ~TIM_CR2_OIS3;
  20889. tmpcr2 &= ~TIM_CR2_OIS3N;
  20890. 8009916: f424 5440 bic.w r4, r4, #12288 @ 0x3000
  20891. /* Set the Output Idle state */
  20892. tmpcr2 |= (OC_Config->OCIdleState << 4U);
  20893. /* Set the Output N Idle state */
  20894. tmpcr2 |= (OC_Config->OCNIdleState << 4U);
  20895. 800991a: e9d1 6505 ldrd r6, r5, [r1, #20]
  20896. 800991e: ea46 0c05 orr.w ip, r6, r5
  20897. 8009922: ea44 140c orr.w r4, r4, ip, lsl #4
  20898. /* Write to TIMx CCMR2 */
  20899. TIMx->CCMR2 = tmpccmrx;
  20900. /* Set the Capture Compare Register value */
  20901. TIMx->CCR3 = OC_Config->Pulse;
  20902. 8009926: 6849 ldr r1, [r1, #4]
  20903. TIMx->CR2 = tmpcr2;
  20904. 8009928: 6044 str r4, [r0, #4]
  20905. TIMx->CCMR2 = tmpccmrx;
  20906. 800992a: 61c2 str r2, [r0, #28]
  20907. TIMx->CCR3 = OC_Config->Pulse;
  20908. 800992c: 63c1 str r1, [r0, #60] @ 0x3c
  20909. /* Write to TIMx CCER */
  20910. TIMx->CCER = tmpccer;
  20911. 800992e: 6203 str r3, [r0, #32]
  20912. }
  20913. 8009930: bc70 pop {r4, r5, r6}
  20914. 8009932: 4770 bx lr
  20915. 8009934: fffeff8c .word 0xfffeff8c
  20916. 8009938: 40010000 .word 0x40010000
  20917. 800993c: 40014000 .word 0x40014000
  20918. 08009940 <HAL_TIM_Base_Init>:
  20919. if (htim == NULL)
  20920. 8009940: 2800 cmp r0, #0
  20921. 8009942: f000 8094 beq.w 8009a6e <HAL_TIM_Base_Init+0x12e>
  20922. {
  20923. 8009946: b5f8 push {r3, r4, r5, r6, r7, lr}
  20924. if (htim->State == HAL_TIM_STATE_RESET)
  20925. 8009948: f890 303d ldrb.w r3, [r0, #61] @ 0x3d
  20926. 800994c: 4604 mov r4, r0
  20927. 800994e: f003 02ff and.w r2, r3, #255 @ 0xff
  20928. 8009952: 2b00 cmp r3, #0
  20929. 8009954: d07b beq.n 8009a4e <HAL_TIM_Base_Init+0x10e>
  20930. TIM_Base_SetConfig(htim->Instance, &htim->Init);
  20931. 8009956: 6823 ldr r3, [r4, #0]
  20932. htim->State = HAL_TIM_STATE_BUSY;
  20933. 8009958: 2202 movs r2, #2
  20934. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  20935. 800995a: 4946 ldr r1, [pc, #280] @ (8009a74 <HAL_TIM_Base_Init+0x134>)
  20936. 800995c: 4846 ldr r0, [pc, #280] @ (8009a78 <HAL_TIM_Base_Init+0x138>)
  20937. 800995e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
  20938. 8009962: eba3 0101 sub.w r1, r3, r1
  20939. htim->State = HAL_TIM_STATE_BUSY;
  20940. 8009966: f884 203d strb.w r2, [r4, #61] @ 0x3d
  20941. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  20942. 800996a: eba3 0e00 sub.w lr, r3, r0
  20943. tmpcr1 = TIMx->CR1;
  20944. 800996e: 681a ldr r2, [r3, #0]
  20945. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  20946. 8009970: fab1 f181 clz r1, r1
  20947. MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  20948. 8009974: 69a7 ldr r7, [r4, #24]
  20949. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  20950. 8009976: fabe fe8e clz lr, lr
  20951. TIMx->PSC = Structure->Prescaler;
  20952. 800997a: 6865 ldr r5, [r4, #4]
  20953. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  20954. 800997c: ea4f 1151 mov.w r1, r1, lsr #5
  20955. TIMx->ARR = (uint32_t)Structure->Period ;
  20956. 8009980: 68e6 ldr r6, [r4, #12]
  20957. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  20958. 8009982: ea4f 1e5e mov.w lr, lr, lsr #5
  20959. 8009986: d020 beq.n 80099ca <HAL_TIM_Base_Init+0x8a>
  20960. 8009988: b9f9 cbnz r1, 80099ca <HAL_TIM_Base_Init+0x8a>
  20961. 800998a: f8df c0fc ldr.w ip, [pc, #252] @ 8009a88 <HAL_TIM_Base_Init+0x148>
  20962. 800998e: 4563 cmp r3, ip
  20963. 8009990: d01b beq.n 80099ca <HAL_TIM_Base_Init+0x8a>
  20964. 8009992: f50c 6c80 add.w ip, ip, #1024 @ 0x400
  20965. 8009996: 4563 cmp r3, ip
  20966. 8009998: d017 beq.n 80099ca <HAL_TIM_Base_Init+0x8a>
  20967. 800999a: f50c 6c80 add.w ip, ip, #1024 @ 0x400
  20968. 800999e: 4563 cmp r3, ip
  20969. 80099a0: d013 beq.n 80099ca <HAL_TIM_Base_Init+0x8a>
  20970. 80099a2: f1be 0f00 cmp.w lr, #0
  20971. 80099a6: d110 bne.n 80099ca <HAL_TIM_Base_Init+0x8a>
  20972. if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  20973. 80099a8: 4834 ldr r0, [pc, #208] @ (8009a7c <HAL_TIM_Base_Init+0x13c>)
  20974. 80099aa: 4935 ldr r1, [pc, #212] @ (8009a80 <HAL_TIM_Base_Init+0x140>)
  20975. 80099ac: 428b cmp r3, r1
  20976. 80099ae: bf18 it ne
  20977. 80099b0: 4283 cmpne r3, r0
  20978. 80099b2: d051 beq.n 8009a58 <HAL_TIM_Base_Init+0x118>
  20979. 80099b4: f501 6180 add.w r1, r1, #1024 @ 0x400
  20980. 80099b8: 428b cmp r3, r1
  20981. 80099ba: d04d beq.n 8009a58 <HAL_TIM_Base_Init+0x118>
  20982. MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  20983. 80099bc: f022 0280 bic.w r2, r2, #128 @ 0x80
  20984. 80099c0: 433a orrs r2, r7
  20985. TIMx->CR1 = tmpcr1;
  20986. 80099c2: 601a str r2, [r3, #0]
  20987. TIMx->ARR = (uint32_t)Structure->Period ;
  20988. 80099c4: 62de str r6, [r3, #44] @ 0x2c
  20989. TIMx->PSC = Structure->Prescaler;
  20990. 80099c6: 629d str r5, [r3, #40] @ 0x28
  20991. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  20992. 80099c8: e01d b.n 8009a06 <HAL_TIM_Base_Init+0xc6>
  20993. tmpcr1 |= Structure->CounterMode;
  20994. 80099ca: 68a0 ldr r0, [r4, #8]
  20995. tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
  20996. 80099cc: f022 0270 bic.w r2, r2, #112 @ 0x70
  20997. tmpcr1 |= Structure->CounterMode;
  20998. 80099d0: 4302 orrs r2, r0
  20999. tmpcr1 |= (uint32_t)Structure->ClockDivision;
  21000. 80099d2: 6920 ldr r0, [r4, #16]
  21001. tmpcr1 &= ~TIM_CR1_CKD;
  21002. 80099d4: f422 7240 bic.w r2, r2, #768 @ 0x300
  21003. tmpcr1 |= (uint32_t)Structure->ClockDivision;
  21004. 80099d8: 4302 orrs r2, r0
  21005. MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  21006. 80099da: f022 0280 bic.w r2, r2, #128 @ 0x80
  21007. 80099de: 433a orrs r2, r7
  21008. TIMx->CR1 = tmpcr1;
  21009. 80099e0: 601a str r2, [r3, #0]
  21010. TIMx->ARR = (uint32_t)Structure->Period ;
  21011. 80099e2: 62de str r6, [r3, #44] @ 0x2c
  21012. TIMx->PSC = Structure->Prescaler;
  21013. 80099e4: 629d str r5, [r3, #40] @ 0x28
  21014. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  21015. 80099e6: b961 cbnz r1, 8009a02 <HAL_TIM_Base_Init+0xc2>
  21016. 80099e8: f1be 0f00 cmp.w lr, #0
  21017. 80099ec: d109 bne.n 8009a02 <HAL_TIM_Base_Init+0xc2>
  21018. if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  21019. 80099ee: 4925 ldr r1, [pc, #148] @ (8009a84 <HAL_TIM_Base_Init+0x144>)
  21020. 80099f0: 4a22 ldr r2, [pc, #136] @ (8009a7c <HAL_TIM_Base_Init+0x13c>)
  21021. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  21022. 80099f2: 4293 cmp r3, r2
  21023. 80099f4: bf18 it ne
  21024. 80099f6: 428b cmpne r3, r1
  21025. 80099f8: d003 beq.n 8009a02 <HAL_TIM_Base_Init+0xc2>
  21026. if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  21027. 80099fa: f502 6280 add.w r2, r2, #1024 @ 0x400
  21028. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  21029. 80099fe: 4293 cmp r3, r2
  21030. 8009a00: d101 bne.n 8009a06 <HAL_TIM_Base_Init+0xc6>
  21031. TIMx->RCR = Structure->RepetitionCounter;
  21032. 8009a02: 6962 ldr r2, [r4, #20]
  21033. 8009a04: 631a str r2, [r3, #48] @ 0x30
  21034. TIMx->EGR = TIM_EGR_UG;
  21035. 8009a06: 2201 movs r2, #1
  21036. 8009a08: 615a str r2, [r3, #20]
  21037. if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
  21038. 8009a0a: 691a ldr r2, [r3, #16]
  21039. 8009a0c: 07d2 lsls r2, r2, #31
  21040. 8009a0e: d503 bpl.n 8009a18 <HAL_TIM_Base_Init+0xd8>
  21041. CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
  21042. 8009a10: 691a ldr r2, [r3, #16]
  21043. 8009a12: f022 0201 bic.w r2, r2, #1
  21044. 8009a16: 611a str r2, [r3, #16]
  21045. htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  21046. 8009a18: 2301 movs r3, #1
  21047. return HAL_OK;
  21048. 8009a1a: 2000 movs r0, #0
  21049. htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  21050. 8009a1c: f884 3048 strb.w r3, [r4, #72] @ 0x48
  21051. TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  21052. 8009a20: f884 303e strb.w r3, [r4, #62] @ 0x3e
  21053. 8009a24: f884 303f strb.w r3, [r4, #63] @ 0x3f
  21054. 8009a28: f884 3040 strb.w r3, [r4, #64] @ 0x40
  21055. 8009a2c: f884 3041 strb.w r3, [r4, #65] @ 0x41
  21056. 8009a30: f884 3042 strb.w r3, [r4, #66] @ 0x42
  21057. 8009a34: f884 3043 strb.w r3, [r4, #67] @ 0x43
  21058. TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  21059. 8009a38: f884 3044 strb.w r3, [r4, #68] @ 0x44
  21060. 8009a3c: f884 3045 strb.w r3, [r4, #69] @ 0x45
  21061. 8009a40: f884 3046 strb.w r3, [r4, #70] @ 0x46
  21062. 8009a44: f884 3047 strb.w r3, [r4, #71] @ 0x47
  21063. htim->State = HAL_TIM_STATE_READY;
  21064. 8009a48: f884 303d strb.w r3, [r4, #61] @ 0x3d
  21065. }
  21066. 8009a4c: bdf8 pop {r3, r4, r5, r6, r7, pc}
  21067. htim->Lock = HAL_UNLOCKED;
  21068. 8009a4e: f880 203c strb.w r2, [r0, #60] @ 0x3c
  21069. HAL_TIM_Base_MspInit(htim);
  21070. 8009a52: f7f9 f95b bl 8002d0c <HAL_TIM_Base_MspInit>
  21071. 8009a56: e77e b.n 8009956 <HAL_TIM_Base_Init+0x16>
  21072. tmpcr1 |= (uint32_t)Structure->ClockDivision;
  21073. 8009a58: 6921 ldr r1, [r4, #16]
  21074. tmpcr1 &= ~TIM_CR1_CKD;
  21075. 8009a5a: f422 7240 bic.w r2, r2, #768 @ 0x300
  21076. tmpcr1 |= (uint32_t)Structure->ClockDivision;
  21077. 8009a5e: 430a orrs r2, r1
  21078. MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  21079. 8009a60: f022 0280 bic.w r2, r2, #128 @ 0x80
  21080. 8009a64: 433a orrs r2, r7
  21081. TIMx->CR1 = tmpcr1;
  21082. 8009a66: 601a str r2, [r3, #0]
  21083. TIMx->ARR = (uint32_t)Structure->Period ;
  21084. 8009a68: 62de str r6, [r3, #44] @ 0x2c
  21085. TIMx->PSC = Structure->Prescaler;
  21086. 8009a6a: 629d str r5, [r3, #40] @ 0x28
  21087. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  21088. 8009a6c: e7bf b.n 80099ee <HAL_TIM_Base_Init+0xae>
  21089. return HAL_ERROR;
  21090. 8009a6e: 2001 movs r0, #1
  21091. }
  21092. 8009a70: 4770 bx lr
  21093. 8009a72: bf00 nop
  21094. 8009a74: 40010000 .word 0x40010000
  21095. 8009a78: 40010400 .word 0x40010400
  21096. 8009a7c: 40014000 .word 0x40014000
  21097. 8009a80: 40014400 .word 0x40014400
  21098. 8009a84: 40014800 .word 0x40014800
  21099. 8009a88: 40000400 .word 0x40000400
  21100. 08009a8c <HAL_TIM_Base_Start>:
  21101. if (htim->State != HAL_TIM_STATE_READY)
  21102. 8009a8c: f890 303d ldrb.w r3, [r0, #61] @ 0x3d
  21103. 8009a90: 2b01 cmp r3, #1
  21104. 8009a92: d139 bne.n 8009b08 <HAL_TIM_Base_Start+0x7c>
  21105. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  21106. 8009a94: 6802 ldr r2, [r0, #0]
  21107. 8009a96: 4b1d ldr r3, [pc, #116] @ (8009b0c <HAL_TIM_Base_Start+0x80>)
  21108. 8009a98: 491d ldr r1, [pc, #116] @ (8009b10 <HAL_TIM_Base_Start+0x84>)
  21109. 8009a9a: f1b2 4f80 cmp.w r2, #1073741824 @ 0x40000000
  21110. 8009a9e: bf18 it ne
  21111. 8009aa0: 429a cmpne r2, r3
  21112. {
  21113. 8009aa2: b430 push {r4, r5}
  21114. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  21115. 8009aa4: bf0c ite eq
  21116. 8009aa6: 2301 moveq r3, #1
  21117. 8009aa8: 2300 movne r3, #0
  21118. 8009aaa: 4d1a ldr r5, [pc, #104] @ (8009b14 <HAL_TIM_Base_Start+0x88>)
  21119. htim->State = HAL_TIM_STATE_BUSY;
  21120. 8009aac: 2402 movs r4, #2
  21121. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  21122. 8009aae: 42aa cmp r2, r5
  21123. 8009ab0: bf08 it eq
  21124. 8009ab2: f043 0301 orreq.w r3, r3, #1
  21125. htim->State = HAL_TIM_STATE_BUSY;
  21126. 8009ab6: f880 403d strb.w r4, [r0, #61] @ 0x3d
  21127. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  21128. 8009aba: 4c17 ldr r4, [pc, #92] @ (8009b18 <HAL_TIM_Base_Start+0x8c>)
  21129. 8009abc: 428a cmp r2, r1
  21130. 8009abe: bf08 it eq
  21131. 8009ac0: f043 0301 orreq.w r3, r3, #1
  21132. 8009ac4: 4815 ldr r0, [pc, #84] @ (8009b1c <HAL_TIM_Base_Start+0x90>)
  21133. 8009ac6: f501 5180 add.w r1, r1, #4096 @ 0x1000
  21134. 8009aca: 42a2 cmp r2, r4
  21135. 8009acc: bf08 it eq
  21136. 8009ace: f043 0301 orreq.w r3, r3, #1
  21137. 8009ad2: 4282 cmp r2, r0
  21138. 8009ad4: bf08 it eq
  21139. 8009ad6: f043 0301 orreq.w r3, r3, #1
  21140. 8009ada: 428a cmp r2, r1
  21141. 8009adc: bf08 it eq
  21142. 8009ade: f043 0301 orreq.w r3, r3, #1
  21143. 8009ae2: b913 cbnz r3, 8009aea <HAL_TIM_Base_Start+0x5e>
  21144. 8009ae4: 4b0e ldr r3, [pc, #56] @ (8009b20 <HAL_TIM_Base_Start+0x94>)
  21145. 8009ae6: 429a cmp r2, r3
  21146. 8009ae8: d107 bne.n 8009afa <HAL_TIM_Base_Start+0x6e>
  21147. tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  21148. 8009aea: 6891 ldr r1, [r2, #8]
  21149. 8009aec: 4b0d ldr r3, [pc, #52] @ (8009b24 <HAL_TIM_Base_Start+0x98>)
  21150. 8009aee: 400b ands r3, r1
  21151. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  21152. 8009af0: 2b06 cmp r3, #6
  21153. 8009af2: d006 beq.n 8009b02 <HAL_TIM_Base_Start+0x76>
  21154. 8009af4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
  21155. 8009af8: d003 beq.n 8009b02 <HAL_TIM_Base_Start+0x76>
  21156. __HAL_TIM_ENABLE(htim);
  21157. 8009afa: 6813 ldr r3, [r2, #0]
  21158. 8009afc: f043 0301 orr.w r3, r3, #1
  21159. 8009b00: 6013 str r3, [r2, #0]
  21160. return HAL_OK;
  21161. 8009b02: 2000 movs r0, #0
  21162. }
  21163. 8009b04: bc30 pop {r4, r5}
  21164. 8009b06: 4770 bx lr
  21165. return HAL_ERROR;
  21166. 8009b08: 2001 movs r0, #1
  21167. }
  21168. 8009b0a: 4770 bx lr
  21169. 8009b0c: 40010000 .word 0x40010000
  21170. 8009b10: 40000800 .word 0x40000800
  21171. 8009b14: 40000400 .word 0x40000400
  21172. 8009b18: 40000c00 .word 0x40000c00
  21173. 8009b1c: 40010400 .word 0x40010400
  21174. 8009b20: 40014000 .word 0x40014000
  21175. 8009b24: 00010007 .word 0x00010007
  21176. 08009b28 <HAL_TIM_Base_Start_IT>:
  21177. if (htim->State != HAL_TIM_STATE_READY)
  21178. 8009b28: f890 303d ldrb.w r3, [r0, #61] @ 0x3d
  21179. 8009b2c: 2b01 cmp r3, #1
  21180. 8009b2e: d13d bne.n 8009bac <HAL_TIM_Base_Start_IT+0x84>
  21181. __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
  21182. 8009b30: 6802 ldr r2, [r0, #0]
  21183. htim->State = HAL_TIM_STATE_BUSY;
  21184. 8009b32: 2102 movs r1, #2
  21185. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  21186. 8009b34: 4b1e ldr r3, [pc, #120] @ (8009bb0 <HAL_TIM_Base_Start_IT+0x88>)
  21187. 8009b36: f1b2 4f80 cmp.w r2, #1073741824 @ 0x40000000
  21188. 8009b3a: bf18 it ne
  21189. 8009b3c: 429a cmpne r2, r3
  21190. {
  21191. 8009b3e: b430 push {r4, r5}
  21192. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  21193. 8009b40: bf0c ite eq
  21194. 8009b42: 2301 moveq r3, #1
  21195. 8009b44: 2300 movne r3, #0
  21196. 8009b46: 4d1b ldr r5, [pc, #108] @ (8009bb4 <HAL_TIM_Base_Start_IT+0x8c>)
  21197. 8009b48: 4c1b ldr r4, [pc, #108] @ (8009bb8 <HAL_TIM_Base_Start_IT+0x90>)
  21198. 8009b4a: 42aa cmp r2, r5
  21199. 8009b4c: bf08 it eq
  21200. 8009b4e: f043 0301 orreq.w r3, r3, #1
  21201. htim->State = HAL_TIM_STATE_BUSY;
  21202. 8009b52: f880 103d strb.w r1, [r0, #61] @ 0x3d
  21203. __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
  21204. 8009b56: 68d1 ldr r1, [r2, #12]
  21205. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  21206. 8009b58: 42a2 cmp r2, r4
  21207. 8009b5a: bf08 it eq
  21208. 8009b5c: f043 0301 orreq.w r3, r3, #1
  21209. 8009b60: f504 6480 add.w r4, r4, #1024 @ 0x400
  21210. __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
  21211. 8009b64: f041 0101 orr.w r1, r1, #1
  21212. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  21213. 8009b68: 4814 ldr r0, [pc, #80] @ (8009bbc <HAL_TIM_Base_Start_IT+0x94>)
  21214. 8009b6a: 42a2 cmp r2, r4
  21215. 8009b6c: bf08 it eq
  21216. 8009b6e: f043 0301 orreq.w r3, r3, #1
  21217. __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
  21218. 8009b72: 60d1 str r1, [r2, #12]
  21219. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  21220. 8009b74: 4282 cmp r2, r0
  21221. 8009b76: bf08 it eq
  21222. 8009b78: f043 0301 orreq.w r3, r3, #1
  21223. 8009b7c: 4910 ldr r1, [pc, #64] @ (8009bc0 <HAL_TIM_Base_Start_IT+0x98>)
  21224. 8009b7e: 428a cmp r2, r1
  21225. 8009b80: bf08 it eq
  21226. 8009b82: f043 0301 orreq.w r3, r3, #1
  21227. 8009b86: b913 cbnz r3, 8009b8e <HAL_TIM_Base_Start_IT+0x66>
  21228. 8009b88: 4b0e ldr r3, [pc, #56] @ (8009bc4 <HAL_TIM_Base_Start_IT+0x9c>)
  21229. 8009b8a: 429a cmp r2, r3
  21230. 8009b8c: d107 bne.n 8009b9e <HAL_TIM_Base_Start_IT+0x76>
  21231. tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  21232. 8009b8e: 6891 ldr r1, [r2, #8]
  21233. 8009b90: 4b0d ldr r3, [pc, #52] @ (8009bc8 <HAL_TIM_Base_Start_IT+0xa0>)
  21234. 8009b92: 400b ands r3, r1
  21235. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  21236. 8009b94: 2b06 cmp r3, #6
  21237. 8009b96: d006 beq.n 8009ba6 <HAL_TIM_Base_Start_IT+0x7e>
  21238. 8009b98: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
  21239. 8009b9c: d003 beq.n 8009ba6 <HAL_TIM_Base_Start_IT+0x7e>
  21240. __HAL_TIM_ENABLE(htim);
  21241. 8009b9e: 6813 ldr r3, [r2, #0]
  21242. 8009ba0: f043 0301 orr.w r3, r3, #1
  21243. 8009ba4: 6013 str r3, [r2, #0]
  21244. return HAL_OK;
  21245. 8009ba6: 2000 movs r0, #0
  21246. }
  21247. 8009ba8: bc30 pop {r4, r5}
  21248. 8009baa: 4770 bx lr
  21249. return HAL_ERROR;
  21250. 8009bac: 2001 movs r0, #1
  21251. }
  21252. 8009bae: 4770 bx lr
  21253. 8009bb0: 40010000 .word 0x40010000
  21254. 8009bb4: 40000400 .word 0x40000400
  21255. 8009bb8: 40000800 .word 0x40000800
  21256. 8009bbc: 40010400 .word 0x40010400
  21257. 8009bc0: 40001800 .word 0x40001800
  21258. 8009bc4: 40014000 .word 0x40014000
  21259. 8009bc8: 00010007 .word 0x00010007
  21260. 08009bcc <HAL_TIM_PWM_Init>:
  21261. if (htim == NULL)
  21262. 8009bcc: 2800 cmp r0, #0
  21263. 8009bce: f000 8094 beq.w 8009cfa <HAL_TIM_PWM_Init+0x12e>
  21264. {
  21265. 8009bd2: b5f8 push {r3, r4, r5, r6, r7, lr}
  21266. if (htim->State == HAL_TIM_STATE_RESET)
  21267. 8009bd4: f890 303d ldrb.w r3, [r0, #61] @ 0x3d
  21268. 8009bd8: 4604 mov r4, r0
  21269. 8009bda: f003 02ff and.w r2, r3, #255 @ 0xff
  21270. 8009bde: 2b00 cmp r3, #0
  21271. 8009be0: d07b beq.n 8009cda <HAL_TIM_PWM_Init+0x10e>
  21272. TIM_Base_SetConfig(htim->Instance, &htim->Init);
  21273. 8009be2: 6823 ldr r3, [r4, #0]
  21274. htim->State = HAL_TIM_STATE_BUSY;
  21275. 8009be4: 2202 movs r2, #2
  21276. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  21277. 8009be6: 4946 ldr r1, [pc, #280] @ (8009d00 <HAL_TIM_PWM_Init+0x134>)
  21278. 8009be8: 4846 ldr r0, [pc, #280] @ (8009d04 <HAL_TIM_PWM_Init+0x138>)
  21279. 8009bea: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
  21280. 8009bee: eba3 0101 sub.w r1, r3, r1
  21281. htim->State = HAL_TIM_STATE_BUSY;
  21282. 8009bf2: f884 203d strb.w r2, [r4, #61] @ 0x3d
  21283. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  21284. 8009bf6: eba3 0e00 sub.w lr, r3, r0
  21285. tmpcr1 = TIMx->CR1;
  21286. 8009bfa: 681a ldr r2, [r3, #0]
  21287. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  21288. 8009bfc: fab1 f181 clz r1, r1
  21289. MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  21290. 8009c00: 69a7 ldr r7, [r4, #24]
  21291. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  21292. 8009c02: fabe fe8e clz lr, lr
  21293. TIMx->PSC = Structure->Prescaler;
  21294. 8009c06: 6865 ldr r5, [r4, #4]
  21295. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  21296. 8009c08: ea4f 1151 mov.w r1, r1, lsr #5
  21297. TIMx->ARR = (uint32_t)Structure->Period ;
  21298. 8009c0c: 68e6 ldr r6, [r4, #12]
  21299. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  21300. 8009c0e: ea4f 1e5e mov.w lr, lr, lsr #5
  21301. 8009c12: d020 beq.n 8009c56 <HAL_TIM_PWM_Init+0x8a>
  21302. 8009c14: b9f9 cbnz r1, 8009c56 <HAL_TIM_PWM_Init+0x8a>
  21303. 8009c16: f8df c0fc ldr.w ip, [pc, #252] @ 8009d14 <HAL_TIM_PWM_Init+0x148>
  21304. 8009c1a: 4563 cmp r3, ip
  21305. 8009c1c: d01b beq.n 8009c56 <HAL_TIM_PWM_Init+0x8a>
  21306. 8009c1e: f50c 6c80 add.w ip, ip, #1024 @ 0x400
  21307. 8009c22: 4563 cmp r3, ip
  21308. 8009c24: d017 beq.n 8009c56 <HAL_TIM_PWM_Init+0x8a>
  21309. 8009c26: f50c 6c80 add.w ip, ip, #1024 @ 0x400
  21310. 8009c2a: 4563 cmp r3, ip
  21311. 8009c2c: d013 beq.n 8009c56 <HAL_TIM_PWM_Init+0x8a>
  21312. 8009c2e: f1be 0f00 cmp.w lr, #0
  21313. 8009c32: d110 bne.n 8009c56 <HAL_TIM_PWM_Init+0x8a>
  21314. if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  21315. 8009c34: 4834 ldr r0, [pc, #208] @ (8009d08 <HAL_TIM_PWM_Init+0x13c>)
  21316. 8009c36: 4935 ldr r1, [pc, #212] @ (8009d0c <HAL_TIM_PWM_Init+0x140>)
  21317. 8009c38: 428b cmp r3, r1
  21318. 8009c3a: bf18 it ne
  21319. 8009c3c: 4283 cmpne r3, r0
  21320. 8009c3e: d051 beq.n 8009ce4 <HAL_TIM_PWM_Init+0x118>
  21321. 8009c40: f501 6180 add.w r1, r1, #1024 @ 0x400
  21322. 8009c44: 428b cmp r3, r1
  21323. 8009c46: d04d beq.n 8009ce4 <HAL_TIM_PWM_Init+0x118>
  21324. MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  21325. 8009c48: f022 0280 bic.w r2, r2, #128 @ 0x80
  21326. 8009c4c: 433a orrs r2, r7
  21327. TIMx->CR1 = tmpcr1;
  21328. 8009c4e: 601a str r2, [r3, #0]
  21329. TIMx->ARR = (uint32_t)Structure->Period ;
  21330. 8009c50: 62de str r6, [r3, #44] @ 0x2c
  21331. TIMx->PSC = Structure->Prescaler;
  21332. 8009c52: 629d str r5, [r3, #40] @ 0x28
  21333. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  21334. 8009c54: e01d b.n 8009c92 <HAL_TIM_PWM_Init+0xc6>
  21335. tmpcr1 |= Structure->CounterMode;
  21336. 8009c56: 68a0 ldr r0, [r4, #8]
  21337. tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
  21338. 8009c58: f022 0270 bic.w r2, r2, #112 @ 0x70
  21339. tmpcr1 |= Structure->CounterMode;
  21340. 8009c5c: 4302 orrs r2, r0
  21341. tmpcr1 |= (uint32_t)Structure->ClockDivision;
  21342. 8009c5e: 6920 ldr r0, [r4, #16]
  21343. tmpcr1 &= ~TIM_CR1_CKD;
  21344. 8009c60: f422 7240 bic.w r2, r2, #768 @ 0x300
  21345. tmpcr1 |= (uint32_t)Structure->ClockDivision;
  21346. 8009c64: 4302 orrs r2, r0
  21347. MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  21348. 8009c66: f022 0280 bic.w r2, r2, #128 @ 0x80
  21349. 8009c6a: 433a orrs r2, r7
  21350. TIMx->CR1 = tmpcr1;
  21351. 8009c6c: 601a str r2, [r3, #0]
  21352. TIMx->ARR = (uint32_t)Structure->Period ;
  21353. 8009c6e: 62de str r6, [r3, #44] @ 0x2c
  21354. TIMx->PSC = Structure->Prescaler;
  21355. 8009c70: 629d str r5, [r3, #40] @ 0x28
  21356. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  21357. 8009c72: b961 cbnz r1, 8009c8e <HAL_TIM_PWM_Init+0xc2>
  21358. 8009c74: f1be 0f00 cmp.w lr, #0
  21359. 8009c78: d109 bne.n 8009c8e <HAL_TIM_PWM_Init+0xc2>
  21360. if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  21361. 8009c7a: 4925 ldr r1, [pc, #148] @ (8009d10 <HAL_TIM_PWM_Init+0x144>)
  21362. 8009c7c: 4a22 ldr r2, [pc, #136] @ (8009d08 <HAL_TIM_PWM_Init+0x13c>)
  21363. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  21364. 8009c7e: 4293 cmp r3, r2
  21365. 8009c80: bf18 it ne
  21366. 8009c82: 428b cmpne r3, r1
  21367. 8009c84: d003 beq.n 8009c8e <HAL_TIM_PWM_Init+0xc2>
  21368. if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  21369. 8009c86: f502 6280 add.w r2, r2, #1024 @ 0x400
  21370. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  21371. 8009c8a: 4293 cmp r3, r2
  21372. 8009c8c: d101 bne.n 8009c92 <HAL_TIM_PWM_Init+0xc6>
  21373. TIMx->RCR = Structure->RepetitionCounter;
  21374. 8009c8e: 6962 ldr r2, [r4, #20]
  21375. 8009c90: 631a str r2, [r3, #48] @ 0x30
  21376. TIMx->EGR = TIM_EGR_UG;
  21377. 8009c92: 2201 movs r2, #1
  21378. 8009c94: 615a str r2, [r3, #20]
  21379. if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
  21380. 8009c96: 691a ldr r2, [r3, #16]
  21381. 8009c98: 07d2 lsls r2, r2, #31
  21382. 8009c9a: d503 bpl.n 8009ca4 <HAL_TIM_PWM_Init+0xd8>
  21383. CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
  21384. 8009c9c: 691a ldr r2, [r3, #16]
  21385. 8009c9e: f022 0201 bic.w r2, r2, #1
  21386. 8009ca2: 611a str r2, [r3, #16]
  21387. htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  21388. 8009ca4: 2301 movs r3, #1
  21389. return HAL_OK;
  21390. 8009ca6: 2000 movs r0, #0
  21391. htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  21392. 8009ca8: f884 3048 strb.w r3, [r4, #72] @ 0x48
  21393. TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  21394. 8009cac: f884 303e strb.w r3, [r4, #62] @ 0x3e
  21395. 8009cb0: f884 303f strb.w r3, [r4, #63] @ 0x3f
  21396. 8009cb4: f884 3040 strb.w r3, [r4, #64] @ 0x40
  21397. 8009cb8: f884 3041 strb.w r3, [r4, #65] @ 0x41
  21398. 8009cbc: f884 3042 strb.w r3, [r4, #66] @ 0x42
  21399. 8009cc0: f884 3043 strb.w r3, [r4, #67] @ 0x43
  21400. TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  21401. 8009cc4: f884 3044 strb.w r3, [r4, #68] @ 0x44
  21402. 8009cc8: f884 3045 strb.w r3, [r4, #69] @ 0x45
  21403. 8009ccc: f884 3046 strb.w r3, [r4, #70] @ 0x46
  21404. 8009cd0: f884 3047 strb.w r3, [r4, #71] @ 0x47
  21405. htim->State = HAL_TIM_STATE_READY;
  21406. 8009cd4: f884 303d strb.w r3, [r4, #61] @ 0x3d
  21407. }
  21408. 8009cd8: bdf8 pop {r3, r4, r5, r6, r7, pc}
  21409. htim->Lock = HAL_UNLOCKED;
  21410. 8009cda: f880 203c strb.w r2, [r0, #60] @ 0x3c
  21411. HAL_TIM_PWM_MspInit(htim);
  21412. 8009cde: f7f8 ffe7 bl 8002cb0 <HAL_TIM_PWM_MspInit>
  21413. 8009ce2: e77e b.n 8009be2 <HAL_TIM_PWM_Init+0x16>
  21414. tmpcr1 |= (uint32_t)Structure->ClockDivision;
  21415. 8009ce4: 6921 ldr r1, [r4, #16]
  21416. tmpcr1 &= ~TIM_CR1_CKD;
  21417. 8009ce6: f422 7240 bic.w r2, r2, #768 @ 0x300
  21418. tmpcr1 |= (uint32_t)Structure->ClockDivision;
  21419. 8009cea: 430a orrs r2, r1
  21420. MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  21421. 8009cec: f022 0280 bic.w r2, r2, #128 @ 0x80
  21422. 8009cf0: 433a orrs r2, r7
  21423. TIMx->CR1 = tmpcr1;
  21424. 8009cf2: 601a str r2, [r3, #0]
  21425. TIMx->ARR = (uint32_t)Structure->Period ;
  21426. 8009cf4: 62de str r6, [r3, #44] @ 0x2c
  21427. TIMx->PSC = Structure->Prescaler;
  21428. 8009cf6: 629d str r5, [r3, #40] @ 0x28
  21429. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  21430. 8009cf8: e7bf b.n 8009c7a <HAL_TIM_PWM_Init+0xae>
  21431. return HAL_ERROR;
  21432. 8009cfa: 2001 movs r0, #1
  21433. }
  21434. 8009cfc: 4770 bx lr
  21435. 8009cfe: bf00 nop
  21436. 8009d00: 40010000 .word 0x40010000
  21437. 8009d04: 40010400 .word 0x40010400
  21438. 8009d08: 40014000 .word 0x40014000
  21439. 8009d0c: 40014400 .word 0x40014400
  21440. 8009d10: 40014800 .word 0x40014800
  21441. 8009d14: 40000400 .word 0x40000400
  21442. 08009d18 <HAL_TIM_PWM_Start>:
  21443. HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  21444. 8009d18: 2910 cmp r1, #16
  21445. 8009d1a: d80a bhi.n 8009d32 <HAL_TIM_PWM_Start+0x1a>
  21446. 8009d1c: e8df f001 tbb [pc, r1]
  21447. 8009d20: 09090919 .word 0x09090919
  21448. 8009d24: 09090956 .word 0x09090956
  21449. 8009d28: 0909095e .word 0x0909095e
  21450. 8009d2c: 09090966 .word 0x09090966
  21451. 8009d30: 6e .byte 0x6e
  21452. 8009d31: 00 .byte 0x00
  21453. 8009d32: f890 3043 ldrb.w r3, [r0, #67] @ 0x43
  21454. 8009d36: 2b01 cmp r3, #1
  21455. 8009d38: d171 bne.n 8009e1e <HAL_TIM_PWM_Start+0x106>
  21456. 8009d3a: 1f0b subs r3, r1, #4
  21457. 8009d3c: 2b0c cmp r3, #12
  21458. 8009d3e: d865 bhi.n 8009e0c <HAL_TIM_PWM_Start+0xf4>
  21459. 8009d40: e8df f003 tbb [pc, r3]
  21460. 8009d44: 64646448 .word 0x64646448
  21461. 8009d48: 64646450 .word 0x64646450
  21462. 8009d4c: 64646458 .word 0x64646458
  21463. 8009d50: 60 .byte 0x60
  21464. 8009d51: 00 .byte 0x00
  21465. 8009d52: f890 303e ldrb.w r3, [r0, #62] @ 0x3e
  21466. 8009d56: 2b01 cmp r3, #1
  21467. 8009d58: d161 bne.n 8009e1e <HAL_TIM_PWM_Start+0x106>
  21468. 8009d5a: 2302 movs r3, #2
  21469. 8009d5c: f880 303e strb.w r3, [r0, #62] @ 0x3e
  21470. 8009d60: 6803 ldr r3, [r0, #0]
  21471. 8009d62: f001 011f and.w r1, r1, #31
  21472. 8009d66: 2201 movs r2, #1
  21473. 8009d68: 6a18 ldr r0, [r3, #32]
  21474. 8009d6a: 408a lsls r2, r1
  21475. 8009d6c: ea20 0002 bic.w r0, r0, r2
  21476. 8009d70: b410 push {r4}
  21477. 8009d72: 6218 str r0, [r3, #32]
  21478. 8009d74: 4c33 ldr r4, [pc, #204] @ (8009e44 <HAL_TIM_PWM_Start+0x12c>)
  21479. 8009d76: 6a19 ldr r1, [r3, #32]
  21480. 8009d78: 42a3 cmp r3, r4
  21481. 8009d7a: ea42 0201 orr.w r2, r2, r1
  21482. 8009d7e: 621a str r2, [r3, #32]
  21483. 8009d80: d048 beq.n 8009e14 <HAL_TIM_PWM_Start+0xfc>
  21484. 8009d82: 4a31 ldr r2, [pc, #196] @ (8009e48 <HAL_TIM_PWM_Start+0x130>)
  21485. 8009d84: 4293 cmp r3, r2
  21486. 8009d86: d045 beq.n 8009e14 <HAL_TIM_PWM_Start+0xfc>
  21487. 8009d88: f502 5270 add.w r2, r2, #15360 @ 0x3c00
  21488. 8009d8c: 4293 cmp r3, r2
  21489. 8009d8e: d041 beq.n 8009e14 <HAL_TIM_PWM_Start+0xfc>
  21490. 8009d90: f502 6280 add.w r2, r2, #1024 @ 0x400
  21491. 8009d94: 4293 cmp r3, r2
  21492. 8009d96: d044 beq.n 8009e22 <HAL_TIM_PWM_Start+0x10a>
  21493. 8009d98: f502 6280 add.w r2, r2, #1024 @ 0x400
  21494. 8009d9c: 4293 cmp r3, r2
  21495. 8009d9e: d040 beq.n 8009e22 <HAL_TIM_PWM_Start+0x10a>
  21496. 8009da0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
  21497. 8009da4: d002 beq.n 8009dac <HAL_TIM_PWM_Start+0x94>
  21498. 8009da6: 4a29 ldr r2, [pc, #164] @ (8009e4c <HAL_TIM_PWM_Start+0x134>)
  21499. 8009da8: 4293 cmp r3, r2
  21500. 8009daa: d13f bne.n 8009e2c <HAL_TIM_PWM_Start+0x114>
  21501. 8009dac: 6899 ldr r1, [r3, #8]
  21502. 8009dae: 4a28 ldr r2, [pc, #160] @ (8009e50 <HAL_TIM_PWM_Start+0x138>)
  21503. 8009db0: 400a ands r2, r1
  21504. 8009db2: 2a06 cmp r2, #6
  21505. 8009db4: d006 beq.n 8009dc4 <HAL_TIM_PWM_Start+0xac>
  21506. 8009db6: f5b2 3f80 cmp.w r2, #65536 @ 0x10000
  21507. 8009dba: d003 beq.n 8009dc4 <HAL_TIM_PWM_Start+0xac>
  21508. 8009dbc: 681a ldr r2, [r3, #0]
  21509. 8009dbe: f042 0201 orr.w r2, r2, #1
  21510. 8009dc2: 601a str r2, [r3, #0]
  21511. 8009dc4: 2000 movs r0, #0
  21512. 8009dc6: f85d 4b04 ldr.w r4, [sp], #4
  21513. 8009dca: 4770 bx lr
  21514. 8009dcc: f890 303f ldrb.w r3, [r0, #63] @ 0x3f
  21515. 8009dd0: 2b01 cmp r3, #1
  21516. 8009dd2: d124 bne.n 8009e1e <HAL_TIM_PWM_Start+0x106>
  21517. 8009dd4: 2302 movs r3, #2
  21518. 8009dd6: f880 303f strb.w r3, [r0, #63] @ 0x3f
  21519. 8009dda: e7c1 b.n 8009d60 <HAL_TIM_PWM_Start+0x48>
  21520. 8009ddc: f890 3040 ldrb.w r3, [r0, #64] @ 0x40
  21521. 8009de0: 2b01 cmp r3, #1
  21522. 8009de2: d11c bne.n 8009e1e <HAL_TIM_PWM_Start+0x106>
  21523. 8009de4: 2302 movs r3, #2
  21524. 8009de6: f880 3040 strb.w r3, [r0, #64] @ 0x40
  21525. 8009dea: e7b9 b.n 8009d60 <HAL_TIM_PWM_Start+0x48>
  21526. 8009dec: f890 3041 ldrb.w r3, [r0, #65] @ 0x41
  21527. 8009df0: 2b01 cmp r3, #1
  21528. 8009df2: d114 bne.n 8009e1e <HAL_TIM_PWM_Start+0x106>
  21529. 8009df4: 2302 movs r3, #2
  21530. 8009df6: f880 3041 strb.w r3, [r0, #65] @ 0x41
  21531. 8009dfa: e7b1 b.n 8009d60 <HAL_TIM_PWM_Start+0x48>
  21532. 8009dfc: f890 3042 ldrb.w r3, [r0, #66] @ 0x42
  21533. 8009e00: 2b01 cmp r3, #1
  21534. 8009e02: d10c bne.n 8009e1e <HAL_TIM_PWM_Start+0x106>
  21535. 8009e04: 2302 movs r3, #2
  21536. 8009e06: f880 3042 strb.w r3, [r0, #66] @ 0x42
  21537. 8009e0a: e7a9 b.n 8009d60 <HAL_TIM_PWM_Start+0x48>
  21538. 8009e0c: 2302 movs r3, #2
  21539. 8009e0e: f880 3043 strb.w r3, [r0, #67] @ 0x43
  21540. 8009e12: e7a5 b.n 8009d60 <HAL_TIM_PWM_Start+0x48>
  21541. 8009e14: 6c5a ldr r2, [r3, #68] @ 0x44
  21542. 8009e16: f442 4200 orr.w r2, r2, #32768 @ 0x8000
  21543. 8009e1a: 645a str r2, [r3, #68] @ 0x44
  21544. 8009e1c: e7c6 b.n 8009dac <HAL_TIM_PWM_Start+0x94>
  21545. 8009e1e: 2001 movs r0, #1
  21546. 8009e20: 4770 bx lr
  21547. 8009e22: 6c5a ldr r2, [r3, #68] @ 0x44
  21548. 8009e24: f442 4200 orr.w r2, r2, #32768 @ 0x8000
  21549. 8009e28: 645a str r2, [r3, #68] @ 0x44
  21550. 8009e2a: e7c7 b.n 8009dbc <HAL_TIM_PWM_Start+0xa4>
  21551. 8009e2c: 4909 ldr r1, [pc, #36] @ (8009e54 <HAL_TIM_PWM_Start+0x13c>)
  21552. 8009e2e: f502 6200 add.w r2, r2, #2048 @ 0x800
  21553. 8009e32: 4293 cmp r3, r2
  21554. 8009e34: bf18 it ne
  21555. 8009e36: 428b cmpne r3, r1
  21556. 8009e38: d0b8 beq.n 8009dac <HAL_TIM_PWM_Start+0x94>
  21557. 8009e3a: f502 6240 add.w r2, r2, #3072 @ 0xc00
  21558. 8009e3e: 4293 cmp r3, r2
  21559. 8009e40: d1bc bne.n 8009dbc <HAL_TIM_PWM_Start+0xa4>
  21560. 8009e42: e7b3 b.n 8009dac <HAL_TIM_PWM_Start+0x94>
  21561. 8009e44: 40010000 .word 0x40010000
  21562. 8009e48: 40010400 .word 0x40010400
  21563. 8009e4c: 40000400 .word 0x40000400
  21564. 8009e50: 00010007 .word 0x00010007
  21565. 8009e54: 40000800 .word 0x40000800
  21566. 08009e58 <HAL_TIM_PWM_Stop>:
  21567. HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  21568. 8009e58: 6803 ldr r3, [r0, #0]
  21569. 8009e5a: f001 0c1f and.w ip, r1, #31
  21570. 8009e5e: 2201 movs r2, #1
  21571. 8009e60: b410 push {r4}
  21572. 8009e62: fa02 f20c lsl.w r2, r2, ip
  21573. 8009e66: 6a1c ldr r4, [r3, #32]
  21574. 8009e68: ea24 0402 bic.w r4, r4, r2
  21575. 8009e6c: 4a37 ldr r2, [pc, #220] @ (8009f4c <HAL_TIM_PWM_Stop+0xf4>)
  21576. 8009e6e: 621c str r4, [r3, #32]
  21577. 8009e70: 6a1c ldr r4, [r3, #32]
  21578. 8009e72: 621c str r4, [r3, #32]
  21579. 8009e74: 4c36 ldr r4, [pc, #216] @ (8009f50 <HAL_TIM_PWM_Stop+0xf8>)
  21580. 8009e76: 42a3 cmp r3, r4
  21581. 8009e78: bf18 it ne
  21582. 8009e7a: 4293 cmpne r3, r2
  21583. 8009e7c: f504 5470 add.w r4, r4, #15360 @ 0x3c00
  21584. 8009e80: bf0c ite eq
  21585. 8009e82: 2201 moveq r2, #1
  21586. 8009e84: 2200 movne r2, #0
  21587. 8009e86: 42a3 cmp r3, r4
  21588. 8009e88: bf08 it eq
  21589. 8009e8a: f042 0201 orreq.w r2, r2, #1
  21590. 8009e8e: f504 6480 add.w r4, r4, #1024 @ 0x400
  21591. 8009e92: 42a3 cmp r3, r4
  21592. 8009e94: bf08 it eq
  21593. 8009e96: f042 0201 orreq.w r2, r2, #1
  21594. 8009e9a: b912 cbnz r2, 8009ea2 <HAL_TIM_PWM_Stop+0x4a>
  21595. 8009e9c: 4a2d ldr r2, [pc, #180] @ (8009f54 <HAL_TIM_PWM_Stop+0xfc>)
  21596. 8009e9e: 4293 cmp r3, r2
  21597. 8009ea0: d10d bne.n 8009ebe <HAL_TIM_PWM_Stop+0x66>
  21598. 8009ea2: 6a1c ldr r4, [r3, #32]
  21599. 8009ea4: f241 1211 movw r2, #4369 @ 0x1111
  21600. 8009ea8: 4214 tst r4, r2
  21601. 8009eaa: d108 bne.n 8009ebe <HAL_TIM_PWM_Stop+0x66>
  21602. 8009eac: 6a1c ldr r4, [r3, #32]
  21603. 8009eae: f240 4244 movw r2, #1092 @ 0x444
  21604. 8009eb2: 4214 tst r4, r2
  21605. 8009eb4: d103 bne.n 8009ebe <HAL_TIM_PWM_Stop+0x66>
  21606. 8009eb6: 6c5a ldr r2, [r3, #68] @ 0x44
  21607. 8009eb8: f422 4200 bic.w r2, r2, #32768 @ 0x8000
  21608. 8009ebc: 645a str r2, [r3, #68] @ 0x44
  21609. 8009ebe: 6a1c ldr r4, [r3, #32]
  21610. 8009ec0: f241 1211 movw r2, #4369 @ 0x1111
  21611. 8009ec4: 4214 tst r4, r2
  21612. 8009ec6: d104 bne.n 8009ed2 <HAL_TIM_PWM_Stop+0x7a>
  21613. 8009ec8: 6a1c ldr r4, [r3, #32]
  21614. 8009eca: f240 4244 movw r2, #1092 @ 0x444
  21615. 8009ece: 4214 tst r4, r2
  21616. 8009ed0: d013 beq.n 8009efa <HAL_TIM_PWM_Stop+0xa2>
  21617. 8009ed2: b931 cbnz r1, 8009ee2 <HAL_TIM_PWM_Stop+0x8a>
  21618. 8009ed4: 2301 movs r3, #1
  21619. 8009ed6: f880 303e strb.w r3, [r0, #62] @ 0x3e
  21620. 8009eda: 2000 movs r0, #0
  21621. 8009edc: f85d 4b04 ldr.w r4, [sp], #4
  21622. 8009ee0: 4770 bx lr
  21623. 8009ee2: 3904 subs r1, #4
  21624. 8009ee4: 290c cmp r1, #12
  21625. 8009ee6: d80d bhi.n 8009f04 <HAL_TIM_PWM_Stop+0xac>
  21626. 8009ee8: e8df f001 tbb [pc, r1]
  21627. 8009eec: 0c0c0c13 .word 0x0c0c0c13
  21628. 8009ef0: 0c0c0c1a .word 0x0c0c0c1a
  21629. 8009ef4: 0c0c0c21 .word 0x0c0c0c21
  21630. 8009ef8: 28 .byte 0x28
  21631. 8009ef9: 00 .byte 0x00
  21632. 8009efa: 681a ldr r2, [r3, #0]
  21633. 8009efc: f022 0201 bic.w r2, r2, #1
  21634. 8009f00: 601a str r2, [r3, #0]
  21635. 8009f02: e7e6 b.n 8009ed2 <HAL_TIM_PWM_Stop+0x7a>
  21636. 8009f04: 2301 movs r3, #1
  21637. 8009f06: f880 3043 strb.w r3, [r0, #67] @ 0x43
  21638. 8009f0a: 2000 movs r0, #0
  21639. 8009f0c: f85d 4b04 ldr.w r4, [sp], #4
  21640. 8009f10: 4770 bx lr
  21641. 8009f12: 2301 movs r3, #1
  21642. 8009f14: f880 303f strb.w r3, [r0, #63] @ 0x3f
  21643. 8009f18: 2000 movs r0, #0
  21644. 8009f1a: f85d 4b04 ldr.w r4, [sp], #4
  21645. 8009f1e: 4770 bx lr
  21646. 8009f20: 2301 movs r3, #1
  21647. 8009f22: f880 3040 strb.w r3, [r0, #64] @ 0x40
  21648. 8009f26: 2000 movs r0, #0
  21649. 8009f28: f85d 4b04 ldr.w r4, [sp], #4
  21650. 8009f2c: 4770 bx lr
  21651. 8009f2e: 2301 movs r3, #1
  21652. 8009f30: f880 3041 strb.w r3, [r0, #65] @ 0x41
  21653. 8009f34: 2000 movs r0, #0
  21654. 8009f36: f85d 4b04 ldr.w r4, [sp], #4
  21655. 8009f3a: 4770 bx lr
  21656. 8009f3c: 2301 movs r3, #1
  21657. 8009f3e: f880 3042 strb.w r3, [r0, #66] @ 0x42
  21658. 8009f42: 2000 movs r0, #0
  21659. 8009f44: f85d 4b04 ldr.w r4, [sp], #4
  21660. 8009f48: 4770 bx lr
  21661. 8009f4a: bf00 nop
  21662. 8009f4c: 40010000 .word 0x40010000
  21663. 8009f50: 40010400 .word 0x40010400
  21664. 8009f54: 40014800 .word 0x40014800
  21665. 08009f58 <HAL_TIM_ConfigClockSource>:
  21666. __HAL_LOCK(htim);
  21667. 8009f58: f890 303c ldrb.w r3, [r0, #60] @ 0x3c
  21668. 8009f5c: 2b01 cmp r3, #1
  21669. 8009f5e: d07e beq.n 800a05e <HAL_TIM_ConfigClockSource+0x106>
  21670. 8009f60: 4602 mov r2, r0
  21671. htim->State = HAL_TIM_STATE_BUSY;
  21672. 8009f62: 2302 movs r3, #2
  21673. {
  21674. 8009f64: b430 push {r4, r5}
  21675. tmpsmcr = htim->Instance->SMCR;
  21676. 8009f66: 6804 ldr r4, [r0, #0]
  21677. __HAL_LOCK(htim);
  21678. 8009f68: 2001 movs r0, #1
  21679. htim->State = HAL_TIM_STATE_BUSY;
  21680. 8009f6a: f882 303d strb.w r3, [r2, #61] @ 0x3d
  21681. __HAL_LOCK(htim);
  21682. 8009f6e: f882 003c strb.w r0, [r2, #60] @ 0x3c
  21683. tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  21684. 8009f72: 4b58 ldr r3, [pc, #352] @ (800a0d4 <HAL_TIM_ConfigClockSource+0x17c>)
  21685. tmpsmcr = htim->Instance->SMCR;
  21686. 8009f74: 68a5 ldr r5, [r4, #8]
  21687. tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  21688. 8009f76: 402b ands r3, r5
  21689. htim->Instance->SMCR = tmpsmcr;
  21690. 8009f78: 60a3 str r3, [r4, #8]
  21691. switch (sClockSourceConfig->ClockSource)
  21692. 8009f7a: 680b ldr r3, [r1, #0]
  21693. 8009f7c: 2b70 cmp r3, #112 @ 0x70
  21694. 8009f7e: f000 8098 beq.w 800a0b2 <HAL_TIM_ConfigClockSource+0x15a>
  21695. 8009f82: d825 bhi.n 8009fd0 <HAL_TIM_ConfigClockSource+0x78>
  21696. 8009f84: 2b50 cmp r3, #80 @ 0x50
  21697. 8009f86: d06c beq.n 800a062 <HAL_TIM_ConfigClockSource+0x10a>
  21698. 8009f88: d938 bls.n 8009ffc <HAL_TIM_ConfigClockSource+0xa4>
  21699. 8009f8a: 2b60 cmp r3, #96 @ 0x60
  21700. 8009f8c: d118 bne.n 8009fc0 <HAL_TIM_ConfigClockSource+0x68>
  21701. sClockSourceConfig->ClockPolarity,
  21702. 8009f8e: 684b ldr r3, [r1, #4]
  21703. sClockSourceConfig->ClockFilter);
  21704. 8009f90: 68cd ldr r5, [r1, #12]
  21705. {
  21706. uint32_t tmpccmr1;
  21707. uint32_t tmpccer;
  21708. /* Disable the Channel 2: Reset the CC2E Bit */
  21709. tmpccer = TIMx->CCER;
  21710. 8009f92: 6a21 ldr r1, [r4, #32]
  21711. TIMx->CCER &= ~TIM_CCER_CC2E;
  21712. 8009f94: 6a20 ldr r0, [r4, #32]
  21713. /* Set the filter */
  21714. tmpccmr1 &= ~TIM_CCMR1_IC2F;
  21715. tmpccmr1 |= (TIM_ICFilter << 12U);
  21716. /* Select the Polarity and set the CC2E Bit */
  21717. tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  21718. 8009f96: f021 01a0 bic.w r1, r1, #160 @ 0xa0
  21719. TIMx->CCER &= ~TIM_CCER_CC2E;
  21720. 8009f9a: f020 0010 bic.w r0, r0, #16
  21721. tmpccer |= (TIM_ICPolarity << 4U);
  21722. 8009f9e: ea41 1103 orr.w r1, r1, r3, lsl #4
  21723. uint32_t tmpsmcr;
  21724. /* Get the TIMx SMCR register value */
  21725. tmpsmcr = TIMx->SMCR;
  21726. /* Reset the TS Bits */
  21727. tmpsmcr &= ~TIM_SMCR_TS;
  21728. 8009fa2: 4b4d ldr r3, [pc, #308] @ (800a0d8 <HAL_TIM_ConfigClockSource+0x180>)
  21729. TIMx->CCER &= ~TIM_CCER_CC2E;
  21730. 8009fa4: 6220 str r0, [r4, #32]
  21731. tmpccmr1 = TIMx->CCMR1;
  21732. 8009fa6: 69a0 ldr r0, [r4, #24]
  21733. tmpccmr1 &= ~TIM_CCMR1_IC2F;
  21734. 8009fa8: f420 4070 bic.w r0, r0, #61440 @ 0xf000
  21735. tmpccmr1 |= (TIM_ICFilter << 12U);
  21736. 8009fac: ea40 3005 orr.w r0, r0, r5, lsl #12
  21737. TIMx->CCMR1 = tmpccmr1 ;
  21738. 8009fb0: 61a0 str r0, [r4, #24]
  21739. HAL_StatusTypeDef status = HAL_OK;
  21740. 8009fb2: 2000 movs r0, #0
  21741. TIMx->CCER = tmpccer;
  21742. 8009fb4: 6221 str r1, [r4, #32]
  21743. tmpsmcr = TIMx->SMCR;
  21744. 8009fb6: 68a1 ldr r1, [r4, #8]
  21745. tmpsmcr &= ~TIM_SMCR_TS;
  21746. 8009fb8: 400b ands r3, r1
  21747. /* Set the Input Trigger source and the slave mode*/
  21748. tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
  21749. 8009fba: f043 0367 orr.w r3, r3, #103 @ 0x67
  21750. /* Write to TIMx SMCR */
  21751. TIMx->SMCR = tmpsmcr;
  21752. 8009fbe: 60a3 str r3, [r4, #8]
  21753. htim->State = HAL_TIM_STATE_READY;
  21754. 8009fc0: 2101 movs r1, #1
  21755. __HAL_UNLOCK(htim);
  21756. 8009fc2: 2300 movs r3, #0
  21757. htim->State = HAL_TIM_STATE_READY;
  21758. 8009fc4: f882 103d strb.w r1, [r2, #61] @ 0x3d
  21759. __HAL_UNLOCK(htim);
  21760. 8009fc8: f882 303c strb.w r3, [r2, #60] @ 0x3c
  21761. }
  21762. 8009fcc: bc30 pop {r4, r5}
  21763. 8009fce: 4770 bx lr
  21764. switch (sClockSourceConfig->ClockSource)
  21765. 8009fd0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
  21766. 8009fd4: d05d beq.n 800a092 <HAL_TIM_ConfigClockSource+0x13a>
  21767. 8009fd6: d931 bls.n 800a03c <HAL_TIM_ConfigClockSource+0xe4>
  21768. 8009fd8: 4940 ldr r1, [pc, #256] @ (800a0dc <HAL_TIM_ConfigClockSource+0x184>)
  21769. 8009fda: 428b cmp r3, r1
  21770. 8009fdc: d006 beq.n 8009fec <HAL_TIM_ConfigClockSource+0x94>
  21771. 8009fde: d927 bls.n 800a030 <HAL_TIM_ConfigClockSource+0xd8>
  21772. 8009fe0: 493f ldr r1, [pc, #252] @ (800a0e0 <HAL_TIM_ConfigClockSource+0x188>)
  21773. 8009fe2: 428b cmp r3, r1
  21774. 8009fe4: d002 beq.n 8009fec <HAL_TIM_ConfigClockSource+0x94>
  21775. 8009fe6: 3110 adds r1, #16
  21776. 8009fe8: 428b cmp r3, r1
  21777. 8009fea: d1e9 bne.n 8009fc0 <HAL_TIM_ConfigClockSource+0x68>
  21778. tmpsmcr = TIMx->SMCR;
  21779. 8009fec: 68a0 ldr r0, [r4, #8]
  21780. tmpsmcr &= ~TIM_SMCR_TS;
  21781. 8009fee: 493a ldr r1, [pc, #232] @ (800a0d8 <HAL_TIM_ConfigClockSource+0x180>)
  21782. 8009ff0: 4001 ands r1, r0
  21783. tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
  21784. 8009ff2: 4319 orrs r1, r3
  21785. 8009ff4: f041 0107 orr.w r1, r1, #7
  21786. TIMx->SMCR = tmpsmcr;
  21787. 8009ff8: 60a1 str r1, [r4, #8]
  21788. }
  21789. 8009ffa: e022 b.n 800a042 <HAL_TIM_ConfigClockSource+0xea>
  21790. switch (sClockSourceConfig->ClockSource)
  21791. 8009ffc: 2b40 cmp r3, #64 @ 0x40
  21792. 8009ffe: d122 bne.n 800a046 <HAL_TIM_ConfigClockSource+0xee>
  21793. tmpccer = TIMx->CCER;
  21794. 800a000: 6a23 ldr r3, [r4, #32]
  21795. sClockSourceConfig->ClockPolarity,
  21796. 800a002: 6848 ldr r0, [r1, #4]
  21797. sClockSourceConfig->ClockFilter);
  21798. 800a004: 68cd ldr r5, [r1, #12]
  21799. tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  21800. 800a006: f023 030a bic.w r3, r3, #10
  21801. TIMx->CCER &= ~TIM_CCER_CC1E;
  21802. 800a00a: 6a21 ldr r1, [r4, #32]
  21803. tmpccer |= TIM_ICPolarity;
  21804. 800a00c: 4318 orrs r0, r3
  21805. tmpsmcr &= ~TIM_SMCR_TS;
  21806. 800a00e: 4b32 ldr r3, [pc, #200] @ (800a0d8 <HAL_TIM_ConfigClockSource+0x180>)
  21807. TIMx->CCER &= ~TIM_CCER_CC1E;
  21808. 800a010: f021 0101 bic.w r1, r1, #1
  21809. 800a014: 6221 str r1, [r4, #32]
  21810. tmpccmr1 = TIMx->CCMR1;
  21811. 800a016: 69a1 ldr r1, [r4, #24]
  21812. tmpccmr1 &= ~TIM_CCMR1_IC1F;
  21813. 800a018: f021 01f0 bic.w r1, r1, #240 @ 0xf0
  21814. tmpccmr1 |= (TIM_ICFilter << 4U);
  21815. 800a01c: ea41 1105 orr.w r1, r1, r5, lsl #4
  21816. TIMx->CCMR1 = tmpccmr1;
  21817. 800a020: 61a1 str r1, [r4, #24]
  21818. TIMx->CCER = tmpccer;
  21819. 800a022: 6220 str r0, [r4, #32]
  21820. tmpsmcr = TIMx->SMCR;
  21821. 800a024: 68a1 ldr r1, [r4, #8]
  21822. tmpsmcr &= ~TIM_SMCR_TS;
  21823. 800a026: 400b ands r3, r1
  21824. tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
  21825. 800a028: f043 0347 orr.w r3, r3, #71 @ 0x47
  21826. TIMx->SMCR = tmpsmcr;
  21827. 800a02c: 60a3 str r3, [r4, #8]
  21828. }
  21829. 800a02e: e008 b.n 800a042 <HAL_TIM_ConfigClockSource+0xea>
  21830. switch (sClockSourceConfig->ClockSource)
  21831. 800a030: f023 0110 bic.w r1, r3, #16
  21832. 800a034: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
  21833. 800a038: d1c2 bne.n 8009fc0 <HAL_TIM_ConfigClockSource+0x68>
  21834. 800a03a: e7d7 b.n 8009fec <HAL_TIM_ConfigClockSource+0x94>
  21835. 800a03c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
  21836. 800a040: d1be bne.n 8009fc0 <HAL_TIM_ConfigClockSource+0x68>
  21837. HAL_StatusTypeDef status = HAL_OK;
  21838. 800a042: 2000 movs r0, #0
  21839. 800a044: e7bc b.n 8009fc0 <HAL_TIM_ConfigClockSource+0x68>
  21840. switch (sClockSourceConfig->ClockSource)
  21841. 800a046: d8bb bhi.n 8009fc0 <HAL_TIM_ConfigClockSource+0x68>
  21842. 800a048: 2b20 cmp r3, #32
  21843. 800a04a: d0cf beq.n 8009fec <HAL_TIM_ConfigClockSource+0x94>
  21844. 800a04c: d903 bls.n 800a056 <HAL_TIM_ConfigClockSource+0xfe>
  21845. 800a04e: 2b30 cmp r3, #48 @ 0x30
  21846. 800a050: d0cc beq.n 8009fec <HAL_TIM_ConfigClockSource+0x94>
  21847. status = HAL_ERROR;
  21848. 800a052: 2001 movs r0, #1
  21849. 800a054: e7b4 b.n 8009fc0 <HAL_TIM_ConfigClockSource+0x68>
  21850. switch (sClockSourceConfig->ClockSource)
  21851. 800a056: f033 0110 bics.w r1, r3, #16
  21852. 800a05a: d1b1 bne.n 8009fc0 <HAL_TIM_ConfigClockSource+0x68>
  21853. 800a05c: e7c6 b.n 8009fec <HAL_TIM_ConfigClockSource+0x94>
  21854. __HAL_LOCK(htim);
  21855. 800a05e: 2002 movs r0, #2
  21856. }
  21857. 800a060: 4770 bx lr
  21858. tmpccer = TIMx->CCER;
  21859. 800a062: 6a23 ldr r3, [r4, #32]
  21860. sClockSourceConfig->ClockPolarity,
  21861. 800a064: 6848 ldr r0, [r1, #4]
  21862. sClockSourceConfig->ClockFilter);
  21863. 800a066: 68cd ldr r5, [r1, #12]
  21864. tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  21865. 800a068: f023 030a bic.w r3, r3, #10
  21866. TIMx->CCER &= ~TIM_CCER_CC1E;
  21867. 800a06c: 6a21 ldr r1, [r4, #32]
  21868. tmpccer |= TIM_ICPolarity;
  21869. 800a06e: 4318 orrs r0, r3
  21870. tmpsmcr &= ~TIM_SMCR_TS;
  21871. 800a070: 4b19 ldr r3, [pc, #100] @ (800a0d8 <HAL_TIM_ConfigClockSource+0x180>)
  21872. TIMx->CCER &= ~TIM_CCER_CC1E;
  21873. 800a072: f021 0101 bic.w r1, r1, #1
  21874. 800a076: 6221 str r1, [r4, #32]
  21875. tmpccmr1 = TIMx->CCMR1;
  21876. 800a078: 69a1 ldr r1, [r4, #24]
  21877. tmpccmr1 &= ~TIM_CCMR1_IC1F;
  21878. 800a07a: f021 01f0 bic.w r1, r1, #240 @ 0xf0
  21879. tmpccmr1 |= (TIM_ICFilter << 4U);
  21880. 800a07e: ea41 1105 orr.w r1, r1, r5, lsl #4
  21881. TIMx->CCMR1 = tmpccmr1;
  21882. 800a082: 61a1 str r1, [r4, #24]
  21883. TIMx->CCER = tmpccer;
  21884. 800a084: 6220 str r0, [r4, #32]
  21885. tmpsmcr = TIMx->SMCR;
  21886. 800a086: 68a1 ldr r1, [r4, #8]
  21887. tmpsmcr &= ~TIM_SMCR_TS;
  21888. 800a088: 400b ands r3, r1
  21889. tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
  21890. 800a08a: f043 0357 orr.w r3, r3, #87 @ 0x57
  21891. TIMx->SMCR = tmpsmcr;
  21892. 800a08e: 60a3 str r3, [r4, #8]
  21893. }
  21894. 800a090: e7d7 b.n 800a042 <HAL_TIM_ConfigClockSource+0xea>
  21895. /* Reset the ETR Bits */
  21896. tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  21897. /* Set the Prescaler, the Filter value and the Polarity */
  21898. tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
  21899. 800a092: e9d1 5301 ldrd r5, r3, [r1, #4]
  21900. tmpsmcr = TIMx->SMCR;
  21901. 800a096: 68a0 ldr r0, [r4, #8]
  21902. tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
  21903. 800a098: 432b orrs r3, r5
  21904. 800a09a: 68cd ldr r5, [r1, #12]
  21905. tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  21906. 800a09c: f420 417f bic.w r1, r0, #65280 @ 0xff00
  21907. tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
  21908. 800a0a0: ea43 2305 orr.w r3, r3, r5, lsl #8
  21909. 800a0a4: 430b orrs r3, r1
  21910. /* Write to TIMx SMCR */
  21911. TIMx->SMCR = tmpsmcr;
  21912. 800a0a6: 60a3 str r3, [r4, #8]
  21913. htim->Instance->SMCR |= TIM_SMCR_ECE;
  21914. 800a0a8: 68a3 ldr r3, [r4, #8]
  21915. 800a0aa: f443 4380 orr.w r3, r3, #16384 @ 0x4000
  21916. 800a0ae: 60a3 str r3, [r4, #8]
  21917. break;
  21918. 800a0b0: e7c7 b.n 800a042 <HAL_TIM_ConfigClockSource+0xea>
  21919. tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
  21920. 800a0b2: e9d1 5301 ldrd r5, r3, [r1, #4]
  21921. tmpsmcr = TIMx->SMCR;
  21922. 800a0b6: 68a0 ldr r0, [r4, #8]
  21923. tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
  21924. 800a0b8: 432b orrs r3, r5
  21925. 800a0ba: 68cd ldr r5, [r1, #12]
  21926. tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  21927. 800a0bc: f420 417f bic.w r1, r0, #65280 @ 0xff00
  21928. tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
  21929. 800a0c0: ea43 2305 orr.w r3, r3, r5, lsl #8
  21930. 800a0c4: 430b orrs r3, r1
  21931. TIMx->SMCR = tmpsmcr;
  21932. 800a0c6: 60a3 str r3, [r4, #8]
  21933. tmpsmcr = htim->Instance->SMCR;
  21934. 800a0c8: 68a3 ldr r3, [r4, #8]
  21935. tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
  21936. 800a0ca: f043 0377 orr.w r3, r3, #119 @ 0x77
  21937. htim->Instance->SMCR = tmpsmcr;
  21938. 800a0ce: 60a3 str r3, [r4, #8]
  21939. break;
  21940. 800a0d0: e7b7 b.n 800a042 <HAL_TIM_ConfigClockSource+0xea>
  21941. 800a0d2: bf00 nop
  21942. 800a0d4: ffce0088 .word 0xffce0088
  21943. 800a0d8: ffcfff8f .word 0xffcfff8f
  21944. 800a0dc: 00100020 .word 0x00100020
  21945. 800a0e0: 00100030 .word 0x00100030
  21946. 0800a0e4 <HAL_TIM_OC_DelayElapsedCallback>:
  21947. __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
  21948. 800a0e4: 4770 bx lr
  21949. 800a0e6: bf00 nop
  21950. 0800a0e8 <HAL_TIM_IC_CaptureCallback>:
  21951. __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
  21952. 800a0e8: 4770 bx lr
  21953. 800a0ea: bf00 nop
  21954. 0800a0ec <HAL_TIM_PWM_PulseFinishedCallback>:
  21955. __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
  21956. 800a0ec: 4770 bx lr
  21957. 800a0ee: bf00 nop
  21958. 0800a0f0 <HAL_TIM_TriggerCallback>:
  21959. __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
  21960. 800a0f0: 4770 bx lr
  21961. 800a0f2: bf00 nop
  21962. 0800a0f4 <HAL_TIM_IRQHandler>:
  21963. {
  21964. 800a0f4: b5f8 push {r3, r4, r5, r6, r7, lr}
  21965. uint32_t itsource = htim->Instance->DIER;
  21966. 800a0f6: 6803 ldr r3, [r0, #0]
  21967. {
  21968. 800a0f8: 4605 mov r5, r0
  21969. uint32_t itsource = htim->Instance->DIER;
  21970. 800a0fa: 68de ldr r6, [r3, #12]
  21971. uint32_t itflag = htim->Instance->SR;
  21972. 800a0fc: 691c ldr r4, [r3, #16]
  21973. if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
  21974. 800a0fe: 07a1 lsls r1, r4, #30
  21975. 800a100: d501 bpl.n 800a106 <HAL_TIM_IRQHandler+0x12>
  21976. if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
  21977. 800a102: 07b2 lsls r2, r6, #30
  21978. 800a104: d457 bmi.n 800a1b6 <HAL_TIM_IRQHandler+0xc2>
  21979. if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
  21980. 800a106: 0767 lsls r7, r4, #29
  21981. 800a108: d501 bpl.n 800a10e <HAL_TIM_IRQHandler+0x1a>
  21982. if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
  21983. 800a10a: 0770 lsls r0, r6, #29
  21984. 800a10c: d440 bmi.n 800a190 <HAL_TIM_IRQHandler+0x9c>
  21985. if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
  21986. 800a10e: 0721 lsls r1, r4, #28
  21987. 800a110: d501 bpl.n 800a116 <HAL_TIM_IRQHandler+0x22>
  21988. if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
  21989. 800a112: 0732 lsls r2, r6, #28
  21990. 800a114: d42a bmi.n 800a16c <HAL_TIM_IRQHandler+0x78>
  21991. if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
  21992. 800a116: 06e7 lsls r7, r4, #27
  21993. 800a118: d501 bpl.n 800a11e <HAL_TIM_IRQHandler+0x2a>
  21994. if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
  21995. 800a11a: 06f0 lsls r0, r6, #27
  21996. 800a11c: d413 bmi.n 800a146 <HAL_TIM_IRQHandler+0x52>
  21997. if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
  21998. 800a11e: 07e1 lsls r1, r4, #31
  21999. 800a120: d501 bpl.n 800a126 <HAL_TIM_IRQHandler+0x32>
  22000. if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
  22001. 800a122: 07f2 lsls r2, r6, #31
  22002. 800a124: d465 bmi.n 800a1f2 <HAL_TIM_IRQHandler+0xfe>
  22003. if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
  22004. 800a126: f414 5f02 tst.w r4, #8320 @ 0x2080
  22005. if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
  22006. 800a12a: f404 7780 and.w r7, r4, #256 @ 0x100
  22007. if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
  22008. 800a12e: d052 beq.n 800a1d6 <HAL_TIM_IRQHandler+0xe2>
  22009. if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
  22010. 800a130: 0633 lsls r3, r6, #24
  22011. 800a132: d466 bmi.n 800a202 <HAL_TIM_IRQHandler+0x10e>
  22012. if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
  22013. 800a134: 0660 lsls r0, r4, #25
  22014. 800a136: d501 bpl.n 800a13c <HAL_TIM_IRQHandler+0x48>
  22015. if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
  22016. 800a138: 0671 lsls r1, r6, #25
  22017. 800a13a: d473 bmi.n 800a224 <HAL_TIM_IRQHandler+0x130>
  22018. if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
  22019. 800a13c: 06a2 lsls r2, r4, #26
  22020. 800a13e: d501 bpl.n 800a144 <HAL_TIM_IRQHandler+0x50>
  22021. if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
  22022. 800a140: 06b3 lsls r3, r6, #26
  22023. 800a142: d44d bmi.n 800a1e0 <HAL_TIM_IRQHandler+0xec>
  22024. }
  22025. 800a144: bdf8 pop {r3, r4, r5, r6, r7, pc}
  22026. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
  22027. 800a146: 682b ldr r3, [r5, #0]
  22028. 800a148: f06f 0210 mvn.w r2, #16
  22029. HAL_TIM_IC_CaptureCallback(htim);
  22030. 800a14c: 4628 mov r0, r5
  22031. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
  22032. 800a14e: 611a str r2, [r3, #16]
  22033. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  22034. 800a150: 2208 movs r2, #8
  22035. 800a152: 772a strb r2, [r5, #28]
  22036. if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
  22037. 800a154: 69db ldr r3, [r3, #28]
  22038. 800a156: f413 7f40 tst.w r3, #768 @ 0x300
  22039. 800a15a: d174 bne.n 800a246 <HAL_TIM_IRQHandler+0x152>
  22040. HAL_TIM_OC_DelayElapsedCallback(htim);
  22041. 800a15c: f7ff ffc2 bl 800a0e4 <HAL_TIM_OC_DelayElapsedCallback>
  22042. HAL_TIM_PWM_PulseFinishedCallback(htim);
  22043. 800a160: 4628 mov r0, r5
  22044. 800a162: f7ff ffc3 bl 800a0ec <HAL_TIM_PWM_PulseFinishedCallback>
  22045. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  22046. 800a166: 2300 movs r3, #0
  22047. 800a168: 772b strb r3, [r5, #28]
  22048. 800a16a: e7d8 b.n 800a11e <HAL_TIM_IRQHandler+0x2a>
  22049. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
  22050. 800a16c: 682b ldr r3, [r5, #0]
  22051. 800a16e: f06f 0208 mvn.w r2, #8
  22052. HAL_TIM_IC_CaptureCallback(htim);
  22053. 800a172: 4628 mov r0, r5
  22054. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
  22055. 800a174: 611a str r2, [r3, #16]
  22056. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  22057. 800a176: 2204 movs r2, #4
  22058. 800a178: 772a strb r2, [r5, #28]
  22059. if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
  22060. 800a17a: 69db ldr r3, [r3, #28]
  22061. 800a17c: 079b lsls r3, r3, #30
  22062. 800a17e: d15f bne.n 800a240 <HAL_TIM_IRQHandler+0x14c>
  22063. HAL_TIM_OC_DelayElapsedCallback(htim);
  22064. 800a180: f7ff ffb0 bl 800a0e4 <HAL_TIM_OC_DelayElapsedCallback>
  22065. HAL_TIM_PWM_PulseFinishedCallback(htim);
  22066. 800a184: 4628 mov r0, r5
  22067. 800a186: f7ff ffb1 bl 800a0ec <HAL_TIM_PWM_PulseFinishedCallback>
  22068. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  22069. 800a18a: 2300 movs r3, #0
  22070. 800a18c: 772b strb r3, [r5, #28]
  22071. 800a18e: e7c2 b.n 800a116 <HAL_TIM_IRQHandler+0x22>
  22072. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
  22073. 800a190: 682b ldr r3, [r5, #0]
  22074. 800a192: f06f 0204 mvn.w r2, #4
  22075. HAL_TIM_IC_CaptureCallback(htim);
  22076. 800a196: 4628 mov r0, r5
  22077. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
  22078. 800a198: 611a str r2, [r3, #16]
  22079. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  22080. 800a19a: 2202 movs r2, #2
  22081. 800a19c: 772a strb r2, [r5, #28]
  22082. if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
  22083. 800a19e: 699b ldr r3, [r3, #24]
  22084. 800a1a0: f413 7f40 tst.w r3, #768 @ 0x300
  22085. 800a1a4: d149 bne.n 800a23a <HAL_TIM_IRQHandler+0x146>
  22086. HAL_TIM_OC_DelayElapsedCallback(htim);
  22087. 800a1a6: f7ff ff9d bl 800a0e4 <HAL_TIM_OC_DelayElapsedCallback>
  22088. HAL_TIM_PWM_PulseFinishedCallback(htim);
  22089. 800a1aa: 4628 mov r0, r5
  22090. 800a1ac: f7ff ff9e bl 800a0ec <HAL_TIM_PWM_PulseFinishedCallback>
  22091. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  22092. 800a1b0: 2300 movs r3, #0
  22093. 800a1b2: 772b strb r3, [r5, #28]
  22094. 800a1b4: e7ab b.n 800a10e <HAL_TIM_IRQHandler+0x1a>
  22095. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
  22096. 800a1b6: f06f 0202 mvn.w r2, #2
  22097. 800a1ba: 611a str r2, [r3, #16]
  22098. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  22099. 800a1bc: 2201 movs r2, #1
  22100. 800a1be: 7702 strb r2, [r0, #28]
  22101. if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
  22102. 800a1c0: 699b ldr r3, [r3, #24]
  22103. 800a1c2: 079b lsls r3, r3, #30
  22104. 800a1c4: d136 bne.n 800a234 <HAL_TIM_IRQHandler+0x140>
  22105. HAL_TIM_OC_DelayElapsedCallback(htim);
  22106. 800a1c6: f7ff ff8d bl 800a0e4 <HAL_TIM_OC_DelayElapsedCallback>
  22107. HAL_TIM_PWM_PulseFinishedCallback(htim);
  22108. 800a1ca: 4628 mov r0, r5
  22109. 800a1cc: f7ff ff8e bl 800a0ec <HAL_TIM_PWM_PulseFinishedCallback>
  22110. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  22111. 800a1d0: 2300 movs r3, #0
  22112. 800a1d2: 772b strb r3, [r5, #28]
  22113. 800a1d4: e797 b.n 800a106 <HAL_TIM_IRQHandler+0x12>
  22114. if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
  22115. 800a1d6: 2f00 cmp r7, #0
  22116. 800a1d8: d0ac beq.n 800a134 <HAL_TIM_IRQHandler+0x40>
  22117. if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
  22118. 800a1da: 0637 lsls r7, r6, #24
  22119. 800a1dc: d41a bmi.n 800a214 <HAL_TIM_IRQHandler+0x120>
  22120. 800a1de: e7a9 b.n 800a134 <HAL_TIM_IRQHandler+0x40>
  22121. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
  22122. 800a1e0: 682b ldr r3, [r5, #0]
  22123. 800a1e2: f06f 0220 mvn.w r2, #32
  22124. HAL_TIMEx_CommutCallback(htim);
  22125. 800a1e6: 4628 mov r0, r5
  22126. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
  22127. 800a1e8: 611a str r2, [r3, #16]
  22128. }
  22129. 800a1ea: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr}
  22130. HAL_TIMEx_CommutCallback(htim);
  22131. 800a1ee: f000 ba4f b.w 800a690 <HAL_TIMEx_CommutCallback>
  22132. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
  22133. 800a1f2: 682b ldr r3, [r5, #0]
  22134. 800a1f4: f06f 0201 mvn.w r2, #1
  22135. HAL_TIM_PeriodElapsedCallback(htim);
  22136. 800a1f8: 4628 mov r0, r5
  22137. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
  22138. 800a1fa: 611a str r2, [r3, #16]
  22139. HAL_TIM_PeriodElapsedCallback(htim);
  22140. 800a1fc: f7f6 fad6 bl 80007ac <HAL_TIM_PeriodElapsedCallback>
  22141. 800a200: e791 b.n 800a126 <HAL_TIM_IRQHandler+0x32>
  22142. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
  22143. 800a202: 682b ldr r3, [r5, #0]
  22144. 800a204: f46f 5202 mvn.w r2, #8320 @ 0x2080
  22145. HAL_TIMEx_BreakCallback(htim);
  22146. 800a208: 4628 mov r0, r5
  22147. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
  22148. 800a20a: 611a str r2, [r3, #16]
  22149. HAL_TIMEx_BreakCallback(htim);
  22150. 800a20c: f000 fa42 bl 800a694 <HAL_TIMEx_BreakCallback>
  22151. if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
  22152. 800a210: 2f00 cmp r7, #0
  22153. 800a212: d08f beq.n 800a134 <HAL_TIM_IRQHandler+0x40>
  22154. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
  22155. 800a214: 682b ldr r3, [r5, #0]
  22156. 800a216: f46f 7280 mvn.w r2, #256 @ 0x100
  22157. HAL_TIMEx_Break2Callback(htim);
  22158. 800a21a: 4628 mov r0, r5
  22159. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
  22160. 800a21c: 611a str r2, [r3, #16]
  22161. HAL_TIMEx_Break2Callback(htim);
  22162. 800a21e: f000 fa3b bl 800a698 <HAL_TIMEx_Break2Callback>
  22163. 800a222: e787 b.n 800a134 <HAL_TIM_IRQHandler+0x40>
  22164. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
  22165. 800a224: 682b ldr r3, [r5, #0]
  22166. 800a226: f06f 0240 mvn.w r2, #64 @ 0x40
  22167. HAL_TIM_TriggerCallback(htim);
  22168. 800a22a: 4628 mov r0, r5
  22169. __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
  22170. 800a22c: 611a str r2, [r3, #16]
  22171. HAL_TIM_TriggerCallback(htim);
  22172. 800a22e: f7ff ff5f bl 800a0f0 <HAL_TIM_TriggerCallback>
  22173. 800a232: e783 b.n 800a13c <HAL_TIM_IRQHandler+0x48>
  22174. HAL_TIM_IC_CaptureCallback(htim);
  22175. 800a234: f7ff ff58 bl 800a0e8 <HAL_TIM_IC_CaptureCallback>
  22176. 800a238: e7ca b.n 800a1d0 <HAL_TIM_IRQHandler+0xdc>
  22177. HAL_TIM_IC_CaptureCallback(htim);
  22178. 800a23a: f7ff ff55 bl 800a0e8 <HAL_TIM_IC_CaptureCallback>
  22179. 800a23e: e7b7 b.n 800a1b0 <HAL_TIM_IRQHandler+0xbc>
  22180. HAL_TIM_IC_CaptureCallback(htim);
  22181. 800a240: f7ff ff52 bl 800a0e8 <HAL_TIM_IC_CaptureCallback>
  22182. 800a244: e7a1 b.n 800a18a <HAL_TIM_IRQHandler+0x96>
  22183. HAL_TIM_IC_CaptureCallback(htim);
  22184. 800a246: f7ff ff4f bl 800a0e8 <HAL_TIM_IC_CaptureCallback>
  22185. 800a24a: e78c b.n 800a166 <HAL_TIM_IRQHandler+0x72>
  22186. 0800a24c <HAL_TIM_GetChannelState>:
  22187. channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  22188. 800a24c: 2910 cmp r1, #16
  22189. 800a24e: d80a bhi.n 800a266 <HAL_TIM_GetChannelState+0x1a>
  22190. 800a250: e8df f001 tbb [pc, r1]
  22191. 800a254: 0909090d .word 0x0909090d
  22192. 800a258: 09090911 .word 0x09090911
  22193. 800a25c: 09090915 .word 0x09090915
  22194. 800a260: 09090919 .word 0x09090919
  22195. 800a264: 1d .byte 0x1d
  22196. 800a265: 00 .byte 0x00
  22197. 800a266: f890 0043 ldrb.w r0, [r0, #67] @ 0x43
  22198. 800a26a: b2c0 uxtb r0, r0
  22199. }
  22200. 800a26c: 4770 bx lr
  22201. channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  22202. 800a26e: f890 003e ldrb.w r0, [r0, #62] @ 0x3e
  22203. 800a272: b2c0 uxtb r0, r0
  22204. 800a274: 4770 bx lr
  22205. 800a276: f890 003f ldrb.w r0, [r0, #63] @ 0x3f
  22206. 800a27a: b2c0 uxtb r0, r0
  22207. 800a27c: 4770 bx lr
  22208. 800a27e: f890 0040 ldrb.w r0, [r0, #64] @ 0x40
  22209. 800a282: b2c0 uxtb r0, r0
  22210. 800a284: 4770 bx lr
  22211. 800a286: f890 0041 ldrb.w r0, [r0, #65] @ 0x41
  22212. 800a28a: b2c0 uxtb r0, r0
  22213. 800a28c: 4770 bx lr
  22214. 800a28e: f890 0042 ldrb.w r0, [r0, #66] @ 0x42
  22215. 800a292: b2c0 uxtb r0, r0
  22216. 800a294: 4770 bx lr
  22217. 800a296: bf00 nop
  22218. 0800a298 <TIM_OC2_SetConfig>:
  22219. tmpccer = TIMx->CCER;
  22220. 800a298: 6a03 ldr r3, [r0, #32]
  22221. TIMx->CCER &= ~TIM_CCER_CC2E;
  22222. 800a29a: 6a02 ldr r2, [r0, #32]
  22223. tmpccer &= ~TIM_CCER_CC2P;
  22224. 800a29c: f023 0320 bic.w r3, r3, #32
  22225. TIMx->CCER &= ~TIM_CCER_CC2E;
  22226. 800a2a0: f022 0210 bic.w r2, r2, #16
  22227. {
  22228. 800a2a4: b470 push {r4, r5, r6}
  22229. TIMx->CCER &= ~TIM_CCER_CC2E;
  22230. 800a2a6: 6202 str r2, [r0, #32]
  22231. tmpccmrx &= ~TIM_CCMR1_CC2S;
  22232. 800a2a8: 4a19 ldr r2, [pc, #100] @ (800a310 <TIM_OC2_SetConfig+0x78>)
  22233. tmpcr2 = TIMx->CR2;
  22234. 800a2aa: 6844 ldr r4, [r0, #4]
  22235. tmpccmrx = TIMx->CCMR1;
  22236. 800a2ac: 6985 ldr r5, [r0, #24]
  22237. tmpccmrx &= ~TIM_CCMR1_CC2S;
  22238. 800a2ae: 402a ands r2, r5
  22239. tmpccmrx |= (OC_Config->OCMode << 8U);
  22240. 800a2b0: 680d ldr r5, [r1, #0]
  22241. 800a2b2: ea42 2205 orr.w r2, r2, r5, lsl #8
  22242. tmpccer |= (OC_Config->OCPolarity << 4U);
  22243. 800a2b6: 688d ldr r5, [r1, #8]
  22244. 800a2b8: ea43 1305 orr.w r3, r3, r5, lsl #4
  22245. if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
  22246. 800a2bc: 4d15 ldr r5, [pc, #84] @ (800a314 <TIM_OC2_SetConfig+0x7c>)
  22247. 800a2be: 42a8 cmp r0, r5
  22248. 800a2c0: d00f beq.n 800a2e2 <TIM_OC2_SetConfig+0x4a>
  22249. 800a2c2: f505 6580 add.w r5, r5, #1024 @ 0x400
  22250. 800a2c6: 42a8 cmp r0, r5
  22251. 800a2c8: d00b beq.n 800a2e2 <TIM_OC2_SetConfig+0x4a>
  22252. if (IS_TIM_BREAK_INSTANCE(TIMx))
  22253. 800a2ca: 4e13 ldr r6, [pc, #76] @ (800a318 <TIM_OC2_SetConfig+0x80>)
  22254. 800a2cc: f505 4580 add.w r5, r5, #16384 @ 0x4000
  22255. 800a2d0: 42a8 cmp r0, r5
  22256. 800a2d2: bf18 it ne
  22257. 800a2d4: 42b0 cmpne r0, r6
  22258. 800a2d6: d00b beq.n 800a2f0 <TIM_OC2_SetConfig+0x58>
  22259. 800a2d8: f505 6580 add.w r5, r5, #1024 @ 0x400
  22260. 800a2dc: 42a8 cmp r0, r5
  22261. 800a2de: d10f bne.n 800a300 <TIM_OC2_SetConfig+0x68>
  22262. 800a2e0: e006 b.n 800a2f0 <TIM_OC2_SetConfig+0x58>
  22263. tmpccer &= ~TIM_CCER_CC2NP;
  22264. 800a2e2: f023 0380 bic.w r3, r3, #128 @ 0x80
  22265. tmpccer |= (OC_Config->OCNPolarity << 4U);
  22266. 800a2e6: 68cd ldr r5, [r1, #12]
  22267. 800a2e8: ea43 1305 orr.w r3, r3, r5, lsl #4
  22268. tmpccer &= ~TIM_CCER_CC2NE;
  22269. 800a2ec: f023 0340 bic.w r3, r3, #64 @ 0x40
  22270. tmpcr2 &= ~TIM_CR2_OIS2N;
  22271. 800a2f0: f424 6440 bic.w r4, r4, #3072 @ 0xc00
  22272. tmpcr2 |= (OC_Config->OCNIdleState << 2U);
  22273. 800a2f4: e9d1 6505 ldrd r6, r5, [r1, #20]
  22274. 800a2f8: ea46 0c05 orr.w ip, r6, r5
  22275. 800a2fc: ea44 048c orr.w r4, r4, ip, lsl #2
  22276. TIMx->CCR2 = OC_Config->Pulse;
  22277. 800a300: 6849 ldr r1, [r1, #4]
  22278. TIMx->CR2 = tmpcr2;
  22279. 800a302: 6044 str r4, [r0, #4]
  22280. TIMx->CCMR1 = tmpccmrx;
  22281. 800a304: 6182 str r2, [r0, #24]
  22282. TIMx->CCR2 = OC_Config->Pulse;
  22283. 800a306: 6381 str r1, [r0, #56] @ 0x38
  22284. TIMx->CCER = tmpccer;
  22285. 800a308: 6203 str r3, [r0, #32]
  22286. }
  22287. 800a30a: bc70 pop {r4, r5, r6}
  22288. 800a30c: 4770 bx lr
  22289. 800a30e: bf00 nop
  22290. 800a310: feff8cff .word 0xfeff8cff
  22291. 800a314: 40010000 .word 0x40010000
  22292. 800a318: 40014000 .word 0x40014000
  22293. 0800a31c <HAL_TIM_PWM_ConfigChannel>:
  22294. {
  22295. 800a31c: b5f8 push {r3, r4, r5, r6, r7, lr}
  22296. __HAL_LOCK(htim);
  22297. 800a31e: f890 303c ldrb.w r3, [r0, #60] @ 0x3c
  22298. 800a322: 2b01 cmp r3, #1
  22299. 800a324: f000 8107 beq.w 800a536 <HAL_TIM_PWM_ConfigChannel+0x21a>
  22300. 800a328: 2301 movs r3, #1
  22301. 800a32a: 4604 mov r4, r0
  22302. 800a32c: 460d mov r5, r1
  22303. 800a32e: f880 303c strb.w r3, [r0, #60] @ 0x3c
  22304. switch (Channel)
  22305. 800a332: 2a14 cmp r2, #20
  22306. 800a334: d816 bhi.n 800a364 <HAL_TIM_PWM_ConfigChannel+0x48>
  22307. 800a336: e8df f012 tbh [pc, r2, lsl #1]
  22308. 800a33a: 0056 .short 0x0056
  22309. 800a33c: 00150015 .word 0x00150015
  22310. 800a340: 00670015 .word 0x00670015
  22311. 800a344: 00150015 .word 0x00150015
  22312. 800a348: 00780015 .word 0x00780015
  22313. 800a34c: 00150015 .word 0x00150015
  22314. 800a350: 00880015 .word 0x00880015
  22315. 800a354: 00150015 .word 0x00150015
  22316. 800a358: 00c40015 .word 0x00c40015
  22317. 800a35c: 00150015 .word 0x00150015
  22318. 800a360: 001a0015 .word 0x001a0015
  22319. 800a364: 2001 movs r0, #1
  22320. __HAL_UNLOCK(htim);
  22321. 800a366: 2300 movs r3, #0
  22322. 800a368: f884 303c strb.w r3, [r4, #60] @ 0x3c
  22323. }
  22324. 800a36c: bdf8 pop {r3, r4, r5, r6, r7, pc}
  22325. TIM_OC6_SetConfig(htim->Instance, sConfig);
  22326. 800a36e: 6803 ldr r3, [r0, #0]
  22327. tmpccer = TIMx->CCER;
  22328. 800a370: 6a1a ldr r2, [r3, #32]
  22329. TIMx->CCER &= ~TIM_CCER_CC6E;
  22330. 800a372: 6a19 ldr r1, [r3, #32]
  22331. tmpccer &= (uint32_t)~TIM_CCER_CC6P;
  22332. 800a374: f422 1200 bic.w r2, r2, #2097152 @ 0x200000
  22333. TIMx->CCER &= ~TIM_CCER_CC6E;
  22334. 800a378: f421 1180 bic.w r1, r1, #1048576 @ 0x100000
  22335. 800a37c: 6219 str r1, [r3, #32]
  22336. tmpccmrx &= ~(TIM_CCMR3_OC6M);
  22337. 800a37e: 496f ldr r1, [pc, #444] @ (800a53c <HAL_TIM_PWM_ConfigChannel+0x220>)
  22338. tmpcr2 = TIMx->CR2;
  22339. 800a380: 6858 ldr r0, [r3, #4]
  22340. tmpccmrx = TIMx->CCMR3;
  22341. 800a382: 6d5e ldr r6, [r3, #84] @ 0x54
  22342. tmpccmrx &= ~(TIM_CCMR3_OC6M);
  22343. 800a384: 4031 ands r1, r6
  22344. tmpccmrx |= (OC_Config->OCMode << 8U);
  22345. 800a386: 682e ldr r6, [r5, #0]
  22346. 800a388: ea41 2106 orr.w r1, r1, r6, lsl #8
  22347. tmpccer |= (OC_Config->OCPolarity << 20U);
  22348. 800a38c: 68ae ldr r6, [r5, #8]
  22349. 800a38e: ea42 5206 orr.w r2, r2, r6, lsl #20
  22350. if (IS_TIM_BREAK_INSTANCE(TIMx))
  22351. 800a392: 4e6b ldr r6, [pc, #428] @ (800a540 <HAL_TIM_PWM_ConfigChannel+0x224>)
  22352. 800a394: 42b3 cmp r3, r6
  22353. 800a396: d00e beq.n 800a3b6 <HAL_TIM_PWM_ConfigChannel+0x9a>
  22354. 800a398: f506 6680 add.w r6, r6, #1024 @ 0x400
  22355. 800a39c: 42b3 cmp r3, r6
  22356. 800a39e: d00a beq.n 800a3b6 <HAL_TIM_PWM_ConfigChannel+0x9a>
  22357. 800a3a0: 4f68 ldr r7, [pc, #416] @ (800a544 <HAL_TIM_PWM_ConfigChannel+0x228>)
  22358. 800a3a2: f506 4680 add.w r6, r6, #16384 @ 0x4000
  22359. 800a3a6: 42b3 cmp r3, r6
  22360. 800a3a8: bf18 it ne
  22361. 800a3aa: 42bb cmpne r3, r7
  22362. 800a3ac: d003 beq.n 800a3b6 <HAL_TIM_PWM_ConfigChannel+0x9a>
  22363. 800a3ae: f506 6680 add.w r6, r6, #1024 @ 0x400
  22364. 800a3b2: 42b3 cmp r3, r6
  22365. 800a3b4: d104 bne.n 800a3c0 <HAL_TIM_PWM_ConfigChannel+0xa4>
  22366. tmpcr2 &= ~TIM_CR2_OIS6;
  22367. 800a3b6: f420 2080 bic.w r0, r0, #262144 @ 0x40000
  22368. tmpcr2 |= (OC_Config->OCIdleState << 10U);
  22369. 800a3ba: 696e ldr r6, [r5, #20]
  22370. 800a3bc: ea40 2086 orr.w r0, r0, r6, lsl #10
  22371. TIMx->CR2 = tmpcr2;
  22372. 800a3c0: 6058 str r0, [r3, #4]
  22373. TIMx->CCR6 = OC_Config->Pulse;
  22374. 800a3c2: 6868 ldr r0, [r5, #4]
  22375. TIMx->CCMR3 = tmpccmrx;
  22376. 800a3c4: 6559 str r1, [r3, #84] @ 0x54
  22377. htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
  22378. 800a3c6: 6929 ldr r1, [r5, #16]
  22379. TIMx->CCR6 = OC_Config->Pulse;
  22380. 800a3c8: 65d8 str r0, [r3, #92] @ 0x5c
  22381. TIMx->CCER = tmpccer;
  22382. 800a3ca: 621a str r2, [r3, #32]
  22383. htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
  22384. 800a3cc: 6d5a ldr r2, [r3, #84] @ 0x54
  22385. 800a3ce: f442 6200 orr.w r2, r2, #2048 @ 0x800
  22386. 800a3d2: 655a str r2, [r3, #84] @ 0x54
  22387. htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
  22388. 800a3d4: 6d5a ldr r2, [r3, #84] @ 0x54
  22389. 800a3d6: f422 6280 bic.w r2, r2, #1024 @ 0x400
  22390. 800a3da: 655a str r2, [r3, #84] @ 0x54
  22391. htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
  22392. 800a3dc: 6d5a ldr r2, [r3, #84] @ 0x54
  22393. 800a3de: ea42 2201 orr.w r2, r2, r1, lsl #8
  22394. 800a3e2: 655a str r2, [r3, #84] @ 0x54
  22395. break;
  22396. 800a3e4: e00e b.n 800a404 <HAL_TIM_PWM_ConfigChannel+0xe8>
  22397. TIM_OC1_SetConfig(htim->Instance, sConfig);
  22398. 800a3e6: 6800 ldr r0, [r0, #0]
  22399. 800a3e8: f7ff fa2e bl 8009848 <TIM_OC1_SetConfig>
  22400. htim->Instance->CCMR1 |= sConfig->OCFastMode;
  22401. 800a3ec: 692a ldr r2, [r5, #16]
  22402. htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
  22403. 800a3ee: 6983 ldr r3, [r0, #24]
  22404. 800a3f0: f043 0308 orr.w r3, r3, #8
  22405. 800a3f4: 6183 str r3, [r0, #24]
  22406. htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
  22407. 800a3f6: 6983 ldr r3, [r0, #24]
  22408. 800a3f8: f023 0304 bic.w r3, r3, #4
  22409. 800a3fc: 6183 str r3, [r0, #24]
  22410. htim->Instance->CCMR1 |= sConfig->OCFastMode;
  22411. 800a3fe: 6983 ldr r3, [r0, #24]
  22412. 800a400: 4313 orrs r3, r2
  22413. 800a402: 6183 str r3, [r0, #24]
  22414. HAL_StatusTypeDef status = HAL_OK;
  22415. 800a404: 2000 movs r0, #0
  22416. 800a406: e7ae b.n 800a366 <HAL_TIM_PWM_ConfigChannel+0x4a>
  22417. TIM_OC2_SetConfig(htim->Instance, sConfig);
  22418. 800a408: 6800 ldr r0, [r0, #0]
  22419. 800a40a: f7ff ff45 bl 800a298 <TIM_OC2_SetConfig>
  22420. htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
  22421. 800a40e: 692a ldr r2, [r5, #16]
  22422. htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
  22423. 800a410: 6983 ldr r3, [r0, #24]
  22424. 800a412: f443 6300 orr.w r3, r3, #2048 @ 0x800
  22425. 800a416: 6183 str r3, [r0, #24]
  22426. htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
  22427. 800a418: 6983 ldr r3, [r0, #24]
  22428. 800a41a: f423 6380 bic.w r3, r3, #1024 @ 0x400
  22429. 800a41e: 6183 str r3, [r0, #24]
  22430. htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
  22431. 800a420: 6983 ldr r3, [r0, #24]
  22432. 800a422: ea43 2302 orr.w r3, r3, r2, lsl #8
  22433. 800a426: 6183 str r3, [r0, #24]
  22434. break;
  22435. 800a428: e7ec b.n 800a404 <HAL_TIM_PWM_ConfigChannel+0xe8>
  22436. TIM_OC3_SetConfig(htim->Instance, sConfig);
  22437. 800a42a: 6800 ldr r0, [r0, #0]
  22438. 800a42c: f7ff fa48 bl 80098c0 <TIM_OC3_SetConfig>
  22439. htim->Instance->CCMR2 |= sConfig->OCFastMode;
  22440. 800a430: 692a ldr r2, [r5, #16]
  22441. htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
  22442. 800a432: 69c3 ldr r3, [r0, #28]
  22443. 800a434: f043 0308 orr.w r3, r3, #8
  22444. 800a438: 61c3 str r3, [r0, #28]
  22445. htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
  22446. 800a43a: 69c3 ldr r3, [r0, #28]
  22447. 800a43c: f023 0304 bic.w r3, r3, #4
  22448. 800a440: 61c3 str r3, [r0, #28]
  22449. htim->Instance->CCMR2 |= sConfig->OCFastMode;
  22450. 800a442: 69c3 ldr r3, [r0, #28]
  22451. 800a444: 4313 orrs r3, r2
  22452. 800a446: 61c3 str r3, [r0, #28]
  22453. break;
  22454. 800a448: e7dc b.n 800a404 <HAL_TIM_PWM_ConfigChannel+0xe8>
  22455. TIM_OC4_SetConfig(htim->Instance, sConfig);
  22456. 800a44a: 6803 ldr r3, [r0, #0]
  22457. tmpccer = TIMx->CCER;
  22458. 800a44c: 6a1a ldr r2, [r3, #32]
  22459. TIMx->CCER &= ~TIM_CCER_CC4E;
  22460. 800a44e: 6a19 ldr r1, [r3, #32]
  22461. tmpccer &= ~TIM_CCER_CC4P;
  22462. 800a450: f422 5200 bic.w r2, r2, #8192 @ 0x2000
  22463. TIMx->CCER &= ~TIM_CCER_CC4E;
  22464. 800a454: f421 5180 bic.w r1, r1, #4096 @ 0x1000
  22465. 800a458: 6219 str r1, [r3, #32]
  22466. tmpccmrx &= ~TIM_CCMR2_CC4S;
  22467. 800a45a: 493b ldr r1, [pc, #236] @ (800a548 <HAL_TIM_PWM_ConfigChannel+0x22c>)
  22468. tmpcr2 = TIMx->CR2;
  22469. 800a45c: 6858 ldr r0, [r3, #4]
  22470. tmpccmrx = TIMx->CCMR2;
  22471. 800a45e: 69de ldr r6, [r3, #28]
  22472. tmpccmrx &= ~TIM_CCMR2_CC4S;
  22473. 800a460: 4031 ands r1, r6
  22474. tmpccmrx |= (OC_Config->OCMode << 8U);
  22475. 800a462: 682e ldr r6, [r5, #0]
  22476. 800a464: ea41 2106 orr.w r1, r1, r6, lsl #8
  22477. tmpccer |= (OC_Config->OCPolarity << 12U);
  22478. 800a468: 68ae ldr r6, [r5, #8]
  22479. 800a46a: ea42 3206 orr.w r2, r2, r6, lsl #12
  22480. if (IS_TIM_BREAK_INSTANCE(TIMx))
  22481. 800a46e: 4e34 ldr r6, [pc, #208] @ (800a540 <HAL_TIM_PWM_ConfigChannel+0x224>)
  22482. 800a470: 42b3 cmp r3, r6
  22483. 800a472: d00e beq.n 800a492 <HAL_TIM_PWM_ConfigChannel+0x176>
  22484. 800a474: f506 6680 add.w r6, r6, #1024 @ 0x400
  22485. 800a478: 42b3 cmp r3, r6
  22486. 800a47a: d00a beq.n 800a492 <HAL_TIM_PWM_ConfigChannel+0x176>
  22487. 800a47c: 4f31 ldr r7, [pc, #196] @ (800a544 <HAL_TIM_PWM_ConfigChannel+0x228>)
  22488. 800a47e: f506 4680 add.w r6, r6, #16384 @ 0x4000
  22489. 800a482: 42b3 cmp r3, r6
  22490. 800a484: bf18 it ne
  22491. 800a486: 42bb cmpne r3, r7
  22492. 800a488: d003 beq.n 800a492 <HAL_TIM_PWM_ConfigChannel+0x176>
  22493. 800a48a: f506 6680 add.w r6, r6, #1024 @ 0x400
  22494. 800a48e: 42b3 cmp r3, r6
  22495. 800a490: d104 bne.n 800a49c <HAL_TIM_PWM_ConfigChannel+0x180>
  22496. tmpcr2 &= ~TIM_CR2_OIS4;
  22497. 800a492: f420 4080 bic.w r0, r0, #16384 @ 0x4000
  22498. tmpcr2 |= (OC_Config->OCIdleState << 6U);
  22499. 800a496: 696e ldr r6, [r5, #20]
  22500. 800a498: ea40 1086 orr.w r0, r0, r6, lsl #6
  22501. TIMx->CR2 = tmpcr2;
  22502. 800a49c: 6058 str r0, [r3, #4]
  22503. TIMx->CCR4 = OC_Config->Pulse;
  22504. 800a49e: 6868 ldr r0, [r5, #4]
  22505. TIMx->CCMR2 = tmpccmrx;
  22506. 800a4a0: 61d9 str r1, [r3, #28]
  22507. htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
  22508. 800a4a2: 6929 ldr r1, [r5, #16]
  22509. TIMx->CCR4 = OC_Config->Pulse;
  22510. 800a4a4: 6418 str r0, [r3, #64] @ 0x40
  22511. TIMx->CCER = tmpccer;
  22512. 800a4a6: 621a str r2, [r3, #32]
  22513. htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
  22514. 800a4a8: 69da ldr r2, [r3, #28]
  22515. 800a4aa: f442 6200 orr.w r2, r2, #2048 @ 0x800
  22516. 800a4ae: 61da str r2, [r3, #28]
  22517. htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
  22518. 800a4b0: 69da ldr r2, [r3, #28]
  22519. 800a4b2: f422 6280 bic.w r2, r2, #1024 @ 0x400
  22520. 800a4b6: 61da str r2, [r3, #28]
  22521. htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
  22522. 800a4b8: 69da ldr r2, [r3, #28]
  22523. 800a4ba: ea42 2201 orr.w r2, r2, r1, lsl #8
  22524. 800a4be: 61da str r2, [r3, #28]
  22525. break;
  22526. 800a4c0: e7a0 b.n 800a404 <HAL_TIM_PWM_ConfigChannel+0xe8>
  22527. TIM_OC5_SetConfig(htim->Instance, sConfig);
  22528. 800a4c2: 6803 ldr r3, [r0, #0]
  22529. tmpccer = TIMx->CCER;
  22530. 800a4c4: 6a1a ldr r2, [r3, #32]
  22531. TIMx->CCER &= ~TIM_CCER_CC5E;
  22532. 800a4c6: 6a19 ldr r1, [r3, #32]
  22533. tmpccer &= ~TIM_CCER_CC5P;
  22534. 800a4c8: f422 3200 bic.w r2, r2, #131072 @ 0x20000
  22535. TIMx->CCER &= ~TIM_CCER_CC5E;
  22536. 800a4cc: f421 3180 bic.w r1, r1, #65536 @ 0x10000
  22537. 800a4d0: 6219 str r1, [r3, #32]
  22538. tmpccmrx &= ~(TIM_CCMR3_OC5M);
  22539. 800a4d2: 491e ldr r1, [pc, #120] @ (800a54c <HAL_TIM_PWM_ConfigChannel+0x230>)
  22540. tmpcr2 = TIMx->CR2;
  22541. 800a4d4: 6858 ldr r0, [r3, #4]
  22542. tmpccmrx = TIMx->CCMR3;
  22543. 800a4d6: 6d5e ldr r6, [r3, #84] @ 0x54
  22544. tmpccmrx &= ~(TIM_CCMR3_OC5M);
  22545. 800a4d8: 4031 ands r1, r6
  22546. tmpccmrx |= OC_Config->OCMode;
  22547. 800a4da: 682e ldr r6, [r5, #0]
  22548. 800a4dc: 4331 orrs r1, r6
  22549. tmpccer |= (OC_Config->OCPolarity << 16U);
  22550. 800a4de: 68ae ldr r6, [r5, #8]
  22551. 800a4e0: ea42 4206 orr.w r2, r2, r6, lsl #16
  22552. if (IS_TIM_BREAK_INSTANCE(TIMx))
  22553. 800a4e4: 4e16 ldr r6, [pc, #88] @ (800a540 <HAL_TIM_PWM_ConfigChannel+0x224>)
  22554. 800a4e6: 42b3 cmp r3, r6
  22555. 800a4e8: d00e beq.n 800a508 <HAL_TIM_PWM_ConfigChannel+0x1ec>
  22556. 800a4ea: f506 6680 add.w r6, r6, #1024 @ 0x400
  22557. 800a4ee: 42b3 cmp r3, r6
  22558. 800a4f0: d00a beq.n 800a508 <HAL_TIM_PWM_ConfigChannel+0x1ec>
  22559. 800a4f2: 4f14 ldr r7, [pc, #80] @ (800a544 <HAL_TIM_PWM_ConfigChannel+0x228>)
  22560. 800a4f4: f506 4680 add.w r6, r6, #16384 @ 0x4000
  22561. 800a4f8: 42b3 cmp r3, r6
  22562. 800a4fa: bf18 it ne
  22563. 800a4fc: 42bb cmpne r3, r7
  22564. 800a4fe: d003 beq.n 800a508 <HAL_TIM_PWM_ConfigChannel+0x1ec>
  22565. 800a500: f506 6680 add.w r6, r6, #1024 @ 0x400
  22566. 800a504: 42b3 cmp r3, r6
  22567. 800a506: d104 bne.n 800a512 <HAL_TIM_PWM_ConfigChannel+0x1f6>
  22568. tmpcr2 &= ~TIM_CR2_OIS5;
  22569. 800a508: f420 3080 bic.w r0, r0, #65536 @ 0x10000
  22570. tmpcr2 |= (OC_Config->OCIdleState << 8U);
  22571. 800a50c: 696e ldr r6, [r5, #20]
  22572. 800a50e: ea40 2006 orr.w r0, r0, r6, lsl #8
  22573. TIMx->CR2 = tmpcr2;
  22574. 800a512: 6058 str r0, [r3, #4]
  22575. TIMx->CCR5 = OC_Config->Pulse;
  22576. 800a514: 6868 ldr r0, [r5, #4]
  22577. TIMx->CCMR3 = tmpccmrx;
  22578. 800a516: 6559 str r1, [r3, #84] @ 0x54
  22579. htim->Instance->CCMR3 |= sConfig->OCFastMode;
  22580. 800a518: 6929 ldr r1, [r5, #16]
  22581. TIMx->CCR5 = OC_Config->Pulse;
  22582. 800a51a: 6598 str r0, [r3, #88] @ 0x58
  22583. TIMx->CCER = tmpccer;
  22584. 800a51c: 621a str r2, [r3, #32]
  22585. htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
  22586. 800a51e: 6d5a ldr r2, [r3, #84] @ 0x54
  22587. 800a520: f042 0208 orr.w r2, r2, #8
  22588. 800a524: 655a str r2, [r3, #84] @ 0x54
  22589. htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
  22590. 800a526: 6d5a ldr r2, [r3, #84] @ 0x54
  22591. 800a528: f022 0204 bic.w r2, r2, #4
  22592. 800a52c: 655a str r2, [r3, #84] @ 0x54
  22593. htim->Instance->CCMR3 |= sConfig->OCFastMode;
  22594. 800a52e: 6d5a ldr r2, [r3, #84] @ 0x54
  22595. 800a530: 430a orrs r2, r1
  22596. 800a532: 655a str r2, [r3, #84] @ 0x54
  22597. break;
  22598. 800a534: e766 b.n 800a404 <HAL_TIM_PWM_ConfigChannel+0xe8>
  22599. __HAL_LOCK(htim);
  22600. 800a536: 2002 movs r0, #2
  22601. }
  22602. 800a538: bdf8 pop {r3, r4, r5, r6, r7, pc}
  22603. 800a53a: bf00 nop
  22604. 800a53c: feff8fff .word 0xfeff8fff
  22605. 800a540: 40010000 .word 0x40010000
  22606. 800a544: 40014000 .word 0x40014000
  22607. 800a548: feff8cff .word 0xfeff8cff
  22608. 800a54c: fffeff8f .word 0xfffeff8f
  22609. 0800a550 <HAL_TIMEx_MasterConfigSynchronization>:
  22610. assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  22611. assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  22612. assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
  22613. /* Check input state */
  22614. __HAL_LOCK(htim);
  22615. 800a550: f890 303c ldrb.w r3, [r0, #60] @ 0x3c
  22616. 800a554: 2b01 cmp r3, #1
  22617. 800a556: d04b beq.n 800a5f0 <HAL_TIMEx_MasterConfigSynchronization+0xa0>
  22618. /* Change the handler state */
  22619. htim->State = HAL_TIM_STATE_BUSY;
  22620. /* Get the TIMx CR2 register value */
  22621. tmpcr2 = htim->Instance->CR2;
  22622. 800a558: 6803 ldr r3, [r0, #0]
  22623. 800a55a: 4602 mov r2, r0
  22624. htim->State = HAL_TIM_STATE_BUSY;
  22625. 800a55c: 2002 movs r0, #2
  22626. {
  22627. 800a55e: b430 push {r4, r5}
  22628. /* Get the TIMx SMCR register value */
  22629. tmpsmcr = htim->Instance->SMCR;
  22630. /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
  22631. if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
  22632. 800a560: 4d24 ldr r5, [pc, #144] @ (800a5f4 <HAL_TIMEx_MasterConfigSynchronization+0xa4>)
  22633. htim->State = HAL_TIM_STATE_BUSY;
  22634. 800a562: f882 003d strb.w r0, [r2, #61] @ 0x3d
  22635. if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
  22636. 800a566: 42ab cmp r3, r5
  22637. tmpcr2 = htim->Instance->CR2;
  22638. 800a568: 6858 ldr r0, [r3, #4]
  22639. tmpsmcr = htim->Instance->SMCR;
  22640. 800a56a: 689c ldr r4, [r3, #8]
  22641. if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
  22642. 800a56c: d029 beq.n 800a5c2 <HAL_TIMEx_MasterConfigSynchronization+0x72>
  22643. 800a56e: f505 6580 add.w r5, r5, #1024 @ 0x400
  22644. 800a572: 42ab cmp r3, r5
  22645. 800a574: d025 beq.n 800a5c2 <HAL_TIMEx_MasterConfigSynchronization+0x72>
  22646. tmpcr2 |= sMasterConfig->MasterOutputTrigger;
  22647. /* Update TIMx CR2 */
  22648. htim->Instance->CR2 = tmpcr2;
  22649. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  22650. 800a576: 4d20 ldr r5, [pc, #128] @ (800a5f8 <HAL_TIMEx_MasterConfigSynchronization+0xa8>)
  22651. tmpcr2 &= ~TIM_CR2_MMS;
  22652. 800a578: f020 0070 bic.w r0, r0, #112 @ 0x70
  22653. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  22654. 800a57c: 42ab cmp r3, r5
  22655. 800a57e: bf18 it ne
  22656. 800a580: f1b3 4f80 cmpne.w r3, #1073741824 @ 0x40000000
  22657. 800a584: f505 6580 add.w r5, r5, #1024 @ 0x400
  22658. 800a588: bf0c ite eq
  22659. 800a58a: f04f 0c01 moveq.w ip, #1
  22660. 800a58e: f04f 0c00 movne.w ip, #0
  22661. 800a592: 42ab cmp r3, r5
  22662. 800a594: bf08 it eq
  22663. 800a596: f04c 0c01 orreq.w ip, ip, #1
  22664. 800a59a: f505 6580 add.w r5, r5, #1024 @ 0x400
  22665. 800a59e: 42ab cmp r3, r5
  22666. 800a5a0: bf08 it eq
  22667. 800a5a2: f04c 0c01 orreq.w ip, ip, #1
  22668. tmpcr2 |= sMasterConfig->MasterOutputTrigger;
  22669. 800a5a6: 680d ldr r5, [r1, #0]
  22670. 800a5a8: 4328 orrs r0, r5
  22671. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  22672. 800a5aa: 4d14 ldr r5, [pc, #80] @ (800a5fc <HAL_TIMEx_MasterConfigSynchronization+0xac>)
  22673. htim->Instance->CR2 = tmpcr2;
  22674. 800a5ac: 6058 str r0, [r3, #4]
  22675. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  22676. 800a5ae: 42ab cmp r3, r5
  22677. 800a5b0: bf14 ite ne
  22678. 800a5b2: 4660 movne r0, ip
  22679. 800a5b4: f04c 0001 orreq.w r0, ip, #1
  22680. 800a5b8: b960 cbnz r0, 800a5d4 <HAL_TIMEx_MasterConfigSynchronization+0x84>
  22681. 800a5ba: 4811 ldr r0, [pc, #68] @ (800a600 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
  22682. 800a5bc: 4283 cmp r3, r0
  22683. 800a5be: d009 beq.n 800a5d4 <HAL_TIMEx_MasterConfigSynchronization+0x84>
  22684. 800a5c0: e00d b.n 800a5de <HAL_TIMEx_MasterConfigSynchronization+0x8e>
  22685. tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
  22686. 800a5c2: 684d ldr r5, [r1, #4]
  22687. tmpcr2 &= ~TIM_CR2_MMS2;
  22688. 800a5c4: f420 0070 bic.w r0, r0, #15728640 @ 0xf00000
  22689. tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
  22690. 800a5c8: 4328 orrs r0, r5
  22691. tmpcr2 |= sMasterConfig->MasterOutputTrigger;
  22692. 800a5ca: 680d ldr r5, [r1, #0]
  22693. tmpcr2 &= ~TIM_CR2_MMS;
  22694. 800a5cc: f020 0070 bic.w r0, r0, #112 @ 0x70
  22695. tmpcr2 |= sMasterConfig->MasterOutputTrigger;
  22696. 800a5d0: 4328 orrs r0, r5
  22697. htim->Instance->CR2 = tmpcr2;
  22698. 800a5d2: 6058 str r0, [r3, #4]
  22699. {
  22700. /* Reset the MSM Bit */
  22701. tmpsmcr &= ~TIM_SMCR_MSM;
  22702. /* Set master mode */
  22703. tmpsmcr |= sMasterConfig->MasterSlaveMode;
  22704. 800a5d4: 6889 ldr r1, [r1, #8]
  22705. tmpsmcr &= ~TIM_SMCR_MSM;
  22706. 800a5d6: f024 0480 bic.w r4, r4, #128 @ 0x80
  22707. tmpsmcr |= sMasterConfig->MasterSlaveMode;
  22708. 800a5da: 430c orrs r4, r1
  22709. /* Update TIMx SMCR */
  22710. htim->Instance->SMCR = tmpsmcr;
  22711. 800a5dc: 609c str r4, [r3, #8]
  22712. }
  22713. /* Change the htim state */
  22714. htim->State = HAL_TIM_STATE_READY;
  22715. __HAL_UNLOCK(htim);
  22716. 800a5de: 2300 movs r3, #0
  22717. htim->State = HAL_TIM_STATE_READY;
  22718. 800a5e0: 2101 movs r1, #1
  22719. return HAL_OK;
  22720. 800a5e2: 4618 mov r0, r3
  22721. htim->State = HAL_TIM_STATE_READY;
  22722. 800a5e4: f882 103d strb.w r1, [r2, #61] @ 0x3d
  22723. __HAL_UNLOCK(htim);
  22724. 800a5e8: f882 303c strb.w r3, [r2, #60] @ 0x3c
  22725. }
  22726. 800a5ec: bc30 pop {r4, r5}
  22727. 800a5ee: 4770 bx lr
  22728. __HAL_LOCK(htim);
  22729. 800a5f0: 2002 movs r0, #2
  22730. }
  22731. 800a5f2: 4770 bx lr
  22732. 800a5f4: 40010000 .word 0x40010000
  22733. 800a5f8: 40000400 .word 0x40000400
  22734. 800a5fc: 40001800 .word 0x40001800
  22735. 800a600: 40014000 .word 0x40014000
  22736. 0800a604 <HAL_TIMEx_ConfigBreakDeadTime>:
  22737. #if defined(TIM_BDTR_BKBID)
  22738. assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
  22739. #endif /* TIM_BDTR_BKBID */
  22740. /* Check input state */
  22741. __HAL_LOCK(htim);
  22742. 800a604: f890 303c ldrb.w r3, [r0, #60] @ 0x3c
  22743. 800a608: 2b01 cmp r3, #1
  22744. 800a60a: d03d beq.n 800a688 <HAL_TIMEx_ConfigBreakDeadTime+0x84>
  22745. the OSSI State, the dead time value and the Automatic Output Enable Bit */
  22746. /* Set the BDTR bits */
  22747. MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
  22748. MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
  22749. MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
  22750. 800a60c: 4602 mov r2, r0
  22751. 800a60e: 6848 ldr r0, [r1, #4]
  22752. {
  22753. 800a610: b410 push {r4}
  22754. MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
  22755. 800a612: e9d1 4302 ldrd r4, r3, [r1, #8]
  22756. 800a616: f423 7340 bic.w r3, r3, #768 @ 0x300
  22757. 800a61a: 4323 orrs r3, r4
  22758. MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
  22759. 800a61c: 680c ldr r4, [r1, #0]
  22760. MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
  22761. 800a61e: f423 6380 bic.w r3, r3, #1024 @ 0x400
  22762. 800a622: 4303 orrs r3, r0
  22763. MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
  22764. 800a624: 6908 ldr r0, [r1, #16]
  22765. MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
  22766. 800a626: f423 6300 bic.w r3, r3, #2048 @ 0x800
  22767. 800a62a: 4323 orrs r3, r4
  22768. MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
  22769. 800a62c: 694c ldr r4, [r1, #20]
  22770. MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
  22771. 800a62e: f423 5380 bic.w r3, r3, #4096 @ 0x1000
  22772. 800a632: 4303 orrs r3, r0
  22773. MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
  22774. 800a634: 6a88 ldr r0, [r1, #40] @ 0x28
  22775. MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
  22776. 800a636: f423 5300 bic.w r3, r3, #8192 @ 0x2000
  22777. 800a63a: 4323 orrs r3, r4
  22778. MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
  22779. 800a63c: 698c ldr r4, [r1, #24]
  22780. MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
  22781. 800a63e: f423 4380 bic.w r3, r3, #16384 @ 0x4000
  22782. 800a642: 4303 orrs r3, r0
  22783. #if defined(TIM_BDTR_BKBID)
  22784. MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
  22785. #endif /* TIM_BDTR_BKBID */
  22786. if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
  22787. 800a644: 6810 ldr r0, [r2, #0]
  22788. MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
  22789. 800a646: f423 2370 bic.w r3, r3, #983040 @ 0xf0000
  22790. 800a64a: ea43 4304 orr.w r3, r3, r4, lsl #16
  22791. if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
  22792. 800a64e: 4c0f ldr r4, [pc, #60] @ (800a68c <HAL_TIMEx_ConfigBreakDeadTime+0x88>)
  22793. 800a650: 42a0 cmp r0, r4
  22794. 800a652: d00b beq.n 800a66c <HAL_TIMEx_ConfigBreakDeadTime+0x68>
  22795. 800a654: f504 6480 add.w r4, r4, #1024 @ 0x400
  22796. 800a658: 42a0 cmp r0, r4
  22797. 800a65a: d007 beq.n 800a66c <HAL_TIMEx_ConfigBreakDeadTime+0x68>
  22798. }
  22799. /* Set TIMx_BDTR */
  22800. htim->Instance->BDTR = tmpbdtr;
  22801. __HAL_UNLOCK(htim);
  22802. 800a65c: 2100 movs r1, #0
  22803. htim->Instance->BDTR = tmpbdtr;
  22804. 800a65e: 6443 str r3, [r0, #68] @ 0x44
  22805. __HAL_UNLOCK(htim);
  22806. 800a660: f882 103c strb.w r1, [r2, #60] @ 0x3c
  22807. return HAL_OK;
  22808. 800a664: 4608 mov r0, r1
  22809. }
  22810. 800a666: f85d 4b04 ldr.w r4, [sp], #4
  22811. 800a66a: 4770 bx lr
  22812. MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
  22813. 800a66c: 6a4c ldr r4, [r1, #36] @ 0x24
  22814. 800a66e: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
  22815. 800a672: ea43 5304 orr.w r3, r3, r4, lsl #20
  22816. MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
  22817. 800a676: e9d1 4107 ldrd r4, r1, [r1, #28]
  22818. MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
  22819. 800a67a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
  22820. 800a67e: 4323 orrs r3, r4
  22821. MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
  22822. 800a680: f023 7300 bic.w r3, r3, #33554432 @ 0x2000000
  22823. 800a684: 430b orrs r3, r1
  22824. 800a686: e7e9 b.n 800a65c <HAL_TIMEx_ConfigBreakDeadTime+0x58>
  22825. __HAL_LOCK(htim);
  22826. 800a688: 2002 movs r0, #2
  22827. }
  22828. 800a68a: 4770 bx lr
  22829. 800a68c: 40010000 .word 0x40010000
  22830. 0800a690 <HAL_TIMEx_CommutCallback>:
  22831. /**
  22832. * @brief Commutation callback in non-blocking mode
  22833. * @param htim TIM handle
  22834. * @retval None
  22835. */
  22836. __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
  22837. 800a690: 4770 bx lr
  22838. 800a692: bf00 nop
  22839. 0800a694 <HAL_TIMEx_BreakCallback>:
  22840. /**
  22841. * @brief Break detection callback in non-blocking mode
  22842. * @param htim TIM handle
  22843. * @retval None
  22844. */
  22845. __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
  22846. 800a694: 4770 bx lr
  22847. 800a696: bf00 nop
  22848. 0800a698 <HAL_TIMEx_Break2Callback>:
  22849. /**
  22850. * @brief Break2 detection callback in non blocking mode
  22851. * @param htim: TIM handle
  22852. * @retval None
  22853. */
  22854. __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
  22855. 800a698: 4770 bx lr
  22856. 800a69a: bf00 nop
  22857. 0800a69c <UART_TxISR_16BIT>:
  22858. static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
  22859. {
  22860. const uint16_t *tmp;
  22861. /* Check that a Tx process is ongoing */
  22862. if (huart->gState == HAL_UART_STATE_BUSY_TX)
  22863. 800a69c: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88
  22864. 800a6a0: 2b21 cmp r3, #33 @ 0x21
  22865. 800a6a2: d000 beq.n 800a6a6 <UART_TxISR_16BIT+0xa>
  22866. huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
  22867. huart->pTxBuffPtr += 2U;
  22868. huart->TxXferCount--;
  22869. }
  22870. }
  22871. }
  22872. 800a6a4: 4770 bx lr
  22873. if (huart->TxXferCount == 0U)
  22874. 800a6a6: f8b0 3056 ldrh.w r3, [r0, #86] @ 0x56
  22875. huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
  22876. 800a6aa: 6802 ldr r2, [r0, #0]
  22877. if (huart->TxXferCount == 0U)
  22878. 800a6ac: b29b uxth r3, r3
  22879. 800a6ae: b983 cbnz r3, 800a6d2 <UART_TxISR_16BIT+0x36>
  22880. */
  22881. __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
  22882. {
  22883. uint32_t result;
  22884. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  22885. 800a6b0: e852 3f00 ldrex r3, [r2]
  22886. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
  22887. 800a6b4: f023 0380 bic.w r3, r3, #128 @ 0x80
  22888. */
  22889. __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
  22890. {
  22891. uint32_t result;
  22892. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  22893. 800a6b8: e842 3100 strex r1, r3, [r2]
  22894. 800a6bc: 2900 cmp r1, #0
  22895. 800a6be: d1f7 bne.n 800a6b0 <UART_TxISR_16BIT+0x14>
  22896. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  22897. 800a6c0: e852 3f00 ldrex r3, [r2]
  22898. ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
  22899. 800a6c4: f043 0340 orr.w r3, r3, #64 @ 0x40
  22900. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  22901. 800a6c8: e842 3100 strex r1, r3, [r2]
  22902. 800a6cc: 2900 cmp r1, #0
  22903. 800a6ce: d1f7 bne.n 800a6c0 <UART_TxISR_16BIT+0x24>
  22904. 800a6d0: 4770 bx lr
  22905. huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
  22906. 800a6d2: 6d01 ldr r1, [r0, #80] @ 0x50
  22907. 800a6d4: f831 3b02 ldrh.w r3, [r1], #2
  22908. 800a6d8: f3c3 0308 ubfx r3, r3, #0, #9
  22909. 800a6dc: 6293 str r3, [r2, #40] @ 0x28
  22910. huart->TxXferCount--;
  22911. 800a6de: f8b0 3056 ldrh.w r3, [r0, #86] @ 0x56
  22912. huart->pTxBuffPtr += 2U;
  22913. 800a6e2: 6501 str r1, [r0, #80] @ 0x50
  22914. huart->TxXferCount--;
  22915. 800a6e4: 3b01 subs r3, #1
  22916. 800a6e6: b29b uxth r3, r3
  22917. 800a6e8: f8a0 3056 strh.w r3, [r0, #86] @ 0x56
  22918. }
  22919. 800a6ec: 4770 bx lr
  22920. 800a6ee: bf00 nop
  22921. 0800a6f0 <UART_TxISR_16BIT_FIFOEN>:
  22922. {
  22923. const uint16_t *tmp;
  22924. uint16_t nb_tx_data;
  22925. /* Check that a Tx process is ongoing */
  22926. if (huart->gState == HAL_UART_STATE_BUSY_TX)
  22927. 800a6f0: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88
  22928. 800a6f4: 2b21 cmp r3, #33 @ 0x21
  22929. 800a6f6: d000 beq.n 800a6fa <UART_TxISR_16BIT_FIFOEN+0xa>
  22930. 800a6f8: 4770 bx lr
  22931. {
  22932. for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
  22933. 800a6fa: f8b0 306a ldrh.w r3, [r0, #106] @ 0x6a
  22934. 800a6fe: 2b00 cmp r3, #0
  22935. 800a700: d0fa beq.n 800a6f8 <UART_TxISR_16BIT_FIFOEN+0x8>
  22936. /* Enable the UART Transmit Complete Interrupt */
  22937. ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
  22938. break; /* force exit loop */
  22939. }
  22940. else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
  22941. 800a702: 6801 ldr r1, [r0, #0]
  22942. {
  22943. 800a704: b410 push {r4}
  22944. if (huart->TxXferCount == 0U)
  22945. 800a706: f8b0 2056 ldrh.w r2, [r0, #86] @ 0x56
  22946. for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
  22947. 800a70a: 3b01 subs r3, #1
  22948. if (huart->TxXferCount == 0U)
  22949. 800a70c: b292 uxth r2, r2
  22950. for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
  22951. 800a70e: b29b uxth r3, r3
  22952. if (huart->TxXferCount == 0U)
  22953. 800a710: b1a2 cbz r2, 800a73c <UART_TxISR_16BIT_FIFOEN+0x4c>
  22954. else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
  22955. 800a712: 69ca ldr r2, [r1, #28]
  22956. 800a714: 0612 lsls r2, r2, #24
  22957. 800a716: d50c bpl.n 800a732 <UART_TxISR_16BIT_FIFOEN+0x42>
  22958. {
  22959. tmp = (const uint16_t *) huart->pTxBuffPtr;
  22960. huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
  22961. 800a718: 6d04 ldr r4, [r0, #80] @ 0x50
  22962. 800a71a: f834 2b02 ldrh.w r2, [r4], #2
  22963. 800a71e: f3c2 0208 ubfx r2, r2, #0, #9
  22964. 800a722: 628a str r2, [r1, #40] @ 0x28
  22965. huart->pTxBuffPtr += 2U;
  22966. huart->TxXferCount--;
  22967. 800a724: f8b0 2056 ldrh.w r2, [r0, #86] @ 0x56
  22968. huart->pTxBuffPtr += 2U;
  22969. 800a728: 6504 str r4, [r0, #80] @ 0x50
  22970. huart->TxXferCount--;
  22971. 800a72a: 3a01 subs r2, #1
  22972. 800a72c: b292 uxth r2, r2
  22973. 800a72e: f8a0 2056 strh.w r2, [r0, #86] @ 0x56
  22974. for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
  22975. 800a732: 2b00 cmp r3, #0
  22976. 800a734: d1e7 bne.n 800a706 <UART_TxISR_16BIT_FIFOEN+0x16>
  22977. {
  22978. /* Nothing to do */
  22979. }
  22980. }
  22981. }
  22982. }
  22983. 800a736: f85d 4b04 ldr.w r4, [sp], #4
  22984. 800a73a: 4770 bx lr
  22985. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  22986. 800a73c: f101 0308 add.w r3, r1, #8
  22987. 800a740: e853 3f00 ldrex r3, [r3]
  22988. ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
  22989. 800a744: f423 0300 bic.w r3, r3, #8388608 @ 0x800000
  22990. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  22991. 800a748: f101 0008 add.w r0, r1, #8
  22992. 800a74c: e840 3200 strex r2, r3, [r0]
  22993. 800a750: 2a00 cmp r2, #0
  22994. 800a752: d1f3 bne.n 800a73c <UART_TxISR_16BIT_FIFOEN+0x4c>
  22995. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  22996. 800a754: e851 3f00 ldrex r3, [r1]
  22997. ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
  22998. 800a758: f043 0340 orr.w r3, r3, #64 @ 0x40
  22999. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23000. 800a75c: e841 3200 strex r2, r3, [r1]
  23001. 800a760: 2a00 cmp r2, #0
  23002. 800a762: d0e8 beq.n 800a736 <UART_TxISR_16BIT_FIFOEN+0x46>
  23003. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23004. 800a764: e851 3f00 ldrex r3, [r1]
  23005. 800a768: f043 0340 orr.w r3, r3, #64 @ 0x40
  23006. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23007. 800a76c: e841 3200 strex r2, r3, [r1]
  23008. 800a770: 2a00 cmp r2, #0
  23009. 800a772: d1ef bne.n 800a754 <UART_TxISR_16BIT_FIFOEN+0x64>
  23010. 800a774: e7df b.n 800a736 <UART_TxISR_16BIT_FIFOEN+0x46>
  23011. 800a776: bf00 nop
  23012. 0800a778 <UART_TxISR_8BIT>:
  23013. if (huart->gState == HAL_UART_STATE_BUSY_TX)
  23014. 800a778: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88
  23015. 800a77c: 2b21 cmp r3, #33 @ 0x21
  23016. 800a77e: d000 beq.n 800a782 <UART_TxISR_8BIT+0xa>
  23017. }
  23018. 800a780: 4770 bx lr
  23019. if (huart->TxXferCount == 0U)
  23020. 800a782: f8b0 3056 ldrh.w r3, [r0, #86] @ 0x56
  23021. huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
  23022. 800a786: 6802 ldr r2, [r0, #0]
  23023. if (huart->TxXferCount == 0U)
  23024. 800a788: b29b uxth r3, r3
  23025. 800a78a: b983 cbnz r3, 800a7ae <UART_TxISR_8BIT+0x36>
  23026. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23027. 800a78c: e852 3f00 ldrex r3, [r2]
  23028. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
  23029. 800a790: f023 0380 bic.w r3, r3, #128 @ 0x80
  23030. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23031. 800a794: e842 3100 strex r1, r3, [r2]
  23032. 800a798: 2900 cmp r1, #0
  23033. 800a79a: d1f7 bne.n 800a78c <UART_TxISR_8BIT+0x14>
  23034. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23035. 800a79c: e852 3f00 ldrex r3, [r2]
  23036. ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
  23037. 800a7a0: f043 0340 orr.w r3, r3, #64 @ 0x40
  23038. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23039. 800a7a4: e842 3100 strex r1, r3, [r2]
  23040. 800a7a8: 2900 cmp r1, #0
  23041. 800a7aa: d1f7 bne.n 800a79c <UART_TxISR_8BIT+0x24>
  23042. 800a7ac: 4770 bx lr
  23043. huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
  23044. 800a7ae: 6d01 ldr r1, [r0, #80] @ 0x50
  23045. 800a7b0: f811 3b01 ldrb.w r3, [r1], #1
  23046. 800a7b4: 6293 str r3, [r2, #40] @ 0x28
  23047. huart->TxXferCount--;
  23048. 800a7b6: f8b0 3056 ldrh.w r3, [r0, #86] @ 0x56
  23049. huart->pTxBuffPtr++;
  23050. 800a7ba: 6501 str r1, [r0, #80] @ 0x50
  23051. huart->TxXferCount--;
  23052. 800a7bc: 3b01 subs r3, #1
  23053. 800a7be: b29b uxth r3, r3
  23054. 800a7c0: f8a0 3056 strh.w r3, [r0, #86] @ 0x56
  23055. }
  23056. 800a7c4: 4770 bx lr
  23057. 800a7c6: bf00 nop
  23058. 0800a7c8 <UART_TxISR_8BIT_FIFOEN>:
  23059. if (huart->gState == HAL_UART_STATE_BUSY_TX)
  23060. 800a7c8: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88
  23061. 800a7cc: 2b21 cmp r3, #33 @ 0x21
  23062. 800a7ce: d000 beq.n 800a7d2 <UART_TxISR_8BIT_FIFOEN+0xa>
  23063. 800a7d0: 4770 bx lr
  23064. for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
  23065. 800a7d2: f8b0 306a ldrh.w r3, [r0, #106] @ 0x6a
  23066. 800a7d6: 2b00 cmp r3, #0
  23067. 800a7d8: d0fa beq.n 800a7d0 <UART_TxISR_8BIT_FIFOEN+0x8>
  23068. else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
  23069. 800a7da: 6801 ldr r1, [r0, #0]
  23070. {
  23071. 800a7dc: b410 push {r4}
  23072. if (huart->TxXferCount == 0U)
  23073. 800a7de: f8b0 2056 ldrh.w r2, [r0, #86] @ 0x56
  23074. for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
  23075. 800a7e2: 3b01 subs r3, #1
  23076. if (huart->TxXferCount == 0U)
  23077. 800a7e4: b292 uxth r2, r2
  23078. for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
  23079. 800a7e6: b29b uxth r3, r3
  23080. if (huart->TxXferCount == 0U)
  23081. 800a7e8: b192 cbz r2, 800a810 <UART_TxISR_8BIT_FIFOEN+0x48>
  23082. else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
  23083. 800a7ea: 69ca ldr r2, [r1, #28]
  23084. 800a7ec: 0612 lsls r2, r2, #24
  23085. 800a7ee: d50a bpl.n 800a806 <UART_TxISR_8BIT_FIFOEN+0x3e>
  23086. huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
  23087. 800a7f0: 6d04 ldr r4, [r0, #80] @ 0x50
  23088. 800a7f2: f814 2b01 ldrb.w r2, [r4], #1
  23089. 800a7f6: 628a str r2, [r1, #40] @ 0x28
  23090. huart->TxXferCount--;
  23091. 800a7f8: f8b0 2056 ldrh.w r2, [r0, #86] @ 0x56
  23092. huart->pTxBuffPtr++;
  23093. 800a7fc: 6504 str r4, [r0, #80] @ 0x50
  23094. huart->TxXferCount--;
  23095. 800a7fe: 3a01 subs r2, #1
  23096. 800a800: b292 uxth r2, r2
  23097. 800a802: f8a0 2056 strh.w r2, [r0, #86] @ 0x56
  23098. for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
  23099. 800a806: 2b00 cmp r3, #0
  23100. 800a808: d1e9 bne.n 800a7de <UART_TxISR_8BIT_FIFOEN+0x16>
  23101. }
  23102. 800a80a: f85d 4b04 ldr.w r4, [sp], #4
  23103. 800a80e: 4770 bx lr
  23104. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23105. 800a810: f101 0308 add.w r3, r1, #8
  23106. 800a814: e853 3f00 ldrex r3, [r3]
  23107. ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
  23108. 800a818: f423 0300 bic.w r3, r3, #8388608 @ 0x800000
  23109. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23110. 800a81c: f101 0008 add.w r0, r1, #8
  23111. 800a820: e840 3200 strex r2, r3, [r0]
  23112. 800a824: 2a00 cmp r2, #0
  23113. 800a826: d1f3 bne.n 800a810 <UART_TxISR_8BIT_FIFOEN+0x48>
  23114. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23115. 800a828: e851 3f00 ldrex r3, [r1]
  23116. ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
  23117. 800a82c: f043 0340 orr.w r3, r3, #64 @ 0x40
  23118. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23119. 800a830: e841 3200 strex r2, r3, [r1]
  23120. 800a834: 2a00 cmp r2, #0
  23121. 800a836: d0e8 beq.n 800a80a <UART_TxISR_8BIT_FIFOEN+0x42>
  23122. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23123. 800a838: e851 3f00 ldrex r3, [r1]
  23124. 800a83c: f043 0340 orr.w r3, r3, #64 @ 0x40
  23125. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23126. 800a840: e841 3200 strex r2, r3, [r1]
  23127. 800a844: 2a00 cmp r2, #0
  23128. 800a846: d1ef bne.n 800a828 <UART_TxISR_8BIT_FIFOEN+0x60>
  23129. 800a848: e7df b.n 800a80a <UART_TxISR_8BIT_FIFOEN+0x42>
  23130. 800a84a: bf00 nop
  23131. 0800a84c <HAL_UART_Transmit_IT>:
  23132. if (huart->gState == HAL_UART_STATE_READY)
  23133. 800a84c: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88
  23134. 800a850: 2b20 cmp r3, #32
  23135. 800a852: d128 bne.n 800a8a6 <HAL_UART_Transmit_IT+0x5a>
  23136. if ((pData == NULL) || (Size == 0U))
  23137. 800a854: b329 cbz r1, 800a8a2 <HAL_UART_Transmit_IT+0x56>
  23138. 800a856: fab2 f382 clz r3, r2
  23139. 800a85a: 095b lsrs r3, r3, #5
  23140. 800a85c: b30a cbz r2, 800a8a2 <HAL_UART_Transmit_IT+0x56>
  23141. {
  23142. 800a85e: b410 push {r4}
  23143. huart->pTxBuffPtr = pData;
  23144. 800a860: 6501 str r1, [r0, #80] @ 0x50
  23145. huart->gState = HAL_UART_STATE_BUSY_TX;
  23146. 800a862: 2421 movs r4, #33 @ 0x21
  23147. if (huart->FifoMode == UART_FIFOMODE_ENABLE)
  23148. 800a864: 6e41 ldr r1, [r0, #100] @ 0x64
  23149. huart->TxXferCount = Size;
  23150. 800a866: f8a0 2056 strh.w r2, [r0, #86] @ 0x56
  23151. if (huart->FifoMode == UART_FIFOMODE_ENABLE)
  23152. 800a86a: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000
  23153. huart->ErrorCode = HAL_UART_ERROR_NONE;
  23154. 800a86e: f8c0 3090 str.w r3, [r0, #144] @ 0x90
  23155. huart->TxXferSize = Size;
  23156. 800a872: f8a0 2054 strh.w r2, [r0, #84] @ 0x54
  23157. if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
  23158. 800a876: 6883 ldr r3, [r0, #8]
  23159. huart->gState = HAL_UART_STATE_BUSY_TX;
  23160. 800a878: f8c0 4088 str.w r4, [r0, #136] @ 0x88
  23161. if (huart->FifoMode == UART_FIFOMODE_ENABLE)
  23162. 800a87c: d01c beq.n 800a8b8 <HAL_UART_Transmit_IT+0x6c>
  23163. if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
  23164. 800a87e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
  23165. 800a882: d012 beq.n 800a8aa <HAL_UART_Transmit_IT+0x5e>
  23166. huart->TxISR = UART_TxISR_8BIT;
  23167. 800a884: 4b1b ldr r3, [pc, #108] @ (800a8f4 <HAL_UART_Transmit_IT+0xa8>)
  23168. 800a886: 6802 ldr r2, [r0, #0]
  23169. 800a888: 6783 str r3, [r0, #120] @ 0x78
  23170. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23171. 800a88a: e852 3f00 ldrex r3, [r2]
  23172. ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
  23173. 800a88e: f043 0380 orr.w r3, r3, #128 @ 0x80
  23174. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23175. 800a892: e842 3100 strex r1, r3, [r2]
  23176. 800a896: 2900 cmp r1, #0
  23177. 800a898: d1f7 bne.n 800a88a <HAL_UART_Transmit_IT+0x3e>
  23178. return HAL_OK;
  23179. 800a89a: 2000 movs r0, #0
  23180. }
  23181. 800a89c: f85d 4b04 ldr.w r4, [sp], #4
  23182. 800a8a0: 4770 bx lr
  23183. return HAL_ERROR;
  23184. 800a8a2: 2001 movs r0, #1
  23185. }
  23186. 800a8a4: 4770 bx lr
  23187. return HAL_BUSY;
  23188. 800a8a6: 2002 movs r0, #2
  23189. 800a8a8: 4770 bx lr
  23190. if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
  23191. 800a8aa: 6901 ldr r1, [r0, #16]
  23192. huart->TxISR = UART_TxISR_16BIT;
  23193. 800a8ac: 4b11 ldr r3, [pc, #68] @ (800a8f4 <HAL_UART_Transmit_IT+0xa8>)
  23194. 800a8ae: 4a12 ldr r2, [pc, #72] @ (800a8f8 <HAL_UART_Transmit_IT+0xac>)
  23195. 800a8b0: 2900 cmp r1, #0
  23196. 800a8b2: bf08 it eq
  23197. 800a8b4: 4613 moveq r3, r2
  23198. 800a8b6: e7e6 b.n 800a886 <HAL_UART_Transmit_IT+0x3a>
  23199. if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
  23200. 800a8b8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
  23201. 800a8bc: d012 beq.n 800a8e4 <HAL_UART_Transmit_IT+0x98>
  23202. huart->TxISR = UART_TxISR_8BIT_FIFOEN;
  23203. 800a8be: 4b0f ldr r3, [pc, #60] @ (800a8fc <HAL_UART_Transmit_IT+0xb0>)
  23204. 800a8c0: 6802 ldr r2, [r0, #0]
  23205. 800a8c2: 6783 str r3, [r0, #120] @ 0x78
  23206. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23207. 800a8c4: f102 0308 add.w r3, r2, #8
  23208. 800a8c8: e853 3f00 ldrex r3, [r3]
  23209. ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
  23210. 800a8cc: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
  23211. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23212. 800a8d0: f102 0008 add.w r0, r2, #8
  23213. 800a8d4: e840 3100 strex r1, r3, [r0]
  23214. 800a8d8: 2900 cmp r1, #0
  23215. 800a8da: d1f3 bne.n 800a8c4 <HAL_UART_Transmit_IT+0x78>
  23216. return HAL_OK;
  23217. 800a8dc: 2000 movs r0, #0
  23218. }
  23219. 800a8de: f85d 4b04 ldr.w r4, [sp], #4
  23220. 800a8e2: 4770 bx lr
  23221. if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
  23222. 800a8e4: 6901 ldr r1, [r0, #16]
  23223. huart->TxISR = UART_TxISR_16BIT_FIFOEN;
  23224. 800a8e6: 4b05 ldr r3, [pc, #20] @ (800a8fc <HAL_UART_Transmit_IT+0xb0>)
  23225. 800a8e8: 4a05 ldr r2, [pc, #20] @ (800a900 <HAL_UART_Transmit_IT+0xb4>)
  23226. 800a8ea: 2900 cmp r1, #0
  23227. 800a8ec: bf08 it eq
  23228. 800a8ee: 4613 moveq r3, r2
  23229. 800a8f0: e7e6 b.n 800a8c0 <HAL_UART_Transmit_IT+0x74>
  23230. 800a8f2: bf00 nop
  23231. 800a8f4: 0800a779 .word 0x0800a779
  23232. 800a8f8: 0800a69d .word 0x0800a69d
  23233. 800a8fc: 0800a7c9 .word 0x0800a7c9
  23234. 800a900: 0800a6f1 .word 0x0800a6f1
  23235. 0800a904 <HAL_UART_ErrorCallback>:
  23236. __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
  23237. 800a904: 4770 bx lr
  23238. 800a906: bf00 nop
  23239. 0800a908 <UART_DMAAbortOnError>:
  23240. {
  23241. 800a908: b508 push {r3, lr}
  23242. UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
  23243. 800a90a: 6b80 ldr r0, [r0, #56] @ 0x38
  23244. huart->RxXferCount = 0U;
  23245. 800a90c: 2300 movs r3, #0
  23246. 800a90e: f8a0 305e strh.w r3, [r0, #94] @ 0x5e
  23247. huart->TxXferCount = 0U;
  23248. 800a912: f8a0 3056 strh.w r3, [r0, #86] @ 0x56
  23249. HAL_UART_ErrorCallback(huart);
  23250. 800a916: f7ff fff5 bl 800a904 <HAL_UART_ErrorCallback>
  23251. }
  23252. 800a91a: bd08 pop {r3, pc}
  23253. 0800a91c <HAL_UART_IRQHandler>:
  23254. uint32_t isrflags = READ_REG(huart->Instance->ISR);
  23255. 800a91c: 6803 ldr r3, [r0, #0]
  23256. errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
  23257. 800a91e: f640 0c0f movw ip, #2063 @ 0x80f
  23258. uint32_t isrflags = READ_REG(huart->Instance->ISR);
  23259. 800a922: 69da ldr r2, [r3, #28]
  23260. uint32_t cr1its = READ_REG(huart->Instance->CR1);
  23261. 800a924: 6819 ldr r1, [r3, #0]
  23262. if (errorflags == 0U)
  23263. 800a926: ea12 0f0c tst.w r2, ip
  23264. {
  23265. 800a92a: b570 push {r4, r5, r6, lr}
  23266. 800a92c: 4604 mov r4, r0
  23267. uint32_t cr3its = READ_REG(huart->Instance->CR3);
  23268. 800a92e: 689d ldr r5, [r3, #8]
  23269. if (errorflags == 0U)
  23270. 800a930: d145 bne.n 800a9be <HAL_UART_IRQHandler+0xa2>
  23271. if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
  23272. 800a932: 0696 lsls r6, r2, #26
  23273. 800a934: d507 bpl.n 800a946 <HAL_UART_IRQHandler+0x2a>
  23274. && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
  23275. 800a936: f001 0c20 and.w ip, r1, #32
  23276. || ((cr3its & USART_CR3_RXFTIE) != 0U)))
  23277. 800a93a: f005 5e80 and.w lr, r5, #268435456 @ 0x10000000
  23278. 800a93e: ea5c 0c0e orrs.w ip, ip, lr
  23279. 800a942: f040 813a bne.w 800abba <HAL_UART_IRQHandler+0x29e>
  23280. if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
  23281. 800a946: 6ee0 ldr r0, [r4, #108] @ 0x6c
  23282. 800a948: 2801 cmp r0, #1
  23283. 800a94a: f000 80d6 beq.w 800aafa <HAL_UART_IRQHandler+0x1de>
  23284. if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
  23285. 800a94e: 02d6 lsls r6, r2, #11
  23286. 800a950: d41d bmi.n 800a98e <HAL_UART_IRQHandler+0x72>
  23287. if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
  23288. 800a952: 0616 lsls r6, r2, #24
  23289. 800a954: d506 bpl.n 800a964 <HAL_UART_IRQHandler+0x48>
  23290. || ((cr3its & USART_CR3_TXFTIE) != 0U)))
  23291. 800a956: f405 0500 and.w r5, r5, #8388608 @ 0x800000
  23292. && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
  23293. 800a95a: f001 0080 and.w r0, r1, #128 @ 0x80
  23294. || ((cr3its & USART_CR3_TXFTIE) != 0U)))
  23295. 800a95e: 4328 orrs r0, r5
  23296. 800a960: f040 8132 bne.w 800abc8 <HAL_UART_IRQHandler+0x2ac>
  23297. if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
  23298. 800a964: 0650 lsls r0, r2, #25
  23299. 800a966: d51c bpl.n 800a9a2 <HAL_UART_IRQHandler+0x86>
  23300. 800a968: 064e lsls r6, r1, #25
  23301. 800a96a: d51a bpl.n 800a9a2 <HAL_UART_IRQHandler+0x86>
  23302. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23303. 800a96c: e853 2f00 ldrex r2, [r3]
  23304. * @retval None
  23305. */
  23306. static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
  23307. {
  23308. /* Disable the UART Transmit Complete Interrupt */
  23309. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
  23310. 800a970: f022 0240 bic.w r2, r2, #64 @ 0x40
  23311. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23312. 800a974: e843 2100 strex r1, r2, [r3]
  23313. 800a978: 2900 cmp r1, #0
  23314. 800a97a: d1f7 bne.n 800a96c <HAL_UART_IRQHandler+0x50>
  23315. /* Tx process is ended, restore huart->gState to Ready */
  23316. huart->gState = HAL_UART_STATE_READY;
  23317. 800a97c: 2220 movs r2, #32
  23318. /* Cleat TxISR function pointer */
  23319. huart->TxISR = NULL;
  23320. 800a97e: 2300 movs r3, #0
  23321. #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  23322. /*Call registered Tx complete callback*/
  23323. huart->TxCpltCallback(huart);
  23324. #else
  23325. /*Call legacy weak Tx complete callback*/
  23326. HAL_UART_TxCpltCallback(huart);
  23327. 800a980: 4620 mov r0, r4
  23328. huart->gState = HAL_UART_STATE_READY;
  23329. 800a982: f8c4 2088 str.w r2, [r4, #136] @ 0x88
  23330. huart->TxISR = NULL;
  23331. 800a986: 67a3 str r3, [r4, #120] @ 0x78
  23332. HAL_UART_TxCpltCallback(huart);
  23333. 800a988: f7f9 fa6c bl 8003e64 <HAL_UART_TxCpltCallback>
  23334. }
  23335. 800a98c: bd70 pop {r4, r5, r6, pc}
  23336. if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
  23337. 800a98e: 0268 lsls r0, r5, #9
  23338. 800a990: d5df bpl.n 800a952 <HAL_UART_IRQHandler+0x36>
  23339. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
  23340. 800a992: f44f 1280 mov.w r2, #1048576 @ 0x100000
  23341. HAL_UARTEx_WakeupCallback(huart);
  23342. 800a996: 4620 mov r0, r4
  23343. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
  23344. 800a998: 621a str r2, [r3, #32]
  23345. }
  23346. 800a99a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  23347. HAL_UARTEx_WakeupCallback(huart);
  23348. 800a99e: f001 b815 b.w 800b9cc <HAL_UARTEx_WakeupCallback>
  23349. if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
  23350. 800a9a2: 0215 lsls r5, r2, #8
  23351. 800a9a4: d502 bpl.n 800a9ac <HAL_UART_IRQHandler+0x90>
  23352. 800a9a6: 0048 lsls r0, r1, #1
  23353. 800a9a8: f100 8134 bmi.w 800ac14 <HAL_UART_IRQHandler+0x2f8>
  23354. if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
  23355. 800a9ac: 01d3 lsls r3, r2, #7
  23356. 800a9ae: d5ed bpl.n 800a98c <HAL_UART_IRQHandler+0x70>
  23357. 800a9b0: 2900 cmp r1, #0
  23358. 800a9b2: daeb bge.n 800a98c <HAL_UART_IRQHandler+0x70>
  23359. HAL_UARTEx_RxFifoFullCallback(huart);
  23360. 800a9b4: 4620 mov r0, r4
  23361. }
  23362. 800a9b6: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  23363. HAL_UARTEx_RxFifoFullCallback(huart);
  23364. 800a9ba: f001 b809 b.w 800b9d0 <HAL_UARTEx_RxFifoFullCallback>
  23365. && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
  23366. 800a9be: 48b6 ldr r0, [pc, #728] @ (800ac98 <HAL_UART_IRQHandler+0x37c>)
  23367. 800a9c0: ea05 0c00 and.w ip, r5, r0
  23368. || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
  23369. 800a9c4: 48b5 ldr r0, [pc, #724] @ (800ac9c <HAL_UART_IRQHandler+0x380>)
  23370. 800a9c6: 4008 ands r0, r1
  23371. 800a9c8: ea50 000c orrs.w r0, r0, ip
  23372. 800a9cc: d0bb beq.n 800a946 <HAL_UART_IRQHandler+0x2a>
  23373. if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
  23374. 800a9ce: 07d6 lsls r6, r2, #31
  23375. 800a9d0: d509 bpl.n 800a9e6 <HAL_UART_IRQHandler+0xca>
  23376. 800a9d2: 05c8 lsls r0, r1, #23
  23377. 800a9d4: d507 bpl.n 800a9e6 <HAL_UART_IRQHandler+0xca>
  23378. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
  23379. 800a9d6: 2001 movs r0, #1
  23380. 800a9d8: 6218 str r0, [r3, #32]
  23381. huart->ErrorCode |= HAL_UART_ERROR_PE;
  23382. 800a9da: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90
  23383. 800a9de: f040 0001 orr.w r0, r0, #1
  23384. 800a9e2: f8c4 0090 str.w r0, [r4, #144] @ 0x90
  23385. if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  23386. 800a9e6: 0796 lsls r6, r2, #30
  23387. if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  23388. 800a9e8: f002 0004 and.w r0, r2, #4
  23389. if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  23390. 800a9ec: f140 80de bpl.w 800abac <HAL_UART_IRQHandler+0x290>
  23391. 800a9f0: 07ee lsls r6, r5, #31
  23392. 800a9f2: d510 bpl.n 800aa16 <HAL_UART_IRQHandler+0xfa>
  23393. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
  23394. 800a9f4: 2602 movs r6, #2
  23395. 800a9f6: 621e str r6, [r3, #32]
  23396. huart->ErrorCode |= HAL_UART_ERROR_FE;
  23397. 800a9f8: f8d4 6090 ldr.w r6, [r4, #144] @ 0x90
  23398. 800a9fc: f046 0604 orr.w r6, r6, #4
  23399. 800aa00: f8c4 6090 str.w r6, [r4, #144] @ 0x90
  23400. if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  23401. 800aa04: b138 cbz r0, 800aa16 <HAL_UART_IRQHandler+0xfa>
  23402. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
  23403. 800aa06: 2004 movs r0, #4
  23404. 800aa08: 6218 str r0, [r3, #32]
  23405. huart->ErrorCode |= HAL_UART_ERROR_NE;
  23406. 800aa0a: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90
  23407. 800aa0e: f040 0002 orr.w r0, r0, #2
  23408. 800aa12: f8c4 0090 str.w r0, [r4, #144] @ 0x90
  23409. if (((isrflags & USART_ISR_ORE) != 0U)
  23410. 800aa16: 0716 lsls r6, r2, #28
  23411. 800aa18: d50c bpl.n 800aa34 <HAL_UART_IRQHandler+0x118>
  23412. && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
  23413. 800aa1a: f001 0020 and.w r0, r1, #32
  23414. 800aa1e: ea50 000c orrs.w r0, r0, ip
  23415. 800aa22: d007 beq.n 800aa34 <HAL_UART_IRQHandler+0x118>
  23416. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
  23417. 800aa24: 2008 movs r0, #8
  23418. 800aa26: 6218 str r0, [r3, #32]
  23419. huart->ErrorCode |= HAL_UART_ERROR_ORE;
  23420. 800aa28: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90
  23421. 800aa2c: f040 0008 orr.w r0, r0, #8
  23422. 800aa30: f8c4 0090 str.w r0, [r4, #144] @ 0x90
  23423. if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
  23424. 800aa34: 0510 lsls r0, r2, #20
  23425. 800aa36: d50a bpl.n 800aa4e <HAL_UART_IRQHandler+0x132>
  23426. 800aa38: 014e lsls r6, r1, #5
  23427. 800aa3a: d508 bpl.n 800aa4e <HAL_UART_IRQHandler+0x132>
  23428. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
  23429. 800aa3c: f44f 6000 mov.w r0, #2048 @ 0x800
  23430. 800aa40: 6218 str r0, [r3, #32]
  23431. huart->ErrorCode |= HAL_UART_ERROR_RTO;
  23432. 800aa42: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90
  23433. 800aa46: f040 0020 orr.w r0, r0, #32
  23434. 800aa4a: f8c4 0090 str.w r0, [r4, #144] @ 0x90
  23435. if (huart->ErrorCode != HAL_UART_ERROR_NONE)
  23436. 800aa4e: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90
  23437. 800aa52: 2800 cmp r0, #0
  23438. 800aa54: d09a beq.n 800a98c <HAL_UART_IRQHandler+0x70>
  23439. if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
  23440. 800aa56: 0690 lsls r0, r2, #26
  23441. 800aa58: d506 bpl.n 800aa68 <HAL_UART_IRQHandler+0x14c>
  23442. && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
  23443. 800aa5a: f001 0120 and.w r1, r1, #32
  23444. || ((cr3its & USART_CR3_RXFTIE) != 0U)))
  23445. 800aa5e: f005 5580 and.w r5, r5, #268435456 @ 0x10000000
  23446. 800aa62: 4329 orrs r1, r5
  23447. 800aa64: f040 80ca bne.w 800abfc <HAL_UART_IRQHandler+0x2e0>
  23448. errorcode = huart->ErrorCode;
  23449. 800aa68: f8d4 1090 ldr.w r1, [r4, #144] @ 0x90
  23450. if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
  23451. 800aa6c: 689a ldr r2, [r3, #8]
  23452. ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
  23453. 800aa6e: f001 0128 and.w r1, r1, #40 @ 0x28
  23454. if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
  23455. 800aa72: f002 0240 and.w r2, r2, #64 @ 0x40
  23456. 800aa76: ea52 0501 orrs.w r5, r2, r1
  23457. 800aa7a: f000 80d0 beq.w 800ac1e <HAL_UART_IRQHandler+0x302>
  23458. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23459. 800aa7e: e853 2f00 ldrex r2, [r3]
  23460. ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
  23461. 800aa82: f422 7290 bic.w r2, r2, #288 @ 0x120
  23462. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23463. 800aa86: e843 2100 strex r1, r2, [r3]
  23464. 800aa8a: 2900 cmp r1, #0
  23465. 800aa8c: d1f7 bne.n 800aa7e <HAL_UART_IRQHandler+0x162>
  23466. ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
  23467. 800aa8e: 4884 ldr r0, [pc, #528] @ (800aca0 <HAL_UART_IRQHandler+0x384>)
  23468. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23469. 800aa90: f103 0208 add.w r2, r3, #8
  23470. 800aa94: e852 2f00 ldrex r2, [r2]
  23471. 800aa98: 4002 ands r2, r0
  23472. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23473. 800aa9a: f103 0508 add.w r5, r3, #8
  23474. 800aa9e: e845 2100 strex r1, r2, [r5]
  23475. 800aaa2: 2900 cmp r1, #0
  23476. 800aaa4: d1f4 bne.n 800aa90 <HAL_UART_IRQHandler+0x174>
  23477. if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
  23478. 800aaa6: 6ee2 ldr r2, [r4, #108] @ 0x6c
  23479. 800aaa8: 2a01 cmp r2, #1
  23480. 800aaaa: f000 8095 beq.w 800abd8 <HAL_UART_IRQHandler+0x2bc>
  23481. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  23482. 800aaae: 2200 movs r2, #0
  23483. huart->RxState = HAL_UART_STATE_READY;
  23484. 800aab0: 2120 movs r1, #32
  23485. 800aab2: f8c4 108c str.w r1, [r4, #140] @ 0x8c
  23486. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  23487. 800aab6: 66e2 str r2, [r4, #108] @ 0x6c
  23488. if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
  23489. 800aab8: 6899 ldr r1, [r3, #8]
  23490. huart->RxISR = NULL;
  23491. 800aaba: 6762 str r2, [r4, #116] @ 0x74
  23492. if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
  23493. 800aabc: 064a lsls r2, r1, #25
  23494. 800aabe: f140 80a5 bpl.w 800ac0c <HAL_UART_IRQHandler+0x2f0>
  23495. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23496. 800aac2: f103 0208 add.w r2, r3, #8
  23497. 800aac6: e852 2f00 ldrex r2, [r2]
  23498. ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
  23499. 800aaca: f022 0240 bic.w r2, r2, #64 @ 0x40
  23500. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23501. 800aace: f103 0008 add.w r0, r3, #8
  23502. 800aad2: e840 2100 strex r1, r2, [r0]
  23503. 800aad6: 2900 cmp r1, #0
  23504. 800aad8: d1f3 bne.n 800aac2 <HAL_UART_IRQHandler+0x1a6>
  23505. if (huart->hdmarx != NULL)
  23506. 800aada: f8d4 0080 ldr.w r0, [r4, #128] @ 0x80
  23507. 800aade: 2800 cmp r0, #0
  23508. 800aae0: f000 8094 beq.w 800ac0c <HAL_UART_IRQHandler+0x2f0>
  23509. huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
  23510. 800aae4: 4b6f ldr r3, [pc, #444] @ (800aca4 <HAL_UART_IRQHandler+0x388>)
  23511. 800aae6: 6503 str r3, [r0, #80] @ 0x50
  23512. if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
  23513. 800aae8: f7fb fe24 bl 8006734 <HAL_DMA_Abort_IT>
  23514. 800aaec: 2800 cmp r0, #0
  23515. 800aaee: f43f af4d beq.w 800a98c <HAL_UART_IRQHandler+0x70>
  23516. huart->hdmarx->XferAbortCallback(huart->hdmarx);
  23517. 800aaf2: f8d4 0080 ldr.w r0, [r4, #128] @ 0x80
  23518. 800aaf6: 6d03 ldr r3, [r0, #80] @ 0x50
  23519. 800aaf8: e063 b.n 800abc2 <HAL_UART_IRQHandler+0x2a6>
  23520. && ((isrflags & USART_ISR_IDLE) != 0U)
  23521. 800aafa: 06d6 lsls r6, r2, #27
  23522. 800aafc: f57f af27 bpl.w 800a94e <HAL_UART_IRQHandler+0x32>
  23523. && ((cr1its & USART_ISR_IDLE) != 0U))
  23524. 800ab00: 06c8 lsls r0, r1, #27
  23525. 800ab02: f57f af24 bpl.w 800a94e <HAL_UART_IRQHandler+0x32>
  23526. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
  23527. 800ab06: 2210 movs r2, #16
  23528. 800ab08: 621a str r2, [r3, #32]
  23529. if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
  23530. 800ab0a: 689a ldr r2, [r3, #8]
  23531. 800ab0c: 0652 lsls r2, r2, #25
  23532. 800ab0e: f140 808c bpl.w 800ac2a <HAL_UART_IRQHandler+0x30e>
  23533. uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
  23534. 800ab12: f8d4 0080 ldr.w r0, [r4, #128] @ 0x80
  23535. 800ab16: 6801 ldr r1, [r0, #0]
  23536. 800ab18: 684a ldr r2, [r1, #4]
  23537. 800ab1a: b292 uxth r2, r2
  23538. if ((nb_remaining_rx_data > 0U)
  23539. 800ab1c: 2a00 cmp r2, #0
  23540. 800ab1e: f43f af35 beq.w 800a98c <HAL_UART_IRQHandler+0x70>
  23541. && (nb_remaining_rx_data < huart->RxXferSize))
  23542. 800ab22: f8b4 105c ldrh.w r1, [r4, #92] @ 0x5c
  23543. 800ab26: 4291 cmp r1, r2
  23544. 800ab28: f67f af30 bls.w 800a98c <HAL_UART_IRQHandler+0x70>
  23545. huart->RxXferCount = nb_remaining_rx_data;
  23546. 800ab2c: f8a4 205e strh.w r2, [r4, #94] @ 0x5e
  23547. if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
  23548. 800ab30: 69c2 ldr r2, [r0, #28]
  23549. 800ab32: f5b2 7f80 cmp.w r2, #256 @ 0x100
  23550. 800ab36: d02f beq.n 800ab98 <HAL_UART_IRQHandler+0x27c>
  23551. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23552. 800ab38: e853 2f00 ldrex r2, [r3]
  23553. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
  23554. 800ab3c: f422 7280 bic.w r2, r2, #256 @ 0x100
  23555. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23556. 800ab40: e843 2100 strex r1, r2, [r3]
  23557. 800ab44: 2900 cmp r1, #0
  23558. 800ab46: d1f7 bne.n 800ab38 <HAL_UART_IRQHandler+0x21c>
  23559. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23560. 800ab48: f103 0208 add.w r2, r3, #8
  23561. 800ab4c: e852 2f00 ldrex r2, [r2]
  23562. ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
  23563. 800ab50: f022 0201 bic.w r2, r2, #1
  23564. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23565. 800ab54: f103 0508 add.w r5, r3, #8
  23566. 800ab58: e845 2100 strex r1, r2, [r5]
  23567. 800ab5c: 2900 cmp r1, #0
  23568. 800ab5e: d1f3 bne.n 800ab48 <HAL_UART_IRQHandler+0x22c>
  23569. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23570. 800ab60: f103 0208 add.w r2, r3, #8
  23571. 800ab64: e852 2f00 ldrex r2, [r2]
  23572. ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
  23573. 800ab68: f022 0240 bic.w r2, r2, #64 @ 0x40
  23574. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23575. 800ab6c: f103 0508 add.w r5, r3, #8
  23576. 800ab70: e845 2100 strex r1, r2, [r5]
  23577. 800ab74: 2900 cmp r1, #0
  23578. 800ab76: d1f3 bne.n 800ab60 <HAL_UART_IRQHandler+0x244>
  23579. huart->RxState = HAL_UART_STATE_READY;
  23580. 800ab78: 2220 movs r2, #32
  23581. 800ab7a: f8c4 208c str.w r2, [r4, #140] @ 0x8c
  23582. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  23583. 800ab7e: 66e1 str r1, [r4, #108] @ 0x6c
  23584. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23585. 800ab80: e853 2f00 ldrex r2, [r3]
  23586. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  23587. 800ab84: f022 0210 bic.w r2, r2, #16
  23588. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23589. 800ab88: e843 2100 strex r1, r2, [r3]
  23590. 800ab8c: 2900 cmp r1, #0
  23591. 800ab8e: d1f7 bne.n 800ab80 <HAL_UART_IRQHandler+0x264>
  23592. (void)HAL_DMA_Abort(huart->hdmarx);
  23593. 800ab90: f7fb fc1e bl 80063d0 <HAL_DMA_Abort>
  23594. HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
  23595. 800ab94: f8b4 105c ldrh.w r1, [r4, #92] @ 0x5c
  23596. huart->RxEventType = HAL_UART_RXEVENT_IDLE;
  23597. 800ab98: 2302 movs r3, #2
  23598. HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
  23599. 800ab9a: 4620 mov r0, r4
  23600. huart->RxEventType = HAL_UART_RXEVENT_IDLE;
  23601. 800ab9c: 6723 str r3, [r4, #112] @ 0x70
  23602. HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
  23603. 800ab9e: f8b4 305e ldrh.w r3, [r4, #94] @ 0x5e
  23604. 800aba2: 1ac9 subs r1, r1, r3
  23605. 800aba4: b289 uxth r1, r1
  23606. 800aba6: f7f9 f993 bl 8003ed0 <HAL_UARTEx_RxEventCallback>
  23607. }
  23608. 800abaa: bd70 pop {r4, r5, r6, pc}
  23609. if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  23610. 800abac: 2800 cmp r0, #0
  23611. 800abae: f43f af32 beq.w 800aa16 <HAL_UART_IRQHandler+0xfa>
  23612. 800abb2: 07e8 lsls r0, r5, #31
  23613. 800abb4: f53f af27 bmi.w 800aa06 <HAL_UART_IRQHandler+0xea>
  23614. 800abb8: e72d b.n 800aa16 <HAL_UART_IRQHandler+0xfa>
  23615. if (huart->RxISR != NULL)
  23616. 800abba: 6f43 ldr r3, [r0, #116] @ 0x74
  23617. 800abbc: 2b00 cmp r3, #0
  23618. 800abbe: f43f aee5 beq.w 800a98c <HAL_UART_IRQHandler+0x70>
  23619. }
  23620. 800abc2: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  23621. huart->hdmarx->XferAbortCallback(huart->hdmarx);
  23622. 800abc6: 4718 bx r3
  23623. if (huart->TxISR != NULL)
  23624. 800abc8: 6fa3 ldr r3, [r4, #120] @ 0x78
  23625. 800abca: 2b00 cmp r3, #0
  23626. 800abcc: f43f aede beq.w 800a98c <HAL_UART_IRQHandler+0x70>
  23627. huart->TxISR(huart);
  23628. 800abd0: 4620 mov r0, r4
  23629. }
  23630. 800abd2: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  23631. huart->TxISR(huart);
  23632. 800abd6: 4718 bx r3
  23633. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23634. 800abd8: e853 2f00 ldrex r2, [r3]
  23635. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  23636. 800abdc: f022 0210 bic.w r2, r2, #16
  23637. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23638. 800abe0: e843 2100 strex r1, r2, [r3]
  23639. 800abe4: 2900 cmp r1, #0
  23640. 800abe6: f43f af62 beq.w 800aaae <HAL_UART_IRQHandler+0x192>
  23641. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23642. 800abea: e853 2f00 ldrex r2, [r3]
  23643. 800abee: f022 0210 bic.w r2, r2, #16
  23644. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23645. 800abf2: e843 2100 strex r1, r2, [r3]
  23646. 800abf6: 2900 cmp r1, #0
  23647. 800abf8: d1ee bne.n 800abd8 <HAL_UART_IRQHandler+0x2bc>
  23648. 800abfa: e758 b.n 800aaae <HAL_UART_IRQHandler+0x192>
  23649. if (huart->RxISR != NULL)
  23650. 800abfc: 6f62 ldr r2, [r4, #116] @ 0x74
  23651. 800abfe: 2a00 cmp r2, #0
  23652. 800ac00: f43f af32 beq.w 800aa68 <HAL_UART_IRQHandler+0x14c>
  23653. huart->RxISR(huart);
  23654. 800ac04: 4620 mov r0, r4
  23655. 800ac06: 4790 blx r2
  23656. if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
  23657. 800ac08: 6823 ldr r3, [r4, #0]
  23658. 800ac0a: e72d b.n 800aa68 <HAL_UART_IRQHandler+0x14c>
  23659. HAL_UART_ErrorCallback(huart);
  23660. 800ac0c: 4620 mov r0, r4
  23661. 800ac0e: f7ff fe79 bl 800a904 <HAL_UART_ErrorCallback>
  23662. }
  23663. 800ac12: bd70 pop {r4, r5, r6, pc}
  23664. HAL_UARTEx_TxFifoEmptyCallback(huart);
  23665. 800ac14: 4620 mov r0, r4
  23666. }
  23667. 800ac16: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  23668. HAL_UARTEx_TxFifoEmptyCallback(huart);
  23669. 800ac1a: f000 bedb b.w 800b9d4 <HAL_UARTEx_TxFifoEmptyCallback>
  23670. HAL_UART_ErrorCallback(huart);
  23671. 800ac1e: 4620 mov r0, r4
  23672. 800ac20: f7ff fe70 bl 800a904 <HAL_UART_ErrorCallback>
  23673. huart->ErrorCode = HAL_UART_ERROR_NONE;
  23674. 800ac24: f8c4 5090 str.w r5, [r4, #144] @ 0x90
  23675. }
  23676. 800ac28: bd70 pop {r4, r5, r6, pc}
  23677. uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
  23678. 800ac2a: f8b4 005e ldrh.w r0, [r4, #94] @ 0x5e
  23679. 800ac2e: f8b4 105c ldrh.w r1, [r4, #92] @ 0x5c
  23680. if ((huart->RxXferCount > 0U)
  23681. 800ac32: f8b4 205e ldrh.w r2, [r4, #94] @ 0x5e
  23682. uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
  23683. 800ac36: 1a09 subs r1, r1, r0
  23684. if ((huart->RxXferCount > 0U)
  23685. 800ac38: b292 uxth r2, r2
  23686. uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
  23687. 800ac3a: b289 uxth r1, r1
  23688. && (nb_rx_data > 0U))
  23689. 800ac3c: 2a00 cmp r2, #0
  23690. 800ac3e: f43f aea5 beq.w 800a98c <HAL_UART_IRQHandler+0x70>
  23691. 800ac42: 2900 cmp r1, #0
  23692. 800ac44: f43f aea2 beq.w 800a98c <HAL_UART_IRQHandler+0x70>
  23693. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23694. 800ac48: e853 2f00 ldrex r2, [r3]
  23695. ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
  23696. 800ac4c: f422 7290 bic.w r2, r2, #288 @ 0x120
  23697. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23698. 800ac50: e843 2000 strex r0, r2, [r3]
  23699. 800ac54: 2800 cmp r0, #0
  23700. 800ac56: d1f7 bne.n 800ac48 <HAL_UART_IRQHandler+0x32c>
  23701. ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
  23702. 800ac58: 4d11 ldr r5, [pc, #68] @ (800aca0 <HAL_UART_IRQHandler+0x384>)
  23703. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23704. 800ac5a: f103 0208 add.w r2, r3, #8
  23705. 800ac5e: e852 2f00 ldrex r2, [r2]
  23706. 800ac62: 402a ands r2, r5
  23707. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23708. 800ac64: f103 0608 add.w r6, r3, #8
  23709. 800ac68: e846 2000 strex r0, r2, [r6]
  23710. 800ac6c: 2800 cmp r0, #0
  23711. 800ac6e: d1f4 bne.n 800ac5a <HAL_UART_IRQHandler+0x33e>
  23712. huart->RxState = HAL_UART_STATE_READY;
  23713. 800ac70: 2220 movs r2, #32
  23714. huart->RxISR = NULL;
  23715. 800ac72: 6760 str r0, [r4, #116] @ 0x74
  23716. huart->RxState = HAL_UART_STATE_READY;
  23717. 800ac74: f8c4 208c str.w r2, [r4, #140] @ 0x8c
  23718. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  23719. 800ac78: 66e0 str r0, [r4, #108] @ 0x6c
  23720. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23721. 800ac7a: e853 2f00 ldrex r2, [r3]
  23722. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  23723. 800ac7e: f022 0210 bic.w r2, r2, #16
  23724. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23725. 800ac82: e843 2000 strex r0, r2, [r3]
  23726. 800ac86: 2800 cmp r0, #0
  23727. 800ac88: d1f7 bne.n 800ac7a <HAL_UART_IRQHandler+0x35e>
  23728. huart->RxEventType = HAL_UART_RXEVENT_IDLE;
  23729. 800ac8a: 2302 movs r3, #2
  23730. HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
  23731. 800ac8c: 4620 mov r0, r4
  23732. huart->RxEventType = HAL_UART_RXEVENT_IDLE;
  23733. 800ac8e: 6723 str r3, [r4, #112] @ 0x70
  23734. HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
  23735. 800ac90: f7f9 f91e bl 8003ed0 <HAL_UARTEx_RxEventCallback>
  23736. }
  23737. 800ac94: bd70 pop {r4, r5, r6, pc}
  23738. 800ac96: bf00 nop
  23739. 800ac98: 10000001 .word 0x10000001
  23740. 800ac9c: 04000120 .word 0x04000120
  23741. 800aca0: effffffe .word 0xeffffffe
  23742. 800aca4: 0800a909 .word 0x0800a909
  23743. 0800aca8 <UART_RxISR_16BIT.part.0>:
  23744. /**
  23745. * @brief RX interrupt handler for 7 or 8 bits data word length .
  23746. * @param huart UART handle.
  23747. * @retval None
  23748. */
  23749. static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
  23750. 800aca8: 6803 ldr r3, [r0, #0]
  23751. 800acaa: b510 push {r4, lr}
  23752. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23753. 800acac: e853 2f00 ldrex r2, [r3]
  23754. huart->RxXferCount--;
  23755. if (huart->RxXferCount == 0U)
  23756. {
  23757. /* Disable the UART Parity Error Interrupt and RXNE interrupts */
  23758. ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
  23759. 800acb0: f422 7290 bic.w r2, r2, #288 @ 0x120
  23760. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23761. 800acb4: e843 2100 strex r1, r2, [r3]
  23762. 800acb8: 2900 cmp r1, #0
  23763. 800acba: d1f7 bne.n 800acac <UART_RxISR_16BIT.part.0+0x4>
  23764. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23765. 800acbc: f103 0208 add.w r2, r3, #8
  23766. 800acc0: e852 2f00 ldrex r2, [r2]
  23767. /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
  23768. ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
  23769. 800acc4: f022 0201 bic.w r2, r2, #1
  23770. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23771. 800acc8: f103 0408 add.w r4, r3, #8
  23772. 800accc: e844 2100 strex r1, r2, [r4]
  23773. 800acd0: 2900 cmp r1, #0
  23774. 800acd2: d1f3 bne.n 800acbc <UART_RxISR_16BIT.part.0+0x14>
  23775. huart->RxISR = NULL;
  23776. /* Initialize type of RxEvent to Transfer Complete */
  23777. huart->RxEventType = HAL_UART_RXEVENT_TC;
  23778. if (!(IS_LPUART_INSTANCE(huart->Instance)))
  23779. 800acd4: 4a1a ldr r2, [pc, #104] @ (800ad40 <UART_RxISR_16BIT.part.0+0x98>)
  23780. huart->RxState = HAL_UART_STATE_READY;
  23781. 800acd6: 2420 movs r4, #32
  23782. huart->RxISR = NULL;
  23783. 800acd8: 6741 str r1, [r0, #116] @ 0x74
  23784. if (!(IS_LPUART_INSTANCE(huart->Instance)))
  23785. 800acda: 4293 cmp r3, r2
  23786. huart->RxState = HAL_UART_STATE_READY;
  23787. 800acdc: f8c0 408c str.w r4, [r0, #140] @ 0x8c
  23788. huart->RxEventType = HAL_UART_RXEVENT_TC;
  23789. 800ace0: 6701 str r1, [r0, #112] @ 0x70
  23790. if (!(IS_LPUART_INSTANCE(huart->Instance)))
  23791. 800ace2: d002 beq.n 800acea <UART_RxISR_16BIT.part.0+0x42>
  23792. {
  23793. /* Check that USART RTOEN bit is set */
  23794. if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
  23795. 800ace4: 685a ldr r2, [r3, #4]
  23796. 800ace6: 0211 lsls r1, r2, #8
  23797. 800ace8: d416 bmi.n 800ad18 <UART_RxISR_16BIT.part.0+0x70>
  23798. }
  23799. }
  23800. /* Check current reception Mode :
  23801. If Reception till IDLE event has been selected : */
  23802. if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
  23803. 800acea: 6ec2 ldr r2, [r0, #108] @ 0x6c
  23804. 800acec: 2a01 cmp r2, #1
  23805. 800acee: d124 bne.n 800ad3a <UART_RxISR_16BIT.part.0+0x92>
  23806. {
  23807. /* Set reception type to Standard */
  23808. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  23809. 800acf0: 2200 movs r2, #0
  23810. 800acf2: 66c2 str r2, [r0, #108] @ 0x6c
  23811. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23812. 800acf4: e853 2f00 ldrex r2, [r3]
  23813. /* Disable IDLE interrupt */
  23814. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  23815. 800acf8: f022 0210 bic.w r2, r2, #16
  23816. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23817. 800acfc: e843 2100 strex r1, r2, [r3]
  23818. 800ad00: 2900 cmp r1, #0
  23819. 800ad02: d1f7 bne.n 800acf4 <UART_RxISR_16BIT.part.0+0x4c>
  23820. if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
  23821. 800ad04: 69da ldr r2, [r3, #28]
  23822. 800ad06: 06d2 lsls r2, r2, #27
  23823. 800ad08: d501 bpl.n 800ad0e <UART_RxISR_16BIT.part.0+0x66>
  23824. {
  23825. /* Clear IDLE Flag */
  23826. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
  23827. 800ad0a: 2210 movs r2, #16
  23828. 800ad0c: 621a str r2, [r3, #32]
  23829. #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  23830. /*Call registered Rx Event callback*/
  23831. huart->RxEventCallback(huart, huart->RxXferSize);
  23832. #else
  23833. /*Call legacy weak Rx Event callback*/
  23834. HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
  23835. 800ad0e: f8b0 105c ldrh.w r1, [r0, #92] @ 0x5c
  23836. 800ad12: f7f9 f8dd bl 8003ed0 <HAL_UARTEx_RxEventCallback>
  23837. else
  23838. {
  23839. /* Clear RXNE interrupt flag */
  23840. __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  23841. }
  23842. }
  23843. 800ad16: bd10 pop {r4, pc}
  23844. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23845. 800ad18: e853 2f00 ldrex r2, [r3]
  23846. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
  23847. 800ad1c: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000
  23848. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23849. 800ad20: e843 2100 strex r1, r2, [r3]
  23850. 800ad24: 2900 cmp r1, #0
  23851. 800ad26: d0e0 beq.n 800acea <UART_RxISR_16BIT.part.0+0x42>
  23852. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  23853. 800ad28: e853 2f00 ldrex r2, [r3]
  23854. 800ad2c: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000
  23855. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  23856. 800ad30: e843 2100 strex r1, r2, [r3]
  23857. 800ad34: 2900 cmp r1, #0
  23858. 800ad36: d1ef bne.n 800ad18 <UART_RxISR_16BIT.part.0+0x70>
  23859. 800ad38: e7d7 b.n 800acea <UART_RxISR_16BIT.part.0+0x42>
  23860. HAL_UART_RxCpltCallback(huart);
  23861. 800ad3a: f7f9 f891 bl 8003e60 <HAL_UART_RxCpltCallback>
  23862. }
  23863. 800ad3e: bd10 pop {r4, pc}
  23864. 800ad40: 58000c00 .word 0x58000c00
  23865. 0800ad44 <UART_RxISR_16BIT>:
  23866. * interruptions have been enabled by HAL_UART_Receive_IT()
  23867. * @param huart UART handle.
  23868. * @retval None
  23869. */
  23870. static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
  23871. {
  23872. 800ad44: b410 push {r4}
  23873. uint16_t *tmp;
  23874. uint16_t uhMask = huart->Mask;
  23875. uint16_t uhdata;
  23876. /* Check that a Rx process is ongoing */
  23877. if (huart->RxState == HAL_UART_STATE_BUSY_RX)
  23878. 800ad46: f8d0 408c ldr.w r4, [r0, #140] @ 0x8c
  23879. uint16_t uhMask = huart->Mask;
  23880. 800ad4a: f8b0 1060 ldrh.w r1, [r0, #96] @ 0x60
  23881. if (huart->RxState == HAL_UART_STATE_BUSY_RX)
  23882. 800ad4e: 2c22 cmp r4, #34 @ 0x22
  23883. {
  23884. uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
  23885. 800ad50: 6802 ldr r2, [r0, #0]
  23886. if (huart->RxState == HAL_UART_STATE_BUSY_RX)
  23887. 800ad52: d006 beq.n 800ad62 <UART_RxISR_16BIT+0x1e>
  23888. }
  23889. }
  23890. else
  23891. {
  23892. /* Clear RXNE interrupt flag */
  23893. __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  23894. 800ad54: 6993 ldr r3, [r2, #24]
  23895. 800ad56: f043 0308 orr.w r3, r3, #8
  23896. 800ad5a: 6193 str r3, [r2, #24]
  23897. }
  23898. }
  23899. 800ad5c: f85d 4b04 ldr.w r4, [sp], #4
  23900. 800ad60: 4770 bx lr
  23901. uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
  23902. 800ad62: 6a52 ldr r2, [r2, #36] @ 0x24
  23903. *tmp = (uint16_t)(uhdata & uhMask);
  23904. 800ad64: 6d84 ldr r4, [r0, #88] @ 0x58
  23905. 800ad66: 4011 ands r1, r2
  23906. 800ad68: f824 1b02 strh.w r1, [r4], #2
  23907. huart->RxXferCount--;
  23908. 800ad6c: f8b0 205e ldrh.w r2, [r0, #94] @ 0x5e
  23909. huart->pRxBuffPtr += 2U;
  23910. 800ad70: 6584 str r4, [r0, #88] @ 0x58
  23911. huart->RxXferCount--;
  23912. 800ad72: 3a01 subs r2, #1
  23913. 800ad74: b292 uxth r2, r2
  23914. 800ad76: f8a0 205e strh.w r2, [r0, #94] @ 0x5e
  23915. if (huart->RxXferCount == 0U)
  23916. 800ad7a: f8b0 305e ldrh.w r3, [r0, #94] @ 0x5e
  23917. 800ad7e: b29b uxth r3, r3
  23918. 800ad80: 2b00 cmp r3, #0
  23919. 800ad82: d1eb bne.n 800ad5c <UART_RxISR_16BIT+0x18>
  23920. }
  23921. 800ad84: f85d 4b04 ldr.w r4, [sp], #4
  23922. 800ad88: f7ff bf8e b.w 800aca8 <UART_RxISR_16BIT.part.0>
  23923. 0800ad8c <UART_RxISR_8BIT>:
  23924. if (huart->RxState == HAL_UART_STATE_BUSY_RX)
  23925. 800ad8c: f8d0 108c ldr.w r1, [r0, #140] @ 0x8c
  23926. uint16_t uhMask = huart->Mask;
  23927. 800ad90: f8b0 c060 ldrh.w ip, [r0, #96] @ 0x60
  23928. if (huart->RxState == HAL_UART_STATE_BUSY_RX)
  23929. 800ad94: 2922 cmp r1, #34 @ 0x22
  23930. uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
  23931. 800ad96: 6802 ldr r2, [r0, #0]
  23932. if (huart->RxState == HAL_UART_STATE_BUSY_RX)
  23933. 800ad98: d004 beq.n 800ada4 <UART_RxISR_8BIT+0x18>
  23934. __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  23935. 800ad9a: 6993 ldr r3, [r2, #24]
  23936. 800ad9c: f043 0308 orr.w r3, r3, #8
  23937. 800ada0: 6193 str r3, [r2, #24]
  23938. }
  23939. 800ada2: 4770 bx lr
  23940. uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
  23941. 800ada4: 6a52 ldr r2, [r2, #36] @ 0x24
  23942. *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
  23943. 800ada6: 6d81 ldr r1, [r0, #88] @ 0x58
  23944. 800ada8: ea02 020c and.w r2, r2, ip
  23945. 800adac: 700a strb r2, [r1, #0]
  23946. huart->RxXferCount--;
  23947. 800adae: f8b0 205e ldrh.w r2, [r0, #94] @ 0x5e
  23948. huart->pRxBuffPtr++;
  23949. 800adb2: 6d81 ldr r1, [r0, #88] @ 0x58
  23950. huart->RxXferCount--;
  23951. 800adb4: 3a01 subs r2, #1
  23952. huart->pRxBuffPtr++;
  23953. 800adb6: 3101 adds r1, #1
  23954. huart->RxXferCount--;
  23955. 800adb8: b292 uxth r2, r2
  23956. huart->pRxBuffPtr++;
  23957. 800adba: 6581 str r1, [r0, #88] @ 0x58
  23958. huart->RxXferCount--;
  23959. 800adbc: f8a0 205e strh.w r2, [r0, #94] @ 0x5e
  23960. if (huart->RxXferCount == 0U)
  23961. 800adc0: f8b0 305e ldrh.w r3, [r0, #94] @ 0x5e
  23962. 800adc4: b29b uxth r3, r3
  23963. 800adc6: 2b00 cmp r3, #0
  23964. 800adc8: d1eb bne.n 800ada2 <UART_RxISR_8BIT+0x16>
  23965. 800adca: f7ff bf6d b.w 800aca8 <UART_RxISR_16BIT.part.0>
  23966. 800adce: bf00 nop
  23967. 0800add0 <UART_RxISR_8BIT_FIFOEN>:
  23968. * interruptions have been enabled by HAL_UART_Receive_IT()
  23969. * @param huart UART handle.
  23970. * @retval None
  23971. */
  23972. static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
  23973. {
  23974. 800add0: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  23975. uint16_t uhMask = huart->Mask;
  23976. uint16_t uhdata;
  23977. uint16_t nb_rx_data;
  23978. uint16_t rxdatacount;
  23979. uint32_t isrflags = READ_REG(huart->Instance->ISR);
  23980. 800add4: 6802 ldr r2, [r0, #0]
  23981. {
  23982. 800add6: 4604 mov r4, r0
  23983. uint16_t uhMask = huart->Mask;
  23984. 800add8: f8b0 a060 ldrh.w sl, [r0, #96] @ 0x60
  23985. uint32_t isrflags = READ_REG(huart->Instance->ISR);
  23986. 800addc: 69d0 ldr r0, [r2, #28]
  23987. uint32_t cr1its = READ_REG(huart->Instance->CR1);
  23988. 800adde: 6816 ldr r6, [r2, #0]
  23989. uint32_t cr3its = READ_REG(huart->Instance->CR3);
  23990. 800ade0: 6895 ldr r5, [r2, #8]
  23991. /* Check that a Rx process is ongoing */
  23992. if (huart->RxState == HAL_UART_STATE_BUSY_RX)
  23993. 800ade2: f8d4 108c ldr.w r1, [r4, #140] @ 0x8c
  23994. 800ade6: 2922 cmp r1, #34 @ 0x22
  23995. 800ade8: d006 beq.n 800adf8 <UART_RxISR_8BIT_FIFOEN+0x28>
  23996. 800adea: 4613 mov r3, r2
  23997. }
  23998. }
  23999. else
  24000. {
  24001. /* Clear RXNE interrupt flag */
  24002. __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  24003. 800adec: 6992 ldr r2, [r2, #24]
  24004. 800adee: f042 0208 orr.w r2, r2, #8
  24005. 800adf2: 619a str r2, [r3, #24]
  24006. }
  24007. }
  24008. 800adf4: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
  24009. while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
  24010. 800adf8: f8b4 3068 ldrh.w r3, [r4, #104] @ 0x68
  24011. 800adfc: 2b00 cmp r3, #0
  24012. 800adfe: f000 80d4 beq.w 800afaa <UART_RxISR_8BIT_FIFOEN+0x1da>
  24013. 800ae02: 0680 lsls r0, r0, #26
  24014. 800ae04: f140 8088 bpl.w 800af18 <UART_RxISR_8BIT_FIFOEN+0x148>
  24015. if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
  24016. 800ae08: f406 7680 and.w r6, r6, #256 @ 0x100
  24017. if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  24018. 800ae0c: f005 0501 and.w r5, r5, #1
  24019. *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
  24020. 800ae10: fa5f fa8a uxtb.w sl, sl
  24021. huart->ErrorCode = HAL_UART_ERROR_NONE;
  24022. 800ae14: f04f 0800 mov.w r8, #0
  24023. ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
  24024. 800ae18: f8df 919c ldr.w r9, [pc, #412] @ 800afb8 <UART_RxISR_8BIT_FIFOEN+0x1e8>
  24025. if (!(IS_LPUART_INSTANCE(huart->Instance)))
  24026. 800ae1c: 4f64 ldr r7, [pc, #400] @ (800afb0 <UART_RxISR_8BIT_FIFOEN+0x1e0>)
  24027. uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
  24028. 800ae1e: 6a52 ldr r2, [r2, #36] @ 0x24
  24029. *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
  24030. 800ae20: 6da3 ldr r3, [r4, #88] @ 0x58
  24031. 800ae22: ea0a 0202 and.w r2, sl, r2
  24032. 800ae26: 701a strb r2, [r3, #0]
  24033. huart->RxXferCount--;
  24034. 800ae28: f8b4 105e ldrh.w r1, [r4, #94] @ 0x5e
  24035. isrflags = READ_REG(huart->Instance->ISR);
  24036. 800ae2c: 6823 ldr r3, [r4, #0]
  24037. huart->RxXferCount--;
  24038. 800ae2e: 3901 subs r1, #1
  24039. huart->pRxBuffPtr++;
  24040. 800ae30: 6da2 ldr r2, [r4, #88] @ 0x58
  24041. huart->RxXferCount--;
  24042. 800ae32: b289 uxth r1, r1
  24043. huart->pRxBuffPtr++;
  24044. 800ae34: 3201 adds r2, #1
  24045. huart->RxXferCount--;
  24046. 800ae36: f8a4 105e strh.w r1, [r4, #94] @ 0x5e
  24047. isrflags = READ_REG(huart->Instance->ISR);
  24048. 800ae3a: f8d3 b01c ldr.w fp, [r3, #28]
  24049. huart->pRxBuffPtr++;
  24050. 800ae3e: 65a2 str r2, [r4, #88] @ 0x58
  24051. if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
  24052. 800ae40: f01b 0f07 tst.w fp, #7
  24053. 800ae44: d01d beq.n 800ae82 <UART_RxISR_8BIT_FIFOEN+0xb2>
  24054. if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
  24055. 800ae46: f01b 0f01 tst.w fp, #1
  24056. 800ae4a: d008 beq.n 800ae5e <UART_RxISR_8BIT_FIFOEN+0x8e>
  24057. 800ae4c: b13e cbz r6, 800ae5e <UART_RxISR_8BIT_FIFOEN+0x8e>
  24058. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
  24059. 800ae4e: 2201 movs r2, #1
  24060. 800ae50: 621a str r2, [r3, #32]
  24061. huart->ErrorCode |= HAL_UART_ERROR_PE;
  24062. 800ae52: f8d4 2090 ldr.w r2, [r4, #144] @ 0x90
  24063. 800ae56: f042 0201 orr.w r2, r2, #1
  24064. 800ae5a: f8c4 2090 str.w r2, [r4, #144] @ 0x90
  24065. if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  24066. 800ae5e: f01b 0f02 tst.w fp, #2
  24067. if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  24068. 800ae62: f00b 0204 and.w r2, fp, #4
  24069. if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  24070. 800ae66: d015 beq.n 800ae94 <UART_RxISR_8BIT_FIFOEN+0xc4>
  24071. 800ae68: b145 cbz r5, 800ae7c <UART_RxISR_8BIT_FIFOEN+0xac>
  24072. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
  24073. 800ae6a: 2102 movs r1, #2
  24074. 800ae6c: 6219 str r1, [r3, #32]
  24075. huart->ErrorCode |= HAL_UART_ERROR_FE;
  24076. 800ae6e: f8d4 1090 ldr.w r1, [r4, #144] @ 0x90
  24077. 800ae72: f041 0104 orr.w r1, r1, #4
  24078. 800ae76: f8c4 1090 str.w r1, [r4, #144] @ 0x90
  24079. if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  24080. 800ae7a: b97a cbnz r2, 800ae9c <UART_RxISR_8BIT_FIFOEN+0xcc>
  24081. if (huart->ErrorCode != HAL_UART_ERROR_NONE)
  24082. 800ae7c: f8d4 3090 ldr.w r3, [r4, #144] @ 0x90
  24083. 800ae80: b9c3 cbnz r3, 800aeb4 <UART_RxISR_8BIT_FIFOEN+0xe4>
  24084. if (huart->RxXferCount == 0U)
  24085. 800ae82: f8b4 305e ldrh.w r3, [r4, #94] @ 0x5e
  24086. 800ae86: b29b uxth r3, r3
  24087. 800ae88: b1f3 cbz r3, 800aec8 <UART_RxISR_8BIT_FIFOEN+0xf8>
  24088. while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
  24089. 800ae8a: f01b 0f20 tst.w fp, #32
  24090. 800ae8e: d043 beq.n 800af18 <UART_RxISR_8BIT_FIFOEN+0x148>
  24091. uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
  24092. 800ae90: 6822 ldr r2, [r4, #0]
  24093. 800ae92: e7c4 b.n 800ae1e <UART_RxISR_8BIT_FIFOEN+0x4e>
  24094. if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  24095. 800ae94: 2a00 cmp r2, #0
  24096. 800ae96: d0f1 beq.n 800ae7c <UART_RxISR_8BIT_FIFOEN+0xac>
  24097. 800ae98: 2d00 cmp r5, #0
  24098. 800ae9a: d0ef beq.n 800ae7c <UART_RxISR_8BIT_FIFOEN+0xac>
  24099. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
  24100. 800ae9c: 2204 movs r2, #4
  24101. 800ae9e: 621a str r2, [r3, #32]
  24102. huart->ErrorCode |= HAL_UART_ERROR_NE;
  24103. 800aea0: f8d4 3090 ldr.w r3, [r4, #144] @ 0x90
  24104. 800aea4: f043 0302 orr.w r3, r3, #2
  24105. 800aea8: f8c4 3090 str.w r3, [r4, #144] @ 0x90
  24106. if (huart->ErrorCode != HAL_UART_ERROR_NONE)
  24107. 800aeac: f8d4 3090 ldr.w r3, [r4, #144] @ 0x90
  24108. 800aeb0: 2b00 cmp r3, #0
  24109. 800aeb2: d0e6 beq.n 800ae82 <UART_RxISR_8BIT_FIFOEN+0xb2>
  24110. HAL_UART_ErrorCallback(huart);
  24111. 800aeb4: 4620 mov r0, r4
  24112. 800aeb6: f7ff fd25 bl 800a904 <HAL_UART_ErrorCallback>
  24113. huart->ErrorCode = HAL_UART_ERROR_NONE;
  24114. 800aeba: f8c4 8090 str.w r8, [r4, #144] @ 0x90
  24115. if (huart->RxXferCount == 0U)
  24116. 800aebe: f8b4 305e ldrh.w r3, [r4, #94] @ 0x5e
  24117. 800aec2: b29b uxth r3, r3
  24118. 800aec4: 2b00 cmp r3, #0
  24119. 800aec6: d1e0 bne.n 800ae8a <UART_RxISR_8BIT_FIFOEN+0xba>
  24120. 800aec8: 6823 ldr r3, [r4, #0]
  24121. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24122. 800aeca: e853 2f00 ldrex r2, [r3]
  24123. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
  24124. 800aece: f422 7280 bic.w r2, r2, #256 @ 0x100
  24125. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24126. 800aed2: e843 2100 strex r1, r2, [r3]
  24127. 800aed6: 2900 cmp r1, #0
  24128. 800aed8: d1f7 bne.n 800aeca <UART_RxISR_8BIT_FIFOEN+0xfa>
  24129. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24130. 800aeda: f103 0208 add.w r2, r3, #8
  24131. 800aede: e852 2f00 ldrex r2, [r2]
  24132. ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
  24133. 800aee2: ea02 0209 and.w r2, r2, r9
  24134. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24135. 800aee6: f103 0008 add.w r0, r3, #8
  24136. 800aeea: e840 2100 strex r1, r2, [r0]
  24137. 800aeee: 2900 cmp r1, #0
  24138. 800aef0: d1f3 bne.n 800aeda <UART_RxISR_8BIT_FIFOEN+0x10a>
  24139. huart->RxState = HAL_UART_STATE_READY;
  24140. 800aef2: 2220 movs r2, #32
  24141. if (!(IS_LPUART_INSTANCE(huart->Instance)))
  24142. 800aef4: 42bb cmp r3, r7
  24143. huart->RxISR = NULL;
  24144. 800aef6: 6761 str r1, [r4, #116] @ 0x74
  24145. huart->RxState = HAL_UART_STATE_READY;
  24146. 800aef8: f8c4 208c str.w r2, [r4, #140] @ 0x8c
  24147. huart->RxEventType = HAL_UART_RXEVENT_TC;
  24148. 800aefc: 6721 str r1, [r4, #112] @ 0x70
  24149. if (!(IS_LPUART_INSTANCE(huart->Instance)))
  24150. 800aefe: d002 beq.n 800af06 <UART_RxISR_8BIT_FIFOEN+0x136>
  24151. if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
  24152. 800af00: 685a ldr r2, [r3, #4]
  24153. 800af02: 0211 lsls r1, r2, #8
  24154. 800af04: d42b bmi.n 800af5e <UART_RxISR_8BIT_FIFOEN+0x18e>
  24155. if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
  24156. 800af06: 6ee2 ldr r2, [r4, #108] @ 0x6c
  24157. 800af08: 2a01 cmp r2, #1
  24158. 800af0a: d039 beq.n 800af80 <UART_RxISR_8BIT_FIFOEN+0x1b0>
  24159. HAL_UART_RxCpltCallback(huart);
  24160. 800af0c: 4620 mov r0, r4
  24161. 800af0e: f7f8 ffa7 bl 8003e60 <HAL_UART_RxCpltCallback>
  24162. while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
  24163. 800af12: f01b 0f20 tst.w fp, #32
  24164. 800af16: d1bb bne.n 800ae90 <UART_RxISR_8BIT_FIFOEN+0xc0>
  24165. rxdatacount = huart->RxXferCount;
  24166. 800af18: f8b4 305e ldrh.w r3, [r4, #94] @ 0x5e
  24167. 800af1c: b29b uxth r3, r3
  24168. if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
  24169. 800af1e: 2b00 cmp r3, #0
  24170. 800af20: f43f af68 beq.w 800adf4 <UART_RxISR_8BIT_FIFOEN+0x24>
  24171. 800af24: f8b4 2068 ldrh.w r2, [r4, #104] @ 0x68
  24172. 800af28: 429a cmp r2, r3
  24173. 800af2a: f67f af63 bls.w 800adf4 <UART_RxISR_8BIT_FIFOEN+0x24>
  24174. 800af2e: 6823 ldr r3, [r4, #0]
  24175. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24176. 800af30: f103 0208 add.w r2, r3, #8
  24177. 800af34: e852 2f00 ldrex r2, [r2]
  24178. ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
  24179. 800af38: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000
  24180. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24181. 800af3c: f103 0008 add.w r0, r3, #8
  24182. 800af40: e840 2100 strex r1, r2, [r0]
  24183. 800af44: 2900 cmp r1, #0
  24184. 800af46: d1f3 bne.n 800af30 <UART_RxISR_8BIT_FIFOEN+0x160>
  24185. huart->RxISR = UART_RxISR_8BIT;
  24186. 800af48: 4a1a ldr r2, [pc, #104] @ (800afb4 <UART_RxISR_8BIT_FIFOEN+0x1e4>)
  24187. 800af4a: 6762 str r2, [r4, #116] @ 0x74
  24188. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24189. 800af4c: e853 2f00 ldrex r2, [r3]
  24190. ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
  24191. 800af50: f042 0220 orr.w r2, r2, #32
  24192. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24193. 800af54: e843 2100 strex r1, r2, [r3]
  24194. 800af58: 2900 cmp r1, #0
  24195. 800af5a: d1f7 bne.n 800af4c <UART_RxISR_8BIT_FIFOEN+0x17c>
  24196. 800af5c: e74a b.n 800adf4 <UART_RxISR_8BIT_FIFOEN+0x24>
  24197. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24198. 800af5e: e853 2f00 ldrex r2, [r3]
  24199. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
  24200. 800af62: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000
  24201. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24202. 800af66: e843 2100 strex r1, r2, [r3]
  24203. 800af6a: 2900 cmp r1, #0
  24204. 800af6c: d0cb beq.n 800af06 <UART_RxISR_8BIT_FIFOEN+0x136>
  24205. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24206. 800af6e: e853 2f00 ldrex r2, [r3]
  24207. 800af72: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000
  24208. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24209. 800af76: e843 2100 strex r1, r2, [r3]
  24210. 800af7a: 2900 cmp r1, #0
  24211. 800af7c: d1ef bne.n 800af5e <UART_RxISR_8BIT_FIFOEN+0x18e>
  24212. 800af7e: e7c2 b.n 800af06 <UART_RxISR_8BIT_FIFOEN+0x136>
  24213. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  24214. 800af80: 2200 movs r2, #0
  24215. 800af82: 66e2 str r2, [r4, #108] @ 0x6c
  24216. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24217. 800af84: e853 2f00 ldrex r2, [r3]
  24218. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  24219. 800af88: f022 0210 bic.w r2, r2, #16
  24220. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24221. 800af8c: e843 2100 strex r1, r2, [r3]
  24222. 800af90: 2900 cmp r1, #0
  24223. 800af92: d1f7 bne.n 800af84 <UART_RxISR_8BIT_FIFOEN+0x1b4>
  24224. if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
  24225. 800af94: 69da ldr r2, [r3, #28]
  24226. 800af96: 06d2 lsls r2, r2, #27
  24227. 800af98: d501 bpl.n 800af9e <UART_RxISR_8BIT_FIFOEN+0x1ce>
  24228. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
  24229. 800af9a: 2210 movs r2, #16
  24230. 800af9c: 621a str r2, [r3, #32]
  24231. HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
  24232. 800af9e: f8b4 105c ldrh.w r1, [r4, #92] @ 0x5c
  24233. 800afa2: 4620 mov r0, r4
  24234. 800afa4: f7f8 ff94 bl 8003ed0 <HAL_UARTEx_RxEventCallback>
  24235. 800afa8: e76f b.n 800ae8a <UART_RxISR_8BIT_FIFOEN+0xba>
  24236. rxdatacount = huart->RxXferCount;
  24237. 800afaa: f8b4 305e ldrh.w r3, [r4, #94] @ 0x5e
  24238. if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
  24239. 800afae: e721 b.n 800adf4 <UART_RxISR_8BIT_FIFOEN+0x24>
  24240. 800afb0: 58000c00 .word 0x58000c00
  24241. 800afb4: 0800ad8d .word 0x0800ad8d
  24242. 800afb8: effffffe .word 0xeffffffe
  24243. 0800afbc <UART_RxISR_16BIT_FIFOEN>:
  24244. * interruptions have been enabled by HAL_UART_Receive_IT()
  24245. * @param huart UART handle.
  24246. * @retval None
  24247. */
  24248. static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
  24249. {
  24250. 800afbc: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  24251. uint16_t *tmp;
  24252. uint16_t uhMask = huart->Mask;
  24253. uint16_t uhdata;
  24254. uint16_t nb_rx_data;
  24255. uint16_t rxdatacount;
  24256. uint32_t isrflags = READ_REG(huart->Instance->ISR);
  24257. 800afc0: 6803 ldr r3, [r0, #0]
  24258. uint16_t uhMask = huart->Mask;
  24259. 800afc2: f8b0 a060 ldrh.w sl, [r0, #96] @ 0x60
  24260. uint32_t isrflags = READ_REG(huart->Instance->ISR);
  24261. 800afc6: 69d9 ldr r1, [r3, #28]
  24262. uint32_t cr1its = READ_REG(huart->Instance->CR1);
  24263. 800afc8: 681e ldr r6, [r3, #0]
  24264. uint32_t cr3its = READ_REG(huart->Instance->CR3);
  24265. 800afca: 689d ldr r5, [r3, #8]
  24266. /* Check that a Rx process is ongoing */
  24267. if (huart->RxState == HAL_UART_STATE_BUSY_RX)
  24268. 800afcc: f8d0 208c ldr.w r2, [r0, #140] @ 0x8c
  24269. 800afd0: 2a22 cmp r2, #34 @ 0x22
  24270. 800afd2: d005 beq.n 800afe0 <UART_RxISR_16BIT_FIFOEN+0x24>
  24271. }
  24272. }
  24273. else
  24274. {
  24275. /* Clear RXNE interrupt flag */
  24276. __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
  24277. 800afd4: 699a ldr r2, [r3, #24]
  24278. 800afd6: f042 0208 orr.w r2, r2, #8
  24279. 800afda: 619a str r2, [r3, #24]
  24280. }
  24281. }
  24282. 800afdc: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
  24283. while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
  24284. 800afe0: f8b0 2068 ldrh.w r2, [r0, #104] @ 0x68
  24285. 800afe4: 4683 mov fp, r0
  24286. 800afe6: 2a00 cmp r2, #0
  24287. 800afe8: f000 80d4 beq.w 800b194 <UART_RxISR_16BIT_FIFOEN+0x1d8>
  24288. 800afec: 0688 lsls r0, r1, #26
  24289. 800afee: f140 8085 bpl.w 800b0fc <UART_RxISR_16BIT_FIFOEN+0x140>
  24290. if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
  24291. 800aff2: f406 7680 and.w r6, r6, #256 @ 0x100
  24292. if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  24293. 800aff6: f005 0501 and.w r5, r5, #1
  24294. huart->ErrorCode = HAL_UART_ERROR_NONE;
  24295. 800affa: f04f 0800 mov.w r8, #0
  24296. ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
  24297. 800affe: f8df 91a4 ldr.w r9, [pc, #420] @ 800b1a4 <UART_RxISR_16BIT_FIFOEN+0x1e8>
  24298. if (!(IS_LPUART_INSTANCE(huart->Instance)))
  24299. 800b002: 4f66 ldr r7, [pc, #408] @ (800b19c <UART_RxISR_16BIT_FIFOEN+0x1e0>)
  24300. uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
  24301. 800b004: 6a5a ldr r2, [r3, #36] @ 0x24
  24302. *tmp = (uint16_t)(uhdata & uhMask);
  24303. 800b006: f8db 1058 ldr.w r1, [fp, #88] @ 0x58
  24304. 800b00a: ea0a 0202 and.w r2, sl, r2
  24305. 800b00e: f821 2b02 strh.w r2, [r1], #2
  24306. huart->RxXferCount--;
  24307. 800b012: f8bb 205e ldrh.w r2, [fp, #94] @ 0x5e
  24308. huart->pRxBuffPtr += 2U;
  24309. 800b016: f8cb 1058 str.w r1, [fp, #88] @ 0x58
  24310. huart->RxXferCount--;
  24311. 800b01a: 3a01 subs r2, #1
  24312. 800b01c: b292 uxth r2, r2
  24313. 800b01e: f8ab 205e strh.w r2, [fp, #94] @ 0x5e
  24314. isrflags = READ_REG(huart->Instance->ISR);
  24315. 800b022: 69dc ldr r4, [r3, #28]
  24316. if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
  24317. 800b024: 0761 lsls r1, r4, #29
  24318. 800b026: d01b beq.n 800b060 <UART_RxISR_16BIT_FIFOEN+0xa4>
  24319. if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
  24320. 800b028: 07e2 lsls r2, r4, #31
  24321. 800b02a: d508 bpl.n 800b03e <UART_RxISR_16BIT_FIFOEN+0x82>
  24322. 800b02c: b13e cbz r6, 800b03e <UART_RxISR_16BIT_FIFOEN+0x82>
  24323. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
  24324. 800b02e: 2201 movs r2, #1
  24325. 800b030: 621a str r2, [r3, #32]
  24326. huart->ErrorCode |= HAL_UART_ERROR_PE;
  24327. 800b032: f8db 2090 ldr.w r2, [fp, #144] @ 0x90
  24328. 800b036: f042 0201 orr.w r2, r2, #1
  24329. 800b03a: f8cb 2090 str.w r2, [fp, #144] @ 0x90
  24330. if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  24331. 800b03e: 07a0 lsls r0, r4, #30
  24332. if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  24333. 800b040: f004 0204 and.w r2, r4, #4
  24334. if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  24335. 800b044: d515 bpl.n 800b072 <UART_RxISR_16BIT_FIFOEN+0xb6>
  24336. 800b046: b145 cbz r5, 800b05a <UART_RxISR_16BIT_FIFOEN+0x9e>
  24337. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
  24338. 800b048: 2102 movs r1, #2
  24339. 800b04a: 6219 str r1, [r3, #32]
  24340. huart->ErrorCode |= HAL_UART_ERROR_FE;
  24341. 800b04c: f8db 1090 ldr.w r1, [fp, #144] @ 0x90
  24342. 800b050: f041 0104 orr.w r1, r1, #4
  24343. 800b054: f8cb 1090 str.w r1, [fp, #144] @ 0x90
  24344. if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  24345. 800b058: b97a cbnz r2, 800b07a <UART_RxISR_16BIT_FIFOEN+0xbe>
  24346. if (huart->ErrorCode != HAL_UART_ERROR_NONE)
  24347. 800b05a: f8db 3090 ldr.w r3, [fp, #144] @ 0x90
  24348. 800b05e: b9c3 cbnz r3, 800b092 <UART_RxISR_16BIT_FIFOEN+0xd6>
  24349. if (huart->RxXferCount == 0U)
  24350. 800b060: f8bb 305e ldrh.w r3, [fp, #94] @ 0x5e
  24351. 800b064: b29b uxth r3, r3
  24352. 800b066: b1f3 cbz r3, 800b0a6 <UART_RxISR_16BIT_FIFOEN+0xea>
  24353. while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
  24354. 800b068: 06a3 lsls r3, r4, #26
  24355. 800b06a: d547 bpl.n 800b0fc <UART_RxISR_16BIT_FIFOEN+0x140>
  24356. uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
  24357. 800b06c: f8db 3000 ldr.w r3, [fp]
  24358. 800b070: e7c8 b.n 800b004 <UART_RxISR_16BIT_FIFOEN+0x48>
  24359. if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
  24360. 800b072: 2a00 cmp r2, #0
  24361. 800b074: d0f1 beq.n 800b05a <UART_RxISR_16BIT_FIFOEN+0x9e>
  24362. 800b076: 2d00 cmp r5, #0
  24363. 800b078: d0ef beq.n 800b05a <UART_RxISR_16BIT_FIFOEN+0x9e>
  24364. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
  24365. 800b07a: 2204 movs r2, #4
  24366. 800b07c: 621a str r2, [r3, #32]
  24367. huart->ErrorCode |= HAL_UART_ERROR_NE;
  24368. 800b07e: f8db 3090 ldr.w r3, [fp, #144] @ 0x90
  24369. 800b082: f043 0302 orr.w r3, r3, #2
  24370. 800b086: f8cb 3090 str.w r3, [fp, #144] @ 0x90
  24371. if (huart->ErrorCode != HAL_UART_ERROR_NONE)
  24372. 800b08a: f8db 3090 ldr.w r3, [fp, #144] @ 0x90
  24373. 800b08e: 2b00 cmp r3, #0
  24374. 800b090: d0e6 beq.n 800b060 <UART_RxISR_16BIT_FIFOEN+0xa4>
  24375. HAL_UART_ErrorCallback(huart);
  24376. 800b092: 4658 mov r0, fp
  24377. 800b094: f7ff fc36 bl 800a904 <HAL_UART_ErrorCallback>
  24378. huart->ErrorCode = HAL_UART_ERROR_NONE;
  24379. 800b098: f8cb 8090 str.w r8, [fp, #144] @ 0x90
  24380. if (huart->RxXferCount == 0U)
  24381. 800b09c: f8bb 305e ldrh.w r3, [fp, #94] @ 0x5e
  24382. 800b0a0: b29b uxth r3, r3
  24383. 800b0a2: 2b00 cmp r3, #0
  24384. 800b0a4: d1e0 bne.n 800b068 <UART_RxISR_16BIT_FIFOEN+0xac>
  24385. 800b0a6: f8db 3000 ldr.w r3, [fp]
  24386. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24387. 800b0aa: e853 2f00 ldrex r2, [r3]
  24388. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
  24389. 800b0ae: f422 7280 bic.w r2, r2, #256 @ 0x100
  24390. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24391. 800b0b2: e843 2100 strex r1, r2, [r3]
  24392. 800b0b6: 2900 cmp r1, #0
  24393. 800b0b8: d1f7 bne.n 800b0aa <UART_RxISR_16BIT_FIFOEN+0xee>
  24394. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24395. 800b0ba: f103 0208 add.w r2, r3, #8
  24396. 800b0be: e852 2f00 ldrex r2, [r2]
  24397. ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
  24398. 800b0c2: ea02 0209 and.w r2, r2, r9
  24399. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24400. 800b0c6: f103 0008 add.w r0, r3, #8
  24401. 800b0ca: e840 2100 strex r1, r2, [r0]
  24402. 800b0ce: 2900 cmp r1, #0
  24403. 800b0d0: d1f3 bne.n 800b0ba <UART_RxISR_16BIT_FIFOEN+0xfe>
  24404. huart->RxState = HAL_UART_STATE_READY;
  24405. 800b0d2: 2220 movs r2, #32
  24406. if (!(IS_LPUART_INSTANCE(huart->Instance)))
  24407. 800b0d4: 42bb cmp r3, r7
  24408. huart->RxISR = NULL;
  24409. 800b0d6: f8cb 1074 str.w r1, [fp, #116] @ 0x74
  24410. huart->RxState = HAL_UART_STATE_READY;
  24411. 800b0da: f8cb 208c str.w r2, [fp, #140] @ 0x8c
  24412. huart->RxEventType = HAL_UART_RXEVENT_TC;
  24413. 800b0de: f8cb 1070 str.w r1, [fp, #112] @ 0x70
  24414. if (!(IS_LPUART_INSTANCE(huart->Instance)))
  24415. 800b0e2: d002 beq.n 800b0ea <UART_RxISR_16BIT_FIFOEN+0x12e>
  24416. if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
  24417. 800b0e4: 685a ldr r2, [r3, #4]
  24418. 800b0e6: 0211 lsls r1, r2, #8
  24419. 800b0e8: d42d bmi.n 800b146 <UART_RxISR_16BIT_FIFOEN+0x18a>
  24420. if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
  24421. 800b0ea: f8db 206c ldr.w r2, [fp, #108] @ 0x6c
  24422. 800b0ee: 2a01 cmp r2, #1
  24423. 800b0f0: d03a beq.n 800b168 <UART_RxISR_16BIT_FIFOEN+0x1ac>
  24424. HAL_UART_RxCpltCallback(huart);
  24425. 800b0f2: 4658 mov r0, fp
  24426. 800b0f4: f7f8 feb4 bl 8003e60 <HAL_UART_RxCpltCallback>
  24427. while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
  24428. 800b0f8: 06a3 lsls r3, r4, #26
  24429. 800b0fa: d4b7 bmi.n 800b06c <UART_RxISR_16BIT_FIFOEN+0xb0>
  24430. rxdatacount = huart->RxXferCount;
  24431. 800b0fc: f8bb 305e ldrh.w r3, [fp, #94] @ 0x5e
  24432. 800b100: b29b uxth r3, r3
  24433. if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
  24434. 800b102: 2b00 cmp r3, #0
  24435. 800b104: f43f af6a beq.w 800afdc <UART_RxISR_16BIT_FIFOEN+0x20>
  24436. 800b108: f8bb 2068 ldrh.w r2, [fp, #104] @ 0x68
  24437. 800b10c: 429a cmp r2, r3
  24438. 800b10e: f67f af65 bls.w 800afdc <UART_RxISR_16BIT_FIFOEN+0x20>
  24439. 800b112: f8db 3000 ldr.w r3, [fp]
  24440. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24441. 800b116: f103 0208 add.w r2, r3, #8
  24442. 800b11a: e852 2f00 ldrex r2, [r2]
  24443. ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
  24444. 800b11e: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000
  24445. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24446. 800b122: f103 0008 add.w r0, r3, #8
  24447. 800b126: e840 2100 strex r1, r2, [r0]
  24448. 800b12a: 2900 cmp r1, #0
  24449. 800b12c: d1f3 bne.n 800b116 <UART_RxISR_16BIT_FIFOEN+0x15a>
  24450. huart->RxISR = UART_RxISR_16BIT;
  24451. 800b12e: 4a1c ldr r2, [pc, #112] @ (800b1a0 <UART_RxISR_16BIT_FIFOEN+0x1e4>)
  24452. 800b130: f8cb 2074 str.w r2, [fp, #116] @ 0x74
  24453. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24454. 800b134: e853 2f00 ldrex r2, [r3]
  24455. ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
  24456. 800b138: f042 0220 orr.w r2, r2, #32
  24457. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24458. 800b13c: e843 2100 strex r1, r2, [r3]
  24459. 800b140: 2900 cmp r1, #0
  24460. 800b142: d1f7 bne.n 800b134 <UART_RxISR_16BIT_FIFOEN+0x178>
  24461. 800b144: e74a b.n 800afdc <UART_RxISR_16BIT_FIFOEN+0x20>
  24462. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24463. 800b146: e853 2f00 ldrex r2, [r3]
  24464. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
  24465. 800b14a: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000
  24466. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24467. 800b14e: e843 2100 strex r1, r2, [r3]
  24468. 800b152: 2900 cmp r1, #0
  24469. 800b154: d0c9 beq.n 800b0ea <UART_RxISR_16BIT_FIFOEN+0x12e>
  24470. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24471. 800b156: e853 2f00 ldrex r2, [r3]
  24472. 800b15a: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000
  24473. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24474. 800b15e: e843 2100 strex r1, r2, [r3]
  24475. 800b162: 2900 cmp r1, #0
  24476. 800b164: d1ef bne.n 800b146 <UART_RxISR_16BIT_FIFOEN+0x18a>
  24477. 800b166: e7c0 b.n 800b0ea <UART_RxISR_16BIT_FIFOEN+0x12e>
  24478. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  24479. 800b168: 2200 movs r2, #0
  24480. 800b16a: f8cb 206c str.w r2, [fp, #108] @ 0x6c
  24481. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  24482. 800b16e: e853 2f00 ldrex r2, [r3]
  24483. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  24484. 800b172: f022 0210 bic.w r2, r2, #16
  24485. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  24486. 800b176: e843 2100 strex r1, r2, [r3]
  24487. 800b17a: 2900 cmp r1, #0
  24488. 800b17c: d1f7 bne.n 800b16e <UART_RxISR_16BIT_FIFOEN+0x1b2>
  24489. if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
  24490. 800b17e: 69da ldr r2, [r3, #28]
  24491. 800b180: 06d2 lsls r2, r2, #27
  24492. 800b182: d501 bpl.n 800b188 <UART_RxISR_16BIT_FIFOEN+0x1cc>
  24493. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
  24494. 800b184: 2210 movs r2, #16
  24495. 800b186: 621a str r2, [r3, #32]
  24496. HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
  24497. 800b188: f8bb 105c ldrh.w r1, [fp, #92] @ 0x5c
  24498. 800b18c: 4658 mov r0, fp
  24499. 800b18e: f7f8 fe9f bl 8003ed0 <HAL_UARTEx_RxEventCallback>
  24500. 800b192: e769 b.n 800b068 <UART_RxISR_16BIT_FIFOEN+0xac>
  24501. rxdatacount = huart->RxXferCount;
  24502. 800b194: f8b0 305e ldrh.w r3, [r0, #94] @ 0x5e
  24503. if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
  24504. 800b198: e720 b.n 800afdc <UART_RxISR_16BIT_FIFOEN+0x20>
  24505. 800b19a: bf00 nop
  24506. 800b19c: 58000c00 .word 0x58000c00
  24507. 800b1a0: 0800ad45 .word 0x0800ad45
  24508. 800b1a4: effffffe .word 0xeffffffe
  24509. 0800b1a8 <UART_SetConfig>:
  24510. tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
  24511. 800b1a8: 6901 ldr r1, [r0, #16]
  24512. 800b1aa: 6882 ldr r2, [r0, #8]
  24513. if (UART_INSTANCE_LOWPOWER(huart))
  24514. 800b1ac: 6803 ldr r3, [r0, #0]
  24515. tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
  24516. 800b1ae: 430a orrs r2, r1
  24517. MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
  24518. 800b1b0: 49a2 ldr r1, [pc, #648] @ (800b43c <UART_SetConfig+0x294>)
  24519. {
  24520. 800b1b2: b570 push {r4, r5, r6, lr}
  24521. tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
  24522. 800b1b4: 6945 ldr r5, [r0, #20]
  24523. {
  24524. 800b1b6: 4604 mov r4, r0
  24525. tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
  24526. 800b1b8: 69c0 ldr r0, [r0, #28]
  24527. {
  24528. 800b1ba: b086 sub sp, #24
  24529. tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
  24530. 800b1bc: 432a orrs r2, r5
  24531. MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
  24532. 800b1be: 681d ldr r5, [r3, #0]
  24533. tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
  24534. 800b1c0: 4302 orrs r2, r0
  24535. MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
  24536. 800b1c2: 4029 ands r1, r5
  24537. MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
  24538. 800b1c4: 6a65 ldr r5, [r4, #36] @ 0x24
  24539. MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
  24540. 800b1c6: 430a orrs r2, r1
  24541. MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
  24542. 800b1c8: 68e1 ldr r1, [r4, #12]
  24543. MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
  24544. 800b1ca: 601a str r2, [r3, #0]
  24545. MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
  24546. 800b1cc: 685a ldr r2, [r3, #4]
  24547. 800b1ce: f422 5240 bic.w r2, r2, #12288 @ 0x3000
  24548. 800b1d2: 430a orrs r2, r1
  24549. tmpreg = (uint32_t)huart->Init.HwFlowCtl;
  24550. 800b1d4: 69a1 ldr r1, [r4, #24]
  24551. MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
  24552. 800b1d6: 605a str r2, [r3, #4]
  24553. if (!(UART_INSTANCE_LOWPOWER(huart)))
  24554. 800b1d8: 4a99 ldr r2, [pc, #612] @ (800b440 <UART_SetConfig+0x298>)
  24555. 800b1da: 4293 cmp r3, r2
  24556. 800b1dc: f000 8118 beq.w 800b410 <UART_SetConfig+0x268>
  24557. tmpreg |= huart->Init.OneBitSampling;
  24558. 800b1e0: 6a22 ldr r2, [r4, #32]
  24559. MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
  24560. 800b1e2: 689e ldr r6, [r3, #8]
  24561. tmpreg |= huart->Init.OneBitSampling;
  24562. 800b1e4: 4311 orrs r1, r2
  24563. MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
  24564. 800b1e6: 4a97 ldr r2, [pc, #604] @ (800b444 <UART_SetConfig+0x29c>)
  24565. 800b1e8: 4032 ands r2, r6
  24566. 800b1ea: 4311 orrs r1, r2
  24567. 800b1ec: 6099 str r1, [r3, #8]
  24568. MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
  24569. 800b1ee: 6ada ldr r2, [r3, #44] @ 0x2c
  24570. 800b1f0: f022 020f bic.w r2, r2, #15
  24571. 800b1f4: 432a orrs r2, r5
  24572. 800b1f6: 62da str r2, [r3, #44] @ 0x2c
  24573. UART_GETCLOCKSOURCE(huart, clocksource);
  24574. 800b1f8: 4a93 ldr r2, [pc, #588] @ (800b448 <UART_SetConfig+0x2a0>)
  24575. 800b1fa: 4293 cmp r3, r2
  24576. 800b1fc: d028 beq.n 800b250 <UART_SetConfig+0xa8>
  24577. 800b1fe: 4a93 ldr r2, [pc, #588] @ (800b44c <UART_SetConfig+0x2a4>)
  24578. 800b200: 4293 cmp r3, r2
  24579. 800b202: d01a beq.n 800b23a <UART_SetConfig+0x92>
  24580. 800b204: 4a92 ldr r2, [pc, #584] @ (800b450 <UART_SetConfig+0x2a8>)
  24581. 800b206: 4293 cmp r3, r2
  24582. 800b208: d017 beq.n 800b23a <UART_SetConfig+0x92>
  24583. 800b20a: 4a92 ldr r2, [pc, #584] @ (800b454 <UART_SetConfig+0x2ac>)
  24584. 800b20c: 4293 cmp r3, r2
  24585. 800b20e: d014 beq.n 800b23a <UART_SetConfig+0x92>
  24586. 800b210: 4a91 ldr r2, [pc, #580] @ (800b458 <UART_SetConfig+0x2b0>)
  24587. 800b212: 4293 cmp r3, r2
  24588. 800b214: d011 beq.n 800b23a <UART_SetConfig+0x92>
  24589. 800b216: 4a91 ldr r2, [pc, #580] @ (800b45c <UART_SetConfig+0x2b4>)
  24590. 800b218: 4293 cmp r3, r2
  24591. 800b21a: d019 beq.n 800b250 <UART_SetConfig+0xa8>
  24592. 800b21c: 4a90 ldr r2, [pc, #576] @ (800b460 <UART_SetConfig+0x2b8>)
  24593. 800b21e: 4293 cmp r3, r2
  24594. 800b220: d00b beq.n 800b23a <UART_SetConfig+0x92>
  24595. 800b222: 4a90 ldr r2, [pc, #576] @ (800b464 <UART_SetConfig+0x2bc>)
  24596. 800b224: 4293 cmp r3, r2
  24597. 800b226: d008 beq.n 800b23a <UART_SetConfig+0x92>
  24598. ret = HAL_ERROR;
  24599. 800b228: 2001 movs r0, #1
  24600. huart->RxISR = NULL;
  24601. 800b22a: 2300 movs r3, #0
  24602. huart->NbRxDataToProcess = 1;
  24603. 800b22c: f04f 1201 mov.w r2, #65537 @ 0x10001
  24604. huart->RxISR = NULL;
  24605. 800b230: 6763 str r3, [r4, #116] @ 0x74
  24606. huart->NbRxDataToProcess = 1;
  24607. 800b232: 66a2 str r2, [r4, #104] @ 0x68
  24608. huart->TxISR = NULL;
  24609. 800b234: 67a3 str r3, [r4, #120] @ 0x78
  24610. }
  24611. 800b236: b006 add sp, #24
  24612. 800b238: bd70 pop {r4, r5, r6, pc}
  24613. UART_GETCLOCKSOURCE(huart, clocksource);
  24614. 800b23a: 4b8b ldr r3, [pc, #556] @ (800b468 <UART_SetConfig+0x2c0>)
  24615. 800b23c: 6d5b ldr r3, [r3, #84] @ 0x54
  24616. 800b23e: f003 0307 and.w r3, r3, #7
  24617. 800b242: 2b05 cmp r3, #5
  24618. 800b244: d8f0 bhi.n 800b228 <UART_SetConfig+0x80>
  24619. 800b246: e8df f003 tbb [pc, r3]
  24620. 800b24a: 5f9d .short 0x5f9d
  24621. 800b24c: 977e7169 .word 0x977e7169
  24622. 800b250: 4b85 ldr r3, [pc, #532] @ (800b468 <UART_SetConfig+0x2c0>)
  24623. 800b252: 6d5b ldr r3, [r3, #84] @ 0x54
  24624. 800b254: f003 0338 and.w r3, r3, #56 @ 0x38
  24625. 800b258: 2b28 cmp r3, #40 @ 0x28
  24626. 800b25a: d8e5 bhi.n 800b228 <UART_SetConfig+0x80>
  24627. 800b25c: a201 add r2, pc, #4 @ (adr r2, 800b264 <UART_SetConfig+0xbc>)
  24628. 800b25e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  24629. 800b262: bf00 nop
  24630. 800b264: 0800b3df .word 0x0800b3df
  24631. 800b268: 0800b229 .word 0x0800b229
  24632. 800b26c: 0800b229 .word 0x0800b229
  24633. 800b270: 0800b229 .word 0x0800b229
  24634. 800b274: 0800b229 .word 0x0800b229
  24635. 800b278: 0800b229 .word 0x0800b229
  24636. 800b27c: 0800b229 .word 0x0800b229
  24637. 800b280: 0800b229 .word 0x0800b229
  24638. 800b284: 0800b309 .word 0x0800b309
  24639. 800b288: 0800b229 .word 0x0800b229
  24640. 800b28c: 0800b229 .word 0x0800b229
  24641. 800b290: 0800b229 .word 0x0800b229
  24642. 800b294: 0800b229 .word 0x0800b229
  24643. 800b298: 0800b229 .word 0x0800b229
  24644. 800b29c: 0800b229 .word 0x0800b229
  24645. 800b2a0: 0800b229 .word 0x0800b229
  24646. 800b2a4: 0800b31d .word 0x0800b31d
  24647. 800b2a8: 0800b229 .word 0x0800b229
  24648. 800b2ac: 0800b229 .word 0x0800b229
  24649. 800b2b0: 0800b229 .word 0x0800b229
  24650. 800b2b4: 0800b229 .word 0x0800b229
  24651. 800b2b8: 0800b229 .word 0x0800b229
  24652. 800b2bc: 0800b229 .word 0x0800b229
  24653. 800b2c0: 0800b229 .word 0x0800b229
  24654. 800b2c4: 0800b32d .word 0x0800b32d
  24655. 800b2c8: 0800b229 .word 0x0800b229
  24656. 800b2cc: 0800b229 .word 0x0800b229
  24657. 800b2d0: 0800b229 .word 0x0800b229
  24658. 800b2d4: 0800b229 .word 0x0800b229
  24659. 800b2d8: 0800b229 .word 0x0800b229
  24660. 800b2dc: 0800b229 .word 0x0800b229
  24661. 800b2e0: 0800b229 .word 0x0800b229
  24662. 800b2e4: 0800b347 .word 0x0800b347
  24663. 800b2e8: 0800b229 .word 0x0800b229
  24664. 800b2ec: 0800b229 .word 0x0800b229
  24665. 800b2f0: 0800b229 .word 0x0800b229
  24666. 800b2f4: 0800b229 .word 0x0800b229
  24667. 800b2f8: 0800b229 .word 0x0800b229
  24668. 800b2fc: 0800b229 .word 0x0800b229
  24669. 800b300: 0800b229 .word 0x0800b229
  24670. 800b304: 0800b379 .word 0x0800b379
  24671. else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
  24672. 800b308: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
  24673. 800b30c: d040 beq.n 800b390 <UART_SetConfig+0x1e8>
  24674. HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
  24675. 800b30e: 4668 mov r0, sp
  24676. 800b310: f7fd fec6 bl 80090a0 <HAL_RCCEx_GetPLL2ClockFreq>
  24677. pclk = pll2_clocks.PLL2_Q_Frequency;
  24678. 800b314: 9801 ldr r0, [sp, #4]
  24679. if (pclk != 0U)
  24680. 800b316: b368 cbz r0, 800b374 <UART_SetConfig+0x1cc>
  24681. usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
  24682. 800b318: 6a65 ldr r5, [r4, #36] @ 0x24
  24683. 800b31a: e018 b.n 800b34e <UART_SetConfig+0x1a6>
  24684. else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
  24685. 800b31c: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
  24686. 800b320: d06e beq.n 800b400 <UART_SetConfig+0x258>
  24687. HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
  24688. 800b322: a803 add r0, sp, #12
  24689. 800b324: f7fd ff56 bl 80091d4 <HAL_RCCEx_GetPLL3ClockFreq>
  24690. pclk = pll3_clocks.PLL3_Q_Frequency;
  24691. 800b328: 9804 ldr r0, [sp, #16]
  24692. break;
  24693. 800b32a: e7f4 b.n 800b316 <UART_SetConfig+0x16e>
  24694. else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
  24695. 800b32c: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
  24696. 800b330: d05b beq.n 800b3ea <UART_SetConfig+0x242>
  24697. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  24698. 800b332: 4b4d ldr r3, [pc, #308] @ (800b468 <UART_SetConfig+0x2c0>)
  24699. 800b334: 681a ldr r2, [r3, #0]
  24700. 800b336: 0692 lsls r2, r2, #26
  24701. 800b338: d54c bpl.n 800b3d4 <UART_SetConfig+0x22c>
  24702. pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
  24703. 800b33a: 681b ldr r3, [r3, #0]
  24704. 800b33c: 484b ldr r0, [pc, #300] @ (800b46c <UART_SetConfig+0x2c4>)
  24705. 800b33e: f3c3 03c1 ubfx r3, r3, #3, #2
  24706. 800b342: 40d8 lsrs r0, r3
  24707. if (pclk != 0U)
  24708. 800b344: e003 b.n 800b34e <UART_SetConfig+0x1a6>
  24709. else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
  24710. 800b346: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
  24711. pclk = (uint32_t) CSI_VALUE;
  24712. 800b34a: 4849 ldr r0, [pc, #292] @ (800b470 <UART_SetConfig+0x2c8>)
  24713. else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
  24714. 800b34c: d027 beq.n 800b39e <UART_SetConfig+0x1f6>
  24715. usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
  24716. 800b34e: 4a49 ldr r2, [pc, #292] @ (800b474 <UART_SetConfig+0x2cc>)
  24717. 800b350: 6863 ldr r3, [r4, #4]
  24718. 800b352: f832 1015 ldrh.w r1, [r2, r5, lsl #1]
  24719. if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
  24720. 800b356: f64f 72ef movw r2, #65519 @ 0xffef
  24721. usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
  24722. 800b35a: fbb0 f0f1 udiv r0, r0, r1
  24723. 800b35e: eb00 0053 add.w r0, r0, r3, lsr #1
  24724. 800b362: fbb0 f0f3 udiv r0, r0, r3
  24725. if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
  24726. 800b366: f1a0 0310 sub.w r3, r0, #16
  24727. 800b36a: 4293 cmp r3, r2
  24728. 800b36c: f63f af5c bhi.w 800b228 <UART_SetConfig+0x80>
  24729. huart->Instance->BRR = usartdiv;
  24730. 800b370: 6823 ldr r3, [r4, #0]
  24731. 800b372: 60d8 str r0, [r3, #12]
  24732. pclk = (uint32_t) HSI_VALUE;
  24733. 800b374: 2000 movs r0, #0
  24734. 800b376: e758 b.n 800b22a <UART_SetConfig+0x82>
  24735. else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
  24736. 800b378: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
  24737. 800b37c: d00f beq.n 800b39e <UART_SetConfig+0x1f6>
  24738. pclk = (uint32_t) LSE_VALUE;
  24739. 800b37e: f44f 4000 mov.w r0, #32768 @ 0x8000
  24740. 800b382: e7e4 b.n 800b34e <UART_SetConfig+0x1a6>
  24741. else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
  24742. 800b384: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
  24743. 800b388: d026 beq.n 800b3d8 <UART_SetConfig+0x230>
  24744. pclk = HAL_RCC_GetPCLK1Freq();
  24745. 800b38a: f7fc fd89 bl 8007ea0 <HAL_RCC_GetPCLK1Freq>
  24746. break;
  24747. 800b38e: e7c2 b.n 800b316 <UART_SetConfig+0x16e>
  24748. HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
  24749. 800b390: 4668 mov r0, sp
  24750. 800b392: f7fd fe85 bl 80090a0 <HAL_RCCEx_GetPLL2ClockFreq>
  24751. pclk = pll2_clocks.PLL2_Q_Frequency;
  24752. 800b396: 9801 ldr r0, [sp, #4]
  24753. if (pclk != 0U)
  24754. 800b398: 2800 cmp r0, #0
  24755. 800b39a: d0eb beq.n 800b374 <UART_SetConfig+0x1cc>
  24756. usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
  24757. 800b39c: 6a65 ldr r5, [r4, #36] @ 0x24
  24758. 800b39e: 4b35 ldr r3, [pc, #212] @ (800b474 <UART_SetConfig+0x2cc>)
  24759. 800b3a0: 6862 ldr r2, [r4, #4]
  24760. 800b3a2: f833 1015 ldrh.w r1, [r3, r5, lsl #1]
  24761. 800b3a6: 0853 lsrs r3, r2, #1
  24762. 800b3a8: fbb0 f0f1 udiv r0, r0, r1
  24763. 800b3ac: eb03 0340 add.w r3, r3, r0, lsl #1
  24764. if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
  24765. 800b3b0: f64f 71ef movw r1, #65519 @ 0xffef
  24766. usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
  24767. 800b3b4: fbb3 f3f2 udiv r3, r3, r2
  24768. if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
  24769. 800b3b8: f1a3 0210 sub.w r2, r3, #16
  24770. 800b3bc: 428a cmp r2, r1
  24771. 800b3be: f63f af33 bhi.w 800b228 <UART_SetConfig+0x80>
  24772. brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
  24773. 800b3c2: f023 020f bic.w r2, r3, #15
  24774. brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
  24775. 800b3c6: f3c3 0342 ubfx r3, r3, #1, #3
  24776. huart->Instance->BRR = brrtemp;
  24777. 800b3ca: 6821 ldr r1, [r4, #0]
  24778. brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
  24779. 800b3cc: b292 uxth r2, r2
  24780. huart->Instance->BRR = brrtemp;
  24781. 800b3ce: 4313 orrs r3, r2
  24782. 800b3d0: 60cb str r3, [r1, #12]
  24783. 800b3d2: e7cf b.n 800b374 <UART_SetConfig+0x1cc>
  24784. pclk = (uint32_t) HSI_VALUE;
  24785. 800b3d4: 4825 ldr r0, [pc, #148] @ (800b46c <UART_SetConfig+0x2c4>)
  24786. 800b3d6: e7ba b.n 800b34e <UART_SetConfig+0x1a6>
  24787. pclk = HAL_RCC_GetPCLK1Freq();
  24788. 800b3d8: f7fc fd62 bl 8007ea0 <HAL_RCC_GetPCLK1Freq>
  24789. break;
  24790. 800b3dc: e7dc b.n 800b398 <UART_SetConfig+0x1f0>
  24791. else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
  24792. 800b3de: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
  24793. 800b3e2: d012 beq.n 800b40a <UART_SetConfig+0x262>
  24794. pclk = HAL_RCC_GetPCLK2Freq();
  24795. 800b3e4: f7fc fda4 bl 8007f30 <HAL_RCC_GetPCLK2Freq>
  24796. break;
  24797. 800b3e8: e795 b.n 800b316 <UART_SetConfig+0x16e>
  24798. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  24799. 800b3ea: 4b1f ldr r3, [pc, #124] @ (800b468 <UART_SetConfig+0x2c0>)
  24800. 800b3ec: 681a ldr r2, [r3, #0]
  24801. 800b3ee: 0691 lsls r1, r2, #26
  24802. 800b3f0: f140 808a bpl.w 800b508 <UART_SetConfig+0x360>
  24803. pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
  24804. 800b3f4: 681b ldr r3, [r3, #0]
  24805. 800b3f6: 481d ldr r0, [pc, #116] @ (800b46c <UART_SetConfig+0x2c4>)
  24806. 800b3f8: f3c3 03c1 ubfx r3, r3, #3, #2
  24807. 800b3fc: 40d8 lsrs r0, r3
  24808. if (pclk != 0U)
  24809. 800b3fe: e7ce b.n 800b39e <UART_SetConfig+0x1f6>
  24810. HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
  24811. 800b400: a803 add r0, sp, #12
  24812. 800b402: f7fd fee7 bl 80091d4 <HAL_RCCEx_GetPLL3ClockFreq>
  24813. pclk = pll3_clocks.PLL3_Q_Frequency;
  24814. 800b406: 9804 ldr r0, [sp, #16]
  24815. break;
  24816. 800b408: e7c6 b.n 800b398 <UART_SetConfig+0x1f0>
  24817. pclk = HAL_RCC_GetPCLK2Freq();
  24818. 800b40a: f7fc fd91 bl 8007f30 <HAL_RCC_GetPCLK2Freq>
  24819. break;
  24820. 800b40e: e7c3 b.n 800b398 <UART_SetConfig+0x1f0>
  24821. MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
  24822. 800b410: 6898 ldr r0, [r3, #8]
  24823. 800b412: 4a0c ldr r2, [pc, #48] @ (800b444 <UART_SetConfig+0x29c>)
  24824. 800b414: 4002 ands r2, r0
  24825. 800b416: 430a orrs r2, r1
  24826. UART_GETCLOCKSOURCE(huart, clocksource);
  24827. 800b418: 4913 ldr r1, [pc, #76] @ (800b468 <UART_SetConfig+0x2c0>)
  24828. MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
  24829. 800b41a: 609a str r2, [r3, #8]
  24830. MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
  24831. 800b41c: 6ada ldr r2, [r3, #44] @ 0x2c
  24832. 800b41e: f022 020f bic.w r2, r2, #15
  24833. 800b422: 432a orrs r2, r5
  24834. 800b424: 62da str r2, [r3, #44] @ 0x2c
  24835. UART_GETCLOCKSOURCE(huart, clocksource);
  24836. 800b426: 6d8b ldr r3, [r1, #88] @ 0x58
  24837. 800b428: f003 0307 and.w r3, r3, #7
  24838. 800b42c: 2b05 cmp r3, #5
  24839. 800b42e: f63f aefb bhi.w 800b228 <UART_SetConfig+0x80>
  24840. 800b432: e8df f003 tbb [pc, r3]
  24841. 800b436: 565b .short 0x565b
  24842. 800b438: 5e61214d .word 0x5e61214d
  24843. 800b43c: cfff69f3 .word 0xcfff69f3
  24844. 800b440: 58000c00 .word 0x58000c00
  24845. 800b444: 11fff4ff .word 0x11fff4ff
  24846. 800b448: 40011000 .word 0x40011000
  24847. 800b44c: 40004400 .word 0x40004400
  24848. 800b450: 40004800 .word 0x40004800
  24849. 800b454: 40004c00 .word 0x40004c00
  24850. 800b458: 40005000 .word 0x40005000
  24851. 800b45c: 40011400 .word 0x40011400
  24852. 800b460: 40007800 .word 0x40007800
  24853. 800b464: 40007c00 .word 0x40007c00
  24854. 800b468: 58024400 .word 0x58024400
  24855. 800b46c: 03d09000 .word 0x03d09000
  24856. 800b470: 003d0900 .word 0x003d0900
  24857. 800b474: 08011a2c .word 0x08011a2c
  24858. if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
  24859. 800b478: 4b24 ldr r3, [pc, #144] @ (800b50c <UART_SetConfig+0x364>)
  24860. 800b47a: 681a ldr r2, [r3, #0]
  24861. 800b47c: 0690 lsls r0, r2, #26
  24862. 800b47e: d43d bmi.n 800b4fc <UART_SetConfig+0x354>
  24863. pclk = (uint32_t) HSI_VALUE;
  24864. 800b480: 4823 ldr r0, [pc, #140] @ (800b510 <UART_SetConfig+0x368>)
  24865. lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
  24866. 800b482: 4b24 ldr r3, [pc, #144] @ (800b514 <UART_SetConfig+0x36c>)
  24867. if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
  24868. 800b484: 6866 ldr r6, [r4, #4]
  24869. lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
  24870. 800b486: f833 2015 ldrh.w r2, [r3, r5, lsl #1]
  24871. if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
  24872. 800b48a: eb06 0146 add.w r1, r6, r6, lsl #1
  24873. lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
  24874. 800b48e: fbb0 f3f2 udiv r3, r0, r2
  24875. if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
  24876. 800b492: 4299 cmp r1, r3
  24877. 800b494: f63f aec8 bhi.w 800b228 <UART_SetConfig+0x80>
  24878. 800b498: ebb3 3f06 cmp.w r3, r6, lsl #12
  24879. 800b49c: f63f aec4 bhi.w 800b228 <UART_SetConfig+0x80>
  24880. usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
  24881. 800b4a0: 2300 movs r3, #0
  24882. 800b4a2: 4619 mov r1, r3
  24883. 800b4a4: f7f4 ff74 bl 8000390 <__aeabi_uldivmod>
  24884. 800b4a8: 4632 mov r2, r6
  24885. 800b4aa: 0209 lsls r1, r1, #8
  24886. 800b4ac: 0203 lsls r3, r0, #8
  24887. 800b4ae: ea41 6110 orr.w r1, r1, r0, lsr #24
  24888. 800b4b2: 0870 lsrs r0, r6, #1
  24889. 800b4b4: 1818 adds r0, r3, r0
  24890. 800b4b6: f04f 0300 mov.w r3, #0
  24891. 800b4ba: f141 0100 adc.w r1, r1, #0
  24892. 800b4be: f7f4 ff67 bl 8000390 <__aeabi_uldivmod>
  24893. if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
  24894. 800b4c2: 4b15 ldr r3, [pc, #84] @ (800b518 <UART_SetConfig+0x370>)
  24895. 800b4c4: f5a0 7240 sub.w r2, r0, #768 @ 0x300
  24896. 800b4c8: 429a cmp r2, r3
  24897. 800b4ca: f63f aead bhi.w 800b228 <UART_SetConfig+0x80>
  24898. 800b4ce: e74f b.n 800b370 <UART_SetConfig+0x1c8>
  24899. HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
  24900. 800b4d0: a803 add r0, sp, #12
  24901. 800b4d2: f7fd fe7f bl 80091d4 <HAL_RCCEx_GetPLL3ClockFreq>
  24902. pclk = pll3_clocks.PLL3_Q_Frequency;
  24903. 800b4d6: 9804 ldr r0, [sp, #16]
  24904. if (pclk != 0U)
  24905. 800b4d8: 2800 cmp r0, #0
  24906. 800b4da: f43f af4b beq.w 800b374 <UART_SetConfig+0x1cc>
  24907. lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
  24908. 800b4de: 6a65 ldr r5, [r4, #36] @ 0x24
  24909. 800b4e0: e7cf b.n 800b482 <UART_SetConfig+0x2da>
  24910. HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
  24911. 800b4e2: 4668 mov r0, sp
  24912. 800b4e4: f7fd fddc bl 80090a0 <HAL_RCCEx_GetPLL2ClockFreq>
  24913. pclk = pll2_clocks.PLL2_Q_Frequency;
  24914. 800b4e8: 9801 ldr r0, [sp, #4]
  24915. break;
  24916. 800b4ea: e7f5 b.n 800b4d8 <UART_SetConfig+0x330>
  24917. pclk = HAL_RCCEx_GetD3PCLK1Freq();
  24918. 800b4ec: f7fd fdc6 bl 800907c <HAL_RCCEx_GetD3PCLK1Freq>
  24919. break;
  24920. 800b4f0: e7f2 b.n 800b4d8 <UART_SetConfig+0x330>
  24921. pclk = (uint32_t) LSE_VALUE;
  24922. 800b4f2: f44f 4000 mov.w r0, #32768 @ 0x8000
  24923. 800b4f6: e7c4 b.n 800b482 <UART_SetConfig+0x2da>
  24924. pclk = (uint32_t) CSI_VALUE;
  24925. 800b4f8: 4808 ldr r0, [pc, #32] @ (800b51c <UART_SetConfig+0x374>)
  24926. 800b4fa: e7c2 b.n 800b482 <UART_SetConfig+0x2da>
  24927. pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
  24928. 800b4fc: 681b ldr r3, [r3, #0]
  24929. 800b4fe: 4804 ldr r0, [pc, #16] @ (800b510 <UART_SetConfig+0x368>)
  24930. 800b500: f3c3 03c1 ubfx r3, r3, #3, #2
  24931. 800b504: 40d8 lsrs r0, r3
  24932. if (pclk != 0U)
  24933. 800b506: e7bc b.n 800b482 <UART_SetConfig+0x2da>
  24934. pclk = (uint32_t) HSI_VALUE;
  24935. 800b508: 4801 ldr r0, [pc, #4] @ (800b510 <UART_SetConfig+0x368>)
  24936. 800b50a: e748 b.n 800b39e <UART_SetConfig+0x1f6>
  24937. 800b50c: 58024400 .word 0x58024400
  24938. 800b510: 03d09000 .word 0x03d09000
  24939. 800b514: 08011a2c .word 0x08011a2c
  24940. 800b518: 000ffcff .word 0x000ffcff
  24941. 800b51c: 003d0900 .word 0x003d0900
  24942. 0800b520 <UART_AdvFeatureConfig>:
  24943. if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
  24944. 800b520: 6a83 ldr r3, [r0, #40] @ 0x28
  24945. 800b522: 071a lsls r2, r3, #28
  24946. {
  24947. 800b524: b410 push {r4}
  24948. if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
  24949. 800b526: d506 bpl.n 800b536 <UART_AdvFeatureConfig+0x16>
  24950. MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
  24951. 800b528: 6801 ldr r1, [r0, #0]
  24952. 800b52a: 6b84 ldr r4, [r0, #56] @ 0x38
  24953. 800b52c: 684a ldr r2, [r1, #4]
  24954. 800b52e: f422 4200 bic.w r2, r2, #32768 @ 0x8000
  24955. 800b532: 4322 orrs r2, r4
  24956. 800b534: 604a str r2, [r1, #4]
  24957. if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
  24958. 800b536: 07dc lsls r4, r3, #31
  24959. 800b538: d506 bpl.n 800b548 <UART_AdvFeatureConfig+0x28>
  24960. MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
  24961. 800b53a: 6801 ldr r1, [r0, #0]
  24962. 800b53c: 6ac4 ldr r4, [r0, #44] @ 0x2c
  24963. 800b53e: 684a ldr r2, [r1, #4]
  24964. 800b540: f422 3200 bic.w r2, r2, #131072 @ 0x20000
  24965. 800b544: 4322 orrs r2, r4
  24966. 800b546: 604a str r2, [r1, #4]
  24967. if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
  24968. 800b548: 0799 lsls r1, r3, #30
  24969. 800b54a: d506 bpl.n 800b55a <UART_AdvFeatureConfig+0x3a>
  24970. MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
  24971. 800b54c: 6801 ldr r1, [r0, #0]
  24972. 800b54e: 6b04 ldr r4, [r0, #48] @ 0x30
  24973. 800b550: 684a ldr r2, [r1, #4]
  24974. 800b552: f422 3280 bic.w r2, r2, #65536 @ 0x10000
  24975. 800b556: 4322 orrs r2, r4
  24976. 800b558: 604a str r2, [r1, #4]
  24977. if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
  24978. 800b55a: 075a lsls r2, r3, #29
  24979. 800b55c: d506 bpl.n 800b56c <UART_AdvFeatureConfig+0x4c>
  24980. MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
  24981. 800b55e: 6801 ldr r1, [r0, #0]
  24982. 800b560: 6b44 ldr r4, [r0, #52] @ 0x34
  24983. 800b562: 684a ldr r2, [r1, #4]
  24984. 800b564: f422 2280 bic.w r2, r2, #262144 @ 0x40000
  24985. 800b568: 4322 orrs r2, r4
  24986. 800b56a: 604a str r2, [r1, #4]
  24987. if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
  24988. 800b56c: 06dc lsls r4, r3, #27
  24989. 800b56e: d506 bpl.n 800b57e <UART_AdvFeatureConfig+0x5e>
  24990. MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
  24991. 800b570: 6801 ldr r1, [r0, #0]
  24992. 800b572: 6bc4 ldr r4, [r0, #60] @ 0x3c
  24993. 800b574: 688a ldr r2, [r1, #8]
  24994. 800b576: f422 5280 bic.w r2, r2, #4096 @ 0x1000
  24995. 800b57a: 4322 orrs r2, r4
  24996. 800b57c: 608a str r2, [r1, #8]
  24997. if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
  24998. 800b57e: 0699 lsls r1, r3, #26
  24999. 800b580: d506 bpl.n 800b590 <UART_AdvFeatureConfig+0x70>
  25000. MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
  25001. 800b582: 6801 ldr r1, [r0, #0]
  25002. 800b584: 6c04 ldr r4, [r0, #64] @ 0x40
  25003. 800b586: 688a ldr r2, [r1, #8]
  25004. 800b588: f422 5200 bic.w r2, r2, #8192 @ 0x2000
  25005. 800b58c: 4322 orrs r2, r4
  25006. 800b58e: 608a str r2, [r1, #8]
  25007. if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
  25008. 800b590: 065a lsls r2, r3, #25
  25009. 800b592: d50a bpl.n 800b5aa <UART_AdvFeatureConfig+0x8a>
  25010. MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
  25011. 800b594: 6801 ldr r1, [r0, #0]
  25012. 800b596: 6c44 ldr r4, [r0, #68] @ 0x44
  25013. 800b598: 684a ldr r2, [r1, #4]
  25014. if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
  25015. 800b59a: f5b4 1f80 cmp.w r4, #1048576 @ 0x100000
  25016. MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
  25017. 800b59e: f422 1280 bic.w r2, r2, #1048576 @ 0x100000
  25018. 800b5a2: ea42 0204 orr.w r2, r2, r4
  25019. 800b5a6: 604a str r2, [r1, #4]
  25020. if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
  25021. 800b5a8: d00b beq.n 800b5c2 <UART_AdvFeatureConfig+0xa2>
  25022. if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
  25023. 800b5aa: 061b lsls r3, r3, #24
  25024. 800b5ac: d506 bpl.n 800b5bc <UART_AdvFeatureConfig+0x9c>
  25025. MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
  25026. 800b5ae: 6802 ldr r2, [r0, #0]
  25027. 800b5b0: 6cc1 ldr r1, [r0, #76] @ 0x4c
  25028. 800b5b2: 6853 ldr r3, [r2, #4]
  25029. 800b5b4: f423 2300 bic.w r3, r3, #524288 @ 0x80000
  25030. 800b5b8: 430b orrs r3, r1
  25031. 800b5ba: 6053 str r3, [r2, #4]
  25032. }
  25033. 800b5bc: f85d 4b04 ldr.w r4, [sp], #4
  25034. 800b5c0: 4770 bx lr
  25035. MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
  25036. 800b5c2: 684a ldr r2, [r1, #4]
  25037. 800b5c4: 6c84 ldr r4, [r0, #72] @ 0x48
  25038. 800b5c6: f422 02c0 bic.w r2, r2, #6291456 @ 0x600000
  25039. 800b5ca: 4322 orrs r2, r4
  25040. 800b5cc: 604a str r2, [r1, #4]
  25041. 800b5ce: e7ec b.n 800b5aa <UART_AdvFeatureConfig+0x8a>
  25042. 0800b5d0 <UART_CheckIdleState>:
  25043. {
  25044. 800b5d0: b538 push {r3, r4, r5, lr}
  25045. huart->ErrorCode = HAL_UART_ERROR_NONE;
  25046. 800b5d2: 2300 movs r3, #0
  25047. {
  25048. 800b5d4: 4604 mov r4, r0
  25049. huart->ErrorCode = HAL_UART_ERROR_NONE;
  25050. 800b5d6: f8c0 3090 str.w r3, [r0, #144] @ 0x90
  25051. tickstart = HAL_GetTick();
  25052. 800b5da: f7f8 fcf9 bl 8003fd0 <HAL_GetTick>
  25053. if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
  25054. 800b5de: 6822 ldr r2, [r4, #0]
  25055. tickstart = HAL_GetTick();
  25056. 800b5e0: 4605 mov r5, r0
  25057. if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
  25058. 800b5e2: 6813 ldr r3, [r2, #0]
  25059. 800b5e4: 071b lsls r3, r3, #28
  25060. 800b5e6: d40f bmi.n 800b608 <UART_CheckIdleState+0x38>
  25061. if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
  25062. 800b5e8: 6813 ldr r3, [r2, #0]
  25063. 800b5ea: 0759 lsls r1, r3, #29
  25064. 800b5ec: d431 bmi.n 800b652 <UART_CheckIdleState+0x82>
  25065. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  25066. 800b5ee: 2300 movs r3, #0
  25067. huart->gState = HAL_UART_STATE_READY;
  25068. 800b5f0: 2220 movs r2, #32
  25069. return HAL_OK;
  25070. 800b5f2: 4618 mov r0, r3
  25071. huart->gState = HAL_UART_STATE_READY;
  25072. 800b5f4: f8c4 2088 str.w r2, [r4, #136] @ 0x88
  25073. huart->RxState = HAL_UART_STATE_READY;
  25074. 800b5f8: f8c4 208c str.w r2, [r4, #140] @ 0x8c
  25075. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  25076. 800b5fc: 66e3 str r3, [r4, #108] @ 0x6c
  25077. huart->RxEventType = HAL_UART_RXEVENT_TC;
  25078. 800b5fe: 6723 str r3, [r4, #112] @ 0x70
  25079. __HAL_UNLOCK(huart);
  25080. 800b600: 2300 movs r3, #0
  25081. 800b602: f884 3084 strb.w r3, [r4, #132] @ 0x84
  25082. }
  25083. 800b606: bd38 pop {r3, r4, r5, pc}
  25084. while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
  25085. 800b608: 69d3 ldr r3, [r2, #28]
  25086. 800b60a: 0298 lsls r0, r3, #10
  25087. 800b60c: d4ec bmi.n 800b5e8 <UART_CheckIdleState+0x18>
  25088. 800b60e: e00c b.n 800b62a <UART_CheckIdleState+0x5a>
  25089. if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
  25090. 800b610: 6819 ldr r1, [r3, #0]
  25091. 800b612: 461a mov r2, r3
  25092. 800b614: 0749 lsls r1, r1, #29
  25093. 800b616: d505 bpl.n 800b624 <UART_CheckIdleState+0x54>
  25094. if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
  25095. 800b618: 69d9 ldr r1, [r3, #28]
  25096. 800b61a: 0708 lsls r0, r1, #28
  25097. 800b61c: d44a bmi.n 800b6b4 <UART_CheckIdleState+0xe4>
  25098. if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
  25099. 800b61e: 69d9 ldr r1, [r3, #28]
  25100. 800b620: 0509 lsls r1, r1, #20
  25101. 800b622: d475 bmi.n 800b710 <UART_CheckIdleState+0x140>
  25102. while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
  25103. 800b624: 69db ldr r3, [r3, #28]
  25104. 800b626: 0298 lsls r0, r3, #10
  25105. 800b628: d4de bmi.n 800b5e8 <UART_CheckIdleState+0x18>
  25106. if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
  25107. 800b62a: f7f8 fcd1 bl 8003fd0 <HAL_GetTick>
  25108. 800b62e: 1b43 subs r3, r0, r5
  25109. 800b630: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
  25110. if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
  25111. 800b634: 6823 ldr r3, [r4, #0]
  25112. if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
  25113. 800b636: d3eb bcc.n 800b610 <UART_CheckIdleState+0x40>
  25114. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25115. 800b638: e853 2f00 ldrex r2, [r3]
  25116. ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
  25117. 800b63c: f022 0280 bic.w r2, r2, #128 @ 0x80
  25118. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25119. 800b640: e843 2100 strex r1, r2, [r3]
  25120. 800b644: 2900 cmp r1, #0
  25121. 800b646: d1f7 bne.n 800b638 <UART_CheckIdleState+0x68>
  25122. huart->gState = HAL_UART_STATE_READY;
  25123. 800b648: 2320 movs r3, #32
  25124. 800b64a: f8c4 3088 str.w r3, [r4, #136] @ 0x88
  25125. return HAL_TIMEOUT;
  25126. 800b64e: 2003 movs r0, #3
  25127. 800b650: e7d6 b.n 800b600 <UART_CheckIdleState+0x30>
  25128. while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
  25129. 800b652: 69d3 ldr r3, [r2, #28]
  25130. 800b654: 025b lsls r3, r3, #9
  25131. 800b656: d4ca bmi.n 800b5ee <UART_CheckIdleState+0x1e>
  25132. 800b658: e00d b.n 800b676 <UART_CheckIdleState+0xa6>
  25133. if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
  25134. 800b65a: 681a ldr r2, [r3, #0]
  25135. 800b65c: 0750 lsls r0, r2, #29
  25136. 800b65e: d507 bpl.n 800b670 <UART_CheckIdleState+0xa0>
  25137. if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
  25138. 800b660: 69da ldr r2, [r3, #28]
  25139. 800b662: 0711 lsls r1, r2, #28
  25140. 800b664: f100 8082 bmi.w 800b76c <UART_CheckIdleState+0x19c>
  25141. if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
  25142. 800b668: 69da ldr r2, [r3, #28]
  25143. 800b66a: 0512 lsls r2, r2, #20
  25144. 800b66c: f100 80ac bmi.w 800b7c8 <UART_CheckIdleState+0x1f8>
  25145. while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
  25146. 800b670: 69db ldr r3, [r3, #28]
  25147. 800b672: 025b lsls r3, r3, #9
  25148. 800b674: d4bb bmi.n 800b5ee <UART_CheckIdleState+0x1e>
  25149. if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
  25150. 800b676: f7f8 fcab bl 8003fd0 <HAL_GetTick>
  25151. 800b67a: 1b43 subs r3, r0, r5
  25152. 800b67c: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
  25153. 800b680: 6823 ldr r3, [r4, #0]
  25154. 800b682: d3ea bcc.n 800b65a <UART_CheckIdleState+0x8a>
  25155. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25156. 800b684: e853 2f00 ldrex r2, [r3]
  25157. ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
  25158. 800b688: f422 7290 bic.w r2, r2, #288 @ 0x120
  25159. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25160. 800b68c: e843 2100 strex r1, r2, [r3]
  25161. 800b690: 2900 cmp r1, #0
  25162. 800b692: d1f7 bne.n 800b684 <UART_CheckIdleState+0xb4>
  25163. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25164. 800b694: f103 0208 add.w r2, r3, #8
  25165. 800b698: e852 2f00 ldrex r2, [r2]
  25166. ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
  25167. 800b69c: f022 0201 bic.w r2, r2, #1
  25168. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25169. 800b6a0: f103 0008 add.w r0, r3, #8
  25170. 800b6a4: e840 2100 strex r1, r2, [r0]
  25171. 800b6a8: 2900 cmp r1, #0
  25172. 800b6aa: d1f3 bne.n 800b694 <UART_CheckIdleState+0xc4>
  25173. huart->RxState = HAL_UART_STATE_READY;
  25174. 800b6ac: 2320 movs r3, #32
  25175. 800b6ae: f8c4 308c str.w r3, [r4, #140] @ 0x8c
  25176. return HAL_TIMEOUT;
  25177. 800b6b2: e7cc b.n 800b64e <UART_CheckIdleState+0x7e>
  25178. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
  25179. 800b6b4: 2208 movs r2, #8
  25180. 800b6b6: 621a str r2, [r3, #32]
  25181. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25182. 800b6b8: e853 2f00 ldrex r2, [r3]
  25183. ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
  25184. 800b6bc: f422 7290 bic.w r2, r2, #288 @ 0x120
  25185. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25186. 800b6c0: e843 2100 strex r1, r2, [r3]
  25187. 800b6c4: 2900 cmp r1, #0
  25188. 800b6c6: d1f7 bne.n 800b6b8 <UART_CheckIdleState+0xe8>
  25189. ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
  25190. 800b6c8: 4856 ldr r0, [pc, #344] @ (800b824 <UART_CheckIdleState+0x254>)
  25191. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25192. 800b6ca: f103 0208 add.w r2, r3, #8
  25193. 800b6ce: e852 2f00 ldrex r2, [r2]
  25194. 800b6d2: 4002 ands r2, r0
  25195. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25196. 800b6d4: f103 0508 add.w r5, r3, #8
  25197. 800b6d8: e845 2100 strex r1, r2, [r5]
  25198. 800b6dc: 2900 cmp r1, #0
  25199. 800b6de: d1f4 bne.n 800b6ca <UART_CheckIdleState+0xfa>
  25200. if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
  25201. 800b6e0: 6ee2 ldr r2, [r4, #108] @ 0x6c
  25202. 800b6e2: 2a01 cmp r2, #1
  25203. 800b6e4: d00b beq.n 800b6fe <UART_CheckIdleState+0x12e>
  25204. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  25205. 800b6e6: 2200 movs r2, #0
  25206. huart->RxState = HAL_UART_STATE_READY;
  25207. 800b6e8: 2020 movs r0, #32
  25208. huart->ErrorCode = HAL_UART_ERROR_ORE;
  25209. 800b6ea: 2108 movs r1, #8
  25210. huart->RxState = HAL_UART_STATE_READY;
  25211. 800b6ec: f8c4 008c str.w r0, [r4, #140] @ 0x8c
  25212. huart->RxISR = NULL;
  25213. 800b6f0: 6762 str r2, [r4, #116] @ 0x74
  25214. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  25215. 800b6f2: 66e2 str r2, [r4, #108] @ 0x6c
  25216. __HAL_UNLOCK(huart);
  25217. 800b6f4: f884 2084 strb.w r2, [r4, #132] @ 0x84
  25218. huart->ErrorCode = HAL_UART_ERROR_ORE;
  25219. 800b6f8: f8c4 1090 str.w r1, [r4, #144] @ 0x90
  25220. return HAL_ERROR;
  25221. 800b6fc: e79c b.n 800b638 <UART_CheckIdleState+0x68>
  25222. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25223. 800b6fe: e853 2f00 ldrex r2, [r3]
  25224. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  25225. 800b702: f022 0210 bic.w r2, r2, #16
  25226. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25227. 800b706: e843 2100 strex r1, r2, [r3]
  25228. 800b70a: 2900 cmp r1, #0
  25229. 800b70c: d1f7 bne.n 800b6fe <UART_CheckIdleState+0x12e>
  25230. 800b70e: e7ea b.n 800b6e6 <UART_CheckIdleState+0x116>
  25231. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
  25232. 800b710: f44f 6200 mov.w r2, #2048 @ 0x800
  25233. 800b714: 621a str r2, [r3, #32]
  25234. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25235. 800b716: e853 2f00 ldrex r2, [r3]
  25236. ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
  25237. 800b71a: f422 7290 bic.w r2, r2, #288 @ 0x120
  25238. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25239. 800b71e: e843 2100 strex r1, r2, [r3]
  25240. 800b722: 2900 cmp r1, #0
  25241. 800b724: d1f7 bne.n 800b716 <UART_CheckIdleState+0x146>
  25242. ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
  25243. 800b726: 483f ldr r0, [pc, #252] @ (800b824 <UART_CheckIdleState+0x254>)
  25244. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25245. 800b728: f103 0208 add.w r2, r3, #8
  25246. 800b72c: e852 2f00 ldrex r2, [r2]
  25247. 800b730: 4002 ands r2, r0
  25248. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25249. 800b732: f103 0508 add.w r5, r3, #8
  25250. 800b736: e845 2100 strex r1, r2, [r5]
  25251. 800b73a: 2900 cmp r1, #0
  25252. 800b73c: d1f4 bne.n 800b728 <UART_CheckIdleState+0x158>
  25253. if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
  25254. 800b73e: 6ee2 ldr r2, [r4, #108] @ 0x6c
  25255. 800b740: 2a01 cmp r2, #1
  25256. 800b742: d00a beq.n 800b75a <UART_CheckIdleState+0x18a>
  25257. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  25258. 800b744: 2200 movs r2, #0
  25259. huart->RxState = HAL_UART_STATE_READY;
  25260. 800b746: 2120 movs r1, #32
  25261. huart->RxISR = NULL;
  25262. 800b748: 6762 str r2, [r4, #116] @ 0x74
  25263. huart->RxState = HAL_UART_STATE_READY;
  25264. 800b74a: f8c4 108c str.w r1, [r4, #140] @ 0x8c
  25265. __HAL_UNLOCK(huart);
  25266. 800b74e: f884 2084 strb.w r2, [r4, #132] @ 0x84
  25267. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  25268. 800b752: 66e2 str r2, [r4, #108] @ 0x6c
  25269. huart->ErrorCode = HAL_UART_ERROR_RTO;
  25270. 800b754: f8c4 1090 str.w r1, [r4, #144] @ 0x90
  25271. return HAL_TIMEOUT;
  25272. 800b758: e76e b.n 800b638 <UART_CheckIdleState+0x68>
  25273. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25274. 800b75a: e853 2f00 ldrex r2, [r3]
  25275. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  25276. 800b75e: f022 0210 bic.w r2, r2, #16
  25277. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25278. 800b762: e843 2100 strex r1, r2, [r3]
  25279. 800b766: 2900 cmp r1, #0
  25280. 800b768: d1f7 bne.n 800b75a <UART_CheckIdleState+0x18a>
  25281. 800b76a: e7eb b.n 800b744 <UART_CheckIdleState+0x174>
  25282. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
  25283. 800b76c: 2208 movs r2, #8
  25284. 800b76e: 621a str r2, [r3, #32]
  25285. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25286. 800b770: e853 2f00 ldrex r2, [r3]
  25287. ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
  25288. 800b774: f422 7290 bic.w r2, r2, #288 @ 0x120
  25289. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25290. 800b778: e843 2100 strex r1, r2, [r3]
  25291. 800b77c: 2900 cmp r1, #0
  25292. 800b77e: d1f7 bne.n 800b770 <UART_CheckIdleState+0x1a0>
  25293. ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
  25294. 800b780: 4828 ldr r0, [pc, #160] @ (800b824 <UART_CheckIdleState+0x254>)
  25295. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25296. 800b782: f103 0208 add.w r2, r3, #8
  25297. 800b786: e852 2f00 ldrex r2, [r2]
  25298. 800b78a: 4002 ands r2, r0
  25299. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25300. 800b78c: f103 0508 add.w r5, r3, #8
  25301. 800b790: e845 2100 strex r1, r2, [r5]
  25302. 800b794: 2900 cmp r1, #0
  25303. 800b796: d1f4 bne.n 800b782 <UART_CheckIdleState+0x1b2>
  25304. if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
  25305. 800b798: 6ee2 ldr r2, [r4, #108] @ 0x6c
  25306. 800b79a: 2a01 cmp r2, #1
  25307. 800b79c: d00b beq.n 800b7b6 <UART_CheckIdleState+0x1e6>
  25308. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  25309. 800b79e: 2200 movs r2, #0
  25310. huart->RxState = HAL_UART_STATE_READY;
  25311. 800b7a0: 2020 movs r0, #32
  25312. huart->ErrorCode = HAL_UART_ERROR_ORE;
  25313. 800b7a2: 2108 movs r1, #8
  25314. huart->RxState = HAL_UART_STATE_READY;
  25315. 800b7a4: f8c4 008c str.w r0, [r4, #140] @ 0x8c
  25316. huart->RxISR = NULL;
  25317. 800b7a8: 6762 str r2, [r4, #116] @ 0x74
  25318. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  25319. 800b7aa: 66e2 str r2, [r4, #108] @ 0x6c
  25320. __HAL_UNLOCK(huart);
  25321. 800b7ac: f884 2084 strb.w r2, [r4, #132] @ 0x84
  25322. huart->ErrorCode = HAL_UART_ERROR_ORE;
  25323. 800b7b0: f8c4 1090 str.w r1, [r4, #144] @ 0x90
  25324. return HAL_ERROR;
  25325. 800b7b4: e766 b.n 800b684 <UART_CheckIdleState+0xb4>
  25326. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25327. 800b7b6: e853 2f00 ldrex r2, [r3]
  25328. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  25329. 800b7ba: f022 0210 bic.w r2, r2, #16
  25330. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25331. 800b7be: e843 2100 strex r1, r2, [r3]
  25332. 800b7c2: 2900 cmp r1, #0
  25333. 800b7c4: d1f7 bne.n 800b7b6 <UART_CheckIdleState+0x1e6>
  25334. 800b7c6: e7ea b.n 800b79e <UART_CheckIdleState+0x1ce>
  25335. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
  25336. 800b7c8: f44f 6200 mov.w r2, #2048 @ 0x800
  25337. 800b7cc: 621a str r2, [r3, #32]
  25338. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25339. 800b7ce: e853 2f00 ldrex r2, [r3]
  25340. ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
  25341. 800b7d2: f422 7290 bic.w r2, r2, #288 @ 0x120
  25342. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25343. 800b7d6: e843 2100 strex r1, r2, [r3]
  25344. 800b7da: 2900 cmp r1, #0
  25345. 800b7dc: d1f7 bne.n 800b7ce <UART_CheckIdleState+0x1fe>
  25346. ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
  25347. 800b7de: 4811 ldr r0, [pc, #68] @ (800b824 <UART_CheckIdleState+0x254>)
  25348. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25349. 800b7e0: f103 0208 add.w r2, r3, #8
  25350. 800b7e4: e852 2f00 ldrex r2, [r2]
  25351. 800b7e8: 4002 ands r2, r0
  25352. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25353. 800b7ea: f103 0508 add.w r5, r3, #8
  25354. 800b7ee: e845 2100 strex r1, r2, [r5]
  25355. 800b7f2: 2900 cmp r1, #0
  25356. 800b7f4: d1f4 bne.n 800b7e0 <UART_CheckIdleState+0x210>
  25357. if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
  25358. 800b7f6: 6ee2 ldr r2, [r4, #108] @ 0x6c
  25359. 800b7f8: 2a01 cmp r2, #1
  25360. 800b7fa: d00a beq.n 800b812 <UART_CheckIdleState+0x242>
  25361. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  25362. 800b7fc: 2200 movs r2, #0
  25363. huart->RxState = HAL_UART_STATE_READY;
  25364. 800b7fe: 2120 movs r1, #32
  25365. huart->RxISR = NULL;
  25366. 800b800: 6762 str r2, [r4, #116] @ 0x74
  25367. huart->RxState = HAL_UART_STATE_READY;
  25368. 800b802: f8c4 108c str.w r1, [r4, #140] @ 0x8c
  25369. __HAL_UNLOCK(huart);
  25370. 800b806: f884 2084 strb.w r2, [r4, #132] @ 0x84
  25371. huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
  25372. 800b80a: 66e2 str r2, [r4, #108] @ 0x6c
  25373. huart->ErrorCode = HAL_UART_ERROR_RTO;
  25374. 800b80c: f8c4 1090 str.w r1, [r4, #144] @ 0x90
  25375. return HAL_TIMEOUT;
  25376. 800b810: e738 b.n 800b684 <UART_CheckIdleState+0xb4>
  25377. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25378. 800b812: e853 2f00 ldrex r2, [r3]
  25379. ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  25380. 800b816: f022 0210 bic.w r2, r2, #16
  25381. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25382. 800b81a: e843 2100 strex r1, r2, [r3]
  25383. 800b81e: 2900 cmp r1, #0
  25384. 800b820: d1f7 bne.n 800b812 <UART_CheckIdleState+0x242>
  25385. 800b822: e7eb b.n 800b7fc <UART_CheckIdleState+0x22c>
  25386. 800b824: effffffe .word 0xeffffffe
  25387. 0800b828 <HAL_UART_Init>:
  25388. if (huart == NULL)
  25389. 800b828: b380 cbz r0, 800b88c <HAL_UART_Init+0x64>
  25390. if (huart->gState == HAL_UART_STATE_RESET)
  25391. 800b82a: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88
  25392. {
  25393. 800b82e: b510 push {r4, lr}
  25394. 800b830: 4604 mov r4, r0
  25395. if (huart->gState == HAL_UART_STATE_RESET)
  25396. 800b832: b333 cbz r3, 800b882 <HAL_UART_Init+0x5a>
  25397. __HAL_UART_DISABLE(huart);
  25398. 800b834: 6822 ldr r2, [r4, #0]
  25399. huart->gState = HAL_UART_STATE_BUSY;
  25400. 800b836: 2324 movs r3, #36 @ 0x24
  25401. if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
  25402. 800b838: 6aa1 ldr r1, [r4, #40] @ 0x28
  25403. huart->gState = HAL_UART_STATE_BUSY;
  25404. 800b83a: f8c4 3088 str.w r3, [r4, #136] @ 0x88
  25405. __HAL_UART_DISABLE(huart);
  25406. 800b83e: 6813 ldr r3, [r2, #0]
  25407. 800b840: f023 0301 bic.w r3, r3, #1
  25408. 800b844: 6013 str r3, [r2, #0]
  25409. if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
  25410. 800b846: b9c1 cbnz r1, 800b87a <HAL_UART_Init+0x52>
  25411. if (UART_SetConfig(huart) == HAL_ERROR)
  25412. 800b848: 4620 mov r0, r4
  25413. 800b84a: f7ff fcad bl 800b1a8 <UART_SetConfig>
  25414. 800b84e: 2801 cmp r0, #1
  25415. 800b850: d011 beq.n 800b876 <HAL_UART_Init+0x4e>
  25416. CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
  25417. 800b852: 6823 ldr r3, [r4, #0]
  25418. return (UART_CheckIdleState(huart));
  25419. 800b854: 4620 mov r0, r4
  25420. CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
  25421. 800b856: 685a ldr r2, [r3, #4]
  25422. 800b858: f422 4290 bic.w r2, r2, #18432 @ 0x4800
  25423. 800b85c: 605a str r2, [r3, #4]
  25424. CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
  25425. 800b85e: 689a ldr r2, [r3, #8]
  25426. 800b860: f022 022a bic.w r2, r2, #42 @ 0x2a
  25427. 800b864: 609a str r2, [r3, #8]
  25428. __HAL_UART_ENABLE(huart);
  25429. 800b866: 681a ldr r2, [r3, #0]
  25430. 800b868: f042 0201 orr.w r2, r2, #1
  25431. }
  25432. 800b86c: e8bd 4010 ldmia.w sp!, {r4, lr}
  25433. __HAL_UART_ENABLE(huart);
  25434. 800b870: 601a str r2, [r3, #0]
  25435. return (UART_CheckIdleState(huart));
  25436. 800b872: f7ff bead b.w 800b5d0 <UART_CheckIdleState>
  25437. }
  25438. 800b876: 2001 movs r0, #1
  25439. 800b878: bd10 pop {r4, pc}
  25440. UART_AdvFeatureConfig(huart);
  25441. 800b87a: 4620 mov r0, r4
  25442. 800b87c: f7ff fe50 bl 800b520 <UART_AdvFeatureConfig>
  25443. 800b880: e7e2 b.n 800b848 <HAL_UART_Init+0x20>
  25444. huart->Lock = HAL_UNLOCKED;
  25445. 800b882: f880 3084 strb.w r3, [r0, #132] @ 0x84
  25446. HAL_UART_MspInit(huart);
  25447. 800b886: f7f7 fab3 bl 8002df0 <HAL_UART_MspInit>
  25448. 800b88a: e7d3 b.n 800b834 <HAL_UART_Init+0xc>
  25449. }
  25450. 800b88c: 2001 movs r0, #1
  25451. 800b88e: 4770 bx lr
  25452. 0800b890 <UART_Start_Receive_IT>:
  25453. {
  25454. 800b890: b430 push {r4, r5}
  25455. UART_MASK_COMPUTATION(huart);
  25456. 800b892: 6884 ldr r4, [r0, #8]
  25457. huart->RxISR = NULL;
  25458. 800b894: 2300 movs r3, #0
  25459. huart->pRxBuffPtr = pData;
  25460. 800b896: 6581 str r1, [r0, #88] @ 0x58
  25461. UART_MASK_COMPUTATION(huart);
  25462. 800b898: f5b4 5f80 cmp.w r4, #4096 @ 0x1000
  25463. huart->RxXferSize = Size;
  25464. 800b89c: f8a0 205c strh.w r2, [r0, #92] @ 0x5c
  25465. huart->RxXferCount = Size;
  25466. 800b8a0: f8a0 205e strh.w r2, [r0, #94] @ 0x5e
  25467. huart->RxISR = NULL;
  25468. 800b8a4: 6743 str r3, [r0, #116] @ 0x74
  25469. UART_MASK_COMPUTATION(huart);
  25470. 800b8a6: d04f beq.n 800b948 <UART_Start_Receive_IT+0xb8>
  25471. 800b8a8: bb84 cbnz r4, 800b90c <UART_Start_Receive_IT+0x7c>
  25472. 800b8aa: 6903 ldr r3, [r0, #16]
  25473. 800b8ac: 2b00 cmp r3, #0
  25474. 800b8ae: bf14 ite ne
  25475. 800b8b0: 237f movne r3, #127 @ 0x7f
  25476. 800b8b2: 23ff moveq r3, #255 @ 0xff
  25477. huart->ErrorCode = HAL_UART_ERROR_NONE;
  25478. 800b8b4: 2100 movs r1, #0
  25479. huart->RxState = HAL_UART_STATE_BUSY_RX;
  25480. 800b8b6: 2422 movs r4, #34 @ 0x22
  25481. UART_MASK_COMPUTATION(huart);
  25482. 800b8b8: f8a0 3060 strh.w r3, [r0, #96] @ 0x60
  25483. huart->ErrorCode = HAL_UART_ERROR_NONE;
  25484. 800b8bc: f8c0 1090 str.w r1, [r0, #144] @ 0x90
  25485. huart->RxState = HAL_UART_STATE_BUSY_RX;
  25486. 800b8c0: 6801 ldr r1, [r0, #0]
  25487. 800b8c2: f8c0 408c str.w r4, [r0, #140] @ 0x8c
  25488. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25489. 800b8c6: f101 0308 add.w r3, r1, #8
  25490. 800b8ca: e853 3f00 ldrex r3, [r3]
  25491. ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
  25492. 800b8ce: f043 0301 orr.w r3, r3, #1
  25493. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25494. 800b8d2: f101 0508 add.w r5, r1, #8
  25495. 800b8d6: e845 3400 strex r4, r3, [r5]
  25496. 800b8da: 2c00 cmp r4, #0
  25497. 800b8dc: d1f3 bne.n 800b8c6 <UART_Start_Receive_IT+0x36>
  25498. if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
  25499. 800b8de: 6e43 ldr r3, [r0, #100] @ 0x64
  25500. if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
  25501. 800b8e0: 6885 ldr r5, [r0, #8]
  25502. if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
  25503. 800b8e2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
  25504. if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
  25505. 800b8e6: 6904 ldr r4, [r0, #16]
  25506. if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
  25507. 800b8e8: d035 beq.n 800b956 <UART_Start_Receive_IT+0xc6>
  25508. if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
  25509. 800b8ea: f5b5 5f80 cmp.w r5, #4096 @ 0x1000
  25510. 800b8ee: d016 beq.n 800b91e <UART_Start_Receive_IT+0x8e>
  25511. 800b8f0: 4b32 ldr r3, [pc, #200] @ (800b9bc <UART_Start_Receive_IT+0x12c>)
  25512. 800b8f2: 6743 str r3, [r0, #116] @ 0x74
  25513. if (huart->Init.Parity != UART_PARITY_NONE)
  25514. 800b8f4: b1bc cbz r4, 800b926 <UART_Start_Receive_IT+0x96>
  25515. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25516. 800b8f6: e851 3f00 ldrex r3, [r1]
  25517. ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
  25518. 800b8fa: f443 7390 orr.w r3, r3, #288 @ 0x120
  25519. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25520. 800b8fe: e841 3200 strex r2, r3, [r1]
  25521. 800b902: 2a00 cmp r2, #0
  25522. 800b904: d1f7 bne.n 800b8f6 <UART_Start_Receive_IT+0x66>
  25523. }
  25524. 800b906: 2000 movs r0, #0
  25525. 800b908: bc30 pop {r4, r5}
  25526. 800b90a: 4770 bx lr
  25527. UART_MASK_COMPUTATION(huart);
  25528. 800b90c: f1b4 5f80 cmp.w r4, #268435456 @ 0x10000000
  25529. 800b910: d1d0 bne.n 800b8b4 <UART_Start_Receive_IT+0x24>
  25530. 800b912: 6903 ldr r3, [r0, #16]
  25531. 800b914: 2b00 cmp r3, #0
  25532. 800b916: bf14 ite ne
  25533. 800b918: 233f movne r3, #63 @ 0x3f
  25534. 800b91a: 237f moveq r3, #127 @ 0x7f
  25535. 800b91c: e7ca b.n 800b8b4 <UART_Start_Receive_IT+0x24>
  25536. if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
  25537. 800b91e: 2c00 cmp r4, #0
  25538. 800b920: d146 bne.n 800b9b0 <UART_Start_Receive_IT+0x120>
  25539. 800b922: 4b27 ldr r3, [pc, #156] @ (800b9c0 <UART_Start_Receive_IT+0x130>)
  25540. 800b924: 6743 str r3, [r0, #116] @ 0x74
  25541. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25542. 800b926: e851 3f00 ldrex r3, [r1]
  25543. ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
  25544. 800b92a: f043 0320 orr.w r3, r3, #32
  25545. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25546. 800b92e: e841 3200 strex r2, r3, [r1]
  25547. 800b932: 2a00 cmp r2, #0
  25548. 800b934: d0e7 beq.n 800b906 <UART_Start_Receive_IT+0x76>
  25549. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25550. 800b936: e851 3f00 ldrex r3, [r1]
  25551. 800b93a: f043 0320 orr.w r3, r3, #32
  25552. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25553. 800b93e: e841 3200 strex r2, r3, [r1]
  25554. 800b942: 2a00 cmp r2, #0
  25555. 800b944: d1ef bne.n 800b926 <UART_Start_Receive_IT+0x96>
  25556. 800b946: e7de b.n 800b906 <UART_Start_Receive_IT+0x76>
  25557. UART_MASK_COMPUTATION(huart);
  25558. 800b948: 6901 ldr r1, [r0, #16]
  25559. 800b94a: f240 13ff movw r3, #511 @ 0x1ff
  25560. 800b94e: 2900 cmp r1, #0
  25561. 800b950: bf18 it ne
  25562. 800b952: 23ff movne r3, #255 @ 0xff
  25563. 800b954: e7ae b.n 800b8b4 <UART_Start_Receive_IT+0x24>
  25564. if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
  25565. 800b956: f8b0 3068 ldrh.w r3, [r0, #104] @ 0x68
  25566. 800b95a: 4293 cmp r3, r2
  25567. 800b95c: d8c5 bhi.n 800b8ea <UART_Start_Receive_IT+0x5a>
  25568. if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
  25569. 800b95e: f5b5 5f80 cmp.w r5, #4096 @ 0x1000
  25570. 800b962: d011 beq.n 800b988 <UART_Start_Receive_IT+0xf8>
  25571. huart->RxISR = UART_RxISR_8BIT_FIFOEN;
  25572. 800b964: 4b17 ldr r3, [pc, #92] @ (800b9c4 <UART_Start_Receive_IT+0x134>)
  25573. 800b966: 6743 str r3, [r0, #116] @ 0x74
  25574. if (huart->Init.Parity != UART_PARITY_NONE)
  25575. 800b968: b98c cbnz r4, 800b98e <UART_Start_Receive_IT+0xfe>
  25576. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25577. 800b96a: f101 0308 add.w r3, r1, #8
  25578. 800b96e: e853 3f00 ldrex r3, [r3]
  25579. ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
  25580. 800b972: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
  25581. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25582. 800b976: f101 0008 add.w r0, r1, #8
  25583. 800b97a: e840 3200 strex r2, r3, [r0]
  25584. 800b97e: 2a00 cmp r2, #0
  25585. 800b980: d1f3 bne.n 800b96a <UART_Start_Receive_IT+0xda>
  25586. }
  25587. 800b982: 2000 movs r0, #0
  25588. 800b984: bc30 pop {r4, r5}
  25589. 800b986: 4770 bx lr
  25590. if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
  25591. 800b988: b1ac cbz r4, 800b9b6 <UART_Start_Receive_IT+0x126>
  25592. huart->RxISR = UART_RxISR_8BIT_FIFOEN;
  25593. 800b98a: 4b0e ldr r3, [pc, #56] @ (800b9c4 <UART_Start_Receive_IT+0x134>)
  25594. 800b98c: 6743 str r3, [r0, #116] @ 0x74
  25595. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25596. 800b98e: e851 3f00 ldrex r3, [r1]
  25597. ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
  25598. 800b992: f443 7380 orr.w r3, r3, #256 @ 0x100
  25599. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25600. 800b996: e841 3200 strex r2, r3, [r1]
  25601. 800b99a: 2a00 cmp r2, #0
  25602. 800b99c: d0e5 beq.n 800b96a <UART_Start_Receive_IT+0xda>
  25603. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25604. 800b99e: e851 3f00 ldrex r3, [r1]
  25605. 800b9a2: f443 7380 orr.w r3, r3, #256 @ 0x100
  25606. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25607. 800b9a6: e841 3200 strex r2, r3, [r1]
  25608. 800b9aa: 2a00 cmp r2, #0
  25609. 800b9ac: d1ef bne.n 800b98e <UART_Start_Receive_IT+0xfe>
  25610. 800b9ae: e7dc b.n 800b96a <UART_Start_Receive_IT+0xda>
  25611. 800b9b0: 4b02 ldr r3, [pc, #8] @ (800b9bc <UART_Start_Receive_IT+0x12c>)
  25612. 800b9b2: 6743 str r3, [r0, #116] @ 0x74
  25613. if (huart->Init.Parity != UART_PARITY_NONE)
  25614. 800b9b4: e79f b.n 800b8f6 <UART_Start_Receive_IT+0x66>
  25615. 800b9b6: 4b04 ldr r3, [pc, #16] @ (800b9c8 <UART_Start_Receive_IT+0x138>)
  25616. 800b9b8: 6743 str r3, [r0, #116] @ 0x74
  25617. if (huart->Init.Parity != UART_PARITY_NONE)
  25618. 800b9ba: e7d6 b.n 800b96a <UART_Start_Receive_IT+0xda>
  25619. 800b9bc: 0800ad8d .word 0x0800ad8d
  25620. 800b9c0: 0800ad45 .word 0x0800ad45
  25621. 800b9c4: 0800add1 .word 0x0800add1
  25622. 800b9c8: 0800afbd .word 0x0800afbd
  25623. 0800b9cc <HAL_UARTEx_WakeupCallback>:
  25624. UNUSED(huart);
  25625. /* NOTE : This function should not be modified, when the callback is needed,
  25626. the HAL_UARTEx_WakeupCallback can be implemented in the user file.
  25627. */
  25628. }
  25629. 800b9cc: 4770 bx lr
  25630. 800b9ce: bf00 nop
  25631. 0800b9d0 <HAL_UARTEx_RxFifoFullCallback>:
  25632. /**
  25633. * @brief UART RX Fifo full callback.
  25634. * @param huart UART handle.
  25635. * @retval None
  25636. */
  25637. __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
  25638. 800b9d0: 4770 bx lr
  25639. 800b9d2: bf00 nop
  25640. 0800b9d4 <HAL_UARTEx_TxFifoEmptyCallback>:
  25641. /**
  25642. * @brief UART TX Fifo empty callback.
  25643. * @param huart UART handle.
  25644. * @retval None
  25645. */
  25646. __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
  25647. 800b9d4: 4770 bx lr
  25648. 800b9d6: bf00 nop
  25649. 0800b9d8 <HAL_UARTEx_DisableFifoMode>:
  25650. /* Check parameters */
  25651. assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
  25652. /* Process Locked */
  25653. __HAL_LOCK(huart);
  25654. 800b9d8: f890 2084 ldrb.w r2, [r0, #132] @ 0x84
  25655. 800b9dc: 2a01 cmp r2, #1
  25656. 800b9de: d017 beq.n 800ba10 <HAL_UARTEx_DisableFifoMode+0x38>
  25657. huart->gState = HAL_UART_STATE_BUSY;
  25658. /* Save actual UART configuration */
  25659. tmpcr1 = READ_REG(huart->Instance->CR1);
  25660. 800b9e0: 6802 ldr r2, [r0, #0]
  25661. 800b9e2: 4603 mov r3, r0
  25662. huart->gState = HAL_UART_STATE_BUSY;
  25663. 800b9e4: 2024 movs r0, #36 @ 0x24
  25664. /* Disable UART */
  25665. __HAL_UART_DISABLE(huart);
  25666. /* Enable FIFO mode */
  25667. CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
  25668. huart->FifoMode = UART_FIFOMODE_DISABLE;
  25669. 800b9e6: 2100 movs r1, #0
  25670. {
  25671. 800b9e8: b430 push {r4, r5}
  25672. huart->gState = HAL_UART_STATE_BUSY;
  25673. 800b9ea: f8c3 0088 str.w r0, [r3, #136] @ 0x88
  25674. /* Restore UART configuration */
  25675. WRITE_REG(huart->Instance->CR1, tmpcr1);
  25676. huart->gState = HAL_UART_STATE_READY;
  25677. 800b9ee: 2520 movs r5, #32
  25678. tmpcr1 = READ_REG(huart->Instance->CR1);
  25679. 800b9f0: 6810 ldr r0, [r2, #0]
  25680. __HAL_UART_DISABLE(huart);
  25681. 800b9f2: 6814 ldr r4, [r2, #0]
  25682. CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
  25683. 800b9f4: f020 5000 bic.w r0, r0, #536870912 @ 0x20000000
  25684. __HAL_UART_DISABLE(huart);
  25685. 800b9f8: f024 0401 bic.w r4, r4, #1
  25686. 800b9fc: 6014 str r4, [r2, #0]
  25687. huart->FifoMode = UART_FIFOMODE_DISABLE;
  25688. 800b9fe: 6659 str r1, [r3, #100] @ 0x64
  25689. WRITE_REG(huart->Instance->CR1, tmpcr1);
  25690. 800ba00: 6010 str r0, [r2, #0]
  25691. /* Process Unlocked */
  25692. __HAL_UNLOCK(huart);
  25693. return HAL_OK;
  25694. 800ba02: 4608 mov r0, r1
  25695. huart->gState = HAL_UART_STATE_READY;
  25696. 800ba04: f8c3 5088 str.w r5, [r3, #136] @ 0x88
  25697. __HAL_UNLOCK(huart);
  25698. 800ba08: f883 1084 strb.w r1, [r3, #132] @ 0x84
  25699. }
  25700. 800ba0c: bc30 pop {r4, r5}
  25701. 800ba0e: 4770 bx lr
  25702. __HAL_LOCK(huart);
  25703. 800ba10: 2002 movs r0, #2
  25704. }
  25705. 800ba12: 4770 bx lr
  25706. 0800ba14 <HAL_UARTEx_SetTxFifoThreshold>:
  25707. /* Check parameters */
  25708. assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
  25709. assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
  25710. /* Process Locked */
  25711. __HAL_LOCK(huart);
  25712. 800ba14: f890 2084 ldrb.w r2, [r0, #132] @ 0x84
  25713. 800ba18: 2a01 cmp r2, #1
  25714. 800ba1a: d037 beq.n 800ba8c <HAL_UARTEx_SetTxFifoThreshold+0x78>
  25715. huart->gState = HAL_UART_STATE_BUSY;
  25716. /* Save actual UART configuration */
  25717. tmpcr1 = READ_REG(huart->Instance->CR1);
  25718. 800ba1c: 6802 ldr r2, [r0, #0]
  25719. 800ba1e: 4603 mov r3, r0
  25720. huart->gState = HAL_UART_STATE_BUSY;
  25721. 800ba20: 2024 movs r0, #36 @ 0x24
  25722. {
  25723. 800ba22: b530 push {r4, r5, lr}
  25724. huart->gState = HAL_UART_STATE_BUSY;
  25725. 800ba24: f8c3 0088 str.w r0, [r3, #136] @ 0x88
  25726. tmpcr1 = READ_REG(huart->Instance->CR1);
  25727. 800ba28: 6814 ldr r4, [r2, #0]
  25728. /* Disable UART */
  25729. __HAL_UART_DISABLE(huart);
  25730. 800ba2a: 6810 ldr r0, [r2, #0]
  25731. 800ba2c: f020 0001 bic.w r0, r0, #1
  25732. 800ba30: 6010 str r0, [r2, #0]
  25733. /* Update TX threshold configuration */
  25734. MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
  25735. 800ba32: 6890 ldr r0, [r2, #8]
  25736. 800ba34: f020 4060 bic.w r0, r0, #3758096384 @ 0xe0000000
  25737. 800ba38: 4301 orrs r1, r0
  25738. uint8_t rx_fifo_threshold;
  25739. uint8_t tx_fifo_threshold;
  25740. static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
  25741. static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
  25742. if (huart->FifoMode == UART_FIFOMODE_DISABLE)
  25743. 800ba3a: 6e58 ldr r0, [r3, #100] @ 0x64
  25744. MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
  25745. 800ba3c: 6091 str r1, [r2, #8]
  25746. if (huart->FifoMode == UART_FIFOMODE_DISABLE)
  25747. 800ba3e: b310 cbz r0, 800ba86 <HAL_UARTEx_SetTxFifoThreshold+0x72>
  25748. }
  25749. else
  25750. {
  25751. rx_fifo_depth = RX_FIFO_DEPTH;
  25752. tx_fifo_depth = TX_FIFO_DEPTH;
  25753. rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
  25754. 800ba40: 6891 ldr r1, [r2, #8]
  25755. tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
  25756. 800ba42: 6890 ldr r0, [r2, #8]
  25757. huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
  25758. (uint16_t)denominator[tx_fifo_threshold];
  25759. huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
  25760. 800ba44: f3c1 6c42 ubfx ip, r1, #25, #3
  25761. huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
  25762. 800ba48: 4911 ldr r1, [pc, #68] @ (800ba90 <HAL_UARTEx_SetTxFifoThreshold+0x7c>)
  25763. tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
  25764. 800ba4a: ea4f 7e50 mov.w lr, r0, lsr #29
  25765. (uint16_t)denominator[tx_fifo_threshold];
  25766. 800ba4e: 4d11 ldr r5, [pc, #68] @ (800ba94 <HAL_UARTEx_SetTxFifoThreshold+0x80>)
  25767. huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
  25768. 800ba50: f811 000e ldrb.w r0, [r1, lr]
  25769. huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
  25770. 800ba54: f811 100c ldrb.w r1, [r1, ip]
  25771. (uint16_t)denominator[tx_fifo_threshold];
  25772. 800ba58: f815 e00e ldrb.w lr, [r5, lr]
  25773. huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
  25774. 800ba5c: 0100 lsls r0, r0, #4
  25775. (uint16_t)denominator[rx_fifo_threshold];
  25776. 800ba5e: f815 500c ldrb.w r5, [r5, ip]
  25777. huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
  25778. 800ba62: 0109 lsls r1, r1, #4
  25779. huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
  25780. 800ba64: fbb0 f0fe udiv r0, r0, lr
  25781. huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
  25782. 800ba68: fbb1 f1f5 udiv r1, r1, r5
  25783. 800ba6c: f8a3 1068 strh.w r1, [r3, #104] @ 0x68
  25784. huart->gState = HAL_UART_STATE_READY;
  25785. 800ba70: 2520 movs r5, #32
  25786. __HAL_UNLOCK(huart);
  25787. 800ba72: 2100 movs r1, #0
  25788. 800ba74: f8a3 006a strh.w r0, [r3, #106] @ 0x6a
  25789. WRITE_REG(huart->Instance->CR1, tmpcr1);
  25790. 800ba78: 6014 str r4, [r2, #0]
  25791. return HAL_OK;
  25792. 800ba7a: 4608 mov r0, r1
  25793. huart->gState = HAL_UART_STATE_READY;
  25794. 800ba7c: f8c3 5088 str.w r5, [r3, #136] @ 0x88
  25795. __HAL_UNLOCK(huart);
  25796. 800ba80: f883 1084 strb.w r1, [r3, #132] @ 0x84
  25797. }
  25798. 800ba84: bd30 pop {r4, r5, pc}
  25799. huart->NbRxDataToProcess = 1U;
  25800. 800ba86: 2101 movs r1, #1
  25801. huart->NbTxDataToProcess = 1U;
  25802. 800ba88: 4608 mov r0, r1
  25803. 800ba8a: e7ef b.n 800ba6c <HAL_UARTEx_SetTxFifoThreshold+0x58>
  25804. __HAL_LOCK(huart);
  25805. 800ba8c: 2002 movs r0, #2
  25806. }
  25807. 800ba8e: 4770 bx lr
  25808. 800ba90: 08011a4c .word 0x08011a4c
  25809. 800ba94: 08011a44 .word 0x08011a44
  25810. 0800ba98 <HAL_UARTEx_SetRxFifoThreshold>:
  25811. __HAL_LOCK(huart);
  25812. 800ba98: f890 2084 ldrb.w r2, [r0, #132] @ 0x84
  25813. 800ba9c: 2a01 cmp r2, #1
  25814. 800ba9e: d037 beq.n 800bb10 <HAL_UARTEx_SetRxFifoThreshold+0x78>
  25815. tmpcr1 = READ_REG(huart->Instance->CR1);
  25816. 800baa0: 6802 ldr r2, [r0, #0]
  25817. 800baa2: 4603 mov r3, r0
  25818. huart->gState = HAL_UART_STATE_BUSY;
  25819. 800baa4: 2024 movs r0, #36 @ 0x24
  25820. {
  25821. 800baa6: b530 push {r4, r5, lr}
  25822. huart->gState = HAL_UART_STATE_BUSY;
  25823. 800baa8: f8c3 0088 str.w r0, [r3, #136] @ 0x88
  25824. tmpcr1 = READ_REG(huart->Instance->CR1);
  25825. 800baac: 6814 ldr r4, [r2, #0]
  25826. __HAL_UART_DISABLE(huart);
  25827. 800baae: 6810 ldr r0, [r2, #0]
  25828. 800bab0: f020 0001 bic.w r0, r0, #1
  25829. 800bab4: 6010 str r0, [r2, #0]
  25830. MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
  25831. 800bab6: 6890 ldr r0, [r2, #8]
  25832. 800bab8: f020 6060 bic.w r0, r0, #234881024 @ 0xe000000
  25833. 800babc: 4301 orrs r1, r0
  25834. if (huart->FifoMode == UART_FIFOMODE_DISABLE)
  25835. 800babe: 6e58 ldr r0, [r3, #100] @ 0x64
  25836. MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
  25837. 800bac0: 6091 str r1, [r2, #8]
  25838. if (huart->FifoMode == UART_FIFOMODE_DISABLE)
  25839. 800bac2: b310 cbz r0, 800bb0a <HAL_UARTEx_SetRxFifoThreshold+0x72>
  25840. rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
  25841. 800bac4: 6891 ldr r1, [r2, #8]
  25842. tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
  25843. 800bac6: 6890 ldr r0, [r2, #8]
  25844. huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
  25845. 800bac8: f3c1 6c42 ubfx ip, r1, #25, #3
  25846. huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
  25847. 800bacc: 4911 ldr r1, [pc, #68] @ (800bb14 <HAL_UARTEx_SetRxFifoThreshold+0x7c>)
  25848. tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
  25849. 800bace: ea4f 7e50 mov.w lr, r0, lsr #29
  25850. (uint16_t)denominator[tx_fifo_threshold];
  25851. 800bad2: 4d11 ldr r5, [pc, #68] @ (800bb18 <HAL_UARTEx_SetRxFifoThreshold+0x80>)
  25852. huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
  25853. 800bad4: f811 000e ldrb.w r0, [r1, lr]
  25854. huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
  25855. 800bad8: f811 100c ldrb.w r1, [r1, ip]
  25856. (uint16_t)denominator[tx_fifo_threshold];
  25857. 800badc: f815 e00e ldrb.w lr, [r5, lr]
  25858. huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
  25859. 800bae0: 0100 lsls r0, r0, #4
  25860. (uint16_t)denominator[rx_fifo_threshold];
  25861. 800bae2: f815 500c ldrb.w r5, [r5, ip]
  25862. huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
  25863. 800bae6: 0109 lsls r1, r1, #4
  25864. huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
  25865. 800bae8: fbb0 f0fe udiv r0, r0, lr
  25866. huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
  25867. 800baec: fbb1 f1f5 udiv r1, r1, r5
  25868. 800baf0: f8a3 1068 strh.w r1, [r3, #104] @ 0x68
  25869. huart->gState = HAL_UART_STATE_READY;
  25870. 800baf4: 2520 movs r5, #32
  25871. __HAL_UNLOCK(huart);
  25872. 800baf6: 2100 movs r1, #0
  25873. 800baf8: f8a3 006a strh.w r0, [r3, #106] @ 0x6a
  25874. WRITE_REG(huart->Instance->CR1, tmpcr1);
  25875. 800bafc: 6014 str r4, [r2, #0]
  25876. return HAL_OK;
  25877. 800bafe: 4608 mov r0, r1
  25878. huart->gState = HAL_UART_STATE_READY;
  25879. 800bb00: f8c3 5088 str.w r5, [r3, #136] @ 0x88
  25880. __HAL_UNLOCK(huart);
  25881. 800bb04: f883 1084 strb.w r1, [r3, #132] @ 0x84
  25882. }
  25883. 800bb08: bd30 pop {r4, r5, pc}
  25884. huart->NbRxDataToProcess = 1U;
  25885. 800bb0a: 2101 movs r1, #1
  25886. huart->NbTxDataToProcess = 1U;
  25887. 800bb0c: 4608 mov r0, r1
  25888. 800bb0e: e7ef b.n 800baf0 <HAL_UARTEx_SetRxFifoThreshold+0x58>
  25889. __HAL_LOCK(huart);
  25890. 800bb10: 2002 movs r0, #2
  25891. }
  25892. 800bb12: 4770 bx lr
  25893. 800bb14: 08011a4c .word 0x08011a4c
  25894. 800bb18: 08011a44 .word 0x08011a44
  25895. 0800bb1c <HAL_UARTEx_ReceiveToIdle_IT>:
  25896. {
  25897. 800bb1c: b570 push {r4, r5, r6, lr}
  25898. if (huart->RxState == HAL_UART_STATE_READY)
  25899. 800bb1e: f8d0 608c ldr.w r6, [r0, #140] @ 0x8c
  25900. 800bb22: 2e20 cmp r6, #32
  25901. 800bb24: d10f bne.n 800bb46 <HAL_UARTEx_ReceiveToIdle_IT+0x2a>
  25902. if ((pData == NULL) || (Size == 0U))
  25903. 800bb26: b161 cbz r1, 800bb42 <HAL_UARTEx_ReceiveToIdle_IT+0x26>
  25904. 800bb28: fab2 f582 clz r5, r2
  25905. 800bb2c: 096d lsrs r5, r5, #5
  25906. 800bb2e: b142 cbz r2, 800bb42 <HAL_UARTEx_ReceiveToIdle_IT+0x26>
  25907. huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
  25908. 800bb30: 2301 movs r3, #1
  25909. 800bb32: 4604 mov r4, r0
  25910. 800bb34: 66c3 str r3, [r0, #108] @ 0x6c
  25911. huart->RxEventType = HAL_UART_RXEVENT_TC;
  25912. 800bb36: 6705 str r5, [r0, #112] @ 0x70
  25913. (void)UART_Start_Receive_IT(huart, pData, Size);
  25914. 800bb38: f7ff feaa bl 800b890 <UART_Start_Receive_IT>
  25915. if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
  25916. 800bb3c: 6ee3 ldr r3, [r4, #108] @ 0x6c
  25917. 800bb3e: 2b01 cmp r3, #1
  25918. 800bb40: d003 beq.n 800bb4a <HAL_UARTEx_ReceiveToIdle_IT+0x2e>
  25919. return HAL_ERROR;
  25920. 800bb42: 2001 movs r0, #1
  25921. }
  25922. 800bb44: bd70 pop {r4, r5, r6, pc}
  25923. return HAL_BUSY;
  25924. 800bb46: 2002 movs r0, #2
  25925. }
  25926. 800bb48: bd70 pop {r4, r5, r6, pc}
  25927. __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
  25928. 800bb4a: 6822 ldr r2, [r4, #0]
  25929. 800bb4c: 2310 movs r3, #16
  25930. 800bb4e: 6213 str r3, [r2, #32]
  25931. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  25932. 800bb50: e852 3f00 ldrex r3, [r2]
  25933. ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  25934. 800bb54: f043 0310 orr.w r3, r3, #16
  25935. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  25936. 800bb58: e842 3100 strex r1, r3, [r2]
  25937. 800bb5c: 2900 cmp r1, #0
  25938. 800bb5e: d1f7 bne.n 800bb50 <HAL_UARTEx_ReceiveToIdle_IT+0x34>
  25939. HAL_StatusTypeDef status = HAL_OK;
  25940. 800bb60: 2000 movs r0, #0
  25941. }
  25942. 800bb62: bd70 pop {r4, r5, r6, pc}
  25943. 0800bb64 <TimerCallback>:
  25944. }
  25945. /*---------------------------------------------------------------------------*/
  25946. #if (configUSE_OS2_TIMER == 1)
  25947. static void TimerCallback (TimerHandle_t hTimer) {
  25948. 800bb64: b510 push {r4, lr}
  25949. TimerCallback_t *callb;
  25950. callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer);
  25951. 800bb66: f002 fe9f bl 800e8a8 <pvTimerGetTimerID>
  25952. if (callb != NULL) {
  25953. 800bb6a: b120 cbz r0, 800bb76 <TimerCallback+0x12>
  25954. callb->func (callb->arg);
  25955. 800bb6c: e9d0 3000 ldrd r3, r0, [r0]
  25956. }
  25957. }
  25958. 800bb70: e8bd 4010 ldmia.w sp!, {r4, lr}
  25959. callb->func (callb->arg);
  25960. 800bb74: 4718 bx r3
  25961. }
  25962. 800bb76: bd10 pop {r4, pc}
  25963. 0800bb78 <SysTick_Handler>:
  25964. void SysTick_Handler (void) {
  25965. 800bb78: b508 push {r3, lr}
  25966. SysTick->CTRL;
  25967. 800bb7a: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  25968. 800bb7e: 691b ldr r3, [r3, #16]
  25969. if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
  25970. 800bb80: f002 f8d6 bl 800dd30 <xTaskGetSchedulerState>
  25971. 800bb84: 2801 cmp r0, #1
  25972. 800bb86: d100 bne.n 800bb8a <SysTick_Handler+0x12>
  25973. }
  25974. 800bb88: bd08 pop {r3, pc}
  25975. 800bb8a: e8bd 4008 ldmia.w sp!, {r3, lr}
  25976. xPortSysTickHandler();
  25977. 800bb8e: f002 bf71 b.w 800ea74 <xPortSysTickHandler>
  25978. 800bb92: bf00 nop
  25979. 0800bb94 <osKernelInitialize>:
  25980. __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
  25981. 800bb94: f3ef 8305 mrs r3, IPSR
  25982. if (IS_IRQ()) {
  25983. 800bb98: b92b cbnz r3, 800bba6 <osKernelInitialize+0x12>
  25984. if (KernelState == osKernelInactive) {
  25985. 800bb9a: 4b06 ldr r3, [pc, #24] @ (800bbb4 <osKernelInitialize+0x20>)
  25986. 800bb9c: 6818 ldr r0, [r3, #0]
  25987. 800bb9e: b928 cbnz r0, 800bbac <osKernelInitialize+0x18>
  25988. KernelState = osKernelReady;
  25989. 800bba0: 2201 movs r2, #1
  25990. 800bba2: 601a str r2, [r3, #0]
  25991. stat = osOK;
  25992. 800bba4: 4770 bx lr
  25993. stat = osErrorISR;
  25994. 800bba6: f06f 0005 mvn.w r0, #5
  25995. 800bbaa: 4770 bx lr
  25996. stat = osError;
  25997. 800bbac: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  25998. }
  25999. 800bbb0: 4770 bx lr
  26000. 800bbb2: bf00 nop
  26001. 800bbb4: 24002b00 .word 0x24002b00
  26002. 0800bbb8 <osKernelStart>:
  26003. osStatus_t osKernelStart (void) {
  26004. 800bbb8: b510 push {r4, lr}
  26005. 800bbba: f3ef 8405 mrs r4, IPSR
  26006. if (IS_IRQ()) {
  26007. 800bbbe: b974 cbnz r4, 800bbde <osKernelStart+0x26>
  26008. if (KernelState == osKernelReady) {
  26009. 800bbc0: 4b08 ldr r3, [pc, #32] @ (800bbe4 <osKernelStart+0x2c>)
  26010. 800bbc2: 681a ldr r2, [r3, #0]
  26011. 800bbc4: 2a01 cmp r2, #1
  26012. 800bbc6: d107 bne.n 800bbd8 <osKernelStart+0x20>
  26013. SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  26014. 800bbc8: 4907 ldr r1, [pc, #28] @ (800bbe8 <osKernelStart+0x30>)
  26015. KernelState = osKernelRunning;
  26016. 800bbca: 2202 movs r2, #2
  26017. 800bbcc: 77cc strb r4, [r1, #31]
  26018. 800bbce: 601a str r2, [r3, #0]
  26019. vTaskStartScheduler();
  26020. 800bbd0: f001 fe64 bl 800d89c <vTaskStartScheduler>
  26021. stat = osOK;
  26022. 800bbd4: 4620 mov r0, r4
  26023. }
  26024. 800bbd6: bd10 pop {r4, pc}
  26025. stat = osError;
  26026. 800bbd8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  26027. }
  26028. 800bbdc: bd10 pop {r4, pc}
  26029. stat = osErrorISR;
  26030. 800bbde: f06f 0005 mvn.w r0, #5
  26031. }
  26032. 800bbe2: bd10 pop {r4, pc}
  26033. 800bbe4: 24002b00 .word 0x24002b00
  26034. 800bbe8: e000ed00 .word 0xe000ed00
  26035. 0800bbec <osThreadNew>:
  26036. osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
  26037. 800bbec: b5f0 push {r4, r5, r6, r7, lr}
  26038. hTask = NULL;
  26039. 800bbee: 2500 movs r5, #0
  26040. osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
  26041. 800bbf0: b087 sub sp, #28
  26042. hTask = NULL;
  26043. 800bbf2: 9505 str r5, [sp, #20]
  26044. 800bbf4: f3ef 8305 mrs r3, IPSR
  26045. if (!IS_IRQ() && (func != NULL)) {
  26046. 800bbf8: b300 cbz r0, 800bc3c <osThreadNew+0x50>
  26047. 800bbfa: b9fb cbnz r3, 800bc3c <osThreadNew+0x50>
  26048. if (attr != NULL) {
  26049. 800bbfc: 4614 mov r4, r2
  26050. 800bbfe: b302 cbz r2, 800bc42 <osThreadNew+0x56>
  26051. if (attr->priority != osPriorityNone) {
  26052. 800bc00: 6996 ldr r6, [r2, #24]
  26053. 800bc02: b9c6 cbnz r6, 800bc36 <osThreadNew+0x4a>
  26054. 800bc04: 2618 movs r6, #24
  26055. if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
  26056. 800bc06: 6863 ldr r3, [r4, #4]
  26057. 800bc08: 07db lsls r3, r3, #31
  26058. 800bc0a: d417 bmi.n 800bc3c <osThreadNew+0x50>
  26059. if (attr->stack_size > 0U) {
  26060. 800bc0c: 6963 ldr r3, [r4, #20]
  26061. 800bc0e: b333 cbz r3, 800bc5e <osThreadNew+0x72>
  26062. stack = attr->stack_size / sizeof(StackType_t);
  26063. 800bc10: 089a lsrs r2, r3, #2
  26064. if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
  26065. 800bc12: 68a5 ldr r5, [r4, #8]
  26066. if (attr->name != NULL) {
  26067. 800bc14: f8d4 c000 ldr.w ip, [r4]
  26068. if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
  26069. 800bc18: 68e7 ldr r7, [r4, #12]
  26070. 800bc1a: b31d cbz r5, 800bc64 <osThreadNew+0x78>
  26071. 800bc1c: 2fa7 cmp r7, #167 @ 0xa7
  26072. 800bc1e: d90d bls.n 800bc3c <osThreadNew+0x50>
  26073. (attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
  26074. 800bc20: 6924 ldr r4, [r4, #16]
  26075. 800bc22: b15b cbz r3, 800bc3c <osThreadNew+0x50>
  26076. 800bc24: b154 cbz r4, 800bc3c <osThreadNew+0x50>
  26077. hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
  26078. 800bc26: 460b mov r3, r1
  26079. 800bc28: 9600 str r6, [sp, #0]
  26080. 800bc2a: 4661 mov r1, ip
  26081. 800bc2c: e9cd 4501 strd r4, r5, [sp, #4]
  26082. 800bc30: f001 fd74 bl 800d71c <xTaskCreateStatic>
  26083. 800bc34: e003 b.n 800bc3e <osThreadNew+0x52>
  26084. if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
  26085. 800bc36: 1e72 subs r2, r6, #1
  26086. 800bc38: 2a37 cmp r2, #55 @ 0x37
  26087. 800bc3a: d9e4 bls.n 800bc06 <osThreadNew+0x1a>
  26088. return (NULL);
  26089. 800bc3c: 2000 movs r0, #0
  26090. }
  26091. 800bc3e: b007 add sp, #28
  26092. 800bc40: bdf0 pop {r4, r5, r6, r7, pc}
  26093. 800bc42: f44f 7200 mov.w r2, #512 @ 0x200
  26094. prio = (UBaseType_t)osPriorityNormal;
  26095. 800bc46: 2618 movs r6, #24
  26096. if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
  26097. 800bc48: 460b mov r3, r1
  26098. 800bc4a: 4621 mov r1, r4
  26099. 800bc4c: ac05 add r4, sp, #20
  26100. 800bc4e: 9600 str r6, [sp, #0]
  26101. 800bc50: 9401 str r4, [sp, #4]
  26102. 800bc52: f001 fd9d bl 800d790 <xTaskCreate>
  26103. 800bc56: 2801 cmp r0, #1
  26104. 800bc58: d1f0 bne.n 800bc3c <osThreadNew+0x50>
  26105. return ((osThreadId_t)hTask);
  26106. 800bc5a: 9805 ldr r0, [sp, #20]
  26107. 800bc5c: e7ef b.n 800bc3e <osThreadNew+0x52>
  26108. stack = configMINIMAL_STACK_SIZE;
  26109. 800bc5e: f44f 7200 mov.w r2, #512 @ 0x200
  26110. 800bc62: e7d6 b.n 800bc12 <osThreadNew+0x26>
  26111. if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
  26112. 800bc64: 2f00 cmp r7, #0
  26113. 800bc66: d1e9 bne.n 800bc3c <osThreadNew+0x50>
  26114. 800bc68: 6923 ldr r3, [r4, #16]
  26115. 800bc6a: 2b00 cmp r3, #0
  26116. 800bc6c: d1e6 bne.n 800bc3c <osThreadNew+0x50>
  26117. if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
  26118. 800bc6e: b292 uxth r2, r2
  26119. 800bc70: 4664 mov r4, ip
  26120. 800bc72: e7e9 b.n 800bc48 <osThreadNew+0x5c>
  26121. 0800bc74 <osDelay>:
  26122. 800bc74: f3ef 8205 mrs r2, IPSR
  26123. if (IS_IRQ()) {
  26124. 800bc78: b93a cbnz r2, 800bc8a <osDelay+0x16>
  26125. osStatus_t osDelay (uint32_t ticks) {
  26126. 800bc7a: b508 push {r3, lr}
  26127. if (ticks != 0U) {
  26128. 800bc7c: b908 cbnz r0, 800bc82 <osDelay+0xe>
  26129. stat = osOK;
  26130. 800bc7e: 2000 movs r0, #0
  26131. }
  26132. 800bc80: bd08 pop {r3, pc}
  26133. vTaskDelay(ticks);
  26134. 800bc82: f001 fdb5 bl 800d7f0 <vTaskDelay>
  26135. stat = osOK;
  26136. 800bc86: 2000 movs r0, #0
  26137. }
  26138. 800bc88: bd08 pop {r3, pc}
  26139. stat = osErrorISR;
  26140. 800bc8a: f06f 0005 mvn.w r0, #5
  26141. }
  26142. 800bc8e: 4770 bx lr
  26143. 0800bc90 <osTimerNew>:
  26144. osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {
  26145. 800bc90: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  26146. 800bc94: 461c mov r4, r3
  26147. 800bc96: b082 sub sp, #8
  26148. 800bc98: f3ef 8305 mrs r3, IPSR
  26149. UBaseType_t reload;
  26150. int32_t mem;
  26151. hTimer = NULL;
  26152. if (!IS_IRQ() && (func != NULL)) {
  26153. 800bc9c: b1b8 cbz r0, 800bcce <osTimerNew+0x3e>
  26154. 800bc9e: b9b3 cbnz r3, 800bcce <osTimerNew+0x3e>
  26155. /* Allocate memory to store callback function and argument */
  26156. callb = pvPortMalloc (sizeof(TimerCallback_t));
  26157. 800bca0: 4605 mov r5, r0
  26158. 800bca2: 2008 movs r0, #8
  26159. 800bca4: 460e mov r6, r1
  26160. 800bca6: 4617 mov r7, r2
  26161. 800bca8: f002 ffdc bl 800ec64 <pvPortMalloc>
  26162. if (callb != NULL) {
  26163. 800bcac: 4680 mov r8, r0
  26164. 800bcae: b170 cbz r0, 800bcce <osTimerNew+0x3e>
  26165. callb->func = func;
  26166. callb->arg = argument;
  26167. if (type == osTimerOnce) {
  26168. 800bcb0: 3e00 subs r6, #0
  26169. callb->arg = argument;
  26170. 800bcb2: e9c0 5700 strd r5, r7, [r0]
  26171. if (type == osTimerOnce) {
  26172. 800bcb6: bf18 it ne
  26173. 800bcb8: 2601 movne r6, #1
  26174. }
  26175. mem = -1;
  26176. name = NULL;
  26177. if (attr != NULL) {
  26178. 800bcba: b1e4 cbz r4, 800bcf6 <osTimerNew+0x66>
  26179. if (attr->name != NULL) {
  26180. name = attr->name;
  26181. }
  26182. if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) {
  26183. 800bcbc: 68a3 ldr r3, [r4, #8]
  26184. if (attr->name != NULL) {
  26185. 800bcbe: 6820 ldr r0, [r4, #0]
  26186. if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) {
  26187. 800bcc0: 68e2 ldr r2, [r4, #12]
  26188. 800bcc2: b1ab cbz r3, 800bcf0 <osTimerNew+0x60>
  26189. 800bcc4: 2a2b cmp r2, #43 @ 0x2b
  26190. 800bcc6: d806 bhi.n 800bcd6 <osTimerNew+0x46>
  26191. #endif
  26192. }
  26193. }
  26194. if ((hTimer == NULL) && (callb != NULL)) {
  26195. vPortFree (callb);
  26196. 800bcc8: 4640 mov r0, r8
  26197. 800bcca: f003 f887 bl 800eddc <vPortFree>
  26198. hTimer = NULL;
  26199. 800bcce: 2000 movs r0, #0
  26200. }
  26201. }
  26202. }
  26203. return ((osTimerId_t)hTimer);
  26204. }
  26205. 800bcd0: b002 add sp, #8
  26206. 800bcd2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  26207. hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem);
  26208. 800bcd6: 4c0d ldr r4, [pc, #52] @ (800bd0c <osTimerNew+0x7c>)
  26209. 800bcd8: 4632 mov r2, r6
  26210. 800bcda: 2101 movs r1, #1
  26211. 800bcdc: e9cd 4300 strd r4, r3, [sp]
  26212. 800bce0: 4643 mov r3, r8
  26213. 800bce2: f002 fd15 bl 800e710 <xTimerCreateStatic>
  26214. if ((hTimer == NULL) && (callb != NULL)) {
  26215. 800bce6: 2800 cmp r0, #0
  26216. 800bce8: d0ee beq.n 800bcc8 <osTimerNew+0x38>
  26217. }
  26218. 800bcea: b002 add sp, #8
  26219. 800bcec: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  26220. if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
  26221. 800bcf0: 2a00 cmp r2, #0
  26222. 800bcf2: d1e9 bne.n 800bcc8 <osTimerNew+0x38>
  26223. 800bcf4: 4604 mov r4, r0
  26224. hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback);
  26225. 800bcf6: 4d05 ldr r5, [pc, #20] @ (800bd0c <osTimerNew+0x7c>)
  26226. 800bcf8: 4643 mov r3, r8
  26227. 800bcfa: 4632 mov r2, r6
  26228. 800bcfc: 4620 mov r0, r4
  26229. 800bcfe: 2101 movs r1, #1
  26230. 800bd00: 9500 str r5, [sp, #0]
  26231. 800bd02: f002 fc9d bl 800e640 <xTimerCreate>
  26232. if ((hTimer == NULL) && (callb != NULL)) {
  26233. 800bd06: 2800 cmp r0, #0
  26234. 800bd08: d1ef bne.n 800bcea <osTimerNew+0x5a>
  26235. 800bd0a: e7dd b.n 800bcc8 <osTimerNew+0x38>
  26236. 800bd0c: 0800bb65 .word 0x0800bb65
  26237. 0800bd10 <osTimerStart>:
  26238. 800bd10: f3ef 8305 mrs r3, IPSR
  26239. osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) {
  26240. TimerHandle_t hTimer = (TimerHandle_t)timer_id;
  26241. osStatus_t stat;
  26242. if (IS_IRQ()) {
  26243. 800bd14: b973 cbnz r3, 800bd34 <osTimerStart+0x24>
  26244. osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) {
  26245. 800bd16: b510 push {r4, lr}
  26246. 800bd18: b082 sub sp, #8
  26247. stat = osErrorISR;
  26248. }
  26249. else if (hTimer == NULL) {
  26250. 800bd1a: b170 cbz r0, 800bd3a <osTimerStart+0x2a>
  26251. stat = osErrorParameter;
  26252. }
  26253. else {
  26254. if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) {
  26255. 800bd1c: 460a mov r2, r1
  26256. 800bd1e: 9300 str r3, [sp, #0]
  26257. 800bd20: 2104 movs r1, #4
  26258. 800bd22: f002 fd75 bl 800e810 <xTimerGenericCommand>
  26259. stat = osOK;
  26260. 800bd26: 2801 cmp r0, #1
  26261. 800bd28: bf14 ite ne
  26262. 800bd2a: f06f 0002 mvnne.w r0, #2
  26263. 800bd2e: 2000 moveq r0, #0
  26264. stat = osErrorResource;
  26265. }
  26266. }
  26267. return (stat);
  26268. }
  26269. 800bd30: b002 add sp, #8
  26270. 800bd32: bd10 pop {r4, pc}
  26271. stat = osErrorISR;
  26272. 800bd34: f06f 0005 mvn.w r0, #5
  26273. }
  26274. 800bd38: 4770 bx lr
  26275. stat = osErrorParameter;
  26276. 800bd3a: f06f 0003 mvn.w r0, #3
  26277. 800bd3e: e7f7 b.n 800bd30 <osTimerStart+0x20>
  26278. 0800bd40 <osTimerStop>:
  26279. osStatus_t osTimerStop (osTimerId_t timer_id) {
  26280. 800bd40: b530 push {r4, r5, lr}
  26281. 800bd42: b083 sub sp, #12
  26282. 800bd44: f3ef 8505 mrs r5, IPSR
  26283. TimerHandle_t hTimer = (TimerHandle_t)timer_id;
  26284. osStatus_t stat;
  26285. if (IS_IRQ()) {
  26286. 800bd48: b9a5 cbnz r5, 800bd74 <osTimerStop+0x34>
  26287. stat = osErrorISR;
  26288. }
  26289. else if (hTimer == NULL) {
  26290. 800bd4a: 4604 mov r4, r0
  26291. 800bd4c: b1a8 cbz r0, 800bd7a <osTimerStop+0x3a>
  26292. stat = osErrorParameter;
  26293. }
  26294. else {
  26295. if (xTimerIsTimerActive (hTimer) == pdFALSE) {
  26296. 800bd4e: f002 fd95 bl 800e87c <xTimerIsTimerActive>
  26297. 800bd52: b160 cbz r0, 800bd6e <osTimerStop+0x2e>
  26298. stat = osErrorResource;
  26299. }
  26300. else {
  26301. if (xTimerStop (hTimer, 0) == pdPASS) {
  26302. 800bd54: 462b mov r3, r5
  26303. 800bd56: 462a mov r2, r5
  26304. 800bd58: 2103 movs r1, #3
  26305. 800bd5a: 4620 mov r0, r4
  26306. 800bd5c: 9500 str r5, [sp, #0]
  26307. 800bd5e: f002 fd57 bl 800e810 <xTimerGenericCommand>
  26308. 800bd62: 3801 subs r0, #1
  26309. 800bd64: bf18 it ne
  26310. 800bd66: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
  26311. }
  26312. }
  26313. }
  26314. return (stat);
  26315. }
  26316. 800bd6a: b003 add sp, #12
  26317. 800bd6c: bd30 pop {r4, r5, pc}
  26318. stat = osErrorResource;
  26319. 800bd6e: f06f 0002 mvn.w r0, #2
  26320. return (stat);
  26321. 800bd72: e7fa b.n 800bd6a <osTimerStop+0x2a>
  26322. stat = osErrorISR;
  26323. 800bd74: f06f 0005 mvn.w r0, #5
  26324. 800bd78: e7f7 b.n 800bd6a <osTimerStop+0x2a>
  26325. stat = osErrorParameter;
  26326. 800bd7a: f06f 0003 mvn.w r0, #3
  26327. 800bd7e: e7f4 b.n 800bd6a <osTimerStop+0x2a>
  26328. 0800bd80 <osMutexNew>:
  26329. }
  26330. /*---------------------------------------------------------------------------*/
  26331. #if (configUSE_OS2_MUTEX == 1)
  26332. osMutexId_t osMutexNew (const osMutexAttr_t *attr) {
  26333. 800bd80: b530 push {r4, r5, lr}
  26334. 800bd82: b083 sub sp, #12
  26335. 800bd84: f3ef 8505 mrs r5, IPSR
  26336. const char *name;
  26337. #endif
  26338. hMutex = NULL;
  26339. if (!IS_IRQ()) {
  26340. 800bd88: b9bd cbnz r5, 800bdba <osMutexNew+0x3a>
  26341. if (attr != NULL) {
  26342. 800bd8a: 4604 mov r4, r0
  26343. 800bd8c: b1c0 cbz r0, 800bdc0 <osMutexNew+0x40>
  26344. type = attr->attr_bits;
  26345. 800bd8e: 6845 ldr r5, [r0, #4]
  26346. rmtx = 1U;
  26347. } else {
  26348. rmtx = 0U;
  26349. }
  26350. if ((type & osMutexRobust) != osMutexRobust) {
  26351. 800bd90: 072b lsls r3, r5, #28
  26352. 800bd92: d412 bmi.n 800bdba <osMutexNew+0x3a>
  26353. mem = -1;
  26354. if (attr != NULL) {
  26355. if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {
  26356. 800bd94: 6881 ldr r1, [r0, #8]
  26357. if ((type & osMutexRecursive) == osMutexRecursive) {
  26358. 800bd96: f005 0501 and.w r5, r5, #1
  26359. if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {
  26360. 800bd9a: 68c3 ldr r3, [r0, #12]
  26361. 800bd9c: b309 cbz r1, 800bde2 <osMutexNew+0x62>
  26362. 800bd9e: 2b4f cmp r3, #79 @ 0x4f
  26363. 800bda0: d90b bls.n 800bdba <osMutexNew+0x3a>
  26364. mem = 0;
  26365. }
  26366. if (mem == 1) {
  26367. #if (configSUPPORT_STATIC_ALLOCATION == 1)
  26368. if (rmtx != 0U) {
  26369. 800bda2: b345 cbz r5, 800bdf6 <osMutexNew+0x76>
  26370. #if (configUSE_RECURSIVE_MUTEXES == 1)
  26371. hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem);
  26372. 800bda4: 2004 movs r0, #4
  26373. 800bda6: f000 fbf7 bl 800c598 <xQueueCreateMutexStatic>
  26374. #endif
  26375. }
  26376. }
  26377. #if (configQUEUE_REGISTRY_SIZE > 0)
  26378. if (hMutex != NULL) {
  26379. 800bdaa: b130 cbz r0, 800bdba <osMutexNew+0x3a>
  26380. if (attr != NULL) {
  26381. name = attr->name;
  26382. 800bdac: 6824 ldr r4, [r4, #0]
  26383. 800bdae: e00c b.n 800bdca <osMutexNew+0x4a>
  26384. hMutex = xSemaphoreCreateRecursiveMutex ();
  26385. 800bdb0: 2004 movs r0, #4
  26386. 800bdb2: f000 fc61 bl 800c678 <xQueueCreateMutex>
  26387. if (hMutex != NULL) {
  26388. 800bdb6: 2800 cmp r0, #0
  26389. 800bdb8: d1f8 bne.n 800bdac <osMutexNew+0x2c>
  26390. hMutex = NULL;
  26391. 800bdba: 2000 movs r0, #0
  26392. }
  26393. }
  26394. }
  26395. return ((osMutexId_t)hMutex);
  26396. }
  26397. 800bdbc: b003 add sp, #12
  26398. 800bdbe: bd30 pop {r4, r5, pc}
  26399. hMutex = xSemaphoreCreateMutex ();
  26400. 800bdc0: 2001 movs r0, #1
  26401. 800bdc2: f000 fc59 bl 800c678 <xQueueCreateMutex>
  26402. if (hMutex != NULL) {
  26403. 800bdc6: 2800 cmp r0, #0
  26404. 800bdc8: d0f7 beq.n 800bdba <osMutexNew+0x3a>
  26405. vQueueAddToRegistry (hMutex, name);
  26406. 800bdca: 4621 mov r1, r4
  26407. 800bdcc: 9001 str r0, [sp, #4]
  26408. 800bdce: f001 f87f bl 800ced0 <vQueueAddToRegistry>
  26409. if ((hMutex != NULL) && (rmtx != 0U)) {
  26410. 800bdd2: 9801 ldr r0, [sp, #4]
  26411. 800bdd4: f015 0f01 tst.w r5, #1
  26412. hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U);
  26413. 800bdd8: bf18 it ne
  26414. 800bdda: f040 0001 orrne.w r0, r0, #1
  26415. }
  26416. 800bdde: b003 add sp, #12
  26417. 800bde0: bd30 pop {r4, r5, pc}
  26418. if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
  26419. 800bde2: 2b00 cmp r3, #0
  26420. 800bde4: d1e9 bne.n 800bdba <osMutexNew+0x3a>
  26421. if (rmtx != 0U) {
  26422. 800bde6: 2d00 cmp r5, #0
  26423. 800bde8: d1e2 bne.n 800bdb0 <osMutexNew+0x30>
  26424. hMutex = xSemaphoreCreateMutex ();
  26425. 800bdea: 2001 movs r0, #1
  26426. 800bdec: f000 fc44 bl 800c678 <xQueueCreateMutex>
  26427. if (hMutex != NULL) {
  26428. 800bdf0: 2800 cmp r0, #0
  26429. 800bdf2: d1db bne.n 800bdac <osMutexNew+0x2c>
  26430. 800bdf4: e7e1 b.n 800bdba <osMutexNew+0x3a>
  26431. hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem);
  26432. 800bdf6: 2001 movs r0, #1
  26433. 800bdf8: f000 fbce bl 800c598 <xQueueCreateMutexStatic>
  26434. if (hMutex != NULL) {
  26435. 800bdfc: 2800 cmp r0, #0
  26436. 800bdfe: d1d5 bne.n 800bdac <osMutexNew+0x2c>
  26437. 800be00: e7db b.n 800bdba <osMutexNew+0x3a>
  26438. 800be02: bf00 nop
  26439. 0800be04 <osMutexAcquire>:
  26440. 800be04: f3ef 8205 mrs r2, IPSR
  26441. rmtx = (uint32_t)mutex_id & 1U;
  26442. stat = osOK;
  26443. if (IS_IRQ()) {
  26444. 800be08: b9d2 cbnz r2, 800be40 <osMutexAcquire+0x3c>
  26445. stat = osErrorISR;
  26446. }
  26447. else if (hMutex == NULL) {
  26448. 800be0a: 2801 cmp r0, #1
  26449. osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
  26450. 800be0c: b538 push {r3, r4, r5, lr}
  26451. 800be0e: 4603 mov r3, r0
  26452. else if (hMutex == NULL) {
  26453. 800be10: d919 bls.n 800be46 <osMutexAcquire+0x42>
  26454. stat = osErrorParameter;
  26455. }
  26456. else {
  26457. if (rmtx != 0U) {
  26458. 800be12: f003 0501 and.w r5, r3, #1
  26459. 800be16: 460c mov r4, r1
  26460. 800be18: f020 0001 bic.w r0, r0, #1
  26461. 800be1c: b955 cbnz r5, 800be34 <osMutexAcquire+0x30>
  26462. }
  26463. }
  26464. #endif
  26465. }
  26466. else {
  26467. if (xSemaphoreTake (hMutex, timeout) != pdPASS) {
  26468. 800be1e: f000 fe4f bl 800cac0 <xQueueSemaphoreTake>
  26469. 800be22: 2801 cmp r0, #1
  26470. 800be24: d00a beq.n 800be3c <osMutexAcquire+0x38>
  26471. if (timeout != 0U) {
  26472. stat = osErrorTimeout;
  26473. } else {
  26474. stat = osErrorResource;
  26475. 800be26: 2c00 cmp r4, #0
  26476. 800be28: bf14 ite ne
  26477. 800be2a: f06f 0001 mvnne.w r0, #1
  26478. 800be2e: f06f 0002 mvneq.w r0, #2
  26479. }
  26480. }
  26481. }
  26482. return (stat);
  26483. }
  26484. 800be32: bd38 pop {r3, r4, r5, pc}
  26485. if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) {
  26486. 800be34: f000 ffd0 bl 800cdd8 <xQueueTakeMutexRecursive>
  26487. 800be38: 2801 cmp r0, #1
  26488. 800be3a: d1f4 bne.n 800be26 <osMutexAcquire+0x22>
  26489. stat = osOK;
  26490. 800be3c: 2000 movs r0, #0
  26491. }
  26492. 800be3e: bd38 pop {r3, r4, r5, pc}
  26493. stat = osErrorISR;
  26494. 800be40: f06f 0005 mvn.w r0, #5
  26495. }
  26496. 800be44: 4770 bx lr
  26497. stat = osErrorParameter;
  26498. 800be46: f06f 0003 mvn.w r0, #3
  26499. }
  26500. 800be4a: bd38 pop {r3, r4, r5, pc}
  26501. 0800be4c <osMutexRelease>:
  26502. 800be4c: f3ef 8105 mrs r1, IPSR
  26503. rmtx = (uint32_t)mutex_id & 1U;
  26504. stat = osOK;
  26505. if (IS_IRQ()) {
  26506. 800be50: b9b9 cbnz r1, 800be82 <osMutexRelease+0x36>
  26507. stat = osErrorISR;
  26508. }
  26509. else if (hMutex == NULL) {
  26510. 800be52: 2801 cmp r0, #1
  26511. 800be54: 4602 mov r2, r0
  26512. 800be56: d917 bls.n 800be88 <osMutexRelease+0x3c>
  26513. stat = osErrorParameter;
  26514. }
  26515. else {
  26516. if (rmtx != 0U) {
  26517. 800be58: f020 0001 bic.w r0, r0, #1
  26518. osStatus_t osMutexRelease (osMutexId_t mutex_id) {
  26519. 800be5c: b508 push {r3, lr}
  26520. 800be5e: f002 0301 and.w r3, r2, #1
  26521. if (rmtx != 0U) {
  26522. 800be62: b93b cbnz r3, 800be74 <osMutexRelease+0x28>
  26523. stat = osErrorResource;
  26524. }
  26525. #endif
  26526. }
  26527. else {
  26528. if (xSemaphoreGive (hMutex) != pdPASS) {
  26529. 800be64: 461a mov r2, r3
  26530. 800be66: 4619 mov r1, r3
  26531. 800be68: f000 fa14 bl 800c294 <xQueueGenericSend>
  26532. 800be6c: 2801 cmp r0, #1
  26533. 800be6e: d105 bne.n 800be7c <osMutexRelease+0x30>
  26534. stat = osOK;
  26535. 800be70: 2000 movs r0, #0
  26536. }
  26537. }
  26538. }
  26539. return (stat);
  26540. }
  26541. 800be72: bd08 pop {r3, pc}
  26542. if (xSemaphoreGiveRecursive (hMutex) != pdPASS) {
  26543. 800be74: f000 fbe0 bl 800c638 <xQueueGiveMutexRecursive>
  26544. 800be78: 2801 cmp r0, #1
  26545. 800be7a: d0f9 beq.n 800be70 <osMutexRelease+0x24>
  26546. stat = osErrorResource;
  26547. 800be7c: f06f 0002 mvn.w r0, #2
  26548. }
  26549. 800be80: bd08 pop {r3, pc}
  26550. stat = osErrorISR;
  26551. 800be82: f06f 0005 mvn.w r0, #5
  26552. 800be86: 4770 bx lr
  26553. stat = osErrorParameter;
  26554. 800be88: f06f 0003 mvn.w r0, #3
  26555. }
  26556. 800be8c: 4770 bx lr
  26557. 800be8e: bf00 nop
  26558. 0800be90 <osMessageQueueNew>:
  26559. return (stat);
  26560. }
  26561. /*---------------------------------------------------------------------------*/
  26562. osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
  26563. 800be90: b5f0 push {r4, r5, r6, r7, lr}
  26564. 800be92: b083 sub sp, #12
  26565. 800be94: f3ef 8705 mrs r7, IPSR
  26566. const char *name;
  26567. #endif
  26568. hQueue = NULL;
  26569. if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) {
  26570. 800be98: b987 cbnz r7, 800bebc <osMessageQueueNew+0x2c>
  26571. 800be9a: 4605 mov r5, r0
  26572. 800be9c: b170 cbz r0, 800bebc <osMessageQueueNew+0x2c>
  26573. 800be9e: b169 cbz r1, 800bebc <osMessageQueueNew+0x2c>
  26574. mem = -1;
  26575. if (attr != NULL) {
  26576. 800bea0: 4614 mov r4, r2
  26577. 800bea2: b17a cbz r2, 800bec4 <osMessageQueueNew+0x34>
  26578. if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&
  26579. 800bea4: e9d2 3202 ldrd r3, r2, [r2, #8]
  26580. 800bea8: b1c3 cbz r3, 800bedc <osMessageQueueNew+0x4c>
  26581. 800beaa: 2a4f cmp r2, #79 @ 0x4f
  26582. 800beac: d906 bls.n 800bebc <osMessageQueueNew+0x2c>
  26583. (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {
  26584. 800beae: 6922 ldr r2, [r4, #16]
  26585. if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&
  26586. 800beb0: b122 cbz r2, 800bebc <osMessageQueueNew+0x2c>
  26587. (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {
  26588. 800beb2: fb01 f505 mul.w r5, r1, r5
  26589. 800beb6: 6966 ldr r6, [r4, #20]
  26590. 800beb8: 42ae cmp r6, r5
  26591. 800beba: d21e bcs.n 800befa <osMessageQueueNew+0x6a>
  26592. hQueue = NULL;
  26593. 800bebc: 2500 movs r5, #0
  26594. #endif
  26595. }
  26596. return ((osMessageQueueId_t)hQueue);
  26597. }
  26598. 800bebe: 4628 mov r0, r5
  26599. 800bec0: b003 add sp, #12
  26600. 800bec2: bdf0 pop {r4, r5, r6, r7, pc}
  26601. hQueue = xQueueCreate (msg_count, msg_size);
  26602. 800bec4: f000 f9a4 bl 800c210 <xQueueGenericCreate>
  26603. if (hQueue != NULL) {
  26604. 800bec8: 4605 mov r5, r0
  26605. 800beca: 2800 cmp r0, #0
  26606. 800becc: d0f6 beq.n 800bebc <osMessageQueueNew+0x2c>
  26607. vQueueAddToRegistry (hQueue, name);
  26608. 800bece: 4628 mov r0, r5
  26609. 800bed0: 4621 mov r1, r4
  26610. 800bed2: f000 fffd bl 800ced0 <vQueueAddToRegistry>
  26611. }
  26612. 800bed6: 4628 mov r0, r5
  26613. 800bed8: b003 add sp, #12
  26614. 800beda: bdf0 pop {r4, r5, r6, r7, pc}
  26615. if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&
  26616. 800bedc: 2a00 cmp r2, #0
  26617. 800bede: d1ed bne.n 800bebc <osMessageQueueNew+0x2c>
  26618. 800bee0: 6923 ldr r3, [r4, #16]
  26619. 800bee2: 2b00 cmp r3, #0
  26620. 800bee4: d1ea bne.n 800bebc <osMessageQueueNew+0x2c>
  26621. (attr->mq_mem == NULL) && (attr->mq_size == 0U)) {
  26622. 800bee6: 6962 ldr r2, [r4, #20]
  26623. 800bee8: 2a00 cmp r2, #0
  26624. 800beea: d1e7 bne.n 800bebc <osMessageQueueNew+0x2c>
  26625. hQueue = xQueueCreate (msg_count, msg_size);
  26626. 800beec: f000 f990 bl 800c210 <xQueueGenericCreate>
  26627. if (hQueue != NULL) {
  26628. 800bef0: 4605 mov r5, r0
  26629. 800bef2: 2800 cmp r0, #0
  26630. 800bef4: d0e2 beq.n 800bebc <osMessageQueueNew+0x2c>
  26631. name = attr->name;
  26632. 800bef6: 6824 ldr r4, [r4, #0]
  26633. 800bef8: e7e9 b.n 800bece <osMessageQueueNew+0x3e>
  26634. hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem);
  26635. 800befa: 9700 str r7, [sp, #0]
  26636. 800befc: f000 f91c bl 800c138 <xQueueGenericCreateStatic>
  26637. if (hQueue != NULL) {
  26638. 800bf00: 4605 mov r5, r0
  26639. 800bf02: 2800 cmp r0, #0
  26640. 800bf04: d1f7 bne.n 800bef6 <osMessageQueueNew+0x66>
  26641. 800bf06: e7d9 b.n 800bebc <osMessageQueueNew+0x2c>
  26642. 0800bf08 <osMessageQueuePut>:
  26643. osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
  26644. 800bf08: b560 push {r5, r6, lr}
  26645. 800bf0a: 461e mov r6, r3
  26646. 800bf0c: b083 sub sp, #12
  26647. 800bf0e: f3ef 8205 mrs r2, IPSR
  26648. (void)msg_prio; /* Message priority is ignored */
  26649. stat = osOK;
  26650. if (IS_IRQ()) {
  26651. if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
  26652. 800bf12: fab0 f580 clz r5, r0
  26653. 800bf16: fab1 f381 clz r3, r1
  26654. 800bf1a: 096d lsrs r5, r5, #5
  26655. 800bf1c: 095b lsrs r3, r3, #5
  26656. if (IS_IRQ()) {
  26657. 800bf1e: b1da cbz r2, 800bf58 <osMessageQueuePut+0x50>
  26658. if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
  26659. 800bf20: 2e00 cmp r6, #0
  26660. 800bf22: bf18 it ne
  26661. 800bf24: f043 0301 orrne.w r3, r3, #1
  26662. 800bf28: bb33 cbnz r3, 800bf78 <osMessageQueuePut+0x70>
  26663. 800bf2a: bb2d cbnz r5, 800bf78 <osMessageQueuePut+0x70>
  26664. stat = osErrorParameter;
  26665. }
  26666. else {
  26667. yield = pdFALSE;
  26668. if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) {
  26669. 800bf2c: 462b mov r3, r5
  26670. 800bf2e: aa01 add r2, sp, #4
  26671. yield = pdFALSE;
  26672. 800bf30: 9501 str r5, [sp, #4]
  26673. if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) {
  26674. 800bf32: f000 fbd9 bl 800c6e8 <xQueueGenericSendFromISR>
  26675. 800bf36: 2801 cmp r0, #1
  26676. 800bf38: d11a bne.n 800bf70 <osMessageQueuePut+0x68>
  26677. stat = osErrorResource;
  26678. } else {
  26679. portYIELD_FROM_ISR (yield);
  26680. 800bf3a: 9b01 ldr r3, [sp, #4]
  26681. 800bf3c: b14b cbz r3, 800bf52 <osMessageQueuePut+0x4a>
  26682. 800bf3e: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  26683. 800bf42: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  26684. 800bf46: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  26685. 800bf4a: f3bf 8f4f dsb sy
  26686. 800bf4e: f3bf 8f6f isb sy
  26687. stat = osOK;
  26688. 800bf52: 2000 movs r0, #0
  26689. }
  26690. }
  26691. }
  26692. return (stat);
  26693. }
  26694. 800bf54: b003 add sp, #12
  26695. 800bf56: bd60 pop {r5, r6, pc}
  26696. if ((hQueue == NULL) || (msg_ptr == NULL)) {
  26697. 800bf58: b975 cbnz r5, 800bf78 <osMessageQueuePut+0x70>
  26698. 800bf5a: b96b cbnz r3, 800bf78 <osMessageQueuePut+0x70>
  26699. if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
  26700. 800bf5c: 4632 mov r2, r6
  26701. 800bf5e: f000 f999 bl 800c294 <xQueueGenericSend>
  26702. 800bf62: 2801 cmp r0, #1
  26703. 800bf64: d0f5 beq.n 800bf52 <osMessageQueuePut+0x4a>
  26704. if (timeout != 0U) {
  26705. 800bf66: b11e cbz r6, 800bf70 <osMessageQueuePut+0x68>
  26706. stat = osErrorTimeout;
  26707. 800bf68: f06f 0001 mvn.w r0, #1
  26708. }
  26709. 800bf6c: b003 add sp, #12
  26710. 800bf6e: bd60 pop {r5, r6, pc}
  26711. stat = osErrorResource;
  26712. 800bf70: f06f 0002 mvn.w r0, #2
  26713. }
  26714. 800bf74: b003 add sp, #12
  26715. 800bf76: bd60 pop {r5, r6, pc}
  26716. stat = osErrorParameter;
  26717. 800bf78: f06f 0003 mvn.w r0, #3
  26718. return (stat);
  26719. 800bf7c: e7ea b.n 800bf54 <osMessageQueuePut+0x4c>
  26720. 800bf7e: bf00 nop
  26721. 0800bf80 <osMessageQueueGet>:
  26722. osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
  26723. 800bf80: b570 push {r4, r5, r6, lr}
  26724. 800bf82: 461e mov r6, r3
  26725. 800bf84: b082 sub sp, #8
  26726. 800bf86: f3ef 8305 mrs r3, IPSR
  26727. (void)msg_prio; /* Message priority is ignored */
  26728. stat = osOK;
  26729. if (IS_IRQ()) {
  26730. if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
  26731. 800bf8a: fab0 f580 clz r5, r0
  26732. 800bf8e: fab1 f481 clz r4, r1
  26733. 800bf92: 096d lsrs r5, r5, #5
  26734. 800bf94: 0964 lsrs r4, r4, #5
  26735. if (IS_IRQ()) {
  26736. 800bf96: b1d3 cbz r3, 800bfce <osMessageQueueGet+0x4e>
  26737. if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
  26738. 800bf98: 2e00 cmp r6, #0
  26739. 800bf9a: bf18 it ne
  26740. 800bf9c: f044 0401 orrne.w r4, r4, #1
  26741. 800bfa0: bb2c cbnz r4, 800bfee <osMessageQueueGet+0x6e>
  26742. 800bfa2: bb25 cbnz r5, 800bfee <osMessageQueueGet+0x6e>
  26743. stat = osErrorParameter;
  26744. }
  26745. else {
  26746. yield = pdFALSE;
  26747. if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) {
  26748. 800bfa4: aa01 add r2, sp, #4
  26749. yield = pdFALSE;
  26750. 800bfa6: 9501 str r5, [sp, #4]
  26751. if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) {
  26752. 800bfa8: f000 ff36 bl 800ce18 <xQueueReceiveFromISR>
  26753. 800bfac: 2801 cmp r0, #1
  26754. 800bfae: d11a bne.n 800bfe6 <osMessageQueueGet+0x66>
  26755. stat = osErrorResource;
  26756. } else {
  26757. portYIELD_FROM_ISR (yield);
  26758. 800bfb0: 9b01 ldr r3, [sp, #4]
  26759. 800bfb2: b14b cbz r3, 800bfc8 <osMessageQueueGet+0x48>
  26760. 800bfb4: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  26761. 800bfb8: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  26762. 800bfbc: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  26763. 800bfc0: f3bf 8f4f dsb sy
  26764. 800bfc4: f3bf 8f6f isb sy
  26765. stat = osOK;
  26766. 800bfc8: 2000 movs r0, #0
  26767. }
  26768. }
  26769. }
  26770. return (stat);
  26771. }
  26772. 800bfca: b002 add sp, #8
  26773. 800bfcc: bd70 pop {r4, r5, r6, pc}
  26774. if ((hQueue == NULL) || (msg_ptr == NULL)) {
  26775. 800bfce: b975 cbnz r5, 800bfee <osMessageQueueGet+0x6e>
  26776. 800bfd0: b96c cbnz r4, 800bfee <osMessageQueueGet+0x6e>
  26777. if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
  26778. 800bfd2: 4632 mov r2, r6
  26779. 800bfd4: f000 fbee bl 800c7b4 <xQueueReceive>
  26780. 800bfd8: 2801 cmp r0, #1
  26781. 800bfda: d0f5 beq.n 800bfc8 <osMessageQueueGet+0x48>
  26782. if (timeout != 0U) {
  26783. 800bfdc: b11e cbz r6, 800bfe6 <osMessageQueueGet+0x66>
  26784. stat = osErrorTimeout;
  26785. 800bfde: f06f 0001 mvn.w r0, #1
  26786. }
  26787. 800bfe2: b002 add sp, #8
  26788. 800bfe4: bd70 pop {r4, r5, r6, pc}
  26789. stat = osErrorResource;
  26790. 800bfe6: f06f 0002 mvn.w r0, #2
  26791. }
  26792. 800bfea: b002 add sp, #8
  26793. 800bfec: bd70 pop {r4, r5, r6, pc}
  26794. stat = osErrorParameter;
  26795. 800bfee: f06f 0003 mvn.w r0, #3
  26796. return (stat);
  26797. 800bff2: e7ea b.n 800bfca <osMessageQueueGet+0x4a>
  26798. 0800bff4 <vApplicationGetIdleTaskMemory>:
  26799. __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
  26800. /* Idle task control block and stack */
  26801. static StaticTask_t Idle_TCB;
  26802. static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE];
  26803. *ppxIdleTaskTCBBuffer = &Idle_TCB;
  26804. 800bff4: 4b05 ldr r3, [pc, #20] @ (800c00c <vApplicationGetIdleTaskMemory+0x18>)
  26805. __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
  26806. 800bff6: b410 push {r4}
  26807. *ppxIdleTaskTCBBuffer = &Idle_TCB;
  26808. 800bff8: 6003 str r3, [r0, #0]
  26809. *ppxIdleTaskStackBuffer = &Idle_Stack[0];
  26810. *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE;
  26811. 800bffa: f44f 7300 mov.w r3, #512 @ 0x200
  26812. *ppxIdleTaskStackBuffer = &Idle_Stack[0];
  26813. 800bffe: 4c04 ldr r4, [pc, #16] @ (800c010 <vApplicationGetIdleTaskMemory+0x1c>)
  26814. 800c000: 600c str r4, [r1, #0]
  26815. }
  26816. 800c002: f85d 4b04 ldr.w r4, [sp], #4
  26817. *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE;
  26818. 800c006: 6013 str r3, [r2, #0]
  26819. }
  26820. 800c008: 4770 bx lr
  26821. 800c00a: bf00 nop
  26822. 800c00c: 24002a58 .word 0x24002a58
  26823. 800c010: 24002258 .word 0x24002258
  26824. 0800c014 <vApplicationGetTimerTaskMemory>:
  26825. __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
  26826. /* Timer task control block and stack */
  26827. static StaticTask_t Timer_TCB;
  26828. static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH];
  26829. *ppxTimerTaskTCBBuffer = &Timer_TCB;
  26830. 800c014: 4b05 ldr r3, [pc, #20] @ (800c02c <vApplicationGetTimerTaskMemory+0x18>)
  26831. __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
  26832. 800c016: b410 push {r4}
  26833. *ppxTimerTaskTCBBuffer = &Timer_TCB;
  26834. 800c018: 6003 str r3, [r0, #0]
  26835. *ppxTimerTaskStackBuffer = &Timer_Stack[0];
  26836. *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH;
  26837. 800c01a: f44f 6380 mov.w r3, #1024 @ 0x400
  26838. *ppxTimerTaskStackBuffer = &Timer_Stack[0];
  26839. 800c01e: 4c04 ldr r4, [pc, #16] @ (800c030 <vApplicationGetTimerTaskMemory+0x1c>)
  26840. 800c020: 600c str r4, [r1, #0]
  26841. }
  26842. 800c022: f85d 4b04 ldr.w r4, [sp], #4
  26843. *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH;
  26844. 800c026: 6013 str r3, [r2, #0]
  26845. }
  26846. 800c028: 4770 bx lr
  26847. 800c02a: bf00 nop
  26848. 800c02c: 240021b0 .word 0x240021b0
  26849. 800c030: 240011b0 .word 0x240011b0
  26850. 0800c034 <vListInitialise>:
  26851. void vListInitialise( List_t * const pxList )
  26852. {
  26853. /* The list structure contains a list item which is used to mark the
  26854. end of the list. To initialise the list the list end is inserted
  26855. as the only list entry. */
  26856. pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
  26857. 800c034: f100 0308 add.w r3, r0, #8
  26858. /* The list end value is the highest possible value in the list to
  26859. ensure it remains at the end of the list. */
  26860. pxList->xListEnd.xItemValue = portMAX_DELAY;
  26861. 800c038: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
  26862. /* The list end next and previous pointers point to itself so we know
  26863. when the list is empty. */
  26864. pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
  26865. pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
  26866. pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
  26867. 800c03c: 2200 movs r2, #0
  26868. pxList->xListEnd.xItemValue = portMAX_DELAY;
  26869. 800c03e: 6081 str r1, [r0, #8]
  26870. pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
  26871. 800c040: 6002 str r2, [r0, #0]
  26872. pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
  26873. 800c042: 6043 str r3, [r0, #4]
  26874. pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
  26875. 800c044: e9c0 3303 strd r3, r3, [r0, #12]
  26876. /* Write known values into the list if
  26877. configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
  26878. listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
  26879. listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
  26880. }
  26881. 800c048: 4770 bx lr
  26882. 800c04a: bf00 nop
  26883. 0800c04c <vListInitialiseItem>:
  26884. /*-----------------------------------------------------------*/
  26885. void vListInitialiseItem( ListItem_t * const pxItem )
  26886. {
  26887. /* Make sure the list item is not recorded as being on a list. */
  26888. pxItem->pxContainer = NULL;
  26889. 800c04c: 2300 movs r3, #0
  26890. 800c04e: 6103 str r3, [r0, #16]
  26891. /* Write known values into the list item if
  26892. configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
  26893. listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
  26894. listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
  26895. }
  26896. 800c050: 4770 bx lr
  26897. 800c052: bf00 nop
  26898. 0800c054 <vListInsertEnd>:
  26899. pxIndex->pxPrevious = pxNewListItem;
  26900. /* Remember which list the item is in. */
  26901. pxNewListItem->pxContainer = pxList;
  26902. ( pxList->uxNumberOfItems )++;
  26903. 800c054: 6803 ldr r3, [r0, #0]
  26904. ListItem_t * const pxIndex = pxList->pxIndex;
  26905. 800c056: 6842 ldr r2, [r0, #4]
  26906. ( pxList->uxNumberOfItems )++;
  26907. 800c058: 3301 adds r3, #1
  26908. {
  26909. 800c05a: b410 push {r4}
  26910. pxNewListItem->pxPrevious = pxIndex->pxPrevious;
  26911. 800c05c: 6894 ldr r4, [r2, #8]
  26912. 800c05e: e9c1 2401 strd r2, r4, [r1, #4]
  26913. pxIndex->pxPrevious->pxNext = pxNewListItem;
  26914. 800c062: 6061 str r1, [r4, #4]
  26915. pxIndex->pxPrevious = pxNewListItem;
  26916. 800c064: 6091 str r1, [r2, #8]
  26917. }
  26918. 800c066: f85d 4b04 ldr.w r4, [sp], #4
  26919. pxNewListItem->pxContainer = pxList;
  26920. 800c06a: 6108 str r0, [r1, #16]
  26921. ( pxList->uxNumberOfItems )++;
  26922. 800c06c: 6003 str r3, [r0, #0]
  26923. }
  26924. 800c06e: 4770 bx lr
  26925. 0800c070 <vListInsert>:
  26926. /*-----------------------------------------------------------*/
  26927. void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
  26928. {
  26929. 800c070: b430 push {r4, r5}
  26930. ListItem_t *pxIterator;
  26931. const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
  26932. 800c072: 680d ldr r5, [r1, #0]
  26933. new list item should be placed after it. This ensures that TCBs which are
  26934. stored in ready lists (all of which have the same xItemValue value) get a
  26935. share of the CPU. However, if the xItemValue is the same as the back marker
  26936. the iteration loop below will not end. Therefore the value is checked
  26937. first, and the algorithm slightly modified if necessary. */
  26938. if( xValueOfInsertion == portMAX_DELAY )
  26939. 800c074: 1c6b adds r3, r5, #1
  26940. 800c076: d010 beq.n 800c09a <vListInsert+0x2a>
  26941. 4) Using a queue or semaphore before it has been initialised or
  26942. before the scheduler has been started (are interrupts firing
  26943. before vTaskStartScheduler() has been called?).
  26944. **********************************************************************/
  26945. for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
  26946. 800c078: f100 0308 add.w r3, r0, #8
  26947. 800c07c: 461c mov r4, r3
  26948. 800c07e: 685b ldr r3, [r3, #4]
  26949. 800c080: 681a ldr r2, [r3, #0]
  26950. 800c082: 42aa cmp r2, r5
  26951. 800c084: d9fa bls.n 800c07c <vListInsert+0xc>
  26952. /* Remember which list the item is in. This allows fast removal of the
  26953. item later. */
  26954. pxNewListItem->pxContainer = pxList;
  26955. ( pxList->uxNumberOfItems )++;
  26956. 800c086: 6802 ldr r2, [r0, #0]
  26957. pxNewListItem->pxNext = pxIterator->pxNext;
  26958. 800c088: 604b str r3, [r1, #4]
  26959. ( pxList->uxNumberOfItems )++;
  26960. 800c08a: 3201 adds r2, #1
  26961. pxNewListItem->pxNext->pxPrevious = pxNewListItem;
  26962. 800c08c: 6099 str r1, [r3, #8]
  26963. pxNewListItem->pxPrevious = pxIterator;
  26964. 800c08e: 608c str r4, [r1, #8]
  26965. pxIterator->pxNext = pxNewListItem;
  26966. 800c090: 6061 str r1, [r4, #4]
  26967. pxNewListItem->pxContainer = pxList;
  26968. 800c092: 6108 str r0, [r1, #16]
  26969. ( pxList->uxNumberOfItems )++;
  26970. 800c094: 6002 str r2, [r0, #0]
  26971. }
  26972. 800c096: bc30 pop {r4, r5}
  26973. 800c098: 4770 bx lr
  26974. pxIterator = pxList->xListEnd.pxPrevious;
  26975. 800c09a: 6904 ldr r4, [r0, #16]
  26976. pxNewListItem->pxNext = pxIterator->pxNext;
  26977. 800c09c: 6863 ldr r3, [r4, #4]
  26978. 800c09e: e7f2 b.n 800c086 <vListInsert+0x16>
  26979. 0800c0a0 <uxListRemove>:
  26980. UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
  26981. {
  26982. /* The list item knows which list it is in. Obtain the list from the list
  26983. item. */
  26984. List_t * const pxList = pxItemToRemove->pxContainer;
  26985. 800c0a0: 6903 ldr r3, [r0, #16]
  26986. {
  26987. 800c0a2: b410 push {r4}
  26988. /* Only used during decision coverage testing. */
  26989. mtCOVERAGE_TEST_DELAY();
  26990. /* Make sure the index is left pointing to a valid item. */
  26991. if( pxList->pxIndex == pxItemToRemove )
  26992. 800c0a4: 685c ldr r4, [r3, #4]
  26993. pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
  26994. 800c0a6: e9d0 1201 ldrd r1, r2, [r0, #4]
  26995. if( pxList->pxIndex == pxItemToRemove )
  26996. 800c0aa: 4284 cmp r4, r0
  26997. pxItemToRemove->pxContainer = NULL;
  26998. ( pxList->uxNumberOfItems )--;
  26999. return pxList->uxNumberOfItems;
  27000. }
  27001. 800c0ac: f85d 4b04 ldr.w r4, [sp], #4
  27002. pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
  27003. 800c0b0: 608a str r2, [r1, #8]
  27004. pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
  27005. 800c0b2: 6051 str r1, [r2, #4]
  27006. pxItemToRemove->pxContainer = NULL;
  27007. 800c0b4: f04f 0100 mov.w r1, #0
  27008. pxList->pxIndex = pxItemToRemove->pxPrevious;
  27009. 800c0b8: bf08 it eq
  27010. 800c0ba: 605a streq r2, [r3, #4]
  27011. ( pxList->uxNumberOfItems )--;
  27012. 800c0bc: 681a ldr r2, [r3, #0]
  27013. pxItemToRemove->pxContainer = NULL;
  27014. 800c0be: 6101 str r1, [r0, #16]
  27015. ( pxList->uxNumberOfItems )--;
  27016. 800c0c0: 3a01 subs r2, #1
  27017. 800c0c2: 601a str r2, [r3, #0]
  27018. return pxList->uxNumberOfItems;
  27019. 800c0c4: 6818 ldr r0, [r3, #0]
  27020. }
  27021. 800c0c6: 4770 bx lr
  27022. 0800c0c8 <prvCopyDataToQueue>:
  27023. #endif /* configUSE_MUTEXES */
  27024. /*-----------------------------------------------------------*/
  27025. static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
  27026. {
  27027. 800c0c8: b570 push {r4, r5, r6, lr}
  27028. 800c0ca: 4616 mov r6, r2
  27029. /* This function is called from a critical section. */
  27030. uxMessagesWaiting = pxQueue->uxMessagesWaiting;
  27031. if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
  27032. 800c0cc: 6c02 ldr r2, [r0, #64] @ 0x40
  27033. {
  27034. 800c0ce: 4604 mov r4, r0
  27035. uxMessagesWaiting = pxQueue->uxMessagesWaiting;
  27036. 800c0d0: 6b85 ldr r5, [r0, #56] @ 0x38
  27037. if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
  27038. 800c0d2: b92a cbnz r2, 800c0e0 <prvCopyDataToQueue+0x18>
  27039. {
  27040. #if ( configUSE_MUTEXES == 1 )
  27041. {
  27042. if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
  27043. 800c0d4: 6806 ldr r6, [r0, #0]
  27044. {
  27045. mtCOVERAGE_TEST_MARKER();
  27046. }
  27047. }
  27048. pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
  27049. 800c0d6: 3501 adds r5, #1
  27050. if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
  27051. 800c0d8: b34e cbz r6, 800c12e <prvCopyDataToQueue+0x66>
  27052. BaseType_t xReturn = pdFALSE;
  27053. 800c0da: 4610 mov r0, r2
  27054. pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
  27055. 800c0dc: 63a5 str r5, [r4, #56] @ 0x38
  27056. return xReturn;
  27057. }
  27058. 800c0de: bd70 pop {r4, r5, r6, pc}
  27059. else if( xPosition == queueSEND_TO_BACK )
  27060. 800c0e0: b97e cbnz r6, 800c102 <prvCopyDataToQueue+0x3a>
  27061. ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
  27062. 800c0e2: 6840 ldr r0, [r0, #4]
  27063. 800c0e4: f003 fde5 bl 800fcb2 <memcpy>
  27064. pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
  27065. 800c0e8: 6863 ldr r3, [r4, #4]
  27066. 800c0ea: 6c21 ldr r1, [r4, #64] @ 0x40
  27067. if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
  27068. 800c0ec: 68a2 ldr r2, [r4, #8]
  27069. pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
  27070. 800c0ee: 440b add r3, r1
  27071. if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
  27072. 800c0f0: 4293 cmp r3, r2
  27073. pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
  27074. 800c0f2: 6063 str r3, [r4, #4]
  27075. pxQueue->pcWriteTo = pxQueue->pcHead;
  27076. 800c0f4: bf24 itt cs
  27077. 800c0f6: 6823 ldrcs r3, [r4, #0]
  27078. 800c0f8: 6063 strcs r3, [r4, #4]
  27079. pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
  27080. 800c0fa: 3501 adds r5, #1
  27081. BaseType_t xReturn = pdFALSE;
  27082. 800c0fc: 2000 movs r0, #0
  27083. pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
  27084. 800c0fe: 63a5 str r5, [r4, #56] @ 0x38
  27085. }
  27086. 800c100: bd70 pop {r4, r5, r6, pc}
  27087. ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
  27088. 800c102: 68c0 ldr r0, [r0, #12]
  27089. 800c104: f003 fdd5 bl 800fcb2 <memcpy>
  27090. pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
  27091. 800c108: 6c22 ldr r2, [r4, #64] @ 0x40
  27092. 800c10a: 68e3 ldr r3, [r4, #12]
  27093. 800c10c: 4251 negs r1, r2
  27094. 800c10e: 1a9b subs r3, r3, r2
  27095. if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
  27096. 800c110: 6822 ldr r2, [r4, #0]
  27097. 800c112: 4293 cmp r3, r2
  27098. pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
  27099. 800c114: 60e3 str r3, [r4, #12]
  27100. if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
  27101. 800c116: d202 bcs.n 800c11e <prvCopyDataToQueue+0x56>
  27102. pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
  27103. 800c118: 68a3 ldr r3, [r4, #8]
  27104. 800c11a: 440b add r3, r1
  27105. 800c11c: 60e3 str r3, [r4, #12]
  27106. if( xPosition == queueOVERWRITE )
  27107. 800c11e: 2e02 cmp r6, #2
  27108. 800c120: d1eb bne.n 800c0fa <prvCopyDataToQueue+0x32>
  27109. if( uxMessagesWaiting > ( UBaseType_t ) 0 )
  27110. 800c122: 2d01 cmp r5, #1
  27111. BaseType_t xReturn = pdFALSE;
  27112. 800c124: f04f 0000 mov.w r0, #0
  27113. 800c128: bf38 it cc
  27114. 800c12a: 2501 movcc r5, #1
  27115. 800c12c: e7d6 b.n 800c0dc <prvCopyDataToQueue+0x14>
  27116. xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
  27117. 800c12e: 6880 ldr r0, [r0, #8]
  27118. 800c130: f001 fe4e bl 800ddd0 <xTaskPriorityDisinherit>
  27119. pxQueue->u.xSemaphore.xMutexHolder = NULL;
  27120. 800c134: 60a6 str r6, [r4, #8]
  27121. 800c136: e7d1 b.n 800c0dc <prvCopyDataToQueue+0x14>
  27122. 0800c138 <xQueueGenericCreateStatic>:
  27123. {
  27124. 800c138: b530 push {r4, r5, lr}
  27125. 800c13a: b083 sub sp, #12
  27126. 800c13c: f89d 5018 ldrb.w r5, [sp, #24]
  27127. configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
  27128. 800c140: b940 cbnz r0, 800c154 <xQueueGenericCreateStatic+0x1c>
  27129. portFORCE_INLINE static void vPortRaiseBASEPRI( void )
  27130. {
  27131. uint32_t ulNewBASEPRI;
  27132. __asm volatile
  27133. 800c142: f04f 0350 mov.w r3, #80 @ 0x50
  27134. 800c146: f383 8811 msr BASEPRI, r3
  27135. 800c14a: f3bf 8f6f isb sy
  27136. 800c14e: f3bf 8f4f dsb sy
  27137. 800c152: e7fe b.n 800c152 <xQueueGenericCreateStatic+0x1a>
  27138. configASSERT( pxStaticQueue != NULL );
  27139. 800c154: 461c mov r4, r3
  27140. 800c156: b153 cbz r3, 800c16e <xQueueGenericCreateStatic+0x36>
  27141. configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
  27142. 800c158: b30a cbz r2, 800c19e <xQueueGenericCreateStatic+0x66>
  27143. 800c15a: b989 cbnz r1, 800c180 <xQueueGenericCreateStatic+0x48>
  27144. 800c15c: f04f 0350 mov.w r3, #80 @ 0x50
  27145. 800c160: f383 8811 msr BASEPRI, r3
  27146. 800c164: f3bf 8f6f isb sy
  27147. 800c168: f3bf 8f4f dsb sy
  27148. 800c16c: e7fe b.n 800c16c <xQueueGenericCreateStatic+0x34>
  27149. 800c16e: f04f 0350 mov.w r3, #80 @ 0x50
  27150. 800c172: f383 8811 msr BASEPRI, r3
  27151. 800c176: f3bf 8f6f isb sy
  27152. 800c17a: f3bf 8f4f dsb sy
  27153. configASSERT( pxStaticQueue != NULL );
  27154. 800c17e: e7fe b.n 800c17e <xQueueGenericCreateStatic+0x46>
  27155. configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
  27156. 800c180: b16a cbz r2, 800c19e <xQueueGenericCreateStatic+0x66>
  27157. volatile size_t xSize = sizeof( StaticQueue_t );
  27158. 800c182: 2350 movs r3, #80 @ 0x50
  27159. 800c184: 9301 str r3, [sp, #4]
  27160. configASSERT( xSize == sizeof( Queue_t ) );
  27161. 800c186: 9b01 ldr r3, [sp, #4]
  27162. 800c188: 2b50 cmp r3, #80 @ 0x50
  27163. 800c18a: d013 beq.n 800c1b4 <xQueueGenericCreateStatic+0x7c>
  27164. 800c18c: f04f 0350 mov.w r3, #80 @ 0x50
  27165. 800c190: f383 8811 msr BASEPRI, r3
  27166. 800c194: f3bf 8f6f isb sy
  27167. 800c198: f3bf 8f4f dsb sy
  27168. 800c19c: e7fe b.n 800c19c <xQueueGenericCreateStatic+0x64>
  27169. configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
  27170. 800c19e: 2900 cmp r1, #0
  27171. 800c1a0: d0ef beq.n 800c182 <xQueueGenericCreateStatic+0x4a>
  27172. 800c1a2: f04f 0350 mov.w r3, #80 @ 0x50
  27173. 800c1a6: f383 8811 msr BASEPRI, r3
  27174. 800c1aa: f3bf 8f6f isb sy
  27175. 800c1ae: f3bf 8f4f dsb sy
  27176. 800c1b2: e7fe b.n 800c1b2 <xQueueGenericCreateStatic+0x7a>
  27177. pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
  27178. 800c1b4: 2900 cmp r1, #0
  27179. 800c1b6: bf08 it eq
  27180. 800c1b8: 4622 moveq r2, r4
  27181. ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
  27182. 800c1ba: 9b01 ldr r3, [sp, #4]
  27183. pxNewQueue->ucStaticallyAllocated = pdTRUE;
  27184. 800c1bc: 2301 movs r3, #1
  27185. pxNewQueue->uxLength = uxQueueLength;
  27186. 800c1be: 63e0 str r0, [r4, #60] @ 0x3c
  27187. 800c1c0: 6022 str r2, [r4, #0]
  27188. pxNewQueue->uxItemSize = uxItemSize;
  27189. 800c1c2: 6421 str r1, [r4, #64] @ 0x40
  27190. pxNewQueue->ucStaticallyAllocated = pdTRUE;
  27191. 800c1c4: f884 3046 strb.w r3, [r4, #70] @ 0x46
  27192. taskENTER_CRITICAL();
  27193. 800c1c8: f002 fbec bl 800e9a4 <vPortEnterCritical>
  27194. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27195. 800c1cc: 6822 ldr r2, [r4, #0]
  27196. vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
  27197. 800c1ce: f104 0010 add.w r0, r4, #16
  27198. pxQueue->pcWriteTo = pxQueue->pcHead;
  27199. 800c1d2: 6062 str r2, [r4, #4]
  27200. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27201. 800c1d4: e9d4 310f ldrd r3, r1, [r4, #60] @ 0x3c
  27202. 800c1d8: fb01 f303 mul.w r3, r1, r3
  27203. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27204. 800c1dc: 1a59 subs r1, r3, r1
  27205. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27206. 800c1de: 4413 add r3, r2
  27207. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27208. 800c1e0: 440a add r2, r1
  27209. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27210. 800c1e2: 60a3 str r3, [r4, #8]
  27211. pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
  27212. 800c1e4: 2100 movs r1, #0
  27213. pxQueue->cRxLock = queueUNLOCKED;
  27214. 800c1e6: 23ff movs r3, #255 @ 0xff
  27215. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27216. 800c1e8: 60e2 str r2, [r4, #12]
  27217. pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
  27218. 800c1ea: 63a1 str r1, [r4, #56] @ 0x38
  27219. pxQueue->cRxLock = queueUNLOCKED;
  27220. 800c1ec: f884 3044 strb.w r3, [r4, #68] @ 0x44
  27221. pxQueue->cTxLock = queueUNLOCKED;
  27222. 800c1f0: f884 3045 strb.w r3, [r4, #69] @ 0x45
  27223. vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
  27224. 800c1f4: f7ff ff1e bl 800c034 <vListInitialise>
  27225. vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
  27226. 800c1f8: f104 0024 add.w r0, r4, #36 @ 0x24
  27227. 800c1fc: f7ff ff1a bl 800c034 <vListInitialise>
  27228. taskEXIT_CRITICAL();
  27229. 800c200: f002 fbf2 bl 800e9e8 <vPortExitCritical>
  27230. }
  27231. 800c204: 4620 mov r0, r4
  27232. pxNewQueue->ucQueueType = ucQueueType;
  27233. 800c206: f884 504c strb.w r5, [r4, #76] @ 0x4c
  27234. }
  27235. 800c20a: b003 add sp, #12
  27236. 800c20c: bd30 pop {r4, r5, pc}
  27237. 800c20e: bf00 nop
  27238. 0800c210 <xQueueGenericCreate>:
  27239. {
  27240. 800c210: b5f8 push {r3, r4, r5, r6, r7, lr}
  27241. configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
  27242. 800c212: b940 cbnz r0, 800c226 <xQueueGenericCreate+0x16>
  27243. 800c214: f04f 0350 mov.w r3, #80 @ 0x50
  27244. 800c218: f383 8811 msr BASEPRI, r3
  27245. 800c21c: f3bf 8f6f isb sy
  27246. 800c220: f3bf 8f4f dsb sy
  27247. 800c224: e7fe b.n 800c224 <xQueueGenericCreate+0x14>
  27248. 800c226: 4605 mov r5, r0
  27249. xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
  27250. 800c228: fb01 f000 mul.w r0, r1, r0
  27251. 800c22c: 460e mov r6, r1
  27252. 800c22e: 4617 mov r7, r2
  27253. pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
  27254. 800c230: 3050 adds r0, #80 @ 0x50
  27255. 800c232: f002 fd17 bl 800ec64 <pvPortMalloc>
  27256. if( pxNewQueue != NULL )
  27257. 800c236: 4604 mov r4, r0
  27258. 800c238: b340 cbz r0, 800c28c <xQueueGenericCreate+0x7c>
  27259. pxNewQueue->ucStaticallyAllocated = pdFALSE;
  27260. 800c23a: 2300 movs r3, #0
  27261. 800c23c: f880 3046 strb.w r3, [r0, #70] @ 0x46
  27262. if( uxItemSize == ( UBaseType_t ) 0 )
  27263. 800c240: b336 cbz r6, 800c290 <xQueueGenericCreate+0x80>
  27264. pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27265. 800c242: f100 0350 add.w r3, r0, #80 @ 0x50
  27266. pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
  27267. 800c246: 6023 str r3, [r4, #0]
  27268. pxNewQueue->uxItemSize = uxItemSize;
  27269. 800c248: e9c4 560f strd r5, r6, [r4, #60] @ 0x3c
  27270. taskENTER_CRITICAL();
  27271. 800c24c: f002 fbaa bl 800e9a4 <vPortEnterCritical>
  27272. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27273. 800c250: 6822 ldr r2, [r4, #0]
  27274. vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
  27275. 800c252: f104 0010 add.w r0, r4, #16
  27276. pxQueue->pcWriteTo = pxQueue->pcHead;
  27277. 800c256: 6062 str r2, [r4, #4]
  27278. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27279. 800c258: e9d4 310f ldrd r3, r1, [r4, #60] @ 0x3c
  27280. 800c25c: fb01 f303 mul.w r3, r1, r3
  27281. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27282. 800c260: 1a59 subs r1, r3, r1
  27283. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27284. 800c262: 4413 add r3, r2
  27285. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27286. 800c264: 440a add r2, r1
  27287. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27288. 800c266: 60a3 str r3, [r4, #8]
  27289. pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
  27290. 800c268: 2100 movs r1, #0
  27291. pxQueue->cRxLock = queueUNLOCKED;
  27292. 800c26a: 23ff movs r3, #255 @ 0xff
  27293. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27294. 800c26c: 60e2 str r2, [r4, #12]
  27295. pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
  27296. 800c26e: 63a1 str r1, [r4, #56] @ 0x38
  27297. pxQueue->cRxLock = queueUNLOCKED;
  27298. 800c270: f884 3044 strb.w r3, [r4, #68] @ 0x44
  27299. pxQueue->cTxLock = queueUNLOCKED;
  27300. 800c274: f884 3045 strb.w r3, [r4, #69] @ 0x45
  27301. vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
  27302. 800c278: f7ff fedc bl 800c034 <vListInitialise>
  27303. vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
  27304. 800c27c: f104 0024 add.w r0, r4, #36 @ 0x24
  27305. 800c280: f7ff fed8 bl 800c034 <vListInitialise>
  27306. taskEXIT_CRITICAL();
  27307. 800c284: f002 fbb0 bl 800e9e8 <vPortExitCritical>
  27308. pxNewQueue->ucQueueType = ucQueueType;
  27309. 800c288: f884 704c strb.w r7, [r4, #76] @ 0x4c
  27310. }
  27311. 800c28c: 4620 mov r0, r4
  27312. 800c28e: bdf8 pop {r3, r4, r5, r6, r7, pc}
  27313. pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
  27314. 800c290: 4603 mov r3, r0
  27315. 800c292: e7d8 b.n 800c246 <xQueueGenericCreate+0x36>
  27316. 0800c294 <xQueueGenericSend>:
  27317. {
  27318. 800c294: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  27319. 800c298: b084 sub sp, #16
  27320. 800c29a: 9201 str r2, [sp, #4]
  27321. configASSERT( pxQueue );
  27322. 800c29c: 2800 cmp r0, #0
  27323. 800c29e: f000 8103 beq.w 800c4a8 <xQueueGenericSend+0x214>
  27324. configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
  27325. 800c2a2: 4688 mov r8, r1
  27326. 800c2a4: 4604 mov r4, r0
  27327. 800c2a6: 461f mov r7, r3
  27328. 800c2a8: 2900 cmp r1, #0
  27329. 800c2aa: f000 8097 beq.w 800c3dc <xQueueGenericSend+0x148>
  27330. configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
  27331. 800c2ae: 2f02 cmp r7, #2
  27332. 800c2b0: d10b bne.n 800c2ca <xQueueGenericSend+0x36>
  27333. 800c2b2: 6be3 ldr r3, [r4, #60] @ 0x3c
  27334. 800c2b4: 2b01 cmp r3, #1
  27335. 800c2b6: d008 beq.n 800c2ca <xQueueGenericSend+0x36>
  27336. 800c2b8: f04f 0350 mov.w r3, #80 @ 0x50
  27337. 800c2bc: f383 8811 msr BASEPRI, r3
  27338. 800c2c0: f3bf 8f6f isb sy
  27339. 800c2c4: f3bf 8f4f dsb sy
  27340. 800c2c8: e7fe b.n 800c2c8 <xQueueGenericSend+0x34>
  27341. configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
  27342. 800c2ca: f001 fd31 bl 800dd30 <xTaskGetSchedulerState>
  27343. 800c2ce: 2800 cmp r0, #0
  27344. 800c2d0: f000 80f3 beq.w 800c4ba <xQueueGenericSend+0x226>
  27345. if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
  27346. 800c2d4: f1a7 0902 sub.w r9, r7, #2
  27347. 800c2d8: 2500 movs r5, #0
  27348. {
  27349. /* Tasks that are removed from the event list will get added to
  27350. the pending ready list as the scheduler is still suspended. */
  27351. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  27352. {
  27353. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  27354. 800c2da: f104 0624 add.w r6, r4, #36 @ 0x24
  27355. if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
  27356. 800c2de: fab9 f989 clz r9, r9
  27357. 800c2e2: ea4f 1959 mov.w r9, r9, lsr #5
  27358. taskENTER_CRITICAL();
  27359. 800c2e6: f002 fb5d bl 800e9a4 <vPortEnterCritical>
  27360. if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
  27361. 800c2ea: 6ba2 ldr r2, [r4, #56] @ 0x38
  27362. 800c2ec: 6be3 ldr r3, [r4, #60] @ 0x3c
  27363. 800c2ee: 429a cmp r2, r3
  27364. 800c2f0: f0c0 80f0 bcc.w 800c4d4 <xQueueGenericSend+0x240>
  27365. 800c2f4: f1b9 0f00 cmp.w r9, #0
  27366. 800c2f8: f040 80ec bne.w 800c4d4 <xQueueGenericSend+0x240>
  27367. if( xTicksToWait == ( TickType_t ) 0 )
  27368. 800c2fc: 9b01 ldr r3, [sp, #4]
  27369. 800c2fe: 2b00 cmp r3, #0
  27370. 800c300: f000 8101 beq.w 800c506 <xQueueGenericSend+0x272>
  27371. else if( xEntryTimeSet == pdFALSE )
  27372. 800c304: 2d00 cmp r5, #0
  27373. 800c306: f000 80cb beq.w 800c4a0 <xQueueGenericSend+0x20c>
  27374. taskEXIT_CRITICAL();
  27375. 800c30a: f002 fb6d bl 800e9e8 <vPortExitCritical>
  27376. vTaskSuspendAll();
  27377. 800c30e: f001 fb41 bl 800d994 <vTaskSuspendAll>
  27378. prvLockQueue( pxQueue );
  27379. 800c312: f002 fb47 bl 800e9a4 <vPortEnterCritical>
  27380. 800c316: f894 3044 ldrb.w r3, [r4, #68] @ 0x44
  27381. 800c31a: 2bff cmp r3, #255 @ 0xff
  27382. 800c31c: d102 bne.n 800c324 <xQueueGenericSend+0x90>
  27383. 800c31e: 2300 movs r3, #0
  27384. 800c320: f884 3044 strb.w r3, [r4, #68] @ 0x44
  27385. 800c324: f894 3045 ldrb.w r3, [r4, #69] @ 0x45
  27386. 800c328: 2bff cmp r3, #255 @ 0xff
  27387. 800c32a: d102 bne.n 800c332 <xQueueGenericSend+0x9e>
  27388. 800c32c: 2300 movs r3, #0
  27389. 800c32e: f884 3045 strb.w r3, [r4, #69] @ 0x45
  27390. 800c332: f002 fb59 bl 800e9e8 <vPortExitCritical>
  27391. if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
  27392. 800c336: a901 add r1, sp, #4
  27393. 800c338: a802 add r0, sp, #8
  27394. 800c33a: f001 fcab bl 800dc94 <xTaskCheckForTimeOut>
  27395. 800c33e: 2800 cmp r0, #0
  27396. 800c340: f040 80e5 bne.w 800c50e <xQueueGenericSend+0x27a>
  27397. static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
  27398. {
  27399. BaseType_t xReturn;
  27400. taskENTER_CRITICAL();
  27401. 800c344: f002 fb2e bl 800e9a4 <vPortEnterCritical>
  27402. {
  27403. if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
  27404. 800c348: 6ba2 ldr r2, [r4, #56] @ 0x38
  27405. 800c34a: 6be3 ldr r3, [r4, #60] @ 0x3c
  27406. 800c34c: 429a cmp r2, r3
  27407. 800c34e: d052 beq.n 800c3f6 <xQueueGenericSend+0x162>
  27408. else
  27409. {
  27410. xReturn = pdFALSE;
  27411. }
  27412. }
  27413. taskEXIT_CRITICAL();
  27414. 800c350: f002 fb4a bl 800e9e8 <vPortExitCritical>
  27415. taskENTER_CRITICAL();
  27416. 800c354: f002 fb26 bl 800e9a4 <vPortEnterCritical>
  27417. int8_t cTxLock = pxQueue->cTxLock;
  27418. 800c358: f894 2045 ldrb.w r2, [r4, #69] @ 0x45
  27419. 800c35c: b255 sxtb r5, r2
  27420. while( cTxLock > queueLOCKED_UNMODIFIED )
  27421. 800c35e: 2d00 cmp r5, #0
  27422. 800c360: dc04 bgt.n 800c36c <xQueueGenericSend+0xd8>
  27423. 800c362: e011 b.n 800c388 <xQueueGenericSend+0xf4>
  27424. --cTxLock;
  27425. 800c364: 1e6a subs r2, r5, #1
  27426. 800c366: b2d3 uxtb r3, r2
  27427. 800c368: b255 sxtb r5, r2
  27428. while( cTxLock > queueLOCKED_UNMODIFIED )
  27429. 800c36a: b16b cbz r3, 800c388 <xQueueGenericSend+0xf4>
  27430. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  27431. 800c36c: 6a63 ldr r3, [r4, #36] @ 0x24
  27432. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  27433. 800c36e: 4630 mov r0, r6
  27434. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  27435. 800c370: b153 cbz r3, 800c388 <xQueueGenericSend+0xf4>
  27436. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  27437. 800c372: f001 fc21 bl 800dbb8 <xTaskRemoveFromEventList>
  27438. 800c376: 2800 cmp r0, #0
  27439. 800c378: d0f4 beq.n 800c364 <xQueueGenericSend+0xd0>
  27440. vTaskMissedYield();
  27441. 800c37a: f001 fccd bl 800dd18 <vTaskMissedYield>
  27442. --cTxLock;
  27443. 800c37e: 1e6a subs r2, r5, #1
  27444. 800c380: b2d3 uxtb r3, r2
  27445. 800c382: b255 sxtb r5, r2
  27446. while( cTxLock > queueLOCKED_UNMODIFIED )
  27447. 800c384: 2b00 cmp r3, #0
  27448. 800c386: d1f1 bne.n 800c36c <xQueueGenericSend+0xd8>
  27449. pxQueue->cTxLock = queueUNLOCKED;
  27450. 800c388: 23ff movs r3, #255 @ 0xff
  27451. 800c38a: f884 3045 strb.w r3, [r4, #69] @ 0x45
  27452. taskEXIT_CRITICAL();
  27453. 800c38e: f002 fb2b bl 800e9e8 <vPortExitCritical>
  27454. taskENTER_CRITICAL();
  27455. 800c392: f002 fb07 bl 800e9a4 <vPortEnterCritical>
  27456. int8_t cRxLock = pxQueue->cRxLock;
  27457. 800c396: f894 2044 ldrb.w r2, [r4, #68] @ 0x44
  27458. 800c39a: b255 sxtb r5, r2
  27459. while( cRxLock > queueLOCKED_UNMODIFIED )
  27460. 800c39c: 2d00 cmp r5, #0
  27461. 800c39e: dd14 ble.n 800c3ca <xQueueGenericSend+0x136>
  27462. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  27463. 800c3a0: f104 0a10 add.w sl, r4, #16
  27464. 800c3a4: e003 b.n 800c3ae <xQueueGenericSend+0x11a>
  27465. --cRxLock;
  27466. 800c3a6: 1e6a subs r2, r5, #1
  27467. 800c3a8: b2d3 uxtb r3, r2
  27468. 800c3aa: b255 sxtb r5, r2
  27469. while( cRxLock > queueLOCKED_UNMODIFIED )
  27470. 800c3ac: b16b cbz r3, 800c3ca <xQueueGenericSend+0x136>
  27471. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  27472. 800c3ae: 6923 ldr r3, [r4, #16]
  27473. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  27474. 800c3b0: 4650 mov r0, sl
  27475. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  27476. 800c3b2: b153 cbz r3, 800c3ca <xQueueGenericSend+0x136>
  27477. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  27478. 800c3b4: f001 fc00 bl 800dbb8 <xTaskRemoveFromEventList>
  27479. 800c3b8: 2800 cmp r0, #0
  27480. 800c3ba: d0f4 beq.n 800c3a6 <xQueueGenericSend+0x112>
  27481. vTaskMissedYield();
  27482. 800c3bc: f001 fcac bl 800dd18 <vTaskMissedYield>
  27483. --cRxLock;
  27484. 800c3c0: 1e6a subs r2, r5, #1
  27485. 800c3c2: b2d3 uxtb r3, r2
  27486. 800c3c4: b255 sxtb r5, r2
  27487. while( cRxLock > queueLOCKED_UNMODIFIED )
  27488. 800c3c6: 2b00 cmp r3, #0
  27489. 800c3c8: d1f1 bne.n 800c3ae <xQueueGenericSend+0x11a>
  27490. pxQueue->cRxLock = queueUNLOCKED;
  27491. 800c3ca: 23ff movs r3, #255 @ 0xff
  27492. 800c3cc: f884 3044 strb.w r3, [r4, #68] @ 0x44
  27493. taskEXIT_CRITICAL();
  27494. 800c3d0: f002 fb0a bl 800e9e8 <vPortExitCritical>
  27495. ( void ) xTaskResumeAll();
  27496. 800c3d4: f001 fae6 bl 800d9a4 <xTaskResumeAll>
  27497. if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
  27498. 800c3d8: 2501 movs r5, #1
  27499. 800c3da: e784 b.n 800c2e6 <xQueueGenericSend+0x52>
  27500. configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
  27501. 800c3dc: 6c03 ldr r3, [r0, #64] @ 0x40
  27502. 800c3de: 2b00 cmp r3, #0
  27503. 800c3e0: f43f af65 beq.w 800c2ae <xQueueGenericSend+0x1a>
  27504. 800c3e4: f04f 0350 mov.w r3, #80 @ 0x50
  27505. 800c3e8: f383 8811 msr BASEPRI, r3
  27506. 800c3ec: f3bf 8f6f isb sy
  27507. 800c3f0: f3bf 8f4f dsb sy
  27508. 800c3f4: e7fe b.n 800c3f4 <xQueueGenericSend+0x160>
  27509. vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
  27510. 800c3f6: f104 0a10 add.w sl, r4, #16
  27511. taskEXIT_CRITICAL();
  27512. 800c3fa: f002 faf5 bl 800e9e8 <vPortExitCritical>
  27513. vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
  27514. 800c3fe: 9901 ldr r1, [sp, #4]
  27515. 800c400: 4650 mov r0, sl
  27516. 800c402: f001 fb4b bl 800da9c <vTaskPlaceOnEventList>
  27517. taskENTER_CRITICAL();
  27518. 800c406: f002 facd bl 800e9a4 <vPortEnterCritical>
  27519. int8_t cTxLock = pxQueue->cTxLock;
  27520. 800c40a: f894 3045 ldrb.w r3, [r4, #69] @ 0x45
  27521. 800c40e: b25d sxtb r5, r3
  27522. while( cTxLock > queueLOCKED_UNMODIFIED )
  27523. 800c410: 2d00 cmp r5, #0
  27524. 800c412: dc04 bgt.n 800c41e <xQueueGenericSend+0x18a>
  27525. 800c414: e011 b.n 800c43a <xQueueGenericSend+0x1a6>
  27526. --cTxLock;
  27527. 800c416: 1e6b subs r3, r5, #1
  27528. 800c418: b2da uxtb r2, r3
  27529. 800c41a: b25d sxtb r5, r3
  27530. while( cTxLock > queueLOCKED_UNMODIFIED )
  27531. 800c41c: b16a cbz r2, 800c43a <xQueueGenericSend+0x1a6>
  27532. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  27533. 800c41e: 6a63 ldr r3, [r4, #36] @ 0x24
  27534. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  27535. 800c420: 4630 mov r0, r6
  27536. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  27537. 800c422: b153 cbz r3, 800c43a <xQueueGenericSend+0x1a6>
  27538. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  27539. 800c424: f001 fbc8 bl 800dbb8 <xTaskRemoveFromEventList>
  27540. 800c428: 2800 cmp r0, #0
  27541. 800c42a: d0f4 beq.n 800c416 <xQueueGenericSend+0x182>
  27542. vTaskMissedYield();
  27543. 800c42c: f001 fc74 bl 800dd18 <vTaskMissedYield>
  27544. --cTxLock;
  27545. 800c430: 1e6b subs r3, r5, #1
  27546. 800c432: b2da uxtb r2, r3
  27547. 800c434: b25d sxtb r5, r3
  27548. while( cTxLock > queueLOCKED_UNMODIFIED )
  27549. 800c436: 2a00 cmp r2, #0
  27550. 800c438: d1f1 bne.n 800c41e <xQueueGenericSend+0x18a>
  27551. pxQueue->cTxLock = queueUNLOCKED;
  27552. 800c43a: 23ff movs r3, #255 @ 0xff
  27553. 800c43c: f884 3045 strb.w r3, [r4, #69] @ 0x45
  27554. taskEXIT_CRITICAL();
  27555. 800c440: f002 fad2 bl 800e9e8 <vPortExitCritical>
  27556. taskENTER_CRITICAL();
  27557. 800c444: f002 faae bl 800e9a4 <vPortEnterCritical>
  27558. int8_t cRxLock = pxQueue->cRxLock;
  27559. 800c448: f894 3044 ldrb.w r3, [r4, #68] @ 0x44
  27560. 800c44c: b25d sxtb r5, r3
  27561. while( cRxLock > queueLOCKED_UNMODIFIED )
  27562. 800c44e: 2d00 cmp r5, #0
  27563. 800c450: dc04 bgt.n 800c45c <xQueueGenericSend+0x1c8>
  27564. 800c452: e011 b.n 800c478 <xQueueGenericSend+0x1e4>
  27565. --cRxLock;
  27566. 800c454: 1e6b subs r3, r5, #1
  27567. 800c456: b2da uxtb r2, r3
  27568. 800c458: b25d sxtb r5, r3
  27569. while( cRxLock > queueLOCKED_UNMODIFIED )
  27570. 800c45a: b16a cbz r2, 800c478 <xQueueGenericSend+0x1e4>
  27571. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  27572. 800c45c: 6923 ldr r3, [r4, #16]
  27573. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  27574. 800c45e: 4650 mov r0, sl
  27575. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  27576. 800c460: b153 cbz r3, 800c478 <xQueueGenericSend+0x1e4>
  27577. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  27578. 800c462: f001 fba9 bl 800dbb8 <xTaskRemoveFromEventList>
  27579. 800c466: 2800 cmp r0, #0
  27580. 800c468: d0f4 beq.n 800c454 <xQueueGenericSend+0x1c0>
  27581. vTaskMissedYield();
  27582. 800c46a: f001 fc55 bl 800dd18 <vTaskMissedYield>
  27583. --cRxLock;
  27584. 800c46e: 1e6b subs r3, r5, #1
  27585. 800c470: b2da uxtb r2, r3
  27586. 800c472: b25d sxtb r5, r3
  27587. while( cRxLock > queueLOCKED_UNMODIFIED )
  27588. 800c474: 2a00 cmp r2, #0
  27589. 800c476: d1f1 bne.n 800c45c <xQueueGenericSend+0x1c8>
  27590. pxQueue->cRxLock = queueUNLOCKED;
  27591. 800c478: 23ff movs r3, #255 @ 0xff
  27592. 800c47a: f884 3044 strb.w r3, [r4, #68] @ 0x44
  27593. taskEXIT_CRITICAL();
  27594. 800c47e: f002 fab3 bl 800e9e8 <vPortExitCritical>
  27595. if( xTaskResumeAll() == pdFALSE )
  27596. 800c482: f001 fa8f bl 800d9a4 <xTaskResumeAll>
  27597. 800c486: 2800 cmp r0, #0
  27598. 800c488: d1a6 bne.n 800c3d8 <xQueueGenericSend+0x144>
  27599. portYIELD_WITHIN_API();
  27600. 800c48a: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  27601. 800c48e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  27602. 800c492: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  27603. 800c496: f3bf 8f4f dsb sy
  27604. 800c49a: f3bf 8f6f isb sy
  27605. 800c49e: e79b b.n 800c3d8 <xQueueGenericSend+0x144>
  27606. vTaskInternalSetTimeOutState( &xTimeOut );
  27607. 800c4a0: a802 add r0, sp, #8
  27608. 800c4a2: f001 fbeb bl 800dc7c <vTaskInternalSetTimeOutState>
  27609. xEntryTimeSet = pdTRUE;
  27610. 800c4a6: e730 b.n 800c30a <xQueueGenericSend+0x76>
  27611. 800c4a8: f04f 0350 mov.w r3, #80 @ 0x50
  27612. 800c4ac: f383 8811 msr BASEPRI, r3
  27613. 800c4b0: f3bf 8f6f isb sy
  27614. 800c4b4: f3bf 8f4f dsb sy
  27615. configASSERT( pxQueue );
  27616. 800c4b8: e7fe b.n 800c4b8 <xQueueGenericSend+0x224>
  27617. configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
  27618. 800c4ba: 9b01 ldr r3, [sp, #4]
  27619. 800c4bc: 2b00 cmp r3, #0
  27620. 800c4be: f43f af09 beq.w 800c2d4 <xQueueGenericSend+0x40>
  27621. 800c4c2: f04f 0350 mov.w r3, #80 @ 0x50
  27622. 800c4c6: f383 8811 msr BASEPRI, r3
  27623. 800c4ca: f3bf 8f6f isb sy
  27624. 800c4ce: f3bf 8f4f dsb sy
  27625. 800c4d2: e7fe b.n 800c4d2 <xQueueGenericSend+0x23e>
  27626. xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
  27627. 800c4d4: 463a mov r2, r7
  27628. 800c4d6: 4641 mov r1, r8
  27629. 800c4d8: 4620 mov r0, r4
  27630. 800c4da: f7ff fdf5 bl 800c0c8 <prvCopyDataToQueue>
  27631. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  27632. 800c4de: 6a63 ldr r3, [r4, #36] @ 0x24
  27633. 800c4e0: 2b00 cmp r3, #0
  27634. 800c4e2: d151 bne.n 800c588 <xQueueGenericSend+0x2f4>
  27635. else if( xYieldRequired != pdFALSE )
  27636. 800c4e4: b148 cbz r0, 800c4fa <xQueueGenericSend+0x266>
  27637. queueYIELD_IF_USING_PREEMPTION();
  27638. 800c4e6: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  27639. 800c4ea: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  27640. 800c4ee: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  27641. 800c4f2: f3bf 8f4f dsb sy
  27642. 800c4f6: f3bf 8f6f isb sy
  27643. taskEXIT_CRITICAL();
  27644. 800c4fa: f002 fa75 bl 800e9e8 <vPortExitCritical>
  27645. return pdPASS;
  27646. 800c4fe: 2001 movs r0, #1
  27647. }
  27648. 800c500: b004 add sp, #16
  27649. 800c502: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  27650. taskEXIT_CRITICAL();
  27651. 800c506: f002 fa6f bl 800e9e8 <vPortExitCritical>
  27652. return errQUEUE_FULL;
  27653. 800c50a: 2000 movs r0, #0
  27654. 800c50c: e7f8 b.n 800c500 <xQueueGenericSend+0x26c>
  27655. taskENTER_CRITICAL();
  27656. 800c50e: f002 fa49 bl 800e9a4 <vPortEnterCritical>
  27657. int8_t cTxLock = pxQueue->cTxLock;
  27658. 800c512: f894 3045 ldrb.w r3, [r4, #69] @ 0x45
  27659. 800c516: b25d sxtb r5, r3
  27660. while( cTxLock > queueLOCKED_UNMODIFIED )
  27661. 800c518: 2d00 cmp r5, #0
  27662. 800c51a: dd10 ble.n 800c53e <xQueueGenericSend+0x2aa>
  27663. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  27664. 800c51c: f104 0624 add.w r6, r4, #36 @ 0x24
  27665. 800c520: e003 b.n 800c52a <xQueueGenericSend+0x296>
  27666. --cTxLock;
  27667. 800c522: 1e6b subs r3, r5, #1
  27668. 800c524: b2da uxtb r2, r3
  27669. 800c526: b25d sxtb r5, r3
  27670. while( cTxLock > queueLOCKED_UNMODIFIED )
  27671. 800c528: b14a cbz r2, 800c53e <xQueueGenericSend+0x2aa>
  27672. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  27673. 800c52a: 6a63 ldr r3, [r4, #36] @ 0x24
  27674. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  27675. 800c52c: 4630 mov r0, r6
  27676. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  27677. 800c52e: b133 cbz r3, 800c53e <xQueueGenericSend+0x2aa>
  27678. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  27679. 800c530: f001 fb42 bl 800dbb8 <xTaskRemoveFromEventList>
  27680. 800c534: 2800 cmp r0, #0
  27681. 800c536: d0f4 beq.n 800c522 <xQueueGenericSend+0x28e>
  27682. vTaskMissedYield();
  27683. 800c538: f001 fbee bl 800dd18 <vTaskMissedYield>
  27684. 800c53c: e7f1 b.n 800c522 <xQueueGenericSend+0x28e>
  27685. pxQueue->cTxLock = queueUNLOCKED;
  27686. 800c53e: 23ff movs r3, #255 @ 0xff
  27687. 800c540: f884 3045 strb.w r3, [r4, #69] @ 0x45
  27688. taskEXIT_CRITICAL();
  27689. 800c544: f002 fa50 bl 800e9e8 <vPortExitCritical>
  27690. taskENTER_CRITICAL();
  27691. 800c548: f002 fa2c bl 800e9a4 <vPortEnterCritical>
  27692. int8_t cRxLock = pxQueue->cRxLock;
  27693. 800c54c: f894 3044 ldrb.w r3, [r4, #68] @ 0x44
  27694. 800c550: b25d sxtb r5, r3
  27695. while( cRxLock > queueLOCKED_UNMODIFIED )
  27696. 800c552: 2d00 cmp r5, #0
  27697. 800c554: dd10 ble.n 800c578 <xQueueGenericSend+0x2e4>
  27698. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  27699. 800c556: f104 0610 add.w r6, r4, #16
  27700. 800c55a: e003 b.n 800c564 <xQueueGenericSend+0x2d0>
  27701. --cRxLock;
  27702. 800c55c: 1e6b subs r3, r5, #1
  27703. 800c55e: b2da uxtb r2, r3
  27704. 800c560: b25d sxtb r5, r3
  27705. while( cRxLock > queueLOCKED_UNMODIFIED )
  27706. 800c562: b14a cbz r2, 800c578 <xQueueGenericSend+0x2e4>
  27707. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  27708. 800c564: 6923 ldr r3, [r4, #16]
  27709. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  27710. 800c566: 4630 mov r0, r6
  27711. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  27712. 800c568: b133 cbz r3, 800c578 <xQueueGenericSend+0x2e4>
  27713. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  27714. 800c56a: f001 fb25 bl 800dbb8 <xTaskRemoveFromEventList>
  27715. 800c56e: 2800 cmp r0, #0
  27716. 800c570: d0f4 beq.n 800c55c <xQueueGenericSend+0x2c8>
  27717. vTaskMissedYield();
  27718. 800c572: f001 fbd1 bl 800dd18 <vTaskMissedYield>
  27719. 800c576: e7f1 b.n 800c55c <xQueueGenericSend+0x2c8>
  27720. pxQueue->cRxLock = queueUNLOCKED;
  27721. 800c578: 23ff movs r3, #255 @ 0xff
  27722. 800c57a: f884 3044 strb.w r3, [r4, #68] @ 0x44
  27723. taskEXIT_CRITICAL();
  27724. 800c57e: f002 fa33 bl 800e9e8 <vPortExitCritical>
  27725. ( void ) xTaskResumeAll();
  27726. 800c582: f001 fa0f bl 800d9a4 <xTaskResumeAll>
  27727. return errQUEUE_FULL;
  27728. 800c586: e7c0 b.n 800c50a <xQueueGenericSend+0x276>
  27729. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  27730. 800c588: f104 0024 add.w r0, r4, #36 @ 0x24
  27731. 800c58c: f001 fb14 bl 800dbb8 <xTaskRemoveFromEventList>
  27732. 800c590: 2800 cmp r0, #0
  27733. 800c592: d0b2 beq.n 800c4fa <xQueueGenericSend+0x266>
  27734. 800c594: e7a7 b.n 800c4e6 <xQueueGenericSend+0x252>
  27735. 800c596: bf00 nop
  27736. 0800c598 <xQueueCreateMutexStatic>:
  27737. configASSERT( pxStaticQueue != NULL );
  27738. 800c598: b179 cbz r1, 800c5ba <xQueueCreateMutexStatic+0x22>
  27739. volatile size_t xSize = sizeof( StaticQueue_t );
  27740. 800c59a: 2350 movs r3, #80 @ 0x50
  27741. {
  27742. 800c59c: b570 push {r4, r5, r6, lr}
  27743. 800c59e: b082 sub sp, #8
  27744. volatile size_t xSize = sizeof( StaticQueue_t );
  27745. 800c5a0: 9301 str r3, [sp, #4]
  27746. configASSERT( xSize == sizeof( Queue_t ) );
  27747. 800c5a2: 9b01 ldr r3, [sp, #4]
  27748. 800c5a4: 2b50 cmp r3, #80 @ 0x50
  27749. 800c5a6: d011 beq.n 800c5cc <xQueueCreateMutexStatic+0x34>
  27750. 800c5a8: f04f 0350 mov.w r3, #80 @ 0x50
  27751. 800c5ac: f383 8811 msr BASEPRI, r3
  27752. 800c5b0: f3bf 8f6f isb sy
  27753. 800c5b4: f3bf 8f4f dsb sy
  27754. 800c5b8: e7fe b.n 800c5b8 <xQueueCreateMutexStatic+0x20>
  27755. 800c5ba: f04f 0350 mov.w r3, #80 @ 0x50
  27756. 800c5be: f383 8811 msr BASEPRI, r3
  27757. 800c5c2: f3bf 8f6f isb sy
  27758. 800c5c6: f3bf 8f4f dsb sy
  27759. configASSERT( pxStaticQueue != NULL );
  27760. 800c5ca: e7fe b.n 800c5ca <xQueueCreateMutexStatic+0x32>
  27761. pxNewQueue->uxLength = uxQueueLength;
  27762. 800c5cc: 2600 movs r6, #0
  27763. pxNewQueue->ucStaticallyAllocated = pdTRUE;
  27764. 800c5ce: 2301 movs r3, #1
  27765. 800c5d0: 460c mov r4, r1
  27766. pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
  27767. 800c5d2: 6009 str r1, [r1, #0]
  27768. pxNewQueue->ucStaticallyAllocated = pdTRUE;
  27769. 800c5d4: f881 3046 strb.w r3, [r1, #70] @ 0x46
  27770. 800c5d8: 4605 mov r5, r0
  27771. ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
  27772. 800c5da: 9a01 ldr r2, [sp, #4]
  27773. pxNewQueue->uxLength = uxQueueLength;
  27774. 800c5dc: e9c1 360f strd r3, r6, [r1, #60] @ 0x3c
  27775. taskENTER_CRITICAL();
  27776. 800c5e0: f002 f9e0 bl 800e9a4 <vPortEnterCritical>
  27777. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27778. 800c5e4: 6821 ldr r1, [r4, #0]
  27779. pxQueue->cRxLock = queueUNLOCKED;
  27780. 800c5e6: 23ff movs r3, #255 @ 0xff
  27781. pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
  27782. 800c5e8: 63a6 str r6, [r4, #56] @ 0x38
  27783. pxQueue->pcWriteTo = pxQueue->pcHead;
  27784. 800c5ea: 6061 str r1, [r4, #4]
  27785. pxQueue->cRxLock = queueUNLOCKED;
  27786. 800c5ec: f884 3044 strb.w r3, [r4, #68] @ 0x44
  27787. pxQueue->cTxLock = queueUNLOCKED;
  27788. 800c5f0: f884 3045 strb.w r3, [r4, #69] @ 0x45
  27789. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27790. 800c5f4: e9d4 200f ldrd r2, r0, [r4, #60] @ 0x3c
  27791. 800c5f8: fb00 f202 mul.w r2, r0, r2
  27792. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27793. 800c5fc: 1a10 subs r0, r2, r0
  27794. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27795. 800c5fe: 440a add r2, r1
  27796. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27797. 800c600: 4401 add r1, r0
  27798. vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
  27799. 800c602: f104 0010 add.w r0, r4, #16
  27800. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27801. 800c606: e9c4 2102 strd r2, r1, [r4, #8]
  27802. vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
  27803. 800c60a: f7ff fd13 bl 800c034 <vListInitialise>
  27804. vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
  27805. 800c60e: f104 0024 add.w r0, r4, #36 @ 0x24
  27806. 800c612: f7ff fd0f bl 800c034 <vListInitialise>
  27807. taskEXIT_CRITICAL();
  27808. 800c616: f002 f9e7 bl 800e9e8 <vPortExitCritical>
  27809. ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
  27810. 800c61a: 4633 mov r3, r6
  27811. 800c61c: 4632 mov r2, r6
  27812. 800c61e: 4631 mov r1, r6
  27813. 800c620: 4620 mov r0, r4
  27814. pxNewQueue->ucQueueType = ucQueueType;
  27815. 800c622: f884 504c strb.w r5, [r4, #76] @ 0x4c
  27816. pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
  27817. 800c626: 60a6 str r6, [r4, #8]
  27818. pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
  27819. 800c628: 6026 str r6, [r4, #0]
  27820. pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
  27821. 800c62a: 60e6 str r6, [r4, #12]
  27822. ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
  27823. 800c62c: f7ff fe32 bl 800c294 <xQueueGenericSend>
  27824. }
  27825. 800c630: 4620 mov r0, r4
  27826. 800c632: b002 add sp, #8
  27827. 800c634: bd70 pop {r4, r5, r6, pc}
  27828. 800c636: bf00 nop
  27829. 0800c638 <xQueueGiveMutexRecursive>:
  27830. {
  27831. 800c638: b538 push {r3, r4, r5, lr}
  27832. configASSERT( pxMutex );
  27833. 800c63a: b138 cbz r0, 800c64c <xQueueGiveMutexRecursive+0x14>
  27834. if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
  27835. 800c63c: 6885 ldr r5, [r0, #8]
  27836. 800c63e: 4604 mov r4, r0
  27837. 800c640: f001 fb70 bl 800dd24 <xTaskGetCurrentTaskHandle>
  27838. 800c644: 4285 cmp r5, r0
  27839. 800c646: d00a beq.n 800c65e <xQueueGiveMutexRecursive+0x26>
  27840. xReturn = pdFAIL;
  27841. 800c648: 2000 movs r0, #0
  27842. }
  27843. 800c64a: bd38 pop {r3, r4, r5, pc}
  27844. 800c64c: f04f 0350 mov.w r3, #80 @ 0x50
  27845. 800c650: f383 8811 msr BASEPRI, r3
  27846. 800c654: f3bf 8f6f isb sy
  27847. 800c658: f3bf 8f4f dsb sy
  27848. configASSERT( pxMutex );
  27849. 800c65c: e7fe b.n 800c65c <xQueueGiveMutexRecursive+0x24>
  27850. ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
  27851. 800c65e: 68e3 ldr r3, [r4, #12]
  27852. 800c660: 3b01 subs r3, #1
  27853. 800c662: 60e3 str r3, [r4, #12]
  27854. if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
  27855. 800c664: b10b cbz r3, 800c66a <xQueueGiveMutexRecursive+0x32>
  27856. xReturn = pdPASS;
  27857. 800c666: 2001 movs r0, #1
  27858. }
  27859. 800c668: bd38 pop {r3, r4, r5, pc}
  27860. ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
  27861. 800c66a: 461a mov r2, r3
  27862. 800c66c: 4619 mov r1, r3
  27863. 800c66e: 4620 mov r0, r4
  27864. 800c670: f7ff fe10 bl 800c294 <xQueueGenericSend>
  27865. 800c674: e7f7 b.n 800c666 <xQueueGiveMutexRecursive+0x2e>
  27866. 800c676: bf00 nop
  27867. 0800c678 <xQueueCreateMutex>:
  27868. {
  27869. 800c678: b570 push {r4, r5, r6, lr}
  27870. 800c67a: 4605 mov r5, r0
  27871. pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
  27872. 800c67c: 2050 movs r0, #80 @ 0x50
  27873. 800c67e: f002 faf1 bl 800ec64 <pvPortMalloc>
  27874. if( pxNewQueue != NULL )
  27875. 800c682: 4604 mov r4, r0
  27876. 800c684: b370 cbz r0, 800c6e4 <xQueueCreateMutex+0x6c>
  27877. pxNewQueue->ucStaticallyAllocated = pdFALSE;
  27878. 800c686: 2600 movs r6, #0
  27879. pxNewQueue->uxLength = uxQueueLength;
  27880. 800c688: 2301 movs r3, #1
  27881. pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
  27882. 800c68a: 6020 str r0, [r4, #0]
  27883. pxNewQueue->ucStaticallyAllocated = pdFALSE;
  27884. 800c68c: f880 6046 strb.w r6, [r0, #70] @ 0x46
  27885. pxNewQueue->uxLength = uxQueueLength;
  27886. 800c690: e9c0 360f strd r3, r6, [r0, #60] @ 0x3c
  27887. taskENTER_CRITICAL();
  27888. 800c694: f002 f986 bl 800e9a4 <vPortEnterCritical>
  27889. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27890. 800c698: 6821 ldr r1, [r4, #0]
  27891. pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
  27892. 800c69a: 63a6 str r6, [r4, #56] @ 0x38
  27893. vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
  27894. 800c69c: f104 0010 add.w r0, r4, #16
  27895. pxQueue->pcWriteTo = pxQueue->pcHead;
  27896. 800c6a0: 6061 str r1, [r4, #4]
  27897. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27898. 800c6a2: e9d4 230f ldrd r2, r3, [r4, #60] @ 0x3c
  27899. 800c6a6: fb03 f202 mul.w r2, r3, r2
  27900. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27901. 800c6aa: 1ad3 subs r3, r2, r3
  27902. pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27903. 800c6ac: 440a add r2, r1
  27904. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27905. 800c6ae: 4419 add r1, r3
  27906. pxQueue->cRxLock = queueUNLOCKED;
  27907. 800c6b0: 23ff movs r3, #255 @ 0xff
  27908. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
  27909. 800c6b2: e9c4 2102 strd r2, r1, [r4, #8]
  27910. pxQueue->cRxLock = queueUNLOCKED;
  27911. 800c6b6: f884 3044 strb.w r3, [r4, #68] @ 0x44
  27912. pxQueue->cTxLock = queueUNLOCKED;
  27913. 800c6ba: f884 3045 strb.w r3, [r4, #69] @ 0x45
  27914. vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
  27915. 800c6be: f7ff fcb9 bl 800c034 <vListInitialise>
  27916. vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
  27917. 800c6c2: f104 0024 add.w r0, r4, #36 @ 0x24
  27918. 800c6c6: f7ff fcb5 bl 800c034 <vListInitialise>
  27919. taskEXIT_CRITICAL();
  27920. 800c6ca: f002 f98d bl 800e9e8 <vPortExitCritical>
  27921. ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
  27922. 800c6ce: 4633 mov r3, r6
  27923. 800c6d0: 4632 mov r2, r6
  27924. 800c6d2: 4631 mov r1, r6
  27925. 800c6d4: 4620 mov r0, r4
  27926. pxNewQueue->ucQueueType = ucQueueType;
  27927. 800c6d6: f884 504c strb.w r5, [r4, #76] @ 0x4c
  27928. pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
  27929. 800c6da: 60a6 str r6, [r4, #8]
  27930. pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
  27931. 800c6dc: 6026 str r6, [r4, #0]
  27932. pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
  27933. 800c6de: 60e6 str r6, [r4, #12]
  27934. ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
  27935. 800c6e0: f7ff fdd8 bl 800c294 <xQueueGenericSend>
  27936. }
  27937. 800c6e4: 4620 mov r0, r4
  27938. 800c6e6: bd70 pop {r4, r5, r6, pc}
  27939. 0800c6e8 <xQueueGenericSendFromISR>:
  27940. configASSERT( pxQueue );
  27941. 800c6e8: 2800 cmp r0, #0
  27942. 800c6ea: d04b beq.n 800c784 <xQueueGenericSendFromISR+0x9c>
  27943. {
  27944. 800c6ec: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  27945. 800c6f0: 460e mov r6, r1
  27946. 800c6f2: 4604 mov r4, r0
  27947. 800c6f4: 4617 mov r7, r2
  27948. 800c6f6: 461d mov r5, r3
  27949. configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
  27950. 800c6f8: b339 cbz r1, 800c74a <xQueueGenericSendFromISR+0x62>
  27951. configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
  27952. 800c6fa: 2d02 cmp r5, #2
  27953. 800c6fc: d10b bne.n 800c716 <xQueueGenericSendFromISR+0x2e>
  27954. 800c6fe: 6be3 ldr r3, [r4, #60] @ 0x3c
  27955. 800c700: 2b01 cmp r3, #1
  27956. 800c702: d008 beq.n 800c716 <xQueueGenericSendFromISR+0x2e>
  27957. 800c704: f04f 0350 mov.w r3, #80 @ 0x50
  27958. 800c708: f383 8811 msr BASEPRI, r3
  27959. 800c70c: f3bf 8f6f isb sy
  27960. 800c710: f3bf 8f4f dsb sy
  27961. 800c714: e7fe b.n 800c714 <xQueueGenericSendFromISR+0x2c>
  27962. portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
  27963. 800c716: f002 fa77 bl 800ec08 <vPortValidateInterruptPriority>
  27964. portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
  27965. {
  27966. uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
  27967. __asm volatile
  27968. 800c71a: f3ef 8811 mrs r8, BASEPRI
  27969. 800c71e: f04f 0350 mov.w r3, #80 @ 0x50
  27970. 800c722: f383 8811 msr BASEPRI, r3
  27971. 800c726: f3bf 8f6f isb sy
  27972. 800c72a: f3bf 8f4f dsb sy
  27973. if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
  27974. 800c72e: 6ba2 ldr r2, [r4, #56] @ 0x38
  27975. 800c730: 6be3 ldr r3, [r4, #60] @ 0x3c
  27976. 800c732: 429a cmp r2, r3
  27977. 800c734: d315 bcc.n 800c762 <xQueueGenericSendFromISR+0x7a>
  27978. 800c736: f1a5 0002 sub.w r0, r5, #2
  27979. 800c73a: fab0 f080 clz r0, r0
  27980. 800c73e: 0940 lsrs r0, r0, #5
  27981. 800c740: b978 cbnz r0, 800c762 <xQueueGenericSendFromISR+0x7a>
  27982. }
  27983. /*-----------------------------------------------------------*/
  27984. portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
  27985. {
  27986. __asm volatile
  27987. 800c742: f388 8811 msr BASEPRI, r8
  27988. }
  27989. 800c746: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  27990. configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
  27991. 800c74a: 6c03 ldr r3, [r0, #64] @ 0x40
  27992. 800c74c: 2b00 cmp r3, #0
  27993. 800c74e: d0d4 beq.n 800c6fa <xQueueGenericSendFromISR+0x12>
  27994. __asm volatile
  27995. 800c750: f04f 0350 mov.w r3, #80 @ 0x50
  27996. 800c754: f383 8811 msr BASEPRI, r3
  27997. 800c758: f3bf 8f6f isb sy
  27998. 800c75c: f3bf 8f4f dsb sy
  27999. 800c760: e7fe b.n 800c760 <xQueueGenericSendFromISR+0x78>
  28000. ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
  28001. 800c762: 462a mov r2, r5
  28002. const int8_t cTxLock = pxQueue->cTxLock;
  28003. 800c764: f894 5045 ldrb.w r5, [r4, #69] @ 0x45
  28004. ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
  28005. 800c768: 4631 mov r1, r6
  28006. 800c76a: 4620 mov r0, r4
  28007. const int8_t cTxLock = pxQueue->cTxLock;
  28008. 800c76c: b26d sxtb r5, r5
  28009. const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
  28010. 800c76e: 6ba3 ldr r3, [r4, #56] @ 0x38
  28011. ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
  28012. 800c770: f7ff fcaa bl 800c0c8 <prvCopyDataToQueue>
  28013. if( cTxLock == queueUNLOCKED )
  28014. 800c774: 1c6b adds r3, r5, #1
  28015. 800c776: d00e beq.n 800c796 <xQueueGenericSendFromISR+0xae>
  28016. pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
  28017. 800c778: 1c6b adds r3, r5, #1
  28018. 800c77a: b25b sxtb r3, r3
  28019. 800c77c: f884 3045 strb.w r3, [r4, #69] @ 0x45
  28020. xReturn = pdPASS;
  28021. 800c780: 2001 movs r0, #1
  28022. 800c782: e7de b.n 800c742 <xQueueGenericSendFromISR+0x5a>
  28023. 800c784: f04f 0350 mov.w r3, #80 @ 0x50
  28024. 800c788: f383 8811 msr BASEPRI, r3
  28025. 800c78c: f3bf 8f6f isb sy
  28026. 800c790: f3bf 8f4f dsb sy
  28027. configASSERT( pxQueue );
  28028. 800c794: e7fe b.n 800c794 <xQueueGenericSendFromISR+0xac>
  28029. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28030. 800c796: 6a63 ldr r3, [r4, #36] @ 0x24
  28031. 800c798: 2b00 cmp r3, #0
  28032. 800c79a: d0f1 beq.n 800c780 <xQueueGenericSendFromISR+0x98>
  28033. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28034. 800c79c: f104 0024 add.w r0, r4, #36 @ 0x24
  28035. 800c7a0: f001 fa0a bl 800dbb8 <xTaskRemoveFromEventList>
  28036. if( pxHigherPriorityTaskWoken != NULL )
  28037. 800c7a4: 2800 cmp r0, #0
  28038. 800c7a6: d0eb beq.n 800c780 <xQueueGenericSendFromISR+0x98>
  28039. 800c7a8: 2f00 cmp r7, #0
  28040. 800c7aa: d0e9 beq.n 800c780 <xQueueGenericSendFromISR+0x98>
  28041. *pxHigherPriorityTaskWoken = pdTRUE;
  28042. 800c7ac: 2301 movs r3, #1
  28043. 800c7ae: 603b str r3, [r7, #0]
  28044. 800c7b0: e7e6 b.n 800c780 <xQueueGenericSendFromISR+0x98>
  28045. 800c7b2: bf00 nop
  28046. 0800c7b4 <xQueueReceive>:
  28047. {
  28048. 800c7b4: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
  28049. 800c7b8: b085 sub sp, #20
  28050. 800c7ba: 9201 str r2, [sp, #4]
  28051. configASSERT( ( pxQueue ) );
  28052. 800c7bc: 2800 cmp r0, #0
  28053. 800c7be: f000 8164 beq.w 800ca8a <xQueueReceive+0x2d6>
  28054. configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
  28055. 800c7c2: 460f mov r7, r1
  28056. 800c7c4: 4604 mov r4, r0
  28057. 800c7c6: 2900 cmp r1, #0
  28058. 800c7c8: f000 8097 beq.w 800c8fa <xQueueReceive+0x146>
  28059. configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
  28060. 800c7cc: f001 fab0 bl 800dd30 <xTaskGetSchedulerState>
  28061. 800c7d0: 2800 cmp r0, #0
  28062. 800c7d2: f000 809f beq.w 800c914 <xQueueReceive+0x160>
  28063. taskENTER_CRITICAL();
  28064. 800c7d6: f002 f8e5 bl 800e9a4 <vPortEnterCritical>
  28065. const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
  28066. 800c7da: 6ba5 ldr r5, [r4, #56] @ 0x38
  28067. if( uxMessagesWaiting > ( UBaseType_t ) 0 )
  28068. 800c7dc: 2d00 cmp r5, #0
  28069. 800c7de: d175 bne.n 800c8cc <xQueueReceive+0x118>
  28070. if( xTicksToWait == ( TickType_t ) 0 )
  28071. 800c7e0: 9b01 ldr r3, [sp, #4]
  28072. 800c7e2: 2b00 cmp r3, #0
  28073. 800c7e4: f000 80f4 beq.w 800c9d0 <xQueueReceive+0x21c>
  28074. prvLockQueue( pxQueue );
  28075. 800c7e8: 46a8 mov r8, r5
  28076. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28077. 800c7ea: f104 0624 add.w r6, r4, #36 @ 0x24
  28078. vTaskInternalSetTimeOutState( &xTimeOut );
  28079. 800c7ee: a802 add r0, sp, #8
  28080. 800c7f0: f001 fa44 bl 800dc7c <vTaskInternalSetTimeOutState>
  28081. taskEXIT_CRITICAL();
  28082. 800c7f4: f002 f8f8 bl 800e9e8 <vPortExitCritical>
  28083. vTaskSuspendAll();
  28084. 800c7f8: f001 f8cc bl 800d994 <vTaskSuspendAll>
  28085. prvLockQueue( pxQueue );
  28086. 800c7fc: f002 f8d2 bl 800e9a4 <vPortEnterCritical>
  28087. 800c800: f894 3044 ldrb.w r3, [r4, #68] @ 0x44
  28088. 800c804: 2bff cmp r3, #255 @ 0xff
  28089. 800c806: d101 bne.n 800c80c <xQueueReceive+0x58>
  28090. 800c808: f884 8044 strb.w r8, [r4, #68] @ 0x44
  28091. 800c80c: f894 3045 ldrb.w r3, [r4, #69] @ 0x45
  28092. 800c810: 2bff cmp r3, #255 @ 0xff
  28093. 800c812: d101 bne.n 800c818 <xQueueReceive+0x64>
  28094. 800c814: f884 8045 strb.w r8, [r4, #69] @ 0x45
  28095. 800c818: f002 f8e6 bl 800e9e8 <vPortExitCritical>
  28096. if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
  28097. 800c81c: a901 add r1, sp, #4
  28098. 800c81e: a802 add r0, sp, #8
  28099. 800c820: f001 fa38 bl 800dc94 <xTaskCheckForTimeOut>
  28100. 800c824: 2800 cmp r0, #0
  28101. 800c826: f040 8082 bne.w 800c92e <xQueueReceive+0x17a>
  28102. taskENTER_CRITICAL();
  28103. 800c82a: f002 f8bb bl 800e9a4 <vPortEnterCritical>
  28104. if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
  28105. 800c82e: 6ba3 ldr r3, [r4, #56] @ 0x38
  28106. 800c830: 2b00 cmp r3, #0
  28107. 800c832: f000 80d3 beq.w 800c9dc <xQueueReceive+0x228>
  28108. taskEXIT_CRITICAL();
  28109. 800c836: f002 f8d7 bl 800e9e8 <vPortExitCritical>
  28110. taskENTER_CRITICAL();
  28111. 800c83a: f002 f8b3 bl 800e9a4 <vPortEnterCritical>
  28112. int8_t cTxLock = pxQueue->cTxLock;
  28113. 800c83e: f894 3045 ldrb.w r3, [r4, #69] @ 0x45
  28114. 800c842: b25d sxtb r5, r3
  28115. while( cTxLock > queueLOCKED_UNMODIFIED )
  28116. 800c844: 2d00 cmp r5, #0
  28117. 800c846: dd14 ble.n 800c872 <xQueueReceive+0xbe>
  28118. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28119. 800c848: f104 0924 add.w r9, r4, #36 @ 0x24
  28120. 800c84c: e003 b.n 800c856 <xQueueReceive+0xa2>
  28121. --cTxLock;
  28122. 800c84e: 1e6b subs r3, r5, #1
  28123. 800c850: b2da uxtb r2, r3
  28124. 800c852: b25d sxtb r5, r3
  28125. while( cTxLock > queueLOCKED_UNMODIFIED )
  28126. 800c854: b16a cbz r2, 800c872 <xQueueReceive+0xbe>
  28127. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28128. 800c856: 6a63 ldr r3, [r4, #36] @ 0x24
  28129. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28130. 800c858: 4648 mov r0, r9
  28131. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28132. 800c85a: b153 cbz r3, 800c872 <xQueueReceive+0xbe>
  28133. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28134. 800c85c: f001 f9ac bl 800dbb8 <xTaskRemoveFromEventList>
  28135. 800c860: 2800 cmp r0, #0
  28136. 800c862: d0f4 beq.n 800c84e <xQueueReceive+0x9a>
  28137. vTaskMissedYield();
  28138. 800c864: f001 fa58 bl 800dd18 <vTaskMissedYield>
  28139. --cTxLock;
  28140. 800c868: 1e6b subs r3, r5, #1
  28141. 800c86a: b2da uxtb r2, r3
  28142. 800c86c: b25d sxtb r5, r3
  28143. while( cTxLock > queueLOCKED_UNMODIFIED )
  28144. 800c86e: 2a00 cmp r2, #0
  28145. 800c870: d1f1 bne.n 800c856 <xQueueReceive+0xa2>
  28146. pxQueue->cTxLock = queueUNLOCKED;
  28147. 800c872: 23ff movs r3, #255 @ 0xff
  28148. 800c874: f884 3045 strb.w r3, [r4, #69] @ 0x45
  28149. taskEXIT_CRITICAL();
  28150. 800c878: f002 f8b6 bl 800e9e8 <vPortExitCritical>
  28151. taskENTER_CRITICAL();
  28152. 800c87c: f002 f892 bl 800e9a4 <vPortEnterCritical>
  28153. int8_t cRxLock = pxQueue->cRxLock;
  28154. 800c880: f894 3044 ldrb.w r3, [r4, #68] @ 0x44
  28155. 800c884: b25d sxtb r5, r3
  28156. while( cRxLock > queueLOCKED_UNMODIFIED )
  28157. 800c886: 2d00 cmp r5, #0
  28158. 800c888: dd14 ble.n 800c8b4 <xQueueReceive+0x100>
  28159. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28160. 800c88a: f104 0910 add.w r9, r4, #16
  28161. 800c88e: e003 b.n 800c898 <xQueueReceive+0xe4>
  28162. --cRxLock;
  28163. 800c890: 1e6b subs r3, r5, #1
  28164. 800c892: b2da uxtb r2, r3
  28165. 800c894: b25d sxtb r5, r3
  28166. while( cRxLock > queueLOCKED_UNMODIFIED )
  28167. 800c896: b16a cbz r2, 800c8b4 <xQueueReceive+0x100>
  28168. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28169. 800c898: 6923 ldr r3, [r4, #16]
  28170. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28171. 800c89a: 4648 mov r0, r9
  28172. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28173. 800c89c: b153 cbz r3, 800c8b4 <xQueueReceive+0x100>
  28174. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28175. 800c89e: f001 f98b bl 800dbb8 <xTaskRemoveFromEventList>
  28176. 800c8a2: 2800 cmp r0, #0
  28177. 800c8a4: d0f4 beq.n 800c890 <xQueueReceive+0xdc>
  28178. vTaskMissedYield();
  28179. 800c8a6: f001 fa37 bl 800dd18 <vTaskMissedYield>
  28180. --cRxLock;
  28181. 800c8aa: 1e6b subs r3, r5, #1
  28182. 800c8ac: b2da uxtb r2, r3
  28183. 800c8ae: b25d sxtb r5, r3
  28184. while( cRxLock > queueLOCKED_UNMODIFIED )
  28185. 800c8b0: 2a00 cmp r2, #0
  28186. 800c8b2: d1f1 bne.n 800c898 <xQueueReceive+0xe4>
  28187. pxQueue->cRxLock = queueUNLOCKED;
  28188. 800c8b4: 23ff movs r3, #255 @ 0xff
  28189. 800c8b6: f884 3044 strb.w r3, [r4, #68] @ 0x44
  28190. taskEXIT_CRITICAL();
  28191. 800c8ba: f002 f895 bl 800e9e8 <vPortExitCritical>
  28192. ( void ) xTaskResumeAll();
  28193. 800c8be: f001 f871 bl 800d9a4 <xTaskResumeAll>
  28194. taskENTER_CRITICAL();
  28195. 800c8c2: f002 f86f bl 800e9a4 <vPortEnterCritical>
  28196. const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
  28197. 800c8c6: 6ba5 ldr r5, [r4, #56] @ 0x38
  28198. if( uxMessagesWaiting > ( UBaseType_t ) 0 )
  28199. 800c8c8: 2d00 cmp r5, #0
  28200. 800c8ca: d07d beq.n 800c9c8 <xQueueReceive+0x214>
  28201. if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
  28202. 800c8cc: 6c22 ldr r2, [r4, #64] @ 0x40
  28203. 800c8ce: b152 cbz r2, 800c8e6 <xQueueReceive+0x132>
  28204. pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
  28205. 800c8d0: 68e1 ldr r1, [r4, #12]
  28206. if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
  28207. 800c8d2: 68a3 ldr r3, [r4, #8]
  28208. pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
  28209. 800c8d4: 4411 add r1, r2
  28210. if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
  28211. 800c8d6: 4299 cmp r1, r3
  28212. pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
  28213. 800c8d8: 60e1 str r1, [r4, #12]
  28214. if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
  28215. 800c8da: d301 bcc.n 800c8e0 <xQueueReceive+0x12c>
  28216. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
  28217. 800c8dc: 6821 ldr r1, [r4, #0]
  28218. 800c8de: 60e1 str r1, [r4, #12]
  28219. ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
  28220. 800c8e0: 4638 mov r0, r7
  28221. 800c8e2: f003 f9e6 bl 800fcb2 <memcpy>
  28222. pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
  28223. 800c8e6: 3d01 subs r5, #1
  28224. 800c8e8: 63a5 str r5, [r4, #56] @ 0x38
  28225. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28226. 800c8ea: 6923 ldr r3, [r4, #16]
  28227. 800c8ec: 2b00 cmp r3, #0
  28228. 800c8ee: f040 80d5 bne.w 800ca9c <xQueueReceive+0x2e8>
  28229. taskEXIT_CRITICAL();
  28230. 800c8f2: f002 f879 bl 800e9e8 <vPortExitCritical>
  28231. return pdPASS;
  28232. 800c8f6: 2001 movs r0, #1
  28233. 800c8f8: e06d b.n 800c9d6 <xQueueReceive+0x222>
  28234. configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
  28235. 800c8fa: 6c03 ldr r3, [r0, #64] @ 0x40
  28236. 800c8fc: 2b00 cmp r3, #0
  28237. 800c8fe: f43f af65 beq.w 800c7cc <xQueueReceive+0x18>
  28238. 800c902: f04f 0350 mov.w r3, #80 @ 0x50
  28239. 800c906: f383 8811 msr BASEPRI, r3
  28240. 800c90a: f3bf 8f6f isb sy
  28241. 800c90e: f3bf 8f4f dsb sy
  28242. 800c912: e7fe b.n 800c912 <xQueueReceive+0x15e>
  28243. configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
  28244. 800c914: 9b01 ldr r3, [sp, #4]
  28245. 800c916: 2b00 cmp r3, #0
  28246. 800c918: f43f af5d beq.w 800c7d6 <xQueueReceive+0x22>
  28247. 800c91c: f04f 0350 mov.w r3, #80 @ 0x50
  28248. 800c920: f383 8811 msr BASEPRI, r3
  28249. 800c924: f3bf 8f6f isb sy
  28250. 800c928: f3bf 8f4f dsb sy
  28251. 800c92c: e7fe b.n 800c92c <xQueueReceive+0x178>
  28252. taskENTER_CRITICAL();
  28253. 800c92e: f002 f839 bl 800e9a4 <vPortEnterCritical>
  28254. int8_t cTxLock = pxQueue->cTxLock;
  28255. 800c932: f894 3045 ldrb.w r3, [r4, #69] @ 0x45
  28256. 800c936: b25d sxtb r5, r3
  28257. while( cTxLock > queueLOCKED_UNMODIFIED )
  28258. 800c938: 2d00 cmp r5, #0
  28259. 800c93a: dc04 bgt.n 800c946 <xQueueReceive+0x192>
  28260. 800c93c: e011 b.n 800c962 <xQueueReceive+0x1ae>
  28261. --cTxLock;
  28262. 800c93e: 1e6b subs r3, r5, #1
  28263. 800c940: b2da uxtb r2, r3
  28264. 800c942: b25d sxtb r5, r3
  28265. while( cTxLock > queueLOCKED_UNMODIFIED )
  28266. 800c944: b16a cbz r2, 800c962 <xQueueReceive+0x1ae>
  28267. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28268. 800c946: 6a63 ldr r3, [r4, #36] @ 0x24
  28269. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28270. 800c948: 4630 mov r0, r6
  28271. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28272. 800c94a: b153 cbz r3, 800c962 <xQueueReceive+0x1ae>
  28273. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28274. 800c94c: f001 f934 bl 800dbb8 <xTaskRemoveFromEventList>
  28275. 800c950: 2800 cmp r0, #0
  28276. 800c952: d0f4 beq.n 800c93e <xQueueReceive+0x18a>
  28277. vTaskMissedYield();
  28278. 800c954: f001 f9e0 bl 800dd18 <vTaskMissedYield>
  28279. --cTxLock;
  28280. 800c958: 1e6b subs r3, r5, #1
  28281. 800c95a: b2da uxtb r2, r3
  28282. 800c95c: b25d sxtb r5, r3
  28283. while( cTxLock > queueLOCKED_UNMODIFIED )
  28284. 800c95e: 2a00 cmp r2, #0
  28285. 800c960: d1f1 bne.n 800c946 <xQueueReceive+0x192>
  28286. pxQueue->cTxLock = queueUNLOCKED;
  28287. 800c962: 23ff movs r3, #255 @ 0xff
  28288. 800c964: f884 3045 strb.w r3, [r4, #69] @ 0x45
  28289. taskEXIT_CRITICAL();
  28290. 800c968: f002 f83e bl 800e9e8 <vPortExitCritical>
  28291. taskENTER_CRITICAL();
  28292. 800c96c: f002 f81a bl 800e9a4 <vPortEnterCritical>
  28293. int8_t cRxLock = pxQueue->cRxLock;
  28294. 800c970: f894 3044 ldrb.w r3, [r4, #68] @ 0x44
  28295. 800c974: b25d sxtb r5, r3
  28296. while( cRxLock > queueLOCKED_UNMODIFIED )
  28297. 800c976: 2d00 cmp r5, #0
  28298. 800c978: dd14 ble.n 800c9a4 <xQueueReceive+0x1f0>
  28299. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28300. 800c97a: f104 0910 add.w r9, r4, #16
  28301. 800c97e: e003 b.n 800c988 <xQueueReceive+0x1d4>
  28302. --cRxLock;
  28303. 800c980: 1e6b subs r3, r5, #1
  28304. 800c982: b2da uxtb r2, r3
  28305. 800c984: b25d sxtb r5, r3
  28306. while( cRxLock > queueLOCKED_UNMODIFIED )
  28307. 800c986: b16a cbz r2, 800c9a4 <xQueueReceive+0x1f0>
  28308. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28309. 800c988: 6923 ldr r3, [r4, #16]
  28310. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28311. 800c98a: 4648 mov r0, r9
  28312. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28313. 800c98c: b153 cbz r3, 800c9a4 <xQueueReceive+0x1f0>
  28314. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28315. 800c98e: f001 f913 bl 800dbb8 <xTaskRemoveFromEventList>
  28316. 800c992: 2800 cmp r0, #0
  28317. 800c994: d0f4 beq.n 800c980 <xQueueReceive+0x1cc>
  28318. vTaskMissedYield();
  28319. 800c996: f001 f9bf bl 800dd18 <vTaskMissedYield>
  28320. --cRxLock;
  28321. 800c99a: 1e6b subs r3, r5, #1
  28322. 800c99c: b2da uxtb r2, r3
  28323. 800c99e: b25d sxtb r5, r3
  28324. while( cRxLock > queueLOCKED_UNMODIFIED )
  28325. 800c9a0: 2a00 cmp r2, #0
  28326. 800c9a2: d1f1 bne.n 800c988 <xQueueReceive+0x1d4>
  28327. pxQueue->cRxLock = queueUNLOCKED;
  28328. 800c9a4: 23ff movs r3, #255 @ 0xff
  28329. 800c9a6: f884 3044 strb.w r3, [r4, #68] @ 0x44
  28330. taskEXIT_CRITICAL();
  28331. 800c9aa: f002 f81d bl 800e9e8 <vPortExitCritical>
  28332. ( void ) xTaskResumeAll();
  28333. 800c9ae: f000 fff9 bl 800d9a4 <xTaskResumeAll>
  28334. taskENTER_CRITICAL();
  28335. 800c9b2: f001 fff7 bl 800e9a4 <vPortEnterCritical>
  28336. if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
  28337. 800c9b6: 6ba3 ldr r3, [r4, #56] @ 0x38
  28338. 800c9b8: b153 cbz r3, 800c9d0 <xQueueReceive+0x21c>
  28339. taskEXIT_CRITICAL();
  28340. 800c9ba: f002 f815 bl 800e9e8 <vPortExitCritical>
  28341. taskENTER_CRITICAL();
  28342. 800c9be: f001 fff1 bl 800e9a4 <vPortEnterCritical>
  28343. const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
  28344. 800c9c2: 6ba5 ldr r5, [r4, #56] @ 0x38
  28345. if( uxMessagesWaiting > ( UBaseType_t ) 0 )
  28346. 800c9c4: 2d00 cmp r5, #0
  28347. 800c9c6: d181 bne.n 800c8cc <xQueueReceive+0x118>
  28348. if( xTicksToWait == ( TickType_t ) 0 )
  28349. 800c9c8: 9b01 ldr r3, [sp, #4]
  28350. 800c9ca: 2b00 cmp r3, #0
  28351. 800c9cc: f47f af12 bne.w 800c7f4 <xQueueReceive+0x40>
  28352. taskEXIT_CRITICAL();
  28353. 800c9d0: f002 f80a bl 800e9e8 <vPortExitCritical>
  28354. return errQUEUE_EMPTY;
  28355. 800c9d4: 2000 movs r0, #0
  28356. }
  28357. 800c9d6: b005 add sp, #20
  28358. 800c9d8: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
  28359. vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
  28360. 800c9dc: f104 0924 add.w r9, r4, #36 @ 0x24
  28361. taskEXIT_CRITICAL();
  28362. 800c9e0: f002 f802 bl 800e9e8 <vPortExitCritical>
  28363. vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
  28364. 800c9e4: 9901 ldr r1, [sp, #4]
  28365. 800c9e6: 4648 mov r0, r9
  28366. 800c9e8: f001 f858 bl 800da9c <vTaskPlaceOnEventList>
  28367. taskENTER_CRITICAL();
  28368. 800c9ec: f001 ffda bl 800e9a4 <vPortEnterCritical>
  28369. int8_t cTxLock = pxQueue->cTxLock;
  28370. 800c9f0: f894 3045 ldrb.w r3, [r4, #69] @ 0x45
  28371. 800c9f4: b25d sxtb r5, r3
  28372. while( cTxLock > queueLOCKED_UNMODIFIED )
  28373. 800c9f6: 2d00 cmp r5, #0
  28374. 800c9f8: dc04 bgt.n 800ca04 <xQueueReceive+0x250>
  28375. 800c9fa: e011 b.n 800ca20 <xQueueReceive+0x26c>
  28376. --cTxLock;
  28377. 800c9fc: 1e6b subs r3, r5, #1
  28378. 800c9fe: b2da uxtb r2, r3
  28379. 800ca00: b25d sxtb r5, r3
  28380. while( cTxLock > queueLOCKED_UNMODIFIED )
  28381. 800ca02: b16a cbz r2, 800ca20 <xQueueReceive+0x26c>
  28382. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28383. 800ca04: 6a63 ldr r3, [r4, #36] @ 0x24
  28384. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28385. 800ca06: 4648 mov r0, r9
  28386. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28387. 800ca08: b153 cbz r3, 800ca20 <xQueueReceive+0x26c>
  28388. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28389. 800ca0a: f001 f8d5 bl 800dbb8 <xTaskRemoveFromEventList>
  28390. 800ca0e: 2800 cmp r0, #0
  28391. 800ca10: d0f4 beq.n 800c9fc <xQueueReceive+0x248>
  28392. vTaskMissedYield();
  28393. 800ca12: f001 f981 bl 800dd18 <vTaskMissedYield>
  28394. --cTxLock;
  28395. 800ca16: 1e6b subs r3, r5, #1
  28396. 800ca18: b2da uxtb r2, r3
  28397. 800ca1a: b25d sxtb r5, r3
  28398. while( cTxLock > queueLOCKED_UNMODIFIED )
  28399. 800ca1c: 2a00 cmp r2, #0
  28400. 800ca1e: d1f1 bne.n 800ca04 <xQueueReceive+0x250>
  28401. pxQueue->cTxLock = queueUNLOCKED;
  28402. 800ca20: 23ff movs r3, #255 @ 0xff
  28403. 800ca22: f884 3045 strb.w r3, [r4, #69] @ 0x45
  28404. taskEXIT_CRITICAL();
  28405. 800ca26: f001 ffdf bl 800e9e8 <vPortExitCritical>
  28406. taskENTER_CRITICAL();
  28407. 800ca2a: f001 ffbb bl 800e9a4 <vPortEnterCritical>
  28408. int8_t cRxLock = pxQueue->cRxLock;
  28409. 800ca2e: f894 3044 ldrb.w r3, [r4, #68] @ 0x44
  28410. 800ca32: b25d sxtb r5, r3
  28411. while( cRxLock > queueLOCKED_UNMODIFIED )
  28412. 800ca34: 2d00 cmp r5, #0
  28413. 800ca36: dd14 ble.n 800ca62 <xQueueReceive+0x2ae>
  28414. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28415. 800ca38: f104 0910 add.w r9, r4, #16
  28416. 800ca3c: e003 b.n 800ca46 <xQueueReceive+0x292>
  28417. --cRxLock;
  28418. 800ca3e: 1e6b subs r3, r5, #1
  28419. 800ca40: b2da uxtb r2, r3
  28420. 800ca42: b25d sxtb r5, r3
  28421. while( cRxLock > queueLOCKED_UNMODIFIED )
  28422. 800ca44: b16a cbz r2, 800ca62 <xQueueReceive+0x2ae>
  28423. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28424. 800ca46: 6923 ldr r3, [r4, #16]
  28425. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28426. 800ca48: 4648 mov r0, r9
  28427. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28428. 800ca4a: b153 cbz r3, 800ca62 <xQueueReceive+0x2ae>
  28429. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28430. 800ca4c: f001 f8b4 bl 800dbb8 <xTaskRemoveFromEventList>
  28431. 800ca50: 2800 cmp r0, #0
  28432. 800ca52: d0f4 beq.n 800ca3e <xQueueReceive+0x28a>
  28433. vTaskMissedYield();
  28434. 800ca54: f001 f960 bl 800dd18 <vTaskMissedYield>
  28435. --cRxLock;
  28436. 800ca58: 1e6b subs r3, r5, #1
  28437. 800ca5a: b2da uxtb r2, r3
  28438. 800ca5c: b25d sxtb r5, r3
  28439. while( cRxLock > queueLOCKED_UNMODIFIED )
  28440. 800ca5e: 2a00 cmp r2, #0
  28441. 800ca60: d1f1 bne.n 800ca46 <xQueueReceive+0x292>
  28442. pxQueue->cRxLock = queueUNLOCKED;
  28443. 800ca62: 23ff movs r3, #255 @ 0xff
  28444. 800ca64: f884 3044 strb.w r3, [r4, #68] @ 0x44
  28445. taskEXIT_CRITICAL();
  28446. 800ca68: f001 ffbe bl 800e9e8 <vPortExitCritical>
  28447. if( xTaskResumeAll() == pdFALSE )
  28448. 800ca6c: f000 ff9a bl 800d9a4 <xTaskResumeAll>
  28449. 800ca70: 2800 cmp r0, #0
  28450. 800ca72: d1a4 bne.n 800c9be <xQueueReceive+0x20a>
  28451. portYIELD_WITHIN_API();
  28452. 800ca74: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  28453. 800ca78: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  28454. 800ca7c: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  28455. 800ca80: f3bf 8f4f dsb sy
  28456. 800ca84: f3bf 8f6f isb sy
  28457. taskENTER_CRITICAL();
  28458. 800ca88: e799 b.n 800c9be <xQueueReceive+0x20a>
  28459. 800ca8a: f04f 0350 mov.w r3, #80 @ 0x50
  28460. 800ca8e: f383 8811 msr BASEPRI, r3
  28461. 800ca92: f3bf 8f6f isb sy
  28462. 800ca96: f3bf 8f4f dsb sy
  28463. configASSERT( ( pxQueue ) );
  28464. 800ca9a: e7fe b.n 800ca9a <xQueueReceive+0x2e6>
  28465. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28466. 800ca9c: f104 0010 add.w r0, r4, #16
  28467. 800caa0: f001 f88a bl 800dbb8 <xTaskRemoveFromEventList>
  28468. 800caa4: 2800 cmp r0, #0
  28469. 800caa6: f43f af24 beq.w 800c8f2 <xQueueReceive+0x13e>
  28470. queueYIELD_IF_USING_PREEMPTION();
  28471. 800caaa: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  28472. 800caae: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  28473. 800cab2: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  28474. 800cab6: f3bf 8f4f dsb sy
  28475. 800caba: f3bf 8f6f isb sy
  28476. 800cabe: e718 b.n 800c8f2 <xQueueReceive+0x13e>
  28477. 0800cac0 <xQueueSemaphoreTake>:
  28478. {
  28479. 800cac0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  28480. 800cac4: b084 sub sp, #16
  28481. 800cac6: 9101 str r1, [sp, #4]
  28482. configASSERT( ( pxQueue ) );
  28483. 800cac8: 2800 cmp r0, #0
  28484. 800caca: d05e beq.n 800cb8a <xQueueSemaphoreTake+0xca>
  28485. configASSERT( pxQueue->uxItemSize == 0 );
  28486. 800cacc: 6c07 ldr r7, [r0, #64] @ 0x40
  28487. 800cace: 4604 mov r4, r0
  28488. 800cad0: b147 cbz r7, 800cae4 <xQueueSemaphoreTake+0x24>
  28489. 800cad2: f04f 0350 mov.w r3, #80 @ 0x50
  28490. 800cad6: f383 8811 msr BASEPRI, r3
  28491. 800cada: f3bf 8f6f isb sy
  28492. 800cade: f3bf 8f4f dsb sy
  28493. 800cae2: e7fe b.n 800cae2 <xQueueSemaphoreTake+0x22>
  28494. configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
  28495. 800cae4: f001 f924 bl 800dd30 <xTaskGetSchedulerState>
  28496. 800cae8: 4605 mov r5, r0
  28497. 800caea: 2800 cmp r0, #0
  28498. 800caec: d056 beq.n 800cb9c <xQueueSemaphoreTake+0xdc>
  28499. 800caee: 463d mov r5, r7
  28500. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28501. 800caf0: f104 0624 add.w r6, r4, #36 @ 0x24
  28502. taskENTER_CRITICAL();
  28503. 800caf4: f001 ff56 bl 800e9a4 <vPortEnterCritical>
  28504. const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
  28505. 800caf8: 6ba3 ldr r3, [r4, #56] @ 0x38
  28506. if( uxSemaphoreCount > ( UBaseType_t ) 0 )
  28507. 800cafa: 2b00 cmp r3, #0
  28508. 800cafc: f040 814d bne.w 800cd9a <xQueueSemaphoreTake+0x2da>
  28509. if( xTicksToWait == ( TickType_t ) 0 )
  28510. 800cb00: 9b01 ldr r3, [sp, #4]
  28511. 800cb02: 2b00 cmp r3, #0
  28512. 800cb04: f000 813e beq.w 800cd84 <xQueueSemaphoreTake+0x2c4>
  28513. else if( xEntryTimeSet == pdFALSE )
  28514. 800cb08: 2d00 cmp r5, #0
  28515. 800cb0a: f000 80a3 beq.w 800cc54 <xQueueSemaphoreTake+0x194>
  28516. taskEXIT_CRITICAL();
  28517. 800cb0e: f001 ff6b bl 800e9e8 <vPortExitCritical>
  28518. vTaskSuspendAll();
  28519. 800cb12: f000 ff3f bl 800d994 <vTaskSuspendAll>
  28520. prvLockQueue( pxQueue );
  28521. 800cb16: f001 ff45 bl 800e9a4 <vPortEnterCritical>
  28522. 800cb1a: f894 3044 ldrb.w r3, [r4, #68] @ 0x44
  28523. 800cb1e: 2bff cmp r3, #255 @ 0xff
  28524. 800cb20: d102 bne.n 800cb28 <xQueueSemaphoreTake+0x68>
  28525. 800cb22: 2300 movs r3, #0
  28526. 800cb24: f884 3044 strb.w r3, [r4, #68] @ 0x44
  28527. 800cb28: f894 3045 ldrb.w r3, [r4, #69] @ 0x45
  28528. 800cb2c: 2bff cmp r3, #255 @ 0xff
  28529. 800cb2e: d102 bne.n 800cb36 <xQueueSemaphoreTake+0x76>
  28530. 800cb30: 2300 movs r3, #0
  28531. 800cb32: f884 3045 strb.w r3, [r4, #69] @ 0x45
  28532. 800cb36: f001 ff57 bl 800e9e8 <vPortExitCritical>
  28533. if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
  28534. 800cb3a: a901 add r1, sp, #4
  28535. 800cb3c: a802 add r0, sp, #8
  28536. 800cb3e: f001 f8a9 bl 800dc94 <xTaskCheckForTimeOut>
  28537. 800cb42: 2800 cmp r0, #0
  28538. 800cb44: d137 bne.n 800cbb6 <xQueueSemaphoreTake+0xf6>
  28539. taskENTER_CRITICAL();
  28540. 800cb46: f001 ff2d bl 800e9a4 <vPortEnterCritical>
  28541. if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
  28542. 800cb4a: 6ba3 ldr r3, [r4, #56] @ 0x38
  28543. 800cb4c: 2b00 cmp r3, #0
  28544. 800cb4e: f000 80ae beq.w 800ccae <xQueueSemaphoreTake+0x1ee>
  28545. taskEXIT_CRITICAL();
  28546. 800cb52: f001 ff49 bl 800e9e8 <vPortExitCritical>
  28547. taskENTER_CRITICAL();
  28548. 800cb56: f001 ff25 bl 800e9a4 <vPortEnterCritical>
  28549. int8_t cTxLock = pxQueue->cTxLock;
  28550. 800cb5a: f894 3045 ldrb.w r3, [r4, #69] @ 0x45
  28551. 800cb5e: b25d sxtb r5, r3
  28552. while( cTxLock > queueLOCKED_UNMODIFIED )
  28553. 800cb60: 2d00 cmp r5, #0
  28554. 800cb62: dd7f ble.n 800cc64 <xQueueSemaphoreTake+0x1a4>
  28555. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28556. 800cb64: f104 0824 add.w r8, r4, #36 @ 0x24
  28557. 800cb68: e004 b.n 800cb74 <xQueueSemaphoreTake+0xb4>
  28558. --cTxLock;
  28559. 800cb6a: 1e6b subs r3, r5, #1
  28560. 800cb6c: b2da uxtb r2, r3
  28561. 800cb6e: b25d sxtb r5, r3
  28562. while( cTxLock > queueLOCKED_UNMODIFIED )
  28563. 800cb70: 2a00 cmp r2, #0
  28564. 800cb72: d077 beq.n 800cc64 <xQueueSemaphoreTake+0x1a4>
  28565. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28566. 800cb74: 6a63 ldr r3, [r4, #36] @ 0x24
  28567. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28568. 800cb76: 4640 mov r0, r8
  28569. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28570. 800cb78: 2b00 cmp r3, #0
  28571. 800cb7a: d073 beq.n 800cc64 <xQueueSemaphoreTake+0x1a4>
  28572. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28573. 800cb7c: f001 f81c bl 800dbb8 <xTaskRemoveFromEventList>
  28574. 800cb80: 2800 cmp r0, #0
  28575. 800cb82: d0f2 beq.n 800cb6a <xQueueSemaphoreTake+0xaa>
  28576. vTaskMissedYield();
  28577. 800cb84: f001 f8c8 bl 800dd18 <vTaskMissedYield>
  28578. 800cb88: e7ef b.n 800cb6a <xQueueSemaphoreTake+0xaa>
  28579. 800cb8a: f04f 0350 mov.w r3, #80 @ 0x50
  28580. 800cb8e: f383 8811 msr BASEPRI, r3
  28581. 800cb92: f3bf 8f6f isb sy
  28582. 800cb96: f3bf 8f4f dsb sy
  28583. configASSERT( ( pxQueue ) );
  28584. 800cb9a: e7fe b.n 800cb9a <xQueueSemaphoreTake+0xda>
  28585. configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
  28586. 800cb9c: 9b01 ldr r3, [sp, #4]
  28587. 800cb9e: 2b00 cmp r3, #0
  28588. 800cba0: f000 80d7 beq.w 800cd52 <xQueueSemaphoreTake+0x292>
  28589. 800cba4: f04f 0350 mov.w r3, #80 @ 0x50
  28590. 800cba8: f383 8811 msr BASEPRI, r3
  28591. 800cbac: f3bf 8f6f isb sy
  28592. 800cbb0: f3bf 8f4f dsb sy
  28593. 800cbb4: e7fe b.n 800cbb4 <xQueueSemaphoreTake+0xf4>
  28594. taskENTER_CRITICAL();
  28595. 800cbb6: f001 fef5 bl 800e9a4 <vPortEnterCritical>
  28596. int8_t cTxLock = pxQueue->cTxLock;
  28597. 800cbba: f894 3045 ldrb.w r3, [r4, #69] @ 0x45
  28598. 800cbbe: b25d sxtb r5, r3
  28599. while( cTxLock > queueLOCKED_UNMODIFIED )
  28600. 800cbc0: 2d00 cmp r5, #0
  28601. 800cbc2: dc04 bgt.n 800cbce <xQueueSemaphoreTake+0x10e>
  28602. 800cbc4: e011 b.n 800cbea <xQueueSemaphoreTake+0x12a>
  28603. --cTxLock;
  28604. 800cbc6: 1e6b subs r3, r5, #1
  28605. 800cbc8: b2da uxtb r2, r3
  28606. 800cbca: b25d sxtb r5, r3
  28607. while( cTxLock > queueLOCKED_UNMODIFIED )
  28608. 800cbcc: b16a cbz r2, 800cbea <xQueueSemaphoreTake+0x12a>
  28609. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28610. 800cbce: 6a63 ldr r3, [r4, #36] @ 0x24
  28611. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28612. 800cbd0: 4630 mov r0, r6
  28613. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28614. 800cbd2: b153 cbz r3, 800cbea <xQueueSemaphoreTake+0x12a>
  28615. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28616. 800cbd4: f000 fff0 bl 800dbb8 <xTaskRemoveFromEventList>
  28617. 800cbd8: 2800 cmp r0, #0
  28618. 800cbda: d0f4 beq.n 800cbc6 <xQueueSemaphoreTake+0x106>
  28619. vTaskMissedYield();
  28620. 800cbdc: f001 f89c bl 800dd18 <vTaskMissedYield>
  28621. --cTxLock;
  28622. 800cbe0: 1e6b subs r3, r5, #1
  28623. 800cbe2: b2da uxtb r2, r3
  28624. 800cbe4: b25d sxtb r5, r3
  28625. while( cTxLock > queueLOCKED_UNMODIFIED )
  28626. 800cbe6: 2a00 cmp r2, #0
  28627. 800cbe8: d1f1 bne.n 800cbce <xQueueSemaphoreTake+0x10e>
  28628. pxQueue->cTxLock = queueUNLOCKED;
  28629. 800cbea: 23ff movs r3, #255 @ 0xff
  28630. 800cbec: f884 3045 strb.w r3, [r4, #69] @ 0x45
  28631. taskEXIT_CRITICAL();
  28632. 800cbf0: f001 fefa bl 800e9e8 <vPortExitCritical>
  28633. taskENTER_CRITICAL();
  28634. 800cbf4: f001 fed6 bl 800e9a4 <vPortEnterCritical>
  28635. int8_t cRxLock = pxQueue->cRxLock;
  28636. 800cbf8: f894 3044 ldrb.w r3, [r4, #68] @ 0x44
  28637. 800cbfc: b25d sxtb r5, r3
  28638. while( cRxLock > queueLOCKED_UNMODIFIED )
  28639. 800cbfe: 2d00 cmp r5, #0
  28640. 800cc00: dd14 ble.n 800cc2c <xQueueSemaphoreTake+0x16c>
  28641. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28642. 800cc02: f104 0810 add.w r8, r4, #16
  28643. 800cc06: e003 b.n 800cc10 <xQueueSemaphoreTake+0x150>
  28644. --cRxLock;
  28645. 800cc08: 1e6b subs r3, r5, #1
  28646. 800cc0a: b2da uxtb r2, r3
  28647. 800cc0c: b25d sxtb r5, r3
  28648. while( cRxLock > queueLOCKED_UNMODIFIED )
  28649. 800cc0e: b16a cbz r2, 800cc2c <xQueueSemaphoreTake+0x16c>
  28650. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28651. 800cc10: 6923 ldr r3, [r4, #16]
  28652. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28653. 800cc12: 4640 mov r0, r8
  28654. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28655. 800cc14: b153 cbz r3, 800cc2c <xQueueSemaphoreTake+0x16c>
  28656. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28657. 800cc16: f000 ffcf bl 800dbb8 <xTaskRemoveFromEventList>
  28658. 800cc1a: 2800 cmp r0, #0
  28659. 800cc1c: d0f4 beq.n 800cc08 <xQueueSemaphoreTake+0x148>
  28660. vTaskMissedYield();
  28661. 800cc1e: f001 f87b bl 800dd18 <vTaskMissedYield>
  28662. --cRxLock;
  28663. 800cc22: 1e6b subs r3, r5, #1
  28664. 800cc24: b2da uxtb r2, r3
  28665. 800cc26: b25d sxtb r5, r3
  28666. while( cRxLock > queueLOCKED_UNMODIFIED )
  28667. 800cc28: 2a00 cmp r2, #0
  28668. 800cc2a: d1f1 bne.n 800cc10 <xQueueSemaphoreTake+0x150>
  28669. pxQueue->cRxLock = queueUNLOCKED;
  28670. 800cc2c: 23ff movs r3, #255 @ 0xff
  28671. 800cc2e: f884 3044 strb.w r3, [r4, #68] @ 0x44
  28672. taskEXIT_CRITICAL();
  28673. 800cc32: f001 fed9 bl 800e9e8 <vPortExitCritical>
  28674. ( void ) xTaskResumeAll();
  28675. 800cc36: f000 feb5 bl 800d9a4 <xTaskResumeAll>
  28676. taskENTER_CRITICAL();
  28677. 800cc3a: f001 feb3 bl 800e9a4 <vPortEnterCritical>
  28678. if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
  28679. 800cc3e: 6ba3 ldr r3, [r4, #56] @ 0x38
  28680. 800cc40: b963 cbnz r3, 800cc5c <xQueueSemaphoreTake+0x19c>
  28681. taskEXIT_CRITICAL();
  28682. 800cc42: f001 fed1 bl 800e9e8 <vPortExitCritical>
  28683. if( xInheritanceOccurred != pdFALSE )
  28684. 800cc46: 2f00 cmp r7, #0
  28685. 800cc48: f040 8085 bne.w 800cd56 <xQueueSemaphoreTake+0x296>
  28686. return errQUEUE_EMPTY;
  28687. 800cc4c: 2000 movs r0, #0
  28688. }
  28689. 800cc4e: b004 add sp, #16
  28690. 800cc50: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  28691. vTaskInternalSetTimeOutState( &xTimeOut );
  28692. 800cc54: a802 add r0, sp, #8
  28693. 800cc56: f001 f811 bl 800dc7c <vTaskInternalSetTimeOutState>
  28694. xEntryTimeSet = pdTRUE;
  28695. 800cc5a: e758 b.n 800cb0e <xQueueSemaphoreTake+0x4e>
  28696. taskEXIT_CRITICAL();
  28697. 800cc5c: f001 fec4 bl 800e9e8 <vPortExitCritical>
  28698. return xReturn;
  28699. 800cc60: 2501 movs r5, #1
  28700. 800cc62: e747 b.n 800caf4 <xQueueSemaphoreTake+0x34>
  28701. pxQueue->cTxLock = queueUNLOCKED;
  28702. 800cc64: 23ff movs r3, #255 @ 0xff
  28703. 800cc66: f884 3045 strb.w r3, [r4, #69] @ 0x45
  28704. taskEXIT_CRITICAL();
  28705. 800cc6a: f001 febd bl 800e9e8 <vPortExitCritical>
  28706. taskENTER_CRITICAL();
  28707. 800cc6e: f001 fe99 bl 800e9a4 <vPortEnterCritical>
  28708. int8_t cRxLock = pxQueue->cRxLock;
  28709. 800cc72: f894 3044 ldrb.w r3, [r4, #68] @ 0x44
  28710. 800cc76: b25d sxtb r5, r3
  28711. while( cRxLock > queueLOCKED_UNMODIFIED )
  28712. 800cc78: 2d00 cmp r5, #0
  28713. 800cc7a: dd10 ble.n 800cc9e <xQueueSemaphoreTake+0x1de>
  28714. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28715. 800cc7c: f104 0810 add.w r8, r4, #16
  28716. 800cc80: e003 b.n 800cc8a <xQueueSemaphoreTake+0x1ca>
  28717. --cRxLock;
  28718. 800cc82: 1e6b subs r3, r5, #1
  28719. 800cc84: b2da uxtb r2, r3
  28720. 800cc86: b25d sxtb r5, r3
  28721. while( cRxLock > queueLOCKED_UNMODIFIED )
  28722. 800cc88: b14a cbz r2, 800cc9e <xQueueSemaphoreTake+0x1de>
  28723. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28724. 800cc8a: 6923 ldr r3, [r4, #16]
  28725. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28726. 800cc8c: 4640 mov r0, r8
  28727. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28728. 800cc8e: b133 cbz r3, 800cc9e <xQueueSemaphoreTake+0x1de>
  28729. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28730. 800cc90: f000 ff92 bl 800dbb8 <xTaskRemoveFromEventList>
  28731. 800cc94: 2800 cmp r0, #0
  28732. 800cc96: d0f4 beq.n 800cc82 <xQueueSemaphoreTake+0x1c2>
  28733. vTaskMissedYield();
  28734. 800cc98: f001 f83e bl 800dd18 <vTaskMissedYield>
  28735. 800cc9c: e7f1 b.n 800cc82 <xQueueSemaphoreTake+0x1c2>
  28736. pxQueue->cRxLock = queueUNLOCKED;
  28737. 800cc9e: 23ff movs r3, #255 @ 0xff
  28738. 800cca0: f884 3044 strb.w r3, [r4, #68] @ 0x44
  28739. taskEXIT_CRITICAL();
  28740. 800cca4: f001 fea0 bl 800e9e8 <vPortExitCritical>
  28741. ( void ) xTaskResumeAll();
  28742. 800cca8: f000 fe7c bl 800d9a4 <xTaskResumeAll>
  28743. 800ccac: e7d8 b.n 800cc60 <xQueueSemaphoreTake+0x1a0>
  28744. taskEXIT_CRITICAL();
  28745. 800ccae: f001 fe9b bl 800e9e8 <vPortExitCritical>
  28746. if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
  28747. 800ccb2: 6823 ldr r3, [r4, #0]
  28748. 800ccb4: 2b00 cmp r3, #0
  28749. 800ccb6: d05c beq.n 800cd72 <xQueueSemaphoreTake+0x2b2>
  28750. vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
  28751. 800ccb8: f104 0824 add.w r8, r4, #36 @ 0x24
  28752. 800ccbc: 9901 ldr r1, [sp, #4]
  28753. 800ccbe: 4640 mov r0, r8
  28754. 800ccc0: f000 feec bl 800da9c <vTaskPlaceOnEventList>
  28755. taskENTER_CRITICAL();
  28756. 800ccc4: f001 fe6e bl 800e9a4 <vPortEnterCritical>
  28757. int8_t cTxLock = pxQueue->cTxLock;
  28758. 800ccc8: f894 3045 ldrb.w r3, [r4, #69] @ 0x45
  28759. 800cccc: b25d sxtb r5, r3
  28760. while( cTxLock > queueLOCKED_UNMODIFIED )
  28761. 800ccce: 2d00 cmp r5, #0
  28762. 800ccd0: dc04 bgt.n 800ccdc <xQueueSemaphoreTake+0x21c>
  28763. 800ccd2: e00d b.n 800ccf0 <xQueueSemaphoreTake+0x230>
  28764. --cTxLock;
  28765. 800ccd4: 1e6b subs r3, r5, #1
  28766. 800ccd6: b2da uxtb r2, r3
  28767. 800ccd8: b25d sxtb r5, r3
  28768. while( cTxLock > queueLOCKED_UNMODIFIED )
  28769. 800ccda: b14a cbz r2, 800ccf0 <xQueueSemaphoreTake+0x230>
  28770. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28771. 800ccdc: 6a63 ldr r3, [r4, #36] @ 0x24
  28772. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28773. 800ccde: 4640 mov r0, r8
  28774. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  28775. 800cce0: b133 cbz r3, 800ccf0 <xQueueSemaphoreTake+0x230>
  28776. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  28777. 800cce2: f000 ff69 bl 800dbb8 <xTaskRemoveFromEventList>
  28778. 800cce6: 2800 cmp r0, #0
  28779. 800cce8: d0f4 beq.n 800ccd4 <xQueueSemaphoreTake+0x214>
  28780. vTaskMissedYield();
  28781. 800ccea: f001 f815 bl 800dd18 <vTaskMissedYield>
  28782. 800ccee: e7f1 b.n 800ccd4 <xQueueSemaphoreTake+0x214>
  28783. pxQueue->cTxLock = queueUNLOCKED;
  28784. 800ccf0: 23ff movs r3, #255 @ 0xff
  28785. 800ccf2: f884 3045 strb.w r3, [r4, #69] @ 0x45
  28786. taskEXIT_CRITICAL();
  28787. 800ccf6: f001 fe77 bl 800e9e8 <vPortExitCritical>
  28788. taskENTER_CRITICAL();
  28789. 800ccfa: f001 fe53 bl 800e9a4 <vPortEnterCritical>
  28790. int8_t cRxLock = pxQueue->cRxLock;
  28791. 800ccfe: f894 3044 ldrb.w r3, [r4, #68] @ 0x44
  28792. 800cd02: b25d sxtb r5, r3
  28793. while( cRxLock > queueLOCKED_UNMODIFIED )
  28794. 800cd04: 2d00 cmp r5, #0
  28795. 800cd06: dd10 ble.n 800cd2a <xQueueSemaphoreTake+0x26a>
  28796. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28797. 800cd08: f104 0810 add.w r8, r4, #16
  28798. 800cd0c: e003 b.n 800cd16 <xQueueSemaphoreTake+0x256>
  28799. --cRxLock;
  28800. 800cd0e: 1e6b subs r3, r5, #1
  28801. 800cd10: b2da uxtb r2, r3
  28802. 800cd12: b25d sxtb r5, r3
  28803. while( cRxLock > queueLOCKED_UNMODIFIED )
  28804. 800cd14: b14a cbz r2, 800cd2a <xQueueSemaphoreTake+0x26a>
  28805. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28806. 800cd16: 6923 ldr r3, [r4, #16]
  28807. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28808. 800cd18: 4640 mov r0, r8
  28809. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28810. 800cd1a: b133 cbz r3, 800cd2a <xQueueSemaphoreTake+0x26a>
  28811. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28812. 800cd1c: f000 ff4c bl 800dbb8 <xTaskRemoveFromEventList>
  28813. 800cd20: 2800 cmp r0, #0
  28814. 800cd22: d0f4 beq.n 800cd0e <xQueueSemaphoreTake+0x24e>
  28815. vTaskMissedYield();
  28816. 800cd24: f000 fff8 bl 800dd18 <vTaskMissedYield>
  28817. 800cd28: e7f1 b.n 800cd0e <xQueueSemaphoreTake+0x24e>
  28818. pxQueue->cRxLock = queueUNLOCKED;
  28819. 800cd2a: 23ff movs r3, #255 @ 0xff
  28820. 800cd2c: f884 3044 strb.w r3, [r4, #68] @ 0x44
  28821. taskEXIT_CRITICAL();
  28822. 800cd30: f001 fe5a bl 800e9e8 <vPortExitCritical>
  28823. if( xTaskResumeAll() == pdFALSE )
  28824. 800cd34: f000 fe36 bl 800d9a4 <xTaskResumeAll>
  28825. 800cd38: 2800 cmp r0, #0
  28826. 800cd3a: d191 bne.n 800cc60 <xQueueSemaphoreTake+0x1a0>
  28827. portYIELD_WITHIN_API();
  28828. 800cd3c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  28829. 800cd40: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  28830. 800cd44: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  28831. 800cd48: f3bf 8f4f dsb sy
  28832. 800cd4c: f3bf 8f6f isb sy
  28833. 800cd50: e786 b.n 800cc60 <xQueueSemaphoreTake+0x1a0>
  28834. 800cd52: 462f mov r7, r5
  28835. 800cd54: e6cc b.n 800caf0 <xQueueSemaphoreTake+0x30>
  28836. taskENTER_CRITICAL();
  28837. 800cd56: f001 fe25 bl 800e9a4 <vPortEnterCritical>
  28838. if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
  28839. 800cd5a: 6a61 ldr r1, [r4, #36] @ 0x24
  28840. 800cd5c: b119 cbz r1, 800cd66 <xQueueSemaphoreTake+0x2a6>
  28841. uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
  28842. 800cd5e: 6b23 ldr r3, [r4, #48] @ 0x30
  28843. 800cd60: 6819 ldr r1, [r3, #0]
  28844. 800cd62: f1c1 0138 rsb r1, r1, #56 @ 0x38
  28845. vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
  28846. 800cd66: 68a0 ldr r0, [r4, #8]
  28847. 800cd68: f001 f876 bl 800de58 <vTaskPriorityDisinheritAfterTimeout>
  28848. taskEXIT_CRITICAL();
  28849. 800cd6c: f001 fe3c bl 800e9e8 <vPortExitCritical>
  28850. 800cd70: e76c b.n 800cc4c <xQueueSemaphoreTake+0x18c>
  28851. taskENTER_CRITICAL();
  28852. 800cd72: f001 fe17 bl 800e9a4 <vPortEnterCritical>
  28853. xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
  28854. 800cd76: 68a0 ldr r0, [r4, #8]
  28855. 800cd78: f000 ffea bl 800dd50 <xTaskPriorityInherit>
  28856. 800cd7c: 4607 mov r7, r0
  28857. taskEXIT_CRITICAL();
  28858. 800cd7e: f001 fe33 bl 800e9e8 <vPortExitCritical>
  28859. 800cd82: e799 b.n 800ccb8 <xQueueSemaphoreTake+0x1f8>
  28860. configASSERT( xInheritanceOccurred == pdFALSE );
  28861. 800cd84: 2f00 cmp r7, #0
  28862. 800cd86: d0f1 beq.n 800cd6c <xQueueSemaphoreTake+0x2ac>
  28863. 800cd88: f04f 0350 mov.w r3, #80 @ 0x50
  28864. 800cd8c: f383 8811 msr BASEPRI, r3
  28865. 800cd90: f3bf 8f6f isb sy
  28866. 800cd94: f3bf 8f4f dsb sy
  28867. 800cd98: e7fe b.n 800cd98 <xQueueSemaphoreTake+0x2d8>
  28868. pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
  28869. 800cd9a: 3b01 subs r3, #1
  28870. if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
  28871. 800cd9c: 6822 ldr r2, [r4, #0]
  28872. pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
  28873. 800cd9e: 63a3 str r3, [r4, #56] @ 0x38
  28874. if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
  28875. 800cda0: b12a cbz r2, 800cdae <xQueueSemaphoreTake+0x2ee>
  28876. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  28877. 800cda2: 6923 ldr r3, [r4, #16]
  28878. 800cda4: b93b cbnz r3, 800cdb6 <xQueueSemaphoreTake+0x2f6>
  28879. taskEXIT_CRITICAL();
  28880. 800cda6: f001 fe1f bl 800e9e8 <vPortExitCritical>
  28881. return pdPASS;
  28882. 800cdaa: 2001 movs r0, #1
  28883. 800cdac: e74f b.n 800cc4e <xQueueSemaphoreTake+0x18e>
  28884. pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
  28885. 800cdae: f001 f8a3 bl 800def8 <pvTaskIncrementMutexHeldCount>
  28886. 800cdb2: 60a0 str r0, [r4, #8]
  28887. 800cdb4: e7f5 b.n 800cda2 <xQueueSemaphoreTake+0x2e2>
  28888. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  28889. 800cdb6: f104 0010 add.w r0, r4, #16
  28890. 800cdba: f000 fefd bl 800dbb8 <xTaskRemoveFromEventList>
  28891. 800cdbe: 2800 cmp r0, #0
  28892. 800cdc0: d0f1 beq.n 800cda6 <xQueueSemaphoreTake+0x2e6>
  28893. queueYIELD_IF_USING_PREEMPTION();
  28894. 800cdc2: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  28895. 800cdc6: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  28896. 800cdca: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  28897. 800cdce: f3bf 8f4f dsb sy
  28898. 800cdd2: f3bf 8f6f isb sy
  28899. 800cdd6: e7e6 b.n 800cda6 <xQueueSemaphoreTake+0x2e6>
  28900. 0800cdd8 <xQueueTakeMutexRecursive>:
  28901. configASSERT( pxMutex );
  28902. 800cdd8: b1a8 cbz r0, 800ce06 <xQueueTakeMutexRecursive+0x2e>
  28903. {
  28904. 800cdda: b570 push {r4, r5, r6, lr}
  28905. if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
  28906. 800cddc: 6886 ldr r6, [r0, #8]
  28907. 800cdde: 4604 mov r4, r0
  28908. 800cde0: 460d mov r5, r1
  28909. 800cde2: f000 ff9f bl 800dd24 <xTaskGetCurrentTaskHandle>
  28910. 800cde6: 4286 cmp r6, r0
  28911. 800cde8: d008 beq.n 800cdfc <xQueueTakeMutexRecursive+0x24>
  28912. xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
  28913. 800cdea: 4629 mov r1, r5
  28914. 800cdec: 4620 mov r0, r4
  28915. 800cdee: f7ff fe67 bl 800cac0 <xQueueSemaphoreTake>
  28916. if( xReturn != pdFAIL )
  28917. 800cdf2: b110 cbz r0, 800cdfa <xQueueTakeMutexRecursive+0x22>
  28918. ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
  28919. 800cdf4: 68e3 ldr r3, [r4, #12]
  28920. 800cdf6: 3301 adds r3, #1
  28921. 800cdf8: 60e3 str r3, [r4, #12]
  28922. }
  28923. 800cdfa: bd70 pop {r4, r5, r6, pc}
  28924. ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
  28925. 800cdfc: 68e3 ldr r3, [r4, #12]
  28926. xReturn = pdPASS;
  28927. 800cdfe: 2001 movs r0, #1
  28928. ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
  28929. 800ce00: 4403 add r3, r0
  28930. 800ce02: 60e3 str r3, [r4, #12]
  28931. }
  28932. 800ce04: bd70 pop {r4, r5, r6, pc}
  28933. 800ce06: f04f 0350 mov.w r3, #80 @ 0x50
  28934. 800ce0a: f383 8811 msr BASEPRI, r3
  28935. 800ce0e: f3bf 8f6f isb sy
  28936. 800ce12: f3bf 8f4f dsb sy
  28937. configASSERT( pxMutex );
  28938. 800ce16: e7fe b.n 800ce16 <xQueueTakeMutexRecursive+0x3e>
  28939. 0800ce18 <xQueueReceiveFromISR>:
  28940. {
  28941. 800ce18: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  28942. configASSERT( pxQueue );
  28943. 800ce1c: b310 cbz r0, 800ce64 <xQueueReceiveFromISR+0x4c>
  28944. configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
  28945. 800ce1e: 460f mov r7, r1
  28946. 800ce20: 4604 mov r4, r0
  28947. 800ce22: 4616 mov r6, r2
  28948. 800ce24: b191 cbz r1, 800ce4c <xQueueReceiveFromISR+0x34>
  28949. portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
  28950. 800ce26: f001 feef bl 800ec08 <vPortValidateInterruptPriority>
  28951. __asm volatile
  28952. 800ce2a: f3ef 8911 mrs r9, BASEPRI
  28953. 800ce2e: f04f 0350 mov.w r3, #80 @ 0x50
  28954. 800ce32: f383 8811 msr BASEPRI, r3
  28955. 800ce36: f3bf 8f6f isb sy
  28956. 800ce3a: f3bf 8f4f dsb sy
  28957. const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
  28958. 800ce3e: 6ba5 ldr r5, [r4, #56] @ 0x38
  28959. if( uxMessagesWaiting > ( UBaseType_t ) 0 )
  28960. 800ce40: b9cd cbnz r5, 800ce76 <xQueueReceiveFromISR+0x5e>
  28961. xReturn = pdFAIL;
  28962. 800ce42: 4628 mov r0, r5
  28963. __asm volatile
  28964. 800ce44: f389 8811 msr BASEPRI, r9
  28965. }
  28966. 800ce48: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  28967. configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
  28968. 800ce4c: 6c03 ldr r3, [r0, #64] @ 0x40
  28969. 800ce4e: 2b00 cmp r3, #0
  28970. 800ce50: d0e9 beq.n 800ce26 <xQueueReceiveFromISR+0xe>
  28971. __asm volatile
  28972. 800ce52: f04f 0350 mov.w r3, #80 @ 0x50
  28973. 800ce56: f383 8811 msr BASEPRI, r3
  28974. 800ce5a: f3bf 8f6f isb sy
  28975. 800ce5e: f3bf 8f4f dsb sy
  28976. 800ce62: e7fe b.n 800ce62 <xQueueReceiveFromISR+0x4a>
  28977. 800ce64: f04f 0350 mov.w r3, #80 @ 0x50
  28978. 800ce68: f383 8811 msr BASEPRI, r3
  28979. 800ce6c: f3bf 8f6f isb sy
  28980. 800ce70: f3bf 8f4f dsb sy
  28981. configASSERT( pxQueue );
  28982. 800ce74: e7fe b.n 800ce74 <xQueueReceiveFromISR+0x5c>
  28983. const int8_t cRxLock = pxQueue->cRxLock;
  28984. 800ce76: f894 8044 ldrb.w r8, [r4, #68] @ 0x44
  28985. if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
  28986. 800ce7a: 6c22 ldr r2, [r4, #64] @ 0x40
  28987. const int8_t cRxLock = pxQueue->cRxLock;
  28988. 800ce7c: fa4f f888 sxtb.w r8, r8
  28989. if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
  28990. 800ce80: b142 cbz r2, 800ce94 <xQueueReceiveFromISR+0x7c>
  28991. pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
  28992. 800ce82: 68e1 ldr r1, [r4, #12]
  28993. if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
  28994. 800ce84: 68a3 ldr r3, [r4, #8]
  28995. pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
  28996. 800ce86: 4411 add r1, r2
  28997. if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
  28998. 800ce88: 4299 cmp r1, r3
  28999. pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
  29000. 800ce8a: 60e1 str r1, [r4, #12]
  29001. if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
  29002. 800ce8c: d21c bcs.n 800cec8 <xQueueReceiveFromISR+0xb0>
  29003. ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
  29004. 800ce8e: 4638 mov r0, r7
  29005. 800ce90: f002 ff0f bl 800fcb2 <memcpy>
  29006. pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
  29007. 800ce94: 3d01 subs r5, #1
  29008. if( cRxLock == queueUNLOCKED )
  29009. 800ce96: f1b8 3fff cmp.w r8, #4294967295 @ 0xffffffff
  29010. pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
  29011. 800ce9a: 63a5 str r5, [r4, #56] @ 0x38
  29012. if( cRxLock == queueUNLOCKED )
  29013. 800ce9c: d006 beq.n 800ceac <xQueueReceiveFromISR+0x94>
  29014. pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
  29015. 800ce9e: f108 0301 add.w r3, r8, #1
  29016. 800cea2: b25b sxtb r3, r3
  29017. 800cea4: f884 3044 strb.w r3, [r4, #68] @ 0x44
  29018. xReturn = pdPASS;
  29019. 800cea8: 2001 movs r0, #1
  29020. 800ceaa: e7cb b.n 800ce44 <xQueueReceiveFromISR+0x2c>
  29021. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  29022. 800ceac: 6923 ldr r3, [r4, #16]
  29023. 800ceae: 2b00 cmp r3, #0
  29024. 800ceb0: d0fa beq.n 800cea8 <xQueueReceiveFromISR+0x90>
  29025. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  29026. 800ceb2: f104 0010 add.w r0, r4, #16
  29027. 800ceb6: f000 fe7f bl 800dbb8 <xTaskRemoveFromEventList>
  29028. if( pxHigherPriorityTaskWoken != NULL )
  29029. 800ceba: 2e00 cmp r6, #0
  29030. 800cebc: d0f4 beq.n 800cea8 <xQueueReceiveFromISR+0x90>
  29031. 800cebe: 2800 cmp r0, #0
  29032. 800cec0: d0f2 beq.n 800cea8 <xQueueReceiveFromISR+0x90>
  29033. *pxHigherPriorityTaskWoken = pdTRUE;
  29034. 800cec2: 2301 movs r3, #1
  29035. 800cec4: 6033 str r3, [r6, #0]
  29036. 800cec6: e7ef b.n 800cea8 <xQueueReceiveFromISR+0x90>
  29037. pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
  29038. 800cec8: 6821 ldr r1, [r4, #0]
  29039. 800ceca: 60e1 str r1, [r4, #12]
  29040. 800cecc: e7df b.n 800ce8e <xQueueReceiveFromISR+0x76>
  29041. 800cece: bf00 nop
  29042. 0800ced0 <vQueueAddToRegistry>:
  29043. /* See if there is an empty space in the registry. A NULL name denotes
  29044. a free slot. */
  29045. for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
  29046. {
  29047. if( xQueueRegistry[ ux ].pcQueueName == NULL )
  29048. 800ced0: 4b12 ldr r3, [pc, #72] @ (800cf1c <vQueueAddToRegistry+0x4c>)
  29049. 800ced2: 681a ldr r2, [r3, #0]
  29050. 800ced4: b17a cbz r2, 800cef6 <vQueueAddToRegistry+0x26>
  29051. 800ced6: 689a ldr r2, [r3, #8]
  29052. 800ced8: b162 cbz r2, 800cef4 <vQueueAddToRegistry+0x24>
  29053. 800ceda: 691a ldr r2, [r3, #16]
  29054. 800cedc: b192 cbz r2, 800cf04 <vQueueAddToRegistry+0x34>
  29055. 800cede: 699a ldr r2, [r3, #24]
  29056. 800cee0: b192 cbz r2, 800cf08 <vQueueAddToRegistry+0x38>
  29057. 800cee2: 6a1a ldr r2, [r3, #32]
  29058. 800cee4: b192 cbz r2, 800cf0c <vQueueAddToRegistry+0x3c>
  29059. 800cee6: 6a9a ldr r2, [r3, #40] @ 0x28
  29060. 800cee8: b192 cbz r2, 800cf10 <vQueueAddToRegistry+0x40>
  29061. 800ceea: 6b1a ldr r2, [r3, #48] @ 0x30
  29062. 800ceec: b192 cbz r2, 800cf14 <vQueueAddToRegistry+0x44>
  29063. 800ceee: 6b9a ldr r2, [r3, #56] @ 0x38
  29064. 800cef0: b192 cbz r2, 800cf18 <vQueueAddToRegistry+0x48>
  29065. else
  29066. {
  29067. mtCOVERAGE_TEST_MARKER();
  29068. }
  29069. }
  29070. }
  29071. 800cef2: 4770 bx lr
  29072. for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
  29073. 800cef4: 2201 movs r2, #1
  29074. xQueueRegistry[ ux ].xHandle = xQueue;
  29075. 800cef6: eb03 0cc2 add.w ip, r3, r2, lsl #3
  29076. xQueueRegistry[ ux ].pcQueueName = pcQueueName;
  29077. 800cefa: f843 1032 str.w r1, [r3, r2, lsl #3]
  29078. xQueueRegistry[ ux ].xHandle = xQueue;
  29079. 800cefe: f8cc 0004 str.w r0, [ip, #4]
  29080. }
  29081. 800cf02: 4770 bx lr
  29082. for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
  29083. 800cf04: 2202 movs r2, #2
  29084. 800cf06: e7f6 b.n 800cef6 <vQueueAddToRegistry+0x26>
  29085. 800cf08: 2203 movs r2, #3
  29086. 800cf0a: e7f4 b.n 800cef6 <vQueueAddToRegistry+0x26>
  29087. 800cf0c: 2204 movs r2, #4
  29088. 800cf0e: e7f2 b.n 800cef6 <vQueueAddToRegistry+0x26>
  29089. 800cf10: 2205 movs r2, #5
  29090. 800cf12: e7f0 b.n 800cef6 <vQueueAddToRegistry+0x26>
  29091. 800cf14: 2206 movs r2, #6
  29092. 800cf16: e7ee b.n 800cef6 <vQueueAddToRegistry+0x26>
  29093. 800cf18: 2207 movs r2, #7
  29094. 800cf1a: e7ec b.n 800cef6 <vQueueAddToRegistry+0x26>
  29095. 800cf1c: 24002b08 .word 0x24002b08
  29096. 0800cf20 <vQueueWaitForMessageRestricted>:
  29097. /*-----------------------------------------------------------*/
  29098. #if ( configUSE_TIMERS == 1 )
  29099. void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
  29100. {
  29101. 800cf20: b570 push {r4, r5, r6, lr}
  29102. 800cf22: 4605 mov r5, r0
  29103. 800cf24: 460e mov r6, r1
  29104. 800cf26: 4614 mov r4, r2
  29105. will not actually cause the task to block, just place it on a blocked
  29106. list. It will not block until the scheduler is unlocked - at which
  29107. time a yield will be performed. If an item is added to the queue while
  29108. the queue is locked, and the calling task blocks on the queue, then the
  29109. calling task will be immediately unblocked when the queue is unlocked. */
  29110. prvLockQueue( pxQueue );
  29111. 800cf28: f001 fd3c bl 800e9a4 <vPortEnterCritical>
  29112. 800cf2c: f895 3044 ldrb.w r3, [r5, #68] @ 0x44
  29113. 800cf30: 2bff cmp r3, #255 @ 0xff
  29114. 800cf32: d102 bne.n 800cf3a <vQueueWaitForMessageRestricted+0x1a>
  29115. 800cf34: 2300 movs r3, #0
  29116. 800cf36: f885 3044 strb.w r3, [r5, #68] @ 0x44
  29117. 800cf3a: f895 3045 ldrb.w r3, [r5, #69] @ 0x45
  29118. 800cf3e: 2bff cmp r3, #255 @ 0xff
  29119. 800cf40: d102 bne.n 800cf48 <vQueueWaitForMessageRestricted+0x28>
  29120. 800cf42: 2300 movs r3, #0
  29121. 800cf44: f885 3045 strb.w r3, [r5, #69] @ 0x45
  29122. 800cf48: f001 fd4e bl 800e9e8 <vPortExitCritical>
  29123. if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
  29124. 800cf4c: 6bab ldr r3, [r5, #56] @ 0x38
  29125. 800cf4e: 2b00 cmp r3, #0
  29126. 800cf50: d043 beq.n 800cfda <vQueueWaitForMessageRestricted+0xba>
  29127. taskENTER_CRITICAL();
  29128. 800cf52: f001 fd27 bl 800e9a4 <vPortEnterCritical>
  29129. int8_t cTxLock = pxQueue->cTxLock;
  29130. 800cf56: f895 3045 ldrb.w r3, [r5, #69] @ 0x45
  29131. 800cf5a: b25c sxtb r4, r3
  29132. while( cTxLock > queueLOCKED_UNMODIFIED )
  29133. 800cf5c: 2c00 cmp r4, #0
  29134. 800cf5e: dd14 ble.n 800cf8a <vQueueWaitForMessageRestricted+0x6a>
  29135. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  29136. 800cf60: f105 0624 add.w r6, r5, #36 @ 0x24
  29137. 800cf64: e003 b.n 800cf6e <vQueueWaitForMessageRestricted+0x4e>
  29138. --cTxLock;
  29139. 800cf66: 1e63 subs r3, r4, #1
  29140. 800cf68: b2da uxtb r2, r3
  29141. 800cf6a: b25c sxtb r4, r3
  29142. while( cTxLock > queueLOCKED_UNMODIFIED )
  29143. 800cf6c: b16a cbz r2, 800cf8a <vQueueWaitForMessageRestricted+0x6a>
  29144. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  29145. 800cf6e: 6a6b ldr r3, [r5, #36] @ 0x24
  29146. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  29147. 800cf70: 4630 mov r0, r6
  29148. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
  29149. 800cf72: b153 cbz r3, 800cf8a <vQueueWaitForMessageRestricted+0x6a>
  29150. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
  29151. 800cf74: f000 fe20 bl 800dbb8 <xTaskRemoveFromEventList>
  29152. 800cf78: 2800 cmp r0, #0
  29153. 800cf7a: d0f4 beq.n 800cf66 <vQueueWaitForMessageRestricted+0x46>
  29154. vTaskMissedYield();
  29155. 800cf7c: f000 fecc bl 800dd18 <vTaskMissedYield>
  29156. --cTxLock;
  29157. 800cf80: 1e63 subs r3, r4, #1
  29158. 800cf82: b2da uxtb r2, r3
  29159. 800cf84: b25c sxtb r4, r3
  29160. while( cTxLock > queueLOCKED_UNMODIFIED )
  29161. 800cf86: 2a00 cmp r2, #0
  29162. 800cf88: d1f1 bne.n 800cf6e <vQueueWaitForMessageRestricted+0x4e>
  29163. pxQueue->cTxLock = queueUNLOCKED;
  29164. 800cf8a: 23ff movs r3, #255 @ 0xff
  29165. 800cf8c: f885 3045 strb.w r3, [r5, #69] @ 0x45
  29166. taskEXIT_CRITICAL();
  29167. 800cf90: f001 fd2a bl 800e9e8 <vPortExitCritical>
  29168. taskENTER_CRITICAL();
  29169. 800cf94: f001 fd06 bl 800e9a4 <vPortEnterCritical>
  29170. int8_t cRxLock = pxQueue->cRxLock;
  29171. 800cf98: f895 3044 ldrb.w r3, [r5, #68] @ 0x44
  29172. 800cf9c: b25c sxtb r4, r3
  29173. while( cRxLock > queueLOCKED_UNMODIFIED )
  29174. 800cf9e: 2c00 cmp r4, #0
  29175. 800cfa0: dd14 ble.n 800cfcc <vQueueWaitForMessageRestricted+0xac>
  29176. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  29177. 800cfa2: f105 0610 add.w r6, r5, #16
  29178. 800cfa6: e003 b.n 800cfb0 <vQueueWaitForMessageRestricted+0x90>
  29179. --cRxLock;
  29180. 800cfa8: 1e63 subs r3, r4, #1
  29181. 800cfaa: b2da uxtb r2, r3
  29182. 800cfac: b25c sxtb r4, r3
  29183. while( cRxLock > queueLOCKED_UNMODIFIED )
  29184. 800cfae: b16a cbz r2, 800cfcc <vQueueWaitForMessageRestricted+0xac>
  29185. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  29186. 800cfb0: 692b ldr r3, [r5, #16]
  29187. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  29188. 800cfb2: 4630 mov r0, r6
  29189. if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
  29190. 800cfb4: b153 cbz r3, 800cfcc <vQueueWaitForMessageRestricted+0xac>
  29191. if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
  29192. 800cfb6: f000 fdff bl 800dbb8 <xTaskRemoveFromEventList>
  29193. 800cfba: 2800 cmp r0, #0
  29194. 800cfbc: d0f4 beq.n 800cfa8 <vQueueWaitForMessageRestricted+0x88>
  29195. vTaskMissedYield();
  29196. 800cfbe: f000 feab bl 800dd18 <vTaskMissedYield>
  29197. --cRxLock;
  29198. 800cfc2: 1e63 subs r3, r4, #1
  29199. 800cfc4: b2da uxtb r2, r3
  29200. 800cfc6: b25c sxtb r4, r3
  29201. while( cRxLock > queueLOCKED_UNMODIFIED )
  29202. 800cfc8: 2a00 cmp r2, #0
  29203. 800cfca: d1f1 bne.n 800cfb0 <vQueueWaitForMessageRestricted+0x90>
  29204. pxQueue->cRxLock = queueUNLOCKED;
  29205. 800cfcc: 23ff movs r3, #255 @ 0xff
  29206. 800cfce: f885 3044 strb.w r3, [r5, #68] @ 0x44
  29207. else
  29208. {
  29209. mtCOVERAGE_TEST_MARKER();
  29210. }
  29211. prvUnlockQueue( pxQueue );
  29212. }
  29213. 800cfd2: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  29214. taskEXIT_CRITICAL();
  29215. 800cfd6: f001 bd07 b.w 800e9e8 <vPortExitCritical>
  29216. vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
  29217. 800cfda: 4622 mov r2, r4
  29218. 800cfdc: 4631 mov r1, r6
  29219. 800cfde: f105 0024 add.w r0, r5, #36 @ 0x24
  29220. 800cfe2: f000 fd9f bl 800db24 <vTaskPlaceOnEventListRestricted>
  29221. 800cfe6: e7b4 b.n 800cf52 <vQueueWaitForMessageRestricted+0x32>
  29222. 0800cfe8 <prvWriteBytesToBuffer.part.0>:
  29223. return xReturn;
  29224. }
  29225. /*-----------------------------------------------------------*/
  29226. static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
  29227. 800cfe8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  29228. xNextHead = pxStreamBuffer->xHead;
  29229. /* Calculate the number of bytes that can be added in the first write -
  29230. which may be less than the total number of bytes that need to be added if
  29231. the buffer will wrap back to the beginning. */
  29232. xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
  29233. 800cfec: 6883 ldr r3, [r0, #8]
  29234. static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
  29235. 800cfee: 4615 mov r5, r2
  29236. xNextHead = pxStreamBuffer->xHead;
  29237. 800cff0: 6847 ldr r7, [r0, #4]
  29238. xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
  29239. 800cff2: 1bde subs r6, r3, r7
  29240. 800cff4: 4296 cmp r6, r2
  29241. 800cff6: bf28 it cs
  29242. 800cff8: 4616 movcs r6, r2
  29243. /* Write as many bytes as can be written in the first write. */
  29244. configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
  29245. 800cffa: 19ba adds r2, r7, r6
  29246. 800cffc: 4293 cmp r3, r2
  29247. 800cffe: d208 bcs.n 800d012 <prvWriteBytesToBuffer.part.0+0x2a>
  29248. 800d000: f04f 0350 mov.w r3, #80 @ 0x50
  29249. 800d004: f383 8811 msr BASEPRI, r3
  29250. 800d008: f3bf 8f6f isb sy
  29251. 800d00c: f3bf 8f4f dsb sy
  29252. 800d010: e7fe b.n 800d010 <prvWriteBytesToBuffer.part.0+0x28>
  29253. ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
  29254. 800d012: 4604 mov r4, r0
  29255. 800d014: 6980 ldr r0, [r0, #24]
  29256. 800d016: 4632 mov r2, r6
  29257. 800d018: 4688 mov r8, r1
  29258. 800d01a: 4438 add r0, r7
  29259. 800d01c: f002 fe49 bl 800fcb2 <memcpy>
  29260. /* If the number of bytes written was less than the number that could be
  29261. written in the first write... */
  29262. if( xCount > xFirstLength )
  29263. 800d020: 42b5 cmp r5, r6
  29264. 800d022: d911 bls.n 800d048 <prvWriteBytesToBuffer.part.0+0x60>
  29265. {
  29266. /* ...then write the remaining bytes to the start of the buffer. */
  29267. configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
  29268. 800d024: 1baa subs r2, r5, r6
  29269. 800d026: 68a3 ldr r3, [r4, #8]
  29270. 800d028: 429a cmp r2, r3
  29271. 800d02a: d908 bls.n 800d03e <prvWriteBytesToBuffer.part.0+0x56>
  29272. 800d02c: f04f 0350 mov.w r3, #80 @ 0x50
  29273. 800d030: f383 8811 msr BASEPRI, r3
  29274. 800d034: f3bf 8f6f isb sy
  29275. 800d038: f3bf 8f4f dsb sy
  29276. 800d03c: e7fe b.n 800d03c <prvWriteBytesToBuffer.part.0+0x54>
  29277. ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
  29278. 800d03e: eb08 0106 add.w r1, r8, r6
  29279. 800d042: 69a0 ldr r0, [r4, #24]
  29280. 800d044: f002 fe35 bl 800fcb2 <memcpy>
  29281. else
  29282. {
  29283. mtCOVERAGE_TEST_MARKER();
  29284. }
  29285. xNextHead += xCount;
  29286. 800d048: 442f add r7, r5
  29287. if( xNextHead >= pxStreamBuffer->xLength )
  29288. 800d04a: 68a3 ldr r3, [r4, #8]
  29289. }
  29290. pxStreamBuffer->xHead = xNextHead;
  29291. return xCount;
  29292. }
  29293. 800d04c: 4628 mov r0, r5
  29294. if( xNextHead >= pxStreamBuffer->xLength )
  29295. 800d04e: 429f cmp r7, r3
  29296. xNextHead -= pxStreamBuffer->xLength;
  29297. 800d050: bf28 it cs
  29298. 800d052: 1aff subcs r7, r7, r3
  29299. pxStreamBuffer->xHead = xNextHead;
  29300. 800d054: 6067 str r7, [r4, #4]
  29301. }
  29302. 800d056: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  29303. 800d05a: bf00 nop
  29304. 0800d05c <xStreamBufferSend>:
  29305. {
  29306. 800d05c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
  29307. 800d060: b087 sub sp, #28
  29308. 800d062: 9301 str r3, [sp, #4]
  29309. configASSERT( pvTxData );
  29310. 800d064: 2900 cmp r1, #0
  29311. 800d066: d062 beq.n 800d12e <xStreamBufferSend+0xd2>
  29312. configASSERT( pxStreamBuffer );
  29313. 800d068: 4604 mov r4, r0
  29314. 800d06a: b188 cbz r0, 800d090 <xStreamBufferSend+0x34>
  29315. if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
  29316. 800d06c: 7f03 ldrb r3, [r0, #28]
  29317. 800d06e: 4617 mov r7, r2
  29318. 800d070: 460e mov r6, r1
  29319. 800d072: 07da lsls r2, r3, #31
  29320. 800d074: d515 bpl.n 800d0a2 <xStreamBufferSend+0x46>
  29321. xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
  29322. 800d076: f107 0804 add.w r8, r7, #4
  29323. configASSERT( xRequiredSpace > xDataLengthBytes );
  29324. 800d07a: 4547 cmp r7, r8
  29325. 800d07c: d312 bcc.n 800d0a4 <xStreamBufferSend+0x48>
  29326. 800d07e: f04f 0350 mov.w r3, #80 @ 0x50
  29327. 800d082: f383 8811 msr BASEPRI, r3
  29328. 800d086: f3bf 8f6f isb sy
  29329. 800d08a: f3bf 8f4f dsb sy
  29330. 800d08e: e7fe b.n 800d08e <xStreamBufferSend+0x32>
  29331. 800d090: f04f 0350 mov.w r3, #80 @ 0x50
  29332. 800d094: f383 8811 msr BASEPRI, r3
  29333. 800d098: f3bf 8f6f isb sy
  29334. 800d09c: f3bf 8f4f dsb sy
  29335. configASSERT( pxStreamBuffer );
  29336. 800d0a0: e7fe b.n 800d0a0 <xStreamBufferSend+0x44>
  29337. 800d0a2: 46b8 mov r8, r7
  29338. if( xTicksToWait != ( TickType_t ) 0 )
  29339. 800d0a4: 9b01 ldr r3, [sp, #4]
  29340. 800d0a6: 2b00 cmp r3, #0
  29341. 800d0a8: d04a beq.n 800d140 <xStreamBufferSend+0xe4>
  29342. vTaskSetTimeOutState( &xTimeOut );
  29343. 800d0aa: a804 add r0, sp, #16
  29344. 800d0ac: f000 fdca bl 800dc44 <vTaskSetTimeOutState>
  29345. taskENTER_CRITICAL();
  29346. 800d0b0: f001 fc78 bl 800e9a4 <vPortEnterCritical>
  29347. xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
  29348. 800d0b4: 68a3 ldr r3, [r4, #8]
  29349. 800d0b6: 6825 ldr r5, [r4, #0]
  29350. ( void ) xTaskNotifyStateClear( NULL );
  29351. 800d0b8: 2000 movs r0, #0
  29352. xSpace -= pxStreamBuffer->xHead;
  29353. 800d0ba: 6862 ldr r2, [r4, #4]
  29354. xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
  29355. 800d0bc: 441d add r5, r3
  29356. 800d0be: 3d01 subs r5, #1
  29357. xSpace -= ( size_t ) 1;
  29358. 800d0c0: 1aad subs r5, r5, r2
  29359. if( xSpace >= pxStreamBuffer->xLength )
  29360. 800d0c2: 42ab cmp r3, r5
  29361. xSpace -= pxStreamBuffer->xLength;
  29362. 800d0c4: bf98 it ls
  29363. 800d0c6: 1aed subls r5, r5, r3
  29364. if( xSpace < xRequiredSpace )
  29365. 800d0c8: 45a8 cmp r8, r5
  29366. 800d0ca: d97a bls.n 800d1c2 <xStreamBufferSend+0x166>
  29367. ( void ) xTaskNotifyStateClear( NULL );
  29368. 800d0cc: f001 f8a8 bl 800e220 <xTaskNotifyStateClear>
  29369. configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
  29370. 800d0d0: f8d4 9014 ldr.w r9, [r4, #20]
  29371. 800d0d4: f1b9 0f00 cmp.w r9, #0
  29372. 800d0d8: d16a bne.n 800d1b0 <xStreamBufferSend+0x154>
  29373. pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
  29374. 800d0da: f000 fe23 bl 800dd24 <xTaskGetCurrentTaskHandle>
  29375. 800d0de: 6160 str r0, [r4, #20]
  29376. taskEXIT_CRITICAL();
  29377. 800d0e0: f001 fc82 bl 800e9e8 <vPortExitCritical>
  29378. ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
  29379. 800d0e4: 4649 mov r1, r9
  29380. 800d0e6: 9b01 ldr r3, [sp, #4]
  29381. 800d0e8: 464a mov r2, r9
  29382. 800d0ea: 4648 mov r0, r9
  29383. 800d0ec: f000 ff10 bl 800df10 <xTaskNotifyWait>
  29384. } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
  29385. 800d0f0: a901 add r1, sp, #4
  29386. 800d0f2: a804 add r0, sp, #16
  29387. pxStreamBuffer->xTaskWaitingToSend = NULL;
  29388. 800d0f4: f8c4 9014 str.w r9, [r4, #20]
  29389. } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
  29390. 800d0f8: f000 fdcc bl 800dc94 <xTaskCheckForTimeOut>
  29391. 800d0fc: 2800 cmp r0, #0
  29392. 800d0fe: d0d7 beq.n 800d0b0 <xStreamBufferSend+0x54>
  29393. if( xSpace == ( size_t ) 0 )
  29394. 800d100: b1f5 cbz r5, 800d140 <xStreamBufferSend+0xe4>
  29395. xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
  29396. 800d102: 9703 str r7, [sp, #12]
  29397. else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
  29398. 800d104: 7f23 ldrb r3, [r4, #28]
  29399. 800d106: 07db lsls r3, r3, #31
  29400. 800d108: d52b bpl.n 800d162 <xStreamBufferSend+0x106>
  29401. else if( xSpace >= xRequiredSpace )
  29402. 800d10a: 4545 cmp r5, r8
  29403. 800d10c: d324 bcc.n 800d158 <xStreamBufferSend+0xfc>
  29404. configASSERT( xCount > ( size_t ) 0 );
  29405. 800d10e: 2204 movs r2, #4
  29406. 800d110: a903 add r1, sp, #12
  29407. 800d112: 4620 mov r0, r4
  29408. 800d114: f7ff ff68 bl 800cfe8 <prvWriteBytesToBuffer.part.0>
  29409. xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
  29410. 800d118: 9a03 ldr r2, [sp, #12]
  29411. configASSERT( xCount > ( size_t ) 0 );
  29412. 800d11a: bb42 cbnz r2, 800d16e <xStreamBufferSend+0x112>
  29413. 800d11c: f04f 0350 mov.w r3, #80 @ 0x50
  29414. 800d120: f383 8811 msr BASEPRI, r3
  29415. 800d124: f3bf 8f6f isb sy
  29416. 800d128: f3bf 8f4f dsb sy
  29417. 800d12c: e7fe b.n 800d12c <xStreamBufferSend+0xd0>
  29418. 800d12e: f04f 0350 mov.w r3, #80 @ 0x50
  29419. 800d132: f383 8811 msr BASEPRI, r3
  29420. 800d136: f3bf 8f6f isb sy
  29421. 800d13a: f3bf 8f4f dsb sy
  29422. configASSERT( pvTxData );
  29423. 800d13e: e7fe b.n 800d13e <xStreamBufferSend+0xe2>
  29424. xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
  29425. 800d140: 68a3 ldr r3, [r4, #8]
  29426. 800d142: 6825 ldr r5, [r4, #0]
  29427. xSpace -= pxStreamBuffer->xHead;
  29428. 800d144: 6862 ldr r2, [r4, #4]
  29429. xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
  29430. 800d146: 441d add r5, r3
  29431. 800d148: 9703 str r7, [sp, #12]
  29432. 800d14a: 3d01 subs r5, #1
  29433. xSpace -= ( size_t ) 1;
  29434. 800d14c: 1aad subs r5, r5, r2
  29435. if( xSpace >= pxStreamBuffer->xLength )
  29436. 800d14e: 42ab cmp r3, r5
  29437. xSpace -= pxStreamBuffer->xLength;
  29438. 800d150: bf98 it ls
  29439. 800d152: 1aed subls r5, r5, r3
  29440. if( xSpace == ( size_t ) 0 )
  29441. 800d154: 2d00 cmp r5, #0
  29442. 800d156: d1d5 bne.n 800d104 <xStreamBufferSend+0xa8>
  29443. 800d158: 2500 movs r5, #0
  29444. }
  29445. 800d15a: 4628 mov r0, r5
  29446. 800d15c: b007 add sp, #28
  29447. 800d15e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
  29448. xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
  29449. 800d162: 42bd cmp r5, r7
  29450. 800d164: 462a mov r2, r5
  29451. 800d166: bf28 it cs
  29452. 800d168: 463a movcs r2, r7
  29453. 800d16a: 9203 str r2, [sp, #12]
  29454. if( xShouldWrite != pdFALSE )
  29455. 800d16c: e7d5 b.n 800d11a <xStreamBufferSend+0xbe>
  29456. 800d16e: 4631 mov r1, r6
  29457. 800d170: 4620 mov r0, r4
  29458. 800d172: f7ff ff39 bl 800cfe8 <prvWriteBytesToBuffer.part.0>
  29459. if( xReturn > ( size_t ) 0 )
  29460. 800d176: 4605 mov r5, r0
  29461. 800d178: 2800 cmp r0, #0
  29462. 800d17a: d0ed beq.n 800d158 <xStreamBufferSend+0xfc>
  29463. static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
  29464. {
  29465. /* Returns the distance between xTail and xHead. */
  29466. size_t xCount;
  29467. xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
  29468. 800d17c: 68a2 ldr r2, [r4, #8]
  29469. 800d17e: 6863 ldr r3, [r4, #4]
  29470. xCount -= pxStreamBuffer->xTail;
  29471. 800d180: 6821 ldr r1, [r4, #0]
  29472. xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
  29473. 800d182: 4413 add r3, r2
  29474. xCount -= pxStreamBuffer->xTail;
  29475. 800d184: 1a5b subs r3, r3, r1
  29476. if ( xCount >= pxStreamBuffer->xLength )
  29477. 800d186: 429a cmp r2, r3
  29478. {
  29479. xCount -= pxStreamBuffer->xLength;
  29480. 800d188: bf98 it ls
  29481. 800d18a: 1a9b subls r3, r3, r2
  29482. if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
  29483. 800d18c: 68e2 ldr r2, [r4, #12]
  29484. 800d18e: 429a cmp r2, r3
  29485. 800d190: d8e3 bhi.n 800d15a <xStreamBufferSend+0xfe>
  29486. sbSEND_COMPLETED( pxStreamBuffer );
  29487. 800d192: f000 fbff bl 800d994 <vTaskSuspendAll>
  29488. 800d196: 6923 ldr r3, [r4, #16]
  29489. 800d198: b13b cbz r3, 800d1aa <xStreamBufferSend+0x14e>
  29490. 800d19a: 2300 movs r3, #0
  29491. 800d19c: 6920 ldr r0, [r4, #16]
  29492. 800d19e: 461a mov r2, r3
  29493. 800d1a0: 4619 mov r1, r3
  29494. 800d1a2: f000 ff2b bl 800dffc <xTaskGenericNotify>
  29495. 800d1a6: 2300 movs r3, #0
  29496. 800d1a8: 6123 str r3, [r4, #16]
  29497. 800d1aa: f000 fbfb bl 800d9a4 <xTaskResumeAll>
  29498. return xReturn;
  29499. 800d1ae: e7d4 b.n 800d15a <xStreamBufferSend+0xfe>
  29500. 800d1b0: f04f 0350 mov.w r3, #80 @ 0x50
  29501. 800d1b4: f383 8811 msr BASEPRI, r3
  29502. 800d1b8: f3bf 8f6f isb sy
  29503. 800d1bc: f3bf 8f4f dsb sy
  29504. configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
  29505. 800d1c0: e7fe b.n 800d1c0 <xStreamBufferSend+0x164>
  29506. taskEXIT_CRITICAL();
  29507. 800d1c2: f001 fc11 bl 800e9e8 <vPortExitCritical>
  29508. break;
  29509. 800d1c6: e79b b.n 800d100 <xStreamBufferSend+0xa4>
  29510. 0800d1c8 <prvAddNewTaskToReadyList>:
  29511. }
  29512. }
  29513. /*-----------------------------------------------------------*/
  29514. static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
  29515. {
  29516. 800d1c8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  29517. 800d1cc: 4605 mov r5, r0
  29518. /* Ensure interrupts don't access the task lists while the lists are being
  29519. updated. */
  29520. taskENTER_CRITICAL();
  29521. 800d1ce: f001 fbe9 bl 800e9a4 <vPortEnterCritical>
  29522. {
  29523. uxCurrentNumberOfTasks++;
  29524. 800d1d2: 4a34 ldr r2, [pc, #208] @ (800d2a4 <prvAddNewTaskToReadyList+0xdc>)
  29525. if( pxCurrentTCB == NULL )
  29526. 800d1d4: 4e34 ldr r6, [pc, #208] @ (800d2a8 <prvAddNewTaskToReadyList+0xe0>)
  29527. uxCurrentNumberOfTasks++;
  29528. 800d1d6: 6813 ldr r3, [r2, #0]
  29529. 800d1d8: 3301 adds r3, #1
  29530. 800d1da: 6013 str r3, [r2, #0]
  29531. if( pxCurrentTCB == NULL )
  29532. 800d1dc: 6833 ldr r3, [r6, #0]
  29533. 800d1de: 2b00 cmp r3, #0
  29534. 800d1e0: d031 beq.n 800d246 <prvAddNewTaskToReadyList+0x7e>
  29535. else
  29536. {
  29537. /* If the scheduler is not already running, make this task the
  29538. current task if it is the highest priority task to be created
  29539. so far. */
  29540. if( xSchedulerRunning == pdFALSE )
  29541. 800d1e2: 4c32 ldr r4, [pc, #200] @ (800d2ac <prvAddNewTaskToReadyList+0xe4>)
  29542. {
  29543. if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
  29544. 800d1e4: 6ae8 ldr r0, [r5, #44] @ 0x2c
  29545. if( xSchedulerRunning == pdFALSE )
  29546. 800d1e6: 6823 ldr r3, [r4, #0]
  29547. 800d1e8: b333 cbz r3, 800d238 <prvAddNewTaskToReadyList+0x70>
  29548. 800d1ea: 4f31 ldr r7, [pc, #196] @ (800d2b0 <prvAddNewTaskToReadyList+0xe8>)
  29549. {
  29550. mtCOVERAGE_TEST_MARKER();
  29551. }
  29552. }
  29553. uxTaskNumber++;
  29554. 800d1ec: 4a31 ldr r2, [pc, #196] @ (800d2b4 <prvAddNewTaskToReadyList+0xec>)
  29555. pxNewTCB->uxTCBNumber = uxTaskNumber;
  29556. }
  29557. #endif /* configUSE_TRACE_FACILITY */
  29558. traceTASK_CREATE( pxNewTCB );
  29559. prvAddTaskToReadyList( pxNewTCB );
  29560. 800d1ee: 4932 ldr r1, [pc, #200] @ (800d2b8 <prvAddNewTaskToReadyList+0xf0>)
  29561. uxTaskNumber++;
  29562. 800d1f0: 6813 ldr r3, [r2, #0]
  29563. 800d1f2: 3301 adds r3, #1
  29564. 800d1f4: 6013 str r3, [r2, #0]
  29565. pxNewTCB->uxTCBNumber = uxTaskNumber;
  29566. 800d1f6: 646b str r3, [r5, #68] @ 0x44
  29567. prvAddTaskToReadyList( pxNewTCB );
  29568. 800d1f8: 680b ldr r3, [r1, #0]
  29569. 800d1fa: 4283 cmp r3, r0
  29570. 800d1fc: d200 bcs.n 800d200 <prvAddNewTaskToReadyList+0x38>
  29571. 800d1fe: 6008 str r0, [r1, #0]
  29572. 800d200: eb00 0080 add.w r0, r0, r0, lsl #2
  29573. 800d204: 1d29 adds r1, r5, #4
  29574. 800d206: eb07 0080 add.w r0, r7, r0, lsl #2
  29575. 800d20a: f7fe ff23 bl 800c054 <vListInsertEnd>
  29576. portSETUP_TCB( pxNewTCB );
  29577. }
  29578. taskEXIT_CRITICAL();
  29579. 800d20e: f001 fbeb bl 800e9e8 <vPortExitCritical>
  29580. if( xSchedulerRunning != pdFALSE )
  29581. 800d212: 6823 ldr r3, [r4, #0]
  29582. 800d214: b173 cbz r3, 800d234 <prvAddNewTaskToReadyList+0x6c>
  29583. {
  29584. /* If the created task is of a higher priority than the current task
  29585. then it should run now. */
  29586. if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
  29587. 800d216: 6832 ldr r2, [r6, #0]
  29588. 800d218: 6aeb ldr r3, [r5, #44] @ 0x2c
  29589. 800d21a: 6ad2 ldr r2, [r2, #44] @ 0x2c
  29590. 800d21c: 429a cmp r2, r3
  29591. 800d21e: d209 bcs.n 800d234 <prvAddNewTaskToReadyList+0x6c>
  29592. {
  29593. taskYIELD_IF_USING_PREEMPTION();
  29594. 800d220: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  29595. 800d224: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  29596. 800d228: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  29597. 800d22c: f3bf 8f4f dsb sy
  29598. 800d230: f3bf 8f6f isb sy
  29599. }
  29600. else
  29601. {
  29602. mtCOVERAGE_TEST_MARKER();
  29603. }
  29604. }
  29605. 800d234: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  29606. if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
  29607. 800d238: 6833 ldr r3, [r6, #0]
  29608. 800d23a: 4f1d ldr r7, [pc, #116] @ (800d2b0 <prvAddNewTaskToReadyList+0xe8>)
  29609. 800d23c: 6adb ldr r3, [r3, #44] @ 0x2c
  29610. 800d23e: 4283 cmp r3, r0
  29611. 800d240: d8d4 bhi.n 800d1ec <prvAddNewTaskToReadyList+0x24>
  29612. pxCurrentTCB = pxNewTCB;
  29613. 800d242: 6035 str r5, [r6, #0]
  29614. 800d244: e7d2 b.n 800d1ec <prvAddNewTaskToReadyList+0x24>
  29615. pxCurrentTCB = pxNewTCB;
  29616. 800d246: 6035 str r5, [r6, #0]
  29617. if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
  29618. 800d248: 6813 ldr r3, [r2, #0]
  29619. 800d24a: 2b01 cmp r3, #1
  29620. 800d24c: d003 beq.n 800d256 <prvAddNewTaskToReadyList+0x8e>
  29621. if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
  29622. 800d24e: 6ae8 ldr r0, [r5, #44] @ 0x2c
  29623. 800d250: 4f17 ldr r7, [pc, #92] @ (800d2b0 <prvAddNewTaskToReadyList+0xe8>)
  29624. 800d252: 4c16 ldr r4, [pc, #88] @ (800d2ac <prvAddNewTaskToReadyList+0xe4>)
  29625. 800d254: e7ca b.n 800d1ec <prvAddNewTaskToReadyList+0x24>
  29626. 800d256: 4f16 ldr r7, [pc, #88] @ (800d2b0 <prvAddNewTaskToReadyList+0xe8>)
  29627. 800d258: 463c mov r4, r7
  29628. 800d25a: f507 688c add.w r8, r7, #1120 @ 0x460
  29629. {
  29630. UBaseType_t uxPriority;
  29631. for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
  29632. {
  29633. vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
  29634. 800d25e: 4620 mov r0, r4
  29635. for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
  29636. 800d260: 3414 adds r4, #20
  29637. vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
  29638. 800d262: f7fe fee7 bl 800c034 <vListInitialise>
  29639. for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
  29640. 800d266: 45a0 cmp r8, r4
  29641. 800d268: d1f9 bne.n 800d25e <prvAddNewTaskToReadyList+0x96>
  29642. }
  29643. vListInitialise( &xDelayedTaskList1 );
  29644. 800d26a: f8df 9064 ldr.w r9, [pc, #100] @ 800d2d0 <prvAddNewTaskToReadyList+0x108>
  29645. vListInitialise( &xDelayedTaskList2 );
  29646. 800d26e: f8df 8064 ldr.w r8, [pc, #100] @ 800d2d4 <prvAddNewTaskToReadyList+0x10c>
  29647. vListInitialise( &xDelayedTaskList1 );
  29648. 800d272: 4648 mov r0, r9
  29649. 800d274: 4c0d ldr r4, [pc, #52] @ (800d2ac <prvAddNewTaskToReadyList+0xe4>)
  29650. 800d276: f7fe fedd bl 800c034 <vListInitialise>
  29651. vListInitialise( &xDelayedTaskList2 );
  29652. 800d27a: 4640 mov r0, r8
  29653. 800d27c: f7fe feda bl 800c034 <vListInitialise>
  29654. vListInitialise( &xPendingReadyList );
  29655. 800d280: 480e ldr r0, [pc, #56] @ (800d2bc <prvAddNewTaskToReadyList+0xf4>)
  29656. 800d282: f7fe fed7 bl 800c034 <vListInitialise>
  29657. #if ( INCLUDE_vTaskDelete == 1 )
  29658. {
  29659. vListInitialise( &xTasksWaitingTermination );
  29660. 800d286: 480e ldr r0, [pc, #56] @ (800d2c0 <prvAddNewTaskToReadyList+0xf8>)
  29661. 800d288: f7fe fed4 bl 800c034 <vListInitialise>
  29662. }
  29663. #endif /* INCLUDE_vTaskDelete */
  29664. #if ( INCLUDE_vTaskSuspend == 1 )
  29665. {
  29666. vListInitialise( &xSuspendedTaskList );
  29667. 800d28c: 480d ldr r0, [pc, #52] @ (800d2c4 <prvAddNewTaskToReadyList+0xfc>)
  29668. 800d28e: f7fe fed1 bl 800c034 <vListInitialise>
  29669. }
  29670. #endif /* INCLUDE_vTaskSuspend */
  29671. /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
  29672. using list2. */
  29673. pxDelayedTaskList = &xDelayedTaskList1;
  29674. 800d292: 4b0d ldr r3, [pc, #52] @ (800d2c8 <prvAddNewTaskToReadyList+0x100>)
  29675. prvAddTaskToReadyList( pxNewTCB );
  29676. 800d294: 6ae8 ldr r0, [r5, #44] @ 0x2c
  29677. pxDelayedTaskList = &xDelayedTaskList1;
  29678. 800d296: f8c3 9000 str.w r9, [r3]
  29679. pxOverflowDelayedTaskList = &xDelayedTaskList2;
  29680. 800d29a: 4b0c ldr r3, [pc, #48] @ (800d2cc <prvAddNewTaskToReadyList+0x104>)
  29681. 800d29c: f8c3 8000 str.w r8, [r3]
  29682. }
  29683. 800d2a0: e7a4 b.n 800d1ec <prvAddNewTaskToReadyList+0x24>
  29684. 800d2a2: bf00 nop
  29685. 800d2a4: 24002b6c .word 0x24002b6c
  29686. 800d2a8: 24003040 .word 0x24003040
  29687. 800d2ac: 24002b60 .word 0x24002b60
  29688. 800d2b0: 24002be0 .word 0x24002be0
  29689. 800d2b4: 24002b50 .word 0x24002b50
  29690. 800d2b8: 24002b64 .word 0x24002b64
  29691. 800d2bc: 24002b9c .word 0x24002b9c
  29692. 800d2c0: 24002b88 .word 0x24002b88
  29693. 800d2c4: 24002b70 .word 0x24002b70
  29694. 800d2c8: 24002bb4 .word 0x24002bb4
  29695. 800d2cc: 24002bb0 .word 0x24002bb0
  29696. 800d2d0: 24002bcc .word 0x24002bcc
  29697. 800d2d4: 24002bb8 .word 0x24002bb8
  29698. 0800d2d8 <prvInitialiseNewTask.constprop.0>:
  29699. static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
  29700. 800d2d8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  29701. 800d2dc: 9c0a ldr r4, [sp, #40] @ 0x28
  29702. ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
  29703. 800d2de: 0096 lsls r6, r2, #2
  29704. static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
  29705. 800d2e0: 4607 mov r7, r0
  29706. 800d2e2: 460d mov r5, r1
  29707. ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
  29708. 800d2e4: 4632 mov r2, r6
  29709. 800d2e6: 21a5 movs r1, #165 @ 0xa5
  29710. 800d2e8: 6b20 ldr r0, [r4, #48] @ 0x30
  29711. static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
  29712. 800d2ea: 4698 mov r8, r3
  29713. 800d2ec: f8dd 9024 ldr.w r9, [sp, #36] @ 0x24
  29714. pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
  29715. 800d2f0: 3e04 subs r6, #4
  29716. ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
  29717. 800d2f2: f002 fc09 bl 800fb08 <memset>
  29718. pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
  29719. 800d2f6: 6b23 ldr r3, [r4, #48] @ 0x30
  29720. 800d2f8: 441e add r6, r3
  29721. pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
  29722. 800d2fa: f026 0607 bic.w r6, r6, #7
  29723. if( pcName != NULL )
  29724. 800d2fe: 2d00 cmp r5, #0
  29725. 800d300: d072 beq.n 800d3e8 <prvInitialiseNewTask.constprop.0+0x110>
  29726. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29727. 800d302: 782b ldrb r3, [r5, #0]
  29728. 800d304: f884 3034 strb.w r3, [r4, #52] @ 0x34
  29729. if( pcName[ x ] == ( char ) 0x00 )
  29730. 800d308: 2b00 cmp r3, #0
  29731. 800d30a: d036 beq.n 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29732. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29733. 800d30c: 786b ldrb r3, [r5, #1]
  29734. 800d30e: f884 3035 strb.w r3, [r4, #53] @ 0x35
  29735. if( pcName[ x ] == ( char ) 0x00 )
  29736. 800d312: b393 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29737. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29738. 800d314: 78ab ldrb r3, [r5, #2]
  29739. 800d316: f884 3036 strb.w r3, [r4, #54] @ 0x36
  29740. if( pcName[ x ] == ( char ) 0x00 )
  29741. 800d31a: b373 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29742. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29743. 800d31c: 78eb ldrb r3, [r5, #3]
  29744. 800d31e: f884 3037 strb.w r3, [r4, #55] @ 0x37
  29745. if( pcName[ x ] == ( char ) 0x00 )
  29746. 800d322: b353 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29747. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29748. 800d324: 792b ldrb r3, [r5, #4]
  29749. 800d326: f884 3038 strb.w r3, [r4, #56] @ 0x38
  29750. if( pcName[ x ] == ( char ) 0x00 )
  29751. 800d32a: b333 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29752. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29753. 800d32c: 796b ldrb r3, [r5, #5]
  29754. 800d32e: f884 3039 strb.w r3, [r4, #57] @ 0x39
  29755. if( pcName[ x ] == ( char ) 0x00 )
  29756. 800d332: b313 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29757. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29758. 800d334: 79ab ldrb r3, [r5, #6]
  29759. 800d336: f884 303a strb.w r3, [r4, #58] @ 0x3a
  29760. if( pcName[ x ] == ( char ) 0x00 )
  29761. 800d33a: b1f3 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29762. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29763. 800d33c: 79eb ldrb r3, [r5, #7]
  29764. 800d33e: f884 303b strb.w r3, [r4, #59] @ 0x3b
  29765. if( pcName[ x ] == ( char ) 0x00 )
  29766. 800d342: b1d3 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29767. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29768. 800d344: 7a2b ldrb r3, [r5, #8]
  29769. 800d346: f884 303c strb.w r3, [r4, #60] @ 0x3c
  29770. if( pcName[ x ] == ( char ) 0x00 )
  29771. 800d34a: b1b3 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29772. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29773. 800d34c: 7a6b ldrb r3, [r5, #9]
  29774. 800d34e: f884 303d strb.w r3, [r4, #61] @ 0x3d
  29775. if( pcName[ x ] == ( char ) 0x00 )
  29776. 800d352: b193 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29777. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29778. 800d354: 7aab ldrb r3, [r5, #10]
  29779. 800d356: f884 303e strb.w r3, [r4, #62] @ 0x3e
  29780. if( pcName[ x ] == ( char ) 0x00 )
  29781. 800d35a: b173 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29782. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29783. 800d35c: 7aeb ldrb r3, [r5, #11]
  29784. 800d35e: f884 303f strb.w r3, [r4, #63] @ 0x3f
  29785. if( pcName[ x ] == ( char ) 0x00 )
  29786. 800d362: b153 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29787. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29788. 800d364: 7b2b ldrb r3, [r5, #12]
  29789. 800d366: f884 3040 strb.w r3, [r4, #64] @ 0x40
  29790. if( pcName[ x ] == ( char ) 0x00 )
  29791. 800d36a: b133 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29792. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29793. 800d36c: 7b6b ldrb r3, [r5, #13]
  29794. 800d36e: f884 3041 strb.w r3, [r4, #65] @ 0x41
  29795. if( pcName[ x ] == ( char ) 0x00 )
  29796. 800d372: b113 cbz r3, 800d37a <prvInitialiseNewTask.constprop.0+0xa2>
  29797. pxNewTCB->pcTaskName[ x ] = pcName[ x ];
  29798. 800d374: 7bab ldrb r3, [r5, #14]
  29799. 800d376: f884 3042 strb.w r3, [r4, #66] @ 0x42
  29800. pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
  29801. 800d37a: 2300 movs r3, #0
  29802. 800d37c: f884 3043 strb.w r3, [r4, #67] @ 0x43
  29803. if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
  29804. 800d380: 9d08 ldr r5, [sp, #32]
  29805. pxNewTCB->uxMutexesHeld = 0;
  29806. 800d382: f04f 0a00 mov.w sl, #0
  29807. vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
  29808. 800d386: 1d20 adds r0, r4, #4
  29809. if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
  29810. 800d388: 2d37 cmp r5, #55 @ 0x37
  29811. pxNewTCB->uxMutexesHeld = 0;
  29812. 800d38a: f8c4 a050 str.w sl, [r4, #80] @ 0x50
  29813. if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
  29814. 800d38e: bf28 it cs
  29815. 800d390: 2537 movcs r5, #55 @ 0x37
  29816. pxNewTCB->uxPriority = uxPriority;
  29817. 800d392: 62e5 str r5, [r4, #44] @ 0x2c
  29818. pxNewTCB->uxBasePriority = uxPriority;
  29819. 800d394: 64e5 str r5, [r4, #76] @ 0x4c
  29820. listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
  29821. 800d396: f1c5 0538 rsb r5, r5, #56 @ 0x38
  29822. vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
  29823. 800d39a: f7fe fe57 bl 800c04c <vListInitialiseItem>
  29824. vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
  29825. 800d39e: f104 0018 add.w r0, r4, #24
  29826. 800d3a2: f7fe fe53 bl 800c04c <vListInitialiseItem>
  29827. _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
  29828. 800d3a6: 4651 mov r1, sl
  29829. 800d3a8: 224c movs r2, #76 @ 0x4c
  29830. listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
  29831. 800d3aa: 61a5 str r5, [r4, #24]
  29832. pxNewTCB->ulNotifiedValue = 0;
  29833. 800d3ac: f8c4 a0a0 str.w sl, [r4, #160] @ 0xa0
  29834. _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
  29835. 800d3b0: f104 0054 add.w r0, r4, #84 @ 0x54
  29836. listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
  29837. 800d3b4: 6124 str r4, [r4, #16]
  29838. listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
  29839. 800d3b6: 6264 str r4, [r4, #36] @ 0x24
  29840. pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
  29841. 800d3b8: f884 a0a4 strb.w sl, [r4, #164] @ 0xa4
  29842. _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
  29843. 800d3bc: f002 fba4 bl 800fb08 <memset>
  29844. 800d3c0: 4b0b ldr r3, [pc, #44] @ (800d3f0 <prvInitialiseNewTask.constprop.0+0x118>)
  29845. pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
  29846. 800d3c2: 4642 mov r2, r8
  29847. 800d3c4: 4639 mov r1, r7
  29848. _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
  29849. 800d3c6: f103 0568 add.w r5, r3, #104 @ 0x68
  29850. 800d3ca: 65a3 str r3, [r4, #88] @ 0x58
  29851. 800d3cc: 33d0 adds r3, #208 @ 0xd0
  29852. pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
  29853. 800d3ce: 4630 mov r0, r6
  29854. _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
  29855. 800d3d0: 65e5 str r5, [r4, #92] @ 0x5c
  29856. 800d3d2: 6623 str r3, [r4, #96] @ 0x60
  29857. pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
  29858. 800d3d4: f001 faba bl 800e94c <pxPortInitialiseStack>
  29859. 800d3d8: 6020 str r0, [r4, #0]
  29860. if( pxCreatedTask != NULL )
  29861. 800d3da: f1b9 0f00 cmp.w r9, #0
  29862. 800d3de: d001 beq.n 800d3e4 <prvInitialiseNewTask.constprop.0+0x10c>
  29863. *pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
  29864. 800d3e0: f8c9 4000 str.w r4, [r9]
  29865. }
  29866. 800d3e4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  29867. pxNewTCB->pcTaskName[ 0 ] = 0x00;
  29868. 800d3e8: f884 5034 strb.w r5, [r4, #52] @ 0x34
  29869. 800d3ec: e7c8 b.n 800d380 <prvInitialiseNewTask.constprop.0+0xa8>
  29870. 800d3ee: bf00 nop
  29871. 800d3f0: 24013198 .word 0x24013198
  29872. 0800d3f4 <prvIdleTask>:
  29873. {
  29874. 800d3f4: b580 push {r7, lr}
  29875. 800d3f6: 4d23 ldr r5, [pc, #140] @ (800d484 <prvIdleTask+0x90>)
  29876. 800d3f8: 4f23 ldr r7, [pc, #140] @ (800d488 <prvIdleTask+0x94>)
  29877. 800d3fa: 4e24 ldr r6, [pc, #144] @ (800d48c <prvIdleTask+0x98>)
  29878. 800d3fc: f8df 8090 ldr.w r8, [pc, #144] @ 800d490 <prvIdleTask+0x9c>
  29879. {
  29880. TCB_t *pxTCB;
  29881. /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
  29882. being called too often in the idle task. */
  29883. while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
  29884. 800d400: 682b ldr r3, [r5, #0]
  29885. 800d402: b35b cbz r3, 800d45c <prvIdleTask+0x68>
  29886. {
  29887. taskENTER_CRITICAL();
  29888. 800d404: f001 face bl 800e9a4 <vPortEnterCritical>
  29889. {
  29890. pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  29891. 800d408: 68fb ldr r3, [r7, #12]
  29892. 800d40a: 68dc ldr r4, [r3, #12]
  29893. ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
  29894. 800d40c: 1d20 adds r0, r4, #4
  29895. 800d40e: f7fe fe47 bl 800c0a0 <uxListRemove>
  29896. --uxCurrentNumberOfTasks;
  29897. 800d412: 6833 ldr r3, [r6, #0]
  29898. 800d414: 3b01 subs r3, #1
  29899. 800d416: 6033 str r3, [r6, #0]
  29900. --uxDeletedTasksWaitingCleanUp;
  29901. 800d418: 682b ldr r3, [r5, #0]
  29902. 800d41a: 3b01 subs r3, #1
  29903. 800d41c: 602b str r3, [r5, #0]
  29904. }
  29905. taskEXIT_CRITICAL();
  29906. 800d41e: f001 fae3 bl 800e9e8 <vPortExitCritical>
  29907. to the task to free any memory allocated at the application level.
  29908. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
  29909. for additional information. */
  29910. #if ( configUSE_NEWLIB_REENTRANT == 1 )
  29911. {
  29912. _reclaim_reent( &( pxTCB->xNewLib_reent ) );
  29913. 800d422: f104 0054 add.w r0, r4, #84 @ 0x54
  29914. 800d426: f002 fb8b bl 800fb40 <_reclaim_reent>
  29915. #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
  29916. {
  29917. /* The task could have been allocated statically or dynamically, so
  29918. check what was statically allocated before trying to free the
  29919. memory. */
  29920. if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
  29921. 800d42a: f894 30a5 ldrb.w r3, [r4, #165] @ 0xa5
  29922. 800d42e: b163 cbz r3, 800d44a <prvIdleTask+0x56>
  29923. /* Both the stack and TCB were allocated dynamically, so both
  29924. must be freed. */
  29925. vPortFree( pxTCB->pxStack );
  29926. vPortFree( pxTCB );
  29927. }
  29928. else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
  29929. 800d430: 2b01 cmp r3, #1
  29930. 800d432: d022 beq.n 800d47a <prvIdleTask+0x86>
  29931. }
  29932. else
  29933. {
  29934. /* Neither the stack nor the TCB were allocated dynamically, so
  29935. nothing needs to be freed. */
  29936. configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
  29937. 800d434: 2b02 cmp r3, #2
  29938. 800d436: d0e3 beq.n 800d400 <prvIdleTask+0xc>
  29939. 800d438: f04f 0350 mov.w r3, #80 @ 0x50
  29940. 800d43c: f383 8811 msr BASEPRI, r3
  29941. 800d440: f3bf 8f6f isb sy
  29942. 800d444: f3bf 8f4f dsb sy
  29943. 800d448: e7fe b.n 800d448 <prvIdleTask+0x54>
  29944. vPortFree( pxTCB->pxStack );
  29945. 800d44a: 6b20 ldr r0, [r4, #48] @ 0x30
  29946. 800d44c: f001 fcc6 bl 800eddc <vPortFree>
  29947. vPortFree( pxTCB );
  29948. 800d450: 4620 mov r0, r4
  29949. 800d452: f001 fcc3 bl 800eddc <vPortFree>
  29950. while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
  29951. 800d456: 682b ldr r3, [r5, #0]
  29952. 800d458: 2b00 cmp r3, #0
  29953. 800d45a: d1d3 bne.n 800d404 <prvIdleTask+0x10>
  29954. if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
  29955. 800d45c: f8d8 3000 ldr.w r3, [r8]
  29956. 800d460: 2b01 cmp r3, #1
  29957. 800d462: d9cd bls.n 800d400 <prvIdleTask+0xc>
  29958. taskYIELD();
  29959. 800d464: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  29960. 800d468: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  29961. 800d46c: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  29962. 800d470: f3bf 8f4f dsb sy
  29963. 800d474: f3bf 8f6f isb sy
  29964. 800d478: e7c2 b.n 800d400 <prvIdleTask+0xc>
  29965. vPortFree( pxTCB );
  29966. 800d47a: 4620 mov r0, r4
  29967. 800d47c: f001 fcae bl 800eddc <vPortFree>
  29968. 800d480: e7be b.n 800d400 <prvIdleTask+0xc>
  29969. 800d482: bf00 nop
  29970. 800d484: 24002b84 .word 0x24002b84
  29971. 800d488: 24002b88 .word 0x24002b88
  29972. 800d48c: 24002b6c .word 0x24002b6c
  29973. 800d490: 24002be0 .word 0x24002be0
  29974. 0800d494 <xTaskIncrementTick.part.0>:
  29975. const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
  29976. 800d494: 4b49 ldr r3, [pc, #292] @ (800d5bc <xTaskIncrementTick.part.0+0x128>)
  29977. BaseType_t xTaskIncrementTick( void )
  29978. 800d496: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  29979. const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
  29980. 800d49a: 681e ldr r6, [r3, #0]
  29981. BaseType_t xTaskIncrementTick( void )
  29982. 800d49c: b083 sub sp, #12
  29983. const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
  29984. 800d49e: 3601 adds r6, #1
  29985. xTickCount = xConstTickCount;
  29986. 800d4a0: 601e str r6, [r3, #0]
  29987. if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
  29988. 800d4a2: 2e00 cmp r6, #0
  29989. 800d4a4: d03e beq.n 800d524 <xTaskIncrementTick.part.0+0x90>
  29990. 800d4a6: 4b46 ldr r3, [pc, #280] @ (800d5c0 <xTaskIncrementTick.part.0+0x12c>)
  29991. 800d4a8: 9301 str r3, [sp, #4]
  29992. if( xConstTickCount >= xNextTaskUnblockTime )
  29993. 800d4aa: 681b ldr r3, [r3, #0]
  29994. 800d4ac: 429e cmp r6, r3
  29995. 800d4ae: d346 bcc.n 800d53e <xTaskIncrementTick.part.0+0xaa>
  29996. if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
  29997. 800d4b0: 4f44 ldr r7, [pc, #272] @ (800d5c4 <xTaskIncrementTick.part.0+0x130>)
  29998. 800d4b2: 683b ldr r3, [r7, #0]
  29999. 800d4b4: 681d ldr r5, [r3, #0]
  30000. 800d4b6: 2d00 cmp r5, #0
  30001. 800d4b8: d077 beq.n 800d5aa <xTaskIncrementTick.part.0+0x116>
  30002. BaseType_t xSwitchRequired = pdFALSE;
  30003. 800d4ba: 2500 movs r5, #0
  30004. 800d4bc: f8df 9114 ldr.w r9, [pc, #276] @ 800d5d4 <xTaskIncrementTick.part.0+0x140>
  30005. 800d4c0: f8df a114 ldr.w sl, [pc, #276] @ 800d5d8 <xTaskIncrementTick.part.0+0x144>
  30006. prvAddTaskToReadyList( pxTCB );
  30007. 800d4c4: f8df 8114 ldr.w r8, [pc, #276] @ 800d5dc <xTaskIncrementTick.part.0+0x148>
  30008. 800d4c8: e020 b.n 800d50c <xTaskIncrementTick.part.0+0x78>
  30009. ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
  30010. 800d4ca: f7fe fde9 bl 800c0a0 <uxListRemove>
  30011. if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
  30012. 800d4ce: 6aa3 ldr r3, [r4, #40] @ 0x28
  30013. ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
  30014. 800d4d0: f104 0018 add.w r0, r4, #24
  30015. if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
  30016. 800d4d4: b10b cbz r3, 800d4da <xTaskIncrementTick.part.0+0x46>
  30017. ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
  30018. 800d4d6: f7fe fde3 bl 800c0a0 <uxListRemove>
  30019. prvAddTaskToReadyList( pxTCB );
  30020. 800d4da: 6ae3 ldr r3, [r4, #44] @ 0x2c
  30021. 800d4dc: 4659 mov r1, fp
  30022. 800d4de: f8d8 2000 ldr.w r2, [r8]
  30023. 800d4e2: eb03 0083 add.w r0, r3, r3, lsl #2
  30024. 800d4e6: 4293 cmp r3, r2
  30025. 800d4e8: eb09 0080 add.w r0, r9, r0, lsl #2
  30026. 800d4ec: d901 bls.n 800d4f2 <xTaskIncrementTick.part.0+0x5e>
  30027. 800d4ee: f8c8 3000 str.w r3, [r8]
  30028. 800d4f2: f7fe fdaf bl 800c054 <vListInsertEnd>
  30029. if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
  30030. 800d4f6: f8da 2000 ldr.w r2, [sl]
  30031. if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
  30032. 800d4fa: 683b ldr r3, [r7, #0]
  30033. if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
  30034. 800d4fc: 6ae1 ldr r1, [r4, #44] @ 0x2c
  30035. 800d4fe: 6ad2 ldr r2, [r2, #44] @ 0x2c
  30036. if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
  30037. 800d500: 681b ldr r3, [r3, #0]
  30038. xSwitchRequired = pdTRUE;
  30039. 800d502: 4291 cmp r1, r2
  30040. 800d504: bf28 it cs
  30041. 800d506: 2501 movcs r5, #1
  30042. if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
  30043. 800d508: 2b00 cmp r3, #0
  30044. 800d50a: d052 beq.n 800d5b2 <xTaskIncrementTick.part.0+0x11e>
  30045. pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  30046. 800d50c: 683b ldr r3, [r7, #0]
  30047. 800d50e: 68db ldr r3, [r3, #12]
  30048. 800d510: 68dc ldr r4, [r3, #12]
  30049. xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
  30050. 800d512: 6863 ldr r3, [r4, #4]
  30051. ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
  30052. 800d514: f104 0b04 add.w fp, r4, #4
  30053. if( xConstTickCount < xItemValue )
  30054. 800d518: 429e cmp r6, r3
  30055. ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
  30056. 800d51a: 4658 mov r0, fp
  30057. if( xConstTickCount < xItemValue )
  30058. 800d51c: d2d5 bcs.n 800d4ca <xTaskIncrementTick.part.0+0x36>
  30059. xNextTaskUnblockTime = xItemValue;
  30060. 800d51e: 9a01 ldr r2, [sp, #4]
  30061. 800d520: 6013 str r3, [r2, #0]
  30062. break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
  30063. 800d522: e011 b.n 800d548 <xTaskIncrementTick.part.0+0xb4>
  30064. taskSWITCH_DELAYED_LISTS();
  30065. 800d524: 4b27 ldr r3, [pc, #156] @ (800d5c4 <xTaskIncrementTick.part.0+0x130>)
  30066. 800d526: 681a ldr r2, [r3, #0]
  30067. 800d528: 6812 ldr r2, [r2, #0]
  30068. 800d52a: b30a cbz r2, 800d570 <xTaskIncrementTick.part.0+0xdc>
  30069. 800d52c: f04f 0350 mov.w r3, #80 @ 0x50
  30070. 800d530: f383 8811 msr BASEPRI, r3
  30071. 800d534: f3bf 8f6f isb sy
  30072. 800d538: f3bf 8f4f dsb sy
  30073. 800d53c: e7fe b.n 800d53c <xTaskIncrementTick.part.0+0xa8>
  30074. BaseType_t xSwitchRequired = pdFALSE;
  30075. 800d53e: 2500 movs r5, #0
  30076. 800d540: f8df 9090 ldr.w r9, [pc, #144] @ 800d5d4 <xTaskIncrementTick.part.0+0x140>
  30077. 800d544: f8df a090 ldr.w sl, [pc, #144] @ 800d5d8 <xTaskIncrementTick.part.0+0x144>
  30078. if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
  30079. 800d548: f8da 3000 ldr.w r3, [sl]
  30080. if( xYieldPending != pdFALSE )
  30081. 800d54c: 491e ldr r1, [pc, #120] @ (800d5c8 <xTaskIncrementTick.part.0+0x134>)
  30082. if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
  30083. 800d54e: 6adb ldr r3, [r3, #44] @ 0x2c
  30084. 800d550: eb03 0383 add.w r3, r3, r3, lsl #2
  30085. 800d554: 009b lsls r3, r3, #2
  30086. 800d556: f859 2003 ldr.w r2, [r9, r3]
  30087. if( xYieldPending != pdFALSE )
  30088. 800d55a: 680b ldr r3, [r1, #0]
  30089. xSwitchRequired = pdTRUE;
  30090. 800d55c: 2a02 cmp r2, #2
  30091. 800d55e: bf28 it cs
  30092. 800d560: 2501 movcs r5, #1
  30093. xSwitchRequired = pdTRUE;
  30094. 800d562: 2b00 cmp r3, #0
  30095. }
  30096. 800d564: bf0c ite eq
  30097. 800d566: 4628 moveq r0, r5
  30098. 800d568: 2001 movne r0, #1
  30099. 800d56a: b003 add sp, #12
  30100. 800d56c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  30101. taskSWITCH_DELAYED_LISTS();
  30102. 800d570: 4a16 ldr r2, [pc, #88] @ (800d5cc <xTaskIncrementTick.part.0+0x138>)
  30103. 800d572: 6818 ldr r0, [r3, #0]
  30104. 800d574: 6811 ldr r1, [r2, #0]
  30105. 800d576: 6019 str r1, [r3, #0]
  30106. 800d578: 4915 ldr r1, [pc, #84] @ (800d5d0 <xTaskIncrementTick.part.0+0x13c>)
  30107. 800d57a: 6010 str r0, [r2, #0]
  30108. 800d57c: 680a ldr r2, [r1, #0]
  30109. 800d57e: 3201 adds r2, #1
  30110. 800d580: 600a str r2, [r1, #0]
  30111. static void prvResetNextTaskUnblockTime( void )
  30112. {
  30113. TCB_t *pxTCB;
  30114. if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
  30115. 800d582: 681a ldr r2, [r3, #0]
  30116. 800d584: 6812 ldr r2, [r2, #0]
  30117. 800d586: b93a cbnz r2, 800d598 <xTaskIncrementTick.part.0+0x104>
  30118. {
  30119. /* The new current delayed list is empty. Set xNextTaskUnblockTime to
  30120. the maximum possible value so it is extremely unlikely that the
  30121. if( xTickCount >= xNextTaskUnblockTime ) test will pass until
  30122. there is an item in the delayed list. */
  30123. xNextTaskUnblockTime = portMAX_DELAY;
  30124. 800d588: 4b0d ldr r3, [pc, #52] @ (800d5c0 <xTaskIncrementTick.part.0+0x12c>)
  30125. 800d58a: 461a mov r2, r3
  30126. 800d58c: 9301 str r3, [sp, #4]
  30127. 800d58e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
  30128. 800d592: 6013 str r3, [r2, #0]
  30129. 800d594: 4613 mov r3, r2
  30130. 800d596: e788 b.n 800d4aa <xTaskIncrementTick.part.0+0x16>
  30131. {
  30132. /* The new current delayed list is not empty, get the value of
  30133. the item at the head of the delayed list. This is the time at
  30134. which the task at the head of the delayed list should be removed
  30135. from the Blocked state. */
  30136. ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  30137. 800d598: 681b ldr r3, [r3, #0]
  30138. xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
  30139. 800d59a: 4a09 ldr r2, [pc, #36] @ (800d5c0 <xTaskIncrementTick.part.0+0x12c>)
  30140. ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  30141. 800d59c: 68db ldr r3, [r3, #12]
  30142. xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
  30143. 800d59e: 9201 str r2, [sp, #4]
  30144. 800d5a0: 68db ldr r3, [r3, #12]
  30145. 800d5a2: 685b ldr r3, [r3, #4]
  30146. 800d5a4: 6013 str r3, [r2, #0]
  30147. 800d5a6: 4613 mov r3, r2
  30148. }
  30149. }
  30150. 800d5a8: e77f b.n 800d4aa <xTaskIncrementTick.part.0+0x16>
  30151. 800d5aa: f8df 9028 ldr.w r9, [pc, #40] @ 800d5d4 <xTaskIncrementTick.part.0+0x140>
  30152. 800d5ae: f8df a028 ldr.w sl, [pc, #40] @ 800d5d8 <xTaskIncrementTick.part.0+0x144>
  30153. xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
  30154. 800d5b2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
  30155. 800d5b6: 9a01 ldr r2, [sp, #4]
  30156. 800d5b8: 6013 str r3, [r2, #0]
  30157. break;
  30158. 800d5ba: e7c5 b.n 800d548 <xTaskIncrementTick.part.0+0xb4>
  30159. 800d5bc: 24002b68 .word 0x24002b68
  30160. 800d5c0: 24002b4c .word 0x24002b4c
  30161. 800d5c4: 24002bb4 .word 0x24002bb4
  30162. 800d5c8: 24002b58 .word 0x24002b58
  30163. 800d5cc: 24002bb0 .word 0x24002bb0
  30164. 800d5d0: 24002b54 .word 0x24002b54
  30165. 800d5d4: 24002be0 .word 0x24002be0
  30166. 800d5d8: 24003040 .word 0x24003040
  30167. 800d5dc: 24002b64 .word 0x24002b64
  30168. 0800d5e0 <xTaskResumeAll.part.0>:
  30169. BaseType_t xTaskResumeAll( void )
  30170. 800d5e0: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  30171. --uxSchedulerSuspended;
  30172. 800d5e4: 4d43 ldr r5, [pc, #268] @ (800d6f4 <xTaskResumeAll.part.0+0x114>)
  30173. taskENTER_CRITICAL();
  30174. 800d5e6: f001 f9dd bl 800e9a4 <vPortEnterCritical>
  30175. --uxSchedulerSuspended;
  30176. 800d5ea: 682b ldr r3, [r5, #0]
  30177. 800d5ec: 3b01 subs r3, #1
  30178. 800d5ee: 602b str r3, [r5, #0]
  30179. if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
  30180. 800d5f0: 682b ldr r3, [r5, #0]
  30181. 800d5f2: 2b00 cmp r3, #0
  30182. 800d5f4: d168 bne.n 800d6c8 <xTaskResumeAll.part.0+0xe8>
  30183. if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
  30184. 800d5f6: 4b40 ldr r3, [pc, #256] @ (800d6f8 <xTaskResumeAll.part.0+0x118>)
  30185. 800d5f8: 681b ldr r3, [r3, #0]
  30186. 800d5fa: 2b00 cmp r3, #0
  30187. 800d5fc: d064 beq.n 800d6c8 <xTaskResumeAll.part.0+0xe8>
  30188. while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
  30189. 800d5fe: 4e3f ldr r6, [pc, #252] @ (800d6fc <xTaskResumeAll.part.0+0x11c>)
  30190. 800d600: 6833 ldr r3, [r6, #0]
  30191. 800d602: 2b00 cmp r3, #0
  30192. 800d604: d073 beq.n 800d6ee <xTaskResumeAll.part.0+0x10e>
  30193. 800d606: 4f3e ldr r7, [pc, #248] @ (800d700 <xTaskResumeAll.part.0+0x120>)
  30194. 800d608: f8df 9104 ldr.w r9, [pc, #260] @ 800d710 <xTaskResumeAll.part.0+0x130>
  30195. 800d60c: f8df 8104 ldr.w r8, [pc, #260] @ 800d714 <xTaskResumeAll.part.0+0x134>
  30196. 800d610: f8df a104 ldr.w sl, [pc, #260] @ 800d718 <xTaskResumeAll.part.0+0x138>
  30197. pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  30198. 800d614: 68f3 ldr r3, [r6, #12]
  30199. 800d616: f8d3 b00c ldr.w fp, [r3, #12]
  30200. ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
  30201. 800d61a: f10b 0404 add.w r4, fp, #4
  30202. ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
  30203. 800d61e: f10b 0018 add.w r0, fp, #24
  30204. 800d622: f7fe fd3d bl 800c0a0 <uxListRemove>
  30205. ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
  30206. 800d626: 4620 mov r0, r4
  30207. 800d628: f7fe fd3a bl 800c0a0 <uxListRemove>
  30208. prvAddTaskToReadyList( pxTCB );
  30209. 800d62c: f8db 202c ldr.w r2, [fp, #44] @ 0x2c
  30210. 800d630: 4621 mov r1, r4
  30211. 800d632: 683c ldr r4, [r7, #0]
  30212. 800d634: eb02 0082 add.w r0, r2, r2, lsl #2
  30213. 800d638: 42a2 cmp r2, r4
  30214. 800d63a: eb09 0080 add.w r0, r9, r0, lsl #2
  30215. 800d63e: d900 bls.n 800d642 <xTaskResumeAll.part.0+0x62>
  30216. 800d640: 603a str r2, [r7, #0]
  30217. 800d642: f7fe fd07 bl 800c054 <vListInsertEnd>
  30218. if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
  30219. 800d646: f8d8 1000 ldr.w r1, [r8]
  30220. 800d64a: f8db 202c ldr.w r2, [fp, #44] @ 0x2c
  30221. 800d64e: 6acb ldr r3, [r1, #44] @ 0x2c
  30222. 800d650: 429a cmp r2, r3
  30223. 800d652: d33f bcc.n 800d6d4 <xTaskResumeAll.part.0+0xf4>
  30224. xYieldPending = pdTRUE;
  30225. 800d654: 2301 movs r3, #1
  30226. 800d656: f8ca 3000 str.w r3, [sl]
  30227. while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
  30228. 800d65a: 6833 ldr r3, [r6, #0]
  30229. 800d65c: 2b00 cmp r3, #0
  30230. 800d65e: d1d9 bne.n 800d614 <xTaskResumeAll.part.0+0x34>
  30231. if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
  30232. 800d660: 4b28 ldr r3, [pc, #160] @ (800d704 <xTaskResumeAll.part.0+0x124>)
  30233. 800d662: 681a ldr r2, [r3, #0]
  30234. 800d664: 6812 ldr r2, [r2, #0]
  30235. 800d666: 2a00 cmp r2, #0
  30236. 800d668: d03c beq.n 800d6e4 <xTaskResumeAll.part.0+0x104>
  30237. ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  30238. 800d66a: 681a ldr r2, [r3, #0]
  30239. xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
  30240. 800d66c: 4b26 ldr r3, [pc, #152] @ (800d708 <xTaskResumeAll.part.0+0x128>)
  30241. ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  30242. 800d66e: 68d2 ldr r2, [r2, #12]
  30243. xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
  30244. 800d670: 68d2 ldr r2, [r2, #12]
  30245. 800d672: 6852 ldr r2, [r2, #4]
  30246. 800d674: 601a str r2, [r3, #0]
  30247. TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
  30248. 800d676: 4e25 ldr r6, [pc, #148] @ (800d70c <xTaskResumeAll.part.0+0x12c>)
  30249. 800d678: 6834 ldr r4, [r6, #0]
  30250. if( xPendedCounts > ( TickType_t ) 0U )
  30251. 800d67a: b194 cbz r4, 800d6a2 <xTaskResumeAll.part.0+0xc2>
  30252. xYieldPending = pdTRUE;
  30253. 800d67c: 2701 movs r7, #1
  30254. 800d67e: e006 b.n 800d68e <xTaskResumeAll.part.0+0xae>
  30255. 800d680: f7ff ff08 bl 800d494 <xTaskIncrementTick.part.0>
  30256. if( xTaskIncrementTick() != pdFALSE )
  30257. 800d684: b108 cbz r0, 800d68a <xTaskResumeAll.part.0+0xaa>
  30258. xYieldPending = pdTRUE;
  30259. 800d686: f8ca 7000 str.w r7, [sl]
  30260. } while( xPendedCounts > ( TickType_t ) 0U );
  30261. 800d68a: 3c01 subs r4, #1
  30262. 800d68c: d008 beq.n 800d6a0 <xTaskResumeAll.part.0+0xc0>
  30263. if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
  30264. 800d68e: 682b ldr r3, [r5, #0]
  30265. 800d690: 2b00 cmp r3, #0
  30266. 800d692: d0f5 beq.n 800d680 <xTaskResumeAll.part.0+0xa0>
  30267. ++xPendedTicks;
  30268. 800d694: 6833 ldr r3, [r6, #0]
  30269. } while( xPendedCounts > ( TickType_t ) 0U );
  30270. 800d696: 3c01 subs r4, #1
  30271. ++xPendedTicks;
  30272. 800d698: f103 0301 add.w r3, r3, #1
  30273. 800d69c: 6033 str r3, [r6, #0]
  30274. } while( xPendedCounts > ( TickType_t ) 0U );
  30275. 800d69e: d1f6 bne.n 800d68e <xTaskResumeAll.part.0+0xae>
  30276. xPendedTicks = 0;
  30277. 800d6a0: 6034 str r4, [r6, #0]
  30278. if( xYieldPending != pdFALSE )
  30279. 800d6a2: f8da 3000 ldr.w r3, [sl]
  30280. 800d6a6: b17b cbz r3, 800d6c8 <xTaskResumeAll.part.0+0xe8>
  30281. taskYIELD_IF_USING_PREEMPTION();
  30282. 800d6a8: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  30283. 800d6ac: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  30284. 800d6b0: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  30285. 800d6b4: f3bf 8f4f dsb sy
  30286. 800d6b8: f3bf 8f6f isb sy
  30287. xAlreadyYielded = pdTRUE;
  30288. 800d6bc: 2401 movs r4, #1
  30289. taskEXIT_CRITICAL();
  30290. 800d6be: f001 f993 bl 800e9e8 <vPortExitCritical>
  30291. }
  30292. 800d6c2: 4620 mov r0, r4
  30293. 800d6c4: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
  30294. BaseType_t xAlreadyYielded = pdFALSE;
  30295. 800d6c8: 2400 movs r4, #0
  30296. taskEXIT_CRITICAL();
  30297. 800d6ca: f001 f98d bl 800e9e8 <vPortExitCritical>
  30298. }
  30299. 800d6ce: 4620 mov r0, r4
  30300. 800d6d0: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
  30301. while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
  30302. 800d6d4: 6833 ldr r3, [r6, #0]
  30303. 800d6d6: 2b00 cmp r3, #0
  30304. 800d6d8: d19c bne.n 800d614 <xTaskResumeAll.part.0+0x34>
  30305. if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
  30306. 800d6da: 4b0a ldr r3, [pc, #40] @ (800d704 <xTaskResumeAll.part.0+0x124>)
  30307. 800d6dc: 681a ldr r2, [r3, #0]
  30308. 800d6de: 6812 ldr r2, [r2, #0]
  30309. 800d6e0: 2a00 cmp r2, #0
  30310. 800d6e2: d1c2 bne.n 800d66a <xTaskResumeAll.part.0+0x8a>
  30311. xNextTaskUnblockTime = portMAX_DELAY;
  30312. 800d6e4: 4b08 ldr r3, [pc, #32] @ (800d708 <xTaskResumeAll.part.0+0x128>)
  30313. 800d6e6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
  30314. 800d6ea: 601a str r2, [r3, #0]
  30315. 800d6ec: e7c3 b.n 800d676 <xTaskResumeAll.part.0+0x96>
  30316. 800d6ee: f8df a028 ldr.w sl, [pc, #40] @ 800d718 <xTaskResumeAll.part.0+0x138>
  30317. 800d6f2: e7c0 b.n 800d676 <xTaskResumeAll.part.0+0x96>
  30318. 800d6f4: 24002b48 .word 0x24002b48
  30319. 800d6f8: 24002b6c .word 0x24002b6c
  30320. 800d6fc: 24002b9c .word 0x24002b9c
  30321. 800d700: 24002b64 .word 0x24002b64
  30322. 800d704: 24002bb4 .word 0x24002bb4
  30323. 800d708: 24002b4c .word 0x24002b4c
  30324. 800d70c: 24002b5c .word 0x24002b5c
  30325. 800d710: 24002be0 .word 0x24002be0
  30326. 800d714: 24003040 .word 0x24003040
  30327. 800d718: 24002b58 .word 0x24002b58
  30328. 0800d71c <xTaskCreateStatic>:
  30329. {
  30330. 800d71c: b530 push {r4, r5, lr}
  30331. 800d71e: b087 sub sp, #28
  30332. 800d720: 9c0b ldr r4, [sp, #44] @ 0x2c
  30333. configASSERT( puxStackBuffer != NULL );
  30334. 800d722: b1c4 cbz r4, 800d756 <xTaskCreateStatic+0x3a>
  30335. configASSERT( pxTaskBuffer != NULL );
  30336. 800d724: 9d0c ldr r5, [sp, #48] @ 0x30
  30337. 800d726: b16d cbz r5, 800d744 <xTaskCreateStatic+0x28>
  30338. volatile size_t xSize = sizeof( StaticTask_t );
  30339. 800d728: 25a8 movs r5, #168 @ 0xa8
  30340. 800d72a: 9505 str r5, [sp, #20]
  30341. configASSERT( xSize == sizeof( TCB_t ) );
  30342. 800d72c: 9d05 ldr r5, [sp, #20]
  30343. 800d72e: 2da8 cmp r5, #168 @ 0xa8
  30344. 800d730: d01a beq.n 800d768 <xTaskCreateStatic+0x4c>
  30345. 800d732: f04f 0350 mov.w r3, #80 @ 0x50
  30346. 800d736: f383 8811 msr BASEPRI, r3
  30347. 800d73a: f3bf 8f6f isb sy
  30348. 800d73e: f3bf 8f4f dsb sy
  30349. 800d742: e7fe b.n 800d742 <xTaskCreateStatic+0x26>
  30350. 800d744: f04f 0350 mov.w r3, #80 @ 0x50
  30351. 800d748: f383 8811 msr BASEPRI, r3
  30352. 800d74c: f3bf 8f6f isb sy
  30353. 800d750: f3bf 8f4f dsb sy
  30354. configASSERT( pxTaskBuffer != NULL );
  30355. 800d754: e7fe b.n 800d754 <xTaskCreateStatic+0x38>
  30356. 800d756: f04f 0350 mov.w r3, #80 @ 0x50
  30357. 800d75a: f383 8811 msr BASEPRI, r3
  30358. 800d75e: f3bf 8f6f isb sy
  30359. 800d762: f3bf 8f4f dsb sy
  30360. configASSERT( puxStackBuffer != NULL );
  30361. 800d766: e7fe b.n 800d766 <xTaskCreateStatic+0x4a>
  30362. pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
  30363. 800d768: 9d0c ldr r5, [sp, #48] @ 0x30
  30364. 800d76a: 632c str r4, [r5, #48] @ 0x30
  30365. pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
  30366. 800d76c: 2402 movs r4, #2
  30367. prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
  30368. 800d76e: 9502 str r5, [sp, #8]
  30369. 800d770: 9d0a ldr r5, [sp, #40] @ 0x28
  30370. 800d772: 9500 str r5, [sp, #0]
  30371. pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
  30372. 800d774: 9d0c ldr r5, [sp, #48] @ 0x30
  30373. 800d776: f885 40a5 strb.w r4, [r5, #165] @ 0xa5
  30374. prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
  30375. 800d77a: ac04 add r4, sp, #16
  30376. ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
  30377. 800d77c: 9d05 ldr r5, [sp, #20]
  30378. prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
  30379. 800d77e: 9401 str r4, [sp, #4]
  30380. 800d780: f7ff fdaa bl 800d2d8 <prvInitialiseNewTask.constprop.0>
  30381. prvAddNewTaskToReadyList( pxNewTCB );
  30382. 800d784: 980c ldr r0, [sp, #48] @ 0x30
  30383. 800d786: f7ff fd1f bl 800d1c8 <prvAddNewTaskToReadyList>
  30384. }
  30385. 800d78a: 9804 ldr r0, [sp, #16]
  30386. 800d78c: b007 add sp, #28
  30387. 800d78e: bd30 pop {r4, r5, pc}
  30388. 0800d790 <xTaskCreate>:
  30389. {
  30390. 800d790: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
  30391. 800d794: 4607 mov r7, r0
  30392. 800d796: b085 sub sp, #20
  30393. pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
  30394. 800d798: 0090 lsls r0, r2, #2
  30395. {
  30396. 800d79a: 4615 mov r5, r2
  30397. 800d79c: 4688 mov r8, r1
  30398. 800d79e: 4699 mov r9, r3
  30399. pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
  30400. 800d7a0: f001 fa60 bl 800ec64 <pvPortMalloc>
  30401. if( pxStack != NULL )
  30402. 800d7a4: b1f0 cbz r0, 800d7e4 <xTaskCreate+0x54>
  30403. pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
  30404. 800d7a6: 4604 mov r4, r0
  30405. 800d7a8: 20a8 movs r0, #168 @ 0xa8
  30406. 800d7aa: f001 fa5b bl 800ec64 <pvPortMalloc>
  30407. if( pxNewTCB != NULL )
  30408. 800d7ae: 4606 mov r6, r0
  30409. 800d7b0: b1a8 cbz r0, 800d7de <xTaskCreate+0x4e>
  30410. pxNewTCB->pxStack = pxStack;
  30411. 800d7b2: 6304 str r4, [r0, #48] @ 0x30
  30412. pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
  30413. 800d7b4: 2400 movs r4, #0
  30414. prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
  30415. 800d7b6: 464b mov r3, r9
  30416. 800d7b8: 462a mov r2, r5
  30417. pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
  30418. 800d7ba: f886 40a5 strb.w r4, [r6, #165] @ 0xa5
  30419. prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
  30420. 800d7be: 4641 mov r1, r8
  30421. 800d7c0: 9c0d ldr r4, [sp, #52] @ 0x34
  30422. 800d7c2: 4638 mov r0, r7
  30423. 800d7c4: 9602 str r6, [sp, #8]
  30424. 800d7c6: 9401 str r4, [sp, #4]
  30425. 800d7c8: 9c0c ldr r4, [sp, #48] @ 0x30
  30426. 800d7ca: 9400 str r4, [sp, #0]
  30427. 800d7cc: f7ff fd84 bl 800d2d8 <prvInitialiseNewTask.constprop.0>
  30428. prvAddNewTaskToReadyList( pxNewTCB );
  30429. 800d7d0: 4630 mov r0, r6
  30430. 800d7d2: f7ff fcf9 bl 800d1c8 <prvAddNewTaskToReadyList>
  30431. xReturn = pdPASS;
  30432. 800d7d6: 2001 movs r0, #1
  30433. }
  30434. 800d7d8: b005 add sp, #20
  30435. 800d7da: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
  30436. vPortFree( pxStack );
  30437. 800d7de: 4620 mov r0, r4
  30438. 800d7e0: f001 fafc bl 800eddc <vPortFree>
  30439. xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
  30440. 800d7e4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  30441. }
  30442. 800d7e8: b005 add sp, #20
  30443. 800d7ea: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
  30444. 800d7ee: bf00 nop
  30445. 0800d7f0 <vTaskDelay>:
  30446. {
  30447. 800d7f0: b5f8 push {r3, r4, r5, r6, r7, lr}
  30448. if( xTicksToDelay > ( TickType_t ) 0U )
  30449. 800d7f2: b950 cbnz r0, 800d80a <vTaskDelay+0x1a>
  30450. portYIELD_WITHIN_API();
  30451. 800d7f4: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  30452. 800d7f8: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  30453. 800d7fc: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  30454. 800d800: f3bf 8f4f dsb sy
  30455. 800d804: f3bf 8f6f isb sy
  30456. }
  30457. 800d808: bdf8 pop {r3, r4, r5, r6, r7, pc}
  30458. configASSERT( uxSchedulerSuspended == 0 );
  30459. 800d80a: 4d1e ldr r5, [pc, #120] @ (800d884 <vTaskDelay+0x94>)
  30460. 800d80c: 682b ldr r3, [r5, #0]
  30461. 800d80e: b143 cbz r3, 800d822 <vTaskDelay+0x32>
  30462. 800d810: f04f 0350 mov.w r3, #80 @ 0x50
  30463. 800d814: f383 8811 msr BASEPRI, r3
  30464. 800d818: f3bf 8f6f isb sy
  30465. 800d81c: f3bf 8f4f dsb sy
  30466. 800d820: e7fe b.n 800d820 <vTaskDelay+0x30>
  30467. ++uxSchedulerSuspended;
  30468. 800d822: 682b ldr r3, [r5, #0]
  30469. 800d824: 4604 mov r4, r0
  30470. 800d826: 3301 adds r3, #1
  30471. 800d828: 602b str r3, [r5, #0]
  30472. /*-----------------------------------------------------------*/
  30473. static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
  30474. {
  30475. TickType_t xTimeToWake;
  30476. const TickType_t xConstTickCount = xTickCount;
  30477. 800d82a: 4b17 ldr r3, [pc, #92] @ (800d888 <vTaskDelay+0x98>)
  30478. }
  30479. #endif
  30480. /* Remove the task from the ready list before adding it to the blocked list
  30481. as the same list item is used for both lists. */
  30482. if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
  30483. 800d82c: 4e17 ldr r6, [pc, #92] @ (800d88c <vTaskDelay+0x9c>)
  30484. const TickType_t xConstTickCount = xTickCount;
  30485. 800d82e: 681f ldr r7, [r3, #0]
  30486. if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
  30487. 800d830: 6830 ldr r0, [r6, #0]
  30488. 800d832: 3004 adds r0, #4
  30489. 800d834: f7fe fc34 bl 800c0a0 <uxListRemove>
  30490. else
  30491. {
  30492. /* Calculate the time at which the task should be woken if the event
  30493. does not occur. This may overflow but this doesn't matter, the
  30494. kernel will manage it correctly. */
  30495. xTimeToWake = xConstTickCount + xTicksToWait;
  30496. 800d838: 19e4 adds r4, r4, r7
  30497. /* The list item will be inserted in wake time order. */
  30498. listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
  30499. 800d83a: 6833 ldr r3, [r6, #0]
  30500. 800d83c: 605c str r4, [r3, #4]
  30501. if( xTimeToWake < xConstTickCount )
  30502. 800d83e: d315 bcc.n 800d86c <vTaskDelay+0x7c>
  30503. {
  30504. /* Wake time has overflowed. Place this item in the overflow
  30505. list. */
  30506. vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
  30507. 800d840: 4b13 ldr r3, [pc, #76] @ (800d890 <vTaskDelay+0xa0>)
  30508. 800d842: 6818 ldr r0, [r3, #0]
  30509. 800d844: 6831 ldr r1, [r6, #0]
  30510. 800d846: 3104 adds r1, #4
  30511. 800d848: f7fe fc12 bl 800c070 <vListInsert>
  30512. configASSERT( uxSchedulerSuspended );
  30513. 800d84c: 682b ldr r3, [r5, #0]
  30514. 800d84e: b943 cbnz r3, 800d862 <vTaskDelay+0x72>
  30515. 800d850: f04f 0350 mov.w r3, #80 @ 0x50
  30516. 800d854: f383 8811 msr BASEPRI, r3
  30517. 800d858: f3bf 8f6f isb sy
  30518. 800d85c: f3bf 8f4f dsb sy
  30519. 800d860: e7fe b.n 800d860 <vTaskDelay+0x70>
  30520. 800d862: f7ff febd bl 800d5e0 <xTaskResumeAll.part.0>
  30521. if( xAlreadyYielded == pdFALSE )
  30522. 800d866: 2800 cmp r0, #0
  30523. 800d868: d0c4 beq.n 800d7f4 <vTaskDelay+0x4>
  30524. }
  30525. 800d86a: bdf8 pop {r3, r4, r5, r6, r7, pc}
  30526. }
  30527. else
  30528. {
  30529. /* The wake time has not overflowed, so the current block list
  30530. is used. */
  30531. vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
  30532. 800d86c: 4b09 ldr r3, [pc, #36] @ (800d894 <vTaskDelay+0xa4>)
  30533. 800d86e: 6818 ldr r0, [r3, #0]
  30534. 800d870: 6831 ldr r1, [r6, #0]
  30535. 800d872: 3104 adds r1, #4
  30536. 800d874: f7fe fbfc bl 800c070 <vListInsert>
  30537. /* If the task entering the blocked state was placed at the
  30538. head of the list of blocked tasks then xNextTaskUnblockTime
  30539. needs to be updated too. */
  30540. if( xTimeToWake < xNextTaskUnblockTime )
  30541. 800d878: 4b07 ldr r3, [pc, #28] @ (800d898 <vTaskDelay+0xa8>)
  30542. 800d87a: 681a ldr r2, [r3, #0]
  30543. 800d87c: 4294 cmp r4, r2
  30544. 800d87e: d2e5 bcs.n 800d84c <vTaskDelay+0x5c>
  30545. {
  30546. xNextTaskUnblockTime = xTimeToWake;
  30547. 800d880: 601c str r4, [r3, #0]
  30548. 800d882: e7e3 b.n 800d84c <vTaskDelay+0x5c>
  30549. 800d884: 24002b48 .word 0x24002b48
  30550. 800d888: 24002b68 .word 0x24002b68
  30551. 800d88c: 24003040 .word 0x24003040
  30552. 800d890: 24002bb0 .word 0x24002bb0
  30553. 800d894: 24002bb4 .word 0x24002bb4
  30554. 800d898: 24002b4c .word 0x24002b4c
  30555. 0800d89c <vTaskStartScheduler>:
  30556. {
  30557. 800d89c: b530 push {r4, r5, lr}
  30558. 800d89e: b08b sub sp, #44 @ 0x2c
  30559. StaticTask_t *pxIdleTaskTCBBuffer = NULL;
  30560. 800d8a0: 2400 movs r4, #0
  30561. vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
  30562. 800d8a2: aa07 add r2, sp, #28
  30563. 800d8a4: a906 add r1, sp, #24
  30564. 800d8a6: a805 add r0, sp, #20
  30565. StackType_t *pxIdleTaskStackBuffer = NULL;
  30566. 800d8a8: e9cd 4405 strd r4, r4, [sp, #20]
  30567. vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
  30568. 800d8ac: f7fe fba2 bl 800bff4 <vApplicationGetIdleTaskMemory>
  30569. xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
  30570. 800d8b0: 9d05 ldr r5, [sp, #20]
  30571. 800d8b2: e9dd 3206 ldrd r3, r2, [sp, #24]
  30572. configASSERT( puxStackBuffer != NULL );
  30573. 800d8b6: b1bb cbz r3, 800d8e8 <vTaskStartScheduler+0x4c>
  30574. configASSERT( pxTaskBuffer != NULL );
  30575. 800d8b8: b16d cbz r5, 800d8d6 <vTaskStartScheduler+0x3a>
  30576. volatile size_t xSize = sizeof( StaticTask_t );
  30577. 800d8ba: 21a8 movs r1, #168 @ 0xa8
  30578. 800d8bc: 9109 str r1, [sp, #36] @ 0x24
  30579. configASSERT( xSize == sizeof( TCB_t ) );
  30580. 800d8be: 9909 ldr r1, [sp, #36] @ 0x24
  30581. 800d8c0: 29a8 cmp r1, #168 @ 0xa8
  30582. 800d8c2: d01a beq.n 800d8fa <vTaskStartScheduler+0x5e>
  30583. 800d8c4: f04f 0350 mov.w r3, #80 @ 0x50
  30584. 800d8c8: f383 8811 msr BASEPRI, r3
  30585. 800d8cc: f3bf 8f6f isb sy
  30586. 800d8d0: f3bf 8f4f dsb sy
  30587. 800d8d4: e7fe b.n 800d8d4 <vTaskStartScheduler+0x38>
  30588. 800d8d6: f04f 0350 mov.w r3, #80 @ 0x50
  30589. 800d8da: f383 8811 msr BASEPRI, r3
  30590. 800d8de: f3bf 8f6f isb sy
  30591. 800d8e2: f3bf 8f4f dsb sy
  30592. configASSERT( pxTaskBuffer != NULL );
  30593. 800d8e6: e7fe b.n 800d8e6 <vTaskStartScheduler+0x4a>
  30594. 800d8e8: f04f 0350 mov.w r3, #80 @ 0x50
  30595. 800d8ec: f383 8811 msr BASEPRI, r3
  30596. 800d8f0: f3bf 8f6f isb sy
  30597. 800d8f4: f3bf 8f4f dsb sy
  30598. configASSERT( puxStackBuffer != NULL );
  30599. 800d8f8: e7fe b.n 800d8f8 <vTaskStartScheduler+0x5c>
  30600. pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
  30601. 800d8fa: 2102 movs r1, #2
  30602. pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
  30603. 800d8fc: 632b str r3, [r5, #48] @ 0x30
  30604. prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
  30605. 800d8fe: 481e ldr r0, [pc, #120] @ (800d978 <vTaskStartScheduler+0xdc>)
  30606. pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
  30607. 800d900: f885 10a5 strb.w r1, [r5, #165] @ 0xa5
  30608. prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
  30609. 800d904: a908 add r1, sp, #32
  30610. ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
  30611. 800d906: 9b09 ldr r3, [sp, #36] @ 0x24
  30612. prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
  30613. 800d908: 4623 mov r3, r4
  30614. 800d90a: 9400 str r4, [sp, #0]
  30615. 800d90c: e9cd 1501 strd r1, r5, [sp, #4]
  30616. 800d910: 491a ldr r1, [pc, #104] @ (800d97c <vTaskStartScheduler+0xe0>)
  30617. 800d912: f7ff fce1 bl 800d2d8 <prvInitialiseNewTask.constprop.0>
  30618. prvAddNewTaskToReadyList( pxNewTCB );
  30619. 800d916: 4628 mov r0, r5
  30620. 800d918: f7ff fc56 bl 800d1c8 <prvAddNewTaskToReadyList>
  30621. return xReturn;
  30622. 800d91c: 9b08 ldr r3, [sp, #32]
  30623. if( xIdleTaskHandle != NULL )
  30624. 800d91e: b17b cbz r3, 800d940 <vTaskStartScheduler+0xa4>
  30625. xReturn = xTimerCreateTimerTask();
  30626. 800d920: f000 fe30 bl 800e584 <xTimerCreateTimerTask>
  30627. if( xReturn == pdPASS )
  30628. 800d924: 2801 cmp r0, #1
  30629. xReturn = xTimerCreateTimerTask();
  30630. 800d926: 4603 mov r3, r0
  30631. if( xReturn == pdPASS )
  30632. 800d928: d00c beq.n 800d944 <vTaskStartScheduler+0xa8>
  30633. configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
  30634. 800d92a: 3301 adds r3, #1
  30635. 800d92c: d108 bne.n 800d940 <vTaskStartScheduler+0xa4>
  30636. 800d92e: f04f 0350 mov.w r3, #80 @ 0x50
  30637. 800d932: f383 8811 msr BASEPRI, r3
  30638. 800d936: f3bf 8f6f isb sy
  30639. 800d93a: f3bf 8f4f dsb sy
  30640. 800d93e: e7fe b.n 800d93e <vTaskStartScheduler+0xa2>
  30641. }
  30642. 800d940: b00b add sp, #44 @ 0x2c
  30643. 800d942: bd30 pop {r4, r5, pc}
  30644. 800d944: f04f 0250 mov.w r2, #80 @ 0x50
  30645. 800d948: f382 8811 msr BASEPRI, r2
  30646. 800d94c: f3bf 8f6f isb sy
  30647. 800d950: f3bf 8f4f dsb sy
  30648. _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
  30649. 800d954: 4a0a ldr r2, [pc, #40] @ (800d980 <vTaskStartScheduler+0xe4>)
  30650. 800d956: 490b ldr r1, [pc, #44] @ (800d984 <vTaskStartScheduler+0xe8>)
  30651. 800d958: 6812 ldr r2, [r2, #0]
  30652. xNextTaskUnblockTime = portMAX_DELAY;
  30653. 800d95a: 480b ldr r0, [pc, #44] @ (800d988 <vTaskStartScheduler+0xec>)
  30654. _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
  30655. 800d95c: 3254 adds r2, #84 @ 0x54
  30656. 800d95e: 600a str r2, [r1, #0]
  30657. xNextTaskUnblockTime = portMAX_DELAY;
  30658. 800d960: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
  30659. xSchedulerRunning = pdTRUE;
  30660. 800d964: 4909 ldr r1, [pc, #36] @ (800d98c <vTaskStartScheduler+0xf0>)
  30661. xNextTaskUnblockTime = portMAX_DELAY;
  30662. 800d966: 6002 str r2, [r0, #0]
  30663. xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
  30664. 800d968: 4a09 ldr r2, [pc, #36] @ (800d990 <vTaskStartScheduler+0xf4>)
  30665. xSchedulerRunning = pdTRUE;
  30666. 800d96a: 600b str r3, [r1, #0]
  30667. xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
  30668. 800d96c: 6014 str r4, [r2, #0]
  30669. }
  30670. 800d96e: b00b add sp, #44 @ 0x2c
  30671. 800d970: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
  30672. if( xPortStartScheduler() != pdFALSE )
  30673. 800d974: f001 b8a8 b.w 800eac8 <xPortStartScheduler>
  30674. 800d978: 0800d3f5 .word 0x0800d3f5
  30675. 800d97c: 08011a54 .word 0x08011a54
  30676. 800d980: 24003040 .word 0x24003040
  30677. 800d984: 24000054 .word 0x24000054
  30678. 800d988: 24002b4c .word 0x24002b4c
  30679. 800d98c: 24002b60 .word 0x24002b60
  30680. 800d990: 24002b68 .word 0x24002b68
  30681. 0800d994 <vTaskSuspendAll>:
  30682. ++uxSchedulerSuspended;
  30683. 800d994: 4a02 ldr r2, [pc, #8] @ (800d9a0 <vTaskSuspendAll+0xc>)
  30684. 800d996: 6813 ldr r3, [r2, #0]
  30685. 800d998: 3301 adds r3, #1
  30686. 800d99a: 6013 str r3, [r2, #0]
  30687. }
  30688. 800d99c: 4770 bx lr
  30689. 800d99e: bf00 nop
  30690. 800d9a0: 24002b48 .word 0x24002b48
  30691. 0800d9a4 <xTaskResumeAll>:
  30692. configASSERT( uxSchedulerSuspended );
  30693. 800d9a4: 4b06 ldr r3, [pc, #24] @ (800d9c0 <xTaskResumeAll+0x1c>)
  30694. 800d9a6: 681b ldr r3, [r3, #0]
  30695. 800d9a8: b943 cbnz r3, 800d9bc <xTaskResumeAll+0x18>
  30696. 800d9aa: f04f 0350 mov.w r3, #80 @ 0x50
  30697. 800d9ae: f383 8811 msr BASEPRI, r3
  30698. 800d9b2: f3bf 8f6f isb sy
  30699. 800d9b6: f3bf 8f4f dsb sy
  30700. 800d9ba: e7fe b.n 800d9ba <xTaskResumeAll+0x16>
  30701. 800d9bc: f7ff be10 b.w 800d5e0 <xTaskResumeAll.part.0>
  30702. 800d9c0: 24002b48 .word 0x24002b48
  30703. 0800d9c4 <xTaskGetTickCount>:
  30704. xTicks = xTickCount;
  30705. 800d9c4: 4b01 ldr r3, [pc, #4] @ (800d9cc <xTaskGetTickCount+0x8>)
  30706. 800d9c6: 6818 ldr r0, [r3, #0]
  30707. }
  30708. 800d9c8: 4770 bx lr
  30709. 800d9ca: bf00 nop
  30710. 800d9cc: 24002b68 .word 0x24002b68
  30711. 0800d9d0 <xTaskIncrementTick>:
  30712. if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
  30713. 800d9d0: 4b05 ldr r3, [pc, #20] @ (800d9e8 <xTaskIncrementTick+0x18>)
  30714. 800d9d2: 681b ldr r3, [r3, #0]
  30715. 800d9d4: b90b cbnz r3, 800d9da <xTaskIncrementTick+0xa>
  30716. 800d9d6: f7ff bd5d b.w 800d494 <xTaskIncrementTick.part.0>
  30717. ++xPendedTicks;
  30718. 800d9da: 4a04 ldr r2, [pc, #16] @ (800d9ec <xTaskIncrementTick+0x1c>)
  30719. }
  30720. 800d9dc: 2000 movs r0, #0
  30721. ++xPendedTicks;
  30722. 800d9de: 6813 ldr r3, [r2, #0]
  30723. 800d9e0: 3301 adds r3, #1
  30724. 800d9e2: 6013 str r3, [r2, #0]
  30725. }
  30726. 800d9e4: 4770 bx lr
  30727. 800d9e6: bf00 nop
  30728. 800d9e8: 24002b48 .word 0x24002b48
  30729. 800d9ec: 24002b5c .word 0x24002b5c
  30730. 0800d9f0 <vTaskSwitchContext>:
  30731. {
  30732. 800d9f0: b538 push {r3, r4, r5, lr}
  30733. if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
  30734. 800d9f2: 4b24 ldr r3, [pc, #144] @ (800da84 <vTaskSwitchContext+0x94>)
  30735. 800d9f4: 681b ldr r3, [r3, #0]
  30736. 800d9f6: b11b cbz r3, 800da00 <vTaskSwitchContext+0x10>
  30737. xYieldPending = pdTRUE;
  30738. 800d9f8: 4b23 ldr r3, [pc, #140] @ (800da88 <vTaskSwitchContext+0x98>)
  30739. 800d9fa: 2201 movs r2, #1
  30740. 800d9fc: 601a str r2, [r3, #0]
  30741. }
  30742. 800d9fe: bd38 pop {r3, r4, r5, pc}
  30743. taskCHECK_FOR_STACK_OVERFLOW();
  30744. 800da00: 4c22 ldr r4, [pc, #136] @ (800da8c <vTaskSwitchContext+0x9c>)
  30745. xYieldPending = pdFALSE;
  30746. 800da02: 4a21 ldr r2, [pc, #132] @ (800da88 <vTaskSwitchContext+0x98>)
  30747. 800da04: 6013 str r3, [r2, #0]
  30748. taskCHECK_FOR_STACK_OVERFLOW();
  30749. 800da06: 6822 ldr r2, [r4, #0]
  30750. 800da08: 6823 ldr r3, [r4, #0]
  30751. 800da0a: 6812 ldr r2, [r2, #0]
  30752. 800da0c: 6b1b ldr r3, [r3, #48] @ 0x30
  30753. 800da0e: 429a cmp r2, r3
  30754. 800da10: d92e bls.n 800da70 <vTaskSwitchContext+0x80>
  30755. taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  30756. 800da12: 4d1f ldr r5, [pc, #124] @ (800da90 <vTaskSwitchContext+0xa0>)
  30757. 800da14: 491f ldr r1, [pc, #124] @ (800da94 <vTaskSwitchContext+0xa4>)
  30758. 800da16: 682b ldr r3, [r5, #0]
  30759. 800da18: eb03 0283 add.w r2, r3, r3, lsl #2
  30760. 800da1c: 0098 lsls r0, r3, #2
  30761. 800da1e: 0092 lsls r2, r2, #2
  30762. 800da20: 588a ldr r2, [r1, r2]
  30763. 800da22: b942 cbnz r2, 800da36 <vTaskSwitchContext+0x46>
  30764. 800da24: b1db cbz r3, 800da5e <vTaskSwitchContext+0x6e>
  30765. 800da26: 3b01 subs r3, #1
  30766. 800da28: eb03 0283 add.w r2, r3, r3, lsl #2
  30767. 800da2c: 0098 lsls r0, r3, #2
  30768. 800da2e: f851 2022 ldr.w r2, [r1, r2, lsl #2]
  30769. 800da32: 2a00 cmp r2, #0
  30770. 800da34: d0f6 beq.n 800da24 <vTaskSwitchContext+0x34>
  30771. 800da36: 4418 add r0, r3
  30772. 800da38: eb01 0c80 add.w ip, r1, r0, lsl #2
  30773. 800da3c: f8dc 1004 ldr.w r1, [ip, #4]
  30774. 800da40: 4662 mov r2, ip
  30775. 800da42: 6849 ldr r1, [r1, #4]
  30776. 800da44: 3208 adds r2, #8
  30777. 800da46: 4291 cmp r1, r2
  30778. 800da48: f8cc 1004 str.w r1, [ip, #4]
  30779. 800da4c: d016 beq.n 800da7c <vTaskSwitchContext+0x8c>
  30780. 800da4e: 68c9 ldr r1, [r1, #12]
  30781. _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
  30782. 800da50: 4a11 ldr r2, [pc, #68] @ (800da98 <vTaskSwitchContext+0xa8>)
  30783. taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  30784. 800da52: 6021 str r1, [r4, #0]
  30785. 800da54: 602b str r3, [r5, #0]
  30786. _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
  30787. 800da56: 6823 ldr r3, [r4, #0]
  30788. 800da58: 3354 adds r3, #84 @ 0x54
  30789. 800da5a: 6013 str r3, [r2, #0]
  30790. }
  30791. 800da5c: bd38 pop {r3, r4, r5, pc}
  30792. 800da5e: f04f 0350 mov.w r3, #80 @ 0x50
  30793. 800da62: f383 8811 msr BASEPRI, r3
  30794. 800da66: f3bf 8f6f isb sy
  30795. 800da6a: f3bf 8f4f dsb sy
  30796. configASSERT( pxTaskBuffer != NULL );
  30797. 800da6e: e7fe b.n 800da6e <vTaskSwitchContext+0x7e>
  30798. taskCHECK_FOR_STACK_OVERFLOW();
  30799. 800da70: 6820 ldr r0, [r4, #0]
  30800. 800da72: 6821 ldr r1, [r4, #0]
  30801. 800da74: 3134 adds r1, #52 @ 0x34
  30802. 800da76: f7f2 fe03 bl 8000680 <vApplicationStackOverflowHook>
  30803. 800da7a: e7ca b.n 800da12 <vTaskSwitchContext+0x22>
  30804. taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  30805. 800da7c: 6849 ldr r1, [r1, #4]
  30806. 800da7e: f8cc 1004 str.w r1, [ip, #4]
  30807. 800da82: e7e4 b.n 800da4e <vTaskSwitchContext+0x5e>
  30808. 800da84: 24002b48 .word 0x24002b48
  30809. 800da88: 24002b58 .word 0x24002b58
  30810. 800da8c: 24003040 .word 0x24003040
  30811. 800da90: 24002b64 .word 0x24002b64
  30812. 800da94: 24002be0 .word 0x24002be0
  30813. 800da98: 24000054 .word 0x24000054
  30814. 0800da9c <vTaskPlaceOnEventList>:
  30815. configASSERT( pxEventList );
  30816. 800da9c: b1f0 cbz r0, 800dadc <vTaskPlaceOnEventList+0x40>
  30817. {
  30818. 800da9e: b570 push {r4, r5, r6, lr}
  30819. vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
  30820. 800daa0: 4d1a ldr r5, [pc, #104] @ (800db0c <vTaskPlaceOnEventList+0x70>)
  30821. 800daa2: 460c mov r4, r1
  30822. 800daa4: 6829 ldr r1, [r5, #0]
  30823. 800daa6: 3118 adds r1, #24
  30824. 800daa8: f7fe fae2 bl 800c070 <vListInsert>
  30825. const TickType_t xConstTickCount = xTickCount;
  30826. 800daac: 4b18 ldr r3, [pc, #96] @ (800db10 <vTaskPlaceOnEventList+0x74>)
  30827. 800daae: 681e ldr r6, [r3, #0]
  30828. if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
  30829. 800dab0: 6828 ldr r0, [r5, #0]
  30830. 800dab2: 3004 adds r0, #4
  30831. 800dab4: f7fe faf4 bl 800c0a0 <uxListRemove>
  30832. if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
  30833. 800dab8: 1c63 adds r3, r4, #1
  30834. 800daba: d020 beq.n 800dafe <vTaskPlaceOnEventList+0x62>
  30835. xTimeToWake = xConstTickCount + xTicksToWait;
  30836. 800dabc: 19a4 adds r4, r4, r6
  30837. listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
  30838. 800dabe: 682b ldr r3, [r5, #0]
  30839. 800dac0: 605c str r4, [r3, #4]
  30840. if( xTimeToWake < xConstTickCount )
  30841. 800dac2: d214 bcs.n 800daee <vTaskPlaceOnEventList+0x52>
  30842. vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
  30843. 800dac4: 4b13 ldr r3, [pc, #76] @ (800db14 <vTaskPlaceOnEventList+0x78>)
  30844. 800dac6: 6818 ldr r0, [r3, #0]
  30845. 800dac8: 6829 ldr r1, [r5, #0]
  30846. 800daca: 3104 adds r1, #4
  30847. 800dacc: f7fe fad0 bl 800c070 <vListInsert>
  30848. if( xTimeToWake < xNextTaskUnblockTime )
  30849. 800dad0: 4b11 ldr r3, [pc, #68] @ (800db18 <vTaskPlaceOnEventList+0x7c>)
  30850. 800dad2: 681a ldr r2, [r3, #0]
  30851. 800dad4: 4294 cmp r4, r2
  30852. 800dad6: d200 bcs.n 800dada <vTaskPlaceOnEventList+0x3e>
  30853. xNextTaskUnblockTime = xTimeToWake;
  30854. 800dad8: 601c str r4, [r3, #0]
  30855. }
  30856. 800dada: bd70 pop {r4, r5, r6, pc}
  30857. 800dadc: f04f 0350 mov.w r3, #80 @ 0x50
  30858. 800dae0: f383 8811 msr BASEPRI, r3
  30859. 800dae4: f3bf 8f6f isb sy
  30860. 800dae8: f3bf 8f4f dsb sy
  30861. configASSERT( pxEventList );
  30862. 800daec: e7fe b.n 800daec <vTaskPlaceOnEventList+0x50>
  30863. vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
  30864. 800daee: 4b0b ldr r3, [pc, #44] @ (800db1c <vTaskPlaceOnEventList+0x80>)
  30865. 800daf0: 6818 ldr r0, [r3, #0]
  30866. 800daf2: 6829 ldr r1, [r5, #0]
  30867. }
  30868. 800daf4: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  30869. vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
  30870. 800daf8: 3104 adds r1, #4
  30871. 800dafa: f7fe bab9 b.w 800c070 <vListInsert>
  30872. vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
  30873. 800dafe: 6829 ldr r1, [r5, #0]
  30874. 800db00: 4807 ldr r0, [pc, #28] @ (800db20 <vTaskPlaceOnEventList+0x84>)
  30875. 800db02: 3104 adds r1, #4
  30876. }
  30877. 800db04: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  30878. vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
  30879. 800db08: f7fe baa4 b.w 800c054 <vListInsertEnd>
  30880. 800db0c: 24003040 .word 0x24003040
  30881. 800db10: 24002b68 .word 0x24002b68
  30882. 800db14: 24002bb4 .word 0x24002bb4
  30883. 800db18: 24002b4c .word 0x24002b4c
  30884. 800db1c: 24002bb0 .word 0x24002bb0
  30885. 800db20: 24002b70 .word 0x24002b70
  30886. 0800db24 <vTaskPlaceOnEventListRestricted>:
  30887. configASSERT( pxEventList );
  30888. 800db24: b358 cbz r0, 800db7e <vTaskPlaceOnEventListRestricted+0x5a>
  30889. {
  30890. 800db26: b570 push {r4, r5, r6, lr}
  30891. vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
  30892. 800db28: 4e1d ldr r6, [pc, #116] @ (800dba0 <vTaskPlaceOnEventListRestricted+0x7c>)
  30893. 800db2a: 460c mov r4, r1
  30894. 800db2c: 4615 mov r5, r2
  30895. 800db2e: 6831 ldr r1, [r6, #0]
  30896. 800db30: 3118 adds r1, #24
  30897. 800db32: f7fe fa8f bl 800c054 <vListInsertEnd>
  30898. if( xWaitIndefinitely != pdFALSE )
  30899. 800db36: b165 cbz r5, 800db52 <vTaskPlaceOnEventListRestricted+0x2e>
  30900. const TickType_t xConstTickCount = xTickCount;
  30901. 800db38: 4b1a ldr r3, [pc, #104] @ (800dba4 <vTaskPlaceOnEventListRestricted+0x80>)
  30902. 800db3a: 681b ldr r3, [r3, #0]
  30903. if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
  30904. 800db3c: 6830 ldr r0, [r6, #0]
  30905. 800db3e: 3004 adds r0, #4
  30906. 800db40: f7fe faae bl 800c0a0 <uxListRemove>
  30907. vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
  30908. 800db44: 6831 ldr r1, [r6, #0]
  30909. 800db46: 4818 ldr r0, [pc, #96] @ (800dba8 <vTaskPlaceOnEventListRestricted+0x84>)
  30910. 800db48: 3104 adds r1, #4
  30911. }
  30912. 800db4a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  30913. vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
  30914. 800db4e: f7fe ba81 b.w 800c054 <vListInsertEnd>
  30915. const TickType_t xConstTickCount = xTickCount;
  30916. 800db52: 4b14 ldr r3, [pc, #80] @ (800dba4 <vTaskPlaceOnEventListRestricted+0x80>)
  30917. 800db54: 681d ldr r5, [r3, #0]
  30918. if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
  30919. 800db56: 6830 ldr r0, [r6, #0]
  30920. 800db58: 3004 adds r0, #4
  30921. 800db5a: f7fe faa1 bl 800c0a0 <uxListRemove>
  30922. xTimeToWake = xConstTickCount + xTicksToWait;
  30923. 800db5e: 1964 adds r4, r4, r5
  30924. listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
  30925. 800db60: 6833 ldr r3, [r6, #0]
  30926. 800db62: 605c str r4, [r3, #4]
  30927. if( xTimeToWake < xConstTickCount )
  30928. 800db64: d214 bcs.n 800db90 <vTaskPlaceOnEventListRestricted+0x6c>
  30929. vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
  30930. 800db66: 4b11 ldr r3, [pc, #68] @ (800dbac <vTaskPlaceOnEventListRestricted+0x88>)
  30931. 800db68: 6818 ldr r0, [r3, #0]
  30932. 800db6a: 6831 ldr r1, [r6, #0]
  30933. 800db6c: 3104 adds r1, #4
  30934. 800db6e: f7fe fa7f bl 800c070 <vListInsert>
  30935. if( xTimeToWake < xNextTaskUnblockTime )
  30936. 800db72: 4b0f ldr r3, [pc, #60] @ (800dbb0 <vTaskPlaceOnEventListRestricted+0x8c>)
  30937. 800db74: 681a ldr r2, [r3, #0]
  30938. 800db76: 4294 cmp r4, r2
  30939. 800db78: d200 bcs.n 800db7c <vTaskPlaceOnEventListRestricted+0x58>
  30940. xNextTaskUnblockTime = xTimeToWake;
  30941. 800db7a: 601c str r4, [r3, #0]
  30942. }
  30943. 800db7c: bd70 pop {r4, r5, r6, pc}
  30944. 800db7e: f04f 0350 mov.w r3, #80 @ 0x50
  30945. 800db82: f383 8811 msr BASEPRI, r3
  30946. 800db86: f3bf 8f6f isb sy
  30947. 800db8a: f3bf 8f4f dsb sy
  30948. configASSERT( pxEventList );
  30949. 800db8e: e7fe b.n 800db8e <vTaskPlaceOnEventListRestricted+0x6a>
  30950. vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
  30951. 800db90: 4b08 ldr r3, [pc, #32] @ (800dbb4 <vTaskPlaceOnEventListRestricted+0x90>)
  30952. 800db92: 6818 ldr r0, [r3, #0]
  30953. 800db94: 6831 ldr r1, [r6, #0]
  30954. }
  30955. 800db96: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  30956. vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
  30957. 800db9a: 3104 adds r1, #4
  30958. 800db9c: f7fe ba68 b.w 800c070 <vListInsert>
  30959. 800dba0: 24003040 .word 0x24003040
  30960. 800dba4: 24002b68 .word 0x24002b68
  30961. 800dba8: 24002b70 .word 0x24002b70
  30962. 800dbac: 24002bb4 .word 0x24002bb4
  30963. 800dbb0: 24002b4c .word 0x24002b4c
  30964. 800dbb4: 24002bb0 .word 0x24002bb0
  30965. 0800dbb8 <xTaskRemoveFromEventList>:
  30966. {
  30967. 800dbb8: b538 push {r3, r4, r5, lr}
  30968. pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  30969. 800dbba: 68c3 ldr r3, [r0, #12]
  30970. 800dbbc: 68dc ldr r4, [r3, #12]
  30971. configASSERT( pxUnblockedTCB );
  30972. 800dbbe: b34c cbz r4, 800dc14 <xTaskRemoveFromEventList+0x5c>
  30973. ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
  30974. 800dbc0: f104 0518 add.w r5, r4, #24
  30975. 800dbc4: 4628 mov r0, r5
  30976. 800dbc6: f7fe fa6b bl 800c0a0 <uxListRemove>
  30977. if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
  30978. 800dbca: 4b18 ldr r3, [pc, #96] @ (800dc2c <xTaskRemoveFromEventList+0x74>)
  30979. 800dbcc: 681b ldr r3, [r3, #0]
  30980. 800dbce: b173 cbz r3, 800dbee <xTaskRemoveFromEventList+0x36>
  30981. vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
  30982. 800dbd0: 4629 mov r1, r5
  30983. 800dbd2: 4817 ldr r0, [pc, #92] @ (800dc30 <xTaskRemoveFromEventList+0x78>)
  30984. 800dbd4: f7fe fa3e bl 800c054 <vListInsertEnd>
  30985. if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
  30986. 800dbd8: 4b16 ldr r3, [pc, #88] @ (800dc34 <xTaskRemoveFromEventList+0x7c>)
  30987. 800dbda: 6ae2 ldr r2, [r4, #44] @ 0x2c
  30988. 800dbdc: 681b ldr r3, [r3, #0]
  30989. 800dbde: 6adb ldr r3, [r3, #44] @ 0x2c
  30990. 800dbe0: 429a cmp r2, r3
  30991. 800dbe2: d920 bls.n 800dc26 <xTaskRemoveFromEventList+0x6e>
  30992. xYieldPending = pdTRUE;
  30993. 800dbe4: 2301 movs r3, #1
  30994. 800dbe6: 4a14 ldr r2, [pc, #80] @ (800dc38 <xTaskRemoveFromEventList+0x80>)
  30995. xReturn = pdTRUE;
  30996. 800dbe8: 4618 mov r0, r3
  30997. xYieldPending = pdTRUE;
  30998. 800dbea: 6013 str r3, [r2, #0]
  30999. }
  31000. 800dbec: bd38 pop {r3, r4, r5, pc}
  31001. ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
  31002. 800dbee: 1d25 adds r5, r4, #4
  31003. 800dbf0: 4628 mov r0, r5
  31004. 800dbf2: f7fe fa55 bl 800c0a0 <uxListRemove>
  31005. prvAddTaskToReadyList( pxUnblockedTCB );
  31006. 800dbf6: 4b11 ldr r3, [pc, #68] @ (800dc3c <xTaskRemoveFromEventList+0x84>)
  31007. 800dbf8: 6ae0 ldr r0, [r4, #44] @ 0x2c
  31008. 800dbfa: 681a ldr r2, [r3, #0]
  31009. 800dbfc: 4290 cmp r0, r2
  31010. 800dbfe: d900 bls.n 800dc02 <xTaskRemoveFromEventList+0x4a>
  31011. 800dc00: 6018 str r0, [r3, #0]
  31012. 800dc02: 4b0f ldr r3, [pc, #60] @ (800dc40 <xTaskRemoveFromEventList+0x88>)
  31013. 800dc04: eb00 0080 add.w r0, r0, r0, lsl #2
  31014. 800dc08: 4629 mov r1, r5
  31015. 800dc0a: eb03 0080 add.w r0, r3, r0, lsl #2
  31016. 800dc0e: f7fe fa21 bl 800c054 <vListInsertEnd>
  31017. 800dc12: e7e1 b.n 800dbd8 <xTaskRemoveFromEventList+0x20>
  31018. 800dc14: f04f 0350 mov.w r3, #80 @ 0x50
  31019. 800dc18: f383 8811 msr BASEPRI, r3
  31020. 800dc1c: f3bf 8f6f isb sy
  31021. 800dc20: f3bf 8f4f dsb sy
  31022. configASSERT( pxUnblockedTCB );
  31023. 800dc24: e7fe b.n 800dc24 <xTaskRemoveFromEventList+0x6c>
  31024. xReturn = pdFALSE;
  31025. 800dc26: 2000 movs r0, #0
  31026. }
  31027. 800dc28: bd38 pop {r3, r4, r5, pc}
  31028. 800dc2a: bf00 nop
  31029. 800dc2c: 24002b48 .word 0x24002b48
  31030. 800dc30: 24002b9c .word 0x24002b9c
  31031. 800dc34: 24003040 .word 0x24003040
  31032. 800dc38: 24002b58 .word 0x24002b58
  31033. 800dc3c: 24002b64 .word 0x24002b64
  31034. 800dc40: 24002be0 .word 0x24002be0
  31035. 0800dc44 <vTaskSetTimeOutState>:
  31036. configASSERT( pxTimeOut );
  31037. 800dc44: b168 cbz r0, 800dc62 <vTaskSetTimeOutState+0x1e>
  31038. {
  31039. 800dc46: b510 push {r4, lr}
  31040. 800dc48: 4604 mov r4, r0
  31041. taskENTER_CRITICAL();
  31042. 800dc4a: f000 feab bl 800e9a4 <vPortEnterCritical>
  31043. pxTimeOut->xOverflowCount = xNumOfOverflows;
  31044. 800dc4e: 4a09 ldr r2, [pc, #36] @ (800dc74 <vTaskSetTimeOutState+0x30>)
  31045. pxTimeOut->xTimeOnEntering = xTickCount;
  31046. 800dc50: 4b09 ldr r3, [pc, #36] @ (800dc78 <vTaskSetTimeOutState+0x34>)
  31047. pxTimeOut->xOverflowCount = xNumOfOverflows;
  31048. 800dc52: 6812 ldr r2, [r2, #0]
  31049. pxTimeOut->xTimeOnEntering = xTickCount;
  31050. 800dc54: 681b ldr r3, [r3, #0]
  31051. 800dc56: e9c4 2300 strd r2, r3, [r4]
  31052. }
  31053. 800dc5a: e8bd 4010 ldmia.w sp!, {r4, lr}
  31054. taskEXIT_CRITICAL();
  31055. 800dc5e: f000 bec3 b.w 800e9e8 <vPortExitCritical>
  31056. 800dc62: f04f 0350 mov.w r3, #80 @ 0x50
  31057. 800dc66: f383 8811 msr BASEPRI, r3
  31058. 800dc6a: f3bf 8f6f isb sy
  31059. 800dc6e: f3bf 8f4f dsb sy
  31060. configASSERT( pxTimeOut );
  31061. 800dc72: e7fe b.n 800dc72 <vTaskSetTimeOutState+0x2e>
  31062. 800dc74: 24002b54 .word 0x24002b54
  31063. 800dc78: 24002b68 .word 0x24002b68
  31064. 0800dc7c <vTaskInternalSetTimeOutState>:
  31065. pxTimeOut->xOverflowCount = xNumOfOverflows;
  31066. 800dc7c: 4a03 ldr r2, [pc, #12] @ (800dc8c <vTaskInternalSetTimeOutState+0x10>)
  31067. pxTimeOut->xTimeOnEntering = xTickCount;
  31068. 800dc7e: 4b04 ldr r3, [pc, #16] @ (800dc90 <vTaskInternalSetTimeOutState+0x14>)
  31069. pxTimeOut->xOverflowCount = xNumOfOverflows;
  31070. 800dc80: 6812 ldr r2, [r2, #0]
  31071. pxTimeOut->xTimeOnEntering = xTickCount;
  31072. 800dc82: 681b ldr r3, [r3, #0]
  31073. 800dc84: e9c0 2300 strd r2, r3, [r0]
  31074. }
  31075. 800dc88: 4770 bx lr
  31076. 800dc8a: bf00 nop
  31077. 800dc8c: 24002b54 .word 0x24002b54
  31078. 800dc90: 24002b68 .word 0x24002b68
  31079. 0800dc94 <xTaskCheckForTimeOut>:
  31080. {
  31081. 800dc94: b5f8 push {r3, r4, r5, r6, r7, lr}
  31082. configASSERT( pxTimeOut );
  31083. 800dc96: b308 cbz r0, 800dcdc <xTaskCheckForTimeOut+0x48>
  31084. configASSERT( pxTicksToWait );
  31085. 800dc98: 460d mov r5, r1
  31086. 800dc9a: b1b1 cbz r1, 800dcca <xTaskCheckForTimeOut+0x36>
  31087. 800dc9c: 4604 mov r4, r0
  31088. taskENTER_CRITICAL();
  31089. 800dc9e: f000 fe81 bl 800e9a4 <vPortEnterCritical>
  31090. if( *pxTicksToWait == portMAX_DELAY )
  31091. 800dca2: 682b ldr r3, [r5, #0]
  31092. const TickType_t xConstTickCount = xTickCount;
  31093. 800dca4: 4a1a ldr r2, [pc, #104] @ (800dd10 <xTaskCheckForTimeOut+0x7c>)
  31094. if( *pxTicksToWait == portMAX_DELAY )
  31095. 800dca6: 1c58 adds r0, r3, #1
  31096. const TickType_t xConstTickCount = xTickCount;
  31097. 800dca8: 6811 ldr r1, [r2, #0]
  31098. if( *pxTicksToWait == portMAX_DELAY )
  31099. 800dcaa: d02c beq.n 800dd06 <xTaskCheckForTimeOut+0x72>
  31100. if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
  31101. 800dcac: f8df c064 ldr.w ip, [pc, #100] @ 800dd14 <xTaskCheckForTimeOut+0x80>
  31102. 800dcb0: 6826 ldr r6, [r4, #0]
  31103. 800dcb2: f8dc 7000 ldr.w r7, [ip]
  31104. const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
  31105. 800dcb6: 6860 ldr r0, [r4, #4]
  31106. if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
  31107. 800dcb8: 42be cmp r6, r7
  31108. 800dcba: d018 beq.n 800dcee <xTaskCheckForTimeOut+0x5a>
  31109. 800dcbc: 4288 cmp r0, r1
  31110. 800dcbe: d816 bhi.n 800dcee <xTaskCheckForTimeOut+0x5a>
  31111. xReturn = pdTRUE;
  31112. 800dcc0: 2401 movs r4, #1
  31113. taskEXIT_CRITICAL();
  31114. 800dcc2: f000 fe91 bl 800e9e8 <vPortExitCritical>
  31115. }
  31116. 800dcc6: 4620 mov r0, r4
  31117. 800dcc8: bdf8 pop {r3, r4, r5, r6, r7, pc}
  31118. 800dcca: f04f 0350 mov.w r3, #80 @ 0x50
  31119. 800dcce: f383 8811 msr BASEPRI, r3
  31120. 800dcd2: f3bf 8f6f isb sy
  31121. 800dcd6: f3bf 8f4f dsb sy
  31122. configASSERT( pxTicksToWait );
  31123. 800dcda: e7fe b.n 800dcda <xTaskCheckForTimeOut+0x46>
  31124. 800dcdc: f04f 0350 mov.w r3, #80 @ 0x50
  31125. 800dce0: f383 8811 msr BASEPRI, r3
  31126. 800dce4: f3bf 8f6f isb sy
  31127. 800dce8: f3bf 8f4f dsb sy
  31128. configASSERT( pxTimeOut );
  31129. 800dcec: e7fe b.n 800dcec <xTaskCheckForTimeOut+0x58>
  31130. const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
  31131. 800dcee: eba1 0e00 sub.w lr, r1, r0
  31132. else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
  31133. 800dcf2: 4573 cmp r3, lr
  31134. 800dcf4: d909 bls.n 800dd0a <xTaskCheckForTimeOut+0x76>
  31135. *pxTicksToWait -= xElapsedTime;
  31136. 800dcf6: 1a5b subs r3, r3, r1
  31137. pxTimeOut->xOverflowCount = xNumOfOverflows;
  31138. 800dcf8: f8dc 1000 ldr.w r1, [ip]
  31139. pxTimeOut->xTimeOnEntering = xTickCount;
  31140. 800dcfc: 6812 ldr r2, [r2, #0]
  31141. *pxTicksToWait -= xElapsedTime;
  31142. 800dcfe: 4403 add r3, r0
  31143. 800dd00: 602b str r3, [r5, #0]
  31144. pxTimeOut->xTimeOnEntering = xTickCount;
  31145. 800dd02: e9c4 1200 strd r1, r2, [r4]
  31146. xReturn = pdFALSE;
  31147. 800dd06: 2400 movs r4, #0
  31148. 800dd08: e7db b.n 800dcc2 <xTaskCheckForTimeOut+0x2e>
  31149. *pxTicksToWait = 0;
  31150. 800dd0a: 2300 movs r3, #0
  31151. 800dd0c: 602b str r3, [r5, #0]
  31152. xReturn = pdTRUE;
  31153. 800dd0e: e7d7 b.n 800dcc0 <xTaskCheckForTimeOut+0x2c>
  31154. 800dd10: 24002b68 .word 0x24002b68
  31155. 800dd14: 24002b54 .word 0x24002b54
  31156. 0800dd18 <vTaskMissedYield>:
  31157. xYieldPending = pdTRUE;
  31158. 800dd18: 4b01 ldr r3, [pc, #4] @ (800dd20 <vTaskMissedYield+0x8>)
  31159. 800dd1a: 2201 movs r2, #1
  31160. 800dd1c: 601a str r2, [r3, #0]
  31161. }
  31162. 800dd1e: 4770 bx lr
  31163. 800dd20: 24002b58 .word 0x24002b58
  31164. 0800dd24 <xTaskGetCurrentTaskHandle>:
  31165. xReturn = pxCurrentTCB;
  31166. 800dd24: 4b01 ldr r3, [pc, #4] @ (800dd2c <xTaskGetCurrentTaskHandle+0x8>)
  31167. 800dd26: 6818 ldr r0, [r3, #0]
  31168. }
  31169. 800dd28: 4770 bx lr
  31170. 800dd2a: bf00 nop
  31171. 800dd2c: 24003040 .word 0x24003040
  31172. 0800dd30 <xTaskGetSchedulerState>:
  31173. if( xSchedulerRunning == pdFALSE )
  31174. 800dd30: 4b05 ldr r3, [pc, #20] @ (800dd48 <xTaskGetSchedulerState+0x18>)
  31175. 800dd32: 681b ldr r3, [r3, #0]
  31176. 800dd34: b133 cbz r3, 800dd44 <xTaskGetSchedulerState+0x14>
  31177. if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
  31178. 800dd36: 4b05 ldr r3, [pc, #20] @ (800dd4c <xTaskGetSchedulerState+0x1c>)
  31179. 800dd38: 6818 ldr r0, [r3, #0]
  31180. 800dd3a: fab0 f080 clz r0, r0
  31181. 800dd3e: 0940 lsrs r0, r0, #5
  31182. 800dd40: 0040 lsls r0, r0, #1
  31183. 800dd42: 4770 bx lr
  31184. xReturn = taskSCHEDULER_NOT_STARTED;
  31185. 800dd44: 2001 movs r0, #1
  31186. }
  31187. 800dd46: 4770 bx lr
  31188. 800dd48: 24002b60 .word 0x24002b60
  31189. 800dd4c: 24002b48 .word 0x24002b48
  31190. 0800dd50 <xTaskPriorityInherit>:
  31191. {
  31192. 800dd50: b5f8 push {r3, r4, r5, r6, r7, lr}
  31193. if( pxMutexHolder != NULL )
  31194. 800dd52: 4604 mov r4, r0
  31195. 800dd54: b1c8 cbz r0, 800dd8a <xTaskPriorityInherit+0x3a>
  31196. if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
  31197. 800dd56: 4d1b ldr r5, [pc, #108] @ (800ddc4 <xTaskPriorityInherit+0x74>)
  31198. 800dd58: 6ac3 ldr r3, [r0, #44] @ 0x2c
  31199. 800dd5a: 682a ldr r2, [r5, #0]
  31200. 800dd5c: 6ad2 ldr r2, [r2, #44] @ 0x2c
  31201. 800dd5e: 4293 cmp r3, r2
  31202. 800dd60: d214 bcs.n 800dd8c <xTaskPriorityInherit+0x3c>
  31203. if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
  31204. 800dd62: 6982 ldr r2, [r0, #24]
  31205. 800dd64: 2a00 cmp r2, #0
  31206. 800dd66: db04 blt.n 800dd72 <xTaskPriorityInherit+0x22>
  31207. listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
  31208. 800dd68: 682a ldr r2, [r5, #0]
  31209. 800dd6a: 6ad2 ldr r2, [r2, #44] @ 0x2c
  31210. 800dd6c: f1c2 0238 rsb r2, r2, #56 @ 0x38
  31211. 800dd70: 6182 str r2, [r0, #24]
  31212. if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
  31213. 800dd72: eb03 0383 add.w r3, r3, r3, lsl #2
  31214. 800dd76: 4e14 ldr r6, [pc, #80] @ (800ddc8 <xTaskPriorityInherit+0x78>)
  31215. 800dd78: 6962 ldr r2, [r4, #20]
  31216. 800dd7a: eb06 0383 add.w r3, r6, r3, lsl #2
  31217. 800dd7e: 429a cmp r2, r3
  31218. 800dd80: d00c beq.n 800dd9c <xTaskPriorityInherit+0x4c>
  31219. pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
  31220. 800dd82: 682b ldr r3, [r5, #0]
  31221. 800dd84: 6adb ldr r3, [r3, #44] @ 0x2c
  31222. 800dd86: 62e3 str r3, [r4, #44] @ 0x2c
  31223. xReturn = pdTRUE;
  31224. 800dd88: 2001 movs r0, #1
  31225. }
  31226. 800dd8a: bdf8 pop {r3, r4, r5, r6, r7, pc}
  31227. if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
  31228. 800dd8c: 682b ldr r3, [r5, #0]
  31229. 800dd8e: 6cc0 ldr r0, [r0, #76] @ 0x4c
  31230. 800dd90: 6adb ldr r3, [r3, #44] @ 0x2c
  31231. 800dd92: 4298 cmp r0, r3
  31232. 800dd94: bf2c ite cs
  31233. 800dd96: 2000 movcs r0, #0
  31234. 800dd98: 2001 movcc r0, #1
  31235. }
  31236. 800dd9a: bdf8 pop {r3, r4, r5, r6, r7, pc}
  31237. if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
  31238. 800dd9c: 1d27 adds r7, r4, #4
  31239. 800dd9e: 4638 mov r0, r7
  31240. 800dda0: f7fe f97e bl 800c0a0 <uxListRemove>
  31241. pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
  31242. 800dda4: 682a ldr r2, [r5, #0]
  31243. prvAddTaskToReadyList( pxMutexHolderTCB );
  31244. 800dda6: 4b09 ldr r3, [pc, #36] @ (800ddcc <xTaskPriorityInherit+0x7c>)
  31245. pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
  31246. 800dda8: 6ad0 ldr r0, [r2, #44] @ 0x2c
  31247. prvAddTaskToReadyList( pxMutexHolderTCB );
  31248. 800ddaa: 681a ldr r2, [r3, #0]
  31249. pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
  31250. 800ddac: 62e0 str r0, [r4, #44] @ 0x2c
  31251. prvAddTaskToReadyList( pxMutexHolderTCB );
  31252. 800ddae: 4290 cmp r0, r2
  31253. 800ddb0: d900 bls.n 800ddb4 <xTaskPriorityInherit+0x64>
  31254. 800ddb2: 6018 str r0, [r3, #0]
  31255. 800ddb4: eb00 0080 add.w r0, r0, r0, lsl #2
  31256. 800ddb8: 4639 mov r1, r7
  31257. 800ddba: eb06 0080 add.w r0, r6, r0, lsl #2
  31258. 800ddbe: f7fe f949 bl 800c054 <vListInsertEnd>
  31259. 800ddc2: e7e1 b.n 800dd88 <xTaskPriorityInherit+0x38>
  31260. 800ddc4: 24003040 .word 0x24003040
  31261. 800ddc8: 24002be0 .word 0x24002be0
  31262. 800ddcc: 24002b64 .word 0x24002b64
  31263. 0800ddd0 <xTaskPriorityDisinherit>:
  31264. if( pxMutexHolder != NULL )
  31265. 800ddd0: b308 cbz r0, 800de16 <xTaskPriorityDisinherit+0x46>
  31266. {
  31267. 800ddd2: b538 push {r3, r4, r5, lr}
  31268. configASSERT( pxTCB == pxCurrentTCB );
  31269. 800ddd4: 4b1d ldr r3, [pc, #116] @ (800de4c <xTaskPriorityDisinherit+0x7c>)
  31270. 800ddd6: 681c ldr r4, [r3, #0]
  31271. 800ddd8: 4284 cmp r4, r0
  31272. 800ddda: d008 beq.n 800ddee <xTaskPriorityDisinherit+0x1e>
  31273. 800dddc: f04f 0350 mov.w r3, #80 @ 0x50
  31274. 800dde0: f383 8811 msr BASEPRI, r3
  31275. 800dde4: f3bf 8f6f isb sy
  31276. 800dde8: f3bf 8f4f dsb sy
  31277. 800ddec: e7fe b.n 800ddec <xTaskPriorityDisinherit+0x1c>
  31278. configASSERT( pxTCB->uxMutexesHeld );
  31279. 800ddee: 6d23 ldr r3, [r4, #80] @ 0x50
  31280. 800ddf0: b143 cbz r3, 800de04 <xTaskPriorityDisinherit+0x34>
  31281. if( pxTCB->uxPriority != pxTCB->uxBasePriority )
  31282. 800ddf2: 6ae1 ldr r1, [r4, #44] @ 0x2c
  31283. ( pxTCB->uxMutexesHeld )--;
  31284. 800ddf4: 3b01 subs r3, #1
  31285. if( pxTCB->uxPriority != pxTCB->uxBasePriority )
  31286. 800ddf6: 6ce2 ldr r2, [r4, #76] @ 0x4c
  31287. ( pxTCB->uxMutexesHeld )--;
  31288. 800ddf8: 6523 str r3, [r4, #80] @ 0x50
  31289. if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
  31290. 800ddfa: 4291 cmp r1, r2
  31291. 800ddfc: d000 beq.n 800de00 <xTaskPriorityDisinherit+0x30>
  31292. 800ddfe: b163 cbz r3, 800de1a <xTaskPriorityDisinherit+0x4a>
  31293. BaseType_t xReturn = pdFALSE;
  31294. 800de00: 2000 movs r0, #0
  31295. }
  31296. 800de02: bd38 pop {r3, r4, r5, pc}
  31297. 800de04: f04f 0350 mov.w r3, #80 @ 0x50
  31298. 800de08: f383 8811 msr BASEPRI, r3
  31299. 800de0c: f3bf 8f6f isb sy
  31300. 800de10: f3bf 8f4f dsb sy
  31301. configASSERT( pxTCB->uxMutexesHeld );
  31302. 800de14: e7fe b.n 800de14 <xTaskPriorityDisinherit+0x44>
  31303. BaseType_t xReturn = pdFALSE;
  31304. 800de16: 2000 movs r0, #0
  31305. }
  31306. 800de18: 4770 bx lr
  31307. if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
  31308. 800de1a: 1d25 adds r5, r4, #4
  31309. 800de1c: 4628 mov r0, r5
  31310. 800de1e: f7fe f93f bl 800c0a0 <uxListRemove>
  31311. pxTCB->uxPriority = pxTCB->uxBasePriority;
  31312. 800de22: 6ce0 ldr r0, [r4, #76] @ 0x4c
  31313. prvAddTaskToReadyList( pxTCB );
  31314. 800de24: 4b0a ldr r3, [pc, #40] @ (800de50 <xTaskPriorityDisinherit+0x80>)
  31315. listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
  31316. 800de26: f1c0 0238 rsb r2, r0, #56 @ 0x38
  31317. pxTCB->uxPriority = pxTCB->uxBasePriority;
  31318. 800de2a: 62e0 str r0, [r4, #44] @ 0x2c
  31319. listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
  31320. 800de2c: 61a2 str r2, [r4, #24]
  31321. prvAddTaskToReadyList( pxTCB );
  31322. 800de2e: 681a ldr r2, [r3, #0]
  31323. 800de30: 4290 cmp r0, r2
  31324. 800de32: d900 bls.n 800de36 <xTaskPriorityDisinherit+0x66>
  31325. 800de34: 6018 str r0, [r3, #0]
  31326. 800de36: 4b07 ldr r3, [pc, #28] @ (800de54 <xTaskPriorityDisinherit+0x84>)
  31327. 800de38: eb00 0080 add.w r0, r0, r0, lsl #2
  31328. 800de3c: 4629 mov r1, r5
  31329. 800de3e: eb03 0080 add.w r0, r3, r0, lsl #2
  31330. 800de42: f7fe f907 bl 800c054 <vListInsertEnd>
  31331. xReturn = pdTRUE;
  31332. 800de46: 2001 movs r0, #1
  31333. }
  31334. 800de48: bd38 pop {r3, r4, r5, pc}
  31335. 800de4a: bf00 nop
  31336. 800de4c: 24003040 .word 0x24003040
  31337. 800de50: 24002b64 .word 0x24002b64
  31338. 800de54: 24002be0 .word 0x24002be0
  31339. 0800de58 <vTaskPriorityDisinheritAfterTimeout>:
  31340. if( pxMutexHolder != NULL )
  31341. 800de58: 2800 cmp r0, #0
  31342. 800de5a: d03c beq.n 800ded6 <vTaskPriorityDisinheritAfterTimeout+0x7e>
  31343. configASSERT( pxTCB->uxMutexesHeld );
  31344. 800de5c: 6d03 ldr r3, [r0, #80] @ 0x50
  31345. {
  31346. 800de5e: b570 push {r4, r5, r6, lr}
  31347. 800de60: 4604 mov r4, r0
  31348. configASSERT( pxTCB->uxMutexesHeld );
  31349. 800de62: b14b cbz r3, 800de78 <vTaskPriorityDisinheritAfterTimeout+0x20>
  31350. if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
  31351. 800de64: 6cc0 ldr r0, [r0, #76] @ 0x4c
  31352. if( pxTCB->uxPriority != uxPriorityToUse )
  31353. 800de66: 6ae2 ldr r2, [r4, #44] @ 0x2c
  31354. 800de68: 4281 cmp r1, r0
  31355. 800de6a: bf38 it cc
  31356. 800de6c: 4601 movcc r1, r0
  31357. if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
  31358. 800de6e: 2b01 cmp r3, #1
  31359. 800de70: d101 bne.n 800de76 <vTaskPriorityDisinheritAfterTimeout+0x1e>
  31360. 800de72: 428a cmp r2, r1
  31361. 800de74: d109 bne.n 800de8a <vTaskPriorityDisinheritAfterTimeout+0x32>
  31362. }
  31363. 800de76: bd70 pop {r4, r5, r6, pc}
  31364. 800de78: f04f 0350 mov.w r3, #80 @ 0x50
  31365. 800de7c: f383 8811 msr BASEPRI, r3
  31366. 800de80: f3bf 8f6f isb sy
  31367. 800de84: f3bf 8f4f dsb sy
  31368. configASSERT( pxTCB->uxMutexesHeld );
  31369. 800de88: e7fe b.n 800de88 <vTaskPriorityDisinheritAfterTimeout+0x30>
  31370. configASSERT( pxTCB != pxCurrentTCB );
  31371. 800de8a: 4b18 ldr r3, [pc, #96] @ (800deec <vTaskPriorityDisinheritAfterTimeout+0x94>)
  31372. 800de8c: 681b ldr r3, [r3, #0]
  31373. 800de8e: 42a3 cmp r3, r4
  31374. 800de90: d022 beq.n 800ded8 <vTaskPriorityDisinheritAfterTimeout+0x80>
  31375. if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
  31376. 800de92: 69a3 ldr r3, [r4, #24]
  31377. pxTCB->uxPriority = uxPriorityToUse;
  31378. 800de94: 62e1 str r1, [r4, #44] @ 0x2c
  31379. if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
  31380. 800de96: 2b00 cmp r3, #0
  31381. 800de98: db02 blt.n 800dea0 <vTaskPriorityDisinheritAfterTimeout+0x48>
  31382. listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
  31383. 800de9a: f1c1 0138 rsb r1, r1, #56 @ 0x38
  31384. 800de9e: 61a1 str r1, [r4, #24]
  31385. if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
  31386. 800dea0: eb02 0282 add.w r2, r2, r2, lsl #2
  31387. 800dea4: 4d12 ldr r5, [pc, #72] @ (800def0 <vTaskPriorityDisinheritAfterTimeout+0x98>)
  31388. 800dea6: 6961 ldr r1, [r4, #20]
  31389. 800dea8: eb05 0382 add.w r3, r5, r2, lsl #2
  31390. 800deac: 4299 cmp r1, r3
  31391. 800deae: d1e2 bne.n 800de76 <vTaskPriorityDisinheritAfterTimeout+0x1e>
  31392. if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
  31393. 800deb0: 1d26 adds r6, r4, #4
  31394. 800deb2: 4630 mov r0, r6
  31395. 800deb4: f7fe f8f4 bl 800c0a0 <uxListRemove>
  31396. prvAddTaskToReadyList( pxTCB );
  31397. 800deb8: 4b0e ldr r3, [pc, #56] @ (800def4 <vTaskPriorityDisinheritAfterTimeout+0x9c>)
  31398. 800deba: 6ae0 ldr r0, [r4, #44] @ 0x2c
  31399. 800debc: 681a ldr r2, [r3, #0]
  31400. 800debe: 4290 cmp r0, r2
  31401. 800dec0: d900 bls.n 800dec4 <vTaskPriorityDisinheritAfterTimeout+0x6c>
  31402. 800dec2: 6018 str r0, [r3, #0]
  31403. 800dec4: eb00 0080 add.w r0, r0, r0, lsl #2
  31404. 800dec8: 4631 mov r1, r6
  31405. 800deca: eb05 0080 add.w r0, r5, r0, lsl #2
  31406. }
  31407. 800dece: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  31408. prvAddTaskToReadyList( pxTCB );
  31409. 800ded2: f7fe b8bf b.w 800c054 <vListInsertEnd>
  31410. 800ded6: 4770 bx lr
  31411. 800ded8: f04f 0350 mov.w r3, #80 @ 0x50
  31412. 800dedc: f383 8811 msr BASEPRI, r3
  31413. 800dee0: f3bf 8f6f isb sy
  31414. 800dee4: f3bf 8f4f dsb sy
  31415. configASSERT( pxTCB != pxCurrentTCB );
  31416. 800dee8: e7fe b.n 800dee8 <vTaskPriorityDisinheritAfterTimeout+0x90>
  31417. 800deea: bf00 nop
  31418. 800deec: 24003040 .word 0x24003040
  31419. 800def0: 24002be0 .word 0x24002be0
  31420. 800def4: 24002b64 .word 0x24002b64
  31421. 0800def8 <pvTaskIncrementMutexHeldCount>:
  31422. if( pxCurrentTCB != NULL )
  31423. 800def8: 4b04 ldr r3, [pc, #16] @ (800df0c <pvTaskIncrementMutexHeldCount+0x14>)
  31424. 800defa: 681a ldr r2, [r3, #0]
  31425. 800defc: b11a cbz r2, 800df06 <pvTaskIncrementMutexHeldCount+0xe>
  31426. ( pxCurrentTCB->uxMutexesHeld )++;
  31427. 800defe: 6819 ldr r1, [r3, #0]
  31428. 800df00: 6d0a ldr r2, [r1, #80] @ 0x50
  31429. 800df02: 3201 adds r2, #1
  31430. 800df04: 650a str r2, [r1, #80] @ 0x50
  31431. return pxCurrentTCB;
  31432. 800df06: 6818 ldr r0, [r3, #0]
  31433. }
  31434. 800df08: 4770 bx lr
  31435. 800df0a: bf00 nop
  31436. 800df0c: 24003040 .word 0x24003040
  31437. 0800df10 <xTaskNotifyWait>:
  31438. {
  31439. 800df10: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  31440. if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
  31441. 800df14: 4c33 ldr r4, [pc, #204] @ (800dfe4 <xTaskNotifyWait+0xd4>)
  31442. {
  31443. 800df16: 461d mov r5, r3
  31444. 800df18: 4606 mov r6, r0
  31445. 800df1a: 4688 mov r8, r1
  31446. 800df1c: 4617 mov r7, r2
  31447. taskENTER_CRITICAL();
  31448. 800df1e: f000 fd41 bl 800e9a4 <vPortEnterCritical>
  31449. if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
  31450. 800df22: 6823 ldr r3, [r4, #0]
  31451. 800df24: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4
  31452. 800df28: 2b02 cmp r3, #2
  31453. 800df2a: d00b beq.n 800df44 <xTaskNotifyWait+0x34>
  31454. pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
  31455. 800df2c: 6822 ldr r2, [r4, #0]
  31456. pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
  31457. 800df2e: 2101 movs r1, #1
  31458. pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
  31459. 800df30: f8d2 30a0 ldr.w r3, [r2, #160] @ 0xa0
  31460. 800df34: ea23 0306 bic.w r3, r3, r6
  31461. 800df38: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0
  31462. pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
  31463. 800df3c: 6823 ldr r3, [r4, #0]
  31464. 800df3e: f883 10a4 strb.w r1, [r3, #164] @ 0xa4
  31465. if( xTicksToWait > ( TickType_t ) 0 )
  31466. 800df42: b9bd cbnz r5, 800df74 <xTaskNotifyWait+0x64>
  31467. taskEXIT_CRITICAL();
  31468. 800df44: f000 fd50 bl 800e9e8 <vPortExitCritical>
  31469. taskENTER_CRITICAL();
  31470. 800df48: f000 fd2c bl 800e9a4 <vPortEnterCritical>
  31471. if( pulNotificationValue != NULL )
  31472. 800df4c: b11f cbz r7, 800df56 <xTaskNotifyWait+0x46>
  31473. *pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
  31474. 800df4e: 6823 ldr r3, [r4, #0]
  31475. 800df50: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0
  31476. 800df54: 603b str r3, [r7, #0]
  31477. if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
  31478. 800df56: 6823 ldr r3, [r4, #0]
  31479. 800df58: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4
  31480. 800df5c: 2b02 cmp r3, #2
  31481. 800df5e: d026 beq.n 800dfae <xTaskNotifyWait+0x9e>
  31482. xReturn = pdFALSE;
  31483. 800df60: 2500 movs r5, #0
  31484. pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
  31485. 800df62: 6823 ldr r3, [r4, #0]
  31486. 800df64: 2200 movs r2, #0
  31487. 800df66: f883 20a4 strb.w r2, [r3, #164] @ 0xa4
  31488. taskEXIT_CRITICAL();
  31489. 800df6a: f000 fd3d bl 800e9e8 <vPortExitCritical>
  31490. }
  31491. 800df6e: 4628 mov r0, r5
  31492. 800df70: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  31493. const TickType_t xConstTickCount = xTickCount;
  31494. 800df74: 4b1c ldr r3, [pc, #112] @ (800dfe8 <xTaskNotifyWait+0xd8>)
  31495. 800df76: 681e ldr r6, [r3, #0]
  31496. if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
  31497. 800df78: 6820 ldr r0, [r4, #0]
  31498. 800df7a: 3004 adds r0, #4
  31499. 800df7c: f7fe f890 bl 800c0a0 <uxListRemove>
  31500. if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
  31501. 800df80: 1c6b adds r3, r5, #1
  31502. 800df82: d01d beq.n 800dfc0 <xTaskNotifyWait+0xb0>
  31503. xTimeToWake = xConstTickCount + xTicksToWait;
  31504. 800df84: 19ad adds r5, r5, r6
  31505. listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
  31506. 800df86: 6823 ldr r3, [r4, #0]
  31507. 800df88: 605d str r5, [r3, #4]
  31508. if( xTimeToWake < xConstTickCount )
  31509. 800df8a: d31f bcc.n 800dfcc <xTaskNotifyWait+0xbc>
  31510. vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
  31511. 800df8c: 4b17 ldr r3, [pc, #92] @ (800dfec <xTaskNotifyWait+0xdc>)
  31512. 800df8e: 6818 ldr r0, [r3, #0]
  31513. 800df90: 6821 ldr r1, [r4, #0]
  31514. 800df92: 3104 adds r1, #4
  31515. 800df94: f7fe f86c bl 800c070 <vListInsert>
  31516. portYIELD_WITHIN_API();
  31517. 800df98: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  31518. 800df9c: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  31519. 800dfa0: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  31520. 800dfa4: f3bf 8f4f dsb sy
  31521. 800dfa8: f3bf 8f6f isb sy
  31522. 800dfac: e7ca b.n 800df44 <xTaskNotifyWait+0x34>
  31523. pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
  31524. 800dfae: 6822 ldr r2, [r4, #0]
  31525. xReturn = pdTRUE;
  31526. 800dfb0: 2501 movs r5, #1
  31527. pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
  31528. 800dfb2: f8d2 30a0 ldr.w r3, [r2, #160] @ 0xa0
  31529. 800dfb6: ea23 0308 bic.w r3, r3, r8
  31530. 800dfba: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0
  31531. xReturn = pdTRUE;
  31532. 800dfbe: e7d0 b.n 800df62 <xTaskNotifyWait+0x52>
  31533. vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
  31534. 800dfc0: 6821 ldr r1, [r4, #0]
  31535. 800dfc2: 480b ldr r0, [pc, #44] @ (800dff0 <xTaskNotifyWait+0xe0>)
  31536. 800dfc4: 3104 adds r1, #4
  31537. 800dfc6: f7fe f845 bl 800c054 <vListInsertEnd>
  31538. /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
  31539. ( void ) xCanBlockIndefinitely;
  31540. }
  31541. #endif /* INCLUDE_vTaskSuspend */
  31542. }
  31543. 800dfca: e7e5 b.n 800df98 <xTaskNotifyWait+0x88>
  31544. vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
  31545. 800dfcc: 4b09 ldr r3, [pc, #36] @ (800dff4 <xTaskNotifyWait+0xe4>)
  31546. 800dfce: 6818 ldr r0, [r3, #0]
  31547. 800dfd0: 6821 ldr r1, [r4, #0]
  31548. 800dfd2: 3104 adds r1, #4
  31549. 800dfd4: f7fe f84c bl 800c070 <vListInsert>
  31550. if( xTimeToWake < xNextTaskUnblockTime )
  31551. 800dfd8: 4b07 ldr r3, [pc, #28] @ (800dff8 <xTaskNotifyWait+0xe8>)
  31552. 800dfda: 681a ldr r2, [r3, #0]
  31553. 800dfdc: 4295 cmp r5, r2
  31554. 800dfde: d2db bcs.n 800df98 <xTaskNotifyWait+0x88>
  31555. xNextTaskUnblockTime = xTimeToWake;
  31556. 800dfe0: 601d str r5, [r3, #0]
  31557. 800dfe2: e7d9 b.n 800df98 <xTaskNotifyWait+0x88>
  31558. 800dfe4: 24003040 .word 0x24003040
  31559. 800dfe8: 24002b68 .word 0x24002b68
  31560. 800dfec: 24002bb0 .word 0x24002bb0
  31561. 800dff0: 24002b70 .word 0x24002b70
  31562. 800dff4: 24002bb4 .word 0x24002bb4
  31563. 800dff8: 24002b4c .word 0x24002b4c
  31564. 0800dffc <xTaskGenericNotify>:
  31565. {
  31566. 800dffc: b5f8 push {r3, r4, r5, r6, r7, lr}
  31567. configASSERT( xTaskToNotify );
  31568. 800dffe: b308 cbz r0, 800e044 <xTaskGenericNotify+0x48>
  31569. pxTCB = xTaskToNotify;
  31570. 800e000: 461e mov r6, r3
  31571. 800e002: 460f mov r7, r1
  31572. 800e004: 4604 mov r4, r0
  31573. taskENTER_CRITICAL();
  31574. 800e006: 4615 mov r5, r2
  31575. 800e008: f000 fccc bl 800e9a4 <vPortEnterCritical>
  31576. if( pulPreviousNotificationValue != NULL )
  31577. 800e00c: b116 cbz r6, 800e014 <xTaskGenericNotify+0x18>
  31578. *pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
  31579. 800e00e: f8d4 30a0 ldr.w r3, [r4, #160] @ 0xa0
  31580. 800e012: 6033 str r3, [r6, #0]
  31581. ucOriginalNotifyState = pxTCB->ucNotifyState;
  31582. 800e014: f894 30a4 ldrb.w r3, [r4, #164] @ 0xa4
  31583. pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
  31584. 800e018: 2202 movs r2, #2
  31585. ucOriginalNotifyState = pxTCB->ucNotifyState;
  31586. 800e01a: b2db uxtb r3, r3
  31587. pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
  31588. 800e01c: f884 20a4 strb.w r2, [r4, #164] @ 0xa4
  31589. switch( eAction )
  31590. 800e020: 2d04 cmp r5, #4
  31591. 800e022: d855 bhi.n 800e0d0 <xTaskGenericNotify+0xd4>
  31592. 800e024: e8df f005 tbb [pc, r5]
  31593. 800e028: 051d1707 .word 0x051d1707
  31594. 800e02c: 03 .byte 0x03
  31595. 800e02d: 00 .byte 0x00
  31596. if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
  31597. 800e02e: 2b02 cmp r3, #2
  31598. 800e030: d03b beq.n 800e0aa <xTaskGenericNotify+0xae>
  31599. pxTCB->ulNotifiedValue = ulValue;
  31600. 800e032: f8c4 70a0 str.w r7, [r4, #160] @ 0xa0
  31601. if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
  31602. 800e036: 2b01 cmp r3, #1
  31603. 800e038: d019 beq.n 800e06e <xTaskGenericNotify+0x72>
  31604. {
  31605. 800e03a: 2401 movs r4, #1
  31606. taskEXIT_CRITICAL();
  31607. 800e03c: f000 fcd4 bl 800e9e8 <vPortExitCritical>
  31608. }
  31609. 800e040: 4620 mov r0, r4
  31610. 800e042: bdf8 pop {r3, r4, r5, r6, r7, pc}
  31611. 800e044: f04f 0350 mov.w r3, #80 @ 0x50
  31612. 800e048: f383 8811 msr BASEPRI, r3
  31613. 800e04c: f3bf 8f6f isb sy
  31614. 800e050: f3bf 8f4f dsb sy
  31615. configASSERT( xTaskToNotify );
  31616. 800e054: e7fe b.n 800e054 <xTaskGenericNotify+0x58>
  31617. pxTCB->ulNotifiedValue |= ulValue;
  31618. 800e056: f8d4 20a0 ldr.w r2, [r4, #160] @ 0xa0
  31619. 800e05a: 433a orrs r2, r7
  31620. 800e05c: f8c4 20a0 str.w r2, [r4, #160] @ 0xa0
  31621. break;
  31622. 800e060: e7e9 b.n 800e036 <xTaskGenericNotify+0x3a>
  31623. ( pxTCB->ulNotifiedValue )++;
  31624. 800e062: f8d4 20a0 ldr.w r2, [r4, #160] @ 0xa0
  31625. 800e066: 3201 adds r2, #1
  31626. 800e068: f8c4 20a0 str.w r2, [r4, #160] @ 0xa0
  31627. break;
  31628. 800e06c: e7e3 b.n 800e036 <xTaskGenericNotify+0x3a>
  31629. ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
  31630. 800e06e: 1d25 adds r5, r4, #4
  31631. 800e070: 4628 mov r0, r5
  31632. 800e072: f7fe f815 bl 800c0a0 <uxListRemove>
  31633. prvAddTaskToReadyList( pxTCB );
  31634. 800e076: 4b1d ldr r3, [pc, #116] @ (800e0ec <xTaskGenericNotify+0xf0>)
  31635. 800e078: 6ae0 ldr r0, [r4, #44] @ 0x2c
  31636. 800e07a: 681a ldr r2, [r3, #0]
  31637. 800e07c: 4290 cmp r0, r2
  31638. 800e07e: d812 bhi.n 800e0a6 <xTaskGenericNotify+0xaa>
  31639. 800e080: 4b1b ldr r3, [pc, #108] @ (800e0f0 <xTaskGenericNotify+0xf4>)
  31640. 800e082: eb00 0080 add.w r0, r0, r0, lsl #2
  31641. 800e086: 4629 mov r1, r5
  31642. 800e088: eb03 0080 add.w r0, r3, r0, lsl #2
  31643. 800e08c: f7fd ffe2 bl 800c054 <vListInsertEnd>
  31644. configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
  31645. 800e090: 6aa3 ldr r3, [r4, #40] @ 0x28
  31646. 800e092: b163 cbz r3, 800e0ae <xTaskGenericNotify+0xb2>
  31647. 800e094: f04f 0350 mov.w r3, #80 @ 0x50
  31648. 800e098: f383 8811 msr BASEPRI, r3
  31649. 800e09c: f3bf 8f6f isb sy
  31650. 800e0a0: f3bf 8f4f dsb sy
  31651. 800e0a4: e7fe b.n 800e0a4 <xTaskGenericNotify+0xa8>
  31652. prvAddTaskToReadyList( pxTCB );
  31653. 800e0a6: 6018 str r0, [r3, #0]
  31654. 800e0a8: e7ea b.n 800e080 <xTaskGenericNotify+0x84>
  31655. xReturn = pdFAIL;
  31656. 800e0aa: 2400 movs r4, #0
  31657. 800e0ac: e7c6 b.n 800e03c <xTaskGenericNotify+0x40>
  31658. if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
  31659. 800e0ae: 4b11 ldr r3, [pc, #68] @ (800e0f4 <xTaskGenericNotify+0xf8>)
  31660. 800e0b0: 6ae2 ldr r2, [r4, #44] @ 0x2c
  31661. 800e0b2: 681b ldr r3, [r3, #0]
  31662. 800e0b4: 6adb ldr r3, [r3, #44] @ 0x2c
  31663. 800e0b6: 429a cmp r2, r3
  31664. 800e0b8: d9bf bls.n 800e03a <xTaskGenericNotify+0x3e>
  31665. taskYIELD_IF_USING_PREEMPTION();
  31666. 800e0ba: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  31667. 800e0be: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  31668. 800e0c2: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  31669. 800e0c6: f3bf 8f4f dsb sy
  31670. 800e0ca: f3bf 8f6f isb sy
  31671. 800e0ce: e7b4 b.n 800e03a <xTaskGenericNotify+0x3e>
  31672. configASSERT( pxTCB->ulNotifiedValue == ~0UL );
  31673. 800e0d0: f8d4 20a0 ldr.w r2, [r4, #160] @ 0xa0
  31674. 800e0d4: 3201 adds r2, #1
  31675. 800e0d6: d0ae beq.n 800e036 <xTaskGenericNotify+0x3a>
  31676. 800e0d8: f04f 0350 mov.w r3, #80 @ 0x50
  31677. 800e0dc: f383 8811 msr BASEPRI, r3
  31678. 800e0e0: f3bf 8f6f isb sy
  31679. 800e0e4: f3bf 8f4f dsb sy
  31680. 800e0e8: e7fe b.n 800e0e8 <xTaskGenericNotify+0xec>
  31681. 800e0ea: bf00 nop
  31682. 800e0ec: 24002b64 .word 0x24002b64
  31683. 800e0f0: 24002be0 .word 0x24002be0
  31684. 800e0f4: 24003040 .word 0x24003040
  31685. 0800e0f8 <xTaskGenericNotifyFromISR>:
  31686. configASSERT( xTaskToNotify );
  31687. 800e0f8: b368 cbz r0, 800e156 <xTaskGenericNotifyFromISR+0x5e>
  31688. {
  31689. 800e0fa: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  31690. 800e0fe: 460f mov r7, r1
  31691. 800e100: 4616 mov r6, r2
  31692. 800e102: 461d mov r5, r3
  31693. 800e104: 4604 mov r4, r0
  31694. portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
  31695. 800e106: f000 fd7f bl 800ec08 <vPortValidateInterruptPriority>
  31696. __asm volatile
  31697. 800e10a: f3ef 8811 mrs r8, BASEPRI
  31698. 800e10e: f04f 0350 mov.w r3, #80 @ 0x50
  31699. 800e112: f383 8811 msr BASEPRI, r3
  31700. 800e116: f3bf 8f6f isb sy
  31701. 800e11a: f3bf 8f4f dsb sy
  31702. if( pulPreviousNotificationValue != NULL )
  31703. 800e11e: b115 cbz r5, 800e126 <xTaskGenericNotifyFromISR+0x2e>
  31704. *pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
  31705. 800e120: f8d4 30a0 ldr.w r3, [r4, #160] @ 0xa0
  31706. 800e124: 602b str r3, [r5, #0]
  31707. ucOriginalNotifyState = pxTCB->ucNotifyState;
  31708. 800e126: f894 30a4 ldrb.w r3, [r4, #164] @ 0xa4
  31709. pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
  31710. 800e12a: 2202 movs r2, #2
  31711. ucOriginalNotifyState = pxTCB->ucNotifyState;
  31712. 800e12c: b2db uxtb r3, r3
  31713. pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
  31714. 800e12e: f884 20a4 strb.w r2, [r4, #164] @ 0xa4
  31715. switch( eAction )
  31716. 800e132: 2e04 cmp r6, #4
  31717. 800e134: d85b bhi.n 800e1ee <xTaskGenericNotifyFromISR+0xf6>
  31718. 800e136: e8df f006 tbb [pc, r6]
  31719. 800e13a: 1707 .short 0x1707
  31720. 800e13c: 051d .short 0x051d
  31721. 800e13e: 03 .byte 0x03
  31722. 800e13f: 00 .byte 0x00
  31723. if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
  31724. 800e140: 2b02 cmp r3, #2
  31725. 800e142: d028 beq.n 800e196 <xTaskGenericNotifyFromISR+0x9e>
  31726. pxTCB->ulNotifiedValue = ulValue;
  31727. 800e144: f8c4 70a0 str.w r7, [r4, #160] @ 0xa0
  31728. if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
  31729. 800e148: 2b01 cmp r3, #1
  31730. 800e14a: d019 beq.n 800e180 <xTaskGenericNotifyFromISR+0x88>
  31731. {
  31732. 800e14c: 2001 movs r0, #1
  31733. __asm volatile
  31734. 800e14e: f388 8811 msr BASEPRI, r8
  31735. }
  31736. 800e152: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  31737. __asm volatile
  31738. 800e156: f04f 0350 mov.w r3, #80 @ 0x50
  31739. 800e15a: f383 8811 msr BASEPRI, r3
  31740. 800e15e: f3bf 8f6f isb sy
  31741. 800e162: f3bf 8f4f dsb sy
  31742. configASSERT( xTaskToNotify );
  31743. 800e166: e7fe b.n 800e166 <xTaskGenericNotifyFromISR+0x6e>
  31744. pxTCB->ulNotifiedValue |= ulValue;
  31745. 800e168: f8d4 20a0 ldr.w r2, [r4, #160] @ 0xa0
  31746. 800e16c: 433a orrs r2, r7
  31747. 800e16e: f8c4 20a0 str.w r2, [r4, #160] @ 0xa0
  31748. break;
  31749. 800e172: e7e9 b.n 800e148 <xTaskGenericNotifyFromISR+0x50>
  31750. ( pxTCB->ulNotifiedValue )++;
  31751. 800e174: f8d4 20a0 ldr.w r2, [r4, #160] @ 0xa0
  31752. 800e178: 3201 adds r2, #1
  31753. 800e17a: f8c4 20a0 str.w r2, [r4, #160] @ 0xa0
  31754. break;
  31755. 800e17e: e7e3 b.n 800e148 <xTaskGenericNotifyFromISR+0x50>
  31756. configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
  31757. 800e180: 6aa3 ldr r3, [r4, #40] @ 0x28
  31758. 800e182: b153 cbz r3, 800e19a <xTaskGenericNotifyFromISR+0xa2>
  31759. 800e184: f04f 0350 mov.w r3, #80 @ 0x50
  31760. 800e188: f383 8811 msr BASEPRI, r3
  31761. 800e18c: f3bf 8f6f isb sy
  31762. 800e190: f3bf 8f4f dsb sy
  31763. 800e194: e7fe b.n 800e194 <xTaskGenericNotifyFromISR+0x9c>
  31764. xReturn = pdFAIL;
  31765. 800e196: 2000 movs r0, #0
  31766. 800e198: e7d9 b.n 800e14e <xTaskGenericNotifyFromISR+0x56>
  31767. if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
  31768. 800e19a: 4b1b ldr r3, [pc, #108] @ (800e208 <xTaskGenericNotifyFromISR+0x110>)
  31769. 800e19c: 681b ldr r3, [r3, #0]
  31770. 800e19e: bb03 cbnz r3, 800e1e2 <xTaskGenericNotifyFromISR+0xea>
  31771. ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
  31772. 800e1a0: 1d25 adds r5, r4, #4
  31773. 800e1a2: 4628 mov r0, r5
  31774. 800e1a4: f7fd ff7c bl 800c0a0 <uxListRemove>
  31775. prvAddTaskToReadyList( pxTCB );
  31776. 800e1a8: 4b18 ldr r3, [pc, #96] @ (800e20c <xTaskGenericNotifyFromISR+0x114>)
  31777. 800e1aa: 6ae0 ldr r0, [r4, #44] @ 0x2c
  31778. 800e1ac: 681a ldr r2, [r3, #0]
  31779. 800e1ae: 4290 cmp r0, r2
  31780. 800e1b0: d900 bls.n 800e1b4 <xTaskGenericNotifyFromISR+0xbc>
  31781. 800e1b2: 6018 str r0, [r3, #0]
  31782. 800e1b4: eb00 0080 add.w r0, r0, r0, lsl #2
  31783. 800e1b8: 4b15 ldr r3, [pc, #84] @ (800e210 <xTaskGenericNotifyFromISR+0x118>)
  31784. 800e1ba: 4629 mov r1, r5
  31785. 800e1bc: eb03 0080 add.w r0, r3, r0, lsl #2
  31786. 800e1c0: f7fd ff48 bl 800c054 <vListInsertEnd>
  31787. if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
  31788. 800e1c4: 4b13 ldr r3, [pc, #76] @ (800e214 <xTaskGenericNotifyFromISR+0x11c>)
  31789. 800e1c6: 6ae2 ldr r2, [r4, #44] @ 0x2c
  31790. 800e1c8: 681b ldr r3, [r3, #0]
  31791. 800e1ca: 6adb ldr r3, [r3, #44] @ 0x2c
  31792. 800e1cc: 429a cmp r2, r3
  31793. 800e1ce: d9bd bls.n 800e14c <xTaskGenericNotifyFromISR+0x54>
  31794. if( pxHigherPriorityTaskWoken != NULL )
  31795. 800e1d0: 9b06 ldr r3, [sp, #24]
  31796. 800e1d2: b113 cbz r3, 800e1da <xTaskGenericNotifyFromISR+0xe2>
  31797. 800e1d4: 461a mov r2, r3
  31798. *pxHigherPriorityTaskWoken = pdTRUE;
  31799. 800e1d6: 2301 movs r3, #1
  31800. 800e1d8: 6013 str r3, [r2, #0]
  31801. xYieldPending = pdTRUE;
  31802. 800e1da: 4b0f ldr r3, [pc, #60] @ (800e218 <xTaskGenericNotifyFromISR+0x120>)
  31803. 800e1dc: 2201 movs r2, #1
  31804. 800e1de: 601a str r2, [r3, #0]
  31805. 800e1e0: e7b4 b.n 800e14c <xTaskGenericNotifyFromISR+0x54>
  31806. vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
  31807. 800e1e2: f104 0118 add.w r1, r4, #24
  31808. 800e1e6: 480d ldr r0, [pc, #52] @ (800e21c <xTaskGenericNotifyFromISR+0x124>)
  31809. 800e1e8: f7fd ff34 bl 800c054 <vListInsertEnd>
  31810. 800e1ec: e7ea b.n 800e1c4 <xTaskGenericNotifyFromISR+0xcc>
  31811. configASSERT( pxTCB->ulNotifiedValue == ~0UL );
  31812. 800e1ee: f8d4 20a0 ldr.w r2, [r4, #160] @ 0xa0
  31813. 800e1f2: 3201 adds r2, #1
  31814. 800e1f4: d0a8 beq.n 800e148 <xTaskGenericNotifyFromISR+0x50>
  31815. 800e1f6: f04f 0350 mov.w r3, #80 @ 0x50
  31816. 800e1fa: f383 8811 msr BASEPRI, r3
  31817. 800e1fe: f3bf 8f6f isb sy
  31818. 800e202: f3bf 8f4f dsb sy
  31819. 800e206: e7fe b.n 800e206 <xTaskGenericNotifyFromISR+0x10e>
  31820. 800e208: 24002b48 .word 0x24002b48
  31821. 800e20c: 24002b64 .word 0x24002b64
  31822. 800e210: 24002be0 .word 0x24002be0
  31823. 800e214: 24003040 .word 0x24003040
  31824. 800e218: 24002b58 .word 0x24002b58
  31825. 800e21c: 24002b9c .word 0x24002b9c
  31826. 0800e220 <xTaskNotifyStateClear>:
  31827. {
  31828. 800e220: b538 push {r3, r4, r5, lr}
  31829. pxTCB = prvGetTCBFromHandle( xTask );
  31830. 800e222: b198 cbz r0, 800e24c <xTaskNotifyStateClear+0x2c>
  31831. 800e224: 4604 mov r4, r0
  31832. taskENTER_CRITICAL();
  31833. 800e226: f000 fbbd bl 800e9a4 <vPortEnterCritical>
  31834. if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
  31835. 800e22a: f894 30a4 ldrb.w r3, [r4, #164] @ 0xa4
  31836. 800e22e: 2b02 cmp r3, #2
  31837. 800e230: d004 beq.n 800e23c <xTaskNotifyStateClear+0x1c>
  31838. xReturn = pdFAIL;
  31839. 800e232: 2500 movs r5, #0
  31840. taskEXIT_CRITICAL();
  31841. 800e234: f000 fbd8 bl 800e9e8 <vPortExitCritical>
  31842. }
  31843. 800e238: 4628 mov r0, r5
  31844. 800e23a: bd38 pop {r3, r4, r5, pc}
  31845. pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
  31846. 800e23c: 2300 movs r3, #0
  31847. xReturn = pdPASS;
  31848. 800e23e: 2501 movs r5, #1
  31849. pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
  31850. 800e240: f884 30a4 strb.w r3, [r4, #164] @ 0xa4
  31851. taskEXIT_CRITICAL();
  31852. 800e244: f000 fbd0 bl 800e9e8 <vPortExitCritical>
  31853. }
  31854. 800e248: 4628 mov r0, r5
  31855. 800e24a: bd38 pop {r3, r4, r5, pc}
  31856. pxTCB = prvGetTCBFromHandle( xTask );
  31857. 800e24c: 4b01 ldr r3, [pc, #4] @ (800e254 <xTaskNotifyStateClear+0x34>)
  31858. 800e24e: 681c ldr r4, [r3, #0]
  31859. 800e250: e7e9 b.n 800e226 <xTaskNotifyStateClear+0x6>
  31860. 800e252: bf00 nop
  31861. 800e254: 24003040 .word 0x24003040
  31862. 0800e258 <prvSwitchTimerLists>:
  31863. }
  31864. }
  31865. /*-----------------------------------------------------------*/
  31866. static void prvSwitchTimerLists( void )
  31867. {
  31868. 800e258: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  31869. 800e25c: 4e21 ldr r6, [pc, #132] @ (800e2e4 <prvSwitchTimerLists+0x8c>)
  31870. 800e25e: b084 sub sp, #16
  31871. /* The tick count has overflowed. The timer lists must be switched.
  31872. If there are any timers still referenced from the current timer list
  31873. then they must have expired and should be processed before the lists
  31874. are switched. */
  31875. while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
  31876. 800e260: e00d b.n 800e27e <prvSwitchTimerLists+0x26>
  31877. {
  31878. xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
  31879. 800e262: 68db ldr r3, [r3, #12]
  31880. /* Remove the timer from the list. */
  31881. pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  31882. 800e264: 68dc ldr r4, [r3, #12]
  31883. xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
  31884. 800e266: 681f ldr r7, [r3, #0]
  31885. ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
  31886. 800e268: 1d25 adds r5, r4, #4
  31887. 800e26a: 4628 mov r0, r5
  31888. 800e26c: f7fd ff18 bl 800c0a0 <uxListRemove>
  31889. traceTIMER_EXPIRED( pxTimer );
  31890. /* Execute its callback, then send a command to restart the timer if
  31891. it is an auto-reload timer. It cannot be restarted here as the lists
  31892. have not yet been switched. */
  31893. pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
  31894. 800e270: 6a23 ldr r3, [r4, #32]
  31895. 800e272: 4620 mov r0, r4
  31896. 800e274: 4798 blx r3
  31897. if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
  31898. 800e276: f894 3028 ldrb.w r3, [r4, #40] @ 0x28
  31899. 800e27a: 075b lsls r3, r3, #29
  31900. 800e27c: d40a bmi.n 800e294 <prvSwitchTimerLists+0x3c>
  31901. while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
  31902. 800e27e: 6833 ldr r3, [r6, #0]
  31903. 800e280: 681a ldr r2, [r3, #0]
  31904. 800e282: 2a00 cmp r2, #0
  31905. 800e284: d1ed bne.n 800e262 <prvSwitchTimerLists+0xa>
  31906. mtCOVERAGE_TEST_MARKER();
  31907. }
  31908. }
  31909. pxTemp = pxCurrentTimerList;
  31910. pxCurrentTimerList = pxOverflowTimerList;
  31911. 800e286: 4a18 ldr r2, [pc, #96] @ (800e2e8 <prvSwitchTimerLists+0x90>)
  31912. 800e288: 6811 ldr r1, [r2, #0]
  31913. pxOverflowTimerList = pxTemp;
  31914. 800e28a: 6013 str r3, [r2, #0]
  31915. pxCurrentTimerList = pxOverflowTimerList;
  31916. 800e28c: 6031 str r1, [r6, #0]
  31917. }
  31918. 800e28e: b004 add sp, #16
  31919. 800e290: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  31920. xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
  31921. 800e294: 69a3 ldr r3, [r4, #24]
  31922. vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
  31923. 800e296: 4629 mov r1, r5
  31924. if( xTimerQueue != NULL )
  31925. 800e298: f8df 8050 ldr.w r8, [pc, #80] @ 800e2ec <prvSwitchTimerLists+0x94>
  31926. xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
  31927. 800e29c: 443b add r3, r7
  31928. if( xReloadTime > xNextExpireTime )
  31929. 800e29e: 429f cmp r7, r3
  31930. 800e2a0: d205 bcs.n 800e2ae <prvSwitchTimerLists+0x56>
  31931. vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
  31932. 800e2a2: 6830 ldr r0, [r6, #0]
  31933. listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
  31934. 800e2a4: 6063 str r3, [r4, #4]
  31935. listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
  31936. 800e2a6: 6124 str r4, [r4, #16]
  31937. vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
  31938. 800e2a8: f7fd fee2 bl 800c070 <vListInsert>
  31939. 800e2ac: e7e7 b.n 800e27e <prvSwitchTimerLists+0x26>
  31940. if( xTimerQueue != NULL )
  31941. 800e2ae: f8d8 3000 ldr.w r3, [r8]
  31942. xMessage.xMessageID = xCommandID;
  31943. 800e2b2: 2500 movs r5, #0
  31944. if( xTimerQueue != NULL )
  31945. 800e2b4: b16b cbz r3, 800e2d2 <prvSwitchTimerLists+0x7a>
  31946. xMessage.u.xTimerParameters.pxTimer = xTimer;
  31947. 800e2b6: 9402 str r4, [sp, #8]
  31948. xMessage.xMessageID = xCommandID;
  31949. 800e2b8: e9cd 5700 strd r5, r7, [sp]
  31950. if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
  31951. 800e2bc: f7ff fd38 bl 800dd30 <xTaskGetSchedulerState>
  31952. xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
  31953. 800e2c0: 462b mov r3, r5
  31954. 800e2c2: 462a mov r2, r5
  31955. 800e2c4: 4669 mov r1, sp
  31956. 800e2c6: f8d8 0000 ldr.w r0, [r8]
  31957. 800e2ca: f7fd ffe3 bl 800c294 <xQueueGenericSend>
  31958. configASSERT( xResult );
  31959. 800e2ce: 2800 cmp r0, #0
  31960. 800e2d0: d1d5 bne.n 800e27e <prvSwitchTimerLists+0x26>
  31961. 800e2d2: f04f 0350 mov.w r3, #80 @ 0x50
  31962. 800e2d6: f383 8811 msr BASEPRI, r3
  31963. 800e2da: f3bf 8f6f isb sy
  31964. 800e2de: f3bf 8f4f dsb sy
  31965. 800e2e2: e7fe b.n 800e2e2 <prvSwitchTimerLists+0x8a>
  31966. 800e2e4: 24003144 .word 0x24003144
  31967. 800e2e8: 24003140 .word 0x24003140
  31968. 800e2ec: 2400313c .word 0x2400313c
  31969. 0800e2f0 <prvTimerTask>:
  31970. {
  31971. 800e2f0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  31972. 800e2f4: 4e9f ldr r6, [pc, #636] @ (800e574 <prvTimerTask+0x284>)
  31973. 800e2f6: b089 sub sp, #36 @ 0x24
  31974. 800e2f8: 4d9f ldr r5, [pc, #636] @ (800e578 <prvTimerTask+0x288>)
  31975. portYIELD_WITHIN_API();
  31976. 800e2fa: f04f 29e0 mov.w r9, #3758153728 @ 0xe000e000
  31977. 800e2fe: 4c9f ldr r4, [pc, #636] @ (800e57c <prvTimerTask+0x28c>)
  31978. *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
  31979. 800e300: 6833 ldr r3, [r6, #0]
  31980. 800e302: 681f ldr r7, [r3, #0]
  31981. 800e304: 2f00 cmp r7, #0
  31982. 800e306: f000 80b2 beq.w 800e46e <prvTimerTask+0x17e>
  31983. xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
  31984. 800e30a: 68db ldr r3, [r3, #12]
  31985. 800e30c: 681f ldr r7, [r3, #0]
  31986. vTaskSuspendAll();
  31987. 800e30e: f7ff fb41 bl 800d994 <vTaskSuspendAll>
  31988. xTimeNow = xTaskGetTickCount();
  31989. 800e312: f7ff fb57 bl 800d9c4 <xTaskGetTickCount>
  31990. if( xTimeNow < xLastTime )
  31991. 800e316: 682b ldr r3, [r5, #0]
  31992. xTimeNow = xTaskGetTickCount();
  31993. 800e318: 4682 mov sl, r0
  31994. if( xTimeNow < xLastTime )
  31995. 800e31a: 4298 cmp r0, r3
  31996. 800e31c: f0c0 80af bcc.w 800e47e <prvTimerTask+0x18e>
  31997. if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
  31998. 800e320: 4287 cmp r7, r0
  31999. xLastTime = xTimeNow;
  32000. 800e322: 6028 str r0, [r5, #0]
  32001. if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
  32002. 800e324: f200 80d0 bhi.w 800e4c8 <prvTimerTask+0x1d8>
  32003. ( void ) xTaskResumeAll();
  32004. 800e328: f7ff fb3c bl 800d9a4 <xTaskResumeAll>
  32005. Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
  32006. 800e32c: 6833 ldr r3, [r6, #0]
  32007. 800e32e: 68db ldr r3, [r3, #12]
  32008. 800e330: f8d3 b00c ldr.w fp, [r3, #12]
  32009. ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
  32010. 800e334: f10b 0804 add.w r8, fp, #4
  32011. 800e338: 4640 mov r0, r8
  32012. 800e33a: f7fd feb1 bl 800c0a0 <uxListRemove>
  32013. if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
  32014. 800e33e: f89b 3028 ldrb.w r3, [fp, #40] @ 0x28
  32015. 800e342: 0758 lsls r0, r3, #29
  32016. 800e344: f100 80d0 bmi.w 800e4e8 <prvTimerTask+0x1f8>
  32017. pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
  32018. 800e348: f023 0301 bic.w r3, r3, #1
  32019. 800e34c: f88b 3028 strb.w r3, [fp, #40] @ 0x28
  32020. pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
  32021. 800e350: f8db 3020 ldr.w r3, [fp, #32]
  32022. 800e354: 4658 mov r0, fp
  32023. 800e356: 4798 blx r3
  32024. while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
  32025. 800e358: 2200 movs r2, #0
  32026. 800e35a: 4669 mov r1, sp
  32027. 800e35c: 6820 ldr r0, [r4, #0]
  32028. 800e35e: f7fe fa29 bl 800c7b4 <xQueueReceive>
  32029. 800e362: 2800 cmp r0, #0
  32030. 800e364: d0cc beq.n 800e300 <prvTimerTask+0x10>
  32031. if( xMessage.xMessageID < ( BaseType_t ) 0 )
  32032. 800e366: 9b00 ldr r3, [sp, #0]
  32033. pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
  32034. 800e368: 9802 ldr r0, [sp, #8]
  32035. if( xMessage.xMessageID < ( BaseType_t ) 0 )
  32036. 800e36a: 2b00 cmp r3, #0
  32037. 800e36c: db77 blt.n 800e45e <prvTimerTask+0x16e>
  32038. pxTimer = xMessage.u.xTimerParameters.pxTimer;
  32039. 800e36e: 9f02 ldr r7, [sp, #8]
  32040. if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
  32041. 800e370: 697b ldr r3, [r7, #20]
  32042. 800e372: b113 cbz r3, 800e37a <prvTimerTask+0x8a>
  32043. ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
  32044. 800e374: 1d38 adds r0, r7, #4
  32045. 800e376: f7fd fe93 bl 800c0a0 <uxListRemove>
  32046. xTimeNow = xTaskGetTickCount();
  32047. 800e37a: f7ff fb23 bl 800d9c4 <xTaskGetTickCount>
  32048. if( xTimeNow < xLastTime )
  32049. 800e37e: 682b ldr r3, [r5, #0]
  32050. xTimeNow = xTaskGetTickCount();
  32051. 800e380: 4683 mov fp, r0
  32052. if( xTimeNow < xLastTime )
  32053. 800e382: 4298 cmp r0, r3
  32054. 800e384: f0c0 8082 bcc.w 800e48c <prvTimerTask+0x19c>
  32055. switch( xMessage.xMessageID )
  32056. 800e388: 9b00 ldr r3, [sp, #0]
  32057. xLastTime = xTimeNow;
  32058. 800e38a: f8c5 b000 str.w fp, [r5]
  32059. switch( xMessage.xMessageID )
  32060. 800e38e: 2b09 cmp r3, #9
  32061. 800e390: d8e2 bhi.n 800e358 <prvTimerTask+0x68>
  32062. 800e392: e8df f003 tbb [pc, r3]
  32063. 800e396: 0505 .short 0x0505
  32064. 800e398: 5b3e5405 .word 0x5b3e5405
  32065. 800e39c: 3e540505 .word 0x3e540505
  32066. pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
  32067. 800e3a0: f897 2028 ldrb.w r2, [r7, #40] @ 0x28
  32068. if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
  32069. 800e3a4: 9b01 ldr r3, [sp, #4]
  32070. pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
  32071. 800e3a6: f042 0201 orr.w r2, r2, #1
  32072. listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
  32073. 800e3aa: 613f str r7, [r7, #16]
  32074. pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
  32075. 800e3ac: f887 2028 strb.w r2, [r7, #40] @ 0x28
  32076. if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
  32077. 800e3b0: 69ba ldr r2, [r7, #24]
  32078. 800e3b2: 1899 adds r1, r3, r2
  32079. 800e3b4: bf2c ite cs
  32080. 800e3b6: 2001 movcs r0, #1
  32081. 800e3b8: 2000 movcc r0, #0
  32082. if( xNextExpiryTime <= xTimeNow )
  32083. 800e3ba: 4559 cmp r1, fp
  32084. listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
  32085. 800e3bc: 6079 str r1, [r7, #4]
  32086. if( xNextExpiryTime <= xTimeNow )
  32087. 800e3be: f200 8085 bhi.w 800e4cc <prvTimerTask+0x1dc>
  32088. if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
  32089. 800e3c2: ebab 0303 sub.w r3, fp, r3
  32090. 800e3c6: 429a cmp r2, r3
  32091. 800e3c8: f200 80be bhi.w 800e548 <prvTimerTask+0x258>
  32092. pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
  32093. 800e3cc: 6a3b ldr r3, [r7, #32]
  32094. 800e3ce: 4638 mov r0, r7
  32095. 800e3d0: 4798 blx r3
  32096. if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
  32097. 800e3d2: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
  32098. 800e3d6: 0759 lsls r1, r3, #29
  32099. 800e3d8: d5be bpl.n 800e358 <prvTimerTask+0x68>
  32100. if( xTimerQueue != NULL )
  32101. 800e3da: 6821 ldr r1, [r4, #0]
  32102. xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
  32103. 800e3dc: 9b01 ldr r3, [sp, #4]
  32104. 800e3de: 69ba ldr r2, [r7, #24]
  32105. if( xTimerQueue != NULL )
  32106. 800e3e0: b171 cbz r1, 800e400 <prvTimerTask+0x110>
  32107. xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
  32108. 800e3e2: 4413 add r3, r2
  32109. xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
  32110. 800e3e4: e9cd 3705 strd r3, r7, [sp, #20]
  32111. xMessage.xMessageID = xCommandID;
  32112. 800e3e8: 2700 movs r7, #0
  32113. 800e3ea: 9704 str r7, [sp, #16]
  32114. if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
  32115. 800e3ec: f7ff fca0 bl 800dd30 <xTaskGetSchedulerState>
  32116. xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
  32117. 800e3f0: 463b mov r3, r7
  32118. 800e3f2: 463a mov r2, r7
  32119. 800e3f4: a904 add r1, sp, #16
  32120. 800e3f6: 6820 ldr r0, [r4, #0]
  32121. 800e3f8: f7fd ff4c bl 800c294 <xQueueGenericSend>
  32122. configASSERT( xResult );
  32123. 800e3fc: 2800 cmp r0, #0
  32124. 800e3fe: d1ab bne.n 800e358 <prvTimerTask+0x68>
  32125. 800e400: f04f 0350 mov.w r3, #80 @ 0x50
  32126. 800e404: f383 8811 msr BASEPRI, r3
  32127. 800e408: f3bf 8f6f isb sy
  32128. 800e40c: f3bf 8f4f dsb sy
  32129. 800e410: e7fe b.n 800e410 <prvTimerTask+0x120>
  32130. pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
  32131. 800e412: f897 2028 ldrb.w r2, [r7, #40] @ 0x28
  32132. pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
  32133. 800e416: 9b01 ldr r3, [sp, #4]
  32134. pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
  32135. 800e418: f042 0201 orr.w r2, r2, #1
  32136. pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
  32137. 800e41c: 61bb str r3, [r7, #24]
  32138. pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
  32139. 800e41e: f887 2028 strb.w r2, [r7, #40] @ 0x28
  32140. configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
  32141. 800e422: 2b00 cmp r3, #0
  32142. 800e424: f000 809c beq.w 800e560 <prvTimerTask+0x270>
  32143. ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
  32144. 800e428: 445b add r3, fp
  32145. ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
  32146. 800e42a: 1d39 adds r1, r7, #4
  32147. listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
  32148. 800e42c: 613f str r7, [r7, #16]
  32149. if( xNextExpiryTime <= xTimeNow )
  32150. 800e42e: 455b cmp r3, fp
  32151. listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
  32152. 800e430: 607b str r3, [r7, #4]
  32153. if( xNextExpiryTime <= xTimeNow )
  32154. 800e432: d855 bhi.n 800e4e0 <prvTimerTask+0x1f0>
  32155. vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
  32156. 800e434: 4b52 ldr r3, [pc, #328] @ (800e580 <prvTimerTask+0x290>)
  32157. 800e436: 6818 ldr r0, [r3, #0]
  32158. 800e438: f7fd fe1a bl 800c070 <vListInsert>
  32159. 800e43c: e78c b.n 800e358 <prvTimerTask+0x68>
  32160. pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
  32161. 800e43e: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
  32162. 800e442: f023 0301 bic.w r3, r3, #1
  32163. 800e446: f887 3028 strb.w r3, [r7, #40] @ 0x28
  32164. break;
  32165. 800e44a: e785 b.n 800e358 <prvTimerTask+0x68>
  32166. if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
  32167. 800e44c: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
  32168. 800e450: 079a lsls r2, r3, #30
  32169. 800e452: d570 bpl.n 800e536 <prvTimerTask+0x246>
  32170. pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
  32171. 800e454: f023 0301 bic.w r3, r3, #1
  32172. 800e458: f887 3028 strb.w r3, [r7, #40] @ 0x28
  32173. 800e45c: e77c b.n 800e358 <prvTimerTask+0x68>
  32174. pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
  32175. 800e45e: 9b01 ldr r3, [sp, #4]
  32176. 800e460: 9903 ldr r1, [sp, #12]
  32177. 800e462: 4798 blx r3
  32178. if( xMessage.xMessageID >= ( BaseType_t ) 0 )
  32179. 800e464: 9b00 ldr r3, [sp, #0]
  32180. 800e466: 2b00 cmp r3, #0
  32181. 800e468: f6ff af76 blt.w 800e358 <prvTimerTask+0x68>
  32182. 800e46c: e77f b.n 800e36e <prvTimerTask+0x7e>
  32183. vTaskSuspendAll();
  32184. 800e46e: f7ff fa91 bl 800d994 <vTaskSuspendAll>
  32185. xTimeNow = xTaskGetTickCount();
  32186. 800e472: f7ff faa7 bl 800d9c4 <xTaskGetTickCount>
  32187. if( xTimeNow < xLastTime )
  32188. 800e476: 682b ldr r3, [r5, #0]
  32189. xTimeNow = xTaskGetTickCount();
  32190. 800e478: 4682 mov sl, r0
  32191. if( xTimeNow < xLastTime )
  32192. 800e47a: 4298 cmp r0, r3
  32193. 800e47c: d209 bcs.n 800e492 <prvTimerTask+0x1a2>
  32194. prvSwitchTimerLists();
  32195. 800e47e: f7ff feeb bl 800e258 <prvSwitchTimerLists>
  32196. xLastTime = xTimeNow;
  32197. 800e482: f8c5 a000 str.w sl, [r5]
  32198. ( void ) xTaskResumeAll();
  32199. 800e486: f7ff fa8d bl 800d9a4 <xTaskResumeAll>
  32200. 800e48a: e765 b.n 800e358 <prvTimerTask+0x68>
  32201. prvSwitchTimerLists();
  32202. 800e48c: f7ff fee4 bl 800e258 <prvSwitchTimerLists>
  32203. *pxTimerListsWereSwitched = pdTRUE;
  32204. 800e490: e77a b.n 800e388 <prvTimerTask+0x98>
  32205. xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
  32206. 800e492: 4b3b ldr r3, [pc, #236] @ (800e580 <prvTimerTask+0x290>)
  32207. xLastTime = xTimeNow;
  32208. 800e494: f8c5 a000 str.w sl, [r5]
  32209. xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
  32210. 800e498: 681b ldr r3, [r3, #0]
  32211. 800e49a: 681a ldr r2, [r3, #0]
  32212. 800e49c: fab2 f282 clz r2, r2
  32213. 800e4a0: 0952 lsrs r2, r2, #5
  32214. vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
  32215. 800e4a2: eba7 010a sub.w r1, r7, sl
  32216. 800e4a6: 6820 ldr r0, [r4, #0]
  32217. 800e4a8: f7fe fd3a bl 800cf20 <vQueueWaitForMessageRestricted>
  32218. if( xTaskResumeAll() == pdFALSE )
  32219. 800e4ac: f7ff fa7a bl 800d9a4 <xTaskResumeAll>
  32220. 800e4b0: 2800 cmp r0, #0
  32221. 800e4b2: f47f af51 bne.w 800e358 <prvTimerTask+0x68>
  32222. portYIELD_WITHIN_API();
  32223. 800e4b6: f04f 5380 mov.w r3, #268435456 @ 0x10000000
  32224. 800e4ba: f8c9 3d04 str.w r3, [r9, #3332] @ 0xd04
  32225. 800e4be: f3bf 8f4f dsb sy
  32226. 800e4c2: f3bf 8f6f isb sy
  32227. 800e4c6: e747 b.n 800e358 <prvTimerTask+0x68>
  32228. 800e4c8: 2200 movs r2, #0
  32229. 800e4ca: e7ea b.n 800e4a2 <prvTimerTask+0x1b2>
  32230. if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
  32231. 800e4cc: 455b cmp r3, fp
  32232. 800e4ce: d902 bls.n 800e4d6 <prvTimerTask+0x1e6>
  32233. 800e4d0: 2800 cmp r0, #0
  32234. 800e4d2: f43f af7b beq.w 800e3cc <prvTimerTask+0xdc>
  32235. vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
  32236. 800e4d6: 1d39 adds r1, r7, #4
  32237. 800e4d8: 6830 ldr r0, [r6, #0]
  32238. 800e4da: f7fd fdc9 bl 800c070 <vListInsert>
  32239. return xProcessTimerNow;
  32240. 800e4de: e73b b.n 800e358 <prvTimerTask+0x68>
  32241. vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
  32242. 800e4e0: 6830 ldr r0, [r6, #0]
  32243. 800e4e2: f7fd fdc5 bl 800c070 <vListInsert>
  32244. 800e4e6: e737 b.n 800e358 <prvTimerTask+0x68>
  32245. if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
  32246. 800e4e8: f8db 0018 ldr.w r0, [fp, #24]
  32247. listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
  32248. 800e4ec: f8cb b010 str.w fp, [fp, #16]
  32249. if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
  32250. 800e4f0: 183b adds r3, r7, r0
  32251. if( xNextExpiryTime <= xTimeNow )
  32252. 800e4f2: 459a cmp sl, r3
  32253. listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
  32254. 800e4f4: f8cb 3004 str.w r3, [fp, #4]
  32255. if( xNextExpiryTime <= xTimeNow )
  32256. 800e4f8: d321 bcc.n 800e53e <prvTimerTask+0x24e>
  32257. if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
  32258. 800e4fa: ebaa 0a07 sub.w sl, sl, r7
  32259. 800e4fe: 4550 cmp r0, sl
  32260. 800e500: d828 bhi.n 800e554 <prvTimerTask+0x264>
  32261. if( xTimerQueue != NULL )
  32262. 800e502: 6823 ldr r3, [r4, #0]
  32263. 800e504: b173 cbz r3, 800e524 <prvTimerTask+0x234>
  32264. xMessage.u.xTimerParameters.pxTimer = xTimer;
  32265. 800e506: e9cd 7b05 strd r7, fp, [sp, #20]
  32266. xMessage.xMessageID = xCommandID;
  32267. 800e50a: 2700 movs r7, #0
  32268. 800e50c: 9704 str r7, [sp, #16]
  32269. if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
  32270. 800e50e: f7ff fc0f bl 800dd30 <xTaskGetSchedulerState>
  32271. xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
  32272. 800e512: 463b mov r3, r7
  32273. 800e514: 463a mov r2, r7
  32274. 800e516: a904 add r1, sp, #16
  32275. 800e518: 6820 ldr r0, [r4, #0]
  32276. 800e51a: f7fd febb bl 800c294 <xQueueGenericSend>
  32277. configASSERT( xResult );
  32278. 800e51e: 2800 cmp r0, #0
  32279. 800e520: f47f af16 bne.w 800e350 <prvTimerTask+0x60>
  32280. 800e524: f04f 0350 mov.w r3, #80 @ 0x50
  32281. 800e528: f383 8811 msr BASEPRI, r3
  32282. 800e52c: f3bf 8f6f isb sy
  32283. 800e530: f3bf 8f4f dsb sy
  32284. 800e534: e7fe b.n 800e534 <prvTimerTask+0x244>
  32285. vPortFree( pxTimer );
  32286. 800e536: 4638 mov r0, r7
  32287. 800e538: f000 fc50 bl 800eddc <vPortFree>
  32288. 800e53c: e70c b.n 800e358 <prvTimerTask+0x68>
  32289. vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
  32290. 800e53e: 4641 mov r1, r8
  32291. 800e540: 6830 ldr r0, [r6, #0]
  32292. 800e542: f7fd fd95 bl 800c070 <vListInsert>
  32293. return xProcessTimerNow;
  32294. 800e546: e703 b.n 800e350 <prvTimerTask+0x60>
  32295. vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
  32296. 800e548: 4b0d ldr r3, [pc, #52] @ (800e580 <prvTimerTask+0x290>)
  32297. 800e54a: 1d39 adds r1, r7, #4
  32298. 800e54c: 6818 ldr r0, [r3, #0]
  32299. 800e54e: f7fd fd8f bl 800c070 <vListInsert>
  32300. return xProcessTimerNow;
  32301. 800e552: e701 b.n 800e358 <prvTimerTask+0x68>
  32302. vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
  32303. 800e554: 4b0a ldr r3, [pc, #40] @ (800e580 <prvTimerTask+0x290>)
  32304. 800e556: 4641 mov r1, r8
  32305. 800e558: 6818 ldr r0, [r3, #0]
  32306. 800e55a: f7fd fd89 bl 800c070 <vListInsert>
  32307. return xProcessTimerNow;
  32308. 800e55e: e6f7 b.n 800e350 <prvTimerTask+0x60>
  32309. 800e560: f04f 0350 mov.w r3, #80 @ 0x50
  32310. 800e564: f383 8811 msr BASEPRI, r3
  32311. 800e568: f3bf 8f6f isb sy
  32312. 800e56c: f3bf 8f4f dsb sy
  32313. configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
  32314. 800e570: e7fe b.n 800e570 <prvTimerTask+0x280>
  32315. 800e572: bf00 nop
  32316. 800e574: 24003144 .word 0x24003144
  32317. 800e578: 24003134 .word 0x24003134
  32318. 800e57c: 2400313c .word 0x2400313c
  32319. 800e580: 24003140 .word 0x24003140
  32320. 0800e584 <xTimerCreateTimerTask>:
  32321. {
  32322. 800e584: b5f0 push {r4, r5, r6, r7, lr}
  32323. /* Check that the list from which active timers are referenced, and the
  32324. queue used to communicate with the timer service, have been
  32325. initialised. */
  32326. taskENTER_CRITICAL();
  32327. {
  32328. if( xTimerQueue == NULL )
  32329. 800e586: 4c23 ldr r4, [pc, #140] @ (800e614 <xTimerCreateTimerTask+0x90>)
  32330. {
  32331. 800e588: b089 sub sp, #36 @ 0x24
  32332. taskENTER_CRITICAL();
  32333. 800e58a: f000 fa0b bl 800e9a4 <vPortEnterCritical>
  32334. if( xTimerQueue == NULL )
  32335. 800e58e: 6825 ldr r5, [r4, #0]
  32336. 800e590: b335 cbz r5, 800e5e0 <xTimerCreateTimerTask+0x5c>
  32337. else
  32338. {
  32339. mtCOVERAGE_TEST_MARKER();
  32340. }
  32341. }
  32342. taskEXIT_CRITICAL();
  32343. 800e592: f000 fa29 bl 800e9e8 <vPortExitCritical>
  32344. if( xTimerQueue != NULL )
  32345. 800e596: 6823 ldr r3, [r4, #0]
  32346. 800e598: b1cb cbz r3, 800e5ce <xTimerCreateTimerTask+0x4a>
  32347. StaticTask_t *pxTimerTaskTCBBuffer = NULL;
  32348. 800e59a: 2400 movs r4, #0
  32349. vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
  32350. 800e59c: aa07 add r2, sp, #28
  32351. 800e59e: a906 add r1, sp, #24
  32352. 800e5a0: a805 add r0, sp, #20
  32353. xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
  32354. 800e5a2: 2502 movs r5, #2
  32355. StackType_t *pxTimerTaskStackBuffer = NULL;
  32356. 800e5a4: e9cd 4405 strd r4, r4, [sp, #20]
  32357. vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
  32358. 800e5a8: f7fd fd34 bl 800c014 <vApplicationGetTimerTaskMemory>
  32359. xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
  32360. 800e5ac: 4623 mov r3, r4
  32361. 800e5ae: 9a07 ldr r2, [sp, #28]
  32362. 800e5b0: 9500 str r5, [sp, #0]
  32363. 800e5b2: e9dd 0105 ldrd r0, r1, [sp, #20]
  32364. 800e5b6: e9cd 1001 strd r1, r0, [sp, #4]
  32365. 800e5ba: 4917 ldr r1, [pc, #92] @ (800e618 <xTimerCreateTimerTask+0x94>)
  32366. 800e5bc: 4817 ldr r0, [pc, #92] @ (800e61c <xTimerCreateTimerTask+0x98>)
  32367. 800e5be: f7ff f8ad bl 800d71c <xTaskCreateStatic>
  32368. 800e5c2: 4b17 ldr r3, [pc, #92] @ (800e620 <xTimerCreateTimerTask+0x9c>)
  32369. 800e5c4: 6018 str r0, [r3, #0]
  32370. if( xTimerTaskHandle != NULL )
  32371. 800e5c6: b110 cbz r0, 800e5ce <xTimerCreateTimerTask+0x4a>
  32372. }
  32373. 800e5c8: 2001 movs r0, #1
  32374. 800e5ca: b009 add sp, #36 @ 0x24
  32375. 800e5cc: bdf0 pop {r4, r5, r6, r7, pc}
  32376. 800e5ce: f04f 0350 mov.w r3, #80 @ 0x50
  32377. 800e5d2: f383 8811 msr BASEPRI, r3
  32378. 800e5d6: f3bf 8f6f isb sy
  32379. 800e5da: f3bf 8f4f dsb sy
  32380. configASSERT( xReturn );
  32381. 800e5de: e7fe b.n 800e5de <xTimerCreateTimerTask+0x5a>
  32382. vListInitialise( &xActiveTimerList1 );
  32383. 800e5e0: 4f10 ldr r7, [pc, #64] @ (800e624 <xTimerCreateTimerTask+0xa0>)
  32384. vListInitialise( &xActiveTimerList2 );
  32385. 800e5e2: 4e11 ldr r6, [pc, #68] @ (800e628 <xTimerCreateTimerTask+0xa4>)
  32386. vListInitialise( &xActiveTimerList1 );
  32387. 800e5e4: 4638 mov r0, r7
  32388. 800e5e6: f7fd fd25 bl 800c034 <vListInitialise>
  32389. vListInitialise( &xActiveTimerList2 );
  32390. 800e5ea: 4630 mov r0, r6
  32391. 800e5ec: f7fd fd22 bl 800c034 <vListInitialise>
  32392. pxCurrentTimerList = &xActiveTimerList1;
  32393. 800e5f0: 4a0e ldr r2, [pc, #56] @ (800e62c <xTimerCreateTimerTask+0xa8>)
  32394. xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
  32395. 800e5f2: 9500 str r5, [sp, #0]
  32396. 800e5f4: 2110 movs r1, #16
  32397. pxCurrentTimerList = &xActiveTimerList1;
  32398. 800e5f6: 6017 str r7, [r2, #0]
  32399. xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
  32400. 800e5f8: 200a movs r0, #10
  32401. pxOverflowTimerList = &xActiveTimerList2;
  32402. 800e5fa: 4a0d ldr r2, [pc, #52] @ (800e630 <xTimerCreateTimerTask+0xac>)
  32403. xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
  32404. 800e5fc: 4b0d ldr r3, [pc, #52] @ (800e634 <xTimerCreateTimerTask+0xb0>)
  32405. pxOverflowTimerList = &xActiveTimerList2;
  32406. 800e5fe: 6016 str r6, [r2, #0]
  32407. xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
  32408. 800e600: 4a0d ldr r2, [pc, #52] @ (800e638 <xTimerCreateTimerTask+0xb4>)
  32409. 800e602: f7fd fd99 bl 800c138 <xQueueGenericCreateStatic>
  32410. 800e606: 6020 str r0, [r4, #0]
  32411. if( xTimerQueue != NULL )
  32412. 800e608: 2800 cmp r0, #0
  32413. 800e60a: d0c2 beq.n 800e592 <xTimerCreateTimerTask+0xe>
  32414. vQueueAddToRegistry( xTimerQueue, "TmrQ" );
  32415. 800e60c: 490b ldr r1, [pc, #44] @ (800e63c <xTimerCreateTimerTask+0xb8>)
  32416. 800e60e: f7fe fc5f bl 800ced0 <vQueueAddToRegistry>
  32417. 800e612: e7be b.n 800e592 <xTimerCreateTimerTask+0xe>
  32418. 800e614: 2400313c .word 0x2400313c
  32419. 800e618: 08011a64 .word 0x08011a64
  32420. 800e61c: 0800e2f1 .word 0x0800e2f1
  32421. 800e620: 24003138 .word 0x24003138
  32422. 800e624: 2400315c .word 0x2400315c
  32423. 800e628: 24003148 .word 0x24003148
  32424. 800e62c: 24003144 .word 0x24003144
  32425. 800e630: 24003140 .word 0x24003140
  32426. 800e634: 24003044 .word 0x24003044
  32427. 800e638: 24003094 .word 0x24003094
  32428. 800e63c: 08011a5c .word 0x08011a5c
  32429. 0800e640 <xTimerCreate>:
  32430. {
  32431. 800e640: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  32432. 800e644: 4607 mov r7, r0
  32433. 800e646: b085 sub sp, #20
  32434. pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
  32435. 800e648: 202c movs r0, #44 @ 0x2c
  32436. {
  32437. 800e64a: 4688 mov r8, r1
  32438. 800e64c: 4616 mov r6, r2
  32439. 800e64e: 461d mov r5, r3
  32440. pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
  32441. 800e650: f000 fb08 bl 800ec64 <pvPortMalloc>
  32442. if( pxNewTimer != NULL )
  32443. 800e654: 4604 mov r4, r0
  32444. 800e656: b1e8 cbz r0, 800e694 <xTimerCreate+0x54>
  32445. pxNewTimer->ucStatus = 0x00;
  32446. 800e658: 2300 movs r3, #0
  32447. 800e65a: f880 3028 strb.w r3, [r0, #40] @ 0x28
  32448. configASSERT( ( xTimerPeriodInTicks > 0 ) );
  32449. 800e65e: f1b8 0f00 cmp.w r8, #0
  32450. 800e662: d01b beq.n 800e69c <xTimerCreate+0x5c>
  32451. if( xTimerQueue == NULL )
  32452. 800e664: f8df 909c ldr.w r9, [pc, #156] @ 800e704 <xTimerCreate+0xc4>
  32453. taskENTER_CRITICAL();
  32454. 800e668: f000 f99c bl 800e9a4 <vPortEnterCritical>
  32455. if( xTimerQueue == NULL )
  32456. 800e66c: f8d9 3000 ldr.w r3, [r9]
  32457. 800e670: b1eb cbz r3, 800e6ae <xTimerCreate+0x6e>
  32458. taskEXIT_CRITICAL();
  32459. 800e672: f000 f9b9 bl 800e9e8 <vPortExitCritical>
  32460. pxNewTimer->pxCallbackFunction = pxCallbackFunction;
  32461. 800e676: 9b0e ldr r3, [sp, #56] @ 0x38
  32462. vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
  32463. 800e678: 1d20 adds r0, r4, #4
  32464. pxNewTimer->pcTimerName = pcTimerName;
  32465. 800e67a: 6027 str r7, [r4, #0]
  32466. pxNewTimer->pxCallbackFunction = pxCallbackFunction;
  32467. 800e67c: 6223 str r3, [r4, #32]
  32468. pxNewTimer->pvTimerID = pvTimerID;
  32469. 800e67e: e9c4 8506 strd r8, r5, [r4, #24]
  32470. vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
  32471. 800e682: f7fd fce3 bl 800c04c <vListInitialiseItem>
  32472. if( uxAutoReload != pdFALSE )
  32473. 800e686: b12e cbz r6, 800e694 <xTimerCreate+0x54>
  32474. pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
  32475. 800e688: f894 3028 ldrb.w r3, [r4, #40] @ 0x28
  32476. 800e68c: f043 0304 orr.w r3, r3, #4
  32477. 800e690: f884 3028 strb.w r3, [r4, #40] @ 0x28
  32478. }
  32479. 800e694: 4620 mov r0, r4
  32480. 800e696: b005 add sp, #20
  32481. 800e698: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  32482. 800e69c: f04f 0350 mov.w r3, #80 @ 0x50
  32483. 800e6a0: f383 8811 msr BASEPRI, r3
  32484. 800e6a4: f3bf 8f6f isb sy
  32485. 800e6a8: f3bf 8f4f dsb sy
  32486. configASSERT( ( xTimerPeriodInTicks > 0 ) );
  32487. 800e6ac: e7fe b.n 800e6ac <xTimerCreate+0x6c>
  32488. vListInitialise( &xActiveTimerList1 );
  32489. 800e6ae: f8df b058 ldr.w fp, [pc, #88] @ 800e708 <xTimerCreate+0xc8>
  32490. vListInitialise( &xActiveTimerList2 );
  32491. 800e6b2: f8df a058 ldr.w sl, [pc, #88] @ 800e70c <xTimerCreate+0xcc>
  32492. vListInitialise( &xActiveTimerList1 );
  32493. 800e6b6: 4658 mov r0, fp
  32494. 800e6b8: 9303 str r3, [sp, #12]
  32495. 800e6ba: f7fd fcbb bl 800c034 <vListInitialise>
  32496. vListInitialise( &xActiveTimerList2 );
  32497. 800e6be: 4650 mov r0, sl
  32498. 800e6c0: f7fd fcb8 bl 800c034 <vListInitialise>
  32499. xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
  32500. 800e6c4: 9b03 ldr r3, [sp, #12]
  32501. 800e6c6: 4a0a ldr r2, [pc, #40] @ (800e6f0 <xTimerCreate+0xb0>)
  32502. 800e6c8: 2110 movs r1, #16
  32503. 800e6ca: 9300 str r3, [sp, #0]
  32504. 800e6cc: 200a movs r0, #10
  32505. pxCurrentTimerList = &xActiveTimerList1;
  32506. 800e6ce: 4b09 ldr r3, [pc, #36] @ (800e6f4 <xTimerCreate+0xb4>)
  32507. 800e6d0: f8c3 b000 str.w fp, [r3]
  32508. pxOverflowTimerList = &xActiveTimerList2;
  32509. 800e6d4: 4b08 ldr r3, [pc, #32] @ (800e6f8 <xTimerCreate+0xb8>)
  32510. 800e6d6: f8c3 a000 str.w sl, [r3]
  32511. xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
  32512. 800e6da: 4b08 ldr r3, [pc, #32] @ (800e6fc <xTimerCreate+0xbc>)
  32513. 800e6dc: f7fd fd2c bl 800c138 <xQueueGenericCreateStatic>
  32514. 800e6e0: f8c9 0000 str.w r0, [r9]
  32515. if( xTimerQueue != NULL )
  32516. 800e6e4: 2800 cmp r0, #0
  32517. 800e6e6: d0c4 beq.n 800e672 <xTimerCreate+0x32>
  32518. vQueueAddToRegistry( xTimerQueue, "TmrQ" );
  32519. 800e6e8: 4905 ldr r1, [pc, #20] @ (800e700 <xTimerCreate+0xc0>)
  32520. 800e6ea: f7fe fbf1 bl 800ced0 <vQueueAddToRegistry>
  32521. 800e6ee: e7c0 b.n 800e672 <xTimerCreate+0x32>
  32522. 800e6f0: 24003094 .word 0x24003094
  32523. 800e6f4: 24003144 .word 0x24003144
  32524. 800e6f8: 24003140 .word 0x24003140
  32525. 800e6fc: 24003044 .word 0x24003044
  32526. 800e700: 08011a5c .word 0x08011a5c
  32527. 800e704: 2400313c .word 0x2400313c
  32528. 800e708: 2400315c .word 0x2400315c
  32529. 800e70c: 24003148 .word 0x24003148
  32530. 0800e710 <xTimerCreateStatic>:
  32531. {
  32532. 800e710: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  32533. volatile size_t xSize = sizeof( StaticTimer_t );
  32534. 800e714: 242c movs r4, #44 @ 0x2c
  32535. {
  32536. 800e716: b085 sub sp, #20
  32537. volatile size_t xSize = sizeof( StaticTimer_t );
  32538. 800e718: 9403 str r4, [sp, #12]
  32539. configASSERT( xSize == sizeof( Timer_t ) );
  32540. 800e71a: 9c03 ldr r4, [sp, #12]
  32541. 800e71c: 2c2c cmp r4, #44 @ 0x2c
  32542. 800e71e: d008 beq.n 800e732 <xTimerCreateStatic+0x22>
  32543. 800e720: f04f 0350 mov.w r3, #80 @ 0x50
  32544. 800e724: f383 8811 msr BASEPRI, r3
  32545. 800e728: f3bf 8f6f isb sy
  32546. 800e72c: f3bf 8f4f dsb sy
  32547. 800e730: e7fe b.n 800e730 <xTimerCreateStatic+0x20>
  32548. ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
  32549. 800e732: 461d mov r5, r3
  32550. 800e734: 9b03 ldr r3, [sp, #12]
  32551. configASSERT( pxTimerBuffer );
  32552. 800e736: 9b0f ldr r3, [sp, #60] @ 0x3c
  32553. 800e738: b343 cbz r3, 800e78c <xTimerCreateStatic+0x7c>
  32554. pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
  32555. 800e73a: 4616 mov r6, r2
  32556. 800e73c: 461a mov r2, r3
  32557. 800e73e: 2302 movs r3, #2
  32558. 800e740: 460f mov r7, r1
  32559. 800e742: f882 3028 strb.w r3, [r2, #40] @ 0x28
  32560. configASSERT( ( xTimerPeriodInTicks > 0 ) );
  32561. 800e746: b351 cbz r1, 800e79e <xTimerCreateStatic+0x8e>
  32562. if( xTimerQueue == NULL )
  32563. 800e748: 4c29 ldr r4, [pc, #164] @ (800e7f0 <xTimerCreateStatic+0xe0>)
  32564. 800e74a: 4680 mov r8, r0
  32565. taskENTER_CRITICAL();
  32566. 800e74c: f000 f92a bl 800e9a4 <vPortEnterCritical>
  32567. if( xTimerQueue == NULL )
  32568. 800e750: f8d4 b000 ldr.w fp, [r4]
  32569. 800e754: f1bb 0f00 cmp.w fp, #0
  32570. 800e758: d02a beq.n 800e7b0 <xTimerCreateStatic+0xa0>
  32571. taskEXIT_CRITICAL();
  32572. 800e75a: f000 f945 bl 800e9e8 <vPortExitCritical>
  32573. vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
  32574. 800e75e: 9b0f ldr r3, [sp, #60] @ 0x3c
  32575. pxNewTimer->pxCallbackFunction = pxCallbackFunction;
  32576. 800e760: 9a0e ldr r2, [sp, #56] @ 0x38
  32577. vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
  32578. 800e762: 1d18 adds r0, r3, #4
  32579. pxNewTimer->pcTimerName = pcTimerName;
  32580. 800e764: f8c3 8000 str.w r8, [r3]
  32581. pxNewTimer->pxCallbackFunction = pxCallbackFunction;
  32582. 800e768: 621a str r2, [r3, #32]
  32583. pxNewTimer->pvTimerID = pvTimerID;
  32584. 800e76a: e9c3 7506 strd r7, r5, [r3, #24]
  32585. vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
  32586. 800e76e: f7fd fc6d bl 800c04c <vListInitialiseItem>
  32587. if( uxAutoReload != pdFALSE )
  32588. 800e772: b13e cbz r6, 800e784 <xTimerCreateStatic+0x74>
  32589. pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
  32590. 800e774: 9b0f ldr r3, [sp, #60] @ 0x3c
  32591. 800e776: 9a0f ldr r2, [sp, #60] @ 0x3c
  32592. 800e778: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
  32593. 800e77c: f043 0304 orr.w r3, r3, #4
  32594. 800e780: f882 3028 strb.w r3, [r2, #40] @ 0x28
  32595. }
  32596. 800e784: 980f ldr r0, [sp, #60] @ 0x3c
  32597. 800e786: b005 add sp, #20
  32598. 800e788: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  32599. 800e78c: f04f 0350 mov.w r3, #80 @ 0x50
  32600. 800e790: f383 8811 msr BASEPRI, r3
  32601. 800e794: f3bf 8f6f isb sy
  32602. 800e798: f3bf 8f4f dsb sy
  32603. configASSERT( pxTimerBuffer );
  32604. 800e79c: e7fe b.n 800e79c <xTimerCreateStatic+0x8c>
  32605. 800e79e: f04f 0350 mov.w r3, #80 @ 0x50
  32606. 800e7a2: f383 8811 msr BASEPRI, r3
  32607. 800e7a6: f3bf 8f6f isb sy
  32608. 800e7aa: f3bf 8f4f dsb sy
  32609. configASSERT( ( xTimerPeriodInTicks > 0 ) );
  32610. 800e7ae: e7fe b.n 800e7ae <xTimerCreateStatic+0x9e>
  32611. vListInitialise( &xActiveTimerList1 );
  32612. 800e7b0: f8df a054 ldr.w sl, [pc, #84] @ 800e808 <xTimerCreateStatic+0xf8>
  32613. vListInitialise( &xActiveTimerList2 );
  32614. 800e7b4: f8df 9054 ldr.w r9, [pc, #84] @ 800e80c <xTimerCreateStatic+0xfc>
  32615. vListInitialise( &xActiveTimerList1 );
  32616. 800e7b8: 4650 mov r0, sl
  32617. 800e7ba: f7fd fc3b bl 800c034 <vListInitialise>
  32618. vListInitialise( &xActiveTimerList2 );
  32619. 800e7be: 4648 mov r0, r9
  32620. 800e7c0: f7fd fc38 bl 800c034 <vListInitialise>
  32621. pxCurrentTimerList = &xActiveTimerList1;
  32622. 800e7c4: 4a0b ldr r2, [pc, #44] @ (800e7f4 <xTimerCreateStatic+0xe4>)
  32623. pxOverflowTimerList = &xActiveTimerList2;
  32624. 800e7c6: 4b0c ldr r3, [pc, #48] @ (800e7f8 <xTimerCreateStatic+0xe8>)
  32625. xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
  32626. 800e7c8: 2110 movs r1, #16
  32627. 800e7ca: f8cd b000 str.w fp, [sp]
  32628. 800e7ce: 200a movs r0, #10
  32629. pxCurrentTimerList = &xActiveTimerList1;
  32630. 800e7d0: f8c2 a000 str.w sl, [r2]
  32631. pxOverflowTimerList = &xActiveTimerList2;
  32632. 800e7d4: f8c3 9000 str.w r9, [r3]
  32633. xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
  32634. 800e7d8: 4a08 ldr r2, [pc, #32] @ (800e7fc <xTimerCreateStatic+0xec>)
  32635. 800e7da: 4b09 ldr r3, [pc, #36] @ (800e800 <xTimerCreateStatic+0xf0>)
  32636. 800e7dc: f7fd fcac bl 800c138 <xQueueGenericCreateStatic>
  32637. 800e7e0: 6020 str r0, [r4, #0]
  32638. if( xTimerQueue != NULL )
  32639. 800e7e2: 2800 cmp r0, #0
  32640. 800e7e4: d0b9 beq.n 800e75a <xTimerCreateStatic+0x4a>
  32641. vQueueAddToRegistry( xTimerQueue, "TmrQ" );
  32642. 800e7e6: 4907 ldr r1, [pc, #28] @ (800e804 <xTimerCreateStatic+0xf4>)
  32643. 800e7e8: f7fe fb72 bl 800ced0 <vQueueAddToRegistry>
  32644. 800e7ec: e7b5 b.n 800e75a <xTimerCreateStatic+0x4a>
  32645. 800e7ee: bf00 nop
  32646. 800e7f0: 2400313c .word 0x2400313c
  32647. 800e7f4: 24003144 .word 0x24003144
  32648. 800e7f8: 24003140 .word 0x24003140
  32649. 800e7fc: 24003094 .word 0x24003094
  32650. 800e800: 24003044 .word 0x24003044
  32651. 800e804: 08011a5c .word 0x08011a5c
  32652. 800e808: 2400315c .word 0x2400315c
  32653. 800e80c: 24003148 .word 0x24003148
  32654. 0800e810 <xTimerGenericCommand>:
  32655. configASSERT( xTimer );
  32656. 800e810: b1c8 cbz r0, 800e846 <xTimerGenericCommand+0x36>
  32657. {
  32658. 800e812: b530 push {r4, r5, lr}
  32659. if( xTimerQueue != NULL )
  32660. 800e814: 4d18 ldr r5, [pc, #96] @ (800e878 <xTimerGenericCommand+0x68>)
  32661. {
  32662. 800e816: b085 sub sp, #20
  32663. if( xTimerQueue != NULL )
  32664. 800e818: 682c ldr r4, [r5, #0]
  32665. 800e81a: b18c cbz r4, 800e840 <xTimerGenericCommand+0x30>
  32666. if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
  32667. 800e81c: 2905 cmp r1, #5
  32668. xMessage.u.xTimerParameters.pxTimer = xTimer;
  32669. 800e81e: 9002 str r0, [sp, #8]
  32670. xMessage.xMessageID = xCommandID;
  32671. 800e820: e9cd 1200 strd r1, r2, [sp]
  32672. if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
  32673. 800e824: dc18 bgt.n 800e858 <xTimerGenericCommand+0x48>
  32674. if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
  32675. 800e826: f7ff fa83 bl 800dd30 <xTaskGetSchedulerState>
  32676. 800e82a: 2802 cmp r0, #2
  32677. xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
  32678. 800e82c: f04f 0300 mov.w r3, #0
  32679. if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
  32680. 800e830: d01b beq.n 800e86a <xTimerGenericCommand+0x5a>
  32681. xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
  32682. 800e832: 4669 mov r1, sp
  32683. 800e834: 461a mov r2, r3
  32684. 800e836: 6828 ldr r0, [r5, #0]
  32685. 800e838: f7fd fd2c bl 800c294 <xQueueGenericSend>
  32686. }
  32687. 800e83c: b005 add sp, #20
  32688. 800e83e: bd30 pop {r4, r5, pc}
  32689. BaseType_t xReturn = pdFAIL;
  32690. 800e840: 4620 mov r0, r4
  32691. }
  32692. 800e842: b005 add sp, #20
  32693. 800e844: bd30 pop {r4, r5, pc}
  32694. 800e846: f04f 0350 mov.w r3, #80 @ 0x50
  32695. 800e84a: f383 8811 msr BASEPRI, r3
  32696. 800e84e: f3bf 8f6f isb sy
  32697. 800e852: f3bf 8f4f dsb sy
  32698. configASSERT( xTimer );
  32699. 800e856: e7fe b.n 800e856 <xTimerGenericCommand+0x46>
  32700. xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
  32701. 800e858: 469c mov ip, r3
  32702. 800e85a: 4669 mov r1, sp
  32703. 800e85c: 2300 movs r3, #0
  32704. 800e85e: 4620 mov r0, r4
  32705. 800e860: 4662 mov r2, ip
  32706. 800e862: f7fd ff41 bl 800c6e8 <xQueueGenericSendFromISR>
  32707. }
  32708. 800e866: b005 add sp, #20
  32709. 800e868: bd30 pop {r4, r5, pc}
  32710. xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
  32711. 800e86a: 9a08 ldr r2, [sp, #32]
  32712. 800e86c: 4669 mov r1, sp
  32713. 800e86e: 6828 ldr r0, [r5, #0]
  32714. 800e870: f7fd fd10 bl 800c294 <xQueueGenericSend>
  32715. 800e874: e7e5 b.n 800e842 <xTimerGenericCommand+0x32>
  32716. 800e876: bf00 nop
  32717. 800e878: 2400313c .word 0x2400313c
  32718. 0800e87c <xTimerIsTimerActive>:
  32719. BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
  32720. {
  32721. BaseType_t xReturn;
  32722. Timer_t *pxTimer = xTimer;
  32723. configASSERT( xTimer );
  32724. 800e87c: b158 cbz r0, 800e896 <xTimerIsTimerActive+0x1a>
  32725. {
  32726. 800e87e: b510 push {r4, lr}
  32727. 800e880: 4604 mov r4, r0
  32728. /* Is the timer in the list of active timers? */
  32729. taskENTER_CRITICAL();
  32730. 800e882: f000 f88f bl 800e9a4 <vPortEnterCritical>
  32731. {
  32732. if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
  32733. 800e886: f894 4028 ldrb.w r4, [r4, #40] @ 0x28
  32734. else
  32735. {
  32736. xReturn = pdTRUE;
  32737. }
  32738. }
  32739. taskEXIT_CRITICAL();
  32740. 800e88a: f000 f8ad bl 800e9e8 <vPortExitCritical>
  32741. 800e88e: f004 0401 and.w r4, r4, #1
  32742. return xReturn;
  32743. } /*lint !e818 Can't be pointer to const due to the typedef. */
  32744. 800e892: 4620 mov r0, r4
  32745. 800e894: bd10 pop {r4, pc}
  32746. 800e896: f04f 0350 mov.w r3, #80 @ 0x50
  32747. 800e89a: f383 8811 msr BASEPRI, r3
  32748. 800e89e: f3bf 8f6f isb sy
  32749. 800e8a2: f3bf 8f4f dsb sy
  32750. configASSERT( xTimer );
  32751. 800e8a6: e7fe b.n 800e8a6 <xTimerIsTimerActive+0x2a>
  32752. 0800e8a8 <pvTimerGetTimerID>:
  32753. void *pvTimerGetTimerID( const TimerHandle_t xTimer )
  32754. {
  32755. Timer_t * const pxTimer = xTimer;
  32756. void *pvReturn;
  32757. configASSERT( xTimer );
  32758. 800e8a8: b140 cbz r0, 800e8bc <pvTimerGetTimerID+0x14>
  32759. {
  32760. 800e8aa: b510 push {r4, lr}
  32761. 800e8ac: 4604 mov r4, r0
  32762. taskENTER_CRITICAL();
  32763. 800e8ae: f000 f879 bl 800e9a4 <vPortEnterCritical>
  32764. {
  32765. pvReturn = pxTimer->pvTimerID;
  32766. 800e8b2: 69e4 ldr r4, [r4, #28]
  32767. }
  32768. taskEXIT_CRITICAL();
  32769. 800e8b4: f000 f898 bl 800e9e8 <vPortExitCritical>
  32770. return pvReturn;
  32771. }
  32772. 800e8b8: 4620 mov r0, r4
  32773. 800e8ba: bd10 pop {r4, pc}
  32774. 800e8bc: f04f 0350 mov.w r3, #80 @ 0x50
  32775. 800e8c0: f383 8811 msr BASEPRI, r3
  32776. 800e8c4: f3bf 8f6f isb sy
  32777. 800e8c8: f3bf 8f4f dsb sy
  32778. configASSERT( xTimer );
  32779. 800e8cc: e7fe b.n 800e8cc <pvTimerGetTimerID+0x24>
  32780. 800e8ce: bf00 nop
  32781. 0800e8d0 <prvPortStartFirstTask>:
  32782. {
  32783. /* Start the first task. This also clears the bit that indicates the FPU is
  32784. in use in case the FPU was used before the scheduler was started - which
  32785. would otherwise result in the unnecessary leaving of space in the SVC stack
  32786. for lazy saving of FPU registers. */
  32787. __asm volatile(
  32788. 800e8d0: 4808 ldr r0, [pc, #32] @ (800e8f4 <prvPortStartFirstTask+0x24>)
  32789. 800e8d2: 6800 ldr r0, [r0, #0]
  32790. 800e8d4: 6800 ldr r0, [r0, #0]
  32791. 800e8d6: f380 8808 msr MSP, r0
  32792. 800e8da: f04f 0000 mov.w r0, #0
  32793. 800e8de: f380 8814 msr CONTROL, r0
  32794. 800e8e2: b662 cpsie i
  32795. 800e8e4: b661 cpsie f
  32796. 800e8e6: f3bf 8f4f dsb sy
  32797. 800e8ea: f3bf 8f6f isb sy
  32798. 800e8ee: df00 svc 0
  32799. 800e8f0: bf00 nop
  32800. " dsb \n"
  32801. " isb \n"
  32802. " svc 0 \n" /* System call to start first task. */
  32803. " nop \n"
  32804. );
  32805. }
  32806. 800e8f2: 0000 .short 0x0000
  32807. 800e8f4: e000ed08 .word 0xe000ed08
  32808. 0800e8f8 <vPortEnableVFP>:
  32809. /*-----------------------------------------------------------*/
  32810. /* This is a naked function. */
  32811. static void vPortEnableVFP( void )
  32812. {
  32813. __asm volatile
  32814. 800e8f8: f8df 000c ldr.w r0, [pc, #12] @ 800e908 <vPortEnableVFP+0x10>
  32815. 800e8fc: 6801 ldr r1, [r0, #0]
  32816. 800e8fe: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
  32817. 800e902: 6001 str r1, [r0, #0]
  32818. 800e904: 4770 bx lr
  32819. " \n"
  32820. " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
  32821. " str r1, [r0] \n"
  32822. " bx r14 "
  32823. );
  32824. }
  32825. 800e906: 0000 .short 0x0000
  32826. 800e908: e000ed88 .word 0xe000ed88
  32827. 0800e90c <prvTaskExitError>:
  32828. configASSERT( uxCriticalNesting == ~0UL );
  32829. 800e90c: 4b0e ldr r3, [pc, #56] @ (800e948 <prvTaskExitError+0x3c>)
  32830. {
  32831. 800e90e: b082 sub sp, #8
  32832. volatile uint32_t ulDummy = 0;
  32833. 800e910: 2200 movs r2, #0
  32834. configASSERT( uxCriticalNesting == ~0UL );
  32835. 800e912: 681b ldr r3, [r3, #0]
  32836. volatile uint32_t ulDummy = 0;
  32837. 800e914: 9201 str r2, [sp, #4]
  32838. configASSERT( uxCriticalNesting == ~0UL );
  32839. 800e916: 3301 adds r3, #1
  32840. 800e918: d008 beq.n 800e92c <prvTaskExitError+0x20>
  32841. 800e91a: f04f 0350 mov.w r3, #80 @ 0x50
  32842. 800e91e: f383 8811 msr BASEPRI, r3
  32843. 800e922: f3bf 8f6f isb sy
  32844. 800e926: f3bf 8f4f dsb sy
  32845. 800e92a: e7fe b.n 800e92a <prvTaskExitError+0x1e>
  32846. 800e92c: f04f 0350 mov.w r3, #80 @ 0x50
  32847. 800e930: f383 8811 msr BASEPRI, r3
  32848. 800e934: f3bf 8f6f isb sy
  32849. 800e938: f3bf 8f4f dsb sy
  32850. while( ulDummy == 0 )
  32851. 800e93c: 9b01 ldr r3, [sp, #4]
  32852. 800e93e: 2b00 cmp r3, #0
  32853. 800e940: d0fc beq.n 800e93c <prvTaskExitError+0x30>
  32854. }
  32855. 800e942: b002 add sp, #8
  32856. 800e944: 4770 bx lr
  32857. 800e946: bf00 nop
  32858. 800e948: 24000044 .word 0x24000044
  32859. 0800e94c <pxPortInitialiseStack>:
  32860. {
  32861. 800e94c: 4603 mov r3, r0
  32862. *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
  32863. 800e94e: f021 0101 bic.w r1, r1, #1
  32864. *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
  32865. 800e952: 4809 ldr r0, [pc, #36] @ (800e978 <pxPortInitialiseStack+0x2c>)
  32866. {
  32867. 800e954: b410 push {r4}
  32868. *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
  32869. 800e956: f04f 7480 mov.w r4, #16777216 @ 0x1000000
  32870. *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
  32871. 800e95a: f843 0c0c str.w r0, [r3, #-12]
  32872. *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
  32873. 800e95e: f843 2c20 str.w r2, [r3, #-32]
  32874. }
  32875. 800e962: f1a3 0044 sub.w r0, r3, #68 @ 0x44
  32876. *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
  32877. 800e966: e943 1402 strd r1, r4, [r3, #-8]
  32878. *pxTopOfStack = portINITIAL_EXC_RETURN;
  32879. 800e96a: f06f 0102 mvn.w r1, #2
  32880. }
  32881. 800e96e: f85d 4b04 ldr.w r4, [sp], #4
  32882. *pxTopOfStack = portINITIAL_EXC_RETURN;
  32883. 800e972: f843 1c24 str.w r1, [r3, #-36]
  32884. }
  32885. 800e976: 4770 bx lr
  32886. 800e978: 0800e90d .word 0x0800e90d
  32887. 800e97c: 00000000 .word 0x00000000
  32888. 0800e980 <SVC_Handler>:
  32889. __asm volatile (
  32890. 800e980: 4b07 ldr r3, [pc, #28] @ (800e9a0 <pxCurrentTCBConst2>)
  32891. 800e982: 6819 ldr r1, [r3, #0]
  32892. 800e984: 6808 ldr r0, [r1, #0]
  32893. 800e986: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  32894. 800e98a: f380 8809 msr PSP, r0
  32895. 800e98e: f3bf 8f6f isb sy
  32896. 800e992: f04f 0000 mov.w r0, #0
  32897. 800e996: f380 8811 msr BASEPRI, r0
  32898. 800e99a: 4770 bx lr
  32899. 800e99c: f3af 8000 nop.w
  32900. 0800e9a0 <pxCurrentTCBConst2>:
  32901. 800e9a0: 24003040 .word 0x24003040
  32902. 0800e9a4 <vPortEnterCritical>:
  32903. 800e9a4: f04f 0350 mov.w r3, #80 @ 0x50
  32904. 800e9a8: f383 8811 msr BASEPRI, r3
  32905. 800e9ac: f3bf 8f6f isb sy
  32906. 800e9b0: f3bf 8f4f dsb sy
  32907. uxCriticalNesting++;
  32908. 800e9b4: 4a0b ldr r2, [pc, #44] @ (800e9e4 <vPortEnterCritical+0x40>)
  32909. 800e9b6: 6813 ldr r3, [r2, #0]
  32910. 800e9b8: 3301 adds r3, #1
  32911. if( uxCriticalNesting == 1 )
  32912. 800e9ba: 2b01 cmp r3, #1
  32913. uxCriticalNesting++;
  32914. 800e9bc: 6013 str r3, [r2, #0]
  32915. if( uxCriticalNesting == 1 )
  32916. 800e9be: d000 beq.n 800e9c2 <vPortEnterCritical+0x1e>
  32917. }
  32918. 800e9c0: 4770 bx lr
  32919. configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
  32920. 800e9c2: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  32921. 800e9c6: f8d3 3d04 ldr.w r3, [r3, #3332] @ 0xd04
  32922. 800e9ca: b2db uxtb r3, r3
  32923. 800e9cc: 2b00 cmp r3, #0
  32924. 800e9ce: d0f7 beq.n 800e9c0 <vPortEnterCritical+0x1c>
  32925. 800e9d0: f04f 0350 mov.w r3, #80 @ 0x50
  32926. 800e9d4: f383 8811 msr BASEPRI, r3
  32927. 800e9d8: f3bf 8f6f isb sy
  32928. 800e9dc: f3bf 8f4f dsb sy
  32929. 800e9e0: e7fe b.n 800e9e0 <vPortEnterCritical+0x3c>
  32930. 800e9e2: bf00 nop
  32931. 800e9e4: 24000044 .word 0x24000044
  32932. 0800e9e8 <vPortExitCritical>:
  32933. configASSERT( uxCriticalNesting );
  32934. 800e9e8: 4a08 ldr r2, [pc, #32] @ (800ea0c <vPortExitCritical+0x24>)
  32935. 800e9ea: 6813 ldr r3, [r2, #0]
  32936. 800e9ec: b943 cbnz r3, 800ea00 <vPortExitCritical+0x18>
  32937. 800e9ee: f04f 0350 mov.w r3, #80 @ 0x50
  32938. 800e9f2: f383 8811 msr BASEPRI, r3
  32939. 800e9f6: f3bf 8f6f isb sy
  32940. 800e9fa: f3bf 8f4f dsb sy
  32941. 800e9fe: e7fe b.n 800e9fe <vPortExitCritical+0x16>
  32942. uxCriticalNesting--;
  32943. 800ea00: 3b01 subs r3, #1
  32944. 800ea02: 6013 str r3, [r2, #0]
  32945. if( uxCriticalNesting == 0 )
  32946. 800ea04: b90b cbnz r3, 800ea0a <vPortExitCritical+0x22>
  32947. __asm volatile
  32948. 800ea06: f383 8811 msr BASEPRI, r3
  32949. }
  32950. 800ea0a: 4770 bx lr
  32951. 800ea0c: 24000044 .word 0x24000044
  32952. 0800ea10 <PendSV_Handler>:
  32953. __asm volatile
  32954. 800ea10: f3ef 8009 mrs r0, PSP
  32955. 800ea14: f3bf 8f6f isb sy
  32956. 800ea18: 4b15 ldr r3, [pc, #84] @ (800ea70 <pxCurrentTCBConst>)
  32957. 800ea1a: 681a ldr r2, [r3, #0]
  32958. 800ea1c: f01e 0f10 tst.w lr, #16
  32959. 800ea20: bf08 it eq
  32960. 800ea22: ed20 8a10 vstmdbeq r0!, {s16-s31}
  32961. 800ea26: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  32962. 800ea2a: 6010 str r0, [r2, #0]
  32963. 800ea2c: e92d 0009 stmdb sp!, {r0, r3}
  32964. 800ea30: f04f 0050 mov.w r0, #80 @ 0x50
  32965. 800ea34: f380 8811 msr BASEPRI, r0
  32966. 800ea38: f3bf 8f4f dsb sy
  32967. 800ea3c: f3bf 8f6f isb sy
  32968. 800ea40: f7fe ffd6 bl 800d9f0 <vTaskSwitchContext>
  32969. 800ea44: f04f 0000 mov.w r0, #0
  32970. 800ea48: f380 8811 msr BASEPRI, r0
  32971. 800ea4c: bc09 pop {r0, r3}
  32972. 800ea4e: 6819 ldr r1, [r3, #0]
  32973. 800ea50: 6808 ldr r0, [r1, #0]
  32974. 800ea52: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  32975. 800ea56: f01e 0f10 tst.w lr, #16
  32976. 800ea5a: bf08 it eq
  32977. 800ea5c: ecb0 8a10 vldmiaeq r0!, {s16-s31}
  32978. 800ea60: f380 8809 msr PSP, r0
  32979. 800ea64: f3bf 8f6f isb sy
  32980. 800ea68: 4770 bx lr
  32981. 800ea6a: bf00 nop
  32982. 800ea6c: f3af 8000 nop.w
  32983. 0800ea70 <pxCurrentTCBConst>:
  32984. 800ea70: 24003040 .word 0x24003040
  32985. 0800ea74 <xPortSysTickHandler>:
  32986. {
  32987. 800ea74: b508 push {r3, lr}
  32988. __asm volatile
  32989. 800ea76: f04f 0350 mov.w r3, #80 @ 0x50
  32990. 800ea7a: f383 8811 msr BASEPRI, r3
  32991. 800ea7e: f3bf 8f6f isb sy
  32992. 800ea82: f3bf 8f4f dsb sy
  32993. if( xTaskIncrementTick() != pdFALSE )
  32994. 800ea86: f7fe ffa3 bl 800d9d0 <xTaskIncrementTick>
  32995. 800ea8a: b128 cbz r0, 800ea98 <xPortSysTickHandler+0x24>
  32996. portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
  32997. 800ea8c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  32998. 800ea90: f04f 5280 mov.w r2, #268435456 @ 0x10000000
  32999. 800ea94: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04
  33000. __asm volatile
  33001. 800ea98: 2300 movs r3, #0
  33002. 800ea9a: f383 8811 msr BASEPRI, r3
  33003. }
  33004. 800ea9e: bd08 pop {r3, pc}
  33005. 0800eaa0 <vPortSetupTimerInterrupt>:
  33006. portNVIC_SYSTICK_CTRL_REG = 0UL;
  33007. 800eaa0: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000
  33008. 800eaa4: 2300 movs r3, #0
  33009. portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
  33010. 800eaa6: 4806 ldr r0, [pc, #24] @ (800eac0 <vPortSetupTimerInterrupt+0x20>)
  33011. portNVIC_SYSTICK_CTRL_REG = 0UL;
  33012. 800eaa8: 6113 str r3, [r2, #16]
  33013. portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
  33014. 800eaaa: 4906 ldr r1, [pc, #24] @ (800eac4 <vPortSetupTimerInterrupt+0x24>)
  33015. portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
  33016. 800eaac: 6193 str r3, [r2, #24]
  33017. portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
  33018. 800eaae: 6803 ldr r3, [r0, #0]
  33019. portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
  33020. 800eab0: 2007 movs r0, #7
  33021. portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
  33022. 800eab2: fba1 1303 umull r1, r3, r1, r3
  33023. 800eab6: 099b lsrs r3, r3, #6
  33024. 800eab8: 3b01 subs r3, #1
  33025. 800eaba: 6153 str r3, [r2, #20]
  33026. portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
  33027. 800eabc: 6110 str r0, [r2, #16]
  33028. }
  33029. 800eabe: 4770 bx lr
  33030. 800eac0: 24000038 .word 0x24000038
  33031. 800eac4: 10624dd3 .word 0x10624dd3
  33032. 0800eac8 <xPortStartScheduler>:
  33033. configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
  33034. 800eac8: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  33035. 800eacc: 4a48 ldr r2, [pc, #288] @ (800ebf0 <xPortStartScheduler+0x128>)
  33036. 800eace: f8d3 1d00 ldr.w r1, [r3, #3328] @ 0xd00
  33037. 800ead2: 4291 cmp r1, r2
  33038. 800ead4: d041 beq.n 800eb5a <xPortStartScheduler+0x92>
  33039. configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
  33040. 800ead6: f8d3 2d00 ldr.w r2, [r3, #3328] @ 0xd00
  33041. 800eada: 4b46 ldr r3, [pc, #280] @ (800ebf4 <xPortStartScheduler+0x12c>)
  33042. 800eadc: 429a cmp r2, r3
  33043. 800eade: d033 beq.n 800eb48 <xPortStartScheduler+0x80>
  33044. ulOriginalPriority = *pucFirstUserPriorityRegister;
  33045. 800eae0: 4b45 ldr r3, [pc, #276] @ (800ebf8 <xPortStartScheduler+0x130>)
  33046. *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
  33047. 800eae2: f04f 0cff mov.w ip, #255 @ 0xff
  33048. ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
  33049. 800eae6: 4845 ldr r0, [pc, #276] @ (800ebfc <xPortStartScheduler+0x134>)
  33050. ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
  33051. 800eae8: 4945 ldr r1, [pc, #276] @ (800ec00 <xPortStartScheduler+0x138>)
  33052. {
  33053. 800eaea: b570 push {r4, r5, r6, lr}
  33054. ulOriginalPriority = *pucFirstUserPriorityRegister;
  33055. 800eaec: 781a ldrb r2, [r3, #0]
  33056. {
  33057. 800eaee: b084 sub sp, #16
  33058. ulOriginalPriority = *pucFirstUserPriorityRegister;
  33059. 800eaf0: b2d2 uxtb r2, r2
  33060. 800eaf2: 9202 str r2, [sp, #8]
  33061. ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
  33062. 800eaf4: 2207 movs r2, #7
  33063. *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
  33064. 800eaf6: f883 c000 strb.w ip, [r3]
  33065. ucMaxPriorityValue = *pucFirstUserPriorityRegister;
  33066. 800eafa: 781b ldrb r3, [r3, #0]
  33067. ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
  33068. 800eafc: 6002 str r2, [r0, #0]
  33069. ucMaxPriorityValue = *pucFirstUserPriorityRegister;
  33070. 800eafe: b2db uxtb r3, r3
  33071. 800eb00: f88d 3007 strb.w r3, [sp, #7]
  33072. ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
  33073. 800eb04: f89d 3007 ldrb.w r3, [sp, #7]
  33074. while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
  33075. 800eb08: f89d 2007 ldrb.w r2, [sp, #7]
  33076. ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
  33077. 800eb0c: f003 0350 and.w r3, r3, #80 @ 0x50
  33078. while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
  33079. 800eb10: 0612 lsls r2, r2, #24
  33080. ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
  33081. 800eb12: 700b strb r3, [r1, #0]
  33082. while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
  33083. 800eb14: d50f bpl.n 800eb36 <xPortStartScheduler+0x6e>
  33084. 800eb16: 2206 movs r2, #6
  33085. ucMaxPriorityValue <<= ( uint8_t ) 0x01;
  33086. 800eb18: f89d 3007 ldrb.w r3, [sp, #7]
  33087. 800eb1c: 4611 mov r1, r2
  33088. while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
  33089. 800eb1e: 3a01 subs r2, #1
  33090. ucMaxPriorityValue <<= ( uint8_t ) 0x01;
  33091. 800eb20: 005b lsls r3, r3, #1
  33092. 800eb22: b2db uxtb r3, r3
  33093. 800eb24: f88d 3007 strb.w r3, [sp, #7]
  33094. while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
  33095. 800eb28: f89d 3007 ldrb.w r3, [sp, #7]
  33096. 800eb2c: 061b lsls r3, r3, #24
  33097. 800eb2e: d4f3 bmi.n 800eb18 <xPortStartScheduler+0x50>
  33098. configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
  33099. 800eb30: 2903 cmp r1, #3
  33100. 800eb32: d01b beq.n 800eb6c <xPortStartScheduler+0xa4>
  33101. 800eb34: 6001 str r1, [r0, #0]
  33102. __asm volatile
  33103. 800eb36: f04f 0350 mov.w r3, #80 @ 0x50
  33104. 800eb3a: f383 8811 msr BASEPRI, r3
  33105. 800eb3e: f3bf 8f6f isb sy
  33106. 800eb42: f3bf 8f4f dsb sy
  33107. 800eb46: e7fe b.n 800eb46 <xPortStartScheduler+0x7e>
  33108. 800eb48: f04f 0350 mov.w r3, #80 @ 0x50
  33109. 800eb4c: f383 8811 msr BASEPRI, r3
  33110. 800eb50: f3bf 8f6f isb sy
  33111. 800eb54: f3bf 8f4f dsb sy
  33112. configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
  33113. 800eb58: e7fe b.n 800eb58 <xPortStartScheduler+0x90>
  33114. 800eb5a: f04f 0350 mov.w r3, #80 @ 0x50
  33115. 800eb5e: f383 8811 msr BASEPRI, r3
  33116. 800eb62: f3bf 8f6f isb sy
  33117. 800eb66: f3bf 8f4f dsb sy
  33118. configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
  33119. 800eb6a: e7fe b.n 800eb6a <xPortStartScheduler+0xa2>
  33120. *pucFirstUserPriorityRegister = ulOriginalPriority;
  33121. 800eb6c: 9b02 ldr r3, [sp, #8]
  33122. portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
  33123. 800eb6e: f04f 24e0 mov.w r4, #3758153728 @ 0xe000e000
  33124. ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
  33125. 800eb72: f44f 7140 mov.w r1, #768 @ 0x300
  33126. *pucFirstUserPriorityRegister = ulOriginalPriority;
  33127. 800eb76: 4a20 ldr r2, [pc, #128] @ (800ebf8 <xPortStartScheduler+0x130>)
  33128. 800eb78: b2db uxtb r3, r3
  33129. uxCriticalNesting = 0;
  33130. 800eb7a: 4e22 ldr r6, [pc, #136] @ (800ec04 <xPortStartScheduler+0x13c>)
  33131. ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
  33132. 800eb7c: 6001 str r1, [r0, #0]
  33133. uxCriticalNesting = 0;
  33134. 800eb7e: 2500 movs r5, #0
  33135. *pucFirstUserPriorityRegister = ulOriginalPriority;
  33136. 800eb80: 7013 strb r3, [r2, #0]
  33137. portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
  33138. 800eb82: f8d4 3d20 ldr.w r3, [r4, #3360] @ 0xd20
  33139. 800eb86: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
  33140. 800eb8a: f8c4 3d20 str.w r3, [r4, #3360] @ 0xd20
  33141. portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
  33142. 800eb8e: f8d4 3d20 ldr.w r3, [r4, #3360] @ 0xd20
  33143. 800eb92: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000
  33144. 800eb96: f8c4 3d20 str.w r3, [r4, #3360] @ 0xd20
  33145. vPortSetupTimerInterrupt();
  33146. 800eb9a: f7ff ff81 bl 800eaa0 <vPortSetupTimerInterrupt>
  33147. uxCriticalNesting = 0;
  33148. 800eb9e: 6035 str r5, [r6, #0]
  33149. vPortEnableVFP();
  33150. 800eba0: f7ff feaa bl 800e8f8 <vPortEnableVFP>
  33151. *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
  33152. 800eba4: f8d4 3f34 ldr.w r3, [r4, #3892] @ 0xf34
  33153. 800eba8: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000
  33154. 800ebac: f8c4 3f34 str.w r3, [r4, #3892] @ 0xf34
  33155. prvPortStartFirstTask();
  33156. 800ebb0: f7ff fe8e bl 800e8d0 <prvPortStartFirstTask>
  33157. vTaskSwitchContext();
  33158. 800ebb4: f7fe ff1c bl 800d9f0 <vTaskSwitchContext>
  33159. configASSERT( uxCriticalNesting == ~0UL );
  33160. 800ebb8: 6833 ldr r3, [r6, #0]
  33161. volatile uint32_t ulDummy = 0;
  33162. 800ebba: 9503 str r5, [sp, #12]
  33163. configASSERT( uxCriticalNesting == ~0UL );
  33164. 800ebbc: 3301 adds r3, #1
  33165. 800ebbe: d008 beq.n 800ebd2 <xPortStartScheduler+0x10a>
  33166. 800ebc0: f04f 0350 mov.w r3, #80 @ 0x50
  33167. 800ebc4: f383 8811 msr BASEPRI, r3
  33168. 800ebc8: f3bf 8f6f isb sy
  33169. 800ebcc: f3bf 8f4f dsb sy
  33170. 800ebd0: e7fe b.n 800ebd0 <xPortStartScheduler+0x108>
  33171. 800ebd2: f04f 0350 mov.w r3, #80 @ 0x50
  33172. 800ebd6: f383 8811 msr BASEPRI, r3
  33173. 800ebda: f3bf 8f6f isb sy
  33174. 800ebde: f3bf 8f4f dsb sy
  33175. while( ulDummy == 0 )
  33176. 800ebe2: 9b03 ldr r3, [sp, #12]
  33177. 800ebe4: 2b00 cmp r3, #0
  33178. 800ebe6: d0fc beq.n 800ebe2 <xPortStartScheduler+0x11a>
  33179. }
  33180. 800ebe8: 2000 movs r0, #0
  33181. 800ebea: b004 add sp, #16
  33182. 800ebec: bd70 pop {r4, r5, r6, pc}
  33183. 800ebee: bf00 nop
  33184. 800ebf0: 410fc271 .word 0x410fc271
  33185. 800ebf4: 410fc270 .word 0x410fc270
  33186. 800ebf8: e000e400 .word 0xe000e400
  33187. 800ebfc: 24003170 .word 0x24003170
  33188. 800ec00: 24003174 .word 0x24003174
  33189. 800ec04: 24000044 .word 0x24000044
  33190. 0800ec08 <vPortValidateInterruptPriority>:
  33191. {
  33192. uint32_t ulCurrentInterrupt;
  33193. uint8_t ucCurrentPriority;
  33194. /* Obtain the number of the currently executing interrupt. */
  33195. __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
  33196. 800ec08: f3ef 8305 mrs r3, IPSR
  33197. /* Is the interrupt number a user defined interrupt? */
  33198. if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
  33199. 800ec0c: 2b0f cmp r3, #15
  33200. 800ec0e: d90e bls.n 800ec2e <vPortValidateInterruptPriority+0x26>
  33201. {
  33202. /* Look up the interrupt's priority. */
  33203. ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
  33204. 800ec10: 4911 ldr r1, [pc, #68] @ (800ec58 <vPortValidateInterruptPriority+0x50>)
  33205. interrupt entry is as fast and simple as possible.
  33206. The following links provide detailed information:
  33207. http://www.freertos.org/RTOS-Cortex-M3-M4.html
  33208. http://www.freertos.org/FAQHelp.html */
  33209. configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
  33210. 800ec12: 4a12 ldr r2, [pc, #72] @ (800ec5c <vPortValidateInterruptPriority+0x54>)
  33211. ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
  33212. 800ec14: 5c5b ldrb r3, [r3, r1]
  33213. configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
  33214. 800ec16: 7812 ldrb r2, [r2, #0]
  33215. 800ec18: 429a cmp r2, r3
  33216. 800ec1a: d908 bls.n 800ec2e <vPortValidateInterruptPriority+0x26>
  33217. 800ec1c: f04f 0350 mov.w r3, #80 @ 0x50
  33218. 800ec20: f383 8811 msr BASEPRI, r3
  33219. 800ec24: f3bf 8f6f isb sy
  33220. 800ec28: f3bf 8f4f dsb sy
  33221. 800ec2c: e7fe b.n 800ec2c <vPortValidateInterruptPriority+0x24>
  33222. configuration then the correct setting can be achieved on all Cortex-M
  33223. devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
  33224. scheduler. Note however that some vendor specific peripheral libraries
  33225. assume a non-zero priority group setting, in which cases using a value
  33226. of zero will result in unpredictable behaviour. */
  33227. configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
  33228. 800ec2e: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
  33229. 800ec32: 4a0b ldr r2, [pc, #44] @ (800ec60 <vPortValidateInterruptPriority+0x58>)
  33230. 800ec34: f8d3 3d0c ldr.w r3, [r3, #3340] @ 0xd0c
  33231. 800ec38: 6812 ldr r2, [r2, #0]
  33232. 800ec3a: f403 63e0 and.w r3, r3, #1792 @ 0x700
  33233. 800ec3e: 4293 cmp r3, r2
  33234. 800ec40: d908 bls.n 800ec54 <vPortValidateInterruptPriority+0x4c>
  33235. 800ec42: f04f 0350 mov.w r3, #80 @ 0x50
  33236. 800ec46: f383 8811 msr BASEPRI, r3
  33237. 800ec4a: f3bf 8f6f isb sy
  33238. 800ec4e: f3bf 8f4f dsb sy
  33239. 800ec52: e7fe b.n 800ec52 <vPortValidateInterruptPriority+0x4a>
  33240. }
  33241. 800ec54: 4770 bx lr
  33242. 800ec56: bf00 nop
  33243. 800ec58: e000e3f0 .word 0xe000e3f0
  33244. 800ec5c: 24003174 .word 0x24003174
  33245. 800ec60: 24003170 .word 0x24003170
  33246. 0800ec64 <pvPortMalloc>:
  33247. static size_t xBlockAllocatedBit = 0;
  33248. /*-----------------------------------------------------------*/
  33249. void *pvPortMalloc( size_t xWantedSize )
  33250. {
  33251. 800ec64: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  33252. 800ec68: 4604 mov r4, r0
  33253. BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
  33254. void *pvReturn = NULL;
  33255. vTaskSuspendAll();
  33256. 800ec6a: f7fe fe93 bl 800d994 <vTaskSuspendAll>
  33257. {
  33258. /* If this is the first call to malloc then the heap will require
  33259. initialisation to setup the list of free blocks. */
  33260. if( pxEnd == NULL )
  33261. 800ec6e: 4a53 ldr r2, [pc, #332] @ (800edbc <pvPortMalloc+0x158>)
  33262. 800ec70: 6815 ldr r5, [r2, #0]
  33263. 800ec72: 2d00 cmp r5, #0
  33264. 800ec74: d035 beq.n 800ece2 <pvPortMalloc+0x7e>
  33265. /* Check the requested block size is not so large that the top bit is
  33266. set. The top bit of the block size member of the BlockLink_t structure
  33267. is used to determine who owns the block - the application or the
  33268. kernel, so it must be free. */
  33269. if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
  33270. 800ec76: 4b52 ldr r3, [pc, #328] @ (800edc0 <pvPortMalloc+0x15c>)
  33271. 800ec78: 681e ldr r6, [r3, #0]
  33272. 800ec7a: 4234 tst r4, r6
  33273. 800ec7c: d12b bne.n 800ecd6 <pvPortMalloc+0x72>
  33274. {
  33275. /* The wanted size is increased so it can contain a BlockLink_t
  33276. structure in addition to the requested amount of bytes. */
  33277. if( xWantedSize > 0 )
  33278. 800ec7e: b354 cbz r4, 800ecd6 <pvPortMalloc+0x72>
  33279. {
  33280. xWantedSize += xHeapStructSize;
  33281. 800ec80: f104 0008 add.w r0, r4, #8
  33282. /* Ensure that blocks are always aligned to the required number
  33283. of bytes. */
  33284. if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
  33285. 800ec84: 0764 lsls r4, r4, #29
  33286. 800ec86: d002 beq.n 800ec8e <pvPortMalloc+0x2a>
  33287. {
  33288. /* Byte alignment required. */
  33289. xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
  33290. 800ec88: f020 0007 bic.w r0, r0, #7
  33291. 800ec8c: 3008 adds r0, #8
  33292. else
  33293. {
  33294. mtCOVERAGE_TEST_MARKER();
  33295. }
  33296. if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
  33297. 800ec8e: b310 cbz r0, 800ecd6 <pvPortMalloc+0x72>
  33298. 800ec90: f8df e140 ldr.w lr, [pc, #320] @ 800edd4 <pvPortMalloc+0x170>
  33299. 800ec94: f8de c000 ldr.w ip, [lr]
  33300. 800ec98: 4584 cmp ip, r0
  33301. 800ec9a: d31c bcc.n 800ecd6 <pvPortMalloc+0x72>
  33302. {
  33303. /* Traverse the list from the start (lowest address) block until
  33304. one of adequate size is found. */
  33305. pxPreviousBlock = &xStart;
  33306. pxBlock = xStart.pxNextFreeBlock;
  33307. 800ec9c: 4c49 ldr r4, [pc, #292] @ (800edc4 <pvPortMalloc+0x160>)
  33308. 800ec9e: 6823 ldr r3, [r4, #0]
  33309. while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
  33310. 800eca0: e003 b.n 800ecaa <pvPortMalloc+0x46>
  33311. 800eca2: 681a ldr r2, [r3, #0]
  33312. 800eca4: b122 cbz r2, 800ecb0 <pvPortMalloc+0x4c>
  33313. 800eca6: 461c mov r4, r3
  33314. 800eca8: 4613 mov r3, r2
  33315. 800ecaa: 6859 ldr r1, [r3, #4]
  33316. 800ecac: 4281 cmp r1, r0
  33317. 800ecae: d3f8 bcc.n 800eca2 <pvPortMalloc+0x3e>
  33318. pxBlock = pxBlock->pxNextFreeBlock;
  33319. }
  33320. /* If the end marker was reached then a block of adequate size
  33321. was not found. */
  33322. if( pxBlock != pxEnd )
  33323. 800ecb0: 42ab cmp r3, r5
  33324. 800ecb2: d010 beq.n 800ecd6 <pvPortMalloc+0x72>
  33325. BlockLink_t structure at its start. */
  33326. pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
  33327. /* This block is being returned for use so must be taken out
  33328. of the list of free blocks. */
  33329. pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
  33330. 800ecb4: 681a ldr r2, [r3, #0]
  33331. 800ecb6: 6022 str r2, [r4, #0]
  33332. /* If the block is larger than required it can be split into
  33333. two. */
  33334. if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
  33335. 800ecb8: 1a0a subs r2, r1, r0
  33336. 800ecba: 2a10 cmp r2, #16
  33337. 800ecbc: d947 bls.n 800ed4e <pvPortMalloc+0xea>
  33338. {
  33339. /* This block is to be split into two. Create a new
  33340. block following the number of bytes requested. The void
  33341. cast is used to prevent byte alignment warnings from the
  33342. compiler. */
  33343. pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
  33344. 800ecbe: 181c adds r4, r3, r0
  33345. configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
  33346. 800ecc0: 0761 lsls r1, r4, #29
  33347. 800ecc2: d02d beq.n 800ed20 <pvPortMalloc+0xbc>
  33348. 800ecc4: f04f 0350 mov.w r3, #80 @ 0x50
  33349. 800ecc8: f383 8811 msr BASEPRI, r3
  33350. 800eccc: f3bf 8f6f isb sy
  33351. 800ecd0: f3bf 8f4f dsb sy
  33352. 800ecd4: e7fe b.n 800ecd4 <pvPortMalloc+0x70>
  33353. void *pvReturn = NULL;
  33354. 800ecd6: 2400 movs r4, #0
  33355. mtCOVERAGE_TEST_MARKER();
  33356. }
  33357. traceMALLOC( pvReturn, xWantedSize );
  33358. }
  33359. ( void ) xTaskResumeAll();
  33360. 800ecd8: f7fe fe64 bl 800d9a4 <xTaskResumeAll>
  33361. }
  33362. #endif
  33363. configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
  33364. return pvReturn;
  33365. }
  33366. 800ecdc: 4620 mov r0, r4
  33367. 800ecde: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  33368. uint8_t *pucAlignedHeap;
  33369. size_t uxAddress;
  33370. size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
  33371. /* Ensure the heap starts on a correctly aligned boundary. */
  33372. uxAddress = ( size_t ) ucHeap;
  33373. 800ece2: 4b39 ldr r3, [pc, #228] @ (800edc8 <pvPortMalloc+0x164>)
  33374. /* Only one block exists - and it covers the entire usable heap space. */
  33375. xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
  33376. xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
  33377. /* Work out the position of the top bit in a size_t variable. */
  33378. xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
  33379. 800ece4: f04f 4000 mov.w r0, #2147483648 @ 0x80000000
  33380. xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
  33381. 800ece8: 4e36 ldr r6, [pc, #216] @ (800edc4 <pvPortMalloc+0x160>)
  33382. if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
  33383. 800ecea: 075d lsls r5, r3, #29
  33384. uxAddress -= xHeapStructSize;
  33385. 800ecec: 4d37 ldr r5, [pc, #220] @ (800edcc <pvPortMalloc+0x168>)
  33386. uxAddress += ( portBYTE_ALIGNMENT - 1 );
  33387. 800ecee: bf18 it ne
  33388. 800ecf0: 3307 addne r3, #7
  33389. uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
  33390. 800ecf2: f025 0507 bic.w r5, r5, #7
  33391. uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
  33392. 800ecf6: bf18 it ne
  33393. 800ecf8: f023 0307 bicne.w r3, r3, #7
  33394. pxEnd = ( void * ) uxAddress;
  33395. 800ecfc: 6015 str r5, [r2, #0]
  33396. xStart.xBlockSize = ( size_t ) 0;
  33397. 800ecfe: 2200 movs r2, #0
  33398. xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
  33399. 800ed00: 6033 str r3, [r6, #0]
  33400. 800ed02: 4619 mov r1, r3
  33401. xStart.xBlockSize = ( size_t ) 0;
  33402. 800ed04: 6072 str r2, [r6, #4]
  33403. pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
  33404. 800ed06: 1aeb subs r3, r5, r3
  33405. }
  33406. 800ed08: 4606 mov r6, r0
  33407. pxEnd->pxNextFreeBlock = NULL;
  33408. 800ed0a: e9c5 2200 strd r2, r2, [r5]
  33409. xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
  33410. 800ed0e: 4a30 ldr r2, [pc, #192] @ (800edd0 <pvPortMalloc+0x16c>)
  33411. 800ed10: 6013 str r3, [r2, #0]
  33412. xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
  33413. 800ed12: 4a30 ldr r2, [pc, #192] @ (800edd4 <pvPortMalloc+0x170>)
  33414. pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
  33415. 800ed14: e9c1 5300 strd r5, r3, [r1]
  33416. xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
  33417. 800ed18: 6013 str r3, [r2, #0]
  33418. xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
  33419. 800ed1a: 4b29 ldr r3, [pc, #164] @ (800edc0 <pvPortMalloc+0x15c>)
  33420. 800ed1c: 6018 str r0, [r3, #0]
  33421. }
  33422. 800ed1e: e7ac b.n 800ec7a <pvPortMalloc+0x16>
  33423. pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
  33424. 800ed20: 6062 str r2, [r4, #4]
  33425. BlockLink_t *pxIterator;
  33426. uint8_t *puc;
  33427. /* Iterate through the list until a block is found that has a higher address
  33428. than the block being inserted. */
  33429. for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
  33430. 800ed22: 4a28 ldr r2, [pc, #160] @ (800edc4 <pvPortMalloc+0x160>)
  33431. pxBlock->xBlockSize = xWantedSize;
  33432. 800ed24: 6058 str r0, [r3, #4]
  33433. for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
  33434. 800ed26: 4617 mov r7, r2
  33435. 800ed28: 6812 ldr r2, [r2, #0]
  33436. 800ed2a: 4294 cmp r4, r2
  33437. 800ed2c: d8fb bhi.n 800ed26 <pvPortMalloc+0xc2>
  33438. }
  33439. /* Do the block being inserted, and the block it is being inserted after
  33440. make a contiguous block of memory? */
  33441. puc = ( uint8_t * ) pxIterator;
  33442. if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
  33443. 800ed2e: 6879 ldr r1, [r7, #4]
  33444. {
  33445. pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
  33446. 800ed30: f8d4 8004 ldr.w r8, [r4, #4]
  33447. if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
  33448. 800ed34: eb07 0901 add.w r9, r7, r1
  33449. 800ed38: 454c cmp r4, r9
  33450. 800ed3a: d028 beq.n 800ed8e <pvPortMalloc+0x12a>
  33451. }
  33452. /* Do the block being inserted, and the block it is being inserted before
  33453. make a contiguous block of memory? */
  33454. puc = ( uint8_t * ) pxBlockToInsert;
  33455. if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
  33456. 800ed3c: eb04 0108 add.w r1, r4, r8
  33457. 800ed40: 428a cmp r2, r1
  33458. 800ed42: d02e beq.n 800eda2 <pvPortMalloc+0x13e>
  33459. pxBlockToInsert->pxNextFreeBlock = pxEnd;
  33460. }
  33461. }
  33462. else
  33463. {
  33464. pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
  33465. 800ed44: 4601 mov r1, r0
  33466. 800ed46: 6022 str r2, [r4, #0]
  33467. /* If the block being inserted plugged a gab, so was merged with the block
  33468. before and the block after, then it's pxNextFreeBlock pointer will have
  33469. already been set, and should not be set here as that would make it point
  33470. to itself. */
  33471. if( pxIterator != pxBlockToInsert )
  33472. 800ed48: 42a7 cmp r7, r4
  33473. {
  33474. pxIterator->pxNextFreeBlock = pxBlockToInsert;
  33475. 800ed4a: bf18 it ne
  33476. 800ed4c: 603c strne r4, [r7, #0]
  33477. if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
  33478. 800ed4e: 4820 ldr r0, [pc, #128] @ (800edd0 <pvPortMalloc+0x16c>)
  33479. xFreeBytesRemaining -= pxBlock->xBlockSize;
  33480. 800ed50: ebac 0201 sub.w r2, ip, r1
  33481. pxBlock->pxNextFreeBlock = NULL;
  33482. 800ed54: 2500 movs r5, #0
  33483. pxBlock->xBlockSize |= xBlockAllocatedBit;
  33484. 800ed56: 4331 orrs r1, r6
  33485. if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
  33486. 800ed58: 6804 ldr r4, [r0, #0]
  33487. xFreeBytesRemaining -= pxBlock->xBlockSize;
  33488. 800ed5a: f8ce 2000 str.w r2, [lr]
  33489. if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
  33490. 800ed5e: 42a2 cmp r2, r4
  33491. pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
  33492. 800ed60: f103 0408 add.w r4, r3, #8
  33493. pxBlock->xBlockSize |= xBlockAllocatedBit;
  33494. 800ed64: 6059 str r1, [r3, #4]
  33495. xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
  33496. 800ed66: bf38 it cc
  33497. 800ed68: 6002 strcc r2, [r0, #0]
  33498. xNumberOfSuccessfulAllocations++;
  33499. 800ed6a: 481b ldr r0, [pc, #108] @ (800edd8 <pvPortMalloc+0x174>)
  33500. pxBlock->pxNextFreeBlock = NULL;
  33501. 800ed6c: 601d str r5, [r3, #0]
  33502. xNumberOfSuccessfulAllocations++;
  33503. 800ed6e: 6802 ldr r2, [r0, #0]
  33504. 800ed70: 3201 adds r2, #1
  33505. 800ed72: 6002 str r2, [r0, #0]
  33506. ( void ) xTaskResumeAll();
  33507. 800ed74: f7fe fe16 bl 800d9a4 <xTaskResumeAll>
  33508. configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
  33509. 800ed78: 0763 lsls r3, r4, #29
  33510. 800ed7a: d0af beq.n 800ecdc <pvPortMalloc+0x78>
  33511. 800ed7c: f04f 0350 mov.w r3, #80 @ 0x50
  33512. 800ed80: f383 8811 msr BASEPRI, r3
  33513. 800ed84: f3bf 8f6f isb sy
  33514. 800ed88: f3bf 8f4f dsb sy
  33515. 800ed8c: e7fe b.n 800ed8c <pvPortMalloc+0x128>
  33516. pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
  33517. 800ed8e: 4488 add r8, r1
  33518. if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
  33519. 800ed90: eb07 0108 add.w r1, r7, r8
  33520. pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
  33521. 800ed94: f8c7 8004 str.w r8, [r7, #4]
  33522. if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
  33523. 800ed98: 428a cmp r2, r1
  33524. 800ed9a: d001 beq.n 800eda0 <pvPortMalloc+0x13c>
  33525. xFreeBytesRemaining -= pxBlock->xBlockSize;
  33526. 800ed9c: 6859 ldr r1, [r3, #4]
  33527. 800ed9e: e7d6 b.n 800ed4e <pvPortMalloc+0xea>
  33528. if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
  33529. 800eda0: 463c mov r4, r7
  33530. if( pxIterator->pxNextFreeBlock != pxEnd )
  33531. 800eda2: 42aa cmp r2, r5
  33532. 800eda4: d006 beq.n 800edb4 <pvPortMalloc+0x150>
  33533. pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
  33534. 800eda6: 6851 ldr r1, [r2, #4]
  33535. pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
  33536. 800eda8: 6812 ldr r2, [r2, #0]
  33537. pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
  33538. 800edaa: 4441 add r1, r8
  33539. pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
  33540. 800edac: 6022 str r2, [r4, #0]
  33541. pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
  33542. 800edae: 6061 str r1, [r4, #4]
  33543. xFreeBytesRemaining -= pxBlock->xBlockSize;
  33544. 800edb0: 6859 ldr r1, [r3, #4]
  33545. 800edb2: e7c9 b.n 800ed48 <pvPortMalloc+0xe4>
  33546. 800edb4: 6859 ldr r1, [r3, #4]
  33547. pxBlockToInsert->pxNextFreeBlock = pxEnd;
  33548. 800edb6: 6022 str r2, [r4, #0]
  33549. 800edb8: e7c6 b.n 800ed48 <pvPortMalloc+0xe4>
  33550. 800edba: bf00 nop
  33551. 800edbc: 2400318c .word 0x2400318c
  33552. 800edc0: 24003178 .word 0x24003178
  33553. 800edc4: 24003190 .word 0x24003190
  33554. 800edc8: 24003198 .word 0x24003198
  33555. 800edcc: 24013190 .word 0x24013190
  33556. 800edd0: 24003184 .word 0x24003184
  33557. 800edd4: 24003188 .word 0x24003188
  33558. 800edd8: 24003180 .word 0x24003180
  33559. 0800eddc <vPortFree>:
  33560. if( pv != NULL )
  33561. 800eddc: b1d0 cbz r0, 800ee14 <vPortFree+0x38>
  33562. configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
  33563. 800edde: 4a2d ldr r2, [pc, #180] @ (800ee94 <vPortFree+0xb8>)
  33564. 800ede0: f850 3c04 ldr.w r3, [r0, #-4]
  33565. 800ede4: 6812 ldr r2, [r2, #0]
  33566. 800ede6: 4213 tst r3, r2
  33567. 800ede8: d00b beq.n 800ee02 <vPortFree+0x26>
  33568. configASSERT( pxLink->pxNextFreeBlock == NULL );
  33569. 800edea: f850 1c08 ldr.w r1, [r0, #-8]
  33570. 800edee: b191 cbz r1, 800ee16 <vPortFree+0x3a>
  33571. 800edf0: f04f 0350 mov.w r3, #80 @ 0x50
  33572. 800edf4: f383 8811 msr BASEPRI, r3
  33573. 800edf8: f3bf 8f6f isb sy
  33574. 800edfc: f3bf 8f4f dsb sy
  33575. 800ee00: e7fe b.n 800ee00 <vPortFree+0x24>
  33576. 800ee02: f04f 0350 mov.w r3, #80 @ 0x50
  33577. 800ee06: f383 8811 msr BASEPRI, r3
  33578. 800ee0a: f3bf 8f6f isb sy
  33579. 800ee0e: f3bf 8f4f dsb sy
  33580. configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
  33581. 800ee12: e7fe b.n 800ee12 <vPortFree+0x36>
  33582. 800ee14: 4770 bx lr
  33583. pxLink->xBlockSize &= ~xBlockAllocatedBit;
  33584. 800ee16: ea23 0302 bic.w r3, r3, r2
  33585. {
  33586. 800ee1a: b530 push {r4, r5, lr}
  33587. 800ee1c: b083 sub sp, #12
  33588. pxLink->xBlockSize &= ~xBlockAllocatedBit;
  33589. 800ee1e: f840 3c04 str.w r3, [r0, #-4]
  33590. puc -= xHeapStructSize;
  33591. 800ee22: f1a0 0408 sub.w r4, r0, #8
  33592. pxLink->xBlockSize &= ~xBlockAllocatedBit;
  33593. 800ee26: 9001 str r0, [sp, #4]
  33594. vTaskSuspendAll();
  33595. 800ee28: f7fe fdb4 bl 800d994 <vTaskSuspendAll>
  33596. xFreeBytesRemaining += pxLink->xBlockSize;
  33597. 800ee2c: 4a1a ldr r2, [pc, #104] @ (800ee98 <vPortFree+0xbc>)
  33598. 800ee2e: 9801 ldr r0, [sp, #4]
  33599. 800ee30: 6813 ldr r3, [r2, #0]
  33600. 800ee32: f850 1c04 ldr.w r1, [r0, #-4]
  33601. 800ee36: 440b add r3, r1
  33602. 800ee38: 6013 str r3, [r2, #0]
  33603. for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
  33604. 800ee3a: 4b18 ldr r3, [pc, #96] @ (800ee9c <vPortFree+0xc0>)
  33605. 800ee3c: 461a mov r2, r3
  33606. 800ee3e: 681b ldr r3, [r3, #0]
  33607. 800ee40: 429c cmp r4, r3
  33608. 800ee42: d8fb bhi.n 800ee3c <vPortFree+0x60>
  33609. if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
  33610. 800ee44: 6855 ldr r5, [r2, #4]
  33611. 800ee46: eb02 0e05 add.w lr, r2, r5
  33612. 800ee4a: 4574 cmp r4, lr
  33613. 800ee4c: d011 beq.n 800ee72 <vPortFree+0x96>
  33614. if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
  33615. 800ee4e: eb04 0c01 add.w ip, r4, r1
  33616. 800ee52: 4563 cmp r3, ip
  33617. 800ee54: d013 beq.n 800ee7e <vPortFree+0xa2>
  33618. pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
  33619. 800ee56: f840 3c08 str.w r3, [r0, #-8]
  33620. if( pxIterator != pxBlockToInsert )
  33621. 800ee5a: 42a2 cmp r2, r4
  33622. pxIterator->pxNextFreeBlock = pxBlockToInsert;
  33623. 800ee5c: bf18 it ne
  33624. 800ee5e: 6014 strne r4, [r2, #0]
  33625. xNumberOfSuccessfulFrees++;
  33626. 800ee60: 4a0f ldr r2, [pc, #60] @ (800eea0 <vPortFree+0xc4>)
  33627. 800ee62: 6813 ldr r3, [r2, #0]
  33628. 800ee64: 3301 adds r3, #1
  33629. 800ee66: 6013 str r3, [r2, #0]
  33630. }
  33631. 800ee68: b003 add sp, #12
  33632. 800ee6a: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
  33633. ( void ) xTaskResumeAll();
  33634. 800ee6e: f7fe bd99 b.w 800d9a4 <xTaskResumeAll>
  33635. pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
  33636. 800ee72: 4429 add r1, r5
  33637. if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
  33638. 800ee74: 1850 adds r0, r2, r1
  33639. pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
  33640. 800ee76: 6051 str r1, [r2, #4]
  33641. if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
  33642. 800ee78: 4283 cmp r3, r0
  33643. 800ee7a: d1f1 bne.n 800ee60 <vPortFree+0x84>
  33644. 800ee7c: 4614 mov r4, r2
  33645. if( pxIterator->pxNextFreeBlock != pxEnd )
  33646. 800ee7e: 4809 ldr r0, [pc, #36] @ (800eea4 <vPortFree+0xc8>)
  33647. 800ee80: 6800 ldr r0, [r0, #0]
  33648. 800ee82: 4283 cmp r3, r0
  33649. 800ee84: d003 beq.n 800ee8e <vPortFree+0xb2>
  33650. pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
  33651. 800ee86: e9d3 0500 ldrd r0, r5, [r3]
  33652. pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
  33653. 800ee8a: 4429 add r1, r5
  33654. 800ee8c: 6061 str r1, [r4, #4]
  33655. pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
  33656. 800ee8e: 6020 str r0, [r4, #0]
  33657. 800ee90: e7e3 b.n 800ee5a <vPortFree+0x7e>
  33658. 800ee92: bf00 nop
  33659. 800ee94: 24003178 .word 0x24003178
  33660. 800ee98: 24003188 .word 0x24003188
  33661. 800ee9c: 24003190 .word 0x24003190
  33662. 800eea0: 2400317c .word 0x2400317c
  33663. 800eea4: 2400318c .word 0x2400318c
  33664. 0800eea8 <__cvt>:
  33665. 800eea8: b5f0 push {r4, r5, r6, r7, lr}
  33666. 800eeaa: ed2d 8b02 vpush {d8}
  33667. 800eeae: eeb0 8b40 vmov.f64 d8, d0
  33668. 800eeb2: b085 sub sp, #20
  33669. 800eeb4: 4617 mov r7, r2
  33670. 800eeb6: 9d0d ldr r5, [sp, #52] @ 0x34
  33671. 800eeb8: 9e0c ldr r6, [sp, #48] @ 0x30
  33672. 800eeba: ee18 2a90 vmov r2, s17
  33673. 800eebe: f025 0520 bic.w r5, r5, #32
  33674. 800eec2: 2a00 cmp r2, #0
  33675. 800eec4: bfb6 itet lt
  33676. 800eec6: 222d movlt r2, #45 @ 0x2d
  33677. 800eec8: 2200 movge r2, #0
  33678. 800eeca: eeb1 8b40 vneglt.f64 d8, d0
  33679. 800eece: 2d46 cmp r5, #70 @ 0x46
  33680. 800eed0: 460c mov r4, r1
  33681. 800eed2: 701a strb r2, [r3, #0]
  33682. 800eed4: d004 beq.n 800eee0 <__cvt+0x38>
  33683. 800eed6: 2d45 cmp r5, #69 @ 0x45
  33684. 800eed8: d100 bne.n 800eedc <__cvt+0x34>
  33685. 800eeda: 3401 adds r4, #1
  33686. 800eedc: 2102 movs r1, #2
  33687. 800eede: e000 b.n 800eee2 <__cvt+0x3a>
  33688. 800eee0: 2103 movs r1, #3
  33689. 800eee2: ab03 add r3, sp, #12
  33690. 800eee4: 9301 str r3, [sp, #4]
  33691. 800eee6: ab02 add r3, sp, #8
  33692. 800eee8: 9300 str r3, [sp, #0]
  33693. 800eeea: 4622 mov r2, r4
  33694. 800eeec: 4633 mov r3, r6
  33695. 800eeee: eeb0 0b48 vmov.f64 d0, d8
  33696. 800eef2: f000 ff75 bl 800fde0 <_dtoa_r>
  33697. 800eef6: 2d47 cmp r5, #71 @ 0x47
  33698. 800eef8: d114 bne.n 800ef24 <__cvt+0x7c>
  33699. 800eefa: 07fb lsls r3, r7, #31
  33700. 800eefc: d50a bpl.n 800ef14 <__cvt+0x6c>
  33701. 800eefe: 1902 adds r2, r0, r4
  33702. 800ef00: eeb5 8b40 vcmp.f64 d8, #0.0
  33703. 800ef04: eef1 fa10 vmrs APSR_nzcv, fpscr
  33704. 800ef08: bf08 it eq
  33705. 800ef0a: 9203 streq r2, [sp, #12]
  33706. 800ef0c: 2130 movs r1, #48 @ 0x30
  33707. 800ef0e: 9b03 ldr r3, [sp, #12]
  33708. 800ef10: 4293 cmp r3, r2
  33709. 800ef12: d319 bcc.n 800ef48 <__cvt+0xa0>
  33710. 800ef14: 9b03 ldr r3, [sp, #12]
  33711. 800ef16: 9a0e ldr r2, [sp, #56] @ 0x38
  33712. 800ef18: 1a1b subs r3, r3, r0
  33713. 800ef1a: 6013 str r3, [r2, #0]
  33714. 800ef1c: b005 add sp, #20
  33715. 800ef1e: ecbd 8b02 vpop {d8}
  33716. 800ef22: bdf0 pop {r4, r5, r6, r7, pc}
  33717. 800ef24: 2d46 cmp r5, #70 @ 0x46
  33718. 800ef26: eb00 0204 add.w r2, r0, r4
  33719. 800ef2a: d1e9 bne.n 800ef00 <__cvt+0x58>
  33720. 800ef2c: 7803 ldrb r3, [r0, #0]
  33721. 800ef2e: 2b30 cmp r3, #48 @ 0x30
  33722. 800ef30: d107 bne.n 800ef42 <__cvt+0x9a>
  33723. 800ef32: eeb5 8b40 vcmp.f64 d8, #0.0
  33724. 800ef36: eef1 fa10 vmrs APSR_nzcv, fpscr
  33725. 800ef3a: bf1c itt ne
  33726. 800ef3c: f1c4 0401 rsbne r4, r4, #1
  33727. 800ef40: 6034 strne r4, [r6, #0]
  33728. 800ef42: 6833 ldr r3, [r6, #0]
  33729. 800ef44: 441a add r2, r3
  33730. 800ef46: e7db b.n 800ef00 <__cvt+0x58>
  33731. 800ef48: 1c5c adds r4, r3, #1
  33732. 800ef4a: 9403 str r4, [sp, #12]
  33733. 800ef4c: 7019 strb r1, [r3, #0]
  33734. 800ef4e: e7de b.n 800ef0e <__cvt+0x66>
  33735. 0800ef50 <__exponent>:
  33736. 800ef50: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
  33737. 800ef52: 2900 cmp r1, #0
  33738. 800ef54: bfba itte lt
  33739. 800ef56: 4249 neglt r1, r1
  33740. 800ef58: 232d movlt r3, #45 @ 0x2d
  33741. 800ef5a: 232b movge r3, #43 @ 0x2b
  33742. 800ef5c: 2909 cmp r1, #9
  33743. 800ef5e: 7002 strb r2, [r0, #0]
  33744. 800ef60: 7043 strb r3, [r0, #1]
  33745. 800ef62: dd29 ble.n 800efb8 <__exponent+0x68>
  33746. 800ef64: f10d 0307 add.w r3, sp, #7
  33747. 800ef68: 461d mov r5, r3
  33748. 800ef6a: 270a movs r7, #10
  33749. 800ef6c: 461a mov r2, r3
  33750. 800ef6e: fbb1 f6f7 udiv r6, r1, r7
  33751. 800ef72: fb07 1416 mls r4, r7, r6, r1
  33752. 800ef76: 3430 adds r4, #48 @ 0x30
  33753. 800ef78: f802 4c01 strb.w r4, [r2, #-1]
  33754. 800ef7c: 460c mov r4, r1
  33755. 800ef7e: 2c63 cmp r4, #99 @ 0x63
  33756. 800ef80: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff
  33757. 800ef84: 4631 mov r1, r6
  33758. 800ef86: dcf1 bgt.n 800ef6c <__exponent+0x1c>
  33759. 800ef88: 3130 adds r1, #48 @ 0x30
  33760. 800ef8a: 1e94 subs r4, r2, #2
  33761. 800ef8c: f803 1c01 strb.w r1, [r3, #-1]
  33762. 800ef90: 1c41 adds r1, r0, #1
  33763. 800ef92: 4623 mov r3, r4
  33764. 800ef94: 42ab cmp r3, r5
  33765. 800ef96: d30a bcc.n 800efae <__exponent+0x5e>
  33766. 800ef98: f10d 0309 add.w r3, sp, #9
  33767. 800ef9c: 1a9b subs r3, r3, r2
  33768. 800ef9e: 42ac cmp r4, r5
  33769. 800efa0: bf88 it hi
  33770. 800efa2: 2300 movhi r3, #0
  33771. 800efa4: 3302 adds r3, #2
  33772. 800efa6: 4403 add r3, r0
  33773. 800efa8: 1a18 subs r0, r3, r0
  33774. 800efaa: b003 add sp, #12
  33775. 800efac: bdf0 pop {r4, r5, r6, r7, pc}
  33776. 800efae: f813 6b01 ldrb.w r6, [r3], #1
  33777. 800efb2: f801 6f01 strb.w r6, [r1, #1]!
  33778. 800efb6: e7ed b.n 800ef94 <__exponent+0x44>
  33779. 800efb8: 2330 movs r3, #48 @ 0x30
  33780. 800efba: 3130 adds r1, #48 @ 0x30
  33781. 800efbc: 7083 strb r3, [r0, #2]
  33782. 800efbe: 70c1 strb r1, [r0, #3]
  33783. 800efc0: 1d03 adds r3, r0, #4
  33784. 800efc2: e7f1 b.n 800efa8 <__exponent+0x58>
  33785. 800efc4: 0000 movs r0, r0
  33786. ...
  33787. 0800efc8 <_printf_float>:
  33788. 800efc8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  33789. 800efcc: b08d sub sp, #52 @ 0x34
  33790. 800efce: 460c mov r4, r1
  33791. 800efd0: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58
  33792. 800efd4: 4616 mov r6, r2
  33793. 800efd6: 461f mov r7, r3
  33794. 800efd8: 4605 mov r5, r0
  33795. 800efda: f000 fd9d bl 800fb18 <_localeconv_r>
  33796. 800efde: f8d0 b000 ldr.w fp, [r0]
  33797. 800efe2: 4658 mov r0, fp
  33798. 800efe4: f7f1 f9cc bl 8000380 <strlen>
  33799. 800efe8: 2300 movs r3, #0
  33800. 800efea: 930a str r3, [sp, #40] @ 0x28
  33801. 800efec: f8d8 3000 ldr.w r3, [r8]
  33802. 800eff0: f894 9018 ldrb.w r9, [r4, #24]
  33803. 800eff4: 6822 ldr r2, [r4, #0]
  33804. 800eff6: 9005 str r0, [sp, #20]
  33805. 800eff8: 3307 adds r3, #7
  33806. 800effa: f023 0307 bic.w r3, r3, #7
  33807. 800effe: f103 0108 add.w r1, r3, #8
  33808. 800f002: f8c8 1000 str.w r1, [r8]
  33809. 800f006: ed93 0b00 vldr d0, [r3]
  33810. 800f00a: ed9f 6b97 vldr d6, [pc, #604] @ 800f268 <_printf_float+0x2a0>
  33811. 800f00e: eeb0 7bc0 vabs.f64 d7, d0
  33812. 800f012: eeb4 7b46 vcmp.f64 d7, d6
  33813. 800f016: eef1 fa10 vmrs APSR_nzcv, fpscr
  33814. 800f01a: ed84 0b12 vstr d0, [r4, #72] @ 0x48
  33815. 800f01e: dd24 ble.n 800f06a <_printf_float+0xa2>
  33816. 800f020: eeb5 0bc0 vcmpe.f64 d0, #0.0
  33817. 800f024: eef1 fa10 vmrs APSR_nzcv, fpscr
  33818. 800f028: d502 bpl.n 800f030 <_printf_float+0x68>
  33819. 800f02a: 232d movs r3, #45 @ 0x2d
  33820. 800f02c: f884 3043 strb.w r3, [r4, #67] @ 0x43
  33821. 800f030: 498f ldr r1, [pc, #572] @ (800f270 <_printf_float+0x2a8>)
  33822. 800f032: 4b90 ldr r3, [pc, #576] @ (800f274 <_printf_float+0x2ac>)
  33823. 800f034: f1b9 0f47 cmp.w r9, #71 @ 0x47
  33824. 800f038: bf94 ite ls
  33825. 800f03a: 4688 movls r8, r1
  33826. 800f03c: 4698 movhi r8, r3
  33827. 800f03e: f022 0204 bic.w r2, r2, #4
  33828. 800f042: 2303 movs r3, #3
  33829. 800f044: 6123 str r3, [r4, #16]
  33830. 800f046: 6022 str r2, [r4, #0]
  33831. 800f048: f04f 0a00 mov.w sl, #0
  33832. 800f04c: 9700 str r7, [sp, #0]
  33833. 800f04e: 4633 mov r3, r6
  33834. 800f050: aa0b add r2, sp, #44 @ 0x2c
  33835. 800f052: 4621 mov r1, r4
  33836. 800f054: 4628 mov r0, r5
  33837. 800f056: f000 f9d1 bl 800f3fc <_printf_common>
  33838. 800f05a: 3001 adds r0, #1
  33839. 800f05c: f040 8089 bne.w 800f172 <_printf_float+0x1aa>
  33840. 800f060: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  33841. 800f064: b00d add sp, #52 @ 0x34
  33842. 800f066: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  33843. 800f06a: eeb4 0b40 vcmp.f64 d0, d0
  33844. 800f06e: eef1 fa10 vmrs APSR_nzcv, fpscr
  33845. 800f072: d709 bvc.n 800f088 <_printf_float+0xc0>
  33846. 800f074: ee10 3a90 vmov r3, s1
  33847. 800f078: 2b00 cmp r3, #0
  33848. 800f07a: bfbc itt lt
  33849. 800f07c: 232d movlt r3, #45 @ 0x2d
  33850. 800f07e: f884 3043 strblt.w r3, [r4, #67] @ 0x43
  33851. 800f082: 497d ldr r1, [pc, #500] @ (800f278 <_printf_float+0x2b0>)
  33852. 800f084: 4b7d ldr r3, [pc, #500] @ (800f27c <_printf_float+0x2b4>)
  33853. 800f086: e7d5 b.n 800f034 <_printf_float+0x6c>
  33854. 800f088: 6863 ldr r3, [r4, #4]
  33855. 800f08a: 1c59 adds r1, r3, #1
  33856. 800f08c: f009 0adf and.w sl, r9, #223 @ 0xdf
  33857. 800f090: d139 bne.n 800f106 <_printf_float+0x13e>
  33858. 800f092: 2306 movs r3, #6
  33859. 800f094: 6063 str r3, [r4, #4]
  33860. 800f096: f442 6280 orr.w r2, r2, #1024 @ 0x400
  33861. 800f09a: 2300 movs r3, #0
  33862. 800f09c: 6022 str r2, [r4, #0]
  33863. 800f09e: 9303 str r3, [sp, #12]
  33864. 800f0a0: ab0a add r3, sp, #40 @ 0x28
  33865. 800f0a2: e9cd 9301 strd r9, r3, [sp, #4]
  33866. 800f0a6: ab09 add r3, sp, #36 @ 0x24
  33867. 800f0a8: 9300 str r3, [sp, #0]
  33868. 800f0aa: 6861 ldr r1, [r4, #4]
  33869. 800f0ac: f10d 0323 add.w r3, sp, #35 @ 0x23
  33870. 800f0b0: 4628 mov r0, r5
  33871. 800f0b2: f7ff fef9 bl 800eea8 <__cvt>
  33872. 800f0b6: f1ba 0f47 cmp.w sl, #71 @ 0x47
  33873. 800f0ba: 9909 ldr r1, [sp, #36] @ 0x24
  33874. 800f0bc: 4680 mov r8, r0
  33875. 800f0be: d129 bne.n 800f114 <_printf_float+0x14c>
  33876. 800f0c0: 1cc8 adds r0, r1, #3
  33877. 800f0c2: db02 blt.n 800f0ca <_printf_float+0x102>
  33878. 800f0c4: 6863 ldr r3, [r4, #4]
  33879. 800f0c6: 4299 cmp r1, r3
  33880. 800f0c8: dd41 ble.n 800f14e <_printf_float+0x186>
  33881. 800f0ca: f1a9 0902 sub.w r9, r9, #2
  33882. 800f0ce: fa5f f989 uxtb.w r9, r9
  33883. 800f0d2: 3901 subs r1, #1
  33884. 800f0d4: 464a mov r2, r9
  33885. 800f0d6: f104 0050 add.w r0, r4, #80 @ 0x50
  33886. 800f0da: 9109 str r1, [sp, #36] @ 0x24
  33887. 800f0dc: f7ff ff38 bl 800ef50 <__exponent>
  33888. 800f0e0: 9a0a ldr r2, [sp, #40] @ 0x28
  33889. 800f0e2: 1813 adds r3, r2, r0
  33890. 800f0e4: 2a01 cmp r2, #1
  33891. 800f0e6: 4682 mov sl, r0
  33892. 800f0e8: 6123 str r3, [r4, #16]
  33893. 800f0ea: dc02 bgt.n 800f0f2 <_printf_float+0x12a>
  33894. 800f0ec: 6822 ldr r2, [r4, #0]
  33895. 800f0ee: 07d2 lsls r2, r2, #31
  33896. 800f0f0: d501 bpl.n 800f0f6 <_printf_float+0x12e>
  33897. 800f0f2: 3301 adds r3, #1
  33898. 800f0f4: 6123 str r3, [r4, #16]
  33899. 800f0f6: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23
  33900. 800f0fa: 2b00 cmp r3, #0
  33901. 800f0fc: d0a6 beq.n 800f04c <_printf_float+0x84>
  33902. 800f0fe: 232d movs r3, #45 @ 0x2d
  33903. 800f100: f884 3043 strb.w r3, [r4, #67] @ 0x43
  33904. 800f104: e7a2 b.n 800f04c <_printf_float+0x84>
  33905. 800f106: f1ba 0f47 cmp.w sl, #71 @ 0x47
  33906. 800f10a: d1c4 bne.n 800f096 <_printf_float+0xce>
  33907. 800f10c: 2b00 cmp r3, #0
  33908. 800f10e: d1c2 bne.n 800f096 <_printf_float+0xce>
  33909. 800f110: 2301 movs r3, #1
  33910. 800f112: e7bf b.n 800f094 <_printf_float+0xcc>
  33911. 800f114: f1b9 0f65 cmp.w r9, #101 @ 0x65
  33912. 800f118: d9db bls.n 800f0d2 <_printf_float+0x10a>
  33913. 800f11a: f1b9 0f66 cmp.w r9, #102 @ 0x66
  33914. 800f11e: d118 bne.n 800f152 <_printf_float+0x18a>
  33915. 800f120: 2900 cmp r1, #0
  33916. 800f122: 6863 ldr r3, [r4, #4]
  33917. 800f124: dd0b ble.n 800f13e <_printf_float+0x176>
  33918. 800f126: 6121 str r1, [r4, #16]
  33919. 800f128: b913 cbnz r3, 800f130 <_printf_float+0x168>
  33920. 800f12a: 6822 ldr r2, [r4, #0]
  33921. 800f12c: 07d0 lsls r0, r2, #31
  33922. 800f12e: d502 bpl.n 800f136 <_printf_float+0x16e>
  33923. 800f130: 3301 adds r3, #1
  33924. 800f132: 440b add r3, r1
  33925. 800f134: 6123 str r3, [r4, #16]
  33926. 800f136: 65a1 str r1, [r4, #88] @ 0x58
  33927. 800f138: f04f 0a00 mov.w sl, #0
  33928. 800f13c: e7db b.n 800f0f6 <_printf_float+0x12e>
  33929. 800f13e: b913 cbnz r3, 800f146 <_printf_float+0x17e>
  33930. 800f140: 6822 ldr r2, [r4, #0]
  33931. 800f142: 07d2 lsls r2, r2, #31
  33932. 800f144: d501 bpl.n 800f14a <_printf_float+0x182>
  33933. 800f146: 3302 adds r3, #2
  33934. 800f148: e7f4 b.n 800f134 <_printf_float+0x16c>
  33935. 800f14a: 2301 movs r3, #1
  33936. 800f14c: e7f2 b.n 800f134 <_printf_float+0x16c>
  33937. 800f14e: f04f 0967 mov.w r9, #103 @ 0x67
  33938. 800f152: 9b0a ldr r3, [sp, #40] @ 0x28
  33939. 800f154: 4299 cmp r1, r3
  33940. 800f156: db05 blt.n 800f164 <_printf_float+0x19c>
  33941. 800f158: 6823 ldr r3, [r4, #0]
  33942. 800f15a: 6121 str r1, [r4, #16]
  33943. 800f15c: 07d8 lsls r0, r3, #31
  33944. 800f15e: d5ea bpl.n 800f136 <_printf_float+0x16e>
  33945. 800f160: 1c4b adds r3, r1, #1
  33946. 800f162: e7e7 b.n 800f134 <_printf_float+0x16c>
  33947. 800f164: 2900 cmp r1, #0
  33948. 800f166: bfd4 ite le
  33949. 800f168: f1c1 0202 rsble r2, r1, #2
  33950. 800f16c: 2201 movgt r2, #1
  33951. 800f16e: 4413 add r3, r2
  33952. 800f170: e7e0 b.n 800f134 <_printf_float+0x16c>
  33953. 800f172: 6823 ldr r3, [r4, #0]
  33954. 800f174: 055a lsls r2, r3, #21
  33955. 800f176: d407 bmi.n 800f188 <_printf_float+0x1c0>
  33956. 800f178: 6923 ldr r3, [r4, #16]
  33957. 800f17a: 4642 mov r2, r8
  33958. 800f17c: 4631 mov r1, r6
  33959. 800f17e: 4628 mov r0, r5
  33960. 800f180: 47b8 blx r7
  33961. 800f182: 3001 adds r0, #1
  33962. 800f184: d12a bne.n 800f1dc <_printf_float+0x214>
  33963. 800f186: e76b b.n 800f060 <_printf_float+0x98>
  33964. 800f188: f1b9 0f65 cmp.w r9, #101 @ 0x65
  33965. 800f18c: f240 80e0 bls.w 800f350 <_printf_float+0x388>
  33966. 800f190: ed94 7b12 vldr d7, [r4, #72] @ 0x48
  33967. 800f194: eeb5 7b40 vcmp.f64 d7, #0.0
  33968. 800f198: eef1 fa10 vmrs APSR_nzcv, fpscr
  33969. 800f19c: d133 bne.n 800f206 <_printf_float+0x23e>
  33970. 800f19e: 4a38 ldr r2, [pc, #224] @ (800f280 <_printf_float+0x2b8>)
  33971. 800f1a0: 2301 movs r3, #1
  33972. 800f1a2: 4631 mov r1, r6
  33973. 800f1a4: 4628 mov r0, r5
  33974. 800f1a6: 47b8 blx r7
  33975. 800f1a8: 3001 adds r0, #1
  33976. 800f1aa: f43f af59 beq.w 800f060 <_printf_float+0x98>
  33977. 800f1ae: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24
  33978. 800f1b2: 4543 cmp r3, r8
  33979. 800f1b4: db02 blt.n 800f1bc <_printf_float+0x1f4>
  33980. 800f1b6: 6823 ldr r3, [r4, #0]
  33981. 800f1b8: 07d8 lsls r0, r3, #31
  33982. 800f1ba: d50f bpl.n 800f1dc <_printf_float+0x214>
  33983. 800f1bc: 9b05 ldr r3, [sp, #20]
  33984. 800f1be: 465a mov r2, fp
  33985. 800f1c0: 4631 mov r1, r6
  33986. 800f1c2: 4628 mov r0, r5
  33987. 800f1c4: 47b8 blx r7
  33988. 800f1c6: 3001 adds r0, #1
  33989. 800f1c8: f43f af4a beq.w 800f060 <_printf_float+0x98>
  33990. 800f1cc: f04f 0900 mov.w r9, #0
  33991. 800f1d0: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff
  33992. 800f1d4: f104 0a1a add.w sl, r4, #26
  33993. 800f1d8: 45c8 cmp r8, r9
  33994. 800f1da: dc09 bgt.n 800f1f0 <_printf_float+0x228>
  33995. 800f1dc: 6823 ldr r3, [r4, #0]
  33996. 800f1de: 079b lsls r3, r3, #30
  33997. 800f1e0: f100 8107 bmi.w 800f3f2 <_printf_float+0x42a>
  33998. 800f1e4: 68e0 ldr r0, [r4, #12]
  33999. 800f1e6: 9b0b ldr r3, [sp, #44] @ 0x2c
  34000. 800f1e8: 4298 cmp r0, r3
  34001. 800f1ea: bfb8 it lt
  34002. 800f1ec: 4618 movlt r0, r3
  34003. 800f1ee: e739 b.n 800f064 <_printf_float+0x9c>
  34004. 800f1f0: 2301 movs r3, #1
  34005. 800f1f2: 4652 mov r2, sl
  34006. 800f1f4: 4631 mov r1, r6
  34007. 800f1f6: 4628 mov r0, r5
  34008. 800f1f8: 47b8 blx r7
  34009. 800f1fa: 3001 adds r0, #1
  34010. 800f1fc: f43f af30 beq.w 800f060 <_printf_float+0x98>
  34011. 800f200: f109 0901 add.w r9, r9, #1
  34012. 800f204: e7e8 b.n 800f1d8 <_printf_float+0x210>
  34013. 800f206: 9b09 ldr r3, [sp, #36] @ 0x24
  34014. 800f208: 2b00 cmp r3, #0
  34015. 800f20a: dc3b bgt.n 800f284 <_printf_float+0x2bc>
  34016. 800f20c: 4a1c ldr r2, [pc, #112] @ (800f280 <_printf_float+0x2b8>)
  34017. 800f20e: 2301 movs r3, #1
  34018. 800f210: 4631 mov r1, r6
  34019. 800f212: 4628 mov r0, r5
  34020. 800f214: 47b8 blx r7
  34021. 800f216: 3001 adds r0, #1
  34022. 800f218: f43f af22 beq.w 800f060 <_printf_float+0x98>
  34023. 800f21c: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24
  34024. 800f220: ea59 0303 orrs.w r3, r9, r3
  34025. 800f224: d102 bne.n 800f22c <_printf_float+0x264>
  34026. 800f226: 6823 ldr r3, [r4, #0]
  34027. 800f228: 07d9 lsls r1, r3, #31
  34028. 800f22a: d5d7 bpl.n 800f1dc <_printf_float+0x214>
  34029. 800f22c: 9b05 ldr r3, [sp, #20]
  34030. 800f22e: 465a mov r2, fp
  34031. 800f230: 4631 mov r1, r6
  34032. 800f232: 4628 mov r0, r5
  34033. 800f234: 47b8 blx r7
  34034. 800f236: 3001 adds r0, #1
  34035. 800f238: f43f af12 beq.w 800f060 <_printf_float+0x98>
  34036. 800f23c: f04f 0a00 mov.w sl, #0
  34037. 800f240: f104 0b1a add.w fp, r4, #26
  34038. 800f244: 9b09 ldr r3, [sp, #36] @ 0x24
  34039. 800f246: 425b negs r3, r3
  34040. 800f248: 4553 cmp r3, sl
  34041. 800f24a: dc01 bgt.n 800f250 <_printf_float+0x288>
  34042. 800f24c: 464b mov r3, r9
  34043. 800f24e: e794 b.n 800f17a <_printf_float+0x1b2>
  34044. 800f250: 2301 movs r3, #1
  34045. 800f252: 465a mov r2, fp
  34046. 800f254: 4631 mov r1, r6
  34047. 800f256: 4628 mov r0, r5
  34048. 800f258: 47b8 blx r7
  34049. 800f25a: 3001 adds r0, #1
  34050. 800f25c: f43f af00 beq.w 800f060 <_printf_float+0x98>
  34051. 800f260: f10a 0a01 add.w sl, sl, #1
  34052. 800f264: e7ee b.n 800f244 <_printf_float+0x27c>
  34053. 800f266: bf00 nop
  34054. 800f268: ffffffff .word 0xffffffff
  34055. 800f26c: 7fefffff .word 0x7fefffff
  34056. 800f270: 08011a6c .word 0x08011a6c
  34057. 800f274: 08011a70 .word 0x08011a70
  34058. 800f278: 08011a74 .word 0x08011a74
  34059. 800f27c: 08011a78 .word 0x08011a78
  34060. 800f280: 08011a7c .word 0x08011a7c
  34061. 800f284: 6da3 ldr r3, [r4, #88] @ 0x58
  34062. 800f286: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
  34063. 800f28a: 4553 cmp r3, sl
  34064. 800f28c: bfa8 it ge
  34065. 800f28e: 4653 movge r3, sl
  34066. 800f290: 2b00 cmp r3, #0
  34067. 800f292: 4699 mov r9, r3
  34068. 800f294: dc37 bgt.n 800f306 <_printf_float+0x33e>
  34069. 800f296: 2300 movs r3, #0
  34070. 800f298: 9307 str r3, [sp, #28]
  34071. 800f29a: ea29 79e9 bic.w r9, r9, r9, asr #31
  34072. 800f29e: f104 021a add.w r2, r4, #26
  34073. 800f2a2: 6da3 ldr r3, [r4, #88] @ 0x58
  34074. 800f2a4: 9907 ldr r1, [sp, #28]
  34075. 800f2a6: 9306 str r3, [sp, #24]
  34076. 800f2a8: eba3 0309 sub.w r3, r3, r9
  34077. 800f2ac: 428b cmp r3, r1
  34078. 800f2ae: dc31 bgt.n 800f314 <_printf_float+0x34c>
  34079. 800f2b0: 9b09 ldr r3, [sp, #36] @ 0x24
  34080. 800f2b2: 459a cmp sl, r3
  34081. 800f2b4: dc3b bgt.n 800f32e <_printf_float+0x366>
  34082. 800f2b6: 6823 ldr r3, [r4, #0]
  34083. 800f2b8: 07da lsls r2, r3, #31
  34084. 800f2ba: d438 bmi.n 800f32e <_printf_float+0x366>
  34085. 800f2bc: 9b09 ldr r3, [sp, #36] @ 0x24
  34086. 800f2be: ebaa 0903 sub.w r9, sl, r3
  34087. 800f2c2: 9b06 ldr r3, [sp, #24]
  34088. 800f2c4: ebaa 0303 sub.w r3, sl, r3
  34089. 800f2c8: 4599 cmp r9, r3
  34090. 800f2ca: bfa8 it ge
  34091. 800f2cc: 4699 movge r9, r3
  34092. 800f2ce: f1b9 0f00 cmp.w r9, #0
  34093. 800f2d2: dc34 bgt.n 800f33e <_printf_float+0x376>
  34094. 800f2d4: f04f 0800 mov.w r8, #0
  34095. 800f2d8: ea29 79e9 bic.w r9, r9, r9, asr #31
  34096. 800f2dc: f104 0b1a add.w fp, r4, #26
  34097. 800f2e0: 9b09 ldr r3, [sp, #36] @ 0x24
  34098. 800f2e2: ebaa 0303 sub.w r3, sl, r3
  34099. 800f2e6: eba3 0309 sub.w r3, r3, r9
  34100. 800f2ea: 4543 cmp r3, r8
  34101. 800f2ec: f77f af76 ble.w 800f1dc <_printf_float+0x214>
  34102. 800f2f0: 2301 movs r3, #1
  34103. 800f2f2: 465a mov r2, fp
  34104. 800f2f4: 4631 mov r1, r6
  34105. 800f2f6: 4628 mov r0, r5
  34106. 800f2f8: 47b8 blx r7
  34107. 800f2fa: 3001 adds r0, #1
  34108. 800f2fc: f43f aeb0 beq.w 800f060 <_printf_float+0x98>
  34109. 800f300: f108 0801 add.w r8, r8, #1
  34110. 800f304: e7ec b.n 800f2e0 <_printf_float+0x318>
  34111. 800f306: 4642 mov r2, r8
  34112. 800f308: 4631 mov r1, r6
  34113. 800f30a: 4628 mov r0, r5
  34114. 800f30c: 47b8 blx r7
  34115. 800f30e: 3001 adds r0, #1
  34116. 800f310: d1c1 bne.n 800f296 <_printf_float+0x2ce>
  34117. 800f312: e6a5 b.n 800f060 <_printf_float+0x98>
  34118. 800f314: 2301 movs r3, #1
  34119. 800f316: 4631 mov r1, r6
  34120. 800f318: 4628 mov r0, r5
  34121. 800f31a: 9206 str r2, [sp, #24]
  34122. 800f31c: 47b8 blx r7
  34123. 800f31e: 3001 adds r0, #1
  34124. 800f320: f43f ae9e beq.w 800f060 <_printf_float+0x98>
  34125. 800f324: 9b07 ldr r3, [sp, #28]
  34126. 800f326: 9a06 ldr r2, [sp, #24]
  34127. 800f328: 3301 adds r3, #1
  34128. 800f32a: 9307 str r3, [sp, #28]
  34129. 800f32c: e7b9 b.n 800f2a2 <_printf_float+0x2da>
  34130. 800f32e: 9b05 ldr r3, [sp, #20]
  34131. 800f330: 465a mov r2, fp
  34132. 800f332: 4631 mov r1, r6
  34133. 800f334: 4628 mov r0, r5
  34134. 800f336: 47b8 blx r7
  34135. 800f338: 3001 adds r0, #1
  34136. 800f33a: d1bf bne.n 800f2bc <_printf_float+0x2f4>
  34137. 800f33c: e690 b.n 800f060 <_printf_float+0x98>
  34138. 800f33e: 9a06 ldr r2, [sp, #24]
  34139. 800f340: 464b mov r3, r9
  34140. 800f342: 4442 add r2, r8
  34141. 800f344: 4631 mov r1, r6
  34142. 800f346: 4628 mov r0, r5
  34143. 800f348: 47b8 blx r7
  34144. 800f34a: 3001 adds r0, #1
  34145. 800f34c: d1c2 bne.n 800f2d4 <_printf_float+0x30c>
  34146. 800f34e: e687 b.n 800f060 <_printf_float+0x98>
  34147. 800f350: f8dd 9028 ldr.w r9, [sp, #40] @ 0x28
  34148. 800f354: f1b9 0f01 cmp.w r9, #1
  34149. 800f358: dc01 bgt.n 800f35e <_printf_float+0x396>
  34150. 800f35a: 07db lsls r3, r3, #31
  34151. 800f35c: d536 bpl.n 800f3cc <_printf_float+0x404>
  34152. 800f35e: 2301 movs r3, #1
  34153. 800f360: 4642 mov r2, r8
  34154. 800f362: 4631 mov r1, r6
  34155. 800f364: 4628 mov r0, r5
  34156. 800f366: 47b8 blx r7
  34157. 800f368: 3001 adds r0, #1
  34158. 800f36a: f43f ae79 beq.w 800f060 <_printf_float+0x98>
  34159. 800f36e: 9b05 ldr r3, [sp, #20]
  34160. 800f370: 465a mov r2, fp
  34161. 800f372: 4631 mov r1, r6
  34162. 800f374: 4628 mov r0, r5
  34163. 800f376: 47b8 blx r7
  34164. 800f378: 3001 adds r0, #1
  34165. 800f37a: f43f ae71 beq.w 800f060 <_printf_float+0x98>
  34166. 800f37e: ed94 7b12 vldr d7, [r4, #72] @ 0x48
  34167. 800f382: eeb5 7b40 vcmp.f64 d7, #0.0
  34168. 800f386: eef1 fa10 vmrs APSR_nzcv, fpscr
  34169. 800f38a: f109 39ff add.w r9, r9, #4294967295 @ 0xffffffff
  34170. 800f38e: d018 beq.n 800f3c2 <_printf_float+0x3fa>
  34171. 800f390: 464b mov r3, r9
  34172. 800f392: f108 0201 add.w r2, r8, #1
  34173. 800f396: 4631 mov r1, r6
  34174. 800f398: 4628 mov r0, r5
  34175. 800f39a: 47b8 blx r7
  34176. 800f39c: 3001 adds r0, #1
  34177. 800f39e: d10c bne.n 800f3ba <_printf_float+0x3f2>
  34178. 800f3a0: e65e b.n 800f060 <_printf_float+0x98>
  34179. 800f3a2: 2301 movs r3, #1
  34180. 800f3a4: 465a mov r2, fp
  34181. 800f3a6: 4631 mov r1, r6
  34182. 800f3a8: 4628 mov r0, r5
  34183. 800f3aa: 47b8 blx r7
  34184. 800f3ac: 3001 adds r0, #1
  34185. 800f3ae: f43f ae57 beq.w 800f060 <_printf_float+0x98>
  34186. 800f3b2: f108 0801 add.w r8, r8, #1
  34187. 800f3b6: 45c8 cmp r8, r9
  34188. 800f3b8: dbf3 blt.n 800f3a2 <_printf_float+0x3da>
  34189. 800f3ba: 4653 mov r3, sl
  34190. 800f3bc: f104 0250 add.w r2, r4, #80 @ 0x50
  34191. 800f3c0: e6dc b.n 800f17c <_printf_float+0x1b4>
  34192. 800f3c2: f04f 0800 mov.w r8, #0
  34193. 800f3c6: f104 0b1a add.w fp, r4, #26
  34194. 800f3ca: e7f4 b.n 800f3b6 <_printf_float+0x3ee>
  34195. 800f3cc: 2301 movs r3, #1
  34196. 800f3ce: 4642 mov r2, r8
  34197. 800f3d0: e7e1 b.n 800f396 <_printf_float+0x3ce>
  34198. 800f3d2: 2301 movs r3, #1
  34199. 800f3d4: 464a mov r2, r9
  34200. 800f3d6: 4631 mov r1, r6
  34201. 800f3d8: 4628 mov r0, r5
  34202. 800f3da: 47b8 blx r7
  34203. 800f3dc: 3001 adds r0, #1
  34204. 800f3de: f43f ae3f beq.w 800f060 <_printf_float+0x98>
  34205. 800f3e2: f108 0801 add.w r8, r8, #1
  34206. 800f3e6: 68e3 ldr r3, [r4, #12]
  34207. 800f3e8: 990b ldr r1, [sp, #44] @ 0x2c
  34208. 800f3ea: 1a5b subs r3, r3, r1
  34209. 800f3ec: 4543 cmp r3, r8
  34210. 800f3ee: dcf0 bgt.n 800f3d2 <_printf_float+0x40a>
  34211. 800f3f0: e6f8 b.n 800f1e4 <_printf_float+0x21c>
  34212. 800f3f2: f04f 0800 mov.w r8, #0
  34213. 800f3f6: f104 0919 add.w r9, r4, #25
  34214. 800f3fa: e7f4 b.n 800f3e6 <_printf_float+0x41e>
  34215. 0800f3fc <_printf_common>:
  34216. 800f3fc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  34217. 800f400: 4616 mov r6, r2
  34218. 800f402: 4698 mov r8, r3
  34219. 800f404: 688a ldr r2, [r1, #8]
  34220. 800f406: 690b ldr r3, [r1, #16]
  34221. 800f408: f8dd 9020 ldr.w r9, [sp, #32]
  34222. 800f40c: 4293 cmp r3, r2
  34223. 800f40e: bfb8 it lt
  34224. 800f410: 4613 movlt r3, r2
  34225. 800f412: 6033 str r3, [r6, #0]
  34226. 800f414: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
  34227. 800f418: 4607 mov r7, r0
  34228. 800f41a: 460c mov r4, r1
  34229. 800f41c: b10a cbz r2, 800f422 <_printf_common+0x26>
  34230. 800f41e: 3301 adds r3, #1
  34231. 800f420: 6033 str r3, [r6, #0]
  34232. 800f422: 6823 ldr r3, [r4, #0]
  34233. 800f424: 0699 lsls r1, r3, #26
  34234. 800f426: bf42 ittt mi
  34235. 800f428: 6833 ldrmi r3, [r6, #0]
  34236. 800f42a: 3302 addmi r3, #2
  34237. 800f42c: 6033 strmi r3, [r6, #0]
  34238. 800f42e: 6825 ldr r5, [r4, #0]
  34239. 800f430: f015 0506 ands.w r5, r5, #6
  34240. 800f434: d106 bne.n 800f444 <_printf_common+0x48>
  34241. 800f436: f104 0a19 add.w sl, r4, #25
  34242. 800f43a: 68e3 ldr r3, [r4, #12]
  34243. 800f43c: 6832 ldr r2, [r6, #0]
  34244. 800f43e: 1a9b subs r3, r3, r2
  34245. 800f440: 42ab cmp r3, r5
  34246. 800f442: dc26 bgt.n 800f492 <_printf_common+0x96>
  34247. 800f444: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
  34248. 800f448: 6822 ldr r2, [r4, #0]
  34249. 800f44a: 3b00 subs r3, #0
  34250. 800f44c: bf18 it ne
  34251. 800f44e: 2301 movne r3, #1
  34252. 800f450: 0692 lsls r2, r2, #26
  34253. 800f452: d42b bmi.n 800f4ac <_printf_common+0xb0>
  34254. 800f454: f104 0243 add.w r2, r4, #67 @ 0x43
  34255. 800f458: 4641 mov r1, r8
  34256. 800f45a: 4638 mov r0, r7
  34257. 800f45c: 47c8 blx r9
  34258. 800f45e: 3001 adds r0, #1
  34259. 800f460: d01e beq.n 800f4a0 <_printf_common+0xa4>
  34260. 800f462: 6823 ldr r3, [r4, #0]
  34261. 800f464: 6922 ldr r2, [r4, #16]
  34262. 800f466: f003 0306 and.w r3, r3, #6
  34263. 800f46a: 2b04 cmp r3, #4
  34264. 800f46c: bf02 ittt eq
  34265. 800f46e: 68e5 ldreq r5, [r4, #12]
  34266. 800f470: 6833 ldreq r3, [r6, #0]
  34267. 800f472: 1aed subeq r5, r5, r3
  34268. 800f474: 68a3 ldr r3, [r4, #8]
  34269. 800f476: bf0c ite eq
  34270. 800f478: ea25 75e5 biceq.w r5, r5, r5, asr #31
  34271. 800f47c: 2500 movne r5, #0
  34272. 800f47e: 4293 cmp r3, r2
  34273. 800f480: bfc4 itt gt
  34274. 800f482: 1a9b subgt r3, r3, r2
  34275. 800f484: 18ed addgt r5, r5, r3
  34276. 800f486: 2600 movs r6, #0
  34277. 800f488: 341a adds r4, #26
  34278. 800f48a: 42b5 cmp r5, r6
  34279. 800f48c: d11a bne.n 800f4c4 <_printf_common+0xc8>
  34280. 800f48e: 2000 movs r0, #0
  34281. 800f490: e008 b.n 800f4a4 <_printf_common+0xa8>
  34282. 800f492: 2301 movs r3, #1
  34283. 800f494: 4652 mov r2, sl
  34284. 800f496: 4641 mov r1, r8
  34285. 800f498: 4638 mov r0, r7
  34286. 800f49a: 47c8 blx r9
  34287. 800f49c: 3001 adds r0, #1
  34288. 800f49e: d103 bne.n 800f4a8 <_printf_common+0xac>
  34289. 800f4a0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  34290. 800f4a4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  34291. 800f4a8: 3501 adds r5, #1
  34292. 800f4aa: e7c6 b.n 800f43a <_printf_common+0x3e>
  34293. 800f4ac: 18e1 adds r1, r4, r3
  34294. 800f4ae: 1c5a adds r2, r3, #1
  34295. 800f4b0: 2030 movs r0, #48 @ 0x30
  34296. 800f4b2: f881 0043 strb.w r0, [r1, #67] @ 0x43
  34297. 800f4b6: 4422 add r2, r4
  34298. 800f4b8: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
  34299. 800f4bc: f882 1043 strb.w r1, [r2, #67] @ 0x43
  34300. 800f4c0: 3302 adds r3, #2
  34301. 800f4c2: e7c7 b.n 800f454 <_printf_common+0x58>
  34302. 800f4c4: 2301 movs r3, #1
  34303. 800f4c6: 4622 mov r2, r4
  34304. 800f4c8: 4641 mov r1, r8
  34305. 800f4ca: 4638 mov r0, r7
  34306. 800f4cc: 47c8 blx r9
  34307. 800f4ce: 3001 adds r0, #1
  34308. 800f4d0: d0e6 beq.n 800f4a0 <_printf_common+0xa4>
  34309. 800f4d2: 3601 adds r6, #1
  34310. 800f4d4: e7d9 b.n 800f48a <_printf_common+0x8e>
  34311. ...
  34312. 0800f4d8 <_printf_i>:
  34313. 800f4d8: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
  34314. 800f4dc: 7e0f ldrb r7, [r1, #24]
  34315. 800f4de: 9e0c ldr r6, [sp, #48] @ 0x30
  34316. 800f4e0: 2f78 cmp r7, #120 @ 0x78
  34317. 800f4e2: 4691 mov r9, r2
  34318. 800f4e4: 4680 mov r8, r0
  34319. 800f4e6: 460c mov r4, r1
  34320. 800f4e8: 469a mov sl, r3
  34321. 800f4ea: f101 0243 add.w r2, r1, #67 @ 0x43
  34322. 800f4ee: d807 bhi.n 800f500 <_printf_i+0x28>
  34323. 800f4f0: 2f62 cmp r7, #98 @ 0x62
  34324. 800f4f2: d80a bhi.n 800f50a <_printf_i+0x32>
  34325. 800f4f4: 2f00 cmp r7, #0
  34326. 800f4f6: f000 80d2 beq.w 800f69e <_printf_i+0x1c6>
  34327. 800f4fa: 2f58 cmp r7, #88 @ 0x58
  34328. 800f4fc: f000 80b9 beq.w 800f672 <_printf_i+0x19a>
  34329. 800f500: f104 0642 add.w r6, r4, #66 @ 0x42
  34330. 800f504: f884 7042 strb.w r7, [r4, #66] @ 0x42
  34331. 800f508: e03a b.n 800f580 <_printf_i+0xa8>
  34332. 800f50a: f1a7 0363 sub.w r3, r7, #99 @ 0x63
  34333. 800f50e: 2b15 cmp r3, #21
  34334. 800f510: d8f6 bhi.n 800f500 <_printf_i+0x28>
  34335. 800f512: a101 add r1, pc, #4 @ (adr r1, 800f518 <_printf_i+0x40>)
  34336. 800f514: f851 f023 ldr.w pc, [r1, r3, lsl #2]
  34337. 800f518: 0800f571 .word 0x0800f571
  34338. 800f51c: 0800f585 .word 0x0800f585
  34339. 800f520: 0800f501 .word 0x0800f501
  34340. 800f524: 0800f501 .word 0x0800f501
  34341. 800f528: 0800f501 .word 0x0800f501
  34342. 800f52c: 0800f501 .word 0x0800f501
  34343. 800f530: 0800f585 .word 0x0800f585
  34344. 800f534: 0800f501 .word 0x0800f501
  34345. 800f538: 0800f501 .word 0x0800f501
  34346. 800f53c: 0800f501 .word 0x0800f501
  34347. 800f540: 0800f501 .word 0x0800f501
  34348. 800f544: 0800f685 .word 0x0800f685
  34349. 800f548: 0800f5af .word 0x0800f5af
  34350. 800f54c: 0800f63f .word 0x0800f63f
  34351. 800f550: 0800f501 .word 0x0800f501
  34352. 800f554: 0800f501 .word 0x0800f501
  34353. 800f558: 0800f6a7 .word 0x0800f6a7
  34354. 800f55c: 0800f501 .word 0x0800f501
  34355. 800f560: 0800f5af .word 0x0800f5af
  34356. 800f564: 0800f501 .word 0x0800f501
  34357. 800f568: 0800f501 .word 0x0800f501
  34358. 800f56c: 0800f647 .word 0x0800f647
  34359. 800f570: 6833 ldr r3, [r6, #0]
  34360. 800f572: 1d1a adds r2, r3, #4
  34361. 800f574: 681b ldr r3, [r3, #0]
  34362. 800f576: 6032 str r2, [r6, #0]
  34363. 800f578: f104 0642 add.w r6, r4, #66 @ 0x42
  34364. 800f57c: f884 3042 strb.w r3, [r4, #66] @ 0x42
  34365. 800f580: 2301 movs r3, #1
  34366. 800f582: e09d b.n 800f6c0 <_printf_i+0x1e8>
  34367. 800f584: 6833 ldr r3, [r6, #0]
  34368. 800f586: 6820 ldr r0, [r4, #0]
  34369. 800f588: 1d19 adds r1, r3, #4
  34370. 800f58a: 6031 str r1, [r6, #0]
  34371. 800f58c: 0606 lsls r6, r0, #24
  34372. 800f58e: d501 bpl.n 800f594 <_printf_i+0xbc>
  34373. 800f590: 681d ldr r5, [r3, #0]
  34374. 800f592: e003 b.n 800f59c <_printf_i+0xc4>
  34375. 800f594: 0645 lsls r5, r0, #25
  34376. 800f596: d5fb bpl.n 800f590 <_printf_i+0xb8>
  34377. 800f598: f9b3 5000 ldrsh.w r5, [r3]
  34378. 800f59c: 2d00 cmp r5, #0
  34379. 800f59e: da03 bge.n 800f5a8 <_printf_i+0xd0>
  34380. 800f5a0: 232d movs r3, #45 @ 0x2d
  34381. 800f5a2: 426d negs r5, r5
  34382. 800f5a4: f884 3043 strb.w r3, [r4, #67] @ 0x43
  34383. 800f5a8: 4859 ldr r0, [pc, #356] @ (800f710 <_printf_i+0x238>)
  34384. 800f5aa: 230a movs r3, #10
  34385. 800f5ac: e011 b.n 800f5d2 <_printf_i+0xfa>
  34386. 800f5ae: 6821 ldr r1, [r4, #0]
  34387. 800f5b0: 6833 ldr r3, [r6, #0]
  34388. 800f5b2: 0608 lsls r0, r1, #24
  34389. 800f5b4: f853 5b04 ldr.w r5, [r3], #4
  34390. 800f5b8: d402 bmi.n 800f5c0 <_printf_i+0xe8>
  34391. 800f5ba: 0649 lsls r1, r1, #25
  34392. 800f5bc: bf48 it mi
  34393. 800f5be: b2ad uxthmi r5, r5
  34394. 800f5c0: 2f6f cmp r7, #111 @ 0x6f
  34395. 800f5c2: 4853 ldr r0, [pc, #332] @ (800f710 <_printf_i+0x238>)
  34396. 800f5c4: 6033 str r3, [r6, #0]
  34397. 800f5c6: bf14 ite ne
  34398. 800f5c8: 230a movne r3, #10
  34399. 800f5ca: 2308 moveq r3, #8
  34400. 800f5cc: 2100 movs r1, #0
  34401. 800f5ce: f884 1043 strb.w r1, [r4, #67] @ 0x43
  34402. 800f5d2: 6866 ldr r6, [r4, #4]
  34403. 800f5d4: 60a6 str r6, [r4, #8]
  34404. 800f5d6: 2e00 cmp r6, #0
  34405. 800f5d8: bfa2 ittt ge
  34406. 800f5da: 6821 ldrge r1, [r4, #0]
  34407. 800f5dc: f021 0104 bicge.w r1, r1, #4
  34408. 800f5e0: 6021 strge r1, [r4, #0]
  34409. 800f5e2: b90d cbnz r5, 800f5e8 <_printf_i+0x110>
  34410. 800f5e4: 2e00 cmp r6, #0
  34411. 800f5e6: d04b beq.n 800f680 <_printf_i+0x1a8>
  34412. 800f5e8: 4616 mov r6, r2
  34413. 800f5ea: fbb5 f1f3 udiv r1, r5, r3
  34414. 800f5ee: fb03 5711 mls r7, r3, r1, r5
  34415. 800f5f2: 5dc7 ldrb r7, [r0, r7]
  34416. 800f5f4: f806 7d01 strb.w r7, [r6, #-1]!
  34417. 800f5f8: 462f mov r7, r5
  34418. 800f5fa: 42bb cmp r3, r7
  34419. 800f5fc: 460d mov r5, r1
  34420. 800f5fe: d9f4 bls.n 800f5ea <_printf_i+0x112>
  34421. 800f600: 2b08 cmp r3, #8
  34422. 800f602: d10b bne.n 800f61c <_printf_i+0x144>
  34423. 800f604: 6823 ldr r3, [r4, #0]
  34424. 800f606: 07df lsls r7, r3, #31
  34425. 800f608: d508 bpl.n 800f61c <_printf_i+0x144>
  34426. 800f60a: 6923 ldr r3, [r4, #16]
  34427. 800f60c: 6861 ldr r1, [r4, #4]
  34428. 800f60e: 4299 cmp r1, r3
  34429. 800f610: bfde ittt le
  34430. 800f612: 2330 movle r3, #48 @ 0x30
  34431. 800f614: f806 3c01 strble.w r3, [r6, #-1]
  34432. 800f618: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff
  34433. 800f61c: 1b92 subs r2, r2, r6
  34434. 800f61e: 6122 str r2, [r4, #16]
  34435. 800f620: f8cd a000 str.w sl, [sp]
  34436. 800f624: 464b mov r3, r9
  34437. 800f626: aa03 add r2, sp, #12
  34438. 800f628: 4621 mov r1, r4
  34439. 800f62a: 4640 mov r0, r8
  34440. 800f62c: f7ff fee6 bl 800f3fc <_printf_common>
  34441. 800f630: 3001 adds r0, #1
  34442. 800f632: d14a bne.n 800f6ca <_printf_i+0x1f2>
  34443. 800f634: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  34444. 800f638: b004 add sp, #16
  34445. 800f63a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  34446. 800f63e: 6823 ldr r3, [r4, #0]
  34447. 800f640: f043 0320 orr.w r3, r3, #32
  34448. 800f644: 6023 str r3, [r4, #0]
  34449. 800f646: 4833 ldr r0, [pc, #204] @ (800f714 <_printf_i+0x23c>)
  34450. 800f648: 2778 movs r7, #120 @ 0x78
  34451. 800f64a: f884 7045 strb.w r7, [r4, #69] @ 0x45
  34452. 800f64e: 6823 ldr r3, [r4, #0]
  34453. 800f650: 6831 ldr r1, [r6, #0]
  34454. 800f652: 061f lsls r7, r3, #24
  34455. 800f654: f851 5b04 ldr.w r5, [r1], #4
  34456. 800f658: d402 bmi.n 800f660 <_printf_i+0x188>
  34457. 800f65a: 065f lsls r7, r3, #25
  34458. 800f65c: bf48 it mi
  34459. 800f65e: b2ad uxthmi r5, r5
  34460. 800f660: 6031 str r1, [r6, #0]
  34461. 800f662: 07d9 lsls r1, r3, #31
  34462. 800f664: bf44 itt mi
  34463. 800f666: f043 0320 orrmi.w r3, r3, #32
  34464. 800f66a: 6023 strmi r3, [r4, #0]
  34465. 800f66c: b11d cbz r5, 800f676 <_printf_i+0x19e>
  34466. 800f66e: 2310 movs r3, #16
  34467. 800f670: e7ac b.n 800f5cc <_printf_i+0xf4>
  34468. 800f672: 4827 ldr r0, [pc, #156] @ (800f710 <_printf_i+0x238>)
  34469. 800f674: e7e9 b.n 800f64a <_printf_i+0x172>
  34470. 800f676: 6823 ldr r3, [r4, #0]
  34471. 800f678: f023 0320 bic.w r3, r3, #32
  34472. 800f67c: 6023 str r3, [r4, #0]
  34473. 800f67e: e7f6 b.n 800f66e <_printf_i+0x196>
  34474. 800f680: 4616 mov r6, r2
  34475. 800f682: e7bd b.n 800f600 <_printf_i+0x128>
  34476. 800f684: 6833 ldr r3, [r6, #0]
  34477. 800f686: 6825 ldr r5, [r4, #0]
  34478. 800f688: 6961 ldr r1, [r4, #20]
  34479. 800f68a: 1d18 adds r0, r3, #4
  34480. 800f68c: 6030 str r0, [r6, #0]
  34481. 800f68e: 062e lsls r6, r5, #24
  34482. 800f690: 681b ldr r3, [r3, #0]
  34483. 800f692: d501 bpl.n 800f698 <_printf_i+0x1c0>
  34484. 800f694: 6019 str r1, [r3, #0]
  34485. 800f696: e002 b.n 800f69e <_printf_i+0x1c6>
  34486. 800f698: 0668 lsls r0, r5, #25
  34487. 800f69a: d5fb bpl.n 800f694 <_printf_i+0x1bc>
  34488. 800f69c: 8019 strh r1, [r3, #0]
  34489. 800f69e: 2300 movs r3, #0
  34490. 800f6a0: 6123 str r3, [r4, #16]
  34491. 800f6a2: 4616 mov r6, r2
  34492. 800f6a4: e7bc b.n 800f620 <_printf_i+0x148>
  34493. 800f6a6: 6833 ldr r3, [r6, #0]
  34494. 800f6a8: 1d1a adds r2, r3, #4
  34495. 800f6aa: 6032 str r2, [r6, #0]
  34496. 800f6ac: 681e ldr r6, [r3, #0]
  34497. 800f6ae: 6862 ldr r2, [r4, #4]
  34498. 800f6b0: 2100 movs r1, #0
  34499. 800f6b2: 4630 mov r0, r6
  34500. 800f6b4: f7f0 fe14 bl 80002e0 <memchr>
  34501. 800f6b8: b108 cbz r0, 800f6be <_printf_i+0x1e6>
  34502. 800f6ba: 1b80 subs r0, r0, r6
  34503. 800f6bc: 6060 str r0, [r4, #4]
  34504. 800f6be: 6863 ldr r3, [r4, #4]
  34505. 800f6c0: 6123 str r3, [r4, #16]
  34506. 800f6c2: 2300 movs r3, #0
  34507. 800f6c4: f884 3043 strb.w r3, [r4, #67] @ 0x43
  34508. 800f6c8: e7aa b.n 800f620 <_printf_i+0x148>
  34509. 800f6ca: 6923 ldr r3, [r4, #16]
  34510. 800f6cc: 4632 mov r2, r6
  34511. 800f6ce: 4649 mov r1, r9
  34512. 800f6d0: 4640 mov r0, r8
  34513. 800f6d2: 47d0 blx sl
  34514. 800f6d4: 3001 adds r0, #1
  34515. 800f6d6: d0ad beq.n 800f634 <_printf_i+0x15c>
  34516. 800f6d8: 6823 ldr r3, [r4, #0]
  34517. 800f6da: 079b lsls r3, r3, #30
  34518. 800f6dc: d413 bmi.n 800f706 <_printf_i+0x22e>
  34519. 800f6de: 68e0 ldr r0, [r4, #12]
  34520. 800f6e0: 9b03 ldr r3, [sp, #12]
  34521. 800f6e2: 4298 cmp r0, r3
  34522. 800f6e4: bfb8 it lt
  34523. 800f6e6: 4618 movlt r0, r3
  34524. 800f6e8: e7a6 b.n 800f638 <_printf_i+0x160>
  34525. 800f6ea: 2301 movs r3, #1
  34526. 800f6ec: 4632 mov r2, r6
  34527. 800f6ee: 4649 mov r1, r9
  34528. 800f6f0: 4640 mov r0, r8
  34529. 800f6f2: 47d0 blx sl
  34530. 800f6f4: 3001 adds r0, #1
  34531. 800f6f6: d09d beq.n 800f634 <_printf_i+0x15c>
  34532. 800f6f8: 3501 adds r5, #1
  34533. 800f6fa: 68e3 ldr r3, [r4, #12]
  34534. 800f6fc: 9903 ldr r1, [sp, #12]
  34535. 800f6fe: 1a5b subs r3, r3, r1
  34536. 800f700: 42ab cmp r3, r5
  34537. 800f702: dcf2 bgt.n 800f6ea <_printf_i+0x212>
  34538. 800f704: e7eb b.n 800f6de <_printf_i+0x206>
  34539. 800f706: 2500 movs r5, #0
  34540. 800f708: f104 0619 add.w r6, r4, #25
  34541. 800f70c: e7f5 b.n 800f6fa <_printf_i+0x222>
  34542. 800f70e: bf00 nop
  34543. 800f710: 08011a7e .word 0x08011a7e
  34544. 800f714: 08011a8f .word 0x08011a8f
  34545. 0800f718 <std>:
  34546. 800f718: 2300 movs r3, #0
  34547. 800f71a: b510 push {r4, lr}
  34548. 800f71c: 4604 mov r4, r0
  34549. 800f71e: e9c0 3300 strd r3, r3, [r0]
  34550. 800f722: e9c0 3304 strd r3, r3, [r0, #16]
  34551. 800f726: 6083 str r3, [r0, #8]
  34552. 800f728: 8181 strh r1, [r0, #12]
  34553. 800f72a: 6643 str r3, [r0, #100] @ 0x64
  34554. 800f72c: 81c2 strh r2, [r0, #14]
  34555. 800f72e: 6183 str r3, [r0, #24]
  34556. 800f730: 4619 mov r1, r3
  34557. 800f732: 2208 movs r2, #8
  34558. 800f734: 305c adds r0, #92 @ 0x5c
  34559. 800f736: f000 f9e7 bl 800fb08 <memset>
  34560. 800f73a: 4b0d ldr r3, [pc, #52] @ (800f770 <std+0x58>)
  34561. 800f73c: 6263 str r3, [r4, #36] @ 0x24
  34562. 800f73e: 4b0d ldr r3, [pc, #52] @ (800f774 <std+0x5c>)
  34563. 800f740: 62a3 str r3, [r4, #40] @ 0x28
  34564. 800f742: 4b0d ldr r3, [pc, #52] @ (800f778 <std+0x60>)
  34565. 800f744: 62e3 str r3, [r4, #44] @ 0x2c
  34566. 800f746: 4b0d ldr r3, [pc, #52] @ (800f77c <std+0x64>)
  34567. 800f748: 6323 str r3, [r4, #48] @ 0x30
  34568. 800f74a: 4b0d ldr r3, [pc, #52] @ (800f780 <std+0x68>)
  34569. 800f74c: 6224 str r4, [r4, #32]
  34570. 800f74e: 429c cmp r4, r3
  34571. 800f750: d006 beq.n 800f760 <std+0x48>
  34572. 800f752: f103 0268 add.w r2, r3, #104 @ 0x68
  34573. 800f756: 4294 cmp r4, r2
  34574. 800f758: d002 beq.n 800f760 <std+0x48>
  34575. 800f75a: 33d0 adds r3, #208 @ 0xd0
  34576. 800f75c: 429c cmp r4, r3
  34577. 800f75e: d105 bne.n 800f76c <std+0x54>
  34578. 800f760: f104 0058 add.w r0, r4, #88 @ 0x58
  34579. 800f764: e8bd 4010 ldmia.w sp!, {r4, lr}
  34580. 800f768: f000 baa0 b.w 800fcac <__retarget_lock_init_recursive>
  34581. 800f76c: bd10 pop {r4, pc}
  34582. 800f76e: bf00 nop
  34583. 800f770: 0800f959 .word 0x0800f959
  34584. 800f774: 0800f97b .word 0x0800f97b
  34585. 800f778: 0800f9b3 .word 0x0800f9b3
  34586. 800f77c: 0800f9d7 .word 0x0800f9d7
  34587. 800f780: 24013198 .word 0x24013198
  34588. 0800f784 <stdio_exit_handler>:
  34589. 800f784: 4a02 ldr r2, [pc, #8] @ (800f790 <stdio_exit_handler+0xc>)
  34590. 800f786: 4903 ldr r1, [pc, #12] @ (800f794 <stdio_exit_handler+0x10>)
  34591. 800f788: 4803 ldr r0, [pc, #12] @ (800f798 <stdio_exit_handler+0x14>)
  34592. 800f78a: f000 b869 b.w 800f860 <_fwalk_sglue>
  34593. 800f78e: bf00 nop
  34594. 800f790: 24000048 .word 0x24000048
  34595. 800f794: 08011299 .word 0x08011299
  34596. 800f798: 24000058 .word 0x24000058
  34597. 0800f79c <cleanup_stdio>:
  34598. 800f79c: 6841 ldr r1, [r0, #4]
  34599. 800f79e: 4b0c ldr r3, [pc, #48] @ (800f7d0 <cleanup_stdio+0x34>)
  34600. 800f7a0: 4299 cmp r1, r3
  34601. 800f7a2: b510 push {r4, lr}
  34602. 800f7a4: 4604 mov r4, r0
  34603. 800f7a6: d001 beq.n 800f7ac <cleanup_stdio+0x10>
  34604. 800f7a8: f001 fd76 bl 8011298 <_fflush_r>
  34605. 800f7ac: 68a1 ldr r1, [r4, #8]
  34606. 800f7ae: 4b09 ldr r3, [pc, #36] @ (800f7d4 <cleanup_stdio+0x38>)
  34607. 800f7b0: 4299 cmp r1, r3
  34608. 800f7b2: d002 beq.n 800f7ba <cleanup_stdio+0x1e>
  34609. 800f7b4: 4620 mov r0, r4
  34610. 800f7b6: f001 fd6f bl 8011298 <_fflush_r>
  34611. 800f7ba: 68e1 ldr r1, [r4, #12]
  34612. 800f7bc: 4b06 ldr r3, [pc, #24] @ (800f7d8 <cleanup_stdio+0x3c>)
  34613. 800f7be: 4299 cmp r1, r3
  34614. 800f7c0: d004 beq.n 800f7cc <cleanup_stdio+0x30>
  34615. 800f7c2: 4620 mov r0, r4
  34616. 800f7c4: e8bd 4010 ldmia.w sp!, {r4, lr}
  34617. 800f7c8: f001 bd66 b.w 8011298 <_fflush_r>
  34618. 800f7cc: bd10 pop {r4, pc}
  34619. 800f7ce: bf00 nop
  34620. 800f7d0: 24013198 .word 0x24013198
  34621. 800f7d4: 24013200 .word 0x24013200
  34622. 800f7d8: 24013268 .word 0x24013268
  34623. 0800f7dc <global_stdio_init.part.0>:
  34624. 800f7dc: b510 push {r4, lr}
  34625. 800f7de: 4b0b ldr r3, [pc, #44] @ (800f80c <global_stdio_init.part.0+0x30>)
  34626. 800f7e0: 4c0b ldr r4, [pc, #44] @ (800f810 <global_stdio_init.part.0+0x34>)
  34627. 800f7e2: 4a0c ldr r2, [pc, #48] @ (800f814 <global_stdio_init.part.0+0x38>)
  34628. 800f7e4: 601a str r2, [r3, #0]
  34629. 800f7e6: 4620 mov r0, r4
  34630. 800f7e8: 2200 movs r2, #0
  34631. 800f7ea: 2104 movs r1, #4
  34632. 800f7ec: f7ff ff94 bl 800f718 <std>
  34633. 800f7f0: f104 0068 add.w r0, r4, #104 @ 0x68
  34634. 800f7f4: 2201 movs r2, #1
  34635. 800f7f6: 2109 movs r1, #9
  34636. 800f7f8: f7ff ff8e bl 800f718 <std>
  34637. 800f7fc: f104 00d0 add.w r0, r4, #208 @ 0xd0
  34638. 800f800: 2202 movs r2, #2
  34639. 800f802: e8bd 4010 ldmia.w sp!, {r4, lr}
  34640. 800f806: 2112 movs r1, #18
  34641. 800f808: f7ff bf86 b.w 800f718 <std>
  34642. 800f80c: 240132d0 .word 0x240132d0
  34643. 800f810: 24013198 .word 0x24013198
  34644. 800f814: 0800f785 .word 0x0800f785
  34645. 0800f818 <__sfp_lock_acquire>:
  34646. 800f818: 4801 ldr r0, [pc, #4] @ (800f820 <__sfp_lock_acquire+0x8>)
  34647. 800f81a: f000 ba48 b.w 800fcae <__retarget_lock_acquire_recursive>
  34648. 800f81e: bf00 nop
  34649. 800f820: 240132d9 .word 0x240132d9
  34650. 0800f824 <__sfp_lock_release>:
  34651. 800f824: 4801 ldr r0, [pc, #4] @ (800f82c <__sfp_lock_release+0x8>)
  34652. 800f826: f000 ba43 b.w 800fcb0 <__retarget_lock_release_recursive>
  34653. 800f82a: bf00 nop
  34654. 800f82c: 240132d9 .word 0x240132d9
  34655. 0800f830 <__sinit>:
  34656. 800f830: b510 push {r4, lr}
  34657. 800f832: 4604 mov r4, r0
  34658. 800f834: f7ff fff0 bl 800f818 <__sfp_lock_acquire>
  34659. 800f838: 6a23 ldr r3, [r4, #32]
  34660. 800f83a: b11b cbz r3, 800f844 <__sinit+0x14>
  34661. 800f83c: e8bd 4010 ldmia.w sp!, {r4, lr}
  34662. 800f840: f7ff bff0 b.w 800f824 <__sfp_lock_release>
  34663. 800f844: 4b04 ldr r3, [pc, #16] @ (800f858 <__sinit+0x28>)
  34664. 800f846: 6223 str r3, [r4, #32]
  34665. 800f848: 4b04 ldr r3, [pc, #16] @ (800f85c <__sinit+0x2c>)
  34666. 800f84a: 681b ldr r3, [r3, #0]
  34667. 800f84c: 2b00 cmp r3, #0
  34668. 800f84e: d1f5 bne.n 800f83c <__sinit+0xc>
  34669. 800f850: f7ff ffc4 bl 800f7dc <global_stdio_init.part.0>
  34670. 800f854: e7f2 b.n 800f83c <__sinit+0xc>
  34671. 800f856: bf00 nop
  34672. 800f858: 0800f79d .word 0x0800f79d
  34673. 800f85c: 240132d0 .word 0x240132d0
  34674. 0800f860 <_fwalk_sglue>:
  34675. 800f860: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  34676. 800f864: 4607 mov r7, r0
  34677. 800f866: 4688 mov r8, r1
  34678. 800f868: 4614 mov r4, r2
  34679. 800f86a: 2600 movs r6, #0
  34680. 800f86c: e9d4 9501 ldrd r9, r5, [r4, #4]
  34681. 800f870: f1b9 0901 subs.w r9, r9, #1
  34682. 800f874: d505 bpl.n 800f882 <_fwalk_sglue+0x22>
  34683. 800f876: 6824 ldr r4, [r4, #0]
  34684. 800f878: 2c00 cmp r4, #0
  34685. 800f87a: d1f7 bne.n 800f86c <_fwalk_sglue+0xc>
  34686. 800f87c: 4630 mov r0, r6
  34687. 800f87e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  34688. 800f882: 89ab ldrh r3, [r5, #12]
  34689. 800f884: 2b01 cmp r3, #1
  34690. 800f886: d907 bls.n 800f898 <_fwalk_sglue+0x38>
  34691. 800f888: f9b5 300e ldrsh.w r3, [r5, #14]
  34692. 800f88c: 3301 adds r3, #1
  34693. 800f88e: d003 beq.n 800f898 <_fwalk_sglue+0x38>
  34694. 800f890: 4629 mov r1, r5
  34695. 800f892: 4638 mov r0, r7
  34696. 800f894: 47c0 blx r8
  34697. 800f896: 4306 orrs r6, r0
  34698. 800f898: 3568 adds r5, #104 @ 0x68
  34699. 800f89a: e7e9 b.n 800f870 <_fwalk_sglue+0x10>
  34700. 0800f89c <_puts_r>:
  34701. 800f89c: 6a03 ldr r3, [r0, #32]
  34702. 800f89e: b570 push {r4, r5, r6, lr}
  34703. 800f8a0: 6884 ldr r4, [r0, #8]
  34704. 800f8a2: 4605 mov r5, r0
  34705. 800f8a4: 460e mov r6, r1
  34706. 800f8a6: b90b cbnz r3, 800f8ac <_puts_r+0x10>
  34707. 800f8a8: f7ff ffc2 bl 800f830 <__sinit>
  34708. 800f8ac: 6e63 ldr r3, [r4, #100] @ 0x64
  34709. 800f8ae: 07db lsls r3, r3, #31
  34710. 800f8b0: d405 bmi.n 800f8be <_puts_r+0x22>
  34711. 800f8b2: 89a3 ldrh r3, [r4, #12]
  34712. 800f8b4: 0598 lsls r0, r3, #22
  34713. 800f8b6: d402 bmi.n 800f8be <_puts_r+0x22>
  34714. 800f8b8: 6da0 ldr r0, [r4, #88] @ 0x58
  34715. 800f8ba: f000 f9f8 bl 800fcae <__retarget_lock_acquire_recursive>
  34716. 800f8be: 89a3 ldrh r3, [r4, #12]
  34717. 800f8c0: 0719 lsls r1, r3, #28
  34718. 800f8c2: d502 bpl.n 800f8ca <_puts_r+0x2e>
  34719. 800f8c4: 6923 ldr r3, [r4, #16]
  34720. 800f8c6: 2b00 cmp r3, #0
  34721. 800f8c8: d135 bne.n 800f936 <_puts_r+0x9a>
  34722. 800f8ca: 4621 mov r1, r4
  34723. 800f8cc: 4628 mov r0, r5
  34724. 800f8ce: f000 f8c5 bl 800fa5c <__swsetup_r>
  34725. 800f8d2: b380 cbz r0, 800f936 <_puts_r+0x9a>
  34726. 800f8d4: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff
  34727. 800f8d8: 6e63 ldr r3, [r4, #100] @ 0x64
  34728. 800f8da: 07da lsls r2, r3, #31
  34729. 800f8dc: d405 bmi.n 800f8ea <_puts_r+0x4e>
  34730. 800f8de: 89a3 ldrh r3, [r4, #12]
  34731. 800f8e0: 059b lsls r3, r3, #22
  34732. 800f8e2: d402 bmi.n 800f8ea <_puts_r+0x4e>
  34733. 800f8e4: 6da0 ldr r0, [r4, #88] @ 0x58
  34734. 800f8e6: f000 f9e3 bl 800fcb0 <__retarget_lock_release_recursive>
  34735. 800f8ea: 4628 mov r0, r5
  34736. 800f8ec: bd70 pop {r4, r5, r6, pc}
  34737. 800f8ee: 2b00 cmp r3, #0
  34738. 800f8f0: da04 bge.n 800f8fc <_puts_r+0x60>
  34739. 800f8f2: 69a2 ldr r2, [r4, #24]
  34740. 800f8f4: 429a cmp r2, r3
  34741. 800f8f6: dc17 bgt.n 800f928 <_puts_r+0x8c>
  34742. 800f8f8: 290a cmp r1, #10
  34743. 800f8fa: d015 beq.n 800f928 <_puts_r+0x8c>
  34744. 800f8fc: 6823 ldr r3, [r4, #0]
  34745. 800f8fe: 1c5a adds r2, r3, #1
  34746. 800f900: 6022 str r2, [r4, #0]
  34747. 800f902: 7019 strb r1, [r3, #0]
  34748. 800f904: 68a3 ldr r3, [r4, #8]
  34749. 800f906: f816 1f01 ldrb.w r1, [r6, #1]!
  34750. 800f90a: 3b01 subs r3, #1
  34751. 800f90c: 60a3 str r3, [r4, #8]
  34752. 800f90e: 2900 cmp r1, #0
  34753. 800f910: d1ed bne.n 800f8ee <_puts_r+0x52>
  34754. 800f912: 2b00 cmp r3, #0
  34755. 800f914: da11 bge.n 800f93a <_puts_r+0x9e>
  34756. 800f916: 4622 mov r2, r4
  34757. 800f918: 210a movs r1, #10
  34758. 800f91a: 4628 mov r0, r5
  34759. 800f91c: f000 f85f bl 800f9de <__swbuf_r>
  34760. 800f920: 3001 adds r0, #1
  34761. 800f922: d0d7 beq.n 800f8d4 <_puts_r+0x38>
  34762. 800f924: 250a movs r5, #10
  34763. 800f926: e7d7 b.n 800f8d8 <_puts_r+0x3c>
  34764. 800f928: 4622 mov r2, r4
  34765. 800f92a: 4628 mov r0, r5
  34766. 800f92c: f000 f857 bl 800f9de <__swbuf_r>
  34767. 800f930: 3001 adds r0, #1
  34768. 800f932: d1e7 bne.n 800f904 <_puts_r+0x68>
  34769. 800f934: e7ce b.n 800f8d4 <_puts_r+0x38>
  34770. 800f936: 3e01 subs r6, #1
  34771. 800f938: e7e4 b.n 800f904 <_puts_r+0x68>
  34772. 800f93a: 6823 ldr r3, [r4, #0]
  34773. 800f93c: 1c5a adds r2, r3, #1
  34774. 800f93e: 6022 str r2, [r4, #0]
  34775. 800f940: 220a movs r2, #10
  34776. 800f942: 701a strb r2, [r3, #0]
  34777. 800f944: e7ee b.n 800f924 <_puts_r+0x88>
  34778. ...
  34779. 0800f948 <puts>:
  34780. 800f948: 4b02 ldr r3, [pc, #8] @ (800f954 <puts+0xc>)
  34781. 800f94a: 4601 mov r1, r0
  34782. 800f94c: 6818 ldr r0, [r3, #0]
  34783. 800f94e: f7ff bfa5 b.w 800f89c <_puts_r>
  34784. 800f952: bf00 nop
  34785. 800f954: 24000054 .word 0x24000054
  34786. 0800f958 <__sread>:
  34787. 800f958: b510 push {r4, lr}
  34788. 800f95a: 460c mov r4, r1
  34789. 800f95c: f9b1 100e ldrsh.w r1, [r1, #14]
  34790. 800f960: f000 f956 bl 800fc10 <_read_r>
  34791. 800f964: 2800 cmp r0, #0
  34792. 800f966: bfab itete ge
  34793. 800f968: 6d63 ldrge r3, [r4, #84] @ 0x54
  34794. 800f96a: 89a3 ldrhlt r3, [r4, #12]
  34795. 800f96c: 181b addge r3, r3, r0
  34796. 800f96e: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
  34797. 800f972: bfac ite ge
  34798. 800f974: 6563 strge r3, [r4, #84] @ 0x54
  34799. 800f976: 81a3 strhlt r3, [r4, #12]
  34800. 800f978: bd10 pop {r4, pc}
  34801. 0800f97a <__swrite>:
  34802. 800f97a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  34803. 800f97e: 461f mov r7, r3
  34804. 800f980: 898b ldrh r3, [r1, #12]
  34805. 800f982: 05db lsls r3, r3, #23
  34806. 800f984: 4605 mov r5, r0
  34807. 800f986: 460c mov r4, r1
  34808. 800f988: 4616 mov r6, r2
  34809. 800f98a: d505 bpl.n 800f998 <__swrite+0x1e>
  34810. 800f98c: f9b1 100e ldrsh.w r1, [r1, #14]
  34811. 800f990: 2302 movs r3, #2
  34812. 800f992: 2200 movs r2, #0
  34813. 800f994: f000 f92a bl 800fbec <_lseek_r>
  34814. 800f998: 89a3 ldrh r3, [r4, #12]
  34815. 800f99a: f9b4 100e ldrsh.w r1, [r4, #14]
  34816. 800f99e: f423 5380 bic.w r3, r3, #4096 @ 0x1000
  34817. 800f9a2: 81a3 strh r3, [r4, #12]
  34818. 800f9a4: 4632 mov r2, r6
  34819. 800f9a6: 463b mov r3, r7
  34820. 800f9a8: 4628 mov r0, r5
  34821. 800f9aa: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
  34822. 800f9ae: f000 b941 b.w 800fc34 <_write_r>
  34823. 0800f9b2 <__sseek>:
  34824. 800f9b2: b510 push {r4, lr}
  34825. 800f9b4: 460c mov r4, r1
  34826. 800f9b6: f9b1 100e ldrsh.w r1, [r1, #14]
  34827. 800f9ba: f000 f917 bl 800fbec <_lseek_r>
  34828. 800f9be: 1c43 adds r3, r0, #1
  34829. 800f9c0: 89a3 ldrh r3, [r4, #12]
  34830. 800f9c2: bf15 itete ne
  34831. 800f9c4: 6560 strne r0, [r4, #84] @ 0x54
  34832. 800f9c6: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
  34833. 800f9ca: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
  34834. 800f9ce: 81a3 strheq r3, [r4, #12]
  34835. 800f9d0: bf18 it ne
  34836. 800f9d2: 81a3 strhne r3, [r4, #12]
  34837. 800f9d4: bd10 pop {r4, pc}
  34838. 0800f9d6 <__sclose>:
  34839. 800f9d6: f9b1 100e ldrsh.w r1, [r1, #14]
  34840. 800f9da: f000 b8a1 b.w 800fb20 <_close_r>
  34841. 0800f9de <__swbuf_r>:
  34842. 800f9de: b5f8 push {r3, r4, r5, r6, r7, lr}
  34843. 800f9e0: 460e mov r6, r1
  34844. 800f9e2: 4614 mov r4, r2
  34845. 800f9e4: 4605 mov r5, r0
  34846. 800f9e6: b118 cbz r0, 800f9f0 <__swbuf_r+0x12>
  34847. 800f9e8: 6a03 ldr r3, [r0, #32]
  34848. 800f9ea: b90b cbnz r3, 800f9f0 <__swbuf_r+0x12>
  34849. 800f9ec: f7ff ff20 bl 800f830 <__sinit>
  34850. 800f9f0: 69a3 ldr r3, [r4, #24]
  34851. 800f9f2: 60a3 str r3, [r4, #8]
  34852. 800f9f4: 89a3 ldrh r3, [r4, #12]
  34853. 800f9f6: 071a lsls r2, r3, #28
  34854. 800f9f8: d501 bpl.n 800f9fe <__swbuf_r+0x20>
  34855. 800f9fa: 6923 ldr r3, [r4, #16]
  34856. 800f9fc: b943 cbnz r3, 800fa10 <__swbuf_r+0x32>
  34857. 800f9fe: 4621 mov r1, r4
  34858. 800fa00: 4628 mov r0, r5
  34859. 800fa02: f000 f82b bl 800fa5c <__swsetup_r>
  34860. 800fa06: b118 cbz r0, 800fa10 <__swbuf_r+0x32>
  34861. 800fa08: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff
  34862. 800fa0c: 4638 mov r0, r7
  34863. 800fa0e: bdf8 pop {r3, r4, r5, r6, r7, pc}
  34864. 800fa10: 6823 ldr r3, [r4, #0]
  34865. 800fa12: 6922 ldr r2, [r4, #16]
  34866. 800fa14: 1a98 subs r0, r3, r2
  34867. 800fa16: 6963 ldr r3, [r4, #20]
  34868. 800fa18: b2f6 uxtb r6, r6
  34869. 800fa1a: 4283 cmp r3, r0
  34870. 800fa1c: 4637 mov r7, r6
  34871. 800fa1e: dc05 bgt.n 800fa2c <__swbuf_r+0x4e>
  34872. 800fa20: 4621 mov r1, r4
  34873. 800fa22: 4628 mov r0, r5
  34874. 800fa24: f001 fc38 bl 8011298 <_fflush_r>
  34875. 800fa28: 2800 cmp r0, #0
  34876. 800fa2a: d1ed bne.n 800fa08 <__swbuf_r+0x2a>
  34877. 800fa2c: 68a3 ldr r3, [r4, #8]
  34878. 800fa2e: 3b01 subs r3, #1
  34879. 800fa30: 60a3 str r3, [r4, #8]
  34880. 800fa32: 6823 ldr r3, [r4, #0]
  34881. 800fa34: 1c5a adds r2, r3, #1
  34882. 800fa36: 6022 str r2, [r4, #0]
  34883. 800fa38: 701e strb r6, [r3, #0]
  34884. 800fa3a: 6962 ldr r2, [r4, #20]
  34885. 800fa3c: 1c43 adds r3, r0, #1
  34886. 800fa3e: 429a cmp r2, r3
  34887. 800fa40: d004 beq.n 800fa4c <__swbuf_r+0x6e>
  34888. 800fa42: 89a3 ldrh r3, [r4, #12]
  34889. 800fa44: 07db lsls r3, r3, #31
  34890. 800fa46: d5e1 bpl.n 800fa0c <__swbuf_r+0x2e>
  34891. 800fa48: 2e0a cmp r6, #10
  34892. 800fa4a: d1df bne.n 800fa0c <__swbuf_r+0x2e>
  34893. 800fa4c: 4621 mov r1, r4
  34894. 800fa4e: 4628 mov r0, r5
  34895. 800fa50: f001 fc22 bl 8011298 <_fflush_r>
  34896. 800fa54: 2800 cmp r0, #0
  34897. 800fa56: d0d9 beq.n 800fa0c <__swbuf_r+0x2e>
  34898. 800fa58: e7d6 b.n 800fa08 <__swbuf_r+0x2a>
  34899. ...
  34900. 0800fa5c <__swsetup_r>:
  34901. 800fa5c: b538 push {r3, r4, r5, lr}
  34902. 800fa5e: 4b29 ldr r3, [pc, #164] @ (800fb04 <__swsetup_r+0xa8>)
  34903. 800fa60: 4605 mov r5, r0
  34904. 800fa62: 6818 ldr r0, [r3, #0]
  34905. 800fa64: 460c mov r4, r1
  34906. 800fa66: b118 cbz r0, 800fa70 <__swsetup_r+0x14>
  34907. 800fa68: 6a03 ldr r3, [r0, #32]
  34908. 800fa6a: b90b cbnz r3, 800fa70 <__swsetup_r+0x14>
  34909. 800fa6c: f7ff fee0 bl 800f830 <__sinit>
  34910. 800fa70: f9b4 300c ldrsh.w r3, [r4, #12]
  34911. 800fa74: 0719 lsls r1, r3, #28
  34912. 800fa76: d422 bmi.n 800fabe <__swsetup_r+0x62>
  34913. 800fa78: 06da lsls r2, r3, #27
  34914. 800fa7a: d407 bmi.n 800fa8c <__swsetup_r+0x30>
  34915. 800fa7c: 2209 movs r2, #9
  34916. 800fa7e: 602a str r2, [r5, #0]
  34917. 800fa80: f043 0340 orr.w r3, r3, #64 @ 0x40
  34918. 800fa84: 81a3 strh r3, [r4, #12]
  34919. 800fa86: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  34920. 800fa8a: e033 b.n 800faf4 <__swsetup_r+0x98>
  34921. 800fa8c: 0758 lsls r0, r3, #29
  34922. 800fa8e: d512 bpl.n 800fab6 <__swsetup_r+0x5a>
  34923. 800fa90: 6b61 ldr r1, [r4, #52] @ 0x34
  34924. 800fa92: b141 cbz r1, 800faa6 <__swsetup_r+0x4a>
  34925. 800fa94: f104 0344 add.w r3, r4, #68 @ 0x44
  34926. 800fa98: 4299 cmp r1, r3
  34927. 800fa9a: d002 beq.n 800faa2 <__swsetup_r+0x46>
  34928. 800fa9c: 4628 mov r0, r5
  34929. 800fa9e: f000 fef5 bl 801088c <_free_r>
  34930. 800faa2: 2300 movs r3, #0
  34931. 800faa4: 6363 str r3, [r4, #52] @ 0x34
  34932. 800faa6: 89a3 ldrh r3, [r4, #12]
  34933. 800faa8: f023 0324 bic.w r3, r3, #36 @ 0x24
  34934. 800faac: 81a3 strh r3, [r4, #12]
  34935. 800faae: 2300 movs r3, #0
  34936. 800fab0: 6063 str r3, [r4, #4]
  34937. 800fab2: 6923 ldr r3, [r4, #16]
  34938. 800fab4: 6023 str r3, [r4, #0]
  34939. 800fab6: 89a3 ldrh r3, [r4, #12]
  34940. 800fab8: f043 0308 orr.w r3, r3, #8
  34941. 800fabc: 81a3 strh r3, [r4, #12]
  34942. 800fabe: 6923 ldr r3, [r4, #16]
  34943. 800fac0: b94b cbnz r3, 800fad6 <__swsetup_r+0x7a>
  34944. 800fac2: 89a3 ldrh r3, [r4, #12]
  34945. 800fac4: f403 7320 and.w r3, r3, #640 @ 0x280
  34946. 800fac8: f5b3 7f00 cmp.w r3, #512 @ 0x200
  34947. 800facc: d003 beq.n 800fad6 <__swsetup_r+0x7a>
  34948. 800face: 4621 mov r1, r4
  34949. 800fad0: 4628 mov r0, r5
  34950. 800fad2: f001 fc2f bl 8011334 <__smakebuf_r>
  34951. 800fad6: f9b4 300c ldrsh.w r3, [r4, #12]
  34952. 800fada: f013 0201 ands.w r2, r3, #1
  34953. 800fade: d00a beq.n 800faf6 <__swsetup_r+0x9a>
  34954. 800fae0: 2200 movs r2, #0
  34955. 800fae2: 60a2 str r2, [r4, #8]
  34956. 800fae4: 6962 ldr r2, [r4, #20]
  34957. 800fae6: 4252 negs r2, r2
  34958. 800fae8: 61a2 str r2, [r4, #24]
  34959. 800faea: 6922 ldr r2, [r4, #16]
  34960. 800faec: b942 cbnz r2, 800fb00 <__swsetup_r+0xa4>
  34961. 800faee: f013 0080 ands.w r0, r3, #128 @ 0x80
  34962. 800faf2: d1c5 bne.n 800fa80 <__swsetup_r+0x24>
  34963. 800faf4: bd38 pop {r3, r4, r5, pc}
  34964. 800faf6: 0799 lsls r1, r3, #30
  34965. 800faf8: bf58 it pl
  34966. 800fafa: 6962 ldrpl r2, [r4, #20]
  34967. 800fafc: 60a2 str r2, [r4, #8]
  34968. 800fafe: e7f4 b.n 800faea <__swsetup_r+0x8e>
  34969. 800fb00: 2000 movs r0, #0
  34970. 800fb02: e7f7 b.n 800faf4 <__swsetup_r+0x98>
  34971. 800fb04: 24000054 .word 0x24000054
  34972. 0800fb08 <memset>:
  34973. 800fb08: 4402 add r2, r0
  34974. 800fb0a: 4603 mov r3, r0
  34975. 800fb0c: 4293 cmp r3, r2
  34976. 800fb0e: d100 bne.n 800fb12 <memset+0xa>
  34977. 800fb10: 4770 bx lr
  34978. 800fb12: f803 1b01 strb.w r1, [r3], #1
  34979. 800fb16: e7f9 b.n 800fb0c <memset+0x4>
  34980. 0800fb18 <_localeconv_r>:
  34981. 800fb18: 4800 ldr r0, [pc, #0] @ (800fb1c <_localeconv_r+0x4>)
  34982. 800fb1a: 4770 bx lr
  34983. 800fb1c: 24000194 .word 0x24000194
  34984. 0800fb20 <_close_r>:
  34985. 800fb20: b538 push {r3, r4, r5, lr}
  34986. 800fb22: 4d06 ldr r5, [pc, #24] @ (800fb3c <_close_r+0x1c>)
  34987. 800fb24: 2300 movs r3, #0
  34988. 800fb26: 4604 mov r4, r0
  34989. 800fb28: 4608 mov r0, r1
  34990. 800fb2a: 602b str r3, [r5, #0]
  34991. 800fb2c: f7f3 fad8 bl 80030e0 <_close>
  34992. 800fb30: 1c43 adds r3, r0, #1
  34993. 800fb32: d102 bne.n 800fb3a <_close_r+0x1a>
  34994. 800fb34: 682b ldr r3, [r5, #0]
  34995. 800fb36: b103 cbz r3, 800fb3a <_close_r+0x1a>
  34996. 800fb38: 6023 str r3, [r4, #0]
  34997. 800fb3a: bd38 pop {r3, r4, r5, pc}
  34998. 800fb3c: 240132d4 .word 0x240132d4
  34999. 0800fb40 <_reclaim_reent>:
  35000. 800fb40: 4b29 ldr r3, [pc, #164] @ (800fbe8 <_reclaim_reent+0xa8>)
  35001. 800fb42: 681b ldr r3, [r3, #0]
  35002. 800fb44: 4283 cmp r3, r0
  35003. 800fb46: b570 push {r4, r5, r6, lr}
  35004. 800fb48: 4604 mov r4, r0
  35005. 800fb4a: d04b beq.n 800fbe4 <_reclaim_reent+0xa4>
  35006. 800fb4c: 69c3 ldr r3, [r0, #28]
  35007. 800fb4e: b1ab cbz r3, 800fb7c <_reclaim_reent+0x3c>
  35008. 800fb50: 68db ldr r3, [r3, #12]
  35009. 800fb52: b16b cbz r3, 800fb70 <_reclaim_reent+0x30>
  35010. 800fb54: 2500 movs r5, #0
  35011. 800fb56: 69e3 ldr r3, [r4, #28]
  35012. 800fb58: 68db ldr r3, [r3, #12]
  35013. 800fb5a: 5959 ldr r1, [r3, r5]
  35014. 800fb5c: 2900 cmp r1, #0
  35015. 800fb5e: d13b bne.n 800fbd8 <_reclaim_reent+0x98>
  35016. 800fb60: 3504 adds r5, #4
  35017. 800fb62: 2d80 cmp r5, #128 @ 0x80
  35018. 800fb64: d1f7 bne.n 800fb56 <_reclaim_reent+0x16>
  35019. 800fb66: 69e3 ldr r3, [r4, #28]
  35020. 800fb68: 4620 mov r0, r4
  35021. 800fb6a: 68d9 ldr r1, [r3, #12]
  35022. 800fb6c: f000 fe8e bl 801088c <_free_r>
  35023. 800fb70: 69e3 ldr r3, [r4, #28]
  35024. 800fb72: 6819 ldr r1, [r3, #0]
  35025. 800fb74: b111 cbz r1, 800fb7c <_reclaim_reent+0x3c>
  35026. 800fb76: 4620 mov r0, r4
  35027. 800fb78: f000 fe88 bl 801088c <_free_r>
  35028. 800fb7c: 6961 ldr r1, [r4, #20]
  35029. 800fb7e: b111 cbz r1, 800fb86 <_reclaim_reent+0x46>
  35030. 800fb80: 4620 mov r0, r4
  35031. 800fb82: f000 fe83 bl 801088c <_free_r>
  35032. 800fb86: 69e1 ldr r1, [r4, #28]
  35033. 800fb88: b111 cbz r1, 800fb90 <_reclaim_reent+0x50>
  35034. 800fb8a: 4620 mov r0, r4
  35035. 800fb8c: f000 fe7e bl 801088c <_free_r>
  35036. 800fb90: 6b21 ldr r1, [r4, #48] @ 0x30
  35037. 800fb92: b111 cbz r1, 800fb9a <_reclaim_reent+0x5a>
  35038. 800fb94: 4620 mov r0, r4
  35039. 800fb96: f000 fe79 bl 801088c <_free_r>
  35040. 800fb9a: 6b61 ldr r1, [r4, #52] @ 0x34
  35041. 800fb9c: b111 cbz r1, 800fba4 <_reclaim_reent+0x64>
  35042. 800fb9e: 4620 mov r0, r4
  35043. 800fba0: f000 fe74 bl 801088c <_free_r>
  35044. 800fba4: 6ba1 ldr r1, [r4, #56] @ 0x38
  35045. 800fba6: b111 cbz r1, 800fbae <_reclaim_reent+0x6e>
  35046. 800fba8: 4620 mov r0, r4
  35047. 800fbaa: f000 fe6f bl 801088c <_free_r>
  35048. 800fbae: 6ca1 ldr r1, [r4, #72] @ 0x48
  35049. 800fbb0: b111 cbz r1, 800fbb8 <_reclaim_reent+0x78>
  35050. 800fbb2: 4620 mov r0, r4
  35051. 800fbb4: f000 fe6a bl 801088c <_free_r>
  35052. 800fbb8: 6c61 ldr r1, [r4, #68] @ 0x44
  35053. 800fbba: b111 cbz r1, 800fbc2 <_reclaim_reent+0x82>
  35054. 800fbbc: 4620 mov r0, r4
  35055. 800fbbe: f000 fe65 bl 801088c <_free_r>
  35056. 800fbc2: 6ae1 ldr r1, [r4, #44] @ 0x2c
  35057. 800fbc4: b111 cbz r1, 800fbcc <_reclaim_reent+0x8c>
  35058. 800fbc6: 4620 mov r0, r4
  35059. 800fbc8: f000 fe60 bl 801088c <_free_r>
  35060. 800fbcc: 6a23 ldr r3, [r4, #32]
  35061. 800fbce: b14b cbz r3, 800fbe4 <_reclaim_reent+0xa4>
  35062. 800fbd0: 4620 mov r0, r4
  35063. 800fbd2: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  35064. 800fbd6: 4718 bx r3
  35065. 800fbd8: 680e ldr r6, [r1, #0]
  35066. 800fbda: 4620 mov r0, r4
  35067. 800fbdc: f000 fe56 bl 801088c <_free_r>
  35068. 800fbe0: 4631 mov r1, r6
  35069. 800fbe2: e7bb b.n 800fb5c <_reclaim_reent+0x1c>
  35070. 800fbe4: bd70 pop {r4, r5, r6, pc}
  35071. 800fbe6: bf00 nop
  35072. 800fbe8: 24000054 .word 0x24000054
  35073. 0800fbec <_lseek_r>:
  35074. 800fbec: b538 push {r3, r4, r5, lr}
  35075. 800fbee: 4d07 ldr r5, [pc, #28] @ (800fc0c <_lseek_r+0x20>)
  35076. 800fbf0: 4604 mov r4, r0
  35077. 800fbf2: 4608 mov r0, r1
  35078. 800fbf4: 4611 mov r1, r2
  35079. 800fbf6: 2200 movs r2, #0
  35080. 800fbf8: 602a str r2, [r5, #0]
  35081. 800fbfa: 461a mov r2, r3
  35082. 800fbfc: f7f3 fa7c bl 80030f8 <_lseek>
  35083. 800fc00: 1c43 adds r3, r0, #1
  35084. 800fc02: d102 bne.n 800fc0a <_lseek_r+0x1e>
  35085. 800fc04: 682b ldr r3, [r5, #0]
  35086. 800fc06: b103 cbz r3, 800fc0a <_lseek_r+0x1e>
  35087. 800fc08: 6023 str r3, [r4, #0]
  35088. 800fc0a: bd38 pop {r3, r4, r5, pc}
  35089. 800fc0c: 240132d4 .word 0x240132d4
  35090. 0800fc10 <_read_r>:
  35091. 800fc10: b538 push {r3, r4, r5, lr}
  35092. 800fc12: 4d07 ldr r5, [pc, #28] @ (800fc30 <_read_r+0x20>)
  35093. 800fc14: 4604 mov r4, r0
  35094. 800fc16: 4608 mov r0, r1
  35095. 800fc18: 4611 mov r1, r2
  35096. 800fc1a: 2200 movs r2, #0
  35097. 800fc1c: 602a str r2, [r5, #0]
  35098. 800fc1e: 461a mov r2, r3
  35099. 800fc20: f7f3 fa42 bl 80030a8 <_read>
  35100. 800fc24: 1c43 adds r3, r0, #1
  35101. 800fc26: d102 bne.n 800fc2e <_read_r+0x1e>
  35102. 800fc28: 682b ldr r3, [r5, #0]
  35103. 800fc2a: b103 cbz r3, 800fc2e <_read_r+0x1e>
  35104. 800fc2c: 6023 str r3, [r4, #0]
  35105. 800fc2e: bd38 pop {r3, r4, r5, pc}
  35106. 800fc30: 240132d4 .word 0x240132d4
  35107. 0800fc34 <_write_r>:
  35108. 800fc34: b538 push {r3, r4, r5, lr}
  35109. 800fc36: 4d07 ldr r5, [pc, #28] @ (800fc54 <_write_r+0x20>)
  35110. 800fc38: 4604 mov r4, r0
  35111. 800fc3a: 4608 mov r0, r1
  35112. 800fc3c: 4611 mov r1, r2
  35113. 800fc3e: 2200 movs r2, #0
  35114. 800fc40: 602a str r2, [r5, #0]
  35115. 800fc42: 461a mov r2, r3
  35116. 800fc44: f7f3 fa3e bl 80030c4 <_write>
  35117. 800fc48: 1c43 adds r3, r0, #1
  35118. 800fc4a: d102 bne.n 800fc52 <_write_r+0x1e>
  35119. 800fc4c: 682b ldr r3, [r5, #0]
  35120. 800fc4e: b103 cbz r3, 800fc52 <_write_r+0x1e>
  35121. 800fc50: 6023 str r3, [r4, #0]
  35122. 800fc52: bd38 pop {r3, r4, r5, pc}
  35123. 800fc54: 240132d4 .word 0x240132d4
  35124. 0800fc58 <__errno>:
  35125. 800fc58: 4b01 ldr r3, [pc, #4] @ (800fc60 <__errno+0x8>)
  35126. 800fc5a: 6818 ldr r0, [r3, #0]
  35127. 800fc5c: 4770 bx lr
  35128. 800fc5e: bf00 nop
  35129. 800fc60: 24000054 .word 0x24000054
  35130. 0800fc64 <__libc_init_array>:
  35131. 800fc64: b570 push {r4, r5, r6, lr}
  35132. 800fc66: 4d0d ldr r5, [pc, #52] @ (800fc9c <__libc_init_array+0x38>)
  35133. 800fc68: 4c0d ldr r4, [pc, #52] @ (800fca0 <__libc_init_array+0x3c>)
  35134. 800fc6a: 1b64 subs r4, r4, r5
  35135. 800fc6c: 10a4 asrs r4, r4, #2
  35136. 800fc6e: 2600 movs r6, #0
  35137. 800fc70: 42a6 cmp r6, r4
  35138. 800fc72: d109 bne.n 800fc88 <__libc_init_array+0x24>
  35139. 800fc74: 4d0b ldr r5, [pc, #44] @ (800fca4 <__libc_init_array+0x40>)
  35140. 800fc76: 4c0c ldr r4, [pc, #48] @ (800fca8 <__libc_init_array+0x44>)
  35141. 800fc78: f001 fe5c bl 8011934 <_init>
  35142. 800fc7c: 1b64 subs r4, r4, r5
  35143. 800fc7e: 10a4 asrs r4, r4, #2
  35144. 800fc80: 2600 movs r6, #0
  35145. 800fc82: 42a6 cmp r6, r4
  35146. 800fc84: d105 bne.n 800fc92 <__libc_init_array+0x2e>
  35147. 800fc86: bd70 pop {r4, r5, r6, pc}
  35148. 800fc88: f855 3b04 ldr.w r3, [r5], #4
  35149. 800fc8c: 4798 blx r3
  35150. 800fc8e: 3601 adds r6, #1
  35151. 800fc90: e7ee b.n 800fc70 <__libc_init_array+0xc>
  35152. 800fc92: f855 3b04 ldr.w r3, [r5], #4
  35153. 800fc96: 4798 blx r3
  35154. 800fc98: 3601 adds r6, #1
  35155. 800fc9a: e7f2 b.n 800fc82 <__libc_init_array+0x1e>
  35156. 800fc9c: 08011df0 .word 0x08011df0
  35157. 800fca0: 08011df0 .word 0x08011df0
  35158. 800fca4: 08011df0 .word 0x08011df0
  35159. 800fca8: 08011df4 .word 0x08011df4
  35160. 0800fcac <__retarget_lock_init_recursive>:
  35161. 800fcac: 4770 bx lr
  35162. 0800fcae <__retarget_lock_acquire_recursive>:
  35163. 800fcae: 4770 bx lr
  35164. 0800fcb0 <__retarget_lock_release_recursive>:
  35165. 800fcb0: 4770 bx lr
  35166. 0800fcb2 <memcpy>:
  35167. 800fcb2: 440a add r2, r1
  35168. 800fcb4: 4291 cmp r1, r2
  35169. 800fcb6: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
  35170. 800fcba: d100 bne.n 800fcbe <memcpy+0xc>
  35171. 800fcbc: 4770 bx lr
  35172. 800fcbe: b510 push {r4, lr}
  35173. 800fcc0: f811 4b01 ldrb.w r4, [r1], #1
  35174. 800fcc4: f803 4f01 strb.w r4, [r3, #1]!
  35175. 800fcc8: 4291 cmp r1, r2
  35176. 800fcca: d1f9 bne.n 800fcc0 <memcpy+0xe>
  35177. 800fccc: bd10 pop {r4, pc}
  35178. 0800fcce <quorem>:
  35179. 800fcce: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  35180. 800fcd2: 6903 ldr r3, [r0, #16]
  35181. 800fcd4: 690c ldr r4, [r1, #16]
  35182. 800fcd6: 42a3 cmp r3, r4
  35183. 800fcd8: 4607 mov r7, r0
  35184. 800fcda: db7e blt.n 800fdda <quorem+0x10c>
  35185. 800fcdc: 3c01 subs r4, #1
  35186. 800fcde: f101 0814 add.w r8, r1, #20
  35187. 800fce2: 00a3 lsls r3, r4, #2
  35188. 800fce4: f100 0514 add.w r5, r0, #20
  35189. 800fce8: 9300 str r3, [sp, #0]
  35190. 800fcea: eb05 0384 add.w r3, r5, r4, lsl #2
  35191. 800fcee: 9301 str r3, [sp, #4]
  35192. 800fcf0: f858 3024 ldr.w r3, [r8, r4, lsl #2]
  35193. 800fcf4: f855 2024 ldr.w r2, [r5, r4, lsl #2]
  35194. 800fcf8: 3301 adds r3, #1
  35195. 800fcfa: 429a cmp r2, r3
  35196. 800fcfc: eb08 0984 add.w r9, r8, r4, lsl #2
  35197. 800fd00: fbb2 f6f3 udiv r6, r2, r3
  35198. 800fd04: d32e bcc.n 800fd64 <quorem+0x96>
  35199. 800fd06: f04f 0a00 mov.w sl, #0
  35200. 800fd0a: 46c4 mov ip, r8
  35201. 800fd0c: 46ae mov lr, r5
  35202. 800fd0e: 46d3 mov fp, sl
  35203. 800fd10: f85c 3b04 ldr.w r3, [ip], #4
  35204. 800fd14: b298 uxth r0, r3
  35205. 800fd16: fb06 a000 mla r0, r6, r0, sl
  35206. 800fd1a: 0c02 lsrs r2, r0, #16
  35207. 800fd1c: 0c1b lsrs r3, r3, #16
  35208. 800fd1e: fb06 2303 mla r3, r6, r3, r2
  35209. 800fd22: f8de 2000 ldr.w r2, [lr]
  35210. 800fd26: b280 uxth r0, r0
  35211. 800fd28: b292 uxth r2, r2
  35212. 800fd2a: 1a12 subs r2, r2, r0
  35213. 800fd2c: 445a add r2, fp
  35214. 800fd2e: f8de 0000 ldr.w r0, [lr]
  35215. 800fd32: ea4f 4a13 mov.w sl, r3, lsr #16
  35216. 800fd36: b29b uxth r3, r3
  35217. 800fd38: ebc3 4322 rsb r3, r3, r2, asr #16
  35218. 800fd3c: eb03 4310 add.w r3, r3, r0, lsr #16
  35219. 800fd40: b292 uxth r2, r2
  35220. 800fd42: ea42 4203 orr.w r2, r2, r3, lsl #16
  35221. 800fd46: 45e1 cmp r9, ip
  35222. 800fd48: f84e 2b04 str.w r2, [lr], #4
  35223. 800fd4c: ea4f 4b23 mov.w fp, r3, asr #16
  35224. 800fd50: d2de bcs.n 800fd10 <quorem+0x42>
  35225. 800fd52: 9b00 ldr r3, [sp, #0]
  35226. 800fd54: 58eb ldr r3, [r5, r3]
  35227. 800fd56: b92b cbnz r3, 800fd64 <quorem+0x96>
  35228. 800fd58: 9b01 ldr r3, [sp, #4]
  35229. 800fd5a: 3b04 subs r3, #4
  35230. 800fd5c: 429d cmp r5, r3
  35231. 800fd5e: 461a mov r2, r3
  35232. 800fd60: d32f bcc.n 800fdc2 <quorem+0xf4>
  35233. 800fd62: 613c str r4, [r7, #16]
  35234. 800fd64: 4638 mov r0, r7
  35235. 800fd66: f001 f90b bl 8010f80 <__mcmp>
  35236. 800fd6a: 2800 cmp r0, #0
  35237. 800fd6c: db25 blt.n 800fdba <quorem+0xec>
  35238. 800fd6e: 4629 mov r1, r5
  35239. 800fd70: 2000 movs r0, #0
  35240. 800fd72: f858 2b04 ldr.w r2, [r8], #4
  35241. 800fd76: f8d1 c000 ldr.w ip, [r1]
  35242. 800fd7a: fa1f fe82 uxth.w lr, r2
  35243. 800fd7e: fa1f f38c uxth.w r3, ip
  35244. 800fd82: eba3 030e sub.w r3, r3, lr
  35245. 800fd86: 4403 add r3, r0
  35246. 800fd88: 0c12 lsrs r2, r2, #16
  35247. 800fd8a: ebc2 4223 rsb r2, r2, r3, asr #16
  35248. 800fd8e: eb02 421c add.w r2, r2, ip, lsr #16
  35249. 800fd92: b29b uxth r3, r3
  35250. 800fd94: ea43 4302 orr.w r3, r3, r2, lsl #16
  35251. 800fd98: 45c1 cmp r9, r8
  35252. 800fd9a: f841 3b04 str.w r3, [r1], #4
  35253. 800fd9e: ea4f 4022 mov.w r0, r2, asr #16
  35254. 800fda2: d2e6 bcs.n 800fd72 <quorem+0xa4>
  35255. 800fda4: f855 2024 ldr.w r2, [r5, r4, lsl #2]
  35256. 800fda8: eb05 0384 add.w r3, r5, r4, lsl #2
  35257. 800fdac: b922 cbnz r2, 800fdb8 <quorem+0xea>
  35258. 800fdae: 3b04 subs r3, #4
  35259. 800fdb0: 429d cmp r5, r3
  35260. 800fdb2: 461a mov r2, r3
  35261. 800fdb4: d30b bcc.n 800fdce <quorem+0x100>
  35262. 800fdb6: 613c str r4, [r7, #16]
  35263. 800fdb8: 3601 adds r6, #1
  35264. 800fdba: 4630 mov r0, r6
  35265. 800fdbc: b003 add sp, #12
  35266. 800fdbe: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  35267. 800fdc2: 6812 ldr r2, [r2, #0]
  35268. 800fdc4: 3b04 subs r3, #4
  35269. 800fdc6: 2a00 cmp r2, #0
  35270. 800fdc8: d1cb bne.n 800fd62 <quorem+0x94>
  35271. 800fdca: 3c01 subs r4, #1
  35272. 800fdcc: e7c6 b.n 800fd5c <quorem+0x8e>
  35273. 800fdce: 6812 ldr r2, [r2, #0]
  35274. 800fdd0: 3b04 subs r3, #4
  35275. 800fdd2: 2a00 cmp r2, #0
  35276. 800fdd4: d1ef bne.n 800fdb6 <quorem+0xe8>
  35277. 800fdd6: 3c01 subs r4, #1
  35278. 800fdd8: e7ea b.n 800fdb0 <quorem+0xe2>
  35279. 800fdda: 2000 movs r0, #0
  35280. 800fddc: e7ee b.n 800fdbc <quorem+0xee>
  35281. ...
  35282. 0800fde0 <_dtoa_r>:
  35283. 800fde0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  35284. 800fde4: ed2d 8b02 vpush {d8}
  35285. 800fde8: 69c7 ldr r7, [r0, #28]
  35286. 800fdea: b091 sub sp, #68 @ 0x44
  35287. 800fdec: ed8d 0b02 vstr d0, [sp, #8]
  35288. 800fdf0: ec55 4b10 vmov r4, r5, d0
  35289. 800fdf4: 9e1c ldr r6, [sp, #112] @ 0x70
  35290. 800fdf6: 9107 str r1, [sp, #28]
  35291. 800fdf8: 4681 mov r9, r0
  35292. 800fdfa: 9209 str r2, [sp, #36] @ 0x24
  35293. 800fdfc: 930d str r3, [sp, #52] @ 0x34
  35294. 800fdfe: b97f cbnz r7, 800fe20 <_dtoa_r+0x40>
  35295. 800fe00: 2010 movs r0, #16
  35296. 800fe02: f000 fd8d bl 8010920 <malloc>
  35297. 800fe06: 4602 mov r2, r0
  35298. 800fe08: f8c9 001c str.w r0, [r9, #28]
  35299. 800fe0c: b920 cbnz r0, 800fe18 <_dtoa_r+0x38>
  35300. 800fe0e: 4ba0 ldr r3, [pc, #640] @ (8010090 <_dtoa_r+0x2b0>)
  35301. 800fe10: 21ef movs r1, #239 @ 0xef
  35302. 800fe12: 48a0 ldr r0, [pc, #640] @ (8010094 <_dtoa_r+0x2b4>)
  35303. 800fe14: f001 fafc bl 8011410 <__assert_func>
  35304. 800fe18: e9c0 7701 strd r7, r7, [r0, #4]
  35305. 800fe1c: 6007 str r7, [r0, #0]
  35306. 800fe1e: 60c7 str r7, [r0, #12]
  35307. 800fe20: f8d9 301c ldr.w r3, [r9, #28]
  35308. 800fe24: 6819 ldr r1, [r3, #0]
  35309. 800fe26: b159 cbz r1, 800fe40 <_dtoa_r+0x60>
  35310. 800fe28: 685a ldr r2, [r3, #4]
  35311. 800fe2a: 604a str r2, [r1, #4]
  35312. 800fe2c: 2301 movs r3, #1
  35313. 800fe2e: 4093 lsls r3, r2
  35314. 800fe30: 608b str r3, [r1, #8]
  35315. 800fe32: 4648 mov r0, r9
  35316. 800fe34: f000 fe6a bl 8010b0c <_Bfree>
  35317. 800fe38: f8d9 301c ldr.w r3, [r9, #28]
  35318. 800fe3c: 2200 movs r2, #0
  35319. 800fe3e: 601a str r2, [r3, #0]
  35320. 800fe40: 1e2b subs r3, r5, #0
  35321. 800fe42: bfbb ittet lt
  35322. 800fe44: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000
  35323. 800fe48: 9303 strlt r3, [sp, #12]
  35324. 800fe4a: 2300 movge r3, #0
  35325. 800fe4c: 2201 movlt r2, #1
  35326. 800fe4e: bfac ite ge
  35327. 800fe50: 6033 strge r3, [r6, #0]
  35328. 800fe52: 6032 strlt r2, [r6, #0]
  35329. 800fe54: 4b90 ldr r3, [pc, #576] @ (8010098 <_dtoa_r+0x2b8>)
  35330. 800fe56: 9e03 ldr r6, [sp, #12]
  35331. 800fe58: 43b3 bics r3, r6
  35332. 800fe5a: d110 bne.n 800fe7e <_dtoa_r+0x9e>
  35333. 800fe5c: 9a0d ldr r2, [sp, #52] @ 0x34
  35334. 800fe5e: f242 730f movw r3, #9999 @ 0x270f
  35335. 800fe62: 6013 str r3, [r2, #0]
  35336. 800fe64: f3c6 0313 ubfx r3, r6, #0, #20
  35337. 800fe68: 4323 orrs r3, r4
  35338. 800fe6a: f000 84de beq.w 801082a <_dtoa_r+0xa4a>
  35339. 800fe6e: 9b1d ldr r3, [sp, #116] @ 0x74
  35340. 800fe70: 4f8a ldr r7, [pc, #552] @ (801009c <_dtoa_r+0x2bc>)
  35341. 800fe72: 2b00 cmp r3, #0
  35342. 800fe74: f000 84e0 beq.w 8010838 <_dtoa_r+0xa58>
  35343. 800fe78: 1cfb adds r3, r7, #3
  35344. 800fe7a: f000 bcdb b.w 8010834 <_dtoa_r+0xa54>
  35345. 800fe7e: ed9d 8b02 vldr d8, [sp, #8]
  35346. 800fe82: eeb5 8b40 vcmp.f64 d8, #0.0
  35347. 800fe86: eef1 fa10 vmrs APSR_nzcv, fpscr
  35348. 800fe8a: d10a bne.n 800fea2 <_dtoa_r+0xc2>
  35349. 800fe8c: 9a0d ldr r2, [sp, #52] @ 0x34
  35350. 800fe8e: 2301 movs r3, #1
  35351. 800fe90: 6013 str r3, [r2, #0]
  35352. 800fe92: 9b1d ldr r3, [sp, #116] @ 0x74
  35353. 800fe94: b113 cbz r3, 800fe9c <_dtoa_r+0xbc>
  35354. 800fe96: 9a1d ldr r2, [sp, #116] @ 0x74
  35355. 800fe98: 4b81 ldr r3, [pc, #516] @ (80100a0 <_dtoa_r+0x2c0>)
  35356. 800fe9a: 6013 str r3, [r2, #0]
  35357. 800fe9c: 4f81 ldr r7, [pc, #516] @ (80100a4 <_dtoa_r+0x2c4>)
  35358. 800fe9e: f000 bccb b.w 8010838 <_dtoa_r+0xa58>
  35359. 800fea2: aa0e add r2, sp, #56 @ 0x38
  35360. 800fea4: a90f add r1, sp, #60 @ 0x3c
  35361. 800fea6: 4648 mov r0, r9
  35362. 800fea8: eeb0 0b48 vmov.f64 d0, d8
  35363. 800feac: f001 f918 bl 80110e0 <__d2b>
  35364. 800feb0: f3c6 530a ubfx r3, r6, #20, #11
  35365. 800feb4: 9a0e ldr r2, [sp, #56] @ 0x38
  35366. 800feb6: 9001 str r0, [sp, #4]
  35367. 800feb8: 2b00 cmp r3, #0
  35368. 800feba: d045 beq.n 800ff48 <_dtoa_r+0x168>
  35369. 800febc: eeb0 7b48 vmov.f64 d7, d8
  35370. 800fec0: ee18 1a90 vmov r1, s17
  35371. 800fec4: f3c1 0113 ubfx r1, r1, #0, #20
  35372. 800fec8: f041 517f orr.w r1, r1, #1069547520 @ 0x3fc00000
  35373. 800fecc: f441 1140 orr.w r1, r1, #3145728 @ 0x300000
  35374. 800fed0: f2a3 33ff subw r3, r3, #1023 @ 0x3ff
  35375. 800fed4: 2500 movs r5, #0
  35376. 800fed6: ee07 1a90 vmov s15, r1
  35377. 800feda: eeb7 6b08 vmov.f64 d6, #120 @ 0x3fc00000 1.5
  35378. 800fede: ed9f 5b66 vldr d5, [pc, #408] @ 8010078 <_dtoa_r+0x298>
  35379. 800fee2: ee37 7b46 vsub.f64 d7, d7, d6
  35380. 800fee6: ed9f 6b66 vldr d6, [pc, #408] @ 8010080 <_dtoa_r+0x2a0>
  35381. 800feea: eea7 6b05 vfma.f64 d6, d7, d5
  35382. 800feee: ed9f 5b66 vldr d5, [pc, #408] @ 8010088 <_dtoa_r+0x2a8>
  35383. 800fef2: ee07 3a90 vmov s15, r3
  35384. 800fef6: eeb8 4be7 vcvt.f64.s32 d4, s15
  35385. 800fefa: eeb0 7b46 vmov.f64 d7, d6
  35386. 800fefe: eea4 7b05 vfma.f64 d7, d4, d5
  35387. 800ff02: eefd 6bc7 vcvt.s32.f64 s13, d7
  35388. 800ff06: eeb5 7bc0 vcmpe.f64 d7, #0.0
  35389. 800ff0a: eef1 fa10 vmrs APSR_nzcv, fpscr
  35390. 800ff0e: ee16 8a90 vmov r8, s13
  35391. 800ff12: d508 bpl.n 800ff26 <_dtoa_r+0x146>
  35392. 800ff14: eeb8 6be6 vcvt.f64.s32 d6, s13
  35393. 800ff18: eeb4 6b47 vcmp.f64 d6, d7
  35394. 800ff1c: eef1 fa10 vmrs APSR_nzcv, fpscr
  35395. 800ff20: bf18 it ne
  35396. 800ff22: f108 38ff addne.w r8, r8, #4294967295 @ 0xffffffff
  35397. 800ff26: f1b8 0f16 cmp.w r8, #22
  35398. 800ff2a: d82b bhi.n 800ff84 <_dtoa_r+0x1a4>
  35399. 800ff2c: 495e ldr r1, [pc, #376] @ (80100a8 <_dtoa_r+0x2c8>)
  35400. 800ff2e: eb01 01c8 add.w r1, r1, r8, lsl #3
  35401. 800ff32: ed91 7b00 vldr d7, [r1]
  35402. 800ff36: eeb4 8bc7 vcmpe.f64 d8, d7
  35403. 800ff3a: eef1 fa10 vmrs APSR_nzcv, fpscr
  35404. 800ff3e: d501 bpl.n 800ff44 <_dtoa_r+0x164>
  35405. 800ff40: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff
  35406. 800ff44: 2100 movs r1, #0
  35407. 800ff46: e01e b.n 800ff86 <_dtoa_r+0x1a6>
  35408. 800ff48: 9b0f ldr r3, [sp, #60] @ 0x3c
  35409. 800ff4a: 4413 add r3, r2
  35410. 800ff4c: f203 4132 addw r1, r3, #1074 @ 0x432
  35411. 800ff50: 2920 cmp r1, #32
  35412. 800ff52: bfc1 itttt gt
  35413. 800ff54: f1c1 0140 rsbgt r1, r1, #64 @ 0x40
  35414. 800ff58: 408e lslgt r6, r1
  35415. 800ff5a: f203 4112 addwgt r1, r3, #1042 @ 0x412
  35416. 800ff5e: fa24 f101 lsrgt.w r1, r4, r1
  35417. 800ff62: bfd6 itet le
  35418. 800ff64: f1c1 0120 rsble r1, r1, #32
  35419. 800ff68: 4331 orrgt r1, r6
  35420. 800ff6a: fa04 f101 lslle.w r1, r4, r1
  35421. 800ff6e: ee07 1a90 vmov s15, r1
  35422. 800ff72: eeb8 7b67 vcvt.f64.u32 d7, s15
  35423. 800ff76: 3b01 subs r3, #1
  35424. 800ff78: ee17 1a90 vmov r1, s15
  35425. 800ff7c: 2501 movs r5, #1
  35426. 800ff7e: f1a1 71f8 sub.w r1, r1, #32505856 @ 0x1f00000
  35427. 800ff82: e7a8 b.n 800fed6 <_dtoa_r+0xf6>
  35428. 800ff84: 2101 movs r1, #1
  35429. 800ff86: 1ad2 subs r2, r2, r3
  35430. 800ff88: 1e53 subs r3, r2, #1
  35431. 800ff8a: 9306 str r3, [sp, #24]
  35432. 800ff8c: bf45 ittet mi
  35433. 800ff8e: f1c2 0301 rsbmi r3, r2, #1
  35434. 800ff92: 9305 strmi r3, [sp, #20]
  35435. 800ff94: 2300 movpl r3, #0
  35436. 800ff96: 2300 movmi r3, #0
  35437. 800ff98: bf4c ite mi
  35438. 800ff9a: 9306 strmi r3, [sp, #24]
  35439. 800ff9c: 9305 strpl r3, [sp, #20]
  35440. 800ff9e: f1b8 0f00 cmp.w r8, #0
  35441. 800ffa2: 910c str r1, [sp, #48] @ 0x30
  35442. 800ffa4: db18 blt.n 800ffd8 <_dtoa_r+0x1f8>
  35443. 800ffa6: 9b06 ldr r3, [sp, #24]
  35444. 800ffa8: f8cd 8028 str.w r8, [sp, #40] @ 0x28
  35445. 800ffac: 4443 add r3, r8
  35446. 800ffae: 9306 str r3, [sp, #24]
  35447. 800ffb0: 2300 movs r3, #0
  35448. 800ffb2: 9a07 ldr r2, [sp, #28]
  35449. 800ffb4: 2a09 cmp r2, #9
  35450. 800ffb6: d849 bhi.n 801004c <_dtoa_r+0x26c>
  35451. 800ffb8: 2a05 cmp r2, #5
  35452. 800ffba: bfc4 itt gt
  35453. 800ffbc: 3a04 subgt r2, #4
  35454. 800ffbe: 9207 strgt r2, [sp, #28]
  35455. 800ffc0: 9a07 ldr r2, [sp, #28]
  35456. 800ffc2: f1a2 0202 sub.w r2, r2, #2
  35457. 800ffc6: bfcc ite gt
  35458. 800ffc8: 2400 movgt r4, #0
  35459. 800ffca: 2401 movle r4, #1
  35460. 800ffcc: 2a03 cmp r2, #3
  35461. 800ffce: d848 bhi.n 8010062 <_dtoa_r+0x282>
  35462. 800ffd0: e8df f002 tbb [pc, r2]
  35463. 800ffd4: 3a2c2e0b .word 0x3a2c2e0b
  35464. 800ffd8: 9b05 ldr r3, [sp, #20]
  35465. 800ffda: 2200 movs r2, #0
  35466. 800ffdc: eba3 0308 sub.w r3, r3, r8
  35467. 800ffe0: 9305 str r3, [sp, #20]
  35468. 800ffe2: 920a str r2, [sp, #40] @ 0x28
  35469. 800ffe4: f1c8 0300 rsb r3, r8, #0
  35470. 800ffe8: e7e3 b.n 800ffb2 <_dtoa_r+0x1d2>
  35471. 800ffea: 2200 movs r2, #0
  35472. 800ffec: 9208 str r2, [sp, #32]
  35473. 800ffee: 9a09 ldr r2, [sp, #36] @ 0x24
  35474. 800fff0: 2a00 cmp r2, #0
  35475. 800fff2: dc39 bgt.n 8010068 <_dtoa_r+0x288>
  35476. 800fff4: f04f 0b01 mov.w fp, #1
  35477. 800fff8: 46da mov sl, fp
  35478. 800fffa: 465a mov r2, fp
  35479. 800fffc: f8cd b024 str.w fp, [sp, #36] @ 0x24
  35480. 8010000: f8d9 701c ldr.w r7, [r9, #28]
  35481. 8010004: 2100 movs r1, #0
  35482. 8010006: 2004 movs r0, #4
  35483. 8010008: f100 0614 add.w r6, r0, #20
  35484. 801000c: 4296 cmp r6, r2
  35485. 801000e: d930 bls.n 8010072 <_dtoa_r+0x292>
  35486. 8010010: 6079 str r1, [r7, #4]
  35487. 8010012: 4648 mov r0, r9
  35488. 8010014: 9304 str r3, [sp, #16]
  35489. 8010016: f000 fd39 bl 8010a8c <_Balloc>
  35490. 801001a: 9b04 ldr r3, [sp, #16]
  35491. 801001c: 4607 mov r7, r0
  35492. 801001e: 2800 cmp r0, #0
  35493. 8010020: d146 bne.n 80100b0 <_dtoa_r+0x2d0>
  35494. 8010022: 4b22 ldr r3, [pc, #136] @ (80100ac <_dtoa_r+0x2cc>)
  35495. 8010024: 4602 mov r2, r0
  35496. 8010026: f240 11af movw r1, #431 @ 0x1af
  35497. 801002a: e6f2 b.n 800fe12 <_dtoa_r+0x32>
  35498. 801002c: 2201 movs r2, #1
  35499. 801002e: e7dd b.n 800ffec <_dtoa_r+0x20c>
  35500. 8010030: 2200 movs r2, #0
  35501. 8010032: 9208 str r2, [sp, #32]
  35502. 8010034: 9a09 ldr r2, [sp, #36] @ 0x24
  35503. 8010036: eb08 0b02 add.w fp, r8, r2
  35504. 801003a: f10b 0a01 add.w sl, fp, #1
  35505. 801003e: 4652 mov r2, sl
  35506. 8010040: 2a01 cmp r2, #1
  35507. 8010042: bfb8 it lt
  35508. 8010044: 2201 movlt r2, #1
  35509. 8010046: e7db b.n 8010000 <_dtoa_r+0x220>
  35510. 8010048: 2201 movs r2, #1
  35511. 801004a: e7f2 b.n 8010032 <_dtoa_r+0x252>
  35512. 801004c: 2401 movs r4, #1
  35513. 801004e: 2200 movs r2, #0
  35514. 8010050: e9cd 2407 strd r2, r4, [sp, #28]
  35515. 8010054: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff
  35516. 8010058: 2100 movs r1, #0
  35517. 801005a: 46da mov sl, fp
  35518. 801005c: 2212 movs r2, #18
  35519. 801005e: 9109 str r1, [sp, #36] @ 0x24
  35520. 8010060: e7ce b.n 8010000 <_dtoa_r+0x220>
  35521. 8010062: 2201 movs r2, #1
  35522. 8010064: 9208 str r2, [sp, #32]
  35523. 8010066: e7f5 b.n 8010054 <_dtoa_r+0x274>
  35524. 8010068: f8dd b024 ldr.w fp, [sp, #36] @ 0x24
  35525. 801006c: 46da mov sl, fp
  35526. 801006e: 465a mov r2, fp
  35527. 8010070: e7c6 b.n 8010000 <_dtoa_r+0x220>
  35528. 8010072: 3101 adds r1, #1
  35529. 8010074: 0040 lsls r0, r0, #1
  35530. 8010076: e7c7 b.n 8010008 <_dtoa_r+0x228>
  35531. 8010078: 636f4361 .word 0x636f4361
  35532. 801007c: 3fd287a7 .word 0x3fd287a7
  35533. 8010080: 8b60c8b3 .word 0x8b60c8b3
  35534. 8010084: 3fc68a28 .word 0x3fc68a28
  35535. 8010088: 509f79fb .word 0x509f79fb
  35536. 801008c: 3fd34413 .word 0x3fd34413
  35537. 8010090: 08011aad .word 0x08011aad
  35538. 8010094: 08011ac4 .word 0x08011ac4
  35539. 8010098: 7ff00000 .word 0x7ff00000
  35540. 801009c: 08011aa9 .word 0x08011aa9
  35541. 80100a0: 08011a7d .word 0x08011a7d
  35542. 80100a4: 08011a7c .word 0x08011a7c
  35543. 80100a8: 08011bc0 .word 0x08011bc0
  35544. 80100ac: 08011b1c .word 0x08011b1c
  35545. 80100b0: f8d9 201c ldr.w r2, [r9, #28]
  35546. 80100b4: f1ba 0f0e cmp.w sl, #14
  35547. 80100b8: 6010 str r0, [r2, #0]
  35548. 80100ba: d86f bhi.n 801019c <_dtoa_r+0x3bc>
  35549. 80100bc: 2c00 cmp r4, #0
  35550. 80100be: d06d beq.n 801019c <_dtoa_r+0x3bc>
  35551. 80100c0: f1b8 0f00 cmp.w r8, #0
  35552. 80100c4: f340 80c2 ble.w 801024c <_dtoa_r+0x46c>
  35553. 80100c8: 4aca ldr r2, [pc, #808] @ (80103f4 <_dtoa_r+0x614>)
  35554. 80100ca: f008 010f and.w r1, r8, #15
  35555. 80100ce: eb02 02c1 add.w r2, r2, r1, lsl #3
  35556. 80100d2: f418 7f80 tst.w r8, #256 @ 0x100
  35557. 80100d6: ed92 7b00 vldr d7, [r2]
  35558. 80100da: ea4f 1128 mov.w r1, r8, asr #4
  35559. 80100de: f000 80a9 beq.w 8010234 <_dtoa_r+0x454>
  35560. 80100e2: 4ac5 ldr r2, [pc, #788] @ (80103f8 <_dtoa_r+0x618>)
  35561. 80100e4: ed92 6b08 vldr d6, [r2, #32]
  35562. 80100e8: ee88 6b06 vdiv.f64 d6, d8, d6
  35563. 80100ec: ed8d 6b02 vstr d6, [sp, #8]
  35564. 80100f0: f001 010f and.w r1, r1, #15
  35565. 80100f4: 2203 movs r2, #3
  35566. 80100f6: 48c0 ldr r0, [pc, #768] @ (80103f8 <_dtoa_r+0x618>)
  35567. 80100f8: 2900 cmp r1, #0
  35568. 80100fa: f040 809d bne.w 8010238 <_dtoa_r+0x458>
  35569. 80100fe: ed9d 6b02 vldr d6, [sp, #8]
  35570. 8010102: ee86 7b07 vdiv.f64 d7, d6, d7
  35571. 8010106: ed8d 7b02 vstr d7, [sp, #8]
  35572. 801010a: 990c ldr r1, [sp, #48] @ 0x30
  35573. 801010c: ed9d 7b02 vldr d7, [sp, #8]
  35574. 8010110: 2900 cmp r1, #0
  35575. 8010112: f000 80c1 beq.w 8010298 <_dtoa_r+0x4b8>
  35576. 8010116: eeb7 6b00 vmov.f64 d6, #112 @ 0x3f800000 1.0
  35577. 801011a: eeb4 7bc6 vcmpe.f64 d7, d6
  35578. 801011e: eef1 fa10 vmrs APSR_nzcv, fpscr
  35579. 8010122: f140 80b9 bpl.w 8010298 <_dtoa_r+0x4b8>
  35580. 8010126: f1ba 0f00 cmp.w sl, #0
  35581. 801012a: f000 80b5 beq.w 8010298 <_dtoa_r+0x4b8>
  35582. 801012e: f1bb 0f00 cmp.w fp, #0
  35583. 8010132: dd31 ble.n 8010198 <_dtoa_r+0x3b8>
  35584. 8010134: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0
  35585. 8010138: ee27 7b06 vmul.f64 d7, d7, d6
  35586. 801013c: ed8d 7b02 vstr d7, [sp, #8]
  35587. 8010140: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff
  35588. 8010144: 9104 str r1, [sp, #16]
  35589. 8010146: 3201 adds r2, #1
  35590. 8010148: 465c mov r4, fp
  35591. 801014a: ed9d 6b02 vldr d6, [sp, #8]
  35592. 801014e: eeb1 5b0c vmov.f64 d5, #28 @ 0x40e00000 7.0
  35593. 8010152: ee07 2a90 vmov s15, r2
  35594. 8010156: eeb8 7be7 vcvt.f64.s32 d7, s15
  35595. 801015a: eea7 5b06 vfma.f64 d5, d7, d6
  35596. 801015e: ee15 2a90 vmov r2, s11
  35597. 8010162: ec51 0b15 vmov r0, r1, d5
  35598. 8010166: f1a2 7150 sub.w r1, r2, #54525952 @ 0x3400000
  35599. 801016a: 2c00 cmp r4, #0
  35600. 801016c: f040 8098 bne.w 80102a0 <_dtoa_r+0x4c0>
  35601. 8010170: eeb1 7b04 vmov.f64 d7, #20 @ 0x40a00000 5.0
  35602. 8010174: ee36 6b47 vsub.f64 d6, d6, d7
  35603. 8010178: ec41 0b17 vmov d7, r0, r1
  35604. 801017c: eeb4 6bc7 vcmpe.f64 d6, d7
  35605. 8010180: eef1 fa10 vmrs APSR_nzcv, fpscr
  35606. 8010184: f300 8261 bgt.w 801064a <_dtoa_r+0x86a>
  35607. 8010188: eeb1 7b47 vneg.f64 d7, d7
  35608. 801018c: eeb4 6bc7 vcmpe.f64 d6, d7
  35609. 8010190: eef1 fa10 vmrs APSR_nzcv, fpscr
  35610. 8010194: f100 80f5 bmi.w 8010382 <_dtoa_r+0x5a2>
  35611. 8010198: ed8d 8b02 vstr d8, [sp, #8]
  35612. 801019c: 9a0f ldr r2, [sp, #60] @ 0x3c
  35613. 801019e: 2a00 cmp r2, #0
  35614. 80101a0: f2c0 812c blt.w 80103fc <_dtoa_r+0x61c>
  35615. 80101a4: f1b8 0f0e cmp.w r8, #14
  35616. 80101a8: f300 8128 bgt.w 80103fc <_dtoa_r+0x61c>
  35617. 80101ac: 4b91 ldr r3, [pc, #580] @ (80103f4 <_dtoa_r+0x614>)
  35618. 80101ae: eb03 03c8 add.w r3, r3, r8, lsl #3
  35619. 80101b2: ed93 6b00 vldr d6, [r3]
  35620. 80101b6: 9b09 ldr r3, [sp, #36] @ 0x24
  35621. 80101b8: 2b00 cmp r3, #0
  35622. 80101ba: da03 bge.n 80101c4 <_dtoa_r+0x3e4>
  35623. 80101bc: f1ba 0f00 cmp.w sl, #0
  35624. 80101c0: f340 80d2 ble.w 8010368 <_dtoa_r+0x588>
  35625. 80101c4: eeb2 4b04 vmov.f64 d4, #36 @ 0x41200000 10.0
  35626. 80101c8: ed9d 7b02 vldr d7, [sp, #8]
  35627. 80101cc: 463e mov r6, r7
  35628. 80101ce: ee87 5b06 vdiv.f64 d5, d7, d6
  35629. 80101d2: eebd 5bc5 vcvt.s32.f64 s10, d5
  35630. 80101d6: ee15 3a10 vmov r3, s10
  35631. 80101da: 3330 adds r3, #48 @ 0x30
  35632. 80101dc: f806 3b01 strb.w r3, [r6], #1
  35633. 80101e0: 1bf3 subs r3, r6, r7
  35634. 80101e2: 459a cmp sl, r3
  35635. 80101e4: eeb8 3bc5 vcvt.f64.s32 d3, s10
  35636. 80101e8: eea3 7b46 vfms.f64 d7, d3, d6
  35637. 80101ec: f040 80f8 bne.w 80103e0 <_dtoa_r+0x600>
  35638. 80101f0: ee37 7b07 vadd.f64 d7, d7, d7
  35639. 80101f4: eeb4 7bc6 vcmpe.f64 d7, d6
  35640. 80101f8: eef1 fa10 vmrs APSR_nzcv, fpscr
  35641. 80101fc: f300 80dd bgt.w 80103ba <_dtoa_r+0x5da>
  35642. 8010200: eeb4 7b46 vcmp.f64 d7, d6
  35643. 8010204: eef1 fa10 vmrs APSR_nzcv, fpscr
  35644. 8010208: d104 bne.n 8010214 <_dtoa_r+0x434>
  35645. 801020a: ee15 3a10 vmov r3, s10
  35646. 801020e: 07db lsls r3, r3, #31
  35647. 8010210: f100 80d3 bmi.w 80103ba <_dtoa_r+0x5da>
  35648. 8010214: 9901 ldr r1, [sp, #4]
  35649. 8010216: 4648 mov r0, r9
  35650. 8010218: f000 fc78 bl 8010b0c <_Bfree>
  35651. 801021c: 2300 movs r3, #0
  35652. 801021e: 9a0d ldr r2, [sp, #52] @ 0x34
  35653. 8010220: 7033 strb r3, [r6, #0]
  35654. 8010222: f108 0301 add.w r3, r8, #1
  35655. 8010226: 6013 str r3, [r2, #0]
  35656. 8010228: 9b1d ldr r3, [sp, #116] @ 0x74
  35657. 801022a: 2b00 cmp r3, #0
  35658. 801022c: f000 8304 beq.w 8010838 <_dtoa_r+0xa58>
  35659. 8010230: 601e str r6, [r3, #0]
  35660. 8010232: e301 b.n 8010838 <_dtoa_r+0xa58>
  35661. 8010234: 2202 movs r2, #2
  35662. 8010236: e75e b.n 80100f6 <_dtoa_r+0x316>
  35663. 8010238: 07cc lsls r4, r1, #31
  35664. 801023a: d504 bpl.n 8010246 <_dtoa_r+0x466>
  35665. 801023c: ed90 6b00 vldr d6, [r0]
  35666. 8010240: 3201 adds r2, #1
  35667. 8010242: ee27 7b06 vmul.f64 d7, d7, d6
  35668. 8010246: 1049 asrs r1, r1, #1
  35669. 8010248: 3008 adds r0, #8
  35670. 801024a: e755 b.n 80100f8 <_dtoa_r+0x318>
  35671. 801024c: d022 beq.n 8010294 <_dtoa_r+0x4b4>
  35672. 801024e: f1c8 0100 rsb r1, r8, #0
  35673. 8010252: 4a68 ldr r2, [pc, #416] @ (80103f4 <_dtoa_r+0x614>)
  35674. 8010254: f001 000f and.w r0, r1, #15
  35675. 8010258: eb02 02c0 add.w r2, r2, r0, lsl #3
  35676. 801025c: ed92 7b00 vldr d7, [r2]
  35677. 8010260: ee28 7b07 vmul.f64 d7, d8, d7
  35678. 8010264: ed8d 7b02 vstr d7, [sp, #8]
  35679. 8010268: 4863 ldr r0, [pc, #396] @ (80103f8 <_dtoa_r+0x618>)
  35680. 801026a: 1109 asrs r1, r1, #4
  35681. 801026c: 2400 movs r4, #0
  35682. 801026e: 2202 movs r2, #2
  35683. 8010270: b929 cbnz r1, 801027e <_dtoa_r+0x49e>
  35684. 8010272: 2c00 cmp r4, #0
  35685. 8010274: f43f af49 beq.w 801010a <_dtoa_r+0x32a>
  35686. 8010278: ed8d 7b02 vstr d7, [sp, #8]
  35687. 801027c: e745 b.n 801010a <_dtoa_r+0x32a>
  35688. 801027e: 07ce lsls r6, r1, #31
  35689. 8010280: d505 bpl.n 801028e <_dtoa_r+0x4ae>
  35690. 8010282: ed90 6b00 vldr d6, [r0]
  35691. 8010286: 3201 adds r2, #1
  35692. 8010288: 2401 movs r4, #1
  35693. 801028a: ee27 7b06 vmul.f64 d7, d7, d6
  35694. 801028e: 1049 asrs r1, r1, #1
  35695. 8010290: 3008 adds r0, #8
  35696. 8010292: e7ed b.n 8010270 <_dtoa_r+0x490>
  35697. 8010294: 2202 movs r2, #2
  35698. 8010296: e738 b.n 801010a <_dtoa_r+0x32a>
  35699. 8010298: f8cd 8010 str.w r8, [sp, #16]
  35700. 801029c: 4654 mov r4, sl
  35701. 801029e: e754 b.n 801014a <_dtoa_r+0x36a>
  35702. 80102a0: 4a54 ldr r2, [pc, #336] @ (80103f4 <_dtoa_r+0x614>)
  35703. 80102a2: eb02 02c4 add.w r2, r2, r4, lsl #3
  35704. 80102a6: ed12 4b02 vldr d4, [r2, #-8]
  35705. 80102aa: 9a08 ldr r2, [sp, #32]
  35706. 80102ac: ec41 0b17 vmov d7, r0, r1
  35707. 80102b0: 443c add r4, r7
  35708. 80102b2: b34a cbz r2, 8010308 <_dtoa_r+0x528>
  35709. 80102b4: eeb6 3b00 vmov.f64 d3, #96 @ 0x3f000000 0.5
  35710. 80102b8: eeb7 2b00 vmov.f64 d2, #112 @ 0x3f800000 1.0
  35711. 80102bc: 463e mov r6, r7
  35712. 80102be: ee83 5b04 vdiv.f64 d5, d3, d4
  35713. 80102c2: eeb2 3b04 vmov.f64 d3, #36 @ 0x41200000 10.0
  35714. 80102c6: ee35 7b47 vsub.f64 d7, d5, d7
  35715. 80102ca: eefd 4bc6 vcvt.s32.f64 s9, d6
  35716. 80102ce: ee14 2a90 vmov r2, s9
  35717. 80102d2: eeb8 5be4 vcvt.f64.s32 d5, s9
  35718. 80102d6: 3230 adds r2, #48 @ 0x30
  35719. 80102d8: ee36 6b45 vsub.f64 d6, d6, d5
  35720. 80102dc: eeb4 6bc7 vcmpe.f64 d6, d7
  35721. 80102e0: eef1 fa10 vmrs APSR_nzcv, fpscr
  35722. 80102e4: f806 2b01 strb.w r2, [r6], #1
  35723. 80102e8: d438 bmi.n 801035c <_dtoa_r+0x57c>
  35724. 80102ea: ee32 5b46 vsub.f64 d5, d2, d6
  35725. 80102ee: eeb4 5bc7 vcmpe.f64 d5, d7
  35726. 80102f2: eef1 fa10 vmrs APSR_nzcv, fpscr
  35727. 80102f6: d462 bmi.n 80103be <_dtoa_r+0x5de>
  35728. 80102f8: 42a6 cmp r6, r4
  35729. 80102fa: f43f af4d beq.w 8010198 <_dtoa_r+0x3b8>
  35730. 80102fe: ee27 7b03 vmul.f64 d7, d7, d3
  35731. 8010302: ee26 6b03 vmul.f64 d6, d6, d3
  35732. 8010306: e7e0 b.n 80102ca <_dtoa_r+0x4ea>
  35733. 8010308: 4621 mov r1, r4
  35734. 801030a: 463e mov r6, r7
  35735. 801030c: ee27 7b04 vmul.f64 d7, d7, d4
  35736. 8010310: eeb2 3b04 vmov.f64 d3, #36 @ 0x41200000 10.0
  35737. 8010314: eefd 4bc6 vcvt.s32.f64 s9, d6
  35738. 8010318: ee14 2a90 vmov r2, s9
  35739. 801031c: 3230 adds r2, #48 @ 0x30
  35740. 801031e: f806 2b01 strb.w r2, [r6], #1
  35741. 8010322: 42a6 cmp r6, r4
  35742. 8010324: eeb8 5be4 vcvt.f64.s32 d5, s9
  35743. 8010328: ee36 6b45 vsub.f64 d6, d6, d5
  35744. 801032c: d119 bne.n 8010362 <_dtoa_r+0x582>
  35745. 801032e: eeb6 5b00 vmov.f64 d5, #96 @ 0x3f000000 0.5
  35746. 8010332: ee37 4b05 vadd.f64 d4, d7, d5
  35747. 8010336: eeb4 6bc4 vcmpe.f64 d6, d4
  35748. 801033a: eef1 fa10 vmrs APSR_nzcv, fpscr
  35749. 801033e: dc3e bgt.n 80103be <_dtoa_r+0x5de>
  35750. 8010340: ee35 5b47 vsub.f64 d5, d5, d7
  35751. 8010344: eeb4 6bc5 vcmpe.f64 d6, d5
  35752. 8010348: eef1 fa10 vmrs APSR_nzcv, fpscr
  35753. 801034c: f57f af24 bpl.w 8010198 <_dtoa_r+0x3b8>
  35754. 8010350: 460e mov r6, r1
  35755. 8010352: 3901 subs r1, #1
  35756. 8010354: f816 3c01 ldrb.w r3, [r6, #-1]
  35757. 8010358: 2b30 cmp r3, #48 @ 0x30
  35758. 801035a: d0f9 beq.n 8010350 <_dtoa_r+0x570>
  35759. 801035c: f8dd 8010 ldr.w r8, [sp, #16]
  35760. 8010360: e758 b.n 8010214 <_dtoa_r+0x434>
  35761. 8010362: ee26 6b03 vmul.f64 d6, d6, d3
  35762. 8010366: e7d5 b.n 8010314 <_dtoa_r+0x534>
  35763. 8010368: d10b bne.n 8010382 <_dtoa_r+0x5a2>
  35764. 801036a: eeb1 7b04 vmov.f64 d7, #20 @ 0x40a00000 5.0
  35765. 801036e: ee26 6b07 vmul.f64 d6, d6, d7
  35766. 8010372: ed9d 7b02 vldr d7, [sp, #8]
  35767. 8010376: eeb4 6bc7 vcmpe.f64 d6, d7
  35768. 801037a: eef1 fa10 vmrs APSR_nzcv, fpscr
  35769. 801037e: f2c0 8161 blt.w 8010644 <_dtoa_r+0x864>
  35770. 8010382: 2400 movs r4, #0
  35771. 8010384: 4625 mov r5, r4
  35772. 8010386: 9b09 ldr r3, [sp, #36] @ 0x24
  35773. 8010388: 43db mvns r3, r3
  35774. 801038a: 9304 str r3, [sp, #16]
  35775. 801038c: 463e mov r6, r7
  35776. 801038e: f04f 0800 mov.w r8, #0
  35777. 8010392: 4621 mov r1, r4
  35778. 8010394: 4648 mov r0, r9
  35779. 8010396: f000 fbb9 bl 8010b0c <_Bfree>
  35780. 801039a: 2d00 cmp r5, #0
  35781. 801039c: d0de beq.n 801035c <_dtoa_r+0x57c>
  35782. 801039e: f1b8 0f00 cmp.w r8, #0
  35783. 80103a2: d005 beq.n 80103b0 <_dtoa_r+0x5d0>
  35784. 80103a4: 45a8 cmp r8, r5
  35785. 80103a6: d003 beq.n 80103b0 <_dtoa_r+0x5d0>
  35786. 80103a8: 4641 mov r1, r8
  35787. 80103aa: 4648 mov r0, r9
  35788. 80103ac: f000 fbae bl 8010b0c <_Bfree>
  35789. 80103b0: 4629 mov r1, r5
  35790. 80103b2: 4648 mov r0, r9
  35791. 80103b4: f000 fbaa bl 8010b0c <_Bfree>
  35792. 80103b8: e7d0 b.n 801035c <_dtoa_r+0x57c>
  35793. 80103ba: f8cd 8010 str.w r8, [sp, #16]
  35794. 80103be: 4633 mov r3, r6
  35795. 80103c0: 461e mov r6, r3
  35796. 80103c2: f813 2d01 ldrb.w r2, [r3, #-1]!
  35797. 80103c6: 2a39 cmp r2, #57 @ 0x39
  35798. 80103c8: d106 bne.n 80103d8 <_dtoa_r+0x5f8>
  35799. 80103ca: 429f cmp r7, r3
  35800. 80103cc: d1f8 bne.n 80103c0 <_dtoa_r+0x5e0>
  35801. 80103ce: 9a04 ldr r2, [sp, #16]
  35802. 80103d0: 3201 adds r2, #1
  35803. 80103d2: 9204 str r2, [sp, #16]
  35804. 80103d4: 2230 movs r2, #48 @ 0x30
  35805. 80103d6: 703a strb r2, [r7, #0]
  35806. 80103d8: 781a ldrb r2, [r3, #0]
  35807. 80103da: 3201 adds r2, #1
  35808. 80103dc: 701a strb r2, [r3, #0]
  35809. 80103de: e7bd b.n 801035c <_dtoa_r+0x57c>
  35810. 80103e0: ee27 7b04 vmul.f64 d7, d7, d4
  35811. 80103e4: eeb5 7b40 vcmp.f64 d7, #0.0
  35812. 80103e8: eef1 fa10 vmrs APSR_nzcv, fpscr
  35813. 80103ec: f47f aeef bne.w 80101ce <_dtoa_r+0x3ee>
  35814. 80103f0: e710 b.n 8010214 <_dtoa_r+0x434>
  35815. 80103f2: bf00 nop
  35816. 80103f4: 08011bc0 .word 0x08011bc0
  35817. 80103f8: 08011b98 .word 0x08011b98
  35818. 80103fc: 9908 ldr r1, [sp, #32]
  35819. 80103fe: 2900 cmp r1, #0
  35820. 8010400: f000 80e3 beq.w 80105ca <_dtoa_r+0x7ea>
  35821. 8010404: 9907 ldr r1, [sp, #28]
  35822. 8010406: 2901 cmp r1, #1
  35823. 8010408: f300 80c8 bgt.w 801059c <_dtoa_r+0x7bc>
  35824. 801040c: 2d00 cmp r5, #0
  35825. 801040e: f000 80c1 beq.w 8010594 <_dtoa_r+0x7b4>
  35826. 8010412: f202 4233 addw r2, r2, #1075 @ 0x433
  35827. 8010416: 9e05 ldr r6, [sp, #20]
  35828. 8010418: 461c mov r4, r3
  35829. 801041a: 9304 str r3, [sp, #16]
  35830. 801041c: 9b05 ldr r3, [sp, #20]
  35831. 801041e: 4413 add r3, r2
  35832. 8010420: 9305 str r3, [sp, #20]
  35833. 8010422: 9b06 ldr r3, [sp, #24]
  35834. 8010424: 2101 movs r1, #1
  35835. 8010426: 4413 add r3, r2
  35836. 8010428: 4648 mov r0, r9
  35837. 801042a: 9306 str r3, [sp, #24]
  35838. 801042c: f000 fc22 bl 8010c74 <__i2b>
  35839. 8010430: 9b04 ldr r3, [sp, #16]
  35840. 8010432: 4605 mov r5, r0
  35841. 8010434: b166 cbz r6, 8010450 <_dtoa_r+0x670>
  35842. 8010436: 9a06 ldr r2, [sp, #24]
  35843. 8010438: 2a00 cmp r2, #0
  35844. 801043a: dd09 ble.n 8010450 <_dtoa_r+0x670>
  35845. 801043c: 42b2 cmp r2, r6
  35846. 801043e: 9905 ldr r1, [sp, #20]
  35847. 8010440: bfa8 it ge
  35848. 8010442: 4632 movge r2, r6
  35849. 8010444: 1a89 subs r1, r1, r2
  35850. 8010446: 9105 str r1, [sp, #20]
  35851. 8010448: 9906 ldr r1, [sp, #24]
  35852. 801044a: 1ab6 subs r6, r6, r2
  35853. 801044c: 1a8a subs r2, r1, r2
  35854. 801044e: 9206 str r2, [sp, #24]
  35855. 8010450: b1fb cbz r3, 8010492 <_dtoa_r+0x6b2>
  35856. 8010452: 9a08 ldr r2, [sp, #32]
  35857. 8010454: 2a00 cmp r2, #0
  35858. 8010456: f000 80bc beq.w 80105d2 <_dtoa_r+0x7f2>
  35859. 801045a: b19c cbz r4, 8010484 <_dtoa_r+0x6a4>
  35860. 801045c: 4629 mov r1, r5
  35861. 801045e: 4622 mov r2, r4
  35862. 8010460: 4648 mov r0, r9
  35863. 8010462: 930b str r3, [sp, #44] @ 0x2c
  35864. 8010464: f000 fcc6 bl 8010df4 <__pow5mult>
  35865. 8010468: 9a01 ldr r2, [sp, #4]
  35866. 801046a: 4601 mov r1, r0
  35867. 801046c: 4605 mov r5, r0
  35868. 801046e: 4648 mov r0, r9
  35869. 8010470: f000 fc16 bl 8010ca0 <__multiply>
  35870. 8010474: 9901 ldr r1, [sp, #4]
  35871. 8010476: 9004 str r0, [sp, #16]
  35872. 8010478: 4648 mov r0, r9
  35873. 801047a: f000 fb47 bl 8010b0c <_Bfree>
  35874. 801047e: 9a04 ldr r2, [sp, #16]
  35875. 8010480: 9b0b ldr r3, [sp, #44] @ 0x2c
  35876. 8010482: 9201 str r2, [sp, #4]
  35877. 8010484: 1b1a subs r2, r3, r4
  35878. 8010486: d004 beq.n 8010492 <_dtoa_r+0x6b2>
  35879. 8010488: 9901 ldr r1, [sp, #4]
  35880. 801048a: 4648 mov r0, r9
  35881. 801048c: f000 fcb2 bl 8010df4 <__pow5mult>
  35882. 8010490: 9001 str r0, [sp, #4]
  35883. 8010492: 2101 movs r1, #1
  35884. 8010494: 4648 mov r0, r9
  35885. 8010496: f000 fbed bl 8010c74 <__i2b>
  35886. 801049a: 9b0a ldr r3, [sp, #40] @ 0x28
  35887. 801049c: 4604 mov r4, r0
  35888. 801049e: 2b00 cmp r3, #0
  35889. 80104a0: f000 81d0 beq.w 8010844 <_dtoa_r+0xa64>
  35890. 80104a4: 461a mov r2, r3
  35891. 80104a6: 4601 mov r1, r0
  35892. 80104a8: 4648 mov r0, r9
  35893. 80104aa: f000 fca3 bl 8010df4 <__pow5mult>
  35894. 80104ae: 9b07 ldr r3, [sp, #28]
  35895. 80104b0: 2b01 cmp r3, #1
  35896. 80104b2: 4604 mov r4, r0
  35897. 80104b4: f300 8095 bgt.w 80105e2 <_dtoa_r+0x802>
  35898. 80104b8: 9b02 ldr r3, [sp, #8]
  35899. 80104ba: 2b00 cmp r3, #0
  35900. 80104bc: f040 808b bne.w 80105d6 <_dtoa_r+0x7f6>
  35901. 80104c0: 9b03 ldr r3, [sp, #12]
  35902. 80104c2: f3c3 0213 ubfx r2, r3, #0, #20
  35903. 80104c6: 2a00 cmp r2, #0
  35904. 80104c8: f040 8087 bne.w 80105da <_dtoa_r+0x7fa>
  35905. 80104cc: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
  35906. 80104d0: 0d12 lsrs r2, r2, #20
  35907. 80104d2: 0512 lsls r2, r2, #20
  35908. 80104d4: 2a00 cmp r2, #0
  35909. 80104d6: f000 8082 beq.w 80105de <_dtoa_r+0x7fe>
  35910. 80104da: 9b05 ldr r3, [sp, #20]
  35911. 80104dc: 3301 adds r3, #1
  35912. 80104de: 9305 str r3, [sp, #20]
  35913. 80104e0: 9b06 ldr r3, [sp, #24]
  35914. 80104e2: 3301 adds r3, #1
  35915. 80104e4: 9306 str r3, [sp, #24]
  35916. 80104e6: 2301 movs r3, #1
  35917. 80104e8: 930b str r3, [sp, #44] @ 0x2c
  35918. 80104ea: 9b0a ldr r3, [sp, #40] @ 0x28
  35919. 80104ec: 2b00 cmp r3, #0
  35920. 80104ee: f000 81af beq.w 8010850 <_dtoa_r+0xa70>
  35921. 80104f2: 6922 ldr r2, [r4, #16]
  35922. 80104f4: eb04 0282 add.w r2, r4, r2, lsl #2
  35923. 80104f8: 6910 ldr r0, [r2, #16]
  35924. 80104fa: f000 fb6f bl 8010bdc <__hi0bits>
  35925. 80104fe: f1c0 0020 rsb r0, r0, #32
  35926. 8010502: 9b06 ldr r3, [sp, #24]
  35927. 8010504: 4418 add r0, r3
  35928. 8010506: f010 001f ands.w r0, r0, #31
  35929. 801050a: d076 beq.n 80105fa <_dtoa_r+0x81a>
  35930. 801050c: f1c0 0220 rsb r2, r0, #32
  35931. 8010510: 2a04 cmp r2, #4
  35932. 8010512: dd69 ble.n 80105e8 <_dtoa_r+0x808>
  35933. 8010514: 9b05 ldr r3, [sp, #20]
  35934. 8010516: f1c0 001c rsb r0, r0, #28
  35935. 801051a: 4403 add r3, r0
  35936. 801051c: 9305 str r3, [sp, #20]
  35937. 801051e: 9b06 ldr r3, [sp, #24]
  35938. 8010520: 4406 add r6, r0
  35939. 8010522: 4403 add r3, r0
  35940. 8010524: 9306 str r3, [sp, #24]
  35941. 8010526: 9b05 ldr r3, [sp, #20]
  35942. 8010528: 2b00 cmp r3, #0
  35943. 801052a: dd05 ble.n 8010538 <_dtoa_r+0x758>
  35944. 801052c: 9901 ldr r1, [sp, #4]
  35945. 801052e: 461a mov r2, r3
  35946. 8010530: 4648 mov r0, r9
  35947. 8010532: f000 fcb9 bl 8010ea8 <__lshift>
  35948. 8010536: 9001 str r0, [sp, #4]
  35949. 8010538: 9b06 ldr r3, [sp, #24]
  35950. 801053a: 2b00 cmp r3, #0
  35951. 801053c: dd05 ble.n 801054a <_dtoa_r+0x76a>
  35952. 801053e: 4621 mov r1, r4
  35953. 8010540: 461a mov r2, r3
  35954. 8010542: 4648 mov r0, r9
  35955. 8010544: f000 fcb0 bl 8010ea8 <__lshift>
  35956. 8010548: 4604 mov r4, r0
  35957. 801054a: 9b0c ldr r3, [sp, #48] @ 0x30
  35958. 801054c: 2b00 cmp r3, #0
  35959. 801054e: d056 beq.n 80105fe <_dtoa_r+0x81e>
  35960. 8010550: 9801 ldr r0, [sp, #4]
  35961. 8010552: 4621 mov r1, r4
  35962. 8010554: f000 fd14 bl 8010f80 <__mcmp>
  35963. 8010558: 2800 cmp r0, #0
  35964. 801055a: da50 bge.n 80105fe <_dtoa_r+0x81e>
  35965. 801055c: f108 33ff add.w r3, r8, #4294967295 @ 0xffffffff
  35966. 8010560: 9304 str r3, [sp, #16]
  35967. 8010562: 9901 ldr r1, [sp, #4]
  35968. 8010564: 2300 movs r3, #0
  35969. 8010566: 220a movs r2, #10
  35970. 8010568: 4648 mov r0, r9
  35971. 801056a: f000 faf1 bl 8010b50 <__multadd>
  35972. 801056e: 9b08 ldr r3, [sp, #32]
  35973. 8010570: 9001 str r0, [sp, #4]
  35974. 8010572: 2b00 cmp r3, #0
  35975. 8010574: f000 816e beq.w 8010854 <_dtoa_r+0xa74>
  35976. 8010578: 4629 mov r1, r5
  35977. 801057a: 2300 movs r3, #0
  35978. 801057c: 220a movs r2, #10
  35979. 801057e: 4648 mov r0, r9
  35980. 8010580: f000 fae6 bl 8010b50 <__multadd>
  35981. 8010584: f1bb 0f00 cmp.w fp, #0
  35982. 8010588: 4605 mov r5, r0
  35983. 801058a: dc64 bgt.n 8010656 <_dtoa_r+0x876>
  35984. 801058c: 9b07 ldr r3, [sp, #28]
  35985. 801058e: 2b02 cmp r3, #2
  35986. 8010590: dc3e bgt.n 8010610 <_dtoa_r+0x830>
  35987. 8010592: e060 b.n 8010656 <_dtoa_r+0x876>
  35988. 8010594: 9a0e ldr r2, [sp, #56] @ 0x38
  35989. 8010596: f1c2 0236 rsb r2, r2, #54 @ 0x36
  35990. 801059a: e73c b.n 8010416 <_dtoa_r+0x636>
  35991. 801059c: f10a 34ff add.w r4, sl, #4294967295 @ 0xffffffff
  35992. 80105a0: 42a3 cmp r3, r4
  35993. 80105a2: bfbf itttt lt
  35994. 80105a4: 1ae2 sublt r2, r4, r3
  35995. 80105a6: 9b0a ldrlt r3, [sp, #40] @ 0x28
  35996. 80105a8: 189b addlt r3, r3, r2
  35997. 80105aa: 930a strlt r3, [sp, #40] @ 0x28
  35998. 80105ac: bfae itee ge
  35999. 80105ae: 1b1c subge r4, r3, r4
  36000. 80105b0: 4623 movlt r3, r4
  36001. 80105b2: 2400 movlt r4, #0
  36002. 80105b4: f1ba 0f00 cmp.w sl, #0
  36003. 80105b8: bfb5 itete lt
  36004. 80105ba: 9a05 ldrlt r2, [sp, #20]
  36005. 80105bc: 9e05 ldrge r6, [sp, #20]
  36006. 80105be: eba2 060a sublt.w r6, r2, sl
  36007. 80105c2: 4652 movge r2, sl
  36008. 80105c4: bfb8 it lt
  36009. 80105c6: 2200 movlt r2, #0
  36010. 80105c8: e727 b.n 801041a <_dtoa_r+0x63a>
  36011. 80105ca: 9e05 ldr r6, [sp, #20]
  36012. 80105cc: 9d08 ldr r5, [sp, #32]
  36013. 80105ce: 461c mov r4, r3
  36014. 80105d0: e730 b.n 8010434 <_dtoa_r+0x654>
  36015. 80105d2: 461a mov r2, r3
  36016. 80105d4: e758 b.n 8010488 <_dtoa_r+0x6a8>
  36017. 80105d6: 2300 movs r3, #0
  36018. 80105d8: e786 b.n 80104e8 <_dtoa_r+0x708>
  36019. 80105da: 9b02 ldr r3, [sp, #8]
  36020. 80105dc: e784 b.n 80104e8 <_dtoa_r+0x708>
  36021. 80105de: 920b str r2, [sp, #44] @ 0x2c
  36022. 80105e0: e783 b.n 80104ea <_dtoa_r+0x70a>
  36023. 80105e2: 2300 movs r3, #0
  36024. 80105e4: 930b str r3, [sp, #44] @ 0x2c
  36025. 80105e6: e784 b.n 80104f2 <_dtoa_r+0x712>
  36026. 80105e8: d09d beq.n 8010526 <_dtoa_r+0x746>
  36027. 80105ea: 9b05 ldr r3, [sp, #20]
  36028. 80105ec: 321c adds r2, #28
  36029. 80105ee: 4413 add r3, r2
  36030. 80105f0: 9305 str r3, [sp, #20]
  36031. 80105f2: 9b06 ldr r3, [sp, #24]
  36032. 80105f4: 4416 add r6, r2
  36033. 80105f6: 4413 add r3, r2
  36034. 80105f8: e794 b.n 8010524 <_dtoa_r+0x744>
  36035. 80105fa: 4602 mov r2, r0
  36036. 80105fc: e7f5 b.n 80105ea <_dtoa_r+0x80a>
  36037. 80105fe: f1ba 0f00 cmp.w sl, #0
  36038. 8010602: f8cd 8010 str.w r8, [sp, #16]
  36039. 8010606: 46d3 mov fp, sl
  36040. 8010608: dc21 bgt.n 801064e <_dtoa_r+0x86e>
  36041. 801060a: 9b07 ldr r3, [sp, #28]
  36042. 801060c: 2b02 cmp r3, #2
  36043. 801060e: dd1e ble.n 801064e <_dtoa_r+0x86e>
  36044. 8010610: f1bb 0f00 cmp.w fp, #0
  36045. 8010614: f47f aeb7 bne.w 8010386 <_dtoa_r+0x5a6>
  36046. 8010618: 4621 mov r1, r4
  36047. 801061a: 465b mov r3, fp
  36048. 801061c: 2205 movs r2, #5
  36049. 801061e: 4648 mov r0, r9
  36050. 8010620: f000 fa96 bl 8010b50 <__multadd>
  36051. 8010624: 4601 mov r1, r0
  36052. 8010626: 4604 mov r4, r0
  36053. 8010628: 9801 ldr r0, [sp, #4]
  36054. 801062a: f000 fca9 bl 8010f80 <__mcmp>
  36055. 801062e: 2800 cmp r0, #0
  36056. 8010630: f77f aea9 ble.w 8010386 <_dtoa_r+0x5a6>
  36057. 8010634: 463e mov r6, r7
  36058. 8010636: 2331 movs r3, #49 @ 0x31
  36059. 8010638: f806 3b01 strb.w r3, [r6], #1
  36060. 801063c: 9b04 ldr r3, [sp, #16]
  36061. 801063e: 3301 adds r3, #1
  36062. 8010640: 9304 str r3, [sp, #16]
  36063. 8010642: e6a4 b.n 801038e <_dtoa_r+0x5ae>
  36064. 8010644: f8cd 8010 str.w r8, [sp, #16]
  36065. 8010648: 4654 mov r4, sl
  36066. 801064a: 4625 mov r5, r4
  36067. 801064c: e7f2 b.n 8010634 <_dtoa_r+0x854>
  36068. 801064e: 9b08 ldr r3, [sp, #32]
  36069. 8010650: 2b00 cmp r3, #0
  36070. 8010652: f000 8103 beq.w 801085c <_dtoa_r+0xa7c>
  36071. 8010656: 2e00 cmp r6, #0
  36072. 8010658: dd05 ble.n 8010666 <_dtoa_r+0x886>
  36073. 801065a: 4629 mov r1, r5
  36074. 801065c: 4632 mov r2, r6
  36075. 801065e: 4648 mov r0, r9
  36076. 8010660: f000 fc22 bl 8010ea8 <__lshift>
  36077. 8010664: 4605 mov r5, r0
  36078. 8010666: 9b0b ldr r3, [sp, #44] @ 0x2c
  36079. 8010668: 2b00 cmp r3, #0
  36080. 801066a: d058 beq.n 801071e <_dtoa_r+0x93e>
  36081. 801066c: 6869 ldr r1, [r5, #4]
  36082. 801066e: 4648 mov r0, r9
  36083. 8010670: f000 fa0c bl 8010a8c <_Balloc>
  36084. 8010674: 4606 mov r6, r0
  36085. 8010676: b928 cbnz r0, 8010684 <_dtoa_r+0x8a4>
  36086. 8010678: 4b82 ldr r3, [pc, #520] @ (8010884 <_dtoa_r+0xaa4>)
  36087. 801067a: 4602 mov r2, r0
  36088. 801067c: f240 21ef movw r1, #751 @ 0x2ef
  36089. 8010680: f7ff bbc7 b.w 800fe12 <_dtoa_r+0x32>
  36090. 8010684: 692a ldr r2, [r5, #16]
  36091. 8010686: 3202 adds r2, #2
  36092. 8010688: 0092 lsls r2, r2, #2
  36093. 801068a: f105 010c add.w r1, r5, #12
  36094. 801068e: 300c adds r0, #12
  36095. 8010690: f7ff fb0f bl 800fcb2 <memcpy>
  36096. 8010694: 2201 movs r2, #1
  36097. 8010696: 4631 mov r1, r6
  36098. 8010698: 4648 mov r0, r9
  36099. 801069a: f000 fc05 bl 8010ea8 <__lshift>
  36100. 801069e: 1c7b adds r3, r7, #1
  36101. 80106a0: 9305 str r3, [sp, #20]
  36102. 80106a2: eb07 030b add.w r3, r7, fp
  36103. 80106a6: 9309 str r3, [sp, #36] @ 0x24
  36104. 80106a8: 9b02 ldr r3, [sp, #8]
  36105. 80106aa: f003 0301 and.w r3, r3, #1
  36106. 80106ae: 46a8 mov r8, r5
  36107. 80106b0: 9308 str r3, [sp, #32]
  36108. 80106b2: 4605 mov r5, r0
  36109. 80106b4: 9b05 ldr r3, [sp, #20]
  36110. 80106b6: 9801 ldr r0, [sp, #4]
  36111. 80106b8: 4621 mov r1, r4
  36112. 80106ba: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff
  36113. 80106be: f7ff fb06 bl 800fcce <quorem>
  36114. 80106c2: 4641 mov r1, r8
  36115. 80106c4: 9002 str r0, [sp, #8]
  36116. 80106c6: f100 0a30 add.w sl, r0, #48 @ 0x30
  36117. 80106ca: 9801 ldr r0, [sp, #4]
  36118. 80106cc: f000 fc58 bl 8010f80 <__mcmp>
  36119. 80106d0: 462a mov r2, r5
  36120. 80106d2: 9006 str r0, [sp, #24]
  36121. 80106d4: 4621 mov r1, r4
  36122. 80106d6: 4648 mov r0, r9
  36123. 80106d8: f000 fc6e bl 8010fb8 <__mdiff>
  36124. 80106dc: 68c2 ldr r2, [r0, #12]
  36125. 80106de: 4606 mov r6, r0
  36126. 80106e0: b9fa cbnz r2, 8010722 <_dtoa_r+0x942>
  36127. 80106e2: 4601 mov r1, r0
  36128. 80106e4: 9801 ldr r0, [sp, #4]
  36129. 80106e6: f000 fc4b bl 8010f80 <__mcmp>
  36130. 80106ea: 4602 mov r2, r0
  36131. 80106ec: 4631 mov r1, r6
  36132. 80106ee: 4648 mov r0, r9
  36133. 80106f0: 920a str r2, [sp, #40] @ 0x28
  36134. 80106f2: f000 fa0b bl 8010b0c <_Bfree>
  36135. 80106f6: 9b07 ldr r3, [sp, #28]
  36136. 80106f8: 9a0a ldr r2, [sp, #40] @ 0x28
  36137. 80106fa: 9e05 ldr r6, [sp, #20]
  36138. 80106fc: ea43 0102 orr.w r1, r3, r2
  36139. 8010700: 9b08 ldr r3, [sp, #32]
  36140. 8010702: 4319 orrs r1, r3
  36141. 8010704: d10f bne.n 8010726 <_dtoa_r+0x946>
  36142. 8010706: f1ba 0f39 cmp.w sl, #57 @ 0x39
  36143. 801070a: d028 beq.n 801075e <_dtoa_r+0x97e>
  36144. 801070c: 9b06 ldr r3, [sp, #24]
  36145. 801070e: 2b00 cmp r3, #0
  36146. 8010710: dd02 ble.n 8010718 <_dtoa_r+0x938>
  36147. 8010712: 9b02 ldr r3, [sp, #8]
  36148. 8010714: f103 0a31 add.w sl, r3, #49 @ 0x31
  36149. 8010718: f88b a000 strb.w sl, [fp]
  36150. 801071c: e639 b.n 8010392 <_dtoa_r+0x5b2>
  36151. 801071e: 4628 mov r0, r5
  36152. 8010720: e7bd b.n 801069e <_dtoa_r+0x8be>
  36153. 8010722: 2201 movs r2, #1
  36154. 8010724: e7e2 b.n 80106ec <_dtoa_r+0x90c>
  36155. 8010726: 9b06 ldr r3, [sp, #24]
  36156. 8010728: 2b00 cmp r3, #0
  36157. 801072a: db04 blt.n 8010736 <_dtoa_r+0x956>
  36158. 801072c: 9907 ldr r1, [sp, #28]
  36159. 801072e: 430b orrs r3, r1
  36160. 8010730: 9908 ldr r1, [sp, #32]
  36161. 8010732: 430b orrs r3, r1
  36162. 8010734: d120 bne.n 8010778 <_dtoa_r+0x998>
  36163. 8010736: 2a00 cmp r2, #0
  36164. 8010738: ddee ble.n 8010718 <_dtoa_r+0x938>
  36165. 801073a: 9901 ldr r1, [sp, #4]
  36166. 801073c: 2201 movs r2, #1
  36167. 801073e: 4648 mov r0, r9
  36168. 8010740: f000 fbb2 bl 8010ea8 <__lshift>
  36169. 8010744: 4621 mov r1, r4
  36170. 8010746: 9001 str r0, [sp, #4]
  36171. 8010748: f000 fc1a bl 8010f80 <__mcmp>
  36172. 801074c: 2800 cmp r0, #0
  36173. 801074e: dc03 bgt.n 8010758 <_dtoa_r+0x978>
  36174. 8010750: d1e2 bne.n 8010718 <_dtoa_r+0x938>
  36175. 8010752: f01a 0f01 tst.w sl, #1
  36176. 8010756: d0df beq.n 8010718 <_dtoa_r+0x938>
  36177. 8010758: f1ba 0f39 cmp.w sl, #57 @ 0x39
  36178. 801075c: d1d9 bne.n 8010712 <_dtoa_r+0x932>
  36179. 801075e: 2339 movs r3, #57 @ 0x39
  36180. 8010760: f88b 3000 strb.w r3, [fp]
  36181. 8010764: 4633 mov r3, r6
  36182. 8010766: 461e mov r6, r3
  36183. 8010768: 3b01 subs r3, #1
  36184. 801076a: f816 2c01 ldrb.w r2, [r6, #-1]
  36185. 801076e: 2a39 cmp r2, #57 @ 0x39
  36186. 8010770: d053 beq.n 801081a <_dtoa_r+0xa3a>
  36187. 8010772: 3201 adds r2, #1
  36188. 8010774: 701a strb r2, [r3, #0]
  36189. 8010776: e60c b.n 8010392 <_dtoa_r+0x5b2>
  36190. 8010778: 2a00 cmp r2, #0
  36191. 801077a: dd07 ble.n 801078c <_dtoa_r+0x9ac>
  36192. 801077c: f1ba 0f39 cmp.w sl, #57 @ 0x39
  36193. 8010780: d0ed beq.n 801075e <_dtoa_r+0x97e>
  36194. 8010782: f10a 0301 add.w r3, sl, #1
  36195. 8010786: f88b 3000 strb.w r3, [fp]
  36196. 801078a: e602 b.n 8010392 <_dtoa_r+0x5b2>
  36197. 801078c: 9b05 ldr r3, [sp, #20]
  36198. 801078e: 9a05 ldr r2, [sp, #20]
  36199. 8010790: f803 ac01 strb.w sl, [r3, #-1]
  36200. 8010794: 9b09 ldr r3, [sp, #36] @ 0x24
  36201. 8010796: 4293 cmp r3, r2
  36202. 8010798: d029 beq.n 80107ee <_dtoa_r+0xa0e>
  36203. 801079a: 9901 ldr r1, [sp, #4]
  36204. 801079c: 2300 movs r3, #0
  36205. 801079e: 220a movs r2, #10
  36206. 80107a0: 4648 mov r0, r9
  36207. 80107a2: f000 f9d5 bl 8010b50 <__multadd>
  36208. 80107a6: 45a8 cmp r8, r5
  36209. 80107a8: 9001 str r0, [sp, #4]
  36210. 80107aa: f04f 0300 mov.w r3, #0
  36211. 80107ae: f04f 020a mov.w r2, #10
  36212. 80107b2: 4641 mov r1, r8
  36213. 80107b4: 4648 mov r0, r9
  36214. 80107b6: d107 bne.n 80107c8 <_dtoa_r+0x9e8>
  36215. 80107b8: f000 f9ca bl 8010b50 <__multadd>
  36216. 80107bc: 4680 mov r8, r0
  36217. 80107be: 4605 mov r5, r0
  36218. 80107c0: 9b05 ldr r3, [sp, #20]
  36219. 80107c2: 3301 adds r3, #1
  36220. 80107c4: 9305 str r3, [sp, #20]
  36221. 80107c6: e775 b.n 80106b4 <_dtoa_r+0x8d4>
  36222. 80107c8: f000 f9c2 bl 8010b50 <__multadd>
  36223. 80107cc: 4629 mov r1, r5
  36224. 80107ce: 4680 mov r8, r0
  36225. 80107d0: 2300 movs r3, #0
  36226. 80107d2: 220a movs r2, #10
  36227. 80107d4: 4648 mov r0, r9
  36228. 80107d6: f000 f9bb bl 8010b50 <__multadd>
  36229. 80107da: 4605 mov r5, r0
  36230. 80107dc: e7f0 b.n 80107c0 <_dtoa_r+0x9e0>
  36231. 80107de: f1bb 0f00 cmp.w fp, #0
  36232. 80107e2: bfcc ite gt
  36233. 80107e4: 465e movgt r6, fp
  36234. 80107e6: 2601 movle r6, #1
  36235. 80107e8: 443e add r6, r7
  36236. 80107ea: f04f 0800 mov.w r8, #0
  36237. 80107ee: 9901 ldr r1, [sp, #4]
  36238. 80107f0: 2201 movs r2, #1
  36239. 80107f2: 4648 mov r0, r9
  36240. 80107f4: f000 fb58 bl 8010ea8 <__lshift>
  36241. 80107f8: 4621 mov r1, r4
  36242. 80107fa: 9001 str r0, [sp, #4]
  36243. 80107fc: f000 fbc0 bl 8010f80 <__mcmp>
  36244. 8010800: 2800 cmp r0, #0
  36245. 8010802: dcaf bgt.n 8010764 <_dtoa_r+0x984>
  36246. 8010804: d102 bne.n 801080c <_dtoa_r+0xa2c>
  36247. 8010806: f01a 0f01 tst.w sl, #1
  36248. 801080a: d1ab bne.n 8010764 <_dtoa_r+0x984>
  36249. 801080c: 4633 mov r3, r6
  36250. 801080e: 461e mov r6, r3
  36251. 8010810: f813 2d01 ldrb.w r2, [r3, #-1]!
  36252. 8010814: 2a30 cmp r2, #48 @ 0x30
  36253. 8010816: d0fa beq.n 801080e <_dtoa_r+0xa2e>
  36254. 8010818: e5bb b.n 8010392 <_dtoa_r+0x5b2>
  36255. 801081a: 429f cmp r7, r3
  36256. 801081c: d1a3 bne.n 8010766 <_dtoa_r+0x986>
  36257. 801081e: 9b04 ldr r3, [sp, #16]
  36258. 8010820: 3301 adds r3, #1
  36259. 8010822: 9304 str r3, [sp, #16]
  36260. 8010824: 2331 movs r3, #49 @ 0x31
  36261. 8010826: 703b strb r3, [r7, #0]
  36262. 8010828: e5b3 b.n 8010392 <_dtoa_r+0x5b2>
  36263. 801082a: 9b1d ldr r3, [sp, #116] @ 0x74
  36264. 801082c: 4f16 ldr r7, [pc, #88] @ (8010888 <_dtoa_r+0xaa8>)
  36265. 801082e: b11b cbz r3, 8010838 <_dtoa_r+0xa58>
  36266. 8010830: f107 0308 add.w r3, r7, #8
  36267. 8010834: 9a1d ldr r2, [sp, #116] @ 0x74
  36268. 8010836: 6013 str r3, [r2, #0]
  36269. 8010838: 4638 mov r0, r7
  36270. 801083a: b011 add sp, #68 @ 0x44
  36271. 801083c: ecbd 8b02 vpop {d8}
  36272. 8010840: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  36273. 8010844: 9b07 ldr r3, [sp, #28]
  36274. 8010846: 2b01 cmp r3, #1
  36275. 8010848: f77f ae36 ble.w 80104b8 <_dtoa_r+0x6d8>
  36276. 801084c: 9b0a ldr r3, [sp, #40] @ 0x28
  36277. 801084e: 930b str r3, [sp, #44] @ 0x2c
  36278. 8010850: 2001 movs r0, #1
  36279. 8010852: e656 b.n 8010502 <_dtoa_r+0x722>
  36280. 8010854: f1bb 0f00 cmp.w fp, #0
  36281. 8010858: f77f aed7 ble.w 801060a <_dtoa_r+0x82a>
  36282. 801085c: 463e mov r6, r7
  36283. 801085e: 9801 ldr r0, [sp, #4]
  36284. 8010860: 4621 mov r1, r4
  36285. 8010862: f7ff fa34 bl 800fcce <quorem>
  36286. 8010866: f100 0a30 add.w sl, r0, #48 @ 0x30
  36287. 801086a: f806 ab01 strb.w sl, [r6], #1
  36288. 801086e: 1bf2 subs r2, r6, r7
  36289. 8010870: 4593 cmp fp, r2
  36290. 8010872: ddb4 ble.n 80107de <_dtoa_r+0x9fe>
  36291. 8010874: 9901 ldr r1, [sp, #4]
  36292. 8010876: 2300 movs r3, #0
  36293. 8010878: 220a movs r2, #10
  36294. 801087a: 4648 mov r0, r9
  36295. 801087c: f000 f968 bl 8010b50 <__multadd>
  36296. 8010880: 9001 str r0, [sp, #4]
  36297. 8010882: e7ec b.n 801085e <_dtoa_r+0xa7e>
  36298. 8010884: 08011b1c .word 0x08011b1c
  36299. 8010888: 08011aa0 .word 0x08011aa0
  36300. 0801088c <_free_r>:
  36301. 801088c: b538 push {r3, r4, r5, lr}
  36302. 801088e: 4605 mov r5, r0
  36303. 8010890: 2900 cmp r1, #0
  36304. 8010892: d041 beq.n 8010918 <_free_r+0x8c>
  36305. 8010894: f851 3c04 ldr.w r3, [r1, #-4]
  36306. 8010898: 1f0c subs r4, r1, #4
  36307. 801089a: 2b00 cmp r3, #0
  36308. 801089c: bfb8 it lt
  36309. 801089e: 18e4 addlt r4, r4, r3
  36310. 80108a0: f000 f8e8 bl 8010a74 <__malloc_lock>
  36311. 80108a4: 4a1d ldr r2, [pc, #116] @ (801091c <_free_r+0x90>)
  36312. 80108a6: 6813 ldr r3, [r2, #0]
  36313. 80108a8: b933 cbnz r3, 80108b8 <_free_r+0x2c>
  36314. 80108aa: 6063 str r3, [r4, #4]
  36315. 80108ac: 6014 str r4, [r2, #0]
  36316. 80108ae: 4628 mov r0, r5
  36317. 80108b0: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
  36318. 80108b4: f000 b8e4 b.w 8010a80 <__malloc_unlock>
  36319. 80108b8: 42a3 cmp r3, r4
  36320. 80108ba: d908 bls.n 80108ce <_free_r+0x42>
  36321. 80108bc: 6820 ldr r0, [r4, #0]
  36322. 80108be: 1821 adds r1, r4, r0
  36323. 80108c0: 428b cmp r3, r1
  36324. 80108c2: bf01 itttt eq
  36325. 80108c4: 6819 ldreq r1, [r3, #0]
  36326. 80108c6: 685b ldreq r3, [r3, #4]
  36327. 80108c8: 1809 addeq r1, r1, r0
  36328. 80108ca: 6021 streq r1, [r4, #0]
  36329. 80108cc: e7ed b.n 80108aa <_free_r+0x1e>
  36330. 80108ce: 461a mov r2, r3
  36331. 80108d0: 685b ldr r3, [r3, #4]
  36332. 80108d2: b10b cbz r3, 80108d8 <_free_r+0x4c>
  36333. 80108d4: 42a3 cmp r3, r4
  36334. 80108d6: d9fa bls.n 80108ce <_free_r+0x42>
  36335. 80108d8: 6811 ldr r1, [r2, #0]
  36336. 80108da: 1850 adds r0, r2, r1
  36337. 80108dc: 42a0 cmp r0, r4
  36338. 80108de: d10b bne.n 80108f8 <_free_r+0x6c>
  36339. 80108e0: 6820 ldr r0, [r4, #0]
  36340. 80108e2: 4401 add r1, r0
  36341. 80108e4: 1850 adds r0, r2, r1
  36342. 80108e6: 4283 cmp r3, r0
  36343. 80108e8: 6011 str r1, [r2, #0]
  36344. 80108ea: d1e0 bne.n 80108ae <_free_r+0x22>
  36345. 80108ec: 6818 ldr r0, [r3, #0]
  36346. 80108ee: 685b ldr r3, [r3, #4]
  36347. 80108f0: 6053 str r3, [r2, #4]
  36348. 80108f2: 4408 add r0, r1
  36349. 80108f4: 6010 str r0, [r2, #0]
  36350. 80108f6: e7da b.n 80108ae <_free_r+0x22>
  36351. 80108f8: d902 bls.n 8010900 <_free_r+0x74>
  36352. 80108fa: 230c movs r3, #12
  36353. 80108fc: 602b str r3, [r5, #0]
  36354. 80108fe: e7d6 b.n 80108ae <_free_r+0x22>
  36355. 8010900: 6820 ldr r0, [r4, #0]
  36356. 8010902: 1821 adds r1, r4, r0
  36357. 8010904: 428b cmp r3, r1
  36358. 8010906: bf04 itt eq
  36359. 8010908: 6819 ldreq r1, [r3, #0]
  36360. 801090a: 685b ldreq r3, [r3, #4]
  36361. 801090c: 6063 str r3, [r4, #4]
  36362. 801090e: bf04 itt eq
  36363. 8010910: 1809 addeq r1, r1, r0
  36364. 8010912: 6021 streq r1, [r4, #0]
  36365. 8010914: 6054 str r4, [r2, #4]
  36366. 8010916: e7ca b.n 80108ae <_free_r+0x22>
  36367. 8010918: bd38 pop {r3, r4, r5, pc}
  36368. 801091a: bf00 nop
  36369. 801091c: 240132e0 .word 0x240132e0
  36370. 08010920 <malloc>:
  36371. 8010920: 4b02 ldr r3, [pc, #8] @ (801092c <malloc+0xc>)
  36372. 8010922: 4601 mov r1, r0
  36373. 8010924: 6818 ldr r0, [r3, #0]
  36374. 8010926: f000 b825 b.w 8010974 <_malloc_r>
  36375. 801092a: bf00 nop
  36376. 801092c: 24000054 .word 0x24000054
  36377. 08010930 <sbrk_aligned>:
  36378. 8010930: b570 push {r4, r5, r6, lr}
  36379. 8010932: 4e0f ldr r6, [pc, #60] @ (8010970 <sbrk_aligned+0x40>)
  36380. 8010934: 460c mov r4, r1
  36381. 8010936: 6831 ldr r1, [r6, #0]
  36382. 8010938: 4605 mov r5, r0
  36383. 801093a: b911 cbnz r1, 8010942 <sbrk_aligned+0x12>
  36384. 801093c: f000 fd58 bl 80113f0 <_sbrk_r>
  36385. 8010940: 6030 str r0, [r6, #0]
  36386. 8010942: 4621 mov r1, r4
  36387. 8010944: 4628 mov r0, r5
  36388. 8010946: f000 fd53 bl 80113f0 <_sbrk_r>
  36389. 801094a: 1c43 adds r3, r0, #1
  36390. 801094c: d103 bne.n 8010956 <sbrk_aligned+0x26>
  36391. 801094e: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff
  36392. 8010952: 4620 mov r0, r4
  36393. 8010954: bd70 pop {r4, r5, r6, pc}
  36394. 8010956: 1cc4 adds r4, r0, #3
  36395. 8010958: f024 0403 bic.w r4, r4, #3
  36396. 801095c: 42a0 cmp r0, r4
  36397. 801095e: d0f8 beq.n 8010952 <sbrk_aligned+0x22>
  36398. 8010960: 1a21 subs r1, r4, r0
  36399. 8010962: 4628 mov r0, r5
  36400. 8010964: f000 fd44 bl 80113f0 <_sbrk_r>
  36401. 8010968: 3001 adds r0, #1
  36402. 801096a: d1f2 bne.n 8010952 <sbrk_aligned+0x22>
  36403. 801096c: e7ef b.n 801094e <sbrk_aligned+0x1e>
  36404. 801096e: bf00 nop
  36405. 8010970: 240132dc .word 0x240132dc
  36406. 08010974 <_malloc_r>:
  36407. 8010974: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  36408. 8010978: 1ccd adds r5, r1, #3
  36409. 801097a: f025 0503 bic.w r5, r5, #3
  36410. 801097e: 3508 adds r5, #8
  36411. 8010980: 2d0c cmp r5, #12
  36412. 8010982: bf38 it cc
  36413. 8010984: 250c movcc r5, #12
  36414. 8010986: 2d00 cmp r5, #0
  36415. 8010988: 4606 mov r6, r0
  36416. 801098a: db01 blt.n 8010990 <_malloc_r+0x1c>
  36417. 801098c: 42a9 cmp r1, r5
  36418. 801098e: d904 bls.n 801099a <_malloc_r+0x26>
  36419. 8010990: 230c movs r3, #12
  36420. 8010992: 6033 str r3, [r6, #0]
  36421. 8010994: 2000 movs r0, #0
  36422. 8010996: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  36423. 801099a: f8df 80d4 ldr.w r8, [pc, #212] @ 8010a70 <_malloc_r+0xfc>
  36424. 801099e: f000 f869 bl 8010a74 <__malloc_lock>
  36425. 80109a2: f8d8 3000 ldr.w r3, [r8]
  36426. 80109a6: 461c mov r4, r3
  36427. 80109a8: bb44 cbnz r4, 80109fc <_malloc_r+0x88>
  36428. 80109aa: 4629 mov r1, r5
  36429. 80109ac: 4630 mov r0, r6
  36430. 80109ae: f7ff ffbf bl 8010930 <sbrk_aligned>
  36431. 80109b2: 1c43 adds r3, r0, #1
  36432. 80109b4: 4604 mov r4, r0
  36433. 80109b6: d158 bne.n 8010a6a <_malloc_r+0xf6>
  36434. 80109b8: f8d8 4000 ldr.w r4, [r8]
  36435. 80109bc: 4627 mov r7, r4
  36436. 80109be: 2f00 cmp r7, #0
  36437. 80109c0: d143 bne.n 8010a4a <_malloc_r+0xd6>
  36438. 80109c2: 2c00 cmp r4, #0
  36439. 80109c4: d04b beq.n 8010a5e <_malloc_r+0xea>
  36440. 80109c6: 6823 ldr r3, [r4, #0]
  36441. 80109c8: 4639 mov r1, r7
  36442. 80109ca: 4630 mov r0, r6
  36443. 80109cc: eb04 0903 add.w r9, r4, r3
  36444. 80109d0: f000 fd0e bl 80113f0 <_sbrk_r>
  36445. 80109d4: 4581 cmp r9, r0
  36446. 80109d6: d142 bne.n 8010a5e <_malloc_r+0xea>
  36447. 80109d8: 6821 ldr r1, [r4, #0]
  36448. 80109da: 1a6d subs r5, r5, r1
  36449. 80109dc: 4629 mov r1, r5
  36450. 80109de: 4630 mov r0, r6
  36451. 80109e0: f7ff ffa6 bl 8010930 <sbrk_aligned>
  36452. 80109e4: 3001 adds r0, #1
  36453. 80109e6: d03a beq.n 8010a5e <_malloc_r+0xea>
  36454. 80109e8: 6823 ldr r3, [r4, #0]
  36455. 80109ea: 442b add r3, r5
  36456. 80109ec: 6023 str r3, [r4, #0]
  36457. 80109ee: f8d8 3000 ldr.w r3, [r8]
  36458. 80109f2: 685a ldr r2, [r3, #4]
  36459. 80109f4: bb62 cbnz r2, 8010a50 <_malloc_r+0xdc>
  36460. 80109f6: f8c8 7000 str.w r7, [r8]
  36461. 80109fa: e00f b.n 8010a1c <_malloc_r+0xa8>
  36462. 80109fc: 6822 ldr r2, [r4, #0]
  36463. 80109fe: 1b52 subs r2, r2, r5
  36464. 8010a00: d420 bmi.n 8010a44 <_malloc_r+0xd0>
  36465. 8010a02: 2a0b cmp r2, #11
  36466. 8010a04: d917 bls.n 8010a36 <_malloc_r+0xc2>
  36467. 8010a06: 1961 adds r1, r4, r5
  36468. 8010a08: 42a3 cmp r3, r4
  36469. 8010a0a: 6025 str r5, [r4, #0]
  36470. 8010a0c: bf18 it ne
  36471. 8010a0e: 6059 strne r1, [r3, #4]
  36472. 8010a10: 6863 ldr r3, [r4, #4]
  36473. 8010a12: bf08 it eq
  36474. 8010a14: f8c8 1000 streq.w r1, [r8]
  36475. 8010a18: 5162 str r2, [r4, r5]
  36476. 8010a1a: 604b str r3, [r1, #4]
  36477. 8010a1c: 4630 mov r0, r6
  36478. 8010a1e: f000 f82f bl 8010a80 <__malloc_unlock>
  36479. 8010a22: f104 000b add.w r0, r4, #11
  36480. 8010a26: 1d23 adds r3, r4, #4
  36481. 8010a28: f020 0007 bic.w r0, r0, #7
  36482. 8010a2c: 1ac2 subs r2, r0, r3
  36483. 8010a2e: bf1c itt ne
  36484. 8010a30: 1a1b subne r3, r3, r0
  36485. 8010a32: 50a3 strne r3, [r4, r2]
  36486. 8010a34: e7af b.n 8010996 <_malloc_r+0x22>
  36487. 8010a36: 6862 ldr r2, [r4, #4]
  36488. 8010a38: 42a3 cmp r3, r4
  36489. 8010a3a: bf0c ite eq
  36490. 8010a3c: f8c8 2000 streq.w r2, [r8]
  36491. 8010a40: 605a strne r2, [r3, #4]
  36492. 8010a42: e7eb b.n 8010a1c <_malloc_r+0xa8>
  36493. 8010a44: 4623 mov r3, r4
  36494. 8010a46: 6864 ldr r4, [r4, #4]
  36495. 8010a48: e7ae b.n 80109a8 <_malloc_r+0x34>
  36496. 8010a4a: 463c mov r4, r7
  36497. 8010a4c: 687f ldr r7, [r7, #4]
  36498. 8010a4e: e7b6 b.n 80109be <_malloc_r+0x4a>
  36499. 8010a50: 461a mov r2, r3
  36500. 8010a52: 685b ldr r3, [r3, #4]
  36501. 8010a54: 42a3 cmp r3, r4
  36502. 8010a56: d1fb bne.n 8010a50 <_malloc_r+0xdc>
  36503. 8010a58: 2300 movs r3, #0
  36504. 8010a5a: 6053 str r3, [r2, #4]
  36505. 8010a5c: e7de b.n 8010a1c <_malloc_r+0xa8>
  36506. 8010a5e: 230c movs r3, #12
  36507. 8010a60: 6033 str r3, [r6, #0]
  36508. 8010a62: 4630 mov r0, r6
  36509. 8010a64: f000 f80c bl 8010a80 <__malloc_unlock>
  36510. 8010a68: e794 b.n 8010994 <_malloc_r+0x20>
  36511. 8010a6a: 6005 str r5, [r0, #0]
  36512. 8010a6c: e7d6 b.n 8010a1c <_malloc_r+0xa8>
  36513. 8010a6e: bf00 nop
  36514. 8010a70: 240132e0 .word 0x240132e0
  36515. 08010a74 <__malloc_lock>:
  36516. 8010a74: 4801 ldr r0, [pc, #4] @ (8010a7c <__malloc_lock+0x8>)
  36517. 8010a76: f7ff b91a b.w 800fcae <__retarget_lock_acquire_recursive>
  36518. 8010a7a: bf00 nop
  36519. 8010a7c: 240132d8 .word 0x240132d8
  36520. 08010a80 <__malloc_unlock>:
  36521. 8010a80: 4801 ldr r0, [pc, #4] @ (8010a88 <__malloc_unlock+0x8>)
  36522. 8010a82: f7ff b915 b.w 800fcb0 <__retarget_lock_release_recursive>
  36523. 8010a86: bf00 nop
  36524. 8010a88: 240132d8 .word 0x240132d8
  36525. 08010a8c <_Balloc>:
  36526. 8010a8c: b570 push {r4, r5, r6, lr}
  36527. 8010a8e: 69c6 ldr r6, [r0, #28]
  36528. 8010a90: 4604 mov r4, r0
  36529. 8010a92: 460d mov r5, r1
  36530. 8010a94: b976 cbnz r6, 8010ab4 <_Balloc+0x28>
  36531. 8010a96: 2010 movs r0, #16
  36532. 8010a98: f7ff ff42 bl 8010920 <malloc>
  36533. 8010a9c: 4602 mov r2, r0
  36534. 8010a9e: 61e0 str r0, [r4, #28]
  36535. 8010aa0: b920 cbnz r0, 8010aac <_Balloc+0x20>
  36536. 8010aa2: 4b18 ldr r3, [pc, #96] @ (8010b04 <_Balloc+0x78>)
  36537. 8010aa4: 4818 ldr r0, [pc, #96] @ (8010b08 <_Balloc+0x7c>)
  36538. 8010aa6: 216b movs r1, #107 @ 0x6b
  36539. 8010aa8: f000 fcb2 bl 8011410 <__assert_func>
  36540. 8010aac: e9c0 6601 strd r6, r6, [r0, #4]
  36541. 8010ab0: 6006 str r6, [r0, #0]
  36542. 8010ab2: 60c6 str r6, [r0, #12]
  36543. 8010ab4: 69e6 ldr r6, [r4, #28]
  36544. 8010ab6: 68f3 ldr r3, [r6, #12]
  36545. 8010ab8: b183 cbz r3, 8010adc <_Balloc+0x50>
  36546. 8010aba: 69e3 ldr r3, [r4, #28]
  36547. 8010abc: 68db ldr r3, [r3, #12]
  36548. 8010abe: f853 0025 ldr.w r0, [r3, r5, lsl #2]
  36549. 8010ac2: b9b8 cbnz r0, 8010af4 <_Balloc+0x68>
  36550. 8010ac4: 2101 movs r1, #1
  36551. 8010ac6: fa01 f605 lsl.w r6, r1, r5
  36552. 8010aca: 1d72 adds r2, r6, #5
  36553. 8010acc: 0092 lsls r2, r2, #2
  36554. 8010ace: 4620 mov r0, r4
  36555. 8010ad0: f000 fcbc bl 801144c <_calloc_r>
  36556. 8010ad4: b160 cbz r0, 8010af0 <_Balloc+0x64>
  36557. 8010ad6: e9c0 5601 strd r5, r6, [r0, #4]
  36558. 8010ada: e00e b.n 8010afa <_Balloc+0x6e>
  36559. 8010adc: 2221 movs r2, #33 @ 0x21
  36560. 8010ade: 2104 movs r1, #4
  36561. 8010ae0: 4620 mov r0, r4
  36562. 8010ae2: f000 fcb3 bl 801144c <_calloc_r>
  36563. 8010ae6: 69e3 ldr r3, [r4, #28]
  36564. 8010ae8: 60f0 str r0, [r6, #12]
  36565. 8010aea: 68db ldr r3, [r3, #12]
  36566. 8010aec: 2b00 cmp r3, #0
  36567. 8010aee: d1e4 bne.n 8010aba <_Balloc+0x2e>
  36568. 8010af0: 2000 movs r0, #0
  36569. 8010af2: bd70 pop {r4, r5, r6, pc}
  36570. 8010af4: 6802 ldr r2, [r0, #0]
  36571. 8010af6: f843 2025 str.w r2, [r3, r5, lsl #2]
  36572. 8010afa: 2300 movs r3, #0
  36573. 8010afc: e9c0 3303 strd r3, r3, [r0, #12]
  36574. 8010b00: e7f7 b.n 8010af2 <_Balloc+0x66>
  36575. 8010b02: bf00 nop
  36576. 8010b04: 08011aad .word 0x08011aad
  36577. 8010b08: 08011b2d .word 0x08011b2d
  36578. 08010b0c <_Bfree>:
  36579. 8010b0c: b570 push {r4, r5, r6, lr}
  36580. 8010b0e: 69c6 ldr r6, [r0, #28]
  36581. 8010b10: 4605 mov r5, r0
  36582. 8010b12: 460c mov r4, r1
  36583. 8010b14: b976 cbnz r6, 8010b34 <_Bfree+0x28>
  36584. 8010b16: 2010 movs r0, #16
  36585. 8010b18: f7ff ff02 bl 8010920 <malloc>
  36586. 8010b1c: 4602 mov r2, r0
  36587. 8010b1e: 61e8 str r0, [r5, #28]
  36588. 8010b20: b920 cbnz r0, 8010b2c <_Bfree+0x20>
  36589. 8010b22: 4b09 ldr r3, [pc, #36] @ (8010b48 <_Bfree+0x3c>)
  36590. 8010b24: 4809 ldr r0, [pc, #36] @ (8010b4c <_Bfree+0x40>)
  36591. 8010b26: 218f movs r1, #143 @ 0x8f
  36592. 8010b28: f000 fc72 bl 8011410 <__assert_func>
  36593. 8010b2c: e9c0 6601 strd r6, r6, [r0, #4]
  36594. 8010b30: 6006 str r6, [r0, #0]
  36595. 8010b32: 60c6 str r6, [r0, #12]
  36596. 8010b34: b13c cbz r4, 8010b46 <_Bfree+0x3a>
  36597. 8010b36: 69eb ldr r3, [r5, #28]
  36598. 8010b38: 6862 ldr r2, [r4, #4]
  36599. 8010b3a: 68db ldr r3, [r3, #12]
  36600. 8010b3c: f853 1022 ldr.w r1, [r3, r2, lsl #2]
  36601. 8010b40: 6021 str r1, [r4, #0]
  36602. 8010b42: f843 4022 str.w r4, [r3, r2, lsl #2]
  36603. 8010b46: bd70 pop {r4, r5, r6, pc}
  36604. 8010b48: 08011aad .word 0x08011aad
  36605. 8010b4c: 08011b2d .word 0x08011b2d
  36606. 08010b50 <__multadd>:
  36607. 8010b50: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  36608. 8010b54: 690d ldr r5, [r1, #16]
  36609. 8010b56: 4607 mov r7, r0
  36610. 8010b58: 460c mov r4, r1
  36611. 8010b5a: 461e mov r6, r3
  36612. 8010b5c: f101 0c14 add.w ip, r1, #20
  36613. 8010b60: 2000 movs r0, #0
  36614. 8010b62: f8dc 3000 ldr.w r3, [ip]
  36615. 8010b66: b299 uxth r1, r3
  36616. 8010b68: fb02 6101 mla r1, r2, r1, r6
  36617. 8010b6c: 0c1e lsrs r6, r3, #16
  36618. 8010b6e: 0c0b lsrs r3, r1, #16
  36619. 8010b70: fb02 3306 mla r3, r2, r6, r3
  36620. 8010b74: b289 uxth r1, r1
  36621. 8010b76: 3001 adds r0, #1
  36622. 8010b78: eb01 4103 add.w r1, r1, r3, lsl #16
  36623. 8010b7c: 4285 cmp r5, r0
  36624. 8010b7e: f84c 1b04 str.w r1, [ip], #4
  36625. 8010b82: ea4f 4613 mov.w r6, r3, lsr #16
  36626. 8010b86: dcec bgt.n 8010b62 <__multadd+0x12>
  36627. 8010b88: b30e cbz r6, 8010bce <__multadd+0x7e>
  36628. 8010b8a: 68a3 ldr r3, [r4, #8]
  36629. 8010b8c: 42ab cmp r3, r5
  36630. 8010b8e: dc19 bgt.n 8010bc4 <__multadd+0x74>
  36631. 8010b90: 6861 ldr r1, [r4, #4]
  36632. 8010b92: 4638 mov r0, r7
  36633. 8010b94: 3101 adds r1, #1
  36634. 8010b96: f7ff ff79 bl 8010a8c <_Balloc>
  36635. 8010b9a: 4680 mov r8, r0
  36636. 8010b9c: b928 cbnz r0, 8010baa <__multadd+0x5a>
  36637. 8010b9e: 4602 mov r2, r0
  36638. 8010ba0: 4b0c ldr r3, [pc, #48] @ (8010bd4 <__multadd+0x84>)
  36639. 8010ba2: 480d ldr r0, [pc, #52] @ (8010bd8 <__multadd+0x88>)
  36640. 8010ba4: 21ba movs r1, #186 @ 0xba
  36641. 8010ba6: f000 fc33 bl 8011410 <__assert_func>
  36642. 8010baa: 6922 ldr r2, [r4, #16]
  36643. 8010bac: 3202 adds r2, #2
  36644. 8010bae: f104 010c add.w r1, r4, #12
  36645. 8010bb2: 0092 lsls r2, r2, #2
  36646. 8010bb4: 300c adds r0, #12
  36647. 8010bb6: f7ff f87c bl 800fcb2 <memcpy>
  36648. 8010bba: 4621 mov r1, r4
  36649. 8010bbc: 4638 mov r0, r7
  36650. 8010bbe: f7ff ffa5 bl 8010b0c <_Bfree>
  36651. 8010bc2: 4644 mov r4, r8
  36652. 8010bc4: eb04 0385 add.w r3, r4, r5, lsl #2
  36653. 8010bc8: 3501 adds r5, #1
  36654. 8010bca: 615e str r6, [r3, #20]
  36655. 8010bcc: 6125 str r5, [r4, #16]
  36656. 8010bce: 4620 mov r0, r4
  36657. 8010bd0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  36658. 8010bd4: 08011b1c .word 0x08011b1c
  36659. 8010bd8: 08011b2d .word 0x08011b2d
  36660. 08010bdc <__hi0bits>:
  36661. 8010bdc: f5b0 3f80 cmp.w r0, #65536 @ 0x10000
  36662. 8010be0: 4603 mov r3, r0
  36663. 8010be2: bf36 itet cc
  36664. 8010be4: 0403 lslcc r3, r0, #16
  36665. 8010be6: 2000 movcs r0, #0
  36666. 8010be8: 2010 movcc r0, #16
  36667. 8010bea: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
  36668. 8010bee: bf3c itt cc
  36669. 8010bf0: 021b lslcc r3, r3, #8
  36670. 8010bf2: 3008 addcc r0, #8
  36671. 8010bf4: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
  36672. 8010bf8: bf3c itt cc
  36673. 8010bfa: 011b lslcc r3, r3, #4
  36674. 8010bfc: 3004 addcc r0, #4
  36675. 8010bfe: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
  36676. 8010c02: bf3c itt cc
  36677. 8010c04: 009b lslcc r3, r3, #2
  36678. 8010c06: 3002 addcc r0, #2
  36679. 8010c08: 2b00 cmp r3, #0
  36680. 8010c0a: db05 blt.n 8010c18 <__hi0bits+0x3c>
  36681. 8010c0c: f013 4f80 tst.w r3, #1073741824 @ 0x40000000
  36682. 8010c10: f100 0001 add.w r0, r0, #1
  36683. 8010c14: bf08 it eq
  36684. 8010c16: 2020 moveq r0, #32
  36685. 8010c18: 4770 bx lr
  36686. 08010c1a <__lo0bits>:
  36687. 8010c1a: 6803 ldr r3, [r0, #0]
  36688. 8010c1c: 4602 mov r2, r0
  36689. 8010c1e: f013 0007 ands.w r0, r3, #7
  36690. 8010c22: d00b beq.n 8010c3c <__lo0bits+0x22>
  36691. 8010c24: 07d9 lsls r1, r3, #31
  36692. 8010c26: d421 bmi.n 8010c6c <__lo0bits+0x52>
  36693. 8010c28: 0798 lsls r0, r3, #30
  36694. 8010c2a: bf49 itett mi
  36695. 8010c2c: 085b lsrmi r3, r3, #1
  36696. 8010c2e: 089b lsrpl r3, r3, #2
  36697. 8010c30: 2001 movmi r0, #1
  36698. 8010c32: 6013 strmi r3, [r2, #0]
  36699. 8010c34: bf5c itt pl
  36700. 8010c36: 6013 strpl r3, [r2, #0]
  36701. 8010c38: 2002 movpl r0, #2
  36702. 8010c3a: 4770 bx lr
  36703. 8010c3c: b299 uxth r1, r3
  36704. 8010c3e: b909 cbnz r1, 8010c44 <__lo0bits+0x2a>
  36705. 8010c40: 0c1b lsrs r3, r3, #16
  36706. 8010c42: 2010 movs r0, #16
  36707. 8010c44: b2d9 uxtb r1, r3
  36708. 8010c46: b909 cbnz r1, 8010c4c <__lo0bits+0x32>
  36709. 8010c48: 3008 adds r0, #8
  36710. 8010c4a: 0a1b lsrs r3, r3, #8
  36711. 8010c4c: 0719 lsls r1, r3, #28
  36712. 8010c4e: bf04 itt eq
  36713. 8010c50: 091b lsreq r3, r3, #4
  36714. 8010c52: 3004 addeq r0, #4
  36715. 8010c54: 0799 lsls r1, r3, #30
  36716. 8010c56: bf04 itt eq
  36717. 8010c58: 089b lsreq r3, r3, #2
  36718. 8010c5a: 3002 addeq r0, #2
  36719. 8010c5c: 07d9 lsls r1, r3, #31
  36720. 8010c5e: d403 bmi.n 8010c68 <__lo0bits+0x4e>
  36721. 8010c60: 085b lsrs r3, r3, #1
  36722. 8010c62: f100 0001 add.w r0, r0, #1
  36723. 8010c66: d003 beq.n 8010c70 <__lo0bits+0x56>
  36724. 8010c68: 6013 str r3, [r2, #0]
  36725. 8010c6a: 4770 bx lr
  36726. 8010c6c: 2000 movs r0, #0
  36727. 8010c6e: 4770 bx lr
  36728. 8010c70: 2020 movs r0, #32
  36729. 8010c72: 4770 bx lr
  36730. 08010c74 <__i2b>:
  36731. 8010c74: b510 push {r4, lr}
  36732. 8010c76: 460c mov r4, r1
  36733. 8010c78: 2101 movs r1, #1
  36734. 8010c7a: f7ff ff07 bl 8010a8c <_Balloc>
  36735. 8010c7e: 4602 mov r2, r0
  36736. 8010c80: b928 cbnz r0, 8010c8e <__i2b+0x1a>
  36737. 8010c82: 4b05 ldr r3, [pc, #20] @ (8010c98 <__i2b+0x24>)
  36738. 8010c84: 4805 ldr r0, [pc, #20] @ (8010c9c <__i2b+0x28>)
  36739. 8010c86: f240 1145 movw r1, #325 @ 0x145
  36740. 8010c8a: f000 fbc1 bl 8011410 <__assert_func>
  36741. 8010c8e: 2301 movs r3, #1
  36742. 8010c90: 6144 str r4, [r0, #20]
  36743. 8010c92: 6103 str r3, [r0, #16]
  36744. 8010c94: bd10 pop {r4, pc}
  36745. 8010c96: bf00 nop
  36746. 8010c98: 08011b1c .word 0x08011b1c
  36747. 8010c9c: 08011b2d .word 0x08011b2d
  36748. 08010ca0 <__multiply>:
  36749. 8010ca0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  36750. 8010ca4: 4614 mov r4, r2
  36751. 8010ca6: 690a ldr r2, [r1, #16]
  36752. 8010ca8: 6923 ldr r3, [r4, #16]
  36753. 8010caa: 429a cmp r2, r3
  36754. 8010cac: bfa8 it ge
  36755. 8010cae: 4623 movge r3, r4
  36756. 8010cb0: 460f mov r7, r1
  36757. 8010cb2: bfa4 itt ge
  36758. 8010cb4: 460c movge r4, r1
  36759. 8010cb6: 461f movge r7, r3
  36760. 8010cb8: f8d4 a010 ldr.w sl, [r4, #16]
  36761. 8010cbc: f8d7 9010 ldr.w r9, [r7, #16]
  36762. 8010cc0: 68a3 ldr r3, [r4, #8]
  36763. 8010cc2: 6861 ldr r1, [r4, #4]
  36764. 8010cc4: eb0a 0609 add.w r6, sl, r9
  36765. 8010cc8: 42b3 cmp r3, r6
  36766. 8010cca: b085 sub sp, #20
  36767. 8010ccc: bfb8 it lt
  36768. 8010cce: 3101 addlt r1, #1
  36769. 8010cd0: f7ff fedc bl 8010a8c <_Balloc>
  36770. 8010cd4: b930 cbnz r0, 8010ce4 <__multiply+0x44>
  36771. 8010cd6: 4602 mov r2, r0
  36772. 8010cd8: 4b44 ldr r3, [pc, #272] @ (8010dec <__multiply+0x14c>)
  36773. 8010cda: 4845 ldr r0, [pc, #276] @ (8010df0 <__multiply+0x150>)
  36774. 8010cdc: f44f 71b1 mov.w r1, #354 @ 0x162
  36775. 8010ce0: f000 fb96 bl 8011410 <__assert_func>
  36776. 8010ce4: f100 0514 add.w r5, r0, #20
  36777. 8010ce8: eb05 0886 add.w r8, r5, r6, lsl #2
  36778. 8010cec: 462b mov r3, r5
  36779. 8010cee: 2200 movs r2, #0
  36780. 8010cf0: 4543 cmp r3, r8
  36781. 8010cf2: d321 bcc.n 8010d38 <__multiply+0x98>
  36782. 8010cf4: f107 0114 add.w r1, r7, #20
  36783. 8010cf8: f104 0214 add.w r2, r4, #20
  36784. 8010cfc: eb02 028a add.w r2, r2, sl, lsl #2
  36785. 8010d00: eb01 0389 add.w r3, r1, r9, lsl #2
  36786. 8010d04: 9302 str r3, [sp, #8]
  36787. 8010d06: 1b13 subs r3, r2, r4
  36788. 8010d08: 3b15 subs r3, #21
  36789. 8010d0a: f023 0303 bic.w r3, r3, #3
  36790. 8010d0e: 3304 adds r3, #4
  36791. 8010d10: f104 0715 add.w r7, r4, #21
  36792. 8010d14: 42ba cmp r2, r7
  36793. 8010d16: bf38 it cc
  36794. 8010d18: 2304 movcc r3, #4
  36795. 8010d1a: 9301 str r3, [sp, #4]
  36796. 8010d1c: 9b02 ldr r3, [sp, #8]
  36797. 8010d1e: 9103 str r1, [sp, #12]
  36798. 8010d20: 428b cmp r3, r1
  36799. 8010d22: d80c bhi.n 8010d3e <__multiply+0x9e>
  36800. 8010d24: 2e00 cmp r6, #0
  36801. 8010d26: dd03 ble.n 8010d30 <__multiply+0x90>
  36802. 8010d28: f858 3d04 ldr.w r3, [r8, #-4]!
  36803. 8010d2c: 2b00 cmp r3, #0
  36804. 8010d2e: d05b beq.n 8010de8 <__multiply+0x148>
  36805. 8010d30: 6106 str r6, [r0, #16]
  36806. 8010d32: b005 add sp, #20
  36807. 8010d34: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  36808. 8010d38: f843 2b04 str.w r2, [r3], #4
  36809. 8010d3c: e7d8 b.n 8010cf0 <__multiply+0x50>
  36810. 8010d3e: f8b1 a000 ldrh.w sl, [r1]
  36811. 8010d42: f1ba 0f00 cmp.w sl, #0
  36812. 8010d46: d024 beq.n 8010d92 <__multiply+0xf2>
  36813. 8010d48: f104 0e14 add.w lr, r4, #20
  36814. 8010d4c: 46a9 mov r9, r5
  36815. 8010d4e: f04f 0c00 mov.w ip, #0
  36816. 8010d52: f85e 7b04 ldr.w r7, [lr], #4
  36817. 8010d56: f8d9 3000 ldr.w r3, [r9]
  36818. 8010d5a: fa1f fb87 uxth.w fp, r7
  36819. 8010d5e: b29b uxth r3, r3
  36820. 8010d60: fb0a 330b mla r3, sl, fp, r3
  36821. 8010d64: ea4f 4b17 mov.w fp, r7, lsr #16
  36822. 8010d68: f8d9 7000 ldr.w r7, [r9]
  36823. 8010d6c: 4463 add r3, ip
  36824. 8010d6e: ea4f 4c17 mov.w ip, r7, lsr #16
  36825. 8010d72: fb0a c70b mla r7, sl, fp, ip
  36826. 8010d76: eb07 4713 add.w r7, r7, r3, lsr #16
  36827. 8010d7a: b29b uxth r3, r3
  36828. 8010d7c: ea43 4307 orr.w r3, r3, r7, lsl #16
  36829. 8010d80: 4572 cmp r2, lr
  36830. 8010d82: f849 3b04 str.w r3, [r9], #4
  36831. 8010d86: ea4f 4c17 mov.w ip, r7, lsr #16
  36832. 8010d8a: d8e2 bhi.n 8010d52 <__multiply+0xb2>
  36833. 8010d8c: 9b01 ldr r3, [sp, #4]
  36834. 8010d8e: f845 c003 str.w ip, [r5, r3]
  36835. 8010d92: 9b03 ldr r3, [sp, #12]
  36836. 8010d94: f8b3 9002 ldrh.w r9, [r3, #2]
  36837. 8010d98: 3104 adds r1, #4
  36838. 8010d9a: f1b9 0f00 cmp.w r9, #0
  36839. 8010d9e: d021 beq.n 8010de4 <__multiply+0x144>
  36840. 8010da0: 682b ldr r3, [r5, #0]
  36841. 8010da2: f104 0c14 add.w ip, r4, #20
  36842. 8010da6: 46ae mov lr, r5
  36843. 8010da8: f04f 0a00 mov.w sl, #0
  36844. 8010dac: f8bc b000 ldrh.w fp, [ip]
  36845. 8010db0: f8be 7002 ldrh.w r7, [lr, #2]
  36846. 8010db4: fb09 770b mla r7, r9, fp, r7
  36847. 8010db8: 4457 add r7, sl
  36848. 8010dba: b29b uxth r3, r3
  36849. 8010dbc: ea43 4307 orr.w r3, r3, r7, lsl #16
  36850. 8010dc0: f84e 3b04 str.w r3, [lr], #4
  36851. 8010dc4: f85c 3b04 ldr.w r3, [ip], #4
  36852. 8010dc8: ea4f 4a13 mov.w sl, r3, lsr #16
  36853. 8010dcc: f8be 3000 ldrh.w r3, [lr]
  36854. 8010dd0: fb09 330a mla r3, r9, sl, r3
  36855. 8010dd4: eb03 4317 add.w r3, r3, r7, lsr #16
  36856. 8010dd8: 4562 cmp r2, ip
  36857. 8010dda: ea4f 4a13 mov.w sl, r3, lsr #16
  36858. 8010dde: d8e5 bhi.n 8010dac <__multiply+0x10c>
  36859. 8010de0: 9f01 ldr r7, [sp, #4]
  36860. 8010de2: 51eb str r3, [r5, r7]
  36861. 8010de4: 3504 adds r5, #4
  36862. 8010de6: e799 b.n 8010d1c <__multiply+0x7c>
  36863. 8010de8: 3e01 subs r6, #1
  36864. 8010dea: e79b b.n 8010d24 <__multiply+0x84>
  36865. 8010dec: 08011b1c .word 0x08011b1c
  36866. 8010df0: 08011b2d .word 0x08011b2d
  36867. 08010df4 <__pow5mult>:
  36868. 8010df4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  36869. 8010df8: 4615 mov r5, r2
  36870. 8010dfa: f012 0203 ands.w r2, r2, #3
  36871. 8010dfe: 4607 mov r7, r0
  36872. 8010e00: 460e mov r6, r1
  36873. 8010e02: d007 beq.n 8010e14 <__pow5mult+0x20>
  36874. 8010e04: 4c25 ldr r4, [pc, #148] @ (8010e9c <__pow5mult+0xa8>)
  36875. 8010e06: 3a01 subs r2, #1
  36876. 8010e08: 2300 movs r3, #0
  36877. 8010e0a: f854 2022 ldr.w r2, [r4, r2, lsl #2]
  36878. 8010e0e: f7ff fe9f bl 8010b50 <__multadd>
  36879. 8010e12: 4606 mov r6, r0
  36880. 8010e14: 10ad asrs r5, r5, #2
  36881. 8010e16: d03d beq.n 8010e94 <__pow5mult+0xa0>
  36882. 8010e18: 69fc ldr r4, [r7, #28]
  36883. 8010e1a: b97c cbnz r4, 8010e3c <__pow5mult+0x48>
  36884. 8010e1c: 2010 movs r0, #16
  36885. 8010e1e: f7ff fd7f bl 8010920 <malloc>
  36886. 8010e22: 4602 mov r2, r0
  36887. 8010e24: 61f8 str r0, [r7, #28]
  36888. 8010e26: b928 cbnz r0, 8010e34 <__pow5mult+0x40>
  36889. 8010e28: 4b1d ldr r3, [pc, #116] @ (8010ea0 <__pow5mult+0xac>)
  36890. 8010e2a: 481e ldr r0, [pc, #120] @ (8010ea4 <__pow5mult+0xb0>)
  36891. 8010e2c: f240 11b3 movw r1, #435 @ 0x1b3
  36892. 8010e30: f000 faee bl 8011410 <__assert_func>
  36893. 8010e34: e9c0 4401 strd r4, r4, [r0, #4]
  36894. 8010e38: 6004 str r4, [r0, #0]
  36895. 8010e3a: 60c4 str r4, [r0, #12]
  36896. 8010e3c: f8d7 801c ldr.w r8, [r7, #28]
  36897. 8010e40: f8d8 4008 ldr.w r4, [r8, #8]
  36898. 8010e44: b94c cbnz r4, 8010e5a <__pow5mult+0x66>
  36899. 8010e46: f240 2171 movw r1, #625 @ 0x271
  36900. 8010e4a: 4638 mov r0, r7
  36901. 8010e4c: f7ff ff12 bl 8010c74 <__i2b>
  36902. 8010e50: 2300 movs r3, #0
  36903. 8010e52: f8c8 0008 str.w r0, [r8, #8]
  36904. 8010e56: 4604 mov r4, r0
  36905. 8010e58: 6003 str r3, [r0, #0]
  36906. 8010e5a: f04f 0900 mov.w r9, #0
  36907. 8010e5e: 07eb lsls r3, r5, #31
  36908. 8010e60: d50a bpl.n 8010e78 <__pow5mult+0x84>
  36909. 8010e62: 4631 mov r1, r6
  36910. 8010e64: 4622 mov r2, r4
  36911. 8010e66: 4638 mov r0, r7
  36912. 8010e68: f7ff ff1a bl 8010ca0 <__multiply>
  36913. 8010e6c: 4631 mov r1, r6
  36914. 8010e6e: 4680 mov r8, r0
  36915. 8010e70: 4638 mov r0, r7
  36916. 8010e72: f7ff fe4b bl 8010b0c <_Bfree>
  36917. 8010e76: 4646 mov r6, r8
  36918. 8010e78: 106d asrs r5, r5, #1
  36919. 8010e7a: d00b beq.n 8010e94 <__pow5mult+0xa0>
  36920. 8010e7c: 6820 ldr r0, [r4, #0]
  36921. 8010e7e: b938 cbnz r0, 8010e90 <__pow5mult+0x9c>
  36922. 8010e80: 4622 mov r2, r4
  36923. 8010e82: 4621 mov r1, r4
  36924. 8010e84: 4638 mov r0, r7
  36925. 8010e86: f7ff ff0b bl 8010ca0 <__multiply>
  36926. 8010e8a: 6020 str r0, [r4, #0]
  36927. 8010e8c: f8c0 9000 str.w r9, [r0]
  36928. 8010e90: 4604 mov r4, r0
  36929. 8010e92: e7e4 b.n 8010e5e <__pow5mult+0x6a>
  36930. 8010e94: 4630 mov r0, r6
  36931. 8010e96: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  36932. 8010e9a: bf00 nop
  36933. 8010e9c: 08011b88 .word 0x08011b88
  36934. 8010ea0: 08011aad .word 0x08011aad
  36935. 8010ea4: 08011b2d .word 0x08011b2d
  36936. 08010ea8 <__lshift>:
  36937. 8010ea8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  36938. 8010eac: 460c mov r4, r1
  36939. 8010eae: 6849 ldr r1, [r1, #4]
  36940. 8010eb0: 6923 ldr r3, [r4, #16]
  36941. 8010eb2: eb03 1862 add.w r8, r3, r2, asr #5
  36942. 8010eb6: 68a3 ldr r3, [r4, #8]
  36943. 8010eb8: 4607 mov r7, r0
  36944. 8010eba: 4691 mov r9, r2
  36945. 8010ebc: ea4f 1a62 mov.w sl, r2, asr #5
  36946. 8010ec0: f108 0601 add.w r6, r8, #1
  36947. 8010ec4: 42b3 cmp r3, r6
  36948. 8010ec6: db0b blt.n 8010ee0 <__lshift+0x38>
  36949. 8010ec8: 4638 mov r0, r7
  36950. 8010eca: f7ff fddf bl 8010a8c <_Balloc>
  36951. 8010ece: 4605 mov r5, r0
  36952. 8010ed0: b948 cbnz r0, 8010ee6 <__lshift+0x3e>
  36953. 8010ed2: 4602 mov r2, r0
  36954. 8010ed4: 4b28 ldr r3, [pc, #160] @ (8010f78 <__lshift+0xd0>)
  36955. 8010ed6: 4829 ldr r0, [pc, #164] @ (8010f7c <__lshift+0xd4>)
  36956. 8010ed8: f44f 71ef mov.w r1, #478 @ 0x1de
  36957. 8010edc: f000 fa98 bl 8011410 <__assert_func>
  36958. 8010ee0: 3101 adds r1, #1
  36959. 8010ee2: 005b lsls r3, r3, #1
  36960. 8010ee4: e7ee b.n 8010ec4 <__lshift+0x1c>
  36961. 8010ee6: 2300 movs r3, #0
  36962. 8010ee8: f100 0114 add.w r1, r0, #20
  36963. 8010eec: f100 0210 add.w r2, r0, #16
  36964. 8010ef0: 4618 mov r0, r3
  36965. 8010ef2: 4553 cmp r3, sl
  36966. 8010ef4: db33 blt.n 8010f5e <__lshift+0xb6>
  36967. 8010ef6: 6920 ldr r0, [r4, #16]
  36968. 8010ef8: ea2a 7aea bic.w sl, sl, sl, asr #31
  36969. 8010efc: f104 0314 add.w r3, r4, #20
  36970. 8010f00: f019 091f ands.w r9, r9, #31
  36971. 8010f04: eb01 018a add.w r1, r1, sl, lsl #2
  36972. 8010f08: eb03 0c80 add.w ip, r3, r0, lsl #2
  36973. 8010f0c: d02b beq.n 8010f66 <__lshift+0xbe>
  36974. 8010f0e: f1c9 0e20 rsb lr, r9, #32
  36975. 8010f12: 468a mov sl, r1
  36976. 8010f14: 2200 movs r2, #0
  36977. 8010f16: 6818 ldr r0, [r3, #0]
  36978. 8010f18: fa00 f009 lsl.w r0, r0, r9
  36979. 8010f1c: 4310 orrs r0, r2
  36980. 8010f1e: f84a 0b04 str.w r0, [sl], #4
  36981. 8010f22: f853 2b04 ldr.w r2, [r3], #4
  36982. 8010f26: 459c cmp ip, r3
  36983. 8010f28: fa22 f20e lsr.w r2, r2, lr
  36984. 8010f2c: d8f3 bhi.n 8010f16 <__lshift+0x6e>
  36985. 8010f2e: ebac 0304 sub.w r3, ip, r4
  36986. 8010f32: 3b15 subs r3, #21
  36987. 8010f34: f023 0303 bic.w r3, r3, #3
  36988. 8010f38: 3304 adds r3, #4
  36989. 8010f3a: f104 0015 add.w r0, r4, #21
  36990. 8010f3e: 4584 cmp ip, r0
  36991. 8010f40: bf38 it cc
  36992. 8010f42: 2304 movcc r3, #4
  36993. 8010f44: 50ca str r2, [r1, r3]
  36994. 8010f46: b10a cbz r2, 8010f4c <__lshift+0xa4>
  36995. 8010f48: f108 0602 add.w r6, r8, #2
  36996. 8010f4c: 3e01 subs r6, #1
  36997. 8010f4e: 4638 mov r0, r7
  36998. 8010f50: 612e str r6, [r5, #16]
  36999. 8010f52: 4621 mov r1, r4
  37000. 8010f54: f7ff fdda bl 8010b0c <_Bfree>
  37001. 8010f58: 4628 mov r0, r5
  37002. 8010f5a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  37003. 8010f5e: f842 0f04 str.w r0, [r2, #4]!
  37004. 8010f62: 3301 adds r3, #1
  37005. 8010f64: e7c5 b.n 8010ef2 <__lshift+0x4a>
  37006. 8010f66: 3904 subs r1, #4
  37007. 8010f68: f853 2b04 ldr.w r2, [r3], #4
  37008. 8010f6c: f841 2f04 str.w r2, [r1, #4]!
  37009. 8010f70: 459c cmp ip, r3
  37010. 8010f72: d8f9 bhi.n 8010f68 <__lshift+0xc0>
  37011. 8010f74: e7ea b.n 8010f4c <__lshift+0xa4>
  37012. 8010f76: bf00 nop
  37013. 8010f78: 08011b1c .word 0x08011b1c
  37014. 8010f7c: 08011b2d .word 0x08011b2d
  37015. 08010f80 <__mcmp>:
  37016. 8010f80: 690a ldr r2, [r1, #16]
  37017. 8010f82: 4603 mov r3, r0
  37018. 8010f84: 6900 ldr r0, [r0, #16]
  37019. 8010f86: 1a80 subs r0, r0, r2
  37020. 8010f88: b530 push {r4, r5, lr}
  37021. 8010f8a: d10e bne.n 8010faa <__mcmp+0x2a>
  37022. 8010f8c: 3314 adds r3, #20
  37023. 8010f8e: 3114 adds r1, #20
  37024. 8010f90: eb03 0482 add.w r4, r3, r2, lsl #2
  37025. 8010f94: eb01 0182 add.w r1, r1, r2, lsl #2
  37026. 8010f98: f854 5d04 ldr.w r5, [r4, #-4]!
  37027. 8010f9c: f851 2d04 ldr.w r2, [r1, #-4]!
  37028. 8010fa0: 4295 cmp r5, r2
  37029. 8010fa2: d003 beq.n 8010fac <__mcmp+0x2c>
  37030. 8010fa4: d205 bcs.n 8010fb2 <__mcmp+0x32>
  37031. 8010fa6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  37032. 8010faa: bd30 pop {r4, r5, pc}
  37033. 8010fac: 42a3 cmp r3, r4
  37034. 8010fae: d3f3 bcc.n 8010f98 <__mcmp+0x18>
  37035. 8010fb0: e7fb b.n 8010faa <__mcmp+0x2a>
  37036. 8010fb2: 2001 movs r0, #1
  37037. 8010fb4: e7f9 b.n 8010faa <__mcmp+0x2a>
  37038. ...
  37039. 08010fb8 <__mdiff>:
  37040. 8010fb8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  37041. 8010fbc: 4689 mov r9, r1
  37042. 8010fbe: 4606 mov r6, r0
  37043. 8010fc0: 4611 mov r1, r2
  37044. 8010fc2: 4648 mov r0, r9
  37045. 8010fc4: 4614 mov r4, r2
  37046. 8010fc6: f7ff ffdb bl 8010f80 <__mcmp>
  37047. 8010fca: 1e05 subs r5, r0, #0
  37048. 8010fcc: d112 bne.n 8010ff4 <__mdiff+0x3c>
  37049. 8010fce: 4629 mov r1, r5
  37050. 8010fd0: 4630 mov r0, r6
  37051. 8010fd2: f7ff fd5b bl 8010a8c <_Balloc>
  37052. 8010fd6: 4602 mov r2, r0
  37053. 8010fd8: b928 cbnz r0, 8010fe6 <__mdiff+0x2e>
  37054. 8010fda: 4b3f ldr r3, [pc, #252] @ (80110d8 <__mdiff+0x120>)
  37055. 8010fdc: f240 2137 movw r1, #567 @ 0x237
  37056. 8010fe0: 483e ldr r0, [pc, #248] @ (80110dc <__mdiff+0x124>)
  37057. 8010fe2: f000 fa15 bl 8011410 <__assert_func>
  37058. 8010fe6: 2301 movs r3, #1
  37059. 8010fe8: e9c0 3504 strd r3, r5, [r0, #16]
  37060. 8010fec: 4610 mov r0, r2
  37061. 8010fee: b003 add sp, #12
  37062. 8010ff0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  37063. 8010ff4: bfbc itt lt
  37064. 8010ff6: 464b movlt r3, r9
  37065. 8010ff8: 46a1 movlt r9, r4
  37066. 8010ffa: 4630 mov r0, r6
  37067. 8010ffc: f8d9 1004 ldr.w r1, [r9, #4]
  37068. 8011000: bfba itte lt
  37069. 8011002: 461c movlt r4, r3
  37070. 8011004: 2501 movlt r5, #1
  37071. 8011006: 2500 movge r5, #0
  37072. 8011008: f7ff fd40 bl 8010a8c <_Balloc>
  37073. 801100c: 4602 mov r2, r0
  37074. 801100e: b918 cbnz r0, 8011018 <__mdiff+0x60>
  37075. 8011010: 4b31 ldr r3, [pc, #196] @ (80110d8 <__mdiff+0x120>)
  37076. 8011012: f240 2145 movw r1, #581 @ 0x245
  37077. 8011016: e7e3 b.n 8010fe0 <__mdiff+0x28>
  37078. 8011018: f8d9 7010 ldr.w r7, [r9, #16]
  37079. 801101c: 6926 ldr r6, [r4, #16]
  37080. 801101e: 60c5 str r5, [r0, #12]
  37081. 8011020: f109 0310 add.w r3, r9, #16
  37082. 8011024: f109 0514 add.w r5, r9, #20
  37083. 8011028: f104 0e14 add.w lr, r4, #20
  37084. 801102c: f100 0b14 add.w fp, r0, #20
  37085. 8011030: eb05 0887 add.w r8, r5, r7, lsl #2
  37086. 8011034: eb0e 0686 add.w r6, lr, r6, lsl #2
  37087. 8011038: 9301 str r3, [sp, #4]
  37088. 801103a: 46d9 mov r9, fp
  37089. 801103c: f04f 0c00 mov.w ip, #0
  37090. 8011040: 9b01 ldr r3, [sp, #4]
  37091. 8011042: f85e 0b04 ldr.w r0, [lr], #4
  37092. 8011046: f853 af04 ldr.w sl, [r3, #4]!
  37093. 801104a: 9301 str r3, [sp, #4]
  37094. 801104c: fa1f f38a uxth.w r3, sl
  37095. 8011050: 4619 mov r1, r3
  37096. 8011052: b283 uxth r3, r0
  37097. 8011054: 1acb subs r3, r1, r3
  37098. 8011056: 0c00 lsrs r0, r0, #16
  37099. 8011058: 4463 add r3, ip
  37100. 801105a: ebc0 401a rsb r0, r0, sl, lsr #16
  37101. 801105e: eb00 4023 add.w r0, r0, r3, asr #16
  37102. 8011062: b29b uxth r3, r3
  37103. 8011064: ea43 4300 orr.w r3, r3, r0, lsl #16
  37104. 8011068: 4576 cmp r6, lr
  37105. 801106a: f849 3b04 str.w r3, [r9], #4
  37106. 801106e: ea4f 4c20 mov.w ip, r0, asr #16
  37107. 8011072: d8e5 bhi.n 8011040 <__mdiff+0x88>
  37108. 8011074: 1b33 subs r3, r6, r4
  37109. 8011076: 3b15 subs r3, #21
  37110. 8011078: f023 0303 bic.w r3, r3, #3
  37111. 801107c: 3415 adds r4, #21
  37112. 801107e: 3304 adds r3, #4
  37113. 8011080: 42a6 cmp r6, r4
  37114. 8011082: bf38 it cc
  37115. 8011084: 2304 movcc r3, #4
  37116. 8011086: 441d add r5, r3
  37117. 8011088: 445b add r3, fp
  37118. 801108a: 461e mov r6, r3
  37119. 801108c: 462c mov r4, r5
  37120. 801108e: 4544 cmp r4, r8
  37121. 8011090: d30e bcc.n 80110b0 <__mdiff+0xf8>
  37122. 8011092: f108 0103 add.w r1, r8, #3
  37123. 8011096: 1b49 subs r1, r1, r5
  37124. 8011098: f021 0103 bic.w r1, r1, #3
  37125. 801109c: 3d03 subs r5, #3
  37126. 801109e: 45a8 cmp r8, r5
  37127. 80110a0: bf38 it cc
  37128. 80110a2: 2100 movcc r1, #0
  37129. 80110a4: 440b add r3, r1
  37130. 80110a6: f853 1d04 ldr.w r1, [r3, #-4]!
  37131. 80110aa: b191 cbz r1, 80110d2 <__mdiff+0x11a>
  37132. 80110ac: 6117 str r7, [r2, #16]
  37133. 80110ae: e79d b.n 8010fec <__mdiff+0x34>
  37134. 80110b0: f854 1b04 ldr.w r1, [r4], #4
  37135. 80110b4: 46e6 mov lr, ip
  37136. 80110b6: 0c08 lsrs r0, r1, #16
  37137. 80110b8: fa1c fc81 uxtah ip, ip, r1
  37138. 80110bc: 4471 add r1, lr
  37139. 80110be: eb00 402c add.w r0, r0, ip, asr #16
  37140. 80110c2: b289 uxth r1, r1
  37141. 80110c4: ea41 4100 orr.w r1, r1, r0, lsl #16
  37142. 80110c8: f846 1b04 str.w r1, [r6], #4
  37143. 80110cc: ea4f 4c20 mov.w ip, r0, asr #16
  37144. 80110d0: e7dd b.n 801108e <__mdiff+0xd6>
  37145. 80110d2: 3f01 subs r7, #1
  37146. 80110d4: e7e7 b.n 80110a6 <__mdiff+0xee>
  37147. 80110d6: bf00 nop
  37148. 80110d8: 08011b1c .word 0x08011b1c
  37149. 80110dc: 08011b2d .word 0x08011b2d
  37150. 080110e0 <__d2b>:
  37151. 80110e0: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
  37152. 80110e4: 460f mov r7, r1
  37153. 80110e6: 2101 movs r1, #1
  37154. 80110e8: ec59 8b10 vmov r8, r9, d0
  37155. 80110ec: 4616 mov r6, r2
  37156. 80110ee: f7ff fccd bl 8010a8c <_Balloc>
  37157. 80110f2: 4604 mov r4, r0
  37158. 80110f4: b930 cbnz r0, 8011104 <__d2b+0x24>
  37159. 80110f6: 4602 mov r2, r0
  37160. 80110f8: 4b23 ldr r3, [pc, #140] @ (8011188 <__d2b+0xa8>)
  37161. 80110fa: 4824 ldr r0, [pc, #144] @ (801118c <__d2b+0xac>)
  37162. 80110fc: f240 310f movw r1, #783 @ 0x30f
  37163. 8011100: f000 f986 bl 8011410 <__assert_func>
  37164. 8011104: f3c9 550a ubfx r5, r9, #20, #11
  37165. 8011108: f3c9 0313 ubfx r3, r9, #0, #20
  37166. 801110c: b10d cbz r5, 8011112 <__d2b+0x32>
  37167. 801110e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
  37168. 8011112: 9301 str r3, [sp, #4]
  37169. 8011114: f1b8 0300 subs.w r3, r8, #0
  37170. 8011118: d023 beq.n 8011162 <__d2b+0x82>
  37171. 801111a: 4668 mov r0, sp
  37172. 801111c: 9300 str r3, [sp, #0]
  37173. 801111e: f7ff fd7c bl 8010c1a <__lo0bits>
  37174. 8011122: e9dd 1200 ldrd r1, r2, [sp]
  37175. 8011126: b1d0 cbz r0, 801115e <__d2b+0x7e>
  37176. 8011128: f1c0 0320 rsb r3, r0, #32
  37177. 801112c: fa02 f303 lsl.w r3, r2, r3
  37178. 8011130: 430b orrs r3, r1
  37179. 8011132: 40c2 lsrs r2, r0
  37180. 8011134: 6163 str r3, [r4, #20]
  37181. 8011136: 9201 str r2, [sp, #4]
  37182. 8011138: 9b01 ldr r3, [sp, #4]
  37183. 801113a: 61a3 str r3, [r4, #24]
  37184. 801113c: 2b00 cmp r3, #0
  37185. 801113e: bf0c ite eq
  37186. 8011140: 2201 moveq r2, #1
  37187. 8011142: 2202 movne r2, #2
  37188. 8011144: 6122 str r2, [r4, #16]
  37189. 8011146: b1a5 cbz r5, 8011172 <__d2b+0x92>
  37190. 8011148: f2a5 4533 subw r5, r5, #1075 @ 0x433
  37191. 801114c: 4405 add r5, r0
  37192. 801114e: 603d str r5, [r7, #0]
  37193. 8011150: f1c0 0035 rsb r0, r0, #53 @ 0x35
  37194. 8011154: 6030 str r0, [r6, #0]
  37195. 8011156: 4620 mov r0, r4
  37196. 8011158: b003 add sp, #12
  37197. 801115a: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
  37198. 801115e: 6161 str r1, [r4, #20]
  37199. 8011160: e7ea b.n 8011138 <__d2b+0x58>
  37200. 8011162: a801 add r0, sp, #4
  37201. 8011164: f7ff fd59 bl 8010c1a <__lo0bits>
  37202. 8011168: 9b01 ldr r3, [sp, #4]
  37203. 801116a: 6163 str r3, [r4, #20]
  37204. 801116c: 3020 adds r0, #32
  37205. 801116e: 2201 movs r2, #1
  37206. 8011170: e7e8 b.n 8011144 <__d2b+0x64>
  37207. 8011172: eb04 0382 add.w r3, r4, r2, lsl #2
  37208. 8011176: f2a0 4032 subw r0, r0, #1074 @ 0x432
  37209. 801117a: 6038 str r0, [r7, #0]
  37210. 801117c: 6918 ldr r0, [r3, #16]
  37211. 801117e: f7ff fd2d bl 8010bdc <__hi0bits>
  37212. 8011182: ebc0 1042 rsb r0, r0, r2, lsl #5
  37213. 8011186: e7e5 b.n 8011154 <__d2b+0x74>
  37214. 8011188: 08011b1c .word 0x08011b1c
  37215. 801118c: 08011b2d .word 0x08011b2d
  37216. 08011190 <__sflush_r>:
  37217. 8011190: f9b1 200c ldrsh.w r2, [r1, #12]
  37218. 8011194: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  37219. 8011198: 0716 lsls r6, r2, #28
  37220. 801119a: 4605 mov r5, r0
  37221. 801119c: 460c mov r4, r1
  37222. 801119e: d454 bmi.n 801124a <__sflush_r+0xba>
  37223. 80111a0: 684b ldr r3, [r1, #4]
  37224. 80111a2: 2b00 cmp r3, #0
  37225. 80111a4: dc02 bgt.n 80111ac <__sflush_r+0x1c>
  37226. 80111a6: 6c0b ldr r3, [r1, #64] @ 0x40
  37227. 80111a8: 2b00 cmp r3, #0
  37228. 80111aa: dd48 ble.n 801123e <__sflush_r+0xae>
  37229. 80111ac: 6ae6 ldr r6, [r4, #44] @ 0x2c
  37230. 80111ae: 2e00 cmp r6, #0
  37231. 80111b0: d045 beq.n 801123e <__sflush_r+0xae>
  37232. 80111b2: 2300 movs r3, #0
  37233. 80111b4: f412 5280 ands.w r2, r2, #4096 @ 0x1000
  37234. 80111b8: 682f ldr r7, [r5, #0]
  37235. 80111ba: 6a21 ldr r1, [r4, #32]
  37236. 80111bc: 602b str r3, [r5, #0]
  37237. 80111be: d030 beq.n 8011222 <__sflush_r+0x92>
  37238. 80111c0: 6d62 ldr r2, [r4, #84] @ 0x54
  37239. 80111c2: 89a3 ldrh r3, [r4, #12]
  37240. 80111c4: 0759 lsls r1, r3, #29
  37241. 80111c6: d505 bpl.n 80111d4 <__sflush_r+0x44>
  37242. 80111c8: 6863 ldr r3, [r4, #4]
  37243. 80111ca: 1ad2 subs r2, r2, r3
  37244. 80111cc: 6b63 ldr r3, [r4, #52] @ 0x34
  37245. 80111ce: b10b cbz r3, 80111d4 <__sflush_r+0x44>
  37246. 80111d0: 6c23 ldr r3, [r4, #64] @ 0x40
  37247. 80111d2: 1ad2 subs r2, r2, r3
  37248. 80111d4: 2300 movs r3, #0
  37249. 80111d6: 6ae6 ldr r6, [r4, #44] @ 0x2c
  37250. 80111d8: 6a21 ldr r1, [r4, #32]
  37251. 80111da: 4628 mov r0, r5
  37252. 80111dc: 47b0 blx r6
  37253. 80111de: 1c43 adds r3, r0, #1
  37254. 80111e0: 89a3 ldrh r3, [r4, #12]
  37255. 80111e2: d106 bne.n 80111f2 <__sflush_r+0x62>
  37256. 80111e4: 6829 ldr r1, [r5, #0]
  37257. 80111e6: 291d cmp r1, #29
  37258. 80111e8: d82b bhi.n 8011242 <__sflush_r+0xb2>
  37259. 80111ea: 4a2a ldr r2, [pc, #168] @ (8011294 <__sflush_r+0x104>)
  37260. 80111ec: 410a asrs r2, r1
  37261. 80111ee: 07d6 lsls r6, r2, #31
  37262. 80111f0: d427 bmi.n 8011242 <__sflush_r+0xb2>
  37263. 80111f2: 2200 movs r2, #0
  37264. 80111f4: 6062 str r2, [r4, #4]
  37265. 80111f6: 04d9 lsls r1, r3, #19
  37266. 80111f8: 6922 ldr r2, [r4, #16]
  37267. 80111fa: 6022 str r2, [r4, #0]
  37268. 80111fc: d504 bpl.n 8011208 <__sflush_r+0x78>
  37269. 80111fe: 1c42 adds r2, r0, #1
  37270. 8011200: d101 bne.n 8011206 <__sflush_r+0x76>
  37271. 8011202: 682b ldr r3, [r5, #0]
  37272. 8011204: b903 cbnz r3, 8011208 <__sflush_r+0x78>
  37273. 8011206: 6560 str r0, [r4, #84] @ 0x54
  37274. 8011208: 6b61 ldr r1, [r4, #52] @ 0x34
  37275. 801120a: 602f str r7, [r5, #0]
  37276. 801120c: b1b9 cbz r1, 801123e <__sflush_r+0xae>
  37277. 801120e: f104 0344 add.w r3, r4, #68 @ 0x44
  37278. 8011212: 4299 cmp r1, r3
  37279. 8011214: d002 beq.n 801121c <__sflush_r+0x8c>
  37280. 8011216: 4628 mov r0, r5
  37281. 8011218: f7ff fb38 bl 801088c <_free_r>
  37282. 801121c: 2300 movs r3, #0
  37283. 801121e: 6363 str r3, [r4, #52] @ 0x34
  37284. 8011220: e00d b.n 801123e <__sflush_r+0xae>
  37285. 8011222: 2301 movs r3, #1
  37286. 8011224: 4628 mov r0, r5
  37287. 8011226: 47b0 blx r6
  37288. 8011228: 4602 mov r2, r0
  37289. 801122a: 1c50 adds r0, r2, #1
  37290. 801122c: d1c9 bne.n 80111c2 <__sflush_r+0x32>
  37291. 801122e: 682b ldr r3, [r5, #0]
  37292. 8011230: 2b00 cmp r3, #0
  37293. 8011232: d0c6 beq.n 80111c2 <__sflush_r+0x32>
  37294. 8011234: 2b1d cmp r3, #29
  37295. 8011236: d001 beq.n 801123c <__sflush_r+0xac>
  37296. 8011238: 2b16 cmp r3, #22
  37297. 801123a: d11e bne.n 801127a <__sflush_r+0xea>
  37298. 801123c: 602f str r7, [r5, #0]
  37299. 801123e: 2000 movs r0, #0
  37300. 8011240: e022 b.n 8011288 <__sflush_r+0xf8>
  37301. 8011242: f043 0340 orr.w r3, r3, #64 @ 0x40
  37302. 8011246: b21b sxth r3, r3
  37303. 8011248: e01b b.n 8011282 <__sflush_r+0xf2>
  37304. 801124a: 690f ldr r7, [r1, #16]
  37305. 801124c: 2f00 cmp r7, #0
  37306. 801124e: d0f6 beq.n 801123e <__sflush_r+0xae>
  37307. 8011250: 0793 lsls r3, r2, #30
  37308. 8011252: 680e ldr r6, [r1, #0]
  37309. 8011254: bf08 it eq
  37310. 8011256: 694b ldreq r3, [r1, #20]
  37311. 8011258: 600f str r7, [r1, #0]
  37312. 801125a: bf18 it ne
  37313. 801125c: 2300 movne r3, #0
  37314. 801125e: eba6 0807 sub.w r8, r6, r7
  37315. 8011262: 608b str r3, [r1, #8]
  37316. 8011264: f1b8 0f00 cmp.w r8, #0
  37317. 8011268: dde9 ble.n 801123e <__sflush_r+0xae>
  37318. 801126a: 6a21 ldr r1, [r4, #32]
  37319. 801126c: 6aa6 ldr r6, [r4, #40] @ 0x28
  37320. 801126e: 4643 mov r3, r8
  37321. 8011270: 463a mov r2, r7
  37322. 8011272: 4628 mov r0, r5
  37323. 8011274: 47b0 blx r6
  37324. 8011276: 2800 cmp r0, #0
  37325. 8011278: dc08 bgt.n 801128c <__sflush_r+0xfc>
  37326. 801127a: f9b4 300c ldrsh.w r3, [r4, #12]
  37327. 801127e: f043 0340 orr.w r3, r3, #64 @ 0x40
  37328. 8011282: 81a3 strh r3, [r4, #12]
  37329. 8011284: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  37330. 8011288: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  37331. 801128c: 4407 add r7, r0
  37332. 801128e: eba8 0800 sub.w r8, r8, r0
  37333. 8011292: e7e7 b.n 8011264 <__sflush_r+0xd4>
  37334. 8011294: dfbffffe .word 0xdfbffffe
  37335. 08011298 <_fflush_r>:
  37336. 8011298: b538 push {r3, r4, r5, lr}
  37337. 801129a: 690b ldr r3, [r1, #16]
  37338. 801129c: 4605 mov r5, r0
  37339. 801129e: 460c mov r4, r1
  37340. 80112a0: b913 cbnz r3, 80112a8 <_fflush_r+0x10>
  37341. 80112a2: 2500 movs r5, #0
  37342. 80112a4: 4628 mov r0, r5
  37343. 80112a6: bd38 pop {r3, r4, r5, pc}
  37344. 80112a8: b118 cbz r0, 80112b2 <_fflush_r+0x1a>
  37345. 80112aa: 6a03 ldr r3, [r0, #32]
  37346. 80112ac: b90b cbnz r3, 80112b2 <_fflush_r+0x1a>
  37347. 80112ae: f7fe fabf bl 800f830 <__sinit>
  37348. 80112b2: f9b4 300c ldrsh.w r3, [r4, #12]
  37349. 80112b6: 2b00 cmp r3, #0
  37350. 80112b8: d0f3 beq.n 80112a2 <_fflush_r+0xa>
  37351. 80112ba: 6e62 ldr r2, [r4, #100] @ 0x64
  37352. 80112bc: 07d0 lsls r0, r2, #31
  37353. 80112be: d404 bmi.n 80112ca <_fflush_r+0x32>
  37354. 80112c0: 0599 lsls r1, r3, #22
  37355. 80112c2: d402 bmi.n 80112ca <_fflush_r+0x32>
  37356. 80112c4: 6da0 ldr r0, [r4, #88] @ 0x58
  37357. 80112c6: f7fe fcf2 bl 800fcae <__retarget_lock_acquire_recursive>
  37358. 80112ca: 4628 mov r0, r5
  37359. 80112cc: 4621 mov r1, r4
  37360. 80112ce: f7ff ff5f bl 8011190 <__sflush_r>
  37361. 80112d2: 6e63 ldr r3, [r4, #100] @ 0x64
  37362. 80112d4: 07da lsls r2, r3, #31
  37363. 80112d6: 4605 mov r5, r0
  37364. 80112d8: d4e4 bmi.n 80112a4 <_fflush_r+0xc>
  37365. 80112da: 89a3 ldrh r3, [r4, #12]
  37366. 80112dc: 059b lsls r3, r3, #22
  37367. 80112de: d4e1 bmi.n 80112a4 <_fflush_r+0xc>
  37368. 80112e0: 6da0 ldr r0, [r4, #88] @ 0x58
  37369. 80112e2: f7fe fce5 bl 800fcb0 <__retarget_lock_release_recursive>
  37370. 80112e6: e7dd b.n 80112a4 <_fflush_r+0xc>
  37371. 080112e8 <__swhatbuf_r>:
  37372. 80112e8: b570 push {r4, r5, r6, lr}
  37373. 80112ea: 460c mov r4, r1
  37374. 80112ec: f9b1 100e ldrsh.w r1, [r1, #14]
  37375. 80112f0: 2900 cmp r1, #0
  37376. 80112f2: b096 sub sp, #88 @ 0x58
  37377. 80112f4: 4615 mov r5, r2
  37378. 80112f6: 461e mov r6, r3
  37379. 80112f8: da0d bge.n 8011316 <__swhatbuf_r+0x2e>
  37380. 80112fa: 89a3 ldrh r3, [r4, #12]
  37381. 80112fc: f013 0f80 tst.w r3, #128 @ 0x80
  37382. 8011300: f04f 0100 mov.w r1, #0
  37383. 8011304: bf14 ite ne
  37384. 8011306: 2340 movne r3, #64 @ 0x40
  37385. 8011308: f44f 6380 moveq.w r3, #1024 @ 0x400
  37386. 801130c: 2000 movs r0, #0
  37387. 801130e: 6031 str r1, [r6, #0]
  37388. 8011310: 602b str r3, [r5, #0]
  37389. 8011312: b016 add sp, #88 @ 0x58
  37390. 8011314: bd70 pop {r4, r5, r6, pc}
  37391. 8011316: 466a mov r2, sp
  37392. 8011318: f000 f848 bl 80113ac <_fstat_r>
  37393. 801131c: 2800 cmp r0, #0
  37394. 801131e: dbec blt.n 80112fa <__swhatbuf_r+0x12>
  37395. 8011320: 9901 ldr r1, [sp, #4]
  37396. 8011322: f401 4170 and.w r1, r1, #61440 @ 0xf000
  37397. 8011326: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
  37398. 801132a: 4259 negs r1, r3
  37399. 801132c: 4159 adcs r1, r3
  37400. 801132e: f44f 6380 mov.w r3, #1024 @ 0x400
  37401. 8011332: e7eb b.n 801130c <__swhatbuf_r+0x24>
  37402. 08011334 <__smakebuf_r>:
  37403. 8011334: 898b ldrh r3, [r1, #12]
  37404. 8011336: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
  37405. 8011338: 079d lsls r5, r3, #30
  37406. 801133a: 4606 mov r6, r0
  37407. 801133c: 460c mov r4, r1
  37408. 801133e: d507 bpl.n 8011350 <__smakebuf_r+0x1c>
  37409. 8011340: f104 0347 add.w r3, r4, #71 @ 0x47
  37410. 8011344: 6023 str r3, [r4, #0]
  37411. 8011346: 6123 str r3, [r4, #16]
  37412. 8011348: 2301 movs r3, #1
  37413. 801134a: 6163 str r3, [r4, #20]
  37414. 801134c: b003 add sp, #12
  37415. 801134e: bdf0 pop {r4, r5, r6, r7, pc}
  37416. 8011350: ab01 add r3, sp, #4
  37417. 8011352: 466a mov r2, sp
  37418. 8011354: f7ff ffc8 bl 80112e8 <__swhatbuf_r>
  37419. 8011358: 9f00 ldr r7, [sp, #0]
  37420. 801135a: 4605 mov r5, r0
  37421. 801135c: 4639 mov r1, r7
  37422. 801135e: 4630 mov r0, r6
  37423. 8011360: f7ff fb08 bl 8010974 <_malloc_r>
  37424. 8011364: b948 cbnz r0, 801137a <__smakebuf_r+0x46>
  37425. 8011366: f9b4 300c ldrsh.w r3, [r4, #12]
  37426. 801136a: 059a lsls r2, r3, #22
  37427. 801136c: d4ee bmi.n 801134c <__smakebuf_r+0x18>
  37428. 801136e: f023 0303 bic.w r3, r3, #3
  37429. 8011372: f043 0302 orr.w r3, r3, #2
  37430. 8011376: 81a3 strh r3, [r4, #12]
  37431. 8011378: e7e2 b.n 8011340 <__smakebuf_r+0xc>
  37432. 801137a: 89a3 ldrh r3, [r4, #12]
  37433. 801137c: 6020 str r0, [r4, #0]
  37434. 801137e: f043 0380 orr.w r3, r3, #128 @ 0x80
  37435. 8011382: 81a3 strh r3, [r4, #12]
  37436. 8011384: 9b01 ldr r3, [sp, #4]
  37437. 8011386: e9c4 0704 strd r0, r7, [r4, #16]
  37438. 801138a: b15b cbz r3, 80113a4 <__smakebuf_r+0x70>
  37439. 801138c: f9b4 100e ldrsh.w r1, [r4, #14]
  37440. 8011390: 4630 mov r0, r6
  37441. 8011392: f000 f81d bl 80113d0 <_isatty_r>
  37442. 8011396: b128 cbz r0, 80113a4 <__smakebuf_r+0x70>
  37443. 8011398: 89a3 ldrh r3, [r4, #12]
  37444. 801139a: f023 0303 bic.w r3, r3, #3
  37445. 801139e: f043 0301 orr.w r3, r3, #1
  37446. 80113a2: 81a3 strh r3, [r4, #12]
  37447. 80113a4: 89a3 ldrh r3, [r4, #12]
  37448. 80113a6: 431d orrs r5, r3
  37449. 80113a8: 81a5 strh r5, [r4, #12]
  37450. 80113aa: e7cf b.n 801134c <__smakebuf_r+0x18>
  37451. 080113ac <_fstat_r>:
  37452. 80113ac: b538 push {r3, r4, r5, lr}
  37453. 80113ae: 4d07 ldr r5, [pc, #28] @ (80113cc <_fstat_r+0x20>)
  37454. 80113b0: 2300 movs r3, #0
  37455. 80113b2: 4604 mov r4, r0
  37456. 80113b4: 4608 mov r0, r1
  37457. 80113b6: 4611 mov r1, r2
  37458. 80113b8: 602b str r3, [r5, #0]
  37459. 80113ba: f7f1 fe95 bl 80030e8 <_fstat>
  37460. 80113be: 1c43 adds r3, r0, #1
  37461. 80113c0: d102 bne.n 80113c8 <_fstat_r+0x1c>
  37462. 80113c2: 682b ldr r3, [r5, #0]
  37463. 80113c4: b103 cbz r3, 80113c8 <_fstat_r+0x1c>
  37464. 80113c6: 6023 str r3, [r4, #0]
  37465. 80113c8: bd38 pop {r3, r4, r5, pc}
  37466. 80113ca: bf00 nop
  37467. 80113cc: 240132d4 .word 0x240132d4
  37468. 080113d0 <_isatty_r>:
  37469. 80113d0: b538 push {r3, r4, r5, lr}
  37470. 80113d2: 4d06 ldr r5, [pc, #24] @ (80113ec <_isatty_r+0x1c>)
  37471. 80113d4: 2300 movs r3, #0
  37472. 80113d6: 4604 mov r4, r0
  37473. 80113d8: 4608 mov r0, r1
  37474. 80113da: 602b str r3, [r5, #0]
  37475. 80113dc: f7f1 fe8a bl 80030f4 <_isatty>
  37476. 80113e0: 1c43 adds r3, r0, #1
  37477. 80113e2: d102 bne.n 80113ea <_isatty_r+0x1a>
  37478. 80113e4: 682b ldr r3, [r5, #0]
  37479. 80113e6: b103 cbz r3, 80113ea <_isatty_r+0x1a>
  37480. 80113e8: 6023 str r3, [r4, #0]
  37481. 80113ea: bd38 pop {r3, r4, r5, pc}
  37482. 80113ec: 240132d4 .word 0x240132d4
  37483. 080113f0 <_sbrk_r>:
  37484. 80113f0: b538 push {r3, r4, r5, lr}
  37485. 80113f2: 4d06 ldr r5, [pc, #24] @ (801140c <_sbrk_r+0x1c>)
  37486. 80113f4: 2300 movs r3, #0
  37487. 80113f6: 4604 mov r4, r0
  37488. 80113f8: 4608 mov r0, r1
  37489. 80113fa: 602b str r3, [r5, #0]
  37490. 80113fc: f7f1 fe7e bl 80030fc <_sbrk>
  37491. 8011400: 1c43 adds r3, r0, #1
  37492. 8011402: d102 bne.n 801140a <_sbrk_r+0x1a>
  37493. 8011404: 682b ldr r3, [r5, #0]
  37494. 8011406: b103 cbz r3, 801140a <_sbrk_r+0x1a>
  37495. 8011408: 6023 str r3, [r4, #0]
  37496. 801140a: bd38 pop {r3, r4, r5, pc}
  37497. 801140c: 240132d4 .word 0x240132d4
  37498. 08011410 <__assert_func>:
  37499. 8011410: b51f push {r0, r1, r2, r3, r4, lr}
  37500. 8011412: 4614 mov r4, r2
  37501. 8011414: 461a mov r2, r3
  37502. 8011416: 4b09 ldr r3, [pc, #36] @ (801143c <__assert_func+0x2c>)
  37503. 8011418: 681b ldr r3, [r3, #0]
  37504. 801141a: 4605 mov r5, r0
  37505. 801141c: 68d8 ldr r0, [r3, #12]
  37506. 801141e: b954 cbnz r4, 8011436 <__assert_func+0x26>
  37507. 8011420: 4b07 ldr r3, [pc, #28] @ (8011440 <__assert_func+0x30>)
  37508. 8011422: 461c mov r4, r3
  37509. 8011424: e9cd 3401 strd r3, r4, [sp, #4]
  37510. 8011428: 9100 str r1, [sp, #0]
  37511. 801142a: 462b mov r3, r5
  37512. 801142c: 4905 ldr r1, [pc, #20] @ (8011444 <__assert_func+0x34>)
  37513. 801142e: f000 f841 bl 80114b4 <fiprintf>
  37514. 8011432: f000 f851 bl 80114d8 <abort>
  37515. 8011436: 4b04 ldr r3, [pc, #16] @ (8011448 <__assert_func+0x38>)
  37516. 8011438: e7f4 b.n 8011424 <__assert_func+0x14>
  37517. 801143a: bf00 nop
  37518. 801143c: 24000054 .word 0x24000054
  37519. 8011440: 08011ccd .word 0x08011ccd
  37520. 8011444: 08011c9f .word 0x08011c9f
  37521. 8011448: 08011c92 .word 0x08011c92
  37522. 0801144c <_calloc_r>:
  37523. 801144c: b570 push {r4, r5, r6, lr}
  37524. 801144e: fba1 5402 umull r5, r4, r1, r2
  37525. 8011452: b93c cbnz r4, 8011464 <_calloc_r+0x18>
  37526. 8011454: 4629 mov r1, r5
  37527. 8011456: f7ff fa8d bl 8010974 <_malloc_r>
  37528. 801145a: 4606 mov r6, r0
  37529. 801145c: b928 cbnz r0, 801146a <_calloc_r+0x1e>
  37530. 801145e: 2600 movs r6, #0
  37531. 8011460: 4630 mov r0, r6
  37532. 8011462: bd70 pop {r4, r5, r6, pc}
  37533. 8011464: 220c movs r2, #12
  37534. 8011466: 6002 str r2, [r0, #0]
  37535. 8011468: e7f9 b.n 801145e <_calloc_r+0x12>
  37536. 801146a: 462a mov r2, r5
  37537. 801146c: 4621 mov r1, r4
  37538. 801146e: f7fe fb4b bl 800fb08 <memset>
  37539. 8011472: e7f5 b.n 8011460 <_calloc_r+0x14>
  37540. 08011474 <__ascii_mbtowc>:
  37541. 8011474: b082 sub sp, #8
  37542. 8011476: b901 cbnz r1, 801147a <__ascii_mbtowc+0x6>
  37543. 8011478: a901 add r1, sp, #4
  37544. 801147a: b142 cbz r2, 801148e <__ascii_mbtowc+0x1a>
  37545. 801147c: b14b cbz r3, 8011492 <__ascii_mbtowc+0x1e>
  37546. 801147e: 7813 ldrb r3, [r2, #0]
  37547. 8011480: 600b str r3, [r1, #0]
  37548. 8011482: 7812 ldrb r2, [r2, #0]
  37549. 8011484: 1e10 subs r0, r2, #0
  37550. 8011486: bf18 it ne
  37551. 8011488: 2001 movne r0, #1
  37552. 801148a: b002 add sp, #8
  37553. 801148c: 4770 bx lr
  37554. 801148e: 4610 mov r0, r2
  37555. 8011490: e7fb b.n 801148a <__ascii_mbtowc+0x16>
  37556. 8011492: f06f 0001 mvn.w r0, #1
  37557. 8011496: e7f8 b.n 801148a <__ascii_mbtowc+0x16>
  37558. 08011498 <__ascii_wctomb>:
  37559. 8011498: 4603 mov r3, r0
  37560. 801149a: 4608 mov r0, r1
  37561. 801149c: b141 cbz r1, 80114b0 <__ascii_wctomb+0x18>
  37562. 801149e: 2aff cmp r2, #255 @ 0xff
  37563. 80114a0: d904 bls.n 80114ac <__ascii_wctomb+0x14>
  37564. 80114a2: 228a movs r2, #138 @ 0x8a
  37565. 80114a4: 601a str r2, [r3, #0]
  37566. 80114a6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  37567. 80114aa: 4770 bx lr
  37568. 80114ac: 700a strb r2, [r1, #0]
  37569. 80114ae: 2001 movs r0, #1
  37570. 80114b0: 4770 bx lr
  37571. ...
  37572. 080114b4 <fiprintf>:
  37573. 80114b4: b40e push {r1, r2, r3}
  37574. 80114b6: b503 push {r0, r1, lr}
  37575. 80114b8: 4601 mov r1, r0
  37576. 80114ba: ab03 add r3, sp, #12
  37577. 80114bc: 4805 ldr r0, [pc, #20] @ (80114d4 <fiprintf+0x20>)
  37578. 80114be: f853 2b04 ldr.w r2, [r3], #4
  37579. 80114c2: 6800 ldr r0, [r0, #0]
  37580. 80114c4: 9301 str r3, [sp, #4]
  37581. 80114c6: f000 f837 bl 8011538 <_vfiprintf_r>
  37582. 80114ca: b002 add sp, #8
  37583. 80114cc: f85d eb04 ldr.w lr, [sp], #4
  37584. 80114d0: b003 add sp, #12
  37585. 80114d2: 4770 bx lr
  37586. 80114d4: 24000054 .word 0x24000054
  37587. 080114d8 <abort>:
  37588. 80114d8: b508 push {r3, lr}
  37589. 80114da: 2006 movs r0, #6
  37590. 80114dc: f000 f96c bl 80117b8 <raise>
  37591. 80114e0: 2001 movs r0, #1
  37592. 80114e2: f7f1 fddb bl 800309c <_exit>
  37593. 080114e6 <__sfputc_r>:
  37594. 80114e6: 6893 ldr r3, [r2, #8]
  37595. 80114e8: 3b01 subs r3, #1
  37596. 80114ea: 2b00 cmp r3, #0
  37597. 80114ec: b410 push {r4}
  37598. 80114ee: 6093 str r3, [r2, #8]
  37599. 80114f0: da08 bge.n 8011504 <__sfputc_r+0x1e>
  37600. 80114f2: 6994 ldr r4, [r2, #24]
  37601. 80114f4: 42a3 cmp r3, r4
  37602. 80114f6: db01 blt.n 80114fc <__sfputc_r+0x16>
  37603. 80114f8: 290a cmp r1, #10
  37604. 80114fa: d103 bne.n 8011504 <__sfputc_r+0x1e>
  37605. 80114fc: f85d 4b04 ldr.w r4, [sp], #4
  37606. 8011500: f7fe ba6d b.w 800f9de <__swbuf_r>
  37607. 8011504: 6813 ldr r3, [r2, #0]
  37608. 8011506: 1c58 adds r0, r3, #1
  37609. 8011508: 6010 str r0, [r2, #0]
  37610. 801150a: 7019 strb r1, [r3, #0]
  37611. 801150c: 4608 mov r0, r1
  37612. 801150e: f85d 4b04 ldr.w r4, [sp], #4
  37613. 8011512: 4770 bx lr
  37614. 08011514 <__sfputs_r>:
  37615. 8011514: b5f8 push {r3, r4, r5, r6, r7, lr}
  37616. 8011516: 4606 mov r6, r0
  37617. 8011518: 460f mov r7, r1
  37618. 801151a: 4614 mov r4, r2
  37619. 801151c: 18d5 adds r5, r2, r3
  37620. 801151e: 42ac cmp r4, r5
  37621. 8011520: d101 bne.n 8011526 <__sfputs_r+0x12>
  37622. 8011522: 2000 movs r0, #0
  37623. 8011524: e007 b.n 8011536 <__sfputs_r+0x22>
  37624. 8011526: f814 1b01 ldrb.w r1, [r4], #1
  37625. 801152a: 463a mov r2, r7
  37626. 801152c: 4630 mov r0, r6
  37627. 801152e: f7ff ffda bl 80114e6 <__sfputc_r>
  37628. 8011532: 1c43 adds r3, r0, #1
  37629. 8011534: d1f3 bne.n 801151e <__sfputs_r+0xa>
  37630. 8011536: bdf8 pop {r3, r4, r5, r6, r7, pc}
  37631. 08011538 <_vfiprintf_r>:
  37632. 8011538: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  37633. 801153c: 460d mov r5, r1
  37634. 801153e: b09d sub sp, #116 @ 0x74
  37635. 8011540: 4614 mov r4, r2
  37636. 8011542: 4698 mov r8, r3
  37637. 8011544: 4606 mov r6, r0
  37638. 8011546: b118 cbz r0, 8011550 <_vfiprintf_r+0x18>
  37639. 8011548: 6a03 ldr r3, [r0, #32]
  37640. 801154a: b90b cbnz r3, 8011550 <_vfiprintf_r+0x18>
  37641. 801154c: f7fe f970 bl 800f830 <__sinit>
  37642. 8011550: 6e6b ldr r3, [r5, #100] @ 0x64
  37643. 8011552: 07d9 lsls r1, r3, #31
  37644. 8011554: d405 bmi.n 8011562 <_vfiprintf_r+0x2a>
  37645. 8011556: 89ab ldrh r3, [r5, #12]
  37646. 8011558: 059a lsls r2, r3, #22
  37647. 801155a: d402 bmi.n 8011562 <_vfiprintf_r+0x2a>
  37648. 801155c: 6da8 ldr r0, [r5, #88] @ 0x58
  37649. 801155e: f7fe fba6 bl 800fcae <__retarget_lock_acquire_recursive>
  37650. 8011562: 89ab ldrh r3, [r5, #12]
  37651. 8011564: 071b lsls r3, r3, #28
  37652. 8011566: d501 bpl.n 801156c <_vfiprintf_r+0x34>
  37653. 8011568: 692b ldr r3, [r5, #16]
  37654. 801156a: b99b cbnz r3, 8011594 <_vfiprintf_r+0x5c>
  37655. 801156c: 4629 mov r1, r5
  37656. 801156e: 4630 mov r0, r6
  37657. 8011570: f7fe fa74 bl 800fa5c <__swsetup_r>
  37658. 8011574: b170 cbz r0, 8011594 <_vfiprintf_r+0x5c>
  37659. 8011576: 6e6b ldr r3, [r5, #100] @ 0x64
  37660. 8011578: 07dc lsls r4, r3, #31
  37661. 801157a: d504 bpl.n 8011586 <_vfiprintf_r+0x4e>
  37662. 801157c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  37663. 8011580: b01d add sp, #116 @ 0x74
  37664. 8011582: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  37665. 8011586: 89ab ldrh r3, [r5, #12]
  37666. 8011588: 0598 lsls r0, r3, #22
  37667. 801158a: d4f7 bmi.n 801157c <_vfiprintf_r+0x44>
  37668. 801158c: 6da8 ldr r0, [r5, #88] @ 0x58
  37669. 801158e: f7fe fb8f bl 800fcb0 <__retarget_lock_release_recursive>
  37670. 8011592: e7f3 b.n 801157c <_vfiprintf_r+0x44>
  37671. 8011594: 2300 movs r3, #0
  37672. 8011596: 9309 str r3, [sp, #36] @ 0x24
  37673. 8011598: 2320 movs r3, #32
  37674. 801159a: f88d 3029 strb.w r3, [sp, #41] @ 0x29
  37675. 801159e: f8cd 800c str.w r8, [sp, #12]
  37676. 80115a2: 2330 movs r3, #48 @ 0x30
  37677. 80115a4: f8df 81ac ldr.w r8, [pc, #428] @ 8011754 <_vfiprintf_r+0x21c>
  37678. 80115a8: f88d 302a strb.w r3, [sp, #42] @ 0x2a
  37679. 80115ac: f04f 0901 mov.w r9, #1
  37680. 80115b0: 4623 mov r3, r4
  37681. 80115b2: 469a mov sl, r3
  37682. 80115b4: f813 2b01 ldrb.w r2, [r3], #1
  37683. 80115b8: b10a cbz r2, 80115be <_vfiprintf_r+0x86>
  37684. 80115ba: 2a25 cmp r2, #37 @ 0x25
  37685. 80115bc: d1f9 bne.n 80115b2 <_vfiprintf_r+0x7a>
  37686. 80115be: ebba 0b04 subs.w fp, sl, r4
  37687. 80115c2: d00b beq.n 80115dc <_vfiprintf_r+0xa4>
  37688. 80115c4: 465b mov r3, fp
  37689. 80115c6: 4622 mov r2, r4
  37690. 80115c8: 4629 mov r1, r5
  37691. 80115ca: 4630 mov r0, r6
  37692. 80115cc: f7ff ffa2 bl 8011514 <__sfputs_r>
  37693. 80115d0: 3001 adds r0, #1
  37694. 80115d2: f000 80a7 beq.w 8011724 <_vfiprintf_r+0x1ec>
  37695. 80115d6: 9a09 ldr r2, [sp, #36] @ 0x24
  37696. 80115d8: 445a add r2, fp
  37697. 80115da: 9209 str r2, [sp, #36] @ 0x24
  37698. 80115dc: f89a 3000 ldrb.w r3, [sl]
  37699. 80115e0: 2b00 cmp r3, #0
  37700. 80115e2: f000 809f beq.w 8011724 <_vfiprintf_r+0x1ec>
  37701. 80115e6: 2300 movs r3, #0
  37702. 80115e8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
  37703. 80115ec: e9cd 2305 strd r2, r3, [sp, #20]
  37704. 80115f0: f10a 0a01 add.w sl, sl, #1
  37705. 80115f4: 9304 str r3, [sp, #16]
  37706. 80115f6: 9307 str r3, [sp, #28]
  37707. 80115f8: f88d 3053 strb.w r3, [sp, #83] @ 0x53
  37708. 80115fc: 931a str r3, [sp, #104] @ 0x68
  37709. 80115fe: 4654 mov r4, sl
  37710. 8011600: 2205 movs r2, #5
  37711. 8011602: f814 1b01 ldrb.w r1, [r4], #1
  37712. 8011606: 4853 ldr r0, [pc, #332] @ (8011754 <_vfiprintf_r+0x21c>)
  37713. 8011608: f7ee fe6a bl 80002e0 <memchr>
  37714. 801160c: 9a04 ldr r2, [sp, #16]
  37715. 801160e: b9d8 cbnz r0, 8011648 <_vfiprintf_r+0x110>
  37716. 8011610: 06d1 lsls r1, r2, #27
  37717. 8011612: bf44 itt mi
  37718. 8011614: 2320 movmi r3, #32
  37719. 8011616: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
  37720. 801161a: 0713 lsls r3, r2, #28
  37721. 801161c: bf44 itt mi
  37722. 801161e: 232b movmi r3, #43 @ 0x2b
  37723. 8011620: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
  37724. 8011624: f89a 3000 ldrb.w r3, [sl]
  37725. 8011628: 2b2a cmp r3, #42 @ 0x2a
  37726. 801162a: d015 beq.n 8011658 <_vfiprintf_r+0x120>
  37727. 801162c: 9a07 ldr r2, [sp, #28]
  37728. 801162e: 4654 mov r4, sl
  37729. 8011630: 2000 movs r0, #0
  37730. 8011632: f04f 0c0a mov.w ip, #10
  37731. 8011636: 4621 mov r1, r4
  37732. 8011638: f811 3b01 ldrb.w r3, [r1], #1
  37733. 801163c: 3b30 subs r3, #48 @ 0x30
  37734. 801163e: 2b09 cmp r3, #9
  37735. 8011640: d94b bls.n 80116da <_vfiprintf_r+0x1a2>
  37736. 8011642: b1b0 cbz r0, 8011672 <_vfiprintf_r+0x13a>
  37737. 8011644: 9207 str r2, [sp, #28]
  37738. 8011646: e014 b.n 8011672 <_vfiprintf_r+0x13a>
  37739. 8011648: eba0 0308 sub.w r3, r0, r8
  37740. 801164c: fa09 f303 lsl.w r3, r9, r3
  37741. 8011650: 4313 orrs r3, r2
  37742. 8011652: 9304 str r3, [sp, #16]
  37743. 8011654: 46a2 mov sl, r4
  37744. 8011656: e7d2 b.n 80115fe <_vfiprintf_r+0xc6>
  37745. 8011658: 9b03 ldr r3, [sp, #12]
  37746. 801165a: 1d19 adds r1, r3, #4
  37747. 801165c: 681b ldr r3, [r3, #0]
  37748. 801165e: 9103 str r1, [sp, #12]
  37749. 8011660: 2b00 cmp r3, #0
  37750. 8011662: bfbb ittet lt
  37751. 8011664: 425b neglt r3, r3
  37752. 8011666: f042 0202 orrlt.w r2, r2, #2
  37753. 801166a: 9307 strge r3, [sp, #28]
  37754. 801166c: 9307 strlt r3, [sp, #28]
  37755. 801166e: bfb8 it lt
  37756. 8011670: 9204 strlt r2, [sp, #16]
  37757. 8011672: 7823 ldrb r3, [r4, #0]
  37758. 8011674: 2b2e cmp r3, #46 @ 0x2e
  37759. 8011676: d10a bne.n 801168e <_vfiprintf_r+0x156>
  37760. 8011678: 7863 ldrb r3, [r4, #1]
  37761. 801167a: 2b2a cmp r3, #42 @ 0x2a
  37762. 801167c: d132 bne.n 80116e4 <_vfiprintf_r+0x1ac>
  37763. 801167e: 9b03 ldr r3, [sp, #12]
  37764. 8011680: 1d1a adds r2, r3, #4
  37765. 8011682: 681b ldr r3, [r3, #0]
  37766. 8011684: 9203 str r2, [sp, #12]
  37767. 8011686: ea43 73e3 orr.w r3, r3, r3, asr #31
  37768. 801168a: 3402 adds r4, #2
  37769. 801168c: 9305 str r3, [sp, #20]
  37770. 801168e: f8df a0d4 ldr.w sl, [pc, #212] @ 8011764 <_vfiprintf_r+0x22c>
  37771. 8011692: 7821 ldrb r1, [r4, #0]
  37772. 8011694: 2203 movs r2, #3
  37773. 8011696: 4650 mov r0, sl
  37774. 8011698: f7ee fe22 bl 80002e0 <memchr>
  37775. 801169c: b138 cbz r0, 80116ae <_vfiprintf_r+0x176>
  37776. 801169e: 9b04 ldr r3, [sp, #16]
  37777. 80116a0: eba0 000a sub.w r0, r0, sl
  37778. 80116a4: 2240 movs r2, #64 @ 0x40
  37779. 80116a6: 4082 lsls r2, r0
  37780. 80116a8: 4313 orrs r3, r2
  37781. 80116aa: 3401 adds r4, #1
  37782. 80116ac: 9304 str r3, [sp, #16]
  37783. 80116ae: f814 1b01 ldrb.w r1, [r4], #1
  37784. 80116b2: 4829 ldr r0, [pc, #164] @ (8011758 <_vfiprintf_r+0x220>)
  37785. 80116b4: f88d 1028 strb.w r1, [sp, #40] @ 0x28
  37786. 80116b8: 2206 movs r2, #6
  37787. 80116ba: f7ee fe11 bl 80002e0 <memchr>
  37788. 80116be: 2800 cmp r0, #0
  37789. 80116c0: d03f beq.n 8011742 <_vfiprintf_r+0x20a>
  37790. 80116c2: 4b26 ldr r3, [pc, #152] @ (801175c <_vfiprintf_r+0x224>)
  37791. 80116c4: bb1b cbnz r3, 801170e <_vfiprintf_r+0x1d6>
  37792. 80116c6: 9b03 ldr r3, [sp, #12]
  37793. 80116c8: 3307 adds r3, #7
  37794. 80116ca: f023 0307 bic.w r3, r3, #7
  37795. 80116ce: 3308 adds r3, #8
  37796. 80116d0: 9303 str r3, [sp, #12]
  37797. 80116d2: 9b09 ldr r3, [sp, #36] @ 0x24
  37798. 80116d4: 443b add r3, r7
  37799. 80116d6: 9309 str r3, [sp, #36] @ 0x24
  37800. 80116d8: e76a b.n 80115b0 <_vfiprintf_r+0x78>
  37801. 80116da: fb0c 3202 mla r2, ip, r2, r3
  37802. 80116de: 460c mov r4, r1
  37803. 80116e0: 2001 movs r0, #1
  37804. 80116e2: e7a8 b.n 8011636 <_vfiprintf_r+0xfe>
  37805. 80116e4: 2300 movs r3, #0
  37806. 80116e6: 3401 adds r4, #1
  37807. 80116e8: 9305 str r3, [sp, #20]
  37808. 80116ea: 4619 mov r1, r3
  37809. 80116ec: f04f 0c0a mov.w ip, #10
  37810. 80116f0: 4620 mov r0, r4
  37811. 80116f2: f810 2b01 ldrb.w r2, [r0], #1
  37812. 80116f6: 3a30 subs r2, #48 @ 0x30
  37813. 80116f8: 2a09 cmp r2, #9
  37814. 80116fa: d903 bls.n 8011704 <_vfiprintf_r+0x1cc>
  37815. 80116fc: 2b00 cmp r3, #0
  37816. 80116fe: d0c6 beq.n 801168e <_vfiprintf_r+0x156>
  37817. 8011700: 9105 str r1, [sp, #20]
  37818. 8011702: e7c4 b.n 801168e <_vfiprintf_r+0x156>
  37819. 8011704: fb0c 2101 mla r1, ip, r1, r2
  37820. 8011708: 4604 mov r4, r0
  37821. 801170a: 2301 movs r3, #1
  37822. 801170c: e7f0 b.n 80116f0 <_vfiprintf_r+0x1b8>
  37823. 801170e: ab03 add r3, sp, #12
  37824. 8011710: 9300 str r3, [sp, #0]
  37825. 8011712: 462a mov r2, r5
  37826. 8011714: 4b12 ldr r3, [pc, #72] @ (8011760 <_vfiprintf_r+0x228>)
  37827. 8011716: a904 add r1, sp, #16
  37828. 8011718: 4630 mov r0, r6
  37829. 801171a: f7fd fc55 bl 800efc8 <_printf_float>
  37830. 801171e: 4607 mov r7, r0
  37831. 8011720: 1c78 adds r0, r7, #1
  37832. 8011722: d1d6 bne.n 80116d2 <_vfiprintf_r+0x19a>
  37833. 8011724: 6e6b ldr r3, [r5, #100] @ 0x64
  37834. 8011726: 07d9 lsls r1, r3, #31
  37835. 8011728: d405 bmi.n 8011736 <_vfiprintf_r+0x1fe>
  37836. 801172a: 89ab ldrh r3, [r5, #12]
  37837. 801172c: 059a lsls r2, r3, #22
  37838. 801172e: d402 bmi.n 8011736 <_vfiprintf_r+0x1fe>
  37839. 8011730: 6da8 ldr r0, [r5, #88] @ 0x58
  37840. 8011732: f7fe fabd bl 800fcb0 <__retarget_lock_release_recursive>
  37841. 8011736: 89ab ldrh r3, [r5, #12]
  37842. 8011738: 065b lsls r3, r3, #25
  37843. 801173a: f53f af1f bmi.w 801157c <_vfiprintf_r+0x44>
  37844. 801173e: 9809 ldr r0, [sp, #36] @ 0x24
  37845. 8011740: e71e b.n 8011580 <_vfiprintf_r+0x48>
  37846. 8011742: ab03 add r3, sp, #12
  37847. 8011744: 9300 str r3, [sp, #0]
  37848. 8011746: 462a mov r2, r5
  37849. 8011748: 4b05 ldr r3, [pc, #20] @ (8011760 <_vfiprintf_r+0x228>)
  37850. 801174a: a904 add r1, sp, #16
  37851. 801174c: 4630 mov r0, r6
  37852. 801174e: f7fd fec3 bl 800f4d8 <_printf_i>
  37853. 8011752: e7e4 b.n 801171e <_vfiprintf_r+0x1e6>
  37854. 8011754: 08011dcf .word 0x08011dcf
  37855. 8011758: 08011dd9 .word 0x08011dd9
  37856. 801175c: 0800efc9 .word 0x0800efc9
  37857. 8011760: 08011515 .word 0x08011515
  37858. 8011764: 08011dd5 .word 0x08011dd5
  37859. 08011768 <_raise_r>:
  37860. 8011768: 291f cmp r1, #31
  37861. 801176a: b538 push {r3, r4, r5, lr}
  37862. 801176c: 4605 mov r5, r0
  37863. 801176e: 460c mov r4, r1
  37864. 8011770: d904 bls.n 801177c <_raise_r+0x14>
  37865. 8011772: 2316 movs r3, #22
  37866. 8011774: 6003 str r3, [r0, #0]
  37867. 8011776: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
  37868. 801177a: bd38 pop {r3, r4, r5, pc}
  37869. 801177c: 6bc2 ldr r2, [r0, #60] @ 0x3c
  37870. 801177e: b112 cbz r2, 8011786 <_raise_r+0x1e>
  37871. 8011780: f852 3021 ldr.w r3, [r2, r1, lsl #2]
  37872. 8011784: b94b cbnz r3, 801179a <_raise_r+0x32>
  37873. 8011786: 4628 mov r0, r5
  37874. 8011788: f000 f830 bl 80117ec <_getpid_r>
  37875. 801178c: 4622 mov r2, r4
  37876. 801178e: 4601 mov r1, r0
  37877. 8011790: 4628 mov r0, r5
  37878. 8011792: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
  37879. 8011796: f000 b817 b.w 80117c8 <_kill_r>
  37880. 801179a: 2b01 cmp r3, #1
  37881. 801179c: d00a beq.n 80117b4 <_raise_r+0x4c>
  37882. 801179e: 1c59 adds r1, r3, #1
  37883. 80117a0: d103 bne.n 80117aa <_raise_r+0x42>
  37884. 80117a2: 2316 movs r3, #22
  37885. 80117a4: 6003 str r3, [r0, #0]
  37886. 80117a6: 2001 movs r0, #1
  37887. 80117a8: e7e7 b.n 801177a <_raise_r+0x12>
  37888. 80117aa: 2100 movs r1, #0
  37889. 80117ac: f842 1024 str.w r1, [r2, r4, lsl #2]
  37890. 80117b0: 4620 mov r0, r4
  37891. 80117b2: 4798 blx r3
  37892. 80117b4: 2000 movs r0, #0
  37893. 80117b6: e7e0 b.n 801177a <_raise_r+0x12>
  37894. 080117b8 <raise>:
  37895. 80117b8: 4b02 ldr r3, [pc, #8] @ (80117c4 <raise+0xc>)
  37896. 80117ba: 4601 mov r1, r0
  37897. 80117bc: 6818 ldr r0, [r3, #0]
  37898. 80117be: f7ff bfd3 b.w 8011768 <_raise_r>
  37899. 80117c2: bf00 nop
  37900. 80117c4: 24000054 .word 0x24000054
  37901. 080117c8 <_kill_r>:
  37902. 80117c8: b538 push {r3, r4, r5, lr}
  37903. 80117ca: 4d07 ldr r5, [pc, #28] @ (80117e8 <_kill_r+0x20>)
  37904. 80117cc: 2300 movs r3, #0
  37905. 80117ce: 4604 mov r4, r0
  37906. 80117d0: 4608 mov r0, r1
  37907. 80117d2: 4611 mov r1, r2
  37908. 80117d4: 602b str r3, [r5, #0]
  37909. 80117d6: f7f1 fc57 bl 8003088 <_kill>
  37910. 80117da: 1c43 adds r3, r0, #1
  37911. 80117dc: d102 bne.n 80117e4 <_kill_r+0x1c>
  37912. 80117de: 682b ldr r3, [r5, #0]
  37913. 80117e0: b103 cbz r3, 80117e4 <_kill_r+0x1c>
  37914. 80117e2: 6023 str r3, [r4, #0]
  37915. 80117e4: bd38 pop {r3, r4, r5, pc}
  37916. 80117e6: bf00 nop
  37917. 80117e8: 240132d4 .word 0x240132d4
  37918. 080117ec <_getpid_r>:
  37919. 80117ec: f7f1 bc4a b.w 8003084 <_getpid>
  37920. 080117f0 <fmodf>:
  37921. 80117f0: b508 push {r3, lr}
  37922. 80117f2: ed2d 8b02 vpush {d8}
  37923. 80117f6: eef0 8a40 vmov.f32 s17, s0
  37924. 80117fa: eeb0 8a60 vmov.f32 s16, s1
  37925. 80117fe: f000 f817 bl 8011830 <__ieee754_fmodf>
  37926. 8011802: eef4 8a48 vcmp.f32 s17, s16
  37927. 8011806: eef1 fa10 vmrs APSR_nzcv, fpscr
  37928. 801180a: d60c bvs.n 8011826 <fmodf+0x36>
  37929. 801180c: eddf 8a07 vldr s17, [pc, #28] @ 801182c <fmodf+0x3c>
  37930. 8011810: eeb4 8a68 vcmp.f32 s16, s17
  37931. 8011814: eef1 fa10 vmrs APSR_nzcv, fpscr
  37932. 8011818: d105 bne.n 8011826 <fmodf+0x36>
  37933. 801181a: f7fe fa1d bl 800fc58 <__errno>
  37934. 801181e: ee88 0aa8 vdiv.f32 s0, s17, s17
  37935. 8011822: 2321 movs r3, #33 @ 0x21
  37936. 8011824: 6003 str r3, [r0, #0]
  37937. 8011826: ecbd 8b02 vpop {d8}
  37938. 801182a: bd08 pop {r3, pc}
  37939. 801182c: 00000000 .word 0x00000000
  37940. 08011830 <__ieee754_fmodf>:
  37941. 8011830: b5f0 push {r4, r5, r6, r7, lr}
  37942. 8011832: ee10 5a90 vmov r5, s1
  37943. 8011836: f025 4000 bic.w r0, r5, #2147483648 @ 0x80000000
  37944. 801183a: 1e43 subs r3, r0, #1
  37945. 801183c: f1b3 4fff cmp.w r3, #2139095040 @ 0x7f800000
  37946. 8011840: d206 bcs.n 8011850 <__ieee754_fmodf+0x20>
  37947. 8011842: ee10 3a10 vmov r3, s0
  37948. 8011846: f023 4600 bic.w r6, r3, #2147483648 @ 0x80000000
  37949. 801184a: f1b6 4fff cmp.w r6, #2139095040 @ 0x7f800000
  37950. 801184e: d304 bcc.n 801185a <__ieee754_fmodf+0x2a>
  37951. 8011850: ee60 0a20 vmul.f32 s1, s0, s1
  37952. 8011854: ee80 0aa0 vdiv.f32 s0, s1, s1
  37953. 8011858: bdf0 pop {r4, r5, r6, r7, pc}
  37954. 801185a: 4286 cmp r6, r0
  37955. 801185c: dbfc blt.n 8011858 <__ieee754_fmodf+0x28>
  37956. 801185e: f003 4400 and.w r4, r3, #2147483648 @ 0x80000000
  37957. 8011862: d105 bne.n 8011870 <__ieee754_fmodf+0x40>
  37958. 8011864: 4b32 ldr r3, [pc, #200] @ (8011930 <__ieee754_fmodf+0x100>)
  37959. 8011866: eb03 7354 add.w r3, r3, r4, lsr #29
  37960. 801186a: ed93 0a00 vldr s0, [r3]
  37961. 801186e: e7f3 b.n 8011858 <__ieee754_fmodf+0x28>
  37962. 8011870: f013 4fff tst.w r3, #2139095040 @ 0x7f800000
  37963. 8011874: d140 bne.n 80118f8 <__ieee754_fmodf+0xc8>
  37964. 8011876: 0232 lsls r2, r6, #8
  37965. 8011878: f06f 017d mvn.w r1, #125 @ 0x7d
  37966. 801187c: 2a00 cmp r2, #0
  37967. 801187e: dc38 bgt.n 80118f2 <__ieee754_fmodf+0xc2>
  37968. 8011880: f015 4fff tst.w r5, #2139095040 @ 0x7f800000
  37969. 8011884: d13e bne.n 8011904 <__ieee754_fmodf+0xd4>
  37970. 8011886: 0207 lsls r7, r0, #8
  37971. 8011888: f06f 027d mvn.w r2, #125 @ 0x7d
  37972. 801188c: 2f00 cmp r7, #0
  37973. 801188e: da36 bge.n 80118fe <__ieee754_fmodf+0xce>
  37974. 8011890: f111 0f7e cmn.w r1, #126 @ 0x7e
  37975. 8011894: bfb9 ittee lt
  37976. 8011896: f06f 037d mvnlt.w r3, #125 @ 0x7d
  37977. 801189a: 1a5b sublt r3, r3, r1
  37978. 801189c: f3c3 0316 ubfxge r3, r3, #0, #23
  37979. 80118a0: f443 0300 orrge.w r3, r3, #8388608 @ 0x800000
  37980. 80118a4: bfb8 it lt
  37981. 80118a6: fa06 f303 lsllt.w r3, r6, r3
  37982. 80118aa: f112 0f7e cmn.w r2, #126 @ 0x7e
  37983. 80118ae: bfb5 itete lt
  37984. 80118b0: f06f 057d mvnlt.w r5, #125 @ 0x7d
  37985. 80118b4: f3c5 0516 ubfxge r5, r5, #0, #23
  37986. 80118b8: 1aad sublt r5, r5, r2
  37987. 80118ba: f445 0000 orrge.w r0, r5, #8388608 @ 0x800000
  37988. 80118be: bfb8 it lt
  37989. 80118c0: 40a8 lsllt r0, r5
  37990. 80118c2: 1a89 subs r1, r1, r2
  37991. 80118c4: 1a1d subs r5, r3, r0
  37992. 80118c6: bb01 cbnz r1, 801190a <__ieee754_fmodf+0xda>
  37993. 80118c8: ea13 0325 ands.w r3, r3, r5, asr #32
  37994. 80118cc: bf38 it cc
  37995. 80118ce: 462b movcc r3, r5
  37996. 80118d0: 2b00 cmp r3, #0
  37997. 80118d2: d0c7 beq.n 8011864 <__ieee754_fmodf+0x34>
  37998. 80118d4: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
  37999. 80118d8: db1f blt.n 801191a <__ieee754_fmodf+0xea>
  38000. 80118da: f112 0f7e cmn.w r2, #126 @ 0x7e
  38001. 80118de: db1f blt.n 8011920 <__ieee754_fmodf+0xf0>
  38002. 80118e0: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000
  38003. 80118e4: 327f adds r2, #127 @ 0x7f
  38004. 80118e6: 4323 orrs r3, r4
  38005. 80118e8: ea43 53c2 orr.w r3, r3, r2, lsl #23
  38006. 80118ec: ee00 3a10 vmov s0, r3
  38007. 80118f0: e7b2 b.n 8011858 <__ieee754_fmodf+0x28>
  38008. 80118f2: 3901 subs r1, #1
  38009. 80118f4: 0052 lsls r2, r2, #1
  38010. 80118f6: e7c1 b.n 801187c <__ieee754_fmodf+0x4c>
  38011. 80118f8: 15f1 asrs r1, r6, #23
  38012. 80118fa: 397f subs r1, #127 @ 0x7f
  38013. 80118fc: e7c0 b.n 8011880 <__ieee754_fmodf+0x50>
  38014. 80118fe: 3a01 subs r2, #1
  38015. 8011900: 007f lsls r7, r7, #1
  38016. 8011902: e7c3 b.n 801188c <__ieee754_fmodf+0x5c>
  38017. 8011904: 15c2 asrs r2, r0, #23
  38018. 8011906: 3a7f subs r2, #127 @ 0x7f
  38019. 8011908: e7c2 b.n 8011890 <__ieee754_fmodf+0x60>
  38020. 801190a: 2d00 cmp r5, #0
  38021. 801190c: da02 bge.n 8011914 <__ieee754_fmodf+0xe4>
  38022. 801190e: 005b lsls r3, r3, #1
  38023. 8011910: 3901 subs r1, #1
  38024. 8011912: e7d7 b.n 80118c4 <__ieee754_fmodf+0x94>
  38025. 8011914: d0a6 beq.n 8011864 <__ieee754_fmodf+0x34>
  38026. 8011916: 006b lsls r3, r5, #1
  38027. 8011918: e7fa b.n 8011910 <__ieee754_fmodf+0xe0>
  38028. 801191a: 005b lsls r3, r3, #1
  38029. 801191c: 3a01 subs r2, #1
  38030. 801191e: e7d9 b.n 80118d4 <__ieee754_fmodf+0xa4>
  38031. 8011920: f1c2 22ff rsb r2, r2, #4278255360 @ 0xff00ff00
  38032. 8011924: f502 027f add.w r2, r2, #16711680 @ 0xff0000
  38033. 8011928: 3282 adds r2, #130 @ 0x82
  38034. 801192a: 4113 asrs r3, r2
  38035. 801192c: 4323 orrs r3, r4
  38036. 801192e: e7dd b.n 80118ec <__ieee754_fmodf+0xbc>
  38037. 8011930: 08011de0 .word 0x08011de0
  38038. 08011934 <_init>:
  38039. 8011934: b5f8 push {r3, r4, r5, r6, r7, lr}
  38040. 8011936: bf00 nop
  38041. 8011938: bcf8 pop {r3, r4, r5, r6, r7}
  38042. 801193a: bc08 pop {r3}
  38043. 801193c: 469e mov lr, r3
  38044. 801193e: 4770 bx lr
  38045. 08011940 <_fini>:
  38046. 8011940: b5f8 push {r3, r4, r5, r6, r7, lr}
  38047. 8011942: bf00 nop
  38048. 8011944: bcf8 pop {r3, r4, r5, r6, r7}
  38049. 8011946: bc08 pop {r3}
  38050. 8011948: 469e mov lr, r3
  38051. 801194a: 4770 bx lr