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- #ifndef __STM32H7xx_LL_SYSTEM_H
- #define __STM32H7xx_LL_SYSTEM_H
- #ifdef __cplusplus
- extern "C" {
- #endif
- #include "stm32h7xx.h"
- #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
- #define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U
- #define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U
- #define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U
- #define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U
- #define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U
- #define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U
- #define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U
- #define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U
- #define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U
- #define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U
- #define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U
- #define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U
- #define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U
- #define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U
- #define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U
- #define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U
- #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP
- #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP
- #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP
- #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP
- #if defined(I2C5)
- #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP
- #endif
- #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP
- #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP
- #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP
- #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP
- #if defined(SYSCFG_PMCR_BOOSTEN)
- #define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN
- #endif
- #define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO
- #define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO
- #define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO
- #define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO
- #if defined(SYSCFG_PMCR_EPIS_SEL)
- #define LL_SYSCFG_ETH_MII 0x00000000U
- #define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2
- #endif
- #define LL_SYSCFG_EXTI_PORTA 0U
- #define LL_SYSCFG_EXTI_PORTB 1U
- #define LL_SYSCFG_EXTI_PORTC 2U
- #define LL_SYSCFG_EXTI_PORTD 3U
- #define LL_SYSCFG_EXTI_PORTE 4U
- #define LL_SYSCFG_EXTI_PORTF 5U
- #define LL_SYSCFG_EXTI_PORTG 6U
- #define LL_SYSCFG_EXTI_PORTH 7U
- #if defined(GPIOI)
- #define LL_SYSCFG_EXTI_PORTI 8U
- #endif
- #define LL_SYSCFG_EXTI_PORTJ 9U
- #define LL_SYSCFG_EXTI_PORTK 10U
- #define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U)
- #define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U)
- #define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U)
- #define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U)
- #define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U)
- #define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U)
- #define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U)
- #define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U)
- #define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U)
- #define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U)
- #define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U)
- #define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U)
- #define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U)
- #define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U)
- #define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U)
- #define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U)
- #define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML
- #define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML
- #define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML
- #define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L
- #define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L
- #if defined(SYSCFG_CFGR_SRAM3L)
- #define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L
- #endif
- #define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L
- #define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML
- #define LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L
- #define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL
- #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL
- #if defined(DUAL_CORE)
- #define LL_SYSCFG_TIMBREAK_CM4_LOCKUP SYSCFG_CFGR_CM4L
- #endif
- #define LL_SYSCFG_CELL_CODE 0U
- #define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS
- #define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U
- #define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M
- #if defined (DUAL_CORE)
- #define LL_SYSCFG_IWDG2_SW_CONTROL_MODE 0U
- #define LL_SYSCFG_IWDG2_HW_CONTROL_MODE SYSCFG_UR12_IWDG2M
- #endif
- #define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U
- #define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U
- #define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U
- #define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U
- #ifdef SYSCFG_UR17_TCM_AXI_CFG
- #define LL_SYSCFG_ITCM_AXI_64KB_320KB 0U
- #define LL_SYSCFG_ITCM_AXI_128KB_256KB 1U
- #define LL_SYSCFG_ITCM_AXI_192KB_192KB 2U
- #define LL_SYSCFG_ITCM_AXI_256KB_128KB 3U
- #endif
- #if defined(SYSCFG_PKGR_PKG)
- #if (STM32H7_DEV_ID == 0x450UL)
- #define LL_SYSCFG_LQFP100_PACKAGE 0U
- #define LL_SYSCFG_TQFP144_PACKAGE 2U
- #define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U
- #define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U
- #elif (STM32H7_DEV_ID == 0x483UL)
- #define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE 0U
- #define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE 1U
- #define LL_SYSCFG_LQFP100_INDUS_PACKAGE 2U
- #define LL_SYSCFG_TFBGA100_INDUS_PACKAGE 3U
- #define LL_SYSCFG_WLCSP115_INDUS_PACKAGE 4U
- #define LL_SYSCFG_LQFP144_PACKAGE 5U
- #define LL_SYSCFG_UFBGA144_PACKAGE 6U
- #define LL_SYSCFG_LQFP144_INDUS_PACKAGE 7U
- #define LL_SYSCFG_UFBGA169_INDUS_PACKAGE 8U
- #define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U
- #define LL_SYSCFG_LQFP176_INDUS_PACKAGE 10U
- #endif
- #endif
-
- #define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U
- #define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0
- #define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1
- #define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH
- #define LL_DBGMCU_TRACE_NONE 0x00000000U
- #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
- #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
- #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
- #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)
- #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2
- #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3
- #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4
- #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5
- #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6
- #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7
- #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12
- #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13
- #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14
- #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1
- #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1
- #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2
- #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3
- #if defined(I2C5)
- #define LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1LFZ1_DBG_I2C5
- #endif
- #if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)
- #define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN
- #endif
- #if defined(TIM23)
- #define LL_DBGMCU_APB1_GRP2_TIM23_STOP DBGMCU_APB1HFZ1_DBG_TIM23
- #endif
- #if defined(TIM24)
- #define LL_DBGMCU_APB1_GRP2_TIM24_STOP DBGMCU_APB1HFZ1_DBG_TIM24
- #endif
- #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1
- #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8
- #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15
- #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16
- #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17
- #if defined(HRTIM1)
- #define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM
- #endif
- #define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1
- #define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4
- #define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2
- #define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3
- #define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4
- #define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5
- #define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC
- #define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1
- #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
- #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
- #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
- #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
- #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
- #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
- #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
- #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
- #if defined(SYSCFG_PMCR_EPIS_SEL)
- __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
- {
- MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));
- }
- #endif
- __STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
- {
- SET_BIT(SYSCFG->PMCR, AnalogSwitch);
- }
- __STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
- {
- CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);
- }
- #ifdef SYSCFG_PMCR_BOOSTEN
- __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
- {
- SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
- }
- __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
- {
- CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
- }
- #endif
- __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
- {
- SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);
- }
- __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
- {
- CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);
- }
- __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
- {
- MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
- {
- return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));
- }
- __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
- {
- #if defined(DUAL_CORE)
- MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
- SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
- SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L, Break);
- #elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
- MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
- SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
- SYSCFG_CFGR_PVDL, Break);
- #elif defined(SYSCFG_CFGR_AXISRAML)
- MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
- SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\
- Break);
- #else
- MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML |\
- SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
- SYSCFG_CFGR_PVDL, Break);
- #endif
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
- {
- #if defined(DUAL_CORE)
- return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
- SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
- SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
- SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L));
- #elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
- return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
- SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
- SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
- SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
- #elif defined (SYSCFG_CFGR_AXISRAML)
- return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
- SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
- SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
- SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
- #else
- return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_CM7L | \
- SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
- #endif
- }
- __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
- {
- SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
- }
- __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
- {
- CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
- {
- return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
- {
- return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);
- }
- __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)
- {
- #if defined(SYSCFG_CCCSR_HSLV)
- SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
- #else
- SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
- #endif
- }
- #if defined(SYSCFG_CCCSR_HSLV1)
- __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void)
- {
- SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
- }
- __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void)
- {
- SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
- }
- __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void)
- {
- SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
- }
- #endif
- __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)
- {
- #if defined(SYSCFG_CCCSR_HSLV)
- CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
- #else
- CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
- #endif
- }
- #if defined(SYSCFG_CCCSR_HSLV1)
- __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void)
- {
- CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
- }
- __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void)
- {
- CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
- }
- __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void)
- {
- CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
- }
- #endif
- __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)
- {
- #if defined(SYSCFG_CCCSR_HSLV)
- return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);
- #else
- return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL);
- #endif
- }
- #if defined(SYSCFG_CCCSR_HSLV1)
- __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)
- {
- return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)
- {
- return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)
- {
- return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL);
- }
- #endif
- __STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
- {
- SET_BIT(SYSCFG->CCCSR, CompCode);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));
- }
- #ifdef SYSCFG_CCCSR_CS_MMC
- __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC));
- }
- #endif
- __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));
- }
- __STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
- {
- MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));
- }
- #ifdef SYSCFG_CCCR_PCC_MMC
- __STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)
- {
- MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC));
- }
- #endif
- __STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
- {
- MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));
- }
- #ifdef SYSCFG_CCCR_NCC_MMC
- __STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)
- {
- MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC));
- }
- #endif
- #ifdef SYSCFG_PKGR_PKG
- __STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));
- }
- #endif
- #ifdef SYSCFG_UR0_RDP
- __STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
- }
- #ifdef SYSCFG_UR0_BKS
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)
- {
- return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
- }
- #endif
- __STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));
- }
- __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)
- {
-
- #if defined(DUAL_CORE)
- MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos));
- #else
- MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));
- #endif
- }
- __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)
- {
-
- #if defined(DUAL_CORE)
- return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos);
- #else
- return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);
- #endif
- }
- __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)
- {
-
- #if defined(DUAL_CORE)
- MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress);
- #else
- MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);
- #endif
- }
- __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)
- {
-
- #if defined(DUAL_CORE)
- return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1));
- #else
- return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));
- #endif
- }
- #if defined(DUAL_CORE)
- __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)
- {
-
- MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos));
- }
- __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void)
- {
-
- return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos);
- }
- __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)
- {
-
- MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress);
- }
- __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void)
- {
-
- return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1));
- }
- #endif
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)
- {
- return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)
- {
- return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
- }
- #ifdef SYSCFG_UR8_MEPAD_BANK2
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)
- {
- return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)
- {
- return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
- }
- #endif
- #ifdef SYSCFG_UR9_WRPN_BANK2
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)
- {
- return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
- }
- #endif
- #ifdef SYSCFG_UR10_PAEND_BANK2
- __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
- }
- #endif
- #ifdef SYSCFG_UR11_SAEND_BANK2
- __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
- }
- #endif
- __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));
- }
- #if defined (DUAL_CORE)
- __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M));
- }
- #endif
- __STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)
- {
- return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)
- {
- return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)
- {
- return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);
- }
- #if defined (DUAL_CORE)
- __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void)
- {
- return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void)
- {
- return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL);
- }
- #endif
- __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)
- {
- return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)
- {
- return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)
- {
- return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);
- }
- __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)
- {
- return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
- }
- #ifdef SYSCFG_UR17_TCM_AXI_CFG
- __STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void)
- {
- return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG));
- }
- #endif
- #ifdef SYSCFG_UR18_CPU_FREQ_BOOST
- __STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void)
- {
- return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL);
- }
- #endif
- #endif
- __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
- {
- return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
- }
- __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
- {
- return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
- }
- __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)
- {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
- }
- __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)
- {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
- }
- __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)
- {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
- }
- __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)
- {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
- }
- __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)
- {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
- }
- __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)
- {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
- }
- #if defined (DUAL_CORE)
- __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void)
- {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
- }
- __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void)
- {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
- }
- __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void)
- {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
- }
- __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void)
- {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
- }
- __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void)
- {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
- }
- __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void)
- {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
- }
- #endif
- #if defined(DBGMCU_CR_DBG_STOPD3)
- __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)
- {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
- }
- __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)
- {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
- }
- #endif
- #if defined(DBGMCU_CR_DBG_STANDBYD3)
- __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)
- {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
- }
- __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)
- {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
- }
- #endif
- __STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)
- {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
- }
- __STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)
- {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
- }
- __STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)
- {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
- }
- __STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)
- {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
- }
- __STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)
- {
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
- }
- __STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)
- {
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
- }
- #define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U
- #define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN
- __STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
- {
- MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
- }
- __STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
- {
- return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
- }
- __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
- {
- SET_BIT(DBGMCU->APB1LFZ1, Periphs);
- }
- __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
- {
- CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
- }
- #ifdef DBGMCU_APB1HFZ1_DBG_FDCAN
- __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
- {
- SET_BIT(DBGMCU->APB1HFZ1, Periphs);
- }
- __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
- {
- CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
- }
- #endif
- #if defined(TIM23) || defined(TIM24)
- __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
- {
- SET_BIT(DBGMCU->APB1HFZ1, Periphs);
- }
- __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
- {
- CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
- }
- #endif
- __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
- {
- SET_BIT(DBGMCU->APB2FZ1, Periphs);
- }
- __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
- {
- CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);
- }
- __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
- {
- SET_BIT(DBGMCU->APB3FZ1, Periphs);
- }
- __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
- {
- CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);
- }
- __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
- {
- SET_BIT(DBGMCU->APB4FZ1, Periphs);
- }
- __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
- {
- CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);
- }
- __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
- {
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
- }
- __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
- {
- return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
- }
- #if defined(DUAL_CORE)
- __STATIC_INLINE void LL_ART_Enable(void)
- {
- SET_BIT(ART->CTR, ART_CTR_EN);
- }
- __STATIC_INLINE void LL_ART_Disable(void)
- {
- CLEAR_BIT(ART->CTR, ART_CTR_EN);
- }
- __STATIC_INLINE uint32_t LL_ART_IsEnabled(void)
- {
- return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);
- }
- __STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)
- {
- MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));
- }
- __STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
- {
- return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);
- }
- #endif
- #endif
- #ifdef __cplusplus
- }
- #endif
- #endif
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