DEPS_SOLVE_TMP += no2memcache
RTL_SRCS_SOLVE_TMP += /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_match.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v
SIM_SRCS_SOLVE_TMP += /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//sim/mem_sim.v
PREREQ_SOLVE_TMP +=  
