DEPS_SOLVE_TMP += no2misc
RTL_SRCS_SOLVE_TMP += /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/i2c_master.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/i2c_master_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/muacm2wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/prims.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/pdm.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/pwm.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/stream2wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart2wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/xclk_strobe.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/xclk_wb.v
SIM_SRCS_SOLVE_TMP += 
PREREQ_SOLVE_TMP +=  
