DEPS_SOLVE_TMP += no2usb
RTL_SRCS_SOLVE_TMP += /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_crc.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_ep_buf.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_ep_status.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_phy.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_rx_ll.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_rx_pkt.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_trans.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_tx_ll.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_tx_pkt.v
SIM_SRCS_SOLVE_TMP += 
PREREQ_SOLVE_TMP +=  /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_defs.vh /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/build-tmp/usb_trans_mc.hex /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/build-tmp/usb_ep_status.hex
