`timescale 1ns / 1ps

module duty(
	input CLK,
	input [15:0] cmp,
	output reg out
    );	
	reg [15:0]cnt;
	reg [15:0]cmp_buf;

	always @(posedge CLK) begin
		cnt<=cnt+1;
		out<=cnt>cmp_buf;
		cmp_buf<=cmp;
	end

endmodule
