DEPS_SOLVE_TMP += video
RTL_SRCS_SOLVE_TMP += /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_phy_1x.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_phy_2x.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_phy_4x.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_text_2x.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_shared_ram.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_text.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v
SIM_SRCS_SOLVE_TMP += 
PREREQ_SOLVE_TMP +=  
