DEPS_SOLVE_TMP += no2ice40
RTL_SRCS_SOLVE_TMP += /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_i2c_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_rgb_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spi_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_oserdes.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_dff.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_sync.v
SIM_SRCS_SOLVE_TMP += 
PREREQ_SOLVE_TMP +=  
