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@@ -48,8 +48,12 @@ include $(BUILD_TMP)/proj-deps.mk
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PROJ_RTL_SRCS := $(abspath $(PROJ_RTL_SRCS))
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PROJ_TOP_SRC := $(abspath $(PROJ_TOP_SRC))
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+# Board config
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PIN_DEF ?= $(abspath data/$(PROJ_TOP_MOD)-$(BOARD).pcf)
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+BOARD_DEFINE=BOARD_$(shell echo $(BOARD) | tr a-z A-Z)
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+YOSYS_READ_ARGS += -D$(BOARD_DEFINE)=1
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+
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# Add those to the list
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PROJ_ALL_RTL_SRCS += $(PROJ_RTL_SRCS)
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PROJ_ALL_SIM_SRCS += $(PROJ_SIM_SRCS)
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@@ -85,7 +89,7 @@ $(BUILD_TMP)/$(PROJ).pnr.rpt $(BUILD_TMP)/$(PROJ).asc: $(BUILD_TMP)/$(PROJ).json
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# Simulation
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$(BUILD_TMP)/%_tb: sim/%_tb.v $(ICE40_LIBS) $(PROJ_ALL_PREREQ) $(PROJ_ALL_RTL_SRCS) $(PROJ_ALL_SIM_SRCS)
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- iverilog -Wall -DSIM=1 -o $@ \
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+ iverilog -Wall -DSIM=1 -D$(BOARD_DEFINE)=1 -o $@ \
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$(PROJ_SYNTH_INCLUDES) $(PROJ_SIM_INCLUDES) \
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$(addprefix -l, $(ICE40_LIBS) $(PROJ_ALL_RTL_SRCS) $(PROJ_ALL_SIM_SRCS)) \
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$<
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