cores/hub75: Add support for Inc/Rst style address lines

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

cores/hub75/rtl/hub75_bcm.v

@@ -33,6 +33,8 @@ module hub75_bcm #(
 	parameter integer LOG_N_ROWS  = $clog2(N_ROWS)
 )(
 	// PHY
+	output wire phy_addr_inc,
+	output wire phy_addr_rst,
 	output wire [LOG_N_ROWS-1:0] phy_addr,
 	output wire phy_le,
 
@@ -48,6 +50,7 @@ module hub75_bcm #(
 
 	// Control
 	input  wire [LOG_N_ROWS-1:0] ctrl_row,
+	input  wire ctrl_row_first,
 	input  wire ctrl_go,
 	output wire ctrl_rdy,
 
@@ -87,7 +90,8 @@ module hub75_bcm #(
 
 	reg  [LOG_N_ROWS-1:0] addr;
 	reg  [LOG_N_ROWS-1:0] addr_out;
-	wire addr_ce;
+	reg  addr_do_inc;
+	reg  addr_do_rst;
 	wire le;
 
 
@@ -190,6 +194,12 @@ module hub75_bcm #(
 			addr <= ctrl_row;
 
 	always @(posedge clk)
+	begin
+		addr_do_inc <= (addr_do_inc | (ctrl_go & ~ctrl_row_first)) & ~(fsm_state == ST_POST_LATCH);
+		addr_do_rst <= (addr_do_rst | (ctrl_go &  ctrl_row_first)) & ~(fsm_state == ST_POST_LATCH);
+	end
+
+	always @(posedge clk)
 		if (fsm_state == ST_DO_LATCH)
 			addr_out <= addr;
 
@@ -206,4 +216,7 @@ module hub75_bcm #(
 	assign phy_addr = addr_out;
 	assign phy_le = le;
 
+	assign phy_addr_inc = (fsm_state == ST_DO_LATCH) ? addr_do_inc : 1'b0;
+	assign phy_addr_rst = (fsm_state == ST_DO_LATCH) ? addr_do_rst : 1'b0;
+
 endmodule // hub75_bcm

cores/hub75/rtl/hub75_phy.v

@@ -30,11 +30,14 @@ module hub75_phy #(
 	parameter integer N_BANKS  = 2,
 	parameter integer N_ROWS   = 32,
 	parameter integer N_CHANS  = 3,
+	parameter integer PHY_AIR  = 0,		// PHY Address Inc/Reset
 
 	// Auto-set
 	parameter integer LOG_N_ROWS  = $clog2(N_ROWS)
 )(
 	// Hub75 interface pads
+	output wire hub75_addr_inc,
+	output wire hub75_addr_rst,
 	output wire [LOG_N_ROWS-1:0] hub75_addr,
 	output wire [(N_BANKS*N_CHANS)-1:0] hub75_data,
 	output wire hub75_clk,
@@ -42,6 +45,8 @@ module hub75_phy #(
 	output wire hub75_blank,
 
 	// PHY interface signals
+	input wire phy_addr_inc,
+	input wire phy_addr_rst,
 	input wire [LOG_N_ROWS-1:0] phy_addr,
 	input wire [(N_BANKS*N_CHANS)-1:0] phy_data,
 	input wire phy_clk,
@@ -59,18 +64,43 @@ module hub75_phy #(
 
 	// Address
 	generate
-		for (i=0; i<LOG_N_ROWS; i=i+1)
+		if (PHY_AIR == 0) begin
 			SB_IO #(
 				.PIN_TYPE(6'b010100),
 				.PULLUP(1'b0),
 				.NEG_TRIGGER(1'b0),
 				.IO_STANDARD("SB_LVCMOS")
-			) iob_addr_I (
-				.PACKAGE_PIN(hub75_addr[i]),
+			) iob_addr_I[LOG_N_ROWS-1:0] (
+				.PACKAGE_PIN(hub75_addr),
 				.CLOCK_ENABLE(1'b1),
 				.OUTPUT_CLK(clk),
-				.D_OUT_0(phy_addr[i])
+				.D_OUT_0(phy_addr)
 			);
+		end else begin
+			SB_IO #(
+				.PIN_TYPE(6'b010100),
+				.PULLUP(1'b0),
+				.NEG_TRIGGER(1'b0),
+				.IO_STANDARD("SB_LVCMOS")
+			) iob_addr_inc_I (
+				.PACKAGE_PIN(hub75_addr_inc),
+				.CLOCK_ENABLE(1'b1),
+				.OUTPUT_CLK(clk),
+				.D_OUT_0(phy_addr_inc ^ PHY_AIR[1])
+			);
+
+			SB_IO #(
+				.PIN_TYPE(6'b010100),
+				.PULLUP(1'b0),
+				.NEG_TRIGGER(1'b0),
+				.IO_STANDARD("SB_LVCMOS")
+			) iob_addr_rst_I (
+				.PACKAGE_PIN(hub75_addr_rst),
+				.CLOCK_ENABLE(1'b1),
+				.OUTPUT_CLK(clk),
+				.D_OUT_0(phy_addr_rst ^ PHY_AIR[2])
+			);
+		end
 	endgenerate
 
 	// Data lines

cores/hub75/rtl/hub75_scan.v

@@ -35,6 +35,7 @@ module hub75_scan #(
 )(
 	// BCM interface
 	output wire [LOG_N_ROWS-1:0] bcm_row,
+	output wire bcm_row_first,
 	output wire bcm_go,
 	input  wire bcm_rdy,
 
@@ -68,6 +69,7 @@ module hub75_scan #(
 
 	// Row counter
 	reg [LOG_N_ROWS-1:0] row;
+	reg row_first;
 	reg row_last;
 
 
@@ -112,14 +114,17 @@ module hub75_scan #(
 	always @(posedge clk)
 		if (fsm_state == ST_IDLE) begin
 			row <= 0;
-			row_last <= 1'b0;
+			row_first <= 1'b1;
+			row_last  <= 1'b0;
 		end else if (fsm_state == ST_PAINT) begin
 			if (SCAN_MODE == "ZIGZAG") begin
 				row <= ~(row + {LOG_N_ROWS{row[LOG_N_ROWS-1]}});
-				row_last <= (row == {1'b0, {(LOG_N_ROWS-1){1'b1}}});
+				row_first <= 1'b0;
+				row_last  <= (row == {1'b0, {(LOG_N_ROWS-1){1'b1}}});
 			end else begin
 				row <= row + 1;
-				row_last <= (row == {{(LOG_N_ROWS-1){1'b1}}, 1'b0});
+				row_first <= 1'b0;
+				row_last  <= (row == {{(LOG_N_ROWS-1){1'b1}}, 1'b0});
 			end
 		end
 
@@ -128,8 +133,9 @@ module hub75_scan #(
 	// -------------------
 
 	// BCM
-	assign bcm_row = row;
-	assign bcm_go  = (fsm_state == ST_PAINT);
+	assign bcm_row       = row;
+	assign bcm_row_first = row_first;
+	assign bcm_go        = (fsm_state == ST_PAINT);
 
 	// Frame Buffer pre loader
 	assign fb_row_addr = row;

cores/hub75/rtl/hub75_top.v

@@ -32,6 +32,7 @@ module hub75_top #(
 	parameter integer N_CHANS  = 3,		// # of data channel
 	parameter integer N_PLANES = 8,		// # bitplanes
 	parameter integer BITDEPTH = 24,	// # bits per color
+	parameter integer PHY_AIR  = 0,		// PHY Address Inc/Reset
 
 	parameter SCAN_MODE = "ZIGZAG",		// 'LINEAR' or 'ZIGZAG'
 
@@ -41,6 +42,8 @@ module hub75_top #(
 	parameter integer LOG_N_COLS  = $clog2(N_COLS)
 )(
 	// Hub75 interface pads
+	output wire hub75_addr_inc,
+	output wire hub75_addr_rst,
 	output wire [LOG_N_ROWS-1:0] hub75_addr,
 	output wire [(N_BANKS*N_CHANS)-1:0] hub75_data,
 	output wire hub75_clk,
@@ -85,6 +88,8 @@ module hub75_top #(
 	wire frame_swap_fb;
 
 	// PHY interface
+	wire phy_addr_inc;
+	wire phy_addr_rst;
 	wire [LOG_N_ROWS-1:0] phy_addr;
 	wire [(N_BANKS*N_CHANS)-1:0] phy_data;
 	wire phy_clk;
@@ -109,6 +114,7 @@ module hub75_top #(
 
 	// Binary Code Modulator
 	wire [LOG_N_ROWS-1:0] bcm_row;
+	wire bcm_row_first;
 	wire bcm_go;
 	wire bcm_rdy;
 
@@ -182,6 +188,7 @@ module hub75_top #(
 		.SCAN_MODE(SCAN_MODE)
 	) scan_I (
 		.bcm_row(bcm_row),				// -> hub75_bcm
+		.bcm_row_first(bcm_row_first),	// -> hub75_bcm
 		.bcm_go(bcm_go),				// -> hub75_bcm
 		.bcm_rdy(bcm_rdy),				// <- hub75_bcm
 		.fb_row_addr(fbr_row_addr),		// -> hub75_framebuffer
@@ -198,6 +205,8 @@ module hub75_top #(
 	hub75_bcm #(
 		.N_PLANES(N_PLANES)
 	) bcm_I (
+		.phy_addr_inc(phy_addr_inc),	// -> hub75_phy
+		.phy_addr_rst(phy_addr_rst),	// -> hub75_phy
 		.phy_addr(phy_addr),			// -> hub75_phy
 		.phy_le(phy_le),				// -> hub75_phy
 		.shift_plane(shift_plane),		// -> hub75_shift
@@ -207,6 +216,7 @@ module hub75_top #(
 		.blank_go(blank_go),			// -> hub75_blanking
 		.blank_rdy(blank_rdy),			// <- hub75_blanking
 		.ctrl_row(bcm_row),				// <- hub75_scan
+		.ctrl_row_first(bcm_row_first),	// <- hub75_scan
 		.ctrl_go(bcm_go),				// <- hub75_scan
 		.ctrl_rdy(bcm_rdy),				// -> hub75_scan
 		.cfg_pre_latch_len(cfg_pre_latch_len),		// <- top
@@ -252,13 +262,18 @@ module hub75_top #(
 	hub75_phy #(
 		.N_BANKS(N_BANKS),
 		.N_ROWS(N_ROWS),
-		.N_CHANS(N_CHANS)
+		.N_CHANS(N_CHANS),
+		.PHY_AIR(PHY_AIR)
 	) phy_I (
+		.hub75_addr_inc(hub75_addr_inc),// -> pad
+		.hub75_addr_rst(hub75_addr_rst),// -> pad
 		.hub75_addr(hub75_addr),		// -> pad
 		.hub75_data(hub75_data),		// -> pad
 		.hub75_clk(hub75_clk),			// -> pad
 		.hub75_le(hub75_le),			// -> pad
 		.hub75_blank(hub75_blank),		// -> pad
+		.phy_addr_inc(phy_addr_inc),	// <- hub75_bcm
+		.phy_addr_rst(phy_addr_rst),	// <- hub75_bcm
 		.phy_addr(phy_addr),			// <- hub75_bcm
 		.phy_data(phy_data),			// <- hub75_shift
 		.phy_clk(phy_clk),				// <- hub75_shift