projects/riscv_usb: Whitespace fixes for soc_{bram,spram}

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

projects/riscv_usb/rtl/soc_bram.v

@@ -14,11 +14,11 @@ module soc_bram #(
 	parameter INIT_FILE = ""
 )(
 	input  wire [AW-1:0] addr,
-	output reg  [31:0] rdata,
-	input  wire [31:0] wdata,
-	input  wire [ 3:0] wmsk,
-	input  wire we,
-	input  wire clk
+	output reg    [31:0] rdata,
+	input  wire   [31:0] wdata,
+	input  wire   [ 3:0] wmsk,
+	input  wire          we,
+	input  wire          clk
 );
 
 	reg [31:0] mem [0:(1<<AW)-1];

projects/riscv_usb/rtl/soc_spram.v

@@ -13,11 +13,11 @@ module soc_spram #(
 	parameter integer AW = 14
 )(
 	input  wire [AW-1:0] addr,
-	output wire [31:0] rdata,
-	input  wire [31:0] wdata,
-	input  wire [ 3:0] wmsk,
-	input  wire we,
-	input  wire clk
+	output wire   [31:0] rdata,
+	input  wire   [31:0] wdata,
+	input  wire   [ 3:0] wmsk,
+	input  wire          we,
+	input  wire          clk
 );
 
 	wire [7:0] msk_nibble = {