cores/video: Don't force reg in simulation

iverilog seems to have issues with some constructs used in
the 'prims.v' file, so just avoid them for now.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

cores/video/rtl/vid_tgen.v

@@ -34,7 +34,10 @@
  */
 
 `default_nettype none
+
+`ifndef SIM
 `define FORCE_REG		// Yosys fuckery workaround :/
+`endif
 
 module vid_tgen #(
 	parameter integer H_WIDTH  = 12,