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@@ -0,0 +1,426 @@
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+/*
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+ * vid_text.v
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+ *
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+ * Video Text Mode generator
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+ *
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+ * Copyright (C) 2019 Sylvain Munaut <tnt@246tNt.com>
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+ * All rights reserved.
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+ *
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+ * BSD 3-clause, see LICENSE.bsd
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions are met:
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+ * * Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ * * Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in the
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+ * documentation and/or other materials provided with the distribution.
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+ * * Neither the name of the <organization> nor the
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+ * names of its contributors may be used to endorse or promote products
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+ * derived from this software without specific prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ *
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+ * vim: ts=4 sw=4
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+ */
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+
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+`default_nettype none
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+
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+module vid_text (
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+ // Timing input
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+ input wire vid_active_0,
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+ input wire vid_h_first_0,
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+ input wire vid_h_last_0,
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+ input wire vid_v_first_0,
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+ input wire vid_v_last_0,
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+
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+ // Pixel output
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+ output wire [15:0] vid_pix0_11,
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+ output wire [15:0] vid_pix1_11,
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+
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+ // Bus interface
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+ input wire [15:0] bus_addr,
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+ input wire [15:0] bus_din,
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+ output wire [15:0] bus_dout,
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+ input wire bus_cyc,
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+ input wire bus_we,
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+ output wire bus_ack,
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+
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+ // Clock / Reset
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+ input wire clk,
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+ input wire rst
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+);
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+ // Signals
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+ // -------
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+
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+ // Char look-up
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+ reg [10:0] cl_y_cnt_0;
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+
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+ reg [ 9:0] cl_y_cnt_1;
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+ reg [ 9:0] cl_x_cnt_1;
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+ reg cl_fetch_1;
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+ reg cl_valid_1;
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+
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+ wire cl_stb_3;
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+ wire cl_valid_3;
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+
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+ wire [15:0] cl_char_4;
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+
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+ // Glyph look-up
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+ reg [ 1:0] gl_x_4;
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+ wire [ 3:0] gl_y_4;
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+ reg gl_fetch_4;
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+
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+ wire gl_flip_x_4;
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+ wire gl_flip_y_4;
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+
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+ wire gl_flip_x_7;
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+ wire [ 3:0] gl_pixa_7;
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+ wire [ 3:0] gl_pixb_7;
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+
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+ reg [ 3:0] gl_pix0_8;
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+ reg [ 3:0] gl_pix1_8;
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+ wire [ 7:0] gl_attrs_8;
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+ wire gl_valid_8;
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+
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+ // RAM fetch interfaces
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+ wire [13:0] sm_addr_1;
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+ wire [15:0] sm_data_4;
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+ wire sm_read_1;
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+
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+ wire [13:0] gm_addr_4;
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+ wire [15:0] gm_data_7;
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+ wire gm_read_4;
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+
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+ wire [ 7:0] cm_addr0_8;
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+ wire [ 7:0] cm_addr1_8;
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+ wire [15:0] cm_data0_11;
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+ wire [15:0] cm_data1_11;
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+ wire cm_read_8;
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+ wire cm_zero_8;
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+
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+ // RAM bus interfaces
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+ wire smb_ready;
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+ reg smb_read;
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+ reg smb_zero;
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+ reg smb_write;
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+
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+ wire gmb_ready;
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+ reg gmb_read;
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+ reg gmb_zero;
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+ reg gmb_write;
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+
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+ wire cmb_ready;
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+ reg cmb_read;
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+ reg cmb_zero;
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+ reg cmb_write;
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+
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+ wire [15:0] smb_dout;
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+ wire [15:0] gmb_dout;
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+ wire [15:0] cmb_dout;
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+
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+ // Bus interface
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+ reg smb_req;
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+ wire smb_clear;
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+
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+ reg gmb_req;
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+ wire gmb_clear;
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+
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+ reg cmb_req;
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+ wire cmb_clear;
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+
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+ reg bus_ack_wait;
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+ wire bus_req_ok;
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+ reg [2:0] bus_req_ok_dly;
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+
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+
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+ // Char lookup
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+ // -----------
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+
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+ // Y counter
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+ always @(posedge clk)
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+ if (vid_v_first_0)
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+ // Start at -27 to center the 1024 in the 1080 of full HD
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+ cl_y_cnt_0 <= 11'h7e5;
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+ else
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+ cl_y_cnt_0 <= cl_y_cnt_0 + vid_h_last_0;
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+
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+ always @(posedge clk)
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+ cl_y_cnt_1 <= cl_y_cnt_0[9:0];
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+
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+ // X counter
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+ always @(posedge clk)
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+ if (vid_h_first_0)
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+ cl_x_cnt_1 <= 0;
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+ else
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+ cl_x_cnt_1 <= cl_x_cnt_1 + 1;
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+
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+ // Valid flag
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+ always @(posedge clk)
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+ cl_valid_1 <= ~cl_y_cnt_0[10] & vid_active_0;
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+
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+ // Fetch
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+ always @(posedge clk)
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+ cl_fetch_1 <= ~cl_y_cnt_0[10] & vid_active_0 & (vid_h_first_0 | (cl_x_cnt_1[1:0] == 3'b11));
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+
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+ // RAM interface
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+ assign sm_addr_1 = { cl_y_cnt_1[9:4], cl_x_cnt_1[9:2] };
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+ assign sm_read_1 = cl_fetch_1;
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+
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+ assign cl_char_4 = sm_data_4;
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+
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+ // Provide some sync signals to the next stage
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+ delay_bit #(2) dly_stb13 ( .d(cl_fetch_1), .q(cl_stb_3), .clk(clk) );
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+ delay_bit #(2) dly_valid13 ( .d(cl_valid_1), .q(cl_valid_3), .clk(clk) );
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+
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+
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+ // Glyph lookup
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+ // ------------
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+
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+ // X Counter
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+ always @(posedge clk)
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+ if (cl_stb_3)
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+ gl_x_4 <= 2'b00;
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+ else
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+ gl_x_4 <= gl_x_4 + 1;
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+
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+ // Y counter
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+ delay_bus #(3, 4) dly_y_cnt ( .d(cl_y_cnt_1[3:0]), .q(gl_y_4), .clk(clk) );
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+
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+ // Fetch
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+ always @(posedge clk)
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+ gl_fetch_4 <= cl_stb_3 | gl_x_4[0];
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+
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+ // X/Y flips attributes
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+ assign gl_flip_y_4 = cl_char_4[10] & ~cl_char_4[9];
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+ assign gl_flip_x_4 = cl_char_4[11] & ~cl_char_4[9];
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+
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+ // RAM interface
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+ assign gm_addr_4 = {
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+ cl_char_4[8:0],
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+ gl_y_4 ^ { 4{gl_flip_y_4} }, // Handle Y-flip
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+ gl_x_4[1] ^ gl_flip_x_4 // Handle X-flip
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+ };
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+ assign gm_read_4 = gl_fetch_4;
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+
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+ // Delay control signal for the mux
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+ delay_bit #(3) dly_flip_h ( .d(gl_flip_x_4), .q(gl_flip_x_7), .clk(clk) );
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+
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+ // Mux
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+ assign gl_pixa_7 = (gl_x_4[0] ^ gl_flip_x_7) ? gm_data_7[11: 8] : gm_data_7[3:0];
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+ assign gl_pixb_7 = (gl_x_4[0] ^ gl_flip_x_7) ? gm_data_7[15:12] : gm_data_7[7:4];
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+
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+ always @(posedge clk)
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+ begin
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+ gl_pix0_8 <= gl_flip_x_7 ? gl_pixa_7 : gl_pixb_7;
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+ gl_pix1_8 <= gl_flip_x_7 ? gl_pixb_7 : gl_pixa_7;
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+ end
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+
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+ // Forward the attributes & validity to the next stage
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+ delay_bit #(5) dly_valid38 ( .d(cl_valid_3), .q(gl_valid_8), .clk(clk) );
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+ delay_bus #(4, 8) dly_attrs ( .d(cl_char_4[15:8]), .q(gl_attrs_8), .clk(clk) );
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+
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+
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+ // Color lookup
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+ // ------------
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+
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+ // RAM interface
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+ vid_color_map cmap0_I (
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+ .attrs(gl_attrs_8),
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+ .glyph(gl_pix0_8),
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+ .color(cm_addr0_8)
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+ );
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+
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+ vid_color_map cmap1_I (
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+ .attrs(gl_attrs_8),
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+ .glyph(gl_pix1_8),
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+ .color(cm_addr1_8)
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+ );
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+
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+ assign cm_read_8 = gl_valid_8;
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+ assign cm_zero_8 = ~gl_valid_8;
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+
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+ assign vid_pix0_11 = cm_data0_11;
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+ assign vid_pix1_11 = cm_data1_11;
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+
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+
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+ // Memories
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+ // --------
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+
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+ // Screen memory (contains chars and attributes)
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+ vid_shared_ram #(
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+ .TYPE("SPRAM")
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+ ) screen_mem_I (
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+ .p_addr_0(sm_addr_1),
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+ .p_read_0(sm_read_1),
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+ .p_zero_0(1'b0),
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+ .p_dout_3(sm_data_4),
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+ .s_addr_0(bus_addr[13:0]),
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+ .s_din_0(bus_din),
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+ .s_read_0(smb_read),
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+ .s_zero_0(smb_zero),
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+ .s_write_0(smb_write),
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+ .s_dout_3(smb_dout),
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+ .s_ready_0(smb_ready),
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+ .clk(clk),
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+ .rst(rst)
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+ );
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+
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+ // Glyph memory (contains bitmap for each character)
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+ vid_shared_ram #(
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+ .TYPE("SPRAM")
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+ ) glyph_mem_I (
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+ .p_addr_0(gm_addr_4),
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+ .p_read_0(gm_read_4),
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+ .p_zero_0(1'b0),
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+ .p_dout_3(gm_data_7),
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+ .s_addr_0(bus_addr[13:0]),
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+ .s_din_0(bus_din),
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+ .s_read_0(gmb_read),
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+ .s_zero_0(gmb_zero),
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+ .s_write_0(gmb_write),
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+ .s_dout_3(gmb_dout),
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+ .s_ready_0(gmb_ready),
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+ .clk(clk),
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+ .rst(rst)
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+ );
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+
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+ // Palette memory (contain mapping to real color)
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+ // (duplicated to allow 2 looks ups in //)
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+ vid_shared_ram #(
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+ .TYPE("EBR")
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+ ) color_mem_a_I (
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+ .p_addr_0(cm_addr0_8),
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+ .p_read_0(cm_read_8),
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+ .p_zero_0(cm_zero_8),
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+ .p_dout_3(cm_data0_11),
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+ .s_addr_0(bus_addr[7:0]),
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+ .s_din_0(bus_din),
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+ .s_read_0(cmb_read),
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+ .s_zero_0(cmb_zero),
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+ .s_write_0(cmb_write),
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+ .s_dout_3(cmb_dout),
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+ .s_ready_0(cmb_ready),
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+ .clk(clk),
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+ .rst(rst)
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+ );
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+
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+ vid_shared_ram #(
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+ .TYPE("EBR")
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+ ) color_mem_b_I (
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+ .p_addr_0(cm_addr1_8),
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+ .p_read_0(cm_read_8),
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+ .p_zero_0(cm_zero_8),
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+ .p_dout_3(cm_data1_11),
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+ .s_addr_0(bus_addr[7:0]),
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+ .s_din_0(bus_din),
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+ .s_read_0(1'b0),
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+ .s_zero_0(1'b0),
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+ .s_write_0(cmb_write),
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+ .s_dout_3(),
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+ .s_ready_0(),
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+ .clk(clk),
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+ .rst(rst)
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+ );
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+
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+
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+ // External bus interface
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+ // ----------------------
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+
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+ // Request lines from the various memories
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+ always @(posedge clk)
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+ if (smb_clear) begin
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+ smb_read <= 1'b0;
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+ smb_zero <= 1'b0;
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+ smb_write <= 1'b0;
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+ smb_req <= 1'b0;
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+ end else begin
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+ smb_read <= (bus_addr[15:14] == 2'b10) & ~bus_we;
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+ smb_zero <= (bus_addr[15:14] != 2'b10);
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+ smb_write <= (bus_addr[15:14] == 2'b10) & bus_we;
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+ smb_req <= (bus_addr[15:14] == 2'b10);
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+ end
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+
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+ always @(posedge clk)
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+ if (gmb_clear) begin
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+ gmb_read <= 1'b0;
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+ gmb_zero <= 1'b0;
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+ gmb_write <= 1'b0;
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+ gmb_req <= 1'b0;
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+ end else begin
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+ gmb_read <= (bus_addr[15:14] == 2'b11) & ~bus_we;
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+ gmb_zero <= (bus_addr[15:14] != 2'b11);
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+ gmb_write <= (bus_addr[15:14] == 2'b11) & bus_we;
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+ gmb_req <= (bus_addr[15:14] == 2'b11);
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+ end
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+
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+ always @(posedge clk)
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+ if (cmb_clear) begin
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+ cmb_read <= 1'b0;
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+ cmb_zero <= 1'b0;
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+ cmb_write <= 1'b0;
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+ cmb_req <= 1'b0;
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+ end else begin
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+ cmb_read <= (bus_addr[15:13] == 3'b011) & ~bus_we;
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+ cmb_zero <= (bus_addr[15:13] != 3'b011);
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+ cmb_write <= (bus_addr[15:13] == 3'b011) & bus_we;
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+ cmb_req <= (bus_addr[15:13] == 3'b011);
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+ end
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+
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+ // Condition to force the requests to zero :
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+ // no access needed, ack pending or this cycle went through
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+ assign smb_clear = ~bus_cyc | bus_ack_wait | (smb_req & smb_ready);
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+ assign gmb_clear = ~bus_cyc | bus_ack_wait | (gmb_req & gmb_ready);
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+ assign cmb_clear = ~bus_cyc | bus_ack_wait | (cmb_req & cmb_ready);
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+
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+ // Track when request are accepted by the RAM
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+ assign bus_req_ok = (smb_req & smb_ready) | (gmb_req & gmb_ready) | (cmb_req & cmb_ready);
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+
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+ always @(posedge clk)
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+ bus_req_ok_dly <= { bus_req_ok_dly[1:0], bus_req_ok & ~bus_we };
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+
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+ // ACK wait state tracking
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+ always @(posedge clk)
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+ if (rst)
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+ bus_ack_wait <= 1'b0;
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+ else
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+ bus_ack_wait <= ((bus_ack_wait & ~bus_we) | bus_req_ok) & ~bus_req_ok_dly[2];
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+
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+ // Bus Ack
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+ assign bus_ack = bus_ack_wait & (bus_we | bus_req_ok_dly[2]);
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+
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+ // Output is simply the OR of all memory since we force them to zero if
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+ // they're not accessed
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+ assign bus_dout = smb_dout | gmb_dout | cmb_dout;
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+
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+endmodule // vid_text
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+
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+
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+module vid_color_map (
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+ input wire [7:0] attrs,
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+ input wire [3:0] glyph,
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+ output reg [7:0] color
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+);
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+
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+ always @(*)
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+ begin
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+ if (attrs[1]) begin
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+ if (glyph[3:1] == 3'b000)
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+ color <= { 4'b0000, glyph[0], glyph[0] ? attrs[7:5] : attrs[4:2] };
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+ else
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+ color <= { 4'b0001, glyph };
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+ end else begin
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+ color <= { attrs[7:4], glyph };
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+ end
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+ end
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+
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+endmodule
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Sylvain Munaut