cores/misc: Replace in-tree core with submodule

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

.gitmodules

@@ -1,3 +1,6 @@
 [submodule "build"]
 	path = build
 	url = https://github.com/no2fpga/no2build.git
+[submodule "cores/no2misc"]
+	path = cores/no2misc
+	url = https://github.com/no2fpga/no2misc.git

cores/misc/Makefile

@@ -1,4 +0,0 @@
-CORE := no2misc
-
-NO2BUILD_DIR ?= $(abspath ../../build)
-include $(NO2BUILD_DIR)/core-rules.mk

cores/misc/README.md

@@ -1,6 +0,0 @@
-Misc
-====
-
-This contains a collection of small utility cores.
-
-These cores are licensed under the BSD 3-clause licence (see LICENSE.bsd)

cores/misc/no2core.mk

@@ -1,24 +0,0 @@
-CORE := no2misc
-
-RTL_SRCS_no2misc = $(addprefix rtl/, \
-	delay.v \
-	fifo_sync_ram.v \
-	fifo_sync_shift.v \
-	glitch_filter.v \
-	ram_sdp.v \
-	prims.v \
-	pdm.v \
-	pwm.v \
-	uart_rx.v \
-	uart_tx.v \
-	uart_wb.v \
-	xclk_strobe.v \
-	xclk_wb.v \
-)
-
-TESTBENCHES_no2misc := \
-	fifo_tb \
-	pdm_tb \
-	uart_tb \
-
-include $(NO2BUILD_DIR)/core-magic.mk

cores/misc/rtl/delay.v

@@ -1,110 +0,0 @@
-/*
- * delay.v
- *
- * vim: ts=4 sw=4
- *
- * Generates a delay line/bus
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-// ---------------------------------------------------------------------------
-// Single line delay
-// ---------------------------------------------------------------------------
-
-module delay_bit #(
-	parameter integer DELAY = 1
-)(
-	input  wire d,
-	output wire q,
-	input  wire clk
-);
-
-	reg [DELAY-1:0] dl;
-
-	generate
-		if (DELAY > 1)
-			always @(posedge clk)
-				dl <= { dl[DELAY-2:0], d };
-		else
-			always @(posedge clk)
-				dl <= d;
-	endgenerate
-
-	assign q = dl[DELAY-1];
-
-endmodule // delay_bit
-
-
-// ---------------------------------------------------------------------------
-// Bus delay
-// ---------------------------------------------------------------------------
-
-module delay_bus #(
-	parameter integer DELAY = 1,
-	parameter integer WIDTH = 1
-)(
-	input  wire [WIDTH-1:0] d,
-	output wire [WIDTH-1:0] q,
-	input  wire clk
-);
-
-	genvar i;
-	reg [WIDTH-1:0] dl[0:DELAY-1];
-
-	always @(posedge clk)
-		dl[0] <= d;
-
-	generate
-		for (i=1; i<DELAY; i=i+1)
-			always @(posedge clk)
-				dl[i] <= dl[i-1];
-	endgenerate
-
-	assign q = dl[DELAY-1];
-
-endmodule // delay_bus
-
-
-// ---------------------------------------------------------------------------
-// Toggle delay
-// ---------------------------------------------------------------------------
-
-module delay_toggle #(
-	parameter integer DELAY = 1
-)(
-	input  wire d,
-	output wire q,
-	input  wire clk
-);
-
-	// FIXME: TODO
-
-endmodule // delay_toggle

cores/misc/rtl/fifo_sync_ram.v

@@ -1,160 +0,0 @@
-/*
- * fifo_sync_ram.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-module fifo_sync_ram #(
-	parameter integer DEPTH = 256,
-	parameter integer WIDTH = 16
-)(
-	input  wire [WIDTH-1:0] wr_data,
-	input  wire wr_ena,
-	output wire wr_full,
-
-	output wire [WIDTH-1:0] rd_data,
-	input  wire rd_ena,
-	output wire rd_empty,
-
-	input  wire clk,
-	input  wire rst
-);
-
-	localparam AWIDTH = $clog2(DEPTH);
-
-
-	// Signals
-	// -------
-
-	// RAM
-	reg  [AWIDTH-1:0] ram_wr_addr;
-	wire [ WIDTH-1:0] ram_wr_data;
-	wire ram_wr_ena;
-
-	reg  [AWIDTH-1:0] ram_rd_addr;
-	wire [ WIDTH-1:0] ram_rd_data;
-	wire ram_rd_ena;
-
-	// Fill-level
-	reg  [AWIDTH:0] level;
-	(* keep="true" *) wire lvl_dec;
-	(* keep="true" *) wire lvl_mov;
-	wire lvl_empty;
-
-	// Full
-	wire full_nxt;
-	reg  full;
-
-	// Read logic
-	reg  rd_valid;
-
-
-	// Fill level counter
-	// ------------------
-	// (counts the number of used words - 1)
-
-	always @(posedge clk or posedge rst)
-		if (rst)
-			level <= {(AWIDTH+1){1'b1}};
-		else
-			level <= level + { {AWIDTH{lvl_dec}}, lvl_mov };
-
-	assign lvl_dec = ram_rd_ena & ~ram_wr_ena;
-	assign lvl_mov = ram_rd_ena ^  ram_wr_ena;
-	assign lvl_empty = level[AWIDTH];
-
-
-	// Full flag generation
-	// --------------------
-
-	assign full_nxt = level == { 1'b0, {(AWIDTH-2){1'b1}}, 2'b01 };
-
-	always @(posedge clk or posedge rst)
-		if (rst)
-			full <= 1'b0;
-		else
-			full <= (full | (wr_ena & ~rd_ena & full_nxt)) & ~(rd_ena & ~wr_ena);
-
-	assign wr_full = full;
-
-
-	// Write
-	// -----
-
-	always @(posedge clk or posedge rst)
-		if (rst)
-			ram_wr_addr <= 0;
-		else if (ram_wr_ena)
-			ram_wr_addr <= ram_wr_addr + 1;
-
-	assign ram_wr_data = wr_data;
-	assign ram_wr_ena  = wr_ena;
-
-
-	// Read
-	// ----
-
-	always @(posedge clk or posedge rst)
-		if (rst)
-			ram_rd_addr <= 0;
-		else if (ram_rd_ena)
-			ram_rd_addr <= ram_rd_addr + 1;
-
-	assign ram_rd_ena = (rd_ena | ~rd_valid) & ~lvl_empty;
-
-	always @(posedge clk or posedge rst)
-		if (rst)
-			rd_valid <= 1'b0;
-		else if (rd_ena | ~rd_valid)
-			rd_valid <= ~lvl_empty;
-
-	assign rd_data = ram_rd_data;
-	assign rd_empty = ~rd_valid;
-
-
-	// RAM
-	// ---
-
-	ram_sdp #(
-		.AWIDTH(AWIDTH),
-		.DWIDTH(WIDTH)
-	) ram_I (
-		.wr_addr(ram_wr_addr),
-		.wr_data(ram_wr_data),
-		.wr_ena(ram_wr_ena),
-		.rd_addr(ram_rd_addr),
-		.rd_data(ram_rd_data),
-		.rd_ena(ram_rd_ena),
-		.clk(clk)
-	);
-
-endmodule // fifo_sync_ram

cores/misc/rtl/fifo_sync_shift.v

@@ -1,113 +0,0 @@
-/*
- * fifo_sync_shift.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-module fifo_sync_shift #(
-	parameter integer DEPTH =  4,
-	parameter integer WIDTH = 16
-)(
-	input  wire [WIDTH-1:0] wr_data,
-	input  wire wr_ena,
-	output wire wr_full,
-
-	output wire [WIDTH-1:0] rd_data,
-	input  wire rd_ena,
-	output wire rd_empty,
-
-	input  wire clk,
-	input  wire rst
-);
-
-	// Signals
-	// -------
-
-	wire  [DEPTH+1:0] ce;
-	wire  [DEPTH+1:0] valid;
-	wire  [WIDTH-1:0] data [DEPTH+1:0];
-
-
-	// Stages
-	// ------
-
-	// Generate loop
-	genvar i;
-
-	generate
-		for (i=1; i<=DEPTH; i=i+1)
-		begin : stage
-			// Local signals
-			reg [WIDTH-1:0] l_data;
-			reg l_valid;
-
-			// Data register
-			always @(posedge clk)
-				if (ce[i])
-					l_data <= valid[i+1] ? data[i+1] : wr_data;
-
-			// Valid flag
-			always @(posedge clk or posedge rst)
-				if (rst)
-					l_valid <= 1'b0;
-				else if (ce[i])
-					l_valid <= ~rd_ena | valid[i+1] | (wr_ena & valid[i]);
-
-			// CE for this stage
-			assign ce[i] = rd_ena | (wr_ena & ~valid[i] & valid[i-1]);
-
-			// Map
-			assign data[i]  = l_data;
-			assign valid[i] = l_valid;
-		end
-	endgenerate
-
-	// Boundary conditions
-	assign data[DEPTH+1] = wr_data;
-	assign data[0] = { WIDTH{1'bx} };
-
-	assign valid[DEPTH+1] = 1'b0;
-	assign valid[0] = 1'b1;
-
-	assign ce[DEPTH+1] = 1'bx;
-	assign ce[0] = 1'bx;
-
-
-	// User IF
-	// -------
-
-	assign wr_full = valid[DEPTH];
-
-	assign rd_empty = ~valid[1];
-	assign rd_data  = data[1];
-
-endmodule // fifo_sync_shift

cores/misc/rtl/glitch_filter.v

@@ -1,105 +0,0 @@
-/*
- * glitch_filter.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-module glitch_filter #(
-	parameter integer L = 2
-)(
-	input wire  pin_iob_reg,
-	input wire  cond,
-
-	output wire val,
-	output reg  rise,
-	output reg  fall,
-
-	input  wire clk,
-	input  wire rst
-);
-	// Signals
-	wire [L-1:0] all_zero;
-	wire [L-1:0] all_one;
-
-	reg [1:0] sync;
-	reg state;
-	reg [L-1:0] cnt;
-
-	// Constants
-	assign all_zero = { L{1'b0} };
-	assign all_one  = { L{1'b1} };
-
-	// Synchronizer
-	always @(posedge clk)
-		sync <= { sync[0], pin_iob_reg };
-
-	// Filter
-	always @(posedge clk)
-		if (rst)
-			cnt <= all_one;
-		else begin
-			if (sync[1] & (cnt != all_one))
-				cnt <= cnt + 1;
-			else if (~sync[1] & (cnt != all_zero))
-				cnt <= cnt - 1;
-			else
-				cnt <= cnt;
-		end
-
-	// State
-	always @(posedge clk)
-		if (rst)
-			state <= 1'b1;
-		else begin
-			if (state & cnt == all_zero)
-				state <= 1'b0;
-			else if (~state & cnt == all_one)
-				state <= 1'b1;
-			else
-				state <= state;
-		end
-
-	assign val = state;
-
-	// Rise / Fall detection
-	always @(posedge clk)
-	begin
-		if (~cond) begin
-			rise <= 1'b0;
-			fall <= 1'b0;
-		end else begin
-			rise <= ~state & (cnt == all_one);
-			fall <=  state & (cnt == all_zero);
-		end
-	end
-
-endmodule // glitch_filter

cores/misc/rtl/pdm.v

@@ -1,163 +0,0 @@
-/*
- * pdm.v
- *
- * vim: ts=4 sw=4
- *
- * Pulse Density Modulation core (1st order with dither)
- *
- * Copyright (C) 2020  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-module pdm #(
-	parameter integer WIDTH = 8,
-	parameter DITHER = "NO",
-	parameter PHY = "GENERIC"
-)(
-	// PWM out
-	output wire pdm,
-
-	// Config
-	input  wire [WIDTH-1:0] cfg_val,
-	input  wire cfg_oe,
-
-	// Clock / Reset
-	input  wire clk,
-	input  wire rst
-);
-
-	// Signals
-	wire [WIDTH:0] inc;
-	reg  [WIDTH:0] acc;
-
-	reg  dither;
-
-	wire pdm_i;
-
-	// Delta Sigma
-	assign inc = { acc[WIDTH], cfg_val };
-
-	always @(posedge clk)
-	begin
-		if (rst)
-			acc <= 0;
-		else
-			acc <= acc + inc + dither;
-	end
-
-	assign pdm_i = acc[WIDTH];
-
-	// Dither generator
-	generate
-		if (DITHER == "YES") begin
-			// Dither using a simple LFSR
-			wire [7:0] lfsr_out;
-
-			pdm_lfsr #(
-				.WIDTH(8),
-				.POLY(8'h71)
-			) lfsr_I (
-				.out(lfsr_out),
-				.clk(clk),
-				.rst(rst)
-			);
-
-			always @(posedge clk)
-				dither <= lfsr_out[0] ^ lfsr_out[3];
-
-		end else begin
-			// No dither
-			always @(*)
-				dither = 1'b0;
-		end
-	endgenerate
-
-	// PHY (Basically just IO register)
-	generate
-		if (PHY == "NONE") begin
-			// No PHY (and no OE support)
-			assign pdm = pdm_i;
-		end else if (PHY == "GENERIC") begin
-			// Generic IO register, let tool figure it out
-			reg pdm_d_r;
-			reg pdm_oe_r;
-			always @(posedge clk)
-			begin
-				pdm_d_r  <= pdm_i;
-				pdm_oe_r <= cfg_oe;
-			end
-			assign pdm = pdm_oe_r ? pdm_d_r : 1'bz;
-		end else if (PHY == "ICE40") begin
-			// iCE40 specific IOB
-			SB_IO #(
-				.PIN_TYPE(6'b110100),
-				.PULLUP(1'b0),
-				.NEG_TRIGGER(1'b0),
-				.IO_STANDARD("SB_LVCMOS")
-			) io_reg_I (
-				.PACKAGE_PIN(pdm),
-				.LATCH_INPUT_VALUE(1'b0),
-				.CLOCK_ENABLE(1'b1),
-				.INPUT_CLK(1'b0),
-				.OUTPUT_CLK(clk),
-				.OUTPUT_ENABLE(cfg_oe),
-				.D_OUT_0(pdm_i),
-				.D_OUT_1(1'b0),
-				.D_IN_0(),
-				.D_IN_1()
-			);
-		end
-	endgenerate
-
-endmodule // pdm
-
-
-module pdm_lfsr #(
-	parameter integer WIDTH = 8,
-	parameter POLY = 8'h71
-)(
-	output reg  [WIDTH-1:0] out,
-	input  wire clk,
-	input  wire rst
- );
-
-	// Signals
-	wire fb;
-
-	// Linear Feedback
-	assign fb = ^(out & POLY);
-
-	// Register
-	always @(posedge clk)
-		if (rst)
-			out <= { {(WIDTH-1){1'b0}}, 1'b1 };
-		else
-			out <= { fb, out[WIDTH-1:1] };
-
-endmodule // pdm_lfsr

cores/misc/rtl/prims.v

@@ -1,291 +0,0 @@
-/*
- * prims.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-
-module lut4_n #(
-	parameter [15:0] LUT_INIT = 0,
-	parameter integer WIDTH  = 16,
-	parameter integer RBEL_X = 0,
-	parameter integer RBEL_Y = 0,
-	parameter integer RBEL_Z = 0,
-	parameter RBEL_GROUP = ""
-)(
-	input  wire [WIDTH-1:0] i0,
-	input  wire [WIDTH-1:0] i1,
-	input  wire [WIDTH-1:0] i2,
-	input  wire [WIDTH-1:0] i3,
-	output wire [WIDTH-1:0] o
-);
-
-	genvar i;
-	generate
-		for (i=0; i<WIDTH; i=i+1)
-		begin : bit
-			(* RBEL_X=RBEL_X *)
-			(* RBEL_Y=RBEL_Y+(RBEL_Z+i)>>3 *)
-			(* RBEL_Z=(RBEL_Z+i)&7 *)
-			(* RBEL_GROUP=RBEL_GROUP *)
-			SB_LUT4 #(
-				.LUT_INIT(LUT_INIT)
-			) lut_I (
-				.I0(i0[i]),
-				.I1(i1[i]),
-				.I2(i2[i]),
-				.I3(i3[i]),
-				.O(o[i])
-			);
-		end
-	endgenerate
-
-endmodule // lut4_n
-
-
-module lut4_carry_n #(
-	parameter [15:0] LUT_INIT = 0,
-	parameter integer WIDTH  = 16,
-	parameter integer RBEL_X = 0,
-	parameter integer RBEL_Y = 0,
-	parameter integer RBEL_Z = 0,
-	parameter RBEL_GROUP = ""
-)(
-	input  wire [WIDTH-1:0] i0,
-	input  wire [WIDTH-1:0] i1,
-	input  wire [WIDTH-1:0] i2,
-	input  wire cin,
-	output wire [WIDTH-1:0] o,
-	output wire cout
-);
-
-	wire [WIDTH:0] carry;
-
-	assign cout = carry[WIDTH];
-	assign carry[0] = cin;
-
-	genvar i;
-	generate
-		for (i=0; i<WIDTH; i=i+1)
-		begin : bit
-			(* RBEL_X=RBEL_X *)
-			(* RBEL_Y=RBEL_Y+(RBEL_Z+i)>>3 *)
-			(* RBEL_Z=(RBEL_Z+i)&7 *)
-			(* RBEL_GROUP=RBEL_GROUP *)
-			SB_LUT4 #(
-				.LUT_INIT(LUT_INIT)
-			) lut_I (
-				.I0(i0[i]),
-				.I1(i1[i]),
-				.I2(i2[i]),
-				.I3(carry[i]),
-				.O(o[i])
-			);
-
-			SB_CARRY carry_I (
-				.CO(carry[i+1]),
-				.I0(i0[i]),
-				.I1(i1[i]),
-				.CI(carry[i])
-			);
-		end
-	endgenerate
-
-endmodule // lut4_carry_n
-
-
-module dff_n #(
-	parameter integer WIDTH  = 16,
-	parameter integer RBEL_X = 0,
-	parameter integer RBEL_Y = 0,
-	parameter integer RBEL_Z = 0,
-	parameter RBEL_GROUP = ""
-)(
-	input  wire [WIDTH-1:0] d,
-	output wire [WIDTH-1:0] q,
-	input  wire clk
-);
-
-	genvar i;
-	generate
-		for (i=0; i<WIDTH; i=i+1)
-		begin : bit
-			(* RBEL_X=RBEL_X *)
-			(* RBEL_Y=RBEL_Y+(RBEL_Z+i)>>3 *)
-			(* RBEL_Z=(RBEL_Z+i)&7 *)
-			(* RBEL_GROUP=RBEL_GROUP *)
-			(* dont_touch="true" *)
-			SB_DFF dff_I (
-				.D(d[i]),
-				.Q(q[i]),
-				.C(clk)
-			);
-		end
-	endgenerate
-
-endmodule // dff_n
-
-
-module dffe_n #(
-	parameter integer WIDTH  = 16,
-	parameter integer RBEL_X = 0,
-	parameter integer RBEL_Y = 0,
-	parameter integer RBEL_Z = 0,
-	parameter RBEL_GROUP = ""
-)(
-	input  wire [WIDTH-1:0] d,
-	output wire [WIDTH-1:0] q,
-	input  wire ce,
-	input  wire clk
-);
-
-	genvar i;
-	generate
-		for (i=0; i<WIDTH; i=i+1)
-		begin : bit
-			(* RBEL_X=RBEL_X *)
-			(* RBEL_Y=RBEL_Y+((RBEL_Z+i)>>3) *)
-			(* RBEL_Z=(RBEL_Z+i)&7 *)
-			(* RBEL_GROUP=RBEL_GROUP *)
-			(* dont_touch="true" *)
-			SB_DFFE dff_I (
-				.D(d[i]),
-				.Q(q[i]),
-				.E(ce),
-				.C(clk)
-			);
-		end
-	endgenerate
-
-endmodule // dffe_n
-
-
-module dffer_n #(
-	parameter RSTVAL = 16'h0000,
-	parameter integer WIDTH  = 16,
-	parameter integer RBEL_X = 0,
-	parameter integer RBEL_Y = 0,
-	parameter integer RBEL_Z = 0,
-	parameter RBEL_GROUP = ""
-)(
-	input  wire [WIDTH-1:0] d,
-	output wire [WIDTH-1:0] q,
-	input  wire ce,
-	input  wire clk,
-	input  wire rst
-);
-
-	genvar i;
-	generate
-		for (i=0; i<WIDTH; i=i+1)
-		begin : bit
-			if (RSTVAL[i] == 1'b1)
-				(* RBEL_X=RBEL_X *)
-				(* RBEL_Y=RBEL_Y+((RBEL_Z+i)>>3) *)
-				(* RBEL_Z=(RBEL_Z+i)&7 *)
-				(* RBEL_GROUP=RBEL_GROUP *)
-				(* dont_touch="true" *)
-				SB_DFFES dff_I (
-					.D(d[i]),
-					.Q(q[i]),
-					.E(ce),
-					.S(rst),
-					.C(clk)
-				);
-			else
-				(* RBEL_X=RBEL_X *)
-				(* RBEL_Y=RBEL_Y+((RBEL_Z+i)>>3) *)
-				(* RBEL_Z=(RBEL_Z+i)&7 *)
-				(* RBEL_GROUP=RBEL_GROUP *)
-				(* dont_touch="true" *)
-				SB_DFFER dff_I (
-					.D(d[i]),
-					.Q(q[i]),
-					.E(ce),
-					.R(rst),
-					.C(clk)
-				);
-		end
-	endgenerate
-
-endmodule // dffer_n
-
-
-module dffesr_n #(
-	parameter RSTVAL = 16'h0000,
-	parameter integer WIDTH  = 16,
-	parameter integer RBEL_X = 0,
-	parameter integer RBEL_Y = 0,
-	parameter integer RBEL_Z = 0,
-	parameter RBEL_GROUP = ""
-)(
-	input  wire [WIDTH-1:0] d,
-	output wire [WIDTH-1:0] q,
-	input  wire ce,
-	input  wire clk,
-	input  wire rst
-);
-
-	genvar i;
-	generate
-		for (i=0; i<WIDTH; i=i+1)
-		begin : bit
-			if (RSTVAL[i] == 1'b1)
-				(* RBEL_X=RBEL_X *)
-				(* RBEL_Y=RBEL_Y+((RBEL_Z+i)>>3) *)
-				(* RBEL_Z=(RBEL_Z+i)&7 *)
-				(* RBEL_GROUP=RBEL_GROUP *)
-				(* dont_touch="true" *)
-				SB_DFFESS dff_I (
-					.D(d[i]),
-					.Q(q[i]),
-					.E(ce),
-					.S(rst),
-					.C(clk)
-				);
-			else
-				(* RBEL_X=RBEL_X *)
-				(* RBEL_Y=RBEL_Y+((RBEL_Z+i)>>3) *)
-				(* RBEL_Z=(RBEL_Z+i)&7 *)
-				(* RBEL_GROUP=RBEL_GROUP *)
-				(* dont_touch="true" *)
-				SB_DFFESR dff_I (
-					.D(d[i]),
-					.Q(q[i]),
-					.E(ce),
-					.R(rst),
-					.C(clk)
-				);
-		end
-	endgenerate
-
-endmodule // dffesr_n

cores/misc/rtl/pwm.v

@@ -1,112 +0,0 @@
-/*
- * pwm.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2020  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-module pwm #(
-	parameter integer WIDTH = 10,
-	parameter PHY = "GENERIC"
-)(
-	// PWM out
-	output wire pwm,
-
-	// Config
-	input  wire [WIDTH-1:0] cfg_val,
-	input  wire cfg_oe,
-
-	// Clock / Reset
-	input  wire  clk,
-	input  wire  rst
-);
-	// Signals
-	wire [WIDTH:0] cnt_cycle_rst;
-	reg  [WIDTH:0] cnt_cycle;
-	reg  [WIDTH:0] cnt_on;
-	wire pwm_i;
-
-	// Cycle counter (counts 2^WIDTH - 1 cycles)
-	assign cnt_cycle_rst = { { (WIDTH-1){1'b0} }, 2'b10 };
-
-	always @(posedge clk or posedge rst)
-		if (rst)
-			cnt_cycle <= cnt_cycle_rst;
-		else
-			cnt_cycle <= cnt_cycle[WIDTH] ? cnt_cycle_rst : (cnt_cycle + 1);
-
-	// ON counter (counts cycles with output high)
-	always @(posedge clk or posedge rst)
-		if (rst)
-			cnt_on <= 0;
-		else
-			cnt_on <= cnt_cycle[WIDTH] ? { 1'b1, cfg_val } : (cnt_on - 1);
-
-	assign pwm_i = cnt_on[WIDTH];
-
-	// PHY (Basically just IO register)
-	generate
-		if (PHY == "NONE") begin
-			// No PHY (and no OE support)
-			assign pwm = pwm_i;
-		end else if (PHY == "GENERIC") begin
-			// Generic IO register, let tool figure it out
-			reg pwm_d_r;
-			reg pwm_oe_r;
-			always @(posedge clk)
-			begin
-				pwm_d_r  <= pwm_i;
-				pwm_oe_r <= cfg_oe;
-			end
-			assign pwm = pwm_oe_r ? pwm_d_r : 1'bz;
-		end else if (PHY == "ICE40") begin
-			// iCE40 specific IOB
-			SB_IO #(
-				.PIN_TYPE(6'b110100),
-				.PULLUP(1'b0),
-				.NEG_TRIGGER(1'b0),
-				.IO_STANDARD("SB_LVCMOS")
-			) io_reg_I (
-				.PACKAGE_PIN(pwm),
-				.LATCH_INPUT_VALUE(1'b0),
-				.CLOCK_ENABLE(1'b1),
-				.INPUT_CLK(1'b0),
-				.OUTPUT_CLK(clk),
-				.OUTPUT_ENABLE(cfg_oe),
-				.D_OUT_0(pwm_i),
-				.D_OUT_1(1'b0),
-				.D_IN_0(),
-				.D_IN_1()
-			);
-		end
-	endgenerate
-
-endmodule // pwm

cores/misc/rtl/ram_sdp.v

@@ -1,71 +0,0 @@
-/*
- * ram_sdp.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-module ram_sdp #(
-	parameter integer AWIDTH = 9,
-	parameter integer DWIDTH = 8
-)(
-	input  wire [AWIDTH-1:0] wr_addr,
-	input  wire [DWIDTH-1:0] wr_data,
-	input  wire wr_ena,
-
-	input  wire [AWIDTH-1:0] rd_addr,
-	output reg  [DWIDTH-1:0] rd_data,
-	input  wire rd_ena,
-
-	input  wire clk
-);
-	// Signals
-	reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
-
-`ifdef SIM
-	integer i;
-	initial
-		for (i=0; i<(1<<AWIDTH); i=i+1)
-			ram[i] = 0;
-`endif
-
-	always @(posedge clk)
-	begin
-		// Read
-		if (rd_ena)
-			rd_data <= ram[rd_addr];
-
-		// Write
-		if (wr_ena)
-			ram[wr_addr] <= wr_data;
-	end
-
-endmodule // ram_sdp

cores/misc/rtl/uart_rx.v

@@ -1,128 +0,0 @@
-/*
- * uart_rx.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-module uart_rx #(
-	parameter integer DIV_WIDTH = 8,
-	parameter integer GLITCH_FILTER = 2
-)(
-	input  wire rx,
-	output wire [7:0] data,
-	output reg  stb,
-	input  wire [DIV_WIDTH-1:0] div,	// div - 2
-	input  wire clk,
-	input  wire rst
-);
-	// Signals
-	wire rx_val;
-	wire rx_fall;
-
-	wire go, done, ce;
-	reg  active;
-	reg [DIV_WIDTH:0] div_cnt;
-	reg [4:0] bit_cnt;
-	reg [8:0] shift;
-
-	// Input stage (synchronizer / de-glitch / change detect)
-	generate
-		// Glitch filter
-		if (GLITCH_FILTER > 0)
-			glitch_filter #(
-				.L(GLITCH_FILTER)
-			) gf_I (
-				.pin_iob_reg(rx),
-				.cond(1'b1),
-				.val(rx_val),
-				.rise(),
-				.fall(rx_fall),
-				.clk(clk),
-				.rst(rst)
-			);
-
-		// Or simple synchronizer
-		else begin
-			reg [1:0] rx_sync;
-			reg rx_fd;
-
-			always @(posedge clk)
-			begin
-				rx_sync <= { rx_sync[0], rx };
-				rx_fd   <= rx_sync[1] & ~rx_sync[0];
-			end
-
-			assign rx_fall = rx_fd;
-			assign rx_val  = rx_sync[1];
-		end
-	endgenerate
-
-	// Control
-	assign go = rx_fall & ~active;
-	assign done = ce & bit_cnt[4];
-
-	always @(posedge clk or posedge rst)
-		if (rst)
-			active <= 1'b0;
-		else
-			active <= (active & ~done) | go;
-
-	// Baud rate generator
-	always @(posedge clk)
-		if (~active)
-			div_cnt <= { 2'b00, div[DIV_WIDTH-1:1] } - 1;
-		else if (div_cnt[DIV_WIDTH])
-			div_cnt <= { 1'b0, div };
-		else
-			div_cnt <= div_cnt - 1;
-
-	assign ce = div_cnt[DIV_WIDTH];
-
-	// Bit counter
-	always @(posedge clk)
-		if (~active)
-			bit_cnt <= 5'h08;
-		else if (ce)
-			bit_cnt <= bit_cnt - 1;
-
-	// Shift register
-	always @(posedge clk)
-		if (ce)
-			shift <= { rx_val, shift[8:1] };
-
-	// Outputs
-	assign data = shift[7:0];
-
-	always @(posedge clk)
-		stb <= ce & bit_cnt[4] & rx_val;
-
-endmodule // uart_rx

cores/misc/rtl/uart_tx.v

@@ -1,96 +0,0 @@
-/*
- * uart_tx.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-module uart_tx #(
-	parameter integer DIV_WIDTH = 8
-)(
-	output wire tx,
-	input  wire [7:0] data,
-	input  wire valid,
-	output reg  ack,
-	input  wire [DIV_WIDTH-1:0] div,	// div - 2
-	input  wire clk,
-	input  wire rst
-);
-
-	// Signals
-	wire go, done, ce;
-	reg  active;
-	reg [9:0] shift;
-	reg [DIV_WIDTH:0] div_cnt;
-	reg [4:0] bit_cnt;
-
-	// Control
-	assign go = valid & ~active;
-	assign done = ce & bit_cnt[4];
-
-	always @(posedge clk or posedge rst)
-		if (rst)
-			active <= 1'b0;
-		else
-			active <= (active & ~done) | go;
-
-	// Baud rate generator
-	always @(posedge clk)
-		if (~active | div_cnt[DIV_WIDTH])
-			div_cnt <= { 1'b0, div };
-		else
-			div_cnt <= div_cnt - 1;
-
-	assign ce = div_cnt[DIV_WIDTH];
-
-	// Bit counter
-	always @(posedge clk)
-		if (~active)
-			bit_cnt <= 5'h08;
-		else if (ce)
-			bit_cnt <= bit_cnt - 1;
-
-	// Shift register
-	always @(posedge clk or posedge rst)
-		if (rst)
-			shift <= 10'h3ff;
-		else if (go)
-			shift <= { 1'b1, data, 1'b0 };
-		else if (ce)
-			shift <= { 1'b1, shift[9:1] };
-
-	// Outputs
-	always @(posedge clk)
-		ack <= go;
-
-	assign tx = shift[0];
-
-endmodule // uart_tx

cores/misc/rtl/uart_wb.v

@@ -1,230 +0,0 @@
-/*
- * uart_wb.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-module uart_wb #(
-	parameter integer DIV_WIDTH = 8,
-	parameter integer DW = 16
-)(
-	// UART
-	output wire uart_tx,
-	input  wire uart_rx,
-
-	// Bus interface
-	input  wire [1:0] bus_addr,
-	input  wire [DW-1:0] bus_wdata,
-	output wire [DW-1:0] bus_rdata,
-	input  wire bus_cyc,
-	output wire bus_ack,
-	input  wire bus_we,
-
-	// Clock / Reset
-	input  wire clk,
-	input  wire rst
-);
-
-	// Signals
-	// -------
-
-	// RX fifo
-	wire [ 7:0] urf_wdata;
-	wire        urf_wren;
-	wire        urf_full;
-	wire [ 7:0] urf_rdata;
-	wire        urf_rden;
-	wire        urf_empty;
-
-	reg         urf_overflow;
-	wire        urf_overflow_clr;
-
-	// TX fifo
-	wire [ 7:0] utf_wdata;
-	wire        utf_wren;
-	wire        utf_full;
-	wire [ 7:0] utf_rdata;
-	wire        utf_rden;
-	wire        utf_empty;
-
-	// TX core
-	wire [ 7:0] uart_tx_data;
-	wire        uart_tx_valid;
-	wire        uart_tx_ack;
-
-	// RX core
-	wire [ 7:0] uart_rx_data;
-	wire        uart_rx_stb;
-
-	// CSR
-	reg  [DIV_WIDTH-1:0] uart_div;
-
-	// Bus IF
-	wire          ub_rdata_rst;
-	reg  [DW-1:0] ub_rdata;
-	reg           ub_rd_data;
-	reg           ub_rd_ctrl;
-	reg           ub_wr_data;
-	reg           ub_wr_div;
-	reg           ub_ack;
-
-
-	// TX Core
-	// -------
-
-	uart_tx #(
-		.DIV_WIDTH(DIV_WIDTH)
-	) uart_tx_I (
-		.data(uart_tx_data),
-		.valid(uart_tx_valid),
-		.ack(uart_tx_ack),
-		.tx(uart_tx),
-		.div(uart_div),
-		.clk(clk),
-		.rst(rst)
-	);
-
-
-	// TX FIFO
-	// -------
-
-	fifo_sync_ram #(
-		.DEPTH(512),
-		.WIDTH(8)
-	) uart_tx_fifo_I (
-		.wr_data(utf_wdata),
-		.wr_ena(utf_wren),
-		.wr_full(utf_full),
-		.rd_data(utf_rdata),
-		.rd_ena(utf_rden),
-		.rd_empty(utf_empty),
-		.clk(clk),
-		.rst(rst)
-	);
-
-	// TX glue
-	assign uart_tx_data  =  utf_rdata;
-	assign uart_tx_valid = ~utf_empty;
-	assign utf_rden      =  uart_tx_ack;
-
-
-	// RX Core
-	// -------
-
-	uart_rx #(
-		.DIV_WIDTH(DIV_WIDTH),
-		.GLITCH_FILTER(2)
-	) uart_rx_I (
-		.rx(uart_rx),
-		.data(uart_rx_data),
-		.stb(uart_rx_stb),
-		.div(uart_div),
-		.clk(clk),
-		.rst(rst)
-	);
-
-
-	// RX FIFO
-	// -------
-
-	fifo_sync_ram #(
-		.DEPTH(512),
-		.WIDTH(8)
-	) uart_rx_fifo_I (
-		.wr_data(urf_wdata),
-		.wr_ena(urf_wren),
-		.wr_full(urf_full),
-		.rd_data(urf_rdata),
-		.rd_ena(urf_rden),
-		.rd_empty(urf_empty),
-		.clk(clk),
-		.rst(rst)
-	);
-
-	// RX glue
-	assign urf_wdata = uart_rx_data;
-	assign urf_wren  = uart_rx_stb & ~urf_full;
-
-	// Overflow
-	always @(posedge clk or posedge rst)
-		if (rst)
-			urf_overflow <= 1'b0;
-		else
-			urf_overflow <= (urf_overflow & ~urf_overflow_clr) | (uart_rx_stb & urf_full);
-
-
-	// Bus interface
-	// -------------
-
-	always @(posedge clk)
-		if (ub_ack) begin
-			ub_rd_data <= 1'b0;
-			ub_rd_ctrl <= 1'b0;
-			ub_wr_data <= 1'b0;
-			ub_wr_div  <= 1'b0;
-		end else begin
-			ub_rd_data <= ~bus_we & bus_cyc & (bus_addr == 2'b00);
-			ub_rd_ctrl <= ~bus_we & bus_cyc & (bus_addr == 2'b01);
-			ub_wr_data <=  bus_we & bus_cyc & (bus_addr == 2'b00) & ~utf_full;
-			ub_wr_div  <=  bus_we & bus_cyc & (bus_addr == 2'b01);
-		end
-
-	always @(posedge clk)
-		if (ub_ack)
-			ub_ack <= 1'b0;
-		else
-			ub_ack <= bus_cyc & (~bus_we | (bus_addr == 2'b01) | ~utf_full);
-
-	assign ub_rdata_rst = ub_ack | bus_we | ~bus_cyc;
-
-	always @(posedge clk)
-		if (ub_rdata_rst)
-			ub_rdata <= { DW{1'b0} };
-		else
-			ub_rdata <= bus_addr[0] ?
-				{ urf_empty, urf_overflow, utf_empty, utf_full, { (DW-DIV_WIDTH-4){1'b0} }, uart_div } :
-				{ urf_empty, { (DW-9){1'b0} }, urf_rdata };
-
-	always @(posedge clk)
-		if (ub_wr_div)
-			uart_div <= bus_wdata[DIV_WIDTH-1:0];
-
-	assign utf_wdata = bus_wdata[7:0];
-	assign utf_wren  = ub_wr_data;
-
-	assign urf_rden  = ub_rd_data & ~ub_rdata[DW-1];
-	assign urf_overflow_clr = ub_rd_ctrl & ub_rdata[DW-2];
-
-	assign bus_rdata = ub_rdata;
-	assign bus_ack = ub_ack;
-
-endmodule // uart_wb

cores/misc/rtl/xclk_strobe.v

@@ -1,65 +0,0 @@
-/*
- * xclk_strobe.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-module xclk_strobe (
-	input  wire in_stb,
-	input  wire in_clk,
-	output reg  out_stb,
-	input  wire out_clk,
-	input  wire rst
-);
-
-	reg src;
-	reg [1:0] dst;
-
-	always @(posedge in_clk or posedge rst)
-		if (rst)
-			src <= 1'b0;
-		else
-			src <= src ^ in_stb;
-
-	always @(posedge out_clk or posedge rst)
-		if (rst)
-			dst <= 2'b00;
-		else
-			dst <= { dst[0], src };
-
-	always @(posedge out_clk or posedge rst)
-		if (rst)
-			out_stb <= 1'b0;
-		else
-			out_stb <= ^dst[1:0];
-
-endmodule

cores/misc/rtl/xclk_wb.v

@@ -1,139 +0,0 @@
-/*
- * xclk_wb.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-
-module xclk_wb #(
-	parameter integer DW = 16,
-	parameter integer AW = 16
-)(
-	// Slave bus interface
-	input  wire [AW-1:0] s_addr,
-	input  wire [DW-1:0] s_wdata,
-	output reg  [DW-1:0] s_rdata,
-	input  wire s_cyc,
-	output wire s_ack,
-	input  wire s_we,
-	input  wire s_clk,
-
-	// Master bus interface
-	output wire [AW-1:0] m_addr,
-	output wire [DW-1:0] m_wdata,
-	input  wire [DW-1:0] m_rdata,
-	output wire m_cyc,
-	input  wire m_ack,
-	output wire m_we,
-	input  wire m_clk,
-
-	// Reset
-	input  wire rst
-);
-
-	// Signals
-	// -------
-
-	reg  s_cyc_d;
-	reg  m_cyc_i;
-
-	wire s_req_i;
-	wire m_req_i;
-
-	wire s_ack_i;
-	reg  s_ack_d;
-	reg  m_ack_i;
-
-	reg [DW-1:0] m_rdata_i;
-
-
-	// Data and address
-	// ----------------
-
-		// These will have settled down for some time while we pass around
-		// the handshake signals, so we can just connect them
-		// Ideally we'd still need a maxdelay constraint between clock domains
-
-	assign m_addr = s_addr;
-	assign m_wdata  = s_wdata;
-	assign m_we   = s_we;
-
-		// Still need to capture data during ack
-	always @(posedge m_clk)
-		if (m_ack)
-			m_rdata_i <= m_rdata;
-
-		// ... and ensure its zero cycle-accurately
-	always @(posedge s_clk)
-		if (s_ack_i || ~s_cyc)
-			s_rdata <= 0;
-		else
-			s_rdata <= m_rdata_i;
-
-
-	// Handshake
-	// ---------
-
-	always @(posedge s_clk)
-	begin
-		s_cyc_d <= s_cyc;
-		s_ack_d <= s_ack_i;
-	end
-
-	assign s_req_i = s_cyc & (~s_cyc_d | s_ack_d);
-
-	xclk_strobe xclk_req (
-		.in_stb(s_req_i),
-		.in_clk(s_clk),
-		.out_stb(m_req_i),
-		.out_clk(m_clk),
-		.rst(rst)
-	);
-
-	always @(posedge m_clk or posedge rst)
-		if (rst)
-			m_cyc_i <= 1'b0;
-		else
-			m_cyc_i <= (m_cyc_i | m_req_i) & ~m_ack;
-
-	assign m_cyc = m_cyc_i;
-
-	xclk_strobe xclk_ack (
-		.in_stb(m_ack),
-		.in_clk(m_clk),
-		.out_stb(s_ack_i),
-		.out_clk(s_clk),
-		.rst(rst)
-	);
-
-	assign s_ack = s_ack_i;
-
-endmodule

cores/misc/sim/fifo_tb.v

@@ -1,102 +0,0 @@
-/*
- * fifo_tb.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-`timescale 1ns / 100ps
-
-module fifo_tb;
-
-	// Signals
-	reg rst = 1'b1;
-	reg clk = 1'b0;
-
-	wire [7:0] wr_data;
-	wire wr_ena;
-	wire wr_full;
-
-	wire [7:0] rd_data;
-	wire rd_ena;
-	wire rd_empty;
-
-	// Setup recording
-	initial begin
-		$dumpfile("fifo_tb.vcd");
-		$dumpvars(0,fifo_tb);
-	end
-
-	// Reset pulse
-	initial begin
-		# 200 rst = 0;
-		# 1000000 $finish;
-	end
-
-	// Clocks
-	always #10 clk = !clk;
-
-	// DUT
-//	fifo_sync_shift #(
-	fifo_sync_ram #(
-		.DEPTH(4),
-		.WIDTH(8)
-	) dut_I (
-		.wr_data(wr_data),
-		.wr_ena(wr_ena),
-		.wr_full(wr_full),
-		.rd_data(rd_data),
-		.rd_ena(rd_ena),
-		.rd_empty(rd_empty),
-		.clk(clk),
-		.rst(rst)
-	);
-
-	// Data generateion
-	reg [7:0] cnt;
-	reg rnd_rd;
-	reg rnd_wr;
-
-	always @(posedge clk)
-		if (rst) begin
-			cnt <= 8'h00;
-			rnd_rd <= 1'b0;
-			rnd_wr <= 1'b0;
-		end else begin
-			cnt <= cnt + wr_ena;
-			rnd_rd <= $random;
-			rnd_wr <= $random;
-		end
-
-	assign wr_data = wr_ena ? cnt : 8'hxx;
-	assign wr_ena = rnd_wr & ~wr_full;
-	assign rd_ena = rnd_rd & ~rd_empty;
-
-endmodule // fifo_tb

cores/misc/sim/pdm_tb.v

@@ -1,81 +0,0 @@
-/*
- * pdm_tb.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-`timescale 1ns / 100ps
-
-module pdm_tb;
-
-	// Signals
-	reg rst = 1;
-	reg clk = 1;
-
-	reg [7:0] data;
-	wire pdm;
-
-	// Setup recording
-	initial begin
-		$dumpfile("pdm_tb.vcd");
-		$dumpvars(0,pdm_tb);
-	end
-
-	// Reset pulse
-	initial begin
-		# 31 rst = 0;
-		# 20000 $finish;
-	end
-
-	// Clocks
-	always #5 clk = !clk;
-
-	// DUT
-	pdm #(
-		.WIDTH(12),
-		.DITHER("ON"),
-		.PHY("ICE40")
-	) dut_I (
-		.pdm(pdm),
-		.cfg_val({data[7:4],data}),
-		.cfg_oe(1'b1),
-		.clk(clk),
-		.rst(rst)
-	);
-
-	initial begin
-		#0		data <= 8'hc1;
-		#5000	data <= 8'h10;
-		#5000	data <= 8'hf0;
-		#5000	data <= 8'h80;
-	end
-
-endmodule // pdm_tb

cores/misc/sim/uart_tb.v

@@ -1,102 +0,0 @@
-/*
- * uart_tb.v
- *
- * vim: ts=4 sw=4
- *
- * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
- * All rights reserved.
- *
- * BSD 3-clause, see LICENSE.bsd
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of the <organization> nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-`default_nettype none
-`timescale 1ns / 100ps
-
-module uart_tb;
-
-	// Signals
-	reg rst = 1'b1;
-	reg clk_rx = 1'b0;
-	reg clk_tx = 1'b0;
-
-	wire serial;
-
-	reg  [7:0] tx_data;
-	wire tx_valid;
-	wire tx_ack;
-
-	wire [7:0] rx_data;
-	wire rx_stb;
-
-	// Setup recording
-	initial begin
-		$dumpfile("uart_tb.vcd");
-		$dumpvars(0,uart_tb);
-	end
-
-	// Reset pulse
-	initial begin
-		# 200 rst = 0;
-		# 1000000 $finish;
-	end
-
-	// Clocks
-	always #10.4 clk_rx = !clk_rx;
-	always #10.0 clk_tx = !clk_tx;
-
-	// DUT
-	uart_tx #(
-		.DIV_WIDTH(4)
-	) dut_tx_I (
-		.tx(serial),
-		.data(tx_data),
-		.valid(tx_valid),
-		.ack(tx_ack),
-		.div(4'h3),
-		.clk(clk_tx),
-		.rst(rst)
-	);
-
-	uart_rx #(
-		.DIV_WIDTH(4),
-		.GLITCH_FILTER(2)
-	) dut_rx_I (
-		.rx(serial),
-		.data(rx_data),
-		.stb(rx_stb),
-		.div(4'h3),
-		.clk(clk_rx),
-		.rst(rst)
-	);
-
-	always @(posedge clk_tx)
-		if (rst)
-			tx_data <= 8'h00;
-		else if (tx_ack)
-			tx_data <= tx_data + 1;
-
-	assign tx_valid = ~rst;
-
-endmodule // uart_tb

cores/no2misc

@@ -0,0 +1 @@
+Subproject commit d7e0208ac11637baf1d004aa13b0570a013aff14