Increase the internal registers to 32 bits for WB compatibility.

Signed-off-by: Jakub Duchniewicz <j.duchniewicz@gmail.com>

projects/riscv_usb/rtl/mailbox_wb.v

@@ -11,7 +11,7 @@
 
 module mailbox_wb #(
     parameter AW = 4,  // Address width for 16 registers (4 bits)
-    parameter DW = 16   // Data width for each register (16 bits)
+    parameter DW = 32   // Data width for the Wishbone interface (32 bits)
 )(
     input  wire             clk,
     input  wire             rst,
@@ -24,11 +24,11 @@ module mailbox_wb #(
     output reg              wb_ack,
 
     // Flattened custom hardware side (RTL)
-    output wire [DW*16-1:0] registers_flat  // Flattened register array (16 registers of 16 bits each)
+    output wire [16*DW-1:0]     registers_flat  // Flattened register array (16 registers of 16 bits each)
 );
 
-    // Internal registers (flattened version)
-    reg [DW-1:0] registers_array[15:0];  // 16 registers, each 16 bits wide
+    // Internal registers (16 registers, each 16 bits wide)
+    reg [15:0] registers_array[15:0];
 
     // Always reset the registers on reset signal
     integer i;
@@ -36,7 +36,7 @@ module mailbox_wb #(
         if (rst) begin
             wb_ack <= 1'b0;
             for (i = 0; i < 16; i = i + 1) begin
-                registers_array[i] <= {DW{1'b0}}; // Reset all registers to 0
+                registers_array[i] <= 16'h0; // Reset all registers to 0
             end
         end else begin
             // Handle Wishbone communication
@@ -45,44 +45,44 @@ module mailbox_wb #(
             // Write operation (if write enable is active)
             if (wb_we && wb_cyc) begin
                 case (wb_addr)
-                    4'b0000: registers_array[0] <= wb_wdata;
-                    4'b0001: registers_array[1] <= wb_wdata;
-                    4'b0010: registers_array[2] <= wb_wdata;
-                    4'b0011: registers_array[3] <= wb_wdata;
-                    4'b0100: registers_array[4] <= wb_wdata;
-                    4'b0101: registers_array[5] <= wb_wdata;
-                    4'b0110: registers_array[6] <= wb_wdata;
-                    4'b0111: registers_array[7] <= wb_wdata;
-                    4'b1000: registers_array[8] <= wb_wdata;
-                    4'b1001: registers_array[9] <= wb_wdata;
-                    4'b1010: registers_array[10] <= wb_wdata;
-                    4'b1011: registers_array[11] <= wb_wdata;
-                    4'b1100: registers_array[12] <= wb_wdata;
-                    4'b1101: registers_array[13] <= wb_wdata;
-                    4'b1110: registers_array[14] <= wb_wdata;
-                    4'b1111: registers_array[15] <= wb_wdata;
+                    4'b0000: registers_array[0] <= wb_wdata[15:0]; // Only use lower 16 bits
+                    4'b0001: registers_array[1] <= wb_wdata[15:0];
+                    4'b0010: registers_array[2] <= wb_wdata[15:0];
+                    4'b0011: registers_array[3] <= wb_wdata[15:0];
+                    4'b0100: registers_array[4] <= wb_wdata[15:0];
+                    4'b0101: registers_array[5] <= wb_wdata[15:0];
+                    4'b0110: registers_array[6] <= wb_wdata[15:0];
+                    4'b0111: registers_array[7] <= wb_wdata[15:0];
+                    4'b1000: registers_array[8] <= wb_wdata[15:0];
+                    4'b1001: registers_array[9] <= wb_wdata[15:0];
+                    4'b1010: registers_array[10] <= wb_wdata[15:0];
+                    4'b1011: registers_array[11] <= wb_wdata[15:0];
+                    4'b1100: registers_array[12] <= wb_wdata[15:0];
+                    4'b1101: registers_array[13] <= wb_wdata[15:0];
+                    4'b1110: registers_array[14] <= wb_wdata[15:0];
+                    4'b1111: registers_array[15] <= wb_wdata[15:0];
                 endcase
             end
 
             // Read operation (read the correct register based on address)
             case (wb_addr)
-                4'b0000: wb_rdata <= registers_array[0];
-                4'b0001: wb_rdata <= registers_array[1];
-                4'b0010: wb_rdata <= registers_array[2];
-                4'b0011: wb_rdata <= registers_array[3];
-                4'b0100: wb_rdata <= registers_array[4];
-                4'b0101: wb_rdata <= registers_array[5];
-                4'b0110: wb_rdata <= registers_array[6];
-                4'b0111: wb_rdata <= registers_array[7];
-                4'b1000: wb_rdata <= registers_array[8];
-                4'b1001: wb_rdata <= registers_array[9];
-                4'b1010: wb_rdata <= registers_array[10];
-                4'b1011: wb_rdata <= registers_array[11];
-                4'b1100: wb_rdata <= registers_array[12];
-                4'b1101: wb_rdata <= registers_array[13];
-                4'b1110: wb_rdata <= registers_array[14];
-                4'b1111: wb_rdata <= registers_array[15];
-                default: wb_rdata <= {DW{1'b0}}; // Default error value
+                4'b0000: wb_rdata <= {16'h0, registers_array[0]}; // Place 16-bit value in lower half of 32-bit bus
+                4'b0001: wb_rdata <= {16'h0, registers_array[1]};
+                4'b0010: wb_rdata <= {16'h0, registers_array[2]};
+                4'b0011: wb_rdata <= {16'h0, registers_array[3]};
+                4'b0100: wb_rdata <= {16'h0, registers_array[4]};
+                4'b0101: wb_rdata <= {16'h0, registers_array[5]};
+                4'b0110: wb_rdata <= {16'h0, registers_array[6]};
+                4'b0111: wb_rdata <= {16'h0, registers_array[7]};
+                4'b1000: wb_rdata <= {16'h0, registers_array[8]};
+                4'b1001: wb_rdata <= {16'h0, registers_array[9]};
+                4'b1010: wb_rdata <= {16'h0, registers_array[10]};
+                4'b1011: wb_rdata <= {16'h0, registers_array[11]};
+                4'b1100: wb_rdata <= {16'h0, registers_array[12]};
+                4'b1101: wb_rdata <= {16'h0, registers_array[13]};
+                4'b1110: wb_rdata <= {16'h0, registers_array[14]};
+                4'b1111: wb_rdata <= {16'h0, registers_array[15]};
+                default: wb_rdata <= 32'hDEAD_BEEF; // Default error value
             endcase
         end
     end
@@ -91,9 +91,8 @@ module mailbox_wb #(
     generate
         genvar j;
         for (j = 0; j < 16; j = j + 1) begin : flatten
-            assign registers_flat[DW*(j+1)-1:DW*j] = registers_array[j];
+            assign registers_flat[16*(j+1)-1:16*j] = registers_array[j];
         end
     endgenerate
 
 endmodule
-