This wasn't updated to properly reflect the actual bitdepth Thanks to @kbob for pointing it out. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
@@ -59,7 +59,7 @@ module vgen #(
input wire fbw_row_rdy,
output wire fbw_row_swap,
- output wire [23:0] fbw_data,
+ output wire [BITDEPTH-1:0] fbw_data,
output wire [LOG_N_COLS-1:0] fbw_col_addr,
output wire fbw_wren,
@@ -54,7 +54,7 @@ module vstream #(