freq increase voodoo

projects/riscv_usb/rtl/3signal.v

@@ -96,8 +96,8 @@ module compare_gt#(
     wire [WIDTH_DIV4-1:0] B0_pt0, B0_pt1, B0_pt2;
     wire [WIDTH_REM-1:0] B0_pt3;
 
-    assign {A0_pt3, A0_pt2, A0_pt1, A0_pt0} = A;
-    assign {B0_pt3, B0_pt2, B0_pt1, B0_pt0} = B;
+    assign {A0_pt3, A0_pt2, A0_pt1, A0_pt0} = Ab;
+    assign {B0_pt3, B0_pt2, B0_pt1, B0_pt0} = Bb;
 
     reg pt0_gt, pt1_gt, pt2_gt, pt3_gt;
     reg pt0_eq, pt1_eq, pt2_eq, pt3_eq;
@@ -105,8 +105,12 @@ module compare_gt#(
     reg pt01_eq, pt23_eq;
     reg pt01_gt, pt23_gt;
 
+    reg [WIDTH-1:0] Ab, Bb; // buffer regs for shorter wires
 
     always @(posedge clk) begin
+        Ab <= A;
+        Bb <= B;
+
         pt0_gt <= A0_pt0>B0_pt0;
         pt1_gt <= A0_pt1>B0_pt1;
         pt2_gt <= A0_pt2>B0_pt2;
@@ -276,43 +280,38 @@ endmodule*/
 module single_shot_gen#(
     parameter WIDTH = 16
 )(
-    input wire nrst, clk,
+    input wire nrst,clk,
     input wire trigger,
     input [WIDTH-1:0] delay,
     input [WIDTH-1:0] period,
-
-    output reg [0:0] pwm_out
+    output reg pwm_out
 );
-    reg [WIDTH:0] counter;
-    reg [WIDTH:0] counter2;
-
+    reg [WIDTH-1:0] counter;
+    reg [WIDTH-1:0] counter2; // Buffer register for better timing
     wire pwm_gt;
 
-    //reg [0:0] is_counting;
-    //reg [WIDTH-1:0] next_cnt;
-    //reg [WIDTH-1:0] period;
-    //wire [WIDTH-1:0] last_avail_cnt=period-1;
-
-    always @(posedge clk /*or negedge nrst*/) begin
+    always @(posedge clk) begin
         if (trigger) begin
-            counter <= {1'b0,period};
+            counter <= period; //########TODO WARNING: counter will underflow which may trigger unwanted pulses. Add logic to fix that.
         end else begin
-            counter <= counter-1;
+            counter <= counter - 1;
         end
 
+        // Buffer register to reduce timing pressure
         counter2 <= counter;
 
-        pwm_out <= pwm_gt & !counter2[WIDTH];
+        // Output register to reduce delay
+        pwm_out <= pwm_gt;
     end
 
-    compare_gt#(.WIDTH(WIDTH))cmp_out(
+    // Parallel comparison with buffered counter
+    compare_gt #(.WIDTH(WIDTH)) cmp_out (
         .clk(clk),
         .A(delay),
-        .B(counter2[WIDTH-1:0]),
+        .B(counter2),
         .was_gt(pwm_gt)
     );
 
-
 endmodule
 
 /*module phase_delay#(