projects/riscv_usb: Reformat UART peripheral instance

Just formatting fixes, no functional changes

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

projects/riscv_usb/rtl/top.v

@@ -135,23 +135,23 @@ module top (
 
 
 
-	// UART
+	// UART [1]
 	// ----
 
 	uart_wb #(
 		.DIV_WIDTH(12),
 		.DW(WB_DW)
 	) uart_I (
-		.uart_tx(uart_tx),
-		.uart_rx(uart_rx),
-		.wb_addr(wb_addr[1:0]),
-		.wb_rdata(wb_rdata[1]),
-		.wb_we(wb_we),
-		.wb_wdata(wb_wdata),
-		.wb_cyc(wb_cyc[1]),
-		.wb_ack(wb_ack[1]),
-		.clk(clk_24m),
-		.rst(rst)
+		.uart_tx  (uart_tx),
+		.uart_rx  (uart_rx),
+		.wb_addr  (wb_addr[1:0]),
+		.wb_rdata (wb_rdata[1]),
+		.wb_we    (wb_we),
+		.wb_wdata (wb_wdata),
+		.wb_cyc   (wb_cyc[1]),
+		.wb_ack   (wb_ack[1]),
+		.clk      (clk_24m),
+		.rst      (rst)
 	);