cores/qspi_master: Rework the CS_n driving path in PHYs

 - Actively drive CS_n, don't rely on external pull up.
   We run this quite fast, need a clean fast rising edge

 - Don't use the IOB register for CS.
   It often conflicts with other IO site and since it's
   enabled before/after the access, timing is not super
   critical.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

cores/qspi_master/rtl/qspi_phy_ice40_1x.v

@@ -107,16 +107,14 @@ module qspi_phy_ice40_1x #(
 	generate
 		if (N_CS)
 			SB_IO #(
-				.PIN_TYPE(6'b110111),
-				.PULLUP(1'b1),
+				.PIN_TYPE(6'b0101_11),
+				.PULLUP(1'b0),
 				.NEG_TRIGGER(1'b0),
 				.IO_STANDARD("SB_LVCMOS")
 			) iob_cs_I[N_CS-1:0] (
 				.PACKAGE_PIN(pad_cs_n),
-				.CLOCK_ENABLE(1'b1),
 				.OUTPUT_CLK(clk),
-				.OUTPUT_ENABLE(~phy_cs_o),
-				.D_OUT_0(1'b0)
+				.D_OUT_0(phy_cs_o)
 			);
 	endgenerate
 

cores/qspi_master/rtl/qspi_phy_ice40_2x.v

@@ -141,20 +141,18 @@ module qspi_phy_ice40_2x #(
 	// Chip select
 	generate
 		// FIXME register CS config ?
-		// Because the default CS (for the config flash) shares an IO site
-		// with CLK, we can't use clk_1x here. So instead we don't register
-		// the signal at all and count of the fact it's held low a bit longer
-		// than needed by the controller ...
+		// Because of potential conflict with IO site, we don't register
+		// the CS signal at all and rely on the fact it's held low a bit longer
+		// than needed by the controller.
 		if (N_CS)
 			SB_IO #(
-				.PIN_TYPE(6'b101011),
+				.PIN_TYPE(6'b0110_11),
 				.PULLUP(1'b1),
 				.NEG_TRIGGER(1'b0),
 				.IO_STANDARD("SB_LVCMOS")
 			) iob_cs_I[N_CS-1:0] (
 				.PACKAGE_PIN(pad_cs_n),
-				.OUTPUT_ENABLE(~phy_cs_o),
-				.D_OUT_0(1'b0)
+				.D_OUT_0(phy_cs_o)
 			);
 	endgenerate
 

cores/qspi_master/rtl/qspi_phy_ice40_4x.v

@@ -64,7 +64,7 @@ module qspi_phy_ice40_4x #(
 	wire [ 3:0] iob_io_oe;
 	wire [ 3:0] iob_io_o;
 	wire [ 3:0] iob_io_i;
-	reg  [CL:0] iob_cs_oe;
+	reg  [CL:0] iob_cs_o;
 
 
 	// IOs
@@ -177,21 +177,21 @@ module qspi_phy_ice40_4x #(
 
 	generate
 		if (N_CS) begin
-			// Simple register
+			// Delay to match serdes delay
 			always @(posedge clk_1x)
-				iob_cs_oe <= ~phy_cs_o;
+				iob_cs_o <= phy_cs_o;
 
-			// IOB: Chip select
+			// Because of potential conflict with IO site, we don't register
+			// the CS signal at all and rely on the fact it's held low a bit longer
+			// than needed by the controller.
 			SB_IO #(
-				.PIN_TYPE(6'b 1101_01),	// Out:SDRwOE, In:n/a
+				.PIN_TYPE(6'b0110_11),
 				.PULLUP(1'b1),
 				.NEG_TRIGGER(1'b0),
 				.IO_STANDARD("SB_LVCMOS")
 			) iob_spi_cs_I[N_CS-1:0] (
 				.PACKAGE_PIN(pad_cs_n),
-				.OUTPUT_ENABLE(iob_cs_oe),
-				.D_OUT_0(1'b0),
-				.OUTPUT_CLK(clk_4x)
+				.D_OUT_0(iob_cs_o)
 			);
 		end
 	endgenerate