projects/riscv_doom: Initial project import

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

projects/riscv_doom/Makefile

@@ -0,0 +1,40 @@
+# Project config
+PROJ = riscv_doom
+
+PROJ_DEPS := no2usb no2misc no2ice40 qspi_master mem_cache video
+PROJ_RTL_SRCS := $(addprefix rtl/, \
+	vid_top.v \
+	vid_palette.v \
+	vid_framebuf.v \
+	soc_bram.v \
+	sysmgr.v \
+	VexRiscv.v \
+)
+PROJ_SIM_SRCS := $(addprefix sim/, \
+	spiflash.v \
+)
+PROJ_SIM_SRCS += rtl/top.v
+PROJ_TESTBENCHES := \
+	top_tb
+PROJ_PREREQ = \
+	$(BUILD_TMP)/boot.hex
+PROJ_TOP_SRC := rtl/top.v
+PROJ_TOP_MOD := top
+
+# Target config
+BOARD ?= icebreaker
+DEVICE = up5k
+PACKAGE = sg48
+
+YOSYS_SYNTH_ARGS = -dffe_min_ce_use 4 -abc9 -device u -dsp
+NEXTPNR_ARGS = --pre-pack data/clocks.py --pre-place $(CORE_no2ice40_DIR)/sw/serdes-nextpnr-place.py --seed 4
+
+# Include default rules
+include ../../build/project-rules.mk
+
+# Custom rules
+fw_boot/boot.hex:
+	make -C fw_boot boot.hex
+
+$(BUILD_TMP)/boot.hex: fw_boot/boot.hex
+	cp $< $@

projects/riscv_doom/README.md

@@ -0,0 +1,2 @@
+RISC-V Doom for iCE40UP5k
+=========================

projects/riscv_doom/data/clocks.py

@@ -0,0 +1,4 @@
+BASE = 25.175
+
+ctx.addClock("clk_1x", 0.925 * BASE)	# Allow overclock ...
+ctx.addClock("clk_4x", 4     * BASE)

projects/riscv_doom/data/top-icebreaker.pcf

@@ -0,0 +1,41 @@
+# SPI
+set_io --warn-no-port             spi_sck   15
+set_io --warn-no-port -pullup no  spi_io[0] 14
+set_io --warn-no-port -pullup no  spi_io[1] 17
+set_io --warn-no-port -pullup no  spi_io[2] 12
+set_io --warn-no-port -pullup no  spi_io[3] 13
+set_io --warn-no-port -pullup yes spi_cs_n[0] 16
+set_io --warn-no-port -pullup yes spi_cs_n[1] 37
+
+# HDMI 12 bit pmod on 1A/1B
+set_io -nowarn hdmi_clk 38
+set_io -nowarn hdmi_de 32
+set_io -nowarn hdmi_hsync 31
+set_io -nowarn hdmi_vsync 28
+set_io -nowarn hdmi_b[3] 43
+set_io -nowarn hdmi_b[2] 42
+set_io -nowarn hdmi_b[1] 36
+set_io -nowarn hdmi_b[0] 34
+set_io -nowarn hdmi_g[3] 47
+set_io -nowarn hdmi_g[2] 46
+set_io -nowarn hdmi_g[1] 45
+set_io -nowarn hdmi_g[0] 44
+set_io -nowarn hdmi_r[3] 4
+set_io -nowarn hdmi_r[2] 3
+set_io -nowarn hdmi_r[1] 2
+set_io -nowarn hdmi_r[0] 48
+
+# UART
+set_io -nowarn uart_rx 6
+set_io -nowarn uart_tx 9
+
+# Clock
+set_io -nowarn clk_in 35
+
+# Button
+set_io -nowarn btn 10
+
+# Leds
+set_io -nowarn rgb[0] 39
+set_io -nowarn rgb[1] 40
+set_io -nowarn rgb[2] 41

projects/riscv_doom/fw_boot/Makefile

@@ -0,0 +1,20 @@
+CROSS ?= riscv-none-embed-
+
+CC = $(CROSS)gcc
+OBJCOPY = $(CROSS)objcopy
+
+CFLAGS=-Wall -Os -march=rv32i -mabi=ilp32 -ffreestanding -flto -nostartfiles -fomit-frame-pointer -Wl,--gc-section --specs=nano.specs
+
+boot.elf: lnk-boot.lds boot.S
+	$(CC) $(CFLAGS) -Wl,-Bstatic,-T,lnk-boot.lds,--strip-debug -DFLASH_APP_ADDR=0x00100000 -o $@ boot.S
+
+%.hex: %.bin
+	./bin2hex.py $< $@
+
+%.bin: %.elf
+	$(OBJCOPY) -O binary $< $@
+
+clean:
+	rm -f *.bin *.hex *.elf *.o
+
+.PHONY: clean

projects/riscv_doom/fw_boot/bin2hex.py

@@ -0,0 +1 @@
+../../riscv_usb/fw/bin2hex.py

projects/riscv_doom/fw_boot/boot.S

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+/*
+ * boot.S
+ *
+ * Boot code
+ *
+ * Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef FLASH_APP_ADDR
+#define FLASH_APP_ADDR 0x00100000
+#endif
+
+#define BOOT_DEBUG
+
+	.section .text.start
+	.global _start
+_start:
+
+#ifdef BOOT_DEBUG
+	// Set UART divisor
+	li	a0, 0x82000004
+	li	a1, 23
+	sw	a1, 0(a0)
+#endif
+
+	// Delay boot
+	li	t0, 0x01000000
+1:
+	addi	t0, t0, -1
+	bne	t0, zero, 1b
+
+	// SPI init
+	jal	spi_init
+
+	// Setup reboot code
+	li	t0, 0x0002006f
+	sw	t0, 0(zero)
+
+	// Jump to main code in flash
+	li	ra, (0x40000000 + FLASH_APP_ADDR)
+	ret
+
+	.equ    SPI_BASE, 0x80000000
+	.equ    SPI_CSR,  4 * 0x00
+	.equ	SPI_RF,   4 * 0x03
+
+
+spi_init:
+	// Save return address
+	// -------------------
+
+	mv	t6, ra
+
+
+	// Flash QSPI enable
+	// -----------------
+
+	li	t5, SPI_BASE
+
+	// Request external control
+	li	t0, 0x00000004
+	sw	t0, SPI_CSR(t5)
+
+	li	t0, 0x00000002
+	sw	t0, SPI_CSR(t5)
+
+	// Enable QSPI (0x38)
+	li	t0, 0x38000000
+	sw	t0, 0x40(t5)
+
+	// Read and discard response
+	lw	t0, SPI_RF(t5)
+
+	// Release external control
+	li	t0, 0x00000004
+	sw	t0, SPI_CSR(t5)
+
+
+	// Flash QSPI config
+	// -----------------
+
+	// Request external control
+	li	t0, 0x00000004
+	sw	t0, SPI_CSR(t5)
+
+	li	t0, 0x00000002
+	sw	t0, SPI_CSR(t5)
+
+	// Set QSPI parameters (dummy=6, wrap=64b)
+	li	t0, 0xc0230000
+	sw	t0, 0x74(t5)
+
+	// Release external control
+	li	t0, 0x00000004
+	sw	t0, SPI_CSR(t5)
+
+
+	// PSRAM init
+	// ----------
+
+	// Request external control
+	li	t0, 0x00000004
+	sw	t0, SPI_CSR(t5)
+
+	li	t0, 0x00000012
+	sw	t0, SPI_CSR(t5)
+
+	// Enable QSPI (0x35)
+	li	t0, 0x35000000
+	sw	t0, 0x40(t5)
+
+	// Read and discard response
+	lw	t0, SPI_RF(t5)
+
+	// Release external control
+	li	t0, 0x00000004
+	sw	t0, SPI_CSR(t5)
+
+
+	// Return
+	// ------
+
+	mv	ra, t6
+	ret
+
+
+#ifdef BOOT_DEBUG
+// Agument in a0
+// Clobbers a0, t0-t3
+print_hex:
+	li	t0, 0x82000000
+	li	t1, 8
+	la	t2, hexchar
+
+1:
+	srli	t3, a0, 28
+	add	t3, t3, t2
+	lb	t3, 0(t3)
+	sw	t3, 0(t0)
+
+	slli	a0, a0, 4
+
+	addi	t1, t1, -1
+	bne	zero, t1, 1b
+
+print_nl:
+	li	t0, 0x82000000
+	li	a0, '\r'
+	sw	a0, 0(t0)
+	li	a0, '\n'
+	sw	a0, 0(t0)
+
+	ret
+
+hexchar:
+	.ascii	"0123456789abcdef"
+#endif

projects/riscv_doom/fw_boot/lnk-boot.lds

@@ -0,0 +1,14 @@
+MEMORY
+{
+    ROM (rx)    : ORIGIN = 0x00000000, LENGTH = 0x0400
+}
+ENTRY(_start)
+SECTIONS {
+    .text :
+    {
+        . = ALIGN(4);
+        *(.text.start)
+        *(.text)
+        *(.text*)
+    } >ROM
+}

projects/riscv_doom/rtl/soc_bram.v

@@ -0,0 +1,38 @@
+/*
+ * soc_bram.v
+ *
+ * vim: ts=4 sw=4
+ *
+ * Copyright (C) 2020  Sylvain Munaut <tnt@246tNt.com>
+ * SPDX-License-Identifier: CERN-OHL-P-2.0
+ */
+
+`default_nettype none
+
+module soc_bram #(
+	parameter integer AW = 8,
+	parameter INIT_FILE = ""
+)(
+	input  wire [AW-1:0] addr,
+	output reg    [31:0] rdata,
+	input  wire   [31:0] wdata,
+	input  wire   [ 3:0] wmsk,
+	input  wire          we,
+	input  wire          clk
+);
+
+	reg [31:0] mem [0:(1<<AW)-1];
+
+	initial
+		if (INIT_FILE != "")
+			$readmemh(INIT_FILE, mem);
+
+	always @(posedge clk) begin
+		rdata <= mem[addr];
+		if (we & ~wmsk[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
+		if (we & ~wmsk[1]) mem[addr][15: 8] <= wdata[15: 8];
+		if (we & ~wmsk[2]) mem[addr][23:16] <= wdata[23:16];
+		if (we & ~wmsk[3]) mem[addr][31:24] <= wdata[31:24];
+	end
+
+endmodule // soc_bram

projects/riscv_doom/rtl/sysmgr.v

@@ -0,0 +1,65 @@
+/*
+ * sysmgr.v
+ *
+ * vim: ts=4 sw=4
+ *
+ * Copyright (C) 2021  Sylvain Munaut <tnt@246tNt.com>
+ * SPDX-License-Identifier: CERN-OHL-P-2.0
+ */
+
+`default_nettype none
+
+module sysmgr (
+	input  wire clk_in,
+	output wire clk_1x,
+	output wire clk_4x,
+	output wire sync_4x,
+	output wire rst
+);
+
+	wire pll_lock;
+
+	SB_PLL40_2F_PAD #(
+		.FEEDBACK_PATH("SIMPLE"),
+		.DIVR(4'b0000),
+		.DIVF(7'b1000010),
+		.DIVQ(3'b011),
+		.FILTER_RANGE(3'b001),
+		.DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
+		.FDA_RELATIVE(15),
+		.SHIFTREG_DIV_MODE(0),
+		.PLLOUT_SELECT_PORTA("GENCLK"),
+		.PLLOUT_SELECT_PORTB("GENCLK")
+	) pll_I (
+		.PACKAGEPIN    (clk_in),
+		.DYNAMICDELAY  (8'h0),
+		.PLLOUTGLOBALA (),
+		.PLLOUTGLOBALB (clk_4x),
+		.RESETB        (1'b1),
+		.LOCK          (pll_lock)
+	);
+
+	ice40_serdes_crg #(
+		.NO_CLOCK_2X(1)
+	) crg_I (
+		.clk_4x   (clk_4x),
+		.pll_lock (pll_lock),
+		.clk_1x   (clk_1x),
+		.clk_2x   (),
+		.rst      (rst)
+	);
+
+	ice40_serdes_sync #(
+		.PHASE      (2),
+		.NEG_EDGE   (0),
+		.GLOBAL_BUF (0),
+		.BEL_COL    ("X20"),
+		.BEL_ROW    ("Y4")
+	) sync_96m_I (
+		.clk_slow (clk_1x),
+		.clk_fast (clk_4x),
+		.rst      (rst),
+		.sync     (sync_4x)
+	);
+
+endmodule

projects/riscv_doom/rtl/top.v

@@ -0,0 +1,469 @@
+/*
+ * top.v
+ *
+ * vim: ts=4 sw=4
+ *
+ * Copyright (C) 2021  Sylvain Munaut <tnt@246tNt.com>
+ * SPDX-License-Identifier: CERN-OHL-P-2.0
+ */
+
+`default_nettype none
+
+module top (
+	// SPI
+	inout  wire [3:0] spi_io,
+	inout  wire       spi_sck,
+	inout  wire [1:0] spi_cs_n,
+
+	// Video output
+	output wire [3:0] hdmi_r,
+	output wire [3:0] hdmi_g,
+	output wire [3:0] hdmi_b,
+	output wire       hdmi_hsync,
+	output wire       hdmi_vsync,
+	output wire       hdmi_de,
+	output wire       hdmi_clk,
+
+	// Debug UART
+	input  wire uart_rx,
+	output wire uart_tx,
+
+	// Button
+	input  wire btn,
+
+	// LED
+	output wire [2:0] rgb,
+
+	// Clock
+	input  wire clk_in
+);
+
+	localparam integer WB_N  =  4;
+
+	localparam integer WB_DW = 32;
+	localparam integer WB_AW = 22;
+	localparam integer WB_RW = WB_DW * WB_N;
+	localparam integer WB_MW = WB_DW / 8;
+
+	genvar i;
+
+
+	// Signals
+	// -------
+
+	// Vex Misc
+	wire [31:0] vex_externalResetVector;
+	wire        vex_timerInterrupt;
+	wire        vex_softwareInterrupt;
+	wire [31:0] vex_externalInterruptArray;
+
+	// Vex busses
+	wire        i_axi_ar_valid;
+	wire        i_axi_ar_ready;
+	wire [31:0] i_axi_ar_payload_addr;
+	wire [ 7:0] i_axi_ar_payload_len;
+	wire [ 1:0] i_axi_ar_payload_burst;
+	wire [ 3:0] i_axi_ar_payload_cache;
+	wire [ 2:0] i_axi_ar_payload_prot;
+	wire        i_axi_r_valid;
+	wire        i_axi_r_ready;
+	wire [31:0] i_axi_r_payload_data;
+	wire [ 1:0] i_axi_r_payload_resp;
+	wire        i_axi_r_payload_last;
+
+	wire        d_wb_cyc;
+	wire        d_wb_stb;
+	wire        d_wb_ack;
+	wire        d_wb_we;
+	wire [29:0] d_wb_adr;
+	wire [31:0] d_wb_dat_miso;
+	wire [31:0] d_wb_dat_mosi;
+	wire [ 3:0] d_wb_sel;
+	wire        d_wb_err;
+	wire [ 1:0] d_wb_bte;
+	wire [ 2:0] d_wb_cti;
+
+	// RAM
+	wire [27:0] ram_addr;
+	wire [31:0] ram_rdata;
+	wire [31:0] ram_wdata;
+	wire [ 3:0] ram_wmsk;
+	wire        ram_we;
+
+	// Cache Request / Response interface
+	wire [27:0] cache_req_addr_pre;
+	wire        cache_req_valid;
+	wire        cache_req_write;
+	wire [31:0] cache_req_wdata;
+	wire [ 3:0] cache_req_wmsk;
+
+	wire        cache_resp_ack;
+	wire        cache_resp_nak;
+	wire [31:0] cache_resp_rdata;
+
+	// Memory interface
+	wire [23:0] mi_addr;
+	wire [ 6:0] mi_len;
+	wire        mi_rw;
+	wire        mi_linear;
+	wire        mi_valid;
+	wire        mi_ready;
+
+	wire [31:0] mi_wdata;
+	wire [ 3:0] mi_wmsk;
+	wire        mi_wack;
+	wire        mi_wlast;
+
+	wire [31:0] mi_rdata;
+	wire        mi_rstb;
+	wire        mi_rlast;
+
+	// QSPI PHY signals
+	wire [15:0] phy_io_i;
+	wire [15:0] phy_io_o;
+	wire [ 3:0] phy_io_oe;
+	wire [ 3:0] phy_clk_o;
+	wire [ 1:0] phy_cs_o;
+
+	// Wishbone
+	wire [WB_AW-1:0] wb_addr;
+	wire [WB_DW-1:0] wb_rdata [0:WB_N-1];
+	wire [WB_RW-1:0] wb_rdata_flat;
+	wire [WB_DW-1:0] wb_wdata;
+	wire [WB_MW-1:0] wb_wmsk;
+	wire             wb_we;
+	wire [WB_N -1:0] wb_cyc;
+	wire [WB_N -1:0] wb_ack;
+
+	// Clock / Reset logic
+	wire clk_1x;
+	wire clk_4x;
+	wire sync_4x;
+	wire rst;
+
+
+	// SoC
+	// ---
+
+	// CPU
+	VexRiscv cpu_I (
+		.externalResetVector      (vex_externalResetVector),
+		.timerInterrupt           (vex_timerInterrupt),
+		.softwareInterrupt        (vex_softwareInterrupt),
+		.externalInterruptArray   (vex_externalInterruptArray),
+		.iBusAXI_ar_valid         (i_axi_ar_valid),
+		.iBusAXI_ar_ready         (i_axi_ar_ready),
+		.iBusAXI_ar_payload_addr  (i_axi_ar_payload_addr),
+		.iBusAXI_ar_payload_len   (i_axi_ar_payload_len),
+		.iBusAXI_ar_payload_burst (i_axi_ar_payload_burst),
+		.iBusAXI_ar_payload_cache (i_axi_ar_payload_cache),
+		.iBusAXI_ar_payload_prot  (i_axi_ar_payload_prot),
+		.iBusAXI_r_valid          (i_axi_r_valid),
+		.iBusAXI_r_ready          (i_axi_r_ready),
+		.iBusAXI_r_payload_data   (i_axi_r_payload_data),
+		.iBusAXI_r_payload_resp   (i_axi_r_payload_resp),
+		.iBusAXI_r_payload_last   (i_axi_r_payload_last),
+		.dBusWishbone_CYC         (d_wb_cyc),
+		.dBusWishbone_STB         (d_wb_stb),
+		.dBusWishbone_ACK         (d_wb_ack),
+		.dBusWishbone_WE          (d_wb_we),
+		.dBusWishbone_ADR         (d_wb_adr),
+		.dBusWishbone_DAT_MISO    (d_wb_dat_miso),
+		.dBusWishbone_DAT_MOSI    (d_wb_dat_mosi),
+		.dBusWishbone_SEL         (d_wb_sel),
+		.dBusWishbone_ERR         (d_wb_err),
+		.dBusWishbone_BTE         (d_wb_bte),
+		.dBusWishbone_CTI         (d_wb_cti),
+		.clk                      (clk_1x),
+		.reset                    (rst)
+	);
+
+	// CPU interrupt wiring
+	assign vex_externalResetVector    = 32'h00000000;
+	assign vex_timerInterrupt         = 1'b0;
+	assign vex_softwareInterrupt      = 1'b0;
+	assign vex_externalInterruptArray = 32'h00000000;
+
+	// Cache bus interface / bridge
+	mc_bus_vex #(
+		.WB_N(WB_N)
+	) cache_bus_I (
+		.i_axi_ar_valid         (i_axi_ar_valid),
+		.i_axi_ar_ready         (i_axi_ar_ready),
+		.i_axi_ar_payload_addr  (i_axi_ar_payload_addr),
+		.i_axi_ar_payload_len   (i_axi_ar_payload_len),
+		.i_axi_ar_payload_burst (i_axi_ar_payload_burst),
+		.i_axi_ar_payload_cache (i_axi_ar_payload_cache),
+		.i_axi_ar_payload_prot  (i_axi_ar_payload_prot),
+		.i_axi_r_valid          (i_axi_r_valid),
+		.i_axi_r_ready          (i_axi_r_ready),
+		.i_axi_r_payload_data   (i_axi_r_payload_data),
+		.i_axi_r_payload_resp   (i_axi_r_payload_resp),
+		.i_axi_r_payload_last   (i_axi_r_payload_last),
+		.d_wb_cyc               (d_wb_cyc),
+		.d_wb_stb               (d_wb_stb),
+		.d_wb_ack               (d_wb_ack),
+		.d_wb_we                (d_wb_we),
+		.d_wb_adr               (d_wb_adr),
+		.d_wb_dat_miso          (d_wb_dat_miso),
+		.d_wb_dat_mosi          (d_wb_dat_mosi),
+		.d_wb_sel               (d_wb_sel),
+		.d_wb_err               (d_wb_err),
+		.d_wb_bte               (d_wb_bte),
+		.d_wb_cti               (d_wb_cti),
+		.wb_addr                (wb_addr),
+		.wb_wdata               (wb_wdata),
+		.wb_wmsk                (wb_wmsk),
+		.wb_rdata               (wb_rdata_flat),
+		.wb_cyc                 (wb_cyc),
+		.wb_we                  (wb_we),
+		.wb_ack                 (wb_ack),
+		.ram_addr               (ram_addr),
+		.ram_wdata              (ram_wdata),
+		.ram_wmsk               (ram_wmsk),
+		.ram_rdata              (ram_rdata),
+		.ram_we                 (ram_we),
+		.req_addr_pre           (cache_req_addr_pre),
+		.req_valid              (cache_req_valid),
+		.req_write              (cache_req_write),
+		.req_wdata              (cache_req_wdata),
+		.req_wmsk               (cache_req_wmsk),
+		.resp_ack               (cache_resp_ack),
+		.resp_nak               (cache_resp_nak),
+		.resp_rdata             (cache_resp_rdata),
+		.clk                    (clk_1x),
+		.rst                    (rst)
+	);
+
+	for (i=0; i<WB_N; i=i+1)
+		assign wb_rdata_flat[i*WB_DW+:WB_DW] = wb_rdata[i];
+
+	// Boot memory
+	soc_bram #(
+		.AW(8),
+		.INIT_FILE("boot.hex")
+	) bram_I (
+		.addr  (ram_addr[7:0]),
+		.rdata (ram_rdata),
+		.wdata (ram_wdata),
+		.wmsk  (ram_wmsk),
+		.we    (ram_we),
+		.clk   (clk_1x)
+	);
+
+	// Cache
+	mc_core #(
+		.N_WAYS(4),
+		.ADDR_WIDTH(24),
+		.CACHE_LINE(32),
+		.CACHE_SIZE(64)
+	) cache_I (
+		.req_addr_pre (cache_req_addr_pre[23:0]),
+		.req_valid    (cache_req_valid),
+		.req_write    (cache_req_write),
+		.req_wdata    (cache_req_wdata),
+		.req_wmsk     (cache_req_wmsk),
+		.resp_ack     (cache_resp_ack),
+		.resp_nak     (cache_resp_nak),
+		.resp_rdata   (cache_resp_rdata),
+		.mi_addr      (mi_addr),
+		.mi_len       (mi_len),
+		.mi_rw        (mi_rw),
+		.mi_valid     (mi_valid),
+		.mi_ready     (mi_ready),
+		.mi_wdata     (mi_wdata),
+		.mi_wack      (mi_wack),
+		.mi_wlast     (mi_wlast),
+		.mi_rdata     (mi_rdata),
+		.mi_rstb      (mi_rstb),
+		.mi_rlast     (mi_rlast),
+		.clk          (clk_1x),
+		.rst          (rst)
+	);
+
+
+	// QSPI
+	// ----
+
+	// Simulation
+`ifdef SIM
+	mem_sim #(
+		.INIT_FILE("firmware.hex"),
+		.AW(20)
+	) qspi_sim (
+		.mi_addr  ({mi_addr[22], mi_addr[18:0]}),
+		.mi_len   (mi_len),
+		.mi_rw    (mi_rw),
+		.mi_valid (mi_valid),
+		.mi_ready (mi_ready),
+		.mi_wdata (mi_wdata),
+		.mi_wack  (mi_wack),
+		.mi_wlast (mi_wlast),
+		.mi_rdata (mi_rdata),
+		.mi_rstb  (mi_rstb),
+		.mi_rlast (mi_rlast),
+		.clk      (clk_1x),
+		.rst      (rst)
+	);
+
+	assign wb_ack[0] = wb_cyc[0];
+`else
+	// Controller
+	qspi_master #(
+		.CMD_READ   (16'hEB0B),
+		.CMD_WRITE  (16'h0202),
+		.DUMMY_CLK  (6),
+		.PAUSE_CLK  (8),
+		.FIFO_DEPTH (1),
+		.N_CS       (2),
+		.PHY_SPEED  (4),
+		.PHY_WIDTH  (1),
+		.PHY_DELAY  (4)
+	) memctrl_I (
+		.phy_io_i   (phy_io_i),
+		.phy_io_o   (phy_io_o),
+		.phy_io_oe  (phy_io_oe),
+		.phy_clk_o  (phy_clk_o),
+		.phy_cs_o   (phy_cs_o),
+		.mi_addr_cs (mi_addr[23:22]),
+		.mi_addr    ({mi_addr[21:0], 2'b00 }),	/* 32 bits aligned */
+		.mi_len     (mi_len),
+		.mi_rw      (mi_rw),
+		.mi_valid   (mi_valid),
+		.mi_ready   (mi_ready),
+		.mi_wdata   ({mi_wdata[7:0], mi_wdata[15:8], mi_wdata[23:16], mi_wdata[31:24]}),
+		.mi_wack    (mi_wack),
+		.mi_wlast   (mi_wlast),
+		.mi_rdata   ({mi_rdata[7:0], mi_rdata[15:8], mi_rdata[23:16], mi_rdata[31:24]}),
+		.mi_rstb    (mi_rstb),
+		.mi_rlast   (mi_rlast),
+		.wb_wdata   (wb_wdata),
+		.wb_rdata   (wb_rdata[0]),
+		.wb_addr    (wb_addr[4:0]),
+		.wb_we      (wb_we),
+		.wb_cyc     (wb_cyc[0]),
+		.wb_ack     (wb_ack[0]),
+		.clk        (clk_1x),
+		.rst        (rst)
+	);
+
+	// PHY
+	qspi_phy_ice40_4x #(
+		.N_CS(2),
+		.WITH_CLK(1)
+	) phy_I (
+		.pad_io    (spi_io),
+		.pad_clk   (spi_sck),
+		.pad_cs_n  (spi_cs_n),
+		.phy_io_i  (phy_io_i),
+		.phy_io_o  (phy_io_o),
+		.phy_io_oe (phy_io_oe),
+		.phy_clk_o (phy_clk_o),
+		.phy_cs_o  (phy_cs_o),
+		.clk_1x    (clk_1x),
+		.clk_4x    (clk_4x),
+		.clk_sync  (sync_4x)
+	);
+`endif
+
+
+	// Video [1]
+	// -----
+
+	vid_top vid_I (
+		.hdmi_r     (hdmi_r),
+		.hdmi_g     (hdmi_g),
+		.hdmi_b     (hdmi_b),
+		.hdmi_hsync (hdmi_hsync),
+		.hdmi_vsync (hdmi_vsync),
+		.hdmi_de    (hdmi_de),
+		.hdmi_clk   (hdmi_clk),
+		.wb_addr    (wb_addr[15:0]),
+		.wb_rdata   (wb_rdata[1]),
+		.wb_wdata   (wb_wdata),
+		.wb_wmsk    (wb_wmsk),
+		.wb_we      (wb_we),
+		.wb_cyc     (wb_cyc[1]),
+		.wb_ack     (wb_ack[1]),
+		.clk        (clk_1x),
+		.rst        (rst)
+	);
+
+
+	// UART [2]
+	// ----
+
+	uart_wb #(
+		.DIV_WIDTH(12),
+		.DW(WB_DW)
+	) uart_I (
+		.uart_tx  (uart_tx),
+		.uart_rx  (uart_rx),
+		.wb_addr  (wb_addr[1:0]),
+		.wb_rdata (wb_rdata[2]),
+		.wb_we    (wb_we),
+		.wb_wdata (wb_wdata),
+		.wb_cyc   (wb_cyc[2]),
+		.wb_ack   (wb_ack[2]),
+		.clk      (clk_1x),
+		.rst      (rst)
+	);
+
+
+	// LEDs [3]
+	// ----
+
+	ice40_rgb_wb #(
+		.CURRENT_MODE("0b1"),
+		.RGB0_CURRENT("0b000001"),
+		.RGB1_CURRENT("0b000001"),
+		.RGB2_CURRENT("0b000001")
+	) rgb_I (
+		.pad_rgb    (rgb),
+		.wb_addr    (wb_addr[4:0]),
+		.wb_rdata   (wb_rdata[3]),
+		.wb_wdata   (wb_wdata),
+		.wb_we      (wb_we),
+		.wb_cyc     (wb_cyc[3]),
+		.wb_ack     (wb_ack[3]),
+		.clk        (clk_1x),
+		.rst        (rst)
+	);
+
+
+	// Clock / Reset
+	// -------------
+
+`ifdef SIM
+	reg       rst_s = 1'b1;
+	reg       clk_4x_s = 1'b0;
+	reg       clk_1x_s = 1'b0;
+	reg [1:0] clk_sync_cnt = 2'b00;
+
+	always  #5 clk_4x_s <= !clk_4x_s;
+	always #20 clk_1x_s <= !clk_1x_s;
+
+	initial
+		#200 rst_s = 0;
+
+	always @(posedge clk_4x_s)
+		if (rst)
+			clk_sync_cnt <= 2'b00;
+		else
+			clk_sync_cnt <= clk_sync_cnt + 1;
+
+	assign clk_4x  = clk_4x_s;
+	assign clk_1x  = clk_1x_s;
+	assign sync_4x = (clk_sync_cnt == 2'b10);
+	assign rst     = rst_s;
+`else
+	sysmgr sys_mgr_I (
+		.clk_in  (clk_in),
+		.clk_1x  (clk_1x),
+		.clk_4x  (clk_4x),
+		.sync_4x (sync_4x),
+		.rst     (rst)
+	);
+`endif
+
+endmodule // top

projects/riscv_doom/rtl/vid_framebuf.v

@@ -0,0 +1,78 @@
+/*
+ * vid_framebuf.v
+ *
+ * Video framebuffer memory
+ *
+ * vim: ts=4 sw=4
+ *
+ * Copyright (C) 2021  Sylvain Munaut <tnt@246tNt.com>
+ * SPDX-License-Identifier: CERN-OHL-P-2.0
+ */
+
+`default_nettype none
+
+module vid_framebuf (
+	// Video Read port
+	input  wire [13:0] v_addr_0,
+	output wire [31:0] v_data_1,
+	input  wire        v_re_0,
+
+	// Aux R/W port
+	input  wire [13:0] a_addr_0,
+	output wire [31:0] a_rdata_1,
+	input  wire [31:0] a_wdata_0,
+	input  wire [ 3:0] a_wmsk_0,
+	input  wire        a_we_0,
+	output wire        a_rdy_0,
+
+	// Clock
+	input  wire clk
+);
+
+	// Signals
+	// -------
+
+	wire [13:0] ram_addr;
+	wire [31:0] ram_rdata;
+	wire [31:0] ram_wdata;
+	wire [ 7:0] ram_mask_n;
+	wire        ram_we;
+
+
+	// Memory
+	// ------
+
+	SB_SPRAM256KA spram_I[1:0] (
+		.DATAIN     (ram_wdata),
+		.ADDRESS    (ram_addr),
+		.MASKWREN   (ram_mask_n),
+		.WREN       (ram_we),
+		.CHIPSELECT (1'b1),
+		.CLOCK      (clk),
+		.STANDBY    (1'b0),
+		.SLEEP      (1'b0),
+		.POWEROFF   (1'b1),
+		.DATAOUT    (ram_rdata)
+	);
+
+
+	// Muxing
+	// ------
+
+	assign ram_addr = v_re_0 ? v_addr_0 : a_addr_0;
+
+	assign ram_wdata = a_wdata_0;
+	assign ram_mask_n  = {
+		~a_wmsk_0[3], ~a_wmsk_0[3],
+		~a_wmsk_0[2], ~a_wmsk_0[2],
+		~a_wmsk_0[1], ~a_wmsk_0[1],
+		~a_wmsk_0[0], ~a_wmsk_0[0]
+	};
+	assign ram_we = a_we_0 & ~v_re_0;
+
+	assign a_rdata_1 = ram_rdata;
+	assign v_data_1  = ram_rdata;
+
+	assign a_rdy_0 = ~v_re_0;
+
+endmodule // vid_framebuf

projects/riscv_doom/rtl/vid_palette.v

@@ -0,0 +1,45 @@
+/*
+ * vid_palette.v
+ *
+ * Video palette memory
+ *
+ * vim: ts=4 sw=4
+ *
+ * Copyright (C) 2021  Sylvain Munaut <tnt@246tNt.com>
+ * SPDX-License-Identifier: CERN-OHL-P-2.0
+ */
+
+`default_nettype none
+
+module vid_palette (
+	// Write port
+	input  wire [ 7:0] w_addr_0,
+	input  wire [15:0] w_data_0,
+	input  wire        w_ena_0,
+
+	// Read port
+	input  wire [ 7:0] r_addr_0,
+	output wire [15:0] r_data_1,
+
+	// Clock
+	input wire clk
+);
+
+	SB_RAM40_4K #(
+		.WRITE_MODE(0),
+		.READ_MODE(0)
+	) ebr_I (
+		.RDATA (r_data_1),
+		.RADDR ({3'b000, r_addr_0}),
+		.RCLK  (clk),
+		.RCLKE (1'b1),
+		.RE    (1'b1),
+		.WDATA (w_data_0),
+		.WADDR ({3'b000, w_addr_0}),
+		.MASK  (16'h0000),
+		.WCLK  (clk),
+		.WCLKE (w_ena_0),
+		.WE    (1'b1)
+	);
+
+endmodule // vid_palette

projects/riscv_doom/rtl/vid_top.v

@@ -0,0 +1,304 @@
+/*
+ * vid_top.v
+ *
+ * Top-level for the video module
+ *
+ * vim: ts=4 sw=4
+ *
+ * Copyright (C) 2021  Sylvain Munaut <tnt@246tNt.com>
+ * SPDX-License-Identifier: CERN-OHL-P-2.0
+ */
+
+`default_nettype none
+
+/* Use 640x480 60 Hz video and not original 640x400 70 Hz mode */
+`define COMPAT_MODE
+
+module vid_top (
+	// Video output
+	output wire [3:0] hdmi_r,
+	output wire [3:0] hdmi_g,
+	output wire [3:0] hdmi_b,
+	output wire       hdmi_hsync,
+	output wire       hdmi_vsync,
+	output wire       hdmi_de,
+	output wire       hdmi_clk,
+
+	// Wishbone
+	input  wire [15:0] wb_addr,
+	output reg  [31:0] wb_rdata,
+	input  wire [31:0] wb_wdata,
+	input  wire [ 3:0] wb_wmsk,
+	input  wire        wb_we,
+	input  wire        wb_cyc,
+	output reg         wb_ack,
+
+	// Clock / Reset
+	input  wire        clk,
+	input  wire        rst
+);
+
+	// Signals
+	// -------
+
+	// Frame Buffer
+	wire [13:0] fb_v_addr_0;
+	wire [31:0] fb_v_data_1;
+	wire        fb_v_re_0;
+	wire [13:0] fb_a_addr_0;
+	wire [31:0] fb_a_rdata_1;
+	wire [31:0] fb_a_wdata_0;
+	wire [ 3:0] fb_a_wmsk_0;
+	wire        fb_a_we_0;
+	wire        fb_a_rdy_0;
+
+	// Palette
+	wire [ 7:0] pal_w_addr;
+	wire [15:0] pal_w_data;
+	wire        pal_w_ena;
+
+	wire [ 7:0] pal_r_addr_0;
+	wire [15:0] pal_r_data_1;
+
+	// Timing gen
+	wire        tg_hsync_0;
+	wire        tg_vsync_0;
+	wire        tg_active_0;
+	wire        tg_h_first_0;
+	wire        tg_h_last_0;
+	wire        tg_v_first_0;
+	wire        tg_v_last_0;
+
+	// Video status
+	reg  [15:0] vs_frame_cnt;
+	reg         vs_in_vbl;
+
+	// Pixel pipeline
+	reg         pp_active_1;
+	reg         pp_ydbl_1;
+	reg         pp_xdbl_1;
+	reg  [15:0] pp_addr_base_1;
+	reg  [15:0] pp_addr_cur_1;
+
+	reg         pp_data_load_2;
+	reg  [31:0] pp_data_3;
+
+	wire [11:0] pp_data_4;
+	wire        pp_hsync_4;
+	wire        pp_vsync_4;
+	wire        pp_de_4;
+
+
+
+	// Frame Buffer
+	// ------------
+
+	vid_framebuf fb_I (
+		.v_addr_0  (fb_v_addr_0),
+		.v_data_1  (fb_v_data_1),
+		.v_re_0    (fb_v_re_0),
+		.a_addr_0  (fb_a_addr_0),
+		.a_rdata_1 (fb_a_rdata_1),
+		.a_wdata_0 (fb_a_wdata_0),
+		.a_wmsk_0  (fb_a_wmsk_0),
+		.a_we_0    (fb_a_we_0),
+		.a_rdy_0   (fb_a_rdy_0),
+		.clk       (clk)
+	);
+
+
+	// Palette
+	// -------
+
+	vid_palette pal_I (
+		.w_addr_0 (pal_w_addr),
+		.w_data_0 (pal_w_data),
+		.w_ena_0  (pal_w_ena),
+		.r_addr_0 (pal_r_addr_0),
+		.r_data_1 (pal_r_data_1),
+		.clk      (clk)
+	);
+
+
+	// Timing Generator
+	// ----------------
+
+	vid_tgen #(
+`ifndef COMPAT_MODE
+		.H_WIDTH  (  10 ),
+		.H_FP     (  16 ),
+		.H_SYNC   (  96 ),
+		.H_BP     (  48 ),
+		.H_ACTIVE ( 640 ),
+		.V_WIDTH  (   9 ),
+		.V_FP     (  12 ),
+		.V_SYNC   (   2 ),
+		.V_BP     (  35 ),
+		.V_ACTIVE ( 400 )
+`else
+		.H_WIDTH  (  10 ),
+		.H_FP     (  16 ),
+		.H_SYNC   (  96 ),
+		.H_BP     (  48 ),
+		.H_ACTIVE ( 640 ),
+		.V_WIDTH  (   9 ),
+		.V_FP     (  10 ),
+		.V_SYNC   (   2 ),
+		.V_BP     (  33 ),
+		.V_ACTIVE ( 480 )
+`endif
+	) tgen_I (
+		.vid_hsync   (tg_hsync_0),
+		.vid_vsync   (tg_vsync_0),
+		.vid_active  (tg_active_0),
+		.vid_h_first (tg_h_first_0),
+		.vid_h_last  (tg_h_last_0),
+		.vid_v_first (tg_v_first_0),
+		.vid_v_last  (tg_v_last_0),
+		.clk         (clk),
+		.rst         (rst)
+	);
+
+
+	// Video Status and counter
+	// ------------------------
+
+	always @(posedge clk)
+		vs_in_vbl <= (vs_in_vbl & ~tg_v_first_0) | (tg_v_last_0 & tg_h_last_0);
+
+	always @(posedge clk)
+		if (rst)
+			vs_frame_cnt <= 0;
+		else
+			vs_frame_cnt <= vs_frame_cnt + (tg_v_last_0 & tg_h_last_0);
+
+
+	// Video Pipeline
+	// --------------
+
+	// Pixel fetch
+`ifndef COMPAT_MODE
+		// Counter control in 640x400 -> Double pixels
+	always @(posedge clk) begin
+		pp_active_1 <= tg_active_0;
+		pp_ydbl_1   <= (pp_ydbl_1 ^ tg_h_first_0) |  tg_v_first_0;
+		pp_xdbl_1   <= (pp_xdbl_1 ^ 1'b1        ) & ~tg_h_first_0;
+	end
+`else
+		// Counter control in 640x480 -> Double X, Double-or-Triple Y
+	reg [3:0] pp_yscale_state;
+
+	always @(posedge clk)
+		if (tg_h_first_0) begin
+			if (tg_v_first_0) begin
+				pp_yscale_state <= 4'h0;
+				pp_ydbl_1       <= 1'b0;
+			end else begin
+				case (pp_yscale_state)
+					4'h0:    { pp_ydbl_1, pp_yscale_state } <= { 1'b1, 4'h1 };
+					4'h1:    { pp_ydbl_1, pp_yscale_state } <= { 1'b0, 4'h2 };
+					4'h2:    { pp_ydbl_1, pp_yscale_state } <= { 1'b1, 4'h3 };
+					4'h3:    { pp_ydbl_1, pp_yscale_state } <= { 1'b0, 4'h4 };
+					4'h4:    { pp_ydbl_1, pp_yscale_state } <= { 1'b0, 4'h5 };
+					4'h5:    { pp_ydbl_1, pp_yscale_state } <= { 1'b1, 4'h6 };
+					4'h6:    { pp_ydbl_1, pp_yscale_state } <= { 1'b0, 4'h7 };
+					4'h7:    { pp_ydbl_1, pp_yscale_state } <= { 1'b1, 4'h8 };
+					4'h8:    { pp_ydbl_1, pp_yscale_state } <= { 1'b0, 4'h9 };
+					4'h9:    { pp_ydbl_1, pp_yscale_state } <= { 1'b0, 4'ha };
+					4'ha:    { pp_ydbl_1, pp_yscale_state } <= { 1'b1, 4'hb };
+					4'hb:    { pp_ydbl_1, pp_yscale_state } <= { 1'b0, 4'h0 };
+					default: { pp_ydbl_1, pp_yscale_state } <= { 1'b0, 4'h0 };
+				endcase;
+			end
+		end
+
+	always @(posedge clk) begin
+		pp_active_1 <= tg_active_0;
+		pp_xdbl_1   <= (pp_xdbl_1 ^ 1'b1) & ~tg_h_first_0;
+	end
+`endif
+
+		// Counters
+	always @(posedge clk)
+		if (tg_h_first_0) begin
+			if (tg_v_first_0)
+				pp_addr_base_1 <= 0;
+			else
+				pp_addr_base_1 <= pp_addr_base_1 + (pp_ydbl_1 ? 16'd320 : 16'd0);
+		end
+
+	always @(posedge clk)
+		if (tg_h_first_0)
+			pp_addr_cur_1 <= tg_v_first_0 ? 16'd0 : pp_addr_base_1;
+		else
+			pp_addr_cur_1 <= pp_addr_cur_1 + pp_xdbl_1;
+
+		// Frame Buffer
+	assign fb_v_addr_0 = pp_addr_cur_1[15:2];
+	assign fb_v_re_0   = pp_active_1 & (pp_addr_cur_1[1:0] == 2'b00) & ~pp_xdbl_1;
+
+		// Shift Reg
+	always @(posedge clk)
+		pp_data_load_2 <= fb_v_re_0;
+
+	always @(posedge clk)
+		if (pp_xdbl_1)
+			pp_data_3 <= pp_data_load_2 ? fb_v_data_1 : { 8'h00, pp_data_3[31:8] };
+
+	// Palette fetch
+	assign pal_r_addr_0 = pp_data_3[7:0];
+	assign pp_data_4 = {
+		pal_r_data_1[15:12],	// R[15:11]
+		pal_r_data_1[10: 7],	// G[10: 5]
+		pal_r_data_1[4:1]		// B[ 4: 0]
+	};
+
+	// Sync signals
+	delay_bit #(4) dly_hsync ( ~tg_hsync_0,  pp_hsync_4, clk );
+	delay_bit #(4) dly_vsync ( ~tg_vsync_0,  pp_vsync_4, clk );
+	delay_bit #(4) dly_de    (  tg_active_0, pp_de_4,    clk );
+
+	// Output buffers
+	hdmi_phy_1x #(
+		.DW(12)
+	) phy_I (
+		.hdmi_data  ({hdmi_r, hdmi_g, hdmi_b}),
+		.hdmi_hsync (hdmi_hsync),
+		.hdmi_vsync (hdmi_vsync),
+		.hdmi_de    (hdmi_de),
+		.hdmi_clk   (hdmi_clk),
+		.in_data    (pp_data_4),
+		.in_hsync   (pp_hsync_4),
+		.in_vsync   (pp_vsync_4),
+		.in_de      (pp_de_4),
+		.clk        (clk)
+	);
+
+
+	// Bus Interface
+	// -------------
+
+	// Ack
+	always @(posedge clk)
+		wb_ack <= wb_cyc & ~wb_ack & (~wb_addr[15] | fb_a_rdy_0);
+
+	// Read Mux
+	always @(*)
+	begin
+		wb_rdata = 32'h00000000;
+		if (wb_ack)
+			wb_rdata = wb_addr[15] ? fb_a_rdata_1 : { 15'h0000, vs_in_vbl, vs_frame_cnt };
+	end
+
+	// Frame Buffer write
+	assign fb_a_addr_0  = wb_addr[13:0];
+	assign fb_a_wdata_0 = wb_wdata;
+	assign fb_a_wmsk_0  = wb_wmsk;
+	assign fb_a_we_0    = wb_cyc & wb_we & ~wb_ack & wb_addr[15];
+
+	// Palette write
+	assign pal_w_addr = wb_addr[7:0];
+	assign pal_w_data = { wb_wdata[23:19], wb_wdata[15:10], wb_wdata[7:3] };
+	assign pal_w_ena  = wb_cyc & wb_we & ~wb_ack & (wb_addr[15:14] == 2'b01);
+
+endmodule // vid_top

projects/riscv_doom/sim/spiflash.v

@@ -0,0 +1 @@
+../../riscv_usb/sim/spiflash.v

projects/riscv_doom/sim/top_tb.v

@@ -0,0 +1,89 @@
+/*
+ * top_tb.v
+ *
+ * vim: ts=4 sw=4
+ *
+ * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
+ * All rights reserved.
+ *
+ * BSD 3-clause, see LICENSE.bsd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of the <organization> nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+`default_nettype none
+
+module top_tb;
+
+	// Signals
+	// -------
+
+	wire [3:0] spi_io;
+	wire       spi_sck;
+	wire [1:0] spi_cs_n;
+
+	wire uart_rx;
+	wire uart_tx;
+
+
+	// Setup recording
+	// ---------------
+
+	initial begin
+		$dumpfile("top_tb.vcd");
+		$dumpvars(0,top_tb);
+		# 2000000 $finish;
+	end
+
+
+	// DUT
+	// ---
+
+	top dut_I (
+		.spi_io   (spi_io),
+		.spi_sck  (spi_sck),
+		.spi_cs_n (spi_cs_n),
+		.uart_rx  (uart_rx),
+		.uart_tx  (uart_tx),
+		.btn      (1'b1),
+		.rgb      (),
+		.clk_in   (1'b0)
+	);
+
+
+	// Support
+	// -------
+
+	pullup(uart_tx);
+	pullup(uart_rx);
+
+	spiflash flash_I (
+		.csb(spi_cs_n[0]),
+		.clk(spi_sck),
+		.io0(spi_io[0]),
+		.io1(spi_io[1]),
+		.io2(spi_io[2]),
+		.io3(spi_io[3])
+	);
+
+endmodule // top_tb

projects/riscv_doom/sw/doom_ctrl.py

@@ -0,0 +1,564 @@
+#!/usr/bin/env python3
+#
+# DOOM control application
+#
+# Copyright (C) 2021 Sylvain Munaut
+# SPDX-License-Identifier: MIT
+#
+
+import base64
+import pygame
+import serial
+import struct
+import sys
+
+from io import BytesIO
+
+# Add local WASD binding ...
+if True:
+	# Tweaked ...
+	KEYBIND = {
+		pygame.K_w:	pygame.K_UP,		# Forward
+		pygame.K_a:	pygame.K_COMMA,		# Strafe left
+		pygame.K_s: pygame.K_DOWN,		# Back
+		pygame.K_d: pygame.K_PERIOD,	# Strafe right
+		pygame.K_e: pygame.K_SPACE,		# Use
+	}
+	DISABLE_MOUSE_Y = True
+else:
+	# Original controls
+	KEYBIND = {}
+	DISABLE_MOUSE_Y = False
+
+
+def map_key(k):
+
+	KEYVAL = {
+		'KEY_LEFTARROW':	 0,
+		'KEY_RIGHTARROW':	 1,
+		'KEY_DOWNARROW':	 2,
+		'KEY_UPARROW':		 3,
+		'KEY_RSHIFT':		 4,
+		'KEY_RCTRL':		 5,
+		'KEY_RALT':			 6,
+		'KEY_ESCAPE':		 7,
+		'KEY_ENTER':		 8,
+		'KEY_TAB':			 9,
+		'KEY_BACKSPACE':	10,
+		'KEY_PAUSE':		11,
+		'KEY_EQUALS':		12,
+		'KEY_MINUS':		13,
+		'KEY_F1':			14,
+		'KEY_F2':			15,
+		'KEY_F3':			16,
+		'KEY_F4':			17,
+		'KEY_F5':			18,
+		'KEY_F6':			19,
+		'KEY_F7':			20,
+		'KEY_F8':			21,
+		'KEY_F9':			22,
+		'KEY_F10':			23,
+		'KEY_F11':			24,
+		'KEY_F12':			25,
+	}
+
+	KEYMAP = {
+		pygame.K_LEFT:		'KEY_LEFTARROW',
+		pygame.K_RIGHT:		'KEY_RIGHTARROW',
+		pygame.K_DOWN:		'KEY_DOWNARROW',
+		pygame.K_UP:		'KEY_UPARROW',
+		pygame.K_RSHIFT:	'KEY_RSHIFT',
+		pygame.K_LSHIFT:	'KEY_RSHIFT',
+		pygame.K_RCTRL:		'KEY_RCTRL',
+		pygame.K_LCTRL:		'KEY_RCTRL',
+		pygame.K_RALT:		'KEY_RALT',
+		pygame.K_LALT:		'KEY_RALT',
+		pygame.K_ESCAPE:	'KEY_ESCAPE',
+		pygame.K_RETURN:	'KEY_ENTER',
+		pygame.K_TAB:		'KEY_TAB',
+		pygame.K_BACKSPACE:	'KEY_BACKSPACE',
+		pygame.K_PAUSE:		'KEY_PAUSE',
+		pygame.K_EQUALS:	'KEY_EQUALS',
+		pygame.K_MINUS:		'KEY_MINUS',
+		pygame.K_F1:		'KEY_F1',
+		pygame.K_F2:		'KEY_F2',
+		pygame.K_F3:		'KEY_F3',
+		pygame.K_F4:		'KEY_F4',
+		pygame.K_F5:		'KEY_F5',
+		pygame.K_F6:		'KEY_F6',
+		pygame.K_F7:		'KEY_F7',
+		pygame.K_F8:		'KEY_F8',
+		pygame.K_F9:		'KEY_F9',
+		pygame.K_F10:		'KEY_F10',
+		pygame.K_F11:		'KEY_F11',
+		pygame.K_F12:		'KEY_F12',
+	}
+
+	# Default is no mapping
+	rc = None
+
+	# Check for local keybindings
+	if k in KEYBIND:
+		k = KEYBIND[k]
+
+	# Check for spcial mapping
+	if k in KEYMAP:
+		rc = KEYVAL[KEYMAP[k]]
+
+	# Map upper case to lowercase
+	elif ord('A') <= k <= ord('Z'):
+		rc = k - ord('A') + ord('a')
+
+	# Default is to map 1:1 for anything in printable ascii range
+	elif 32 <= k <= 127:
+		rc = k
+
+	return rc
+
+
+def main(argv0, dev='/dev/ttyUSB1'):
+
+	# Init PyGame
+	pygame.init()
+
+	# Load logo
+	logo = pygame.image.load(
+		BytesIO(base64.decodebytes(LOGO_DATA)),
+		'logo.jpg'
+	)
+
+	# Init screen
+	screen = pygame.display.set_mode([logo.get_width(), logo.get_height()])
+	pygame.display.set_caption("Doom controller")
+
+	pygame.time.set_timer(pygame.USEREVENT, 50)
+
+	# Open port
+	port = serial.Serial(dev, baudrate=1000000)
+
+	# Main loop
+	running = True
+	held = set()
+
+	mouse_active = False
+	mdx = 0
+	mdy = 0
+
+	while running:
+		# Process event
+		pygame.event.pump()
+		event = pygame.event.wait()
+
+		if event.type == pygame.QUIT:
+			running = False
+
+		elif event.type == pygame.VIDEORESIZE:
+			screen.blit(pygame.transform.scale(logo, event.dict['size']), (0, 0))
+			pygame.display.update()
+
+		elif event.type == pygame.VIDEOEXPOSE:
+			screen.blit(pygame.transform.scale(logo, screen.get_size()), (0, 0))
+			pygame.display.update()
+
+		elif event.type == pygame.KEYDOWN:
+			kv = map_key(event.key)
+			if (kv is not None) and (kv not in held):
+				held.add(kv)
+				cmd = (kv | 0x80).to_bytes(1, 'little')
+				port.write(cmd)
+
+		elif event.type == pygame.KEYUP:
+			if mouse_active and (event.key in (pygame.K_LMETA, pygame.K_RMETA)):
+				# Release mouse
+				pygame.mouse.set_visible(True)
+				pygame.event.set_grab(False)
+
+				# Release all pressed buttons
+				for kv in [28, 29, 30]:
+					if kv in held:
+						held.remove(kv)
+						cmd = kv.to_bytes(1, 'little')
+						port.write(cmd)
+
+				# Not active
+				mouse_active = False
+
+			kv = map_key(event.key)
+			if (kv is not None) and (kv in held):
+				held.remove(kv)
+				cmd = kv.to_bytes(1, 'little')
+				port.write(cmd)
+
+		elif event.type == pygame.MOUSEBUTTONDOWN:
+			if mouse_active:
+				# We have the mouse, send events
+				kv = (28 + event.button - 1) if (1 <= event.button <= 3) else None
+				if (kv is not None) and (kv not in held):
+					held.add(kv)
+					cmd = (kv | 0x80).to_bytes(1, 'little')
+					port.write(cmd)
+
+			elif event.button == 1:
+				# If button 1, grab mouse
+				pygame.mouse.set_visible(False)
+				pygame.event.set_grab(True)
+
+				# Active
+				mouse_active = True
+
+		elif event.type == pygame.MOUSEBUTTONUP:
+			if mouse_active:
+				# We have the mouse, send events
+				kv = (28 + event.button - 1) if (1 <= event.button <= 3) else None
+				if (kv is not None) and (kv in held):
+					held.remove(kv)
+					cmd = kv.to_bytes(1, 'little')
+					port.write(cmd)
+
+		elif event.type == pygame.MOUSEMOTION:
+			if mouse_active:
+				# We accumulate mouse events to not overwhelm
+				# target ...
+				mdx += event.rel[0]
+				mdy += event.rel[1]
+
+		elif event.type == pygame.USEREVENT:
+			# Hack
+			if DISABLE_MOUSE_Y:
+				mdy = 0
+
+			# Send pending mouse events
+			if (mdx != 0) or (mdy != 0):
+
+				# Send what we can
+				x = max(min(mdx, 127), -128)
+				y = max(min(mdy, 127), -128)
+
+				mdx -= x
+				mdy -= y
+
+				# Send it
+				port.write(struct.pack('bbb', 31, x, y))
+
+
+LOGO_DATA = b"""
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+AAEBBAABAAAAjwAAAAIBAwADAAAAdAAAAAMBAwABAAAABgAAAAYBAwABAAAABgAAABUBAwABAAAA
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+"""
+
+if __name__ == '__main__':
+	sys.exit(main(*sys.argv))