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@@ -144,6 +144,10 @@ module top (
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reg [4:0] led_ctrl;
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wire [2:0] rgb_pwm;
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+ // WarmBoot
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+ reg boot_now;
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+ reg [1:0] boot_sel;
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+
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// Clock / Reset logic
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wire clk_24m;
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wire clk_48m;
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@@ -473,6 +477,27 @@ module top (
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assign wb_rdata[5] = wb_cyc[5] ? ep_rx_data_1 : 32'h00000000;
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+ // Warm Boot
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+ // ---------
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+
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+ // Bus interface
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+ always @(posedge clk_24m or posedge rst)
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+ if (rst) begin
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+ boot_now <= 1'b0;
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+ boot_sel <= 2'b00;
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+ end else if (wb_cyc[0] & (wb_addr[2:0] == 3'b000)) begin
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+ boot_now <= wb_wdata[2];
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+ boot_sel <= wb_wdata[1:0];
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+ end
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+
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+ // IP core
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+ SB_WARMBOOT warmboot (
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+ .BOOT(boot_now),
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+ .S0(boot_sel[0]),
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+ .S1(boot_sel[1])
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+ );
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+
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+
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// Clock / Reset
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// -------------
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