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@@ -6,58 +6,78 @@
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* Copyright (C) 2025 Krzysztof Skrzynecki, Jakub Duchniewicz <j.duchniewicz@gmail.com>
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* SPDX-License-Identifier: TODO:
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*/
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-
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`default_nettype none
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module mailbox_wb_rtl2sw #(
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- parameter AW = 4, // Address width for 16 registers (4 bits)
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- parameter DW = 32 // Data width for the Wishbone interface (32 bits)
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+ parameter AW = 4, // 16 registers => 4-bit address
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+ parameter DW = 32 // 32-bit Wishbone Data
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)(
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input wire clk,
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input wire rst,
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+
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+ // -------------------------
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// Wishbone Interface
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- input wire [AW-1:0] wb_addr,
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- output reg [DW-1:0] wb_rdata,
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- input wire wb_cyc,
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- output reg wb_ack,
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+ // -------------------------
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+ input wire [AW-1:0] wb_addr, // register index (0..15)
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+ input wire [DW-1:0] wb_wdata, // Wishbone write data
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+ input wire wb_we, // Wishbone write enable
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+ input wire wb_cyc, // Wishbone cycle (bus valid)
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+ output reg [DW-1:0] wb_rdata, // Wishbone read data
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+ output reg wb_ack, // Wishbone acknowledge
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- input wire [16*16-1:0] registers_flat_in
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+ // -------------------------
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+ // Hardware-driven inputs
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+ // (16 registers x 16 bits = 256 bits total)
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+ // -------------------------
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+ input wire [16*16-1:0] registers_flat_in
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);
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- // Internal registers (16 registers, each 16 bits wide)
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- reg [15:0] registers_array[15:0];
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+ // Internal 16-bit registers. Indices: 0..15
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+ reg [15:0] registers_array [0:15];
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- generate
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- genvar j;
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- for (j = 0; j < 16; j = j + 1) begin : unflatten_ro
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- always @(posedge clk or posedge rst) begin
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- if (rst) begin
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- registers_array[j] <= 16'h0;
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- end else begin
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- // Continuously update read-only registers
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- // from the hardware input
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- registers_array[j] <= registers_flat_in[16*(j+1)-1 : 16*j];
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- end
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- end
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- end
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- endgenerate
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-
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- // Always reset the registers on reset signal
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+ //-------------------------------------------
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+ // A single procedural always block
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+ //-------------------------------------------
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integer i;
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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+ // 1) Reset logic
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wb_ack <= 1'b0;
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for (i = 0; i < 16; i = i + 1) begin
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- registers_array[i] <= 16'h0; // Reset all registers to 0
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+ registers_array[i] <= 16'h0000;
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end
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+ wb_rdata <= 32'h0000_0000;
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end else begin
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- // Default no ack
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+ //-----------------------------------
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+ // 2) Default: no Wishbone ack
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+ //-----------------------------------
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wb_ack <= 1'b0;
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+ //-----------------------------------
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+ // 3) HW vs SW for each register
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+ // - If SW writes (wb_we) to j,
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+ // that overrides the HW input
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+ //-----------------------------------
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+ integer j;
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+ for (j = 0; j < 16; j = j + 1) begin
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+ if (wb_cyc && wb_we && (wb_addr == j)) begin
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+ // CPU write has priority this cycle
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+ registers_array[j] <= wb_wdata[15:0];
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+ end else begin
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+ // Otherwise, updated by HW input
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+ registers_array[j] <= registers_flat_in[16*(j+1)-1 : 16*j];
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+ end
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+ end
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+
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+ //-----------------------------------
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+ // 4) Wishbone read logic
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+ // - If bus is active (wb_cyc),
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+ // read out the requested register
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+ //-----------------------------------
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if (wb_cyc) begin
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- // Read operation (read the correct register based on address)
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+ wb_ack <= 1'b1;
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case (wb_addr)
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- 4'b0000: wb_rdata <= {16'h0, registers_array[0]}; // Place 16-bit value in lower half of 32-bit bus
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+ 4'b0000: wb_rdata <= {16'h0, registers_array[0]};
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4'b0001: wb_rdata <= {16'h0, registers_array[1]};
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4'b0010: wb_rdata <= {16'h0, registers_array[2]};
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4'b0011: wb_rdata <= {16'h0, registers_array[3]};
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@@ -73,13 +93,11 @@ module mailbox_wb_rtl2sw #(
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4'b1101: wb_rdata <= {16'h0, registers_array[13]};
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4'b1110: wb_rdata <= {16'h0, registers_array[14]};
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4'b1111: wb_rdata <= {16'h0, registers_array[15]};
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- default: wb_rdata <= 32'hDEAD_BEEF; // Default error value
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+ default: wb_rdata <= 32'hDEAD_BEEF;
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endcase
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-
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- // Acknowledge for exactly 1 cycle
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- wb_ack <= 1'b1;
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end
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end
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end
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endmodule
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+
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Jakub Duchniewicz