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@@ -133,7 +133,8 @@ module usb_trans (
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reg trans_dir;
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reg [2:0] ep_type;
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- reg ep_dual_buf;
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+ reg ep_bd_dual;
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+ reg ep_bd_ctrl;
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reg ep_bd_idx_cur;
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reg ep_bd_idx_nxt;
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reg ep_data_toggle;
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@@ -357,7 +358,7 @@ module usb_trans (
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assign eps_wrdata_0 = epfw_state[1] ?
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{ bd_state, trans_is_setup, 2'b00, xfer_length[9:0] } :
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- { 10'h000, ep_data_toggle, ep_bd_idx_nxt, ep_dual_buf, ep_type };
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+ { 8'h00, ep_data_toggle, ep_bd_idx_nxt, ep_bd_ctrl, ep_bd_dual, 1'b0, ep_type };
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// Delay line for what to expect on read data
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always @(posedge clk or posedge rst)
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@@ -376,13 +377,14 @@ module usb_trans (
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// EP Status
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if (epfw_cap_dl[1:0] == 2'b01) begin
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ep_type <= eps_rddata_3[2:0];
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- ep_dual_buf <= eps_rddata_3[3];
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- ep_bd_idx_cur <= eps_rddata_3[4];
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- ep_bd_idx_nxt <= eps_rddata_3[4];
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- ep_data_toggle <= eps_rddata_3[5] & ~trans_is_setup; /* For SETUP, DT == 0 */
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+ ep_bd_dual <= eps_rddata_3[4];
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+ ep_bd_ctrl <= eps_rddata_3[5];
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+ ep_bd_idx_cur <= eps_rddata_3[5] ? trans_is_setup : eps_rddata_3[6];
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+ ep_bd_idx_nxt <= eps_rddata_3[6];
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+ ep_data_toggle <= eps_rddata_3[7] & ~trans_is_setup; /* For SETUP, DT == 0 */
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end else begin
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ep_data_toggle <= ep_data_toggle ^ (mc_op_ep & mc_opcode[0]);
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- ep_bd_idx_nxt <= ep_bd_idx_nxt ^ (mc_op_ep & mc_opcode[1] & ep_dual_buf );
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+ ep_bd_idx_nxt <= ep_bd_idx_nxt ^ (mc_op_ep & mc_opcode[1] & ep_bd_dual );
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end
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// BD Word 0
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