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@@ -0,0 +1,481 @@
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+/*
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+ * hram_top.v
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+ *
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+ * vim: ts=4 sw=4
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+ *
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+ * Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com>
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+ * All rights reserved.
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+ *
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+ * BSD 3-clause, see LICENSE.bsd
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions are met:
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+ * * Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ * * Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in the
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+ * documentation and/or other materials provided with the distribution.
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+ * * Neither the name of the <organization> nor the
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+ * names of its contributors may be used to endorse or promote products
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+ * derived from this software without specific prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ */
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+
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+`default_nettype none
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+
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+module hram_top (
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+ // PHY interface
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+ output reg [ 1:0] phy_ck_en,
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+
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+ input wire [ 3:0] phy_rwds_in,
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+ output reg [ 3:0] phy_rwds_out,
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+ output reg [ 1:0] phy_rwds_oe,
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+
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+ input wire [31:0] phy_dq_in,
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+ output reg [31:0] phy_dq_out,
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+ output reg [ 1:0] phy_dq_oe,
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+
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+ output reg [ 3:0] phy_cs_n,
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+ output wire phy_rst_n,
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+
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+ // PHY configuration
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+ output wire [ 7:0] phy_cfg_wdata,
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+ input wire [ 7:0] phy_cfg_rdata,
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+ output wire phy_cfg_stb,
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+
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+ // Memory interface
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+ input wire [ 1:0] mi_addr_cs,
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+ input wire [31:0] mi_addr,
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+ input wire [ 6:0] mi_len,
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+ input wire mi_rw, /* 0=Write, 1=Read */
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+ input wire mi_linear, /* 0=Wrapped burst, 1=Linear */
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+ input wire mi_valid,
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+ output wire mi_ready,
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+
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+ input wire [31:0] mi_wdata,
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+ input wire [ 3:0] mi_wmsk,
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+ output wire mi_wack,
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+ output wire mi_wlast,
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+
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+ output wire [31:0] mi_rdata,
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+ output wire mi_rstb,
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+ output wire mi_rlast,
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+
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+ // Wishbone interface
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+ input wire [31:0] wb_wdata,
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+ output reg [31:0] wb_rdata,
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+ input wire [ 3:0] wb_addr,
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+ input wire wb_we,
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+ input wire wb_cyc,
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+ output wire wb_ack,
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+
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+ // Clock / Reset
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+ input wire clk,
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+ input wire rst
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+);
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+
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+ // FSM
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+ // ---
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+
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+ localparam
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+ ST_IDLE_CFG = 0,
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+ ST_IDLE_RUN = 1,
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+ ST_CMD_ADDR_MSB = 2,
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+ ST_CMD_ADDR_LSB = 3,
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+ ST_LATENCY = 4,
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+ ST_DATA_WRITE = 5,
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+ ST_DATA_READ = 6,
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+ ST_DONE = 7;
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+
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+ reg [3:0] state;
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+ reg [3:0] state_nxt;
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+
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+
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+ // Signals
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+ // -------
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+
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+ // Control
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+ wire running;
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+
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+ reg [ 3:0] lat_cnt;
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+ wire lat_last;
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+
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+ reg [ 7:0] xfer_cnt;
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+ wire xfer_last;
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+
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+ reg [95:0] sr_data;
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+ reg [11:0] sr_mask;
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+ reg [ 5:0] sr_oe;
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+ reg [ 1:0] sr_src;
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+ reg [ 1:0] sr_ce;
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+
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+ wire [ 1:0] cap_in;
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+ wire [ 1:0] cap_out;
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+
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+ // Current transaction
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+ reg cmd_is_read;
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+ reg cmd_is_reg;
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+ reg cmd_is_wb;
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+ reg [ 3:0] cmd_cs;
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+
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+ // Wishbone interface
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+ reg wb_ack_i;
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+
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+ reg wbi_we_csr;
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+ reg wbi_we_exec;
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+ reg wbi_we_wq_data;
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+ reg wbi_ae_wq_data;
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+ reg wbi_we_wq_attr;
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+
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+ wire wbi_cmd_now;
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+ wire [3:0] wbi_cmd_len;
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+ wire [3:0] wbi_cmd_lat;
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+ wire [1:0] wbi_cmd_cs;
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+ wire wbi_cmd_is_reg;
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+ wire wbi_cmd_is_read;
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+
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+ reg [15:0] wbi_csr;
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+ wire [31:0] wbi_csr_rd;
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+ reg [ 5:0] wbi_attr;
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+
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+
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+ // FSM
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+ // ---
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+
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+ // State register
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+ always @(posedge clk)
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+ if (rst)
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+ state <= ST_IDLE_CFG;
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+ else
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+ state <= state_nxt;
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+
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+ // Next-State logic
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+ always @(*)
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+ begin
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+ // Default is to stay put
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+ state_nxt = state;
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+
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+ // Transisions
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+ case (state)
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+ ST_IDLE_CFG:
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+ if (wbi_cmd_now)
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+ state_nxt = ST_CMD_ADDR_MSB;
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+ else if (running)
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+ state_nxt = ST_IDLE_RUN;
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+
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+ ST_IDLE_RUN:
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+ if (mi_valid)
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+ state_nxt = ST_CMD_ADDR_MSB;
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+ else if (!running)
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+ state_nxt = ST_IDLE_CFG;
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+
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+ ST_CMD_ADDR_MSB:
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+ state_nxt = ST_CMD_ADDR_LSB;
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+
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+ ST_CMD_ADDR_LSB:
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+ state_nxt = (cmd_is_reg & ~cmd_is_read) ? ST_DONE : ST_LATENCY;
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+
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+ ST_LATENCY:
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+ if (lat_last)
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+ state_nxt = cmd_is_read ? ST_DATA_READ : ST_DATA_WRITE;
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+
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+ ST_DATA_WRITE:
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+ if (xfer_last)
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+ state_nxt = ST_DONE;
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+
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+ ST_DATA_READ:
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+ if (xfer_last)
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+ state_nxt = ST_DONE;
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+
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+ ST_DONE:
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+ state_nxt = running ? ST_IDLE_RUN : ST_IDLE_CFG;
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+ endcase
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+ end
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+
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+
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+ // Control
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+ // -------
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+
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+ // State
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+ assign running = wbi_csr[0];
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+
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+ // Command latch
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+ always @(posedge clk)
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+ begin
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+ if ((state == ST_IDLE_RUN) & mi_valid)
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+ begin
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+ cmd_is_read <= mi_rw;
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+ cmd_is_reg <= 1'b0;
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+ cmd_is_wb <= 1'b0;
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+ cmd_cs <= 4'hf ^ (1 << mi_addr_cs);
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+ end
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+ else if ((state == ST_IDLE_CFG) & wbi_cmd_now)
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+ begin
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+ cmd_is_read <= wbi_cmd_is_read;
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+ cmd_is_reg <= wbi_cmd_is_reg;
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+ cmd_is_wb <= 1'b1;
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+ cmd_cs <= 4'hf ^ (1 << wbi_cmd_cs);
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+ end
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+ end
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+
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+ // Shift register control
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+ always @(*)
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+ begin
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+ // Defaults
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+ sr_ce[1] = 1'b0;
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+ sr_ce[0] = 1'b0;
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+ sr_src[1] = 1'b0;
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+ sr_src[0] = 1'b0;
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+
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+ // Memory interface Command accept
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+ if ((state == ST_IDLE_RUN) & mi_valid)
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+ begin
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+ sr_ce[1] = 1'b1;
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+ sr_src[1] = 1'b1;
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+ end
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+
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+ // Wishbone accesses
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+ if (wbi_ae_wq_data)
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+ begin
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+ sr_ce[1] = 1'b1;
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+ sr_ce[0] = 1'b1;
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+ sr_src[1] = 1'b0;
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+ sr_src[0] = 1'b1;
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+ end
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+
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+ // Config mode capture
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+ if (cap_out == 2'b01)
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+ begin
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+ sr_ce[1] = 1'b1;
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+ sr_ce[0] = 1'b1;
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+ sr_src[1] = 1'b0;
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+ sr_src[0] = 1'b0;
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+ end
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+
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+ // Normal "shift"
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+ if ((state == ST_CMD_ADDR_MSB) || (state == ST_CMD_ADDR_LSB))
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+ begin
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+ sr_ce[1] = 1'b1;
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+ sr_ce[0] = 1'b1;
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+ sr_src[1] = 1'b0;
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+ sr_src[0] = 1'b0;
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+ end
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+ end
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+
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+ // Shift register
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+ always @(posedge clk)
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+ begin
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+ // MSBs [95:32]
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+ if (sr_ce[1])
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+ begin
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+ sr_oe [ 5: 2] <= sr_src[1] ? 4'b1110 : sr_oe [3:0];
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+ sr_mask[11: 4] <= sr_src[1] ? 8'h00 : sr_mask[7:0];
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+ sr_data[95:32] <= sr_src[1] ?
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+ { mi_rw, 1'b0, mi_linear, mi_addr[31:3], 13'h0000, mi_addr[2:0], 16'h0000 } :
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+ sr_data[63:0];
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+ end
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+
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+ // LSBs [31: 0]
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+ if (sr_ce[0])
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+ begin
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+ sr_oe [ 1:0] <= sr_src[0] ? wbi_attr[5:4] : 2'b11;
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+ sr_mask[ 3:0] <= sr_src[0] ? wbi_attr[3:0] : phy_rwds_in;
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+ sr_data[31:0] <= sr_src[0] ? wb_wdata : phy_dq_in;
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+ end
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+ end
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+
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+ // Latency counter
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+ always @(posedge clk)
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+ begin
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+ if (state == ST_IDLE_RUN)
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+ lat_cnt <= wbi_csr[11:8] - 1;
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+ else if (state == ST_IDLE_CFG)
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+ lat_cnt <= wbi_cmd_lat - 1;
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+ else if (state == ST_LATENCY)
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+ lat_cnt <= lat_cnt - 1;
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+ end
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+
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+ assign lat_last = lat_cnt[3];
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+
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+ // Transfer counter
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+ always @(posedge clk)
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+ begin
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+ if (state == ST_IDLE_RUN)
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+ xfer_cnt <= { 1'b0, mi_len } - 1;
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+ else if (state == ST_IDLE_CFG)
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+ xfer_cnt <= { 4'h0, wbi_cmd_len } - 1;
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+ else if ((state == ST_DATA_WRITE) || (state == ST_DATA_READ))
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+ xfer_cnt <= xfer_cnt - 1;
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+ end
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+
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+ assign xfer_last = xfer_cnt[7];
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+
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+ // Input capture
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+ // 00 - Nothing
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+ // 01 - Capture WB
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+ // 10 - Capture MemIF
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+ // 11 - Capture MemIF last
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+ assign cap_in[1] = (state == ST_DATA_READ) & ~cmd_is_wb;
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+ assign cap_in[0] = (state == ST_DATA_READ) & (cmd_is_wb | xfer_last);
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+
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+ hram_dline #(
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+ .N(3)
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+ ) cap_I[1:0] (
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+ .di(cap_in),
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+ .do(cap_out),
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+ .delay(wbi_csr[14:12]),
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+ .clk(clk)
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+ );
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+
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+
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+ // PHY drive
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+ // ---------
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+
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+ // Main signals
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+ always @(*)
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+ begin
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+ // Defaults
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+ phy_ck_en = 2'b00;
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+ phy_rwds_out = 4'h0;
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+ phy_rwds_oe = 2'b00;
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+ phy_dq_out = sr_data[95:64];
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+ phy_dq_oe = 2'b00;
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+ phy_cs_n = 4'hf;
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+
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+ // Special per-state overrides
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+ case (state)
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+ ST_CMD_ADDR_MSB: begin
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+ phy_ck_en = 2'b11;
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+ phy_dq_oe = sr_oe[5:4];
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+ phy_cs_n = cmd_cs;
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+ end
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+
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+ ST_CMD_ADDR_LSB: begin
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+ phy_ck_en = 2'b11;
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+ phy_dq_oe = sr_oe[5:4];
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+ phy_cs_n = cmd_cs;
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+ end
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+
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+ ST_LATENCY: begin
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+ phy_ck_en = 2'b11;
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+ phy_cs_n = cmd_cs;
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+ end
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+
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+ ST_DATA_WRITE: begin
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+ phy_ck_en = 2'b11;
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+ phy_dq_oe = 2'b11;
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+ phy_rwds_oe = 2'b11;
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+ phy_dq_out = cmd_is_wb ? sr_data[95:64] : mi_wdata;
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+ phy_rwds_out = cmd_is_wb ? sr_mask[11: 8] : mi_wmsk;
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+ phy_cs_n = cmd_cs;
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+ end
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+
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+ ST_DATA_READ: begin
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+ phy_ck_en = 2'b11;
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+ phy_cs_n = cmd_cs;
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+ end
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+
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+ ST_DONE: begin
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+ phy_cs_n = cmd_cs;
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+ end
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+ endcase
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+ end
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+
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+ // OOB
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+ assign phy_rst_n = ~wbi_csr[1];
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+
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+
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+ // Memory interface
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+ // ----------------
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+
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+ assign mi_ready = (state == ST_IDLE_RUN);
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+ assign mi_wack = (state == ST_DATA_WRITE) & ~cmd_is_wb;
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+ assign mi_wlast = xfer_last;
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+
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+ assign mi_rdata = phy_dq_in;
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+ assign mi_rstb = cap_out[1];
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+ assign mi_rlast = cap_out[0];
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+
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+
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+ // Wishbone interface
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+ // ------------------
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+
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+ // Ack
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+ always @(posedge clk)
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+ wb_ack_i <= wb_cyc & ~wb_ack_i;
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+
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+ assign wb_ack = wb_ack_i;
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+
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+ // Read Mux
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+ always @(posedge clk)
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+ if (~wb_cyc | wb_ack)
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+ wb_rdata <= 32'h00000000;
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+ else
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+ case (wb_addr[1:0])
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+ 2'b00: wb_rdata <= wbi_csr_rd;
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+ 2'b10: wb_rdata <= sr_data[95:64];
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+ 2'b11: wb_rdata <= { 26'h0000000, sr_oe[5:4], sr_mask[11:8] };
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+ default: wb_rdata <= 32'hxxxxxxxx;
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+ endcase
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+
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+ assign wbi_csr_rd[31:16] = { 8'h00, phy_cfg_rdata };
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+ assign wbi_csr_rd[15: 0] = (wbi_csr & 16'hff03) | {
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+ 12'h000,
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+ (state == ST_IDLE_RUN),
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+ (state == ST_IDLE_CFG),
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+ 2'b00
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+ };
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+
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+ // Read/Write/Access Enables
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+ always @(posedge clk)
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+ begin
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+ if (wb_ack) begin
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+ wbi_we_csr <= 1'b0;
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+ wbi_we_exec <= 1'b0;
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+ wbi_we_wq_data <= 1'b0;
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+ wbi_ae_wq_data <= 1'b0;
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+ wbi_we_wq_attr <= 1'b0;
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+ end else begin
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+ wbi_we_csr <= wb_cyc & wb_we & (wb_addr[1:0] == 2'b00);
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+ wbi_we_exec <= wb_cyc & wb_we & (wb_addr[1:0] == 2'b01);
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+ wbi_we_wq_data <= wb_cyc & wb_we & (wb_addr[1:0] == 2'b10);
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+ wbi_ae_wq_data <= wb_cyc & (wb_addr[1:0] == 2'b10);
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+ wbi_we_wq_attr <= wb_cyc & wb_we & (wb_addr[1:0] == 2'b11);
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|
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+ end
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+ end
|
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+
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+ // CSR
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+ always @(posedge clk)
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+ if (rst)
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+ wbi_csr <= 16'h0000;
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+ else if (wbi_we_csr)
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+ wbi_csr <= wb_wdata[15:0];
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+
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|
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+ // PHY config
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+ assign phy_cfg_wdata = wb_wdata[23:16];
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|
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+ assign phy_cfg_stb = wbi_we_csr;
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|
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+
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|
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+ // Attrs
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+ always @(posedge clk)
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+ if (wbi_we_wq_attr)
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|
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+ wbi_attr <= wb_wdata[5:0];
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+
|
|
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+ // Command execute
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|
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+ assign wbi_cmd_now = wbi_we_exec;
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|
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+ assign wbi_cmd_len = wb_wdata[11:8];
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|
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+ assign wbi_cmd_lat = wb_wdata[ 7:4];
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+ assign wbi_cmd_cs = wb_wdata[ 3:2];
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|
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+ assign wbi_cmd_is_reg = wb_wdata[1];
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|
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+ assign wbi_cmd_is_read = wb_wdata[0];
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|
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+
|
|
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+endmodule
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Sylvain Munaut