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projects/memtest: Fix reg vs wire in sysmgr.v

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Sylvain Munaut 3 years ago
parent
commit
569cfa684b
1 changed files with 1 additions and 1 deletions
  1. 1 1
      projects/memtest/rtl/sysmgr.v

+ 1 - 1
projects/memtest/rtl/sysmgr.v

@@ -134,7 +134,7 @@ module sysmgr (
 	// -----------------
 
 	// Signals
-	reg       rst_usb_i;
+	wire      rst_usb_i;
 	reg [3:0] rst_usb_cnt;
 
 	// 48 MHz source