build: Disable some of the iverilog warnings

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

build/core-rules.mk

@@ -43,7 +43,7 @@ CORE_SIM_INCLUDES   := $(addsuffix /sim/, $(addprefix -I$(ROOT)/cores/, $(CORE_A
 
 # Simulation
 $(BUILD_TMP)/%_tb: sim/%_tb.v $(ICE40_LIBS) $(CORE_ALL_PREREQ) $(CORE_ALL_RTL_SRCS) $(CORE_ALL_SIM_SRCS)
-	iverilog -Wall -DSIM=1 -o $@ \
+	iverilog -Wall -Wno-portbind -Wno-timescale -DSIM=1 -o $@ \
 		$(CORE_SYNTH_INCLUDES) $(CORE_SIM_INCLUDES) \
 		$(addprefix -l, $(ICE40_LIBS) $(CORE_ALL_RTL_SRCS) $(CORE_ALL_SIM_SRCS)) \
 		$<

build/project-rules.mk

@@ -89,7 +89,7 @@ $(BUILD_TMP)/$(PROJ).pnr.rpt $(BUILD_TMP)/$(PROJ).asc: $(BUILD_TMP)/$(PROJ).json
 
 # Simulation
 $(BUILD_TMP)/%_tb: sim/%_tb.v $(ICE40_LIBS) $(PROJ_ALL_PREREQ) $(PROJ_ALL_RTL_SRCS) $(PROJ_ALL_SIM_SRCS)
-	$(IVERILOG) -Wall -DSIM=1 -D$(BOARD_DEFINE)=1 -o $@ \
+	$(IVERILOG) -Wall -Wno-portbind -Wno-timescale -DSIM=1 -D$(BOARD_DEFINE)=1 -o $@ \
 		$(PROJ_SYNTH_INCLUDES) $(PROJ_SIM_INCLUDES) \
 		$(addprefix -l, $(ICE40_LIBS) $(PROJ_ALL_RTL_SRCS) $(PROJ_ALL_SIM_SRCS)) \
 		$<