Browse Source

build: Use the 'library' mode of iverilog for non-top-level files

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Sylvain Munaut 6 năm trước cách đây
mục cha
commit
66218b042e
2 tập tin đã thay đổi với 6 bổ sung2 xóa
  1. 3 1
      build/core-rules.mk
  2. 3 1
      build/project-rules.mk

+ 3 - 1
build/core-rules.mk

@@ -39,7 +39,9 @@ include $(BUILD_TMP)/core-deps.mk
 
 # Simulation
 $(BUILD_TMP)/%_tb: sim/%_tb.v $(ICE40_LIBS) $(CORE_ALL_PREREQ) $(CORE_ALL_RTL_SRCS) $(CORE_ALL_SIM_SRCS)
-	iverilog -Wall -DSIM=1 -o $@ $(ICE40_LIBS) $(CORE_ALL_RTL_SRCS) $(CORE_ALL_SIM_SRCS) $<
+	iverilog -Wall -DSIM=1 -o $@ \
+		$(addprefix -l, $(ICE40_LIBS) $(CORE_ALL_RTL_SRCS) $(CORE_ALL_SIM_SRCS)) \
+		$<
 
 
 # Action targets

+ 3 - 1
build/project-rules.mk

@@ -77,7 +77,9 @@ $(BUILD_TMP)/$(PROJ).pnr.rpt $(BUILD_TMP)/$(PROJ).asc: $(BUILD_TMP)/$(PROJ).json
 
 # Simulation
 $(BUILD_TMP)/%_tb: sim/%_tb.v $(ICE40_LIBS) $(PROJ_ALL_PREREQ) $(PROJ_ALL_RTL_SRCS) $(PROJ_ALL_SIM_SRCS)
-	iverilog -Wall -DSIM=1 -o $@ $(ICE40_LIBS) $(PROJ_ALL_RTL_SRCS) $(PROJ_ALL_SIM_SRCS) $<
+	iverilog -Wall -DSIM=1 -o $@ \
+		$(addprefix -l, $(ICE40_LIBS) $(PROJ_ALL_RTL_SRCS) $(PROJ_ALL_SIM_SRCS)) \
+		$<
 
 
 # Action targets