build: Update build logic to prepare for split and out-of-tree build

- Remove the 'ROOT' variable and instead use NO2BUILD_DIR and NO2CORES_DIR
- Switch to using no2core.mk instead of core.mk

Obviously also update all cores to use this

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

build/core-magic.mk

@@ -1,12 +1,13 @@
 # Export core directory
-CORE_$(CORE)_DIR := $(abspath $(ROOT)/cores/$(CORE)/)
+penultimateword = $(wordlist $(words $1),$(words $1), x $1)
+CORE_$(CORE)_DIR := $(dir $(call penultimateword,$(MAKEFILE_LIST)))
 
 # Make the sources path absolute
 RTL_SRCS_$(CORE) := $(addprefix $(CORE_$(CORE)_DIR)/,$(RTL_SRCS_$(CORE)))
 SIM_SRCS_$(CORE) := $(addprefix $(CORE_$(CORE)_DIR)/,$(SIM_SRCS_$(CORE)))
 
 # Dependency collection target
-$(BUILD_TMP)/deps-core-$(CORE): $(CORE_$(CORE)_DIR)/core.mk $(addprefix $(BUILD_TMP)/deps-core-,$(DEPS_$(CORE)))
+$(BUILD_TMP)/deps-core-$(CORE): $(CORE_$(CORE)_DIR)/no2core.mk $(addprefix $(BUILD_TMP)/deps-core-,$(DEPS_$(CORE)))
 	$(eval CORE := $(subst $(BUILD_TMP)/deps-core-,,$@))
 	@echo "DEPS_SOLVE_TMP += $(CORE)" > $@
 	@echo "RTL_SRCS_SOLVE_TMP += $(RTL_SRCS_$(CORE))" >> $@

build/core-rules.mk

@@ -14,8 +14,14 @@ ICE40_LIBS ?= $(shell yosys-config --datdir/ice40/cells_sim.v)
 # Must be first rule and call it 'all' by convention
 all: sim
 
-# Root directory
-ROOT := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))/..)
+# Base directories
+ifeq ($(origin NO2BUILD_DIR), undefined)
+NO2BUILD_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+endif
+
+ifeq ($(origin NO2CORES_DIR), undefined)
+NO2CORES_DIR := $(abspath $(NO2BUILD_DIR)/../cores)
+endif
 
 # Temporary build-directory
 BUILD_TMP := $(abspath build-tmp)
@@ -24,7 +30,7 @@ $(BUILD_TMP):
 	mkdir -p $(BUILD_TMP)
 
 # Discover all cores
-$(foreach core_dir, $(wildcard $(ROOT)/cores/*), $(eval include $(core_dir)/core.mk))
+$(foreach core_def, $(wildcard $(NO2CORES_DIR)/*/no2core.mk), $(eval include $(core_def)))
 
 # Resolve dependency tree for project and collect sources
 $(BUILD_TMP)/core-deps.mk: Makefile $(BUILD_TMP) $(BUILD_TMP)/deps-core-$(THIS_CORE)
@@ -38,8 +44,8 @@ $(BUILD_TMP)/core-deps.mk: Makefile $(BUILD_TMP) $(BUILD_TMP)/deps-core-$(THIS_C
 include $(BUILD_TMP)/core-deps.mk
 
 # Include path
-CORE_SYNTH_INCLUDES := $(addsuffix /rtl/, $(addprefix -I$(ROOT)/cores/, $(CORE_ALL_DEPS)))
-CORE_SIM_INCLUDES   := $(addsuffix /sim/, $(addprefix -I$(ROOT)/cores/, $(CORE_ALL_DEPS)))
+CORE_SYNTH_INCLUDES := $(addsuffix /rtl/, $(addprefix -I$(NO2CORES_DIR)/, $(CORE_ALL_DEPS)))
+CORE_SIM_INCLUDES   := $(addsuffix /sim/, $(addprefix -I$(NO2CORES_DIR)/, $(CORE_ALL_DEPS)))
 
 
 # Simulation

build/project-rules.mk

@@ -23,8 +23,14 @@ ICE40_LIBS ?= $(shell yosys-config --datdir/ice40/cells_sim.v)
 # Must be first rule and call it 'all' by convention
 all: synth
 
-# Root directory
-ROOT := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))/..)
+# Base directories
+ifeq ($(origin NO2BUILD_DIR), undefined)
+NO2BUILD_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+endif
+
+ifeq ($(origin NO2CORES_DIR), undefined)
+NO2CORES_DIR := $(abspath $(NO2BUILD_DIR)/../cores)
+endif
 
 # Temporary build-directory
 BUILD_TMP := $(abspath build-tmp)
@@ -33,7 +39,7 @@ $(BUILD_TMP):
 	mkdir -p $(BUILD_TMP)
 
 # Discover all cores
-$(foreach core_dir, $(wildcard $(ROOT)/cores/*), $(eval include $(core_dir)/core.mk))
+$(foreach core_def, $(wildcard $(NO2CORES_DIR)/*/no2core.mk), $(eval include $(core_def)))
 
 # Resolve dependency tree for project and collect sources
 $(BUILD_TMP)/proj-deps.mk: Makefile $(BUILD_TMP) $(addprefix $(BUILD_TMP)/deps-core-,$(PROJ_DEPS))
@@ -62,8 +68,8 @@ PROJ_ALL_SIM_SRCS += $(PROJ_SIM_SRCS)
 PROJ_ALL_PREREQ += $(PROJ_PREREQ)
 
 # Include path
-PROJ_SYNTH_INCLUDES := -I$(abspath rtl/) $(addsuffix /rtl/, $(addprefix -I$(ROOT)/cores/, $(PROJ_ALL_DEPS)))
-PROJ_SIM_INCLUDES   := -I$(abspath sim/) $(addsuffix /sim/, $(addprefix -I$(ROOT)/cores/, $(PROJ_ALL_DEPS)))
+PROJ_SYNTH_INCLUDES := -I$(abspath rtl/) $(addsuffix /rtl/, $(addprefix -I$(NO2CORES_DIR)/, $(PROJ_ALL_DEPS)))
+PROJ_SIM_INCLUDES   := -I$(abspath sim/) $(addsuffix /sim/, $(addprefix -I$(NO2CORES_DIR)/, $(PROJ_ALL_DEPS)))
 
 
 # Synthesis & Place-n-route rules

cores/e1/Makefile

@@ -1,3 +1,4 @@
 CORE := e1
 
-include ../../build/core-rules.mk
+NO2BUILD_DIR ?= $(abspath ../../build)
+include $(NO2BUILD_DIR)/core-rules.mk

cores/e1/core.mk

@@ -23,4 +23,4 @@ TESTBENCHES_e1 := \
 	e1_tx_framer_tb \
 	hdb3_tb \
 
-include $(ROOT)/build/core-magic.mk
+include $(NO2BUILD_DIR)/core-magic.mk

cores/hub75/Makefile

@@ -1,3 +1,4 @@
 CORE := hub75
 
-include ../../build/core-rules.mk
+NO2BUILD_DIR ?= $(abspath ../../build)
+include $(NO2BUILD_DIR)/core-rules.mk

cores/hub75/core.mk

@@ -25,7 +25,7 @@ TESTBENCHES_hub75 := \
 PREREQ_hub75 := \
 	$(BUILD_TMP)/gamma_table.hex
 
-include $(ROOT)/build/core-magic.mk
+include $(NO2BUILD_DIR)/core-magic.mk
 
 $(BUILD_TMP)/gamma_table.hex: $(CORE_hub75_DIR)/sw/mkgamma.py
 	$(CORE_hub75_DIR)/sw/mkgamma.py > $@

cores/hyperram/Makefile

@@ -1,3 +1,4 @@
 CORE := hyperram
 
-include ../../build/core-rules.mk
+NO2BUILD_DIR ?= $(abspath ../../build)
+include $(NO2BUILD_DIR)/core-rules.mk

cores/hyperram/core.mk

@@ -10,4 +10,4 @@ TESTBENCHES_hyperram := \
 	hram_top_tb \
 	$(NULL)
 
-include $(ROOT)/build/core-magic.mk
+include $(NO2BUILD_DIR)/core-magic.mk

cores/ice40/Makefile

@@ -1,3 +1,4 @@
 CORE := ice40
 
-include ../../build/core-rules.mk
+NO2BUILD_DIR ?= $(abspath ../../build)
+include $(NO2BUILD_DIR)/core-rules.mk

cores/ice40/core.mk

@@ -14,4 +14,4 @@ TESTBENCHES_ice40 := \
 	ice40_ebr_tb \
 	$(NULL)
 
-include $(ROOT)/build/core-magic.mk
+include $(NO2BUILD_DIR)/core-magic.mk

cores/mem_cache/Makefile

@@ -1,3 +1,4 @@
 CORE := mem_cache
 
-include ../../build/core-rules.mk
+NO2BUILD_DIR ?= $(abspath ../../build)
+include $(NO2BUILD_DIR)/core-rules.mk

cores/mem_cache/core.mk

@@ -19,4 +19,4 @@ TESTBENCHES_mem_cache := \
 	mem_sim_tb \
 	$(NULL)
 
-include $(ROOT)/build/core-magic.mk
+include $(NO2BUILD_DIR)/core-magic.mk

cores/misc/Makefile

@@ -1,3 +1,4 @@
 CORE := misc
 
-include ../../build/core-rules.mk
+NO2BUILD_DIR ?= $(abspath ../../build)
+include $(NO2BUILD_DIR)/core-rules.mk

cores/misc/core.mk

@@ -21,4 +21,4 @@ TESTBENCHES_misc := \
 	pdm_tb \
 	uart_tb \
 
-include $(ROOT)/build/core-magic.mk
+include $(NO2BUILD_DIR)/core-magic.mk

cores/qspi_master/Makefile

@@ -1,3 +1,4 @@
 CORE := qspi_master
 
-include ../../build/core-rules.mk
+NO2BUILD_DIR ?= $(abspath ../../build)
+include $(NO2BUILD_DIR)/core-rules.mk

cores/qspi_master/core.mk

@@ -13,4 +13,4 @@ TESTBENCHES_qspi_master := \
 	qspi_master_tb \
 	$(NULL)
 
-include $(ROOT)/build/core-magic.mk
+include $(NO2BUILD_DIR)/core-magic.mk

cores/spi_flash/Makefile

@@ -1,3 +1,4 @@
 CORE := spi_flash
 
-include ../../build/core-rules.mk
+NO2BUILD_DIR ?= $(abspath ../../build)
+include $(NO2BUILD_DIR)/core-rules.mk

cores/spi_flash/core.mk

@@ -7,4 +7,4 @@ RTL_SRCS_spi_flash := $(addprefix rtl/, \
 TESTBENCHES_spi_flash := \
 	spi_flash_reader_tb
 
-include $(ROOT)/build/core-magic.mk
+include $(NO2BUILD_DIR)/core-magic.mk

cores/spi_slave/Makefile

@@ -1,3 +1,4 @@
 CORE := spi_slave
 
-include ../../build/core-rules.mk
+NO2BUILD_DIR ?= $(abspath ../../build)
+include $(NO2BUILD_DIR)/core-rules.mk

cores/spi_slave/core.mk

@@ -11,4 +11,4 @@ TESTBENCHES_spi_slave := \
 	spi_fast_core_tb \
 	spi_tb
 
-include $(ROOT)/build/core-magic.mk
+include $(NO2BUILD_DIR)/core-magic.mk

cores/usb/Makefile

@@ -1,3 +1,4 @@
 CORE := usb
 
-include ../../build/core-rules.mk
+NO2BUILD_DIR ?= $(abspath ../../build)
+include $(NO2BUILD_DIR)/core-rules.mk

cores/usb/core.mk

@@ -15,8 +15,8 @@ RTL_SRCS_usb := $(addprefix rtl/, \
 	usb_tx_pkt.v \
 )
 
-PREREQ_usb := \
-	$(ROOT)/cores/usb/rtl/usb_defs.vh \
+PREREQ_usb = \
+	$(CORE_usb_DIR)/rtl/usb_defs.vh \
 	$(BUILD_TMP)/usb_trans_mc.hex \
 	$(BUILD_TMP)/usb_ep_status.hex
 
@@ -25,10 +25,10 @@ TESTBENCHES_usb := \
 	usb_tb \
 	usb_tx_tb
 
-$(BUILD_TMP)/usb_trans_mc.hex: $(ROOT)/cores/usb/utils/microcode.py
-	$(ROOT)/cores/usb/utils/microcode.py > $@
+include $(NO2BUILD_DIR)/core-magic.mk
 
-$(BUILD_TMP)/usb_ep_status.hex: $(ROOT)/cores/usb/data/usb_ep_status.hex
-	cp -a $< $@
+$(BUILD_TMP)/usb_trans_mc.hex: $(CORE_usb_DIR)/utils/microcode.py
+	$(CORE_usb_DIR)/utils/microcode.py > $@
 
-include $(ROOT)/build/core-magic.mk
+$(BUILD_TMP)/usb_ep_status.hex: $(CORE_usb_DIR)/data/usb_ep_status.hex
+	cp -a $< $@

cores/video/Makefile

@@ -1,3 +1,4 @@
 CORE := video
 
-include ../../build/core-rules.mk
+NO2BUILD_DIR ?= $(abspath ../../build)
+include $(NO2BUILD_DIR)/core-rules.mk

cores/video/core.mk

@@ -11,4 +11,4 @@ RTL_SRCS_video := $(addprefix rtl/, \
 	vid_tgen.v \
 )
 
-include $(ROOT)/build/core-magic.mk
+include $(NO2BUILD_DIR)/core-magic.mk