By default it only looks in the first few lines of the file ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
@@ -1,6 +1,8 @@
/*
* hub75_bcm.v
*
+ * vim: ts=4 sw=4
+ *
* Copyright (C) 2019 Sylvain Munaut <tnt@246tNt.com>
* All rights reserved.
@@ -19,8 +21,6 @@
* You should have received a copy of the GNU Lesser General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- *
- * vim: ts=4 sw=4
*/
`default_nettype none
* hub75_blanking.v
* hub75_colormap.v
* hub75_fb_readout.v
* hub75_fb_writein.v
* hub75_framebuffer.v
* hub75_gamma.v
* hub75_linebuffer.v
* hub75_phy.v
* Copyright (C) 2019 Piotr Esden-Tempski <piotr@esden.net>
@@ -20,8 +22,6 @@
* hub75_scan.v
* hub75_shift.v
* hub75_top.v
* delay.v
* Generates a delay line/bus
@@ -29,13 +31,9 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-`ifdef SIM
-`endif
// ---------------------------------------------------------------------------
// Single line delay
* glitch_filter.v
@@ -27,8 +29,6 @@
* prims.v
* pwm.v
* ram_sdp.v
* fifo_tb.v
* spi_flash_reader.v
* spi_flash_reader_tb.v
* spi_fast.v
* spi_fast_core.v
* spi_reg.v
* spi_simple.v
* spi_fast_core_tb.v
* spi_tb.v
* hdmi_phy_2x.v
* HDMI PHY using DDR output to push 2 pixels at once allowing FPGA code
* to run at half the pixel clock.
@@ -30,8 +32,6 @@
* hdmi_text_2x.v
* HDMI text generator core top level running in 1:2 mode
@@ -29,8 +31,6 @@
* vid_shared_ram.v
* vid_text.v
* Video Text Mode generator
* vid_tgen.v
* Video Timing Generator