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@@ -1,233 +0,0 @@
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-/*
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- * uart2wb.v
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- *
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- * vim: ts=4 sw=4
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- *
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- * Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com>
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- * All rights reserved.
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- *
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- * BSD 3-clause, see LICENSE.bsd
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- *
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- * Redistribution and use in source and binary forms, with or without
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- * modification, are permitted provided that the following conditions are met:
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- * * Redistributions of source code must retain the above copyright
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- * notice, this list of conditions and the following disclaimer.
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- * * Redistributions in binary form must reproduce the above copyright
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- * notice, this list of conditions and the following disclaimer in the
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- * documentation and/or other materials provided with the distribution.
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- * * Neither the name of the <organization> nor the
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- * names of its contributors may be used to endorse or promote products
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- * derived from this software without specific prior written permission.
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- *
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- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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- * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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- */
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-
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-`default_nettype none
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-
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-module uart2wb #(
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- parameter integer WB_N = 3,
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-
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- // auto
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- parameter integer DL = (32*WB_N)-1,
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- parameter integer CL = WB_N-1
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-)(
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- // UART
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- input wire uart_rx,
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- output wire uart_tx,
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-
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- input wire [ 7:0] uart_div,
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-
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- // Wishbone
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- output reg [31:0] wb_wdata,
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- input wire [DL:0] wb_rdata,
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- output reg [15:0] wb_addr,
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- output reg wb_we,
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- output reg [CL:0] wb_cyc,
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- input wire [CL:0] wb_ack,
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-
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- // Aux-CSR
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- output reg [31:0] aux_csr,
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-
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- // Clock / Reset
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- input wire clk,
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- input wire rst
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-);
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-
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- localparam
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- CMD_SYNC = 4'h0,
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- CMD_REG_ACCESS = 4'h1,
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- CMD_DATA_SET = 4'h2,
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- CMD_DATA_GET = 4'h3,
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- CMD_AUX_CSR = 4'h4;
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-
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-
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- // Signals
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- // -------
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-
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- // UART serdes
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- wire [7:0] rx_data;
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- wire rx_stb;
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-
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- wire [7:0] tx_data;
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- wire tx_ack;
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- wire tx_valid;
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-
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- // Command RX
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- reg [39:0] rx_reg;
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- reg [ 2:0] rx_cnt;
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-
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- wire [ 3:0] cmd_code;
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- wire [31:0] cmd_data;
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- reg cmd_stb;
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-
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- // Response TX
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- reg [31:0] tx_reg;
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- reg [ 2:0] tx_cnt;
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-
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- reg [31:0] resp_data;
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- reg resp_ld;
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-
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- // Wishbone interface
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- reg [31:0] wb_rdata_i;
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- wire wb_ack_i;
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-
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-
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- // Host interface
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- // --------------
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-
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- // UART module
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- uart_rx #(
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- .DIV_WIDTH(8),
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- .GLITCH_FILTER(0)
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- ) rx_I (
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- .rx(uart_rx),
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- .data(rx_data),
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- .stb(rx_stb),
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- .div(uart_div),
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- .clk(clk),
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- .rst(rst)
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- );
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-
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- uart_tx #(
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- .DIV_WIDTH(8)
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- ) tx_I (
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- .tx(uart_tx),
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- .data(tx_data),
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- .valid(tx_valid),
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- .ack(tx_ack),
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- .div(uart_div),
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- .clk(clk),
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- .rst(rst)
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- );
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-
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- // Command input
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- always @(posedge clk or posedge rst)
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- if (rst)
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- rx_cnt <= 3'd0;
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- else if (rx_stb)
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- rx_cnt <= rx_cnt[2] ? 3'd0 : (rx_cnt + 1);
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-
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- always @(posedge clk)
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- if (rx_stb)
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- rx_reg <= { rx_reg[31:0], rx_data };
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-
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- assign cmd_code = rx_reg[39:36];
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- assign cmd_data = rx_reg[31: 0];
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-
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- always @(posedge clk)
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- cmd_stb <= rx_cnt[2] & rx_stb;
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-
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- // Response output
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- always @(posedge clk or posedge rst)
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- if (rst)
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- tx_cnt <= 3'd0;
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- else begin
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- if (resp_ld)
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- tx_cnt <= 3'd4;
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- else if (tx_ack)
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- tx_cnt <= tx_cnt - 1;
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- end
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-
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- always @(posedge clk)
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- if (resp_ld)
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- tx_reg <= resp_data;
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- else if (tx_ack)
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- tx_reg <= { tx_reg[23:0], 8'h00 };
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-
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- assign tx_data = tx_reg[31:24];
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- assign tx_valid = |tx_cnt;
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-
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- // Commands
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- always @(posedge clk)
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- begin
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- // Defaults
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- resp_ld <= 1'b0;
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- resp_data <= 40'hxxxxxxxxxx;
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-
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- // Commands
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- if (cmd_stb) begin
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- case (cmd_code)
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- CMD_SYNC: begin
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- resp_data <= 432'hcafebabe;
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- resp_ld <= 1'b1;
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- end
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-
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- CMD_REG_ACCESS: begin
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- wb_addr <= cmd_data[15:0];
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- wb_we <= ~cmd_data[20];
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- wb_cyc <= (1 << cmd_data[19:16]);
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- end
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-
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- CMD_DATA_SET: begin
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- wb_wdata <= cmd_data;
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- end
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-
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- CMD_DATA_GET: begin
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- resp_ld <= 1'b1;
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- resp_data <= wb_wdata;
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- end
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-
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- CMD_AUX_CSR: begin
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- aux_csr <= cmd_data;
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- end
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- endcase
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- end
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-
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- if (wb_ack_i) begin
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- // Cycle done
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- wb_cyc <= 0;
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-
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- // Capture read response
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- if (~wb_we)
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- wb_wdata <= wb_rdata_i;
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- end
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-
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- if (rst) begin
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- wb_cyc <= 0;
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- aux_csr <= 32'h00000000;
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- end
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- end
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-
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- // Wishbone multi-slave handling
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- assign wb_ack_i = |wb_ack;
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-
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- always @(*)
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- begin : rdata
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- integer i;
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-
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- wb_rdata_i = 32'h00000000;
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-
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- for (i=0; i<WB_N; i=i+1)
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- wb_rdata_i = wb_rdata_i | wb_rdata[32*i+:32];
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- end
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-
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-endmodule
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Sylvain Munaut