projects/riscv_usb: Add support for write mask to WB bus

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

projects/riscv_usb/rtl/bridge.v

@@ -64,6 +64,7 @@ module bridge #(
 	/* Wishbone buses */
 	output wire [WB_AW-1:0] wb_addr,
 	output wire [WB_DW-1:0] wb_wdata,
+	output wire [(WB_DW/8)-1:0] wb_wmsk,
 	input  wire [(WB_DW*WB_N)-1:0] wb_rdata,
 	output wire [WB_N-1:0] wb_cyc,
 	output wire wb_we,
@@ -118,6 +119,7 @@ module bridge #(
 
 	assign wb_addr  = pb_addr[WB_AW+WB_AI-1:WB_AI];
 	assign wb_wdata = pb_wdata[WB_DW-1:0];
+	assign wb_wmsk  = pb_wstrb[(WB_DW/8)-1:0];
 	assign wb_we    = |pb_wstrb;
 
 	for (i=0; i<WB_N; i=i+1)

projects/riscv_usb/rtl/top.v

@@ -95,6 +95,7 @@ module top (
 	// Wishbone
 	wire [WB_AW-1:0] wb_addr;
 	wire [WB_DW-1:0] wb_wdata;
+	wire [(WB_DW/8)-1:0] wb_wmsk;
 	wire [WB_DW-1:0] wb_rdata [0:WB_N-1];
 	wire [(WB_DW*WB_N)-1:0] wb_rdata_flat;
 	wire [WB_N-1:0] wb_cyc;
@@ -202,6 +203,7 @@ module top (
 		.spram_we(spram_we),
 		.wb_addr(wb_addr),
 		.wb_wdata(wb_wdata),
+		.wb_wmsk(wb_wmsk),
 		.wb_rdata(wb_rdata_flat),
 		.wb_cyc(wb_cyc),
 		.wb_we(wb_we),