cores/misc: Import misc cores

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

cores/misc/Makefile

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+CORE := misc
+
+include ../../build/core-rules.mk

cores/misc/README.md

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+Misc
+====
+
+This contains a collection of small utility cores.
+
+These cores are licensed under the BSD 3-clause licence (see LICENSE.bsd)

cores/misc/core.mk

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+CORE := misc
+
+RTL_SRCS_misc = $(addprefix rtl/, \
+	glitch_filter.v \
+	ram_sdp.v \
+	pwm.v \
+)
+
+include $(ROOT)/build/core-magic.mk

cores/misc/rtl/glitch_filter.v

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+/*
+ * glitch_filter.v
+ *
+ * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
+ * All rights reserved.
+ *
+ * BSD 3-clause, see LICENSE.bsd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of the <organization> nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * vim: ts=4 sw=4
+ */
+
+`default_nettype none
+
+module glitch_filter #(
+	parameter integer L = 2
+)(
+	input wire  pin_iob_reg,
+	input wire  cond,
+
+	output wire val,
+	output reg  rise,
+	output reg  fall,
+
+	input  wire clk,
+	input  wire rst
+);
+	// Signals
+	wire [L-1:0] all_zero;
+	wire [L-1:0] all_one;
+
+	reg [1:0] sync;
+	reg state;
+	reg [L-1:0] cnt;
+
+	// Constants
+	assign all_zero = { L{1'b0} };
+	assign all_one  = { L{1'b1} };
+
+	// Synchronizer
+	always @(posedge clk)
+		sync <= { sync[0], pin_iob_reg };
+
+	// Filter
+	always @(posedge clk)
+		if (rst)
+			cnt <= all_one;
+		else begin
+			if (sync[1] & (cnt != all_one))
+				cnt <= cnt + 1;
+			else if (~sync[1] & (cnt != all_zero))
+				cnt <= cnt - 1;
+			else
+				cnt <= cnt;
+		end
+
+	// State
+	always @(posedge clk)
+		if (rst)
+			state <= 1'b1;
+		else begin
+			if (state & cnt == all_zero)
+				state <= 1'b0;
+			else if (~state & cnt == all_one)
+				state <= 1'b1;
+			else
+				state <= state;
+		end
+
+	assign val = state;
+
+	// Rise / Fall detection
+	always @(posedge clk)
+	begin
+		if (~cond) begin
+			rise <= 1'b0;
+			fall <= 1'b0;
+		end else begin
+			rise <= ~state & (cnt == all_one);
+			fall <=  state & (cnt == all_zero);
+		end
+	end
+
+endmodule // glitch_filter

cores/misc/rtl/pwm.v

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+/*
+ * pwm.v
+ *
+ * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
+ * All rights reserved.
+ *
+ * BSD 3-clause, see LICENSE.bsd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of the <organization> nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * vim: ts=4 sw=4
+ */
+
+`default_nettype none
+
+module pwm #(
+	parameter integer WIDTH = 10
+)(
+	// PWM out
+	output wire pwm,
+
+	// Config
+	input wire [WIDTH-1:0] cfg_val,
+
+	// Clock / Reset
+	input wire  clk,
+	input wire  rst
+);
+	wire [WIDTH:0] cnt_cycle_rst;
+	reg [WIDTH:0] cnt_cycle;
+	reg [WIDTH:0] cnt_on;
+
+	assign cnt_cycle_rst = { { (WIDTH-1){1'b0} }, 2'b10 };
+
+	always @(posedge clk or posedge rst)
+		if (rst)
+			cnt_cycle <= cnt_cycle_rst;
+		else
+			cnt_cycle <= cnt_cycle[WIDTH] ? cnt_cycle_rst : (cnt_cycle + 1);
+
+	always @(posedge clk or posedge rst)
+		if (rst)
+			cnt_on <= 0;
+		else
+			cnt_on <= (cnt_cycle[WIDTH] ? { 1'b1, cfg_val } : cnt_on) - 1;
+
+	assign pwm = cnt_on[WIDTH];
+
+endmodule // pwm

cores/misc/rtl/ram_sdp.v

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+/*
+ * ram_sdp.v
+ *
+ * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
+ * All rights reserved.
+ *
+ * BSD 3-clause, see LICENSE.bsd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of the <organization> nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * vim: ts=4 sw=4
+ */
+
+`default_nettype none
+
+module ram_sdp #(
+	parameter integer AWIDTH = 9,
+    parameter integer DWIDTH = 8
+)(
+	input  wire [AWIDTH-1:0] wr_addr,
+	input  wire [DWIDTH-1:0] wr_data,
+	input  wire wr_ena,
+
+	input  wire [AWIDTH-1:0] rd_addr,
+	output reg  [DWIDTH-1:0] rd_data,
+	input  wire rd_ena,
+
+	input  wire clk
+);
+	// Signals
+	reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
+
+`ifdef SIM
+	integer i;
+	initial
+		for (i=0; i<(1<<AWIDTH); i=i+1)
+			ram[i] = 0;
+`endif
+
+	always @(posedge clk)
+	begin
+		// Read
+		if (rd_ena)
+			rd_data <= ram[rd_addr];
+
+		// Write
+		if (wr_ena)
+			ram[wr_addr] <= wr_data;
+	end
+
+endmodule // ram_sdp