Distinguish between two kinds of mailboxes RTL2SW and SW2RTL.

Signed-off-by: Jakub Duchniewicz <j.duchniewicz@gmail.com>

projects/riscv_usb/Makefile

@@ -13,7 +13,8 @@ PROJ_RTL_SRCS := $(addprefix rtl/, \
 	sysmgr.v \
 	3signal.v \
 	button.v \
-	mailbox_wb.v \
+	mailbox_wb_sw2rtl.v \
+	mailbox_wb_rtl2sw.v \
 )
 PROJ_SIM_SRCS := $(addprefix sim/, \
 	spiflash.v \

projects/riscv_usb/fw/config.h

@@ -27,4 +27,4 @@
 #define SPI_BASE	         0x82000000
 #define LED_BASE	         0x83000000
 #define MAILBOX_REGS_BASE    0x84000000
-#define MAILBOX_BUTTONS_BASE 0x84000000
+#define MAILBOX_BUTTONS_BASE 0x85000000

projects/riscv_usb/rtl/mailbox_wb_rtl2sw.v

@@ -0,0 +1,85 @@
+/*
+ * mailbox_wb_rtl2sw.v
+ *
+ * vim: ts=4 sw=4
+ *
+ * Copyright (C) 2025 Krzysztof Skrzynecki, Jakub Duchniewicz <j.duchniewicz@gmail.com>
+ * SPDX-License-Identifier: TODO:
+ */
+
+`default_nettype none
+
+module mailbox_wb_rtl2sw #(
+    parameter AW = 4,  // Address width for 16 registers (4 bits)
+    parameter DW = 32   // Data width for the Wishbone interface (32 bits)
+)(
+    input  wire             clk,
+    input  wire             rst,
+    // Wishbone Interface
+    input  wire [AW-1:0]    wb_addr,
+    output reg  [DW-1:0]    wb_rdata,
+    input  wire             wb_cyc,
+    output reg              wb_ack,
+
+    input wire [16*16-1:0] registers_flat_in
+);
+
+    // Internal registers (16 registers, each 16 bits wide)
+    reg [15:0] registers_array[15:0];
+
+    generate
+        genvar j;
+        for (j = 0; j < 16; j = j + 1) begin : unflatten_ro
+            always @(posedge clk or posedge rst) begin
+                if (rst) begin
+                    registers_array[j] <= 16'h0;
+                end else begin
+                    // Continuously update read-only registers
+                    // from the hardware input
+                    registers_array[j] <= registers_flat_in[16*(j+1)-1 : 16*j];
+                end
+            end
+        end
+    endgenerate
+
+    // Always reset the registers on reset signal
+    integer i;
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            wb_ack <= 1'b0;
+            for (i = 0; i < 16; i = i + 1) begin
+                registers_array[i] <= 16'h0; // Reset all registers to 0
+            end
+        end else begin
+            // Default no ack
+            wb_ack <= 1'b0;
+
+            if (wb_cyc) begin
+                // Read operation (read the correct register based on address)
+                case (wb_addr)
+                    4'b0000: wb_rdata <= {16'h0, registers_array[0]}; // Place 16-bit value in lower half of 32-bit bus
+                    4'b0001: wb_rdata <= {16'h0, registers_array[1]};
+                    4'b0010: wb_rdata <= {16'h0, registers_array[2]};
+                    4'b0011: wb_rdata <= {16'h0, registers_array[3]};
+                    4'b0100: wb_rdata <= {16'h0, registers_array[4]};
+                    4'b0101: wb_rdata <= {16'h0, registers_array[5]};
+                    4'b0110: wb_rdata <= {16'h0, registers_array[6]};
+                    4'b0111: wb_rdata <= {16'h0, registers_array[7]};
+                    4'b1000: wb_rdata <= {16'h0, registers_array[8]};
+                    4'b1001: wb_rdata <= {16'h0, registers_array[9]};
+                    4'b1010: wb_rdata <= {16'h0, registers_array[10]};
+                    4'b1011: wb_rdata <= {16'h0, registers_array[11]};
+                    4'b1100: wb_rdata <= {16'h0, registers_array[12]};
+                    4'b1101: wb_rdata <= {16'h0, registers_array[13]};
+                    4'b1110: wb_rdata <= {16'h0, registers_array[14]};
+                    4'b1111: wb_rdata <= {16'h0, registers_array[15]};
+                    default: wb_rdata <= 32'hDEAD_BEEF; // Default error value
+                endcase
+
+                // Acknowledge for exactly 1 cycle
+                wb_ack <= 1'b1;
+            end
+        end
+    end
+
+endmodule

projects/riscv_usb/rtl/mailbox_wb.v

@@ -9,7 +9,7 @@
 
 `default_nettype none
 
-module mailbox_wb #(
+module mailbox_wb_sw2rtl #(
     parameter AW = 4,  // Address width for 16 registers (4 bits)
     parameter DW = 32   // Data width for the Wishbone interface (32 bits)
 )(

projects/riscv_usb/rtl/top.v

@@ -102,22 +102,22 @@ module top (
     wire write_flash;
 
     // Buttons
-    wire [BUTTON_COUNTER_WIDTH-1:0] inc_f1;
-    wire [BUTTON_COUNTER_WIDTH-1:0] dec_f1;
-    wire [BUTTON_COUNTER_WIDTH-1:0] inc_d1;
-    wire [BUTTON_COUNTER_WIDTH-1:0] dec_d1;
-    wire [BUTTON_COUNTER_WIDTH-1:0] inc_d2;
-    wire [BUTTON_COUNTER_WIDTH-1:0] dec_d2;
-    wire [BUTTON_COUNTER_WIDTH-1:0] inc_ph2;
-    wire [BUTTON_COUNTER_WIDTH-1:0] dec_ph2;
-    wire [BUTTON_COUNTER_WIDTH-1:0] inc_f3;
-    wire [BUTTON_COUNTER_WIDTH-1:0] dec_f3;
-    wire [BUTTON_COUNTER_WIDTH-1:0] inc_d3;
-    wire [BUTTON_COUNTER_WIDTH-1:0] dec_d3;
-    wire [BUTTON_COUNTER_WIDTH-1:0] inc_ph3;
-    wire [BUTTON_COUNTER_WIDTH-1:0] dec_ph3;
-    wire [BUTTON_COUNTER_WIDTH-1:0] inc_n3;
-    wire [BUTTON_COUNTER_WIDTH-1:0] dec_n3;
+    reg [BUTTON_COUNTER_WIDTH-1:0] inc_f1;
+    reg [BUTTON_COUNTER_WIDTH-1:0] dec_f1;
+    reg [BUTTON_COUNTER_WIDTH-1:0] inc_d1;
+    reg [BUTTON_COUNTER_WIDTH-1:0] dec_d1;
+    reg [BUTTON_COUNTER_WIDTH-1:0] inc_d2;
+    reg [BUTTON_COUNTER_WIDTH-1:0] dec_d2;
+    reg [BUTTON_COUNTER_WIDTH-1:0] inc_ph2;
+    reg [BUTTON_COUNTER_WIDTH-1:0] dec_ph2;
+    reg [BUTTON_COUNTER_WIDTH-1:0] inc_f3;
+    reg [BUTTON_COUNTER_WIDTH-1:0] dec_f3;
+    reg [BUTTON_COUNTER_WIDTH-1:0] inc_d3;
+    reg [BUTTON_COUNTER_WIDTH-1:0] dec_d3;
+    reg [BUTTON_COUNTER_WIDTH-1:0] inc_ph3;
+    reg [BUTTON_COUNTER_WIDTH-1:0] dec_ph3;
+    reg [BUTTON_COUNTER_WIDTH-1:0] inc_n3;
+    reg [BUTTON_COUNTER_WIDTH-1:0] dec_n3;
 
 	// Mailbox signal wires
     wire [16*16-1:0] mailbox_regs_flat;  // Flattened register array (16 registers of 16 bits each)
@@ -220,7 +220,7 @@ module top (
 
 	// WB Register Mailbox [4]
 	// ----------
-	mailbox_wb #(
+	mailbox_wb_sw2rtl #(
 		.AW(4),
 		.DW(WB_DW)
 	) mailbox_regs_I (
@@ -273,48 +273,44 @@ module top (
 
 	// WB Button Mailbox [5]
 	// ----------
-	mailbox_wb #(
+	mailbox_wb_rtl2sw #(
 		.AW(4),
 		.DW(WB_DW)
 	) mailbox_btns_I (
 		.clk(clk_24m),
 		.rst(rst),
 		.wb_addr(wb_addr[3:0]),
-		.wb_wdata(wb_wdata),
 		.wb_rdata(wb_rdata[5]),
-		.wb_we(wb_we),
 		.wb_cyc(wb_cyc[5]),
 		.wb_ack(wb_ack[5]),
-		.registers_flat(mailbox_btns_flat)
+		.registers_flat_in(mailbox_btns_flat)
 	);
 
 
     // Buttons
-    assign inc_f1 = mailbox_btns_flat[15:0];
-    assign dec_f1 = mailbox_btns_flat[31:16];
-    assign inc_d1 = mailbox_btns_flat[47:32];
-    assign dec_d1 = mailbox_btns_flat[63:48];
-    assign inc_d2 = mailbox_btns_flat[79:64];
-    assign dec_d2 = mailbox_btns_flat[95:80];
-    assign inc_ph2 = mailbox_btns_flat[111:96];
-    assign dec_ph2 = mailbox_btns_flat[127:112];
-    assign inc_f3 = mailbox_btns_flat[143:128];
-    assign dec_f3 = mailbox_btns_flat[159:144];
-    assign inc_d3 = mailbox_btns_flat[175:160];
-    assign dec_d3 = mailbox_btns_flat[191:176];
-    assign inc_ph3 = mailbox_btns_flat[207:192];
-    assign dec_ph3 = mailbox_btns_flat[223:208];
-    assign inc_n3 = mailbox_btns_flat[239:224];
-    assign dec_n3 = mailbox_btns_flat[255:240];
-
-	reg [31:0] pcount; //dummy variable + usage to make sure button will not be optimized out
+    assign mailbox_btns_flat[15:0] = inc_f1;
+    assign mailbox_btns_flat[31:16] = dec_f1;
+    assign mailbox_btns_flat[47:32] = inc_d1;
+    assign mailbox_btns_flat[63:48] = dec_d1;
+    assign mailbox_btns_flat[79:64] = inc_d2;
+    assign mailbox_btns_flat[95:80] = dec_d2;
+    assign mailbox_btns_flat[111:96] = inc_ph2;
+    assign mailbox_btns_flat[127:112] = dec_ph2;
+    assign mailbox_btns_flat[143:128] = inc_f3;
+    assign mailbox_btns_flat[159:144] = dec_f3;
+    assign mailbox_btns_flat[175:160] = inc_d3;
+    assign mailbox_btns_flat[191:176] = dec_d3;
+    assign mailbox_btns_flat[207:192] = inc_ph3;
+    assign mailbox_btns_flat[223:208] = dec_ph3;
+    assign mailbox_btns_flat[239:224] = inc_n3;
+    assign mailbox_btns_flat[255:240] = dec_n3;
 
 	button b1(
 		.clk(clk_24m),
 		.nrst(~rst),
 		.butt(btn_1),
 
-		.press_count(pcount)
+		.press_count(inc_f1)
 	);
 
     // TODO: dummy led onoff when value has been written
@@ -322,7 +318,7 @@ module top (
         if (rst) begin
             led[0] = 1'b0;
             led[1] = 1'b0;
-            led[2] = 1'b0 & pcount[25];
+            led[2] = 1'b0;
         end else if (period1 == 1) begin
             led[0] = 1'b1;
             led[1] = 1'b0;
@@ -345,14 +341,14 @@ module top (
             led[2] = 1'b0;
         end
 
-    always @(posedge clk_24m or posedge rst)
-        if (rst) begin
-            led[3] = 1'b0;
-        end else if (btn_2) begin
-            led[3] = 1'b1;
-        end else begin
-            led[3] = 1'b0;
-        end
+    //always @(posedge clk_24m or posedge rst)
+    //    if (rst) begin
+    //        led[3] = 1'b0;
+    //    end else if (btn_2) begin
+    //        led[3] = 1'b1;
+    //    end else begin
+    //        led[3] = 1'b0;
+    //    end
 
     //// TODO: dummy driving from delay1
     always @(posedge clk_24m or posedge rst)