projects/memtest: Add support for boards using softcore USB

Theses will use no2muacm to provide the connectivity to the host
to run the memory test

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

projects/memtest/Makefile

@@ -1,7 +1,7 @@
 # Project config
 PROJ = memtest
 
-PROJ_DEPS := no2misc no2ice40
+PROJ_DEPS := no2misc no2ice40 no2muacm
 PROJ_RTL_SRCS := $(addprefix rtl/, \
 	memtest.v \
 	sysmgr.v \

projects/memtest/data/top-bitsy-v0-spi.pcf

@@ -0,0 +1,8 @@
+# SPI
+set_io --warn-no-port             spi_sck   15
+set_io --warn-no-port -pullup no  spi_io[0] 14
+set_io --warn-no-port -pullup no  spi_io[1] 17
+set_io --warn-no-port -pullup no  spi_io[2] 12
+set_io --warn-no-port -pullup no  spi_io[3] 13
+set_io --warn-no-port -pullup yes spi_cs_n[0] 16
+set_io --warn-no-port -pullup yes spi_cs_n[1] 37

projects/memtest/data/top-bitsy-v0.pcf

@@ -0,0 +1,10 @@
+# Clock
+set_io --warn-no-port clk_in 35
+
+# USB
+set_io -nowarn usb_dp 43
+set_io -nowarn usb_dn 42
+set_io -nowarn usb_pu 38
+
+# Button
+set_io -nowarn btn 2

projects/memtest/data/top-bitsy-v1-spi.pcf

@@ -0,0 +1,8 @@
+# SPI
+set_io --warn-no-port             spi_sck   15
+set_io --warn-no-port -pullup no  spi_io[0] 14
+set_io --warn-no-port -pullup no  spi_io[1] 17
+set_io --warn-no-port -pullup no  spi_io[2] 18
+set_io --warn-no-port -pullup no  spi_io[3] 19
+set_io --warn-no-port -pullup yes spi_cs_n[0] 16
+set_io --warn-no-port -pullup yes spi_cs_n[1] 6

projects/memtest/data/top-bitsy-v1.pcf

@@ -0,0 +1,10 @@
+# Clock
+set_io --warn-no-port clk_in 35
+
+# USB
+set_io -nowarn usb_dp 42
+set_io -nowarn usb_dn 38
+set_io -nowarn usb_pu 37
+
+# Button
+set_io -nowarn btn 2

projects/memtest/data/top-redip-sid-spi.pcf

@@ -0,0 +1,8 @@
+# SPI
+set_io --warn-no-port             spi_sck   15
+set_io --warn-no-port -pullup no  spi_io[0] 14
+set_io --warn-no-port -pullup no  spi_io[1] 17
+set_io --warn-no-port -pullup no  spi_io[2] 18
+set_io --warn-no-port -pullup no  spi_io[3] 19
+set_io --warn-no-port -pullup yes spi_cs_n[0] 16
+set_io --warn-no-port -pullup yes spi_cs_n[1] 37

projects/memtest/data/top-redip-sid.pcf

@@ -0,0 +1,10 @@
+# Clock
+set_io --warn-no-port clk_in 20
+
+# USB
+set_io -nowarn usb_dp 25
+set_io -nowarn usb_dn 23
+set_io -nowarn usb_pu 35
+
+# Button
+set_io -nowarn btn 9

projects/memtest/rtl/boards.vh

@@ -0,0 +1,57 @@
+/*
+ * boards.vh
+ *
+ * vim: ts=4 sw=4 syntax=verilog
+ *
+ * Copyright (C) 2021  Sylvain Munaut <tnt@246tNt.com>
+ * SPDX-License-Identifier: CERN-OHL-P-2.0
+ */
+
+`ifdef BOARD_BITSY_V0
+	// 1bitsquared iCEbreaker bitsy prototypes (v0.x)
+	`define HAS_USB
+`elsif BOARD_BITSY_V1
+	// 1bitsquared iCEbreaker bitsy prod (v1.x)
+	`define HAS_USB
+`elsif BOARD_REDIP_SID
+	// reDIP-SID
+	`define HAS_USB
+	`define PLL_CORE
+	`define PLL_CUSTOM
+	`define PLL_FILTER_RANGE 3'b010
+	`define PLL_DIVR 4'b0000
+	`define PLL_DIVF 7'b0010111
+	`define PLL_DIVQ 3'b010
+`endif
+
+// Defaults
+	// If no USB, use UART
+`ifndef HAS_USB
+	`define HAS_UART
+`endif
+
+	// PLL params
+`ifndef PLL_CUSTOM
+	`define PLL_FILTER_RANGE 3'b001
+	`define PLL_DIVR 4'b0000
+
+		// 48
+//	`define PLL_DIVF 7'b0111111
+//	`define PLL_DIVQ 3'b100
+
+		// 96
+//	`define PLL_DIVF 7'b0111111
+//	`define PLL_DIVQ 3'b011
+
+		// 144
+//	`define PLL_DIVF 7'b0101111
+//	`define PLL_DIVQ 3'b010
+
+		// 147
+	`define PLL_DIVF 7'b0110000
+	`define PLL_DIVQ 3'b010
+
+		// 200
+//	`define PLL_DIVF 7'b1000010
+//	`define PLL_DIVQ 3'b010
+`endif

projects/memtest/rtl/sysmgr.v

@@ -8,53 +8,53 @@
  */
 
 `default_nettype none
+`include "boards.vh"
 
 module sysmgr (
+	// Memory clocks
 	input  wire [3:0] delay,
-	input  wire clk_in,
-	output wire clk_1x,
-	output wire clk_2x,
-	output wire clk_4x,
-	output wire clk_rd,
-	output wire sync_4x,
-	output wire sync_rd,
-	output wire rst
+	input  wire       clk_in,
+	output wire       clk_1x,
+	output wire       clk_2x,
+	output wire       clk_4x,
+	output wire       clk_rd,
+	output wire       sync_4x,
+	output wire       sync_rd,
+	output wire       rst,
+
+	// USB
+	output wire       clk_usb,
+	output wire       rst_usb
 );
 
+	// Memory clocks / reset
+	// ---------------------
+
+	// Signals
 	wire       pll_lock;
 
+	// PLL
+`ifdef PLL_CORE
+	SB_PLL40_2F_CORE #(
+`else
 	SB_PLL40_2F_PAD #(
+`endif
 		.FEEDBACK_PATH                  ("SIMPLE"),
-		.DIVR                           (4'b0000),
-
-	// 48
-//		.DIVF                           (7'b0111111),
-//		.DIVQ                           (3'b100),
-
-	// 96
-//		.DIVF                           (7'b0111111),
-//		.DIVQ                           (3'b011),
-
-	// 144
-//		.DIVF                           (7'b0101111),
-//		.DIVQ                           (3'b010),
-
-	// 147
-		.DIVF                           (7'b0110000),
-		.DIVQ                           (3'b010),
-
-	// 200
-//		.DIVF                           (7'b1000010),
-//		.DIVQ                           (3'b010),
-
-		.FILTER_RANGE                   (3'b001),
+		.FILTER_RANGE                   (`PLL_FILTER_RANGE),
+		.DIVR                           (`PLL_DIVR),
+		.DIVF                           (`PLL_DIVF),
+		.DIVQ                           (`PLL_DIVQ),
 		.DELAY_ADJUSTMENT_MODE_RELATIVE ("DYNAMIC"),
 		.FDA_RELATIVE                   (15),
 		.SHIFTREG_DIV_MODE              (0),
 		.PLLOUT_SELECT_PORTA            ("GENCLK"),
 		.PLLOUT_SELECT_PORTB            ("GENCLK")
 	) pll_I (
+`ifdef PLL_CORE
+		.REFERENCECLK  (clk_in),
+`else
 		.PACKAGEPIN    (clk_in),
+`endif
 		.DYNAMICDELAY  ({delay, 4'h0}),
 		.PLLOUTGLOBALA (clk_rd),
 		.PLLOUTGLOBALB (clk_4x),
@@ -62,6 +62,7 @@ module sysmgr (
 		.LOCK          (pll_lock)
 	);
 
+	// Fabric derived clocks
 	ice40_serdes_crg #(
 		.NO_CLOCK_2X(0)
 	) crg_I (
@@ -72,6 +73,7 @@ module sysmgr (
 		.rst      (rst)
 	);
 
+	// SPI - Sync signals
 `ifdef MEM_spi
 	ice40_serdes_sync #(
 		.PHASE      (2),
@@ -79,7 +81,7 @@ module sysmgr (
 `ifdef VIDEO_none
 		.GLOBAL_BUF (0),
 		.LOCAL_BUF  (0),
-		.BEL_COL    ("X22"),
+		.BEL_COL    ("X21"),
 		.BEL_ROW    ("Y4"),
 `else
 		.GLOBAL_BUF (0),
@@ -96,6 +98,7 @@ module sysmgr (
 	assign sync_rd = 1'b0;
 `endif
 
+	// HyperRAM - Sync signals
 `ifdef MEM_hyperram
 	ice40_serdes_sync #(
 		.PHASE      (2),
@@ -126,4 +129,36 @@ module sysmgr (
 	);
 `endif
 
+
+	// USB clock / reset
+	// -----------------
+
+	// Signals
+	reg       rst_usb_i;
+	reg [3:0] rst_usb_cnt;
+
+	// 48 MHz source
+	SB_HFOSC #(
+		.TRIM_EN   ("0b0"),
+		.CLKHF_DIV ("0b00")	// 48 MHz
+	) osc_I (
+		.CLKHFPU (1'b1),
+		.CLKHFEN (1'b1),
+		.CLKHF   (clk_usb)
+	);
+
+	// Logic reset generation
+	always @(posedge clk_usb or negedge pll_lock)
+		if (~pll_lock)
+			rst_usb_cnt <= 4'h8;
+		else if (rst_usb_i)
+			rst_usb_cnt <= rst_usb_cnt + 1;
+
+	assign rst_usb_i = rst_usb_cnt[3];
+
+	SB_GB rst_gbuf_I (
+		.USER_SIGNAL_TO_GLOBAL_BUFFER (rst_usb_i),
+		.GLOBAL_BUFFER_OUTPUT         (rst_usb)
+	);
+
 endmodule // sysmgr

projects/memtest/rtl/top.v

@@ -8,6 +8,7 @@
  */
 
 `default_nettype none
+`include "boards.vh"
 
 module top (
 	// SPI
@@ -42,9 +43,18 @@ module top (
 	output wire hdmi_clk,
 `endif
 
+`ifdef HAS_UART
 	// UART
 	input  wire uart_rx,
 	output wire uart_tx,
+`endif
+
+`ifdef HAS_USB
+	// USB
+	inout  wire usb_dp,
+	inout  wire usb_dn,
+	output wire usb_pu,
+`endif
 
 	// Clock (12M)
 	input  wire clk_in
@@ -120,16 +130,33 @@ module top (
 	wire sync_rd;
 	wire rst;
 
+	wire clk_usb;
+	wire rst_usb;
+	wire bootloader;
+
 
 	// Host interface
 	// --------------
 
+`ifdef HAS_UART
 	uart2wb #(
+`elsif HAS_USB
+	muacm2wb #(
+`endif
 		.WB_N(3)
 	) if_I (
+`ifdef HAS_UART
 		.uart_rx  (uart_rx),
 		.uart_tx  (uart_tx),
 		.uart_div (8'd16),
+`elsif HAS_USB
+		.usb_dp   (usb_dp),
+		.usb_dn   (usb_dn),
+		.usb_pu   (usb_pu),
+		.usb_clk  (clk_usb),
+		.usb_rst  (rst_usb),
+		.bootloader (bootloader),
+`endif
 		.wb_wdata (wb_wdata),
 		.wb_rdata (wb_rdata),
 		.wb_addr  (wb_addr),
@@ -143,6 +170,14 @@ module top (
 
 	assign dma_run = aux_csr[0];
 
+`ifdef HAS_USB
+	SB_WARMBOOT warmboot (
+		.BOOT (bootloader),
+		.S0   (1'b1),
+		.S1   (1'b0)
+	);
+`endif
+
 
 	// QSPI Controller
 	// ---------------
@@ -458,7 +493,9 @@ module top (
 		.clk_rd  (clk_rd),
 		.sync_4x (sync_4x),
 		.sync_rd (sync_rd),
-		.rst     (rst)
+		.rst     (rst),
+		.clk_usb (clk_usb),
+		.rst_usb (rst_usb)
 	);
 
 endmodule