Bladeren bron

projects/hdmi_text: Import demo code for the HDMI text on the iCEBreaker

Using the 4bits (or 3 bit) HDMI PMOD in slot 1A.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Sylvain Munaut 6 jaren geleden
bovenliggende
commit
8d856f4493

+ 27 - 0
projects/hdmi_text/Makefile

@@ -0,0 +1,27 @@
+# Project config
+PROJ = hdmi_text
+
+PROJ_DEPS := video spi_slave
+PROJ_RTL_SRCS := $(addprefix rtl/, \
+	sysmgr.v \
+)
+PROJ_TOP_SRC := rtl/top.v
+PROJ_TOP_MOD := top
+
+# Target config
+BOARD ?= icebreaker
+DEVICE = up5k
+PACKAGE = sg48
+
+NEXTPNR_ARGS = --freq 75
+
+# Include default rules
+include ../../build/project-rules.mk
+
+# Custom rules
+
+	# SPI core selection
+SPI ?= fast
+ifeq ($(SPI),fast)
+YOSYS_READ_ARGS += -DSPI_FAST=1
+endif

BIN
projects/hdmi_text/data/VGA-8x16.png


+ 344 - 0
projects/hdmi_text/data/VGA-8x16.png.txt

@@ -0,0 +1,344 @@
+from https://github.com/epto/epto-fonts/blob/master/font-images/img/VGA-8x16.png
+
+and under this license:
+
+
+                  GNU GENERAL PUBLIC LICENSE
+                       Version 2, June 1991
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+ 18 - 0
projects/hdmi_text/data/top-icebreaker.pcf

@@ -0,0 +1,18 @@
+# Clock
+set_io clk12m_in 35
+
+# HDMI pmod on 1A
+set_io -nowarn hdmi_clk 2
+set_io -nowarn hdmi_hsync 47
+set_io -nowarn hdmi_vsync 44
+set_io -nowarn hdmi_de 46
+set_io -nowarn hdmi_r 3
+set_io -nowarn hdmi_g 4
+set_io -nowarn hdmi_b 48
+set_io -nowarn hdmi_i 45
+
+# SPI Slave
+set_io -nowarn slave_mosi 14
+set_io -nowarn slave_miso 17
+set_io -nowarn slave_cs_n 11
+set_io -nowarn slave_clk 15

+ 115 - 0
projects/hdmi_text/rtl/sysmgr.v

@@ -0,0 +1,115 @@
+/*
+ * sysmgr.v
+ *
+ * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
+ * All rights reserved.
+ *
+ * BSD 3-clause, see LICENSE.bsd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of the <organization> nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * vim: ts=4 sw=4
+ */
+
+`default_nettype none
+
+module sysmgr (
+	input  wire clk_in,
+	input  wire rst_in,
+	output wire clk_2x_out,
+	output wire clk_1x_out,
+	output wire rst_out
+);
+
+	// Signals
+	wire pll_lock;
+	wire pll_reset_n;
+
+	wire clk_2x_i;
+	wire clk_1x_i;
+	wire rst_i;
+	reg [7:0] rst_cnt;
+
+	// PLL instance
+`ifdef SIM
+	reg toggle = 1'b0;
+
+	initial
+		rst_cnt <= 8'h80;
+
+	always @(posedge clk_in)
+		toggle <= ~toggle;
+
+	assign clk_1x_i = toggle;
+	assign clk_2x_i = clk_in;
+	assign pll_lock = pll_reset_n;
+`else
+	SB_PLL40_2F_PAD #(
+		// 147 M
+		.DIVR(4'b0000),
+		.DIVF(7'b0110000),
+		.DIVQ(3'b010),
+		.FILTER_RANGE(3'b001),
+		.FEEDBACK_PATH("SIMPLE"),
+		.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
+		.FDA_FEEDBACK(4'b0000),
+		.SHIFTREG_DIV_MODE(2'b00),
+		.PLLOUT_SELECT_PORTA("GENCLK"),
+		.PLLOUT_SELECT_PORTB("GENCLK_HALF"),
+	) pll_I (
+		.PACKAGEPIN(clk_in),
+		.PLLOUTGLOBALA(clk_2x_i),
+		.PLLOUTGLOBALB(clk_1x_i),
+		.EXTFEEDBACK(1'b0),
+		.DYNAMICDELAY(8'h00),
+		.RESETB(pll_reset_n),
+		.BYPASS(1'b0),
+		.LATCHINPUTVALUE(1'b0),
+		.LOCK(pll_lock),
+		.SDI(1'b0),
+		.SDO(),
+		.SCLK(1'b0)
+	);
+`endif
+
+	assign clk_2x_out = clk_2x_i;
+	assign clk_1x_out = clk_1x_i;
+
+	// PLL reset generation
+	assign pll_reset_n = ~rst_in;
+
+	// Logic reset generation
+	always @(posedge clk_1x_i or negedge pll_lock)
+		if (!pll_lock)
+			rst_cnt <= 8'h80;
+		else if (rst_cnt[7])
+			rst_cnt <= rst_cnt + 1;
+
+	assign rst_i = rst_cnt[7];
+
+	SB_GB rst_gbuf_I (
+		.USER_SIGNAL_TO_GLOBAL_BUFFER(rst_i),
+		.GLOBAL_BUFFER_OUTPUT(rst_out)
+	);
+
+endmodule // sysmgr

+ 158 - 0
projects/hdmi_text/rtl/top.v

@@ -0,0 +1,158 @@
+/*
+ * top.v
+ *
+ * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
+ * All rights reserved.
+ *
+ * BSD 3-clause, see LICENSE.bsd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of the <organization> nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * vim: ts=4 sw=4
+ */
+
+`default_nettype none
+
+module top (
+	// HDMI PMOD
+	output wire hdmi_clk,
+	output wire hdmi_hsync,
+	output wire hdmi_vsync,
+	output wire hdmi_de,
+	output wire hdmi_r,
+	output wire hdmi_g,
+	output wire hdmi_b,
+	output wire hdmi_i,
+
+	// Slave SPI interface
+	input  wire slave_mosi,
+	output wire slave_miso,
+	input  wire slave_cs_n,
+	input  wire slave_clk,
+
+	// Clock
+	input  wire clk12m_in
+);
+
+	// Signals
+	// -------
+
+	// Fast Bus
+	wire [15:0] fbus_addr;
+	wire [15:0] fbus_din;
+	wire [15:0] fbus_dout;
+	wire fbus_cyc;
+	wire fbus_we;
+	wire fbus_ack;
+
+	// Slow Bus
+	wire [7:0] sb_addr;
+	wire [7:0] sb_data;
+	wire sb_first;
+	wire sb_last;
+	wire sb_stb;
+	wire [7:0] sb_out;
+
+	// Bridge
+	reg [31:0] data;
+	reg pending;
+
+	// Clocks / Reset
+	wire clk_2x;
+	wire clk_1x;
+	wire rst;
+
+
+	// SPI interface
+	// -------------
+
+	spi_fast spi_I (
+		.spi_mosi(slave_mosi),
+		.spi_miso(slave_miso),
+		.spi_cs_n(slave_cs_n),
+		.spi_clk(slave_clk),
+		.addr(sb_addr),
+		.data(sb_data),
+		.first(sb_first),
+		.last(sb_last),
+		.strobe(sb_stb),
+		.out(sb_out),
+		.clk(clk_1x),
+		.rst(rst)
+	);
+
+
+	// Slow -> Fast bus bridge
+	// -----------------------
+
+	assign fbus_din  = data[15:0];
+	assign fbus_addr = data[31:16];
+	assign fbus_cyc  = pending;
+	assign fbus_we   = 1'b1;
+
+	always @(posedge clk_1x)
+		if (rst)
+			pending <= 1'b0;
+		else
+			pending <= (pending & ~fbus_ack) | (sb_last & sb_stb & |(data[24:22]));
+
+	always @(posedge clk_1x)
+		if (sb_stb & ~pending)
+			data <= { data[24:0], sb_data };
+
+
+	// HDMI text mode core
+	// -------------------
+
+	hdmi_text_2x #(
+		.DW(4)
+	) text_I (
+		.hdmi_data({hdmi_i, hdmi_b, hdmi_g, hdmi_r}),
+		.hdmi_hsync(hdmi_hsync),
+		.hdmi_vsync(hdmi_vsync),
+		.hdmi_de(hdmi_de),
+		.hdmi_clk(hdmi_clk),
+		.bus_addr(fbus_addr),
+		.bus_din(fbus_din),
+		.bus_dout(fbus_dout),
+		.bus_cyc(fbus_cyc),
+		.bus_we(fbus_we),
+		.bus_ack(fbus_ack),
+		.clk_1x(clk_1x),
+		.clk_2x(clk_2x),
+		.rst(rst)
+	);
+
+
+	// Clock / Reset generation
+	// ------------------------
+
+	sysmgr sysmgr_I (
+		.clk_in(clk12m_in),
+		.rst_in(1'b0),
+		.clk_2x_out(clk_2x),
+		.clk_1x_out(clk_1x),
+		.rst_out(rst)
+	);
+
+endmodule // top

+ 1 - 0
projects/hdmi_text/sw/control.py

@@ -0,0 +1 @@
+../../_common/control.py

+ 121 - 0
projects/hdmi_text/sw/text.py

@@ -0,0 +1,121 @@
+#!/usr/bin/env python3
+
+import argparse
+import struct
+from PIL import Image
+
+import control
+
+
+class TextControl(control.BoardControlBase):
+
+	COLOR_BASE  = 0x6000
+	SCREEN_BASE = 0x8000
+	GLYPH_BASE  = 0xc000
+
+	def __init__(self, **kwargs):
+		# Super call
+		super().__init__(**kwargs)
+
+	def bus_write(self, addr, data):
+		self.slave.exchange(struct.pack('>BHH', 0, addr, data))
+
+	def upload_font(self, fn, s=0):
+		img = Image.open(fn)
+
+		for i in range(0x0000, 0x2000):
+			c = (i >> 5)
+			fx = (c & 0xf) * 9
+			fy = ((c >> 4) & 0xf) * 17
+			cx = (i & 0x01) * 4
+			cy = (i & 0x1e) >> 1
+
+			data = (
+				((img.getpixel( (fx+cx+0, fy+cy) )[0] >> 7) << 12) |
+				((img.getpixel( (fx+cx+1, fy+cy) )[0] >> 7) <<  8) |
+				((img.getpixel( (fx+cx+2, fy+cy) )[0] >> 7) <<  4) |
+				((img.getpixel( (fx+cx+3, fy+cy) )[0] >> 7) <<  0)
+			)
+
+			self.bus_write(self.GLYPH_BASE + s*0x2000 + i, data)
+
+
+def default_config(text):
+	# Colors
+		# FG
+	for i in range(0x6000, 0x6008):
+		text.bus_write(i, (i & 0x7) | ((i & 0x7) << 4))
+
+		# BG
+	for i in range(0x6008, 0x6010):
+		text.bus_write(i, (i & 0x7) | ((i & 0x7) << 4) | 0x88)
+
+		# Custom RGBI
+	for i in range(0x6020, 0x6030):
+		text.bus_write(i, (i & 0xf) | ((i & 0xf) << 4))
+
+	# Font
+	text.upload_font('../data/VGA-8x16.png')
+
+
+def show_font(text):
+	# Char matrix
+	for i in range(0x0000, 0x4000):
+		text.bus_write(text.SCREEN_BASE + i,
+			(i & 0xff) |
+			(((i >> 8) & 0x3f) << 10) |
+			(1 << 9)
+		)
+
+
+def show_bars(text):
+	# Create a font
+	for i in range(16):
+		d = (i << 0) | (i << 4) | (i << 8) | (i << 12)
+		for w in range(32):
+			text.bus_write(text.GLYPH_BASE + 0x2000 + i*32 + w, d)
+
+	# Bands on the screen
+	for y in range(64):
+		for x in range(256):
+			addr = text.SCREEN_BASE | (y << 8) | x
+
+			text.bus_write(addr,
+				((x >> 3) & 0xf) |
+				(1 <<  8) |
+				(2 << 12)
+			)
+
+
+def main():
+	# Parse options
+	parser = argparse.ArgumentParser(
+		formatter_class=argparse.ArgumentDefaultsHelpFormatter
+	)
+	g_text  = parser.add_argument_group('test',  'Text core options')
+	g_brd   = parser.add_argument_group('board', 'Board configuration options')
+
+	g_text.add_argument('--show-font', help='Show font over FG/BG palette', action='store_true', default=False)
+	g_text.add_argument('--show-bars', help='Show color bars', action='store_true', default=False)
+
+	control.arg_group_setup(g_brd)
+
+	args = parser.parse_args()
+
+	# Build control object with those params
+	kwargs = control.arg_to_kwargs(args)
+
+	text = TextControl(**kwargs)
+
+	# Commands
+	default_config(text)
+
+	if args.show_font:
+		show_font(text)
+
+	if args.show_bars:
+		show_bars(text)
+
+
+if __name__ == '__main__':
+	main()