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+/*
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+ * spi.c
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+ *
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+ * Copyright (C) 2019 Sylvain Munaut
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+ * All rights reserved.
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+ *
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+ * LGPL v3+, see LICENSE.lgpl3
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU Lesser General Public
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+ * License as published by the Free Software Foundation; either
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+ * version 3 of the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ * Lesser General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU Lesser General Public License
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+ * along with this program; if not, write to the Free Software Foundation,
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+ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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+ */
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+
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+#include <stdbool.h>
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+#include <stdint.h>
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+
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+#include "config.h"
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+#include "spi.h"
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+
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+
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+struct spi {
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+ uint32_t _rsvd0[6];
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+ uint32_t irq; /* 0110 - SPIIRQ - Interrupt Status Register */
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+ uint32_t irqen; /* 0111 - SPIIRQEN - Interrupt Control Register */
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+ uint32_t cr0; /* 1000 - CR0 - Control Register 0 */
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+ uint32_t cr1; /* 1001 - CR1 - Control Register 1 */
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+ uint32_t cr2; /* 1010 - CR2 - Control Register 2 */
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+ uint32_t br; /* 1011 - BR - Baud Rate Register */
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+ uint32_t sr; /* 1100 - SR - Status Register */
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+ uint32_t txdr; /* 1101 - TXDR - Transmit Data Register */
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+ uint32_t rxdr; /* 1110 - RXDR - Receive Data Register */
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+ uint32_t csr; /* 1111 - CSR - Chip Select Register */
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+} __attribute__((packed,aligned(4)));
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+
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+#define SPI_CR0_TIDLE(xcnt) (((xcnt) & 3) << 6)
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+#define SPI_CR0_TTRAIL(xcnt) (((xcnt) & 7) << 3)
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+#define SPI_CR0_TLEAD(xcnt) (((xcnt) & 7) << 0)
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+
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+#define SPI_CR1_ENABLE (1 << 7)
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+#define SPI_CR1_WKUPEN_USER (1 << 6)
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+#define SPI_CR1_TXEDGE (1 << 4)
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+
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+#define SPI_CR2_MASTER (1 << 7)
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+#define SPI_CR2_MCSH (1 << 6)
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+#define SPI_CR2_SDBRE (1 << 5)
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+#define SPI_CR2_CPOL (1 << 2)
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+#define SPI_CR2_CPHA (1 << 1)
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+#define SPI_CR2_LSBF (1 << 0)
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+
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+#define SPI_SR_TIP (1 << 7)
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+#define SPI_SR_BUSY (1 << 6)
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+#define SPI_SR_TRDY (1 << 4)
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+#define SPI_SR_RRDY (1 << 3)
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+#define SPI_SR_TOE (1 << 2)
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+#define SPI_SR_ROE (1 << 1)
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+#define SPI_SR_MDF (1 << 0)
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+
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+
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+static volatile struct spi * const spi_regs = (void*)(SPI_BASE);
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+
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+
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+void
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+spi_init(void)
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+{
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+ spi_regs->cr0 = SPI_CR0_TIDLE(3) |
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+ SPI_CR0_TTRAIL(7) |
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+ SPI_CR0_TLEAD(7);
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+ spi_regs->cr1 = SPI_CR1_ENABLE;
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+ spi_regs->cr2 = SPI_CR2_MASTER | SPI_CR2_MCSH;
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+ spi_regs->br = 3;
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+ spi_regs->csr = 0xf;
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+}
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+
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+void
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+spi_xfer(unsigned cs, struct spi_xfer_chunk *xfer, unsigned n)
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+{
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+ /* Setup CS */
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+ spi_regs->csr = 0xf ^ (1 << cs);
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+
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+ /* Run the chunks */
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+ while (n--) {
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+ for (int i=0; i<xfer->len; i++)
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+ {
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+ spi_regs->txdr = xfer->write ? xfer->data[i] : 0x00;
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+ while (!(spi_regs->sr & SPI_SR_RRDY));
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+ if (xfer->read)
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+ xfer->data[i] = spi_regs->rxdr;
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+ }
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+ xfer++;
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+ }
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+
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+ /* Clear CS */
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+ spi_regs->csr = 0xf ^ (1 << cs);
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+}
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+
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+
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+void flash_cmd(uint8_t cmd)
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+{
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+ struct spi_xfer_chunk xfer[1] = {
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+ { .data = (void*)&cmd, .len = 1, .read = false, .write = true, },
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+ };
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+ spi_xfer(SPI_CS_FLASH, xfer, 1);
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+}
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+
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+uint32_t flash_id(void)
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+{
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+ uint32_t buf = 0x9f;
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+ struct spi_xfer_chunk xfer[2] = {
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+ { .data = (void*)&buf, .len = 1, .read = false, .write = true, },
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+ { .data = (void*)&buf, .len = 3, .read = true, .write = false, },
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+ };
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+ spi_xfer(SPI_CS_FLASH, xfer, 2);
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+ return buf;
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+}
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+
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+void flash_read(void *dst, uint32_t addr, unsigned len)
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+{
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+ uint8_t cmd[4] = { 0x03, ((addr >> 16) & 0xff), ((addr >> 8) & 0xff), (addr & 0xff) };
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+ struct spi_xfer_chunk xfer[2] = {
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+ { .data = (void*)cmd, .len = 4, .read = false, .write = true, },
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+ { .data = (void*)dst, .len = len, .read = true, .write = false, },
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+ };
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+ spi_xfer(SPI_CS_FLASH, xfer, 2);
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+}
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