projects/riscv_usb: Set clock to their real frequency

There is really no point in adding any margin ... there is already
plenty of margin in the nextpnr timing database

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

projects/riscv_usb/data/clocks.py

@@ -1,2 +1,2 @@
-ctx.addClock("clk_24m", 25)
-ctx.addClock("clk_48m", 49)
+ctx.addClock("clk_24m", 24)
+ctx.addClock("clk_48m", 48)