cores/hub75: Use a 'SDW' localparam shortcut for the # of parallel data

SDW = Shifted Data Width = The number of bits shifted out at the same
time

At the same time we cleanup the PHY to use array instances.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

cores/hub75/rtl/hub75_phy.v

@@ -33,13 +33,14 @@ module hub75_phy #(
 	parameter integer PHY_AIR  = 0,		// PHY Address Inc/Reset
 
 	// Auto-set
+	parameter integer SDW         = N_BANKS * N_CHANS,
 	parameter integer LOG_N_ROWS  = $clog2(N_ROWS)
 )(
 	// Hub75 interface pads
 	output wire hub75_addr_inc,
 	output wire hub75_addr_rst,
 	output wire [LOG_N_ROWS-1:0] hub75_addr,
-	output wire [(N_BANKS*N_CHANS)-1:0] hub75_data,
+	output wire [SDW-1:0] hub75_data,
 	output wire hub75_clk,
 	output wire hub75_le,
 	output wire hub75_blank,
@@ -48,7 +49,7 @@ module hub75_phy #(
 	input wire phy_addr_inc,
 	input wire phy_addr_rst,
 	input wire [LOG_N_ROWS-1:0] phy_addr,
-	input wire [(N_BANKS*N_CHANS)-1:0] phy_data,
+	input wire [SDW-1:0] phy_data,
 	input wire phy_clk,
 	input wire phy_le,
 	input wire phy_blank,
@@ -57,8 +58,6 @@ module hub75_phy #(
 	input  wire clk,
 	input  wire rst
 );
-	genvar i;
-
 	// Signals
 	reg phy_clk_f;
 
@@ -104,20 +103,17 @@ module hub75_phy #(
 	endgenerate
 
 	// Data lines
-	generate
-		for (i=0; i<(N_BANKS*N_CHANS); i=i+1)
-			SB_IO #(
-				.PIN_TYPE(6'b010100),
-				.PULLUP(1'b0),
-				.NEG_TRIGGER(1'b0),
-				.IO_STANDARD("SB_LVCMOS")
-			) iob_data_I (
-				.PACKAGE_PIN(hub75_data[i]),
-				.CLOCK_ENABLE(1'b1),
-				.OUTPUT_CLK(clk),
-				.D_OUT_0(phy_data[i])
-			);
-	endgenerate
+	SB_IO #(
+		.PIN_TYPE(6'b010100),
+		.PULLUP(1'b0),
+		.NEG_TRIGGER(1'b0),
+		.IO_STANDARD("SB_LVCMOS")
+	) iob_data_I[SDW-1:0] (
+		.PACKAGE_PIN(hub75_data),
+		.CLOCK_ENABLE(1'b1),
+		.OUTPUT_CLK(clk),
+		.D_OUT_0(phy_data)
+	);
 
 	// Falling edge clock, so we need one more delay so it's not too early !
 	always @(posedge clk or posedge rst)

cores/hub75/rtl/hub75_shift.v

@@ -32,10 +32,11 @@ module hub75_shift #(
 	parameter integer N_PLANES = 8,
 
 	// Auto-set
+	parameter integer SDW         = N_BANKS * N_CHANS,
 	parameter integer LOG_N_COLS  = $clog2(N_COLS)
 )(
 	// PHY
-	output wire [(N_BANKS*N_CHANS)-1:0] phy_data,
+	output wire [SDW-1:0] phy_data,
 	output wire phy_clk,
 
 	// RAM interface
@@ -64,8 +65,8 @@ module hub75_shift #(
 	reg [LOG_N_COLS:0] cnt_0;
 	reg cnt_last_0;
 
-	wire [(N_BANKS*N_CHANS)-1:0] ram_data_bit;
-	reg  [(N_BANKS*N_CHANS)-1:0] data_2;
+	wire [SDW-1:0] ram_data_bit;
+	reg  [SDW-1:0] data_2;
 
 
 	// Control logic
@@ -106,7 +107,7 @@ module hub75_shift #(
 
 	// Data plane mux
 	generate
-		for (i=0; i<(N_BANKS*N_CHANS); i=i+1)
+		for (i=0; i<SDW; i=i+1)
 			assign ram_data_bit[i] = |(ram_data[((i+1)*N_PLANES)-1:i*N_PLANES] & ctrl_plane);
 	endgenerate
 

cores/hub75/rtl/hub75_top.v

@@ -37,6 +37,7 @@ module hub75_top #(
 	parameter SCAN_MODE = "ZIGZAG",		// 'LINEAR' or 'ZIGZAG'
 
 	// Auto-set
+	parameter integer SDW         = N_BANKS * N_CHANS,
 	parameter integer LOG_N_BANKS = $clog2(N_BANKS),
 	parameter integer LOG_N_ROWS  = $clog2(N_ROWS),
 	parameter integer LOG_N_COLS  = $clog2(N_COLS)
@@ -45,7 +46,7 @@ module hub75_top #(
 	output wire hub75_addr_inc,
 	output wire hub75_addr_rst,
 	output wire [LOG_N_ROWS-1:0] hub75_addr,
-	output wire [(N_BANKS*N_CHANS)-1:0] hub75_data,
+	output wire [SDW-1:0] hub75_data,
 	output wire hub75_clk,
 	output wire hub75_le,
 	output wire hub75_blank,
@@ -91,7 +92,7 @@ module hub75_top #(
 	wire phy_addr_inc;
 	wire phy_addr_rst;
 	wire [LOG_N_ROWS-1:0] phy_addr;
-	wire [(N_BANKS*N_CHANS)-1:0] phy_data;
+	wire [SDW-1:0] phy_data;
 	wire phy_clk;
 	wire phy_le;
 	wire phy_blank;