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@@ -64,6 +64,7 @@ module usb_tx_ll (
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// Output
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reg out_active;
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+ wire [1:0] out_sym_nxt;
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reg [1:0] out_sym;
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@@ -76,7 +77,7 @@ module usb_tx_ll (
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else begin
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if (ll_start)
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state <= 3'b100;
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- else if (br_now) begin
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+ else if (br_now & ~bs_now) begin
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if (ll_last)
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state <= 3'b101;
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else
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@@ -127,14 +128,16 @@ module usb_tx_ll (
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// Output symbol. Must be forced to 'J' outside of active area to
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// be ready for the next packet start
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+ assign out_sym_nxt = (bs_bit ^ lvl_prev) ? SYM_K : SYM_J;
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+
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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out_sym <= SYM_J;
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else if (br_now) begin
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case (state[1:0])
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- 2'b00: out_sym <= (bs_bit ^ lvl_prev) ? SYM_K : SYM_J;
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- 2'b01: out_sym <= SYM_SE0;
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+ 2'b00: out_sym <= out_sym_nxt;
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+ 2'b01: out_sym <= bs_now ? out_sym_nxt : SYM_SE0;
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2'b10: out_sym <= SYM_SE0;
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2'b11: out_sym <= SYM_J;
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default: out_sym <= 2'bxx;
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