build: Use IVERILOG variable when building simulation

build/project-rules.mk

@@ -89,7 +89,7 @@ $(BUILD_TMP)/$(PROJ).pnr.rpt $(BUILD_TMP)/$(PROJ).asc: $(BUILD_TMP)/$(PROJ).json
 
 # Simulation
 $(BUILD_TMP)/%_tb: sim/%_tb.v $(ICE40_LIBS) $(PROJ_ALL_PREREQ) $(PROJ_ALL_RTL_SRCS) $(PROJ_ALL_SIM_SRCS)
-	iverilog -Wall -DSIM=1 -D$(BOARD_DEFINE)=1 -o $@ \
+	$(IVERILOG) -Wall -DSIM=1 -D$(BOARD_DEFINE)=1 -o $@ \
 		$(PROJ_SYNTH_INCLUDES) $(PROJ_SIM_INCLUDES) \
 		$(addprefix -l, $(ICE40_LIBS) $(PROJ_ALL_RTL_SRCS) $(PROJ_ALL_SIM_SRCS)) \
 		$<