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cores/mem_cache: Rename wmask to wmsk

I used wmsk everywhere else in the context of wishbone / memory bus,
so might as well use it here too.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Sylvain Munaut 4 years ago
parent
71cf37bb2f
commit
ad398c9bfb
4 changed files with 30 additions and 30 deletions
Split View Show Diff Stats
  1. 3 3
      cores/mem_cache/rtl/mc_bus_wb.v
  2. 11 11
      cores/mem_cache/rtl/mc_core.v
  3. 8 8
      cores/mem_cache/sim/mc_core_tb.v
  4. 8 8
      cores/mem_cache/sim/mc_wb_tb.v

+ 3 - 3
cores/mem_cache/rtl/mc_bus_wb.v
View File 

@@ -42,7 +42,7 @@ module mc_bus_wb #(
 
 	// Wishbone bus
 
 	input  wire [BL:0] wb_addr,
 
 	input  wire [31:0] wb_wdata,
 
-	input  wire [ 3:0] wb_wmask,
 
+	input  wire [ 3:0] wb_wmsk,
 
 	output wire [31:0] wb_rdata,
 
 	input  wire        wb_cyc,
 
 	input  wire        wb_we,
 
@@ -55,7 +55,7 @@ module mc_bus_wb #(
 
 
 	output wire        req_write,
 
 	output wire [31:0] req_wdata,
 
-	output wire [ 3:0] req_wmask,
 
+	output wire [ 3:0] req_wmsk,
 
 
 	// Response input
 
 	input  wire        resp_ack,
 
@@ -87,7 +87,7 @@ module mc_bus_wb #(
 
 	// Write path
 
 	assign req_write = wb_we;
 
 	assign req_wdata = wb_wdata;
 
-	assign req_wmask = wb_wmask;
 
+	assign req_wmsk  = wb_wmsk;
 
 
 	// Read path
 
 	assign wb_rdata  = resp_rdata;

+ 11 - 11
cores/mem_cache/rtl/mc_core.v
View File 

@@ -49,7 +49,7 @@ module mc_core #(
 
 
 	input  wire        req_write,
 
 	input  wire [31:0] req_wdata,
 
-	input  wire [ 3:0] req_wmask,
 
+	input  wire [ 3:0] req_wmsk,
 
 
 	// Response output (1 cycle later)
 
 	output reg         resp_ack,
 
@@ -179,8 +179,8 @@ module mc_core #(
 
 	wire [31:0] dm_rdata;
 
 	reg         dm_re;
 
 	reg  [31:0] dm_wdata;
 
-	wire [ 7:0] dm_wmask_nibble;
 
-	reg  [ 3:0] dm_wmask;
 
+	wire [ 7:0] dm_wmsk_nibble;
 
+	reg  [ 3:0] dm_wmsk;
 
 	reg         dm_we;
 
 
 
@@ -483,17 +483,17 @@ module mc_core #(
 
 		.rd_data(dm_rdata),
 
 		.rd_ena(dm_re),
 
 		.wr_data(dm_wdata),
 
-		.wr_mask(dm_wmask_nibble),
 
+		.wr_mask(dm_wmsk_nibble),
 
 		.wr_ena(dm_we),
 
 		.clk(clk)
 
 	);
 
 
 	// Extend mask to nibbles
 
-	assign dm_wmask_nibble = {
 
-		dm_wmask[3], dm_wmask[3],
 
-		dm_wmask[2], dm_wmask[2],
 
-		dm_wmask[1], dm_wmask[1],
 
-		dm_wmask[0], dm_wmask[0]
 
+	assign dm_wmsk_nibble = {
 
+		dm_wmsk[3], dm_wmsk[3],
 
+		dm_wmsk[2], dm_wmsk[2],
 
+		dm_wmsk[1], dm_wmsk[1],
 
+		dm_wmsk[0], dm_wmsk[0]
 
 	};
 
 
 	// Muxing
 
@@ -504,14 +504,14 @@ module mc_core #(
 
 			dm_addr  = { lu_hit_way, req_addr_idx, req_addr_ofs };
 
 			dm_re    = 1'b1;
 
 			dm_wdata = req_wdata;
 
-			dm_wmask = req_wmask;
 
+			dm_wmsk  = req_wmsk;
 
 			dm_we    = req_write & lu_hit;
 
 		end else begin
 
 			// Read or Write access to/from memory interface
 
 			dm_addr  = { ev_way_r, req_addr_idx, cnt_ofs };
 
 			dm_re    = cnt_ofs_inc;
 
 			dm_wdata = mi_rdata;
 
-			dm_wmask = 4'h0;
 
+			dm_wmsk  = 4'h0;
 
 			dm_we    = mi_rstb;
 
 		end
 
 	end

+ 8 - 8
cores/mem_cache/sim/mc_core_tb.v
View File 

@@ -44,12 +44,12 @@ module mc_core_tb;
 
 	reg         req_valid_pre;
 
 	reg         req_write_pre;
 
 	reg  [31:0] req_wdata_pre;
 
-	reg  [ 3:0] req_wmask_pre;
 
+	reg  [ 3:0] req_wmsk_pre;
 
 
 	reg         req_valid;
 
 	reg         req_write;
 
 	reg  [31:0] req_wdata;
 
-	reg  [ 3:0] req_wmask;
 
+	reg  [ 3:0] req_wmsk;
 
 
 	wire        resp_ack;
 
 	wire        resp_nak;
 
@@ -112,7 +112,7 @@ module mc_core_tb;
 
 		.req_valid(req_valid),
 
 		.req_write(req_write),
 
 		.req_wdata(req_wdata),
 
-		.req_wmask(req_wmask),
 
+		.req_wmsk(req_wmsk),
 
 		.resp_ack(resp_ack),
 
 		.resp_nak(resp_nak),
 
 		.resp_rdata(resp_rdata),
 
@@ -159,20 +159,20 @@ module mc_core_tb;
 
 	task mc_req_write;
 
 		input [20:0] addr;
 
 		input [31:0] data;
 
-		input [ 3:0] mask;
 
+		input [ 3:0] msk;
 
 		begin
 
 			req_addr_pre <= addr;
 
 			req_valid_pre <= 1'b1;
 
 			req_write_pre <= 1'b1;
 
 			req_wdata_pre <= data;
 
-			req_wmask_pre <= mask;
 
+			req_wmsk_pre  <= msk;
 
 			@(posedge clk);
 
 
 			req_addr_pre  <= 20'hxxxxx;
 
 			req_valid_pre <= 1'b0;
 
 			req_write_pre <= 1'bx;
 
 			req_wdata_pre <= 32'hxxxxxxxx;
 
-			req_wmask_pre <=  4'hx;
 
+			req_wmsk_pre  <=  4'hx;
 
 		end
 
 	endtask
 
 
@@ -196,7 +196,7 @@ module mc_core_tb;
 
 		req_valid_pre <= 1'b0;
 
 		req_write_pre <= 1'bx;
 
 		req_wdata_pre <= 32'hxxxxxxxx;
 
-		req_wmask_pre <=  4'hx;
 
+		req_wmsk_pre  <=  4'hx;
 
 
 		@(negedge rst);
 
 		@(posedge clk);
 
@@ -242,7 +242,7 @@ module mc_core_tb;
 
 		req_valid <= req_valid_pre;
 
 		req_write <= req_write_pre;
 
 		req_wdata <= req_wdata_pre;
 
-		req_wmask <= req_wmask_pre;
 
+		req_wmsk  <= req_wmsk_pre;
 
 	end

+ 8 - 8
cores/mem_cache/sim/mc_wb_tb.v
View File 

@@ -42,7 +42,7 @@ module mc_wb_tb;
 
 	// Wishbone bus
 
 	reg  [19:0] wb_addr;
 
 	reg  [31:0] wb_wdata;
 
-	reg  [ 3:0] wb_wmask;
 
+	reg  [ 3:0] wb_wmsk;
 
 	wire [31:0] wb_rdata;
 
 	reg         wb_cyc;
 
 	reg         wb_we;
 
@@ -54,7 +54,7 @@ module mc_wb_tb;
 
 	wire        req_valid;
 
 	wire        req_write;
 
 	wire [31:0] req_wdata;
 
-	wire [ 3:0] req_wmask;
 
+	wire [ 3:0] req_wmsk;
 
 
 	wire        resp_ack;
 
 	wire        resp_nak;
 
@@ -117,7 +117,7 @@ module mc_wb_tb;
 
 		.req_valid(req_valid),
 
 		.req_write(req_write),
 
 		.req_wdata(req_wdata),
 
-		.req_wmask(req_wmask),
 
+		.req_wmsk(req_wmsk),
 
 		.resp_ack(resp_ack),
 
 		.resp_nak(resp_nak),
 
 		.resp_rdata(resp_rdata),
 
@@ -141,7 +141,7 @@ module mc_wb_tb;
 
 	) bus_adapt_I (
 
 		.wb_addr(wb_addr),
 
 		.wb_wdata(wb_wdata),
 
-		.wb_wmask(wb_wmask),
 
+		.wb_wmsk(wb_wmsk),
 
 		.wb_rdata(wb_rdata),
 
 		.wb_cyc(wb_cyc),
 
 		.wb_we(wb_we),
 
@@ -150,7 +150,7 @@ module mc_wb_tb;
 
 		.req_valid(req_valid),
 
 		.req_write(req_write),
 
 		.req_wdata(req_wdata),
 
-		.req_wmask(req_wmask),
 
+		.req_wmsk(req_wmsk),
 
 		.resp_ack(resp_ack),
 
 		.resp_nak(resp_nak),
 
 		.resp_rdata(resp_rdata),
 
@@ -188,7 +188,7 @@ module mc_wb_tb;
 
 		begin
 
 			wb_addr  <= addr;
 
 			wb_wdata <= data;
 
-			wb_wmask <= 4'h0;
 
+			wb_wmsk  <= 4'h0;
 
 			wb_we    <= 1'b1;
 
 			wb_cyc   <= 1'b1;
 
 
@@ -198,7 +198,7 @@ module mc_wb_tb;
 
 
 			wb_addr  <= 4'hx;
 
 			wb_wdata <= 32'hxxxxxxxx;
 
-			wb_wmask <= 4'hx;
 
+			wb_wmsk  <= 4'hx;
 
 			wb_we    <= 1'bx;
 
 			wb_cyc   <= 1'b0;
 
 		end
 
@@ -225,7 +225,7 @@ module mc_wb_tb;
 
 		// Defaults
 
 		wb_addr  <= 4'hx;
 
 		wb_wdata <= 32'hxxxxxxxx;
 
-		wb_wmask <= 4'hx;
 
+		wb_wmsk  <= 4'hx;
 
 		wb_we    <= 1'bx;
 
 		wb_cyc   <= 1'b0;