Fix bridging logic. Hangups are gone. Wrong offset in register map still persits.

Signed-off-by: Jakub Duchniewicz <j.duchniewicz@gmail.com>

projects/riscv_usb/fw/fw_app.c

@@ -55,9 +55,27 @@ serial_no_init()
 	flash_unique_id(buf);
 	printf("Flash Unique ID    : %s\n", hexstr(buf, 8, true));
 
+    //uint32_t old = *(volatile uint32_t *)(MAILBOX_BASE + 0x00);
+    //printf("Old=0x%x\n", old);
+    //*(volatile uint32_t *)(MAILBOX_BASE + 0x00) = 0x00000004;
+    //uint32_t new = *(volatile uint32_t *)(MAILBOX_BASE + 0x00);
+    //printf("New=0x%x\n", new);
+    //printf("Old=0x%x, New=0x%x\n", old, new);
+
     // Print Mailbox contents just to be sure */
-    printf("Mailbox period1: %d\n", mailbox_regs->regs.period1);
-    printf("Mailbox delay1: %d\n", mailbox_regs->regs.delay1);
+    //printf("Mailbox period1: %d\n", mailbox_regs->regs.period1);
+    //printf("Mailbox delay1: %d\n", mailbox_regs->regs.delay1);
+
+    //// Debug print all mailbox memory
+    //for (i = 0; i < 64; ++i) {
+    //    //printf("%x ", *((int*)MAILBOX_BASE+i));
+    //    printf("%x ", *((int*)MAILBOX_BASE+i));
+    //    if (i != 0 && i % 16)
+    //        printf("\n");
+    //}
+
+    //mailbox_regs->regs.delay3= 0x1;
+    //printf("Mailbox delay1: %d\n", mailbox_regs->regs.delay3);
 
     /* Testing floats TODO: test if calculation is correct
     dupa = 3.1415;
@@ -69,31 +87,50 @@ serial_no_init()
     */
 
 	/* Overwrite descriptor string */
-		/* In theory in rodata ... but nothing is ro here */
+	/* In theory in rodata ... but nothing is ro here */
 	id = hexstr(buf, 8, false);
 	desc = (char*)app_stack_desc.str[1];
 	for (i=0; i<16; i++)
 		desc[2 + (i << 1)] = id[i];
 }
 
+static char _printf_buf[128];
+
 static void write_period1()
 {
     printf("Writing period1 0x1\n");
+    //uint8_t *strMem = (uint8_t *)&_printf_buf;
+	//for (int i=0; i<32; i++) {
+	//   printf("%x ", strMem[i]);
+	//}
     mailbox_regs->regs.period1 = 0x1;
     printf("Done writing\n");
+    //uint8_t * strMem = (uint8_t *)&_printf_buf;
+	//for (int i=0; i<32; i++) {
+	//   printf("%x ", strMem[i]);
+	//}
+	printf("\n");
 }
 
 static void write_period1_2()
 {
     printf("Writing period1 0x2\n");
+    //uint8_t *strMem = (uint8_t *)&_printf_buf;
+	//for (int i=0; i<32; i++) {
+	//   printf("%x ", strMem[i]);
+	//}
     mailbox_regs->regs.period1 = 0x2;
     printf("Done writing\n");
+    //uint8_t * strMem = (uint8_t *)&_printf_buf;
+	//for (int i=0; i<32; i++) {
+	//   printf("%x ", strMem[i]);
+	//}
 }
 
 static void write_period1_4()
 {
     printf("Writing period1 0x4\n");
-    mailbox_regs->regs.period1 = 0x3;
+    mailbox_regs->regs.period1 = 0x4;
     printf("Done writing\n");
     printf("Reading now \n");
     printf("value: %d\n", mailbox_regs->regs.period1);
@@ -108,8 +145,8 @@ static void clear_period1()
 
 static void write_delay1()
 {
-    printf("Writing delay1 0x1\n");
-    mailbox_regs->regs.delay1 = 0x1;
+    printf("Writing delay1 0x1234\n");
+    mailbox_regs->regs.delay1 = 0x1234;
     printf("Done writing\n");
 }
 
@@ -203,12 +240,12 @@ void main()
             case 's':
                 write_period1_4();
                 break;
-            //case 'o':
-            //    write_delay1();
-            //    break;
-            //case 'm':
-            //    clear_delay1();
-            //    break;
+            case 'o':
+                write_delay1();
+                break;
+            case 'm':
+                clear_delay1();
+                break;
 			default:
 				break;
 			}

projects/riscv_usb/rtl/soc_picorv32_bridge.v

@@ -144,12 +144,30 @@ module soc_picorv32_bridge #(
 	end
 
 	// Ack / Read-Data
-	always @(*)
-	begin : wb_or
-		integer i;
-		wb_rdata_or = 0;
-		for (i=0; i<WB_N; i=i+1)
-			wb_rdata_or[WB_DW-1:0] = wb_rdata_or[WB_DW-1:0] | wb_rdata[WB_DW*i+:WB_DW];
+	//always @(*)
+	//begin : wb_or
+	//	integer i;
+	//	wb_rdata_or = 0;
+	//	for (i=0; i<WB_N; i=i+1)
+	//		wb_rdata_or[WB_DW-1:0] = wb_rdata_or[WB_DW-1:0] | wb_rdata[WB_DW*i+:WB_DW];
+	//end
+
+	reg [31:0] wb_rdata_sel;
+
+	always @(*) begin : wb_mux
+		// Default to zero
+		wb_rdata_sel = 32'h00000000;
+
+		// If exactly one ack is active, select that slave's read data
+		// If more than one ack is active, we pick the highest or lowest
+		// in this loop. You could also detect an error if needed.
+		integer j;
+		for (j = 0; j < WB_N; j = j + 1) begin
+			if (wb_ack[j]) begin
+				wb_rdata_sel = wb_rdata[j*32 +: 32];
+				// If you want highest-priority or lowest-priority, you could break
+			end
+		end
 	end
 
 	if (WB_REG & 4) begin
@@ -164,7 +182,8 @@ module soc_picorv32_bridge #(
 			if (wb_cyc_rst)
 				wb_rdata_reg <= 32'h00000000;
 			else
-				wb_rdata_reg <= wb_rdata_or;
+				wb_rdata_reg <= wb_rdata_sel;
+				//wb_rdata_reg <= wb_rdata_or;
 
 		assign wb_cyc_rst = ~pb_valid | ~pb_addr[31] | wb_rdy_reg;
 		assign wb_rdy = wb_rdy_reg;
@@ -173,7 +192,8 @@ module soc_picorv32_bridge #(
 		// Direct connection
 		assign wb_cyc_rst = ~pb_valid | ~pb_addr[31];
 		assign wb_rdy = |wb_ack;
-		assign wb_rdata_out = wb_rdata_or;
+		//assign wb_rdata_out = wb_rdata_or;
+		assign wb_rdata_out = wb_rdata_sel;
 	end
 
 

projects/riscv_usb/rtl/top.v

@@ -285,10 +285,10 @@ module top (
             led[0] = 1'b0;
             led[1] = 1'b1;
             led[2] = 1'b0;
-        //end else if (period1 == 3) begin
-        //    led[0] = 1'b0;
-        //    led[1] = 1'b0;
-        //    led[2] = 1'b1;
+        end else if (period1 == 4) begin
+            led[0] = 1'b0;
+            led[1] = 1'b0;
+            led[2] = 1'b1;
         //end else if (period1 != 0) begin
         //    led[0] = 1'b1;
         //    led[1] = 1'b1;
@@ -299,15 +299,24 @@ module top (
             led[2] = 1'b0;
         end
 
+    always @(posedge clk_24m or posedge rst)
+        if (rst) begin
+            led[3] = 1'b0;
+        end else if (btn_2) begin
+            led[3] = 1'b1;
+        end else begin
+            led[3] = 1'b0;
+        end
+
     //// TODO: dummy driving from delay1
-    //always @(posedge clk_48m or posedge rst)
-    //    if (rst) begin
-    //        led[2] = 1'b0;
-    //    end else if (delay1 != 0) begin
-    //        led[2] = 1'b1;
-    //    end else begin
-    //        led[2] = 1'b0;
-    //    end
+    always @(posedge clk_24m or posedge rst)
+        if (rst) begin
+            led[4] = 1'b0;
+        end else if (delay1 !=0 ) begin
+            led[4] = 1'b1;
+        end else begin
+            led[4] = 1'b0;
+        end
 
     //always @(posedge clk_48m or posedge rst)
     //    if (rst) begin