Add patches to submodules.

Signed-off-by: Jakub Duchniewicz <j.duchniewicz@gmail.com>

patches/buildpatch.patch

@@ -0,0 +1,21 @@
+commit e98ef3e8a325418d4c5ab9e07d14faa960b87adb
+Author: Jakub Duchniewicz <j.duchniewicz@gmail.com>
+Date:   Wed Jan 8 13:49:49 2025 +0100
+
+    Port 3signal code and integrate to the top module.
+    
+    Signed-off-by: Jakub Duchniewicz <j.duchniewicz@gmail.com>
+
+diff --git a/project-rules.mk b/project-rules.mk
+index 3ddbaa7..b430486 100644
+--- a/project-rules.mk
++++ b/project-rules.mk
+@@ -79,7 +79,7 @@ PROJ_SIM_INCLUDES   := -I$(abspath sim/) $(addsuffix /sim/, $(addprefix -I$(NO2C
+ # Synthesis & Place-n-route rules
+ 
+ $(BUILD_TMP)/$(PROJ).ys: $(PROJ_TOP_SRC) $(PROJ_ALL_RTL_SRCS)
+-	@echo "read_verilog $(YOSYS_READ_ARGS) $(PROJ_SYNTH_INCLUDES) $(PROJ_TOP_SRC) $(PROJ_ALL_RTL_SRCS)" > $@
++	@echo "read_verilog -sv $(YOSYS_READ_ARGS) $(PROJ_SYNTH_INCLUDES) $(PROJ_TOP_SRC) $(PROJ_ALL_RTL_SRCS)" > $@
+ 	@echo "synth_ice40 $(YOSYS_SYNTH_ARGS) -top $(PROJ_TOP_MOD) -json $(PROJ).json" >> $@
+ 
+ $(BUILD_TMP)/$(PROJ).synth.rpt $(BUILD_TMP)/$(PROJ).json: $(PROJ_ALL_PREREQ) $(BUILD_TMP)/$(PROJ).ys $(PROJ_ALL_RTL_SRCS)

patches/no2miscpatch.patch

@@ -0,0 +1,66 @@
+commit 01b6ac0c7af5b54cbb565fd20eca5777be02c7ef
+Author: Jakub Duchniewicz <j.duchniewicz@gmail.com>
+Date:   Wed Jan 8 13:52:29 2025 +0100
+
+    Update to build with Systemverilog.
+    
+    Signed-off-by: Jakub Duchniewicz <j.duchniewicz@gmail.com>
+
+diff --git a/rtl/prims.v b/rtl/prims.v
+index 9bc5fbc..df03506 100644
+--- a/rtl/prims.v
++++ b/rtl/prims.v
+@@ -28,7 +28,7 @@ module lut4_n #(
+ 	genvar i;
+ 	generate
+ 		for (i=0; i<WIDTH; i=i+1)
+-		begin : bit
++		begin : gen_bit
+ 			(* RBEL_X=RBEL_X *)
+ 			(* RBEL_Y=RBEL_Y+(RBEL_Z+i)>>3 *)
+ 			(* RBEL_Z=(RBEL_Z+i)&7 *)
+@@ -72,7 +72,7 @@ module lut4_carry_n #(
+ 	genvar i;
+ 	generate
+ 		for (i=0; i<WIDTH; i=i+1)
+-		begin : bit
++		begin : gen_bit
+ 			(* RBEL_X=RBEL_X *)
+ 			(* RBEL_Y=RBEL_Y+(RBEL_Z+i)>>3 *)
+ 			(* RBEL_Z=(RBEL_Z+i)&7 *)
+@@ -114,7 +114,7 @@ module dff_n #(
+ 	genvar i;
+ 	generate
+ 		for (i=0; i<WIDTH; i=i+1)
+-		begin : bit
++		begin : gen_bit
+ 			(* RBEL_X=RBEL_X *)
+ 			(* RBEL_Y=RBEL_Y+(RBEL_Z+i)>>3 *)
+ 			(* RBEL_Z=(RBEL_Z+i)&7 *)
+@@ -147,7 +147,7 @@ module dffe_n #(
+ 	genvar i;
+ 	generate
+ 		for (i=0; i<WIDTH; i=i+1)
+-		begin : bit
++		begin : gen_bit
+ 			(* RBEL_X=RBEL_X *)
+ 			(* RBEL_Y=RBEL_Y+((RBEL_Z+i)>>3) *)
+ 			(* RBEL_Z=(RBEL_Z+i)&7 *)
+@@ -183,7 +183,7 @@ module dffer_n #(
+ 	genvar i;
+ 	generate
+ 		for (i=0; i<WIDTH; i=i+1)
+-		begin : bit
++		begin : gen_bit
+ 			if (RSTVAL[i] == 1'b1)
+ 				(* RBEL_X=RBEL_X *)
+ 				(* RBEL_Y=RBEL_Y+((RBEL_Z+i)>>3) *)
+@@ -234,7 +234,7 @@ module dffesr_n #(
+ 	genvar i;
+ 	generate
+ 		for (i=0; i<WIDTH; i=i+1)
+-		begin : bit
++		begin : gen_bit
+ 			if (RSTVAL[i] == 1'b1)
+ 				(* RBEL_X=RBEL_X *)
+ 				(* RBEL_Y=RBEL_Y+((RBEL_Z+i)>>3) *)