projects/riscv_usb: Adapt to allow 64k/128k of SPRAM

 - Switch to using the ice40_spram_gen helper core
 - Modify address space to use 0x20000 -> 0x3ffff for SPRAM
 - Adapt linker and boot/start code

Also standardize on having the "mask" signal be 0=write, 1=masked/no-write

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

projects/riscv_usb/Makefile

@@ -1,7 +1,7 @@
 # Project config
 PROJ = riscv_usb
 
-PROJ_DEPS := usb misc
+PROJ_DEPS := usb misc ice40
 PROJ_RTL_SRCS := $(addprefix rtl/, \
 	bridge.v \
 	dfu_helper.v \

projects/riscv_usb/fw/boot.S

@@ -48,8 +48,12 @@ _start:
 	sw	a1, 0(a0)
 #endif
 
-	li	a0, 0x00010000
+	li	a0, 0x00020000
+#ifdef SPRAM128K
+	li	a1, 0x00020000
+#else
 	li	a1, 0x00010000
+#endif
 	li	a2, FLASH_APP_ADDR
 	jal	spi_flash_read
 
@@ -61,11 +65,11 @@ _start:
 #endif
 
 	// Setup reboot code
-	li	t0, 0x0001006f
+	li	t0, 0x0002006f
 	sw	t0, 0(zero)
 
 	// Jump to main code
-	j	0x00010000
+	j	0x00020000
 
 
 	.equ    SPI_BASE, 0x82000000

projects/riscv_usb/fw/lnk-app.lds

@@ -1,7 +1,6 @@
 MEMORY
 {
-    ROM (rx)    : ORIGIN = 0x00010000, LENGTH = 0xc000
-    SPRAM (xrw) : ORIGIN = 0x0001c000, LENGTH = 0x4000
+    SPRAM (xrw) : ORIGIN = 0x00020000, LENGTH = DEFINED(SPRAM128K) ? 0x20000 : 0x10000
     BRAM  (xrw) : ORIGIN = 0x00000010, LENGTH = 0x03f0
 }
 ENTRY(_start)
@@ -19,7 +18,7 @@ SECTIONS {
         . = ALIGN(4);
         _etext = .;
         _sidata = _etext;
-    } >ROM
+    } >SPRAM
     .data : AT ( _sidata )
     {
         . = ALIGN(4);

projects/riscv_usb/fw/start.S

@@ -67,21 +67,6 @@ _start:
 	sw a1, 0(a0)
 #endif
 
-	// zero initialize entire scratchpad memory
-	li a0, 0x0001c000
-	li a1, 0
-setmemloop:
-	sw a1, 0(a0)
-	addi a0, a0, 4
-	blt a0, sp, setmemloop
-
-#ifdef BOOT_DEBUG
-	// Output '2'
-	li a0, 0x81000000
-	li a1, 50
-	sw a1, 0(a0)
-#endif
-
 	// copy data section
 	la a0, _sidata
 	la a1, _sdata
@@ -96,9 +81,9 @@ loop_init_data:
 end_init_data:
 
 #ifdef BOOT_DEBUG
-	// Output '3'
+	// Output '2'
 	li a0, 0x81000000
-	li a1, 51
+	li a1, 50
 	sw a1, 0(a0)
 #endif
 
@@ -113,9 +98,9 @@ loop_init_bss:
 end_init_bss:
 
 #ifdef BOOT_DEBUG
-	// Output '4'
+	// Output '3'
 	li a0, 0x81000000
-	li a1, 52
+	li a1, 51
 	sw a1, 0(a0)
 #endif
 

projects/riscv_usb/rtl/bridge.v

@@ -56,7 +56,7 @@ module bridge #(
 	output wire        bram_we,
 
 	/* SPRAM */
-	output wire [13:0] spram_addr,
+	output wire [14:0] spram_addr,
 	input  wire [31:0] spram_rdata,
 	output wire [31:0] spram_wdata,
 	output wire [ 3:0] spram_wmsk,
@@ -83,8 +83,8 @@ module bridge #(
 	reg  ram_rdy;
 	wire [31:0] ram_rdata;
 
-	(* keep="true" *) wire [WB_N-1:0] wb_match;
-	(* keep="true" *) wire wb_cyc_rst;
+	(* keep *) wire [WB_N-1:0] wb_match;
+	(* keep *) wire wb_cyc_rst;
 
 	reg  [31:0] wb_rdata_or;
 	wire [31:0] wb_rdata_out;
@@ -94,21 +94,21 @@ module bridge #(
 	// RAM access
 	// ----------
 	// BRAM  : 0x00000000 -> 0x000003ff
-	// SPRAM : 0x00010000 -> 0x0001ffff
+	// SPRAM : 0x00020000 -> 0x0003ffff
 
 	assign bram_addr  = pb_addr[ 9:2];
-	assign spram_addr = pb_addr[15:2];
+	assign spram_addr = pb_addr[16:2];
 
 	assign bram_wdata  = pb_wdata;
 	assign spram_wdata = pb_wdata;
 
-	assign bram_wmsk  = pb_wstrb;
-	assign spram_wmsk = pb_wstrb;
+	assign bram_wmsk  = ~pb_wstrb;
+	assign spram_wmsk = ~pb_wstrb;
 
-	assign bram_we  = pb_valid & ~pb_addr[31] & |pb_wstrb & ~pb_addr[16];
-	assign spram_we = pb_valid & ~pb_addr[31] & |pb_wstrb &  pb_addr[16];
+	assign bram_we  = pb_valid & ~pb_addr[31] & |pb_wstrb & ~pb_addr[17];
+	assign spram_we = pb_valid & ~pb_addr[31] & |pb_wstrb &  pb_addr[17];
 
-	assign ram_rdata = ~pb_addr[31] ? (pb_addr[16] ? spram_rdata : bram_rdata) : 32'h00000000;
+	assign ram_rdata = ~pb_addr[31] ? (pb_addr[17] ? spram_rdata : bram_rdata) : 32'h00000000;
 
 	assign ram_sel = pb_valid & ~pb_addr[31];
 
@@ -151,7 +151,7 @@ module bridge #(
 		begin
 			wb_addr_reg  <= pb_addr[WB_AW+WB_AI-1:WB_AI];
 			wb_wdata_reg <= pb_wdata[WB_DW-1:0];
-			wb_wmsk_reg  <= pb_wstrb[(WB_DW/8)-1:0];
+			wb_wmsk_reg  <= ~pb_wstrb[(WB_DW/8)-1:0];
 			wb_we_reg    <= |pb_wstrb;
 		end
 

projects/riscv_usb/rtl/soc_bram.v

@@ -53,10 +53,10 @@ module soc_bram #(
 
 	always @(posedge clk) begin
 		rdata <= mem[addr];
-		if (we & wmsk[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
-		if (we & wmsk[1]) mem[addr][15: 8] <= wdata[15: 8];
-		if (we & wmsk[2]) mem[addr][23:16] <= wdata[23:16];
-		if (we & wmsk[3]) mem[addr][31:24] <= wdata[31:24];
+		if (we & ~wmsk[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
+		if (we & ~wmsk[1]) mem[addr][15: 8] <= wdata[15: 8];
+		if (we & ~wmsk[2]) mem[addr][23:16] <= wdata[23:16];
+		if (we & ~wmsk[3]) mem[addr][31:24] <= wdata[31:24];
 	end
 
 endmodule // soc_bram

projects/riscv_usb/rtl/soc_spram.v

@@ -33,8 +33,10 @@
 
 `default_nettype none
 
-module soc_spram (
-	input  wire [13:0] addr,
+module soc_spram #(
+	parameter integer AW = 14
+)(
+	input  wire [AW-1:0] addr,
 	output wire [31:0] rdata,
 	input  wire [31:0] wdata,
 	input  wire [ 3:0] wmsk,
@@ -42,33 +44,24 @@ module soc_spram (
 	input  wire clk
 );
 
-	wire [3:0] msk_msb = { wmsk[3], wmsk[3], wmsk[2], wmsk[2] };
-	wire [3:0] msk_lsb = { wmsk[1], wmsk[1], wmsk[0], wmsk[0] };
+	wire [7:0] msk_nibble = {
+		wmsk[3], wmsk[3],
+		wmsk[2], wmsk[2],
+		wmsk[1], wmsk[1],
+		wmsk[0], wmsk[0]
+	};
 
-	SB_SPRAM256KA spram_msb_I (
-		.DATAIN(wdata[31:16]),
-		.ADDRESS(addr[13:0]),
-		.MASKWREN(msk_msb),
-		.WREN(we),
-		.CHIPSELECT(1'b1),
-		.CLOCK(clk),
-		.STANDBY(1'b0),
-		.SLEEP(1'b0),
-		.POWEROFF(1'b1),
-		.DATAOUT(rdata[31:16])
-	);
-
-	SB_SPRAM256KA spram_lsb_I (
-		.DATAIN(wdata[15:0]),
-		.ADDRESS(addr[13:0]),
-		.MASKWREN(msk_lsb),
-		.WREN(we),
-		.CHIPSELECT(1'b1),
-		.CLOCK(clk),
-		.STANDBY(1'b0),
-		.SLEEP(1'b0),
-		.POWEROFF(1'b1),
-		.DATAOUT(rdata[15:0])
+	ice40_spram_gen #(
+		.ADDR_WIDTH(AW),
+		.DATA_WIDTH(32)
+	) spram_I (
+		.addr(addr),
+		.rd_data(rdata),
+		.rd_ena(1'b1),
+		.wr_data(wdata),
+		.wr_mask(msk_nibble),
+		.wr_ena(we),
+		.clk(clk)
 	);
 
 endmodule // soc_spram

projects/riscv_usb/rtl/top.v

@@ -65,6 +65,8 @@ module top (
 	localparam WB_AW = 16;
 	localparam WB_AI =  2;
 
+	localparam SPRAM_AW = 14; /* 14 => 64k, 15 => 128k */
+
 	genvar i;
 
 
@@ -89,7 +91,7 @@ module top (
 	wire        bram_we;
 
 		// SPRAM
-	wire [13:0] spram_addr;
+	wire [14:0] spram_addr;
 	wire [31:0] spram_rdata;
 	wire [31:0] spram_wdata;
 	wire [ 3:0] spram_wmsk;
@@ -235,8 +237,10 @@ module top (
 	);
 
 	// Main memory
-	soc_spram spram_I (
-		.addr(spram_addr),
+	soc_spram #(
+		.AW(SPRAM_AW)
+	) spram_I (
+		.addr(spram_addr[SPRAM_AW-1:0]),
 		.rdata(spram_rdata),
 		.wdata(spram_wdata),
 		.wmsk(spram_wmsk),