cores/usb: Wait for TX complete before BD writeback in Isochronous IN

without this we would write back the buffer descriptor before it's
really done:
 - The write back process might update the internal FSM state and
   invalidate the address counter
 - The CPU would think the BD is done and could start filling it with
   new data

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

cores/usb/utils/microcode.py

@@ -225,6 +225,12 @@ mc = [
 		# Transmit packet (with DATA0, always)
 		TX(PID_DATA0),
 
+		# Wait for TX to complete
+	L('_DO_IN_ISOC_WAIT_TX'),
+		LD('evt'),
+		JEQ('_DO_IN_ISOC_WAIT_TX', 0, EVT_TX_DONE),
+		EVT_CLR(EVT_TX_DONE),
+
 		# "Assume" success
 		EP(bd_state=BD_DONE_OK, bdi_flip=True, dt_flip=False, wb=True),
 		NOTIFY(NOTIFY_SUCCESS),