replace 3 signal with temporary and incomplete (but fast) version

projects/riscv_usb/rtl/3signal.v

@@ -9,46 +9,269 @@
 
 `default_nettype none
 
-module continous_pwm_gen#(
+module compare_eq#(
+    parameter WIDTH = 16
+)(
+    input wire clk,
+
+    input wire [WIDTH-1:0] A,
+    input wire [WIDTH-1:0] B,
+
+    output reg [0:0] was_eq //1 if A and B were equal 2 ticks ago
+);
+    parameter WIDTH_DIV4 = (WIDTH+3)/4;
+    parameter WIDTH_REM  = WIDTH - WIDTH_DIV4*3;
+
+    wire [WIDTH_DIV4-1:0] A0_pt0, A0_pt1, A0_pt2;
+    wire [WIDTH_REM-1:0] A0_pt3;
+
+    wire [WIDTH_DIV4-1:0] B0_pt0, B0_pt1, B0_pt2;
+    wire [WIDTH_REM-1:0] B0_pt3;
+
+    assign {A0_pt3, A0_pt2, A0_pt1, A0_pt0} = A;
+    assign {B0_pt3, B0_pt2, B0_pt1, B0_pt0} = B;
+
+    reg pt0_eq, pt1_eq, pt2_eq, pt3_eq;
+
+    always @(posedge clk) begin
+        pt0_eq <= A0_pt0==B0_pt0;
+        pt1_eq <= A0_pt1==B0_pt1;
+        pt2_eq <= A0_pt2==B0_pt2;
+        pt3_eq <= A0_pt3==B0_pt3;
+
+        was_eq <= pt0_eq & pt1_eq & pt2_eq & pt3_eq;
+    end
+endmodule
+
+module add#(
+    parameter WIDTH = 16
+)(
+    input wire clk,
+
+    input wire [WIDTH-1:0] A,
+    input wire [WIDTH-1:0] B,
+
+    output reg [WIDTH-1:0] sum
+);
+    parameter WIDTH_DIV2 = (WIDTH+1)/2;
+    parameter WIDTH_REM  = WIDTH - WIDTH_DIV2;
+
+    wire [WIDTH_DIV2-1:0] A0_pt0;
+    wire [WIDTH_REM-1:0] A0_pt1;
+
+    wire [WIDTH_DIV2-1:0] B0_pt0;
+    wire [WIDTH_REM-1:0] B0_pt1;
+
+    assign {A0_pt1, A0_pt0} = A;
+    assign {B0_pt1, B0_pt0} = B;
+
+    reg [WIDTH_DIV2:0] C0_pt0;
+    reg [WIDTH_REM-1:0] C0_pt1;
+
+    always @(posedge clk) begin
+        C0_pt0 <= {1'b0, A0_pt0} + {1'b0, B0_pt0};
+        C0_pt1 <= A0_pt1 + B0_pt1;
+
+        sum <= {C0_pt1+{6'b0, C0_pt0[WIDTH_DIV2]}, C0_pt0[WIDTH_DIV2-1:0]};
+    end
+endmodule
+
+
+module compare_gt#(
+    parameter WIDTH = 16
+)(
+    input wire clk,
+
+    input wire [WIDTH-1:0] A,
+    input wire [WIDTH-1:0] B,
+
+    output reg [0:0] was_gt //1 if A was greater than B 3 ticks ago
+);
+    parameter WIDTH_DIV4 = (WIDTH+3)/4;
+    parameter WIDTH_REM  = WIDTH - WIDTH_DIV4*3;
+
+    wire [WIDTH_DIV4-1:0] A0_pt0, A0_pt1, A0_pt2;
+    wire [WIDTH_REM-1:0] A0_pt3;
+
+    wire [WIDTH_DIV4-1:0] B0_pt0, B0_pt1, B0_pt2;
+    wire [WIDTH_REM-1:0] B0_pt3;
+
+    assign {A0_pt3, A0_pt2, A0_pt1, A0_pt0} = A;
+    assign {B0_pt3, B0_pt2, B0_pt1, B0_pt0} = B;
+
+    reg pt0_gt, pt1_gt, pt2_gt, pt3_gt;
+    reg pt0_eq, pt1_eq, pt2_eq, pt3_eq;
+
+    reg pt01_eq, pt23_eq;
+    reg pt01_gt, pt23_gt;
+
+
+    always @(posedge clk) begin
+        pt0_gt <= A0_pt0>B0_pt0;
+        pt1_gt <= A0_pt1>B0_pt1;
+        pt2_gt <= A0_pt2>B0_pt2;
+        pt3_gt <= A0_pt3>B0_pt3;
+
+        pt0_eq <= A0_pt0==B0_pt0;
+        pt1_eq <= A0_pt1==B0_pt1;
+        pt2_eq <= A0_pt2==B0_pt2;
+        pt3_eq <= A0_pt3==B0_pt3;
+
+        pt01_eq <= pt0_eq & pt1_eq;
+        pt01_gt <= pt1_gt | (pt1_eq & pt0_gt);
+
+        pt23_eq <= pt2_eq & pt3_eq;
+        pt23_gt <= pt3_gt | (pt3_eq & pt2_gt);
+
+        was_gt <= pt23_gt | (pt23_eq & pt01_gt);
+    end
+
+endmodule
+
+module cycle_trigger#(
     parameter WIDTH = 16
 ) (
-    input wire nrst, clk,
-    input [WIDTH-1:0] period,
-    input [WIDTH-1:0] delay,
+    input wire /*nrst,*/ clk,
+    input wire [WIDTH-1:0] period,
+
+    output reg [0:0] start_cycle,
+    output reg [0:0] half_cycle,
+    output reg [2:0] trig_out
+);
+    reg [WIDTH-1:0] counter;
+    reg [WIDTH-1:0] counter_delayed;// just to make placement easier - less branches from counter
+    reg [WIDTH-1:0] period_div2;
+    reg [WIDTH-1:0] period_shadow;
+
+    wire zero;
+
+    always @(posedge clk /*or negedge nrst*/) begin
+        /*if (!nrst) begin
+            counter <= 0;
+            //period_div2 <= 16'h0;
+            high_match_a <= 0;
+            high_match_b <= 0;
+            half_match_a <= 0;
+            half_match_b <= 0;
+
+            start_cycle <= 0;
+            half_cycle  <= 0;
+            trig_out    <= 0;
+        end else begin*/
+            if(zero) begin
+                start_cycle <= 1;
+                period_div2 <= period>>1;
+                period_shadow <= period;
+            end else begin
+                start_cycle <= 0;
+            end
 
-    output wire [0:0] last_tick,
-    output wire [0:0] mid_tick,
+            if (start_cycle) begin
+                counter <= period_shadow;
+            end else begin
+                counter <= counter-1;
+            end
+
+            counter_delayed <= counter;
+
+        //end //nrst
+    end
+
+    compare_eq#(.WIDTH(WIDTH))cmp_zero(
+        .clk(clk),
+        .A(counter_delayed),
+        .B(0),
+        .was_eq(zero)
+    );
+
+    compare_eq#(.WIDTH(WIDTH))cmp_half(
+        .clk(clk),
+        .A(counter_delayed),
+        .B(period_div2),
+        .was_eq(half_cycle)
+    );
+
+    compare_eq#(.WIDTH(WIDTH))cmp0(
+        .clk(clk),
+        .A(counter_delayed),
+        .B(3),
+        .was_eq(trig_out[0])
+    );
+
+    compare_eq#(.WIDTH(WIDTH))cmp1(
+        .clk(clk),
+        .A(counter_delayed),
+        .B(3),
+        .was_eq(trig_out[1])
+    );
+
+    compare_eq#(.WIDTH(WIDTH))cmp2(
+        .clk(clk),
+        .A(counter_delayed),
+        .B(9),
+        .was_eq(trig_out[2])
+    );
+
+endmodule
+
+/*module continous_pwm_gen#(
+    parameter WIDTH = 16
+) (
+    input wire nrst, clk,
+    input wire [WIDTH-1:0] period,
+    input wire [WIDTH-1:0] delay,
 
     output reg [0:0] pwm_out
 );
     reg [WIDTH-1:0] counter;
-    wire [WIDTH-1:0] next_cnt=counter+1;
-    wire [WIDTH-1:0] last_avail_cnt=period-1;
+
+    reg [WIDTH-1:0] _period;
+    reg [WIDTH-1:0] _delay;
+
+    reg [0:0] next_out;
+
+
+    reg [0:0] is_last_tick;
+    reg [0:0] is_last_tickA;
+    reg [0:0] is_last_tickB;
+    reg [0:0] is_mid_tick;
 
     // Counter logic
-    always_ff @(posedge clk or negedge nrst) begin
+    always @(posedge clk or negedge nrst) begin
         if (!nrst) begin
             counter <= 0;
             pwm_out <= 0;
+
+
+            next_out <= 0;
+
+            _period <= 0;
+            _delay <= 0;
+
+            is_last_tick <= 0;
+            is_last_tickA <= 0;
+            is_last_tickB <= 0;
         end else begin
-            if(counter >= last_avail_cnt) begin
-                counter <= 0;
-            end else begin
-                counter <= next_cnt;
-            end
+            _period <= period;
+            _delay <= delay;
+
+            is_last_tickA <= counter[WIDTH-1:8]==0;
+            is_last_tickB <= counter[7:0]==2;
+            is_last_tick <= is_last_tickA&is_last_tickB;
 
-            if ((next_cnt<delay) || (counter>=last_avail_cnt)) begin
-                pwm_out <= 0;
+            if (is_last_tick) begin
+                counter <= _period;
             end else begin
-                pwm_out <= 1;
+                counter <= counter-1;
             end
+
+            next_out <= is_last_tick;
+
+            pwm_out <= next_out;
         end
     end
 
-    assign last_tick = (next_cnt>=period);
-    assign mid_tick = ((next_cnt)==(period>>1));
-
-endmodule
+endmodule*/
 
 module single_shot_gen#(
     parameter WIDTH = 16
@@ -56,50 +279,43 @@ module single_shot_gen#(
     input wire nrst, clk,
     input wire trigger,
     input [WIDTH-1:0] delay,
-    input [WIDTH-1:0] duty,
+    input [WIDTH-1:0] period,
 
     output reg [0:0] pwm_out
 );
-    reg [WIDTH-1:0] counter;
-    reg [0:0] is_counting;
-    wire [WIDTH-1:0] next_cnt=counter+1;
-    wire [WIDTH-1:0] period=delay+duty;
+    reg [WIDTH:0] counter;
+    reg [WIDTH:0] counter2;
+
+    wire pwm_gt;
+
+    //reg [0:0] is_counting;
+    //reg [WIDTH-1:0] next_cnt;
+    //reg [WIDTH-1:0] period;
     //wire [WIDTH-1:0] last_avail_cnt=period-1;
 
-    always_ff @(posedge clk or negedge nrst) begin
-        if (!nrst) begin
-            counter <= 0;
-            is_counting <= 0;
+    always @(posedge clk /*or negedge nrst*/) begin
+        if (trigger) begin
+            counter <= {1'b0,period};
         end else begin
-            if (is_counting) begin
-
-                if(counter+1 >= period) begin
-                    counter <= 0;
-                    is_counting <= 0;
-                    pwm_out <= 0;
-                end else begin
-                    counter <= next_cnt;
+            counter <= counter-1;
+        end
 
-                    if (next_cnt>=delay) begin
-                        pwm_out <= 1;
-                    end else begin
-                        pwm_out <= 0;
-                    end
-                end
-            end else begin
-                if (trigger) begin
-                    is_counting <= 1;
+        counter2 <= counter;
 
-                    if ((delay==0) && (duty!=0)) begin
-                        pwm_out <= 1;
-                    end
-                end
-            end
-        end
+        pwm_out <= pwm_gt & !counter2[WIDTH];
     end
+
+    compare_gt#(.WIDTH(WIDTH))cmp_out(
+        .clk(clk),
+        .A(delay),
+        .B(counter2[WIDTH-1:0]),
+        .was_gt(pwm_gt)
+    );
+
+
 endmodule
 
-module phase_delay#(
+/*module phase_delay#(
     parameter WIDTH = 16,
     parameter FORWARD_DATA_WIDTH = 16
 )(
@@ -116,7 +332,7 @@ module phase_delay#(
 
     reg [WIDTH-1:0] delay_latched;
 
-    always_ff @(posedge clk or negedge nrst) begin
+    always @(posedge clk or negedge nrst) begin
         if (!nrst) begin
             counter <= 0;
             is_counting <=0;
@@ -141,79 +357,137 @@ module phase_delay#(
     end
 
     assign out_trig=((counter+1)>=delay) && is_counting;
+endmodule*/
+
+module simple_counter#(
+    parameter WIDTH = 14
+)(
+    input wire clk,
+    input wire trigger,
+    input wire if_counting,
+
+    output reg [WIDTH-1:0] cnt_out
+);
+    parameter HALF_WIDTH=7;
+
+    reg [HALF_WIDTH-1:0] cnt1, cnt0;
+
+    reg cnt0f;
+
+    always @(posedge clk /*or negedge nrst*/) begin
+        if (trigger) begin
+            cnt1 <= 0;
+            cnt0 <= 0;
+
+            cnt0f <= 0;
+        end else begin
+            //cnt1f <= &cnt1;
+            cnt0f <= &cnt0;
+
+            if(if_counting) begin
+                cnt0 <= cnt0+1;
+
+                if(cnt0f) begin
+                    cnt1 <= cnt1+1;
+                end
+
+
+            end
+
+            cnt_out <= {cnt1, cnt0};
+        end
+    end
 endmodule
 
 module pulse_train_gen#(
-    parameter WIDTH = 16,
-    parameter PULSE_COUNTER_WIDTH = 16
+    parameter TOTAL_PERIOD_WIDTH = 14,
+    parameter SINGLE_CYCLE_WIDTH = 8,
+    parameter PULSE_COUNTER_WIDTH = 8
 )(
     input wire nrst, clk,
     input wire trigger,
     input [PULSE_COUNTER_WIDTH-1:0] npuls,
-    input [WIDTH-1:0] period,
-    input [WIDTH-1:0] duty,
+    input [SINGLE_CYCLE_WIDTH-1:0] period,
+    input [SINGLE_CYCLE_WIDTH-1:0] duty,
 
     output reg [0:0] pwm_out
 );
-    reg [WIDTH-1:0] counter;
-    reg [0:0] is_counting;
-    reg [PULSE_COUNTER_WIDTH-1:0] remaining_pulses;
+    reg [TOTAL_PERIOD_WIDTH-1:0] counter;//total waveform counter
+    reg [TOTAL_PERIOD_WIDTH-1:0] counter2;
 
-    reg [WIDTH-1:0] period_local;
-    reg [WIDTH-1:0] duty_local;
+    reg [TOTAL_PERIOD_WIDTH-1:0] cycle_threshold;
 
-    wire [WIDTH-1:0] next_cnt = counter+1;
+    reg [TOTAL_PERIOD_WIDTH-1:0] cycle_threshold2;
 
-    always_ff @(posedge clk or negedge nrst) begin
-        if (!nrst) begin
-            counter <= 0;
-            is_counting <= 0;
-            pwm_out <=0;
-        end else begin
-            if (is_counting) begin
+    reg [TOTAL_PERIOD_WIDTH-1:0] next_cycle_threshold;
 
-                if(next_cnt >= period) begin
-                    counter <= 0;
+    reg [PULSE_COUNTER_WIDTH-1:0] cycle_counter;
+    reg [PULSE_COUNTER_WIDTH-1:0] next_cycle_counter;
 
-                    if (remaining_pulses > 0) begin
-                        remaining_pulses <= remaining_pulses-1;
-                        pwm_out <= 1;
+    reg [SINGLE_CYCLE_WIDTH-1:0] _period;
 
-                    end else begin
-                        pwm_out <= 0;
-                        is_counting <= 0;
-                    end
+    reg if_next_cycle;
 
-                end else begin
-                    counter <= next_cnt;
+    reg is_counting;
+    reg is_counting2;
 
-                    if (next_cnt>=duty) begin
-                        pwm_out <= 0;
-                    end else begin
-                        pwm_out <= 1;
-                    end
-                end
+    always @(posedge clk /*or negedge nrst*/) begin
+        /*if (!nrst) begin
+            is_counting <= 0;
+        end else begin*/
+            if(trigger) begin
+                //counter <= 0;
+                cycle_threshold <= {6'b0, _period};
+                cycle_counter <= npuls;
             end else begin
-                if (trigger) begin
-                    if ((period>0) && (duty!=0) && (npuls>0)) begin
-                        pwm_out <= 1;
-                        remaining_pulses <= npuls-1;
-                        is_counting <= 1;
-                        counter <= 0;
-                        period_local <= period;
-                        duty_local <= duty;
-                    end
-                end
+                //counter <= counter + is_counting2;
             end
-        end
+            counter2 <= counter;
+
+            _period <= period;
+
+            if(if_next_cycle & is_counting2) begin
+                cycle_counter <= next_cycle_counter;
+                cycle_threshold <= next_cycle_threshold;
+            end
+            next_cycle_counter <= cycle_counter-1;
+
+            is_counting <= |next_cycle_counter;
+            is_counting2 <= is_counting;
+
+            pwm_out <= if_next_cycle;
+
+            cycle_threshold2 <= cycle_threshold;
+        //end
     end
+
+    simple_counter cnt(
+        .clk(clk),
+        .trigger(trigger),
+        .if_counting(is_counting2),
+        .cnt_out(counter)
+    );
+
+    compare_eq#(.WIDTH(TOTAL_PERIOD_WIDTH))cmp_cycle(
+        .clk(clk),
+        .A(counter2),
+        .B(cycle_threshold2),
+        .was_eq(if_next_cycle)
+    );
+
+    /*add#(
+        .WIDTH(TOTAL_PERIOD_WIDTH)
+    )cycle_th(
+        .clk(clk),
+        .A(cycle_threshold2),
+        .B({6'b0, _period}),
+        .sum(next_cycle_threshold)
+    );*/
 endmodule
 
-typedef enum logic [1:0] {
-    ODD_TRAIN_FORCE_OFF,
-    ODD_TRAIN_ENA_CONTROL,
-    ODD_TRAIN_FORCE_ON
-} odd_train_flag_t;
+parameter [1:0] ODD_TRAIN_FORCE_OFF   = 2'b00;
+parameter [1:0] ODD_TRAIN_ENA_CONTROL = 2'b01;
+parameter [1:0] ODD_TRAIN_FORCE_ON    = 2'b10;
 
 module three_signal#(
     parameter FAST_PWM_WIDTH=8,
@@ -223,9 +497,10 @@ module three_signal#(
     input wire nrst, clk,
 
     input [SLOW_PWM_WIDTH-1:0] period1,
+
     input [SLOW_PWM_WIDTH-1:0] delay1,
 
-    input [SLOW_PWM_WIDTH-1:0] duty2,
+    input [SLOW_PWM_WIDTH-1:0] period2,
     input [SLOW_PWM_WIDTH-1:0] delay2,
 
     input [FAST_PWM_WIDTH-1:0] period3,
@@ -241,9 +516,47 @@ module three_signal#(
     output reg Out2,
     output reg Out3
 );
-    wire trigger_next_cycle;
-    wire trigger_even_cycle;
-    wire trigger_odd_cycle;
+    reg [SLOW_PWM_WIDTH-1:0] _period1;
+    reg [SLOW_PWM_WIDTH-1:0] _delay1;
+    reg [SLOW_PWM_WIDTH-1:0] _duty1;
+    reg [SLOW_PWM_WIDTH-1:0] _period2;
+    reg [SLOW_PWM_WIDTH-1:0] _delay2;
+    reg [FAST_PWM_WIDTH-1:0] _period3;
+    reg [FAST_PWM_WIDTH-1:0] _duty3;
+    reg [SLOW_PWM_WIDTH-1:0] _delay3;//delay is wrt slow pwm, thus longer bit length
+    reg [PULSE_COUNTER_WIDTH-1:0] _npuls3;
+    reg /*odd_train_flag_t*/ [1:0] _odd_train_flag;
+    reg _ena_odd_out3;
+
+    wire _Out1;
+    wire _Out2;
+    wire _Out3;
+
+
+    always @(posedge clk) begin
+        _period1        <= period1       ;
+        _delay1         <= delay1        ;
+
+        _period2          <= period2         ;
+        _delay2        <= delay2        ;
+
+        _period3        <= period3       ;
+        _duty3          <= duty3         ;
+        _delay3         <= delay3        ;
+        _npuls3         <= npuls3        ;
+        _odd_train_flag <= odd_train_flag;
+        _ena_odd_out3    <= ena_odd_out3 ;
+
+
+        //TODO - output already as reg; no additional latency needed?
+        Out1 <= _Out1;
+        Out2 <= _Out2;
+        Out3 <= _Out3;
+    end
+
+    //wire trigger_next_cycle;
+    //wire trigger_even_cycle;
+    //wire trigger_odd_cycle;
 
     wire [SLOW_PWM_WIDTH-1:0] delay3_part1;
     wire [SLOW_PWM_WIDTH-1:0] delay3_part234;
@@ -251,26 +564,56 @@ module three_signal#(
     assign delay3_part234 = delay3>>2;
     assign delay3_part1 = (delay3<4) ? 0 : (delay3 - (delay3_part234*3));
 
-    continous_pwm_gen #(.WIDTH(SLOW_PWM_WIDTH)) pwm1(
-        .nrst(nrst),
+    wire [0:0] start_cycle;
+    wire [0:0] half_cycle;
+    wire [2:0] trig_out;
+
+    cycle_trigger #(.WIDTH(SLOW_PWM_WIDTH)) cyc_trig(
+        //.nrst(nrst),
         .clk(clk),
+
         .period(period1),
-        .delay(delay1),
-        .last_tick(trigger_next_cycle),
-        .mid_tick(trigger_even_cycle),
-        .pwm_out(Out1)
+
+        .start_cycle(start_cycle),
+        .half_cycle(half_cycle),
+        .trig_out(trig_out)
+    );
+
+    single_shot_gen #(.WIDTH(SLOW_PWM_WIDTH)) pwm1(
+        .nrst(nrst),
+        .clk(clk),
+        .trigger(trig_out[0]),
+        .delay(_delay1),
+        .period(_period1),
+        .pwm_out(_Out1)
     );
 
     single_shot_gen #(.WIDTH(SLOW_PWM_WIDTH)) pwm2(
         .nrst(nrst),
         .clk(clk),
-        .trigger(trigger_next_cycle),
-        .delay(delay2),
-        .duty(duty2),
-        .pwm_out(Out2)
+        .trigger(trig_out[1]),
+        .delay(_delay2),
+        .period(_period2),
+        .pwm_out(_Out2)
     );
 
-    wire trigger_delay_1_to_2;
+    pulse_train_gen#(
+        .TOTAL_PERIOD_WIDTH(SLOW_PWM_WIDTH),
+        .SINGLE_CYCLE_WIDTH(FAST_PWM_WIDTH),
+        .PULSE_COUNTER_WIDTH(PULSE_COUNTER_WIDTH)
+    )pwm3(
+        .nrst(nrst),
+        .clk(clk),
+        .trigger(trig_out[2]),
+
+        .npuls(_npuls3),
+        .period(_period3),
+        .duty(_duty3),
+
+        .pwm_out(_Out3)
+    );
+
+    /*wire trigger_delay_1_to_2;
     wire trigger_delay_2_to_3;
     wire trigger_delay_3_to_4;
     wire trigger_delay_4_to_pulse_train;
@@ -293,57 +636,6 @@ module three_signal#(
 
     assign duty3_gen = data_4_to_gen[FAST_PWM_WIDTH-1:0];
     assign period3_gen = data_4_to_gen[FAST_PWM_WIDTH+FAST_PWM_WIDTH-1:FAST_PWM_WIDTH];
-    assign npuls3_gen = data_4_to_gen[FAST_PWM_WIDTH+FAST_PWM_WIDTH+PULSE_COUNTER_WIDTH-1:FAST_PWM_WIDTH+FAST_PWM_WIDTH];
-
-    phase_delay #(.WIDTH(SLOW_PWM_WIDTH),.FORWARD_DATA_WIDTH(FORWARD_DATA_WIDTH)) pd_1of4(
-        .nrst(nrst),
-        .clk(clk),
-        .in_trig(trigger_odd_cycle | trigger_even_cycle),
-        .delay(delay3_part1),
-        .in_data_fwd({delay3_part234, npuls3, period3, duty3}),
-        .out_trig(trigger_delay_1_to_2),
-        .out_data_fwd(data_1_to_2)
-    );
-
-    phase_delay #(.WIDTH(SLOW_PWM_WIDTH),.FORWARD_DATA_WIDTH(FORWARD_DATA_WIDTH)) pd_2of4(
-        .nrst(nrst),
-        .clk(clk),
-        .in_trig(trigger_delay_1_to_2),
-        .delay(data_1_to_2[DELAY_BITS_POS+SLOW_PWM_WIDTH-1:DELAY_BITS_POS]),
-        .in_data_fwd(data_1_to_2),
-        .out_trig(trigger_delay_2_to_3),
-        .out_data_fwd(data_2_to_3)
-    );
-
-    phase_delay #(.WIDTH(SLOW_PWM_WIDTH),.FORWARD_DATA_WIDTH(FORWARD_DATA_WIDTH)) pd_3of4(
-        .nrst(nrst),
-        .clk(clk),
-        .in_trig(trigger_delay_2_to_3),
-        .delay(data_2_to_3[DELAY_BITS_POS+SLOW_PWM_WIDTH-1:DELAY_BITS_POS]),
-        .in_data_fwd(data_2_to_3),
-        .out_trig(trigger_delay_3_to_4),
-        .out_data_fwd(data_3_to_4)
-    );
-
-    phase_delay #(.WIDTH(SLOW_PWM_WIDTH),.FORWARD_DATA_WIDTH(FORWARD_DATA_WIDTH)) pd_4of4(
-        .nrst(nrst),
-        .clk(clk),
-        .in_trig(trigger_delay_3_to_4),
-        .delay(data_3_to_4[DELAY_BITS_POS+SLOW_PWM_WIDTH-1:DELAY_BITS_POS]),
-        .in_data_fwd(data_3_to_4),
-        .out_trig(trigger_delay_4_to_pulse_train),
-        .out_data_fwd(data_4_to_gen)
-    );
-
-    pulse_train_gen #(.WIDTH(FAST_PWM_WIDTH),.PULSE_COUNTER_WIDTH(PULSE_COUNTER_WIDTH)) pwm3(
-        .nrst(nrst),
-        .clk(clk),
-        .trigger(trigger_delay_4_to_pulse_train),
-        .npuls(npuls3_gen),
-        .period(period3_gen),
-        .duty(duty3_gen),
-        .pwm_out(Out3)
-    );
-
+    assign npuls3_gen = data_4_to_gen[FAST_PWM_WIDTH+FAST_PWM_WIDTH+PULSE_COUNTER_WIDTH-1:FAST_PWM_WIDTH+FAST_PWM_WIDTH];*/
 endmodule
 

projects/riscv_usb/rtl/top.v

@@ -89,7 +89,7 @@ module top (
     // 3 signal
     wire [SLOW_PWM_WIDTH-1:0] period1;
     wire [SLOW_PWM_WIDTH-1:0] delay1;
-    wire [SLOW_PWM_WIDTH-1:0] duty2;
+    wire [SLOW_PWM_WIDTH-1:0] period2;
     wire [SLOW_PWM_WIDTH-1:0] delay2;
     wire [FAST_PWM_WIDTH-1:0] period3;
     wire [FAST_PWM_WIDTH-1:0] duty3;
@@ -244,7 +244,7 @@ module top (
     // --------
     assign period1 = mailbox_regs_flat[15:0];        // First 16 bits for period1
     assign delay1 = mailbox_regs_flat[31:16];        // Next 16 bits for delay1
-    assign duty2 = mailbox_regs_flat[47:32];         // Next 16 bits for duty2
+    assign period2 = mailbox_regs_flat[47:32];         // Next 16 bits for duty2
     assign delay2 = mailbox_regs_flat[63:48];        // Next 16 bits for delay2
     assign period3 = mailbox_regs_flat[79:64];       // Next 16 bits for period3
     assign duty3 = mailbox_regs_flat[95:80];         // Next 16 bits for duty3
@@ -259,10 +259,10 @@ module top (
         .SLOW_PWM_WIDTH(SLOW_PWM_WIDTH)
     ) three_signal_I(
         .nrst(~rst),
-        .clk(clk_24m), // TODO: fix later we have CDC problem here
+        .clk(clk_48m), // TODO: fix later we have CDC problem here
         .period1(period1),
         .delay1(delay1),
-        .duty2(duty2),
+        .period2(period2),
         .delay2(delay2),
         .period3(period3),
         .duty3(duty3),
@@ -371,8 +371,8 @@ module top (
 	reg clk_24m_s = 1'b0;
 	reg rst_s = 1'b1;
 
-	always #10.42 clk_48m_s <= !clk_48m_s;
-	always #20.84 clk_24m_s <= !clk_24m_s;
+	always #5 clk_48m_s <= !clk_48m_s;
+	always #20 clk_24m_s <= !clk_24m_s;
 
 	initial begin
 		#200 rst_s = 0;