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@@ -66,8 +66,10 @@ module e1_wb #(
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input wire bus_we,
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output wire bus_ack,
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- // Interrupt
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+ // External strobes
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output reg irq,
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+ output wire tick_tx,
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+ output wire tick_rx,
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// Common
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input wire clk,
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@@ -459,8 +461,8 @@ module e1_wb #(
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tx_underflow <= (tx_underflow & ~ctx_clear) | bdtx_miss;
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- // IRQ
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- // ---
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+ // External strobes
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+ // ----------------
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always @(posedge clk or posedge rst)
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if (rst)
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@@ -468,4 +470,7 @@ module e1_wb #(
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else
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irq <= ~bro_empty | rx_overflow | ~bto_empty | tx_underflow;
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+ assign tick_tx = int_tick; /* tick used for TX */
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+ assign tick_rx = ext_tick; /* tick recovered from RX */
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+
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endmodule // e1_wb
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