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@@ -127,18 +127,18 @@ module top (
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uart2wb #(
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.WB_N(3)
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) if_I (
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- .uart_rx(uart_rx),
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- .uart_tx(uart_tx),
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- .uart_div(8'd16),
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- .wb_wdata(wb_wdata),
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- .wb_rdata(wb_rdata),
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- .wb_addr(wb_addr),
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- .wb_we(wb_we),
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- .wb_cyc(wb_cyc),
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- .wb_ack(wb_ack),
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- .aux_csr(aux_csr),
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- .clk(clk_1x),
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- .rst(rst)
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+ .uart_rx (uart_rx),
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+ .uart_tx (uart_tx),
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+ .uart_div (8'd16),
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+ .wb_wdata (wb_wdata),
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+ .wb_rdata (wb_rdata),
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+ .wb_addr (wb_addr),
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+ .wb_we (wb_we),
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+ .wb_cyc (wb_cyc),
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+ .wb_ack (wb_ack),
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+ .aux_csr (aux_csr),
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+ .clk (clk_1x),
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+ .rst (rst)
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);
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assign dma_run = aux_csr[0];
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@@ -162,95 +162,95 @@ module top (
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// Controller
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qpi_memctrl #(
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- .CMD_READ(16'hEBEB),
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- .CMD_WRITE(16'h0202),
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- .DUMMY_CLK(6),
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- .PAUSE_CLK(8),
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- .FIFO_DEPTH(1),
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- .N_CS(2),
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- .PHY_SPEED(PHY_SPEED),
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- .PHY_WIDTH(1),
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- .PHY_DELAY((PHY_SPEED == 1) ? 2 : ((PHY_SPEED == 2) ? 3 : 4))
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+ .CMD_READ (16'hEBEB),
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+ .CMD_WRITE (16'h0202),
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+ .DUMMY_CLK (6),
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+ .PAUSE_CLK (8),
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+ .FIFO_DEPTH (1),
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+ .N_CS (2),
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+ .PHY_SPEED (PHY_SPEED),
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+ .PHY_WIDTH (1),
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+ .PHY_DELAY ((PHY_SPEED == 1) ? 2 : ((PHY_SPEED == 2) ? 3 : 4))
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) memctrl_I (
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- .phy_io_i(phy_io_i),
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- .phy_io_o(phy_io_o),
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- .phy_io_oe(phy_io_oe),
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- .phy_clk_o(phy_clk_o),
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- .phy_cs_o(phy_cs_o),
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- .mi_addr_cs(mi_addr[31:30]),
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- .mi_addr({mi_addr[21:0], 2'b00 }), /* 32 bits aligned */
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- .mi_len(mi_len),
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- .mi_rw(mi_rw),
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- .mi_valid(mi_valid),
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- .mi_ready(mi_ready),
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- .mi_wdata(mi_wdata),
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- .mi_wack(mi_wack),
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- .mi_wlast(mi_wlast),
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- .mi_rdata(mi_rdata),
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- .mi_rstb(mi_rstb),
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- .mi_rlast(mi_rlast),
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- .wb_wdata(wb_wdata),
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- .wb_rdata(wb_rdata[31:0]),
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- .wb_addr(wb_addr[4:0]),
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- .wb_we(wb_we),
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- .wb_cyc(wb_cyc[0]),
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- .wb_ack(wb_ack[0]),
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- .clk(clk_1x),
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- .rst(rst)
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+ .phy_io_i (phy_io_i),
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+ .phy_io_o (phy_io_o),
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+ .phy_io_oe (phy_io_oe),
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+ .phy_clk_o (phy_clk_o),
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+ .phy_cs_o (phy_cs_o),
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+ .mi_addr_cs (mi_addr[31:30]),
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+ .mi_addr ({mi_addr[21:0], 2'b00 }), /* 32 bits aligned */
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+ .mi_len (mi_len),
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+ .mi_rw (mi_rw),
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+ .mi_valid (mi_valid),
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+ .mi_ready (mi_ready),
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+ .mi_wdata (mi_wdata),
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+ .mi_wack (mi_wack),
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+ .mi_wlast (mi_wlast),
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+ .mi_rdata (mi_rdata),
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+ .mi_rstb (mi_rstb),
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+ .mi_rlast (mi_rlast),
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+ .wb_wdata (wb_wdata),
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+ .wb_rdata (wb_rdata[31:0]),
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+ .wb_addr (wb_addr[4:0]),
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+ .wb_we (wb_we),
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+ .wb_cyc (wb_cyc[0]),
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+ .wb_ack (wb_ack[0]),
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+ .clk (clk_1x),
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+ .rst (rst)
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);
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// PHY
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generate
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if (PHY_SPEED == 1)
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qpi_phy_ice40_1x #(
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- .N_CS(2),
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- .WITH_CLK(1),
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- .NEG_IN(0)
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+ .N_CS (2),
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+ .WITH_CLK (1),
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+ .NEG_IN (0)
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) phy_I (
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- .pad_io(spi_io),
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- .pad_clk(spi_sck),
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- .pad_cs_n(spi_cs_n),
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- .phy_io_i(phy_io_i),
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- .phy_io_o(phy_io_o),
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- .phy_io_oe(phy_io_oe),
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- .phy_clk_o(phy_clk_o),
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- .phy_cs_o(phy_cs_o),
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- .clk(clk_1x)
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+ .pad_io (spi_io),
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+ .pad_clk (spi_sck),
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+ .pad_cs_n (spi_cs_n),
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+ .phy_io_i (phy_io_i),
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+ .phy_io_o (phy_io_o),
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+ .phy_io_oe (phy_io_oe),
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+ .phy_clk_o (phy_clk_o),
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+ .phy_cs_o (phy_cs_o),
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+ .clk (clk_1x)
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);
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else if (PHY_SPEED == 2)
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qpi_phy_ice40_2x #(
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- .N_CS(2),
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- .WITH_CLK(1),
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+ .N_CS (2),
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+ .WITH_CLK (1),
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) phy_I (
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- .pad_io(spi_io),
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- .pad_clk(spi_sck),
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- .pad_cs_n(spi_cs_n),
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- .phy_io_i(phy_io_i),
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- .phy_io_o(phy_io_o),
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- .phy_io_oe(phy_io_oe),
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- .phy_clk_o(phy_clk_o),
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- .phy_cs_o(phy_cs_o),
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- .clk_1x(clk_1x),
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- .clk_2x(clk_2x)
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+ .pad_io (spi_io),
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+ .pad_clk (spi_sck),
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+ .pad_cs_n (spi_cs_n),
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+ .phy_io_i (phy_io_i),
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+ .phy_io_o (phy_io_o),
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+ .phy_io_oe (phy_io_oe),
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+ .phy_clk_o (phy_clk_o),
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+ .phy_cs_o (phy_cs_o),
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+ .clk_1x (clk_1x),
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+ .clk_2x (clk_2x)
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);
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else if (PHY_SPEED == 4)
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qpi_phy_ice40_4x #(
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- .N_CS(2),
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- .WITH_CLK(1),
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+ .N_CS (2),
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+ .WITH_CLK (1),
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) phy_I (
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- .pad_io(spi_io),
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- .pad_clk(spi_sck),
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- .pad_cs_n(spi_cs_n),
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- .phy_io_i(phy_io_i),
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- .phy_io_o(phy_io_o),
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- .phy_io_oe(phy_io_oe),
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- .phy_clk_o(phy_clk_o),
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- .phy_cs_o(phy_cs_o),
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- .clk_1x(clk_1x),
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- .clk_4x(clk_4x),
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- .clk_sync(sync_4x)
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+ .pad_io (spi_io),
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+ .pad_clk (spi_sck),
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+ .pad_cs_n (spi_cs_n),
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+ .phy_io_i (phy_io_i),
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+ .phy_io_o (phy_io_o),
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+ .phy_io_oe (phy_io_oe),
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+ .phy_clk_o (phy_clk_o),
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+ .phy_cs_o (phy_cs_o),
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+ .clk_1x (clk_1x),
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+ .clk_4x (clk_4x),
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+ .clk_sync (sync_4x)
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);
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endgenerate
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@@ -282,65 +282,65 @@ module top (
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// Controller
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hbus_memctrl hram_ctrl_I (
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- .phy_ck_en(phy_ck_en),
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- .phy_rwds_in(phy_rwds_in),
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- .phy_rwds_out(phy_rwds_out),
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- .phy_rwds_oe(phy_rwds_oe),
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- .phy_dq_in(phy_dq_in),
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- .phy_dq_out(phy_dq_out),
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- .phy_dq_oe(phy_dq_oe),
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- .phy_cs_n(phy_cs_n),
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- .phy_rst_n(phy_rst_n),
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- .phy_cfg_wdata(phy_cfg_wdata),
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- .phy_cfg_rdata(phy_cfg_rdata),
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- .phy_cfg_stb(phy_cfg_stb),
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- .mi_addr_cs(mi_addr[31:30]),
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- .mi_addr({1'b0, mi_addr[29:0], 1'b0}), /* 32b aligned */
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- .mi_len(mi_len),
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- .mi_rw(mi_rw),
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- .mi_linear(1'b0),
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- .mi_valid(mi_valid),
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- .mi_ready(mi_ready),
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- .mi_wdata(mi_wdata),
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- .mi_wmsk(4'h0),
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- .mi_wack(mi_wack),
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- .mi_rdata(mi_rdata),
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- .mi_rstb(mi_rstb),
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- .wb_wdata(wb_wdata),
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- .wb_rdata(wb_rdata[31:0]),
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- .wb_addr(wb_addr[3:0]),
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- .wb_we(wb_we),
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- .wb_cyc(wb_cyc[0]),
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- .wb_ack(wb_ack[0]),
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- .clk(clk_1x),
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- .rst(rst)
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+ .phy_ck_en (phy_ck_en),
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+ .phy_rwds_in (phy_rwds_in),
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+ .phy_rwds_out (phy_rwds_out),
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+ .phy_rwds_oe (phy_rwds_oe),
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+ .phy_dq_in (phy_dq_in),
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+ .phy_dq_out (phy_dq_out),
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+ .phy_dq_oe (phy_dq_oe),
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+ .phy_cs_n (phy_cs_n),
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+ .phy_rst_n (phy_rst_n),
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+ .phy_cfg_wdata (phy_cfg_wdata),
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+ .phy_cfg_rdata (phy_cfg_rdata),
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+ .phy_cfg_stb (phy_cfg_stb),
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+ .mi_addr_cs (mi_addr[31:30]),
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+ .mi_addr ({1'b0, mi_addr[29:0], 1'b0}), /* 32b aligned */
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+ .mi_len (mi_len),
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+ .mi_rw (mi_rw),
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+ .mi_linear (1'b0),
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+ .mi_valid (mi_valid),
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+ .mi_ready (mi_ready),
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+ .mi_wdata (mi_wdata),
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+ .mi_wmsk (4'h0),
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+ .mi_wack (mi_wack),
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+ .mi_rdata (mi_rdata),
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+ .mi_rstb (mi_rstb),
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+ .wb_wdata (wb_wdata),
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+ .wb_rdata (wb_rdata[31:0]),
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+ .wb_addr (wb_addr[3:0]),
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+ .wb_we (wb_we),
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+ .wb_cyc (wb_cyc[0]),
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+ .wb_ack (wb_ack[0]),
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+ .clk (clk_1x),
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+ .rst (rst)
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);
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// PHY
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hbus_phy_ice40 hram_phy_I (
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- .hbus_dq(hram_dq),
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- .hbus_rwds(hram_rwds),
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- .hbus_ck(hram_ck),
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- .hbus_cs_n(hram_cs_n),
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- .hbus_rst_n(hram_rst_n),
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- .phy_ck_en(phy_ck_en),
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- .phy_rwds_in(phy_rwds_in),
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- .phy_rwds_out(phy_rwds_out),
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- .phy_rwds_oe(phy_rwds_oe),
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- .phy_dq_in(phy_dq_in),
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- .phy_dq_out(phy_dq_out),
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- .phy_dq_oe(phy_dq_oe),
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- .phy_cs_n(phy_cs_n),
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- .phy_rst_n(phy_rst_n),
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- .phy_cfg_wdata(phy_cfg_wdata),
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- .phy_cfg_rdata(phy_cfg_rdata),
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- .phy_cfg_stb(phy_cfg_stb),
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- .clk_rd_delay(clk_rd_delay),
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- .clk_1x(clk_1x),
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- .clk_4x(clk_4x),
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- .clk_rd(clk_rd),
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- .sync_4x(sync_4x),
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- .sync_rd(sync_rd)
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+ .hbus_dq (hram_dq),
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+ .hbus_rwds (hram_rwds),
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+ .hbus_ck (hram_ck),
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+ .hbus_cs_n (hram_cs_n),
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+ .hbus_rst_n (hram_rst_n),
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+ .phy_ck_en (phy_ck_en),
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+ .phy_rwds_in (phy_rwds_in),
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+ .phy_rwds_out (phy_rwds_out),
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+ .phy_rwds_oe (phy_rwds_oe),
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+ .phy_dq_in (phy_dq_in),
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+ .phy_dq_out (phy_dq_out),
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+ .phy_dq_oe (phy_dq_oe),
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+ .phy_cs_n (phy_cs_n),
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+ .phy_rst_n (phy_rst_n),
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+ .phy_cfg_wdata (phy_cfg_wdata),
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+ .phy_cfg_rdata (phy_cfg_rdata),
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+ .phy_cfg_stb (phy_cfg_stb),
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+ .clk_rd_delay (clk_rd_delay),
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+ .clk_1x (clk_1x),
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+ .clk_4x (clk_4x),
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+ .clk_rd (clk_rd),
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+ .sync_4x (sync_4x),
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+ .sync_rd (sync_rd)
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);
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`endif
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@@ -351,23 +351,23 @@ module top (
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memtest #(
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.ADDR_WIDTH(32)
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) memtest_I (
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- .mi_addr(mi0_addr),
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- .mi_len(mi0_len),
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- .mi_rw(mi0_rw),
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- .mi_valid(mi0_valid),
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- .mi_ready(mi0_ready),
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- .mi_wdata(mi0_wdata),
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- .mi_wack(mi0_wack),
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- .mi_rdata(mi0_rdata),
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- .mi_rstb(mi0_rstb),
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- .wb_wdata(wb_wdata),
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- .wb_rdata(wb_rdata[63:32]),
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- .wb_addr(wb_addr[8:0]),
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- .wb_we(wb_we),
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- .wb_cyc(wb_cyc[1]),
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- .wb_ack(wb_ack[1]),
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- .clk(clk_1x),
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- .rst(rst)
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+ .mi_addr (mi0_addr),
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+ .mi_len (mi0_len),
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+ .mi_rw (mi0_rw),
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+ .mi_valid (mi0_valid),
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+ .mi_ready (mi0_ready),
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+ .mi_wdata (mi0_wdata),
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+ .mi_wack (mi0_wack),
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+ .mi_rdata (mi0_rdata),
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+ .mi_rstb (mi0_rstb),
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+ .wb_wdata (wb_wdata),
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+ .wb_rdata (wb_rdata[63:32]),
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+ .wb_addr (wb_addr[8:0]),
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+ .wb_we (wb_we),
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+ .wb_cyc (wb_cyc[1]),
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+ .wb_ack (wb_ack[1]),
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+ .clk (clk_1x),
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+ .rst (rst)
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);
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@@ -407,30 +407,30 @@ module top (
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.DW(12)
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`endif
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) hdmi_I (
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- .hdmi_data(hdmi_data),
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- .hdmi_hsync(hdmi_hsync),
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- .hdmi_vsync(hdmi_vsync),
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- .hdmi_de(hdmi_de),
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- .hdmi_clk(hdmi_clk),
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- .wb_wdata(wb_wdata),
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- .wb_rdata(wb_rdata[95:64]),
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- .wb_addr(wb_addr[6:0]),
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- .wb_we(wb_we),
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- .wb_cyc(wb_cyc[2]),
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- .wb_ack(wb_ack[2]),
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- .mi_addr(mi1_addr),
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- .mi_len(mi1_len),
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- .mi_rw(mi1_rw),
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- .mi_valid(mi1_valid),
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- .mi_ready(mi1_ready),
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|
- .mi_wdata(mi1_wdata),
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|
|
- .mi_wack(mi1_wack),
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|
- .mi_rdata(mi1_rdata),
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|
- .mi_rstb(mi1_rstb),
|
|
|
- .clk_1x(clk_1x),
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|
- .clk_4x(clk_4x),
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|
|
- .sync_4x(sync_4x),
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|
|
- .rst(rst)
|
|
|
+ .hdmi_data (hdmi_data),
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|
+ .hdmi_hsync (hdmi_hsync),
|
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|
+ .hdmi_vsync (hdmi_vsync),
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|
|
+ .hdmi_de (hdmi_de),
|
|
|
+ .hdmi_clk (hdmi_clk),
|
|
|
+ .wb_wdata (wb_wdata),
|
|
|
+ .wb_rdata (wb_rdata[95:64]),
|
|
|
+ .wb_addr (wb_addr[6:0]),
|
|
|
+ .wb_we (wb_we),
|
|
|
+ .wb_cyc (wb_cyc[2]),
|
|
|
+ .wb_ack (wb_ack[2]),
|
|
|
+ .mi_addr (mi1_addr),
|
|
|
+ .mi_len (mi1_len),
|
|
|
+ .mi_rw (mi1_rw),
|
|
|
+ .mi_valid (mi1_valid),
|
|
|
+ .mi_ready (mi1_ready),
|
|
|
+ .mi_wdata (mi1_wdata),
|
|
|
+ .mi_wack (mi1_wack),
|
|
|
+ .mi_rdata (mi1_rdata),
|
|
|
+ .mi_rstb (mi1_rstb),
|
|
|
+ .clk_1x (clk_1x),
|
|
|
+ .clk_4x (clk_4x),
|
|
|
+ .sync_4x (sync_4x),
|
|
|
+ .rst (rst)
|
|
|
);
|
|
|
`else
|
|
|
// Dummy wishbone
|
|
|
@@ -450,15 +450,15 @@ module top (
|
|
|
// -------------
|
|
|
|
|
|
sysmgr sysmgr_I (
|
|
|
- .delay(clk_rd_delay),
|
|
|
- .clk_in(clk_in),
|
|
|
- .clk_1x(clk_1x),
|
|
|
- .clk_2x(clk_2x),
|
|
|
- .clk_4x(clk_4x),
|
|
|
- .clk_rd(clk_rd),
|
|
|
- .sync_4x(sync_4x),
|
|
|
- .sync_rd(sync_rd),
|
|
|
- .rst(rst)
|
|
|
+ .delay (clk_rd_delay),
|
|
|
+ .clk_in (clk_in),
|
|
|
+ .clk_1x (clk_1x),
|
|
|
+ .clk_2x (clk_2x),
|
|
|
+ .clk_4x (clk_4x),
|
|
|
+ .clk_rd (clk_rd),
|
|
|
+ .sync_4x (sync_4x),
|
|
|
+ .sync_rd (sync_rd),
|
|
|
+ .rst (rst)
|
|
|
);
|
|
|
|
|
|
endmodule
|
Sylvain Munaut