Flatten the mailbox registers.

Signed-off-by: Jakub Duchniewicz <j.duchniewicz@gmail.com>

projects/riscv_usb/rtl/mailbox_wb.v

@@ -23,17 +23,20 @@ module mailbox_wb #(
     input  wire             wb_cyc,
     output reg              wb_ack,
 
-    // Custom hardware side (RTL)
-    output reg [DW-1:0]     registers [15:0]  // 16 registers of 16 bits width
+    // Flattened custom hardware side (RTL)
+    output wire [DW*16-1:0] registers_flat  // Flattened register array (16 registers of 16 bits each)
 );
 
+    // Internal registers (flattened version)
+    reg [DW-1:0] registers_array[15:0];  // 16 registers, each 16 bits wide
+
     // Always reset the registers on reset signal
     integer i;
     always @(posedge clk or posedge rst) begin
         if (rst) begin
             wb_ack <= 1'b0;
             for (i = 0; i < 16; i = i + 1) begin
-                registers[i] <= 16'h0; // Reset all registers to 0
+                registers_array[i] <= {DW{1'b0}}; // Reset all registers to 0
             end
         end else begin
             // Handle Wishbone communication
@@ -42,47 +45,55 @@ module mailbox_wb #(
             // Write operation (if write enable is active)
             if (wb_we && wb_cyc) begin
                 case (wb_addr)
-                    4'b0000: registers[0] <= wb_wdata;
-                    4'b0001: registers[1] <= wb_wdata;
-                    4'b0010: registers[2] <= wb_wdata;
-                    4'b0011: registers[3] <= wb_wdata;
-                    4'b0100: registers[4] <= wb_wdata;
-                    4'b0101: registers[5] <= wb_wdata;
-                    4'b0110: registers[6] <= wb_wdata;
-                    4'b0111: registers[7] <= wb_wdata;
-                    4'b1000: registers[8] <= wb_wdata;
-                    4'b1001: registers[9] <= wb_wdata;
-                    4'b1010: registers[10] <= wb_wdata;
-                    4'b1011: registers[11] <= wb_wdata;
-                    4'b1100: registers[12] <= wb_wdata;
-                    4'b1101: registers[13] <= wb_wdata;
-                    4'b1110: registers[14] <= wb_wdata;
-                    4'b1111: registers[15] <= wb_wdata;
+                    4'b0000: registers_array[0] <= wb_wdata;
+                    4'b0001: registers_array[1] <= wb_wdata;
+                    4'b0010: registers_array[2] <= wb_wdata;
+                    4'b0011: registers_array[3] <= wb_wdata;
+                    4'b0100: registers_array[4] <= wb_wdata;
+                    4'b0101: registers_array[5] <= wb_wdata;
+                    4'b0110: registers_array[6] <= wb_wdata;
+                    4'b0111: registers_array[7] <= wb_wdata;
+                    4'b1000: registers_array[8] <= wb_wdata;
+                    4'b1001: registers_array[9] <= wb_wdata;
+                    4'b1010: registers_array[10] <= wb_wdata;
+                    4'b1011: registers_array[11] <= wb_wdata;
+                    4'b1100: registers_array[12] <= wb_wdata;
+                    4'b1101: registers_array[13] <= wb_wdata;
+                    4'b1110: registers_array[14] <= wb_wdata;
+                    4'b1111: registers_array[15] <= wb_wdata;
                 endcase
             end
 
             // Read operation (read the correct register based on address)
             case (wb_addr)
-                4'b0000: wb_rdata <= registers[0];
-                4'b0001: wb_rdata <= registers[1];
-                4'b0010: wb_rdata <= registers[2];
-                4'b0011: wb_rdata <= registers[3];
-                4'b0100: wb_rdata <= registers[4];
-                4'b0101: wb_rdata <= registers[5];
-                4'b0110: wb_rdata <= registers[6];
-                4'b0111: wb_rdata <= registers[7];
-                4'b1000: wb_rdata <= registers[8];
-                4'b1001: wb_rdata <= registers[9];
-                4'b1010: wb_rdata <= registers[10];
-                4'b1011: wb_rdata <= registers[11];
-                4'b1100: wb_rdata <= registers[12];
-                4'b1101: wb_rdata <= registers[13];
-                4'b1110: wb_rdata <= registers[14];
-                4'b1111: wb_rdata <= registers[15];
-                default: wb_rdata <= 16'hDEAD; // Default error value
+                4'b0000: wb_rdata <= registers_array[0];
+                4'b0001: wb_rdata <= registers_array[1];
+                4'b0010: wb_rdata <= registers_array[2];
+                4'b0011: wb_rdata <= registers_array[3];
+                4'b0100: wb_rdata <= registers_array[4];
+                4'b0101: wb_rdata <= registers_array[5];
+                4'b0110: wb_rdata <= registers_array[6];
+                4'b0111: wb_rdata <= registers_array[7];
+                4'b1000: wb_rdata <= registers_array[8];
+                4'b1001: wb_rdata <= registers_array[9];
+                4'b1010: wb_rdata <= registers_array[10];
+                4'b1011: wb_rdata <= registers_array[11];
+                4'b1100: wb_rdata <= registers_array[12];
+                4'b1101: wb_rdata <= registers_array[13];
+                4'b1110: wb_rdata <= registers_array[14];
+                4'b1111: wb_rdata <= registers_array[15];
+                default: wb_rdata <= {DW{1'b0}}; // Default error value
             endcase
         end
     end
 
+    // Flatten the registers array to the output port (registers_flat)
+    generate
+        genvar j;
+        for (j = 0; j < 16; j = j + 1) begin : flatten
+            assign registers_flat[DW*(j+1)-1:DW*j] = registers_array[j];
+        end
+    endgenerate
+
 endmodule
 

projects/riscv_usb/rtl/top.v

@@ -50,7 +50,7 @@ module top (
 );
 
 	localparam integer SPRAM_AW = 14; /* 14 => 64k, 15 => 128k */
-	localparam integer WB_N  =  6;
+	localparam integer WB_N  =  8; // TODO: Reduce
 
 	localparam integer WB_DW = 32;
 	localparam integer WB_AW = 16;
@@ -99,7 +99,7 @@ module top (
     wire ena_odd_out3;
 
 	// Mailbox signal wires
-	wire [15:0] mailbox_regs [15:0];
+    wire [16*16-1:0] mailbox_regs_flat;  // Flattened register array (16 registers of 16 bits each)
 
 	// SoC
 	// ---
@@ -217,7 +217,7 @@ module top (
 		.rst      (rst)
 	);
 
-	//assign wb_rdata[5] = 0;
+	assign wb_rdata[5] = 0;
 
 	// WB Mailbox [6] TODO: this will move to lower addresses
 	// ----------
@@ -229,11 +229,11 @@ module top (
 		.rst(rst),
 		.wb_addr(wb_addr[4-1:0]),
 		.wb_wdata(wb_wdata),
-		.wb_rdata(wb_rdata[5]),
+		.wb_rdata(wb_rdata[6]),
 		.wb_we(wb_we),
-		.wb_cyc(wb_cyc),
-		.wb_ack(wb_ack),
-		.registers(mailbox_regs)
+		.wb_cyc(wb_cyc[6]),
+		.wb_ack(wb_ack[6]),
+		.registers_flat(mailbox_regs_flat)
 	);
 
     // 3 Signal