add led example

projects/first_LED_example/.gitignore

@@ -0,0 +1,5 @@
+*.asc
+*.bin
+*.json
+*.log
+*.rpt

projects/first_LED_example/Makefile

@@ -0,0 +1,7 @@
+PROJ = test_duty
+ADD_SRC = buttons.v duty.v
+
+PIN_DEF = icebreaker.pcf
+DEVICE = up5k
+
+include main.mk

projects/first_LED_example/buttons.v

@@ -0,0 +1,27 @@
+`timescale 1ns / 1ps
+
+module buttons(
+	input CLK,
+	input BTN1,
+	input BTN2,
+	input BTN3,
+	input BTN_N,
+	output reg [15:0] duty_val
+	);	
+	
+	wire [3:0]butts={BTN_N,BTN3,BTN2,BTN1};
+	reg [3:0]butts_buf;
+	
+	//b1111111111111100 - ciemne
+	always @(posedge CLK) begin
+		case(butts)
+			4'b0001: duty_val <= 16'b0000000000000000;
+			4'b0010: duty_val <= 16'b0000000000000000;
+			4'b0100: duty_val <= 16'b0000000000000000;
+			4'b1000: duty_val <= 16'b1000000000000000;
+            default: duty_val <= 16'b0000000000000000;
+        endcase
+		butts_buf<=butts;
+	end
+
+endmodule

projects/first_LED_example/duty.v

@@ -0,0 +1,17 @@
+`timescale 1ns / 1ps
+
+module duty(
+	input CLK,
+	input [15:0] cmp,
+	output reg out
+    );	
+	reg [15:0]cnt;
+	reg [15:0]cmp_buf;
+
+	always @(posedge CLK) begin
+		cnt<=cnt+1;
+		out<=cnt>cmp_buf;
+		cmp_buf<=cmp;
+	end
+
+endmodule

projects/first_LED_example/icebreaker.pcf

@@ -0,0 +1,109 @@
+# 12 MHz clock
+set_io -nowarn CLK        35
+
+# RS232
+set_io -nowarn RX          6
+set_io -nowarn TX          9
+
+# LEDs and Button
+set_io -nowarn BTN_N      10
+set_io -nowarn LEDR_N     11
+set_io -nowarn LEDG_N     37
+
+# RGB LED Driver
+set_io -nowarn LED_RED_N  39
+set_io -nowarn LED_GRN_N  40
+set_io -nowarn LED_BLU_N  41
+
+# SPI Flash
+set_io -nowarn FLASH_SCK  15
+set_io -nowarn FLASH_SSB  16
+set_io -nowarn FLASH_IO0  14
+set_io -nowarn FLASH_IO1  17
+set_io -nowarn FLASH_IO2  12
+set_io -nowarn FLASH_IO3  13
+
+# PMOD 1A
+set_io -nowarn P1A1        4
+set_io -nowarn P1A2        2
+set_io -nowarn P1A3       47
+set_io -nowarn P1A4       45
+set_io -nowarn P1A7        3
+set_io -nowarn P1A8       48
+set_io -nowarn P1A9       46
+set_io -nowarn P1A10      44
+
+# PMOD 1B
+set_io -nowarn P1B1       43
+set_io -nowarn P1B2       38
+set_io -nowarn P1B3       34
+set_io -nowarn P1B4       31
+set_io -nowarn P1B7       42
+set_io -nowarn P1B8       36
+set_io -nowarn P1B9       32
+set_io -nowarn P1B10      28
+
+# PMOD 2
+set_io -nowarn P2_1       27
+set_io -nowarn P2_2       25
+set_io -nowarn P2_3       21
+set_io -nowarn P2_4       19
+set_io -nowarn P2_7       26
+set_io -nowarn P2_8       23
+set_io -nowarn P2_9       20
+set_io -nowarn P2_10      18
+
+# LEDs and Buttons (PMOD 2)
+set_io -nowarn LED1       26
+set_io -nowarn LED2       27
+set_io -nowarn LED3       25
+set_io -nowarn LED4       23
+set_io -nowarn LED5       21
+set_io -nowarn BTN1       20
+set_io -nowarn BTN2       19
+set_io -nowarn BTN3       18
+
+set_io -nowarn led[0]     26
+set_io -nowarn led[1]     27
+set_io -nowarn led[2]     25
+set_io -nowarn led[3]     23
+set_io -nowarn led[4]     21
+
+## WTFpga assignments
+# 7 Segment
+set_io -nowarn 7SAA        4
+set_io -nowarn 7SAE        2
+set_io -nowarn 7SAB       47
+set_io -nowarn 7SAF       45
+set_io -nowarn 7SAC        3
+set_io -nowarn 7SAG       48
+set_io -nowarn 7SAD       46
+set_io -nowarn 7SCA       44
+
+set_io -nowarn seg[0]      4
+set_io -nowarn seg[1]      2
+set_io -nowarn seg[2]     47
+set_io -nowarn seg[3]     45
+set_io -nowarn seg[4]      3
+set_io -nowarn seg[5]     48
+set_io -nowarn seg[6]     46
+set_io -nowarn ca         44
+
+# DIP-Switch
+set_io -nowarn DIP1       43
+set_io -nowarn DIP2       38
+set_io -nowarn DIP3       34
+set_io -nowarn DIP4       31
+set_io -nowarn DIP5       42
+set_io -nowarn DIP6       36
+set_io -nowarn DIP7       32
+set_io -nowarn DIP8       28
+
+set_io -nowarn sw[0]     43
+set_io -nowarn sw[1]     38
+set_io -nowarn sw[2]     34
+set_io -nowarn sw[3]     31
+set_io -nowarn sw[4]     42
+set_io -nowarn sw[5]     36
+set_io -nowarn sw[6]     32
+set_io -nowarn sw[7]     28

projects/first_LED_example/main.mk

@@ -0,0 +1,51 @@
+
+all: $(PROJ).rpt $(PROJ).bin
+
+%.blif: %.v $(ADD_SRC) $(ADD_DEPS)
+	yosys -ql $*.log -p 'synth_ice40 -top top -blif $@' $< $(ADD_SRC)
+
+%.json: %.v $(ADD_SRC) $(ADD_DEPS)
+	yosys -ql $*.log -p 'synth_ice40 -top top -json $@' $< $(ADD_SRC)
+
+ifeq ($(USE_ARACHNEPNR),)
+%.asc: $(PIN_DEF) %.json
+	nextpnr-ice40 --$(DEVICE) --json $(filter-out $<,$^) --pcf $< --asc $@
+else
+%.asc: $(PIN_DEF) %.blif
+	arachne-pnr -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) -o $@ -p $^
+endif
+
+
+%.bin: %.asc
+	icepack $< $@
+
+%.rpt: %.asc
+	icetime -d $(DEVICE) -mtr $@ $<
+
+%_tb: %_tb.v %.v
+	iverilog -o $@ $^
+
+%_tb.vcd: %_tb
+	vvp -N $< +vcd=$@
+
+%_syn.v: %.blif
+	yosys -p 'read_blif -wideports $^; write_verilog $@'
+
+%_syntb: %_tb.v %_syn.v
+	iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
+
+%_syntb.vcd: %_syntb
+	vvp -N $< +vcd=$@
+
+prog: $(PROJ).bin
+	iceprog $<
+
+sudo-prog: $(PROJ).bin
+	@echo 'Executing prog as root!!!'
+	sudo iceprog $<
+
+clean:
+	rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin $(PROJ).json $(PROJ).log $(ADD_CLEAN)
+
+.SECONDARY:
+.PHONY: all prog clean

projects/first_LED_example/test_duty.v

@@ -0,0 +1,55 @@
+`timescale 1ns / 1ps
+//define our module and it's inputs/outputs
+module top(
+	input CLK,
+	input BTN1,
+	input BTN2,
+	input BTN3,
+	input BTN_N,
+	//input [7:0] sw,
+	output [4:0] led
+	//output [6:0] seg,
+	//output ca
+    );
+
+	reg [4:0]desired_led;
+
+	assign led=desired_led;
+
+	always @(posedge CLK) begin
+		desired_led[0] = BTN1 & BTN2 & BTN3;
+		desired_led[1] = BTN1;
+		desired_led[2] = BTN2;
+		desired_led[3] = BTN3;
+		desired_led[4] = !BTN_N;
+	end
+
+	/*buttons buttons0(
+		.CLK(CLK),
+		.BTN1(BTN1),
+		.BTN2(BTN2),
+		.BTN3(BTN3),
+		.BTN_N(BTN_N),
+		.duty_val(duty_v),
+	);
+
+	duty duty0(
+		.CLK(CLK),
+		.cmp(duty_v),
+		.out(led[0])
+	);*/
+//	 
+//	clkdiv displayClockGen(
+//		.clk(CLK),
+//		.clkout(displayClock)
+//	);
+//
+//	seven_seg_mux display(
+//		.clk(displayClock),
+//		.disp0(disp0),
+//		.disp1(disp1),
+//		.segout(seg),
+//		.disp_sel(ca)
+//	);
+
+endmodule